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Add -mno-r11 support to PowerPC 64
[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; REGNOS
27 ;;
28
29 (define_constants
30 [(STACK_POINTER_REGNUM 1)
31 (TOC_REGNUM 2)
32 (STATIC_CHAIN_REGNUM 11)
33 (HARD_FRAME_POINTER_REGNUM 31)
34 (MQ_REGNO 64)
35 (LR_REGNO 65)
36 (CTR_REGNO 66)
37 (ARG_POINTER_REGNUM 67)
38 (CR0_REGNO 68)
39 (CR1_REGNO 69)
40 (CR2_REGNO 70)
41 (CR3_REGNO 71)
42 (CR4_REGNO 72)
43 (CR5_REGNO 73)
44 (CR6_REGNO 74)
45 (CR7_REGNO 75)
46 (MAX_CR_REGNO 75)
47 (CA_REGNO 76)
48 (FIRST_ALTIVEC_REGNO 77)
49 (LAST_ALTIVEC_REGNO 108)
50 (VRSAVE_REGNO 109)
51 (VSCR_REGNO 110)
52 (SPE_ACC_REGNO 111)
53 (SPEFSCR_REGNO 112)
54 (FRAME_POINTER_REGNUM 113)
55
56 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
57 (TOC_SAVE_OFFSET_32BIT 20)
58 (TOC_SAVE_OFFSET_64BIT 40)
59
60 ; Function TOC offset in the AIX function descriptor.
61 (AIX_FUNC_DESC_TOC_32BIT 4)
62 (AIX_FUNC_DESC_TOC_64BIT 8)
63
64 ; Static chain offset in the AIX function descriptor.
65 (AIX_FUNC_DESC_SC_32BIT 8)
66 (AIX_FUNC_DESC_SC_64BIT 16)
67 ])
68
69 ;;
70 ;; UNSPEC usage
71 ;;
72
73 (define_c_enum "unspec"
74 [UNSPEC_FRSP ; frsp for POWER machines
75 UNSPEC_PROBE_STACK ; probe stack memory reference
76 UNSPEC_TIE ; tie stack contents and stack pointer
77 UNSPEC_TOCPTR ; address of a word pointing to the TOC
78 UNSPEC_TOC ; address of the TOC (more-or-less)
79 UNSPEC_MOVSI_GOT
80 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
81 UNSPEC_FCTIWZ
82 UNSPEC_FRIM
83 UNSPEC_FRIN
84 UNSPEC_FRIP
85 UNSPEC_FRIZ
86 UNSPEC_LD_MPIC ; load_macho_picbase
87 UNSPEC_MPIC_CORRECT ; macho_correct_pic
88 UNSPEC_TLSGD
89 UNSPEC_TLSLD
90 UNSPEC_MOVESI_FROM_CR
91 UNSPEC_MOVESI_TO_CR
92 UNSPEC_TLSDTPREL
93 UNSPEC_TLSDTPRELHA
94 UNSPEC_TLSDTPRELLO
95 UNSPEC_TLSGOTDTPREL
96 UNSPEC_TLSTPREL
97 UNSPEC_TLSTPRELHA
98 UNSPEC_TLSTPRELLO
99 UNSPEC_TLSGOTTPREL
100 UNSPEC_TLSTLS
101 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
102 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
103 UNSPEC_STFIWX
104 UNSPEC_POPCNTB
105 UNSPEC_FRES
106 UNSPEC_SP_SET
107 UNSPEC_SP_TEST
108 UNSPEC_SYNC
109 UNSPEC_SYNC_OP
110 UNSPEC_ATOMIC
111 UNSPEC_CMPXCHG
112 UNSPEC_XCHG
113 UNSPEC_AND
114 UNSPEC_DLMZB
115 UNSPEC_DLMZB_CR
116 UNSPEC_DLMZB_STRLEN
117 UNSPEC_RSQRT
118 UNSPEC_TOCREL
119 UNSPEC_MACHOPIC_OFFSET
120 UNSPEC_BPERM
121 UNSPEC_COPYSIGN
122 UNSPEC_PARITY
123 UNSPEC_FCTIW
124 UNSPEC_FCTID
125 UNSPEC_LFIWAX
126 UNSPEC_LFIWZX
127 UNSPEC_FCTIWUZ
128 ])
129
130 ;;
131 ;; UNSPEC_VOLATILE usage
132 ;;
133
134 (define_c_enum "unspecv"
135 [UNSPECV_BLOCK
136 UNSPECV_LL ; load-locked
137 UNSPECV_SC ; store-conditional
138 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
139 UNSPECV_EH_RR ; eh_reg_restore
140 UNSPECV_ISYNC ; isync instruction
141 UNSPECV_LWSYNC ; lwsync
142 ])
143
144 \f
145 ;; Define an insn type attribute. This is used in function unit delay
146 ;; computations.
147 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
148 (const_string "integer"))
149
150 ;; Define floating point instruction sub-types for use with Xfpu.md
151 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
152
153 ;; Length (in bytes).
154 ; '(pc)' in the following doesn't include the instruction itself; it is
155 ; calculated as if the instruction had zero size.
156 (define_attr "length" ""
157 (if_then_else (eq_attr "type" "branch")
158 (if_then_else (and (ge (minus (match_dup 0) (pc))
159 (const_int -32768))
160 (lt (minus (match_dup 0) (pc))
161 (const_int 32764)))
162 (const_int 4)
163 (const_int 8))
164 (const_int 4)))
165
166 ;; Processor type -- this attribute must exactly match the processor_type
167 ;; enumeration in rs6000.h.
168
169 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
170 (const (symbol_ref "rs6000_cpu_attr")))
171
172
173 ;; If this instruction is microcoded on the CELL processor
174 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
175 (define_attr "cell_micro" "not,conditional,always"
176 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
177 (const_string "always")
178 (const_string "not")))
179
180 (automata_option "ndfa")
181
182 (include "rios1.md")
183 (include "rios2.md")
184 (include "rs64.md")
185 (include "mpc.md")
186 (include "40x.md")
187 (include "440.md")
188 (include "476.md")
189 (include "603.md")
190 (include "6xx.md")
191 (include "7xx.md")
192 (include "7450.md")
193 (include "8540.md")
194 (include "e300c2c3.md")
195 (include "e500mc.md")
196 (include "e500mc64.md")
197 (include "power4.md")
198 (include "power5.md")
199 (include "power6.md")
200 (include "power7.md")
201 (include "cell.md")
202 (include "xfpu.md")
203 (include "a2.md")
204 (include "titan.md")
205
206 (include "predicates.md")
207 (include "constraints.md")
208
209 (include "darwin.md")
210
211 \f
212 ;; Mode iterators
213
214 ; This mode iterator allows :GPR to be used to indicate the allowable size
215 ; of whole values in GPRs.
216 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
217
218 ; Any supported integer mode.
219 (define_mode_iterator INT [QI HI SI DI TI])
220
221 ; Any supported integer mode that fits in one register.
222 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
223
224 ; extend modes for DImode
225 (define_mode_iterator QHSI [QI HI SI])
226
227 ; SImode or DImode, even if DImode doesn't fit in GPRs.
228 (define_mode_iterator SDI [SI DI])
229
230 ; The size of a pointer. Also, the size of the value that a record-condition
231 ; (one with a '.') will compare; and the size used for arithmetic carries.
232 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
233
234 ; Any hardware-supported floating-point mode
235 (define_mode_iterator FP [
236 (SF "TARGET_HARD_FLOAT
237 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
238 (DF "TARGET_HARD_FLOAT
239 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
240 (TF "!TARGET_IEEEQUAD
241 && TARGET_HARD_FLOAT
242 && (TARGET_FPRS || TARGET_E500_DOUBLE)
243 && TARGET_LONG_DOUBLE_128")
244 (DD "TARGET_DFP")
245 (TD "TARGET_DFP")])
246
247 ; Any fma capable floating-point mode.
248 (define_mode_iterator FMA_F [
249 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
250 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
251 || VECTOR_UNIT_VSX_P (DFmode)")
252 (V2SF "TARGET_PAIRED_FLOAT")
253 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
254 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
255 ])
256
257 ; These modes do not fit in integer registers in 32-bit mode.
258 ; but on e500v2, the gpr are 64 bit registers
259 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
260
261 ; Iterator for reciprocal estimate instructions
262 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
263
264 ; Iterator for just SF/DF
265 (define_mode_iterator SFDF [SF DF])
266
267 ; Various instructions that come in SI and DI forms.
268 ; A generic w/d attribute, for things like cmpw/cmpd.
269 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
270
271 ; DImode bits
272 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
273
274 ;; ISEL/ISEL64 target selection
275 (define_mode_attr sel [(SI "") (DI "64")])
276
277 ;; Suffix for reload patterns
278 (define_mode_attr ptrsize [(SI "32bit")
279 (DI "64bit")])
280
281 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
282 (DI "TARGET_64BIT")])
283
284 (define_mode_attr mptrsize [(SI "si")
285 (DI "di")])
286
287 (define_mode_attr ptrload [(SI "{l|lwz}")
288 (DI "ld")])
289
290 (define_mode_attr rreg [(SF "f")
291 (DF "ws")
292 (V4SF "wf")
293 (V2DF "wd")])
294
295 (define_mode_attr rreg2 [(SF "f")
296 (DF "d")])
297
298 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
299 (DF "TARGET_FCFID")])
300
301 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
302 (DF "TARGET_E500_DOUBLE")])
303
304 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
305 (DF "TARGET_DOUBLE_FLOAT")])
306 \f
307 ;; Start with fixed-point load and store insns. Here we put only the more
308 ;; complex forms. Basic data transfer is done later.
309
310 (define_expand "zero_extend<mode>di2"
311 [(set (match_operand:DI 0 "gpc_reg_operand" "")
312 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
313 "TARGET_POWERPC64"
314 "")
315
316 (define_insn "*zero_extend<mode>di2_internal1"
317 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
318 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
319 "TARGET_POWERPC64"
320 "@
321 l<wd>z%U1%X1 %0,%1
322 rldicl %0,%1,0,<dbits>"
323 [(set_attr "type" "load,*")])
324
325 (define_insn "*zero_extend<mode>di2_internal2"
326 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
327 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
328 (const_int 0)))
329 (clobber (match_scratch:DI 2 "=r,r"))]
330 "TARGET_64BIT"
331 "@
332 rldicl. %2,%1,0,<dbits>
333 #"
334 [(set_attr "type" "compare")
335 (set_attr "length" "4,8")])
336
337 (define_split
338 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
339 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
340 (const_int 0)))
341 (clobber (match_scratch:DI 2 ""))]
342 "TARGET_POWERPC64 && reload_completed"
343 [(set (match_dup 2)
344 (zero_extend:DI (match_dup 1)))
345 (set (match_dup 0)
346 (compare:CC (match_dup 2)
347 (const_int 0)))]
348 "")
349
350 (define_insn "*zero_extend<mode>di2_internal3"
351 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
352 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
353 (const_int 0)))
354 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
355 (zero_extend:DI (match_dup 1)))]
356 "TARGET_64BIT"
357 "@
358 rldicl. %0,%1,0,<dbits>
359 #"
360 [(set_attr "type" "compare")
361 (set_attr "length" "4,8")])
362
363 (define_split
364 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
365 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
366 (const_int 0)))
367 (set (match_operand:DI 0 "gpc_reg_operand" "")
368 (zero_extend:DI (match_dup 1)))]
369 "TARGET_POWERPC64 && reload_completed"
370 [(set (match_dup 0)
371 (zero_extend:DI (match_dup 1)))
372 (set (match_dup 2)
373 (compare:CC (match_dup 0)
374 (const_int 0)))]
375 "")
376
377 (define_insn "extendqidi2"
378 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
379 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
380 "TARGET_POWERPC64"
381 "extsb %0,%1"
382 [(set_attr "type" "exts")])
383
384 (define_insn ""
385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
386 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
387 (const_int 0)))
388 (clobber (match_scratch:DI 2 "=r,r"))]
389 "TARGET_64BIT"
390 "@
391 extsb. %2,%1
392 #"
393 [(set_attr "type" "compare")
394 (set_attr "length" "4,8")])
395
396 (define_split
397 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
398 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
399 (const_int 0)))
400 (clobber (match_scratch:DI 2 ""))]
401 "TARGET_POWERPC64 && reload_completed"
402 [(set (match_dup 2)
403 (sign_extend:DI (match_dup 1)))
404 (set (match_dup 0)
405 (compare:CC (match_dup 2)
406 (const_int 0)))]
407 "")
408
409 (define_insn ""
410 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
411 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
412 (const_int 0)))
413 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
414 (sign_extend:DI (match_dup 1)))]
415 "TARGET_64BIT"
416 "@
417 extsb. %0,%1
418 #"
419 [(set_attr "type" "compare")
420 (set_attr "length" "4,8")])
421
422 (define_split
423 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
424 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
425 (const_int 0)))
426 (set (match_operand:DI 0 "gpc_reg_operand" "")
427 (sign_extend:DI (match_dup 1)))]
428 "TARGET_POWERPC64 && reload_completed"
429 [(set (match_dup 0)
430 (sign_extend:DI (match_dup 1)))
431 (set (match_dup 2)
432 (compare:CC (match_dup 0)
433 (const_int 0)))]
434 "")
435
436 (define_expand "extendhidi2"
437 [(set (match_operand:DI 0 "gpc_reg_operand" "")
438 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
439 "TARGET_POWERPC64"
440 "")
441
442 (define_insn ""
443 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
444 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
445 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
446 "@
447 lha%U1%X1 %0,%1
448 extsh %0,%1"
449 [(set_attr "type" "load_ext,exts")])
450
451 (define_insn ""
452 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
453 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
454 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
455 "extsh %0,%1"
456 [(set_attr "type" "exts")])
457
458 (define_insn ""
459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
460 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
461 (const_int 0)))
462 (clobber (match_scratch:DI 2 "=r,r"))]
463 "TARGET_64BIT"
464 "@
465 extsh. %2,%1
466 #"
467 [(set_attr "type" "compare")
468 (set_attr "length" "4,8")])
469
470 (define_split
471 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
472 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
473 (const_int 0)))
474 (clobber (match_scratch:DI 2 ""))]
475 "TARGET_POWERPC64 && reload_completed"
476 [(set (match_dup 2)
477 (sign_extend:DI (match_dup 1)))
478 (set (match_dup 0)
479 (compare:CC (match_dup 2)
480 (const_int 0)))]
481 "")
482
483 (define_insn ""
484 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
485 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
486 (const_int 0)))
487 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
488 (sign_extend:DI (match_dup 1)))]
489 "TARGET_64BIT"
490 "@
491 extsh. %0,%1
492 #"
493 [(set_attr "type" "compare")
494 (set_attr "length" "4,8")])
495
496 (define_split
497 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
498 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
499 (const_int 0)))
500 (set (match_operand:DI 0 "gpc_reg_operand" "")
501 (sign_extend:DI (match_dup 1)))]
502 "TARGET_POWERPC64 && reload_completed"
503 [(set (match_dup 0)
504 (sign_extend:DI (match_dup 1)))
505 (set (match_dup 2)
506 (compare:CC (match_dup 0)
507 (const_int 0)))]
508 "")
509
510 (define_expand "extendsidi2"
511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
512 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
513 "TARGET_POWERPC64"
514 "")
515
516 (define_insn ""
517 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
518 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
519 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
520 "@
521 lwa%U1%X1 %0,%1
522 extsw %0,%1"
523 [(set_attr "type" "load_ext,exts")])
524
525 (define_insn ""
526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
527 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
528 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
529 "extsw %0,%1"
530 [(set_attr "type" "exts")])
531
532 (define_insn ""
533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
534 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
535 (const_int 0)))
536 (clobber (match_scratch:DI 2 "=r,r"))]
537 "TARGET_64BIT"
538 "@
539 extsw. %2,%1
540 #"
541 [(set_attr "type" "compare")
542 (set_attr "length" "4,8")])
543
544 (define_split
545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
546 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
547 (const_int 0)))
548 (clobber (match_scratch:DI 2 ""))]
549 "TARGET_POWERPC64 && reload_completed"
550 [(set (match_dup 2)
551 (sign_extend:DI (match_dup 1)))
552 (set (match_dup 0)
553 (compare:CC (match_dup 2)
554 (const_int 0)))]
555 "")
556
557 (define_insn ""
558 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
559 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
560 (const_int 0)))
561 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
562 (sign_extend:DI (match_dup 1)))]
563 "TARGET_64BIT"
564 "@
565 extsw. %0,%1
566 #"
567 [(set_attr "type" "compare")
568 (set_attr "length" "4,8")])
569
570 (define_split
571 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
572 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
573 (const_int 0)))
574 (set (match_operand:DI 0 "gpc_reg_operand" "")
575 (sign_extend:DI (match_dup 1)))]
576 "TARGET_POWERPC64 && reload_completed"
577 [(set (match_dup 0)
578 (sign_extend:DI (match_dup 1)))
579 (set (match_dup 2)
580 (compare:CC (match_dup 0)
581 (const_int 0)))]
582 "")
583
584 (define_expand "zero_extendqisi2"
585 [(set (match_operand:SI 0 "gpc_reg_operand" "")
586 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
587 ""
588 "")
589
590 (define_insn ""
591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
592 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
593 ""
594 "@
595 lbz%U1%X1 %0,%1
596 {rlinm|rlwinm} %0,%1,0,0xff"
597 [(set_attr "type" "load,*")])
598
599 (define_insn ""
600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
601 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
602 (const_int 0)))
603 (clobber (match_scratch:SI 2 "=r,r"))]
604 ""
605 "@
606 {andil.|andi.} %2,%1,0xff
607 #"
608 [(set_attr "type" "fast_compare,compare")
609 (set_attr "length" "4,8")])
610
611 (define_split
612 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
613 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
614 (const_int 0)))
615 (clobber (match_scratch:SI 2 ""))]
616 "reload_completed"
617 [(set (match_dup 2)
618 (zero_extend:SI (match_dup 1)))
619 (set (match_dup 0)
620 (compare:CC (match_dup 2)
621 (const_int 0)))]
622 "")
623
624 (define_insn ""
625 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
626 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
627 (const_int 0)))
628 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
629 (zero_extend:SI (match_dup 1)))]
630 ""
631 "@
632 {andil.|andi.} %0,%1,0xff
633 #"
634 [(set_attr "type" "fast_compare,compare")
635 (set_attr "length" "4,8")])
636
637 (define_split
638 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
639 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
640 (const_int 0)))
641 (set (match_operand:SI 0 "gpc_reg_operand" "")
642 (zero_extend:SI (match_dup 1)))]
643 "reload_completed"
644 [(set (match_dup 0)
645 (zero_extend:SI (match_dup 1)))
646 (set (match_dup 2)
647 (compare:CC (match_dup 0)
648 (const_int 0)))]
649 "")
650
651 (define_expand "extendqisi2"
652 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
653 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
654 ""
655 "
656 {
657 if (TARGET_POWERPC)
658 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
659 else if (TARGET_POWER)
660 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
661 else
662 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
663 DONE;
664 }")
665
666 (define_insn "extendqisi2_ppc"
667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
668 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
669 "TARGET_POWERPC"
670 "extsb %0,%1"
671 [(set_attr "type" "exts")])
672
673 (define_insn ""
674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
675 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
676 (const_int 0)))
677 (clobber (match_scratch:SI 2 "=r,r"))]
678 "TARGET_POWERPC"
679 "@
680 extsb. %2,%1
681 #"
682 [(set_attr "type" "compare")
683 (set_attr "length" "4,8")])
684
685 (define_split
686 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
687 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
688 (const_int 0)))
689 (clobber (match_scratch:SI 2 ""))]
690 "TARGET_POWERPC && reload_completed"
691 [(set (match_dup 2)
692 (sign_extend:SI (match_dup 1)))
693 (set (match_dup 0)
694 (compare:CC (match_dup 2)
695 (const_int 0)))]
696 "")
697
698 (define_insn ""
699 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
700 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
701 (const_int 0)))
702 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
703 (sign_extend:SI (match_dup 1)))]
704 "TARGET_POWERPC"
705 "@
706 extsb. %0,%1
707 #"
708 [(set_attr "type" "compare")
709 (set_attr "length" "4,8")])
710
711 (define_split
712 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
713 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
714 (const_int 0)))
715 (set (match_operand:SI 0 "gpc_reg_operand" "")
716 (sign_extend:SI (match_dup 1)))]
717 "TARGET_POWERPC && reload_completed"
718 [(set (match_dup 0)
719 (sign_extend:SI (match_dup 1)))
720 (set (match_dup 2)
721 (compare:CC (match_dup 0)
722 (const_int 0)))]
723 "")
724
725 (define_expand "extendqisi2_power"
726 [(parallel [(set (match_dup 2)
727 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
728 (const_int 24)))
729 (clobber (scratch:SI))])
730 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
731 (ashiftrt:SI (match_dup 2)
732 (const_int 24)))
733 (clobber (scratch:SI))])]
734 "TARGET_POWER"
735 "
736 { operands[1] = gen_lowpart (SImode, operands[1]);
737 operands[2] = gen_reg_rtx (SImode); }")
738
739 (define_expand "extendqisi2_no_power"
740 [(set (match_dup 2)
741 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
742 (const_int 24)))
743 (set (match_operand:SI 0 "gpc_reg_operand" "")
744 (ashiftrt:SI (match_dup 2)
745 (const_int 24)))]
746 "! TARGET_POWER && ! TARGET_POWERPC"
747 "
748 { operands[1] = gen_lowpart (SImode, operands[1]);
749 operands[2] = gen_reg_rtx (SImode); }")
750
751 (define_expand "zero_extendqihi2"
752 [(set (match_operand:HI 0 "gpc_reg_operand" "")
753 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
754 ""
755 "")
756
757 (define_insn ""
758 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
759 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
760 ""
761 "@
762 lbz%U1%X1 %0,%1
763 {rlinm|rlwinm} %0,%1,0,0xff"
764 [(set_attr "type" "load,*")])
765
766 (define_insn ""
767 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
768 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
769 (const_int 0)))
770 (clobber (match_scratch:HI 2 "=r,r"))]
771 ""
772 "@
773 {andil.|andi.} %2,%1,0xff
774 #"
775 [(set_attr "type" "fast_compare,compare")
776 (set_attr "length" "4,8")])
777
778 (define_split
779 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
780 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
781 (const_int 0)))
782 (clobber (match_scratch:HI 2 ""))]
783 "reload_completed"
784 [(set (match_dup 2)
785 (zero_extend:HI (match_dup 1)))
786 (set (match_dup 0)
787 (compare:CC (match_dup 2)
788 (const_int 0)))]
789 "")
790
791 (define_insn ""
792 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
793 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
794 (const_int 0)))
795 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
796 (zero_extend:HI (match_dup 1)))]
797 ""
798 "@
799 {andil.|andi.} %0,%1,0xff
800 #"
801 [(set_attr "type" "fast_compare,compare")
802 (set_attr "length" "4,8")])
803
804 (define_split
805 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
806 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
807 (const_int 0)))
808 (set (match_operand:HI 0 "gpc_reg_operand" "")
809 (zero_extend:HI (match_dup 1)))]
810 "reload_completed"
811 [(set (match_dup 0)
812 (zero_extend:HI (match_dup 1)))
813 (set (match_dup 2)
814 (compare:CC (match_dup 0)
815 (const_int 0)))]
816 "")
817
818 (define_expand "extendqihi2"
819 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
820 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
821 ""
822 "
823 {
824 if (TARGET_POWERPC)
825 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
826 else if (TARGET_POWER)
827 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
828 else
829 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
830 DONE;
831 }")
832
833 (define_insn "extendqihi2_ppc"
834 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
835 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
836 "TARGET_POWERPC"
837 "extsb %0,%1"
838 [(set_attr "type" "exts")])
839
840 (define_insn ""
841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
842 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
843 (const_int 0)))
844 (clobber (match_scratch:HI 2 "=r,r"))]
845 "TARGET_POWERPC"
846 "@
847 extsb. %2,%1
848 #"
849 [(set_attr "type" "compare")
850 (set_attr "length" "4,8")])
851
852 (define_split
853 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
854 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
855 (const_int 0)))
856 (clobber (match_scratch:HI 2 ""))]
857 "TARGET_POWERPC && reload_completed"
858 [(set (match_dup 2)
859 (sign_extend:HI (match_dup 1)))
860 (set (match_dup 0)
861 (compare:CC (match_dup 2)
862 (const_int 0)))]
863 "")
864
865 (define_insn ""
866 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
867 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
868 (const_int 0)))
869 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
870 (sign_extend:HI (match_dup 1)))]
871 "TARGET_POWERPC"
872 "@
873 extsb. %0,%1
874 #"
875 [(set_attr "type" "compare")
876 (set_attr "length" "4,8")])
877
878 (define_split
879 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
880 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
881 (const_int 0)))
882 (set (match_operand:HI 0 "gpc_reg_operand" "")
883 (sign_extend:HI (match_dup 1)))]
884 "TARGET_POWERPC && reload_completed"
885 [(set (match_dup 0)
886 (sign_extend:HI (match_dup 1)))
887 (set (match_dup 2)
888 (compare:CC (match_dup 0)
889 (const_int 0)))]
890 "")
891
892 (define_expand "extendqihi2_power"
893 [(parallel [(set (match_dup 2)
894 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
895 (const_int 24)))
896 (clobber (scratch:SI))])
897 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
898 (ashiftrt:SI (match_dup 2)
899 (const_int 24)))
900 (clobber (scratch:SI))])]
901 "TARGET_POWER"
902 "
903 { operands[0] = gen_lowpart (SImode, operands[0]);
904 operands[1] = gen_lowpart (SImode, operands[1]);
905 operands[2] = gen_reg_rtx (SImode); }")
906
907 (define_expand "extendqihi2_no_power"
908 [(set (match_dup 2)
909 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
910 (const_int 24)))
911 (set (match_operand:HI 0 "gpc_reg_operand" "")
912 (ashiftrt:SI (match_dup 2)
913 (const_int 24)))]
914 "! TARGET_POWER && ! TARGET_POWERPC"
915 "
916 { operands[0] = gen_lowpart (SImode, operands[0]);
917 operands[1] = gen_lowpart (SImode, operands[1]);
918 operands[2] = gen_reg_rtx (SImode); }")
919
920 (define_expand "zero_extendhisi2"
921 [(set (match_operand:SI 0 "gpc_reg_operand" "")
922 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
923 ""
924 "")
925
926 (define_insn ""
927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
928 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
929 ""
930 "@
931 lhz%U1%X1 %0,%1
932 {rlinm|rlwinm} %0,%1,0,0xffff"
933 [(set_attr "type" "load,*")])
934
935 (define_insn ""
936 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
937 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
938 (const_int 0)))
939 (clobber (match_scratch:SI 2 "=r,r"))]
940 ""
941 "@
942 {andil.|andi.} %2,%1,0xffff
943 #"
944 [(set_attr "type" "fast_compare,compare")
945 (set_attr "length" "4,8")])
946
947 (define_split
948 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
949 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
950 (const_int 0)))
951 (clobber (match_scratch:SI 2 ""))]
952 "reload_completed"
953 [(set (match_dup 2)
954 (zero_extend:SI (match_dup 1)))
955 (set (match_dup 0)
956 (compare:CC (match_dup 2)
957 (const_int 0)))]
958 "")
959
960 (define_insn ""
961 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
962 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
963 (const_int 0)))
964 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
965 (zero_extend:SI (match_dup 1)))]
966 ""
967 "@
968 {andil.|andi.} %0,%1,0xffff
969 #"
970 [(set_attr "type" "fast_compare,compare")
971 (set_attr "length" "4,8")])
972
973 (define_split
974 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
975 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
976 (const_int 0)))
977 (set (match_operand:SI 0 "gpc_reg_operand" "")
978 (zero_extend:SI (match_dup 1)))]
979 "reload_completed"
980 [(set (match_dup 0)
981 (zero_extend:SI (match_dup 1)))
982 (set (match_dup 2)
983 (compare:CC (match_dup 0)
984 (const_int 0)))]
985 "")
986
987 (define_expand "extendhisi2"
988 [(set (match_operand:SI 0 "gpc_reg_operand" "")
989 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
990 ""
991 "")
992
993 (define_insn ""
994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
995 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
996 "rs6000_gen_cell_microcode"
997 "@
998 lha%U1%X1 %0,%1
999 {exts|extsh} %0,%1"
1000 [(set_attr "type" "load_ext,exts")])
1001
1002 (define_insn ""
1003 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1004 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1005 "!rs6000_gen_cell_microcode"
1006 "{exts|extsh} %0,%1"
1007 [(set_attr "type" "exts")])
1008
1009 (define_insn ""
1010 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1011 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1012 (const_int 0)))
1013 (clobber (match_scratch:SI 2 "=r,r"))]
1014 ""
1015 "@
1016 {exts.|extsh.} %2,%1
1017 #"
1018 [(set_attr "type" "compare")
1019 (set_attr "length" "4,8")])
1020
1021 (define_split
1022 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1023 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1024 (const_int 0)))
1025 (clobber (match_scratch:SI 2 ""))]
1026 "reload_completed"
1027 [(set (match_dup 2)
1028 (sign_extend:SI (match_dup 1)))
1029 (set (match_dup 0)
1030 (compare:CC (match_dup 2)
1031 (const_int 0)))]
1032 "")
1033
1034 (define_insn ""
1035 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1036 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1037 (const_int 0)))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1039 (sign_extend:SI (match_dup 1)))]
1040 ""
1041 "@
1042 {exts.|extsh.} %0,%1
1043 #"
1044 [(set_attr "type" "compare")
1045 (set_attr "length" "4,8")])
1046 \f
1047 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1048
1049 (define_insn "*macchwc"
1050 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1051 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1052 (match_operand:SI 2 "gpc_reg_operand" "r")
1053 (const_int 16))
1054 (sign_extend:SI
1055 (match_operand:HI 1 "gpc_reg_operand" "r")))
1056 (match_operand:SI 4 "gpc_reg_operand" "0"))
1057 (const_int 0)))
1058 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1059 (plus:SI (mult:SI (ashiftrt:SI
1060 (match_dup 2)
1061 (const_int 16))
1062 (sign_extend:SI
1063 (match_dup 1)))
1064 (match_dup 4)))]
1065 "TARGET_MULHW"
1066 "macchw. %0, %1, %2"
1067 [(set_attr "type" "imul3")])
1068
1069 (define_insn "*macchw"
1070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (ashiftrt:SI
1072 (match_operand:SI 2 "gpc_reg_operand" "r")
1073 (const_int 16))
1074 (sign_extend:SI
1075 (match_operand:HI 1 "gpc_reg_operand" "r")))
1076 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1077 "TARGET_MULHW"
1078 "macchw %0, %1, %2"
1079 [(set_attr "type" "imul3")])
1080
1081 (define_insn "*macchwuc"
1082 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1083 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1084 (match_operand:SI 2 "gpc_reg_operand" "r")
1085 (const_int 16))
1086 (zero_extend:SI
1087 (match_operand:HI 1 "gpc_reg_operand" "r")))
1088 (match_operand:SI 4 "gpc_reg_operand" "0"))
1089 (const_int 0)))
1090 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1091 (plus:SI (mult:SI (lshiftrt:SI
1092 (match_dup 2)
1093 (const_int 16))
1094 (zero_extend:SI
1095 (match_dup 1)))
1096 (match_dup 4)))]
1097 "TARGET_MULHW"
1098 "macchwu. %0, %1, %2"
1099 [(set_attr "type" "imul3")])
1100
1101 (define_insn "*macchwu"
1102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (plus:SI (mult:SI (lshiftrt:SI
1104 (match_operand:SI 2 "gpc_reg_operand" "r")
1105 (const_int 16))
1106 (zero_extend:SI
1107 (match_operand:HI 1 "gpc_reg_operand" "r")))
1108 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1109 "TARGET_MULHW"
1110 "macchwu %0, %1, %2"
1111 [(set_attr "type" "imul3")])
1112
1113 (define_insn "*machhwc"
1114 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1115 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1116 (match_operand:SI 1 "gpc_reg_operand" "%r")
1117 (const_int 16))
1118 (ashiftrt:SI
1119 (match_operand:SI 2 "gpc_reg_operand" "r")
1120 (const_int 16)))
1121 (match_operand:SI 4 "gpc_reg_operand" "0"))
1122 (const_int 0)))
1123 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1124 (plus:SI (mult:SI (ashiftrt:SI
1125 (match_dup 1)
1126 (const_int 16))
1127 (ashiftrt:SI
1128 (match_dup 2)
1129 (const_int 16)))
1130 (match_dup 4)))]
1131 "TARGET_MULHW"
1132 "machhw. %0, %1, %2"
1133 [(set_attr "type" "imul3")])
1134
1135 (define_insn "*machhw"
1136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1137 (plus:SI (mult:SI (ashiftrt:SI
1138 (match_operand:SI 1 "gpc_reg_operand" "%r")
1139 (const_int 16))
1140 (ashiftrt:SI
1141 (match_operand:SI 2 "gpc_reg_operand" "r")
1142 (const_int 16)))
1143 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1144 "TARGET_MULHW"
1145 "machhw %0, %1, %2"
1146 [(set_attr "type" "imul3")])
1147
1148 (define_insn "*machhwuc"
1149 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1150 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1151 (match_operand:SI 1 "gpc_reg_operand" "%r")
1152 (const_int 16))
1153 (lshiftrt:SI
1154 (match_operand:SI 2 "gpc_reg_operand" "r")
1155 (const_int 16)))
1156 (match_operand:SI 4 "gpc_reg_operand" "0"))
1157 (const_int 0)))
1158 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1159 (plus:SI (mult:SI (lshiftrt:SI
1160 (match_dup 1)
1161 (const_int 16))
1162 (lshiftrt:SI
1163 (match_dup 2)
1164 (const_int 16)))
1165 (match_dup 4)))]
1166 "TARGET_MULHW"
1167 "machhwu. %0, %1, %2"
1168 [(set_attr "type" "imul3")])
1169
1170 (define_insn "*machhwu"
1171 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1172 (plus:SI (mult:SI (lshiftrt:SI
1173 (match_operand:SI 1 "gpc_reg_operand" "%r")
1174 (const_int 16))
1175 (lshiftrt:SI
1176 (match_operand:SI 2 "gpc_reg_operand" "r")
1177 (const_int 16)))
1178 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1179 "TARGET_MULHW"
1180 "machhwu %0, %1, %2"
1181 [(set_attr "type" "imul3")])
1182
1183 (define_insn "*maclhwc"
1184 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1185 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1186 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1187 (sign_extend:SI
1188 (match_operand:HI 2 "gpc_reg_operand" "r")))
1189 (match_operand:SI 4 "gpc_reg_operand" "0"))
1190 (const_int 0)))
1191 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1192 (plus:SI (mult:SI (sign_extend:SI
1193 (match_dup 1))
1194 (sign_extend:SI
1195 (match_dup 2)))
1196 (match_dup 4)))]
1197 "TARGET_MULHW"
1198 "maclhw. %0, %1, %2"
1199 [(set_attr "type" "imul3")])
1200
1201 (define_insn "*maclhw"
1202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1203 (plus:SI (mult:SI (sign_extend:SI
1204 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1205 (sign_extend:SI
1206 (match_operand:HI 2 "gpc_reg_operand" "r")))
1207 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1208 "TARGET_MULHW"
1209 "maclhw %0, %1, %2"
1210 [(set_attr "type" "imul3")])
1211
1212 (define_insn "*maclhwuc"
1213 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1214 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1215 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1216 (zero_extend:SI
1217 (match_operand:HI 2 "gpc_reg_operand" "r")))
1218 (match_operand:SI 4 "gpc_reg_operand" "0"))
1219 (const_int 0)))
1220 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1221 (plus:SI (mult:SI (zero_extend:SI
1222 (match_dup 1))
1223 (zero_extend:SI
1224 (match_dup 2)))
1225 (match_dup 4)))]
1226 "TARGET_MULHW"
1227 "maclhwu. %0, %1, %2"
1228 [(set_attr "type" "imul3")])
1229
1230 (define_insn "*maclhwu"
1231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1232 (plus:SI (mult:SI (zero_extend:SI
1233 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1234 (zero_extend:SI
1235 (match_operand:HI 2 "gpc_reg_operand" "r")))
1236 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1237 "TARGET_MULHW"
1238 "maclhwu %0, %1, %2"
1239 [(set_attr "type" "imul3")])
1240
1241 (define_insn "*nmacchwc"
1242 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1243 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1244 (mult:SI (ashiftrt:SI
1245 (match_operand:SI 2 "gpc_reg_operand" "r")
1246 (const_int 16))
1247 (sign_extend:SI
1248 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1249 (const_int 0)))
1250 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1251 (minus:SI (match_dup 4)
1252 (mult:SI (ashiftrt:SI
1253 (match_dup 2)
1254 (const_int 16))
1255 (sign_extend:SI
1256 (match_dup 1)))))]
1257 "TARGET_MULHW"
1258 "nmacchw. %0, %1, %2"
1259 [(set_attr "type" "imul3")])
1260
1261 (define_insn "*nmacchw"
1262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1263 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1264 (mult:SI (ashiftrt:SI
1265 (match_operand:SI 2 "gpc_reg_operand" "r")
1266 (const_int 16))
1267 (sign_extend:SI
1268 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1269 "TARGET_MULHW"
1270 "nmacchw %0, %1, %2"
1271 [(set_attr "type" "imul3")])
1272
1273 (define_insn "*nmachhwc"
1274 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1275 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1276 (mult:SI (ashiftrt:SI
1277 (match_operand:SI 1 "gpc_reg_operand" "%r")
1278 (const_int 16))
1279 (ashiftrt:SI
1280 (match_operand:SI 2 "gpc_reg_operand" "r")
1281 (const_int 16))))
1282 (const_int 0)))
1283 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1284 (minus:SI (match_dup 4)
1285 (mult:SI (ashiftrt:SI
1286 (match_dup 1)
1287 (const_int 16))
1288 (ashiftrt:SI
1289 (match_dup 2)
1290 (const_int 16)))))]
1291 "TARGET_MULHW"
1292 "nmachhw. %0, %1, %2"
1293 [(set_attr "type" "imul3")])
1294
1295 (define_insn "*nmachhw"
1296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1298 (mult:SI (ashiftrt:SI
1299 (match_operand:SI 1 "gpc_reg_operand" "%r")
1300 (const_int 16))
1301 (ashiftrt:SI
1302 (match_operand:SI 2 "gpc_reg_operand" "r")
1303 (const_int 16)))))]
1304 "TARGET_MULHW"
1305 "nmachhw %0, %1, %2"
1306 [(set_attr "type" "imul3")])
1307
1308 (define_insn "*nmaclhwc"
1309 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1310 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1311 (mult:SI (sign_extend:SI
1312 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1313 (sign_extend:SI
1314 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1315 (const_int 0)))
1316 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1317 (minus:SI (match_dup 4)
1318 (mult:SI (sign_extend:SI
1319 (match_dup 1))
1320 (sign_extend:SI
1321 (match_dup 2)))))]
1322 "TARGET_MULHW"
1323 "nmaclhw. %0, %1, %2"
1324 [(set_attr "type" "imul3")])
1325
1326 (define_insn "*nmaclhw"
1327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1328 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1329 (mult:SI (sign_extend:SI
1330 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1331 (sign_extend:SI
1332 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1333 "TARGET_MULHW"
1334 "nmaclhw %0, %1, %2"
1335 [(set_attr "type" "imul3")])
1336
1337 (define_insn "*mulchwc"
1338 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1339 (compare:CC (mult:SI (ashiftrt:SI
1340 (match_operand:SI 2 "gpc_reg_operand" "r")
1341 (const_int 16))
1342 (sign_extend:SI
1343 (match_operand:HI 1 "gpc_reg_operand" "r")))
1344 (const_int 0)))
1345 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (ashiftrt:SI
1347 (match_dup 2)
1348 (const_int 16))
1349 (sign_extend:SI
1350 (match_dup 1))))]
1351 "TARGET_MULHW"
1352 "mulchw. %0, %1, %2"
1353 [(set_attr "type" "imul3")])
1354
1355 (define_insn "*mulchw"
1356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (mult:SI (ashiftrt:SI
1358 (match_operand:SI 2 "gpc_reg_operand" "r")
1359 (const_int 16))
1360 (sign_extend:SI
1361 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1362 "TARGET_MULHW"
1363 "mulchw %0, %1, %2"
1364 [(set_attr "type" "imul3")])
1365
1366 (define_insn "*mulchwuc"
1367 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1368 (compare:CC (mult:SI (lshiftrt:SI
1369 (match_operand:SI 2 "gpc_reg_operand" "r")
1370 (const_int 16))
1371 (zero_extend:SI
1372 (match_operand:HI 1 "gpc_reg_operand" "r")))
1373 (const_int 0)))
1374 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1375 (mult:SI (lshiftrt:SI
1376 (match_dup 2)
1377 (const_int 16))
1378 (zero_extend:SI
1379 (match_dup 1))))]
1380 "TARGET_MULHW"
1381 "mulchwu. %0, %1, %2"
1382 [(set_attr "type" "imul3")])
1383
1384 (define_insn "*mulchwu"
1385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1386 (mult:SI (lshiftrt:SI
1387 (match_operand:SI 2 "gpc_reg_operand" "r")
1388 (const_int 16))
1389 (zero_extend:SI
1390 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1391 "TARGET_MULHW"
1392 "mulchwu %0, %1, %2"
1393 [(set_attr "type" "imul3")])
1394
1395 (define_insn "*mulhhwc"
1396 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1397 (compare:CC (mult:SI (ashiftrt:SI
1398 (match_operand:SI 1 "gpc_reg_operand" "%r")
1399 (const_int 16))
1400 (ashiftrt:SI
1401 (match_operand:SI 2 "gpc_reg_operand" "r")
1402 (const_int 16)))
1403 (const_int 0)))
1404 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (mult:SI (ashiftrt:SI
1406 (match_dup 1)
1407 (const_int 16))
1408 (ashiftrt:SI
1409 (match_dup 2)
1410 (const_int 16))))]
1411 "TARGET_MULHW"
1412 "mulhhw. %0, %1, %2"
1413 [(set_attr "type" "imul3")])
1414
1415 (define_insn "*mulhhw"
1416 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1417 (mult:SI (ashiftrt:SI
1418 (match_operand:SI 1 "gpc_reg_operand" "%r")
1419 (const_int 16))
1420 (ashiftrt:SI
1421 (match_operand:SI 2 "gpc_reg_operand" "r")
1422 (const_int 16))))]
1423 "TARGET_MULHW"
1424 "mulhhw %0, %1, %2"
1425 [(set_attr "type" "imul3")])
1426
1427 (define_insn "*mulhhwuc"
1428 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1429 (compare:CC (mult:SI (lshiftrt:SI
1430 (match_operand:SI 1 "gpc_reg_operand" "%r")
1431 (const_int 16))
1432 (lshiftrt:SI
1433 (match_operand:SI 2 "gpc_reg_operand" "r")
1434 (const_int 16)))
1435 (const_int 0)))
1436 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1437 (mult:SI (lshiftrt:SI
1438 (match_dup 1)
1439 (const_int 16))
1440 (lshiftrt:SI
1441 (match_dup 2)
1442 (const_int 16))))]
1443 "TARGET_MULHW"
1444 "mulhhwu. %0, %1, %2"
1445 [(set_attr "type" "imul3")])
1446
1447 (define_insn "*mulhhwu"
1448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1449 (mult:SI (lshiftrt:SI
1450 (match_operand:SI 1 "gpc_reg_operand" "%r")
1451 (const_int 16))
1452 (lshiftrt:SI
1453 (match_operand:SI 2 "gpc_reg_operand" "r")
1454 (const_int 16))))]
1455 "TARGET_MULHW"
1456 "mulhhwu %0, %1, %2"
1457 [(set_attr "type" "imul3")])
1458
1459 (define_insn "*mullhwc"
1460 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1461 (compare:CC (mult:SI (sign_extend:SI
1462 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1463 (sign_extend:SI
1464 (match_operand:HI 2 "gpc_reg_operand" "r")))
1465 (const_int 0)))
1466 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1467 (mult:SI (sign_extend:SI
1468 (match_dup 1))
1469 (sign_extend:SI
1470 (match_dup 2))))]
1471 "TARGET_MULHW"
1472 "mullhw. %0, %1, %2"
1473 [(set_attr "type" "imul3")])
1474
1475 (define_insn "*mullhw"
1476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1477 (mult:SI (sign_extend:SI
1478 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1479 (sign_extend:SI
1480 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1481 "TARGET_MULHW"
1482 "mullhw %0, %1, %2"
1483 [(set_attr "type" "imul3")])
1484
1485 (define_insn "*mullhwuc"
1486 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1487 (compare:CC (mult:SI (zero_extend:SI
1488 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1489 (zero_extend:SI
1490 (match_operand:HI 2 "gpc_reg_operand" "r")))
1491 (const_int 0)))
1492 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1493 (mult:SI (zero_extend:SI
1494 (match_dup 1))
1495 (zero_extend:SI
1496 (match_dup 2))))]
1497 "TARGET_MULHW"
1498 "mullhwu. %0, %1, %2"
1499 [(set_attr "type" "imul3")])
1500
1501 (define_insn "*mullhwu"
1502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1503 (mult:SI (zero_extend:SI
1504 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1505 (zero_extend:SI
1506 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1507 "TARGET_MULHW"
1508 "mullhwu %0, %1, %2"
1509 [(set_attr "type" "imul3")])
1510 \f
1511 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1512 (define_insn "dlmzb"
1513 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1514 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1515 (match_operand:SI 2 "gpc_reg_operand" "r")]
1516 UNSPEC_DLMZB_CR))
1517 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1518 (unspec:SI [(match_dup 1)
1519 (match_dup 2)]
1520 UNSPEC_DLMZB))]
1521 "TARGET_DLMZB"
1522 "dlmzb. %0, %1, %2")
1523
1524 (define_expand "strlensi"
1525 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1526 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1527 (match_operand:QI 2 "const_int_operand" "")
1528 (match_operand 3 "const_int_operand" "")]
1529 UNSPEC_DLMZB_STRLEN))
1530 (clobber (match_scratch:CC 4 "=x"))]
1531 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1532 {
1533 rtx result = operands[0];
1534 rtx src = operands[1];
1535 rtx search_char = operands[2];
1536 rtx align = operands[3];
1537 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1538 rtx loop_label, end_label, mem, cr0, cond;
1539 if (search_char != const0_rtx
1540 || GET_CODE (align) != CONST_INT
1541 || INTVAL (align) < 8)
1542 FAIL;
1543 word1 = gen_reg_rtx (SImode);
1544 word2 = gen_reg_rtx (SImode);
1545 scratch_dlmzb = gen_reg_rtx (SImode);
1546 scratch_string = gen_reg_rtx (Pmode);
1547 loop_label = gen_label_rtx ();
1548 end_label = gen_label_rtx ();
1549 addr = force_reg (Pmode, XEXP (src, 0));
1550 emit_move_insn (scratch_string, addr);
1551 emit_label (loop_label);
1552 mem = change_address (src, SImode, scratch_string);
1553 emit_move_insn (word1, mem);
1554 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1555 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1556 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1557 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1558 emit_jump_insn (gen_rtx_SET (VOIDmode,
1559 pc_rtx,
1560 gen_rtx_IF_THEN_ELSE (VOIDmode,
1561 cond,
1562 gen_rtx_LABEL_REF
1563 (VOIDmode,
1564 end_label),
1565 pc_rtx)));
1566 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1567 emit_jump_insn (gen_rtx_SET (VOIDmode,
1568 pc_rtx,
1569 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1570 emit_barrier ();
1571 emit_label (end_label);
1572 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1573 emit_insn (gen_subsi3 (result, scratch_string, addr));
1574 emit_insn (gen_subsi3 (result, result, const1_rtx));
1575 DONE;
1576 })
1577 \f
1578 (define_split
1579 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1580 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1581 (const_int 0)))
1582 (set (match_operand:SI 0 "gpc_reg_operand" "")
1583 (sign_extend:SI (match_dup 1)))]
1584 "reload_completed"
1585 [(set (match_dup 0)
1586 (sign_extend:SI (match_dup 1)))
1587 (set (match_dup 2)
1588 (compare:CC (match_dup 0)
1589 (const_int 0)))]
1590 "")
1591
1592 ;; Fixed-point arithmetic insns.
1593
1594 (define_expand "add<mode>3"
1595 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1596 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1597 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1598 ""
1599 {
1600 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1601 {
1602 if (non_short_cint_operand (operands[2], DImode))
1603 FAIL;
1604 }
1605 else if (GET_CODE (operands[2]) == CONST_INT
1606 && ! add_operand (operands[2], <MODE>mode))
1607 {
1608 rtx tmp = ((!can_create_pseudo_p ()
1609 || rtx_equal_p (operands[0], operands[1]))
1610 ? operands[0] : gen_reg_rtx (<MODE>mode));
1611
1612 HOST_WIDE_INT val = INTVAL (operands[2]);
1613 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1614 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1615
1616 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1617 FAIL;
1618
1619 /* The ordering here is important for the prolog expander.
1620 When space is allocated from the stack, adding 'low' first may
1621 produce a temporary deallocation (which would be bad). */
1622 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1623 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1624 DONE;
1625 }
1626 })
1627
1628 ;; Discourage ai/addic because of carry but provide it in an alternative
1629 ;; allowing register zero as source.
1630 (define_insn "*add<mode>3_internal1"
1631 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1632 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1633 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1634 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1635 "@
1636 {cax|add} %0,%1,%2
1637 {cal %0,%2(%1)|addi %0,%1,%2}
1638 {ai|addic} %0,%1,%2
1639 {cau|addis} %0,%1,%v2"
1640 [(set_attr "length" "4,4,4,4")])
1641
1642 (define_insn "addsi3_high"
1643 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1644 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1645 (high:SI (match_operand 2 "" ""))))]
1646 "TARGET_MACHO && !TARGET_64BIT"
1647 "{cau|addis} %0,%1,ha16(%2)"
1648 [(set_attr "length" "4")])
1649
1650 (define_insn "*add<mode>3_internal2"
1651 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1652 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1653 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1654 (const_int 0)))
1655 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1656 ""
1657 "@
1658 {cax.|add.} %3,%1,%2
1659 {ai.|addic.} %3,%1,%2
1660 #
1661 #"
1662 [(set_attr "type" "fast_compare,compare,compare,compare")
1663 (set_attr "length" "4,4,8,8")])
1664
1665 (define_split
1666 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1667 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1668 (match_operand:GPR 2 "reg_or_short_operand" ""))
1669 (const_int 0)))
1670 (clobber (match_scratch:GPR 3 ""))]
1671 "reload_completed"
1672 [(set (match_dup 3)
1673 (plus:GPR (match_dup 1)
1674 (match_dup 2)))
1675 (set (match_dup 0)
1676 (compare:CC (match_dup 3)
1677 (const_int 0)))]
1678 "")
1679
1680 (define_insn "*add<mode>3_internal3"
1681 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1682 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1683 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1684 (const_int 0)))
1685 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1686 (plus:P (match_dup 1)
1687 (match_dup 2)))]
1688 ""
1689 "@
1690 {cax.|add.} %0,%1,%2
1691 {ai.|addic.} %0,%1,%2
1692 #
1693 #"
1694 [(set_attr "type" "fast_compare,compare,compare,compare")
1695 (set_attr "length" "4,4,8,8")])
1696
1697 (define_split
1698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1699 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1700 (match_operand:P 2 "reg_or_short_operand" ""))
1701 (const_int 0)))
1702 (set (match_operand:P 0 "gpc_reg_operand" "")
1703 (plus:P (match_dup 1) (match_dup 2)))]
1704 "reload_completed"
1705 [(set (match_dup 0)
1706 (plus:P (match_dup 1)
1707 (match_dup 2)))
1708 (set (match_dup 3)
1709 (compare:CC (match_dup 0)
1710 (const_int 0)))]
1711 "")
1712
1713 ;; Split an add that we can't do in one insn into two insns, each of which
1714 ;; does one 16-bit part. This is used by combine. Note that the low-order
1715 ;; add should be last in case the result gets used in an address.
1716
1717 (define_split
1718 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1719 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1720 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1721 ""
1722 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1723 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1724 {
1725 HOST_WIDE_INT val = INTVAL (operands[2]);
1726 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1727 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1728
1729 operands[4] = GEN_INT (low);
1730 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1731 operands[3] = GEN_INT (rest);
1732 else if (can_create_pseudo_p ())
1733 {
1734 operands[3] = gen_reg_rtx (DImode);
1735 emit_move_insn (operands[3], operands[2]);
1736 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1737 DONE;
1738 }
1739 else
1740 FAIL;
1741 })
1742
1743 (define_insn "one_cmpl<mode>2"
1744 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1745 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1746 ""
1747 "nor %0,%1,%1")
1748
1749 (define_insn ""
1750 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1751 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1752 (const_int 0)))
1753 (clobber (match_scratch:P 2 "=r,r"))]
1754 ""
1755 "@
1756 nor. %2,%1,%1
1757 #"
1758 [(set_attr "type" "fast_compare,compare")
1759 (set_attr "length" "4,8")])
1760
1761 (define_split
1762 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1763 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1764 (const_int 0)))
1765 (clobber (match_scratch:P 2 ""))]
1766 "reload_completed"
1767 [(set (match_dup 2)
1768 (not:P (match_dup 1)))
1769 (set (match_dup 0)
1770 (compare:CC (match_dup 2)
1771 (const_int 0)))]
1772 "")
1773
1774 (define_insn ""
1775 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1776 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1777 (const_int 0)))
1778 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1779 (not:P (match_dup 1)))]
1780 ""
1781 "@
1782 nor. %0,%1,%1
1783 #"
1784 [(set_attr "type" "fast_compare,compare")
1785 (set_attr "length" "4,8")])
1786
1787 (define_split
1788 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1789 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1790 (const_int 0)))
1791 (set (match_operand:P 0 "gpc_reg_operand" "")
1792 (not:P (match_dup 1)))]
1793 "reload_completed"
1794 [(set (match_dup 0)
1795 (not:P (match_dup 1)))
1796 (set (match_dup 2)
1797 (compare:CC (match_dup 0)
1798 (const_int 0)))]
1799 "")
1800
1801 (define_insn ""
1802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1803 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1804 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1805 "! TARGET_POWERPC"
1806 "{sf%I1|subf%I1c} %0,%2,%1")
1807
1808 (define_insn ""
1809 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1810 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1811 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1812 "TARGET_POWERPC"
1813 "@
1814 subf %0,%2,%1
1815 subfic %0,%2,%1")
1816
1817 (define_insn ""
1818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1819 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1820 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1821 (const_int 0)))
1822 (clobber (match_scratch:SI 3 "=r,r"))]
1823 "! TARGET_POWERPC"
1824 "@
1825 {sf.|subfc.} %3,%2,%1
1826 #"
1827 [(set_attr "type" "compare")
1828 (set_attr "length" "4,8")])
1829
1830 (define_insn ""
1831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1832 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1833 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1834 (const_int 0)))
1835 (clobber (match_scratch:P 3 "=r,r"))]
1836 "TARGET_POWERPC"
1837 "@
1838 subf. %3,%2,%1
1839 #"
1840 [(set_attr "type" "fast_compare")
1841 (set_attr "length" "4,8")])
1842
1843 (define_split
1844 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1845 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1846 (match_operand:P 2 "gpc_reg_operand" ""))
1847 (const_int 0)))
1848 (clobber (match_scratch:P 3 ""))]
1849 "reload_completed"
1850 [(set (match_dup 3)
1851 (minus:P (match_dup 1)
1852 (match_dup 2)))
1853 (set (match_dup 0)
1854 (compare:CC (match_dup 3)
1855 (const_int 0)))]
1856 "")
1857
1858 (define_insn ""
1859 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1860 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1861 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1862 (const_int 0)))
1863 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1864 (minus:SI (match_dup 1) (match_dup 2)))]
1865 "! TARGET_POWERPC"
1866 "@
1867 {sf.|subfc.} %0,%2,%1
1868 #"
1869 [(set_attr "type" "compare")
1870 (set_attr "length" "4,8")])
1871
1872 (define_insn ""
1873 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1874 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1875 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1876 (const_int 0)))
1877 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1878 (minus:P (match_dup 1)
1879 (match_dup 2)))]
1880 "TARGET_POWERPC"
1881 "@
1882 subf. %0,%2,%1
1883 #"
1884 [(set_attr "type" "fast_compare")
1885 (set_attr "length" "4,8")])
1886
1887 (define_split
1888 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1889 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1890 (match_operand:P 2 "gpc_reg_operand" ""))
1891 (const_int 0)))
1892 (set (match_operand:P 0 "gpc_reg_operand" "")
1893 (minus:P (match_dup 1)
1894 (match_dup 2)))]
1895 "reload_completed"
1896 [(set (match_dup 0)
1897 (minus:P (match_dup 1)
1898 (match_dup 2)))
1899 (set (match_dup 3)
1900 (compare:CC (match_dup 0)
1901 (const_int 0)))]
1902 "")
1903
1904 (define_expand "sub<mode>3"
1905 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1906 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1907 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1908 ""
1909 "
1910 {
1911 if (GET_CODE (operands[2]) == CONST_INT)
1912 {
1913 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1914 negate_rtx (<MODE>mode, operands[2])));
1915 DONE;
1916 }
1917 }")
1918
1919 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1920 ;; instruction and some auxiliary computations. Then we just have a single
1921 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1922 ;; combine.
1923
1924 (define_expand "sminsi3"
1925 [(set (match_dup 3)
1926 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1927 (match_operand:SI 2 "reg_or_short_operand" ""))
1928 (const_int 0)
1929 (minus:SI (match_dup 2) (match_dup 1))))
1930 (set (match_operand:SI 0 "gpc_reg_operand" "")
1931 (minus:SI (match_dup 2) (match_dup 3)))]
1932 "TARGET_POWER || TARGET_ISEL"
1933 "
1934 {
1935 if (TARGET_ISEL)
1936 {
1937 operands[2] = force_reg (SImode, operands[2]);
1938 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1939 DONE;
1940 }
1941
1942 operands[3] = gen_reg_rtx (SImode);
1943 }")
1944
1945 (define_split
1946 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1947 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1948 (match_operand:SI 2 "reg_or_short_operand" "")))
1949 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1950 "TARGET_POWER"
1951 [(set (match_dup 3)
1952 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1953 (const_int 0)
1954 (minus:SI (match_dup 2) (match_dup 1))))
1955 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1956 "")
1957
1958 (define_expand "smaxsi3"
1959 [(set (match_dup 3)
1960 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1961 (match_operand:SI 2 "reg_or_short_operand" ""))
1962 (const_int 0)
1963 (minus:SI (match_dup 2) (match_dup 1))))
1964 (set (match_operand:SI 0 "gpc_reg_operand" "")
1965 (plus:SI (match_dup 3) (match_dup 1)))]
1966 "TARGET_POWER || TARGET_ISEL"
1967 "
1968 {
1969 if (TARGET_ISEL)
1970 {
1971 operands[2] = force_reg (SImode, operands[2]);
1972 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1973 DONE;
1974 }
1975 operands[3] = gen_reg_rtx (SImode);
1976 }")
1977
1978 (define_split
1979 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1980 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1981 (match_operand:SI 2 "reg_or_short_operand" "")))
1982 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1983 "TARGET_POWER"
1984 [(set (match_dup 3)
1985 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1986 (const_int 0)
1987 (minus:SI (match_dup 2) (match_dup 1))))
1988 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1989 "")
1990
1991 (define_expand "uminsi3"
1992 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1993 (match_dup 5)))
1994 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1995 (match_dup 5)))
1996 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1997 (const_int 0)
1998 (minus:SI (match_dup 4) (match_dup 3))))
1999 (set (match_operand:SI 0 "gpc_reg_operand" "")
2000 (minus:SI (match_dup 2) (match_dup 3)))]
2001 "TARGET_POWER || TARGET_ISEL"
2002 "
2003 {
2004 if (TARGET_ISEL)
2005 {
2006 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
2007 DONE;
2008 }
2009 operands[3] = gen_reg_rtx (SImode);
2010 operands[4] = gen_reg_rtx (SImode);
2011 operands[5] = GEN_INT (-2147483647 - 1);
2012 }")
2013
2014 (define_expand "umaxsi3"
2015 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2016 (match_dup 5)))
2017 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2018 (match_dup 5)))
2019 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2020 (const_int 0)
2021 (minus:SI (match_dup 4) (match_dup 3))))
2022 (set (match_operand:SI 0 "gpc_reg_operand" "")
2023 (plus:SI (match_dup 3) (match_dup 1)))]
2024 "TARGET_POWER || TARGET_ISEL"
2025 "
2026 {
2027 if (TARGET_ISEL)
2028 {
2029 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
2030 DONE;
2031 }
2032 operands[3] = gen_reg_rtx (SImode);
2033 operands[4] = gen_reg_rtx (SImode);
2034 operands[5] = GEN_INT (-2147483647 - 1);
2035 }")
2036
2037 (define_insn ""
2038 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2039 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2040 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2041 (const_int 0)
2042 (minus:SI (match_dup 2) (match_dup 1))))]
2043 "TARGET_POWER"
2044 "doz%I2 %0,%1,%2")
2045
2046 (define_insn ""
2047 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2048 (compare:CC
2049 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2050 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2051 (const_int 0)
2052 (minus:SI (match_dup 2) (match_dup 1)))
2053 (const_int 0)))
2054 (clobber (match_scratch:SI 3 "=r,r"))]
2055 "TARGET_POWER"
2056 "@
2057 doz%I2. %3,%1,%2
2058 #"
2059 [(set_attr "type" "delayed_compare")
2060 (set_attr "length" "4,8")])
2061
2062 (define_split
2063 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2064 (compare:CC
2065 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2066 (match_operand:SI 2 "reg_or_short_operand" ""))
2067 (const_int 0)
2068 (minus:SI (match_dup 2) (match_dup 1)))
2069 (const_int 0)))
2070 (clobber (match_scratch:SI 3 ""))]
2071 "TARGET_POWER && reload_completed"
2072 [(set (match_dup 3)
2073 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2074 (const_int 0)
2075 (minus:SI (match_dup 2) (match_dup 1))))
2076 (set (match_dup 0)
2077 (compare:CC (match_dup 3)
2078 (const_int 0)))]
2079 "")
2080
2081 (define_insn ""
2082 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2083 (compare:CC
2084 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2085 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2086 (const_int 0)
2087 (minus:SI (match_dup 2) (match_dup 1)))
2088 (const_int 0)))
2089 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2090 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2091 (const_int 0)
2092 (minus:SI (match_dup 2) (match_dup 1))))]
2093 "TARGET_POWER"
2094 "@
2095 doz%I2. %0,%1,%2
2096 #"
2097 [(set_attr "type" "delayed_compare")
2098 (set_attr "length" "4,8")])
2099
2100 (define_split
2101 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2102 (compare:CC
2103 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2104 (match_operand:SI 2 "reg_or_short_operand" ""))
2105 (const_int 0)
2106 (minus:SI (match_dup 2) (match_dup 1)))
2107 (const_int 0)))
2108 (set (match_operand:SI 0 "gpc_reg_operand" "")
2109 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2110 (const_int 0)
2111 (minus:SI (match_dup 2) (match_dup 1))))]
2112 "TARGET_POWER && reload_completed"
2113 [(set (match_dup 0)
2114 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2115 (const_int 0)
2116 (minus:SI (match_dup 2) (match_dup 1))))
2117 (set (match_dup 3)
2118 (compare:CC (match_dup 0)
2119 (const_int 0)))]
2120 "")
2121
2122 ;; We don't need abs with condition code because such comparisons should
2123 ;; never be done.
2124 (define_expand "abssi2"
2125 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2126 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2127 ""
2128 "
2129 {
2130 if (TARGET_ISEL)
2131 {
2132 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2133 DONE;
2134 }
2135 else if (! TARGET_POWER)
2136 {
2137 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2138 DONE;
2139 }
2140 }")
2141
2142 (define_insn "*abssi2_power"
2143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2144 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2145 "TARGET_POWER"
2146 "abs %0,%1")
2147
2148 (define_insn_and_split "abs<mode>2_isel"
2149 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2150 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2151 (clobber (match_scratch:GPR 2 "=&b"))
2152 (clobber (match_scratch:CC 3 "=y"))]
2153 "TARGET_ISEL"
2154 "#"
2155 "&& reload_completed"
2156 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2157 (set (match_dup 3)
2158 (compare:CC (match_dup 1)
2159 (const_int 0)))
2160 (set (match_dup 0)
2161 (if_then_else:GPR (lt (match_dup 3)
2162 (const_int 0))
2163 (match_dup 2)
2164 (match_dup 1)))]
2165 "")
2166
2167 (define_insn_and_split "nabs<mode>2_isel"
2168 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2169 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2170 (clobber (match_scratch:GPR 2 "=&b"))
2171 (clobber (match_scratch:CC 3 "=y"))]
2172 "TARGET_ISEL"
2173 "#"
2174 "&& reload_completed"
2175 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2176 (set (match_dup 3)
2177 (compare:CC (match_dup 1)
2178 (const_int 0)))
2179 (set (match_dup 0)
2180 (if_then_else:GPR (lt (match_dup 3)
2181 (const_int 0))
2182 (match_dup 1)
2183 (match_dup 2)))]
2184 "")
2185
2186 (define_insn_and_split "abssi2_nopower"
2187 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2188 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2189 (clobber (match_scratch:SI 2 "=&r,&r"))]
2190 "! TARGET_POWER && ! TARGET_ISEL"
2191 "#"
2192 "&& reload_completed"
2193 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2194 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2195 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2196 "")
2197
2198 (define_insn "*nabs_power"
2199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2200 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2201 "TARGET_POWER"
2202 "nabs %0,%1")
2203
2204 (define_insn_and_split "*nabs_nopower"
2205 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2206 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2207 (clobber (match_scratch:SI 2 "=&r,&r"))]
2208 "! TARGET_POWER"
2209 "#"
2210 "&& reload_completed"
2211 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2212 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2213 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2214 "")
2215
2216 (define_expand "neg<mode>2"
2217 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2218 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2219 ""
2220 "")
2221
2222 (define_insn "*neg<mode>2_internal"
2223 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2224 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2225 ""
2226 "neg %0,%1")
2227
2228 (define_insn ""
2229 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2230 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2231 (const_int 0)))
2232 (clobber (match_scratch:P 2 "=r,r"))]
2233 ""
2234 "@
2235 neg. %2,%1
2236 #"
2237 [(set_attr "type" "fast_compare")
2238 (set_attr "length" "4,8")])
2239
2240 (define_split
2241 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2242 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2243 (const_int 0)))
2244 (clobber (match_scratch:P 2 ""))]
2245 "reload_completed"
2246 [(set (match_dup 2)
2247 (neg:P (match_dup 1)))
2248 (set (match_dup 0)
2249 (compare:CC (match_dup 2)
2250 (const_int 0)))]
2251 "")
2252
2253 (define_insn ""
2254 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2255 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2256 (const_int 0)))
2257 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2258 (neg:P (match_dup 1)))]
2259 ""
2260 "@
2261 neg. %0,%1
2262 #"
2263 [(set_attr "type" "fast_compare")
2264 (set_attr "length" "4,8")])
2265
2266 (define_split
2267 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2268 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2269 (const_int 0)))
2270 (set (match_operand:P 0 "gpc_reg_operand" "")
2271 (neg:P (match_dup 1)))]
2272 "reload_completed"
2273 [(set (match_dup 0)
2274 (neg:P (match_dup 1)))
2275 (set (match_dup 2)
2276 (compare:CC (match_dup 0)
2277 (const_int 0)))]
2278 "")
2279
2280 (define_insn "clz<mode>2"
2281 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2282 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2283 ""
2284 "{cntlz|cntlz<wd>} %0,%1"
2285 [(set_attr "type" "cntlz")])
2286
2287 (define_expand "ctz<mode>2"
2288 [(set (match_dup 2)
2289 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2290 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2291 (match_dup 2)))
2292 (clobber (scratch:CC))])
2293 (set (match_dup 4) (clz:GPR (match_dup 3)))
2294 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2295 (minus:GPR (match_dup 5) (match_dup 4)))]
2296 ""
2297 {
2298 operands[2] = gen_reg_rtx (<MODE>mode);
2299 operands[3] = gen_reg_rtx (<MODE>mode);
2300 operands[4] = gen_reg_rtx (<MODE>mode);
2301 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2302 })
2303
2304 (define_expand "ffs<mode>2"
2305 [(set (match_dup 2)
2306 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2307 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2308 (match_dup 2)))
2309 (clobber (scratch:CC))])
2310 (set (match_dup 4) (clz:GPR (match_dup 3)))
2311 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2312 (minus:GPR (match_dup 5) (match_dup 4)))]
2313 ""
2314 {
2315 operands[2] = gen_reg_rtx (<MODE>mode);
2316 operands[3] = gen_reg_rtx (<MODE>mode);
2317 operands[4] = gen_reg_rtx (<MODE>mode);
2318 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2319 })
2320
2321 (define_insn "popcntb<mode>2"
2322 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2323 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2324 UNSPEC_POPCNTB))]
2325 "TARGET_POPCNTB"
2326 "popcntb %0,%1")
2327
2328 (define_insn "popcntd<mode>2"
2329 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2330 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2331 "TARGET_POPCNTD"
2332 "popcnt<wd> %0,%1")
2333
2334 (define_expand "popcount<mode>2"
2335 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2336 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2337 "TARGET_POPCNTB || TARGET_POPCNTD"
2338 {
2339 rs6000_emit_popcount (operands[0], operands[1]);
2340 DONE;
2341 })
2342
2343 (define_insn "parity<mode>2_cmpb"
2344 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2345 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2346 "TARGET_CMPB && TARGET_POPCNTB"
2347 "prty<wd> %0,%1")
2348
2349 (define_expand "parity<mode>2"
2350 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2351 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2352 "TARGET_POPCNTB"
2353 {
2354 rs6000_emit_parity (operands[0], operands[1]);
2355 DONE;
2356 })
2357
2358 ;; Since the hardware zeros the upper part of the register, save generating the
2359 ;; AND immediate if we are converting to unsigned
2360 (define_insn "*bswaphi2_extenddi"
2361 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2362 (zero_extend:DI
2363 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2364 "TARGET_POWERPC64"
2365 "lhbrx %0,%y1"
2366 [(set_attr "length" "4")
2367 (set_attr "type" "load")])
2368
2369 (define_insn "*bswaphi2_extendsi"
2370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2371 (zero_extend:SI
2372 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2373 "TARGET_POWERPC"
2374 "lhbrx %0,%y1"
2375 [(set_attr "length" "4")
2376 (set_attr "type" "load")])
2377
2378 (define_expand "bswaphi2"
2379 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2380 (bswap:HI
2381 (match_operand:HI 1 "reg_or_mem_operand" "")))
2382 (clobber (match_scratch:SI 2 ""))])]
2383 ""
2384 {
2385 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2386 operands[1] = force_reg (HImode, operands[1]);
2387 })
2388
2389 (define_insn "bswaphi2_internal"
2390 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2391 (bswap:HI
2392 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2393 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2394 "TARGET_POWERPC"
2395 "@
2396 lhbrx %0,%y1
2397 sthbrx %1,%y0
2398 #"
2399 [(set_attr "length" "4,4,12")
2400 (set_attr "type" "load,store,*")])
2401
2402 (define_split
2403 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2404 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2405 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2406 "TARGET_POWERPC && reload_completed"
2407 [(set (match_dup 3)
2408 (zero_extract:SI (match_dup 4)
2409 (const_int 8)
2410 (const_int 16)))
2411 (set (match_dup 2)
2412 (and:SI (ashift:SI (match_dup 4)
2413 (const_int 8))
2414 (const_int 65280))) ;; 0xff00
2415 (set (match_dup 3)
2416 (ior:SI (match_dup 3)
2417 (match_dup 2)))]
2418 "
2419 {
2420 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2421 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2422 }")
2423
2424 (define_insn "*bswapsi2_extenddi"
2425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2426 (zero_extend:DI
2427 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2428 "TARGET_POWERPC64"
2429 "lwbrx %0,%y1"
2430 [(set_attr "length" "4")
2431 (set_attr "type" "load")])
2432
2433 (define_expand "bswapsi2"
2434 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2435 (bswap:SI
2436 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2437 ""
2438 {
2439 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2440 operands[1] = force_reg (SImode, operands[1]);
2441 })
2442
2443 (define_insn "*bswapsi2_internal"
2444 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2445 (bswap:SI
2446 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2447 ""
2448 "@
2449 {lbrx|lwbrx} %0,%y1
2450 {stbrx|stwbrx} %1,%y0
2451 #"
2452 [(set_attr "length" "4,4,12")
2453 (set_attr "type" "load,store,*")])
2454
2455 (define_split
2456 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2457 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2458 "reload_completed"
2459 [(set (match_dup 0)
2460 (rotate:SI (match_dup 1) (const_int 8)))
2461 (set (zero_extract:SI (match_dup 0)
2462 (const_int 8)
2463 (const_int 0))
2464 (match_dup 1))
2465 (set (zero_extract:SI (match_dup 0)
2466 (const_int 8)
2467 (const_int 16))
2468 (rotate:SI (match_dup 1)
2469 (const_int 16)))]
2470 "")
2471
2472 (define_expand "bswapdi2"
2473 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2474 (bswap:DI
2475 (match_operand:DI 1 "reg_or_mem_operand" "")))
2476 (clobber (match_scratch:DI 2 ""))
2477 (clobber (match_scratch:DI 3 ""))
2478 (clobber (match_scratch:DI 4 ""))])]
2479 ""
2480 {
2481 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2482 operands[1] = force_reg (DImode, operands[1]);
2483
2484 if (!TARGET_POWERPC64)
2485 {
2486 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2487 that uses 64-bit registers needs the same scratch registers as 64-bit
2488 mode. */
2489 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2490 DONE;
2491 }
2492 })
2493
2494 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2495 (define_insn "*bswapdi2_ldbrx"
2496 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2497 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2498 (clobber (match_scratch:DI 2 "=X,X,&r"))
2499 (clobber (match_scratch:DI 3 "=X,X,&r"))
2500 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2501 "TARGET_POWERPC64 && TARGET_LDBRX
2502 && (REG_P (operands[0]) || REG_P (operands[1]))"
2503 "@
2504 ldbrx %0,%y1
2505 stdbrx %1,%y0
2506 #"
2507 [(set_attr "length" "4,4,36")
2508 (set_attr "type" "load,store,*")])
2509
2510 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2511 (define_insn "*bswapdi2_64bit"
2512 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2513 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2514 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2515 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2516 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2517 "TARGET_POWERPC64 && !TARGET_LDBRX
2518 && (REG_P (operands[0]) || REG_P (operands[1]))"
2519 "#"
2520 [(set_attr "length" "16,12,36")])
2521
2522 (define_split
2523 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2524 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2525 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2526 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2527 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2528 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2529 [(const_int 0)]
2530 "
2531 {
2532 rtx dest = operands[0];
2533 rtx src = operands[1];
2534 rtx op2 = operands[2];
2535 rtx op3 = operands[3];
2536 rtx op4 = operands[4];
2537 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2538 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2539 rtx addr1;
2540 rtx addr2;
2541 rtx word_high;
2542 rtx word_low;
2543
2544 addr1 = XEXP (src, 0);
2545 if (GET_CODE (addr1) == PLUS)
2546 {
2547 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2548 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2549 }
2550 else
2551 {
2552 emit_move_insn (op2, GEN_INT (4));
2553 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2554 }
2555
2556 if (BYTES_BIG_ENDIAN)
2557 {
2558 word_high = change_address (src, SImode, addr1);
2559 word_low = change_address (src, SImode, addr2);
2560 }
2561 else
2562 {
2563 word_high = change_address (src, SImode, addr2);
2564 word_low = change_address (src, SImode, addr1);
2565 }
2566
2567 emit_insn (gen_bswapsi2 (op3_32, word_low));
2568 emit_insn (gen_bswapsi2 (op4_32, word_high));
2569 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2570 emit_insn (gen_iordi3 (dest, dest, op4));
2571 }")
2572
2573 (define_split
2574 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2575 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2576 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2577 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2578 (clobber (match_operand:DI 4 "" ""))]
2579 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2580 [(const_int 0)]
2581 "
2582 {
2583 rtx dest = operands[0];
2584 rtx src = operands[1];
2585 rtx op2 = operands[2];
2586 rtx op3 = operands[3];
2587 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2588 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2589 rtx addr1;
2590 rtx addr2;
2591 rtx word_high;
2592 rtx word_low;
2593
2594 addr1 = XEXP (dest, 0);
2595 if (GET_CODE (addr1) == PLUS)
2596 {
2597 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2598 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2599 }
2600 else
2601 {
2602 emit_move_insn (op2, GEN_INT (4));
2603 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2604 }
2605
2606 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2607 if (BYTES_BIG_ENDIAN)
2608 {
2609 word_high = change_address (dest, SImode, addr1);
2610 word_low = change_address (dest, SImode, addr2);
2611 emit_insn (gen_bswapsi2 (word_high, src_si));
2612 emit_insn (gen_bswapsi2 (word_low, op3_si));
2613 }
2614 else
2615 {
2616 word_high = change_address (dest, SImode, addr2);
2617 word_low = change_address (dest, SImode, addr1);
2618 emit_insn (gen_bswapsi2 (word_low, src_si));
2619 emit_insn (gen_bswapsi2 (word_high, op3_si));
2620 }
2621 }")
2622
2623 (define_split
2624 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2625 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2626 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2627 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2628 (clobber (match_operand:DI 4 "" ""))]
2629 "TARGET_POWERPC64 && reload_completed"
2630 [(const_int 0)]
2631 "
2632 {
2633 rtx dest = operands[0];
2634 rtx src = operands[1];
2635 rtx op2 = operands[2];
2636 rtx op3 = operands[3];
2637 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2638 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2639 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2640 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2641
2642 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2643 emit_insn (gen_bswapsi2 (dest_si, src_si));
2644 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2645 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2646 emit_insn (gen_iordi3 (dest, dest, op3));
2647 }")
2648
2649 (define_insn "bswapdi2_32bit"
2650 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2651 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2652 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2653 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2654 "#"
2655 [(set_attr "length" "16,12,36")])
2656
2657 (define_split
2658 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2659 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2660 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2661 "!TARGET_POWERPC64 && reload_completed"
2662 [(const_int 0)]
2663 "
2664 {
2665 rtx dest = operands[0];
2666 rtx src = operands[1];
2667 rtx op2 = operands[2];
2668 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2669 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2670 rtx addr1;
2671 rtx addr2;
2672 rtx word_high;
2673 rtx word_low;
2674
2675 addr1 = XEXP (src, 0);
2676 if (GET_CODE (addr1) == PLUS)
2677 {
2678 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2679 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2680 }
2681 else
2682 {
2683 emit_move_insn (op2, GEN_INT (4));
2684 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2685 }
2686
2687 if (BYTES_BIG_ENDIAN)
2688 {
2689 word_high = change_address (src, SImode, addr1);
2690 word_low = change_address (src, SImode, addr2);
2691 }
2692 else
2693 {
2694 word_high = change_address (src, SImode, addr2);
2695 word_low = change_address (src, SImode, addr1);
2696 }
2697
2698 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2699 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2700 }")
2701
2702 (define_split
2703 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2704 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2705 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2706 "!TARGET_POWERPC64 && reload_completed"
2707 [(const_int 0)]
2708 "
2709 {
2710 rtx dest = operands[0];
2711 rtx src = operands[1];
2712 rtx op2 = operands[2];
2713 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2714 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2715 rtx addr1;
2716 rtx addr2;
2717 rtx word_high;
2718 rtx word_low;
2719
2720 addr1 = XEXP (dest, 0);
2721 if (GET_CODE (addr1) == PLUS)
2722 {
2723 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2724 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2725 }
2726 else
2727 {
2728 emit_move_insn (op2, GEN_INT (4));
2729 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2730 }
2731
2732 if (BYTES_BIG_ENDIAN)
2733 {
2734 word_high = change_address (dest, SImode, addr1);
2735 word_low = change_address (dest, SImode, addr2);
2736 }
2737 else
2738 {
2739 word_high = change_address (dest, SImode, addr2);
2740 word_low = change_address (dest, SImode, addr1);
2741 }
2742
2743 emit_insn (gen_bswapsi2 (word_high, src_low));
2744 emit_insn (gen_bswapsi2 (word_low, src_high));
2745 }")
2746
2747 (define_split
2748 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2749 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2750 (clobber (match_operand:SI 2 "" ""))]
2751 "!TARGET_POWERPC64 && reload_completed"
2752 [(const_int 0)]
2753 "
2754 {
2755 rtx dest = operands[0];
2756 rtx src = operands[1];
2757 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2758 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2759 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2760 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2761
2762 emit_insn (gen_bswapsi2 (dest_high, src_low));
2763 emit_insn (gen_bswapsi2 (dest_low, src_high));
2764 }")
2765
2766 (define_expand "mulsi3"
2767 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2768 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2769 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2770 ""
2771 "
2772 {
2773 if (TARGET_POWER)
2774 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2775 else
2776 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2777 DONE;
2778 }")
2779
2780 (define_insn "mulsi3_mq"
2781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2782 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2783 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2784 (clobber (match_scratch:SI 3 "=q,q"))]
2785 "TARGET_POWER"
2786 "@
2787 {muls|mullw} %0,%1,%2
2788 {muli|mulli} %0,%1,%2"
2789 [(set (attr "type")
2790 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2791 (const_string "imul3")
2792 (match_operand:SI 2 "short_cint_operand" "")
2793 (const_string "imul2")]
2794 (const_string "imul")))])
2795
2796 (define_insn "mulsi3_no_mq"
2797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2798 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2799 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2800 "! TARGET_POWER"
2801 "@
2802 {muls|mullw} %0,%1,%2
2803 {muli|mulli} %0,%1,%2"
2804 [(set (attr "type")
2805 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2806 (const_string "imul3")
2807 (match_operand:SI 2 "short_cint_operand" "")
2808 (const_string "imul2")]
2809 (const_string "imul")))])
2810
2811 (define_insn "*mulsi3_mq_internal1"
2812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2813 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2814 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2815 (const_int 0)))
2816 (clobber (match_scratch:SI 3 "=r,r"))
2817 (clobber (match_scratch:SI 4 "=q,q"))]
2818 "TARGET_POWER"
2819 "@
2820 {muls.|mullw.} %3,%1,%2
2821 #"
2822 [(set_attr "type" "imul_compare")
2823 (set_attr "length" "4,8")])
2824
2825 (define_split
2826 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2827 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2828 (match_operand:SI 2 "gpc_reg_operand" ""))
2829 (const_int 0)))
2830 (clobber (match_scratch:SI 3 ""))
2831 (clobber (match_scratch:SI 4 ""))]
2832 "TARGET_POWER && reload_completed"
2833 [(parallel [(set (match_dup 3)
2834 (mult:SI (match_dup 1) (match_dup 2)))
2835 (clobber (match_dup 4))])
2836 (set (match_dup 0)
2837 (compare:CC (match_dup 3)
2838 (const_int 0)))]
2839 "")
2840
2841 (define_insn "*mulsi3_no_mq_internal1"
2842 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2843 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2844 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2845 (const_int 0)))
2846 (clobber (match_scratch:SI 3 "=r,r"))]
2847 "! TARGET_POWER"
2848 "@
2849 {muls.|mullw.} %3,%1,%2
2850 #"
2851 [(set_attr "type" "imul_compare")
2852 (set_attr "length" "4,8")])
2853
2854 (define_split
2855 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2856 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2857 (match_operand:SI 2 "gpc_reg_operand" ""))
2858 (const_int 0)))
2859 (clobber (match_scratch:SI 3 ""))]
2860 "! TARGET_POWER && reload_completed"
2861 [(set (match_dup 3)
2862 (mult:SI (match_dup 1) (match_dup 2)))
2863 (set (match_dup 0)
2864 (compare:CC (match_dup 3)
2865 (const_int 0)))]
2866 "")
2867
2868 (define_insn "*mulsi3_mq_internal2"
2869 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2870 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2871 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2872 (const_int 0)))
2873 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2874 (mult:SI (match_dup 1) (match_dup 2)))
2875 (clobber (match_scratch:SI 4 "=q,q"))]
2876 "TARGET_POWER"
2877 "@
2878 {muls.|mullw.} %0,%1,%2
2879 #"
2880 [(set_attr "type" "imul_compare")
2881 (set_attr "length" "4,8")])
2882
2883 (define_split
2884 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2885 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2886 (match_operand:SI 2 "gpc_reg_operand" ""))
2887 (const_int 0)))
2888 (set (match_operand:SI 0 "gpc_reg_operand" "")
2889 (mult:SI (match_dup 1) (match_dup 2)))
2890 (clobber (match_scratch:SI 4 ""))]
2891 "TARGET_POWER && reload_completed"
2892 [(parallel [(set (match_dup 0)
2893 (mult:SI (match_dup 1) (match_dup 2)))
2894 (clobber (match_dup 4))])
2895 (set (match_dup 3)
2896 (compare:CC (match_dup 0)
2897 (const_int 0)))]
2898 "")
2899
2900 (define_insn "*mulsi3_no_mq_internal2"
2901 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2902 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2903 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2904 (const_int 0)))
2905 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2906 (mult:SI (match_dup 1) (match_dup 2)))]
2907 "! TARGET_POWER"
2908 "@
2909 {muls.|mullw.} %0,%1,%2
2910 #"
2911 [(set_attr "type" "imul_compare")
2912 (set_attr "length" "4,8")])
2913
2914 (define_split
2915 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2916 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2917 (match_operand:SI 2 "gpc_reg_operand" ""))
2918 (const_int 0)))
2919 (set (match_operand:SI 0 "gpc_reg_operand" "")
2920 (mult:SI (match_dup 1) (match_dup 2)))]
2921 "! TARGET_POWER && reload_completed"
2922 [(set (match_dup 0)
2923 (mult:SI (match_dup 1) (match_dup 2)))
2924 (set (match_dup 3)
2925 (compare:CC (match_dup 0)
2926 (const_int 0)))]
2927 "")
2928
2929 ;; Operand 1 is divided by operand 2; quotient goes to operand
2930 ;; 0 and remainder to operand 3.
2931 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2932
2933 (define_expand "divmodsi4"
2934 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2935 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2936 (match_operand:SI 2 "gpc_reg_operand" "")))
2937 (set (match_operand:SI 3 "register_operand" "")
2938 (mod:SI (match_dup 1) (match_dup 2)))])]
2939 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2940 "
2941 {
2942 if (! TARGET_POWER && ! TARGET_POWERPC)
2943 {
2944 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2945 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2946 emit_insn (gen_divss_call ());
2947 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2948 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2949 DONE;
2950 }
2951 }")
2952
2953 (define_insn "*divmodsi4_internal"
2954 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2955 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2956 (match_operand:SI 2 "gpc_reg_operand" "r")))
2957 (set (match_operand:SI 3 "register_operand" "=q")
2958 (mod:SI (match_dup 1) (match_dup 2)))]
2959 "TARGET_POWER"
2960 "divs %0,%1,%2"
2961 [(set_attr "type" "idiv")])
2962
2963 (define_expand "udiv<mode>3"
2964 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2965 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2966 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2967 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2968 "
2969 {
2970 if (! TARGET_POWER && ! TARGET_POWERPC)
2971 {
2972 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2973 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2974 emit_insn (gen_quous_call ());
2975 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2976 DONE;
2977 }
2978 else if (TARGET_POWER)
2979 {
2980 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2981 DONE;
2982 }
2983 }")
2984
2985 (define_insn "udivsi3_mq"
2986 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2987 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2988 (match_operand:SI 2 "gpc_reg_operand" "r")))
2989 (clobber (match_scratch:SI 3 "=q"))]
2990 "TARGET_POWERPC && TARGET_POWER"
2991 "divwu %0,%1,%2"
2992 [(set_attr "type" "idiv")])
2993
2994 (define_insn "*udivsi3_no_mq"
2995 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2996 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2997 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2998 "TARGET_POWERPC && ! TARGET_POWER"
2999 "div<wd>u %0,%1,%2"
3000 [(set (attr "type")
3001 (cond [(match_operand:SI 0 "" "")
3002 (const_string "idiv")]
3003 (const_string "ldiv")))])
3004
3005
3006 ;; For powers of two we can do srai/aze for divide and then adjust for
3007 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
3008 ;; used; for PowerPC, force operands into register and do a normal divide;
3009 ;; for AIX common-mode, use quoss call on register operands.
3010 (define_expand "div<mode>3"
3011 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3012 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3013 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
3014 ""
3015 "
3016 {
3017 if (GET_CODE (operands[2]) == CONST_INT
3018 && INTVAL (operands[2]) > 0
3019 && exact_log2 (INTVAL (operands[2])) >= 0)
3020 ;
3021 else if (TARGET_POWERPC)
3022 {
3023 operands[2] = force_reg (<MODE>mode, operands[2]);
3024 if (TARGET_POWER)
3025 {
3026 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
3027 DONE;
3028 }
3029 }
3030 else if (TARGET_POWER)
3031 FAIL;
3032 else
3033 {
3034 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3035 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3036 emit_insn (gen_quoss_call ());
3037 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3038 DONE;
3039 }
3040 }")
3041
3042 (define_insn "divsi3_mq"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3045 (match_operand:SI 2 "gpc_reg_operand" "r")))
3046 (clobber (match_scratch:SI 3 "=q"))]
3047 "TARGET_POWERPC && TARGET_POWER"
3048 "divw %0,%1,%2"
3049 [(set_attr "type" "idiv")])
3050
3051 (define_insn "*div<mode>3_no_mq"
3052 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3053 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3054 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3055 "TARGET_POWERPC && ! TARGET_POWER"
3056 "div<wd> %0,%1,%2"
3057 [(set (attr "type")
3058 (cond [(match_operand:SI 0 "" "")
3059 (const_string "idiv")]
3060 (const_string "ldiv")))])
3061
3062 (define_expand "mod<mode>3"
3063 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3064 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3065 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3066 ""
3067 "
3068 {
3069 int i;
3070 rtx temp1;
3071 rtx temp2;
3072
3073 if (GET_CODE (operands[2]) != CONST_INT
3074 || INTVAL (operands[2]) <= 0
3075 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3076 FAIL;
3077
3078 temp1 = gen_reg_rtx (<MODE>mode);
3079 temp2 = gen_reg_rtx (<MODE>mode);
3080
3081 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3082 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3083 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3084 DONE;
3085 }")
3086
3087 (define_insn ""
3088 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3089 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3090 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3091 ""
3092 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3093 [(set_attr "type" "two")
3094 (set_attr "length" "8")])
3095
3096 (define_insn ""
3097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3098 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3099 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3100 (const_int 0)))
3101 (clobber (match_scratch:P 3 "=r,r"))]
3102 ""
3103 "@
3104 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3105 #"
3106 [(set_attr "type" "compare")
3107 (set_attr "length" "8,12")
3108 (set_attr "cell_micro" "not")])
3109
3110 (define_split
3111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3112 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3113 (match_operand:GPR 2 "exact_log2_cint_operand"
3114 ""))
3115 (const_int 0)))
3116 (clobber (match_scratch:GPR 3 ""))]
3117 "reload_completed"
3118 [(set (match_dup 3)
3119 (div:<MODE> (match_dup 1) (match_dup 2)))
3120 (set (match_dup 0)
3121 (compare:CC (match_dup 3)
3122 (const_int 0)))]
3123 "")
3124
3125 (define_insn ""
3126 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3127 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3128 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3129 (const_int 0)))
3130 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3131 (div:P (match_dup 1) (match_dup 2)))]
3132 ""
3133 "@
3134 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3135 #"
3136 [(set_attr "type" "compare")
3137 (set_attr "length" "8,12")
3138 (set_attr "cell_micro" "not")])
3139
3140 (define_split
3141 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3142 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3143 (match_operand:GPR 2 "exact_log2_cint_operand"
3144 ""))
3145 (const_int 0)))
3146 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3147 (div:GPR (match_dup 1) (match_dup 2)))]
3148 "reload_completed"
3149 [(set (match_dup 0)
3150 (div:<MODE> (match_dup 1) (match_dup 2)))
3151 (set (match_dup 3)
3152 (compare:CC (match_dup 0)
3153 (const_int 0)))]
3154 "")
3155
3156 (define_insn ""
3157 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3158 (udiv:SI
3159 (plus:DI (ashift:DI
3160 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3161 (const_int 32))
3162 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3163 (match_operand:SI 3 "gpc_reg_operand" "r")))
3164 (set (match_operand:SI 2 "register_operand" "=*q")
3165 (umod:SI
3166 (plus:DI (ashift:DI
3167 (zero_extend:DI (match_dup 1)) (const_int 32))
3168 (zero_extend:DI (match_dup 4)))
3169 (match_dup 3)))]
3170 "TARGET_POWER"
3171 "div %0,%1,%3"
3172 [(set_attr "type" "idiv")])
3173
3174 ;; To do unsigned divide we handle the cases of the divisor looking like a
3175 ;; negative number. If it is a constant that is less than 2**31, we don't
3176 ;; have to worry about the branches. So make a few subroutines here.
3177 ;;
3178 ;; First comes the normal case.
3179 (define_expand "udivmodsi4_normal"
3180 [(set (match_dup 4) (const_int 0))
3181 (parallel [(set (match_operand:SI 0 "" "")
3182 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3183 (const_int 32))
3184 (zero_extend:DI (match_operand:SI 1 "" "")))
3185 (match_operand:SI 2 "" "")))
3186 (set (match_operand:SI 3 "" "")
3187 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3188 (const_int 32))
3189 (zero_extend:DI (match_dup 1)))
3190 (match_dup 2)))])]
3191 "TARGET_POWER"
3192 "
3193 { operands[4] = gen_reg_rtx (SImode); }")
3194
3195 ;; This handles the branches.
3196 (define_expand "udivmodsi4_tests"
3197 [(set (match_operand:SI 0 "" "") (const_int 0))
3198 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3199 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3200 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3201 (label_ref (match_operand:SI 4 "" "")) (pc)))
3202 (set (match_dup 0) (const_int 1))
3203 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3204 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3205 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3206 (label_ref (match_dup 4)) (pc)))]
3207 "TARGET_POWER"
3208 "
3209 { operands[5] = gen_reg_rtx (CCUNSmode);
3210 operands[6] = gen_reg_rtx (CCmode);
3211 }")
3212
3213 (define_expand "udivmodsi4"
3214 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3215 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3216 (match_operand:SI 2 "reg_or_cint_operand" "")))
3217 (set (match_operand:SI 3 "gpc_reg_operand" "")
3218 (umod:SI (match_dup 1) (match_dup 2)))])]
3219 ""
3220 "
3221 {
3222 rtx label = 0;
3223
3224 if (! TARGET_POWER)
3225 {
3226 if (! TARGET_POWERPC)
3227 {
3228 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3229 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3230 emit_insn (gen_divus_call ());
3231 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3232 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3233 DONE;
3234 }
3235 else
3236 FAIL;
3237 }
3238
3239 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3240 {
3241 operands[2] = force_reg (SImode, operands[2]);
3242 label = gen_label_rtx ();
3243 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3244 operands[3], label));
3245 }
3246 else
3247 operands[2] = force_reg (SImode, operands[2]);
3248
3249 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3250 operands[3]));
3251 if (label)
3252 emit_label (label);
3253
3254 DONE;
3255 }")
3256
3257 ;; AIX architecture-independent common-mode multiply (DImode),
3258 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3259 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3260 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3261 ;; assumed unused if generating common-mode, so ignore.
3262 (define_insn "mulh_call"
3263 [(set (reg:SI 3)
3264 (truncate:SI
3265 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3266 (sign_extend:DI (reg:SI 4)))
3267 (const_int 32))))
3268 (clobber (reg:SI LR_REGNO))]
3269 "! TARGET_POWER && ! TARGET_POWERPC"
3270 "bla __mulh"
3271 [(set_attr "type" "imul")])
3272
3273 (define_insn "mull_call"
3274 [(set (reg:DI 3)
3275 (mult:DI (sign_extend:DI (reg:SI 3))
3276 (sign_extend:DI (reg:SI 4))))
3277 (clobber (reg:SI LR_REGNO))
3278 (clobber (reg:SI 0))]
3279 "! TARGET_POWER && ! TARGET_POWERPC"
3280 "bla __mull"
3281 [(set_attr "type" "imul")])
3282
3283 (define_insn "divss_call"
3284 [(set (reg:SI 3)
3285 (div:SI (reg:SI 3) (reg:SI 4)))
3286 (set (reg:SI 4)
3287 (mod:SI (reg:SI 3) (reg:SI 4)))
3288 (clobber (reg:SI LR_REGNO))
3289 (clobber (reg:SI 0))]
3290 "! TARGET_POWER && ! TARGET_POWERPC"
3291 "bla __divss"
3292 [(set_attr "type" "idiv")])
3293
3294 (define_insn "divus_call"
3295 [(set (reg:SI 3)
3296 (udiv:SI (reg:SI 3) (reg:SI 4)))
3297 (set (reg:SI 4)
3298 (umod:SI (reg:SI 3) (reg:SI 4)))
3299 (clobber (reg:SI LR_REGNO))
3300 (clobber (reg:SI 0))
3301 (clobber (match_scratch:CC 0 "=x"))
3302 (clobber (reg:CC CR1_REGNO))]
3303 "! TARGET_POWER && ! TARGET_POWERPC"
3304 "bla __divus"
3305 [(set_attr "type" "idiv")])
3306
3307 (define_insn "quoss_call"
3308 [(set (reg:SI 3)
3309 (div:SI (reg:SI 3) (reg:SI 4)))
3310 (clobber (reg:SI LR_REGNO))]
3311 "! TARGET_POWER && ! TARGET_POWERPC"
3312 "bla __quoss"
3313 [(set_attr "type" "idiv")])
3314
3315 (define_insn "quous_call"
3316 [(set (reg:SI 3)
3317 (udiv:SI (reg:SI 3) (reg:SI 4)))
3318 (clobber (reg:SI LR_REGNO))
3319 (clobber (reg:SI 0))
3320 (clobber (match_scratch:CC 0 "=x"))
3321 (clobber (reg:CC CR1_REGNO))]
3322 "! TARGET_POWER && ! TARGET_POWERPC"
3323 "bla __quous"
3324 [(set_attr "type" "idiv")])
3325 \f
3326 ;; Logical instructions
3327 ;; The logical instructions are mostly combined by using match_operator,
3328 ;; but the plain AND insns are somewhat different because there is no
3329 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3330 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3331
3332 (define_expand "andsi3"
3333 [(parallel
3334 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3335 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3336 (match_operand:SI 2 "and_operand" "")))
3337 (clobber (match_scratch:CC 3 ""))])]
3338 ""
3339 "")
3340
3341 (define_insn "andsi3_mc"
3342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3343 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3344 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3345 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3346 "rs6000_gen_cell_microcode"
3347 "@
3348 and %0,%1,%2
3349 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3350 {andil.|andi.} %0,%1,%b2
3351 {andiu.|andis.} %0,%1,%u2"
3352 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3353
3354 (define_insn "andsi3_nomc"
3355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3356 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3357 (match_operand:SI 2 "and_operand" "?r,T")))
3358 (clobber (match_scratch:CC 3 "=X,X"))]
3359 "!rs6000_gen_cell_microcode"
3360 "@
3361 and %0,%1,%2
3362 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3363
3364 (define_insn "andsi3_internal0_nomc"
3365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3366 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3367 (match_operand:SI 2 "and_operand" "?r,T")))]
3368 "!rs6000_gen_cell_microcode"
3369 "@
3370 and %0,%1,%2
3371 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3372
3373
3374 ;; Note to set cr's other than cr0 we do the and immediate and then
3375 ;; the test again -- this avoids a mfcr which on the higher end
3376 ;; machines causes an execution serialization
3377
3378 (define_insn "*andsi3_internal2_mc"
3379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3380 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3381 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3382 (const_int 0)))
3383 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3384 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3385 "TARGET_32BIT && rs6000_gen_cell_microcode"
3386 "@
3387 and. %3,%1,%2
3388 {andil.|andi.} %3,%1,%b2
3389 {andiu.|andis.} %3,%1,%u2
3390 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3391 #
3392 #
3393 #
3394 #"
3395 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3396 compare,compare,compare,compare")
3397 (set_attr "length" "4,4,4,4,8,8,8,8")])
3398
3399 (define_insn "*andsi3_internal3_mc"
3400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3401 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3402 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3403 (const_int 0)))
3404 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3405 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3406 "TARGET_64BIT && rs6000_gen_cell_microcode"
3407 "@
3408 #
3409 {andil.|andi.} %3,%1,%b2
3410 {andiu.|andis.} %3,%1,%u2
3411 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3412 #
3413 #
3414 #
3415 #"
3416 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3417 compare,compare,compare")
3418 (set_attr "length" "8,4,4,4,8,8,8,8")])
3419
3420 (define_split
3421 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3422 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3423 (match_operand:GPR 2 "and_operand" ""))
3424 (const_int 0)))
3425 (clobber (match_scratch:GPR 3 ""))
3426 (clobber (match_scratch:CC 4 ""))]
3427 "reload_completed"
3428 [(parallel [(set (match_dup 3)
3429 (and:<MODE> (match_dup 1)
3430 (match_dup 2)))
3431 (clobber (match_dup 4))])
3432 (set (match_dup 0)
3433 (compare:CC (match_dup 3)
3434 (const_int 0)))]
3435 "")
3436
3437 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3438 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3439
3440 (define_split
3441 [(set (match_operand:CC 0 "cc_reg_operand" "")
3442 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3443 (match_operand:SI 2 "gpc_reg_operand" ""))
3444 (const_int 0)))
3445 (clobber (match_scratch:SI 3 ""))
3446 (clobber (match_scratch:CC 4 ""))]
3447 "TARGET_POWERPC64 && reload_completed"
3448 [(parallel [(set (match_dup 3)
3449 (and:SI (match_dup 1)
3450 (match_dup 2)))
3451 (clobber (match_dup 4))])
3452 (set (match_dup 0)
3453 (compare:CC (match_dup 3)
3454 (const_int 0)))]
3455 "")
3456
3457 (define_insn "*andsi3_internal4"
3458 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3459 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3460 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3461 (const_int 0)))
3462 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3463 (and:SI (match_dup 1)
3464 (match_dup 2)))
3465 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3466 "TARGET_32BIT && rs6000_gen_cell_microcode"
3467 "@
3468 and. %0,%1,%2
3469 {andil.|andi.} %0,%1,%b2
3470 {andiu.|andis.} %0,%1,%u2
3471 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3472 #
3473 #
3474 #
3475 #"
3476 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3477 compare,compare,compare,compare")
3478 (set_attr "length" "4,4,4,4,8,8,8,8")])
3479
3480 (define_insn "*andsi3_internal5_mc"
3481 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3482 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3483 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3484 (const_int 0)))
3485 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3486 (and:SI (match_dup 1)
3487 (match_dup 2)))
3488 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3489 "TARGET_64BIT && rs6000_gen_cell_microcode"
3490 "@
3491 #
3492 {andil.|andi.} %0,%1,%b2
3493 {andiu.|andis.} %0,%1,%u2
3494 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3495 #
3496 #
3497 #
3498 #"
3499 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3500 compare,compare,compare")
3501 (set_attr "length" "8,4,4,4,8,8,8,8")])
3502
3503 (define_split
3504 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3505 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3506 (match_operand:SI 2 "and_operand" ""))
3507 (const_int 0)))
3508 (set (match_operand:SI 0 "gpc_reg_operand" "")
3509 (and:SI (match_dup 1)
3510 (match_dup 2)))
3511 (clobber (match_scratch:CC 4 ""))]
3512 "reload_completed"
3513 [(parallel [(set (match_dup 0)
3514 (and:SI (match_dup 1)
3515 (match_dup 2)))
3516 (clobber (match_dup 4))])
3517 (set (match_dup 3)
3518 (compare:CC (match_dup 0)
3519 (const_int 0)))]
3520 "")
3521
3522 (define_split
3523 [(set (match_operand:CC 3 "cc_reg_operand" "")
3524 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3525 (match_operand:SI 2 "gpc_reg_operand" ""))
3526 (const_int 0)))
3527 (set (match_operand:SI 0 "gpc_reg_operand" "")
3528 (and:SI (match_dup 1)
3529 (match_dup 2)))
3530 (clobber (match_scratch:CC 4 ""))]
3531 "TARGET_POWERPC64 && reload_completed"
3532 [(parallel [(set (match_dup 0)
3533 (and:SI (match_dup 1)
3534 (match_dup 2)))
3535 (clobber (match_dup 4))])
3536 (set (match_dup 3)
3537 (compare:CC (match_dup 0)
3538 (const_int 0)))]
3539 "")
3540
3541 ;; Handle the PowerPC64 rlwinm corner case
3542
3543 (define_insn_and_split "*andsi3_internal6"
3544 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3545 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3546 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3547 "TARGET_POWERPC64"
3548 "#"
3549 "TARGET_POWERPC64"
3550 [(set (match_dup 0)
3551 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3552 (match_dup 4)))
3553 (set (match_dup 0)
3554 (rotate:SI (match_dup 0) (match_dup 5)))]
3555 "
3556 {
3557 int mb = extract_MB (operands[2]);
3558 int me = extract_ME (operands[2]);
3559 operands[3] = GEN_INT (me + 1);
3560 operands[5] = GEN_INT (32 - (me + 1));
3561 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3562 }"
3563 [(set_attr "length" "8")])
3564
3565 (define_expand "iorsi3"
3566 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3567 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3568 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3569 ""
3570 "
3571 {
3572 if (GET_CODE (operands[2]) == CONST_INT
3573 && ! logical_operand (operands[2], SImode))
3574 {
3575 HOST_WIDE_INT value = INTVAL (operands[2]);
3576 rtx tmp = ((!can_create_pseudo_p ()
3577 || rtx_equal_p (operands[0], operands[1]))
3578 ? operands[0] : gen_reg_rtx (SImode));
3579
3580 emit_insn (gen_iorsi3 (tmp, operands[1],
3581 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3582 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3583 DONE;
3584 }
3585 }")
3586
3587 (define_expand "xorsi3"
3588 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3589 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3590 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3591 ""
3592 "
3593 {
3594 if (GET_CODE (operands[2]) == CONST_INT
3595 && ! logical_operand (operands[2], SImode))
3596 {
3597 HOST_WIDE_INT value = INTVAL (operands[2]);
3598 rtx tmp = ((!can_create_pseudo_p ()
3599 || rtx_equal_p (operands[0], operands[1]))
3600 ? operands[0] : gen_reg_rtx (SImode));
3601
3602 emit_insn (gen_xorsi3 (tmp, operands[1],
3603 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3604 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3605 DONE;
3606 }
3607 }")
3608
3609 (define_insn "*boolsi3_internal1"
3610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3611 (match_operator:SI 3 "boolean_or_operator"
3612 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3613 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3614 ""
3615 "@
3616 %q3 %0,%1,%2
3617 {%q3il|%q3i} %0,%1,%b2
3618 {%q3iu|%q3is} %0,%1,%u2")
3619
3620 (define_insn "*boolsi3_internal2"
3621 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3622 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3623 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3624 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3625 (const_int 0)))
3626 (clobber (match_scratch:SI 3 "=r,r"))]
3627 "TARGET_32BIT"
3628 "@
3629 %q4. %3,%1,%2
3630 #"
3631 [(set_attr "type" "fast_compare,compare")
3632 (set_attr "length" "4,8")])
3633
3634 (define_split
3635 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3636 (compare:CC (match_operator:SI 4 "boolean_operator"
3637 [(match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "gpc_reg_operand" "")])
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 3 ""))]
3641 "TARGET_32BIT && reload_completed"
3642 [(set (match_dup 3) (match_dup 4))
3643 (set (match_dup 0)
3644 (compare:CC (match_dup 3)
3645 (const_int 0)))]
3646 "")
3647
3648 (define_insn "*boolsi3_internal3"
3649 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3650 (compare:CC (match_operator:SI 4 "boolean_operator"
3651 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3652 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3653 (const_int 0)))
3654 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3655 (match_dup 4))]
3656 "TARGET_32BIT"
3657 "@
3658 %q4. %0,%1,%2
3659 #"
3660 [(set_attr "type" "fast_compare,compare")
3661 (set_attr "length" "4,8")])
3662
3663 (define_split
3664 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3665 (compare:CC (match_operator:SI 4 "boolean_operator"
3666 [(match_operand:SI 1 "gpc_reg_operand" "")
3667 (match_operand:SI 2 "gpc_reg_operand" "")])
3668 (const_int 0)))
3669 (set (match_operand:SI 0 "gpc_reg_operand" "")
3670 (match_dup 4))]
3671 "TARGET_32BIT && reload_completed"
3672 [(set (match_dup 0) (match_dup 4))
3673 (set (match_dup 3)
3674 (compare:CC (match_dup 0)
3675 (const_int 0)))]
3676 "")
3677
3678 ;; Split a logical operation that we can't do in one insn into two insns,
3679 ;; each of which does one 16-bit part. This is used by combine.
3680
3681 (define_split
3682 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3683 (match_operator:SI 3 "boolean_or_operator"
3684 [(match_operand:SI 1 "gpc_reg_operand" "")
3685 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3686 ""
3687 [(set (match_dup 0) (match_dup 4))
3688 (set (match_dup 0) (match_dup 5))]
3689 "
3690 {
3691 rtx i;
3692 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3693 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3694 operands[1], i);
3695 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3696 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3697 operands[0], i);
3698 }")
3699
3700 (define_insn "*boolcsi3_internal1"
3701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3702 (match_operator:SI 3 "boolean_operator"
3703 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3704 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3705 ""
3706 "%q3 %0,%2,%1")
3707
3708 (define_insn "*boolcsi3_internal2"
3709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3710 (compare:CC (match_operator:SI 4 "boolean_operator"
3711 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3712 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3713 (const_int 0)))
3714 (clobber (match_scratch:SI 3 "=r,r"))]
3715 "TARGET_32BIT"
3716 "@
3717 %q4. %3,%2,%1
3718 #"
3719 [(set_attr "type" "compare")
3720 (set_attr "length" "4,8")])
3721
3722 (define_split
3723 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3724 (compare:CC (match_operator:SI 4 "boolean_operator"
3725 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3726 (match_operand:SI 2 "gpc_reg_operand" "")])
3727 (const_int 0)))
3728 (clobber (match_scratch:SI 3 ""))]
3729 "TARGET_32BIT && reload_completed"
3730 [(set (match_dup 3) (match_dup 4))
3731 (set (match_dup 0)
3732 (compare:CC (match_dup 3)
3733 (const_int 0)))]
3734 "")
3735
3736 (define_insn "*boolcsi3_internal3"
3737 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3738 (compare:CC (match_operator:SI 4 "boolean_operator"
3739 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3740 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3741 (const_int 0)))
3742 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3743 (match_dup 4))]
3744 "TARGET_32BIT"
3745 "@
3746 %q4. %0,%2,%1
3747 #"
3748 [(set_attr "type" "compare")
3749 (set_attr "length" "4,8")])
3750
3751 (define_split
3752 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3753 (compare:CC (match_operator:SI 4 "boolean_operator"
3754 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3755 (match_operand:SI 2 "gpc_reg_operand" "")])
3756 (const_int 0)))
3757 (set (match_operand:SI 0 "gpc_reg_operand" "")
3758 (match_dup 4))]
3759 "TARGET_32BIT && reload_completed"
3760 [(set (match_dup 0) (match_dup 4))
3761 (set (match_dup 3)
3762 (compare:CC (match_dup 0)
3763 (const_int 0)))]
3764 "")
3765
3766 (define_insn "*boolccsi3_internal1"
3767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3768 (match_operator:SI 3 "boolean_operator"
3769 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3770 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3771 ""
3772 "%q3 %0,%1,%2")
3773
3774 (define_insn "*boolccsi3_internal2"
3775 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3776 (compare:CC (match_operator:SI 4 "boolean_operator"
3777 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3778 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3779 (const_int 0)))
3780 (clobber (match_scratch:SI 3 "=r,r"))]
3781 "TARGET_32BIT"
3782 "@
3783 %q4. %3,%1,%2
3784 #"
3785 [(set_attr "type" "fast_compare,compare")
3786 (set_attr "length" "4,8")])
3787
3788 (define_split
3789 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3790 (compare:CC (match_operator:SI 4 "boolean_operator"
3791 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3792 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3793 (const_int 0)))
3794 (clobber (match_scratch:SI 3 ""))]
3795 "TARGET_32BIT && reload_completed"
3796 [(set (match_dup 3) (match_dup 4))
3797 (set (match_dup 0)
3798 (compare:CC (match_dup 3)
3799 (const_int 0)))]
3800 "")
3801
3802 (define_insn "*boolccsi3_internal3"
3803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3804 (compare:CC (match_operator:SI 4 "boolean_operator"
3805 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3806 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3807 (const_int 0)))
3808 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3809 (match_dup 4))]
3810 "TARGET_32BIT"
3811 "@
3812 %q4. %0,%1,%2
3813 #"
3814 [(set_attr "type" "fast_compare,compare")
3815 (set_attr "length" "4,8")])
3816
3817 (define_split
3818 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3819 (compare:CC (match_operator:SI 4 "boolean_operator"
3820 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3821 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3822 (const_int 0)))
3823 (set (match_operand:SI 0 "gpc_reg_operand" "")
3824 (match_dup 4))]
3825 "TARGET_32BIT && reload_completed"
3826 [(set (match_dup 0) (match_dup 4))
3827 (set (match_dup 3)
3828 (compare:CC (match_dup 0)
3829 (const_int 0)))]
3830 "")
3831
3832 ;; maskir insn. We need four forms because things might be in arbitrary
3833 ;; orders. Don't define forms that only set CR fields because these
3834 ;; would modify an input register.
3835
3836 (define_insn "*maskir_internal1"
3837 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3838 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3839 (match_operand:SI 1 "gpc_reg_operand" "0"))
3840 (and:SI (match_dup 2)
3841 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3842 "TARGET_POWER"
3843 "maskir %0,%3,%2")
3844
3845 (define_insn "*maskir_internal2"
3846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3847 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3848 (match_operand:SI 1 "gpc_reg_operand" "0"))
3849 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3850 (match_dup 2))))]
3851 "TARGET_POWER"
3852 "maskir %0,%3,%2")
3853
3854 (define_insn "*maskir_internal3"
3855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3856 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3857 (match_operand:SI 3 "gpc_reg_operand" "r"))
3858 (and:SI (not:SI (match_dup 2))
3859 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3860 "TARGET_POWER"
3861 "maskir %0,%3,%2")
3862
3863 (define_insn "*maskir_internal4"
3864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3865 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3866 (match_operand:SI 2 "gpc_reg_operand" "r"))
3867 (and:SI (not:SI (match_dup 2))
3868 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3869 "TARGET_POWER"
3870 "maskir %0,%3,%2")
3871
3872 (define_insn "*maskir_internal5"
3873 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3874 (compare:CC
3875 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3876 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3877 (and:SI (match_dup 2)
3878 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3879 (const_int 0)))
3880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3881 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3882 (and:SI (match_dup 2) (match_dup 3))))]
3883 "TARGET_POWER"
3884 "@
3885 maskir. %0,%3,%2
3886 #"
3887 [(set_attr "type" "compare")
3888 (set_attr "length" "4,8")])
3889
3890 (define_split
3891 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3892 (compare:CC
3893 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3894 (match_operand:SI 1 "gpc_reg_operand" ""))
3895 (and:SI (match_dup 2)
3896 (match_operand:SI 3 "gpc_reg_operand" "")))
3897 (const_int 0)))
3898 (set (match_operand:SI 0 "gpc_reg_operand" "")
3899 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3900 (and:SI (match_dup 2) (match_dup 3))))]
3901 "TARGET_POWER && reload_completed"
3902 [(set (match_dup 0)
3903 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3904 (and:SI (match_dup 2) (match_dup 3))))
3905 (set (match_dup 4)
3906 (compare:CC (match_dup 0)
3907 (const_int 0)))]
3908 "")
3909
3910 (define_insn "*maskir_internal6"
3911 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3912 (compare:CC
3913 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3914 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3915 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3916 (match_dup 2)))
3917 (const_int 0)))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3919 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3920 (and:SI (match_dup 3) (match_dup 2))))]
3921 "TARGET_POWER"
3922 "@
3923 maskir. %0,%3,%2
3924 #"
3925 [(set_attr "type" "compare")
3926 (set_attr "length" "4,8")])
3927
3928 (define_split
3929 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3930 (compare:CC
3931 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3932 (match_operand:SI 1 "gpc_reg_operand" ""))
3933 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3934 (match_dup 2)))
3935 (const_int 0)))
3936 (set (match_operand:SI 0 "gpc_reg_operand" "")
3937 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3938 (and:SI (match_dup 3) (match_dup 2))))]
3939 "TARGET_POWER && reload_completed"
3940 [(set (match_dup 0)
3941 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3942 (and:SI (match_dup 3) (match_dup 2))))
3943 (set (match_dup 4)
3944 (compare:CC (match_dup 0)
3945 (const_int 0)))]
3946 "")
3947
3948 (define_insn "*maskir_internal7"
3949 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3950 (compare:CC
3951 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3952 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3953 (and:SI (not:SI (match_dup 2))
3954 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3955 (const_int 0)))
3956 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3957 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3958 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3959 "TARGET_POWER"
3960 "@
3961 maskir. %0,%3,%2
3962 #"
3963 [(set_attr "type" "compare")
3964 (set_attr "length" "4,8")])
3965
3966 (define_split
3967 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3968 (compare:CC
3969 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3970 (match_operand:SI 3 "gpc_reg_operand" ""))
3971 (and:SI (not:SI (match_dup 2))
3972 (match_operand:SI 1 "gpc_reg_operand" "")))
3973 (const_int 0)))
3974 (set (match_operand:SI 0 "gpc_reg_operand" "")
3975 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3976 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3977 "TARGET_POWER && reload_completed"
3978 [(set (match_dup 0)
3979 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3980 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3981 (set (match_dup 4)
3982 (compare:CC (match_dup 0)
3983 (const_int 0)))]
3984 "")
3985
3986 (define_insn "*maskir_internal8"
3987 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3988 (compare:CC
3989 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3990 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3991 (and:SI (not:SI (match_dup 2))
3992 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3993 (const_int 0)))
3994 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3995 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3996 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3997 "TARGET_POWER"
3998 "@
3999 maskir. %0,%3,%2
4000 #"
4001 [(set_attr "type" "compare")
4002 (set_attr "length" "4,8")])
4003
4004 (define_split
4005 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4006 (compare:CC
4007 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
4008 (match_operand:SI 2 "gpc_reg_operand" ""))
4009 (and:SI (not:SI (match_dup 2))
4010 (match_operand:SI 1 "gpc_reg_operand" "")))
4011 (const_int 0)))
4012 (set (match_operand:SI 0 "gpc_reg_operand" "")
4013 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4014 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
4015 "TARGET_POWER && reload_completed"
4016 [(set (match_dup 0)
4017 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4018 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
4019 (set (match_dup 4)
4020 (compare:CC (match_dup 0)
4021 (const_int 0)))]
4022 "")
4023 \f
4024 ;; Rotate and shift insns, in all their variants. These support shifts,
4025 ;; field inserts and extracts, and various combinations thereof.
4026 (define_expand "insv"
4027 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
4028 (match_operand:SI 1 "const_int_operand" "")
4029 (match_operand:SI 2 "const_int_operand" ""))
4030 (match_operand 3 "gpc_reg_operand" ""))]
4031 ""
4032 "
4033 {
4034 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4035 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4036 compiler if the address of the structure is taken later. Likewise, do
4037 not handle invalid E500 subregs. */
4038 if (GET_CODE (operands[0]) == SUBREG
4039 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
4040 || ((TARGET_E500_DOUBLE || TARGET_SPE)
4041 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
4042 FAIL;
4043
4044 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
4045 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
4046 else
4047 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
4048 DONE;
4049 }")
4050
4051 (define_insn "insvsi"
4052 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4053 (match_operand:SI 1 "const_int_operand" "i")
4054 (match_operand:SI 2 "const_int_operand" "i"))
4055 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4056 ""
4057 "*
4058 {
4059 int start = INTVAL (operands[2]) & 31;
4060 int size = INTVAL (operands[1]) & 31;
4061
4062 operands[4] = GEN_INT (32 - start - size);
4063 operands[1] = GEN_INT (start + size - 1);
4064 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4065 }"
4066 [(set_attr "type" "insert_word")])
4067
4068 (define_insn "*insvsi_internal1"
4069 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4070 (match_operand:SI 1 "const_int_operand" "i")
4071 (match_operand:SI 2 "const_int_operand" "i"))
4072 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4073 (match_operand:SI 4 "const_int_operand" "i")))]
4074 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4075 "*
4076 {
4077 int shift = INTVAL (operands[4]) & 31;
4078 int start = INTVAL (operands[2]) & 31;
4079 int size = INTVAL (operands[1]) & 31;
4080
4081 operands[4] = GEN_INT (shift - start - size);
4082 operands[1] = GEN_INT (start + size - 1);
4083 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4084 }"
4085 [(set_attr "type" "insert_word")])
4086
4087 (define_insn "*insvsi_internal2"
4088 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4089 (match_operand:SI 1 "const_int_operand" "i")
4090 (match_operand:SI 2 "const_int_operand" "i"))
4091 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4092 (match_operand:SI 4 "const_int_operand" "i")))]
4093 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4094 "*
4095 {
4096 int shift = INTVAL (operands[4]) & 31;
4097 int start = INTVAL (operands[2]) & 31;
4098 int size = INTVAL (operands[1]) & 31;
4099
4100 operands[4] = GEN_INT (32 - shift - start - size);
4101 operands[1] = GEN_INT (start + size - 1);
4102 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4103 }"
4104 [(set_attr "type" "insert_word")])
4105
4106 (define_insn "*insvsi_internal3"
4107 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4108 (match_operand:SI 1 "const_int_operand" "i")
4109 (match_operand:SI 2 "const_int_operand" "i"))
4110 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4111 (match_operand:SI 4 "const_int_operand" "i")))]
4112 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4113 "*
4114 {
4115 int shift = INTVAL (operands[4]) & 31;
4116 int start = INTVAL (operands[2]) & 31;
4117 int size = INTVAL (operands[1]) & 31;
4118
4119 operands[4] = GEN_INT (32 - shift - start - size);
4120 operands[1] = GEN_INT (start + size - 1);
4121 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4122 }"
4123 [(set_attr "type" "insert_word")])
4124
4125 (define_insn "*insvsi_internal4"
4126 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4127 (match_operand:SI 1 "const_int_operand" "i")
4128 (match_operand:SI 2 "const_int_operand" "i"))
4129 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4130 (match_operand:SI 4 "const_int_operand" "i")
4131 (match_operand:SI 5 "const_int_operand" "i")))]
4132 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4133 "*
4134 {
4135 int extract_start = INTVAL (operands[5]) & 31;
4136 int extract_size = INTVAL (operands[4]) & 31;
4137 int insert_start = INTVAL (operands[2]) & 31;
4138 int insert_size = INTVAL (operands[1]) & 31;
4139
4140 /* Align extract field with insert field */
4141 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4142 operands[1] = GEN_INT (insert_start + insert_size - 1);
4143 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4144 }"
4145 [(set_attr "type" "insert_word")])
4146
4147 ;; combine patterns for rlwimi
4148 (define_insn "*insvsi_internal5"
4149 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4150 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4151 (match_operand:SI 1 "mask_operand" "i"))
4152 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4153 (match_operand:SI 2 "const_int_operand" "i"))
4154 (match_operand:SI 5 "mask_operand" "i"))))]
4155 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4156 "*
4157 {
4158 int me = extract_ME(operands[5]);
4159 int mb = extract_MB(operands[5]);
4160 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4161 operands[2] = GEN_INT(mb);
4162 operands[1] = GEN_INT(me);
4163 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4164 }"
4165 [(set_attr "type" "insert_word")])
4166
4167 (define_insn "*insvsi_internal6"
4168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4169 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4170 (match_operand:SI 2 "const_int_operand" "i"))
4171 (match_operand:SI 5 "mask_operand" "i"))
4172 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4173 (match_operand:SI 1 "mask_operand" "i"))))]
4174 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4175 "*
4176 {
4177 int me = extract_ME(operands[5]);
4178 int mb = extract_MB(operands[5]);
4179 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4180 operands[2] = GEN_INT(mb);
4181 operands[1] = GEN_INT(me);
4182 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4183 }"
4184 [(set_attr "type" "insert_word")])
4185
4186 (define_insn "insvdi"
4187 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4188 (match_operand:SI 1 "const_int_operand" "i")
4189 (match_operand:SI 2 "const_int_operand" "i"))
4190 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4191 "TARGET_POWERPC64"
4192 "*
4193 {
4194 int start = INTVAL (operands[2]) & 63;
4195 int size = INTVAL (operands[1]) & 63;
4196
4197 operands[1] = GEN_INT (64 - start - size);
4198 return \"rldimi %0,%3,%H1,%H2\";
4199 }"
4200 [(set_attr "type" "insert_dword")])
4201
4202 (define_insn "*insvdi_internal2"
4203 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4204 (match_operand:SI 1 "const_int_operand" "i")
4205 (match_operand:SI 2 "const_int_operand" "i"))
4206 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4207 (match_operand:SI 4 "const_int_operand" "i")))]
4208 "TARGET_POWERPC64
4209 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4210 "*
4211 {
4212 int shift = INTVAL (operands[4]) & 63;
4213 int start = (INTVAL (operands[2]) & 63) - 32;
4214 int size = INTVAL (operands[1]) & 63;
4215
4216 operands[4] = GEN_INT (64 - shift - start - size);
4217 operands[2] = GEN_INT (start);
4218 operands[1] = GEN_INT (start + size - 1);
4219 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4220 }")
4221
4222 (define_insn "*insvdi_internal3"
4223 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4224 (match_operand:SI 1 "const_int_operand" "i")
4225 (match_operand:SI 2 "const_int_operand" "i"))
4226 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4227 (match_operand:SI 4 "const_int_operand" "i")))]
4228 "TARGET_POWERPC64
4229 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4230 "*
4231 {
4232 int shift = INTVAL (operands[4]) & 63;
4233 int start = (INTVAL (operands[2]) & 63) - 32;
4234 int size = INTVAL (operands[1]) & 63;
4235
4236 operands[4] = GEN_INT (64 - shift - start - size);
4237 operands[2] = GEN_INT (start);
4238 operands[1] = GEN_INT (start + size - 1);
4239 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4240 }")
4241
4242 (define_expand "extzv"
4243 [(set (match_operand 0 "gpc_reg_operand" "")
4244 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4245 (match_operand:SI 2 "const_int_operand" "")
4246 (match_operand:SI 3 "const_int_operand" "")))]
4247 ""
4248 "
4249 {
4250 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4251 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4252 compiler if the address of the structure is taken later. */
4253 if (GET_CODE (operands[0]) == SUBREG
4254 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4255 FAIL;
4256
4257 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4258 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4259 else
4260 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4261 DONE;
4262 }")
4263
4264 (define_insn "extzvsi"
4265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4266 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4267 (match_operand:SI 2 "const_int_operand" "i")
4268 (match_operand:SI 3 "const_int_operand" "i")))]
4269 ""
4270 "*
4271 {
4272 int start = INTVAL (operands[3]) & 31;
4273 int size = INTVAL (operands[2]) & 31;
4274
4275 if (start + size >= 32)
4276 operands[3] = const0_rtx;
4277 else
4278 operands[3] = GEN_INT (start + size);
4279 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4280 }")
4281
4282 (define_insn "*extzvsi_internal1"
4283 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4284 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4285 (match_operand:SI 2 "const_int_operand" "i,i")
4286 (match_operand:SI 3 "const_int_operand" "i,i"))
4287 (const_int 0)))
4288 (clobber (match_scratch:SI 4 "=r,r"))]
4289 ""
4290 "*
4291 {
4292 int start = INTVAL (operands[3]) & 31;
4293 int size = INTVAL (operands[2]) & 31;
4294
4295 /* Force split for non-cc0 compare. */
4296 if (which_alternative == 1)
4297 return \"#\";
4298
4299 /* If the bit-field being tested fits in the upper or lower half of a
4300 word, it is possible to use andiu. or andil. to test it. This is
4301 useful because the condition register set-use delay is smaller for
4302 andi[ul]. than for rlinm. This doesn't work when the starting bit
4303 position is 0 because the LT and GT bits may be set wrong. */
4304
4305 if ((start > 0 && start + size <= 16) || start >= 16)
4306 {
4307 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4308 - (1 << (16 - (start & 15) - size))));
4309 if (start < 16)
4310 return \"{andiu.|andis.} %4,%1,%3\";
4311 else
4312 return \"{andil.|andi.} %4,%1,%3\";
4313 }
4314
4315 if (start + size >= 32)
4316 operands[3] = const0_rtx;
4317 else
4318 operands[3] = GEN_INT (start + size);
4319 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4320 }"
4321 [(set_attr "type" "delayed_compare")
4322 (set_attr "length" "4,8")])
4323
4324 (define_split
4325 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4326 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4327 (match_operand:SI 2 "const_int_operand" "")
4328 (match_operand:SI 3 "const_int_operand" ""))
4329 (const_int 0)))
4330 (clobber (match_scratch:SI 4 ""))]
4331 "reload_completed"
4332 [(set (match_dup 4)
4333 (zero_extract:SI (match_dup 1) (match_dup 2)
4334 (match_dup 3)))
4335 (set (match_dup 0)
4336 (compare:CC (match_dup 4)
4337 (const_int 0)))]
4338 "")
4339
4340 (define_insn "*extzvsi_internal2"
4341 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4342 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4343 (match_operand:SI 2 "const_int_operand" "i,i")
4344 (match_operand:SI 3 "const_int_operand" "i,i"))
4345 (const_int 0)))
4346 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4347 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4348 ""
4349 "*
4350 {
4351 int start = INTVAL (operands[3]) & 31;
4352 int size = INTVAL (operands[2]) & 31;
4353
4354 /* Force split for non-cc0 compare. */
4355 if (which_alternative == 1)
4356 return \"#\";
4357
4358 /* Since we are using the output value, we can't ignore any need for
4359 a shift. The bit-field must end at the LSB. */
4360 if (start >= 16 && start + size == 32)
4361 {
4362 operands[3] = GEN_INT ((1 << size) - 1);
4363 return \"{andil.|andi.} %0,%1,%3\";
4364 }
4365
4366 if (start + size >= 32)
4367 operands[3] = const0_rtx;
4368 else
4369 operands[3] = GEN_INT (start + size);
4370 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4371 }"
4372 [(set_attr "type" "delayed_compare")
4373 (set_attr "length" "4,8")])
4374
4375 (define_split
4376 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4377 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4378 (match_operand:SI 2 "const_int_operand" "")
4379 (match_operand:SI 3 "const_int_operand" ""))
4380 (const_int 0)))
4381 (set (match_operand:SI 0 "gpc_reg_operand" "")
4382 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4383 "reload_completed"
4384 [(set (match_dup 0)
4385 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4386 (set (match_dup 4)
4387 (compare:CC (match_dup 0)
4388 (const_int 0)))]
4389 "")
4390
4391 (define_insn "extzvdi"
4392 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4393 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4394 (match_operand:SI 2 "const_int_operand" "i")
4395 (match_operand:SI 3 "const_int_operand" "i")))]
4396 "TARGET_POWERPC64"
4397 "*
4398 {
4399 int start = INTVAL (operands[3]) & 63;
4400 int size = INTVAL (operands[2]) & 63;
4401
4402 if (start + size >= 64)
4403 operands[3] = const0_rtx;
4404 else
4405 operands[3] = GEN_INT (start + size);
4406 operands[2] = GEN_INT (64 - size);
4407 return \"rldicl %0,%1,%3,%2\";
4408 }")
4409
4410 (define_insn "*extzvdi_internal1"
4411 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4412 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4413 (match_operand:SI 2 "const_int_operand" "i")
4414 (match_operand:SI 3 "const_int_operand" "i"))
4415 (const_int 0)))
4416 (clobber (match_scratch:DI 4 "=r"))]
4417 "TARGET_64BIT && rs6000_gen_cell_microcode"
4418 "*
4419 {
4420 int start = INTVAL (operands[3]) & 63;
4421 int size = INTVAL (operands[2]) & 63;
4422
4423 if (start + size >= 64)
4424 operands[3] = const0_rtx;
4425 else
4426 operands[3] = GEN_INT (start + size);
4427 operands[2] = GEN_INT (64 - size);
4428 return \"rldicl. %4,%1,%3,%2\";
4429 }"
4430 [(set_attr "type" "compare")])
4431
4432 (define_insn "*extzvdi_internal2"
4433 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4434 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4435 (match_operand:SI 2 "const_int_operand" "i")
4436 (match_operand:SI 3 "const_int_operand" "i"))
4437 (const_int 0)))
4438 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4439 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4440 "TARGET_64BIT && rs6000_gen_cell_microcode"
4441 "*
4442 {
4443 int start = INTVAL (operands[3]) & 63;
4444 int size = INTVAL (operands[2]) & 63;
4445
4446 if (start + size >= 64)
4447 operands[3] = const0_rtx;
4448 else
4449 operands[3] = GEN_INT (start + size);
4450 operands[2] = GEN_INT (64 - size);
4451 return \"rldicl. %0,%1,%3,%2\";
4452 }"
4453 [(set_attr "type" "compare")])
4454
4455 (define_insn "rotlsi3"
4456 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4457 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4458 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4459 ""
4460 "@
4461 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4462 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4463 [(set_attr "type" "var_shift_rotate,integer")])
4464
4465 (define_insn "*rotlsi3_64"
4466 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4467 (zero_extend:DI
4468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4469 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4470 "TARGET_64BIT"
4471 "@
4472 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4473 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4474 [(set_attr "type" "var_shift_rotate,integer")])
4475
4476 (define_insn "*rotlsi3_internal2"
4477 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4478 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4479 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4480 (const_int 0)))
4481 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4482 ""
4483 "@
4484 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4485 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4486 #
4487 #"
4488 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4489 (set_attr "length" "4,4,8,8")])
4490
4491 (define_split
4492 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4493 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4494 (match_operand:SI 2 "reg_or_cint_operand" ""))
4495 (const_int 0)))
4496 (clobber (match_scratch:SI 3 ""))]
4497 "reload_completed"
4498 [(set (match_dup 3)
4499 (rotate:SI (match_dup 1) (match_dup 2)))
4500 (set (match_dup 0)
4501 (compare:CC (match_dup 3)
4502 (const_int 0)))]
4503 "")
4504
4505 (define_insn "*rotlsi3_internal3"
4506 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4507 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4508 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4509 (const_int 0)))
4510 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4511 (rotate:SI (match_dup 1) (match_dup 2)))]
4512 ""
4513 "@
4514 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4515 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4516 #
4517 #"
4518 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4519 (set_attr "length" "4,4,8,8")])
4520
4521 (define_split
4522 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4523 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4524 (match_operand:SI 2 "reg_or_cint_operand" ""))
4525 (const_int 0)))
4526 (set (match_operand:SI 0 "gpc_reg_operand" "")
4527 (rotate:SI (match_dup 1) (match_dup 2)))]
4528 "reload_completed"
4529 [(set (match_dup 0)
4530 (rotate:SI (match_dup 1) (match_dup 2)))
4531 (set (match_dup 3)
4532 (compare:CC (match_dup 0)
4533 (const_int 0)))]
4534 "")
4535
4536 (define_insn "*rotlsi3_internal4"
4537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4538 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4539 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4540 (match_operand:SI 3 "mask_operand" "n,n")))]
4541 ""
4542 "@
4543 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4544 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4545 [(set_attr "type" "var_shift_rotate,integer")])
4546
4547 (define_insn "*rotlsi3_internal5"
4548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4549 (compare:CC (and:SI
4550 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4551 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4552 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4553 (const_int 0)))
4554 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4555 ""
4556 "@
4557 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4558 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4559 #
4560 #"
4561 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4562 (set_attr "length" "4,4,8,8")])
4563
4564 (define_split
4565 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4566 (compare:CC (and:SI
4567 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4568 (match_operand:SI 2 "reg_or_cint_operand" ""))
4569 (match_operand:SI 3 "mask_operand" ""))
4570 (const_int 0)))
4571 (clobber (match_scratch:SI 4 ""))]
4572 "reload_completed"
4573 [(set (match_dup 4)
4574 (and:SI (rotate:SI (match_dup 1)
4575 (match_dup 2))
4576 (match_dup 3)))
4577 (set (match_dup 0)
4578 (compare:CC (match_dup 4)
4579 (const_int 0)))]
4580 "")
4581
4582 (define_insn "*rotlsi3_internal6"
4583 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4584 (compare:CC (and:SI
4585 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4586 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4587 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4588 (const_int 0)))
4589 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4590 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4591 ""
4592 "@
4593 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4594 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4595 #
4596 #"
4597 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4598 (set_attr "length" "4,4,8,8")])
4599
4600 (define_split
4601 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4602 (compare:CC (and:SI
4603 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4604 (match_operand:SI 2 "reg_or_cint_operand" ""))
4605 (match_operand:SI 3 "mask_operand" ""))
4606 (const_int 0)))
4607 (set (match_operand:SI 0 "gpc_reg_operand" "")
4608 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4609 "reload_completed"
4610 [(set (match_dup 0)
4611 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4612 (set (match_dup 4)
4613 (compare:CC (match_dup 0)
4614 (const_int 0)))]
4615 "")
4616
4617 (define_insn "*rotlsi3_internal7"
4618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4619 (zero_extend:SI
4620 (subreg:QI
4621 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4622 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4623 ""
4624 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4625 [(set (attr "cell_micro")
4626 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4627 (const_string "not")
4628 (const_string "always")))])
4629
4630 (define_insn "*rotlsi3_internal8"
4631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4632 (compare:CC (zero_extend:SI
4633 (subreg:QI
4634 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4635 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4636 (const_int 0)))
4637 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4638 ""
4639 "@
4640 {rlnm.|rlwnm.} %3,%1,%2,0xff
4641 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4642 #
4643 #"
4644 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4645 (set_attr "length" "4,4,8,8")])
4646
4647 (define_split
4648 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4649 (compare:CC (zero_extend:SI
4650 (subreg:QI
4651 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4652 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4653 (const_int 0)))
4654 (clobber (match_scratch:SI 3 ""))]
4655 "reload_completed"
4656 [(set (match_dup 3)
4657 (zero_extend:SI (subreg:QI
4658 (rotate:SI (match_dup 1)
4659 (match_dup 2)) 0)))
4660 (set (match_dup 0)
4661 (compare:CC (match_dup 3)
4662 (const_int 0)))]
4663 "")
4664
4665 (define_insn "*rotlsi3_internal9"
4666 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4667 (compare:CC (zero_extend:SI
4668 (subreg:QI
4669 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4670 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4671 (const_int 0)))
4672 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4673 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4674 ""
4675 "@
4676 {rlnm.|rlwnm.} %0,%1,%2,0xff
4677 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4678 #
4679 #"
4680 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4681 (set_attr "length" "4,4,8,8")])
4682
4683 (define_split
4684 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4685 (compare:CC (zero_extend:SI
4686 (subreg:QI
4687 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4688 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4689 (const_int 0)))
4690 (set (match_operand:SI 0 "gpc_reg_operand" "")
4691 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4692 "reload_completed"
4693 [(set (match_dup 0)
4694 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4695 (set (match_dup 3)
4696 (compare:CC (match_dup 0)
4697 (const_int 0)))]
4698 "")
4699
4700 (define_insn "*rotlsi3_internal10"
4701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4702 (zero_extend:SI
4703 (subreg:HI
4704 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4705 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4706 ""
4707 "@
4708 {rlnm|rlwnm} %0,%1,%2,0xffff
4709 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4710 [(set_attr "type" "var_shift_rotate,integer")])
4711
4712
4713 (define_insn "*rotlsi3_internal11"
4714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4715 (compare:CC (zero_extend:SI
4716 (subreg:HI
4717 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4718 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4719 (const_int 0)))
4720 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4721 ""
4722 "@
4723 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4724 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4725 #
4726 #"
4727 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4728 (set_attr "length" "4,4,8,8")])
4729
4730 (define_split
4731 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4732 (compare:CC (zero_extend:SI
4733 (subreg:HI
4734 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4735 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4736 (const_int 0)))
4737 (clobber (match_scratch:SI 3 ""))]
4738 "reload_completed"
4739 [(set (match_dup 3)
4740 (zero_extend:SI (subreg:HI
4741 (rotate:SI (match_dup 1)
4742 (match_dup 2)) 0)))
4743 (set (match_dup 0)
4744 (compare:CC (match_dup 3)
4745 (const_int 0)))]
4746 "")
4747
4748 (define_insn "*rotlsi3_internal12"
4749 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4750 (compare:CC (zero_extend:SI
4751 (subreg:HI
4752 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4753 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4754 (const_int 0)))
4755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4756 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4757 ""
4758 "@
4759 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4760 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4761 #
4762 #"
4763 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4764 (set_attr "length" "4,4,8,8")])
4765
4766 (define_split
4767 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4768 (compare:CC (zero_extend:SI
4769 (subreg:HI
4770 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4771 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4772 (const_int 0)))
4773 (set (match_operand:SI 0 "gpc_reg_operand" "")
4774 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4775 "reload_completed"
4776 [(set (match_dup 0)
4777 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4778 (set (match_dup 3)
4779 (compare:CC (match_dup 0)
4780 (const_int 0)))]
4781 "")
4782
4783 ;; Note that we use "sle." instead of "sl." so that we can set
4784 ;; SHIFT_COUNT_TRUNCATED.
4785
4786 (define_expand "ashlsi3"
4787 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4788 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4789 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4790 ""
4791 "
4792 {
4793 if (TARGET_POWER)
4794 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4795 else
4796 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4797 DONE;
4798 }")
4799
4800 (define_insn "ashlsi3_power"
4801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4802 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4803 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4804 (clobber (match_scratch:SI 3 "=q,X"))]
4805 "TARGET_POWER"
4806 "@
4807 sle %0,%1,%2
4808 {sli|slwi} %0,%1,%h2")
4809
4810 (define_insn "ashlsi3_no_power"
4811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4812 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4813 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4814 "! TARGET_POWER"
4815 "@
4816 {sl|slw} %0,%1,%2
4817 {sli|slwi} %0,%1,%h2"
4818 [(set_attr "type" "var_shift_rotate,shift")])
4819
4820 (define_insn "*ashlsi3_64"
4821 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4822 (zero_extend:DI
4823 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4824 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4825 "TARGET_POWERPC64"
4826 "@
4827 {sl|slw} %0,%1,%2
4828 {sli|slwi} %0,%1,%h2"
4829 [(set_attr "type" "var_shift_rotate,shift")])
4830
4831 (define_insn ""
4832 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4833 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4834 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4835 (const_int 0)))
4836 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4837 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4838 "TARGET_POWER"
4839 "@
4840 sle. %3,%1,%2
4841 {sli.|slwi.} %3,%1,%h2
4842 #
4843 #"
4844 [(set_attr "type" "delayed_compare")
4845 (set_attr "length" "4,4,8,8")])
4846
4847 (define_split
4848 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4849 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4850 (match_operand:SI 2 "reg_or_cint_operand" ""))
4851 (const_int 0)))
4852 (clobber (match_scratch:SI 3 ""))
4853 (clobber (match_scratch:SI 4 ""))]
4854 "TARGET_POWER && reload_completed"
4855 [(parallel [(set (match_dup 3)
4856 (ashift:SI (match_dup 1) (match_dup 2)))
4857 (clobber (match_dup 4))])
4858 (set (match_dup 0)
4859 (compare:CC (match_dup 3)
4860 (const_int 0)))]
4861 "")
4862
4863 (define_insn ""
4864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4865 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4866 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4867 (const_int 0)))
4868 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4869 "! TARGET_POWER && TARGET_32BIT"
4870 "@
4871 {sl.|slw.} %3,%1,%2
4872 {sli.|slwi.} %3,%1,%h2
4873 #
4874 #"
4875 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4876 (set_attr "length" "4,4,8,8")])
4877
4878 (define_split
4879 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4880 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4881 (match_operand:SI 2 "reg_or_cint_operand" ""))
4882 (const_int 0)))
4883 (clobber (match_scratch:SI 3 ""))]
4884 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4885 [(set (match_dup 3)
4886 (ashift:SI (match_dup 1) (match_dup 2)))
4887 (set (match_dup 0)
4888 (compare:CC (match_dup 3)
4889 (const_int 0)))]
4890 "")
4891
4892 (define_insn ""
4893 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4894 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4895 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4896 (const_int 0)))
4897 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4898 (ashift:SI (match_dup 1) (match_dup 2)))
4899 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4900 "TARGET_POWER"
4901 "@
4902 sle. %0,%1,%2
4903 {sli.|slwi.} %0,%1,%h2
4904 #
4905 #"
4906 [(set_attr "type" "delayed_compare")
4907 (set_attr "length" "4,4,8,8")])
4908
4909 (define_split
4910 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4911 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4912 (match_operand:SI 2 "reg_or_cint_operand" ""))
4913 (const_int 0)))
4914 (set (match_operand:SI 0 "gpc_reg_operand" "")
4915 (ashift:SI (match_dup 1) (match_dup 2)))
4916 (clobber (match_scratch:SI 4 ""))]
4917 "TARGET_POWER && reload_completed"
4918 [(parallel [(set (match_dup 0)
4919 (ashift:SI (match_dup 1) (match_dup 2)))
4920 (clobber (match_dup 4))])
4921 (set (match_dup 3)
4922 (compare:CC (match_dup 0)
4923 (const_int 0)))]
4924 "")
4925
4926 (define_insn ""
4927 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4928 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4929 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4930 (const_int 0)))
4931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4932 (ashift:SI (match_dup 1) (match_dup 2)))]
4933 "! TARGET_POWER && TARGET_32BIT"
4934 "@
4935 {sl.|slw.} %0,%1,%2
4936 {sli.|slwi.} %0,%1,%h2
4937 #
4938 #"
4939 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4940 (set_attr "length" "4,4,8,8")])
4941
4942 (define_split
4943 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4944 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4945 (match_operand:SI 2 "reg_or_cint_operand" ""))
4946 (const_int 0)))
4947 (set (match_operand:SI 0 "gpc_reg_operand" "")
4948 (ashift:SI (match_dup 1) (match_dup 2)))]
4949 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4950 [(set (match_dup 0)
4951 (ashift:SI (match_dup 1) (match_dup 2)))
4952 (set (match_dup 3)
4953 (compare:CC (match_dup 0)
4954 (const_int 0)))]
4955 "")
4956
4957 (define_insn "rlwinm"
4958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4959 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4960 (match_operand:SI 2 "const_int_operand" "i"))
4961 (match_operand:SI 3 "mask_operand" "n")))]
4962 "includes_lshift_p (operands[2], operands[3])"
4963 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4964
4965 (define_insn ""
4966 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4967 (compare:CC
4968 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4969 (match_operand:SI 2 "const_int_operand" "i,i"))
4970 (match_operand:SI 3 "mask_operand" "n,n"))
4971 (const_int 0)))
4972 (clobber (match_scratch:SI 4 "=r,r"))]
4973 "includes_lshift_p (operands[2], operands[3])"
4974 "@
4975 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4976 #"
4977 [(set_attr "type" "delayed_compare")
4978 (set_attr "length" "4,8")])
4979
4980 (define_split
4981 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4982 (compare:CC
4983 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4984 (match_operand:SI 2 "const_int_operand" ""))
4985 (match_operand:SI 3 "mask_operand" ""))
4986 (const_int 0)))
4987 (clobber (match_scratch:SI 4 ""))]
4988 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4989 [(set (match_dup 4)
4990 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4991 (match_dup 3)))
4992 (set (match_dup 0)
4993 (compare:CC (match_dup 4)
4994 (const_int 0)))]
4995 "")
4996
4997 (define_insn ""
4998 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4999 (compare:CC
5000 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5001 (match_operand:SI 2 "const_int_operand" "i,i"))
5002 (match_operand:SI 3 "mask_operand" "n,n"))
5003 (const_int 0)))
5004 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5005 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5006 "includes_lshift_p (operands[2], operands[3])"
5007 "@
5008 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
5009 #"
5010 [(set_attr "type" "delayed_compare")
5011 (set_attr "length" "4,8")])
5012
5013 (define_split
5014 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5015 (compare:CC
5016 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
5017 (match_operand:SI 2 "const_int_operand" ""))
5018 (match_operand:SI 3 "mask_operand" ""))
5019 (const_int 0)))
5020 (set (match_operand:SI 0 "gpc_reg_operand" "")
5021 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5022 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
5023 [(set (match_dup 0)
5024 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5025 (set (match_dup 4)
5026 (compare:CC (match_dup 0)
5027 (const_int 0)))]
5028 "")
5029
5030 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5031 ;; "sli x,x,0".
5032 (define_expand "lshrsi3"
5033 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
5034 (use (match_operand:SI 1 "gpc_reg_operand" ""))
5035 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
5036 ""
5037 "
5038 {
5039 if (TARGET_POWER)
5040 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
5041 else
5042 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
5043 DONE;
5044 }")
5045
5046 (define_insn "lshrsi3_power"
5047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5048 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5049 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
5050 (clobber (match_scratch:SI 3 "=q,X,X"))]
5051 "TARGET_POWER"
5052 "@
5053 sre %0,%1,%2
5054 mr %0,%1
5055 {s%A2i|s%A2wi} %0,%1,%h2")
5056
5057 (define_insn "lshrsi3_no_power"
5058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5059 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5060 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5061 "! TARGET_POWER"
5062 "@
5063 mr %0,%1
5064 {sr|srw} %0,%1,%2
5065 {sri|srwi} %0,%1,%h2"
5066 [(set_attr "type" "integer,var_shift_rotate,shift")])
5067
5068 (define_insn "*lshrsi3_64"
5069 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5070 (zero_extend:DI
5071 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5072 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5073 "TARGET_POWERPC64"
5074 "@
5075 {sr|srw} %0,%1,%2
5076 {sri|srwi} %0,%1,%h2"
5077 [(set_attr "type" "var_shift_rotate,shift")])
5078
5079 (define_insn ""
5080 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5081 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5082 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5083 (const_int 0)))
5084 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5085 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5086 "TARGET_POWER"
5087 "@
5088 sre. %3,%1,%2
5089 mr. %1,%1
5090 {s%A2i.|s%A2wi.} %3,%1,%h2
5091 #
5092 #
5093 #"
5094 [(set_attr "type" "delayed_compare")
5095 (set_attr "length" "4,4,4,8,8,8")])
5096
5097 (define_split
5098 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5099 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5100 (match_operand:SI 2 "reg_or_cint_operand" ""))
5101 (const_int 0)))
5102 (clobber (match_scratch:SI 3 ""))
5103 (clobber (match_scratch:SI 4 ""))]
5104 "TARGET_POWER && reload_completed"
5105 [(parallel [(set (match_dup 3)
5106 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5107 (clobber (match_dup 4))])
5108 (set (match_dup 0)
5109 (compare:CC (match_dup 3)
5110 (const_int 0)))]
5111 "")
5112
5113 (define_insn ""
5114 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5115 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5116 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5117 (const_int 0)))
5118 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5119 "! TARGET_POWER && TARGET_32BIT"
5120 "@
5121 mr. %1,%1
5122 {sr.|srw.} %3,%1,%2
5123 {sri.|srwi.} %3,%1,%h2
5124 #
5125 #
5126 #"
5127 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5128 (set_attr "length" "4,4,4,8,8,8")])
5129
5130 (define_split
5131 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5132 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5133 (match_operand:SI 2 "reg_or_cint_operand" ""))
5134 (const_int 0)))
5135 (clobber (match_scratch:SI 3 ""))]
5136 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5137 [(set (match_dup 3)
5138 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5139 (set (match_dup 0)
5140 (compare:CC (match_dup 3)
5141 (const_int 0)))]
5142 "")
5143
5144 (define_insn ""
5145 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5146 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5147 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5148 (const_int 0)))
5149 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5150 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5151 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5152 "TARGET_POWER"
5153 "@
5154 sre. %0,%1,%2
5155 mr. %0,%1
5156 {s%A2i.|s%A2wi.} %0,%1,%h2
5157 #
5158 #
5159 #"
5160 [(set_attr "type" "delayed_compare")
5161 (set_attr "length" "4,4,4,8,8,8")])
5162
5163 (define_split
5164 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5165 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5166 (match_operand:SI 2 "reg_or_cint_operand" ""))
5167 (const_int 0)))
5168 (set (match_operand:SI 0 "gpc_reg_operand" "")
5169 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5170 (clobber (match_scratch:SI 4 ""))]
5171 "TARGET_POWER && reload_completed"
5172 [(parallel [(set (match_dup 0)
5173 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5174 (clobber (match_dup 4))])
5175 (set (match_dup 3)
5176 (compare:CC (match_dup 0)
5177 (const_int 0)))]
5178 "")
5179
5180 (define_insn ""
5181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5182 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5183 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5184 (const_int 0)))
5185 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5186 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5187 "! TARGET_POWER && TARGET_32BIT"
5188 "@
5189 mr. %0,%1
5190 {sr.|srw.} %0,%1,%2
5191 {sri.|srwi.} %0,%1,%h2
5192 #
5193 #
5194 #"
5195 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5196 (set_attr "length" "4,4,4,8,8,8")])
5197
5198 (define_split
5199 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5200 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5201 (match_operand:SI 2 "reg_or_cint_operand" ""))
5202 (const_int 0)))
5203 (set (match_operand:SI 0 "gpc_reg_operand" "")
5204 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5205 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5206 [(set (match_dup 0)
5207 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5208 (set (match_dup 3)
5209 (compare:CC (match_dup 0)
5210 (const_int 0)))]
5211 "")
5212
5213 (define_insn ""
5214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5215 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5216 (match_operand:SI 2 "const_int_operand" "i"))
5217 (match_operand:SI 3 "mask_operand" "n")))]
5218 "includes_rshift_p (operands[2], operands[3])"
5219 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5220
5221 (define_insn ""
5222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5223 (compare:CC
5224 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5225 (match_operand:SI 2 "const_int_operand" "i,i"))
5226 (match_operand:SI 3 "mask_operand" "n,n"))
5227 (const_int 0)))
5228 (clobber (match_scratch:SI 4 "=r,r"))]
5229 "includes_rshift_p (operands[2], operands[3])"
5230 "@
5231 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5232 #"
5233 [(set_attr "type" "delayed_compare")
5234 (set_attr "length" "4,8")])
5235
5236 (define_split
5237 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5238 (compare:CC
5239 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5240 (match_operand:SI 2 "const_int_operand" ""))
5241 (match_operand:SI 3 "mask_operand" ""))
5242 (const_int 0)))
5243 (clobber (match_scratch:SI 4 ""))]
5244 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5245 [(set (match_dup 4)
5246 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5247 (match_dup 3)))
5248 (set (match_dup 0)
5249 (compare:CC (match_dup 4)
5250 (const_int 0)))]
5251 "")
5252
5253 (define_insn ""
5254 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5255 (compare:CC
5256 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5257 (match_operand:SI 2 "const_int_operand" "i,i"))
5258 (match_operand:SI 3 "mask_operand" "n,n"))
5259 (const_int 0)))
5260 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5261 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5262 "includes_rshift_p (operands[2], operands[3])"
5263 "@
5264 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5265 #"
5266 [(set_attr "type" "delayed_compare")
5267 (set_attr "length" "4,8")])
5268
5269 (define_split
5270 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5271 (compare:CC
5272 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5273 (match_operand:SI 2 "const_int_operand" ""))
5274 (match_operand:SI 3 "mask_operand" ""))
5275 (const_int 0)))
5276 (set (match_operand:SI 0 "gpc_reg_operand" "")
5277 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5278 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5279 [(set (match_dup 0)
5280 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5281 (set (match_dup 4)
5282 (compare:CC (match_dup 0)
5283 (const_int 0)))]
5284 "")
5285
5286 (define_insn ""
5287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5288 (zero_extend:SI
5289 (subreg:QI
5290 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5291 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5292 "includes_rshift_p (operands[2], GEN_INT (255))"
5293 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5294
5295 (define_insn ""
5296 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5297 (compare:CC
5298 (zero_extend:SI
5299 (subreg:QI
5300 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5301 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5302 (const_int 0)))
5303 (clobber (match_scratch:SI 3 "=r,r"))]
5304 "includes_rshift_p (operands[2], GEN_INT (255))"
5305 "@
5306 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5307 #"
5308 [(set_attr "type" "delayed_compare")
5309 (set_attr "length" "4,8")])
5310
5311 (define_split
5312 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5313 (compare:CC
5314 (zero_extend:SI
5315 (subreg:QI
5316 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5317 (match_operand:SI 2 "const_int_operand" "")) 0))
5318 (const_int 0)))
5319 (clobber (match_scratch:SI 3 ""))]
5320 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5321 [(set (match_dup 3)
5322 (zero_extend:SI (subreg:QI
5323 (lshiftrt:SI (match_dup 1)
5324 (match_dup 2)) 0)))
5325 (set (match_dup 0)
5326 (compare:CC (match_dup 3)
5327 (const_int 0)))]
5328 "")
5329
5330 (define_insn ""
5331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5332 (compare:CC
5333 (zero_extend:SI
5334 (subreg:QI
5335 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5336 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5337 (const_int 0)))
5338 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5339 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5340 "includes_rshift_p (operands[2], GEN_INT (255))"
5341 "@
5342 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5343 #"
5344 [(set_attr "type" "delayed_compare")
5345 (set_attr "length" "4,8")])
5346
5347 (define_split
5348 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5349 (compare:CC
5350 (zero_extend:SI
5351 (subreg:QI
5352 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5353 (match_operand:SI 2 "const_int_operand" "")) 0))
5354 (const_int 0)))
5355 (set (match_operand:SI 0 "gpc_reg_operand" "")
5356 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5357 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5358 [(set (match_dup 0)
5359 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5360 (set (match_dup 3)
5361 (compare:CC (match_dup 0)
5362 (const_int 0)))]
5363 "")
5364
5365 (define_insn ""
5366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5367 (zero_extend:SI
5368 (subreg:HI
5369 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5370 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5371 "includes_rshift_p (operands[2], GEN_INT (65535))"
5372 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5373
5374 (define_insn ""
5375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5376 (compare:CC
5377 (zero_extend:SI
5378 (subreg:HI
5379 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5380 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5381 (const_int 0)))
5382 (clobber (match_scratch:SI 3 "=r,r"))]
5383 "includes_rshift_p (operands[2], GEN_INT (65535))"
5384 "@
5385 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5386 #"
5387 [(set_attr "type" "delayed_compare")
5388 (set_attr "length" "4,8")])
5389
5390 (define_split
5391 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5392 (compare:CC
5393 (zero_extend:SI
5394 (subreg:HI
5395 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5396 (match_operand:SI 2 "const_int_operand" "")) 0))
5397 (const_int 0)))
5398 (clobber (match_scratch:SI 3 ""))]
5399 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5400 [(set (match_dup 3)
5401 (zero_extend:SI (subreg:HI
5402 (lshiftrt:SI (match_dup 1)
5403 (match_dup 2)) 0)))
5404 (set (match_dup 0)
5405 (compare:CC (match_dup 3)
5406 (const_int 0)))]
5407 "")
5408
5409 (define_insn ""
5410 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5411 (compare:CC
5412 (zero_extend:SI
5413 (subreg:HI
5414 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5415 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5416 (const_int 0)))
5417 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5418 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5419 "includes_rshift_p (operands[2], GEN_INT (65535))"
5420 "@
5421 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5422 #"
5423 [(set_attr "type" "delayed_compare")
5424 (set_attr "length" "4,8")])
5425
5426 (define_split
5427 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5428 (compare:CC
5429 (zero_extend:SI
5430 (subreg:HI
5431 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5432 (match_operand:SI 2 "const_int_operand" "")) 0))
5433 (const_int 0)))
5434 (set (match_operand:SI 0 "gpc_reg_operand" "")
5435 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5436 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5437 [(set (match_dup 0)
5438 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5439 (set (match_dup 3)
5440 (compare:CC (match_dup 0)
5441 (const_int 0)))]
5442 "")
5443
5444 (define_insn ""
5445 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5446 (const_int 1)
5447 (match_operand:SI 1 "gpc_reg_operand" "r"))
5448 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5449 (const_int 31)))]
5450 "TARGET_POWER"
5451 "rrib %0,%1,%2")
5452
5453 (define_insn ""
5454 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5455 (const_int 1)
5456 (match_operand:SI 1 "gpc_reg_operand" "r"))
5457 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5458 (const_int 31)))]
5459 "TARGET_POWER"
5460 "rrib %0,%1,%2")
5461
5462 (define_insn ""
5463 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5464 (const_int 1)
5465 (match_operand:SI 1 "gpc_reg_operand" "r"))
5466 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5467 (const_int 1)
5468 (const_int 0)))]
5469 "TARGET_POWER"
5470 "rrib %0,%1,%2")
5471
5472 (define_expand "ashrsi3"
5473 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5474 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5475 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5476 ""
5477 "
5478 {
5479 if (TARGET_POWER)
5480 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5481 else
5482 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5483 DONE;
5484 }")
5485
5486 (define_insn "ashrsi3_power"
5487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5488 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5489 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5490 (clobber (match_scratch:SI 3 "=q,X"))]
5491 "TARGET_POWER"
5492 "@
5493 srea %0,%1,%2
5494 {srai|srawi} %0,%1,%h2"
5495 [(set_attr "type" "shift")])
5496
5497 (define_insn "ashrsi3_no_power"
5498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5499 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5500 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5501 "! TARGET_POWER"
5502 "@
5503 {sra|sraw} %0,%1,%2
5504 {srai|srawi} %0,%1,%h2"
5505 [(set_attr "type" "var_shift_rotate,shift")])
5506
5507 (define_insn "*ashrsi3_64"
5508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5509 (sign_extend:DI
5510 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5511 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5512 "TARGET_POWERPC64"
5513 "@
5514 {sra|sraw} %0,%1,%2
5515 {srai|srawi} %0,%1,%h2"
5516 [(set_attr "type" "var_shift_rotate,shift")])
5517
5518 (define_insn ""
5519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5520 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5521 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5522 (const_int 0)))
5523 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5524 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5525 "TARGET_POWER"
5526 "@
5527 srea. %3,%1,%2
5528 {srai.|srawi.} %3,%1,%h2
5529 #
5530 #"
5531 [(set_attr "type" "delayed_compare")
5532 (set_attr "length" "4,4,8,8")])
5533
5534 (define_split
5535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5536 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5537 (match_operand:SI 2 "reg_or_cint_operand" ""))
5538 (const_int 0)))
5539 (clobber (match_scratch:SI 3 ""))
5540 (clobber (match_scratch:SI 4 ""))]
5541 "TARGET_POWER && reload_completed"
5542 [(parallel [(set (match_dup 3)
5543 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5544 (clobber (match_dup 4))])
5545 (set (match_dup 0)
5546 (compare:CC (match_dup 3)
5547 (const_int 0)))]
5548 "")
5549
5550 (define_insn ""
5551 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5552 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5553 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5554 (const_int 0)))
5555 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5556 "! TARGET_POWER"
5557 "@
5558 {sra.|sraw.} %3,%1,%2
5559 {srai.|srawi.} %3,%1,%h2
5560 #
5561 #"
5562 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5563 (set_attr "length" "4,4,8,8")])
5564
5565 (define_split
5566 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5567 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5568 (match_operand:SI 2 "reg_or_cint_operand" ""))
5569 (const_int 0)))
5570 (clobber (match_scratch:SI 3 ""))]
5571 "! TARGET_POWER && reload_completed"
5572 [(set (match_dup 3)
5573 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5574 (set (match_dup 0)
5575 (compare:CC (match_dup 3)
5576 (const_int 0)))]
5577 "")
5578
5579 (define_insn ""
5580 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5581 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5582 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5583 (const_int 0)))
5584 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5585 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5586 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5587 "TARGET_POWER"
5588 "@
5589 srea. %0,%1,%2
5590 {srai.|srawi.} %0,%1,%h2
5591 #
5592 #"
5593 [(set_attr "type" "delayed_compare")
5594 (set_attr "length" "4,4,8,8")])
5595
5596 (define_split
5597 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5598 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5599 (match_operand:SI 2 "reg_or_cint_operand" ""))
5600 (const_int 0)))
5601 (set (match_operand:SI 0 "gpc_reg_operand" "")
5602 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5603 (clobber (match_scratch:SI 4 ""))]
5604 "TARGET_POWER && reload_completed"
5605 [(parallel [(set (match_dup 0)
5606 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5607 (clobber (match_dup 4))])
5608 (set (match_dup 3)
5609 (compare:CC (match_dup 0)
5610 (const_int 0)))]
5611 "")
5612
5613 (define_insn ""
5614 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5615 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5616 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5617 (const_int 0)))
5618 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5619 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5620 "! TARGET_POWER"
5621 "@
5622 {sra.|sraw.} %0,%1,%2
5623 {srai.|srawi.} %0,%1,%h2
5624 #
5625 #"
5626 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5627 (set_attr "length" "4,4,8,8")])
5628 \f
5629 ;; Builtins to replace a division to generate FRE reciprocal estimate
5630 ;; instructions and the necessary fixup instructions
5631 (define_expand "recip<mode>3"
5632 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5633 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5634 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5635 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5636 {
5637 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5638 DONE;
5639 })
5640
5641 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5642 ;; hardware division. This is only done before register allocation and with
5643 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5644 (define_split
5645 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5646 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5647 (match_operand 2 "gpc_reg_operand" "")))]
5648 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5649 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5650 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5651 [(const_int 0)]
5652 {
5653 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5654 DONE;
5655 })
5656
5657 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5658 ;; appropriate fixup.
5659 (define_expand "rsqrt<mode>2"
5660 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5661 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5662 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5663 {
5664 rs6000_emit_swrsqrt (operands[0], operands[1]);
5665 DONE;
5666 })
5667 \f
5668 (define_split
5669 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5670 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5671 (match_operand:SI 2 "reg_or_cint_operand" ""))
5672 (const_int 0)))
5673 (set (match_operand:SI 0 "gpc_reg_operand" "")
5674 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5675 "! TARGET_POWER && reload_completed"
5676 [(set (match_dup 0)
5677 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5678 (set (match_dup 3)
5679 (compare:CC (match_dup 0)
5680 (const_int 0)))]
5681 "")
5682
5683 ;; Floating-point insns, excluding normal data motion.
5684 ;;
5685 ;; PowerPC has a full set of single-precision floating point instructions.
5686 ;;
5687 ;; For the POWER architecture, we pretend that we have both SFmode and
5688 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5689 ;; The only conversions we will do will be when storing to memory. In that
5690 ;; case, we will use the "frsp" instruction before storing.
5691 ;;
5692 ;; Note that when we store into a single-precision memory location, we need to
5693 ;; use the frsp insn first. If the register being stored isn't dead, we
5694 ;; need a scratch register for the frsp. But this is difficult when the store
5695 ;; is done by reload. It is not incorrect to do the frsp on the register in
5696 ;; this case, we just lose precision that we would have otherwise gotten but
5697 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5698
5699 (define_expand "extendsfdf2"
5700 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5701 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5702 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5703 "")
5704
5705 (define_insn_and_split "*extendsfdf2_fpr"
5706 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5707 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5708 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5709 "@
5710 #
5711 fmr %0,%1
5712 lfs%U1%X1 %0,%1"
5713 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5714 [(const_int 0)]
5715 {
5716 emit_note (NOTE_INSN_DELETED);
5717 DONE;
5718 }
5719 [(set_attr "type" "fp,fp,fpload")])
5720
5721 (define_expand "truncdfsf2"
5722 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5723 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5724 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5725 "")
5726
5727 (define_insn "*truncdfsf2_fpr"
5728 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5729 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5730 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5731 "frsp %0,%1"
5732 [(set_attr "type" "fp")])
5733
5734 (define_insn "aux_truncdfsf2"
5735 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5736 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5737 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5738 "frsp %0,%1"
5739 [(set_attr "type" "fp")])
5740
5741 (define_expand "negsf2"
5742 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5743 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5744 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5745 "")
5746
5747 (define_insn "*negsf2"
5748 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5749 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5750 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5751 "fneg %0,%1"
5752 [(set_attr "type" "fp")])
5753
5754 (define_expand "abssf2"
5755 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5756 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5757 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5758 "")
5759
5760 (define_insn "*abssf2"
5761 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5762 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5763 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5764 "fabs %0,%1"
5765 [(set_attr "type" "fp")])
5766
5767 (define_insn ""
5768 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5769 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5770 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5771 "fnabs %0,%1"
5772 [(set_attr "type" "fp")])
5773
5774 (define_expand "addsf3"
5775 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5776 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5777 (match_operand:SF 2 "gpc_reg_operand" "")))]
5778 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5779 "")
5780
5781 (define_insn ""
5782 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5783 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5784 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5785 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5786 "fadds %0,%1,%2"
5787 [(set_attr "type" "fp")
5788 (set_attr "fp_type" "fp_addsub_s")])
5789
5790 (define_insn ""
5791 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5792 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5793 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5794 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5795 "{fa|fadd} %0,%1,%2"
5796 [(set_attr "type" "fp")])
5797
5798 (define_expand "subsf3"
5799 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5800 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5801 (match_operand:SF 2 "gpc_reg_operand" "")))]
5802 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5803 "")
5804
5805 (define_insn ""
5806 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5807 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5808 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5809 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5810 "fsubs %0,%1,%2"
5811 [(set_attr "type" "fp")
5812 (set_attr "fp_type" "fp_addsub_s")])
5813
5814 (define_insn ""
5815 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5816 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5817 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5818 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5819 "{fs|fsub} %0,%1,%2"
5820 [(set_attr "type" "fp")])
5821
5822 (define_expand "mulsf3"
5823 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5824 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5825 (match_operand:SF 2 "gpc_reg_operand" "")))]
5826 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5827 "")
5828
5829 (define_insn ""
5830 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5831 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5832 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5833 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5834 "fmuls %0,%1,%2"
5835 [(set_attr "type" "fp")
5836 (set_attr "fp_type" "fp_mul_s")])
5837
5838 (define_insn ""
5839 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5840 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5841 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5842 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5843 "{fm|fmul} %0,%1,%2"
5844 [(set_attr "type" "dmul")])
5845
5846 (define_expand "divsf3"
5847 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5848 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5849 (match_operand:SF 2 "gpc_reg_operand" "")))]
5850 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5851 "")
5852
5853 (define_insn ""
5854 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5855 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5856 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5857 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5858 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5859 "fdivs %0,%1,%2"
5860 [(set_attr "type" "sdiv")])
5861
5862 (define_insn ""
5863 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5864 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5865 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5866 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5867 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5868 "{fd|fdiv} %0,%1,%2"
5869 [(set_attr "type" "ddiv")])
5870
5871 (define_insn "fres"
5872 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5873 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5874 "TARGET_FRES"
5875 "fres %0,%1"
5876 [(set_attr "type" "fp")])
5877
5878 ; builtin fmaf support
5879 (define_insn "*fmasf4_fpr"
5880 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5881 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5882 (match_operand:SF 2 "gpc_reg_operand" "f")
5883 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5884 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5885 {
5886 return (TARGET_POWERPC
5887 ? "fmadds %0,%1,%2,%3"
5888 : "{fma|fmadd} %0,%1,%2,%3");
5889 }
5890 [(set_attr "type" "fp")
5891 (set_attr "fp_type" "fp_maddsub_s")])
5892
5893 (define_insn "*fmssf4_fpr"
5894 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5895 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5896 (match_operand:SF 2 "gpc_reg_operand" "f")
5897 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5898 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5899 {
5900 return (TARGET_POWERPC
5901 ? "fmsubs %0,%1,%2,%3"
5902 : "{fms|fmsub} %0,%1,%2,%3");
5903 }
5904 [(set_attr "type" "fp")
5905 (set_attr "fp_type" "fp_maddsub_s")])
5906
5907 (define_insn "*nfmasf4_fpr"
5908 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5909 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5910 (match_operand:SF 2 "gpc_reg_operand" "f")
5911 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5912 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5913 {
5914 return (TARGET_POWERPC
5915 ? "fnmadds %0,%1,%2,%3"
5916 : "{fnma|fnmadd} %0,%1,%2,%3");
5917 }
5918 [(set_attr "type" "fp")
5919 (set_attr "fp_type" "fp_maddsub_s")])
5920
5921 (define_insn "*nfmssf4_fpr"
5922 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5923 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5924 (match_operand:SF 2 "gpc_reg_operand" "f")
5925 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5926 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5927 {
5928 return (TARGET_POWERPC
5929 ? "fnmsubs %0,%1,%2,%3"
5930 : "{fnms|fnmsub} %0,%1,%2,%3");
5931 }
5932 [(set_attr "type" "fp")
5933 (set_attr "fp_type" "fp_maddsub_s")])
5934
5935 (define_expand "sqrtsf2"
5936 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5937 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5938 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5939 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5940 && !TARGET_SIMPLE_FPU"
5941 "")
5942
5943 (define_insn ""
5944 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5945 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5946 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5947 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5948 "fsqrts %0,%1"
5949 [(set_attr "type" "ssqrt")])
5950
5951 (define_insn ""
5952 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5953 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5954 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5955 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5956 "fsqrt %0,%1"
5957 [(set_attr "type" "dsqrt")])
5958
5959 (define_insn "*rsqrtsf_internal1"
5960 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5961 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5962 UNSPEC_RSQRT))]
5963 "TARGET_FRSQRTES"
5964 "frsqrtes %0,%1"
5965 [(set_attr "type" "fp")])
5966
5967 (define_expand "copysign<mode>3"
5968 [(set (match_dup 3)
5969 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5970 (set (match_dup 4)
5971 (neg:SFDF (abs:SFDF (match_dup 1))))
5972 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5973 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5974 (match_dup 5))
5975 (match_dup 3)
5976 (match_dup 4)))]
5977 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5978 && ((TARGET_PPC_GFXOPT
5979 && !HONOR_NANS (<MODE>mode)
5980 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5981 || TARGET_CMPB
5982 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5983 {
5984 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5985 {
5986 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5987 operands[2]));
5988 DONE;
5989 }
5990
5991 operands[3] = gen_reg_rtx (<MODE>mode);
5992 operands[4] = gen_reg_rtx (<MODE>mode);
5993 operands[5] = CONST0_RTX (<MODE>mode);
5994 })
5995
5996 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5997 ;; compiler from optimizing -0.0
5998 (define_insn "copysign<mode>3_fcpsgn"
5999 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6000 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
6001 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
6002 UNSPEC_COPYSIGN))]
6003 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6004 "fcpsgn %0,%2,%1"
6005 [(set_attr "type" "fp")])
6006
6007 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
6008 ;; fsel instruction and some auxiliary computations. Then we just have a
6009 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6010 ;; combine.
6011 (define_expand "smaxsf3"
6012 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6013 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6014 (match_operand:SF 2 "gpc_reg_operand" ""))
6015 (match_dup 1)
6016 (match_dup 2)))]
6017 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6018 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6019 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6020
6021 (define_expand "sminsf3"
6022 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6023 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6024 (match_operand:SF 2 "gpc_reg_operand" ""))
6025 (match_dup 2)
6026 (match_dup 1)))]
6027 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6028 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6029 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6030
6031 (define_split
6032 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6033 (match_operator:SF 3 "min_max_operator"
6034 [(match_operand:SF 1 "gpc_reg_operand" "")
6035 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6036 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6037 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6038 [(const_int 0)]
6039 "
6040 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6041 operands[1], operands[2]);
6042 DONE;
6043 }")
6044
6045 (define_expand "mov<mode>cc"
6046 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6047 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6048 (match_operand:GPR 2 "gpc_reg_operand" "")
6049 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6050 "TARGET_ISEL<sel>"
6051 "
6052 {
6053 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6054 DONE;
6055 else
6056 FAIL;
6057 }")
6058
6059 ;; We use the BASE_REGS for the isel input operands because, if rA is
6060 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6061 ;; because we may switch the operands and rB may end up being rA.
6062 ;;
6063 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6064 ;; leave out the mode in operand 4 and use one pattern, but reload can
6065 ;; change the mode underneath our feet and then gets confused trying
6066 ;; to reload the value.
6067 (define_insn "isel_signed_<mode>"
6068 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6069 (if_then_else:GPR
6070 (match_operator 1 "scc_comparison_operator"
6071 [(match_operand:CC 4 "cc_reg_operand" "y,y")
6072 (const_int 0)])
6073 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6074 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6075 "TARGET_ISEL<sel>"
6076 "*
6077 { return output_isel (operands); }"
6078 [(set_attr "type" "isel")
6079 (set_attr "length" "4")])
6080
6081 (define_insn "isel_unsigned_<mode>"
6082 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6083 (if_then_else:GPR
6084 (match_operator 1 "scc_comparison_operator"
6085 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
6086 (const_int 0)])
6087 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6088 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6089 "TARGET_ISEL<sel>"
6090 "*
6091 { return output_isel (operands); }"
6092 [(set_attr "type" "isel")
6093 (set_attr "length" "4")])
6094
6095 ;; These patterns can be useful for combine; they let combine know that
6096 ;; isel can handle reversed comparisons so long as the operands are
6097 ;; registers.
6098
6099 (define_insn "*isel_reversed_signed_<mode>"
6100 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6101 (if_then_else:GPR
6102 (match_operator 1 "scc_rev_comparison_operator"
6103 [(match_operand:CC 4 "cc_reg_operand" "y")
6104 (const_int 0)])
6105 (match_operand:GPR 2 "gpc_reg_operand" "b")
6106 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6107 "TARGET_ISEL<sel>"
6108 "*
6109 { return output_isel (operands); }"
6110 [(set_attr "type" "isel")
6111 (set_attr "length" "4")])
6112
6113 (define_insn "*isel_reversed_unsigned_<mode>"
6114 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6115 (if_then_else:GPR
6116 (match_operator 1 "scc_rev_comparison_operator"
6117 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6118 (const_int 0)])
6119 (match_operand:GPR 2 "gpc_reg_operand" "b")
6120 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6121 "TARGET_ISEL<sel>"
6122 "*
6123 { return output_isel (operands); }"
6124 [(set_attr "type" "isel")
6125 (set_attr "length" "4")])
6126
6127 (define_expand "movsfcc"
6128 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6129 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6130 (match_operand:SF 2 "gpc_reg_operand" "")
6131 (match_operand:SF 3 "gpc_reg_operand" "")))]
6132 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6133 "
6134 {
6135 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6136 DONE;
6137 else
6138 FAIL;
6139 }")
6140
6141 (define_insn "*fselsfsf4"
6142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6143 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6144 (match_operand:SF 4 "zero_fp_constant" "F"))
6145 (match_operand:SF 2 "gpc_reg_operand" "f")
6146 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6147 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6148 "fsel %0,%1,%2,%3"
6149 [(set_attr "type" "fp")])
6150
6151 (define_insn "*fseldfsf4"
6152 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6153 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6154 (match_operand:DF 4 "zero_fp_constant" "F"))
6155 (match_operand:SF 2 "gpc_reg_operand" "f")
6156 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6157 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6158 "fsel %0,%1,%2,%3"
6159 [(set_attr "type" "fp")])
6160
6161 (define_expand "negdf2"
6162 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6163 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6164 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6165 "")
6166
6167 (define_insn "*negdf2_fpr"
6168 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6169 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6170 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6171 && !VECTOR_UNIT_VSX_P (DFmode)"
6172 "fneg %0,%1"
6173 [(set_attr "type" "fp")])
6174
6175 (define_expand "absdf2"
6176 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6177 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6178 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6179 "")
6180
6181 (define_insn "*absdf2_fpr"
6182 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6183 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6184 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6185 && !VECTOR_UNIT_VSX_P (DFmode)"
6186 "fabs %0,%1"
6187 [(set_attr "type" "fp")])
6188
6189 (define_insn "*nabsdf2_fpr"
6190 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6191 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6192 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6193 && !VECTOR_UNIT_VSX_P (DFmode)"
6194 "fnabs %0,%1"
6195 [(set_attr "type" "fp")])
6196
6197 (define_expand "adddf3"
6198 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6199 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6200 (match_operand:DF 2 "gpc_reg_operand" "")))]
6201 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6202 "")
6203
6204 (define_insn "*adddf3_fpr"
6205 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6206 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6207 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6208 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6209 && !VECTOR_UNIT_VSX_P (DFmode)"
6210 "{fa|fadd} %0,%1,%2"
6211 [(set_attr "type" "fp")
6212 (set_attr "fp_type" "fp_addsub_d")])
6213
6214 (define_expand "subdf3"
6215 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6216 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6217 (match_operand:DF 2 "gpc_reg_operand" "")))]
6218 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6219 "")
6220
6221 (define_insn "*subdf3_fpr"
6222 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6223 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6224 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6225 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6226 && !VECTOR_UNIT_VSX_P (DFmode)"
6227 "{fs|fsub} %0,%1,%2"
6228 [(set_attr "type" "fp")
6229 (set_attr "fp_type" "fp_addsub_d")])
6230
6231 (define_expand "muldf3"
6232 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6233 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6234 (match_operand:DF 2 "gpc_reg_operand" "")))]
6235 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6236 "")
6237
6238 (define_insn "*muldf3_fpr"
6239 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6240 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6241 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6242 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6243 && !VECTOR_UNIT_VSX_P (DFmode)"
6244 "{fm|fmul} %0,%1,%2"
6245 [(set_attr "type" "dmul")
6246 (set_attr "fp_type" "fp_mul_d")])
6247
6248 (define_expand "divdf3"
6249 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6250 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6251 (match_operand:DF 2 "gpc_reg_operand" "")))]
6252 "TARGET_HARD_FLOAT
6253 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6254 && !TARGET_SIMPLE_FPU"
6255 "")
6256
6257 (define_insn "*divdf3_fpr"
6258 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6259 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6260 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6261 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6262 && !VECTOR_UNIT_VSX_P (DFmode)"
6263 "{fd|fdiv} %0,%1,%2"
6264 [(set_attr "type" "ddiv")])
6265
6266 (define_insn "*fred_fpr"
6267 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6268 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6269 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6270 "fre %0,%1"
6271 [(set_attr "type" "fp")])
6272
6273 (define_insn "*rsqrtdf_internal1"
6274 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6275 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6276 UNSPEC_RSQRT))]
6277 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6278 "frsqrte %0,%1"
6279 [(set_attr "type" "fp")])
6280
6281 ; builtin fma support
6282 (define_insn "*fmadf4_fpr"
6283 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6284 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6285 (match_operand:DF 2 "gpc_reg_operand" "f")
6286 (match_operand:DF 3 "gpc_reg_operand" "f")))]
6287 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6288 && VECTOR_UNIT_NONE_P (DFmode)"
6289 "{fma|fmadd} %0,%1,%2,%3"
6290 [(set_attr "type" "fp")
6291 (set_attr "fp_type" "fp_maddsub_s")])
6292
6293 (define_insn "*fmsdf4_fpr"
6294 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6295 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6296 (match_operand:DF 2 "gpc_reg_operand" "f")
6297 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6298 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6299 && VECTOR_UNIT_NONE_P (DFmode)"
6300 "{fms|fmsub} %0,%1,%2,%3"
6301 [(set_attr "type" "fp")
6302 (set_attr "fp_type" "fp_maddsub_s")])
6303
6304 (define_insn "*nfmadf4_fpr"
6305 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6306 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6307 (match_operand:DF 2 "gpc_reg_operand" "f")
6308 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6309 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6310 && VECTOR_UNIT_NONE_P (DFmode)"
6311 "{fnma|fnmadd} %0,%1,%2,%3"
6312 [(set_attr "type" "fp")
6313 (set_attr "fp_type" "fp_maddsub_s")])
6314
6315 (define_insn "*nfmsdf4_fpr"
6316 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6317 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6318 (match_operand:DF 2 "gpc_reg_operand" "f")
6319 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
6320 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6321 && VECTOR_UNIT_NONE_P (DFmode)"
6322 "{fnms|fnmsub} %0,%1,%2,%3"
6323 [(set_attr "type" "fp")
6324 (set_attr "fp_type" "fp_maddsub_s")])
6325
6326 (define_expand "sqrtdf2"
6327 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6328 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6329 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6330 && TARGET_DOUBLE_FLOAT"
6331 "")
6332
6333 (define_insn "*sqrtdf2_fpr"
6334 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6335 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6336 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6337 && TARGET_DOUBLE_FLOAT
6338 && !VECTOR_UNIT_VSX_P (DFmode)"
6339 "fsqrt %0,%1"
6340 [(set_attr "type" "dsqrt")])
6341
6342 ;; The conditional move instructions allow us to perform max and min
6343 ;; operations even when
6344
6345 (define_expand "smaxdf3"
6346 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6347 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6348 (match_operand:DF 2 "gpc_reg_operand" ""))
6349 (match_dup 1)
6350 (match_dup 2)))]
6351 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6352 && !flag_trapping_math"
6353 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6354
6355 (define_expand "smindf3"
6356 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6357 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6358 (match_operand:DF 2 "gpc_reg_operand" ""))
6359 (match_dup 2)
6360 (match_dup 1)))]
6361 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6362 && !flag_trapping_math"
6363 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6364
6365 (define_split
6366 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6367 (match_operator:DF 3 "min_max_operator"
6368 [(match_operand:DF 1 "gpc_reg_operand" "")
6369 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6370 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6371 && !flag_trapping_math"
6372 [(const_int 0)]
6373 "
6374 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6375 operands[1], operands[2]);
6376 DONE;
6377 }")
6378
6379 (define_expand "movdfcc"
6380 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6381 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6382 (match_operand:DF 2 "gpc_reg_operand" "")
6383 (match_operand:DF 3 "gpc_reg_operand" "")))]
6384 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6385 "
6386 {
6387 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6388 DONE;
6389 else
6390 FAIL;
6391 }")
6392
6393 (define_insn "*fseldfdf4"
6394 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6395 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6396 (match_operand:DF 4 "zero_fp_constant" "F"))
6397 (match_operand:DF 2 "gpc_reg_operand" "d")
6398 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6399 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6400 "fsel %0,%1,%2,%3"
6401 [(set_attr "type" "fp")])
6402
6403 (define_insn "*fselsfdf4"
6404 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6405 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6406 (match_operand:SF 4 "zero_fp_constant" "F"))
6407 (match_operand:DF 2 "gpc_reg_operand" "d")
6408 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6409 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6410 "fsel %0,%1,%2,%3"
6411 [(set_attr "type" "fp")])
6412 \f
6413 ;; Conversions to and from floating-point.
6414
6415 ; We don't define lfiwax/lfiwzx with the normal definition, because we
6416 ; don't want to support putting SImode in FPR registers.
6417 (define_insn "lfiwax"
6418 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6419 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6420 UNSPEC_LFIWAX))]
6421 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
6422 "lfiwax %0,%y1"
6423 [(set_attr "type" "fpload")])
6424
6425 ; This split must be run before register allocation because it allocates the
6426 ; memory slot that is needed to move values to/from the FPR. We don't allocate
6427 ; it earlier to allow for the combiner to merge insns together where it might
6428 ; not be needed and also in case the insns are deleted as dead code.
6429
6430 (define_insn_and_split "floatsi<mode>2_lfiwax"
6431 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6432 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6433 (clobber (match_scratch:DI 2 "=d"))]
6434 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6435 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
6436 "#"
6437 ""
6438 [(pc)]
6439 "
6440 {
6441 rtx dest = operands[0];
6442 rtx src = operands[1];
6443 rtx tmp;
6444
6445 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6446 tmp = convert_to_mode (DImode, src, false);
6447 else
6448 {
6449 tmp = operands[2];
6450 if (GET_CODE (tmp) == SCRATCH)
6451 tmp = gen_reg_rtx (DImode);
6452 if (MEM_P (src))
6453 {
6454 src = rs6000_address_for_fpconvert (src);
6455 emit_insn (gen_lfiwax (tmp, src));
6456 }
6457 else
6458 {
6459 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6460 emit_move_insn (stack, src);
6461 emit_insn (gen_lfiwax (tmp, stack));
6462 }
6463 }
6464 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6465 DONE;
6466 }"
6467 [(set_attr "length" "12")
6468 (set_attr "type" "fpload")])
6469
6470 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
6471 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6472 (float:SFDF
6473 (sign_extend:DI
6474 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6475 (clobber (match_scratch:DI 2 "=0,d"))]
6476 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6477 && <SI_CONVERT_FP>"
6478 "#"
6479 ""
6480 [(pc)]
6481 "
6482 {
6483 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6484 if (GET_CODE (operands[2]) == SCRATCH)
6485 operands[2] = gen_reg_rtx (DImode);
6486 emit_insn (gen_lfiwax (operands[2], operands[1]));
6487 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6488 DONE;
6489 }"
6490 [(set_attr "length" "8")
6491 (set_attr "type" "fpload")])
6492
6493 (define_insn "lfiwzx"
6494 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6495 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6496 UNSPEC_LFIWZX))]
6497 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
6498 "lfiwzx %0,%y1"
6499 [(set_attr "type" "fpload")])
6500
6501 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
6502 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6503 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6504 (clobber (match_scratch:DI 2 "=d"))]
6505 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6506 && <SI_CONVERT_FP>"
6507 "#"
6508 ""
6509 [(pc)]
6510 "
6511 {
6512 rtx dest = operands[0];
6513 rtx src = operands[1];
6514 rtx tmp;
6515
6516 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6517 tmp = convert_to_mode (DImode, src, true);
6518 else
6519 {
6520 tmp = operands[2];
6521 if (GET_CODE (tmp) == SCRATCH)
6522 tmp = gen_reg_rtx (DImode);
6523 if (MEM_P (src))
6524 {
6525 src = rs6000_address_for_fpconvert (src);
6526 emit_insn (gen_lfiwzx (tmp, src));
6527 }
6528 else
6529 {
6530 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6531 emit_move_insn (stack, src);
6532 emit_insn (gen_lfiwzx (tmp, stack));
6533 }
6534 }
6535 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6536 DONE;
6537 }"
6538 [(set_attr "length" "12")
6539 (set_attr "type" "fpload")])
6540
6541 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
6542 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6543 (unsigned_float:SFDF
6544 (zero_extend:DI
6545 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6546 (clobber (match_scratch:DI 2 "=0,d"))]
6547 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6548 && <SI_CONVERT_FP>"
6549 "#"
6550 ""
6551 [(pc)]
6552 "
6553 {
6554 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6555 if (GET_CODE (operands[2]) == SCRATCH)
6556 operands[2] = gen_reg_rtx (DImode);
6557 emit_insn (gen_lfiwzx (operands[2], operands[1]));
6558 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6559 DONE;
6560 }"
6561 [(set_attr "length" "8")
6562 (set_attr "type" "fpload")])
6563
6564 ; For each of these conversions, there is a define_expand, a define_insn
6565 ; with a '#' template, and a define_split (with C code). The idea is
6566 ; to allow constant folding with the template of the define_insn,
6567 ; then to have the insns split later (between sched1 and final).
6568
6569 (define_expand "floatsidf2"
6570 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6571 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6572 (use (match_dup 2))
6573 (use (match_dup 3))
6574 (clobber (match_dup 4))
6575 (clobber (match_dup 5))
6576 (clobber (match_dup 6))])]
6577 "TARGET_HARD_FLOAT
6578 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6579 "
6580 {
6581 if (TARGET_E500_DOUBLE)
6582 {
6583 if (!REG_P (operands[1]))
6584 operands[1] = force_reg (SImode, operands[1]);
6585 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6586 DONE;
6587 }
6588 else if (TARGET_LFIWAX && TARGET_FCFID)
6589 {
6590 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
6591 DONE;
6592 }
6593 else if (TARGET_FCFID)
6594 {
6595 rtx dreg = operands[1];
6596 if (!REG_P (dreg))
6597 dreg = force_reg (SImode, dreg);
6598 dreg = convert_to_mode (DImode, dreg, false);
6599 emit_insn (gen_floatdidf2 (operands[0], dreg));
6600 DONE;
6601 }
6602
6603 if (!REG_P (operands[1]))
6604 operands[1] = force_reg (SImode, operands[1]);
6605 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6606 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6607 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6608 operands[5] = gen_reg_rtx (DFmode);
6609 operands[6] = gen_reg_rtx (SImode);
6610 }")
6611
6612 (define_insn_and_split "*floatsidf2_internal"
6613 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6614 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6615 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6616 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6617 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6618 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6619 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6620 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6621 "#"
6622 ""
6623 [(pc)]
6624 "
6625 {
6626 rtx lowword, highword;
6627 gcc_assert (MEM_P (operands[4]));
6628 highword = adjust_address (operands[4], SImode, 0);
6629 lowword = adjust_address (operands[4], SImode, 4);
6630 if (! WORDS_BIG_ENDIAN)
6631 {
6632 rtx tmp;
6633 tmp = highword; highword = lowword; lowword = tmp;
6634 }
6635
6636 emit_insn (gen_xorsi3 (operands[6], operands[1],
6637 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6638 emit_move_insn (lowword, operands[6]);
6639 emit_move_insn (highword, operands[2]);
6640 emit_move_insn (operands[5], operands[4]);
6641 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6642 DONE;
6643 }"
6644 [(set_attr "length" "24")
6645 (set_attr "type" "fp")])
6646
6647 ;; If we don't have a direct conversion to single precision, don't enable this
6648 ;; conversion for 32-bit without fast math, because we don't have the insn to
6649 ;; generate the fixup swizzle to avoid double rounding problems.
6650 (define_expand "floatunssisf2"
6651 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6652 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6653 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6654 && (!TARGET_FPRS
6655 || (TARGET_FPRS
6656 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6657 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6658 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6659 "
6660 {
6661 if (!TARGET_FPRS)
6662 {
6663 if (!REG_P (operands[1]))
6664 operands[1] = force_reg (SImode, operands[1]);
6665 }
6666 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
6667 {
6668 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
6669 DONE;
6670 }
6671 else
6672 {
6673 rtx dreg = operands[1];
6674 if (!REG_P (dreg))
6675 dreg = force_reg (SImode, dreg);
6676 dreg = convert_to_mode (DImode, dreg, true);
6677 emit_insn (gen_floatdisf2 (operands[0], dreg));
6678 DONE;
6679 }
6680 }")
6681
6682 (define_expand "floatunssidf2"
6683 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6684 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6685 (use (match_dup 2))
6686 (use (match_dup 3))
6687 (clobber (match_dup 4))
6688 (clobber (match_dup 5))])]
6689 "TARGET_HARD_FLOAT
6690 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6691 "
6692 {
6693 if (TARGET_E500_DOUBLE)
6694 {
6695 if (!REG_P (operands[1]))
6696 operands[1] = force_reg (SImode, operands[1]);
6697 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6698 DONE;
6699 }
6700 else if (TARGET_LFIWZX && TARGET_FCFID)
6701 {
6702 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
6703 DONE;
6704 }
6705 else if (TARGET_FCFID)
6706 {
6707 rtx dreg = operands[1];
6708 if (!REG_P (dreg))
6709 dreg = force_reg (SImode, dreg);
6710 dreg = convert_to_mode (DImode, dreg, true);
6711 emit_insn (gen_floatdidf2 (operands[0], dreg));
6712 DONE;
6713 }
6714
6715 if (!REG_P (operands[1]))
6716 operands[1] = force_reg (SImode, operands[1]);
6717 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6718 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6719 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6720 operands[5] = gen_reg_rtx (DFmode);
6721 }")
6722
6723 (define_insn_and_split "*floatunssidf2_internal"
6724 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6725 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6726 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6727 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6728 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6729 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6730 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6731 && !(TARGET_FCFID && TARGET_POWERPC64)"
6732 "#"
6733 ""
6734 [(pc)]
6735 "
6736 {
6737 rtx lowword, highword;
6738 gcc_assert (MEM_P (operands[4]));
6739 highword = adjust_address (operands[4], SImode, 0);
6740 lowword = adjust_address (operands[4], SImode, 4);
6741 if (! WORDS_BIG_ENDIAN)
6742 {
6743 rtx tmp;
6744 tmp = highword; highword = lowword; lowword = tmp;
6745 }
6746
6747 emit_move_insn (lowword, operands[1]);
6748 emit_move_insn (highword, operands[2]);
6749 emit_move_insn (operands[5], operands[4]);
6750 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6751 DONE;
6752 }"
6753 [(set_attr "length" "20")
6754 (set_attr "type" "fp")])
6755
6756 (define_expand "fix_trunc<mode>si2"
6757 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6758 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6759 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
6760 && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
6761 "
6762 {
6763 if (!<E500_CONVERT>)
6764 {
6765 rtx tmp, stack;
6766
6767 if (TARGET_STFIWX)
6768 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6769 else
6770 {
6771 tmp = gen_reg_rtx (DImode);
6772 stack = rs6000_allocate_stack_temp (DImode, true, false);
6773 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6774 tmp, stack));
6775 }
6776 DONE;
6777 }
6778 }")
6779
6780 ; Like the convert to float patterns, this insn must be split before
6781 ; register allocation so that it can allocate the memory slot if it
6782 ; needed
6783 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6784 [(set (match_operand:SI 0 "general_operand" "=rm")
6785 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6786 (clobber (match_scratch:DI 2 "=d"))]
6787 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6788 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6789 && TARGET_STFIWX && can_create_pseudo_p ()"
6790 "#"
6791 ""
6792 [(pc)]
6793 {
6794 rtx dest = operands[0];
6795 rtx src = operands[1];
6796 rtx tmp = operands[2];
6797
6798 if (GET_CODE (tmp) == SCRATCH)
6799 tmp = gen_reg_rtx (DImode);
6800
6801 emit_insn (gen_fctiwz_<mode> (tmp, src));
6802 if (MEM_P (dest))
6803 {
6804 dest = rs6000_address_for_fpconvert (dest);
6805 emit_insn (gen_stfiwx (dest, tmp));
6806 DONE;
6807 }
6808 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6809 {
6810 dest = gen_lowpart (DImode, dest);
6811 emit_move_insn (dest, tmp);
6812 DONE;
6813 }
6814 else
6815 {
6816 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6817 emit_insn (gen_stfiwx (stack, tmp));
6818 emit_move_insn (dest, stack);
6819 DONE;
6820 }
6821 }
6822 [(set_attr "length" "12")
6823 (set_attr "type" "fp")])
6824
6825 (define_insn_and_split "fix_trunc<mode>si2_internal"
6826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6827 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6828 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6829 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6830 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6831 && TARGET_DOUBLE_FLOAT"
6832 "#"
6833 ""
6834 [(pc)]
6835 "
6836 {
6837 rtx lowword;
6838 gcc_assert (MEM_P (operands[3]));
6839 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6840
6841 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6842 emit_move_insn (operands[3], operands[2]);
6843 emit_move_insn (operands[0], lowword);
6844 DONE;
6845 }"
6846 [(set_attr "length" "16")
6847 (set_attr "type" "fp")])
6848
6849 (define_expand "fix_trunc<mode>di2"
6850 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6851 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6852 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6853 && TARGET_FCFID"
6854 "")
6855
6856 (define_insn "*fix_trunc<mode>di2_fctidz"
6857 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6858 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6859 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6860 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6861 "fctidz %0,%1"
6862 [(set_attr "type" "fp")])
6863
6864 (define_expand "fixuns_trunc<mode>si2"
6865 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6866 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6867 "TARGET_HARD_FLOAT
6868 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6869 || <E500_CONVERT>)"
6870 "
6871 {
6872 if (!<E500_CONVERT>)
6873 {
6874 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6875 DONE;
6876 }
6877 }")
6878
6879 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6880 [(set (match_operand:SI 0 "general_operand" "=rm")
6881 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6882 (clobber (match_scratch:DI 2 "=d"))]
6883 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6884 && TARGET_STFIWX && can_create_pseudo_p ()"
6885 "#"
6886 ""
6887 [(pc)]
6888 {
6889 rtx dest = operands[0];
6890 rtx src = operands[1];
6891 rtx tmp = operands[2];
6892
6893 if (GET_CODE (tmp) == SCRATCH)
6894 tmp = gen_reg_rtx (DImode);
6895
6896 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6897 if (MEM_P (dest))
6898 {
6899 dest = rs6000_address_for_fpconvert (dest);
6900 emit_insn (gen_stfiwx (dest, tmp));
6901 DONE;
6902 }
6903 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6904 {
6905 dest = gen_lowpart (DImode, dest);
6906 emit_move_insn (dest, tmp);
6907 DONE;
6908 }
6909 else
6910 {
6911 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6912 emit_insn (gen_stfiwx (stack, tmp));
6913 emit_move_insn (dest, stack);
6914 DONE;
6915 }
6916 }
6917 [(set_attr "length" "12")
6918 (set_attr "type" "fp")])
6919
6920 (define_expand "fixuns_trunc<mode>di2"
6921 [(set (match_operand:DI 0 "register_operand" "")
6922 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6923 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6924 "")
6925
6926 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6927 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6928 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6929 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6930 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6931 "fctiduz %0,%1"
6932 [(set_attr "type" "fp")])
6933
6934 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6935 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6936 ; because the first makes it clear that operand 0 is not live
6937 ; before the instruction.
6938 (define_insn "fctiwz_<mode>"
6939 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6940 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6941 UNSPEC_FCTIWZ))]
6942 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6943 && TARGET_DOUBLE_FLOAT"
6944 "{fcirz|fctiwz} %0,%1"
6945 [(set_attr "type" "fp")])
6946
6947 (define_insn "fctiwuz_<mode>"
6948 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6949 (unspec:DI [(unsigned_fix:SI
6950 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6951 UNSPEC_FCTIWUZ))]
6952 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6953 "fctiwuz %0,%1"
6954 [(set_attr "type" "fp")])
6955
6956 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6957 ;; since the friz instruction does not truncate the value if the floating
6958 ;; point value is < LONG_MIN or > LONG_MAX.
6959 (define_insn "*friz"
6960 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6961 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6962 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6963 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6964 && !flag_trapping_math && TARGET_FRIZ"
6965 "friz %0,%1"
6966 [(set_attr "type" "fp")])
6967
6968 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6969 ;; load to properly sign extend the value, but at least doing a store, load
6970 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6971 ;; if we have 32-bit memory ops
6972 (define_insn_and_split "*round32<mode>2_fprs"
6973 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6974 (float:SFDF
6975 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6976 (clobber (match_scratch:DI 2 "=d"))
6977 (clobber (match_scratch:DI 3 "=d"))]
6978 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6979 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6980 && can_create_pseudo_p ()"
6981 "#"
6982 ""
6983 [(pc)]
6984 {
6985 rtx dest = operands[0];
6986 rtx src = operands[1];
6987 rtx tmp1 = operands[2];
6988 rtx tmp2 = operands[3];
6989 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6990
6991 if (GET_CODE (tmp1) == SCRATCH)
6992 tmp1 = gen_reg_rtx (DImode);
6993 if (GET_CODE (tmp2) == SCRATCH)
6994 tmp2 = gen_reg_rtx (DImode);
6995
6996 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6997 emit_insn (gen_stfiwx (stack, tmp1));
6998 emit_insn (gen_lfiwax (tmp2, stack));
6999 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7000 DONE;
7001 }
7002 [(set_attr "type" "fpload")
7003 (set_attr "length" "16")])
7004
7005 (define_insn_and_split "*roundu32<mode>2_fprs"
7006 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
7007 (unsigned_float:SFDF
7008 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
7009 (clobber (match_scratch:DI 2 "=d"))
7010 (clobber (match_scratch:DI 3 "=d"))]
7011 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7012 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
7013 && can_create_pseudo_p ()"
7014 "#"
7015 ""
7016 [(pc)]
7017 {
7018 rtx dest = operands[0];
7019 rtx src = operands[1];
7020 rtx tmp1 = operands[2];
7021 rtx tmp2 = operands[3];
7022 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
7023
7024 if (GET_CODE (tmp1) == SCRATCH)
7025 tmp1 = gen_reg_rtx (DImode);
7026 if (GET_CODE (tmp2) == SCRATCH)
7027 tmp2 = gen_reg_rtx (DImode);
7028
7029 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
7030 emit_insn (gen_stfiwx (stack, tmp1));
7031 emit_insn (gen_lfiwzx (tmp2, stack));
7032 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7033 DONE;
7034 }
7035 [(set_attr "type" "fpload")
7036 (set_attr "length" "16")])
7037
7038 ;; No VSX equivalent to fctid
7039 (define_insn "lrint<mode>di2"
7040 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
7041 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7042 UNSPEC_FCTID))]
7043 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7044 "fctid %0,%1"
7045 [(set_attr "type" "fp")])
7046
7047 (define_expand "btrunc<mode>2"
7048 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7049 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7050 UNSPEC_FRIZ))]
7051 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7052 "")
7053
7054 (define_insn "*btrunc<mode>2_fpr"
7055 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7056 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7057 UNSPEC_FRIZ))]
7058 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7059 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7060 "friz %0,%1"
7061 [(set_attr "type" "fp")])
7062
7063 (define_expand "ceil<mode>2"
7064 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7065 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7066 UNSPEC_FRIP))]
7067 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7068 "")
7069
7070 (define_insn "*ceil<mode>2_fpr"
7071 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7072 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7073 UNSPEC_FRIP))]
7074 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7075 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7076 "frip %0,%1"
7077 [(set_attr "type" "fp")])
7078
7079 (define_expand "floor<mode>2"
7080 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7081 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7082 UNSPEC_FRIM))]
7083 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7084 "")
7085
7086 (define_insn "*floor<mode>2_fpr"
7087 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7088 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7089 UNSPEC_FRIM))]
7090 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7091 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7092 "frim %0,%1"
7093 [(set_attr "type" "fp")])
7094
7095 ;; No VSX equivalent to frin
7096 (define_insn "round<mode>2"
7097 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7098 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7099 UNSPEC_FRIN))]
7100 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7101 "frin %0,%1"
7102 [(set_attr "type" "fp")])
7103
7104 ; An UNSPEC is used so we don't have to support SImode in FP registers.
7105 (define_insn "stfiwx"
7106 [(set (match_operand:SI 0 "memory_operand" "=Z")
7107 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
7108 UNSPEC_STFIWX))]
7109 "TARGET_PPC_GFXOPT"
7110 "stfiwx %1,%y0"
7111 [(set_attr "type" "fpstore")])
7112
7113 ;; If we don't have a direct conversion to single precision, don't enable this
7114 ;; conversion for 32-bit without fast math, because we don't have the insn to
7115 ;; generate the fixup swizzle to avoid double rounding problems.
7116 (define_expand "floatsisf2"
7117 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7118 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
7119 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
7120 && (!TARGET_FPRS
7121 || (TARGET_FPRS
7122 && ((TARGET_FCFIDS && TARGET_LFIWAX)
7123 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
7124 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
7125 "
7126 {
7127 if (!TARGET_FPRS)
7128 {
7129 if (!REG_P (operands[1]))
7130 operands[1] = force_reg (SImode, operands[1]);
7131 }
7132 else if (TARGET_FCFIDS && TARGET_LFIWAX)
7133 {
7134 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
7135 DONE;
7136 }
7137 else if (TARGET_FCFID && TARGET_LFIWAX)
7138 {
7139 rtx dfreg = gen_reg_rtx (DFmode);
7140 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
7141 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
7142 DONE;
7143 }
7144 else
7145 {
7146 rtx dreg = operands[1];
7147 if (!REG_P (dreg))
7148 dreg = force_reg (SImode, dreg);
7149 dreg = convert_to_mode (DImode, dreg, false);
7150 emit_insn (gen_floatdisf2 (operands[0], dreg));
7151 DONE;
7152 }
7153 }")
7154
7155 (define_expand "floatdidf2"
7156 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7157 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
7158 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
7159 "")
7160
7161 (define_insn "*floatdidf2_fpr"
7162 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7163 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7164 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
7165 && !VECTOR_UNIT_VSX_P (DFmode)"
7166 "fcfid %0,%1"
7167 [(set_attr "type" "fp")])
7168
7169 ; Allow the combiner to merge source memory operands to the conversion so that
7170 ; the optimizer/register allocator doesn't try to load the value too early in a
7171 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
7172 ; hit. We will split after reload to avoid the trip through the GPRs
7173
7174 (define_insn_and_split "*floatdidf2_mem"
7175 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7176 (float:DF (match_operand:DI 1 "memory_operand" "m")))
7177 (clobber (match_scratch:DI 2 "=d"))]
7178 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
7179 "#"
7180 "&& reload_completed"
7181 [(set (match_dup 2) (match_dup 1))
7182 (set (match_dup 0) (float:DF (match_dup 2)))]
7183 ""
7184 [(set_attr "length" "8")
7185 (set_attr "type" "fpload")])
7186
7187 (define_expand "floatunsdidf2"
7188 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7189 (unsigned_float:DF
7190 (match_operand:DI 1 "gpc_reg_operand" "")))]
7191 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7192 "")
7193
7194 (define_insn "*floatunsdidf2_fcfidu"
7195 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7196 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7197 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
7198 "fcfidu %0,%1"
7199 [(set_attr "type" "fp")
7200 (set_attr "length" "4")])
7201
7202 (define_insn_and_split "*floatunsdidf2_mem"
7203 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7204 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
7205 (clobber (match_scratch:DI 2 "=d"))]
7206 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7207 "#"
7208 "&& reload_completed"
7209 [(set (match_dup 2) (match_dup 1))
7210 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
7211 ""
7212 [(set_attr "length" "8")
7213 (set_attr "type" "fpload")])
7214
7215 (define_expand "floatdisf2"
7216 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7217 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7218 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7219 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
7220 "
7221 {
7222 if (!TARGET_FCFIDS)
7223 {
7224 rtx val = operands[1];
7225 if (!flag_unsafe_math_optimizations)
7226 {
7227 rtx label = gen_label_rtx ();
7228 val = gen_reg_rtx (DImode);
7229 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
7230 emit_label (label);
7231 }
7232 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
7233 DONE;
7234 }
7235 }")
7236
7237 (define_insn "floatdisf2_fcfids"
7238 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7239 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7240 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7241 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7242 "fcfids %0,%1"
7243 [(set_attr "type" "fp")])
7244
7245 (define_insn_and_split "*floatdisf2_mem"
7246 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7247 (float:SF (match_operand:DI 1 "memory_operand" "m")))
7248 (clobber (match_scratch:DI 2 "=f"))]
7249 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7250 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7251 "#"
7252 "&& reload_completed"
7253 [(pc)]
7254 "
7255 {
7256 emit_move_insn (operands[2], operands[1]);
7257 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
7258 DONE;
7259 }"
7260 [(set_attr "length" "8")])
7261
7262 ;; This is not IEEE compliant if rounding mode is "round to nearest".
7263 ;; If the DI->DF conversion is inexact, then it's possible to suffer
7264 ;; from double rounding.
7265 ;; Instead of creating a new cpu type for two FP operations, just use fp
7266 (define_insn_and_split "floatdisf2_internal1"
7267 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7268 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
7269 (clobber (match_scratch:DF 2 "=d"))]
7270 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7271 "#"
7272 "&& reload_completed"
7273 [(set (match_dup 2)
7274 (float:DF (match_dup 1)))
7275 (set (match_dup 0)
7276 (float_truncate:SF (match_dup 2)))]
7277 ""
7278 [(set_attr "length" "8")
7279 (set_attr "type" "fp")])
7280
7281 ;; Twiddles bits to avoid double rounding.
7282 ;; Bits that might be truncated when converting to DFmode are replaced
7283 ;; by a bit that won't be lost at that stage, but is below the SFmode
7284 ;; rounding position.
7285 (define_expand "floatdisf2_internal2"
7286 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
7287 (const_int 53)))
7288 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
7289 (const_int 2047)))
7290 (clobber (scratch:CC))])
7291 (set (match_dup 3) (plus:DI (match_dup 3)
7292 (const_int 1)))
7293 (set (match_dup 0) (plus:DI (match_dup 0)
7294 (const_int 2047)))
7295 (set (match_dup 4) (compare:CCUNS (match_dup 3)
7296 (const_int 2)))
7297 (set (match_dup 0) (ior:DI (match_dup 0)
7298 (match_dup 1)))
7299 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
7300 (const_int -2048)))
7301 (clobber (scratch:CC))])
7302 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
7303 (label_ref (match_operand:DI 2 "" ""))
7304 (pc)))
7305 (set (match_dup 0) (match_dup 1))]
7306 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7307 "
7308 {
7309 operands[3] = gen_reg_rtx (DImode);
7310 operands[4] = gen_reg_rtx (CCUNSmode);
7311 }")
7312
7313 (define_expand "floatunsdisf2"
7314 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7315 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7316 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7317 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7318 "")
7319
7320 (define_insn "floatunsdisf2_fcfidus"
7321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7322 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7323 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7324 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7325 "fcfidus %0,%1"
7326 [(set_attr "type" "fp")])
7327
7328 (define_insn_and_split "*floatunsdisf2_mem"
7329 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7330 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
7331 (clobber (match_scratch:DI 2 "=f"))]
7332 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7333 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7334 "#"
7335 "&& reload_completed"
7336 [(pc)]
7337 "
7338 {
7339 emit_move_insn (operands[2], operands[1]);
7340 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
7341 DONE;
7342 }"
7343 [(set_attr "length" "8")
7344 (set_attr "type" "fpload")])
7345 \f
7346 ;; Define the DImode operations that can be done in a small number
7347 ;; of instructions. The & constraints are to prevent the register
7348 ;; allocator from allocating registers that overlap with the inputs
7349 ;; (for example, having an input in 7,8 and an output in 6,7). We
7350 ;; also allow for the output being the same as one of the inputs.
7351
7352 (define_insn "*adddi3_noppc64"
7353 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
7354 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
7355 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
7356 "! TARGET_POWERPC64"
7357 "*
7358 {
7359 if (WORDS_BIG_ENDIAN)
7360 return (GET_CODE (operands[2])) != CONST_INT
7361 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
7362 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
7363 else
7364 return (GET_CODE (operands[2])) != CONST_INT
7365 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
7366 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
7367 }"
7368 [(set_attr "type" "two")
7369 (set_attr "length" "8")])
7370
7371 (define_insn "*subdi3_noppc64"
7372 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
7373 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
7374 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
7375 "! TARGET_POWERPC64"
7376 "*
7377 {
7378 if (WORDS_BIG_ENDIAN)
7379 return (GET_CODE (operands[1]) != CONST_INT)
7380 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
7381 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
7382 else
7383 return (GET_CODE (operands[1]) != CONST_INT)
7384 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
7385 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
7386 }"
7387 [(set_attr "type" "two")
7388 (set_attr "length" "8")])
7389
7390 (define_insn "*negdi2_noppc64"
7391 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7392 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
7393 "! TARGET_POWERPC64"
7394 "*
7395 {
7396 return (WORDS_BIG_ENDIAN)
7397 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
7398 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
7399 }"
7400 [(set_attr "type" "two")
7401 (set_attr "length" "8")])
7402
7403 (define_expand "mulsidi3"
7404 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7405 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7406 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7407 "! TARGET_POWERPC64"
7408 "
7409 {
7410 if (! TARGET_POWER && ! TARGET_POWERPC)
7411 {
7412 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7413 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7414 emit_insn (gen_mull_call ());
7415 if (WORDS_BIG_ENDIAN)
7416 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
7417 else
7418 {
7419 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
7420 gen_rtx_REG (SImode, 3));
7421 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
7422 gen_rtx_REG (SImode, 4));
7423 }
7424 DONE;
7425 }
7426 else if (TARGET_POWER)
7427 {
7428 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
7429 DONE;
7430 }
7431 }")
7432
7433 (define_insn "mulsidi3_mq"
7434 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7435 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7436 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7437 (clobber (match_scratch:SI 3 "=q"))]
7438 "TARGET_POWER"
7439 "mul %0,%1,%2\;mfmq %L0"
7440 [(set_attr "type" "imul")
7441 (set_attr "length" "8")])
7442
7443 (define_insn "*mulsidi3_no_mq"
7444 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7445 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7446 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7447 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7448 "*
7449 {
7450 return (WORDS_BIG_ENDIAN)
7451 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7452 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7453 }"
7454 [(set_attr "type" "imul")
7455 (set_attr "length" "8")])
7456
7457 (define_split
7458 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7459 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7460 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7461 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7462 [(set (match_dup 3)
7463 (truncate:SI
7464 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7465 (sign_extend:DI (match_dup 2)))
7466 (const_int 32))))
7467 (set (match_dup 4)
7468 (mult:SI (match_dup 1)
7469 (match_dup 2)))]
7470 "
7471 {
7472 int endian = (WORDS_BIG_ENDIAN == 0);
7473 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7474 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7475 }")
7476
7477 (define_expand "umulsidi3"
7478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7479 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7480 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7481 "TARGET_POWERPC && ! TARGET_POWERPC64"
7482 "
7483 {
7484 if (TARGET_POWER)
7485 {
7486 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7487 DONE;
7488 }
7489 }")
7490
7491 (define_insn "umulsidi3_mq"
7492 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7493 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7494 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7495 (clobber (match_scratch:SI 3 "=q"))]
7496 "TARGET_POWERPC && TARGET_POWER"
7497 "*
7498 {
7499 return (WORDS_BIG_ENDIAN)
7500 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7501 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7502 }"
7503 [(set_attr "type" "imul")
7504 (set_attr "length" "8")])
7505
7506 (define_insn "*umulsidi3_no_mq"
7507 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7508 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7509 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7510 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7511 "*
7512 {
7513 return (WORDS_BIG_ENDIAN)
7514 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7515 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7516 }"
7517 [(set_attr "type" "imul")
7518 (set_attr "length" "8")])
7519
7520 (define_split
7521 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7522 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7523 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7524 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7525 [(set (match_dup 3)
7526 (truncate:SI
7527 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7528 (zero_extend:DI (match_dup 2)))
7529 (const_int 32))))
7530 (set (match_dup 4)
7531 (mult:SI (match_dup 1)
7532 (match_dup 2)))]
7533 "
7534 {
7535 int endian = (WORDS_BIG_ENDIAN == 0);
7536 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7537 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7538 }")
7539
7540 (define_expand "smulsi3_highpart"
7541 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7542 (truncate:SI
7543 (lshiftrt:DI (mult:DI (sign_extend:DI
7544 (match_operand:SI 1 "gpc_reg_operand" ""))
7545 (sign_extend:DI
7546 (match_operand:SI 2 "gpc_reg_operand" "")))
7547 (const_int 32))))]
7548 ""
7549 "
7550 {
7551 if (! TARGET_POWER && ! TARGET_POWERPC)
7552 {
7553 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7554 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7555 emit_insn (gen_mulh_call ());
7556 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7557 DONE;
7558 }
7559 else if (TARGET_POWER)
7560 {
7561 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7562 DONE;
7563 }
7564 }")
7565
7566 (define_insn "smulsi3_highpart_mq"
7567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7568 (truncate:SI
7569 (lshiftrt:DI (mult:DI (sign_extend:DI
7570 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7571 (sign_extend:DI
7572 (match_operand:SI 2 "gpc_reg_operand" "r")))
7573 (const_int 32))))
7574 (clobber (match_scratch:SI 3 "=q"))]
7575 "TARGET_POWER"
7576 "mul %0,%1,%2"
7577 [(set_attr "type" "imul")])
7578
7579 (define_insn "*smulsi3_highpart_no_mq"
7580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7581 (truncate:SI
7582 (lshiftrt:DI (mult:DI (sign_extend:DI
7583 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7584 (sign_extend:DI
7585 (match_operand:SI 2 "gpc_reg_operand" "r")))
7586 (const_int 32))))]
7587 "TARGET_POWERPC && ! TARGET_POWER"
7588 "mulhw %0,%1,%2"
7589 [(set_attr "type" "imul")])
7590
7591 (define_expand "umulsi3_highpart"
7592 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7593 (truncate:SI
7594 (lshiftrt:DI (mult:DI (zero_extend:DI
7595 (match_operand:SI 1 "gpc_reg_operand" ""))
7596 (zero_extend:DI
7597 (match_operand:SI 2 "gpc_reg_operand" "")))
7598 (const_int 32))))]
7599 "TARGET_POWERPC"
7600 "
7601 {
7602 if (TARGET_POWER)
7603 {
7604 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7605 DONE;
7606 }
7607 }")
7608
7609 (define_insn "umulsi3_highpart_mq"
7610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7611 (truncate:SI
7612 (lshiftrt:DI (mult:DI (zero_extend:DI
7613 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7614 (zero_extend:DI
7615 (match_operand:SI 2 "gpc_reg_operand" "r")))
7616 (const_int 32))))
7617 (clobber (match_scratch:SI 3 "=q"))]
7618 "TARGET_POWERPC && TARGET_POWER"
7619 "mulhwu %0,%1,%2"
7620 [(set_attr "type" "imul")])
7621
7622 (define_insn "*umulsi3_highpart_no_mq"
7623 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7624 (truncate:SI
7625 (lshiftrt:DI (mult:DI (zero_extend:DI
7626 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7627 (zero_extend:DI
7628 (match_operand:SI 2 "gpc_reg_operand" "r")))
7629 (const_int 32))))]
7630 "TARGET_POWERPC && ! TARGET_POWER"
7631 "mulhwu %0,%1,%2"
7632 [(set_attr "type" "imul")])
7633
7634 ;; If operands 0 and 2 are in the same register, we have a problem. But
7635 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7636 ;; why we have the strange constraints below.
7637 (define_insn "ashldi3_power"
7638 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7639 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7640 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7641 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7642 "TARGET_POWER"
7643 "@
7644 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7645 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7646 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7647 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7648 [(set_attr "length" "8")])
7649
7650 (define_insn "lshrdi3_power"
7651 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7652 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7653 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7654 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7655 "TARGET_POWER"
7656 "@
7657 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7658 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7659 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7660 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7661 [(set_attr "length" "8")])
7662
7663 ;; Shift by a variable amount is too complex to be worth open-coding. We
7664 ;; just handle shifts by constants.
7665 (define_insn "ashrdi3_power"
7666 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7667 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7668 (match_operand:SI 2 "const_int_operand" "M,i")))
7669 (clobber (match_scratch:SI 3 "=X,q"))]
7670 "TARGET_POWER"
7671 "@
7672 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7673 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7674 [(set_attr "type" "shift")
7675 (set_attr "length" "8")])
7676
7677 (define_insn "ashrdi3_no_power"
7678 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7679 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7680 (match_operand:SI 2 "const_int_operand" "M,i")))]
7681 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7682 "@
7683 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7684 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7685 [(set_attr "type" "two,three")
7686 (set_attr "length" "8,12")])
7687
7688 (define_insn "*ashrdisi3_noppc64"
7689 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7690 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7691 (const_int 32)) 4))]
7692 "TARGET_32BIT && !TARGET_POWERPC64"
7693 "*
7694 {
7695 if (REGNO (operands[0]) == REGNO (operands[1]))
7696 return \"\";
7697 else
7698 return \"mr %0,%1\";
7699 }"
7700 [(set_attr "length" "4")])
7701
7702 \f
7703 ;; PowerPC64 DImode operations.
7704
7705 (define_expand "absdi2"
7706 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7707 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7708 "TARGET_POWERPC64"
7709 "
7710 {
7711 if (TARGET_ISEL)
7712 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7713 else
7714 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7715 DONE;
7716 }")
7717
7718 (define_insn_and_split "absdi2_internal"
7719 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7720 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7721 (clobber (match_scratch:DI 2 "=&r,&r"))]
7722 "TARGET_POWERPC64 && !TARGET_ISEL"
7723 "#"
7724 "&& reload_completed"
7725 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7726 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7727 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7728 "")
7729
7730 (define_insn_and_split "*nabsdi2"
7731 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7732 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7733 (clobber (match_scratch:DI 2 "=&r,&r"))]
7734 "TARGET_POWERPC64 && !TARGET_ISEL"
7735 "#"
7736 "&& reload_completed"
7737 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7738 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7739 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7740 "")
7741
7742 (define_insn "muldi3"
7743 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7744 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7745 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7746 "TARGET_POWERPC64"
7747 "@
7748 mulld %0,%1,%2
7749 mulli %0,%1,%2"
7750 [(set (attr "type")
7751 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7752 (const_string "imul3")
7753 (match_operand:SI 2 "short_cint_operand" "")
7754 (const_string "imul2")]
7755 (const_string "lmul")))])
7756
7757 (define_insn "*muldi3_internal1"
7758 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7759 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7760 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7761 (const_int 0)))
7762 (clobber (match_scratch:DI 3 "=r,r"))]
7763 "TARGET_POWERPC64"
7764 "@
7765 mulld. %3,%1,%2
7766 #"
7767 [(set_attr "type" "lmul_compare")
7768 (set_attr "length" "4,8")])
7769
7770 (define_split
7771 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7772 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7773 (match_operand:DI 2 "gpc_reg_operand" ""))
7774 (const_int 0)))
7775 (clobber (match_scratch:DI 3 ""))]
7776 "TARGET_POWERPC64 && reload_completed"
7777 [(set (match_dup 3)
7778 (mult:DI (match_dup 1) (match_dup 2)))
7779 (set (match_dup 0)
7780 (compare:CC (match_dup 3)
7781 (const_int 0)))]
7782 "")
7783
7784 (define_insn "*muldi3_internal2"
7785 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7786 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7787 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7788 (const_int 0)))
7789 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7790 (mult:DI (match_dup 1) (match_dup 2)))]
7791 "TARGET_POWERPC64"
7792 "@
7793 mulld. %0,%1,%2
7794 #"
7795 [(set_attr "type" "lmul_compare")
7796 (set_attr "length" "4,8")])
7797
7798 (define_split
7799 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7800 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7801 (match_operand:DI 2 "gpc_reg_operand" ""))
7802 (const_int 0)))
7803 (set (match_operand:DI 0 "gpc_reg_operand" "")
7804 (mult:DI (match_dup 1) (match_dup 2)))]
7805 "TARGET_POWERPC64 && reload_completed"
7806 [(set (match_dup 0)
7807 (mult:DI (match_dup 1) (match_dup 2)))
7808 (set (match_dup 3)
7809 (compare:CC (match_dup 0)
7810 (const_int 0)))]
7811 "")
7812
7813 (define_insn "smuldi3_highpart"
7814 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7815 (truncate:DI
7816 (lshiftrt:TI (mult:TI (sign_extend:TI
7817 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7818 (sign_extend:TI
7819 (match_operand:DI 2 "gpc_reg_operand" "r")))
7820 (const_int 64))))]
7821 "TARGET_POWERPC64"
7822 "mulhd %0,%1,%2"
7823 [(set_attr "type" "lmul")])
7824
7825 (define_insn "umuldi3_highpart"
7826 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7827 (truncate:DI
7828 (lshiftrt:TI (mult:TI (zero_extend:TI
7829 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7830 (zero_extend:TI
7831 (match_operand:DI 2 "gpc_reg_operand" "r")))
7832 (const_int 64))))]
7833 "TARGET_POWERPC64"
7834 "mulhdu %0,%1,%2"
7835 [(set_attr "type" "lmul")])
7836
7837 (define_insn "rotldi3"
7838 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7839 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7840 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7841 "TARGET_POWERPC64"
7842 "@
7843 rldcl %0,%1,%2,0
7844 rldicl %0,%1,%H2,0"
7845 [(set_attr "type" "var_shift_rotate,integer")])
7846
7847 (define_insn "*rotldi3_internal2"
7848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7849 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7850 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7851 (const_int 0)))
7852 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7853 "TARGET_64BIT"
7854 "@
7855 rldcl. %3,%1,%2,0
7856 rldicl. %3,%1,%H2,0
7857 #
7858 #"
7859 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7860 (set_attr "length" "4,4,8,8")])
7861
7862 (define_split
7863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7864 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7865 (match_operand:DI 2 "reg_or_cint_operand" ""))
7866 (const_int 0)))
7867 (clobber (match_scratch:DI 3 ""))]
7868 "TARGET_POWERPC64 && reload_completed"
7869 [(set (match_dup 3)
7870 (rotate:DI (match_dup 1) (match_dup 2)))
7871 (set (match_dup 0)
7872 (compare:CC (match_dup 3)
7873 (const_int 0)))]
7874 "")
7875
7876 (define_insn "*rotldi3_internal3"
7877 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7878 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7879 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7880 (const_int 0)))
7881 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7882 (rotate:DI (match_dup 1) (match_dup 2)))]
7883 "TARGET_64BIT"
7884 "@
7885 rldcl. %0,%1,%2,0
7886 rldicl. %0,%1,%H2,0
7887 #
7888 #"
7889 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7890 (set_attr "length" "4,4,8,8")])
7891
7892 (define_split
7893 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7894 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7895 (match_operand:DI 2 "reg_or_cint_operand" ""))
7896 (const_int 0)))
7897 (set (match_operand:DI 0 "gpc_reg_operand" "")
7898 (rotate:DI (match_dup 1) (match_dup 2)))]
7899 "TARGET_POWERPC64 && reload_completed"
7900 [(set (match_dup 0)
7901 (rotate:DI (match_dup 1) (match_dup 2)))
7902 (set (match_dup 3)
7903 (compare:CC (match_dup 0)
7904 (const_int 0)))]
7905 "")
7906
7907 (define_insn "*rotldi3_internal4"
7908 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7909 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7910 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7911 (match_operand:DI 3 "mask64_operand" "n,n")))]
7912 "TARGET_POWERPC64"
7913 "@
7914 rldc%B3 %0,%1,%2,%S3
7915 rldic%B3 %0,%1,%H2,%S3"
7916 [(set_attr "type" "var_shift_rotate,integer")])
7917
7918 (define_insn "*rotldi3_internal5"
7919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7920 (compare:CC (and:DI
7921 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7922 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7923 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7924 (const_int 0)))
7925 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7926 "TARGET_64BIT"
7927 "@
7928 rldc%B3. %4,%1,%2,%S3
7929 rldic%B3. %4,%1,%H2,%S3
7930 #
7931 #"
7932 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7933 (set_attr "length" "4,4,8,8")])
7934
7935 (define_split
7936 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7937 (compare:CC (and:DI
7938 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7939 (match_operand:DI 2 "reg_or_cint_operand" ""))
7940 (match_operand:DI 3 "mask64_operand" ""))
7941 (const_int 0)))
7942 (clobber (match_scratch:DI 4 ""))]
7943 "TARGET_POWERPC64 && reload_completed"
7944 [(set (match_dup 4)
7945 (and:DI (rotate:DI (match_dup 1)
7946 (match_dup 2))
7947 (match_dup 3)))
7948 (set (match_dup 0)
7949 (compare:CC (match_dup 4)
7950 (const_int 0)))]
7951 "")
7952
7953 (define_insn "*rotldi3_internal6"
7954 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7955 (compare:CC (and:DI
7956 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7957 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7958 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7959 (const_int 0)))
7960 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7961 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7962 "TARGET_64BIT"
7963 "@
7964 rldc%B3. %0,%1,%2,%S3
7965 rldic%B3. %0,%1,%H2,%S3
7966 #
7967 #"
7968 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7969 (set_attr "length" "4,4,8,8")])
7970
7971 (define_split
7972 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7973 (compare:CC (and:DI
7974 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7975 (match_operand:DI 2 "reg_or_cint_operand" ""))
7976 (match_operand:DI 3 "mask64_operand" ""))
7977 (const_int 0)))
7978 (set (match_operand:DI 0 "gpc_reg_operand" "")
7979 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7980 "TARGET_POWERPC64 && reload_completed"
7981 [(set (match_dup 0)
7982 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7983 (set (match_dup 4)
7984 (compare:CC (match_dup 0)
7985 (const_int 0)))]
7986 "")
7987
7988 (define_insn "*rotldi3_internal7"
7989 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7990 (zero_extend:DI
7991 (subreg:QI
7992 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7993 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7994 "TARGET_POWERPC64"
7995 "@
7996 rldcl %0,%1,%2,56
7997 rldicl %0,%1,%H2,56"
7998 [(set_attr "type" "var_shift_rotate,integer")])
7999
8000 (define_insn "*rotldi3_internal8"
8001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8002 (compare:CC (zero_extend:DI
8003 (subreg:QI
8004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8005 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8006 (const_int 0)))
8007 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8008 "TARGET_64BIT"
8009 "@
8010 rldcl. %3,%1,%2,56
8011 rldicl. %3,%1,%H2,56
8012 #
8013 #"
8014 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8015 (set_attr "length" "4,4,8,8")])
8016
8017 (define_split
8018 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8019 (compare:CC (zero_extend:DI
8020 (subreg:QI
8021 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8022 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8023 (const_int 0)))
8024 (clobber (match_scratch:DI 3 ""))]
8025 "TARGET_POWERPC64 && reload_completed"
8026 [(set (match_dup 3)
8027 (zero_extend:DI (subreg:QI
8028 (rotate:DI (match_dup 1)
8029 (match_dup 2)) 0)))
8030 (set (match_dup 0)
8031 (compare:CC (match_dup 3)
8032 (const_int 0)))]
8033 "")
8034
8035 (define_insn "*rotldi3_internal9"
8036 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8037 (compare:CC (zero_extend:DI
8038 (subreg:QI
8039 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8040 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8041 (const_int 0)))
8042 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8043 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8044 "TARGET_64BIT"
8045 "@
8046 rldcl. %0,%1,%2,56
8047 rldicl. %0,%1,%H2,56
8048 #
8049 #"
8050 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8051 (set_attr "length" "4,4,8,8")])
8052
8053 (define_split
8054 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8055 (compare:CC (zero_extend:DI
8056 (subreg:QI
8057 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8058 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8059 (const_int 0)))
8060 (set (match_operand:DI 0 "gpc_reg_operand" "")
8061 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8062 "TARGET_POWERPC64 && reload_completed"
8063 [(set (match_dup 0)
8064 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8065 (set (match_dup 3)
8066 (compare:CC (match_dup 0)
8067 (const_int 0)))]
8068 "")
8069
8070 (define_insn "*rotldi3_internal10"
8071 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8072 (zero_extend:DI
8073 (subreg:HI
8074 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8075 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8076 "TARGET_POWERPC64"
8077 "@
8078 rldcl %0,%1,%2,48
8079 rldicl %0,%1,%H2,48"
8080 [(set_attr "type" "var_shift_rotate,integer")])
8081
8082 (define_insn "*rotldi3_internal11"
8083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8084 (compare:CC (zero_extend:DI
8085 (subreg:HI
8086 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8087 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8088 (const_int 0)))
8089 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8090 "TARGET_64BIT"
8091 "@
8092 rldcl. %3,%1,%2,48
8093 rldicl. %3,%1,%H2,48
8094 #
8095 #"
8096 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8097 (set_attr "length" "4,4,8,8")])
8098
8099 (define_split
8100 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8101 (compare:CC (zero_extend:DI
8102 (subreg:HI
8103 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8104 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8105 (const_int 0)))
8106 (clobber (match_scratch:DI 3 ""))]
8107 "TARGET_POWERPC64 && reload_completed"
8108 [(set (match_dup 3)
8109 (zero_extend:DI (subreg:HI
8110 (rotate:DI (match_dup 1)
8111 (match_dup 2)) 0)))
8112 (set (match_dup 0)
8113 (compare:CC (match_dup 3)
8114 (const_int 0)))]
8115 "")
8116
8117 (define_insn "*rotldi3_internal12"
8118 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8119 (compare:CC (zero_extend:DI
8120 (subreg:HI
8121 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8122 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8123 (const_int 0)))
8124 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8125 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8126 "TARGET_64BIT"
8127 "@
8128 rldcl. %0,%1,%2,48
8129 rldicl. %0,%1,%H2,48
8130 #
8131 #"
8132 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8133 (set_attr "length" "4,4,8,8")])
8134
8135 (define_split
8136 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8137 (compare:CC (zero_extend:DI
8138 (subreg:HI
8139 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8140 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8141 (const_int 0)))
8142 (set (match_operand:DI 0 "gpc_reg_operand" "")
8143 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8144 "TARGET_POWERPC64 && reload_completed"
8145 [(set (match_dup 0)
8146 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8147 (set (match_dup 3)
8148 (compare:CC (match_dup 0)
8149 (const_int 0)))]
8150 "")
8151
8152 (define_insn "*rotldi3_internal13"
8153 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8154 (zero_extend:DI
8155 (subreg:SI
8156 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8157 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8158 "TARGET_POWERPC64"
8159 "@
8160 rldcl %0,%1,%2,32
8161 rldicl %0,%1,%H2,32"
8162 [(set_attr "type" "var_shift_rotate,integer")])
8163
8164 (define_insn "*rotldi3_internal14"
8165 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8166 (compare:CC (zero_extend:DI
8167 (subreg:SI
8168 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8169 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8170 (const_int 0)))
8171 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8172 "TARGET_64BIT"
8173 "@
8174 rldcl. %3,%1,%2,32
8175 rldicl. %3,%1,%H2,32
8176 #
8177 #"
8178 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8179 (set_attr "length" "4,4,8,8")])
8180
8181 (define_split
8182 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8183 (compare:CC (zero_extend:DI
8184 (subreg:SI
8185 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8186 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8187 (const_int 0)))
8188 (clobber (match_scratch:DI 3 ""))]
8189 "TARGET_POWERPC64 && reload_completed"
8190 [(set (match_dup 3)
8191 (zero_extend:DI (subreg:SI
8192 (rotate:DI (match_dup 1)
8193 (match_dup 2)) 0)))
8194 (set (match_dup 0)
8195 (compare:CC (match_dup 3)
8196 (const_int 0)))]
8197 "")
8198
8199 (define_insn "*rotldi3_internal15"
8200 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8201 (compare:CC (zero_extend:DI
8202 (subreg:SI
8203 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8204 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8205 (const_int 0)))
8206 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8207 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8208 "TARGET_64BIT"
8209 "@
8210 rldcl. %0,%1,%2,32
8211 rldicl. %0,%1,%H2,32
8212 #
8213 #"
8214 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8215 (set_attr "length" "4,4,8,8")])
8216
8217 (define_split
8218 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8219 (compare:CC (zero_extend:DI
8220 (subreg:SI
8221 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8222 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8223 (const_int 0)))
8224 (set (match_operand:DI 0 "gpc_reg_operand" "")
8225 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8226 "TARGET_POWERPC64 && reload_completed"
8227 [(set (match_dup 0)
8228 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8229 (set (match_dup 3)
8230 (compare:CC (match_dup 0)
8231 (const_int 0)))]
8232 "")
8233
8234 (define_expand "ashldi3"
8235 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8236 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8237 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8238 "TARGET_POWERPC64 || TARGET_POWER"
8239 "
8240 {
8241 if (TARGET_POWERPC64)
8242 ;
8243 else if (TARGET_POWER)
8244 {
8245 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
8246 DONE;
8247 }
8248 else
8249 FAIL;
8250 }")
8251
8252 (define_insn "*ashldi3_internal1"
8253 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8254 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8255 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8256 "TARGET_POWERPC64"
8257 "@
8258 sld %0,%1,%2
8259 sldi %0,%1,%H2"
8260 [(set_attr "type" "var_shift_rotate,shift")])
8261
8262 (define_insn "*ashldi3_internal2"
8263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8264 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8265 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8266 (const_int 0)))
8267 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8268 "TARGET_64BIT"
8269 "@
8270 sld. %3,%1,%2
8271 sldi. %3,%1,%H2
8272 #
8273 #"
8274 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8275 (set_attr "length" "4,4,8,8")])
8276
8277 (define_split
8278 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8279 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8280 (match_operand:SI 2 "reg_or_cint_operand" ""))
8281 (const_int 0)))
8282 (clobber (match_scratch:DI 3 ""))]
8283 "TARGET_POWERPC64 && reload_completed"
8284 [(set (match_dup 3)
8285 (ashift:DI (match_dup 1) (match_dup 2)))
8286 (set (match_dup 0)
8287 (compare:CC (match_dup 3)
8288 (const_int 0)))]
8289 "")
8290
8291 (define_insn "*ashldi3_internal3"
8292 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8293 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8294 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8295 (const_int 0)))
8296 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8297 (ashift:DI (match_dup 1) (match_dup 2)))]
8298 "TARGET_64BIT"
8299 "@
8300 sld. %0,%1,%2
8301 sldi. %0,%1,%H2
8302 #
8303 #"
8304 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8305 (set_attr "length" "4,4,8,8")])
8306
8307 (define_split
8308 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8309 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8310 (match_operand:SI 2 "reg_or_cint_operand" ""))
8311 (const_int 0)))
8312 (set (match_operand:DI 0 "gpc_reg_operand" "")
8313 (ashift:DI (match_dup 1) (match_dup 2)))]
8314 "TARGET_POWERPC64 && reload_completed"
8315 [(set (match_dup 0)
8316 (ashift:DI (match_dup 1) (match_dup 2)))
8317 (set (match_dup 3)
8318 (compare:CC (match_dup 0)
8319 (const_int 0)))]
8320 "")
8321
8322 (define_insn "*ashldi3_internal4"
8323 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8324 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8325 (match_operand:SI 2 "const_int_operand" "i"))
8326 (match_operand:DI 3 "const_int_operand" "n")))]
8327 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
8328 "rldic %0,%1,%H2,%W3")
8329
8330 (define_insn "ashldi3_internal5"
8331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8332 (compare:CC
8333 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8334 (match_operand:SI 2 "const_int_operand" "i,i"))
8335 (match_operand:DI 3 "const_int_operand" "n,n"))
8336 (const_int 0)))
8337 (clobber (match_scratch:DI 4 "=r,r"))]
8338 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8339 "@
8340 rldic. %4,%1,%H2,%W3
8341 #"
8342 [(set_attr "type" "compare")
8343 (set_attr "length" "4,8")])
8344
8345 (define_split
8346 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8347 (compare:CC
8348 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8349 (match_operand:SI 2 "const_int_operand" ""))
8350 (match_operand:DI 3 "const_int_operand" ""))
8351 (const_int 0)))
8352 (clobber (match_scratch:DI 4 ""))]
8353 "TARGET_POWERPC64 && reload_completed
8354 && includes_rldic_lshift_p (operands[2], operands[3])"
8355 [(set (match_dup 4)
8356 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8357 (match_dup 3)))
8358 (set (match_dup 0)
8359 (compare:CC (match_dup 4)
8360 (const_int 0)))]
8361 "")
8362
8363 (define_insn "*ashldi3_internal6"
8364 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8365 (compare:CC
8366 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8367 (match_operand:SI 2 "const_int_operand" "i,i"))
8368 (match_operand:DI 3 "const_int_operand" "n,n"))
8369 (const_int 0)))
8370 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8371 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8372 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8373 "@
8374 rldic. %0,%1,%H2,%W3
8375 #"
8376 [(set_attr "type" "compare")
8377 (set_attr "length" "4,8")])
8378
8379 (define_split
8380 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8381 (compare:CC
8382 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8383 (match_operand:SI 2 "const_int_operand" ""))
8384 (match_operand:DI 3 "const_int_operand" ""))
8385 (const_int 0)))
8386 (set (match_operand:DI 0 "gpc_reg_operand" "")
8387 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8388 "TARGET_POWERPC64 && reload_completed
8389 && includes_rldic_lshift_p (operands[2], operands[3])"
8390 [(set (match_dup 0)
8391 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8392 (match_dup 3)))
8393 (set (match_dup 4)
8394 (compare:CC (match_dup 0)
8395 (const_int 0)))]
8396 "")
8397
8398 (define_insn "*ashldi3_internal7"
8399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8400 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8401 (match_operand:SI 2 "const_int_operand" "i"))
8402 (match_operand:DI 3 "mask64_operand" "n")))]
8403 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
8404 "rldicr %0,%1,%H2,%S3")
8405
8406 (define_insn "ashldi3_internal8"
8407 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8408 (compare:CC
8409 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8410 (match_operand:SI 2 "const_int_operand" "i,i"))
8411 (match_operand:DI 3 "mask64_operand" "n,n"))
8412 (const_int 0)))
8413 (clobber (match_scratch:DI 4 "=r,r"))]
8414 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8415 "@
8416 rldicr. %4,%1,%H2,%S3
8417 #"
8418 [(set_attr "type" "compare")
8419 (set_attr "length" "4,8")])
8420
8421 (define_split
8422 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8423 (compare:CC
8424 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8425 (match_operand:SI 2 "const_int_operand" ""))
8426 (match_operand:DI 3 "mask64_operand" ""))
8427 (const_int 0)))
8428 (clobber (match_scratch:DI 4 ""))]
8429 "TARGET_POWERPC64 && reload_completed
8430 && includes_rldicr_lshift_p (operands[2], operands[3])"
8431 [(set (match_dup 4)
8432 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8433 (match_dup 3)))
8434 (set (match_dup 0)
8435 (compare:CC (match_dup 4)
8436 (const_int 0)))]
8437 "")
8438
8439 (define_insn "*ashldi3_internal9"
8440 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8441 (compare:CC
8442 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8443 (match_operand:SI 2 "const_int_operand" "i,i"))
8444 (match_operand:DI 3 "mask64_operand" "n,n"))
8445 (const_int 0)))
8446 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8447 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8448 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8449 "@
8450 rldicr. %0,%1,%H2,%S3
8451 #"
8452 [(set_attr "type" "compare")
8453 (set_attr "length" "4,8")])
8454
8455 (define_split
8456 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8457 (compare:CC
8458 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8459 (match_operand:SI 2 "const_int_operand" ""))
8460 (match_operand:DI 3 "mask64_operand" ""))
8461 (const_int 0)))
8462 (set (match_operand:DI 0 "gpc_reg_operand" "")
8463 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8464 "TARGET_POWERPC64 && reload_completed
8465 && includes_rldicr_lshift_p (operands[2], operands[3])"
8466 [(set (match_dup 0)
8467 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8468 (match_dup 3)))
8469 (set (match_dup 4)
8470 (compare:CC (match_dup 0)
8471 (const_int 0)))]
8472 "")
8473
8474 (define_expand "lshrdi3"
8475 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8476 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8477 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8478 "TARGET_POWERPC64 || TARGET_POWER"
8479 "
8480 {
8481 if (TARGET_POWERPC64)
8482 ;
8483 else if (TARGET_POWER)
8484 {
8485 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8486 DONE;
8487 }
8488 else
8489 FAIL;
8490 }")
8491
8492 (define_insn "*lshrdi3_internal1"
8493 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8494 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8495 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8496 "TARGET_POWERPC64"
8497 "@
8498 srd %0,%1,%2
8499 srdi %0,%1,%H2"
8500 [(set_attr "type" "var_shift_rotate,shift")])
8501
8502 (define_insn "*lshrdi3_internal2"
8503 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8504 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8505 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8506 (const_int 0)))
8507 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8508 "TARGET_64BIT "
8509 "@
8510 srd. %3,%1,%2
8511 srdi. %3,%1,%H2
8512 #
8513 #"
8514 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8515 (set_attr "length" "4,4,8,8")])
8516
8517 (define_split
8518 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8519 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8520 (match_operand:SI 2 "reg_or_cint_operand" ""))
8521 (const_int 0)))
8522 (clobber (match_scratch:DI 3 ""))]
8523 "TARGET_POWERPC64 && reload_completed"
8524 [(set (match_dup 3)
8525 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8526 (set (match_dup 0)
8527 (compare:CC (match_dup 3)
8528 (const_int 0)))]
8529 "")
8530
8531 (define_insn "*lshrdi3_internal3"
8532 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8533 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8534 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8535 (const_int 0)))
8536 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8537 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8538 "TARGET_64BIT"
8539 "@
8540 srd. %0,%1,%2
8541 srdi. %0,%1,%H2
8542 #
8543 #"
8544 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8545 (set_attr "length" "4,4,8,8")])
8546
8547 (define_split
8548 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8549 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8550 (match_operand:SI 2 "reg_or_cint_operand" ""))
8551 (const_int 0)))
8552 (set (match_operand:DI 0 "gpc_reg_operand" "")
8553 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8554 "TARGET_POWERPC64 && reload_completed"
8555 [(set (match_dup 0)
8556 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8557 (set (match_dup 3)
8558 (compare:CC (match_dup 0)
8559 (const_int 0)))]
8560 "")
8561
8562 (define_expand "ashrdi3"
8563 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8564 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8565 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8566 "WORDS_BIG_ENDIAN"
8567 "
8568 {
8569 if (TARGET_POWERPC64)
8570 ;
8571 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8572 {
8573 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8574 DONE;
8575 }
8576 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8577 && WORDS_BIG_ENDIAN)
8578 {
8579 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8580 DONE;
8581 }
8582 else
8583 FAIL;
8584 }")
8585
8586 (define_insn "*ashrdi3_internal1"
8587 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8588 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8589 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8590 "TARGET_POWERPC64"
8591 "@
8592 srad %0,%1,%2
8593 sradi %0,%1,%H2"
8594 [(set_attr "type" "var_shift_rotate,shift")])
8595
8596 (define_insn "*ashrdi3_internal2"
8597 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8598 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8599 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8600 (const_int 0)))
8601 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8602 "TARGET_64BIT"
8603 "@
8604 srad. %3,%1,%2
8605 sradi. %3,%1,%H2
8606 #
8607 #"
8608 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8609 (set_attr "length" "4,4,8,8")])
8610
8611 (define_split
8612 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8613 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8614 (match_operand:SI 2 "reg_or_cint_operand" ""))
8615 (const_int 0)))
8616 (clobber (match_scratch:DI 3 ""))]
8617 "TARGET_POWERPC64 && reload_completed"
8618 [(set (match_dup 3)
8619 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8620 (set (match_dup 0)
8621 (compare:CC (match_dup 3)
8622 (const_int 0)))]
8623 "")
8624
8625 (define_insn "*ashrdi3_internal3"
8626 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8627 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8628 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8629 (const_int 0)))
8630 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8631 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8632 "TARGET_64BIT"
8633 "@
8634 srad. %0,%1,%2
8635 sradi. %0,%1,%H2
8636 #
8637 #"
8638 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8639 (set_attr "length" "4,4,8,8")])
8640
8641 (define_split
8642 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8643 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8644 (match_operand:SI 2 "reg_or_cint_operand" ""))
8645 (const_int 0)))
8646 (set (match_operand:DI 0 "gpc_reg_operand" "")
8647 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8648 "TARGET_POWERPC64 && reload_completed"
8649 [(set (match_dup 0)
8650 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8651 (set (match_dup 3)
8652 (compare:CC (match_dup 0)
8653 (const_int 0)))]
8654 "")
8655
8656 (define_expand "anddi3"
8657 [(parallel
8658 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8659 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8660 (match_operand:DI 2 "and64_2_operand" "")))
8661 (clobber (match_scratch:CC 3 ""))])]
8662 "TARGET_POWERPC64"
8663 "")
8664
8665 (define_insn "anddi3_mc"
8666 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8667 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8668 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8669 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8670 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8671 "@
8672 and %0,%1,%2
8673 rldic%B2 %0,%1,0,%S2
8674 rlwinm %0,%1,0,%m2,%M2
8675 andi. %0,%1,%b2
8676 andis. %0,%1,%u2
8677 #"
8678 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8679 (set_attr "length" "4,4,4,4,4,8")])
8680
8681 (define_insn "anddi3_nomc"
8682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8683 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8684 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8685 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8686 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8687 "@
8688 and %0,%1,%2
8689 rldic%B2 %0,%1,0,%S2
8690 rlwinm %0,%1,0,%m2,%M2
8691 #"
8692 [(set_attr "length" "4,4,4,8")])
8693
8694 (define_split
8695 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8696 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8697 (match_operand:DI 2 "mask64_2_operand" "")))
8698 (clobber (match_scratch:CC 3 ""))]
8699 "TARGET_POWERPC64
8700 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8701 && !mask_operand (operands[2], DImode)
8702 && !mask64_operand (operands[2], DImode)"
8703 [(set (match_dup 0)
8704 (and:DI (rotate:DI (match_dup 1)
8705 (match_dup 4))
8706 (match_dup 5)))
8707 (set (match_dup 0)
8708 (and:DI (rotate:DI (match_dup 0)
8709 (match_dup 6))
8710 (match_dup 7)))]
8711 {
8712 build_mask64_2_operands (operands[2], &operands[4]);
8713 })
8714
8715 (define_insn "*anddi3_internal2_mc"
8716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8717 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8718 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8719 (const_int 0)))
8720 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8721 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8722 "TARGET_64BIT && rs6000_gen_cell_microcode"
8723 "@
8724 and. %3,%1,%2
8725 rldic%B2. %3,%1,0,%S2
8726 rlwinm. %3,%1,0,%m2,%M2
8727 andi. %3,%1,%b2
8728 andis. %3,%1,%u2
8729 #
8730 #
8731 #
8732 #
8733 #
8734 #
8735 #"
8736 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8737 fast_compare,compare,compare,compare,compare,compare,\
8738 compare,compare")
8739 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8740
8741 (define_split
8742 [(set (match_operand:CC 0 "cc_reg_operand" "")
8743 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8744 (match_operand:DI 2 "mask64_2_operand" ""))
8745 (const_int 0)))
8746 (clobber (match_scratch:DI 3 ""))
8747 (clobber (match_scratch:CC 4 ""))]
8748 "TARGET_64BIT && reload_completed
8749 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8750 && !mask_operand (operands[2], DImode)
8751 && !mask64_operand (operands[2], DImode)"
8752 [(set (match_dup 3)
8753 (and:DI (rotate:DI (match_dup 1)
8754 (match_dup 5))
8755 (match_dup 6)))
8756 (parallel [(set (match_dup 0)
8757 (compare:CC (and:DI (rotate:DI (match_dup 3)
8758 (match_dup 7))
8759 (match_dup 8))
8760 (const_int 0)))
8761 (clobber (match_dup 3))])]
8762 "
8763 {
8764 build_mask64_2_operands (operands[2], &operands[5]);
8765 }")
8766
8767 (define_insn "*anddi3_internal3_mc"
8768 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8769 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8770 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8771 (const_int 0)))
8772 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8773 (and:DI (match_dup 1) (match_dup 2)))
8774 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8775 "TARGET_64BIT && rs6000_gen_cell_microcode"
8776 "@
8777 and. %0,%1,%2
8778 rldic%B2. %0,%1,0,%S2
8779 rlwinm. %0,%1,0,%m2,%M2
8780 andi. %0,%1,%b2
8781 andis. %0,%1,%u2
8782 #
8783 #
8784 #
8785 #
8786 #
8787 #
8788 #"
8789 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8790 fast_compare,compare,compare,compare,compare,compare,\
8791 compare,compare")
8792 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8793
8794 (define_split
8795 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8796 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8797 (match_operand:DI 2 "and64_2_operand" ""))
8798 (const_int 0)))
8799 (set (match_operand:DI 0 "gpc_reg_operand" "")
8800 (and:DI (match_dup 1) (match_dup 2)))
8801 (clobber (match_scratch:CC 4 ""))]
8802 "TARGET_64BIT && reload_completed"
8803 [(parallel [(set (match_dup 0)
8804 (and:DI (match_dup 1) (match_dup 2)))
8805 (clobber (match_dup 4))])
8806 (set (match_dup 3)
8807 (compare:CC (match_dup 0)
8808 (const_int 0)))]
8809 "")
8810
8811 (define_split
8812 [(set (match_operand:CC 3 "cc_reg_operand" "")
8813 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8814 (match_operand:DI 2 "mask64_2_operand" ""))
8815 (const_int 0)))
8816 (set (match_operand:DI 0 "gpc_reg_operand" "")
8817 (and:DI (match_dup 1) (match_dup 2)))
8818 (clobber (match_scratch:CC 4 ""))]
8819 "TARGET_64BIT && reload_completed
8820 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8821 && !mask_operand (operands[2], DImode)
8822 && !mask64_operand (operands[2], DImode)"
8823 [(set (match_dup 0)
8824 (and:DI (rotate:DI (match_dup 1)
8825 (match_dup 5))
8826 (match_dup 6)))
8827 (parallel [(set (match_dup 3)
8828 (compare:CC (and:DI (rotate:DI (match_dup 0)
8829 (match_dup 7))
8830 (match_dup 8))
8831 (const_int 0)))
8832 (set (match_dup 0)
8833 (and:DI (rotate:DI (match_dup 0)
8834 (match_dup 7))
8835 (match_dup 8)))])]
8836 "
8837 {
8838 build_mask64_2_operands (operands[2], &operands[5]);
8839 }")
8840
8841 (define_expand "iordi3"
8842 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8843 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8844 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8845 "TARGET_POWERPC64"
8846 "
8847 {
8848 if (non_logical_cint_operand (operands[2], DImode))
8849 {
8850 HOST_WIDE_INT value;
8851 rtx tmp = ((!can_create_pseudo_p ()
8852 || rtx_equal_p (operands[0], operands[1]))
8853 ? operands[0] : gen_reg_rtx (DImode));
8854
8855 if (GET_CODE (operands[2]) == CONST_INT)
8856 {
8857 value = INTVAL (operands[2]);
8858 emit_insn (gen_iordi3 (tmp, operands[1],
8859 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8860 }
8861 else
8862 {
8863 value = CONST_DOUBLE_LOW (operands[2]);
8864 emit_insn (gen_iordi3 (tmp, operands[1],
8865 immed_double_const (value
8866 & (~ (HOST_WIDE_INT) 0xffff),
8867 0, DImode)));
8868 }
8869
8870 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8871 DONE;
8872 }
8873 }")
8874
8875 (define_expand "xordi3"
8876 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8877 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8878 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8879 "TARGET_POWERPC64"
8880 "
8881 {
8882 if (non_logical_cint_operand (operands[2], DImode))
8883 {
8884 HOST_WIDE_INT value;
8885 rtx tmp = ((!can_create_pseudo_p ()
8886 || rtx_equal_p (operands[0], operands[1]))
8887 ? operands[0] : gen_reg_rtx (DImode));
8888
8889 if (GET_CODE (operands[2]) == CONST_INT)
8890 {
8891 value = INTVAL (operands[2]);
8892 emit_insn (gen_xordi3 (tmp, operands[1],
8893 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8894 }
8895 else
8896 {
8897 value = CONST_DOUBLE_LOW (operands[2]);
8898 emit_insn (gen_xordi3 (tmp, operands[1],
8899 immed_double_const (value
8900 & (~ (HOST_WIDE_INT) 0xffff),
8901 0, DImode)));
8902 }
8903
8904 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8905 DONE;
8906 }
8907 }")
8908
8909 (define_insn "*booldi3_internal1"
8910 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8911 (match_operator:DI 3 "boolean_or_operator"
8912 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8913 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8914 "TARGET_POWERPC64"
8915 "@
8916 %q3 %0,%1,%2
8917 %q3i %0,%1,%b2
8918 %q3is %0,%1,%u2")
8919
8920 (define_insn "*booldi3_internal2"
8921 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8922 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8923 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8924 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8925 (const_int 0)))
8926 (clobber (match_scratch:DI 3 "=r,r"))]
8927 "TARGET_64BIT"
8928 "@
8929 %q4. %3,%1,%2
8930 #"
8931 [(set_attr "type" "fast_compare,compare")
8932 (set_attr "length" "4,8")])
8933
8934 (define_split
8935 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8936 (compare:CC (match_operator:DI 4 "boolean_operator"
8937 [(match_operand:DI 1 "gpc_reg_operand" "")
8938 (match_operand:DI 2 "gpc_reg_operand" "")])
8939 (const_int 0)))
8940 (clobber (match_scratch:DI 3 ""))]
8941 "TARGET_POWERPC64 && reload_completed"
8942 [(set (match_dup 3) (match_dup 4))
8943 (set (match_dup 0)
8944 (compare:CC (match_dup 3)
8945 (const_int 0)))]
8946 "")
8947
8948 (define_insn "*booldi3_internal3"
8949 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8950 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8951 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8952 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8953 (const_int 0)))
8954 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8955 (match_dup 4))]
8956 "TARGET_64BIT"
8957 "@
8958 %q4. %0,%1,%2
8959 #"
8960 [(set_attr "type" "fast_compare,compare")
8961 (set_attr "length" "4,8")])
8962
8963 (define_split
8964 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8965 (compare:CC (match_operator:DI 4 "boolean_operator"
8966 [(match_operand:DI 1 "gpc_reg_operand" "")
8967 (match_operand:DI 2 "gpc_reg_operand" "")])
8968 (const_int 0)))
8969 (set (match_operand:DI 0 "gpc_reg_operand" "")
8970 (match_dup 4))]
8971 "TARGET_POWERPC64 && reload_completed"
8972 [(set (match_dup 0) (match_dup 4))
8973 (set (match_dup 3)
8974 (compare:CC (match_dup 0)
8975 (const_int 0)))]
8976 "")
8977
8978 ;; Split a logical operation that we can't do in one insn into two insns,
8979 ;; each of which does one 16-bit part. This is used by combine.
8980
8981 (define_split
8982 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8983 (match_operator:DI 3 "boolean_or_operator"
8984 [(match_operand:DI 1 "gpc_reg_operand" "")
8985 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8986 "TARGET_POWERPC64"
8987 [(set (match_dup 0) (match_dup 4))
8988 (set (match_dup 0) (match_dup 5))]
8989 "
8990 {
8991 rtx i3,i4;
8992
8993 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8994 {
8995 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8996 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8997 0, DImode);
8998 i4 = GEN_INT (value & 0xffff);
8999 }
9000 else
9001 {
9002 i3 = GEN_INT (INTVAL (operands[2])
9003 & (~ (HOST_WIDE_INT) 0xffff));
9004 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9005 }
9006 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
9007 operands[1], i3);
9008 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
9009 operands[0], i4);
9010 }")
9011
9012 (define_insn "*boolcdi3_internal1"
9013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9014 (match_operator:DI 3 "boolean_operator"
9015 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9016 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
9017 "TARGET_POWERPC64"
9018 "%q3 %0,%2,%1")
9019
9020 (define_insn "*boolcdi3_internal2"
9021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9022 (compare:CC (match_operator:DI 4 "boolean_operator"
9023 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9024 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9025 (const_int 0)))
9026 (clobber (match_scratch:DI 3 "=r,r"))]
9027 "TARGET_64BIT"
9028 "@
9029 %q4. %3,%2,%1
9030 #"
9031 [(set_attr "type" "fast_compare,compare")
9032 (set_attr "length" "4,8")])
9033
9034 (define_split
9035 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9036 (compare:CC (match_operator:DI 4 "boolean_operator"
9037 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9038 (match_operand:DI 2 "gpc_reg_operand" "")])
9039 (const_int 0)))
9040 (clobber (match_scratch:DI 3 ""))]
9041 "TARGET_POWERPC64 && reload_completed"
9042 [(set (match_dup 3) (match_dup 4))
9043 (set (match_dup 0)
9044 (compare:CC (match_dup 3)
9045 (const_int 0)))]
9046 "")
9047
9048 (define_insn "*boolcdi3_internal3"
9049 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9050 (compare:CC (match_operator:DI 4 "boolean_operator"
9051 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9052 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9053 (const_int 0)))
9054 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9055 (match_dup 4))]
9056 "TARGET_64BIT"
9057 "@
9058 %q4. %0,%2,%1
9059 #"
9060 [(set_attr "type" "fast_compare,compare")
9061 (set_attr "length" "4,8")])
9062
9063 (define_split
9064 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9065 (compare:CC (match_operator:DI 4 "boolean_operator"
9066 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9067 (match_operand:DI 2 "gpc_reg_operand" "")])
9068 (const_int 0)))
9069 (set (match_operand:DI 0 "gpc_reg_operand" "")
9070 (match_dup 4))]
9071 "TARGET_POWERPC64 && reload_completed"
9072 [(set (match_dup 0) (match_dup 4))
9073 (set (match_dup 3)
9074 (compare:CC (match_dup 0)
9075 (const_int 0)))]
9076 "")
9077
9078 (define_insn "*boolccdi3_internal1"
9079 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9080 (match_operator:DI 3 "boolean_operator"
9081 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9082 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
9083 "TARGET_POWERPC64"
9084 "%q3 %0,%1,%2")
9085
9086 (define_insn "*boolccdi3_internal2"
9087 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9088 (compare:CC (match_operator:DI 4 "boolean_operator"
9089 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9090 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9091 (const_int 0)))
9092 (clobber (match_scratch:DI 3 "=r,r"))]
9093 "TARGET_64BIT"
9094 "@
9095 %q4. %3,%1,%2
9096 #"
9097 [(set_attr "type" "fast_compare,compare")
9098 (set_attr "length" "4,8")])
9099
9100 (define_split
9101 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9102 (compare:CC (match_operator:DI 4 "boolean_operator"
9103 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9104 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9105 (const_int 0)))
9106 (clobber (match_scratch:DI 3 ""))]
9107 "TARGET_POWERPC64 && reload_completed"
9108 [(set (match_dup 3) (match_dup 4))
9109 (set (match_dup 0)
9110 (compare:CC (match_dup 3)
9111 (const_int 0)))]
9112 "")
9113
9114 (define_insn "*boolccdi3_internal3"
9115 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9116 (compare:CC (match_operator:DI 4 "boolean_operator"
9117 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9118 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9119 (const_int 0)))
9120 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9121 (match_dup 4))]
9122 "TARGET_64BIT"
9123 "@
9124 %q4. %0,%1,%2
9125 #"
9126 [(set_attr "type" "fast_compare,compare")
9127 (set_attr "length" "4,8")])
9128
9129 (define_split
9130 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9131 (compare:CC (match_operator:DI 4 "boolean_operator"
9132 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9133 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9134 (const_int 0)))
9135 (set (match_operand:DI 0 "gpc_reg_operand" "")
9136 (match_dup 4))]
9137 "TARGET_POWERPC64 && reload_completed"
9138 [(set (match_dup 0) (match_dup 4))
9139 (set (match_dup 3)
9140 (compare:CC (match_dup 0)
9141 (const_int 0)))]
9142 "")
9143
9144 (define_expand "smindi3"
9145 [(match_operand:DI 0 "gpc_reg_operand" "")
9146 (match_operand:DI 1 "gpc_reg_operand" "")
9147 (match_operand:DI 2 "gpc_reg_operand" "")]
9148 "TARGET_ISEL64"
9149 "
9150 {
9151 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
9152 DONE;
9153 }")
9154
9155 (define_expand "smaxdi3"
9156 [(match_operand:DI 0 "gpc_reg_operand" "")
9157 (match_operand:DI 1 "gpc_reg_operand" "")
9158 (match_operand:DI 2 "gpc_reg_operand" "")]
9159 "TARGET_ISEL64"
9160 "
9161 {
9162 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
9163 DONE;
9164 }")
9165
9166 (define_expand "umindi3"
9167 [(match_operand:DI 0 "gpc_reg_operand" "")
9168 (match_operand:DI 1 "gpc_reg_operand" "")
9169 (match_operand:DI 2 "gpc_reg_operand" "")]
9170 "TARGET_ISEL64"
9171 "
9172 {
9173 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
9174 DONE;
9175 }")
9176
9177 (define_expand "umaxdi3"
9178 [(match_operand:DI 0 "gpc_reg_operand" "")
9179 (match_operand:DI 1 "gpc_reg_operand" "")
9180 (match_operand:DI 2 "gpc_reg_operand" "")]
9181 "TARGET_ISEL64"
9182 "
9183 {
9184 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
9185 DONE;
9186 }")
9187
9188 \f
9189 ;; Now define ways of moving data around.
9190
9191 ;; Set up a register with a value from the GOT table
9192
9193 (define_expand "movsi_got"
9194 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9195 (unspec:SI [(match_operand:SI 1 "got_operand" "")
9196 (match_dup 2)] UNSPEC_MOVSI_GOT))]
9197 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9198 "
9199 {
9200 if (GET_CODE (operands[1]) == CONST)
9201 {
9202 rtx offset = const0_rtx;
9203 HOST_WIDE_INT value;
9204
9205 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
9206 value = INTVAL (offset);
9207 if (value != 0)
9208 {
9209 rtx tmp = (!can_create_pseudo_p ()
9210 ? operands[0]
9211 : gen_reg_rtx (Pmode));
9212 emit_insn (gen_movsi_got (tmp, operands[1]));
9213 emit_insn (gen_addsi3 (operands[0], tmp, offset));
9214 DONE;
9215 }
9216 }
9217
9218 operands[2] = rs6000_got_register (operands[1]);
9219 }")
9220
9221 (define_insn "*movsi_got_internal"
9222 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9223 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9224 (match_operand:SI 2 "gpc_reg_operand" "b")]
9225 UNSPEC_MOVSI_GOT))]
9226 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9227 "{l|lwz} %0,%a1@got(%2)"
9228 [(set_attr "type" "load")])
9229
9230 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
9231 ;; didn't get allocated to a hard register.
9232 (define_split
9233 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9234 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9235 (match_operand:SI 2 "memory_operand" "")]
9236 UNSPEC_MOVSI_GOT))]
9237 "DEFAULT_ABI == ABI_V4
9238 && flag_pic == 1
9239 && (reload_in_progress || reload_completed)"
9240 [(set (match_dup 0) (match_dup 2))
9241 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
9242 UNSPEC_MOVSI_GOT))]
9243 "")
9244
9245 ;; For SI, we special-case integers that can't be loaded in one insn. We
9246 ;; do the load 16-bits at a time. We could do this by loading from memory,
9247 ;; and this is even supposed to be faster, but it is simpler not to get
9248 ;; integers in the TOC.
9249 (define_insn "movsi_low"
9250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9251 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9252 (match_operand 2 "" ""))))]
9253 "TARGET_MACHO && ! TARGET_64BIT"
9254 "{l|lwz} %0,lo16(%2)(%1)"
9255 [(set_attr "type" "load")
9256 (set_attr "length" "4")])
9257
9258 (define_insn "*movsi_internal1"
9259 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
9260 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
9261 "!TARGET_SINGLE_FPU &&
9262 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9263 "@
9264 mr %0,%1
9265 {cal|la} %0,%a1
9266 {l%U1%X1|lwz%U1%X1} %0,%1
9267 {st%U0%X0|stw%U0%X0} %1,%0
9268 {lil|li} %0,%1
9269 {liu|lis} %0,%v1
9270 #
9271 {cal|la} %0,%a1
9272 mf%1 %0
9273 mt%0 %1
9274 mt%0 %1
9275 mt%0 %1
9276 {cror 0,0,0|nop}"
9277 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
9278 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
9279
9280 (define_insn "*movsi_internal1_single"
9281 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
9282 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
9283 "TARGET_SINGLE_FPU &&
9284 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9285 "@
9286 mr %0,%1
9287 {cal|la} %0,%a1
9288 {l%U1%X1|lwz%U1%X1} %0,%1
9289 {st%U0%X0|stw%U0%X0} %1,%0
9290 {lil|li} %0,%1
9291 {liu|lis} %0,%v1
9292 #
9293 {cal|la} %0,%a1
9294 mf%1 %0
9295 mt%0 %1
9296 mt%0 %1
9297 mt%0 %1
9298 {cror 0,0,0|nop}
9299 stfs%U0%X0 %1, %0
9300 lfs%U1%X1 %0, %1"
9301 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
9302 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
9303
9304 ;; Split a load of a large constant into the appropriate two-insn
9305 ;; sequence.
9306
9307 (define_split
9308 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9309 (match_operand:SI 1 "const_int_operand" ""))]
9310 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
9311 && (INTVAL (operands[1]) & 0xffff) != 0"
9312 [(set (match_dup 0)
9313 (match_dup 2))
9314 (set (match_dup 0)
9315 (ior:SI (match_dup 0)
9316 (match_dup 3)))]
9317 "
9318 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
9319
9320 if (tem == operands[0])
9321 DONE;
9322 else
9323 FAIL;
9324 }")
9325
9326 (define_insn "*mov<mode>_internal2"
9327 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
9328 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
9329 (const_int 0)))
9330 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
9331 ""
9332 "@
9333 {cmpi|cmp<wd>i} %2,%0,0
9334 mr. %0,%1
9335 #"
9336 [(set_attr "type" "cmp,compare,cmp")
9337 (set_attr "length" "4,4,8")])
9338
9339 (define_split
9340 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9341 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9342 (const_int 0)))
9343 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
9344 "reload_completed"
9345 [(set (match_dup 0) (match_dup 1))
9346 (set (match_dup 2)
9347 (compare:CC (match_dup 0)
9348 (const_int 0)))]
9349 "")
9350 \f
9351 (define_insn "*movhi_internal"
9352 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9353 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9354 "gpc_reg_operand (operands[0], HImode)
9355 || gpc_reg_operand (operands[1], HImode)"
9356 "@
9357 mr %0,%1
9358 lhz%U1%X1 %0,%1
9359 sth%U0%X0 %1,%0
9360 {lil|li} %0,%w1
9361 mf%1 %0
9362 mt%0 %1
9363 mt%0 %1
9364 {cror 0,0,0|nop}"
9365 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9366
9367 (define_expand "mov<mode>"
9368 [(set (match_operand:INT 0 "general_operand" "")
9369 (match_operand:INT 1 "any_operand" ""))]
9370 ""
9371 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9372
9373 (define_insn "*movqi_internal"
9374 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9375 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9376 "gpc_reg_operand (operands[0], QImode)
9377 || gpc_reg_operand (operands[1], QImode)"
9378 "@
9379 mr %0,%1
9380 lbz%U1%X1 %0,%1
9381 stb%U0%X0 %1,%0
9382 {lil|li} %0,%1
9383 mf%1 %0
9384 mt%0 %1
9385 mt%0 %1
9386 {cror 0,0,0|nop}"
9387 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9388 \f
9389 ;; Here is how to move condition codes around. When we store CC data in
9390 ;; an integer register or memory, we store just the high-order 4 bits.
9391 ;; This lets us not shift in the most common case of CR0.
9392 (define_expand "movcc"
9393 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9394 (match_operand:CC 1 "nonimmediate_operand" ""))]
9395 ""
9396 "")
9397
9398 (define_insn "*movcc_internal1"
9399 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
9400 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
9401 "register_operand (operands[0], CCmode)
9402 || register_operand (operands[1], CCmode)"
9403 "@
9404 mcrf %0,%1
9405 mtcrf 128,%1
9406 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
9407 crxor %0,%0,%0
9408 mfcr %0%Q1
9409 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
9410 mr %0,%1
9411 {lil|li} %0,%1
9412 mf%1 %0
9413 mt%0 %1
9414 mt%0 %1
9415 {l%U1%X1|lwz%U1%X1} %0,%1
9416 {st%U0%U1|stw%U0%U1} %1,%0"
9417 [(set (attr "type")
9418 (cond [(eq_attr "alternative" "0,3")
9419 (const_string "cr_logical")
9420 (eq_attr "alternative" "1,2")
9421 (const_string "mtcr")
9422 (eq_attr "alternative" "6,7,9")
9423 (const_string "integer")
9424 (eq_attr "alternative" "8")
9425 (const_string "mfjmpr")
9426 (eq_attr "alternative" "10")
9427 (const_string "mtjmpr")
9428 (eq_attr "alternative" "11")
9429 (const_string "load")
9430 (eq_attr "alternative" "12")
9431 (const_string "store")
9432 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
9433 (const_string "mfcrf")
9434 ]
9435 (const_string "mfcr")))
9436 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
9437 \f
9438 ;; For floating-point, we normally deal with the floating-point registers
9439 ;; unless -msoft-float is used. The sole exception is that parameter passing
9440 ;; can produce floating-point values in fixed-point registers. Unless the
9441 ;; value is a simple constant or already in memory, we deal with this by
9442 ;; allocating memory and copying the value explicitly via that memory location.
9443 (define_expand "movsf"
9444 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9445 (match_operand:SF 1 "any_operand" ""))]
9446 ""
9447 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
9448
9449 (define_split
9450 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9451 (match_operand:SF 1 "const_double_operand" ""))]
9452 "reload_completed
9453 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9454 || (GET_CODE (operands[0]) == SUBREG
9455 && GET_CODE (SUBREG_REG (operands[0])) == REG
9456 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9457 [(set (match_dup 2) (match_dup 3))]
9458 "
9459 {
9460 long l;
9461 REAL_VALUE_TYPE rv;
9462
9463 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9464 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9465
9466 if (! TARGET_POWERPC64)
9467 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9468 else
9469 operands[2] = gen_lowpart (SImode, operands[0]);
9470
9471 operands[3] = gen_int_mode (l, SImode);
9472 }")
9473
9474 (define_insn "*movsf_hardfloat"
9475 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9476 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9477 "(gpc_reg_operand (operands[0], SFmode)
9478 || gpc_reg_operand (operands[1], SFmode))
9479 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9480 "@
9481 mr %0,%1
9482 {l%U1%X1|lwz%U1%X1} %0,%1
9483 {st%U0%X0|stw%U0%X0} %1,%0
9484 fmr %0,%1
9485 lfs%U1%X1 %0,%1
9486 stfs%U0%X0 %1,%0
9487 mt%0 %1
9488 mt%0 %1
9489 mf%1 %0
9490 {cror 0,0,0|nop}
9491 #
9492 #"
9493 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9494 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9495
9496 (define_insn "*movsf_softfloat"
9497 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9498 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9499 "(gpc_reg_operand (operands[0], SFmode)
9500 || gpc_reg_operand (operands[1], SFmode))
9501 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9502 "@
9503 mr %0,%1
9504 mt%0 %1
9505 mt%0 %1
9506 mf%1 %0
9507 {l%U1%X1|lwz%U1%X1} %0,%1
9508 {st%U0%X0|stw%U0%X0} %1,%0
9509 {lil|li} %0,%1
9510 {liu|lis} %0,%v1
9511 {cal|la} %0,%a1
9512 #
9513 #
9514 {cror 0,0,0|nop}"
9515 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9516 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9517
9518 \f
9519 (define_expand "movdf"
9520 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9521 (match_operand:DF 1 "any_operand" ""))]
9522 ""
9523 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9524
9525 (define_split
9526 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9527 (match_operand:DF 1 "const_int_operand" ""))]
9528 "! TARGET_POWERPC64 && reload_completed
9529 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9530 || (GET_CODE (operands[0]) == SUBREG
9531 && GET_CODE (SUBREG_REG (operands[0])) == REG
9532 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9533 [(set (match_dup 2) (match_dup 4))
9534 (set (match_dup 3) (match_dup 1))]
9535 "
9536 {
9537 int endian = (WORDS_BIG_ENDIAN == 0);
9538 HOST_WIDE_INT value = INTVAL (operands[1]);
9539
9540 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9541 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9542 #if HOST_BITS_PER_WIDE_INT == 32
9543 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9544 #else
9545 operands[4] = GEN_INT (value >> 32);
9546 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9547 #endif
9548 }")
9549
9550 (define_split
9551 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9552 (match_operand:DF 1 "const_double_operand" ""))]
9553 "! TARGET_POWERPC64 && reload_completed
9554 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9555 || (GET_CODE (operands[0]) == SUBREG
9556 && GET_CODE (SUBREG_REG (operands[0])) == REG
9557 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9558 [(set (match_dup 2) (match_dup 4))
9559 (set (match_dup 3) (match_dup 5))]
9560 "
9561 {
9562 int endian = (WORDS_BIG_ENDIAN == 0);
9563 long l[2];
9564 REAL_VALUE_TYPE rv;
9565
9566 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9567 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9568
9569 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9570 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9571 operands[4] = gen_int_mode (l[endian], SImode);
9572 operands[5] = gen_int_mode (l[1 - endian], SImode);
9573 }")
9574
9575 (define_split
9576 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9577 (match_operand:DF 1 "const_double_operand" ""))]
9578 "TARGET_POWERPC64 && reload_completed
9579 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9580 || (GET_CODE (operands[0]) == SUBREG
9581 && GET_CODE (SUBREG_REG (operands[0])) == REG
9582 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9583 [(set (match_dup 2) (match_dup 3))]
9584 "
9585 {
9586 int endian = (WORDS_BIG_ENDIAN == 0);
9587 long l[2];
9588 REAL_VALUE_TYPE rv;
9589 #if HOST_BITS_PER_WIDE_INT >= 64
9590 HOST_WIDE_INT val;
9591 #endif
9592
9593 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9594 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9595
9596 operands[2] = gen_lowpart (DImode, operands[0]);
9597 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9598 #if HOST_BITS_PER_WIDE_INT >= 64
9599 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9600 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9601
9602 operands[3] = gen_int_mode (val, DImode);
9603 #else
9604 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9605 #endif
9606 }")
9607
9608 ;; Don't have reload use general registers to load a constant. First,
9609 ;; it might not work if the output operand is the equivalent of
9610 ;; a non-offsettable memref, but also it is less efficient than loading
9611 ;; the constant into an FP register, since it will probably be used there.
9612 ;; The "??" is a kludge until we can figure out a more reasonable way
9613 ;; of handling these non-offsettable values.
9614 (define_insn "*movdf_hardfloat32"
9615 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9616 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9617 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9618 && (gpc_reg_operand (operands[0], DFmode)
9619 || gpc_reg_operand (operands[1], DFmode))"
9620 "*
9621 {
9622 switch (which_alternative)
9623 {
9624 default:
9625 gcc_unreachable ();
9626 case 0:
9627 case 1:
9628 case 2:
9629 return \"#\";
9630 case 3:
9631 case 4:
9632 return \"xxlor %x0,%x1,%x1\";
9633 case 5:
9634 case 6:
9635 return \"lxsd%U1x %x0,%y1\";
9636 case 7:
9637 case 8:
9638 return \"stxsd%U0x %x1,%y0\";
9639 case 9:
9640 return \"fmr %0,%1\";
9641 case 10:
9642 return \"lfd%U1%X1 %0,%1\";
9643 case 11:
9644 return \"stfd%U0%X0 %1,%0\";
9645 case 12:
9646 return \"xxlxor %x0,%x0,%x0\";
9647 case 13:
9648 case 14:
9649 case 15:
9650 return \"#\";
9651 }
9652 }"
9653 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9654 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9655
9656 (define_insn "*movdf_softfloat32"
9657 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9658 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9659 "! TARGET_POWERPC64
9660 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9661 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9662 && (gpc_reg_operand (operands[0], DFmode)
9663 || gpc_reg_operand (operands[1], DFmode))"
9664 "#"
9665 [(set_attr "type" "two,load,store,*,*,*")
9666 (set_attr "length" "8,8,8,8,12,16")])
9667
9668 ;; Reload patterns to support gpr load/store with misaligned mem.
9669 (define_expand "reload_di_store"
9670 [(parallel [(match_operand 0 "memory_operand" "=m")
9671 (match_operand 1 "gpc_reg_operand" "r")
9672 (match_operand:DI 2 "register_operand" "=&b")])]
9673 "TARGET_POWERPC64"
9674 {
9675 rs6000_secondary_reload_ppc64 (operands[1], operands[0], operands[2], true);
9676 DONE;
9677 })
9678
9679 (define_expand "reload_di_load"
9680 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9681 (match_operand 1 "memory_operand" "m")
9682 (match_operand:DI 2 "register_operand" "=b")])]
9683 "TARGET_POWERPC64"
9684 {
9685 rs6000_secondary_reload_ppc64 (operands[0], operands[1], operands[2], false);
9686 DONE;
9687 })
9688
9689 ; ld/std require word-aligned displacements -> 'Y' constraint.
9690 ; List Y->r and r->Y before r->r for reload.
9691 (define_insn "*movdf_hardfloat64_mfpgpr"
9692 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9693 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9694 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9695 && TARGET_DOUBLE_FLOAT
9696 && (gpc_reg_operand (operands[0], DFmode)
9697 || gpc_reg_operand (operands[1], DFmode))"
9698 "@
9699 std%U0%X0 %1,%0
9700 ld%U1%X1 %0,%1
9701 mr %0,%1
9702 xxlor %x0,%x1,%x1
9703 xxlor %x0,%x1,%x1
9704 lxsd%U1x %x0,%y1
9705 lxsd%U1x %x0,%y1
9706 stxsd%U0x %x1,%y0
9707 stxsd%U0x %x1,%y0
9708 fmr %0,%1
9709 lfd%U1%X1 %0,%1
9710 stfd%U0%X0 %1,%0
9711 xxlxor %x0,%x0,%x0
9712 mt%0 %1
9713 mf%1 %0
9714 {cror 0,0,0|nop}
9715 #
9716 #
9717 #
9718 mftgpr %0,%1
9719 mffgpr %0,%1"
9720 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9721 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9722
9723 ; ld/std require word-aligned displacements -> 'Y' constraint.
9724 ; List Y->r and r->Y before r->r for reload.
9725 (define_insn "*movdf_hardfloat64"
9726 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9727 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9728 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9729 && TARGET_DOUBLE_FLOAT
9730 && (gpc_reg_operand (operands[0], DFmode)
9731 || gpc_reg_operand (operands[1], DFmode))"
9732 "@
9733 std%U0%X0 %1,%0
9734 ld%U1%X1 %0,%1
9735 mr %0,%1
9736 xxlor %x0,%x1,%x1
9737 xxlor %x0,%x1,%x1
9738 lxsd%U1x %x0,%y1
9739 lxsd%U1x %x0,%y1
9740 stxsd%U0x %x1,%y0
9741 stxsd%U0x %x1,%y0
9742 fmr %0,%1
9743 lfd%U1%X1 %0,%1
9744 stfd%U0%X0 %1,%0
9745 xxlxor %x0,%x0,%x0
9746 mt%0 %1
9747 mf%1 %0
9748 {cror 0,0,0|nop}
9749 #
9750 #
9751 #"
9752 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9753 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9754
9755 (define_insn "*movdf_softfloat64"
9756 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9757 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9758 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9759 && (gpc_reg_operand (operands[0], DFmode)
9760 || gpc_reg_operand (operands[1], DFmode))"
9761 "@
9762 ld%U1%X1 %0,%1
9763 std%U0%X0 %1,%0
9764 mr %0,%1
9765 mt%0 %1
9766 mf%1 %0
9767 #
9768 #
9769 #
9770 {cror 0,0,0|nop}"
9771 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9772 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9773 \f
9774 (define_expand "movtf"
9775 [(set (match_operand:TF 0 "general_operand" "")
9776 (match_operand:TF 1 "any_operand" ""))]
9777 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9778 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9779
9780 ; It's important to list the o->f and f->o moves before f->f because
9781 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9782 ; which doesn't make progress. Likewise r->Y must be before r->r.
9783 (define_insn_and_split "*movtf_internal"
9784 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9785 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9786 "!TARGET_IEEEQUAD
9787 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9788 && (gpc_reg_operand (operands[0], TFmode)
9789 || gpc_reg_operand (operands[1], TFmode))"
9790 "#"
9791 "&& reload_completed"
9792 [(pc)]
9793 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9794 [(set_attr "length" "8,8,8,20,20,16")])
9795
9796 (define_insn_and_split "*movtf_softfloat"
9797 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9798 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9799 "!TARGET_IEEEQUAD
9800 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9801 && (gpc_reg_operand (operands[0], TFmode)
9802 || gpc_reg_operand (operands[1], TFmode))"
9803 "#"
9804 "&& reload_completed"
9805 [(pc)]
9806 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9807 [(set_attr "length" "20,20,16")])
9808
9809 (define_expand "extenddftf2"
9810 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9811 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9812 "!TARGET_IEEEQUAD
9813 && TARGET_HARD_FLOAT
9814 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9815 && TARGET_LONG_DOUBLE_128"
9816 {
9817 if (TARGET_E500_DOUBLE)
9818 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9819 else
9820 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9821 DONE;
9822 })
9823
9824 (define_expand "extenddftf2_fprs"
9825 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9826 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9827 (use (match_dup 2))])]
9828 "!TARGET_IEEEQUAD
9829 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9830 && TARGET_LONG_DOUBLE_128"
9831 {
9832 operands[2] = CONST0_RTX (DFmode);
9833 /* Generate GOT reference early for SVR4 PIC. */
9834 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9835 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9836 })
9837
9838 (define_insn_and_split "*extenddftf2_internal"
9839 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9840 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9841 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9842 "!TARGET_IEEEQUAD
9843 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9844 && TARGET_LONG_DOUBLE_128"
9845 "#"
9846 "&& reload_completed"
9847 [(pc)]
9848 {
9849 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9850 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9851 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9852 operands[1]);
9853 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9854 operands[2]);
9855 DONE;
9856 })
9857
9858 (define_expand "extendsftf2"
9859 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9860 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9861 "!TARGET_IEEEQUAD
9862 && TARGET_HARD_FLOAT
9863 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9864 && TARGET_LONG_DOUBLE_128"
9865 {
9866 rtx tmp = gen_reg_rtx (DFmode);
9867 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9868 emit_insn (gen_extenddftf2 (operands[0], tmp));
9869 DONE;
9870 })
9871
9872 (define_expand "trunctfdf2"
9873 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9874 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9875 "!TARGET_IEEEQUAD
9876 && TARGET_HARD_FLOAT
9877 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9878 && TARGET_LONG_DOUBLE_128"
9879 "")
9880
9881 (define_insn_and_split "trunctfdf2_internal1"
9882 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9883 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9884 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9885 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9886 "@
9887 #
9888 fmr %0,%1"
9889 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9890 [(const_int 0)]
9891 {
9892 emit_note (NOTE_INSN_DELETED);
9893 DONE;
9894 }
9895 [(set_attr "type" "fp")])
9896
9897 (define_insn "trunctfdf2_internal2"
9898 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9899 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9900 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9901 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9902 && TARGET_LONG_DOUBLE_128"
9903 "fadd %0,%1,%L1"
9904 [(set_attr "type" "fp")
9905 (set_attr "fp_type" "fp_addsub_d")])
9906
9907 (define_expand "trunctfsf2"
9908 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9909 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9910 "!TARGET_IEEEQUAD
9911 && TARGET_HARD_FLOAT
9912 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9913 && TARGET_LONG_DOUBLE_128"
9914 {
9915 if (TARGET_E500_DOUBLE)
9916 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9917 else
9918 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9919 DONE;
9920 })
9921
9922 (define_insn_and_split "trunctfsf2_fprs"
9923 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9924 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9925 (clobber (match_scratch:DF 2 "=d"))]
9926 "!TARGET_IEEEQUAD
9927 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9928 && TARGET_LONG_DOUBLE_128"
9929 "#"
9930 "&& reload_completed"
9931 [(set (match_dup 2)
9932 (float_truncate:DF (match_dup 1)))
9933 (set (match_dup 0)
9934 (float_truncate:SF (match_dup 2)))]
9935 "")
9936
9937 (define_expand "floatsitf2"
9938 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9939 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9940 "!TARGET_IEEEQUAD
9941 && TARGET_HARD_FLOAT
9942 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9943 && TARGET_LONG_DOUBLE_128"
9944 {
9945 rtx tmp = gen_reg_rtx (DFmode);
9946 expand_float (tmp, operands[1], false);
9947 emit_insn (gen_extenddftf2 (operands[0], tmp));
9948 DONE;
9949 })
9950
9951 ; fadd, but rounding towards zero.
9952 ; This is probably not the optimal code sequence.
9953 (define_insn "fix_trunc_helper"
9954 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9955 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9956 UNSPEC_FIX_TRUNC_TF))
9957 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9958 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9959 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9960 [(set_attr "type" "fp")
9961 (set_attr "length" "20")])
9962
9963 (define_expand "fix_trunctfsi2"
9964 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9965 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9966 "!TARGET_IEEEQUAD
9967 && (TARGET_POWER2 || TARGET_POWERPC)
9968 && TARGET_HARD_FLOAT
9969 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9970 && TARGET_LONG_DOUBLE_128"
9971 {
9972 if (TARGET_E500_DOUBLE)
9973 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9974 else
9975 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9976 DONE;
9977 })
9978
9979 (define_expand "fix_trunctfsi2_fprs"
9980 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9981 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9982 (clobber (match_dup 2))
9983 (clobber (match_dup 3))
9984 (clobber (match_dup 4))
9985 (clobber (match_dup 5))])]
9986 "!TARGET_IEEEQUAD
9987 && (TARGET_POWER2 || TARGET_POWERPC)
9988 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9989 {
9990 operands[2] = gen_reg_rtx (DFmode);
9991 operands[3] = gen_reg_rtx (DFmode);
9992 operands[4] = gen_reg_rtx (DImode);
9993 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9994 })
9995
9996 (define_insn_and_split "*fix_trunctfsi2_internal"
9997 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9998 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9999 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
10000 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
10001 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
10002 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
10003 "!TARGET_IEEEQUAD
10004 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10005 "#"
10006 ""
10007 [(pc)]
10008 {
10009 rtx lowword;
10010 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
10011
10012 gcc_assert (MEM_P (operands[5]));
10013 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
10014
10015 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
10016 emit_move_insn (operands[5], operands[4]);
10017 emit_move_insn (operands[0], lowword);
10018 DONE;
10019 })
10020
10021 (define_expand "negtf2"
10022 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10023 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10024 "!TARGET_IEEEQUAD
10025 && TARGET_HARD_FLOAT
10026 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10027 && TARGET_LONG_DOUBLE_128"
10028 "")
10029
10030 (define_insn "negtf2_internal"
10031 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
10032 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
10033 "!TARGET_IEEEQUAD
10034 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10035 "*
10036 {
10037 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
10038 return \"fneg %L0,%L1\;fneg %0,%1\";
10039 else
10040 return \"fneg %0,%1\;fneg %L0,%L1\";
10041 }"
10042 [(set_attr "type" "fp")
10043 (set_attr "length" "8")])
10044
10045 (define_expand "abstf2"
10046 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10047 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10048 "!TARGET_IEEEQUAD
10049 && TARGET_HARD_FLOAT
10050 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10051 && TARGET_LONG_DOUBLE_128"
10052 "
10053 {
10054 rtx label = gen_label_rtx ();
10055 if (TARGET_E500_DOUBLE)
10056 {
10057 if (flag_finite_math_only && !flag_trapping_math)
10058 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
10059 else
10060 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
10061 }
10062 else
10063 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
10064 emit_label (label);
10065 DONE;
10066 }")
10067
10068 (define_expand "abstf2_internal"
10069 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10070 (match_operand:TF 1 "gpc_reg_operand" ""))
10071 (set (match_dup 3) (match_dup 5))
10072 (set (match_dup 5) (abs:DF (match_dup 5)))
10073 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
10074 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
10075 (label_ref (match_operand 2 "" ""))
10076 (pc)))
10077 (set (match_dup 6) (neg:DF (match_dup 6)))]
10078 "!TARGET_IEEEQUAD
10079 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10080 && TARGET_LONG_DOUBLE_128"
10081 "
10082 {
10083 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10084 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10085 operands[3] = gen_reg_rtx (DFmode);
10086 operands[4] = gen_reg_rtx (CCFPmode);
10087 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
10088 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
10089 }")
10090 \f
10091 ;; Next come the multi-word integer load and store and the load and store
10092 ;; multiple insns.
10093
10094 ; List r->r after r->"o<>", otherwise reload will try to reload a
10095 ; non-offsettable address by using r->r which won't make progress.
10096 (define_insn "*movdi_internal32"
10097 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r,?wa")
10098 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF,O"))]
10099 "! TARGET_POWERPC64
10100 && (gpc_reg_operand (operands[0], DImode)
10101 || gpc_reg_operand (operands[1], DImode))"
10102 "@
10103 #
10104 #
10105 #
10106 fmr %0,%1
10107 lfd%U1%X1 %0,%1
10108 stfd%U0%X0 %1,%0
10109 #
10110 xxlxor %x0,%x0,%x0"
10111 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*,vecsimple")])
10112
10113 (define_split
10114 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10115 (match_operand:DI 1 "const_int_operand" ""))]
10116 "! TARGET_POWERPC64 && reload_completed
10117 && gpr_or_gpr_p (operands[0], operands[1])"
10118 [(set (match_dup 2) (match_dup 4))
10119 (set (match_dup 3) (match_dup 1))]
10120 "
10121 {
10122 HOST_WIDE_INT value = INTVAL (operands[1]);
10123 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10124 DImode);
10125 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10126 DImode);
10127 #if HOST_BITS_PER_WIDE_INT == 32
10128 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
10129 #else
10130 operands[4] = GEN_INT (value >> 32);
10131 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10132 #endif
10133 }")
10134
10135 (define_split
10136 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10137 (match_operand:DIFD 1 "input_operand" ""))]
10138 "reload_completed && !TARGET_POWERPC64
10139 && gpr_or_gpr_p (operands[0], operands[1])"
10140 [(pc)]
10141 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10142
10143 (define_insn "*movdi_mfpgpr"
10144 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
10145 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
10146 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
10147 && (gpc_reg_operand (operands[0], DImode)
10148 || gpc_reg_operand (operands[1], DImode))"
10149 "@
10150 mr %0,%1
10151 ld%U1%X1 %0,%1
10152 std%U0%X0 %1,%0
10153 li %0,%1
10154 lis %0,%v1
10155 #
10156 la %0,%a1
10157 fmr %0,%1
10158 lfd%U1%X1 %0,%1
10159 stfd%U0%X0 %1,%0
10160 mf%1 %0
10161 mt%0 %1
10162 {cror 0,0,0|nop}
10163 mftgpr %0,%1
10164 mffgpr %0,%1"
10165 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
10166 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
10167
10168 (define_insn "*movdi_internal64"
10169 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,?wa")
10170 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,O"))]
10171 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
10172 && (gpc_reg_operand (operands[0], DImode)
10173 || gpc_reg_operand (operands[1], DImode))"
10174 "@
10175 mr %0,%1
10176 ld%U1%X1 %0,%1
10177 std%U0%X0 %1,%0
10178 li %0,%1
10179 lis %0,%v1
10180 #
10181 la %0,%a1
10182 fmr %0,%1
10183 lfd%U1%X1 %0,%1
10184 stfd%U0%X0 %1,%0
10185 mf%1 %0
10186 mt%0 %1
10187 {cror 0,0,0|nop}
10188 xxlxor %x0,%x0,%x0"
10189 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,vecsimple")
10190 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
10191
10192 ;; immediate value valid for a single instruction hiding in a const_double
10193 (define_insn ""
10194 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10195 (match_operand:DI 1 "const_double_operand" "F"))]
10196 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
10197 && GET_CODE (operands[1]) == CONST_DOUBLE
10198 && num_insns_constant (operands[1], DImode) == 1"
10199 "*
10200 {
10201 return ((unsigned HOST_WIDE_INT)
10202 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
10203 ? \"li %0,%1\" : \"lis %0,%v1\";
10204 }")
10205
10206 ;; Generate all one-bits and clear left or right.
10207 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10208 (define_split
10209 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10210 (match_operand:DI 1 "mask64_operand" ""))]
10211 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10212 [(set (match_dup 0) (const_int -1))
10213 (set (match_dup 0)
10214 (and:DI (rotate:DI (match_dup 0)
10215 (const_int 0))
10216 (match_dup 1)))]
10217 "")
10218
10219 ;; Split a load of a large constant into the appropriate five-instruction
10220 ;; sequence. Handle anything in a constant number of insns.
10221 ;; When non-easy constants can go in the TOC, this should use
10222 ;; easy_fp_constant predicate.
10223 (define_split
10224 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10225 (match_operand:DI 1 "const_int_operand" ""))]
10226 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10227 [(set (match_dup 0) (match_dup 2))
10228 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10229 "
10230 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10231
10232 if (tem == operands[0])
10233 DONE;
10234 else
10235 FAIL;
10236 }")
10237
10238 (define_split
10239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10240 (match_operand:DI 1 "const_double_operand" ""))]
10241 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10242 [(set (match_dup 0) (match_dup 2))
10243 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10244 "
10245 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10246
10247 if (tem == operands[0])
10248 DONE;
10249 else
10250 FAIL;
10251 }")
10252 \f
10253 ;; TImode is similar, except that we usually want to compute the address into
10254 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
10255 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
10256
10257 ;; We say that MQ is clobbered in the last alternative because the first
10258 ;; alternative would never get used otherwise since it would need a reload
10259 ;; while the 2nd alternative would not. We put memory cases first so they
10260 ;; are preferred. Otherwise, we'd try to reload the output instead of
10261 ;; giving the SCRATCH mq.
10262
10263 (define_insn "*movti_power"
10264 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
10265 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
10266 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
10267 "TARGET_POWER && ! TARGET_POWERPC64
10268 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10269 "*
10270 {
10271 switch (which_alternative)
10272 {
10273 default:
10274 gcc_unreachable ();
10275
10276 case 0:
10277 if (TARGET_STRING)
10278 return \"{stsi|stswi} %1,%P0,16\";
10279 case 1:
10280 case 2:
10281 return \"#\";
10282 case 3:
10283 /* If the address is not used in the output, we can use lsi. Otherwise,
10284 fall through to generating four loads. */
10285 if (TARGET_STRING
10286 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10287 return \"{lsi|lswi} %0,%P1,16\";
10288 /* ... fall through ... */
10289 case 4:
10290 case 5:
10291 return \"#\";
10292 }
10293 }"
10294 [(set_attr "type" "store,store,*,load,load,*")])
10295
10296 (define_insn "*movti_string"
10297 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
10298 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
10299 "! TARGET_POWER && ! TARGET_POWERPC64
10300 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10301 "*
10302 {
10303 switch (which_alternative)
10304 {
10305 default:
10306 gcc_unreachable ();
10307 case 0:
10308 if (TARGET_STRING)
10309 return \"{stsi|stswi} %1,%P0,16\";
10310 case 1:
10311 case 2:
10312 return \"#\";
10313 case 3:
10314 /* If the address is not used in the output, we can use lsi. Otherwise,
10315 fall through to generating four loads. */
10316 if (TARGET_STRING
10317 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10318 return \"{lsi|lswi} %0,%P1,16\";
10319 /* ... fall through ... */
10320 case 4:
10321 case 5:
10322 return \"#\";
10323 }
10324 }"
10325 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
10326 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
10327 (const_string "always")
10328 (const_string "conditional")))])
10329
10330 (define_insn "*movti_ppc64"
10331 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
10332 (match_operand:TI 1 "input_operand" "r,r,m"))]
10333 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
10334 || gpc_reg_operand (operands[1], TImode)))
10335 && VECTOR_MEM_NONE_P (TImode)"
10336 "#"
10337 [(set_attr "type" "*,store,load")])
10338
10339 (define_split
10340 [(set (match_operand:TI 0 "gpc_reg_operand" "")
10341 (match_operand:TI 1 "const_double_operand" ""))]
10342 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
10343 [(set (match_dup 2) (match_dup 4))
10344 (set (match_dup 3) (match_dup 5))]
10345 "
10346 {
10347 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10348 TImode);
10349 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10350 TImode);
10351 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10352 {
10353 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10354 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10355 }
10356 else if (GET_CODE (operands[1]) == CONST_INT)
10357 {
10358 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10359 operands[5] = operands[1];
10360 }
10361 else
10362 FAIL;
10363 }")
10364
10365 (define_split
10366 [(set (match_operand:TI 0 "nonimmediate_operand" "")
10367 (match_operand:TI 1 "input_operand" ""))]
10368 "reload_completed && VECTOR_MEM_NONE_P (TImode)
10369 && gpr_or_gpr_p (operands[0], operands[1])"
10370 [(pc)]
10371 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10372 \f
10373 (define_expand "load_multiple"
10374 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10375 (match_operand:SI 1 "" ""))
10376 (use (match_operand:SI 2 "" ""))])]
10377 "TARGET_STRING && !TARGET_POWERPC64"
10378 "
10379 {
10380 int regno;
10381 int count;
10382 rtx op1;
10383 int i;
10384
10385 /* Support only loading a constant number of fixed-point registers from
10386 memory and only bother with this if more than two; the machine
10387 doesn't support more than eight. */
10388 if (GET_CODE (operands[2]) != CONST_INT
10389 || INTVAL (operands[2]) <= 2
10390 || INTVAL (operands[2]) > 8
10391 || GET_CODE (operands[1]) != MEM
10392 || GET_CODE (operands[0]) != REG
10393 || REGNO (operands[0]) >= 32)
10394 FAIL;
10395
10396 count = INTVAL (operands[2]);
10397 regno = REGNO (operands[0]);
10398
10399 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10400 op1 = replace_equiv_address (operands[1],
10401 force_reg (SImode, XEXP (operands[1], 0)));
10402
10403 for (i = 0; i < count; i++)
10404 XVECEXP (operands[3], 0, i)
10405 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10406 adjust_address_nv (op1, SImode, i * 4));
10407 }")
10408
10409 (define_insn "*ldmsi8"
10410 [(match_parallel 0 "load_multiple_operation"
10411 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10412 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10413 (set (match_operand:SI 3 "gpc_reg_operand" "")
10414 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10415 (set (match_operand:SI 4 "gpc_reg_operand" "")
10416 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10417 (set (match_operand:SI 5 "gpc_reg_operand" "")
10418 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10419 (set (match_operand:SI 6 "gpc_reg_operand" "")
10420 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10421 (set (match_operand:SI 7 "gpc_reg_operand" "")
10422 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10423 (set (match_operand:SI 8 "gpc_reg_operand" "")
10424 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10425 (set (match_operand:SI 9 "gpc_reg_operand" "")
10426 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10427 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10428 "*
10429 { return rs6000_output_load_multiple (operands); }"
10430 [(set_attr "type" "load_ux")
10431 (set_attr "length" "32")])
10432
10433 (define_insn "*ldmsi7"
10434 [(match_parallel 0 "load_multiple_operation"
10435 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10436 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10437 (set (match_operand:SI 3 "gpc_reg_operand" "")
10438 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10439 (set (match_operand:SI 4 "gpc_reg_operand" "")
10440 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10441 (set (match_operand:SI 5 "gpc_reg_operand" "")
10442 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10443 (set (match_operand:SI 6 "gpc_reg_operand" "")
10444 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10445 (set (match_operand:SI 7 "gpc_reg_operand" "")
10446 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10447 (set (match_operand:SI 8 "gpc_reg_operand" "")
10448 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10449 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10450 "*
10451 { return rs6000_output_load_multiple (operands); }"
10452 [(set_attr "type" "load_ux")
10453 (set_attr "length" "32")])
10454
10455 (define_insn "*ldmsi6"
10456 [(match_parallel 0 "load_multiple_operation"
10457 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10458 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10459 (set (match_operand:SI 3 "gpc_reg_operand" "")
10460 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10461 (set (match_operand:SI 4 "gpc_reg_operand" "")
10462 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10463 (set (match_operand:SI 5 "gpc_reg_operand" "")
10464 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10465 (set (match_operand:SI 6 "gpc_reg_operand" "")
10466 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10467 (set (match_operand:SI 7 "gpc_reg_operand" "")
10468 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10469 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10470 "*
10471 { return rs6000_output_load_multiple (operands); }"
10472 [(set_attr "type" "load_ux")
10473 (set_attr "length" "32")])
10474
10475 (define_insn "*ldmsi5"
10476 [(match_parallel 0 "load_multiple_operation"
10477 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10478 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10479 (set (match_operand:SI 3 "gpc_reg_operand" "")
10480 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10481 (set (match_operand:SI 4 "gpc_reg_operand" "")
10482 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10483 (set (match_operand:SI 5 "gpc_reg_operand" "")
10484 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10485 (set (match_operand:SI 6 "gpc_reg_operand" "")
10486 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10487 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10488 "*
10489 { return rs6000_output_load_multiple (operands); }"
10490 [(set_attr "type" "load_ux")
10491 (set_attr "length" "32")])
10492
10493 (define_insn "*ldmsi4"
10494 [(match_parallel 0 "load_multiple_operation"
10495 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10496 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10497 (set (match_operand:SI 3 "gpc_reg_operand" "")
10498 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10499 (set (match_operand:SI 4 "gpc_reg_operand" "")
10500 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10501 (set (match_operand:SI 5 "gpc_reg_operand" "")
10502 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10503 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10504 "*
10505 { return rs6000_output_load_multiple (operands); }"
10506 [(set_attr "type" "load_ux")
10507 (set_attr "length" "32")])
10508
10509 (define_insn "*ldmsi3"
10510 [(match_parallel 0 "load_multiple_operation"
10511 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10512 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10513 (set (match_operand:SI 3 "gpc_reg_operand" "")
10514 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10515 (set (match_operand:SI 4 "gpc_reg_operand" "")
10516 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10517 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10518 "*
10519 { return rs6000_output_load_multiple (operands); }"
10520 [(set_attr "type" "load_ux")
10521 (set_attr "length" "32")])
10522
10523 (define_expand "store_multiple"
10524 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10525 (match_operand:SI 1 "" ""))
10526 (clobber (scratch:SI))
10527 (use (match_operand:SI 2 "" ""))])]
10528 "TARGET_STRING && !TARGET_POWERPC64"
10529 "
10530 {
10531 int regno;
10532 int count;
10533 rtx to;
10534 rtx op0;
10535 int i;
10536
10537 /* Support only storing a constant number of fixed-point registers to
10538 memory and only bother with this if more than two; the machine
10539 doesn't support more than eight. */
10540 if (GET_CODE (operands[2]) != CONST_INT
10541 || INTVAL (operands[2]) <= 2
10542 || INTVAL (operands[2]) > 8
10543 || GET_CODE (operands[0]) != MEM
10544 || GET_CODE (operands[1]) != REG
10545 || REGNO (operands[1]) >= 32)
10546 FAIL;
10547
10548 count = INTVAL (operands[2]);
10549 regno = REGNO (operands[1]);
10550
10551 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10552 to = force_reg (SImode, XEXP (operands[0], 0));
10553 op0 = replace_equiv_address (operands[0], to);
10554
10555 XVECEXP (operands[3], 0, 0)
10556 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10557 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10558 gen_rtx_SCRATCH (SImode));
10559
10560 for (i = 1; i < count; i++)
10561 XVECEXP (operands[3], 0, i + 1)
10562 = gen_rtx_SET (VOIDmode,
10563 adjust_address_nv (op0, SImode, i * 4),
10564 gen_rtx_REG (SImode, regno + i));
10565 }")
10566
10567 (define_insn "*stmsi8"
10568 [(match_parallel 0 "store_multiple_operation"
10569 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10570 (match_operand:SI 2 "gpc_reg_operand" "r"))
10571 (clobber (match_scratch:SI 3 "=X"))
10572 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10573 (match_operand:SI 4 "gpc_reg_operand" "r"))
10574 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10575 (match_operand:SI 5 "gpc_reg_operand" "r"))
10576 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10577 (match_operand:SI 6 "gpc_reg_operand" "r"))
10578 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10579 (match_operand:SI 7 "gpc_reg_operand" "r"))
10580 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10581 (match_operand:SI 8 "gpc_reg_operand" "r"))
10582 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10583 (match_operand:SI 9 "gpc_reg_operand" "r"))
10584 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10585 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10586 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10587 "{stsi|stswi} %2,%1,%O0"
10588 [(set_attr "type" "store_ux")
10589 (set_attr "cell_micro" "always")])
10590
10591 (define_insn "*stmsi7"
10592 [(match_parallel 0 "store_multiple_operation"
10593 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10594 (match_operand:SI 2 "gpc_reg_operand" "r"))
10595 (clobber (match_scratch:SI 3 "=X"))
10596 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10597 (match_operand:SI 4 "gpc_reg_operand" "r"))
10598 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10599 (match_operand:SI 5 "gpc_reg_operand" "r"))
10600 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10601 (match_operand:SI 6 "gpc_reg_operand" "r"))
10602 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10603 (match_operand:SI 7 "gpc_reg_operand" "r"))
10604 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10605 (match_operand:SI 8 "gpc_reg_operand" "r"))
10606 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10607 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10608 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10609 "{stsi|stswi} %2,%1,%O0"
10610 [(set_attr "type" "store_ux")
10611 (set_attr "cell_micro" "always")])
10612
10613 (define_insn "*stmsi6"
10614 [(match_parallel 0 "store_multiple_operation"
10615 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10616 (match_operand:SI 2 "gpc_reg_operand" "r"))
10617 (clobber (match_scratch:SI 3 "=X"))
10618 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10619 (match_operand:SI 4 "gpc_reg_operand" "r"))
10620 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10621 (match_operand:SI 5 "gpc_reg_operand" "r"))
10622 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10623 (match_operand:SI 6 "gpc_reg_operand" "r"))
10624 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10625 (match_operand:SI 7 "gpc_reg_operand" "r"))
10626 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10627 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10628 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10629 "{stsi|stswi} %2,%1,%O0"
10630 [(set_attr "type" "store_ux")
10631 (set_attr "cell_micro" "always")])
10632
10633 (define_insn "*stmsi5"
10634 [(match_parallel 0 "store_multiple_operation"
10635 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10636 (match_operand:SI 2 "gpc_reg_operand" "r"))
10637 (clobber (match_scratch:SI 3 "=X"))
10638 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10639 (match_operand:SI 4 "gpc_reg_operand" "r"))
10640 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10641 (match_operand:SI 5 "gpc_reg_operand" "r"))
10642 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10643 (match_operand:SI 6 "gpc_reg_operand" "r"))
10644 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10645 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10646 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10647 "{stsi|stswi} %2,%1,%O0"
10648 [(set_attr "type" "store_ux")
10649 (set_attr "cell_micro" "always")])
10650
10651 (define_insn "*stmsi4"
10652 [(match_parallel 0 "store_multiple_operation"
10653 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10654 (match_operand:SI 2 "gpc_reg_operand" "r"))
10655 (clobber (match_scratch:SI 3 "=X"))
10656 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10657 (match_operand:SI 4 "gpc_reg_operand" "r"))
10658 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10659 (match_operand:SI 5 "gpc_reg_operand" "r"))
10660 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10661 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10662 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10663 "{stsi|stswi} %2,%1,%O0"
10664 [(set_attr "type" "store_ux")
10665 (set_attr "cell_micro" "always")])
10666
10667 (define_insn "*stmsi3"
10668 [(match_parallel 0 "store_multiple_operation"
10669 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10670 (match_operand:SI 2 "gpc_reg_operand" "r"))
10671 (clobber (match_scratch:SI 3 "=X"))
10672 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10673 (match_operand:SI 4 "gpc_reg_operand" "r"))
10674 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10675 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10676 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10677 "{stsi|stswi} %2,%1,%O0"
10678 [(set_attr "type" "store_ux")
10679 (set_attr "cell_micro" "always")])
10680
10681 (define_insn "*stmsi8_power"
10682 [(match_parallel 0 "store_multiple_operation"
10683 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10684 (match_operand:SI 2 "gpc_reg_operand" "r"))
10685 (clobber (match_scratch:SI 3 "=q"))
10686 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10687 (match_operand:SI 4 "gpc_reg_operand" "r"))
10688 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10689 (match_operand:SI 5 "gpc_reg_operand" "r"))
10690 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10691 (match_operand:SI 6 "gpc_reg_operand" "r"))
10692 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10693 (match_operand:SI 7 "gpc_reg_operand" "r"))
10694 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10695 (match_operand:SI 8 "gpc_reg_operand" "r"))
10696 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10697 (match_operand:SI 9 "gpc_reg_operand" "r"))
10698 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10699 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10700 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10701 "{stsi|stswi} %2,%1,%O0"
10702 [(set_attr "type" "store_ux")
10703 (set_attr "cell_micro" "always")])
10704
10705 (define_insn "*stmsi7_power"
10706 [(match_parallel 0 "store_multiple_operation"
10707 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10708 (match_operand:SI 2 "gpc_reg_operand" "r"))
10709 (clobber (match_scratch:SI 3 "=q"))
10710 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10711 (match_operand:SI 4 "gpc_reg_operand" "r"))
10712 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10713 (match_operand:SI 5 "gpc_reg_operand" "r"))
10714 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10715 (match_operand:SI 6 "gpc_reg_operand" "r"))
10716 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10717 (match_operand:SI 7 "gpc_reg_operand" "r"))
10718 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10719 (match_operand:SI 8 "gpc_reg_operand" "r"))
10720 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10721 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10722 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10723 "{stsi|stswi} %2,%1,%O0"
10724 [(set_attr "type" "store_ux")
10725 (set_attr "cell_micro" "always")])
10726
10727 (define_insn "*stmsi6_power"
10728 [(match_parallel 0 "store_multiple_operation"
10729 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10730 (match_operand:SI 2 "gpc_reg_operand" "r"))
10731 (clobber (match_scratch:SI 3 "=q"))
10732 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10733 (match_operand:SI 4 "gpc_reg_operand" "r"))
10734 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10735 (match_operand:SI 5 "gpc_reg_operand" "r"))
10736 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10737 (match_operand:SI 6 "gpc_reg_operand" "r"))
10738 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10739 (match_operand:SI 7 "gpc_reg_operand" "r"))
10740 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10741 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10742 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10743 "{stsi|stswi} %2,%1,%O0"
10744 [(set_attr "type" "store_ux")
10745 (set_attr "cell_micro" "always")])
10746
10747 (define_insn "*stmsi5_power"
10748 [(match_parallel 0 "store_multiple_operation"
10749 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10750 (match_operand:SI 2 "gpc_reg_operand" "r"))
10751 (clobber (match_scratch:SI 3 "=q"))
10752 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10753 (match_operand:SI 4 "gpc_reg_operand" "r"))
10754 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10755 (match_operand:SI 5 "gpc_reg_operand" "r"))
10756 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10757 (match_operand:SI 6 "gpc_reg_operand" "r"))
10758 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10759 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10760 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10761 "{stsi|stswi} %2,%1,%O0"
10762 [(set_attr "type" "store_ux")
10763 (set_attr "cell_micro" "always")])
10764
10765 (define_insn "*stmsi4_power"
10766 [(match_parallel 0 "store_multiple_operation"
10767 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10768 (match_operand:SI 2 "gpc_reg_operand" "r"))
10769 (clobber (match_scratch:SI 3 "=q"))
10770 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10771 (match_operand:SI 4 "gpc_reg_operand" "r"))
10772 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10773 (match_operand:SI 5 "gpc_reg_operand" "r"))
10774 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10775 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10776 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10777 "{stsi|stswi} %2,%1,%O0"
10778 [(set_attr "type" "store_ux")
10779 (set_attr "cell_micro" "always")])
10780
10781 (define_insn "*stmsi3_power"
10782 [(match_parallel 0 "store_multiple_operation"
10783 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10784 (match_operand:SI 2 "gpc_reg_operand" "r"))
10785 (clobber (match_scratch:SI 3 "=q"))
10786 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10787 (match_operand:SI 4 "gpc_reg_operand" "r"))
10788 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10789 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10790 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10791 "{stsi|stswi} %2,%1,%O0"
10792 [(set_attr "type" "store_ux")
10793 (set_attr "cell_micro" "always")])
10794 \f
10795 (define_expand "setmemsi"
10796 [(parallel [(set (match_operand:BLK 0 "" "")
10797 (match_operand 2 "const_int_operand" ""))
10798 (use (match_operand:SI 1 "" ""))
10799 (use (match_operand:SI 3 "" ""))])]
10800 ""
10801 "
10802 {
10803 /* If value to set is not zero, use the library routine. */
10804 if (operands[2] != const0_rtx)
10805 FAIL;
10806
10807 if (expand_block_clear (operands))
10808 DONE;
10809 else
10810 FAIL;
10811 }")
10812
10813 ;; String/block move insn.
10814 ;; Argument 0 is the destination
10815 ;; Argument 1 is the source
10816 ;; Argument 2 is the length
10817 ;; Argument 3 is the alignment
10818
10819 (define_expand "movmemsi"
10820 [(parallel [(set (match_operand:BLK 0 "" "")
10821 (match_operand:BLK 1 "" ""))
10822 (use (match_operand:SI 2 "" ""))
10823 (use (match_operand:SI 3 "" ""))])]
10824 ""
10825 "
10826 {
10827 if (expand_block_move (operands))
10828 DONE;
10829 else
10830 FAIL;
10831 }")
10832
10833 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10834 ;; register allocator doesn't have a clue about allocating 8 word registers.
10835 ;; rD/rS = r5 is preferred, efficient form.
10836 (define_expand "movmemsi_8reg"
10837 [(parallel [(set (match_operand 0 "" "")
10838 (match_operand 1 "" ""))
10839 (use (match_operand 2 "" ""))
10840 (use (match_operand 3 "" ""))
10841 (clobber (reg:SI 5))
10842 (clobber (reg:SI 6))
10843 (clobber (reg:SI 7))
10844 (clobber (reg:SI 8))
10845 (clobber (reg:SI 9))
10846 (clobber (reg:SI 10))
10847 (clobber (reg:SI 11))
10848 (clobber (reg:SI 12))
10849 (clobber (match_scratch:SI 4 ""))])]
10850 "TARGET_STRING"
10851 "")
10852
10853 (define_insn ""
10854 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10855 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10856 (use (match_operand:SI 2 "immediate_operand" "i"))
10857 (use (match_operand:SI 3 "immediate_operand" "i"))
10858 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10859 (clobber (reg:SI 6))
10860 (clobber (reg:SI 7))
10861 (clobber (reg:SI 8))
10862 (clobber (reg:SI 9))
10863 (clobber (reg:SI 10))
10864 (clobber (reg:SI 11))
10865 (clobber (reg:SI 12))
10866 (clobber (match_scratch:SI 5 "=q"))]
10867 "TARGET_STRING && TARGET_POWER
10868 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10869 || INTVAL (operands[2]) == 0)
10870 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10871 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10872 && REGNO (operands[4]) == 5"
10873 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10874 [(set_attr "type" "store_ux")
10875 (set_attr "cell_micro" "always")
10876 (set_attr "length" "8")])
10877
10878 (define_insn ""
10879 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10880 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10881 (use (match_operand:SI 2 "immediate_operand" "i"))
10882 (use (match_operand:SI 3 "immediate_operand" "i"))
10883 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10884 (clobber (reg:SI 6))
10885 (clobber (reg:SI 7))
10886 (clobber (reg:SI 8))
10887 (clobber (reg:SI 9))
10888 (clobber (reg:SI 10))
10889 (clobber (reg:SI 11))
10890 (clobber (reg:SI 12))
10891 (clobber (match_scratch:SI 5 "=X"))]
10892 "TARGET_STRING && ! TARGET_POWER
10893 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10894 || INTVAL (operands[2]) == 0)
10895 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10896 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10897 && REGNO (operands[4]) == 5"
10898 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10899 [(set_attr "type" "store_ux")
10900 (set_attr "cell_micro" "always")
10901 (set_attr "length" "8")])
10902
10903 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10904 ;; register allocator doesn't have a clue about allocating 6 word registers.
10905 ;; rD/rS = r5 is preferred, efficient form.
10906 (define_expand "movmemsi_6reg"
10907 [(parallel [(set (match_operand 0 "" "")
10908 (match_operand 1 "" ""))
10909 (use (match_operand 2 "" ""))
10910 (use (match_operand 3 "" ""))
10911 (clobber (reg:SI 5))
10912 (clobber (reg:SI 6))
10913 (clobber (reg:SI 7))
10914 (clobber (reg:SI 8))
10915 (clobber (reg:SI 9))
10916 (clobber (reg:SI 10))
10917 (clobber (match_scratch:SI 4 ""))])]
10918 "TARGET_STRING"
10919 "")
10920
10921 (define_insn ""
10922 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10923 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10924 (use (match_operand:SI 2 "immediate_operand" "i"))
10925 (use (match_operand:SI 3 "immediate_operand" "i"))
10926 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10927 (clobber (reg:SI 6))
10928 (clobber (reg:SI 7))
10929 (clobber (reg:SI 8))
10930 (clobber (reg:SI 9))
10931 (clobber (reg:SI 10))
10932 (clobber (match_scratch:SI 5 "=q"))]
10933 "TARGET_STRING && TARGET_POWER
10934 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10935 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10936 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10937 && REGNO (operands[4]) == 5"
10938 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10939 [(set_attr "type" "store_ux")
10940 (set_attr "cell_micro" "always")
10941 (set_attr "length" "8")])
10942
10943 (define_insn ""
10944 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10945 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10946 (use (match_operand:SI 2 "immediate_operand" "i"))
10947 (use (match_operand:SI 3 "immediate_operand" "i"))
10948 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10949 (clobber (reg:SI 6))
10950 (clobber (reg:SI 7))
10951 (clobber (reg:SI 8))
10952 (clobber (reg:SI 9))
10953 (clobber (reg:SI 10))
10954 (clobber (match_scratch:SI 5 "=X"))]
10955 "TARGET_STRING && ! TARGET_POWER
10956 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10957 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10958 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10959 && REGNO (operands[4]) == 5"
10960 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10961 [(set_attr "type" "store_ux")
10962 (set_attr "cell_micro" "always")
10963 (set_attr "length" "8")])
10964
10965 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10966 ;; problems with TImode.
10967 ;; rD/rS = r5 is preferred, efficient form.
10968 (define_expand "movmemsi_4reg"
10969 [(parallel [(set (match_operand 0 "" "")
10970 (match_operand 1 "" ""))
10971 (use (match_operand 2 "" ""))
10972 (use (match_operand 3 "" ""))
10973 (clobber (reg:SI 5))
10974 (clobber (reg:SI 6))
10975 (clobber (reg:SI 7))
10976 (clobber (reg:SI 8))
10977 (clobber (match_scratch:SI 4 ""))])]
10978 "TARGET_STRING"
10979 "")
10980
10981 (define_insn ""
10982 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10983 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10984 (use (match_operand:SI 2 "immediate_operand" "i"))
10985 (use (match_operand:SI 3 "immediate_operand" "i"))
10986 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10987 (clobber (reg:SI 6))
10988 (clobber (reg:SI 7))
10989 (clobber (reg:SI 8))
10990 (clobber (match_scratch:SI 5 "=q"))]
10991 "TARGET_STRING && TARGET_POWER
10992 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10993 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10994 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10995 && REGNO (operands[4]) == 5"
10996 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10997 [(set_attr "type" "store_ux")
10998 (set_attr "cell_micro" "always")
10999 (set_attr "length" "8")])
11000
11001 (define_insn ""
11002 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11003 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11004 (use (match_operand:SI 2 "immediate_operand" "i"))
11005 (use (match_operand:SI 3 "immediate_operand" "i"))
11006 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
11007 (clobber (reg:SI 6))
11008 (clobber (reg:SI 7))
11009 (clobber (reg:SI 8))
11010 (clobber (match_scratch:SI 5 "=X"))]
11011 "TARGET_STRING && ! TARGET_POWER
11012 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
11013 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
11014 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
11015 && REGNO (operands[4]) == 5"
11016 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11017 [(set_attr "type" "store_ux")
11018 (set_attr "cell_micro" "always")
11019 (set_attr "length" "8")])
11020
11021 ;; Move up to 8 bytes at a time.
11022 (define_expand "movmemsi_2reg"
11023 [(parallel [(set (match_operand 0 "" "")
11024 (match_operand 1 "" ""))
11025 (use (match_operand 2 "" ""))
11026 (use (match_operand 3 "" ""))
11027 (clobber (match_scratch:DI 4 ""))
11028 (clobber (match_scratch:SI 5 ""))])]
11029 "TARGET_STRING && ! TARGET_POWERPC64"
11030 "")
11031
11032 (define_insn ""
11033 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11034 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11035 (use (match_operand:SI 2 "immediate_operand" "i"))
11036 (use (match_operand:SI 3 "immediate_operand" "i"))
11037 (clobber (match_scratch:DI 4 "=&r"))
11038 (clobber (match_scratch:SI 5 "=q"))]
11039 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
11040 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11041 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11042 [(set_attr "type" "store_ux")
11043 (set_attr "cell_micro" "always")
11044 (set_attr "length" "8")])
11045
11046 (define_insn ""
11047 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11048 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11049 (use (match_operand:SI 2 "immediate_operand" "i"))
11050 (use (match_operand:SI 3 "immediate_operand" "i"))
11051 (clobber (match_scratch:DI 4 "=&r"))
11052 (clobber (match_scratch:SI 5 "=X"))]
11053 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
11054 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11055 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11056 [(set_attr "type" "store_ux")
11057 (set_attr "cell_micro" "always")
11058 (set_attr "length" "8")])
11059
11060 ;; Move up to 4 bytes at a time.
11061 (define_expand "movmemsi_1reg"
11062 [(parallel [(set (match_operand 0 "" "")
11063 (match_operand 1 "" ""))
11064 (use (match_operand 2 "" ""))
11065 (use (match_operand 3 "" ""))
11066 (clobber (match_scratch:SI 4 ""))
11067 (clobber (match_scratch:SI 5 ""))])]
11068 "TARGET_STRING"
11069 "")
11070
11071 (define_insn ""
11072 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11073 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11074 (use (match_operand:SI 2 "immediate_operand" "i"))
11075 (use (match_operand:SI 3 "immediate_operand" "i"))
11076 (clobber (match_scratch:SI 4 "=&r"))
11077 (clobber (match_scratch:SI 5 "=q"))]
11078 "TARGET_STRING && TARGET_POWER
11079 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11080 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11081 [(set_attr "type" "store_ux")
11082 (set_attr "cell_micro" "always")
11083 (set_attr "length" "8")])
11084
11085 (define_insn ""
11086 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11087 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11088 (use (match_operand:SI 2 "immediate_operand" "i"))
11089 (use (match_operand:SI 3 "immediate_operand" "i"))
11090 (clobber (match_scratch:SI 4 "=&r"))
11091 (clobber (match_scratch:SI 5 "=X"))]
11092 "TARGET_STRING && ! TARGET_POWER
11093 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11094 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11095 [(set_attr "type" "store_ux")
11096 (set_attr "cell_micro" "always")
11097 (set_attr "length" "8")])
11098 \f
11099 ;; Define insns that do load or store with update. Some of these we can
11100 ;; get by using pre-decrement or pre-increment, but the hardware can also
11101 ;; do cases where the increment is not the size of the object.
11102 ;;
11103 ;; In all these cases, we use operands 0 and 1 for the register being
11104 ;; incremented because those are the operands that local-alloc will
11105 ;; tie and these are the pair most likely to be tieable (and the ones
11106 ;; that will benefit the most).
11107
11108 (define_insn "*movdi_update1"
11109 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
11110 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
11111 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
11112 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
11113 (plus:DI (match_dup 1) (match_dup 2)))]
11114 "TARGET_POWERPC64 && TARGET_UPDATE
11115 && (!avoiding_indexed_address_p (DImode)
11116 || !gpc_reg_operand (operands[2], DImode))"
11117 "@
11118 ldux %3,%0,%2
11119 ldu %3,%2(%0)"
11120 [(set_attr "type" "load_ux,load_u")])
11121
11122 (define_insn "movdi_<mode>_update"
11123 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11124 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11125 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11126 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11127 (plus:P (match_dup 1) (match_dup 2)))]
11128 "TARGET_POWERPC64 && TARGET_UPDATE
11129 && (!avoiding_indexed_address_p (Pmode)
11130 || !gpc_reg_operand (operands[2], Pmode)
11131 || (REG_P (operands[0])
11132 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11133 "@
11134 stdux %3,%0,%2
11135 stdu %3,%2(%0)"
11136 [(set_attr "type" "store_ux,store_u")])
11137
11138 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
11139 ;; needed for stack allocation, even if the user passes -mno-update.
11140 (define_insn "movdi_<mode>_update_stack"
11141 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11142 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11143 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11144 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11145 (plus:P (match_dup 1) (match_dup 2)))]
11146 "TARGET_POWERPC64"
11147 "@
11148 stdux %3,%0,%2
11149 stdu %3,%2(%0)"
11150 [(set_attr "type" "store_ux,store_u")])
11151
11152 (define_insn "*movsi_update1"
11153 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11154 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11155 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11156 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11157 (plus:SI (match_dup 1) (match_dup 2)))]
11158 "TARGET_UPDATE
11159 && (!avoiding_indexed_address_p (SImode)
11160 || !gpc_reg_operand (operands[2], SImode))"
11161 "@
11162 {lux|lwzux} %3,%0,%2
11163 {lu|lwzu} %3,%2(%0)"
11164 [(set_attr "type" "load_ux,load_u")])
11165
11166 (define_insn "*movsi_update2"
11167 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
11168 (sign_extend:DI
11169 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
11170 (match_operand:DI 2 "gpc_reg_operand" "r")))))
11171 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
11172 (plus:DI (match_dup 1) (match_dup 2)))]
11173 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
11174 && !avoiding_indexed_address_p (DImode)"
11175 "lwaux %3,%0,%2"
11176 [(set_attr "type" "load_ext_ux")])
11177
11178 (define_insn "movsi_update"
11179 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11180 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11181 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11182 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11183 (plus:SI (match_dup 1) (match_dup 2)))]
11184 "TARGET_UPDATE
11185 && (!avoiding_indexed_address_p (SImode)
11186 || !gpc_reg_operand (operands[2], SImode)
11187 || (REG_P (operands[0])
11188 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11189 "@
11190 {stux|stwux} %3,%0,%2
11191 {stu|stwu} %3,%2(%0)"
11192 [(set_attr "type" "store_ux,store_u")])
11193
11194 ;; This is an unconditional pattern; needed for stack allocation, even
11195 ;; if the user passes -mno-update.
11196 (define_insn "movsi_update_stack"
11197 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11198 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11199 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11200 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11201 (plus:SI (match_dup 1) (match_dup 2)))]
11202 ""
11203 "@
11204 {stux|stwux} %3,%0,%2
11205 {stu|stwu} %3,%2(%0)"
11206 [(set_attr "type" "store_ux,store_u")])
11207
11208 (define_insn "*movhi_update1"
11209 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
11210 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11211 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11212 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11213 (plus:SI (match_dup 1) (match_dup 2)))]
11214 "TARGET_UPDATE
11215 && (!avoiding_indexed_address_p (SImode)
11216 || !gpc_reg_operand (operands[2], SImode))"
11217 "@
11218 lhzux %3,%0,%2
11219 lhzu %3,%2(%0)"
11220 [(set_attr "type" "load_ux,load_u")])
11221
11222 (define_insn "*movhi_update2"
11223 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11224 (zero_extend:SI
11225 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11226 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11227 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11228 (plus:SI (match_dup 1) (match_dup 2)))]
11229 "TARGET_UPDATE
11230 && (!avoiding_indexed_address_p (SImode)
11231 || !gpc_reg_operand (operands[2], SImode))"
11232 "@
11233 lhzux %3,%0,%2
11234 lhzu %3,%2(%0)"
11235 [(set_attr "type" "load_ux,load_u")])
11236
11237 (define_insn "*movhi_update3"
11238 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11239 (sign_extend:SI
11240 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11241 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11242 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11243 (plus:SI (match_dup 1) (match_dup 2)))]
11244 "TARGET_UPDATE && rs6000_gen_cell_microcode
11245 && (!avoiding_indexed_address_p (SImode)
11246 || !gpc_reg_operand (operands[2], SImode))"
11247 "@
11248 lhaux %3,%0,%2
11249 lhau %3,%2(%0)"
11250 [(set_attr "type" "load_ext_ux,load_ext_u")])
11251
11252 (define_insn "*movhi_update4"
11253 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11254 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11255 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11256 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11257 (plus:SI (match_dup 1) (match_dup 2)))]
11258 "TARGET_UPDATE
11259 && (!avoiding_indexed_address_p (SImode)
11260 || !gpc_reg_operand (operands[2], SImode))"
11261 "@
11262 sthux %3,%0,%2
11263 sthu %3,%2(%0)"
11264 [(set_attr "type" "store_ux,store_u")])
11265
11266 (define_insn "*movqi_update1"
11267 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11268 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11269 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11270 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11271 (plus:SI (match_dup 1) (match_dup 2)))]
11272 "TARGET_UPDATE
11273 && (!avoiding_indexed_address_p (SImode)
11274 || !gpc_reg_operand (operands[2], SImode))"
11275 "@
11276 lbzux %3,%0,%2
11277 lbzu %3,%2(%0)"
11278 [(set_attr "type" "load_ux,load_u")])
11279
11280 (define_insn "*movqi_update2"
11281 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11282 (zero_extend:SI
11283 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11284 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11285 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11286 (plus:SI (match_dup 1) (match_dup 2)))]
11287 "TARGET_UPDATE
11288 && (!avoiding_indexed_address_p (SImode)
11289 || !gpc_reg_operand (operands[2], SImode))"
11290 "@
11291 lbzux %3,%0,%2
11292 lbzu %3,%2(%0)"
11293 [(set_attr "type" "load_ux,load_u")])
11294
11295 (define_insn "*movqi_update3"
11296 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11297 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11298 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11299 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11300 (plus:SI (match_dup 1) (match_dup 2)))]
11301 "TARGET_UPDATE
11302 && (!avoiding_indexed_address_p (SImode)
11303 || !gpc_reg_operand (operands[2], SImode))"
11304 "@
11305 stbux %3,%0,%2
11306 stbu %3,%2(%0)"
11307 [(set_attr "type" "store_ux,store_u")])
11308
11309 (define_insn "*movsf_update1"
11310 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11311 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11312 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11313 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11314 (plus:SI (match_dup 1) (match_dup 2)))]
11315 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11316 && (!avoiding_indexed_address_p (SImode)
11317 || !gpc_reg_operand (operands[2], SImode))"
11318 "@
11319 lfsux %3,%0,%2
11320 lfsu %3,%2(%0)"
11321 [(set_attr "type" "fpload_ux,fpload_u")])
11322
11323 (define_insn "*movsf_update2"
11324 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11325 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11326 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11327 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11328 (plus:SI (match_dup 1) (match_dup 2)))]
11329 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11330 && (!avoiding_indexed_address_p (SImode)
11331 || !gpc_reg_operand (operands[2], SImode))"
11332 "@
11333 stfsux %3,%0,%2
11334 stfsu %3,%2(%0)"
11335 [(set_attr "type" "fpstore_ux,fpstore_u")])
11336
11337 (define_insn "*movsf_update3"
11338 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11339 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11340 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11341 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11342 (plus:SI (match_dup 1) (match_dup 2)))]
11343 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11344 && (!avoiding_indexed_address_p (SImode)
11345 || !gpc_reg_operand (operands[2], SImode))"
11346 "@
11347 {lux|lwzux} %3,%0,%2
11348 {lu|lwzu} %3,%2(%0)"
11349 [(set_attr "type" "load_ux,load_u")])
11350
11351 (define_insn "*movsf_update4"
11352 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11353 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11354 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11355 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11356 (plus:SI (match_dup 1) (match_dup 2)))]
11357 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11358 && (!avoiding_indexed_address_p (SImode)
11359 || !gpc_reg_operand (operands[2], SImode))"
11360 "@
11361 {stux|stwux} %3,%0,%2
11362 {stu|stwu} %3,%2(%0)"
11363 [(set_attr "type" "store_ux,store_u")])
11364
11365 (define_insn "*movdf_update1"
11366 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11367 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11368 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11369 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11370 (plus:SI (match_dup 1) (match_dup 2)))]
11371 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11372 && (!avoiding_indexed_address_p (SImode)
11373 || !gpc_reg_operand (operands[2], SImode))"
11374 "@
11375 lfdux %3,%0,%2
11376 lfdu %3,%2(%0)"
11377 [(set_attr "type" "fpload_ux,fpload_u")])
11378
11379 (define_insn "*movdf_update2"
11380 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11381 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11382 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11383 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11384 (plus:SI (match_dup 1) (match_dup 2)))]
11385 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11386 && (!avoiding_indexed_address_p (SImode)
11387 || !gpc_reg_operand (operands[2], SImode))"
11388 "@
11389 stfdux %3,%0,%2
11390 stfdu %3,%2(%0)"
11391 [(set_attr "type" "fpstore_ux,fpstore_u")])
11392
11393 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
11394
11395 (define_insn "*lfq_power2"
11396 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
11397 (match_operand:V2DF 1 "memory_operand" ""))]
11398 "TARGET_POWER2
11399 && TARGET_HARD_FLOAT && TARGET_FPRS"
11400 "lfq%U1%X1 %0,%1")
11401
11402 (define_peephole2
11403 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11404 (match_operand:DF 1 "memory_operand" ""))
11405 (set (match_operand:DF 2 "gpc_reg_operand" "")
11406 (match_operand:DF 3 "memory_operand" ""))]
11407 "TARGET_POWER2
11408 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11409 && registers_ok_for_quad_peep (operands[0], operands[2])
11410 && mems_ok_for_quad_peep (operands[1], operands[3])"
11411 [(set (match_dup 0)
11412 (match_dup 1))]
11413 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
11414 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
11415
11416 (define_insn "*stfq_power2"
11417 [(set (match_operand:V2DF 0 "memory_operand" "")
11418 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
11419 "TARGET_POWER2
11420 && TARGET_HARD_FLOAT && TARGET_FPRS"
11421 "stfq%U0%X0 %1,%0")
11422
11423
11424 (define_peephole2
11425 [(set (match_operand:DF 0 "memory_operand" "")
11426 (match_operand:DF 1 "gpc_reg_operand" ""))
11427 (set (match_operand:DF 2 "memory_operand" "")
11428 (match_operand:DF 3 "gpc_reg_operand" ""))]
11429 "TARGET_POWER2
11430 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11431 && registers_ok_for_quad_peep (operands[1], operands[3])
11432 && mems_ok_for_quad_peep (operands[0], operands[2])"
11433 [(set (match_dup 0)
11434 (match_dup 1))]
11435 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
11436 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
11437
11438 ;; After inserting conditional returns we can sometimes have
11439 ;; unnecessary register moves. Unfortunately we cannot have a
11440 ;; modeless peephole here, because some single SImode sets have early
11441 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11442 ;; sequences, using get_attr_length here will smash the operands
11443 ;; array. Neither is there an early_cobbler_p predicate.
11444 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11445 (define_peephole2
11446 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11447 (match_operand:DF 1 "any_operand" ""))
11448 (set (match_operand:DF 2 "gpc_reg_operand" "")
11449 (match_dup 0))]
11450 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11451 && peep2_reg_dead_p (2, operands[0])"
11452 [(set (match_dup 2) (match_dup 1))])
11453
11454 (define_peephole2
11455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11456 (match_operand:SF 1 "any_operand" ""))
11457 (set (match_operand:SF 2 "gpc_reg_operand" "")
11458 (match_dup 0))]
11459 "peep2_reg_dead_p (2, operands[0])"
11460 [(set (match_dup 2) (match_dup 1))])
11461
11462 \f
11463 ;; TLS support.
11464
11465 ;; Mode attributes for different ABIs.
11466 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11467 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11468 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11469 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11470
11471 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11472 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11473 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11474 (match_operand 4 "" "g")))
11475 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11476 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11477 UNSPEC_TLSGD)
11478 (clobber (reg:SI LR_REGNO))]
11479 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11480 {
11481 if (TARGET_CMODEL != CMODEL_SMALL)
11482 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
11483 else
11484 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
11485 }
11486 "&& TARGET_TLS_MARKERS"
11487 [(set (match_dup 0)
11488 (unspec:TLSmode [(match_dup 1)
11489 (match_dup 2)]
11490 UNSPEC_TLSGD))
11491 (parallel [(set (match_dup 0)
11492 (call (mem:TLSmode (match_dup 3))
11493 (match_dup 4)))
11494 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11495 (clobber (reg:SI LR_REGNO))])]
11496 ""
11497 [(set_attr "type" "two")
11498 (set (attr "length")
11499 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11500 (const_int 16)
11501 (const_int 12)))])
11502
11503 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11504 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11505 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11506 (match_operand 4 "" "g")))
11507 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11508 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11509 UNSPEC_TLSGD)
11510 (clobber (reg:SI LR_REGNO))]
11511 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11512 {
11513 if (flag_pic)
11514 {
11515 if (TARGET_SECURE_PLT && flag_pic == 2)
11516 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11517 else
11518 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11519 }
11520 else
11521 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11522 }
11523 "&& TARGET_TLS_MARKERS"
11524 [(set (match_dup 0)
11525 (unspec:TLSmode [(match_dup 1)
11526 (match_dup 2)]
11527 UNSPEC_TLSGD))
11528 (parallel [(set (match_dup 0)
11529 (call (mem:TLSmode (match_dup 3))
11530 (match_dup 4)))
11531 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11532 (clobber (reg:SI LR_REGNO))])]
11533 ""
11534 [(set_attr "type" "two")
11535 (set_attr "length" "8")])
11536
11537 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11538 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11539 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11540 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11541 UNSPEC_TLSGD))]
11542 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11543 "addi %0,%1,%2@got@tlsgd"
11544 "&& TARGET_CMODEL != CMODEL_SMALL"
11545 [(set (match_dup 3)
11546 (const:TLSmode
11547 (plus:TLSmode (match_dup 1)
11548 (high:TLSmode
11549 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))))
11550 (set (match_dup 0)
11551 (lo_sum:TLSmode (match_dup 3)
11552 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
11553 "
11554 {
11555 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11556 }"
11557 [(set (attr "length")
11558 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11559 (const_int 8)
11560 (const_int 4)))])
11561
11562 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11563 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11564 (const:TLSmode
11565 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11566 (high:TLSmode
11567 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11568 UNSPEC_TLSGD)))))]
11569 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11570 "addis %0,%1,%2@got@tlsgd@ha"
11571 [(set_attr "length" "4")])
11572
11573 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11574 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11575 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11576 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11577 UNSPEC_TLSGD)))]
11578 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11579 "addi %0,%1,%2@got@tlsgd@l"
11580 [(set_attr "length" "4")])
11581
11582 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11583 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11584 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11585 (match_operand 2 "" "g")))
11586 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11587 UNSPEC_TLSGD)
11588 (clobber (reg:SI LR_REGNO))]
11589 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11590 "bl %z1(%3@tlsgd)\;%."
11591 [(set_attr "type" "branch")
11592 (set_attr "length" "8")])
11593
11594 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11595 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11596 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11597 (match_operand 2 "" "g")))
11598 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11599 UNSPEC_TLSGD)
11600 (clobber (reg:SI LR_REGNO))]
11601 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11602 {
11603 if (flag_pic)
11604 {
11605 if (TARGET_SECURE_PLT && flag_pic == 2)
11606 return "bl %z1+32768(%3@tlsgd)@plt";
11607 return "bl %z1(%3@tlsgd)@plt";
11608 }
11609 return "bl %z1(%3@tlsgd)";
11610 }
11611 [(set_attr "type" "branch")
11612 (set_attr "length" "4")])
11613
11614 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11615 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11616 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11617 (match_operand 3 "" "g")))
11618 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11619 UNSPEC_TLSLD)
11620 (clobber (reg:SI LR_REGNO))]
11621 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11622 {
11623 if (TARGET_CMODEL != CMODEL_SMALL)
11624 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
11625 else
11626 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
11627 }
11628 "&& TARGET_TLS_MARKERS"
11629 [(set (match_dup 0)
11630 (unspec:TLSmode [(match_dup 1)]
11631 UNSPEC_TLSLD))
11632 (parallel [(set (match_dup 0)
11633 (call (mem:TLSmode (match_dup 2))
11634 (match_dup 3)))
11635 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11636 (clobber (reg:SI LR_REGNO))])]
11637 ""
11638 [(set_attr "type" "two")
11639 (set (attr "length")
11640 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11641 (const_int 16)
11642 (const_int 12)))])
11643
11644 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11645 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11646 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11647 (match_operand 3 "" "g")))
11648 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11649 UNSPEC_TLSLD)
11650 (clobber (reg:SI LR_REGNO))]
11651 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11652 {
11653 if (flag_pic)
11654 {
11655 if (TARGET_SECURE_PLT && flag_pic == 2)
11656 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11657 else
11658 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11659 }
11660 else
11661 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11662 }
11663 "&& TARGET_TLS_MARKERS"
11664 [(set (match_dup 0)
11665 (unspec:TLSmode [(match_dup 1)]
11666 UNSPEC_TLSLD))
11667 (parallel [(set (match_dup 0)
11668 (call (mem:TLSmode (match_dup 2))
11669 (match_dup 3)))
11670 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11671 (clobber (reg:SI LR_REGNO))])]
11672 ""
11673 [(set_attr "length" "8")])
11674
11675 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11676 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11677 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11678 UNSPEC_TLSLD))]
11679 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11680 "addi %0,%1,%&@got@tlsld"
11681 "&& TARGET_CMODEL != CMODEL_SMALL"
11682 [(set (match_dup 2)
11683 (const:TLSmode
11684 (plus:TLSmode (match_dup 1)
11685 (high:TLSmode
11686 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))))
11687 (set (match_dup 0)
11688 (lo_sum:TLSmode (match_dup 2)
11689 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11690 "
11691 {
11692 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11693 }"
11694 [(set (attr "length")
11695 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11696 (const_int 8)
11697 (const_int 4)))])
11698
11699 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11700 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11701 (const:TLSmode
11702 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11703 (high:TLSmode
11704 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))))]
11705 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11706 "addis %0,%1,%&@got@tlsld@ha"
11707 [(set_attr "length" "4")])
11708
11709 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11710 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11711 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11712 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11713 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11714 "addi %0,%1,%&@got@tlsld@l"
11715 [(set_attr "length" "4")])
11716
11717 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11718 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11719 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11720 (match_operand 2 "" "g")))
11721 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11722 (clobber (reg:SI LR_REGNO))]
11723 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11724 "bl %z1(%&@tlsld)\;%."
11725 [(set_attr "type" "branch")
11726 (set_attr "length" "8")])
11727
11728 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11729 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11730 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11731 (match_operand 2 "" "g")))
11732 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11733 (clobber (reg:SI LR_REGNO))]
11734 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11735 {
11736 if (flag_pic)
11737 {
11738 if (TARGET_SECURE_PLT && flag_pic == 2)
11739 return "bl %z1+32768(%&@tlsld)@plt";
11740 return "bl %z1(%&@tlsld)@plt";
11741 }
11742 return "bl %z1(%&@tlsld)";
11743 }
11744 [(set_attr "type" "branch")
11745 (set_attr "length" "4")])
11746
11747 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11748 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11749 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11750 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11751 UNSPEC_TLSDTPREL))]
11752 "HAVE_AS_TLS"
11753 "addi %0,%1,%2@dtprel")
11754
11755 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11756 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11757 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11758 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11759 UNSPEC_TLSDTPRELHA))]
11760 "HAVE_AS_TLS"
11761 "addis %0,%1,%2@dtprel@ha")
11762
11763 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11764 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11765 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11766 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11767 UNSPEC_TLSDTPRELLO))]
11768 "HAVE_AS_TLS"
11769 "addi %0,%1,%2@dtprel@l")
11770
11771 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11772 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11773 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11774 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11775 UNSPEC_TLSGOTDTPREL))]
11776 "HAVE_AS_TLS"
11777 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11778 "&& TARGET_CMODEL != CMODEL_SMALL"
11779 [(set (match_dup 3)
11780 (const:TLSmode
11781 (plus:TLSmode (match_dup 1)
11782 (high:TLSmode
11783 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))))
11784 (set (match_dup 0)
11785 (lo_sum:TLSmode (match_dup 3)
11786 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11787 "
11788 {
11789 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11790 }"
11791 [(set (attr "length")
11792 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11793 (const_int 8)
11794 (const_int 4)))])
11795
11796 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11797 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11798 (const:TLSmode
11799 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11800 (high:TLSmode
11801 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11802 UNSPEC_TLSGOTDTPREL)))))]
11803 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11804 "addis %0,%1,%2@got@dtprel@ha"
11805 [(set_attr "length" "4")])
11806
11807 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11808 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11809 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11810 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11811 UNSPEC_TLSGOTDTPREL)))]
11812 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11813 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11814 [(set_attr "length" "4")])
11815
11816 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11817 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11818 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11819 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11820 UNSPEC_TLSTPREL))]
11821 "HAVE_AS_TLS"
11822 "addi %0,%1,%2@tprel")
11823
11824 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11825 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11826 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11827 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11828 UNSPEC_TLSTPRELHA))]
11829 "HAVE_AS_TLS"
11830 "addis %0,%1,%2@tprel@ha")
11831
11832 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11833 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11834 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11835 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11836 UNSPEC_TLSTPRELLO))]
11837 "HAVE_AS_TLS"
11838 "addi %0,%1,%2@tprel@l")
11839
11840 ;; "b" output constraint here and on tls_tls input to support linker tls
11841 ;; optimization. The linker may edit the instructions emitted by a
11842 ;; tls_got_tprel/tls_tls pair to addis,addi.
11843 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11844 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11845 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11846 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11847 UNSPEC_TLSGOTTPREL))]
11848 "HAVE_AS_TLS"
11849 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11850 "&& TARGET_CMODEL != CMODEL_SMALL"
11851 [(set (match_dup 3)
11852 (const:TLSmode
11853 (plus:TLSmode (match_dup 1)
11854 (high:TLSmode
11855 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))))
11856 (set (match_dup 0)
11857 (lo_sum:TLSmode (match_dup 3)
11858 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11859 "
11860 {
11861 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11862 }"
11863 [(set (attr "length")
11864 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11865 (const_int 8)
11866 (const_int 4)))])
11867
11868 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11869 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11870 (const:TLSmode
11871 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11872 (high:TLSmode
11873 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11874 UNSPEC_TLSGOTTPREL)))))]
11875 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11876 "addis %0,%1,%2@got@tprel@ha"
11877 [(set_attr "length" "4")])
11878
11879 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11880 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11881 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11882 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11883 UNSPEC_TLSGOTTPREL)))]
11884 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11885 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11886 [(set_attr "length" "4")])
11887
11888 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11889 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11890 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11891 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11892 UNSPEC_TLSTLS))]
11893 "HAVE_AS_TLS"
11894 "add %0,%1,%2@tls")
11895 \f
11896 ;; Next come insns related to the calling sequence.
11897 ;;
11898 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11899 ;; We move the back-chain and decrement the stack pointer.
11900
11901 (define_expand "allocate_stack"
11902 [(set (match_operand 0 "gpc_reg_operand" "")
11903 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11904 (set (reg 1)
11905 (minus (reg 1) (match_dup 1)))]
11906 ""
11907 "
11908 { rtx chain = gen_reg_rtx (Pmode);
11909 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11910 rtx neg_op0;
11911 rtx insn, par, set, mem;
11912
11913 emit_move_insn (chain, stack_bot);
11914
11915 /* Check stack bounds if necessary. */
11916 if (crtl->limit_stack)
11917 {
11918 rtx available;
11919 available = expand_binop (Pmode, sub_optab,
11920 stack_pointer_rtx, stack_limit_rtx,
11921 NULL_RTX, 1, OPTAB_WIDEN);
11922 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11923 }
11924
11925 if (GET_CODE (operands[1]) != CONST_INT
11926 || INTVAL (operands[1]) < -32767
11927 || INTVAL (operands[1]) > 32768)
11928 {
11929 neg_op0 = gen_reg_rtx (Pmode);
11930 if (TARGET_32BIT)
11931 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11932 else
11933 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11934 }
11935 else
11936 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11937
11938 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11939 : gen_movdi_di_update_stack))
11940 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11941 chain));
11942 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11943 it now and set the alias set/attributes. The above gen_*_update
11944 calls will generate a PARALLEL with the MEM set being the first
11945 operation. */
11946 par = PATTERN (insn);
11947 gcc_assert (GET_CODE (par) == PARALLEL);
11948 set = XVECEXP (par, 0, 0);
11949 gcc_assert (GET_CODE (set) == SET);
11950 mem = SET_DEST (set);
11951 gcc_assert (MEM_P (mem));
11952 MEM_NOTRAP_P (mem) = 1;
11953 set_mem_alias_set (mem, get_frame_alias_set ());
11954
11955 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11956 DONE;
11957 }")
11958
11959 ;; These patterns say how to save and restore the stack pointer. We need not
11960 ;; save the stack pointer at function level since we are careful to
11961 ;; preserve the backchain. At block level, we have to restore the backchain
11962 ;; when we restore the stack pointer.
11963 ;;
11964 ;; For nonlocal gotos, we must save both the stack pointer and its
11965 ;; backchain and restore both. Note that in the nonlocal case, the
11966 ;; save area is a memory location.
11967
11968 (define_expand "save_stack_function"
11969 [(match_operand 0 "any_operand" "")
11970 (match_operand 1 "any_operand" "")]
11971 ""
11972 "DONE;")
11973
11974 (define_expand "restore_stack_function"
11975 [(match_operand 0 "any_operand" "")
11976 (match_operand 1 "any_operand" "")]
11977 ""
11978 "DONE;")
11979
11980 ;; Adjust stack pointer (op0) to a new value (op1).
11981 ;; First copy old stack backchain to new location, and ensure that the
11982 ;; scheduler won't reorder the sp assignment before the backchain write.
11983 (define_expand "restore_stack_block"
11984 [(set (match_dup 2) (match_dup 3))
11985 (set (match_dup 4) (match_dup 2))
11986 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11987 (set (match_operand 0 "register_operand" "")
11988 (match_operand 1 "register_operand" ""))]
11989 ""
11990 "
11991 {
11992 operands[1] = force_reg (Pmode, operands[1]);
11993 operands[2] = gen_reg_rtx (Pmode);
11994 operands[3] = gen_frame_mem (Pmode, operands[0]);
11995 operands[4] = gen_frame_mem (Pmode, operands[1]);
11996 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11997 }")
11998
11999 (define_expand "save_stack_nonlocal"
12000 [(set (match_dup 3) (match_dup 4))
12001 (set (match_operand 0 "memory_operand" "") (match_dup 3))
12002 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
12003 ""
12004 "
12005 {
12006 int units_per_word = (TARGET_32BIT) ? 4 : 8;
12007
12008 /* Copy the backchain to the first word, sp to the second. */
12009 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
12010 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
12011 operands[3] = gen_reg_rtx (Pmode);
12012 operands[4] = gen_frame_mem (Pmode, operands[1]);
12013 }")
12014
12015 (define_expand "restore_stack_nonlocal"
12016 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
12017 (set (match_dup 3) (match_dup 4))
12018 (set (match_dup 5) (match_dup 2))
12019 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
12020 (set (match_operand 0 "register_operand" "") (match_dup 3))]
12021 ""
12022 "
12023 {
12024 int units_per_word = (TARGET_32BIT) ? 4 : 8;
12025
12026 /* Restore the backchain from the first word, sp from the second. */
12027 operands[2] = gen_reg_rtx (Pmode);
12028 operands[3] = gen_reg_rtx (Pmode);
12029 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
12030 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
12031 operands[5] = gen_frame_mem (Pmode, operands[3]);
12032 operands[6] = gen_frame_mem (BLKmode, operands[0]);
12033 }")
12034 \f
12035 ;; TOC register handling.
12036
12037 ;; Code to initialize the TOC register...
12038
12039 (define_insn "load_toc_aix_si"
12040 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12041 (unspec:SI [(const_int 0)] UNSPEC_TOC))
12042 (use (reg:SI 2))])]
12043 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
12044 "*
12045 {
12046 char buf[30];
12047 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12048 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12049 operands[2] = gen_rtx_REG (Pmode, 2);
12050 return \"{l|lwz} %0,%1(%2)\";
12051 }"
12052 [(set_attr "type" "load")])
12053
12054 (define_insn "load_toc_aix_di"
12055 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12056 (unspec:DI [(const_int 0)] UNSPEC_TOC))
12057 (use (reg:DI 2))])]
12058 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
12059 "*
12060 {
12061 char buf[30];
12062 #ifdef TARGET_RELOCATABLE
12063 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
12064 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
12065 #else
12066 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12067 #endif
12068 if (TARGET_ELF)
12069 strcat (buf, \"@toc\");
12070 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12071 operands[2] = gen_rtx_REG (Pmode, 2);
12072 return \"ld %0,%1(%2)\";
12073 }"
12074 [(set_attr "type" "load")])
12075
12076 (define_insn "load_toc_v4_pic_si"
12077 [(set (reg:SI LR_REGNO)
12078 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
12079 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
12080 "bl _GLOBAL_OFFSET_TABLE_@local-4"
12081 [(set_attr "type" "branch")
12082 (set_attr "length" "4")])
12083
12084 (define_insn "load_toc_v4_PIC_1"
12085 [(set (reg:SI LR_REGNO)
12086 (match_operand:SI 0 "immediate_operand" "s"))
12087 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12088 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
12089 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12090 "bcl 20,31,%0\\n%0:"
12091 [(set_attr "type" "branch")
12092 (set_attr "length" "4")])
12093
12094 (define_insn "load_toc_v4_PIC_1b"
12095 [(set (reg:SI LR_REGNO)
12096 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12097 (label_ref (match_operand 1 "" ""))]
12098 UNSPEC_TOCPTR))
12099 (match_dup 1)]
12100 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12101 "bcl 20,31,$+8\;.long %0-$"
12102 [(set_attr "type" "branch")
12103 (set_attr "length" "8")])
12104
12105 (define_insn "load_toc_v4_PIC_2"
12106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12107 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12108 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
12109 (match_operand:SI 3 "immediate_operand" "s")))))]
12110 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12111 "{l|lwz} %0,%2-%3(%1)"
12112 [(set_attr "type" "load")])
12113
12114 (define_insn "load_toc_v4_PIC_3b"
12115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12116 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12117 (high:SI
12118 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12119 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
12120 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12121 "{cau|addis} %0,%1,%2-%3@ha")
12122
12123 (define_insn "load_toc_v4_PIC_3c"
12124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12125 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12126 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12127 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
12128 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12129 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
12130
12131 ;; If the TOC is shared over a translation unit, as happens with all
12132 ;; the kinds of PIC that we support, we need to restore the TOC
12133 ;; pointer only when jumping over units of translation.
12134 ;; On Darwin, we need to reload the picbase.
12135
12136 (define_expand "builtin_setjmp_receiver"
12137 [(use (label_ref (match_operand 0 "" "")))]
12138 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12139 || (TARGET_TOC && TARGET_MINIMAL_TOC)
12140 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
12141 "
12142 {
12143 #if TARGET_MACHO
12144 if (DEFAULT_ABI == ABI_DARWIN)
12145 {
12146 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
12147 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12148 rtx tmplabrtx;
12149 char tmplab[20];
12150
12151 crtl->uses_pic_offset_table = 1;
12152 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
12153 CODE_LABEL_NUMBER (operands[0]));
12154 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
12155
12156 emit_insn (gen_load_macho_picbase (tmplabrtx));
12157 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
12158 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12159 }
12160 else
12161 #endif
12162 rs6000_emit_load_toc_table (FALSE);
12163 DONE;
12164 }")
12165
12166 ;; Elf specific ways of loading addresses for non-PIC code.
12167 ;; The output of this could be r0, but we make a very strong
12168 ;; preference for a base register because it will usually
12169 ;; be needed there.
12170 (define_insn "elf_high"
12171 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12172 (high:SI (match_operand 1 "" "")))]
12173 "TARGET_ELF && ! TARGET_64BIT"
12174 "{liu|lis} %0,%1@ha")
12175
12176 (define_insn "elf_low"
12177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12178 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12179 (match_operand 2 "" "")))]
12180 "TARGET_ELF && ! TARGET_64BIT"
12181 "@
12182 {cal|la} %0,%2@l(%1)
12183 {ai|addic} %0,%1,%K2")
12184
12185 ;; Largetoc support
12186 (define_insn "largetoc_high"
12187 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
12188 (const:DI
12189 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12190 (high:DI (match_operand:DI 2 "" "")))))]
12191 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12192 "{cau|addis} %0,%1,%2@ha")
12193
12194 (define_insn "largetoc_low"
12195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12196 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12197 (match_operand:DI 2 "" "")))]
12198 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12199 "{cal %0,%2@l(%1)|addi %0,%1,%2@l}")
12200 \f
12201 ;; Call and call_value insns
12202 (define_expand "call"
12203 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12204 (match_operand 1 "" ""))
12205 (use (match_operand 2 "" ""))
12206 (clobber (reg:SI LR_REGNO))])]
12207 ""
12208 "
12209 {
12210 #if TARGET_MACHO
12211 if (MACHOPIC_INDIRECT)
12212 operands[0] = machopic_indirect_call_target (operands[0]);
12213 #endif
12214
12215 gcc_assert (GET_CODE (operands[0]) == MEM);
12216 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12217
12218 operands[0] = XEXP (operands[0], 0);
12219
12220 if (GET_CODE (operands[0]) != SYMBOL_REF
12221 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
12222 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12223 {
12224 if (INTVAL (operands[2]) & CALL_LONG)
12225 operands[0] = rs6000_longcall_ref (operands[0]);
12226
12227 switch (DEFAULT_ABI)
12228 {
12229 case ABI_V4:
12230 case ABI_DARWIN:
12231 operands[0] = force_reg (Pmode, operands[0]);
12232 break;
12233
12234 case ABI_AIX:
12235 /* AIX function pointers are really pointers to a three word
12236 area. */
12237 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
12238 DONE;
12239
12240 default:
12241 gcc_unreachable ();
12242 }
12243 }
12244 }")
12245
12246 (define_expand "call_value"
12247 [(parallel [(set (match_operand 0 "" "")
12248 (call (mem:SI (match_operand 1 "address_operand" ""))
12249 (match_operand 2 "" "")))
12250 (use (match_operand 3 "" ""))
12251 (clobber (reg:SI LR_REGNO))])]
12252 ""
12253 "
12254 {
12255 #if TARGET_MACHO
12256 if (MACHOPIC_INDIRECT)
12257 operands[1] = machopic_indirect_call_target (operands[1]);
12258 #endif
12259
12260 gcc_assert (GET_CODE (operands[1]) == MEM);
12261 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12262
12263 operands[1] = XEXP (operands[1], 0);
12264
12265 if (GET_CODE (operands[1]) != SYMBOL_REF
12266 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
12267 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12268 {
12269 if (INTVAL (operands[3]) & CALL_LONG)
12270 operands[1] = rs6000_longcall_ref (operands[1]);
12271
12272 switch (DEFAULT_ABI)
12273 {
12274 case ABI_V4:
12275 case ABI_DARWIN:
12276 operands[1] = force_reg (Pmode, operands[1]);
12277 break;
12278
12279 case ABI_AIX:
12280 /* AIX function pointers are really pointers to a three word
12281 area. */
12282 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
12283 DONE;
12284
12285 default:
12286 gcc_unreachable ();
12287 }
12288 }
12289 }")
12290
12291 ;; Call to function in current module. No TOC pointer reload needed.
12292 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12293 ;; either the function was not prototyped, or it was prototyped as a
12294 ;; variable argument function. It is > 0 if FP registers were passed
12295 ;; and < 0 if they were not.
12296
12297 (define_insn "*call_local32"
12298 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12299 (match_operand 1 "" "g,g"))
12300 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12301 (clobber (reg:SI LR_REGNO))]
12302 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12303 "*
12304 {
12305 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12306 output_asm_insn (\"crxor 6,6,6\", operands);
12307
12308 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12309 output_asm_insn (\"creqv 6,6,6\", operands);
12310
12311 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12312 }"
12313 [(set_attr "type" "branch")
12314 (set_attr "length" "4,8")])
12315
12316 (define_insn "*call_local64"
12317 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12318 (match_operand 1 "" "g,g"))
12319 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12320 (clobber (reg:SI LR_REGNO))]
12321 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12322 "*
12323 {
12324 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12325 output_asm_insn (\"crxor 6,6,6\", operands);
12326
12327 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12328 output_asm_insn (\"creqv 6,6,6\", operands);
12329
12330 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12331 }"
12332 [(set_attr "type" "branch")
12333 (set_attr "length" "4,8")])
12334
12335 (define_insn "*call_value_local32"
12336 [(set (match_operand 0 "" "")
12337 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12338 (match_operand 2 "" "g,g")))
12339 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12340 (clobber (reg:SI LR_REGNO))]
12341 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12342 "*
12343 {
12344 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12345 output_asm_insn (\"crxor 6,6,6\", operands);
12346
12347 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12348 output_asm_insn (\"creqv 6,6,6\", operands);
12349
12350 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12351 }"
12352 [(set_attr "type" "branch")
12353 (set_attr "length" "4,8")])
12354
12355
12356 (define_insn "*call_value_local64"
12357 [(set (match_operand 0 "" "")
12358 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12359 (match_operand 2 "" "g,g")))
12360 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12361 (clobber (reg:SI LR_REGNO))]
12362 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12363 "*
12364 {
12365 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12366 output_asm_insn (\"crxor 6,6,6\", operands);
12367
12368 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12369 output_asm_insn (\"creqv 6,6,6\", operands);
12370
12371 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12372 }"
12373 [(set_attr "type" "branch")
12374 (set_attr "length" "4,8")])
12375
12376 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12377 ;; Operand0 is the addresss of the function to call
12378 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12379 ;; Operand2 is the location in the function descriptor to load r2 from
12380 ;; Operand3 is the stack location to hold the current TOC pointer
12381
12382 (define_insn_and_split "call_indirect_aix<ptrsize>"
12383 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12384 (match_operand 1 "" "g,g"))
12385 (use (match_operand:P 2 "memory_operand" "m,m"))
12386 (use (match_operand:P 3 "memory_operand" "m,m"))
12387 (use (reg:P STATIC_CHAIN_REGNUM))
12388 (clobber (reg:P LR_REGNO))]
12389 "DEFAULT_ABI == ABI_AIX && TARGET_R11"
12390 "#"
12391 "&& reload_completed"
12392 [(set (reg:P TOC_REGNUM) (match_dup 2))
12393 (parallel [(call (mem:SI (match_dup 0))
12394 (match_dup 1))
12395 (use (reg:P TOC_REGNUM))
12396 (use (reg:P STATIC_CHAIN_REGNUM))
12397 (use (match_dup 3))
12398 (set (reg:P TOC_REGNUM) (match_dup 3))
12399 (clobber (reg:P LR_REGNO))])]
12400 ""
12401 [(set_attr "type" "jmpreg")
12402 (set_attr "length" "12")])
12403
12404 (define_insn "*call_indirect_aix<ptrsize>_internal"
12405 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12406 (match_operand 1 "" "g,g"))
12407 (use (reg:P TOC_REGNUM))
12408 (use (reg:P STATIC_CHAIN_REGNUM))
12409 (use (match_operand:P 2 "memory_operand" "m,m"))
12410 (set (reg:P TOC_REGNUM) (match_dup 2))
12411 (clobber (reg:P LR_REGNO))]
12412 "DEFAULT_ABI == ABI_AIX && reload_completed && TARGET_R11"
12413 "b%T0l\;<ptrload> 2,%2"
12414 [(set_attr "type" "jmpreg")
12415 (set_attr "length" "8")])
12416
12417 ;; Like call_indirect_aix<ptrsize>, except don't load the static chain
12418 ;; Operand0 is the addresss of the function to call
12419 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12420 ;; Operand2 is the location in the function descriptor to load r2 from
12421 ;; Operand3 is the stack location to hold the current TOC pointer
12422
12423 (define_insn_and_split "call_indirect_aix<ptrsize>_nor11"
12424 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12425 (match_operand 1 "" "g,g"))
12426 (use (match_operand:P 2 "memory_operand" "m,m"))
12427 (use (match_operand:P 3 "memory_operand" "m,m"))
12428 (clobber (reg:P LR_REGNO))]
12429 "DEFAULT_ABI == ABI_AIX && !TARGET_R11"
12430 "#"
12431 "&& reload_completed"
12432 [(set (reg:P TOC_REGNUM) (match_dup 2))
12433 (parallel [(call (mem:SI (match_dup 0))
12434 (match_dup 1))
12435 (use (reg:P TOC_REGNUM))
12436 (use (match_dup 3))
12437 (set (reg:P TOC_REGNUM) (match_dup 3))
12438 (clobber (reg:P LR_REGNO))])]
12439 ""
12440 [(set_attr "type" "jmpreg")
12441 (set_attr "length" "12")])
12442
12443 (define_insn "*call_indirect_aix<ptrsize>_internal2"
12444 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12445 (match_operand 1 "" "g,g"))
12446 (use (reg:P TOC_REGNUM))
12447 (use (match_operand:P 2 "memory_operand" "m,m"))
12448 (set (reg:P TOC_REGNUM) (match_dup 2))
12449 (clobber (reg:P LR_REGNO))]
12450 "DEFAULT_ABI == ABI_AIX && reload_completed && !TARGET_R11"
12451 "b%T0l\;<ptrload> 2,%2"
12452 [(set_attr "type" "jmpreg")
12453 (set_attr "length" "8")])
12454
12455 ;; Operand0 is the return result of the function
12456 ;; Operand1 is the addresss of the function to call
12457 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12458 ;; Operand3 is the location in the function descriptor to load r2 from
12459 ;; Operand4 is the stack location to hold the current TOC pointer
12460
12461 (define_insn_and_split "call_value_indirect_aix<ptrsize>"
12462 [(set (match_operand 0 "" "")
12463 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12464 (match_operand 2 "" "g,g")))
12465 (use (match_operand:P 3 "memory_operand" "m,m"))
12466 (use (match_operand:P 4 "memory_operand" "m,m"))
12467 (use (reg:P STATIC_CHAIN_REGNUM))
12468 (clobber (reg:P LR_REGNO))]
12469 "DEFAULT_ABI == ABI_AIX && TARGET_R11"
12470 "#"
12471 "&& reload_completed"
12472 [(set (reg:P TOC_REGNUM) (match_dup 3))
12473 (parallel [(set (match_dup 0)
12474 (call (mem:SI (match_dup 1))
12475 (match_dup 2)))
12476 (use (reg:P TOC_REGNUM))
12477 (use (reg:P STATIC_CHAIN_REGNUM))
12478 (use (match_dup 4))
12479 (set (reg:P TOC_REGNUM) (match_dup 4))
12480 (clobber (reg:P LR_REGNO))])]
12481 ""
12482 [(set_attr "type" "jmpreg")
12483 (set_attr "length" "12")])
12484
12485 (define_insn "*call_value_indirect_aix<ptrsize>_internal"
12486 [(set (match_operand 0 "" "")
12487 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12488 (match_operand 2 "" "g,g")))
12489 (use (reg:P TOC_REGNUM))
12490 (use (reg:P STATIC_CHAIN_REGNUM))
12491 (use (match_operand:P 3 "memory_operand" "m,m"))
12492 (set (reg:P TOC_REGNUM) (match_dup 3))
12493 (clobber (reg:P LR_REGNO))]
12494 "DEFAULT_ABI == ABI_AIX && reload_completed && TARGET_R11"
12495 "b%T1l\;<ptrload> 2,%3"
12496 [(set_attr "type" "jmpreg")
12497 (set_attr "length" "8")])
12498
12499 ;; Like call_value_indirect_aix<ptrsize>, but don't load the static chain
12500 ;; Operand0 is the return result of the function
12501 ;; Operand1 is the addresss of the function to call
12502 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12503 ;; Operand3 is the location in the function descriptor to load r2 from
12504 ;; Operand4 is the stack location to hold the current TOC pointer
12505
12506 (define_insn_and_split "call_value_indirect_aix<ptrsize>_nor11"
12507 [(set (match_operand 0 "" "")
12508 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12509 (match_operand 2 "" "g,g")))
12510 (use (match_operand:P 3 "memory_operand" "m,m"))
12511 (use (match_operand:P 4 "memory_operand" "m,m"))
12512 (clobber (reg:P LR_REGNO))]
12513 "DEFAULT_ABI == ABI_AIX && !TARGET_R11"
12514 "#"
12515 "&& reload_completed"
12516 [(set (reg:P TOC_REGNUM) (match_dup 3))
12517 (parallel [(set (match_dup 0)
12518 (call (mem:SI (match_dup 1))
12519 (match_dup 2)))
12520 (use (reg:P TOC_REGNUM))
12521 (use (match_dup 4))
12522 (set (reg:P TOC_REGNUM) (match_dup 4))
12523 (clobber (reg:P LR_REGNO))])]
12524 ""
12525 [(set_attr "type" "jmpreg")
12526 (set_attr "length" "12")])
12527
12528 (define_insn "*call_value_indirect_aix<ptrsize>_internal2"
12529 [(set (match_operand 0 "" "")
12530 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12531 (match_operand 2 "" "g,g")))
12532 (use (reg:P TOC_REGNUM))
12533 (use (match_operand:P 3 "memory_operand" "m,m"))
12534 (set (reg:P TOC_REGNUM) (match_dup 3))
12535 (clobber (reg:P LR_REGNO))]
12536 "DEFAULT_ABI == ABI_AIX && reload_completed && !TARGET_R11"
12537 "b%T1l\;<ptrload> 2,%3"
12538 [(set_attr "type" "jmpreg")
12539 (set_attr "length" "8")])
12540
12541 ;; Call to function which may be in another module. Restore the TOC
12542 ;; pointer (r2) after the call unless this is System V.
12543 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12544 ;; either the function was not prototyped, or it was prototyped as a
12545 ;; variable argument function. It is > 0 if FP registers were passed
12546 ;; and < 0 if they were not.
12547
12548 (define_insn "*call_nonlocal_aix32"
12549 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12550 (match_operand 1 "" "g"))
12551 (use (match_operand:SI 2 "immediate_operand" "O"))
12552 (clobber (reg:SI LR_REGNO))]
12553 "TARGET_32BIT
12554 && DEFAULT_ABI == ABI_AIX
12555 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12556 "bl %z0\;%."
12557 [(set_attr "type" "branch")
12558 (set_attr "length" "8")])
12559
12560 (define_insn "*call_nonlocal_aix64"
12561 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12562 (match_operand 1 "" "g"))
12563 (use (match_operand:SI 2 "immediate_operand" "O"))
12564 (clobber (reg:SI LR_REGNO))]
12565 "TARGET_64BIT
12566 && DEFAULT_ABI == ABI_AIX
12567 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12568 "bl %z0\;%."
12569 [(set_attr "type" "branch")
12570 (set_attr "length" "8")])
12571
12572 (define_insn "*call_value_nonlocal_aix32"
12573 [(set (match_operand 0 "" "")
12574 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12575 (match_operand 2 "" "g")))
12576 (use (match_operand:SI 3 "immediate_operand" "O"))
12577 (clobber (reg:SI LR_REGNO))]
12578 "TARGET_32BIT
12579 && DEFAULT_ABI == ABI_AIX
12580 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12581 "bl %z1\;%."
12582 [(set_attr "type" "branch")
12583 (set_attr "length" "8")])
12584
12585 (define_insn "*call_value_nonlocal_aix64"
12586 [(set (match_operand 0 "" "")
12587 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12588 (match_operand 2 "" "g")))
12589 (use (match_operand:SI 3 "immediate_operand" "O"))
12590 (clobber (reg:SI LR_REGNO))]
12591 "TARGET_64BIT
12592 && DEFAULT_ABI == ABI_AIX
12593 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12594 "bl %z1\;%."
12595 [(set_attr "type" "branch")
12596 (set_attr "length" "8")])
12597
12598 ;; A function pointer under System V is just a normal pointer
12599 ;; operands[0] is the function pointer
12600 ;; operands[1] is the stack size to clean up
12601 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12602 ;; which indicates how to set cr1
12603
12604 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12605 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12606 (match_operand 1 "" "g,g,g,g"))
12607 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12608 (clobber (reg:SI LR_REGNO))]
12609 "DEFAULT_ABI == ABI_V4
12610 || DEFAULT_ABI == ABI_DARWIN"
12611 {
12612 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12613 output_asm_insn ("crxor 6,6,6", operands);
12614
12615 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12616 output_asm_insn ("creqv 6,6,6", operands);
12617
12618 return "b%T0l";
12619 }
12620 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12621 (set_attr "length" "4,4,8,8")])
12622
12623 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12624 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12625 (match_operand 1 "" "g,g"))
12626 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12627 (clobber (reg:SI LR_REGNO))]
12628 "(DEFAULT_ABI == ABI_DARWIN
12629 || (DEFAULT_ABI == ABI_V4
12630 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12631 {
12632 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12633 output_asm_insn ("crxor 6,6,6", operands);
12634
12635 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12636 output_asm_insn ("creqv 6,6,6", operands);
12637
12638 #if TARGET_MACHO
12639 return output_call(insn, operands, 0, 2);
12640 #else
12641 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12642 {
12643 gcc_assert (!TARGET_SECURE_PLT);
12644 return "bl %z0@plt";
12645 }
12646 else
12647 return "bl %z0";
12648 #endif
12649 }
12650 "DEFAULT_ABI == ABI_V4
12651 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12652 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12653 [(parallel [(call (mem:SI (match_dup 0))
12654 (match_dup 1))
12655 (use (match_dup 2))
12656 (use (match_dup 3))
12657 (clobber (reg:SI LR_REGNO))])]
12658 {
12659 operands[3] = pic_offset_table_rtx;
12660 }
12661 [(set_attr "type" "branch,branch")
12662 (set_attr "length" "4,8")])
12663
12664 (define_insn "*call_nonlocal_sysv_secure<mode>"
12665 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12666 (match_operand 1 "" "g,g"))
12667 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12668 (use (match_operand:SI 3 "register_operand" "r,r"))
12669 (clobber (reg:SI LR_REGNO))]
12670 "(DEFAULT_ABI == ABI_V4
12671 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12672 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12673 {
12674 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12675 output_asm_insn ("crxor 6,6,6", operands);
12676
12677 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12678 output_asm_insn ("creqv 6,6,6", operands);
12679
12680 if (flag_pic == 2)
12681 /* The magic 32768 offset here and in the other sysv call insns
12682 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12683 See sysv4.h:toc_section. */
12684 return "bl %z0+32768@plt";
12685 else
12686 return "bl %z0@plt";
12687 }
12688 [(set_attr "type" "branch,branch")
12689 (set_attr "length" "4,8")])
12690
12691 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12692 [(set (match_operand 0 "" "")
12693 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12694 (match_operand 2 "" "g,g,g,g")))
12695 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12696 (clobber (reg:SI LR_REGNO))]
12697 "DEFAULT_ABI == ABI_V4
12698 || DEFAULT_ABI == ABI_DARWIN"
12699 {
12700 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12701 output_asm_insn ("crxor 6,6,6", operands);
12702
12703 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12704 output_asm_insn ("creqv 6,6,6", operands);
12705
12706 return "b%T1l";
12707 }
12708 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12709 (set_attr "length" "4,4,8,8")])
12710
12711 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12712 [(set (match_operand 0 "" "")
12713 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12714 (match_operand 2 "" "g,g")))
12715 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12716 (clobber (reg:SI LR_REGNO))]
12717 "(DEFAULT_ABI == ABI_DARWIN
12718 || (DEFAULT_ABI == ABI_V4
12719 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12720 {
12721 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12722 output_asm_insn ("crxor 6,6,6", operands);
12723
12724 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12725 output_asm_insn ("creqv 6,6,6", operands);
12726
12727 #if TARGET_MACHO
12728 return output_call(insn, operands, 1, 3);
12729 #else
12730 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12731 {
12732 gcc_assert (!TARGET_SECURE_PLT);
12733 return "bl %z1@plt";
12734 }
12735 else
12736 return "bl %z1";
12737 #endif
12738 }
12739 "DEFAULT_ABI == ABI_V4
12740 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12741 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12742 [(parallel [(set (match_dup 0)
12743 (call (mem:SI (match_dup 1))
12744 (match_dup 2)))
12745 (use (match_dup 3))
12746 (use (match_dup 4))
12747 (clobber (reg:SI LR_REGNO))])]
12748 {
12749 operands[4] = pic_offset_table_rtx;
12750 }
12751 [(set_attr "type" "branch,branch")
12752 (set_attr "length" "4,8")])
12753
12754 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12755 [(set (match_operand 0 "" "")
12756 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12757 (match_operand 2 "" "g,g")))
12758 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12759 (use (match_operand:SI 4 "register_operand" "r,r"))
12760 (clobber (reg:SI LR_REGNO))]
12761 "(DEFAULT_ABI == ABI_V4
12762 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12763 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12764 {
12765 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12766 output_asm_insn ("crxor 6,6,6", operands);
12767
12768 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12769 output_asm_insn ("creqv 6,6,6", operands);
12770
12771 if (flag_pic == 2)
12772 return "bl %z1+32768@plt";
12773 else
12774 return "bl %z1@plt";
12775 }
12776 [(set_attr "type" "branch,branch")
12777 (set_attr "length" "4,8")])
12778
12779 ;; Call subroutine returning any type.
12780 (define_expand "untyped_call"
12781 [(parallel [(call (match_operand 0 "" "")
12782 (const_int 0))
12783 (match_operand 1 "" "")
12784 (match_operand 2 "" "")])]
12785 ""
12786 "
12787 {
12788 int i;
12789
12790 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12791
12792 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12793 {
12794 rtx set = XVECEXP (operands[2], 0, i);
12795 emit_move_insn (SET_DEST (set), SET_SRC (set));
12796 }
12797
12798 /* The optimizer does not know that the call sets the function value
12799 registers we stored in the result block. We avoid problems by
12800 claiming that all hard registers are used and clobbered at this
12801 point. */
12802 emit_insn (gen_blockage ());
12803
12804 DONE;
12805 }")
12806
12807 ;; sibling call patterns
12808 (define_expand "sibcall"
12809 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12810 (match_operand 1 "" ""))
12811 (use (match_operand 2 "" ""))
12812 (use (reg:SI LR_REGNO))
12813 (return)])]
12814 ""
12815 "
12816 {
12817 #if TARGET_MACHO
12818 if (MACHOPIC_INDIRECT)
12819 operands[0] = machopic_indirect_call_target (operands[0]);
12820 #endif
12821
12822 gcc_assert (GET_CODE (operands[0]) == MEM);
12823 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12824
12825 operands[0] = XEXP (operands[0], 0);
12826 }")
12827
12828 ;; this and similar patterns must be marked as using LR, otherwise
12829 ;; dataflow will try to delete the store into it. This is true
12830 ;; even when the actual reg to jump to is in CTR, when LR was
12831 ;; saved and restored around the PIC-setting BCL.
12832 (define_insn "*sibcall_local32"
12833 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12834 (match_operand 1 "" "g,g"))
12835 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12836 (use (reg:SI LR_REGNO))
12837 (return)]
12838 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12839 "*
12840 {
12841 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12842 output_asm_insn (\"crxor 6,6,6\", operands);
12843
12844 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12845 output_asm_insn (\"creqv 6,6,6\", operands);
12846
12847 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12848 }"
12849 [(set_attr "type" "branch")
12850 (set_attr "length" "4,8")])
12851
12852 (define_insn "*sibcall_local64"
12853 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12854 (match_operand 1 "" "g,g"))
12855 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12856 (use (reg:SI LR_REGNO))
12857 (return)]
12858 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12859 "*
12860 {
12861 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12862 output_asm_insn (\"crxor 6,6,6\", operands);
12863
12864 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12865 output_asm_insn (\"creqv 6,6,6\", operands);
12866
12867 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12868 }"
12869 [(set_attr "type" "branch")
12870 (set_attr "length" "4,8")])
12871
12872 (define_insn "*sibcall_value_local32"
12873 [(set (match_operand 0 "" "")
12874 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12875 (match_operand 2 "" "g,g")))
12876 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12877 (use (reg:SI LR_REGNO))
12878 (return)]
12879 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12880 "*
12881 {
12882 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12883 output_asm_insn (\"crxor 6,6,6\", operands);
12884
12885 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12886 output_asm_insn (\"creqv 6,6,6\", operands);
12887
12888 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12889 }"
12890 [(set_attr "type" "branch")
12891 (set_attr "length" "4,8")])
12892
12893
12894 (define_insn "*sibcall_value_local64"
12895 [(set (match_operand 0 "" "")
12896 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12897 (match_operand 2 "" "g,g")))
12898 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12899 (use (reg:SI LR_REGNO))
12900 (return)]
12901 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12902 "*
12903 {
12904 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12905 output_asm_insn (\"crxor 6,6,6\", operands);
12906
12907 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12908 output_asm_insn (\"creqv 6,6,6\", operands);
12909
12910 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12911 }"
12912 [(set_attr "type" "branch")
12913 (set_attr "length" "4,8")])
12914
12915 (define_insn "*sibcall_nonlocal_aix<mode>"
12916 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12917 (match_operand 1 "" "g,g"))
12918 (use (match_operand:SI 2 "immediate_operand" "O,O"))
12919 (use (reg:SI LR_REGNO))
12920 (return)]
12921 "DEFAULT_ABI == ABI_AIX
12922 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12923 "@
12924 b %z0
12925 b%T0"
12926 [(set_attr "type" "branch")
12927 (set_attr "length" "4")])
12928
12929 (define_insn "*sibcall_value_nonlocal_aix<mode>"
12930 [(set (match_operand 0 "" "")
12931 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12932 (match_operand 2 "" "g,g")))
12933 (use (match_operand:SI 3 "immediate_operand" "O,O"))
12934 (use (reg:SI LR_REGNO))
12935 (return)]
12936 "DEFAULT_ABI == ABI_AIX
12937 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12938 "@
12939 b %z1
12940 b%T1"
12941 [(set_attr "type" "branch")
12942 (set_attr "length" "4")])
12943
12944 (define_insn "*sibcall_nonlocal_sysv<mode>"
12945 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12946 (match_operand 1 "" ""))
12947 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12948 (use (reg:SI LR_REGNO))
12949 (return)]
12950 "(DEFAULT_ABI == ABI_DARWIN
12951 || DEFAULT_ABI == ABI_V4)
12952 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12953 "*
12954 {
12955 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12956 output_asm_insn (\"crxor 6,6,6\", operands);
12957
12958 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12959 output_asm_insn (\"creqv 6,6,6\", operands);
12960
12961 if (which_alternative >= 2)
12962 return \"b%T0\";
12963 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12964 {
12965 gcc_assert (!TARGET_SECURE_PLT);
12966 return \"b %z0@plt\";
12967 }
12968 else
12969 return \"b %z0\";
12970 }"
12971 [(set_attr "type" "branch")
12972 (set_attr "length" "4,8,4,8")])
12973
12974 (define_expand "sibcall_value"
12975 [(parallel [(set (match_operand 0 "register_operand" "")
12976 (call (mem:SI (match_operand 1 "address_operand" ""))
12977 (match_operand 2 "" "")))
12978 (use (match_operand 3 "" ""))
12979 (use (reg:SI LR_REGNO))
12980 (return)])]
12981 ""
12982 "
12983 {
12984 #if TARGET_MACHO
12985 if (MACHOPIC_INDIRECT)
12986 operands[1] = machopic_indirect_call_target (operands[1]);
12987 #endif
12988
12989 gcc_assert (GET_CODE (operands[1]) == MEM);
12990 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12991
12992 operands[1] = XEXP (operands[1], 0);
12993 }")
12994
12995 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12996 [(set (match_operand 0 "" "")
12997 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12998 (match_operand 2 "" "")))
12999 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
13000 (use (reg:SI LR_REGNO))
13001 (return)]
13002 "(DEFAULT_ABI == ABI_DARWIN
13003 || DEFAULT_ABI == ABI_V4)
13004 && (INTVAL (operands[3]) & CALL_LONG) == 0"
13005 "*
13006 {
13007 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
13008 output_asm_insn (\"crxor 6,6,6\", operands);
13009
13010 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
13011 output_asm_insn (\"creqv 6,6,6\", operands);
13012
13013 if (which_alternative >= 2)
13014 return \"b%T1\";
13015 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
13016 {
13017 gcc_assert (!TARGET_SECURE_PLT);
13018 return \"b %z1@plt\";
13019 }
13020 else
13021 return \"b %z1\";
13022 }"
13023 [(set_attr "type" "branch")
13024 (set_attr "length" "4,8,4,8")])
13025
13026 (define_expand "sibcall_epilogue"
13027 [(use (const_int 0))]
13028 "TARGET_SCHED_PROLOG"
13029 "
13030 {
13031 rs6000_emit_epilogue (TRUE);
13032 DONE;
13033 }")
13034
13035 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13036 ;; all of memory. This blocks insns from being moved across this point.
13037
13038 (define_insn "blockage"
13039 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
13040 ""
13041 "")
13042
13043 (define_insn "probe_stack"
13044 [(set (match_operand 0 "memory_operand" "=m")
13045 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
13046 ""
13047 "{st%U0%X0|stw%U0%X0} 0,%0"
13048 [(set_attr "type" "store")
13049 (set_attr "length" "4")])
13050
13051 (define_insn "probe_stack_range<P:mode>"
13052 [(set (match_operand:P 0 "register_operand" "=r")
13053 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
13054 (match_operand:P 2 "register_operand" "r")]
13055 UNSPECV_PROBE_STACK_RANGE))]
13056 ""
13057 "* return output_probe_stack_range (operands[0], operands[2]);"
13058 [(set_attr "type" "three")])
13059 \f
13060 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
13061 ;; signed & unsigned, and one type of branch.
13062 ;;
13063 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
13064 ;; insns, and branches.
13065
13066 (define_expand "cbranch<mode>4"
13067 [(use (match_operator 0 "rs6000_cbranch_operator"
13068 [(match_operand:GPR 1 "gpc_reg_operand" "")
13069 (match_operand:GPR 2 "reg_or_short_operand" "")]))
13070 (use (match_operand 3 ""))]
13071 ""
13072 "
13073 {
13074 /* Take care of the possibility that operands[2] might be negative but
13075 this might be a logical operation. That insn doesn't exist. */
13076 if (GET_CODE (operands[2]) == CONST_INT
13077 && INTVAL (operands[2]) < 0)
13078 {
13079 operands[2] = force_reg (<MODE>mode, operands[2]);
13080 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
13081 GET_MODE (operands[0]),
13082 operands[1], operands[2]);
13083 }
13084
13085 rs6000_emit_cbranch (<MODE>mode, operands);
13086 DONE;
13087 }")
13088
13089 (define_expand "cbranch<mode>4"
13090 [(use (match_operator 0 "rs6000_cbranch_operator"
13091 [(match_operand:FP 1 "gpc_reg_operand" "")
13092 (match_operand:FP 2 "gpc_reg_operand" "")]))
13093 (use (match_operand 3 ""))]
13094 ""
13095 "
13096 {
13097 rs6000_emit_cbranch (<MODE>mode, operands);
13098 DONE;
13099 }")
13100
13101 (define_expand "cstore<mode>4"
13102 [(use (match_operator 1 "rs6000_cbranch_operator"
13103 [(match_operand:GPR 2 "gpc_reg_operand" "")
13104 (match_operand:GPR 3 "reg_or_short_operand" "")]))
13105 (clobber (match_operand:SI 0 "register_operand"))]
13106 ""
13107 "
13108 {
13109 /* Take care of the possibility that operands[3] might be negative but
13110 this might be a logical operation. That insn doesn't exist. */
13111 if (GET_CODE (operands[3]) == CONST_INT
13112 && INTVAL (operands[3]) < 0)
13113 {
13114 operands[3] = force_reg (<MODE>mode, operands[3]);
13115 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
13116 GET_MODE (operands[1]),
13117 operands[2], operands[3]);
13118 }
13119
13120 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
13121 For SEQ, likewise, except that comparisons with zero should be done
13122 with an scc insns. However, due to the order that combine see the
13123 resulting insns, we must, in fact, allow SEQ for integers. Fail in
13124 the cases we don't want to handle or are best handled by portable
13125 code. */
13126 if (GET_CODE (operands[1]) == NE)
13127 FAIL;
13128 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
13129 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
13130 && operands[3] == const0_rtx)
13131 FAIL;
13132 rs6000_emit_sCOND (<MODE>mode, operands);
13133 DONE;
13134 }")
13135
13136 (define_expand "cstore<mode>4"
13137 [(use (match_operator 1 "rs6000_cbranch_operator"
13138 [(match_operand:FP 2 "gpc_reg_operand" "")
13139 (match_operand:FP 3 "gpc_reg_operand" "")]))
13140 (clobber (match_operand:SI 0 "register_operand"))]
13141 ""
13142 "
13143 {
13144 rs6000_emit_sCOND (<MODE>mode, operands);
13145 DONE;
13146 }")
13147
13148
13149 (define_expand "stack_protect_set"
13150 [(match_operand 0 "memory_operand" "")
13151 (match_operand 1 "memory_operand" "")]
13152 ""
13153 {
13154 #ifdef TARGET_THREAD_SSP_OFFSET
13155 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13156 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13157 operands[1] = gen_rtx_MEM (Pmode, addr);
13158 #endif
13159 if (TARGET_64BIT)
13160 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
13161 else
13162 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
13163 DONE;
13164 })
13165
13166 (define_insn "stack_protect_setsi"
13167 [(set (match_operand:SI 0 "memory_operand" "=m")
13168 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13169 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13170 "TARGET_32BIT"
13171 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
13172 [(set_attr "type" "three")
13173 (set_attr "length" "12")])
13174
13175 (define_insn "stack_protect_setdi"
13176 [(set (match_operand:DI 0 "memory_operand" "=m")
13177 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13178 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13179 "TARGET_64BIT"
13180 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
13181 [(set_attr "type" "three")
13182 (set_attr "length" "12")])
13183
13184 (define_expand "stack_protect_test"
13185 [(match_operand 0 "memory_operand" "")
13186 (match_operand 1 "memory_operand" "")
13187 (match_operand 2 "" "")]
13188 ""
13189 {
13190 rtx test, op0, op1;
13191 #ifdef TARGET_THREAD_SSP_OFFSET
13192 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13193 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13194 operands[1] = gen_rtx_MEM (Pmode, addr);
13195 #endif
13196 op0 = operands[0];
13197 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
13198 test = gen_rtx_EQ (VOIDmode, op0, op1);
13199 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
13200 DONE;
13201 })
13202
13203 (define_insn "stack_protect_testsi"
13204 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13205 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13206 (match_operand:SI 2 "memory_operand" "m,m")]
13207 UNSPEC_SP_TEST))
13208 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13209 (clobber (match_scratch:SI 3 "=&r,&r"))]
13210 "TARGET_32BIT"
13211 "@
13212 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13213 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13214 [(set_attr "length" "16,20")])
13215
13216 (define_insn "stack_protect_testdi"
13217 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13218 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
13219 (match_operand:DI 2 "memory_operand" "m,m")]
13220 UNSPEC_SP_TEST))
13221 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13222 (clobber (match_scratch:DI 3 "=&r,&r"))]
13223 "TARGET_64BIT"
13224 "@
13225 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13226 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13227 [(set_attr "length" "16,20")])
13228
13229 \f
13230 ;; Here are the actual compare insns.
13231 (define_insn "*cmp<mode>_internal1"
13232 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13233 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13234 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13235 ""
13236 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
13237 [(set_attr "type" "cmp")])
13238
13239 ;; If we are comparing a register for equality with a large constant,
13240 ;; we can do this with an XOR followed by a compare. But this is profitable
13241 ;; only if the large constant is only used for the comparison (and in this
13242 ;; case we already have a register to reuse as scratch).
13243 ;;
13244 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13245 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13246
13247 (define_peephole2
13248 [(set (match_operand:SI 0 "register_operand")
13249 (match_operand:SI 1 "logical_const_operand" ""))
13250 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13251 [(match_dup 0)
13252 (match_operand:SI 2 "logical_const_operand" "")]))
13253 (set (match_operand:CC 4 "cc_reg_operand" "")
13254 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13255 (match_dup 0)))
13256 (set (pc)
13257 (if_then_else (match_operator 6 "equality_operator"
13258 [(match_dup 4) (const_int 0)])
13259 (match_operand 7 "" "")
13260 (match_operand 8 "" "")))]
13261 "peep2_reg_dead_p (3, operands[0])
13262 && peep2_reg_dead_p (4, operands[4])"
13263 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13264 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13265 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13266
13267 {
13268 /* Get the constant we are comparing against, and see what it looks like
13269 when sign-extended from 16 to 32 bits. Then see what constant we could
13270 XOR with SEXTC to get the sign-extended value. */
13271 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13272 SImode,
13273 operands[1], operands[2]);
13274 HOST_WIDE_INT c = INTVAL (cnst);
13275 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13276 HOST_WIDE_INT xorv = c ^ sextc;
13277
13278 operands[9] = GEN_INT (xorv);
13279 operands[10] = GEN_INT (sextc);
13280 })
13281
13282 (define_insn "*cmpsi_internal2"
13283 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13284 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13285 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13286 ""
13287 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
13288 [(set_attr "type" "cmp")])
13289
13290 (define_insn "*cmpdi_internal2"
13291 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13292 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13293 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13294 ""
13295 "cmpld%I2 %0,%1,%b2"
13296 [(set_attr "type" "cmp")])
13297
13298 ;; The following two insns don't exist as single insns, but if we provide
13299 ;; them, we can swap an add and compare, which will enable us to overlap more
13300 ;; of the required delay between a compare and branch. We generate code for
13301 ;; them by splitting.
13302
13303 (define_insn ""
13304 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13305 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13306 (match_operand:SI 2 "short_cint_operand" "i")))
13307 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13308 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13309 ""
13310 "#"
13311 [(set_attr "length" "8")])
13312
13313 (define_insn ""
13314 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13315 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13316 (match_operand:SI 2 "u_short_cint_operand" "i")))
13317 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13318 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13319 ""
13320 "#"
13321 [(set_attr "length" "8")])
13322
13323 (define_split
13324 [(set (match_operand:CC 3 "cc_reg_operand" "")
13325 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13326 (match_operand:SI 2 "short_cint_operand" "")))
13327 (set (match_operand:SI 0 "gpc_reg_operand" "")
13328 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13329 ""
13330 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13331 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13332
13333 (define_split
13334 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13335 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13336 (match_operand:SI 2 "u_short_cint_operand" "")))
13337 (set (match_operand:SI 0 "gpc_reg_operand" "")
13338 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13339 ""
13340 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13341 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13342
13343 (define_insn "*cmpsf_internal1"
13344 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13345 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
13346 (match_operand:SF 2 "gpc_reg_operand" "f")))]
13347 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
13348 "fcmpu %0,%1,%2"
13349 [(set_attr "type" "fpcompare")])
13350
13351 (define_insn "*cmpdf_internal1"
13352 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13353 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
13354 (match_operand:DF 2 "gpc_reg_operand" "d")))]
13355 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
13356 && !VECTOR_UNIT_VSX_P (DFmode)"
13357 "fcmpu %0,%1,%2"
13358 [(set_attr "type" "fpcompare")])
13359
13360 ;; Only need to compare second words if first words equal
13361 (define_insn "*cmptf_internal1"
13362 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13363 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13364 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13365 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13366 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13367 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13368 [(set_attr "type" "fpcompare")
13369 (set_attr "length" "12")])
13370
13371 (define_insn_and_split "*cmptf_internal2"
13372 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13373 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13374 (match_operand:TF 2 "gpc_reg_operand" "d")))
13375 (clobber (match_scratch:DF 3 "=d"))
13376 (clobber (match_scratch:DF 4 "=d"))
13377 (clobber (match_scratch:DF 5 "=d"))
13378 (clobber (match_scratch:DF 6 "=d"))
13379 (clobber (match_scratch:DF 7 "=d"))
13380 (clobber (match_scratch:DF 8 "=d"))
13381 (clobber (match_scratch:DF 9 "=d"))
13382 (clobber (match_scratch:DF 10 "=d"))
13383 (clobber (match_scratch:GPR 11 "=b"))]
13384 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13385 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13386 "#"
13387 "&& reload_completed"
13388 [(set (match_dup 3) (match_dup 14))
13389 (set (match_dup 4) (match_dup 15))
13390 (set (match_dup 9) (abs:DF (match_dup 5)))
13391 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13392 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13393 (label_ref (match_dup 12))
13394 (pc)))
13395 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13396 (set (pc) (label_ref (match_dup 13)))
13397 (match_dup 12)
13398 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13399 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13400 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13401 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13402 (match_dup 13)]
13403 {
13404 REAL_VALUE_TYPE rv;
13405 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
13406 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
13407
13408 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13409 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13410 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13411 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13412 operands[12] = gen_label_rtx ();
13413 operands[13] = gen_label_rtx ();
13414 real_inf (&rv);
13415 operands[14] = force_const_mem (DFmode,
13416 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13417 operands[15] = force_const_mem (DFmode,
13418 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13419 DFmode));
13420 if (TARGET_TOC)
13421 {
13422 rtx tocref;
13423 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13424 operands[14] = gen_const_mem (DFmode, tocref);
13425 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13426 operands[15] = gen_const_mem (DFmode, tocref);
13427 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13428 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13429 }
13430 })
13431 \f
13432 ;; Now we have the scc insns. We can do some combinations because of the
13433 ;; way the machine works.
13434 ;;
13435 ;; Note that this is probably faster if we can put an insn between the
13436 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13437 ;; cases the insns below which don't use an intermediate CR field will
13438 ;; be used instead.
13439 (define_insn ""
13440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13441 (match_operator:SI 1 "scc_comparison_operator"
13442 [(match_operand 2 "cc_reg_operand" "y")
13443 (const_int 0)]))]
13444 ""
13445 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13446 [(set (attr "type")
13447 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13448 (const_string "mfcrf")
13449 ]
13450 (const_string "mfcr")))
13451 (set_attr "length" "8")])
13452
13453 ;; Same as above, but get the GT bit.
13454 (define_insn "move_from_CR_gt_bit"
13455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13456 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13457 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13458 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
13459 [(set_attr "type" "mfcr")
13460 (set_attr "length" "8")])
13461
13462 ;; Same as above, but get the OV/ORDERED bit.
13463 (define_insn "move_from_CR_ov_bit"
13464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13465 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
13466 "TARGET_ISEL"
13467 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
13468 [(set_attr "type" "mfcr")
13469 (set_attr "length" "8")])
13470
13471 (define_insn ""
13472 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13473 (match_operator:DI 1 "scc_comparison_operator"
13474 [(match_operand 2 "cc_reg_operand" "y")
13475 (const_int 0)]))]
13476 "TARGET_POWERPC64"
13477 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13478 [(set (attr "type")
13479 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13480 (const_string "mfcrf")
13481 ]
13482 (const_string "mfcr")))
13483 (set_attr "length" "8")])
13484
13485 (define_insn ""
13486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13487 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13488 [(match_operand 2 "cc_reg_operand" "y,y")
13489 (const_int 0)])
13490 (const_int 0)))
13491 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13492 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13493 "TARGET_32BIT"
13494 "@
13495 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13496 #"
13497 [(set_attr "type" "delayed_compare")
13498 (set_attr "length" "8,16")])
13499
13500 (define_split
13501 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13502 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13503 [(match_operand 2 "cc_reg_operand" "")
13504 (const_int 0)])
13505 (const_int 0)))
13506 (set (match_operand:SI 3 "gpc_reg_operand" "")
13507 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13508 "TARGET_32BIT && reload_completed"
13509 [(set (match_dup 3)
13510 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13511 (set (match_dup 0)
13512 (compare:CC (match_dup 3)
13513 (const_int 0)))]
13514 "")
13515
13516 (define_insn ""
13517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13518 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13519 [(match_operand 2 "cc_reg_operand" "y")
13520 (const_int 0)])
13521 (match_operand:SI 3 "const_int_operand" "n")))]
13522 ""
13523 "*
13524 {
13525 int is_bit = ccr_bit (operands[1], 1);
13526 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13527 int count;
13528
13529 if (is_bit >= put_bit)
13530 count = is_bit - put_bit;
13531 else
13532 count = 32 - (put_bit - is_bit);
13533
13534 operands[4] = GEN_INT (count);
13535 operands[5] = GEN_INT (put_bit);
13536
13537 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13538 }"
13539 [(set (attr "type")
13540 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13541 (const_string "mfcrf")
13542 ]
13543 (const_string "mfcr")))
13544 (set_attr "length" "8")])
13545
13546 (define_insn ""
13547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13548 (compare:CC
13549 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13550 [(match_operand 2 "cc_reg_operand" "y,y")
13551 (const_int 0)])
13552 (match_operand:SI 3 "const_int_operand" "n,n"))
13553 (const_int 0)))
13554 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13555 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13556 (match_dup 3)))]
13557 ""
13558 "*
13559 {
13560 int is_bit = ccr_bit (operands[1], 1);
13561 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13562 int count;
13563
13564 /* Force split for non-cc0 compare. */
13565 if (which_alternative == 1)
13566 return \"#\";
13567
13568 if (is_bit >= put_bit)
13569 count = is_bit - put_bit;
13570 else
13571 count = 32 - (put_bit - is_bit);
13572
13573 operands[5] = GEN_INT (count);
13574 operands[6] = GEN_INT (put_bit);
13575
13576 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13577 }"
13578 [(set_attr "type" "delayed_compare")
13579 (set_attr "length" "8,16")])
13580
13581 (define_split
13582 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13583 (compare:CC
13584 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13585 [(match_operand 2 "cc_reg_operand" "")
13586 (const_int 0)])
13587 (match_operand:SI 3 "const_int_operand" ""))
13588 (const_int 0)))
13589 (set (match_operand:SI 4 "gpc_reg_operand" "")
13590 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13591 (match_dup 3)))]
13592 "reload_completed"
13593 [(set (match_dup 4)
13594 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13595 (match_dup 3)))
13596 (set (match_dup 0)
13597 (compare:CC (match_dup 4)
13598 (const_int 0)))]
13599 "")
13600
13601 ;; There is a 3 cycle delay between consecutive mfcr instructions
13602 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13603
13604 (define_peephole
13605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13606 (match_operator:SI 1 "scc_comparison_operator"
13607 [(match_operand 2 "cc_reg_operand" "y")
13608 (const_int 0)]))
13609 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13610 (match_operator:SI 4 "scc_comparison_operator"
13611 [(match_operand 5 "cc_reg_operand" "y")
13612 (const_int 0)]))]
13613 "REGNO (operands[2]) != REGNO (operands[5])"
13614 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13615 [(set_attr "type" "mfcr")
13616 (set_attr "length" "12")])
13617
13618 (define_peephole
13619 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13620 (match_operator:DI 1 "scc_comparison_operator"
13621 [(match_operand 2 "cc_reg_operand" "y")
13622 (const_int 0)]))
13623 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13624 (match_operator:DI 4 "scc_comparison_operator"
13625 [(match_operand 5 "cc_reg_operand" "y")
13626 (const_int 0)]))]
13627 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13628 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13629 [(set_attr "type" "mfcr")
13630 (set_attr "length" "12")])
13631
13632 ;; There are some scc insns that can be done directly, without a compare.
13633 ;; These are faster because they don't involve the communications between
13634 ;; the FXU and branch units. In fact, we will be replacing all of the
13635 ;; integer scc insns here or in the portable methods in emit_store_flag.
13636 ;;
13637 ;; Also support (neg (scc ..)) since that construct is used to replace
13638 ;; branches, (plus (scc ..) ..) since that construct is common and
13639 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13640 ;; cases where it is no more expensive than (neg (scc ..)).
13641
13642 ;; Have reload force a constant into a register for the simple insns that
13643 ;; otherwise won't accept constants. We do this because it is faster than
13644 ;; the cmp/mfcr sequence we would otherwise generate.
13645
13646 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13647 (DI "rKJI")])
13648
13649 (define_insn_and_split "*eq<mode>"
13650 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13651 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13652 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13653 "!TARGET_POWER"
13654 "#"
13655 "!TARGET_POWER"
13656 [(set (match_dup 0)
13657 (clz:GPR (match_dup 3)))
13658 (set (match_dup 0)
13659 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13660 {
13661 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13662 {
13663 /* Use output operand as intermediate. */
13664 operands[3] = operands[0];
13665
13666 if (logical_operand (operands[2], <MODE>mode))
13667 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13668 gen_rtx_XOR (<MODE>mode,
13669 operands[1], operands[2])));
13670 else
13671 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13672 gen_rtx_PLUS (<MODE>mode, operands[1],
13673 negate_rtx (<MODE>mode,
13674 operands[2]))));
13675 }
13676 else
13677 operands[3] = operands[1];
13678
13679 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13680 })
13681
13682 (define_insn_and_split "*eq<mode>_compare"
13683 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13684 (compare:CC
13685 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13686 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13687 (const_int 0)))
13688 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13689 (eq:P (match_dup 1) (match_dup 2)))]
13690 "!TARGET_POWER && optimize_size"
13691 "#"
13692 "!TARGET_POWER && optimize_size"
13693 [(set (match_dup 0)
13694 (clz:P (match_dup 4)))
13695 (parallel [(set (match_dup 3)
13696 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13697 (const_int 0)))
13698 (set (match_dup 0)
13699 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13700 {
13701 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13702 {
13703 /* Use output operand as intermediate. */
13704 operands[4] = operands[0];
13705
13706 if (logical_operand (operands[2], <MODE>mode))
13707 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13708 gen_rtx_XOR (<MODE>mode,
13709 operands[1], operands[2])));
13710 else
13711 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13712 gen_rtx_PLUS (<MODE>mode, operands[1],
13713 negate_rtx (<MODE>mode,
13714 operands[2]))));
13715 }
13716 else
13717 operands[4] = operands[1];
13718
13719 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13720 })
13721
13722 (define_insn "*eqsi_power"
13723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13724 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13725 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13726 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13727 "TARGET_POWER"
13728 "@
13729 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13730 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13731 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13732 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13733 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13734 [(set_attr "type" "three,two,three,three,three")
13735 (set_attr "length" "12,8,12,12,12")])
13736
13737 ;; We have insns of the form shown by the first define_insn below. If
13738 ;; there is something inside the comparison operation, we must split it.
13739 (define_split
13740 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13741 (plus:SI (match_operator 1 "comparison_operator"
13742 [(match_operand:SI 2 "" "")
13743 (match_operand:SI 3
13744 "reg_or_cint_operand" "")])
13745 (match_operand:SI 4 "gpc_reg_operand" "")))
13746 (clobber (match_operand:SI 5 "register_operand" ""))]
13747 "! gpc_reg_operand (operands[2], SImode)"
13748 [(set (match_dup 5) (match_dup 2))
13749 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13750 (match_dup 4)))])
13751
13752 (define_insn "*plus_eqsi"
13753 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13754 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13755 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13756 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13757 "TARGET_32BIT"
13758 "@
13759 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13760 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13761 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13762 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13763 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13764 [(set_attr "type" "three,two,three,three,three")
13765 (set_attr "length" "12,8,12,12,12")])
13766
13767 (define_insn "*compare_plus_eqsi"
13768 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13769 (compare:CC
13770 (plus:SI
13771 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13772 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13773 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13774 (const_int 0)))
13775 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13776 "TARGET_32BIT && optimize_size"
13777 "@
13778 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13779 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13780 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13781 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13782 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13783 #
13784 #
13785 #
13786 #
13787 #"
13788 [(set_attr "type" "compare")
13789 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13790
13791 (define_split
13792 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13793 (compare:CC
13794 (plus:SI
13795 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13796 (match_operand:SI 2 "scc_eq_operand" ""))
13797 (match_operand:SI 3 "gpc_reg_operand" ""))
13798 (const_int 0)))
13799 (clobber (match_scratch:SI 4 ""))]
13800 "TARGET_32BIT && optimize_size && reload_completed"
13801 [(set (match_dup 4)
13802 (plus:SI (eq:SI (match_dup 1)
13803 (match_dup 2))
13804 (match_dup 3)))
13805 (set (match_dup 0)
13806 (compare:CC (match_dup 4)
13807 (const_int 0)))]
13808 "")
13809
13810 (define_insn "*plus_eqsi_compare"
13811 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13812 (compare:CC
13813 (plus:SI
13814 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13815 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13816 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13817 (const_int 0)))
13818 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13819 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13820 "TARGET_32BIT && optimize_size"
13821 "@
13822 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13823 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13824 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13825 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13826 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13827 #
13828 #
13829 #
13830 #
13831 #"
13832 [(set_attr "type" "compare")
13833 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13834
13835 (define_split
13836 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13837 (compare:CC
13838 (plus:SI
13839 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13840 (match_operand:SI 2 "scc_eq_operand" ""))
13841 (match_operand:SI 3 "gpc_reg_operand" ""))
13842 (const_int 0)))
13843 (set (match_operand:SI 0 "gpc_reg_operand" "")
13844 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13845 "TARGET_32BIT && optimize_size && reload_completed"
13846 [(set (match_dup 0)
13847 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13848 (set (match_dup 4)
13849 (compare:CC (match_dup 0)
13850 (const_int 0)))]
13851 "")
13852
13853 (define_insn "*neg_eq0<mode>"
13854 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13855 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13856 (const_int 0))))]
13857 ""
13858 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13859 [(set_attr "type" "two")
13860 (set_attr "length" "8")])
13861
13862 (define_insn_and_split "*neg_eq<mode>"
13863 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13864 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13865 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13866 ""
13867 "#"
13868 ""
13869 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13870 {
13871 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13872 {
13873 /* Use output operand as intermediate. */
13874 operands[3] = operands[0];
13875
13876 if (logical_operand (operands[2], <MODE>mode))
13877 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13878 gen_rtx_XOR (<MODE>mode,
13879 operands[1], operands[2])));
13880 else
13881 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13882 gen_rtx_PLUS (<MODE>mode, operands[1],
13883 negate_rtx (<MODE>mode,
13884 operands[2]))));
13885 }
13886 else
13887 operands[3] = operands[1];
13888 })
13889
13890 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13891 ;; since it nabs/sr is just as fast.
13892 (define_insn "*ne0si"
13893 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13894 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13895 (const_int 31)))
13896 (clobber (match_scratch:SI 2 "=&r"))]
13897 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13898 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13899 [(set_attr "type" "two")
13900 (set_attr "length" "8")])
13901
13902 (define_insn "*ne0di"
13903 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13904 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13905 (const_int 63)))
13906 (clobber (match_scratch:DI 2 "=&r"))]
13907 "TARGET_64BIT"
13908 "addic %2,%1,-1\;subfe %0,%2,%1"
13909 [(set_attr "type" "two")
13910 (set_attr "length" "8")])
13911
13912 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13913 (define_insn "*plus_ne0si"
13914 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13915 (plus:SI (lshiftrt:SI
13916 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13917 (const_int 31))
13918 (match_operand:SI 2 "gpc_reg_operand" "r")))
13919 (clobber (match_scratch:SI 3 "=&r"))]
13920 "TARGET_32BIT"
13921 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13922 [(set_attr "type" "two")
13923 (set_attr "length" "8")])
13924
13925 (define_insn "*plus_ne0di"
13926 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13927 (plus:DI (lshiftrt:DI
13928 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13929 (const_int 63))
13930 (match_operand:DI 2 "gpc_reg_operand" "r")))
13931 (clobber (match_scratch:DI 3 "=&r"))]
13932 "TARGET_64BIT"
13933 "addic %3,%1,-1\;addze %0,%2"
13934 [(set_attr "type" "two")
13935 (set_attr "length" "8")])
13936
13937 (define_insn "*compare_plus_ne0si"
13938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13939 (compare:CC
13940 (plus:SI (lshiftrt:SI
13941 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13942 (const_int 31))
13943 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13944 (const_int 0)))
13945 (clobber (match_scratch:SI 3 "=&r,&r"))
13946 (clobber (match_scratch:SI 4 "=X,&r"))]
13947 "TARGET_32BIT"
13948 "@
13949 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13950 #"
13951 [(set_attr "type" "compare")
13952 (set_attr "length" "8,12")])
13953
13954 (define_split
13955 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13956 (compare:CC
13957 (plus:SI (lshiftrt:SI
13958 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13959 (const_int 31))
13960 (match_operand:SI 2 "gpc_reg_operand" ""))
13961 (const_int 0)))
13962 (clobber (match_scratch:SI 3 ""))
13963 (clobber (match_scratch:SI 4 ""))]
13964 "TARGET_32BIT && reload_completed"
13965 [(parallel [(set (match_dup 3)
13966 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13967 (const_int 31))
13968 (match_dup 2)))
13969 (clobber (match_dup 4))])
13970 (set (match_dup 0)
13971 (compare:CC (match_dup 3)
13972 (const_int 0)))]
13973 "")
13974
13975 (define_insn "*compare_plus_ne0di"
13976 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13977 (compare:CC
13978 (plus:DI (lshiftrt:DI
13979 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13980 (const_int 63))
13981 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13982 (const_int 0)))
13983 (clobber (match_scratch:DI 3 "=&r,&r"))]
13984 "TARGET_64BIT"
13985 "@
13986 addic %3,%1,-1\;addze. %3,%2
13987 #"
13988 [(set_attr "type" "compare")
13989 (set_attr "length" "8,12")])
13990
13991 (define_split
13992 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13993 (compare:CC
13994 (plus:DI (lshiftrt:DI
13995 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13996 (const_int 63))
13997 (match_operand:DI 2 "gpc_reg_operand" ""))
13998 (const_int 0)))
13999 (clobber (match_scratch:DI 3 ""))]
14000 "TARGET_64BIT && reload_completed"
14001 [(set (match_dup 3)
14002 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
14003 (const_int 63))
14004 (match_dup 2)))
14005 (set (match_dup 0)
14006 (compare:CC (match_dup 3)
14007 (const_int 0)))]
14008 "")
14009
14010 (define_insn "*plus_ne0si_compare"
14011 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14012 (compare:CC
14013 (plus:SI (lshiftrt:SI
14014 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
14015 (const_int 31))
14016 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14017 (const_int 0)))
14018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14019 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14020 (match_dup 2)))
14021 (clobber (match_scratch:SI 3 "=&r,&r"))]
14022 "TARGET_32BIT"
14023 "@
14024 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
14025 #"
14026 [(set_attr "type" "compare")
14027 (set_attr "length" "8,12")])
14028
14029 (define_split
14030 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14031 (compare:CC
14032 (plus:SI (lshiftrt:SI
14033 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14034 (const_int 31))
14035 (match_operand:SI 2 "gpc_reg_operand" ""))
14036 (const_int 0)))
14037 (set (match_operand:SI 0 "gpc_reg_operand" "")
14038 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14039 (match_dup 2)))
14040 (clobber (match_scratch:SI 3 ""))]
14041 "TARGET_32BIT && reload_completed"
14042 [(parallel [(set (match_dup 0)
14043 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14044 (match_dup 2)))
14045 (clobber (match_dup 3))])
14046 (set (match_dup 4)
14047 (compare:CC (match_dup 0)
14048 (const_int 0)))]
14049 "")
14050
14051 (define_insn "*plus_ne0di_compare"
14052 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14053 (compare:CC
14054 (plus:DI (lshiftrt:DI
14055 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14056 (const_int 63))
14057 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14058 (const_int 0)))
14059 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
14060 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14061 (match_dup 2)))
14062 (clobber (match_scratch:DI 3 "=&r,&r"))]
14063 "TARGET_64BIT"
14064 "@
14065 addic %3,%1,-1\;addze. %0,%2
14066 #"
14067 [(set_attr "type" "compare")
14068 (set_attr "length" "8,12")])
14069
14070 (define_split
14071 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
14072 (compare:CC
14073 (plus:DI (lshiftrt:DI
14074 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14075 (const_int 63))
14076 (match_operand:DI 2 "gpc_reg_operand" ""))
14077 (const_int 0)))
14078 (set (match_operand:DI 0 "gpc_reg_operand" "")
14079 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14080 (match_dup 2)))
14081 (clobber (match_scratch:DI 3 ""))]
14082 "TARGET_64BIT && reload_completed"
14083 [(parallel [(set (match_dup 0)
14084 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14085 (match_dup 2)))
14086 (clobber (match_dup 3))])
14087 (set (match_dup 4)
14088 (compare:CC (match_dup 0)
14089 (const_int 0)))]
14090 "")
14091
14092 (define_insn ""
14093 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14094 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14095 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
14096 (clobber (match_scratch:SI 3 "=r,X"))]
14097 "TARGET_POWER"
14098 "@
14099 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
14100 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
14101 [(set_attr "length" "12")])
14102
14103 (define_insn ""
14104 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14105 (compare:CC
14106 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14107 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14108 (const_int 0)))
14109 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
14110 (le:SI (match_dup 1) (match_dup 2)))
14111 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
14112 "TARGET_POWER"
14113 "@
14114 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14115 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
14116 #
14117 #"
14118 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
14119 (set_attr "length" "12,12,16,16")])
14120
14121 (define_split
14122 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14123 (compare:CC
14124 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14125 (match_operand:SI 2 "reg_or_short_operand" ""))
14126 (const_int 0)))
14127 (set (match_operand:SI 0 "gpc_reg_operand" "")
14128 (le:SI (match_dup 1) (match_dup 2)))
14129 (clobber (match_scratch:SI 3 ""))]
14130 "TARGET_POWER && reload_completed"
14131 [(parallel [(set (match_dup 0)
14132 (le:SI (match_dup 1) (match_dup 2)))
14133 (clobber (match_dup 3))])
14134 (set (match_dup 4)
14135 (compare:CC (match_dup 0)
14136 (const_int 0)))]
14137 "")
14138
14139 (define_insn ""
14140 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14141 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14142 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
14143 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
14144 "TARGET_POWER"
14145 "@
14146 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
14147 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
14148 [(set_attr "length" "12")])
14149
14150 (define_insn ""
14151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14152 (compare:CC
14153 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14154 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14155 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14156 (const_int 0)))
14157 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14158 "TARGET_POWER"
14159 "@
14160 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14161 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
14162 #
14163 #"
14164 [(set_attr "type" "compare")
14165 (set_attr "length" "12,12,16,16")])
14166
14167 (define_split
14168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14169 (compare:CC
14170 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14171 (match_operand:SI 2 "reg_or_short_operand" ""))
14172 (match_operand:SI 3 "gpc_reg_operand" ""))
14173 (const_int 0)))
14174 (clobber (match_scratch:SI 4 ""))]
14175 "TARGET_POWER && reload_completed"
14176 [(set (match_dup 4)
14177 (plus:SI (le:SI (match_dup 1) (match_dup 2))
14178 (match_dup 3)))
14179 (set (match_dup 0)
14180 (compare:CC (match_dup 4)
14181 (const_int 0)))]
14182 "")
14183
14184 (define_insn ""
14185 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14186 (compare:CC
14187 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14188 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14189 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14190 (const_int 0)))
14191 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14192 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14193 "TARGET_POWER"
14194 "@
14195 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14196 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
14197 #
14198 #"
14199 [(set_attr "type" "compare")
14200 (set_attr "length" "12,12,16,16")])
14201
14202 (define_split
14203 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14204 (compare:CC
14205 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14206 (match_operand:SI 2 "reg_or_short_operand" ""))
14207 (match_operand:SI 3 "gpc_reg_operand" ""))
14208 (const_int 0)))
14209 (set (match_operand:SI 0 "gpc_reg_operand" "")
14210 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14211 "TARGET_POWER && reload_completed"
14212 [(set (match_dup 0)
14213 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14214 (set (match_dup 4)
14215 (compare:CC (match_dup 0)
14216 (const_int 0)))]
14217 "")
14218
14219 (define_insn ""
14220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14221 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14222 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
14223 "TARGET_POWER"
14224 "@
14225 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
14226 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
14227 [(set_attr "length" "12")])
14228
14229 (define_insn "*leu<mode>"
14230 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14231 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14232 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14233 ""
14234 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14235 [(set_attr "type" "three")
14236 (set_attr "length" "12")])
14237
14238 (define_insn "*leu<mode>_compare"
14239 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14240 (compare:CC
14241 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14242 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14243 (const_int 0)))
14244 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14245 (leu:P (match_dup 1) (match_dup 2)))]
14246 ""
14247 "@
14248 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14249 #"
14250 [(set_attr "type" "compare")
14251 (set_attr "length" "12,16")])
14252
14253 (define_split
14254 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14255 (compare:CC
14256 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
14257 (match_operand:P 2 "reg_or_short_operand" ""))
14258 (const_int 0)))
14259 (set (match_operand:P 0 "gpc_reg_operand" "")
14260 (leu:P (match_dup 1) (match_dup 2)))]
14261 "reload_completed"
14262 [(set (match_dup 0)
14263 (leu:P (match_dup 1) (match_dup 2)))
14264 (set (match_dup 3)
14265 (compare:CC (match_dup 0)
14266 (const_int 0)))]
14267 "")
14268
14269 (define_insn "*plus_leu<mode>"
14270 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14271 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14272 (match_operand:P 2 "reg_or_short_operand" "rI"))
14273 (match_operand:P 3 "gpc_reg_operand" "r")))]
14274 ""
14275 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
14276 [(set_attr "type" "two")
14277 (set_attr "length" "8")])
14278
14279 (define_insn ""
14280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14281 (compare:CC
14282 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14283 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14284 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14285 (const_int 0)))
14286 (clobber (match_scratch:SI 4 "=&r,&r"))]
14287 "TARGET_32BIT"
14288 "@
14289 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
14290 #"
14291 [(set_attr "type" "compare")
14292 (set_attr "length" "8,12")])
14293
14294 (define_split
14295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14296 (compare:CC
14297 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14298 (match_operand:SI 2 "reg_or_short_operand" ""))
14299 (match_operand:SI 3 "gpc_reg_operand" ""))
14300 (const_int 0)))
14301 (clobber (match_scratch:SI 4 ""))]
14302 "TARGET_32BIT && reload_completed"
14303 [(set (match_dup 4)
14304 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
14305 (match_dup 3)))
14306 (set (match_dup 0)
14307 (compare:CC (match_dup 4)
14308 (const_int 0)))]
14309 "")
14310
14311 (define_insn ""
14312 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14313 (compare:CC
14314 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14315 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14316 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14317 (const_int 0)))
14318 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14319 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14320 "TARGET_32BIT"
14321 "@
14322 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
14323 #"
14324 [(set_attr "type" "compare")
14325 (set_attr "length" "8,12")])
14326
14327 (define_split
14328 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14329 (compare:CC
14330 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14331 (match_operand:SI 2 "reg_or_short_operand" ""))
14332 (match_operand:SI 3 "gpc_reg_operand" ""))
14333 (const_int 0)))
14334 (set (match_operand:SI 0 "gpc_reg_operand" "")
14335 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14336 "TARGET_32BIT && reload_completed"
14337 [(set (match_dup 0)
14338 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14339 (set (match_dup 4)
14340 (compare:CC (match_dup 0)
14341 (const_int 0)))]
14342 "")
14343
14344 (define_insn "*neg_leu<mode>"
14345 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14346 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14347 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14348 ""
14349 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
14350 [(set_attr "type" "three")
14351 (set_attr "length" "12")])
14352
14353 (define_insn "*and_neg_leu<mode>"
14354 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14355 (and:P (neg:P
14356 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14357 (match_operand:P 2 "reg_or_short_operand" "rI")))
14358 (match_operand:P 3 "gpc_reg_operand" "r")))]
14359 ""
14360 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14361 [(set_attr "type" "three")
14362 (set_attr "length" "12")])
14363
14364 (define_insn ""
14365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14366 (compare:CC
14367 (and:SI (neg:SI
14368 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14369 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14370 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14371 (const_int 0)))
14372 (clobber (match_scratch:SI 4 "=&r,&r"))]
14373 "TARGET_32BIT"
14374 "@
14375 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14376 #"
14377 [(set_attr "type" "compare")
14378 (set_attr "length" "12,16")])
14379
14380 (define_split
14381 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14382 (compare:CC
14383 (and:SI (neg:SI
14384 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14385 (match_operand:SI 2 "reg_or_short_operand" "")))
14386 (match_operand:SI 3 "gpc_reg_operand" ""))
14387 (const_int 0)))
14388 (clobber (match_scratch:SI 4 ""))]
14389 "TARGET_32BIT && reload_completed"
14390 [(set (match_dup 4)
14391 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14392 (match_dup 3)))
14393 (set (match_dup 0)
14394 (compare:CC (match_dup 4)
14395 (const_int 0)))]
14396 "")
14397
14398 (define_insn ""
14399 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14400 (compare:CC
14401 (and:SI (neg:SI
14402 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14403 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14404 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14405 (const_int 0)))
14406 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14407 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14408 "TARGET_32BIT"
14409 "@
14410 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14411 #"
14412 [(set_attr "type" "compare")
14413 (set_attr "length" "12,16")])
14414
14415 (define_split
14416 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14417 (compare:CC
14418 (and:SI (neg:SI
14419 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14420 (match_operand:SI 2 "reg_or_short_operand" "")))
14421 (match_operand:SI 3 "gpc_reg_operand" ""))
14422 (const_int 0)))
14423 (set (match_operand:SI 0 "gpc_reg_operand" "")
14424 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14425 "TARGET_32BIT && reload_completed"
14426 [(set (match_dup 0)
14427 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14428 (match_dup 3)))
14429 (set (match_dup 4)
14430 (compare:CC (match_dup 0)
14431 (const_int 0)))]
14432 "")
14433
14434 (define_insn ""
14435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14436 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14437 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
14438 "TARGET_POWER"
14439 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14440 [(set_attr "length" "12")])
14441
14442 (define_insn ""
14443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14444 (compare:CC
14445 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14446 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14447 (const_int 0)))
14448 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14449 (lt:SI (match_dup 1) (match_dup 2)))]
14450 "TARGET_POWER"
14451 "@
14452 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14453 #"
14454 [(set_attr "type" "delayed_compare")
14455 (set_attr "length" "12,16")])
14456
14457 (define_split
14458 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14459 (compare:CC
14460 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14461 (match_operand:SI 2 "reg_or_short_operand" ""))
14462 (const_int 0)))
14463 (set (match_operand:SI 0 "gpc_reg_operand" "")
14464 (lt:SI (match_dup 1) (match_dup 2)))]
14465 "TARGET_POWER && reload_completed"
14466 [(set (match_dup 0)
14467 (lt:SI (match_dup 1) (match_dup 2)))
14468 (set (match_dup 3)
14469 (compare:CC (match_dup 0)
14470 (const_int 0)))]
14471 "")
14472
14473 (define_insn ""
14474 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14475 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14476 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14477 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14478 "TARGET_POWER"
14479 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14480 [(set_attr "length" "12")])
14481
14482 (define_insn ""
14483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14484 (compare:CC
14485 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14486 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14487 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14488 (const_int 0)))
14489 (clobber (match_scratch:SI 4 "=&r,&r"))]
14490 "TARGET_POWER"
14491 "@
14492 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14493 #"
14494 [(set_attr "type" "compare")
14495 (set_attr "length" "12,16")])
14496
14497 (define_split
14498 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14499 (compare:CC
14500 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14501 (match_operand:SI 2 "reg_or_short_operand" ""))
14502 (match_operand:SI 3 "gpc_reg_operand" ""))
14503 (const_int 0)))
14504 (clobber (match_scratch:SI 4 ""))]
14505 "TARGET_POWER && reload_completed"
14506 [(set (match_dup 4)
14507 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14508 (match_dup 3)))
14509 (set (match_dup 0)
14510 (compare:CC (match_dup 4)
14511 (const_int 0)))]
14512 "")
14513
14514 (define_insn ""
14515 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14516 (compare:CC
14517 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14518 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14519 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14520 (const_int 0)))
14521 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14522 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14523 "TARGET_POWER"
14524 "@
14525 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14526 #"
14527 [(set_attr "type" "compare")
14528 (set_attr "length" "12,16")])
14529
14530 (define_split
14531 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14532 (compare:CC
14533 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14534 (match_operand:SI 2 "reg_or_short_operand" ""))
14535 (match_operand:SI 3 "gpc_reg_operand" ""))
14536 (const_int 0)))
14537 (set (match_operand:SI 0 "gpc_reg_operand" "")
14538 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14539 "TARGET_POWER && reload_completed"
14540 [(set (match_dup 0)
14541 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14542 (set (match_dup 4)
14543 (compare:CC (match_dup 0)
14544 (const_int 0)))]
14545 "")
14546
14547 (define_insn ""
14548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14549 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14550 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14551 "TARGET_POWER"
14552 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14553 [(set_attr "length" "12")])
14554
14555 (define_insn_and_split "*ltu<mode>"
14556 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14557 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14558 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14559 ""
14560 "#"
14561 ""
14562 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14563 (set (match_dup 0) (neg:P (match_dup 0)))]
14564 "")
14565
14566 (define_insn_and_split "*ltu<mode>_compare"
14567 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14568 (compare:CC
14569 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14570 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14571 (const_int 0)))
14572 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14573 (ltu:P (match_dup 1) (match_dup 2)))]
14574 ""
14575 "#"
14576 ""
14577 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14578 (parallel [(set (match_dup 3)
14579 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14580 (set (match_dup 0) (neg:P (match_dup 0)))])]
14581 "")
14582
14583 (define_insn_and_split "*plus_ltu<mode>"
14584 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14585 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14586 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14587 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14588 ""
14589 "#"
14590 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14591 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14592 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14593 "")
14594
14595 (define_insn_and_split "*plus_ltu<mode>_compare"
14596 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14597 (compare:CC
14598 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14599 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14600 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14601 (const_int 0)))
14602 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14603 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14604 ""
14605 "#"
14606 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14607 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14608 (parallel [(set (match_dup 4)
14609 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14610 (const_int 0)))
14611 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14612 "")
14613
14614 (define_insn "*neg_ltu<mode>"
14615 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14616 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14617 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14618 ""
14619 "@
14620 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14621 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14622 [(set_attr "type" "two")
14623 (set_attr "length" "8")])
14624
14625 (define_insn ""
14626 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14627 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14628 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14629 (clobber (match_scratch:SI 3 "=r"))]
14630 "TARGET_POWER"
14631 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14632 [(set_attr "length" "12")])
14633
14634 (define_insn ""
14635 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14636 (compare:CC
14637 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14638 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14639 (const_int 0)))
14640 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14641 (ge:SI (match_dup 1) (match_dup 2)))
14642 (clobber (match_scratch:SI 3 "=r,r"))]
14643 "TARGET_POWER"
14644 "@
14645 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14646 #"
14647 [(set_attr "type" "compare")
14648 (set_attr "length" "12,16")])
14649
14650 (define_split
14651 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14652 (compare:CC
14653 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14654 (match_operand:SI 2 "reg_or_short_operand" ""))
14655 (const_int 0)))
14656 (set (match_operand:SI 0 "gpc_reg_operand" "")
14657 (ge:SI (match_dup 1) (match_dup 2)))
14658 (clobber (match_scratch:SI 3 ""))]
14659 "TARGET_POWER && reload_completed"
14660 [(parallel [(set (match_dup 0)
14661 (ge:SI (match_dup 1) (match_dup 2)))
14662 (clobber (match_dup 3))])
14663 (set (match_dup 4)
14664 (compare:CC (match_dup 0)
14665 (const_int 0)))]
14666 "")
14667
14668 (define_insn ""
14669 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14670 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14671 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14672 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14673 "TARGET_POWER"
14674 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14675 [(set_attr "length" "12")])
14676
14677 (define_insn ""
14678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14679 (compare:CC
14680 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14681 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14682 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14683 (const_int 0)))
14684 (clobber (match_scratch:SI 4 "=&r,&r"))]
14685 "TARGET_POWER"
14686 "@
14687 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14688 #"
14689 [(set_attr "type" "compare")
14690 (set_attr "length" "12,16")])
14691
14692 (define_split
14693 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14694 (compare:CC
14695 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14696 (match_operand:SI 2 "reg_or_short_operand" ""))
14697 (match_operand:SI 3 "gpc_reg_operand" ""))
14698 (const_int 0)))
14699 (clobber (match_scratch:SI 4 ""))]
14700 "TARGET_POWER && reload_completed"
14701 [(set (match_dup 4)
14702 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14703 (match_dup 3)))
14704 (set (match_dup 0)
14705 (compare:CC (match_dup 4)
14706 (const_int 0)))]
14707 "")
14708
14709 (define_insn ""
14710 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14711 (compare:CC
14712 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14713 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14714 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14715 (const_int 0)))
14716 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14717 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14718 "TARGET_POWER"
14719 "@
14720 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14721 #"
14722 [(set_attr "type" "compare")
14723 (set_attr "length" "12,16")])
14724
14725 (define_split
14726 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14727 (compare:CC
14728 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14729 (match_operand:SI 2 "reg_or_short_operand" ""))
14730 (match_operand:SI 3 "gpc_reg_operand" ""))
14731 (const_int 0)))
14732 (set (match_operand:SI 0 "gpc_reg_operand" "")
14733 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14734 "TARGET_POWER && reload_completed"
14735 [(set (match_dup 0)
14736 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14737 (set (match_dup 4)
14738 (compare:CC (match_dup 0)
14739 (const_int 0)))]
14740 "")
14741
14742 (define_insn ""
14743 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14744 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14745 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14746 "TARGET_POWER"
14747 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14748 [(set_attr "length" "12")])
14749
14750 (define_insn "*geu<mode>"
14751 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14752 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14753 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14754 ""
14755 "@
14756 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14757 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14758 [(set_attr "type" "three")
14759 (set_attr "length" "12")])
14760
14761 (define_insn "*geu<mode>_compare"
14762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14763 (compare:CC
14764 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14765 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14766 (const_int 0)))
14767 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14768 (geu:P (match_dup 1) (match_dup 2)))]
14769 ""
14770 "@
14771 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14772 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14773 #
14774 #"
14775 [(set_attr "type" "compare")
14776 (set_attr "length" "12,12,16,16")])
14777
14778 (define_split
14779 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14780 (compare:CC
14781 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14782 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14783 (const_int 0)))
14784 (set (match_operand:P 0 "gpc_reg_operand" "")
14785 (geu:P (match_dup 1) (match_dup 2)))]
14786 "reload_completed"
14787 [(set (match_dup 0)
14788 (geu:P (match_dup 1) (match_dup 2)))
14789 (set (match_dup 3)
14790 (compare:CC (match_dup 0)
14791 (const_int 0)))]
14792 "")
14793
14794 (define_insn "*plus_geu<mode>"
14795 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14796 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14797 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14798 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14799 ""
14800 "@
14801 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14802 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14803 [(set_attr "type" "two")
14804 (set_attr "length" "8")])
14805
14806 (define_insn ""
14807 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14808 (compare:CC
14809 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14810 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14811 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14812 (const_int 0)))
14813 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14814 "TARGET_32BIT"
14815 "@
14816 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14817 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14818 #
14819 #"
14820 [(set_attr "type" "compare")
14821 (set_attr "length" "8,8,12,12")])
14822
14823 (define_split
14824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14825 (compare:CC
14826 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14827 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14828 (match_operand:SI 3 "gpc_reg_operand" ""))
14829 (const_int 0)))
14830 (clobber (match_scratch:SI 4 ""))]
14831 "TARGET_32BIT && reload_completed"
14832 [(set (match_dup 4)
14833 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14834 (match_dup 3)))
14835 (set (match_dup 0)
14836 (compare:CC (match_dup 4)
14837 (const_int 0)))]
14838 "")
14839
14840 (define_insn ""
14841 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14842 (compare:CC
14843 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14844 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14845 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14846 (const_int 0)))
14847 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14848 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14849 "TARGET_32BIT"
14850 "@
14851 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14852 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14853 #
14854 #"
14855 [(set_attr "type" "compare")
14856 (set_attr "length" "8,8,12,12")])
14857
14858 (define_split
14859 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14860 (compare:CC
14861 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14862 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14863 (match_operand:SI 3 "gpc_reg_operand" ""))
14864 (const_int 0)))
14865 (set (match_operand:SI 0 "gpc_reg_operand" "")
14866 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14867 "TARGET_32BIT && reload_completed"
14868 [(set (match_dup 0)
14869 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14870 (set (match_dup 4)
14871 (compare:CC (match_dup 0)
14872 (const_int 0)))]
14873 "")
14874
14875 (define_insn "*neg_geu<mode>"
14876 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14877 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14878 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14879 ""
14880 "@
14881 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14882 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14883 [(set_attr "type" "three")
14884 (set_attr "length" "12")])
14885
14886 (define_insn "*and_neg_geu<mode>"
14887 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14888 (and:P (neg:P
14889 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14890 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14891 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14892 ""
14893 "@
14894 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14895 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14896 [(set_attr "type" "three")
14897 (set_attr "length" "12")])
14898
14899 (define_insn ""
14900 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14901 (compare:CC
14902 (and:SI (neg:SI
14903 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14904 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14905 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14906 (const_int 0)))
14907 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14908 "TARGET_32BIT"
14909 "@
14910 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14911 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14912 #
14913 #"
14914 [(set_attr "type" "compare")
14915 (set_attr "length" "12,12,16,16")])
14916
14917 (define_split
14918 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14919 (compare:CC
14920 (and:SI (neg:SI
14921 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14922 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14923 (match_operand:SI 3 "gpc_reg_operand" ""))
14924 (const_int 0)))
14925 (clobber (match_scratch:SI 4 ""))]
14926 "TARGET_32BIT && reload_completed"
14927 [(set (match_dup 4)
14928 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14929 (match_dup 3)))
14930 (set (match_dup 0)
14931 (compare:CC (match_dup 4)
14932 (const_int 0)))]
14933 "")
14934
14935 (define_insn ""
14936 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14937 (compare:CC
14938 (and:SI (neg:SI
14939 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14940 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14941 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14942 (const_int 0)))
14943 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14944 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14945 "TARGET_32BIT"
14946 "@
14947 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14948 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14949 #
14950 #"
14951 [(set_attr "type" "compare")
14952 (set_attr "length" "12,12,16,16")])
14953
14954 (define_split
14955 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14956 (compare:CC
14957 (and:SI (neg:SI
14958 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14959 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14960 (match_operand:SI 3 "gpc_reg_operand" ""))
14961 (const_int 0)))
14962 (set (match_operand:SI 0 "gpc_reg_operand" "")
14963 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14964 "TARGET_32BIT && reload_completed"
14965 [(set (match_dup 0)
14966 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14967 (set (match_dup 4)
14968 (compare:CC (match_dup 0)
14969 (const_int 0)))]
14970 "")
14971
14972 (define_insn ""
14973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14974 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14975 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14976 "TARGET_POWER"
14977 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14978 [(set_attr "length" "12")])
14979
14980 (define_insn ""
14981 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14982 (compare:CC
14983 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14984 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14985 (const_int 0)))
14986 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14987 (gt:SI (match_dup 1) (match_dup 2)))]
14988 "TARGET_POWER"
14989 "@
14990 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14991 #"
14992 [(set_attr "type" "delayed_compare")
14993 (set_attr "length" "12,16")])
14994
14995 (define_split
14996 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14997 (compare:CC
14998 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14999 (match_operand:SI 2 "reg_or_short_operand" ""))
15000 (const_int 0)))
15001 (set (match_operand:SI 0 "gpc_reg_operand" "")
15002 (gt:SI (match_dup 1) (match_dup 2)))]
15003 "TARGET_POWER && reload_completed"
15004 [(set (match_dup 0)
15005 (gt:SI (match_dup 1) (match_dup 2)))
15006 (set (match_dup 3)
15007 (compare:CC (match_dup 0)
15008 (const_int 0)))]
15009 "")
15010
15011 (define_insn "*plus_gt0<mode>"
15012 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15013 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
15014 (const_int 0))
15015 (match_operand:P 2 "gpc_reg_operand" "r")))]
15016 ""
15017 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
15018 [(set_attr "type" "three")
15019 (set_attr "length" "12")])
15020
15021 (define_insn ""
15022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15023 (compare:CC
15024 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15025 (const_int 0))
15026 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15027 (const_int 0)))
15028 (clobber (match_scratch:SI 3 "=&r,&r"))]
15029 "TARGET_32BIT"
15030 "@
15031 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
15032 #"
15033 [(set_attr "type" "compare")
15034 (set_attr "length" "12,16")])
15035
15036 (define_split
15037 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15038 (compare:CC
15039 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15040 (const_int 0))
15041 (match_operand:SI 2 "gpc_reg_operand" ""))
15042 (const_int 0)))
15043 (clobber (match_scratch:SI 3 ""))]
15044 "TARGET_32BIT && reload_completed"
15045 [(set (match_dup 3)
15046 (plus:SI (gt:SI (match_dup 1) (const_int 0))
15047 (match_dup 2)))
15048 (set (match_dup 0)
15049 (compare:CC (match_dup 3)
15050 (const_int 0)))]
15051 "")
15052
15053 (define_insn ""
15054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15055 (compare:CC
15056 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15057 (const_int 0))
15058 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15059 (const_int 0)))
15060 (clobber (match_scratch:DI 3 "=&r,&r"))]
15061 "TARGET_64BIT"
15062 "@
15063 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
15064 #"
15065 [(set_attr "type" "compare")
15066 (set_attr "length" "12,16")])
15067
15068 (define_split
15069 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
15070 (compare:CC
15071 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15072 (const_int 0))
15073 (match_operand:DI 2 "gpc_reg_operand" ""))
15074 (const_int 0)))
15075 (clobber (match_scratch:DI 3 ""))]
15076 "TARGET_64BIT && reload_completed"
15077 [(set (match_dup 3)
15078 (plus:DI (gt:DI (match_dup 1) (const_int 0))
15079 (match_dup 2)))
15080 (set (match_dup 0)
15081 (compare:CC (match_dup 3)
15082 (const_int 0)))]
15083 "")
15084
15085 (define_insn ""
15086 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15087 (compare:CC
15088 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15089 (const_int 0))
15090 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15091 (const_int 0)))
15092 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15093 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15094 "TARGET_32BIT"
15095 "@
15096 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
15097 #"
15098 [(set_attr "type" "compare")
15099 (set_attr "length" "12,16")])
15100
15101 (define_split
15102 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15103 (compare:CC
15104 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15105 (const_int 0))
15106 (match_operand:SI 2 "gpc_reg_operand" ""))
15107 (const_int 0)))
15108 (set (match_operand:SI 0 "gpc_reg_operand" "")
15109 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15110 "TARGET_32BIT && reload_completed"
15111 [(set (match_dup 0)
15112 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
15113 (set (match_dup 3)
15114 (compare:CC (match_dup 0)
15115 (const_int 0)))]
15116 "")
15117
15118 (define_insn ""
15119 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15120 (compare:CC
15121 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15122 (const_int 0))
15123 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15124 (const_int 0)))
15125 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
15126 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15127 "TARGET_64BIT"
15128 "@
15129 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
15130 #"
15131 [(set_attr "type" "compare")
15132 (set_attr "length" "12,16")])
15133
15134 (define_split
15135 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
15136 (compare:CC
15137 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15138 (const_int 0))
15139 (match_operand:DI 2 "gpc_reg_operand" ""))
15140 (const_int 0)))
15141 (set (match_operand:DI 0 "gpc_reg_operand" "")
15142 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15143 "TARGET_64BIT && reload_completed"
15144 [(set (match_dup 0)
15145 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
15146 (set (match_dup 3)
15147 (compare:CC (match_dup 0)
15148 (const_int 0)))]
15149 "")
15150
15151 (define_insn ""
15152 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
15153 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15154 (match_operand:SI 2 "reg_or_short_operand" "r"))
15155 (match_operand:SI 3 "gpc_reg_operand" "r")))]
15156 "TARGET_POWER"
15157 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
15158 [(set_attr "length" "12")])
15159
15160 (define_insn ""
15161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15162 (compare:CC
15163 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15164 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15165 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15166 (const_int 0)))
15167 (clobber (match_scratch:SI 4 "=&r,&r"))]
15168 "TARGET_POWER"
15169 "@
15170 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
15171 #"
15172 [(set_attr "type" "compare")
15173 (set_attr "length" "12,16")])
15174
15175 (define_split
15176 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15177 (compare:CC
15178 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15179 (match_operand:SI 2 "reg_or_short_operand" ""))
15180 (match_operand:SI 3 "gpc_reg_operand" ""))
15181 (const_int 0)))
15182 (clobber (match_scratch:SI 4 ""))]
15183 "TARGET_POWER && reload_completed"
15184 [(set (match_dup 4)
15185 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15186 (set (match_dup 0)
15187 (compare:CC (match_dup 4)
15188 (const_int 0)))]
15189 "")
15190
15191 (define_insn ""
15192 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
15193 (compare:CC
15194 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15195 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15196 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15197 (const_int 0)))
15198 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15199 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15200 "TARGET_POWER"
15201 "@
15202 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
15203 #"
15204 [(set_attr "type" "compare")
15205 (set_attr "length" "12,16")])
15206
15207 (define_split
15208 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15209 (compare:CC
15210 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15211 (match_operand:SI 2 "reg_or_short_operand" ""))
15212 (match_operand:SI 3 "gpc_reg_operand" ""))
15213 (const_int 0)))
15214 (set (match_operand:SI 0 "gpc_reg_operand" "")
15215 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15216 "TARGET_POWER && reload_completed"
15217 [(set (match_dup 0)
15218 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15219 (set (match_dup 4)
15220 (compare:CC (match_dup 0)
15221 (const_int 0)))]
15222 "")
15223
15224 (define_insn ""
15225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15226 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15227 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
15228 "TARGET_POWER"
15229 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
15230 [(set_attr "length" "12")])
15231
15232 (define_insn_and_split "*gtu<mode>"
15233 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15234 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15235 (match_operand:P 2 "reg_or_short_operand" "rI")))]
15236 ""
15237 "#"
15238 ""
15239 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15240 (set (match_dup 0) (neg:P (match_dup 0)))]
15241 "")
15242
15243 (define_insn_and_split "*gtu<mode>_compare"
15244 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15245 (compare:CC
15246 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
15247 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
15248 (const_int 0)))
15249 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
15250 (gtu:P (match_dup 1) (match_dup 2)))]
15251 ""
15252 "#"
15253 ""
15254 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15255 (parallel [(set (match_dup 3)
15256 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
15257 (set (match_dup 0) (neg:P (match_dup 0)))])]
15258 "")
15259
15260 (define_insn_and_split "*plus_gtu<mode>"
15261 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15262 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15263 (match_operand:P 2 "reg_or_short_operand" "rI"))
15264 (match_operand:P 3 "reg_or_short_operand" "rI")))]
15265 ""
15266 "#"
15267 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15268 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15269 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
15270 "")
15271
15272 (define_insn_and_split "*plus_gtu<mode>_compare"
15273 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
15274 (compare:CC
15275 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
15276 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
15277 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
15278 (const_int 0)))
15279 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
15280 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
15281 ""
15282 "#"
15283 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15284 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15285 (parallel [(set (match_dup 4)
15286 (compare:CC (minus:P (match_dup 3) (match_dup 0))
15287 (const_int 0)))
15288 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
15289 "")
15290
15291 (define_insn "*neg_gtu<mode>"
15292 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15293 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15294 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
15295 ""
15296 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
15297 [(set_attr "type" "two")
15298 (set_attr "length" "8")])
15299
15300 \f
15301 ;; Define both directions of branch and return. If we need a reload
15302 ;; register, we'd rather use CR0 since it is much easier to copy a
15303 ;; register CC value to there.
15304
15305 (define_insn ""
15306 [(set (pc)
15307 (if_then_else (match_operator 1 "branch_comparison_operator"
15308 [(match_operand 2
15309 "cc_reg_operand" "y")
15310 (const_int 0)])
15311 (label_ref (match_operand 0 "" ""))
15312 (pc)))]
15313 ""
15314 "*
15315 {
15316 return output_cbranch (operands[1], \"%l0\", 0, insn);
15317 }"
15318 [(set_attr "type" "branch")])
15319
15320 (define_insn ""
15321 [(set (pc)
15322 (if_then_else (match_operator 0 "branch_comparison_operator"
15323 [(match_operand 1
15324 "cc_reg_operand" "y")
15325 (const_int 0)])
15326 (return)
15327 (pc)))]
15328 "direct_return ()"
15329 "*
15330 {
15331 return output_cbranch (operands[0], NULL, 0, insn);
15332 }"
15333 [(set_attr "type" "jmpreg")
15334 (set_attr "length" "4")])
15335
15336 (define_insn ""
15337 [(set (pc)
15338 (if_then_else (match_operator 1 "branch_comparison_operator"
15339 [(match_operand 2
15340 "cc_reg_operand" "y")
15341 (const_int 0)])
15342 (pc)
15343 (label_ref (match_operand 0 "" ""))))]
15344 ""
15345 "*
15346 {
15347 return output_cbranch (operands[1], \"%l0\", 1, insn);
15348 }"
15349 [(set_attr "type" "branch")])
15350
15351 (define_insn ""
15352 [(set (pc)
15353 (if_then_else (match_operator 0 "branch_comparison_operator"
15354 [(match_operand 1
15355 "cc_reg_operand" "y")
15356 (const_int 0)])
15357 (pc)
15358 (return)))]
15359 "direct_return ()"
15360 "*
15361 {
15362 return output_cbranch (operands[0], NULL, 1, insn);
15363 }"
15364 [(set_attr "type" "jmpreg")
15365 (set_attr "length" "4")])
15366
15367 ;; Logic on condition register values.
15368
15369 ; This pattern matches things like
15370 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
15371 ; (eq:SI (reg:CCFP 68) (const_int 0)))
15372 ; (const_int 1)))
15373 ; which are generated by the branch logic.
15374 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
15375
15376 (define_insn "*cceq_ior_compare"
15377 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15378 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
15379 [(match_operator:SI 2
15380 "branch_positive_comparison_operator"
15381 [(match_operand 3
15382 "cc_reg_operand" "y,y")
15383 (const_int 0)])
15384 (match_operator:SI 4
15385 "branch_positive_comparison_operator"
15386 [(match_operand 5
15387 "cc_reg_operand" "0,y")
15388 (const_int 0)])])
15389 (const_int 1)))]
15390 ""
15391 "cr%q1 %E0,%j2,%j4"
15392 [(set_attr "type" "cr_logical,delayed_cr")])
15393
15394 ; Why is the constant -1 here, but 1 in the previous pattern?
15395 ; Because ~1 has all but the low bit set.
15396 (define_insn ""
15397 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15398 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
15399 [(not:SI (match_operator:SI 2
15400 "branch_positive_comparison_operator"
15401 [(match_operand 3
15402 "cc_reg_operand" "y,y")
15403 (const_int 0)]))
15404 (match_operator:SI 4
15405 "branch_positive_comparison_operator"
15406 [(match_operand 5
15407 "cc_reg_operand" "0,y")
15408 (const_int 0)])])
15409 (const_int -1)))]
15410 ""
15411 "cr%q1 %E0,%j2,%j4"
15412 [(set_attr "type" "cr_logical,delayed_cr")])
15413
15414 (define_insn "*cceq_rev_compare"
15415 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15416 (compare:CCEQ (match_operator:SI 1
15417 "branch_positive_comparison_operator"
15418 [(match_operand 2
15419 "cc_reg_operand" "0,y")
15420 (const_int 0)])
15421 (const_int 0)))]
15422 ""
15423 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
15424 [(set_attr "type" "cr_logical,delayed_cr")])
15425
15426 ;; If we are comparing the result of two comparisons, this can be done
15427 ;; using creqv or crxor.
15428
15429 (define_insn_and_split ""
15430 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
15431 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
15432 [(match_operand 2 "cc_reg_operand" "y")
15433 (const_int 0)])
15434 (match_operator 3 "branch_comparison_operator"
15435 [(match_operand 4 "cc_reg_operand" "y")
15436 (const_int 0)])))]
15437 ""
15438 "#"
15439 ""
15440 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
15441 (match_dup 5)))]
15442 "
15443 {
15444 int positive_1, positive_2;
15445
15446 positive_1 = branch_positive_comparison_operator (operands[1],
15447 GET_MODE (operands[1]));
15448 positive_2 = branch_positive_comparison_operator (operands[3],
15449 GET_MODE (operands[3]));
15450
15451 if (! positive_1)
15452 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
15453 GET_CODE (operands[1])),
15454 SImode,
15455 operands[2], const0_rtx);
15456 else if (GET_MODE (operands[1]) != SImode)
15457 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
15458 operands[2], const0_rtx);
15459
15460 if (! positive_2)
15461 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
15462 GET_CODE (operands[3])),
15463 SImode,
15464 operands[4], const0_rtx);
15465 else if (GET_MODE (operands[3]) != SImode)
15466 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
15467 operands[4], const0_rtx);
15468
15469 if (positive_1 == positive_2)
15470 {
15471 operands[1] = gen_rtx_NOT (SImode, operands[1]);
15472 operands[5] = constm1_rtx;
15473 }
15474 else
15475 {
15476 operands[5] = const1_rtx;
15477 }
15478 }")
15479
15480 ;; Unconditional branch and return.
15481
15482 (define_insn "jump"
15483 [(set (pc)
15484 (label_ref (match_operand 0 "" "")))]
15485 ""
15486 "b %l0"
15487 [(set_attr "type" "branch")])
15488
15489 (define_insn "return"
15490 [(return)]
15491 "direct_return ()"
15492 "{br|blr}"
15493 [(set_attr "type" "jmpreg")])
15494
15495 (define_expand "indirect_jump"
15496 [(set (pc) (match_operand 0 "register_operand" ""))])
15497
15498 (define_insn "*indirect_jump<mode>"
15499 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15500 ""
15501 "@
15502 bctr
15503 {br|blr}"
15504 [(set_attr "type" "jmpreg")])
15505
15506 ;; Table jump for switch statements:
15507 (define_expand "tablejump"
15508 [(use (match_operand 0 "" ""))
15509 (use (label_ref (match_operand 1 "" "")))]
15510 ""
15511 "
15512 {
15513 if (TARGET_32BIT)
15514 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15515 else
15516 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15517 DONE;
15518 }")
15519
15520 (define_expand "tablejumpsi"
15521 [(set (match_dup 3)
15522 (plus:SI (match_operand:SI 0 "" "")
15523 (match_dup 2)))
15524 (parallel [(set (pc) (match_dup 3))
15525 (use (label_ref (match_operand 1 "" "")))])]
15526 "TARGET_32BIT"
15527 "
15528 { operands[0] = force_reg (SImode, operands[0]);
15529 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15530 operands[3] = gen_reg_rtx (SImode);
15531 }")
15532
15533 (define_expand "tablejumpdi"
15534 [(set (match_dup 4)
15535 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15536 (set (match_dup 3)
15537 (plus:DI (match_dup 4)
15538 (match_dup 2)))
15539 (parallel [(set (pc) (match_dup 3))
15540 (use (label_ref (match_operand 1 "" "")))])]
15541 "TARGET_64BIT"
15542 "
15543 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15544 operands[3] = gen_reg_rtx (DImode);
15545 operands[4] = gen_reg_rtx (DImode);
15546 }")
15547
15548 (define_insn "*tablejump<mode>_internal1"
15549 [(set (pc)
15550 (match_operand:P 0 "register_operand" "c,*l"))
15551 (use (label_ref (match_operand 1 "" "")))]
15552 ""
15553 "@
15554 bctr
15555 {br|blr}"
15556 [(set_attr "type" "jmpreg")])
15557
15558 (define_insn "nop"
15559 [(const_int 0)]
15560 ""
15561 "{cror 0,0,0|nop}")
15562 \f
15563 ;; Define the subtract-one-and-jump insns, starting with the template
15564 ;; so loop.c knows what to generate.
15565
15566 (define_expand "doloop_end"
15567 [(use (match_operand 0 "" "")) ; loop pseudo
15568 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15569 (use (match_operand 2 "" "")) ; max iterations
15570 (use (match_operand 3 "" "")) ; loop level
15571 (use (match_operand 4 "" ""))] ; label
15572 ""
15573 "
15574 {
15575 /* Only use this on innermost loops. */
15576 if (INTVAL (operands[3]) > 1)
15577 FAIL;
15578 if (TARGET_64BIT)
15579 {
15580 if (GET_MODE (operands[0]) != DImode)
15581 FAIL;
15582 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15583 }
15584 else
15585 {
15586 if (GET_MODE (operands[0]) != SImode)
15587 FAIL;
15588 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15589 }
15590 DONE;
15591 }")
15592
15593 (define_expand "ctr<mode>"
15594 [(parallel [(set (pc)
15595 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15596 (const_int 1))
15597 (label_ref (match_operand 1 "" ""))
15598 (pc)))
15599 (set (match_dup 0)
15600 (plus:P (match_dup 0)
15601 (const_int -1)))
15602 (clobber (match_scratch:CC 2 ""))
15603 (clobber (match_scratch:P 3 ""))])]
15604 ""
15605 "")
15606
15607 ;; We need to be able to do this for any operand, including MEM, or we
15608 ;; will cause reload to blow up since we don't allow output reloads on
15609 ;; JUMP_INSNs.
15610 ;; For the length attribute to be calculated correctly, the
15611 ;; label MUST be operand 0.
15612
15613 (define_insn "*ctr<mode>_internal1"
15614 [(set (pc)
15615 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15616 (const_int 1))
15617 (label_ref (match_operand 0 "" ""))
15618 (pc)))
15619 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15620 (plus:P (match_dup 1)
15621 (const_int -1)))
15622 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15623 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15624 ""
15625 "*
15626 {
15627 if (which_alternative != 0)
15628 return \"#\";
15629 else if (get_attr_length (insn) == 4)
15630 return \"{bdn|bdnz} %l0\";
15631 else
15632 return \"bdz $+8\;b %l0\";
15633 }"
15634 [(set_attr "type" "branch")
15635 (set_attr "length" "*,12,16,16")])
15636
15637 (define_insn "*ctr<mode>_internal2"
15638 [(set (pc)
15639 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15640 (const_int 1))
15641 (pc)
15642 (label_ref (match_operand 0 "" ""))))
15643 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15644 (plus:P (match_dup 1)
15645 (const_int -1)))
15646 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15647 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15648 ""
15649 "*
15650 {
15651 if (which_alternative != 0)
15652 return \"#\";
15653 else if (get_attr_length (insn) == 4)
15654 return \"bdz %l0\";
15655 else
15656 return \"{bdn|bdnz} $+8\;b %l0\";
15657 }"
15658 [(set_attr "type" "branch")
15659 (set_attr "length" "*,12,16,16")])
15660
15661 ;; Similar but use EQ
15662
15663 (define_insn "*ctr<mode>_internal5"
15664 [(set (pc)
15665 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15666 (const_int 1))
15667 (label_ref (match_operand 0 "" ""))
15668 (pc)))
15669 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15670 (plus:P (match_dup 1)
15671 (const_int -1)))
15672 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15673 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15674 ""
15675 "*
15676 {
15677 if (which_alternative != 0)
15678 return \"#\";
15679 else if (get_attr_length (insn) == 4)
15680 return \"bdz %l0\";
15681 else
15682 return \"{bdn|bdnz} $+8\;b %l0\";
15683 }"
15684 [(set_attr "type" "branch")
15685 (set_attr "length" "*,12,16,16")])
15686
15687 (define_insn "*ctr<mode>_internal6"
15688 [(set (pc)
15689 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15690 (const_int 1))
15691 (pc)
15692 (label_ref (match_operand 0 "" ""))))
15693 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15694 (plus:P (match_dup 1)
15695 (const_int -1)))
15696 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15697 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15698 ""
15699 "*
15700 {
15701 if (which_alternative != 0)
15702 return \"#\";
15703 else if (get_attr_length (insn) == 4)
15704 return \"{bdn|bdnz} %l0\";
15705 else
15706 return \"bdz $+8\;b %l0\";
15707 }"
15708 [(set_attr "type" "branch")
15709 (set_attr "length" "*,12,16,16")])
15710
15711 ;; Now the splitters if we could not allocate the CTR register
15712
15713 (define_split
15714 [(set (pc)
15715 (if_then_else (match_operator 2 "comparison_operator"
15716 [(match_operand:P 1 "gpc_reg_operand" "")
15717 (const_int 1)])
15718 (match_operand 5 "" "")
15719 (match_operand 6 "" "")))
15720 (set (match_operand:P 0 "gpc_reg_operand" "")
15721 (plus:P (match_dup 1) (const_int -1)))
15722 (clobber (match_scratch:CC 3 ""))
15723 (clobber (match_scratch:P 4 ""))]
15724 "reload_completed"
15725 [(parallel [(set (match_dup 3)
15726 (compare:CC (plus:P (match_dup 1)
15727 (const_int -1))
15728 (const_int 0)))
15729 (set (match_dup 0)
15730 (plus:P (match_dup 1)
15731 (const_int -1)))])
15732 (set (pc) (if_then_else (match_dup 7)
15733 (match_dup 5)
15734 (match_dup 6)))]
15735 "
15736 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15737 operands[3], const0_rtx); }")
15738
15739 (define_split
15740 [(set (pc)
15741 (if_then_else (match_operator 2 "comparison_operator"
15742 [(match_operand:P 1 "gpc_reg_operand" "")
15743 (const_int 1)])
15744 (match_operand 5 "" "")
15745 (match_operand 6 "" "")))
15746 (set (match_operand:P 0 "nonimmediate_operand" "")
15747 (plus:P (match_dup 1) (const_int -1)))
15748 (clobber (match_scratch:CC 3 ""))
15749 (clobber (match_scratch:P 4 ""))]
15750 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15751 [(parallel [(set (match_dup 3)
15752 (compare:CC (plus:P (match_dup 1)
15753 (const_int -1))
15754 (const_int 0)))
15755 (set (match_dup 4)
15756 (plus:P (match_dup 1)
15757 (const_int -1)))])
15758 (set (match_dup 0)
15759 (match_dup 4))
15760 (set (pc) (if_then_else (match_dup 7)
15761 (match_dup 5)
15762 (match_dup 6)))]
15763 "
15764 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15765 operands[3], const0_rtx); }")
15766 \f
15767 (define_insn "trap"
15768 [(trap_if (const_int 1) (const_int 0))]
15769 ""
15770 "{t 31,0,0|trap}"
15771 [(set_attr "type" "trap")])
15772
15773 (define_expand "ctrap<mode>4"
15774 [(trap_if (match_operator 0 "ordered_comparison_operator"
15775 [(match_operand:GPR 1 "register_operand")
15776 (match_operand:GPR 2 "reg_or_short_operand")])
15777 (match_operand 3 "zero_constant" ""))]
15778 ""
15779 "")
15780
15781 (define_insn ""
15782 [(trap_if (match_operator 0 "ordered_comparison_operator"
15783 [(match_operand:GPR 1 "register_operand" "r")
15784 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15785 (const_int 0))]
15786 ""
15787 "{t|t<wd>}%V0%I2 %1,%2"
15788 [(set_attr "type" "trap")])
15789 \f
15790 ;; Insns related to generating the function prologue and epilogue.
15791
15792 (define_expand "prologue"
15793 [(use (const_int 0))]
15794 "TARGET_SCHED_PROLOG"
15795 "
15796 {
15797 rs6000_emit_prologue ();
15798 DONE;
15799 }")
15800
15801 (define_insn "*movesi_from_cr_one"
15802 [(match_parallel 0 "mfcr_operation"
15803 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15804 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15805 (match_operand 3 "immediate_operand" "n")]
15806 UNSPEC_MOVESI_FROM_CR))])]
15807 "TARGET_MFCRF"
15808 "*
15809 {
15810 int mask = 0;
15811 int i;
15812 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15813 {
15814 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15815 operands[4] = GEN_INT (mask);
15816 output_asm_insn (\"mfcr %1,%4\", operands);
15817 }
15818 return \"\";
15819 }"
15820 [(set_attr "type" "mfcrf")])
15821
15822 (define_insn "movesi_from_cr"
15823 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15824 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15825 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15826 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15827 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15828 UNSPEC_MOVESI_FROM_CR))]
15829 ""
15830 "mfcr %0"
15831 [(set_attr "type" "mfcr")])
15832
15833 (define_insn "*stmw"
15834 [(match_parallel 0 "stmw_operation"
15835 [(set (match_operand:SI 1 "memory_operand" "=m")
15836 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15837 "TARGET_MULTIPLE"
15838 "{stm|stmw} %2,%1"
15839 [(set_attr "type" "store_ux")])
15840
15841 ; The following comment applies to:
15842 ; save_gpregs_*
15843 ; save_fpregs_*
15844 ; restore_gpregs*
15845 ; return_and_restore_gpregs*
15846 ; return_and_restore_fpregs*
15847 ; return_and_restore_fpregs_aix*
15848 ;
15849 ; The out-of-line save / restore functions expects one input argument.
15850 ; Since those are not standard call_insn's, we must avoid using
15851 ; MATCH_OPERAND for that argument. That way the register rename
15852 ; optimization will not try to rename this register.
15853 ; Each pattern is repeated for each possible register number used in
15854 ; various ABIs (r11, r1, and for some functions r12)
15855
15856 (define_insn "*save_gpregs_<mode>_r11"
15857 [(match_parallel 0 "any_parallel_operand"
15858 [(clobber (reg:P 65))
15859 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15860 (use (reg:P 11))
15861 (set (match_operand:P 2 "memory_operand" "=m")
15862 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15863 ""
15864 "bl %1"
15865 [(set_attr "type" "branch")
15866 (set_attr "length" "4")])
15867
15868 (define_insn "*save_gpregs_<mode>_r12"
15869 [(match_parallel 0 "any_parallel_operand"
15870 [(clobber (reg:P 65))
15871 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15872 (use (reg:P 12))
15873 (set (match_operand:P 2 "memory_operand" "=m")
15874 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15875 ""
15876 "bl %1"
15877 [(set_attr "type" "branch")
15878 (set_attr "length" "4")])
15879
15880 (define_insn "*save_gpregs_<mode>_r1"
15881 [(match_parallel 0 "any_parallel_operand"
15882 [(clobber (reg:P 65))
15883 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15884 (use (reg:P 1))
15885 (set (match_operand:P 2 "memory_operand" "=m")
15886 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15887 ""
15888 "bl %1"
15889 [(set_attr "type" "branch")
15890 (set_attr "length" "4")])
15891
15892 (define_insn "*save_fpregs_<mode>_r11"
15893 [(match_parallel 0 "any_parallel_operand"
15894 [(clobber (reg:P 65))
15895 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15896 (use (reg:P 11))
15897 (set (match_operand:DF 2 "memory_operand" "=m")
15898 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15899 ""
15900 "bl %1"
15901 [(set_attr "type" "branch")
15902 (set_attr "length" "4")])
15903
15904 (define_insn "*save_fpregs_<mode>_r12"
15905 [(match_parallel 0 "any_parallel_operand"
15906 [(clobber (reg:P 65))
15907 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15908 (use (reg:P 12))
15909 (set (match_operand:DF 2 "memory_operand" "=m")
15910 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15911 ""
15912 "bl %1"
15913 [(set_attr "type" "branch")
15914 (set_attr "length" "4")])
15915
15916 (define_insn "*save_fpregs_<mode>_r1"
15917 [(match_parallel 0 "any_parallel_operand"
15918 [(clobber (reg:P 65))
15919 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15920 (use (reg:P 1))
15921 (set (match_operand:DF 2 "memory_operand" "=m")
15922 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15923 ""
15924 "bl %1"
15925 [(set_attr "type" "branch")
15926 (set_attr "length" "4")])
15927
15928 ; These are to explain that changes to the stack pointer should
15929 ; not be moved over stores to stack memory.
15930 (define_insn "stack_tie"
15931 [(set (match_operand:BLK 0 "memory_operand" "+m")
15932 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15933 ""
15934 ""
15935 [(set_attr "length" "0")])
15936
15937 ; Like stack_tie, but depend on both fp and sp based memory.
15938 (define_insn "frame_tie"
15939 [(set (match_operand:BLK 0 "memory_operand" "+m")
15940 (unspec:BLK [(match_dup 0)
15941 (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15942 ""
15943 ""
15944 [(set_attr "length" "0")])
15945
15946
15947 (define_expand "epilogue"
15948 [(use (const_int 0))]
15949 "TARGET_SCHED_PROLOG"
15950 "
15951 {
15952 rs6000_emit_epilogue (FALSE);
15953 DONE;
15954 }")
15955
15956 ; On some processors, doing the mtcrf one CC register at a time is
15957 ; faster (like on the 604e). On others, doing them all at once is
15958 ; faster; for instance, on the 601 and 750.
15959
15960 (define_expand "movsi_to_cr_one"
15961 [(set (match_operand:CC 0 "cc_reg_operand" "")
15962 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15963 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15964 ""
15965 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15966
15967 (define_insn "*movsi_to_cr"
15968 [(match_parallel 0 "mtcrf_operation"
15969 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15970 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15971 (match_operand 3 "immediate_operand" "n")]
15972 UNSPEC_MOVESI_TO_CR))])]
15973 ""
15974 "*
15975 {
15976 int mask = 0;
15977 int i;
15978 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15979 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15980 operands[4] = GEN_INT (mask);
15981 return \"mtcrf %4,%2\";
15982 }"
15983 [(set_attr "type" "mtcr")])
15984
15985 (define_insn "*mtcrfsi"
15986 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15987 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15988 (match_operand 2 "immediate_operand" "n")]
15989 UNSPEC_MOVESI_TO_CR))]
15990 "GET_CODE (operands[0]) == REG
15991 && CR_REGNO_P (REGNO (operands[0]))
15992 && GET_CODE (operands[2]) == CONST_INT
15993 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15994 "mtcrf %R0,%1"
15995 [(set_attr "type" "mtcr")])
15996
15997 ; The load-multiple instructions have similar properties.
15998 ; Note that "load_multiple" is a name known to the machine-independent
15999 ; code that actually corresponds to the PowerPC load-string.
16000
16001 (define_insn "*lmw"
16002 [(match_parallel 0 "lmw_operation"
16003 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
16004 (match_operand:SI 2 "memory_operand" "m"))])]
16005 "TARGET_MULTIPLE"
16006 "{lm|lmw} %1,%2"
16007 [(set_attr "type" "load_ux")
16008 (set_attr "cell_micro" "always")])
16009
16010 (define_insn "*return_internal_<mode>"
16011 [(return)
16012 (use (match_operand:P 0 "register_operand" "lc"))]
16013 ""
16014 "b%T0"
16015 [(set_attr "type" "jmpreg")])
16016
16017 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
16018 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
16019
16020 ; The following comment applies to:
16021 ; save_gpregs_*
16022 ; save_fpregs_*
16023 ; restore_gpregs*
16024 ; return_and_restore_gpregs*
16025 ; return_and_restore_fpregs*
16026 ; return_and_restore_fpregs_aix*
16027 ;
16028 ; The out-of-line save / restore functions expects one input argument.
16029 ; Since those are not standard call_insn's, we must avoid using
16030 ; MATCH_OPERAND for that argument. That way the register rename
16031 ; optimization will not try to rename this register.
16032 ; Each pattern is repeated for each possible register number used in
16033 ; various ABIs (r11, r1, and for some functions r12)
16034
16035 (define_insn "*restore_gpregs_<mode>_r11"
16036 [(match_parallel 0 "any_parallel_operand"
16037 [(clobber (match_operand:P 1 "register_operand" "=l"))
16038 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16039 (use (reg:P 11))
16040 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16041 (match_operand:P 4 "memory_operand" "m"))])]
16042 ""
16043 "bl %2"
16044 [(set_attr "type" "branch")
16045 (set_attr "length" "4")])
16046
16047 (define_insn "*restore_gpregs_<mode>_r12"
16048 [(match_parallel 0 "any_parallel_operand"
16049 [(clobber (match_operand:P 1 "register_operand" "=l"))
16050 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16051 (use (reg:P 12))
16052 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16053 (match_operand:P 4 "memory_operand" "m"))])]
16054 ""
16055 "bl %2"
16056 [(set_attr "type" "branch")
16057 (set_attr "length" "4")])
16058
16059 (define_insn "*restore_gpregs_<mode>_r1"
16060 [(match_parallel 0 "any_parallel_operand"
16061 [(clobber (match_operand:P 1 "register_operand" "=l"))
16062 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16063 (use (reg:P 1))
16064 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16065 (match_operand:P 4 "memory_operand" "m"))])]
16066 ""
16067 "bl %2"
16068 [(set_attr "type" "branch")
16069 (set_attr "length" "4")])
16070
16071 (define_insn "*return_and_restore_gpregs_<mode>_r11"
16072 [(match_parallel 0 "any_parallel_operand"
16073 [(return)
16074 (clobber (match_operand:P 1 "register_operand" "=l"))
16075 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16076 (use (reg:P 11))
16077 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16078 (match_operand:P 4 "memory_operand" "m"))])]
16079 ""
16080 "b %2"
16081 [(set_attr "type" "branch")
16082 (set_attr "length" "4")])
16083
16084 (define_insn "*return_and_restore_gpregs_<mode>_r12"
16085 [(match_parallel 0 "any_parallel_operand"
16086 [(return)
16087 (clobber (match_operand:P 1 "register_operand" "=l"))
16088 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16089 (use (reg:P 12))
16090 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16091 (match_operand:P 4 "memory_operand" "m"))])]
16092 ""
16093 "b %2"
16094 [(set_attr "type" "branch")
16095 (set_attr "length" "4")])
16096
16097 (define_insn "*return_and_restore_gpregs_<mode>_r1"
16098 [(match_parallel 0 "any_parallel_operand"
16099 [(return)
16100 (clobber (match_operand:P 1 "register_operand" "=l"))
16101 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16102 (use (reg:P 1))
16103 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16104 (match_operand:P 4 "memory_operand" "m"))])]
16105 ""
16106 "b %2"
16107 [(set_attr "type" "branch")
16108 (set_attr "length" "4")])
16109
16110 (define_insn "*return_and_restore_fpregs_<mode>_r11"
16111 [(match_parallel 0 "any_parallel_operand"
16112 [(return)
16113 (clobber (match_operand:P 1 "register_operand" "=l"))
16114 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16115 (use (reg:P 11))
16116 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16117 (match_operand:DF 4 "memory_operand" "m"))])]
16118 ""
16119 "b %2"
16120 [(set_attr "type" "branch")
16121 (set_attr "length" "4")])
16122
16123 (define_insn "*return_and_restore_fpregs_<mode>_r12"
16124 [(match_parallel 0 "any_parallel_operand"
16125 [(return)
16126 (clobber (match_operand:P 1 "register_operand" "=l"))
16127 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16128 (use (reg:P 12))
16129 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16130 (match_operand:DF 4 "memory_operand" "m"))])]
16131 ""
16132 "b %2"
16133 [(set_attr "type" "branch")
16134 (set_attr "length" "4")])
16135
16136 (define_insn "*return_and_restore_fpregs_<mode>_r1"
16137 [(match_parallel 0 "any_parallel_operand"
16138 [(return)
16139 (clobber (match_operand:P 1 "register_operand" "=l"))
16140 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16141 (use (reg:P 1))
16142 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16143 (match_operand:DF 4 "memory_operand" "m"))])]
16144 ""
16145 "b %2"
16146 [(set_attr "type" "branch")
16147 (set_attr "length" "4")])
16148
16149 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
16150 [(match_parallel 0 "any_parallel_operand"
16151 [(return)
16152 (use (match_operand:P 1 "register_operand" "l"))
16153 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16154 (use (reg:P 11))
16155 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16156 (match_operand:DF 4 "memory_operand" "m"))])]
16157 ""
16158 "b %2"
16159 [(set_attr "type" "branch")
16160 (set_attr "length" "4")])
16161
16162 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
16163 [(match_parallel 0 "any_parallel_operand"
16164 [(return)
16165 (use (match_operand:P 1 "register_operand" "l"))
16166 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16167 (use (reg:P 1))
16168 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16169 (match_operand:DF 4 "memory_operand" "m"))])]
16170 ""
16171 "b %2"
16172 [(set_attr "type" "branch")
16173 (set_attr "length" "4")])
16174
16175 ; This is used in compiling the unwind routines.
16176 (define_expand "eh_return"
16177 [(use (match_operand 0 "general_operand" ""))]
16178 ""
16179 "
16180 {
16181 if (TARGET_32BIT)
16182 emit_insn (gen_eh_set_lr_si (operands[0]));
16183 else
16184 emit_insn (gen_eh_set_lr_di (operands[0]));
16185 DONE;
16186 }")
16187
16188 ; We can't expand this before we know where the link register is stored.
16189 (define_insn "eh_set_lr_<mode>"
16190 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
16191 UNSPECV_EH_RR)
16192 (clobber (match_scratch:P 1 "=&b"))]
16193 ""
16194 "#")
16195
16196 (define_split
16197 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
16198 (clobber (match_scratch 1 ""))]
16199 "reload_completed"
16200 [(const_int 0)]
16201 "
16202 {
16203 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
16204 DONE;
16205 }")
16206
16207 (define_insn "prefetch"
16208 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
16209 (match_operand:SI 1 "const_int_operand" "n")
16210 (match_operand:SI 2 "const_int_operand" "n"))]
16211 "TARGET_POWERPC"
16212 "*
16213 {
16214 if (GET_CODE (operands[0]) == REG)
16215 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
16216 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
16217 }"
16218 [(set_attr "type" "load")])
16219 \f
16220 (define_insn "bpermd_<mode>"
16221 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
16222 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
16223 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
16224 "TARGET_POPCNTD"
16225 "bpermd %0,%1,%2"
16226 [(set_attr "type" "integer")])
16227
16228 \f
16229 ;; Builtin fma support. Handle
16230 ;; Note that the conditions for expansion are in the FMA_F iterator.
16231
16232 (define_expand "fma<mode>4"
16233 [(set (match_operand:FMA_F 0 "register_operand" "")
16234 (fma:FMA_F
16235 (match_operand:FMA_F 1 "register_operand" "")
16236 (match_operand:FMA_F 2 "register_operand" "")
16237 (match_operand:FMA_F 3 "register_operand" "")))]
16238 ""
16239 "")
16240
16241 ; Altivec only has fma and nfms.
16242 (define_expand "fms<mode>4"
16243 [(set (match_operand:FMA_F 0 "register_operand" "")
16244 (fma:FMA_F
16245 (match_operand:FMA_F 1 "register_operand" "")
16246 (match_operand:FMA_F 2 "register_operand" "")
16247 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
16248 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16249 "")
16250
16251 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
16252 (define_expand "fnma<mode>4"
16253 [(set (match_operand:FMA_F 0 "register_operand" "")
16254 (neg:FMA_F
16255 (fma:FMA_F
16256 (match_operand:FMA_F 1 "register_operand" "")
16257 (match_operand:FMA_F 2 "register_operand" "")
16258 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16259 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
16260 "")
16261
16262 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
16263 (define_expand "fnms<mode>4"
16264 [(set (match_operand:FMA_F 0 "register_operand" "")
16265 (neg:FMA_F
16266 (fma:FMA_F
16267 (match_operand:FMA_F 1 "register_operand" "")
16268 (match_operand:FMA_F 2 "register_operand" "")
16269 (match_operand:FMA_F 3 "register_operand" ""))))]
16270 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16271 "")
16272
16273 ; Not an official optab name, but used from builtins.
16274 (define_expand "nfma<mode>4"
16275 [(set (match_operand:FMA_F 0 "register_operand" "")
16276 (neg:FMA_F
16277 (fma:FMA_F
16278 (match_operand:FMA_F 1 "register_operand" "")
16279 (match_operand:FMA_F 2 "register_operand" "")
16280 (match_operand:FMA_F 3 "register_operand" ""))))]
16281 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16282 "")
16283
16284 ; Not an official optab name, but used from builtins.
16285 (define_expand "nfms<mode>4"
16286 [(set (match_operand:FMA_F 0 "register_operand" "")
16287 (neg:FMA_F
16288 (fma:FMA_F
16289 (match_operand:FMA_F 1 "register_operand" "")
16290 (match_operand:FMA_F 2 "register_operand" "")
16291 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16292 ""
16293 "")
16294
16295 \f
16296
16297 (include "sync.md")
16298 (include "vector.md")
16299 (include "vsx.md")
16300 (include "altivec.md")
16301 (include "spe.md")
16302 (include "dfp.md")
16303 (include "paired.md")