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vector.md (GPR move splitter): Do not split moves of vectors in GPRS if they are...
[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2013 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 ;; This file is part of GCC.
6
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22
23 ;;
24 ;; REGNOS
25 ;;
26
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56
57 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
58 (TOC_SAVE_OFFSET_32BIT 20)
59 (TOC_SAVE_OFFSET_64BIT 40)
60
61 ; Function TOC offset in the AIX function descriptor.
62 (AIX_FUNC_DESC_TOC_32BIT 4)
63 (AIX_FUNC_DESC_TOC_64BIT 8)
64
65 ; Static chain offset in the AIX function descriptor.
66 (AIX_FUNC_DESC_SC_32BIT 8)
67 (AIX_FUNC_DESC_SC_64BIT 16)
68 ])
69
70 ;;
71 ;; UNSPEC usage
72 ;;
73
74 (define_c_enum "unspec"
75 [UNSPEC_FRSP ; frsp for POWER machines
76 UNSPEC_PROBE_STACK ; probe stack memory reference
77 UNSPEC_TOCPTR ; address of a word pointing to the TOC
78 UNSPEC_TOC ; address of the TOC (more-or-less)
79 UNSPEC_MOVSI_GOT
80 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
81 UNSPEC_FCTIWZ
82 UNSPEC_FRIM
83 UNSPEC_FRIN
84 UNSPEC_FRIP
85 UNSPEC_FRIZ
86 UNSPEC_LD_MPIC ; load_macho_picbase
87 UNSPEC_MPIC_CORRECT ; macho_correct_pic
88 UNSPEC_TLSGD
89 UNSPEC_TLSLD
90 UNSPEC_MOVESI_FROM_CR
91 UNSPEC_MOVESI_TO_CR
92 UNSPEC_TLSDTPREL
93 UNSPEC_TLSDTPRELHA
94 UNSPEC_TLSDTPRELLO
95 UNSPEC_TLSGOTDTPREL
96 UNSPEC_TLSTPREL
97 UNSPEC_TLSTPRELHA
98 UNSPEC_TLSTPRELLO
99 UNSPEC_TLSGOTTPREL
100 UNSPEC_TLSTLS
101 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
102 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
103 UNSPEC_STFIWX
104 UNSPEC_POPCNTB
105 UNSPEC_FRES
106 UNSPEC_SP_SET
107 UNSPEC_SP_TEST
108 UNSPEC_SYNC
109 UNSPEC_LWSYNC
110 UNSPEC_SYNC_OP
111 UNSPEC_ATOMIC
112 UNSPEC_CMPXCHG
113 UNSPEC_XCHG
114 UNSPEC_AND
115 UNSPEC_DLMZB
116 UNSPEC_DLMZB_CR
117 UNSPEC_DLMZB_STRLEN
118 UNSPEC_RSQRT
119 UNSPEC_TOCREL
120 UNSPEC_MACHOPIC_OFFSET
121 UNSPEC_BPERM
122 UNSPEC_COPYSIGN
123 UNSPEC_PARITY
124 UNSPEC_FCTIW
125 UNSPEC_FCTID
126 UNSPEC_LFIWAX
127 UNSPEC_LFIWZX
128 UNSPEC_FCTIWUZ
129 UNSPEC_GRP_END_NOP
130 UNSPEC_P8V_FMRGOW
131 UNSPEC_P8V_MTVSRWZ
132 UNSPEC_P8V_RELOAD_FROM_GPR
133 UNSPEC_P8V_MTVSRD
134 UNSPEC_P8V_XXPERMDI
135 UNSPEC_P8V_RELOAD_FROM_VSX
136 UNSPEC_FUSION_GPR
137 ])
138
139 ;;
140 ;; UNSPEC_VOLATILE usage
141 ;;
142
143 (define_c_enum "unspecv"
144 [UNSPECV_BLOCK
145 UNSPECV_LL ; load-locked
146 UNSPECV_SC ; store-conditional
147 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
148 UNSPECV_EH_RR ; eh_reg_restore
149 UNSPECV_ISYNC ; isync instruction
150 UNSPECV_MFTB ; move from time base
151 ])
152
153 \f
154 ;; Define an insn type attribute. This is used in function unit delay
155 ;; computations.
156 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto"
157 (const_string "integer"))
158
159 ;; Define floating point instruction sub-types for use with Xfpu.md
160 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
161
162 ;; Length (in bytes).
163 ; '(pc)' in the following doesn't include the instruction itself; it is
164 ; calculated as if the instruction had zero size.
165 (define_attr "length" ""
166 (if_then_else (eq_attr "type" "branch")
167 (if_then_else (and (ge (minus (match_dup 0) (pc))
168 (const_int -32768))
169 (lt (minus (match_dup 0) (pc))
170 (const_int 32764)))
171 (const_int 4)
172 (const_int 8))
173 (const_int 4)))
174
175 ;; Processor type -- this attribute must exactly match the processor_type
176 ;; enumeration in rs6000-opts.h.
177 (define_attr "cpu"
178 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
179 ppc750,ppc7400,ppc7450,
180 ppc403,ppc405,ppc440,ppc476,
181 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
182 power4,power5,power6,power7,power8,
183 rs64a,mpccore,cell,ppca2,titan"
184 (const (symbol_ref "rs6000_cpu_attr")))
185
186
187 ;; If this instruction is microcoded on the CELL processor
188 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
189 (define_attr "cell_micro" "not,conditional,always"
190 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
191 (const_string "always")
192 (const_string "not")))
193
194 (automata_option "ndfa")
195
196 (include "rs64.md")
197 (include "mpc.md")
198 (include "40x.md")
199 (include "440.md")
200 (include "476.md")
201 (include "601.md")
202 (include "603.md")
203 (include "6xx.md")
204 (include "7xx.md")
205 (include "7450.md")
206 (include "8540.md")
207 (include "e300c2c3.md")
208 (include "e500mc.md")
209 (include "e500mc64.md")
210 (include "e5500.md")
211 (include "e6500.md")
212 (include "power4.md")
213 (include "power5.md")
214 (include "power6.md")
215 (include "power7.md")
216 (include "cell.md")
217 (include "xfpu.md")
218 (include "a2.md")
219 (include "titan.md")
220
221 (include "predicates.md")
222 (include "constraints.md")
223
224 (include "darwin.md")
225
226 \f
227 ;; Mode iterators
228
229 ; This mode iterator allows :GPR to be used to indicate the allowable size
230 ; of whole values in GPRs.
231 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
232
233 ; Any supported integer mode.
234 (define_mode_iterator INT [QI HI SI DI TI PTI])
235
236 ; Any supported integer mode that fits in one register.
237 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
238
239 ; extend modes for DImode
240 (define_mode_iterator QHSI [QI HI SI])
241
242 ; SImode or DImode, even if DImode doesn't fit in GPRs.
243 (define_mode_iterator SDI [SI DI])
244
245 ; The size of a pointer. Also, the size of the value that a record-condition
246 ; (one with a '.') will compare; and the size used for arithmetic carries.
247 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
248
249 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
250 ; PTImode is GPR only)
251 (define_mode_iterator TI2 [TI PTI])
252
253 ; Any hardware-supported floating-point mode
254 (define_mode_iterator FP [
255 (SF "TARGET_HARD_FLOAT
256 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
257 (DF "TARGET_HARD_FLOAT
258 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
259 (TF "!TARGET_IEEEQUAD
260 && TARGET_HARD_FLOAT
261 && (TARGET_FPRS || TARGET_E500_DOUBLE)
262 && TARGET_LONG_DOUBLE_128")
263 (DD "TARGET_DFP")
264 (TD "TARGET_DFP")])
265
266 ; Any fma capable floating-point mode.
267 (define_mode_iterator FMA_F [
268 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
269 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
270 || VECTOR_UNIT_VSX_P (DFmode)")
271 (V2SF "TARGET_PAIRED_FLOAT")
272 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
273 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
274 ])
275
276 ; Floating point move iterators to combine binary and decimal moves
277 (define_mode_iterator FMOVE32 [SF SD])
278 (define_mode_iterator FMOVE64 [DF DD])
279 (define_mode_iterator FMOVE64X [DI DF DD])
280 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
281 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
282
283 ; Iterators for 128 bit types for direct move
284 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
285 (V16QI "")
286 (V8HI "")
287 (V4SI "")
288 (V4SF "")
289 (V2DI "")
290 (V2DF "")])
291
292 ; Whether a floating point move is ok, don't allow SD without hardware FP
293 (define_mode_attr fmove_ok [(SF "")
294 (DF "")
295 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
296 (DD "")])
297
298 ; Convert REAL_VALUE to the appropriate bits
299 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
300 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
301 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
302 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
303
304 ; Definitions for load to 32-bit fpr register
305 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
306 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
307 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
308 (define_mode_attr f32_lv [(SF "lxsspx %0,%y1") (SD "lxsiwzx %0,%y1")])
309
310 ; Definitions for store from 32-bit fpr register
311 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
312 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
313 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
314 (define_mode_attr f32_sv [(SF "stxsspx %1,%y0") (SD "stxsiwzx %1,%y0")])
315
316 ; Definitions for 32-bit fpr direct move
317 (define_mode_attr f32_dm [(SF "wn") (SD "wm")])
318
319 ; These modes do not fit in integer registers in 32-bit mode.
320 ; but on e500v2, the gpr are 64 bit registers
321 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
322
323 ; Iterator for reciprocal estimate instructions
324 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
325
326 ; Iterator for just SF/DF
327 (define_mode_iterator SFDF [SF DF])
328
329 ; Conditional returns.
330 (define_code_iterator any_return [return simple_return])
331 (define_code_attr return_pred [(return "direct_return ()")
332 (simple_return "1")])
333 (define_code_attr return_str [(return "") (simple_return "simple_")])
334
335 ; Various instructions that come in SI and DI forms.
336 ; A generic w/d attribute, for things like cmpw/cmpd.
337 (define_mode_attr wd [(QI "b")
338 (HI "h")
339 (SI "w")
340 (DI "d")
341 (V16QI "b")
342 (V8HI "h")
343 (V4SI "w")
344 (V2DI "d")])
345
346 ; DImode bits
347 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
348
349 ;; ISEL/ISEL64 target selection
350 (define_mode_attr sel [(SI "") (DI "64")])
351
352 ;; Suffix for reload patterns
353 (define_mode_attr ptrsize [(SI "32bit")
354 (DI "64bit")])
355
356 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
357 (DI "TARGET_64BIT")])
358
359 (define_mode_attr mptrsize [(SI "si")
360 (DI "di")])
361
362 (define_mode_attr ptrload [(SI "lwz")
363 (DI "ld")])
364
365 (define_mode_attr ptrm [(SI "m")
366 (DI "Y")])
367
368 (define_mode_attr rreg [(SF "f")
369 (DF "ws")
370 (V4SF "wf")
371 (V2DF "wd")])
372
373 (define_mode_attr rreg2 [(SF "f")
374 (DF "d")])
375
376 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
377 (DF "TARGET_FCFID")])
378
379 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
380 (DF "TARGET_E500_DOUBLE")])
381
382 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
383 (DF "TARGET_DOUBLE_FLOAT")])
384 \f
385 ;; Start with fixed-point load and store insns. Here we put only the more
386 ;; complex forms. Basic data transfer is done later.
387
388 (define_expand "zero_extend<mode>di2"
389 [(set (match_operand:DI 0 "gpc_reg_operand" "")
390 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
391 "TARGET_POWERPC64"
392 "")
393
394 (define_insn "*zero_extend<mode>di2_internal1"
395 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
396 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
397 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
398 "@
399 l<wd>z%U1%X1 %0,%1
400 rldicl %0,%1,0,<dbits>"
401 [(set_attr_alternative "type"
402 [(if_then_else
403 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
404 (const_string "load_ux")
405 (if_then_else
406 (match_test "update_address_mem (operands[1], VOIDmode)")
407 (const_string "load_u")
408 (const_string "load")))
409 (const_string "*")])])
410
411 (define_insn "*zero_extend<mode>di2_internal2"
412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
413 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
414 (const_int 0)))
415 (clobber (match_scratch:DI 2 "=r,r"))]
416 "TARGET_64BIT"
417 "@
418 rldicl. %2,%1,0,<dbits>
419 #"
420 [(set_attr "type" "compare")
421 (set_attr "length" "4,8")])
422
423 (define_split
424 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
425 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
426 (const_int 0)))
427 (clobber (match_scratch:DI 2 ""))]
428 "TARGET_POWERPC64 && reload_completed"
429 [(set (match_dup 2)
430 (zero_extend:DI (match_dup 1)))
431 (set (match_dup 0)
432 (compare:CC (match_dup 2)
433 (const_int 0)))]
434 "")
435
436 (define_insn "*zero_extend<mode>di2_internal3"
437 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
438 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
439 (const_int 0)))
440 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
441 (zero_extend:DI (match_dup 1)))]
442 "TARGET_64BIT"
443 "@
444 rldicl. %0,%1,0,<dbits>
445 #"
446 [(set_attr "type" "compare")
447 (set_attr "length" "4,8")])
448
449 (define_split
450 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
451 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
452 (const_int 0)))
453 (set (match_operand:DI 0 "gpc_reg_operand" "")
454 (zero_extend:DI (match_dup 1)))]
455 "TARGET_POWERPC64 && reload_completed"
456 [(set (match_dup 0)
457 (zero_extend:DI (match_dup 1)))
458 (set (match_dup 2)
459 (compare:CC (match_dup 0)
460 (const_int 0)))]
461 "")
462
463 (define_insn "*zero_extendsidi2_lfiwzx"
464 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wm")
465 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
466 "TARGET_POWERPC64 && TARGET_LFIWZX"
467 "@
468 lwz%U1%X1 %0,%1
469 rldicl %0,%1,0,32
470 mtvsrwz %x0,%1
471 lfiwzx %0,%y1
472 lxsiwzx %x0,%y1"
473 [(set_attr_alternative "type"
474 [(if_then_else
475 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
476 (const_string "load_ux")
477 (if_then_else
478 (match_test "update_address_mem (operands[1], VOIDmode)")
479 (const_string "load_u")
480 (const_string "load")))
481 (const_string "*")
482 (const_string "mffgpr")
483 (const_string "fpload")
484 (const_string "fpload")])])
485
486 (define_insn "extendqidi2"
487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
488 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
489 "TARGET_POWERPC64"
490 "extsb %0,%1"
491 [(set_attr "type" "exts")])
492
493 (define_insn ""
494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
495 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
496 (const_int 0)))
497 (clobber (match_scratch:DI 2 "=r,r"))]
498 "TARGET_64BIT"
499 "@
500 extsb. %2,%1
501 #"
502 [(set_attr "type" "compare")
503 (set_attr "length" "4,8")])
504
505 (define_split
506 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
507 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
508 (const_int 0)))
509 (clobber (match_scratch:DI 2 ""))]
510 "TARGET_POWERPC64 && reload_completed"
511 [(set (match_dup 2)
512 (sign_extend:DI (match_dup 1)))
513 (set (match_dup 0)
514 (compare:CC (match_dup 2)
515 (const_int 0)))]
516 "")
517
518 (define_insn ""
519 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
520 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
521 (const_int 0)))
522 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
523 (sign_extend:DI (match_dup 1)))]
524 "TARGET_64BIT"
525 "@
526 extsb. %0,%1
527 #"
528 [(set_attr "type" "compare")
529 (set_attr "length" "4,8")])
530
531 (define_split
532 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
533 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
534 (const_int 0)))
535 (set (match_operand:DI 0 "gpc_reg_operand" "")
536 (sign_extend:DI (match_dup 1)))]
537 "TARGET_POWERPC64 && reload_completed"
538 [(set (match_dup 0)
539 (sign_extend:DI (match_dup 1)))
540 (set (match_dup 2)
541 (compare:CC (match_dup 0)
542 (const_int 0)))]
543 "")
544
545 (define_expand "extendhidi2"
546 [(set (match_operand:DI 0 "gpc_reg_operand" "")
547 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
548 "TARGET_POWERPC64"
549 "")
550
551 (define_insn ""
552 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
553 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
554 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
555 "@
556 lha%U1%X1 %0,%1
557 extsh %0,%1"
558 [(set_attr_alternative "type"
559 [(if_then_else
560 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
561 (const_string "load_ext_ux")
562 (if_then_else
563 (match_test "update_address_mem (operands[1], VOIDmode)")
564 (const_string "load_ext_u")
565 (const_string "load_ext")))
566 (const_string "exts")])])
567
568 (define_insn ""
569 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
570 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
571 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
572 "extsh %0,%1"
573 [(set_attr "type" "exts")])
574
575 (define_insn ""
576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
577 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
578 (const_int 0)))
579 (clobber (match_scratch:DI 2 "=r,r"))]
580 "TARGET_64BIT"
581 "@
582 extsh. %2,%1
583 #"
584 [(set_attr "type" "compare")
585 (set_attr "length" "4,8")])
586
587 (define_split
588 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
589 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
590 (const_int 0)))
591 (clobber (match_scratch:DI 2 ""))]
592 "TARGET_POWERPC64 && reload_completed"
593 [(set (match_dup 2)
594 (sign_extend:DI (match_dup 1)))
595 (set (match_dup 0)
596 (compare:CC (match_dup 2)
597 (const_int 0)))]
598 "")
599
600 (define_insn ""
601 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
602 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
603 (const_int 0)))
604 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
605 (sign_extend:DI (match_dup 1)))]
606 "TARGET_64BIT"
607 "@
608 extsh. %0,%1
609 #"
610 [(set_attr "type" "compare")
611 (set_attr "length" "4,8")])
612
613 (define_split
614 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
615 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
616 (const_int 0)))
617 (set (match_operand:DI 0 "gpc_reg_operand" "")
618 (sign_extend:DI (match_dup 1)))]
619 "TARGET_POWERPC64 && reload_completed"
620 [(set (match_dup 0)
621 (sign_extend:DI (match_dup 1)))
622 (set (match_dup 2)
623 (compare:CC (match_dup 0)
624 (const_int 0)))]
625 "")
626
627 (define_expand "extendsidi2"
628 [(set (match_operand:DI 0 "gpc_reg_operand" "")
629 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
630 "TARGET_POWERPC64"
631 "")
632
633 (define_insn "*extendsidi2_lfiwax"
634 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wm")
635 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]
636 "TARGET_POWERPC64 && TARGET_LFIWAX"
637 "@
638 lwa%U1%X1 %0,%1
639 extsw %0,%1
640 mtvsrwa %x0,%1
641 lfiwax %0,%y1
642 lxsiwax %x0,%y1"
643 [(set_attr_alternative "type"
644 [(if_then_else
645 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
646 (const_string "load_ext_ux")
647 (if_then_else
648 (match_test "update_address_mem (operands[1], VOIDmode)")
649 (const_string "load_ext_u")
650 (const_string "load_ext")))
651 (const_string "exts")
652 (const_string "mffgpr")
653 (const_string "fpload")
654 (const_string "fpload")])])
655
656 (define_insn "*extendsidi2_nocell"
657 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
658 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
659 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
660 "@
661 lwa%U1%X1 %0,%1
662 extsw %0,%1"
663 [(set_attr_alternative "type"
664 [(if_then_else
665 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
666 (const_string "load_ext_ux")
667 (if_then_else
668 (match_test "update_address_mem (operands[1], VOIDmode)")
669 (const_string "load_ext_u")
670 (const_string "load_ext")))
671 (const_string "exts")])])
672
673 (define_insn "*extendsidi2_nocell"
674 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
675 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
676 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
677 "extsw %0,%1"
678 [(set_attr "type" "exts")])
679
680 (define_insn ""
681 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
682 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
683 (const_int 0)))
684 (clobber (match_scratch:DI 2 "=r,r"))]
685 "TARGET_64BIT"
686 "@
687 extsw. %2,%1
688 #"
689 [(set_attr "type" "compare")
690 (set_attr "length" "4,8")])
691
692 (define_split
693 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
694 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
695 (const_int 0)))
696 (clobber (match_scratch:DI 2 ""))]
697 "TARGET_POWERPC64 && reload_completed"
698 [(set (match_dup 2)
699 (sign_extend:DI (match_dup 1)))
700 (set (match_dup 0)
701 (compare:CC (match_dup 2)
702 (const_int 0)))]
703 "")
704
705 (define_insn ""
706 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
707 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
708 (const_int 0)))
709 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
710 (sign_extend:DI (match_dup 1)))]
711 "TARGET_64BIT"
712 "@
713 extsw. %0,%1
714 #"
715 [(set_attr "type" "compare")
716 (set_attr "length" "4,8")])
717
718 (define_split
719 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
720 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
721 (const_int 0)))
722 (set (match_operand:DI 0 "gpc_reg_operand" "")
723 (sign_extend:DI (match_dup 1)))]
724 "TARGET_POWERPC64 && reload_completed"
725 [(set (match_dup 0)
726 (sign_extend:DI (match_dup 1)))
727 (set (match_dup 2)
728 (compare:CC (match_dup 0)
729 (const_int 0)))]
730 "")
731
732 (define_expand "zero_extendqisi2"
733 [(set (match_operand:SI 0 "gpc_reg_operand" "")
734 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
735 ""
736 "")
737
738 (define_insn ""
739 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
740 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
741 ""
742 "@
743 lbz%U1%X1 %0,%1
744 rlwinm %0,%1,0,0xff"
745 [(set_attr_alternative "type"
746 [(if_then_else
747 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
748 (const_string "load_ux")
749 (if_then_else
750 (match_test "update_address_mem (operands[1], VOIDmode)")
751 (const_string "load_u")
752 (const_string "load")))
753 (const_string "*")])])
754
755 (define_insn ""
756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
757 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
758 (const_int 0)))
759 (clobber (match_scratch:SI 2 "=r,r"))]
760 ""
761 "@
762 andi. %2,%1,0xff
763 #"
764 [(set_attr "type" "fast_compare,compare")
765 (set_attr "length" "4,8")])
766
767 (define_split
768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
769 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
770 (const_int 0)))
771 (clobber (match_scratch:SI 2 ""))]
772 "reload_completed"
773 [(set (match_dup 2)
774 (zero_extend:SI (match_dup 1)))
775 (set (match_dup 0)
776 (compare:CC (match_dup 2)
777 (const_int 0)))]
778 "")
779
780 (define_insn ""
781 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
782 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
783 (const_int 0)))
784 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
785 (zero_extend:SI (match_dup 1)))]
786 ""
787 "@
788 andi. %0,%1,0xff
789 #"
790 [(set_attr "type" "fast_compare,compare")
791 (set_attr "length" "4,8")])
792
793 (define_split
794 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
795 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
796 (const_int 0)))
797 (set (match_operand:SI 0 "gpc_reg_operand" "")
798 (zero_extend:SI (match_dup 1)))]
799 "reload_completed"
800 [(set (match_dup 0)
801 (zero_extend:SI (match_dup 1)))
802 (set (match_dup 2)
803 (compare:CC (match_dup 0)
804 (const_int 0)))]
805 "")
806
807 (define_insn "extendqisi2"
808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
809 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
810 ""
811 "extsb %0,%1"
812 [(set_attr "type" "exts")])
813
814 (define_insn ""
815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
816 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
817 (const_int 0)))
818 (clobber (match_scratch:SI 2 "=r,r"))]
819 ""
820 "@
821 extsb. %2,%1
822 #"
823 [(set_attr "type" "compare")
824 (set_attr "length" "4,8")])
825
826 (define_split
827 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
828 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
829 (const_int 0)))
830 (clobber (match_scratch:SI 2 ""))]
831 "reload_completed"
832 [(set (match_dup 2)
833 (sign_extend:SI (match_dup 1)))
834 (set (match_dup 0)
835 (compare:CC (match_dup 2)
836 (const_int 0)))]
837 "")
838
839 (define_insn ""
840 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
841 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
842 (const_int 0)))
843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
844 (sign_extend:SI (match_dup 1)))]
845 ""
846 "@
847 extsb. %0,%1
848 #"
849 [(set_attr "type" "compare")
850 (set_attr "length" "4,8")])
851
852 (define_split
853 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
854 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
855 (const_int 0)))
856 (set (match_operand:SI 0 "gpc_reg_operand" "")
857 (sign_extend:SI (match_dup 1)))]
858 "reload_completed"
859 [(set (match_dup 0)
860 (sign_extend:SI (match_dup 1)))
861 (set (match_dup 2)
862 (compare:CC (match_dup 0)
863 (const_int 0)))]
864 "")
865
866 (define_insn ""
867 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
868 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
869 ""
870 "@
871 lbz%U1%X1 %0,%1
872 rlwinm %0,%1,0,0xff"
873 [(set_attr_alternative "type"
874 [(if_then_else
875 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
876 (const_string "load_ux")
877 (if_then_else
878 (match_test "update_address_mem (operands[1], VOIDmode)")
879 (const_string "load_u")
880 (const_string "load")))
881 (const_string "*")])])
882
883 (define_insn ""
884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
885 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
886 (const_int 0)))
887 (clobber (match_scratch:HI 2 "=r,r"))]
888 ""
889 "@
890 andi. %2,%1,0xff
891 #"
892 [(set_attr "type" "fast_compare,compare")
893 (set_attr "length" "4,8")])
894
895 (define_split
896 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
897 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
898 (const_int 0)))
899 (clobber (match_scratch:HI 2 ""))]
900 "reload_completed"
901 [(set (match_dup 2)
902 (zero_extend:HI (match_dup 1)))
903 (set (match_dup 0)
904 (compare:CC (match_dup 2)
905 (const_int 0)))]
906 "")
907
908 (define_insn ""
909 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
910 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
911 (const_int 0)))
912 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
913 (zero_extend:HI (match_dup 1)))]
914 ""
915 "@
916 andi. %0,%1,0xff
917 #"
918 [(set_attr "type" "fast_compare,compare")
919 (set_attr "length" "4,8")])
920
921 (define_split
922 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
923 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
924 (const_int 0)))
925 (set (match_operand:HI 0 "gpc_reg_operand" "")
926 (zero_extend:HI (match_dup 1)))]
927 "reload_completed"
928 [(set (match_dup 0)
929 (zero_extend:HI (match_dup 1)))
930 (set (match_dup 2)
931 (compare:CC (match_dup 0)
932 (const_int 0)))]
933 "")
934
935 (define_insn "extendqihi2"
936 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
937 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
938 ""
939 "extsb %0,%1"
940 [(set_attr "type" "exts")])
941
942 (define_insn ""
943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
944 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
945 (const_int 0)))
946 (clobber (match_scratch:HI 2 "=r,r"))]
947 ""
948 "@
949 extsb. %2,%1
950 #"
951 [(set_attr "type" "compare")
952 (set_attr "length" "4,8")])
953
954 (define_split
955 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
956 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
957 (const_int 0)))
958 (clobber (match_scratch:HI 2 ""))]
959 "reload_completed"
960 [(set (match_dup 2)
961 (sign_extend:HI (match_dup 1)))
962 (set (match_dup 0)
963 (compare:CC (match_dup 2)
964 (const_int 0)))]
965 "")
966
967 (define_insn ""
968 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
969 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
970 (const_int 0)))
971 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
972 (sign_extend:HI (match_dup 1)))]
973 ""
974 "@
975 extsb. %0,%1
976 #"
977 [(set_attr "type" "compare")
978 (set_attr "length" "4,8")])
979
980 (define_split
981 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
982 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
983 (const_int 0)))
984 (set (match_operand:HI 0 "gpc_reg_operand" "")
985 (sign_extend:HI (match_dup 1)))]
986 "reload_completed"
987 [(set (match_dup 0)
988 (sign_extend:HI (match_dup 1)))
989 (set (match_dup 2)
990 (compare:CC (match_dup 0)
991 (const_int 0)))]
992 "")
993
994 (define_expand "zero_extendhisi2"
995 [(set (match_operand:SI 0 "gpc_reg_operand" "")
996 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
997 ""
998 "")
999
1000 (define_insn ""
1001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1002 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1003 ""
1004 "@
1005 lhz%U1%X1 %0,%1
1006 rlwinm %0,%1,0,0xffff"
1007 [(set_attr_alternative "type"
1008 [(if_then_else
1009 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1010 (const_string "load_ux")
1011 (if_then_else
1012 (match_test "update_address_mem (operands[1], VOIDmode)")
1013 (const_string "load_u")
1014 (const_string "load")))
1015 (const_string "*")])])
1016
1017 (define_insn ""
1018 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1019 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1020 (const_int 0)))
1021 (clobber (match_scratch:SI 2 "=r,r"))]
1022 ""
1023 "@
1024 andi. %2,%1,0xffff
1025 #"
1026 [(set_attr "type" "fast_compare,compare")
1027 (set_attr "length" "4,8")])
1028
1029 (define_split
1030 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1031 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1032 (const_int 0)))
1033 (clobber (match_scratch:SI 2 ""))]
1034 "reload_completed"
1035 [(set (match_dup 2)
1036 (zero_extend:SI (match_dup 1)))
1037 (set (match_dup 0)
1038 (compare:CC (match_dup 2)
1039 (const_int 0)))]
1040 "")
1041
1042 (define_insn ""
1043 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1044 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1045 (const_int 0)))
1046 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1047 (zero_extend:SI (match_dup 1)))]
1048 ""
1049 "@
1050 andi. %0,%1,0xffff
1051 #"
1052 [(set_attr "type" "fast_compare,compare")
1053 (set_attr "length" "4,8")])
1054
1055 (define_split
1056 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1057 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1058 (const_int 0)))
1059 (set (match_operand:SI 0 "gpc_reg_operand" "")
1060 (zero_extend:SI (match_dup 1)))]
1061 "reload_completed"
1062 [(set (match_dup 0)
1063 (zero_extend:SI (match_dup 1)))
1064 (set (match_dup 2)
1065 (compare:CC (match_dup 0)
1066 (const_int 0)))]
1067 "")
1068
1069 (define_expand "extendhisi2"
1070 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1071 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1072 ""
1073 "")
1074
1075 (define_insn ""
1076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1077 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1078 "rs6000_gen_cell_microcode"
1079 "@
1080 lha%U1%X1 %0,%1
1081 extsh %0,%1"
1082 [(set_attr_alternative "type"
1083 [(if_then_else
1084 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1085 (const_string "load_ext_ux")
1086 (if_then_else
1087 (match_test "update_address_mem (operands[1], VOIDmode)")
1088 (const_string "load_ext_u")
1089 (const_string "load_ext")))
1090 (const_string "exts")])])
1091
1092 (define_insn ""
1093 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1094 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1095 "!rs6000_gen_cell_microcode"
1096 "extsh %0,%1"
1097 [(set_attr "type" "exts")])
1098
1099 (define_insn ""
1100 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1101 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1102 (const_int 0)))
1103 (clobber (match_scratch:SI 2 "=r,r"))]
1104 ""
1105 "@
1106 extsh. %2,%1
1107 #"
1108 [(set_attr "type" "compare")
1109 (set_attr "length" "4,8")])
1110
1111 (define_split
1112 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1113 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1114 (const_int 0)))
1115 (clobber (match_scratch:SI 2 ""))]
1116 "reload_completed"
1117 [(set (match_dup 2)
1118 (sign_extend:SI (match_dup 1)))
1119 (set (match_dup 0)
1120 (compare:CC (match_dup 2)
1121 (const_int 0)))]
1122 "")
1123
1124 (define_insn ""
1125 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1126 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1127 (const_int 0)))
1128 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1129 (sign_extend:SI (match_dup 1)))]
1130 ""
1131 "@
1132 extsh. %0,%1
1133 #"
1134 [(set_attr "type" "compare")
1135 (set_attr "length" "4,8")])
1136
1137 (define_split
1138 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1139 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1140 (const_int 0)))
1141 (set (match_operand:SI 0 "gpc_reg_operand" "")
1142 (sign_extend:SI (match_dup 1)))]
1143 "reload_completed"
1144 [(set (match_dup 0)
1145 (sign_extend:SI (match_dup 1)))
1146 (set (match_dup 2)
1147 (compare:CC (match_dup 0)
1148 (const_int 0)))]
1149 "")
1150 \f
1151 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1152
1153 (define_insn "*macchwc"
1154 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1155 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1156 (match_operand:SI 2 "gpc_reg_operand" "r")
1157 (const_int 16))
1158 (sign_extend:SI
1159 (match_operand:HI 1 "gpc_reg_operand" "r")))
1160 (match_operand:SI 4 "gpc_reg_operand" "0"))
1161 (const_int 0)))
1162 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1163 (plus:SI (mult:SI (ashiftrt:SI
1164 (match_dup 2)
1165 (const_int 16))
1166 (sign_extend:SI
1167 (match_dup 1)))
1168 (match_dup 4)))]
1169 "TARGET_MULHW"
1170 "macchw. %0,%1,%2"
1171 [(set_attr "type" "imul3")])
1172
1173 (define_insn "*macchw"
1174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1175 (plus:SI (mult:SI (ashiftrt:SI
1176 (match_operand:SI 2 "gpc_reg_operand" "r")
1177 (const_int 16))
1178 (sign_extend:SI
1179 (match_operand:HI 1 "gpc_reg_operand" "r")))
1180 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1181 "TARGET_MULHW"
1182 "macchw %0,%1,%2"
1183 [(set_attr "type" "imul3")])
1184
1185 (define_insn "*macchwuc"
1186 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1187 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1188 (match_operand:SI 2 "gpc_reg_operand" "r")
1189 (const_int 16))
1190 (zero_extend:SI
1191 (match_operand:HI 1 "gpc_reg_operand" "r")))
1192 (match_operand:SI 4 "gpc_reg_operand" "0"))
1193 (const_int 0)))
1194 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1195 (plus:SI (mult:SI (lshiftrt:SI
1196 (match_dup 2)
1197 (const_int 16))
1198 (zero_extend:SI
1199 (match_dup 1)))
1200 (match_dup 4)))]
1201 "TARGET_MULHW"
1202 "macchwu. %0,%1,%2"
1203 [(set_attr "type" "imul3")])
1204
1205 (define_insn "*macchwu"
1206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1207 (plus:SI (mult:SI (lshiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1209 (const_int 16))
1210 (zero_extend:SI
1211 (match_operand:HI 1 "gpc_reg_operand" "r")))
1212 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1213 "TARGET_MULHW"
1214 "macchwu %0,%1,%2"
1215 [(set_attr "type" "imul3")])
1216
1217 (define_insn "*machhwc"
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1219 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1220 (match_operand:SI 1 "gpc_reg_operand" "%r")
1221 (const_int 16))
1222 (ashiftrt:SI
1223 (match_operand:SI 2 "gpc_reg_operand" "r")
1224 (const_int 16)))
1225 (match_operand:SI 4 "gpc_reg_operand" "0"))
1226 (const_int 0)))
1227 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1228 (plus:SI (mult:SI (ashiftrt:SI
1229 (match_dup 1)
1230 (const_int 16))
1231 (ashiftrt:SI
1232 (match_dup 2)
1233 (const_int 16)))
1234 (match_dup 4)))]
1235 "TARGET_MULHW"
1236 "machhw. %0,%1,%2"
1237 [(set_attr "type" "imul3")])
1238
1239 (define_insn "*machhw"
1240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1241 (plus:SI (mult:SI (ashiftrt:SI
1242 (match_operand:SI 1 "gpc_reg_operand" "%r")
1243 (const_int 16))
1244 (ashiftrt:SI
1245 (match_operand:SI 2 "gpc_reg_operand" "r")
1246 (const_int 16)))
1247 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1248 "TARGET_MULHW"
1249 "machhw %0,%1,%2"
1250 [(set_attr "type" "imul3")])
1251
1252 (define_insn "*machhwuc"
1253 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1254 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1255 (match_operand:SI 1 "gpc_reg_operand" "%r")
1256 (const_int 16))
1257 (lshiftrt:SI
1258 (match_operand:SI 2 "gpc_reg_operand" "r")
1259 (const_int 16)))
1260 (match_operand:SI 4 "gpc_reg_operand" "0"))
1261 (const_int 0)))
1262 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1263 (plus:SI (mult:SI (lshiftrt:SI
1264 (match_dup 1)
1265 (const_int 16))
1266 (lshiftrt:SI
1267 (match_dup 2)
1268 (const_int 16)))
1269 (match_dup 4)))]
1270 "TARGET_MULHW"
1271 "machhwu. %0,%1,%2"
1272 [(set_attr "type" "imul3")])
1273
1274 (define_insn "*machhwu"
1275 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1276 (plus:SI (mult:SI (lshiftrt:SI
1277 (match_operand:SI 1 "gpc_reg_operand" "%r")
1278 (const_int 16))
1279 (lshiftrt:SI
1280 (match_operand:SI 2 "gpc_reg_operand" "r")
1281 (const_int 16)))
1282 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1283 "TARGET_MULHW"
1284 "machhwu %0,%1,%2"
1285 [(set_attr "type" "imul3")])
1286
1287 (define_insn "*maclhwc"
1288 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1289 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1290 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1291 (sign_extend:SI
1292 (match_operand:HI 2 "gpc_reg_operand" "r")))
1293 (match_operand:SI 4 "gpc_reg_operand" "0"))
1294 (const_int 0)))
1295 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1296 (plus:SI (mult:SI (sign_extend:SI
1297 (match_dup 1))
1298 (sign_extend:SI
1299 (match_dup 2)))
1300 (match_dup 4)))]
1301 "TARGET_MULHW"
1302 "maclhw. %0,%1,%2"
1303 [(set_attr "type" "imul3")])
1304
1305 (define_insn "*maclhw"
1306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1307 (plus:SI (mult:SI (sign_extend:SI
1308 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1309 (sign_extend:SI
1310 (match_operand:HI 2 "gpc_reg_operand" "r")))
1311 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1312 "TARGET_MULHW"
1313 "maclhw %0,%1,%2"
1314 [(set_attr "type" "imul3")])
1315
1316 (define_insn "*maclhwuc"
1317 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1318 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1319 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1320 (zero_extend:SI
1321 (match_operand:HI 2 "gpc_reg_operand" "r")))
1322 (match_operand:SI 4 "gpc_reg_operand" "0"))
1323 (const_int 0)))
1324 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1325 (plus:SI (mult:SI (zero_extend:SI
1326 (match_dup 1))
1327 (zero_extend:SI
1328 (match_dup 2)))
1329 (match_dup 4)))]
1330 "TARGET_MULHW"
1331 "maclhwu. %0,%1,%2"
1332 [(set_attr "type" "imul3")])
1333
1334 (define_insn "*maclhwu"
1335 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1336 (plus:SI (mult:SI (zero_extend:SI
1337 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1338 (zero_extend:SI
1339 (match_operand:HI 2 "gpc_reg_operand" "r")))
1340 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1341 "TARGET_MULHW"
1342 "maclhwu %0,%1,%2"
1343 [(set_attr "type" "imul3")])
1344
1345 (define_insn "*nmacchwc"
1346 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1347 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1348 (mult:SI (ashiftrt:SI
1349 (match_operand:SI 2 "gpc_reg_operand" "r")
1350 (const_int 16))
1351 (sign_extend:SI
1352 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1353 (const_int 0)))
1354 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1355 (minus:SI (match_dup 4)
1356 (mult:SI (ashiftrt:SI
1357 (match_dup 2)
1358 (const_int 16))
1359 (sign_extend:SI
1360 (match_dup 1)))))]
1361 "TARGET_MULHW"
1362 "nmacchw. %0,%1,%2"
1363 [(set_attr "type" "imul3")])
1364
1365 (define_insn "*nmacchw"
1366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1367 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1368 (mult:SI (ashiftrt:SI
1369 (match_operand:SI 2 "gpc_reg_operand" "r")
1370 (const_int 16))
1371 (sign_extend:SI
1372 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1373 "TARGET_MULHW"
1374 "nmacchw %0,%1,%2"
1375 [(set_attr "type" "imul3")])
1376
1377 (define_insn "*nmachhwc"
1378 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1379 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1380 (mult:SI (ashiftrt:SI
1381 (match_operand:SI 1 "gpc_reg_operand" "%r")
1382 (const_int 16))
1383 (ashiftrt:SI
1384 (match_operand:SI 2 "gpc_reg_operand" "r")
1385 (const_int 16))))
1386 (const_int 0)))
1387 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1388 (minus:SI (match_dup 4)
1389 (mult:SI (ashiftrt:SI
1390 (match_dup 1)
1391 (const_int 16))
1392 (ashiftrt:SI
1393 (match_dup 2)
1394 (const_int 16)))))]
1395 "TARGET_MULHW"
1396 "nmachhw. %0,%1,%2"
1397 [(set_attr "type" "imul3")])
1398
1399 (define_insn "*nmachhw"
1400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1401 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1402 (mult:SI (ashiftrt:SI
1403 (match_operand:SI 1 "gpc_reg_operand" "%r")
1404 (const_int 16))
1405 (ashiftrt:SI
1406 (match_operand:SI 2 "gpc_reg_operand" "r")
1407 (const_int 16)))))]
1408 "TARGET_MULHW"
1409 "nmachhw %0,%1,%2"
1410 [(set_attr "type" "imul3")])
1411
1412 (define_insn "*nmaclhwc"
1413 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1414 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1415 (mult:SI (sign_extend:SI
1416 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1417 (sign_extend:SI
1418 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1419 (const_int 0)))
1420 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1421 (minus:SI (match_dup 4)
1422 (mult:SI (sign_extend:SI
1423 (match_dup 1))
1424 (sign_extend:SI
1425 (match_dup 2)))))]
1426 "TARGET_MULHW"
1427 "nmaclhw. %0,%1,%2"
1428 [(set_attr "type" "imul3")])
1429
1430 (define_insn "*nmaclhw"
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1433 (mult:SI (sign_extend:SI
1434 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1435 (sign_extend:SI
1436 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1437 "TARGET_MULHW"
1438 "nmaclhw %0,%1,%2"
1439 [(set_attr "type" "imul3")])
1440
1441 (define_insn "*mulchwc"
1442 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1443 (compare:CC (mult:SI (ashiftrt:SI
1444 (match_operand:SI 2 "gpc_reg_operand" "r")
1445 (const_int 16))
1446 (sign_extend:SI
1447 (match_operand:HI 1 "gpc_reg_operand" "r")))
1448 (const_int 0)))
1449 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1450 (mult:SI (ashiftrt:SI
1451 (match_dup 2)
1452 (const_int 16))
1453 (sign_extend:SI
1454 (match_dup 1))))]
1455 "TARGET_MULHW"
1456 "mulchw. %0,%1,%2"
1457 [(set_attr "type" "imul3")])
1458
1459 (define_insn "*mulchw"
1460 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1461 (mult:SI (ashiftrt:SI
1462 (match_operand:SI 2 "gpc_reg_operand" "r")
1463 (const_int 16))
1464 (sign_extend:SI
1465 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1466 "TARGET_MULHW"
1467 "mulchw %0,%1,%2"
1468 [(set_attr "type" "imul3")])
1469
1470 (define_insn "*mulchwuc"
1471 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1472 (compare:CC (mult:SI (lshiftrt:SI
1473 (match_operand:SI 2 "gpc_reg_operand" "r")
1474 (const_int 16))
1475 (zero_extend:SI
1476 (match_operand:HI 1 "gpc_reg_operand" "r")))
1477 (const_int 0)))
1478 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1479 (mult:SI (lshiftrt:SI
1480 (match_dup 2)
1481 (const_int 16))
1482 (zero_extend:SI
1483 (match_dup 1))))]
1484 "TARGET_MULHW"
1485 "mulchwu. %0,%1,%2"
1486 [(set_attr "type" "imul3")])
1487
1488 (define_insn "*mulchwu"
1489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1490 (mult:SI (lshiftrt:SI
1491 (match_operand:SI 2 "gpc_reg_operand" "r")
1492 (const_int 16))
1493 (zero_extend:SI
1494 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1495 "TARGET_MULHW"
1496 "mulchwu %0,%1,%2"
1497 [(set_attr "type" "imul3")])
1498
1499 (define_insn "*mulhhwc"
1500 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1501 (compare:CC (mult:SI (ashiftrt:SI
1502 (match_operand:SI 1 "gpc_reg_operand" "%r")
1503 (const_int 16))
1504 (ashiftrt:SI
1505 (match_operand:SI 2 "gpc_reg_operand" "r")
1506 (const_int 16)))
1507 (const_int 0)))
1508 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1509 (mult:SI (ashiftrt:SI
1510 (match_dup 1)
1511 (const_int 16))
1512 (ashiftrt:SI
1513 (match_dup 2)
1514 (const_int 16))))]
1515 "TARGET_MULHW"
1516 "mulhhw. %0,%1,%2"
1517 [(set_attr "type" "imul3")])
1518
1519 (define_insn "*mulhhw"
1520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1521 (mult:SI (ashiftrt:SI
1522 (match_operand:SI 1 "gpc_reg_operand" "%r")
1523 (const_int 16))
1524 (ashiftrt:SI
1525 (match_operand:SI 2 "gpc_reg_operand" "r")
1526 (const_int 16))))]
1527 "TARGET_MULHW"
1528 "mulhhw %0,%1,%2"
1529 [(set_attr "type" "imul3")])
1530
1531 (define_insn "*mulhhwuc"
1532 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1533 (compare:CC (mult:SI (lshiftrt:SI
1534 (match_operand:SI 1 "gpc_reg_operand" "%r")
1535 (const_int 16))
1536 (lshiftrt:SI
1537 (match_operand:SI 2 "gpc_reg_operand" "r")
1538 (const_int 16)))
1539 (const_int 0)))
1540 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1541 (mult:SI (lshiftrt:SI
1542 (match_dup 1)
1543 (const_int 16))
1544 (lshiftrt:SI
1545 (match_dup 2)
1546 (const_int 16))))]
1547 "TARGET_MULHW"
1548 "mulhhwu. %0,%1,%2"
1549 [(set_attr "type" "imul3")])
1550
1551 (define_insn "*mulhhwu"
1552 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1553 (mult:SI (lshiftrt:SI
1554 (match_operand:SI 1 "gpc_reg_operand" "%r")
1555 (const_int 16))
1556 (lshiftrt:SI
1557 (match_operand:SI 2 "gpc_reg_operand" "r")
1558 (const_int 16))))]
1559 "TARGET_MULHW"
1560 "mulhhwu %0,%1,%2"
1561 [(set_attr "type" "imul3")])
1562
1563 (define_insn "*mullhwc"
1564 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1565 (compare:CC (mult:SI (sign_extend:SI
1566 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1567 (sign_extend:SI
1568 (match_operand:HI 2 "gpc_reg_operand" "r")))
1569 (const_int 0)))
1570 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1571 (mult:SI (sign_extend:SI
1572 (match_dup 1))
1573 (sign_extend:SI
1574 (match_dup 2))))]
1575 "TARGET_MULHW"
1576 "mullhw. %0,%1,%2"
1577 [(set_attr "type" "imul3")])
1578
1579 (define_insn "*mullhw"
1580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1581 (mult:SI (sign_extend:SI
1582 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1583 (sign_extend:SI
1584 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1585 "TARGET_MULHW"
1586 "mullhw %0,%1,%2"
1587 [(set_attr "type" "imul3")])
1588
1589 (define_insn "*mullhwuc"
1590 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1591 (compare:CC (mult:SI (zero_extend:SI
1592 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1593 (zero_extend:SI
1594 (match_operand:HI 2 "gpc_reg_operand" "r")))
1595 (const_int 0)))
1596 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1597 (mult:SI (zero_extend:SI
1598 (match_dup 1))
1599 (zero_extend:SI
1600 (match_dup 2))))]
1601 "TARGET_MULHW"
1602 "mullhwu. %0,%1,%2"
1603 [(set_attr "type" "imul3")])
1604
1605 (define_insn "*mullhwu"
1606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1607 (mult:SI (zero_extend:SI
1608 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1609 (zero_extend:SI
1610 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1611 "TARGET_MULHW"
1612 "mullhwu %0,%1,%2"
1613 [(set_attr "type" "imul3")])
1614 \f
1615 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1616 (define_insn "dlmzb"
1617 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1618 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1619 (match_operand:SI 2 "gpc_reg_operand" "r")]
1620 UNSPEC_DLMZB_CR))
1621 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1622 (unspec:SI [(match_dup 1)
1623 (match_dup 2)]
1624 UNSPEC_DLMZB))]
1625 "TARGET_DLMZB"
1626 "dlmzb. %0,%1,%2")
1627
1628 (define_expand "strlensi"
1629 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1630 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1631 (match_operand:QI 2 "const_int_operand" "")
1632 (match_operand 3 "const_int_operand" "")]
1633 UNSPEC_DLMZB_STRLEN))
1634 (clobber (match_scratch:CC 4 "=x"))]
1635 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1636 {
1637 rtx result = operands[0];
1638 rtx src = operands[1];
1639 rtx search_char = operands[2];
1640 rtx align = operands[3];
1641 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1642 rtx loop_label, end_label, mem, cr0, cond;
1643 if (search_char != const0_rtx
1644 || GET_CODE (align) != CONST_INT
1645 || INTVAL (align) < 8)
1646 FAIL;
1647 word1 = gen_reg_rtx (SImode);
1648 word2 = gen_reg_rtx (SImode);
1649 scratch_dlmzb = gen_reg_rtx (SImode);
1650 scratch_string = gen_reg_rtx (Pmode);
1651 loop_label = gen_label_rtx ();
1652 end_label = gen_label_rtx ();
1653 addr = force_reg (Pmode, XEXP (src, 0));
1654 emit_move_insn (scratch_string, addr);
1655 emit_label (loop_label);
1656 mem = change_address (src, SImode, scratch_string);
1657 emit_move_insn (word1, mem);
1658 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1659 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1660 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1661 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1662 emit_jump_insn (gen_rtx_SET (VOIDmode,
1663 pc_rtx,
1664 gen_rtx_IF_THEN_ELSE (VOIDmode,
1665 cond,
1666 gen_rtx_LABEL_REF
1667 (VOIDmode,
1668 end_label),
1669 pc_rtx)));
1670 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1671 emit_jump_insn (gen_rtx_SET (VOIDmode,
1672 pc_rtx,
1673 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1674 emit_barrier ();
1675 emit_label (end_label);
1676 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1677 emit_insn (gen_subsi3 (result, scratch_string, addr));
1678 emit_insn (gen_subsi3 (result, result, const1_rtx));
1679 DONE;
1680 })
1681 \f
1682 ;; Fixed-point arithmetic insns.
1683
1684 (define_expand "add<mode>3"
1685 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1686 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1687 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1688 ""
1689 {
1690 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1691 {
1692 if (non_short_cint_operand (operands[2], DImode))
1693 FAIL;
1694 }
1695 else if (GET_CODE (operands[2]) == CONST_INT
1696 && ! add_operand (operands[2], <MODE>mode))
1697 {
1698 rtx tmp = ((!can_create_pseudo_p ()
1699 || rtx_equal_p (operands[0], operands[1]))
1700 ? operands[0] : gen_reg_rtx (<MODE>mode));
1701
1702 HOST_WIDE_INT val = INTVAL (operands[2]);
1703 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1704 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1705
1706 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1707 FAIL;
1708
1709 /* The ordering here is important for the prolog expander.
1710 When space is allocated from the stack, adding 'low' first may
1711 produce a temporary deallocation (which would be bad). */
1712 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1713 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1714 DONE;
1715 }
1716 })
1717
1718 ;; Discourage ai/addic because of carry but provide it in an alternative
1719 ;; allowing register zero as source.
1720 (define_insn "*add<mode>3_internal1"
1721 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1722 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1723 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1724 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1725 "@
1726 add %0,%1,%2
1727 addi %0,%1,%2
1728 addic %0,%1,%2
1729 addis %0,%1,%v2"
1730 [(set_attr "length" "4,4,4,4")])
1731
1732 (define_insn "addsi3_high"
1733 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1734 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1735 (high:SI (match_operand 2 "" ""))))]
1736 "TARGET_MACHO && !TARGET_64BIT"
1737 "addis %0,%1,ha16(%2)"
1738 [(set_attr "length" "4")])
1739
1740 (define_insn "*add<mode>3_internal2"
1741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1742 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1743 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1744 (const_int 0)))
1745 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1746 ""
1747 "@
1748 add. %3,%1,%2
1749 addic. %3,%1,%2
1750 #
1751 #"
1752 [(set_attr "type" "fast_compare,compare,compare,compare")
1753 (set_attr "length" "4,4,8,8")])
1754
1755 (define_split
1756 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1757 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1758 (match_operand:GPR 2 "reg_or_short_operand" ""))
1759 (const_int 0)))
1760 (clobber (match_scratch:GPR 3 ""))]
1761 "reload_completed"
1762 [(set (match_dup 3)
1763 (plus:GPR (match_dup 1)
1764 (match_dup 2)))
1765 (set (match_dup 0)
1766 (compare:CC (match_dup 3)
1767 (const_int 0)))]
1768 "")
1769
1770 (define_insn "*add<mode>3_internal3"
1771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1772 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1773 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1774 (const_int 0)))
1775 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1776 (plus:P (match_dup 1)
1777 (match_dup 2)))]
1778 ""
1779 "@
1780 add. %0,%1,%2
1781 addic. %0,%1,%2
1782 #
1783 #"
1784 [(set_attr "type" "fast_compare,compare,compare,compare")
1785 (set_attr "length" "4,4,8,8")])
1786
1787 (define_split
1788 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1789 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1790 (match_operand:P 2 "reg_or_short_operand" ""))
1791 (const_int 0)))
1792 (set (match_operand:P 0 "gpc_reg_operand" "")
1793 (plus:P (match_dup 1) (match_dup 2)))]
1794 "reload_completed"
1795 [(set (match_dup 0)
1796 (plus:P (match_dup 1)
1797 (match_dup 2)))
1798 (set (match_dup 3)
1799 (compare:CC (match_dup 0)
1800 (const_int 0)))]
1801 "")
1802
1803 ;; Split an add that we can't do in one insn into two insns, each of which
1804 ;; does one 16-bit part. This is used by combine. Note that the low-order
1805 ;; add should be last in case the result gets used in an address.
1806
1807 (define_split
1808 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1809 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1810 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1811 ""
1812 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1813 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1814 {
1815 HOST_WIDE_INT val = INTVAL (operands[2]);
1816 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1817 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1818
1819 operands[4] = GEN_INT (low);
1820 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1821 operands[3] = GEN_INT (rest);
1822 else if (can_create_pseudo_p ())
1823 {
1824 operands[3] = gen_reg_rtx (DImode);
1825 emit_move_insn (operands[3], operands[2]);
1826 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1827 DONE;
1828 }
1829 else
1830 FAIL;
1831 })
1832
1833 (define_insn "one_cmpl<mode>2"
1834 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1835 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1836 ""
1837 "nor %0,%1,%1")
1838
1839 (define_insn ""
1840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1841 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1842 (const_int 0)))
1843 (clobber (match_scratch:P 2 "=r,r"))]
1844 ""
1845 "@
1846 nor. %2,%1,%1
1847 #"
1848 [(set_attr "type" "fast_compare,compare")
1849 (set_attr "length" "4,8")])
1850
1851 (define_split
1852 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1853 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1854 (const_int 0)))
1855 (clobber (match_scratch:P 2 ""))]
1856 "reload_completed"
1857 [(set (match_dup 2)
1858 (not:P (match_dup 1)))
1859 (set (match_dup 0)
1860 (compare:CC (match_dup 2)
1861 (const_int 0)))]
1862 "")
1863
1864 (define_insn ""
1865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1866 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1867 (const_int 0)))
1868 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1869 (not:P (match_dup 1)))]
1870 ""
1871 "@
1872 nor. %0,%1,%1
1873 #"
1874 [(set_attr "type" "fast_compare,compare")
1875 (set_attr "length" "4,8")])
1876
1877 (define_split
1878 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1879 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1880 (const_int 0)))
1881 (set (match_operand:P 0 "gpc_reg_operand" "")
1882 (not:P (match_dup 1)))]
1883 "reload_completed"
1884 [(set (match_dup 0)
1885 (not:P (match_dup 1)))
1886 (set (match_dup 2)
1887 (compare:CC (match_dup 0)
1888 (const_int 0)))]
1889 "")
1890
1891 (define_insn ""
1892 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1893 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1894 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1895 ""
1896 "@
1897 subf %0,%2,%1
1898 subfic %0,%2,%1")
1899
1900 (define_insn ""
1901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1902 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1903 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1904 (const_int 0)))
1905 (clobber (match_scratch:P 3 "=r,r"))]
1906 ""
1907 "@
1908 subf. %3,%2,%1
1909 #"
1910 [(set_attr "type" "fast_compare")
1911 (set_attr "length" "4,8")])
1912
1913 (define_split
1914 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1915 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1916 (match_operand:P 2 "gpc_reg_operand" ""))
1917 (const_int 0)))
1918 (clobber (match_scratch:P 3 ""))]
1919 "reload_completed"
1920 [(set (match_dup 3)
1921 (minus:P (match_dup 1)
1922 (match_dup 2)))
1923 (set (match_dup 0)
1924 (compare:CC (match_dup 3)
1925 (const_int 0)))]
1926 "")
1927
1928 (define_insn ""
1929 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1930 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1931 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1932 (const_int 0)))
1933 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1934 (minus:P (match_dup 1)
1935 (match_dup 2)))]
1936 ""
1937 "@
1938 subf. %0,%2,%1
1939 #"
1940 [(set_attr "type" "fast_compare")
1941 (set_attr "length" "4,8")])
1942
1943 (define_split
1944 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1945 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1946 (match_operand:P 2 "gpc_reg_operand" ""))
1947 (const_int 0)))
1948 (set (match_operand:P 0 "gpc_reg_operand" "")
1949 (minus:P (match_dup 1)
1950 (match_dup 2)))]
1951 "reload_completed"
1952 [(set (match_dup 0)
1953 (minus:P (match_dup 1)
1954 (match_dup 2)))
1955 (set (match_dup 3)
1956 (compare:CC (match_dup 0)
1957 (const_int 0)))]
1958 "")
1959
1960 (define_expand "sub<mode>3"
1961 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1962 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1963 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1964 ""
1965 "
1966 {
1967 if (GET_CODE (operands[2]) == CONST_INT)
1968 {
1969 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1970 negate_rtx (<MODE>mode, operands[2])));
1971 DONE;
1972 }
1973 }")
1974
1975 (define_expand "neg<mode>2"
1976 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1977 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1978 ""
1979 "")
1980
1981 (define_insn "*neg<mode>2_internal"
1982 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1983 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1984 ""
1985 "neg %0,%1")
1986
1987 (define_insn ""
1988 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1989 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1990 (const_int 0)))
1991 (clobber (match_scratch:P 2 "=r,r"))]
1992 ""
1993 "@
1994 neg. %2,%1
1995 #"
1996 [(set_attr "type" "fast_compare")
1997 (set_attr "length" "4,8")])
1998
1999 (define_split
2000 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2001 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2002 (const_int 0)))
2003 (clobber (match_scratch:P 2 ""))]
2004 "reload_completed"
2005 [(set (match_dup 2)
2006 (neg:P (match_dup 1)))
2007 (set (match_dup 0)
2008 (compare:CC (match_dup 2)
2009 (const_int 0)))]
2010 "")
2011
2012 (define_insn ""
2013 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2014 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2015 (const_int 0)))
2016 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2017 (neg:P (match_dup 1)))]
2018 ""
2019 "@
2020 neg. %0,%1
2021 #"
2022 [(set_attr "type" "fast_compare")
2023 (set_attr "length" "4,8")])
2024
2025 (define_split
2026 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2027 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2028 (const_int 0)))
2029 (set (match_operand:P 0 "gpc_reg_operand" "")
2030 (neg:P (match_dup 1)))]
2031 "reload_completed"
2032 [(set (match_dup 0)
2033 (neg:P (match_dup 1)))
2034 (set (match_dup 2)
2035 (compare:CC (match_dup 0)
2036 (const_int 0)))]
2037 "")
2038
2039 (define_insn "clz<mode>2"
2040 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2041 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2042 ""
2043 "cntlz<wd> %0,%1"
2044 [(set_attr "type" "cntlz")])
2045
2046 (define_expand "ctz<mode>2"
2047 [(set (match_dup 2)
2048 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2049 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2050 (match_dup 2)))
2051 (clobber (scratch:CC))])
2052 (set (match_dup 4) (clz:GPR (match_dup 3)))
2053 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2054 (minus:GPR (match_dup 5) (match_dup 4)))]
2055 ""
2056 {
2057 operands[2] = gen_reg_rtx (<MODE>mode);
2058 operands[3] = gen_reg_rtx (<MODE>mode);
2059 operands[4] = gen_reg_rtx (<MODE>mode);
2060 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2061 })
2062
2063 (define_expand "ffs<mode>2"
2064 [(set (match_dup 2)
2065 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2066 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2067 (match_dup 2)))
2068 (clobber (scratch:CC))])
2069 (set (match_dup 4) (clz:GPR (match_dup 3)))
2070 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2071 (minus:GPR (match_dup 5) (match_dup 4)))]
2072 ""
2073 {
2074 operands[2] = gen_reg_rtx (<MODE>mode);
2075 operands[3] = gen_reg_rtx (<MODE>mode);
2076 operands[4] = gen_reg_rtx (<MODE>mode);
2077 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2078 })
2079
2080 (define_insn "popcntb<mode>2"
2081 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2082 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2083 UNSPEC_POPCNTB))]
2084 "TARGET_POPCNTB"
2085 "popcntb %0,%1"
2086 [(set_attr "length" "4")
2087 (set_attr "type" "popcnt")])
2088
2089 (define_insn "popcntd<mode>2"
2090 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2091 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2092 "TARGET_POPCNTD"
2093 "popcnt<wd> %0,%1"
2094 [(set_attr "length" "4")
2095 (set_attr "type" "popcnt")])
2096
2097 (define_expand "popcount<mode>2"
2098 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2099 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2100 "TARGET_POPCNTB || TARGET_POPCNTD"
2101 {
2102 rs6000_emit_popcount (operands[0], operands[1]);
2103 DONE;
2104 })
2105
2106 (define_insn "parity<mode>2_cmpb"
2107 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2108 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2109 "TARGET_CMPB && TARGET_POPCNTB"
2110 "prty<wd> %0,%1"
2111 [(set_attr "length" "4")
2112 (set_attr "type" "popcnt")])
2113
2114 (define_expand "parity<mode>2"
2115 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2116 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2117 "TARGET_POPCNTB"
2118 {
2119 rs6000_emit_parity (operands[0], operands[1]);
2120 DONE;
2121 })
2122
2123 ;; Since the hardware zeros the upper part of the register, save generating the
2124 ;; AND immediate if we are converting to unsigned
2125 (define_insn "*bswaphi2_extenddi"
2126 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2127 (zero_extend:DI
2128 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2129 "TARGET_POWERPC64"
2130 "lhbrx %0,%y1"
2131 [(set_attr "length" "4")
2132 (set_attr "type" "load")])
2133
2134 (define_insn "*bswaphi2_extendsi"
2135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2136 (zero_extend:SI
2137 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2138 ""
2139 "lhbrx %0,%y1"
2140 [(set_attr "length" "4")
2141 (set_attr "type" "load")])
2142
2143 (define_expand "bswaphi2"
2144 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2145 (bswap:HI
2146 (match_operand:HI 1 "reg_or_mem_operand" "")))
2147 (clobber (match_scratch:SI 2 ""))])]
2148 ""
2149 {
2150 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2151 operands[1] = force_reg (HImode, operands[1]);
2152 })
2153
2154 (define_insn "bswaphi2_internal"
2155 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2156 (bswap:HI
2157 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2158 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2159 ""
2160 "@
2161 lhbrx %0,%y1
2162 sthbrx %1,%y0
2163 #"
2164 [(set_attr "length" "4,4,12")
2165 (set_attr "type" "load,store,*")])
2166
2167 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2168 ;; correct for -mlittle as well as -mbig.
2169 (define_split
2170 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2171 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2172 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2173 "reload_completed"
2174 [(set (match_dup 3)
2175 (zero_extract:SI (match_dup 4)
2176 (const_int 8)
2177 (const_int 16)))
2178 (set (match_dup 2)
2179 (and:SI (ashift:SI (match_dup 4)
2180 (const_int 8))
2181 (const_int 65280))) ;; 0xff00
2182 (set (match_dup 3)
2183 (ior:SI (match_dup 3)
2184 (match_dup 2)))]
2185 "
2186 {
2187 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2188 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2189 }")
2190
2191 (define_insn "*bswapsi2_extenddi"
2192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2193 (zero_extend:DI
2194 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2195 "TARGET_POWERPC64"
2196 "lwbrx %0,%y1"
2197 [(set_attr "length" "4")
2198 (set_attr "type" "load")])
2199
2200 (define_expand "bswapsi2"
2201 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2202 (bswap:SI
2203 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2204 ""
2205 {
2206 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2207 operands[1] = force_reg (SImode, operands[1]);
2208 })
2209
2210 (define_insn "*bswapsi2_internal"
2211 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2212 (bswap:SI
2213 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2214 ""
2215 "@
2216 lwbrx %0,%y1
2217 stwbrx %1,%y0
2218 #"
2219 [(set_attr "length" "4,4,12")
2220 (set_attr "type" "load,store,*")])
2221
2222 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2223 ;; zero_extract insns do not change for -mlittle.
2224 (define_split
2225 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2226 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2227 "reload_completed"
2228 [(set (match_dup 0)
2229 (rotate:SI (match_dup 1) (const_int 8)))
2230 (set (zero_extract:SI (match_dup 0)
2231 (const_int 8)
2232 (const_int 0))
2233 (match_dup 1))
2234 (set (zero_extract:SI (match_dup 0)
2235 (const_int 8)
2236 (const_int 16))
2237 (rotate:SI (match_dup 1)
2238 (const_int 16)))]
2239 "")
2240
2241 (define_expand "bswapdi2"
2242 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2243 (bswap:DI
2244 (match_operand:DI 1 "reg_or_mem_operand" "")))
2245 (clobber (match_scratch:DI 2 ""))
2246 (clobber (match_scratch:DI 3 ""))
2247 (clobber (match_scratch:DI 4 ""))])]
2248 ""
2249 {
2250 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2251 operands[1] = force_reg (DImode, operands[1]);
2252
2253 if (!TARGET_POWERPC64)
2254 {
2255 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2256 that uses 64-bit registers needs the same scratch registers as 64-bit
2257 mode. */
2258 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2259 DONE;
2260 }
2261 })
2262
2263 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2264 (define_insn "*bswapdi2_ldbrx"
2265 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2266 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2267 (clobber (match_scratch:DI 2 "=X,X,&r"))
2268 (clobber (match_scratch:DI 3 "=X,X,&r"))
2269 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2270 "TARGET_POWERPC64 && TARGET_LDBRX
2271 && (REG_P (operands[0]) || REG_P (operands[1]))"
2272 "@
2273 ldbrx %0,%y1
2274 stdbrx %1,%y0
2275 #"
2276 [(set_attr "length" "4,4,36")
2277 (set_attr "type" "load,store,*")])
2278
2279 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2280 (define_insn "*bswapdi2_64bit"
2281 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2282 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2283 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2284 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2285 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2286 "TARGET_POWERPC64 && !TARGET_LDBRX
2287 && (REG_P (operands[0]) || REG_P (operands[1]))"
2288 "#"
2289 [(set_attr "length" "16,12,36")])
2290
2291 (define_split
2292 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2293 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2294 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2295 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2296 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2297 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2298 [(const_int 0)]
2299 "
2300 {
2301 rtx dest = operands[0];
2302 rtx src = operands[1];
2303 rtx op2 = operands[2];
2304 rtx op3 = operands[3];
2305 rtx op4 = operands[4];
2306 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2307 BYTES_BIG_ENDIAN ? 4 : 0);
2308 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2309 BYTES_BIG_ENDIAN ? 4 : 0);
2310 rtx addr1;
2311 rtx addr2;
2312 rtx word_high;
2313 rtx word_low;
2314
2315 addr1 = XEXP (src, 0);
2316 if (GET_CODE (addr1) == PLUS)
2317 {
2318 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2319 if (TARGET_AVOID_XFORM)
2320 {
2321 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2322 addr2 = op2;
2323 }
2324 else
2325 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2326 }
2327 else if (TARGET_AVOID_XFORM)
2328 {
2329 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2330 addr2 = op2;
2331 }
2332 else
2333 {
2334 emit_move_insn (op2, GEN_INT (4));
2335 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2336 }
2337
2338 if (BYTES_BIG_ENDIAN)
2339 {
2340 word_high = change_address (src, SImode, addr1);
2341 word_low = change_address (src, SImode, addr2);
2342 }
2343 else
2344 {
2345 word_high = change_address (src, SImode, addr2);
2346 word_low = change_address (src, SImode, addr1);
2347 }
2348
2349 emit_insn (gen_bswapsi2 (op3_32, word_low));
2350 emit_insn (gen_bswapsi2 (op4_32, word_high));
2351 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2352 emit_insn (gen_iordi3 (dest, dest, op4));
2353 }")
2354
2355 (define_split
2356 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2357 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2358 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2359 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2360 (clobber (match_operand:DI 4 "" ""))]
2361 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2362 [(const_int 0)]
2363 "
2364 {
2365 rtx dest = operands[0];
2366 rtx src = operands[1];
2367 rtx op2 = operands[2];
2368 rtx op3 = operands[3];
2369 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2370 BYTES_BIG_ENDIAN ? 4 : 0);
2371 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2372 BYTES_BIG_ENDIAN ? 4 : 0);
2373 rtx addr1;
2374 rtx addr2;
2375 rtx word_high;
2376 rtx word_low;
2377
2378 addr1 = XEXP (dest, 0);
2379 if (GET_CODE (addr1) == PLUS)
2380 {
2381 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2382 if (TARGET_AVOID_XFORM)
2383 {
2384 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2385 addr2 = op2;
2386 }
2387 else
2388 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2389 }
2390 else if (TARGET_AVOID_XFORM)
2391 {
2392 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2393 addr2 = op2;
2394 }
2395 else
2396 {
2397 emit_move_insn (op2, GEN_INT (4));
2398 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2399 }
2400
2401 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2402 if (BYTES_BIG_ENDIAN)
2403 {
2404 word_high = change_address (dest, SImode, addr1);
2405 word_low = change_address (dest, SImode, addr2);
2406 }
2407 else
2408 {
2409 word_high = change_address (dest, SImode, addr2);
2410 word_low = change_address (dest, SImode, addr1);
2411 }
2412 emit_insn (gen_bswapsi2 (word_high, src_si));
2413 emit_insn (gen_bswapsi2 (word_low, op3_si));
2414 }")
2415
2416 (define_split
2417 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2418 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2419 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2420 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2421 (clobber (match_operand:DI 4 "" ""))]
2422 "TARGET_POWERPC64 && reload_completed"
2423 [(const_int 0)]
2424 "
2425 {
2426 rtx dest = operands[0];
2427 rtx src = operands[1];
2428 rtx op2 = operands[2];
2429 rtx op3 = operands[3];
2430 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2431 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2432 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2433 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2434 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2435
2436 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2437 emit_insn (gen_bswapsi2 (dest_si, src_si));
2438 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2439 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2440 emit_insn (gen_iordi3 (dest, dest, op3));
2441 }")
2442
2443 (define_insn "bswapdi2_32bit"
2444 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2445 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2446 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2447 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2448 "#"
2449 [(set_attr "length" "16,12,36")])
2450
2451 (define_split
2452 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2453 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2454 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2455 "!TARGET_POWERPC64 && reload_completed"
2456 [(const_int 0)]
2457 "
2458 {
2459 rtx dest = operands[0];
2460 rtx src = operands[1];
2461 rtx op2 = operands[2];
2462 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2463 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2464 rtx addr1;
2465 rtx addr2;
2466 rtx word1;
2467 rtx word2;
2468
2469 addr1 = XEXP (src, 0);
2470 if (GET_CODE (addr1) == PLUS)
2471 {
2472 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2473 if (TARGET_AVOID_XFORM)
2474 {
2475 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2476 addr2 = op2;
2477 }
2478 else
2479 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2480 }
2481 else if (TARGET_AVOID_XFORM)
2482 {
2483 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2484 addr2 = op2;
2485 }
2486 else
2487 {
2488 emit_move_insn (op2, GEN_INT (4));
2489 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2490 }
2491
2492 word1 = change_address (src, SImode, addr1);
2493 word2 = change_address (src, SImode, addr2);
2494
2495 emit_insn (gen_bswapsi2 (dest2, word1));
2496 emit_insn (gen_bswapsi2 (dest1, word2));
2497 }")
2498
2499 (define_split
2500 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2501 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2502 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2503 "!TARGET_POWERPC64 && reload_completed"
2504 [(const_int 0)]
2505 "
2506 {
2507 rtx dest = operands[0];
2508 rtx src = operands[1];
2509 rtx op2 = operands[2];
2510 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2511 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2512 rtx addr1;
2513 rtx addr2;
2514 rtx word1;
2515 rtx word2;
2516
2517 addr1 = XEXP (dest, 0);
2518 if (GET_CODE (addr1) == PLUS)
2519 {
2520 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2521 if (TARGET_AVOID_XFORM)
2522 {
2523 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2524 addr2 = op2;
2525 }
2526 else
2527 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2528 }
2529 else if (TARGET_AVOID_XFORM)
2530 {
2531 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2532 addr2 = op2;
2533 }
2534 else
2535 {
2536 emit_move_insn (op2, GEN_INT (4));
2537 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2538 }
2539
2540 word1 = change_address (dest, SImode, addr1);
2541 word2 = change_address (dest, SImode, addr2);
2542
2543 emit_insn (gen_bswapsi2 (word2, src1));
2544 emit_insn (gen_bswapsi2 (word1, src2));
2545 }")
2546
2547 (define_split
2548 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2549 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2550 (clobber (match_operand:SI 2 "" ""))]
2551 "!TARGET_POWERPC64 && reload_completed"
2552 [(const_int 0)]
2553 "
2554 {
2555 rtx dest = operands[0];
2556 rtx src = operands[1];
2557 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2558 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2559 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2560 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2561
2562 emit_insn (gen_bswapsi2 (dest1, src2));
2563 emit_insn (gen_bswapsi2 (dest2, src1));
2564 }")
2565
2566 (define_insn "mulsi3"
2567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2568 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2569 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2570 ""
2571 "@
2572 mullw %0,%1,%2
2573 mulli %0,%1,%2"
2574 [(set (attr "type")
2575 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2576 (const_string "imul3")
2577 (match_operand:SI 2 "short_cint_operand" "")
2578 (const_string "imul2")]
2579 (const_string "imul")))])
2580
2581 (define_insn "*mulsi3_internal1"
2582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2583 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2584 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2585 (const_int 0)))
2586 (clobber (match_scratch:SI 3 "=r,r"))]
2587 ""
2588 "@
2589 mullw. %3,%1,%2
2590 #"
2591 [(set_attr "type" "imul_compare")
2592 (set_attr "length" "4,8")])
2593
2594 (define_split
2595 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2596 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2597 (match_operand:SI 2 "gpc_reg_operand" ""))
2598 (const_int 0)))
2599 (clobber (match_scratch:SI 3 ""))]
2600 "reload_completed"
2601 [(set (match_dup 3)
2602 (mult:SI (match_dup 1) (match_dup 2)))
2603 (set (match_dup 0)
2604 (compare:CC (match_dup 3)
2605 (const_int 0)))]
2606 "")
2607
2608 (define_insn "*mulsi3_internal2"
2609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2610 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2611 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2612 (const_int 0)))
2613 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2614 (mult:SI (match_dup 1) (match_dup 2)))]
2615 ""
2616 "@
2617 mullw. %0,%1,%2
2618 #"
2619 [(set_attr "type" "imul_compare")
2620 (set_attr "length" "4,8")])
2621
2622 (define_split
2623 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2624 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2625 (match_operand:SI 2 "gpc_reg_operand" ""))
2626 (const_int 0)))
2627 (set (match_operand:SI 0 "gpc_reg_operand" "")
2628 (mult:SI (match_dup 1) (match_dup 2)))]
2629 "reload_completed"
2630 [(set (match_dup 0)
2631 (mult:SI (match_dup 1) (match_dup 2)))
2632 (set (match_dup 3)
2633 (compare:CC (match_dup 0)
2634 (const_int 0)))]
2635 "")
2636
2637
2638 (define_insn "udiv<mode>3"
2639 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2640 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2641 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2642 ""
2643 "div<wd>u %0,%1,%2"
2644 [(set (attr "type")
2645 (cond [(match_operand:SI 0 "" "")
2646 (const_string "idiv")]
2647 (const_string "ldiv")))])
2648
2649
2650 ;; For powers of two we can do srai/aze for divide and then adjust for
2651 ;; modulus. If it isn't a power of two, force operands into register and do
2652 ;; a normal divide.
2653 (define_expand "div<mode>3"
2654 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2655 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2656 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2657 ""
2658 {
2659 if (GET_CODE (operands[2]) != CONST_INT
2660 || INTVAL (operands[2]) <= 0
2661 || exact_log2 (INTVAL (operands[2])) < 0)
2662 operands[2] = force_reg (<MODE>mode, operands[2]);
2663 })
2664
2665 (define_insn "*div<mode>3"
2666 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2667 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2668 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2669 ""
2670 "div<wd> %0,%1,%2"
2671 [(set (attr "type")
2672 (cond [(match_operand:SI 0 "" "")
2673 (const_string "idiv")]
2674 (const_string "ldiv")))])
2675
2676 (define_expand "mod<mode>3"
2677 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2678 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2679 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2680 ""
2681 "
2682 {
2683 int i;
2684 rtx temp1;
2685 rtx temp2;
2686
2687 if (GET_CODE (operands[2]) != CONST_INT
2688 || INTVAL (operands[2]) <= 0
2689 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2690 FAIL;
2691
2692 temp1 = gen_reg_rtx (<MODE>mode);
2693 temp2 = gen_reg_rtx (<MODE>mode);
2694
2695 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2696 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2697 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2698 DONE;
2699 }")
2700
2701 (define_insn ""
2702 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2703 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2704 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2705 ""
2706 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2707 [(set_attr "type" "two")
2708 (set_attr "length" "8")])
2709
2710 (define_insn ""
2711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2712 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2713 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2714 (const_int 0)))
2715 (clobber (match_scratch:P 3 "=r,r"))]
2716 ""
2717 "@
2718 sra<wd>i %3,%1,%p2\;addze. %3,%3
2719 #"
2720 [(set_attr "type" "compare")
2721 (set_attr "length" "8,12")
2722 (set_attr "cell_micro" "not")])
2723
2724 (define_split
2725 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2726 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2727 (match_operand:GPR 2 "exact_log2_cint_operand"
2728 ""))
2729 (const_int 0)))
2730 (clobber (match_scratch:GPR 3 ""))]
2731 "reload_completed"
2732 [(set (match_dup 3)
2733 (div:<MODE> (match_dup 1) (match_dup 2)))
2734 (set (match_dup 0)
2735 (compare:CC (match_dup 3)
2736 (const_int 0)))]
2737 "")
2738
2739 (define_insn ""
2740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2741 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2742 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2743 (const_int 0)))
2744 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2745 (div:P (match_dup 1) (match_dup 2)))]
2746 ""
2747 "@
2748 sra<wd>i %0,%1,%p2\;addze. %0,%0
2749 #"
2750 [(set_attr "type" "compare")
2751 (set_attr "length" "8,12")
2752 (set_attr "cell_micro" "not")])
2753
2754 (define_split
2755 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2756 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2757 (match_operand:GPR 2 "exact_log2_cint_operand"
2758 ""))
2759 (const_int 0)))
2760 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2761 (div:GPR (match_dup 1) (match_dup 2)))]
2762 "reload_completed"
2763 [(set (match_dup 0)
2764 (div:<MODE> (match_dup 1) (match_dup 2)))
2765 (set (match_dup 3)
2766 (compare:CC (match_dup 0)
2767 (const_int 0)))]
2768 "")
2769 \f
2770 ;; Logical instructions
2771 ;; The logical instructions are mostly combined by using match_operator,
2772 ;; but the plain AND insns are somewhat different because there is no
2773 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2774 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2775
2776 (define_expand "andsi3"
2777 [(parallel
2778 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2779 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2780 (match_operand:SI 2 "and_operand" "")))
2781 (clobber (match_scratch:CC 3 ""))])]
2782 ""
2783 "")
2784
2785 (define_insn "andsi3_mc"
2786 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2787 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2788 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2789 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2790 "rs6000_gen_cell_microcode"
2791 "@
2792 and %0,%1,%2
2793 rlwinm %0,%1,0,%m2,%M2
2794 andi. %0,%1,%b2
2795 andis. %0,%1,%u2"
2796 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2797
2798 (define_insn "andsi3_nomc"
2799 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2800 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2801 (match_operand:SI 2 "and_operand" "?r,T")))
2802 (clobber (match_scratch:CC 3 "=X,X"))]
2803 "!rs6000_gen_cell_microcode"
2804 "@
2805 and %0,%1,%2
2806 rlwinm %0,%1,0,%m2,%M2")
2807
2808 (define_insn "andsi3_internal0_nomc"
2809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2810 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2811 (match_operand:SI 2 "and_operand" "?r,T")))]
2812 "!rs6000_gen_cell_microcode"
2813 "@
2814 and %0,%1,%2
2815 rlwinm %0,%1,0,%m2,%M2")
2816
2817
2818 ;; Note to set cr's other than cr0 we do the and immediate and then
2819 ;; the test again -- this avoids a mfcr which on the higher end
2820 ;; machines causes an execution serialization
2821
2822 (define_insn "*andsi3_internal2_mc"
2823 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2824 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2825 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2826 (const_int 0)))
2827 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2828 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2829 "TARGET_32BIT && rs6000_gen_cell_microcode"
2830 "@
2831 and. %3,%1,%2
2832 andi. %3,%1,%b2
2833 andis. %3,%1,%u2
2834 rlwinm. %3,%1,0,%m2,%M2
2835 #
2836 #
2837 #
2838 #"
2839 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2840 compare,compare,compare,compare")
2841 (set_attr "length" "4,4,4,4,8,8,8,8")])
2842
2843 (define_insn "*andsi3_internal3_mc"
2844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2845 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2846 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2847 (const_int 0)))
2848 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2849 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2850 "TARGET_64BIT && rs6000_gen_cell_microcode"
2851 "@
2852 #
2853 andi. %3,%1,%b2
2854 andis. %3,%1,%u2
2855 rlwinm. %3,%1,0,%m2,%M2
2856 #
2857 #
2858 #
2859 #"
2860 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2861 compare,compare,compare")
2862 (set_attr "length" "8,4,4,4,8,8,8,8")])
2863
2864 (define_split
2865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2866 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2867 (match_operand:GPR 2 "and_operand" ""))
2868 (const_int 0)))
2869 (clobber (match_scratch:GPR 3 ""))
2870 (clobber (match_scratch:CC 4 ""))]
2871 "reload_completed"
2872 [(parallel [(set (match_dup 3)
2873 (and:<MODE> (match_dup 1)
2874 (match_dup 2)))
2875 (clobber (match_dup 4))])
2876 (set (match_dup 0)
2877 (compare:CC (match_dup 3)
2878 (const_int 0)))]
2879 "")
2880
2881 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2882 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2883
2884 (define_split
2885 [(set (match_operand:CC 0 "cc_reg_operand" "")
2886 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2887 (match_operand:SI 2 "gpc_reg_operand" ""))
2888 (const_int 0)))
2889 (clobber (match_scratch:SI 3 ""))
2890 (clobber (match_scratch:CC 4 ""))]
2891 "TARGET_POWERPC64 && reload_completed"
2892 [(parallel [(set (match_dup 3)
2893 (and:SI (match_dup 1)
2894 (match_dup 2)))
2895 (clobber (match_dup 4))])
2896 (set (match_dup 0)
2897 (compare:CC (match_dup 3)
2898 (const_int 0)))]
2899 "")
2900
2901 (define_insn "*andsi3_internal4"
2902 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2903 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2904 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2905 (const_int 0)))
2906 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2907 (and:SI (match_dup 1)
2908 (match_dup 2)))
2909 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2910 "TARGET_32BIT && rs6000_gen_cell_microcode"
2911 "@
2912 and. %0,%1,%2
2913 andi. %0,%1,%b2
2914 andis. %0,%1,%u2
2915 rlwinm. %0,%1,0,%m2,%M2
2916 #
2917 #
2918 #
2919 #"
2920 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2921 compare,compare,compare,compare")
2922 (set_attr "length" "4,4,4,4,8,8,8,8")])
2923
2924 (define_insn "*andsi3_internal5_mc"
2925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2926 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2927 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2928 (const_int 0)))
2929 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2930 (and:SI (match_dup 1)
2931 (match_dup 2)))
2932 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2933 "TARGET_64BIT && rs6000_gen_cell_microcode"
2934 "@
2935 #
2936 andi. %0,%1,%b2
2937 andis. %0,%1,%u2
2938 rlwinm. %0,%1,0,%m2,%M2
2939 #
2940 #
2941 #
2942 #"
2943 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2944 compare,compare,compare")
2945 (set_attr "length" "8,4,4,4,8,8,8,8")])
2946
2947 (define_split
2948 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2949 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2950 (match_operand:SI 2 "and_operand" ""))
2951 (const_int 0)))
2952 (set (match_operand:SI 0 "gpc_reg_operand" "")
2953 (and:SI (match_dup 1)
2954 (match_dup 2)))
2955 (clobber (match_scratch:CC 4 ""))]
2956 "reload_completed"
2957 [(parallel [(set (match_dup 0)
2958 (and:SI (match_dup 1)
2959 (match_dup 2)))
2960 (clobber (match_dup 4))])
2961 (set (match_dup 3)
2962 (compare:CC (match_dup 0)
2963 (const_int 0)))]
2964 "")
2965
2966 (define_split
2967 [(set (match_operand:CC 3 "cc_reg_operand" "")
2968 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2969 (match_operand:SI 2 "gpc_reg_operand" ""))
2970 (const_int 0)))
2971 (set (match_operand:SI 0 "gpc_reg_operand" "")
2972 (and:SI (match_dup 1)
2973 (match_dup 2)))
2974 (clobber (match_scratch:CC 4 ""))]
2975 "TARGET_POWERPC64 && reload_completed"
2976 [(parallel [(set (match_dup 0)
2977 (and:SI (match_dup 1)
2978 (match_dup 2)))
2979 (clobber (match_dup 4))])
2980 (set (match_dup 3)
2981 (compare:CC (match_dup 0)
2982 (const_int 0)))]
2983 "")
2984
2985 ;; Handle the PowerPC64 rlwinm corner case
2986
2987 (define_insn_and_split "*andsi3_internal6"
2988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2989 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2990 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2991 "TARGET_POWERPC64"
2992 "#"
2993 "TARGET_POWERPC64"
2994 [(set (match_dup 0)
2995 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2996 (match_dup 4)))
2997 (set (match_dup 0)
2998 (rotate:SI (match_dup 0) (match_dup 5)))]
2999 "
3000 {
3001 int mb = extract_MB (operands[2]);
3002 int me = extract_ME (operands[2]);
3003 operands[3] = GEN_INT (me + 1);
3004 operands[5] = GEN_INT (32 - (me + 1));
3005 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3006 }"
3007 [(set_attr "length" "8")])
3008
3009 (define_expand "iorsi3"
3010 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3011 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3012 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3013 ""
3014 "
3015 {
3016 if (GET_CODE (operands[2]) == CONST_INT
3017 && ! logical_operand (operands[2], SImode))
3018 {
3019 HOST_WIDE_INT value = INTVAL (operands[2]);
3020 rtx tmp = ((!can_create_pseudo_p ()
3021 || rtx_equal_p (operands[0], operands[1]))
3022 ? operands[0] : gen_reg_rtx (SImode));
3023
3024 emit_insn (gen_iorsi3 (tmp, operands[1],
3025 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3026 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3027 DONE;
3028 }
3029 }")
3030
3031 (define_expand "xorsi3"
3032 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3033 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3034 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3035 ""
3036 "
3037 {
3038 if (GET_CODE (operands[2]) == CONST_INT
3039 && ! logical_operand (operands[2], SImode))
3040 {
3041 HOST_WIDE_INT value = INTVAL (operands[2]);
3042 rtx tmp = ((!can_create_pseudo_p ()
3043 || rtx_equal_p (operands[0], operands[1]))
3044 ? operands[0] : gen_reg_rtx (SImode));
3045
3046 emit_insn (gen_xorsi3 (tmp, operands[1],
3047 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3048 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3049 DONE;
3050 }
3051 }")
3052
3053 (define_insn "*boolsi3_internal1"
3054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3055 (match_operator:SI 3 "boolean_or_operator"
3056 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3057 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3058 ""
3059 "@
3060 %q3 %0,%1,%2
3061 %q3i %0,%1,%b2
3062 %q3is %0,%1,%u2")
3063
3064 (define_insn "*boolsi3_internal2"
3065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3066 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3067 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3068 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3069 (const_int 0)))
3070 (clobber (match_scratch:SI 3 "=r,r"))]
3071 "TARGET_32BIT"
3072 "@
3073 %q4. %3,%1,%2
3074 #"
3075 [(set_attr "type" "fast_compare,compare")
3076 (set_attr "length" "4,8")])
3077
3078 (define_split
3079 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(match_operand:SI 1 "gpc_reg_operand" "")
3082 (match_operand:SI 2 "gpc_reg_operand" "")])
3083 (const_int 0)))
3084 (clobber (match_scratch:SI 3 ""))]
3085 "TARGET_32BIT && reload_completed"
3086 [(set (match_dup 3) (match_dup 4))
3087 (set (match_dup 0)
3088 (compare:CC (match_dup 3)
3089 (const_int 0)))]
3090 "")
3091
3092 (define_insn "*boolsi3_internal3"
3093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3094 (compare:CC (match_operator:SI 4 "boolean_operator"
3095 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3096 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3097 (const_int 0)))
3098 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3099 (match_dup 4))]
3100 "TARGET_32BIT"
3101 "@
3102 %q4. %0,%1,%2
3103 #"
3104 [(set_attr "type" "fast_compare,compare")
3105 (set_attr "length" "4,8")])
3106
3107 (define_split
3108 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3109 (compare:CC (match_operator:SI 4 "boolean_operator"
3110 [(match_operand:SI 1 "gpc_reg_operand" "")
3111 (match_operand:SI 2 "gpc_reg_operand" "")])
3112 (const_int 0)))
3113 (set (match_operand:SI 0 "gpc_reg_operand" "")
3114 (match_dup 4))]
3115 "TARGET_32BIT && reload_completed"
3116 [(set (match_dup 0) (match_dup 4))
3117 (set (match_dup 3)
3118 (compare:CC (match_dup 0)
3119 (const_int 0)))]
3120 "")
3121
3122 ;; Split a logical operation that we can't do in one insn into two insns,
3123 ;; each of which does one 16-bit part. This is used by combine.
3124
3125 (define_split
3126 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3127 (match_operator:SI 3 "boolean_or_operator"
3128 [(match_operand:SI 1 "gpc_reg_operand" "")
3129 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3130 ""
3131 [(set (match_dup 0) (match_dup 4))
3132 (set (match_dup 0) (match_dup 5))]
3133 "
3134 {
3135 rtx i;
3136 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3137 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3138 operands[1], i);
3139 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3140 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3141 operands[0], i);
3142 }")
3143
3144 (define_insn "*boolcsi3_internal1"
3145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3146 (match_operator:SI 3 "boolean_operator"
3147 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3148 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3149 ""
3150 "%q3 %0,%2,%1")
3151
3152 (define_insn "*boolcsi3_internal2"
3153 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3154 (compare:CC (match_operator:SI 4 "boolean_operator"
3155 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3156 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3157 (const_int 0)))
3158 (clobber (match_scratch:SI 3 "=r,r"))]
3159 "TARGET_32BIT"
3160 "@
3161 %q4. %3,%2,%1
3162 #"
3163 [(set_attr "type" "compare")
3164 (set_attr "length" "4,8")])
3165
3166 (define_split
3167 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3168 (compare:CC (match_operator:SI 4 "boolean_operator"
3169 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3170 (match_operand:SI 2 "gpc_reg_operand" "")])
3171 (const_int 0)))
3172 (clobber (match_scratch:SI 3 ""))]
3173 "TARGET_32BIT && reload_completed"
3174 [(set (match_dup 3) (match_dup 4))
3175 (set (match_dup 0)
3176 (compare:CC (match_dup 3)
3177 (const_int 0)))]
3178 "")
3179
3180 (define_insn "*boolcsi3_internal3"
3181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3182 (compare:CC (match_operator:SI 4 "boolean_operator"
3183 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3184 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3185 (const_int 0)))
3186 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3187 (match_dup 4))]
3188 "TARGET_32BIT"
3189 "@
3190 %q4. %0,%2,%1
3191 #"
3192 [(set_attr "type" "compare")
3193 (set_attr "length" "4,8")])
3194
3195 (define_split
3196 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3197 (compare:CC (match_operator:SI 4 "boolean_operator"
3198 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3199 (match_operand:SI 2 "gpc_reg_operand" "")])
3200 (const_int 0)))
3201 (set (match_operand:SI 0 "gpc_reg_operand" "")
3202 (match_dup 4))]
3203 "TARGET_32BIT && reload_completed"
3204 [(set (match_dup 0) (match_dup 4))
3205 (set (match_dup 3)
3206 (compare:CC (match_dup 0)
3207 (const_int 0)))]
3208 "")
3209
3210 (define_insn "*boolccsi3_internal1"
3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3212 (match_operator:SI 3 "boolean_operator"
3213 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3214 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3215 ""
3216 "%q3 %0,%1,%2")
3217
3218 (define_insn "*boolccsi3_internal2"
3219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3220 (compare:CC (match_operator:SI 4 "boolean_operator"
3221 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3222 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3223 (const_int 0)))
3224 (clobber (match_scratch:SI 3 "=r,r"))]
3225 "TARGET_32BIT"
3226 "@
3227 %q4. %3,%1,%2
3228 #"
3229 [(set_attr "type" "fast_compare,compare")
3230 (set_attr "length" "4,8")])
3231
3232 (define_split
3233 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3234 (compare:CC (match_operator:SI 4 "boolean_operator"
3235 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3236 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3237 (const_int 0)))
3238 (clobber (match_scratch:SI 3 ""))]
3239 "TARGET_32BIT && reload_completed"
3240 [(set (match_dup 3) (match_dup 4))
3241 (set (match_dup 0)
3242 (compare:CC (match_dup 3)
3243 (const_int 0)))]
3244 "")
3245
3246 (define_insn "*boolccsi3_internal3"
3247 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3248 (compare:CC (match_operator:SI 4 "boolean_operator"
3249 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3250 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3251 (const_int 0)))
3252 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3253 (match_dup 4))]
3254 "TARGET_32BIT"
3255 "@
3256 %q4. %0,%1,%2
3257 #"
3258 [(set_attr "type" "fast_compare,compare")
3259 (set_attr "length" "4,8")])
3260
3261 (define_split
3262 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3263 (compare:CC (match_operator:SI 4 "boolean_operator"
3264 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3265 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3266 (const_int 0)))
3267 (set (match_operand:SI 0 "gpc_reg_operand" "")
3268 (match_dup 4))]
3269 "TARGET_32BIT && reload_completed"
3270 [(set (match_dup 0) (match_dup 4))
3271 (set (match_dup 3)
3272 (compare:CC (match_dup 0)
3273 (const_int 0)))]
3274 "")
3275 \f
3276 ;; Rotate and shift insns, in all their variants. These support shifts,
3277 ;; field inserts and extracts, and various combinations thereof.
3278 (define_expand "insv"
3279 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3280 (match_operand:SI 1 "const_int_operand" "")
3281 (match_operand:SI 2 "const_int_operand" ""))
3282 (match_operand 3 "gpc_reg_operand" ""))]
3283 ""
3284 "
3285 {
3286 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3287 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3288 compiler if the address of the structure is taken later. Likewise, do
3289 not handle invalid E500 subregs. */
3290 if (GET_CODE (operands[0]) == SUBREG
3291 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3292 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3293 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3294 FAIL;
3295
3296 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3297 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3298 operands[3]));
3299 else
3300 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3301 operands[3]));
3302 DONE;
3303 }")
3304
3305 (define_insn "insvsi_internal"
3306 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3307 (match_operand:SI 1 "const_int_operand" "i")
3308 (match_operand:SI 2 "const_int_operand" "i"))
3309 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3310 ""
3311 "*
3312 {
3313 int start = INTVAL (operands[2]) & 31;
3314 int size = INTVAL (operands[1]) & 31;
3315
3316 operands[4] = GEN_INT (32 - start - size);
3317 operands[1] = GEN_INT (start + size - 1);
3318 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3319 }"
3320 [(set_attr "type" "insert_word")])
3321
3322 (define_insn "*insvsi_internal1"
3323 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3324 (match_operand:SI 1 "const_int_operand" "i")
3325 (match_operand:SI 2 "const_int_operand" "i"))
3326 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3327 (match_operand:SI 4 "const_int_operand" "i")))]
3328 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3329 "*
3330 {
3331 int shift = INTVAL (operands[4]) & 31;
3332 int start = INTVAL (operands[2]) & 31;
3333 int size = INTVAL (operands[1]) & 31;
3334
3335 operands[4] = GEN_INT (shift - start - size);
3336 operands[1] = GEN_INT (start + size - 1);
3337 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3338 }"
3339 [(set_attr "type" "insert_word")])
3340
3341 (define_insn "*insvsi_internal2"
3342 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3343 (match_operand:SI 1 "const_int_operand" "i")
3344 (match_operand:SI 2 "const_int_operand" "i"))
3345 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3346 (match_operand:SI 4 "const_int_operand" "i")))]
3347 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3348 "*
3349 {
3350 int shift = INTVAL (operands[4]) & 31;
3351 int start = INTVAL (operands[2]) & 31;
3352 int size = INTVAL (operands[1]) & 31;
3353
3354 operands[4] = GEN_INT (32 - shift - start - size);
3355 operands[1] = GEN_INT (start + size - 1);
3356 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3357 }"
3358 [(set_attr "type" "insert_word")])
3359
3360 (define_insn "*insvsi_internal3"
3361 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3362 (match_operand:SI 1 "const_int_operand" "i")
3363 (match_operand:SI 2 "const_int_operand" "i"))
3364 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3365 (match_operand:SI 4 "const_int_operand" "i")))]
3366 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3367 "*
3368 {
3369 int shift = INTVAL (operands[4]) & 31;
3370 int start = INTVAL (operands[2]) & 31;
3371 int size = INTVAL (operands[1]) & 31;
3372
3373 operands[4] = GEN_INT (32 - shift - start - size);
3374 operands[1] = GEN_INT (start + size - 1);
3375 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3376 }"
3377 [(set_attr "type" "insert_word")])
3378
3379 (define_insn "*insvsi_internal4"
3380 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3381 (match_operand:SI 1 "const_int_operand" "i")
3382 (match_operand:SI 2 "const_int_operand" "i"))
3383 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3384 (match_operand:SI 4 "const_int_operand" "i")
3385 (match_operand:SI 5 "const_int_operand" "i")))]
3386 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3387 "*
3388 {
3389 int extract_start = INTVAL (operands[5]) & 31;
3390 int extract_size = INTVAL (operands[4]) & 31;
3391 int insert_start = INTVAL (operands[2]) & 31;
3392 int insert_size = INTVAL (operands[1]) & 31;
3393
3394 /* Align extract field with insert field */
3395 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3396 operands[1] = GEN_INT (insert_start + insert_size - 1);
3397 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3398 }"
3399 [(set_attr "type" "insert_word")])
3400
3401 ;; combine patterns for rlwimi
3402 (define_insn "*insvsi_internal5"
3403 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3404 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3405 (match_operand:SI 1 "mask_operand" "i"))
3406 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3407 (match_operand:SI 2 "const_int_operand" "i"))
3408 (match_operand:SI 5 "mask_operand" "i"))))]
3409 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3410 "*
3411 {
3412 int me = extract_ME(operands[5]);
3413 int mb = extract_MB(operands[5]);
3414 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3415 operands[2] = GEN_INT(mb);
3416 operands[1] = GEN_INT(me);
3417 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3418 }"
3419 [(set_attr "type" "insert_word")])
3420
3421 (define_insn "*insvsi_internal6"
3422 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3423 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3424 (match_operand:SI 2 "const_int_operand" "i"))
3425 (match_operand:SI 5 "mask_operand" "i"))
3426 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3427 (match_operand:SI 1 "mask_operand" "i"))))]
3428 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3429 "*
3430 {
3431 int me = extract_ME(operands[5]);
3432 int mb = extract_MB(operands[5]);
3433 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3434 operands[2] = GEN_INT(mb);
3435 operands[1] = GEN_INT(me);
3436 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3437 }"
3438 [(set_attr "type" "insert_word")])
3439
3440 (define_insn "insvdi_internal"
3441 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3442 (match_operand:SI 1 "const_int_operand" "i")
3443 (match_operand:SI 2 "const_int_operand" "i"))
3444 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3445 "TARGET_POWERPC64"
3446 "*
3447 {
3448 int start = INTVAL (operands[2]) & 63;
3449 int size = INTVAL (operands[1]) & 63;
3450
3451 operands[1] = GEN_INT (64 - start - size);
3452 return \"rldimi %0,%3,%H1,%H2\";
3453 }"
3454 [(set_attr "type" "insert_dword")])
3455
3456 (define_insn "*insvdi_internal2"
3457 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3458 (match_operand:SI 1 "const_int_operand" "i")
3459 (match_operand:SI 2 "const_int_operand" "i"))
3460 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3461 (match_operand:SI 4 "const_int_operand" "i")))]
3462 "TARGET_POWERPC64
3463 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3464 "*
3465 {
3466 int shift = INTVAL (operands[4]) & 63;
3467 int start = (INTVAL (operands[2]) & 63) - 32;
3468 int size = INTVAL (operands[1]) & 63;
3469
3470 operands[4] = GEN_INT (64 - shift - start - size);
3471 operands[2] = GEN_INT (start);
3472 operands[1] = GEN_INT (start + size - 1);
3473 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3474 }")
3475
3476 (define_insn "*insvdi_internal3"
3477 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3478 (match_operand:SI 1 "const_int_operand" "i")
3479 (match_operand:SI 2 "const_int_operand" "i"))
3480 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3481 (match_operand:SI 4 "const_int_operand" "i")))]
3482 "TARGET_POWERPC64
3483 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3484 "*
3485 {
3486 int shift = INTVAL (operands[4]) & 63;
3487 int start = (INTVAL (operands[2]) & 63) - 32;
3488 int size = INTVAL (operands[1]) & 63;
3489
3490 operands[4] = GEN_INT (64 - shift - start - size);
3491 operands[2] = GEN_INT (start);
3492 operands[1] = GEN_INT (start + size - 1);
3493 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3494 }")
3495
3496 (define_expand "extzv"
3497 [(set (match_operand 0 "gpc_reg_operand" "")
3498 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3499 (match_operand:SI 2 "const_int_operand" "")
3500 (match_operand:SI 3 "const_int_operand" "")))]
3501 ""
3502 "
3503 {
3504 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3505 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3506 compiler if the address of the structure is taken later. */
3507 if (GET_CODE (operands[0]) == SUBREG
3508 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3509 FAIL;
3510
3511 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3512 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3513 operands[3]));
3514 else
3515 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3516 operands[3]));
3517 DONE;
3518 }")
3519
3520 (define_insn "extzvsi_internal"
3521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3522 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3523 (match_operand:SI 2 "const_int_operand" "i")
3524 (match_operand:SI 3 "const_int_operand" "i")))]
3525 ""
3526 "*
3527 {
3528 int start = INTVAL (operands[3]) & 31;
3529 int size = INTVAL (operands[2]) & 31;
3530
3531 if (start + size >= 32)
3532 operands[3] = const0_rtx;
3533 else
3534 operands[3] = GEN_INT (start + size);
3535 return \"rlwinm %0,%1,%3,%s2,31\";
3536 }")
3537
3538 (define_insn "*extzvsi_internal1"
3539 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3540 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3541 (match_operand:SI 2 "const_int_operand" "i,i")
3542 (match_operand:SI 3 "const_int_operand" "i,i"))
3543 (const_int 0)))
3544 (clobber (match_scratch:SI 4 "=r,r"))]
3545 ""
3546 "*
3547 {
3548 int start = INTVAL (operands[3]) & 31;
3549 int size = INTVAL (operands[2]) & 31;
3550
3551 /* Force split for non-cc0 compare. */
3552 if (which_alternative == 1)
3553 return \"#\";
3554
3555 /* If the bit-field being tested fits in the upper or lower half of a
3556 word, it is possible to use andiu. or andil. to test it. This is
3557 useful because the condition register set-use delay is smaller for
3558 andi[ul]. than for rlinm. This doesn't work when the starting bit
3559 position is 0 because the LT and GT bits may be set wrong. */
3560
3561 if ((start > 0 && start + size <= 16) || start >= 16)
3562 {
3563 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3564 - (1 << (16 - (start & 15) - size))));
3565 if (start < 16)
3566 return \"andis. %4,%1,%3\";
3567 else
3568 return \"andi. %4,%1,%3\";
3569 }
3570
3571 if (start + size >= 32)
3572 operands[3] = const0_rtx;
3573 else
3574 operands[3] = GEN_INT (start + size);
3575 return \"rlwinm. %4,%1,%3,%s2,31\";
3576 }"
3577 [(set_attr "type" "delayed_compare")
3578 (set_attr "length" "4,8")])
3579
3580 (define_split
3581 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3582 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3583 (match_operand:SI 2 "const_int_operand" "")
3584 (match_operand:SI 3 "const_int_operand" ""))
3585 (const_int 0)))
3586 (clobber (match_scratch:SI 4 ""))]
3587 "reload_completed"
3588 [(set (match_dup 4)
3589 (zero_extract:SI (match_dup 1) (match_dup 2)
3590 (match_dup 3)))
3591 (set (match_dup 0)
3592 (compare:CC (match_dup 4)
3593 (const_int 0)))]
3594 "")
3595
3596 (define_insn "*extzvsi_internal2"
3597 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3598 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3599 (match_operand:SI 2 "const_int_operand" "i,i")
3600 (match_operand:SI 3 "const_int_operand" "i,i"))
3601 (const_int 0)))
3602 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3603 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3604 ""
3605 "*
3606 {
3607 int start = INTVAL (operands[3]) & 31;
3608 int size = INTVAL (operands[2]) & 31;
3609
3610 /* Force split for non-cc0 compare. */
3611 if (which_alternative == 1)
3612 return \"#\";
3613
3614 /* Since we are using the output value, we can't ignore any need for
3615 a shift. The bit-field must end at the LSB. */
3616 if (start >= 16 && start + size == 32)
3617 {
3618 operands[3] = GEN_INT ((1 << size) - 1);
3619 return \"andi. %0,%1,%3\";
3620 }
3621
3622 if (start + size >= 32)
3623 operands[3] = const0_rtx;
3624 else
3625 operands[3] = GEN_INT (start + size);
3626 return \"rlwinm. %0,%1,%3,%s2,31\";
3627 }"
3628 [(set_attr "type" "delayed_compare")
3629 (set_attr "length" "4,8")])
3630
3631 (define_split
3632 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3633 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3634 (match_operand:SI 2 "const_int_operand" "")
3635 (match_operand:SI 3 "const_int_operand" ""))
3636 (const_int 0)))
3637 (set (match_operand:SI 0 "gpc_reg_operand" "")
3638 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3639 "reload_completed"
3640 [(set (match_dup 0)
3641 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3642 (set (match_dup 4)
3643 (compare:CC (match_dup 0)
3644 (const_int 0)))]
3645 "")
3646
3647 (define_insn "extzvdi_internal"
3648 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3649 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3650 (match_operand:SI 2 "const_int_operand" "i")
3651 (match_operand:SI 3 "const_int_operand" "i")))]
3652 "TARGET_POWERPC64"
3653 "*
3654 {
3655 int start = INTVAL (operands[3]) & 63;
3656 int size = INTVAL (operands[2]) & 63;
3657
3658 if (start + size >= 64)
3659 operands[3] = const0_rtx;
3660 else
3661 operands[3] = GEN_INT (start + size);
3662 operands[2] = GEN_INT (64 - size);
3663 return \"rldicl %0,%1,%3,%2\";
3664 }")
3665
3666 (define_insn "*extzvdi_internal1"
3667 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3668 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3669 (match_operand:SI 2 "const_int_operand" "i")
3670 (match_operand:SI 3 "const_int_operand" "i"))
3671 (const_int 0)))
3672 (clobber (match_scratch:DI 4 "=r"))]
3673 "TARGET_64BIT && rs6000_gen_cell_microcode"
3674 "*
3675 {
3676 int start = INTVAL (operands[3]) & 63;
3677 int size = INTVAL (operands[2]) & 63;
3678
3679 if (start + size >= 64)
3680 operands[3] = const0_rtx;
3681 else
3682 operands[3] = GEN_INT (start + size);
3683 operands[2] = GEN_INT (64 - size);
3684 return \"rldicl. %4,%1,%3,%2\";
3685 }"
3686 [(set_attr "type" "compare")])
3687
3688 (define_insn "*extzvdi_internal2"
3689 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3690 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3691 (match_operand:SI 2 "const_int_operand" "i")
3692 (match_operand:SI 3 "const_int_operand" "i"))
3693 (const_int 0)))
3694 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3695 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3696 "TARGET_64BIT && rs6000_gen_cell_microcode"
3697 "*
3698 {
3699 int start = INTVAL (operands[3]) & 63;
3700 int size = INTVAL (operands[2]) & 63;
3701
3702 if (start + size >= 64)
3703 operands[3] = const0_rtx;
3704 else
3705 operands[3] = GEN_INT (start + size);
3706 operands[2] = GEN_INT (64 - size);
3707 return \"rldicl. %0,%1,%3,%2\";
3708 }"
3709 [(set_attr "type" "compare")])
3710
3711 (define_insn "rotlsi3"
3712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3713 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3714 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3715 ""
3716 "@
3717 rlwnm %0,%1,%2,0xffffffff
3718 rlwinm %0,%1,%h2,0xffffffff"
3719 [(set_attr "type" "var_shift_rotate,integer")])
3720
3721 (define_insn "*rotlsi3_64"
3722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3723 (zero_extend:DI
3724 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3725 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3726 "TARGET_64BIT"
3727 "@
3728 rlwnm %0,%1,%2,0xffffffff
3729 rlwinm %0,%1,%h2,0xffffffff"
3730 [(set_attr "type" "var_shift_rotate,integer")])
3731
3732 (define_insn "*rotlsi3_internal2"
3733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3734 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3735 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3736 (const_int 0)))
3737 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3738 ""
3739 "@
3740 rlwnm. %3,%1,%2,0xffffffff
3741 rlwinm. %3,%1,%h2,0xffffffff
3742 #
3743 #"
3744 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3745 (set_attr "length" "4,4,8,8")])
3746
3747 (define_split
3748 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3749 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3750 (match_operand:SI 2 "reg_or_cint_operand" ""))
3751 (const_int 0)))
3752 (clobber (match_scratch:SI 3 ""))]
3753 "reload_completed"
3754 [(set (match_dup 3)
3755 (rotate:SI (match_dup 1) (match_dup 2)))
3756 (set (match_dup 0)
3757 (compare:CC (match_dup 3)
3758 (const_int 0)))]
3759 "")
3760
3761 (define_insn "*rotlsi3_internal3"
3762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3763 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3764 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3765 (const_int 0)))
3766 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3767 (rotate:SI (match_dup 1) (match_dup 2)))]
3768 ""
3769 "@
3770 rlwnm. %0,%1,%2,0xffffffff
3771 rlwinm. %0,%1,%h2,0xffffffff
3772 #
3773 #"
3774 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3775 (set_attr "length" "4,4,8,8")])
3776
3777 (define_split
3778 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3779 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3780 (match_operand:SI 2 "reg_or_cint_operand" ""))
3781 (const_int 0)))
3782 (set (match_operand:SI 0 "gpc_reg_operand" "")
3783 (rotate:SI (match_dup 1) (match_dup 2)))]
3784 "reload_completed"
3785 [(set (match_dup 0)
3786 (rotate:SI (match_dup 1) (match_dup 2)))
3787 (set (match_dup 3)
3788 (compare:CC (match_dup 0)
3789 (const_int 0)))]
3790 "")
3791
3792 (define_insn "*rotlsi3_internal4"
3793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3794 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3795 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3796 (match_operand:SI 3 "mask_operand" "n,n")))]
3797 ""
3798 "@
3799 rlwnm %0,%1,%2,%m3,%M3
3800 rlwinm %0,%1,%h2,%m3,%M3"
3801 [(set_attr "type" "var_shift_rotate,integer")])
3802
3803 (define_insn "*rotlsi3_internal5"
3804 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3805 (compare:CC (and:SI
3806 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3807 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3808 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3809 (const_int 0)))
3810 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3811 ""
3812 "@
3813 rlwnm. %4,%1,%2,%m3,%M3
3814 rlwinm. %4,%1,%h2,%m3,%M3
3815 #
3816 #"
3817 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3818 (set_attr "length" "4,4,8,8")])
3819
3820 (define_split
3821 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3822 (compare:CC (and:SI
3823 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3824 (match_operand:SI 2 "reg_or_cint_operand" ""))
3825 (match_operand:SI 3 "mask_operand" ""))
3826 (const_int 0)))
3827 (clobber (match_scratch:SI 4 ""))]
3828 "reload_completed"
3829 [(set (match_dup 4)
3830 (and:SI (rotate:SI (match_dup 1)
3831 (match_dup 2))
3832 (match_dup 3)))
3833 (set (match_dup 0)
3834 (compare:CC (match_dup 4)
3835 (const_int 0)))]
3836 "")
3837
3838 (define_insn "*rotlsi3_internal6"
3839 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3840 (compare:CC (and:SI
3841 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3842 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3843 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3844 (const_int 0)))
3845 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3846 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3847 ""
3848 "@
3849 rlwnm. %0,%1,%2,%m3,%M3
3850 rlwinm. %0,%1,%h2,%m3,%M3
3851 #
3852 #"
3853 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3854 (set_attr "length" "4,4,8,8")])
3855
3856 (define_split
3857 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3858 (compare:CC (and:SI
3859 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3860 (match_operand:SI 2 "reg_or_cint_operand" ""))
3861 (match_operand:SI 3 "mask_operand" ""))
3862 (const_int 0)))
3863 (set (match_operand:SI 0 "gpc_reg_operand" "")
3864 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3865 "reload_completed"
3866 [(set (match_dup 0)
3867 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3868 (set (match_dup 4)
3869 (compare:CC (match_dup 0)
3870 (const_int 0)))]
3871 "")
3872
3873 (define_insn "*rotlsi3_internal7le"
3874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3875 (zero_extend:SI
3876 (subreg:QI
3877 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3878 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3879 "!BYTES_BIG_ENDIAN"
3880 "rlw%I2nm %0,%1,%h2,0xff"
3881 [(set (attr "cell_micro")
3882 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3883 (const_string "not")
3884 (const_string "always")))])
3885
3886 (define_insn "*rotlsi3_internal7be"
3887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3888 (zero_extend:SI
3889 (subreg:QI
3890 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3891 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3892 "BYTES_BIG_ENDIAN"
3893 "rlw%I2nm %0,%1,%h2,0xff"
3894 [(set (attr "cell_micro")
3895 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3896 (const_string "not")
3897 (const_string "always")))])
3898
3899 (define_insn "*rotlsi3_internal8le"
3900 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3901 (compare:CC (zero_extend:SI
3902 (subreg:QI
3903 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3904 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3905 (const_int 0)))
3906 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3907 "!BYTES_BIG_ENDIAN"
3908 "@
3909 rlwnm. %3,%1,%2,0xff
3910 rlwinm. %3,%1,%h2,0xff
3911 #
3912 #"
3913 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3914 (set_attr "length" "4,4,8,8")])
3915
3916 (define_insn "*rotlsi3_internal8be"
3917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3918 (compare:CC (zero_extend:SI
3919 (subreg:QI
3920 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3921 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
3922 (const_int 0)))
3923 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3924 "BYTES_BIG_ENDIAN"
3925 "@
3926 rlwnm. %3,%1,%2,0xff
3927 rlwinm. %3,%1,%h2,0xff
3928 #
3929 #"
3930 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3931 (set_attr "length" "4,4,8,8")])
3932
3933 (define_split
3934 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3935 (compare:CC (zero_extend:SI
3936 (subreg:QI
3937 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3938 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3939 (const_int 0)))
3940 (clobber (match_scratch:SI 3 ""))]
3941 "!BYTES_BIG_ENDIAN && reload_completed"
3942 [(set (match_dup 3)
3943 (zero_extend:SI (subreg:QI
3944 (rotate:SI (match_dup 1)
3945 (match_dup 2)) 0)))
3946 (set (match_dup 0)
3947 (compare:CC (match_dup 3)
3948 (const_int 0)))]
3949 "")
3950
3951 (define_split
3952 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3953 (compare:CC (zero_extend:SI
3954 (subreg:QI
3955 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3956 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3957 (const_int 0)))
3958 (clobber (match_scratch:SI 3 ""))]
3959 "BYTES_BIG_ENDIAN && reload_completed"
3960 [(set (match_dup 3)
3961 (zero_extend:SI (subreg:QI
3962 (rotate:SI (match_dup 1)
3963 (match_dup 2)) 3)))
3964 (set (match_dup 0)
3965 (compare:CC (match_dup 3)
3966 (const_int 0)))]
3967 "")
3968
3969 (define_insn "*rotlsi3_internal9le"
3970 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3971 (compare:CC (zero_extend:SI
3972 (subreg:QI
3973 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3974 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3975 (const_int 0)))
3976 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3977 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3978 "!BYTES_BIG_ENDIAN"
3979 "@
3980 rlwnm. %0,%1,%2,0xff
3981 rlwinm. %0,%1,%h2,0xff
3982 #
3983 #"
3984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3985 (set_attr "length" "4,4,8,8")])
3986
3987 (define_insn "*rotlsi3_internal9be"
3988 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3989 (compare:CC (zero_extend:SI
3990 (subreg:QI
3991 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3992 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
3993 (const_int 0)))
3994 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3995 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3996 "BYTES_BIG_ENDIAN"
3997 "@
3998 rlwnm. %0,%1,%2,0xff
3999 rlwinm. %0,%1,%h2,0xff
4000 #
4001 #"
4002 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4003 (set_attr "length" "4,4,8,8")])
4004
4005 (define_split
4006 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4007 (compare:CC (zero_extend:SI
4008 (subreg:QI
4009 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4010 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4011 (const_int 0)))
4012 (set (match_operand:SI 0 "gpc_reg_operand" "")
4013 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4014 "!BYTES_BIG_ENDIAN && reload_completed"
4015 [(set (match_dup 0)
4016 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4017 (set (match_dup 3)
4018 (compare:CC (match_dup 0)
4019 (const_int 0)))]
4020 "")
4021
4022 (define_split
4023 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4024 (compare:CC (zero_extend:SI
4025 (subreg:QI
4026 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4027 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4028 (const_int 0)))
4029 (set (match_operand:SI 0 "gpc_reg_operand" "")
4030 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4031 "BYTES_BIG_ENDIAN && reload_completed"
4032 [(set (match_dup 0)
4033 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4034 (set (match_dup 3)
4035 (compare:CC (match_dup 0)
4036 (const_int 0)))]
4037 "")
4038
4039 (define_insn "*rotlsi3_internal10le"
4040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4041 (zero_extend:SI
4042 (subreg:HI
4043 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4044 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4045 "!BYTES_BIG_ENDIAN"
4046 "@
4047 rlwnm %0,%1,%2,0xffff
4048 rlwinm %0,%1,%h2,0xffff"
4049 [(set_attr "type" "var_shift_rotate,integer")])
4050
4051 (define_insn "*rotlsi3_internal10be"
4052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4053 (zero_extend:SI
4054 (subreg:HI
4055 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4056 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
4057 "BYTES_BIG_ENDIAN"
4058 "@
4059 rlwnm %0,%1,%2,0xffff
4060 rlwinm %0,%1,%h2,0xffff"
4061 [(set_attr "type" "var_shift_rotate,integer")])
4062
4063 (define_insn "*rotlsi3_internal11le"
4064 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4065 (compare:CC (zero_extend:SI
4066 (subreg:HI
4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4069 (const_int 0)))
4070 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4071 "!BYTES_BIG_ENDIAN"
4072 "@
4073 rlwnm. %3,%1,%2,0xffff
4074 rlwinm. %3,%1,%h2,0xffff
4075 #
4076 #"
4077 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4078 (set_attr "length" "4,4,8,8")])
4079
4080 (define_insn "*rotlsi3_internal11be"
4081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4082 (compare:CC (zero_extend:SI
4083 (subreg:HI
4084 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4085 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4086 (const_int 0)))
4087 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4088 "BYTES_BIG_ENDIAN"
4089 "@
4090 rlwnm. %3,%1,%2,0xffff
4091 rlwinm. %3,%1,%h2,0xffff
4092 #
4093 #"
4094 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4095 (set_attr "length" "4,4,8,8")])
4096
4097 (define_split
4098 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4099 (compare:CC (zero_extend:SI
4100 (subreg:HI
4101 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4102 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4103 (const_int 0)))
4104 (clobber (match_scratch:SI 3 ""))]
4105 "!BYTES_BIG_ENDIAN && reload_completed"
4106 [(set (match_dup 3)
4107 (zero_extend:SI (subreg:HI
4108 (rotate:SI (match_dup 1)
4109 (match_dup 2)) 0)))
4110 (set (match_dup 0)
4111 (compare:CC (match_dup 3)
4112 (const_int 0)))]
4113 "")
4114
4115 (define_split
4116 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4117 (compare:CC (zero_extend:SI
4118 (subreg:HI
4119 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4120 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4121 (const_int 0)))
4122 (clobber (match_scratch:SI 3 ""))]
4123 "BYTES_BIG_ENDIAN && reload_completed"
4124 [(set (match_dup 3)
4125 (zero_extend:SI (subreg:HI
4126 (rotate:SI (match_dup 1)
4127 (match_dup 2)) 2)))
4128 (set (match_dup 0)
4129 (compare:CC (match_dup 3)
4130 (const_int 0)))]
4131 "")
4132
4133 (define_insn "*rotlsi3_internal12le"
4134 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4135 (compare:CC (zero_extend:SI
4136 (subreg:HI
4137 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4138 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4139 (const_int 0)))
4140 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4141 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4142 "!BYTES_BIG_ENDIAN"
4143 "@
4144 rlwnm. %0,%1,%2,0xffff
4145 rlwinm. %0,%1,%h2,0xffff
4146 #
4147 #"
4148 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4149 (set_attr "length" "4,4,8,8")])
4150
4151 (define_insn "*rotlsi3_internal12be"
4152 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4153 (compare:CC (zero_extend:SI
4154 (subreg:HI
4155 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4156 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4157 (const_int 0)))
4158 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4159 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4160 "BYTES_BIG_ENDIAN"
4161 "@
4162 rlwnm. %0,%1,%2,0xffff
4163 rlwinm. %0,%1,%h2,0xffff
4164 #
4165 #"
4166 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4167 (set_attr "length" "4,4,8,8")])
4168
4169 (define_split
4170 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4171 (compare:CC (zero_extend:SI
4172 (subreg:HI
4173 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4174 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4175 (const_int 0)))
4176 (set (match_operand:SI 0 "gpc_reg_operand" "")
4177 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4178 "!BYTES_BIG_ENDIAN && reload_completed"
4179 [(set (match_dup 0)
4180 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4181 (set (match_dup 3)
4182 (compare:CC (match_dup 0)
4183 (const_int 0)))]
4184 "")
4185
4186 (define_split
4187 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4188 (compare:CC (zero_extend:SI
4189 (subreg:HI
4190 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4191 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4192 (const_int 0)))
4193 (set (match_operand:SI 0 "gpc_reg_operand" "")
4194 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4195 "BYTES_BIG_ENDIAN && reload_completed"
4196 [(set (match_dup 0)
4197 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4198 (set (match_dup 3)
4199 (compare:CC (match_dup 0)
4200 (const_int 0)))]
4201 "")
4202
4203 (define_insn "ashlsi3"
4204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4205 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4206 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4207 ""
4208 "@
4209 slw %0,%1,%2
4210 slwi %0,%1,%h2"
4211 [(set_attr "type" "var_shift_rotate,shift")])
4212
4213 (define_insn "*ashlsi3_64"
4214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4215 (zero_extend:DI
4216 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4217 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4218 "TARGET_POWERPC64"
4219 "@
4220 slw %0,%1,%2
4221 slwi %0,%1,%h2"
4222 [(set_attr "type" "var_shift_rotate,shift")])
4223
4224 (define_insn ""
4225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4226 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4227 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4228 (const_int 0)))
4229 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4230 "TARGET_32BIT"
4231 "@
4232 slw. %3,%1,%2
4233 slwi. %3,%1,%h2
4234 #
4235 #"
4236 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4237 (set_attr "length" "4,4,8,8")])
4238
4239 (define_split
4240 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4241 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4242 (match_operand:SI 2 "reg_or_cint_operand" ""))
4243 (const_int 0)))
4244 (clobber (match_scratch:SI 3 ""))]
4245 "TARGET_32BIT && reload_completed"
4246 [(set (match_dup 3)
4247 (ashift:SI (match_dup 1) (match_dup 2)))
4248 (set (match_dup 0)
4249 (compare:CC (match_dup 3)
4250 (const_int 0)))]
4251 "")
4252
4253 (define_insn ""
4254 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4255 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4256 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4257 (const_int 0)))
4258 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4259 (ashift:SI (match_dup 1) (match_dup 2)))]
4260 "TARGET_32BIT"
4261 "@
4262 slw. %0,%1,%2
4263 slwi. %0,%1,%h2
4264 #
4265 #"
4266 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4267 (set_attr "length" "4,4,8,8")])
4268
4269 (define_split
4270 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4271 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4272 (match_operand:SI 2 "reg_or_cint_operand" ""))
4273 (const_int 0)))
4274 (set (match_operand:SI 0 "gpc_reg_operand" "")
4275 (ashift:SI (match_dup 1) (match_dup 2)))]
4276 "TARGET_32BIT && reload_completed"
4277 [(set (match_dup 0)
4278 (ashift:SI (match_dup 1) (match_dup 2)))
4279 (set (match_dup 3)
4280 (compare:CC (match_dup 0)
4281 (const_int 0)))]
4282 "")
4283
4284 (define_insn "rlwinm"
4285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4286 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4287 (match_operand:SI 2 "const_int_operand" "i"))
4288 (match_operand:SI 3 "mask_operand" "n")))]
4289 "includes_lshift_p (operands[2], operands[3])"
4290 "rlwinm %0,%1,%h2,%m3,%M3")
4291
4292 (define_insn ""
4293 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4294 (compare:CC
4295 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4296 (match_operand:SI 2 "const_int_operand" "i,i"))
4297 (match_operand:SI 3 "mask_operand" "n,n"))
4298 (const_int 0)))
4299 (clobber (match_scratch:SI 4 "=r,r"))]
4300 "includes_lshift_p (operands[2], operands[3])"
4301 "@
4302 rlwinm. %4,%1,%h2,%m3,%M3
4303 #"
4304 [(set_attr "type" "delayed_compare")
4305 (set_attr "length" "4,8")])
4306
4307 (define_split
4308 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4309 (compare:CC
4310 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4311 (match_operand:SI 2 "const_int_operand" ""))
4312 (match_operand:SI 3 "mask_operand" ""))
4313 (const_int 0)))
4314 (clobber (match_scratch:SI 4 ""))]
4315 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4316 [(set (match_dup 4)
4317 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4318 (match_dup 3)))
4319 (set (match_dup 0)
4320 (compare:CC (match_dup 4)
4321 (const_int 0)))]
4322 "")
4323
4324 (define_insn ""
4325 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4326 (compare:CC
4327 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4328 (match_operand:SI 2 "const_int_operand" "i,i"))
4329 (match_operand:SI 3 "mask_operand" "n,n"))
4330 (const_int 0)))
4331 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4332 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4333 "includes_lshift_p (operands[2], operands[3])"
4334 "@
4335 rlwinm. %0,%1,%h2,%m3,%M3
4336 #"
4337 [(set_attr "type" "delayed_compare")
4338 (set_attr "length" "4,8")])
4339
4340 (define_split
4341 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4342 (compare:CC
4343 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4344 (match_operand:SI 2 "const_int_operand" ""))
4345 (match_operand:SI 3 "mask_operand" ""))
4346 (const_int 0)))
4347 (set (match_operand:SI 0 "gpc_reg_operand" "")
4348 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4349 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4350 [(set (match_dup 0)
4351 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4352 (set (match_dup 4)
4353 (compare:CC (match_dup 0)
4354 (const_int 0)))]
4355 "")
4356
4357 (define_insn "lshrsi3"
4358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4359 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4360 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4361 ""
4362 "@
4363 mr %0,%1
4364 srw %0,%1,%2
4365 srwi %0,%1,%h2"
4366 [(set_attr "type" "integer,var_shift_rotate,shift")])
4367
4368 (define_insn "*lshrsi3_64"
4369 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4370 (zero_extend:DI
4371 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4372 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4373 "TARGET_POWERPC64"
4374 "@
4375 srw %0,%1,%2
4376 srwi %0,%1,%h2"
4377 [(set_attr "type" "var_shift_rotate,shift")])
4378
4379 (define_insn ""
4380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4381 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4382 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4383 (const_int 0)))
4384 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4385 "TARGET_32BIT"
4386 "@
4387 mr. %1,%1
4388 srw. %3,%1,%2
4389 srwi. %3,%1,%h2
4390 #
4391 #
4392 #"
4393 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4394 (set_attr "length" "4,4,4,8,8,8")])
4395
4396 (define_split
4397 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4398 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4399 (match_operand:SI 2 "reg_or_cint_operand" ""))
4400 (const_int 0)))
4401 (clobber (match_scratch:SI 3 ""))]
4402 "TARGET_32BIT && reload_completed"
4403 [(set (match_dup 3)
4404 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4405 (set (match_dup 0)
4406 (compare:CC (match_dup 3)
4407 (const_int 0)))]
4408 "")
4409
4410 (define_insn ""
4411 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4412 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4413 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4414 (const_int 0)))
4415 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4416 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4417 "TARGET_32BIT"
4418 "@
4419 mr. %0,%1
4420 srw. %0,%1,%2
4421 srwi. %0,%1,%h2
4422 #
4423 #
4424 #"
4425 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4426 (set_attr "length" "4,4,4,8,8,8")])
4427
4428 (define_split
4429 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4430 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4431 (match_operand:SI 2 "reg_or_cint_operand" ""))
4432 (const_int 0)))
4433 (set (match_operand:SI 0 "gpc_reg_operand" "")
4434 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4435 "TARGET_32BIT && reload_completed"
4436 [(set (match_dup 0)
4437 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4438 (set (match_dup 3)
4439 (compare:CC (match_dup 0)
4440 (const_int 0)))]
4441 "")
4442
4443 (define_insn ""
4444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4445 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4446 (match_operand:SI 2 "const_int_operand" "i"))
4447 (match_operand:SI 3 "mask_operand" "n")))]
4448 "includes_rshift_p (operands[2], operands[3])"
4449 "rlwinm %0,%1,%s2,%m3,%M3")
4450
4451 (define_insn ""
4452 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4453 (compare:CC
4454 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4455 (match_operand:SI 2 "const_int_operand" "i,i"))
4456 (match_operand:SI 3 "mask_operand" "n,n"))
4457 (const_int 0)))
4458 (clobber (match_scratch:SI 4 "=r,r"))]
4459 "includes_rshift_p (operands[2], operands[3])"
4460 "@
4461 rlwinm. %4,%1,%s2,%m3,%M3
4462 #"
4463 [(set_attr "type" "delayed_compare")
4464 (set_attr "length" "4,8")])
4465
4466 (define_split
4467 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4468 (compare:CC
4469 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4470 (match_operand:SI 2 "const_int_operand" ""))
4471 (match_operand:SI 3 "mask_operand" ""))
4472 (const_int 0)))
4473 (clobber (match_scratch:SI 4 ""))]
4474 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4475 [(set (match_dup 4)
4476 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4477 (match_dup 3)))
4478 (set (match_dup 0)
4479 (compare:CC (match_dup 4)
4480 (const_int 0)))]
4481 "")
4482
4483 (define_insn ""
4484 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4485 (compare:CC
4486 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4487 (match_operand:SI 2 "const_int_operand" "i,i"))
4488 (match_operand:SI 3 "mask_operand" "n,n"))
4489 (const_int 0)))
4490 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4491 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4492 "includes_rshift_p (operands[2], operands[3])"
4493 "@
4494 rlwinm. %0,%1,%s2,%m3,%M3
4495 #"
4496 [(set_attr "type" "delayed_compare")
4497 (set_attr "length" "4,8")])
4498
4499 (define_split
4500 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4501 (compare:CC
4502 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4503 (match_operand:SI 2 "const_int_operand" ""))
4504 (match_operand:SI 3 "mask_operand" ""))
4505 (const_int 0)))
4506 (set (match_operand:SI 0 "gpc_reg_operand" "")
4507 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4508 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4509 [(set (match_dup 0)
4510 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4511 (set (match_dup 4)
4512 (compare:CC (match_dup 0)
4513 (const_int 0)))]
4514 "")
4515
4516 (define_insn "*lshiftrt_internal1le"
4517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4518 (zero_extend:SI
4519 (subreg:QI
4520 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4521 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4522 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4523 "rlwinm %0,%1,%s2,0xff")
4524
4525 (define_insn "*lshiftrt_internal1be"
4526 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4527 (zero_extend:SI
4528 (subreg:QI
4529 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4530 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4531 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4532 "rlwinm %0,%1,%s2,0xff")
4533
4534 (define_insn "*lshiftrt_internal2le"
4535 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4536 (compare:CC
4537 (zero_extend:SI
4538 (subreg:QI
4539 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4540 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4541 (const_int 0)))
4542 (clobber (match_scratch:SI 3 "=r,r"))]
4543 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4544 "@
4545 rlwinm. %3,%1,%s2,0xff
4546 #"
4547 [(set_attr "type" "delayed_compare")
4548 (set_attr "length" "4,8")])
4549
4550 (define_insn "*lshiftrt_internal2be"
4551 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4552 (compare:CC
4553 (zero_extend:SI
4554 (subreg:QI
4555 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4556 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4557 (const_int 0)))
4558 (clobber (match_scratch:SI 3 "=r,r"))]
4559 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4560 "@
4561 rlwinm. %3,%1,%s2,0xff
4562 #"
4563 [(set_attr "type" "delayed_compare")
4564 (set_attr "length" "4,8")])
4565
4566 (define_split
4567 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4568 (compare:CC
4569 (zero_extend:SI
4570 (subreg:QI
4571 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4572 (match_operand:SI 2 "const_int_operand" "")) 0))
4573 (const_int 0)))
4574 (clobber (match_scratch:SI 3 ""))]
4575 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4576 [(set (match_dup 3)
4577 (zero_extend:SI (subreg:QI
4578 (lshiftrt:SI (match_dup 1)
4579 (match_dup 2)) 0)))
4580 (set (match_dup 0)
4581 (compare:CC (match_dup 3)
4582 (const_int 0)))]
4583 "")
4584
4585 (define_split
4586 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4587 (compare:CC
4588 (zero_extend:SI
4589 (subreg:QI
4590 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4591 (match_operand:SI 2 "const_int_operand" "")) 3))
4592 (const_int 0)))
4593 (clobber (match_scratch:SI 3 ""))]
4594 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4595 [(set (match_dup 3)
4596 (zero_extend:SI (subreg:QI
4597 (lshiftrt:SI (match_dup 1)
4598 (match_dup 2)) 3)))
4599 (set (match_dup 0)
4600 (compare:CC (match_dup 3)
4601 (const_int 0)))]
4602 "")
4603
4604 (define_insn "*lshiftrt_internal3le"
4605 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4606 (compare:CC
4607 (zero_extend:SI
4608 (subreg:QI
4609 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4610 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4611 (const_int 0)))
4612 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4613 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4614 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4615 "@
4616 rlwinm. %0,%1,%s2,0xff
4617 #"
4618 [(set_attr "type" "delayed_compare")
4619 (set_attr "length" "4,8")])
4620
4621 (define_insn "*lshiftrt_internal3be"
4622 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4623 (compare:CC
4624 (zero_extend:SI
4625 (subreg:QI
4626 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4627 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4628 (const_int 0)))
4629 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4630 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4631 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4632 "@
4633 rlwinm. %0,%1,%s2,0xff
4634 #"
4635 [(set_attr "type" "delayed_compare")
4636 (set_attr "length" "4,8")])
4637
4638 (define_split
4639 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4640 (compare:CC
4641 (zero_extend:SI
4642 (subreg:QI
4643 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4644 (match_operand:SI 2 "const_int_operand" "")) 0))
4645 (const_int 0)))
4646 (set (match_operand:SI 0 "gpc_reg_operand" "")
4647 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4648 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4649 [(set (match_dup 0)
4650 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4651 (set (match_dup 3)
4652 (compare:CC (match_dup 0)
4653 (const_int 0)))]
4654 "")
4655
4656 (define_split
4657 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4658 (compare:CC
4659 (zero_extend:SI
4660 (subreg:QI
4661 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4662 (match_operand:SI 2 "const_int_operand" "")) 3))
4663 (const_int 0)))
4664 (set (match_operand:SI 0 "gpc_reg_operand" "")
4665 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4666 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4667 [(set (match_dup 0)
4668 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4669 (set (match_dup 3)
4670 (compare:CC (match_dup 0)
4671 (const_int 0)))]
4672 "")
4673
4674 (define_insn "*lshiftrt_internal4le"
4675 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4676 (zero_extend:SI
4677 (subreg:HI
4678 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4679 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4680 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4681 "rlwinm %0,%1,%s2,0xffff")
4682
4683 (define_insn "*lshiftrt_internal4be"
4684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4685 (zero_extend:SI
4686 (subreg:HI
4687 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4688 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4689 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4690 "rlwinm %0,%1,%s2,0xffff")
4691
4692 (define_insn "*lshiftrt_internal5le"
4693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4694 (compare:CC
4695 (zero_extend:SI
4696 (subreg:HI
4697 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4698 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4699 (const_int 0)))
4700 (clobber (match_scratch:SI 3 "=r,r"))]
4701 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4702 "@
4703 rlwinm. %3,%1,%s2,0xffff
4704 #"
4705 [(set_attr "type" "delayed_compare")
4706 (set_attr "length" "4,8")])
4707
4708 (define_insn "*lshiftrt_internal5be"
4709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4710 (compare:CC
4711 (zero_extend:SI
4712 (subreg:HI
4713 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4714 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4715 (const_int 0)))
4716 (clobber (match_scratch:SI 3 "=r,r"))]
4717 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4718 "@
4719 rlwinm. %3,%1,%s2,0xffff
4720 #"
4721 [(set_attr "type" "delayed_compare")
4722 (set_attr "length" "4,8")])
4723
4724 (define_split
4725 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4726 (compare:CC
4727 (zero_extend:SI
4728 (subreg:HI
4729 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4730 (match_operand:SI 2 "const_int_operand" "")) 0))
4731 (const_int 0)))
4732 (clobber (match_scratch:SI 3 ""))]
4733 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4734 [(set (match_dup 3)
4735 (zero_extend:SI (subreg:HI
4736 (lshiftrt:SI (match_dup 1)
4737 (match_dup 2)) 0)))
4738 (set (match_dup 0)
4739 (compare:CC (match_dup 3)
4740 (const_int 0)))]
4741 "")
4742
4743 (define_split
4744 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4745 (compare:CC
4746 (zero_extend:SI
4747 (subreg:HI
4748 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4749 (match_operand:SI 2 "const_int_operand" "")) 2))
4750 (const_int 0)))
4751 (clobber (match_scratch:SI 3 ""))]
4752 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4753 [(set (match_dup 3)
4754 (zero_extend:SI (subreg:HI
4755 (lshiftrt:SI (match_dup 1)
4756 (match_dup 2)) 2)))
4757 (set (match_dup 0)
4758 (compare:CC (match_dup 3)
4759 (const_int 0)))]
4760 "")
4761
4762 (define_insn "*lshiftrt_internal5le"
4763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4764 (compare:CC
4765 (zero_extend:SI
4766 (subreg:HI
4767 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4768 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4769 (const_int 0)))
4770 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4771 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4772 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4773 "@
4774 rlwinm. %0,%1,%s2,0xffff
4775 #"
4776 [(set_attr "type" "delayed_compare")
4777 (set_attr "length" "4,8")])
4778
4779 (define_insn "*lshiftrt_internal5be"
4780 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4781 (compare:CC
4782 (zero_extend:SI
4783 (subreg:HI
4784 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4785 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4786 (const_int 0)))
4787 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4788 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4789 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4790 "@
4791 rlwinm. %0,%1,%s2,0xffff
4792 #"
4793 [(set_attr "type" "delayed_compare")
4794 (set_attr "length" "4,8")])
4795
4796 (define_split
4797 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4798 (compare:CC
4799 (zero_extend:SI
4800 (subreg:HI
4801 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4802 (match_operand:SI 2 "const_int_operand" "")) 0))
4803 (const_int 0)))
4804 (set (match_operand:SI 0 "gpc_reg_operand" "")
4805 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4806 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4807 [(set (match_dup 0)
4808 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4809 (set (match_dup 3)
4810 (compare:CC (match_dup 0)
4811 (const_int 0)))]
4812 "")
4813
4814 (define_split
4815 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4816 (compare:CC
4817 (zero_extend:SI
4818 (subreg:HI
4819 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4820 (match_operand:SI 2 "const_int_operand" "")) 2))
4821 (const_int 0)))
4822 (set (match_operand:SI 0 "gpc_reg_operand" "")
4823 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4824 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4825 [(set (match_dup 0)
4826 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4827 (set (match_dup 3)
4828 (compare:CC (match_dup 0)
4829 (const_int 0)))]
4830 "")
4831
4832 (define_insn "ashrsi3"
4833 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4834 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4835 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4836 ""
4837 "@
4838 sraw %0,%1,%2
4839 srawi %0,%1,%h2"
4840 [(set_attr "type" "var_shift_rotate,shift")])
4841
4842 (define_insn "*ashrsi3_64"
4843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4844 (sign_extend:DI
4845 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4846 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4847 "TARGET_POWERPC64"
4848 "@
4849 sraw %0,%1,%2
4850 srawi %0,%1,%h2"
4851 [(set_attr "type" "var_shift_rotate,shift")])
4852
4853 (define_insn ""
4854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4855 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4856 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4857 (const_int 0)))
4858 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4859 ""
4860 "@
4861 sraw. %3,%1,%2
4862 srawi. %3,%1,%h2
4863 #
4864 #"
4865 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4866 (set_attr "length" "4,4,8,8")])
4867
4868 (define_split
4869 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4870 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4871 (match_operand:SI 2 "reg_or_cint_operand" ""))
4872 (const_int 0)))
4873 (clobber (match_scratch:SI 3 ""))]
4874 "reload_completed"
4875 [(set (match_dup 3)
4876 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4877 (set (match_dup 0)
4878 (compare:CC (match_dup 3)
4879 (const_int 0)))]
4880 "")
4881
4882 (define_insn ""
4883 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4884 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4885 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4886 (const_int 0)))
4887 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4888 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4889 ""
4890 "@
4891 sraw. %0,%1,%2
4892 srawi. %0,%1,%h2
4893 #
4894 #"
4895 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4896 (set_attr "length" "4,4,8,8")])
4897 \f
4898 ;; Builtins to replace a division to generate FRE reciprocal estimate
4899 ;; instructions and the necessary fixup instructions
4900 (define_expand "recip<mode>3"
4901 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4902 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4903 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4904 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4905 {
4906 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4907 DONE;
4908 })
4909
4910 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4911 ;; hardware division. This is only done before register allocation and with
4912 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4913 (define_split
4914 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4915 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4916 (match_operand 2 "gpc_reg_operand" "")))]
4917 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4918 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4919 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4920 [(const_int 0)]
4921 {
4922 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4923 DONE;
4924 })
4925
4926 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4927 ;; appropriate fixup.
4928 (define_expand "rsqrt<mode>2"
4929 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4930 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4931 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4932 {
4933 rs6000_emit_swrsqrt (operands[0], operands[1]);
4934 DONE;
4935 })
4936 \f
4937 (define_split
4938 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4939 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4940 (match_operand:SI 2 "reg_or_cint_operand" ""))
4941 (const_int 0)))
4942 (set (match_operand:SI 0 "gpc_reg_operand" "")
4943 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4944 "reload_completed"
4945 [(set (match_dup 0)
4946 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4947 (set (match_dup 3)
4948 (compare:CC (match_dup 0)
4949 (const_int 0)))]
4950 "")
4951
4952 ;; Floating-point insns, excluding normal data motion.
4953 ;;
4954 ;; PowerPC has a full set of single-precision floating point instructions.
4955 ;;
4956 ;; For the POWER architecture, we pretend that we have both SFmode and
4957 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4958 ;; The only conversions we will do will be when storing to memory. In that
4959 ;; case, we will use the "frsp" instruction before storing.
4960 ;;
4961 ;; Note that when we store into a single-precision memory location, we need to
4962 ;; use the frsp insn first. If the register being stored isn't dead, we
4963 ;; need a scratch register for the frsp. But this is difficult when the store
4964 ;; is done by reload. It is not incorrect to do the frsp on the register in
4965 ;; this case, we just lose precision that we would have otherwise gotten but
4966 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4967
4968 (define_expand "extendsfdf2"
4969 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4970 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4971 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4972 "")
4973
4974 (define_insn_and_split "*extendsfdf2_fpr"
4975 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4976 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4977 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4978 "@
4979 #
4980 fmr %0,%1
4981 lfs%U1%X1 %0,%1"
4982 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4983 [(const_int 0)]
4984 {
4985 emit_note (NOTE_INSN_DELETED);
4986 DONE;
4987 }
4988 [(set_attr_alternative "type"
4989 [(const_string "fp")
4990 (const_string "fp")
4991 (if_then_else
4992 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
4993 (const_string "fpload_ux")
4994 (if_then_else
4995 (match_test "update_address_mem (operands[1], VOIDmode)")
4996 (const_string "fpload_u")
4997 (const_string "fpload")))])])
4998
4999 (define_expand "truncdfsf2"
5000 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5001 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5002 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5003 "")
5004
5005 (define_insn "*truncdfsf2_fpr"
5006 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5007 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5008 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5009 "frsp %0,%1"
5010 [(set_attr "type" "fp")])
5011
5012 (define_expand "negsf2"
5013 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5014 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5015 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5016 "")
5017
5018 (define_insn "*negsf2"
5019 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5020 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5021 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5022 "fneg %0,%1"
5023 [(set_attr "type" "fp")])
5024
5025 (define_expand "abssf2"
5026 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5027 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5028 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5029 "")
5030
5031 (define_insn "*abssf2"
5032 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5033 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5034 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5035 "fabs %0,%1"
5036 [(set_attr "type" "fp")])
5037
5038 (define_insn ""
5039 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5040 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5041 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5042 "fnabs %0,%1"
5043 [(set_attr "type" "fp")])
5044
5045 (define_expand "addsf3"
5046 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5047 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5048 (match_operand:SF 2 "gpc_reg_operand" "")))]
5049 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5050 "")
5051
5052 (define_insn ""
5053 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5054 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5055 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5056 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5057 "fadds %0,%1,%2"
5058 [(set_attr "type" "fp")
5059 (set_attr "fp_type" "fp_addsub_s")])
5060
5061 (define_expand "subsf3"
5062 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5063 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5064 (match_operand:SF 2 "gpc_reg_operand" "")))]
5065 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5066 "")
5067
5068 (define_insn ""
5069 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5070 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5071 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5072 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5073 "fsubs %0,%1,%2"
5074 [(set_attr "type" "fp")
5075 (set_attr "fp_type" "fp_addsub_s")])
5076
5077 (define_expand "mulsf3"
5078 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5079 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5080 (match_operand:SF 2 "gpc_reg_operand" "")))]
5081 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5082 "")
5083
5084 (define_insn ""
5085 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5086 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5087 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5088 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5089 "fmuls %0,%1,%2"
5090 [(set_attr "type" "fp")
5091 (set_attr "fp_type" "fp_mul_s")])
5092
5093 (define_expand "divsf3"
5094 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5095 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5096 (match_operand:SF 2 "gpc_reg_operand" "")))]
5097 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5098 "")
5099
5100 (define_insn ""
5101 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5102 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5103 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5104 "TARGET_HARD_FLOAT && TARGET_FPRS
5105 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5106 "fdivs %0,%1,%2"
5107 [(set_attr "type" "sdiv")])
5108
5109 (define_insn "fres"
5110 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5111 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5112 "TARGET_FRES"
5113 "fres %0,%1"
5114 [(set_attr "type" "fp")])
5115
5116 ; builtin fmaf support
5117 (define_insn "*fmasf4_fpr"
5118 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5119 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5120 (match_operand:SF 2 "gpc_reg_operand" "f")
5121 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5122 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5123 "fmadds %0,%1,%2,%3"
5124 [(set_attr "type" "fp")
5125 (set_attr "fp_type" "fp_maddsub_s")])
5126
5127 (define_insn "*fmssf4_fpr"
5128 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5129 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5130 (match_operand:SF 2 "gpc_reg_operand" "f")
5131 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5132 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5133 "fmsubs %0,%1,%2,%3"
5134 [(set_attr "type" "fp")
5135 (set_attr "fp_type" "fp_maddsub_s")])
5136
5137 (define_insn "*nfmasf4_fpr"
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5139 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5140 (match_operand:SF 2 "gpc_reg_operand" "f")
5141 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5142 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5143 "fnmadds %0,%1,%2,%3"
5144 [(set_attr "type" "fp")
5145 (set_attr "fp_type" "fp_maddsub_s")])
5146
5147 (define_insn "*nfmssf4_fpr"
5148 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5149 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5150 (match_operand:SF 2 "gpc_reg_operand" "f")
5151 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5152 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5153 "fnmsubs %0,%1,%2,%3"
5154 [(set_attr "type" "fp")
5155 (set_attr "fp_type" "fp_maddsub_s")])
5156
5157 (define_expand "sqrtsf2"
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5159 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5160 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
5161 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5162 && !TARGET_SIMPLE_FPU"
5163 "")
5164
5165 (define_insn ""
5166 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5167 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5168 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5169 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5170 "fsqrts %0,%1"
5171 [(set_attr "type" "ssqrt")])
5172
5173 (define_insn "*rsqrtsf_internal1"
5174 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5175 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5176 UNSPEC_RSQRT))]
5177 "TARGET_FRSQRTES"
5178 "frsqrtes %0,%1"
5179 [(set_attr "type" "fp")])
5180
5181 (define_expand "copysign<mode>3"
5182 [(set (match_dup 3)
5183 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5184 (set (match_dup 4)
5185 (neg:SFDF (abs:SFDF (match_dup 1))))
5186 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5187 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5188 (match_dup 5))
5189 (match_dup 3)
5190 (match_dup 4)))]
5191 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5192 && ((TARGET_PPC_GFXOPT
5193 && !HONOR_NANS (<MODE>mode)
5194 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5195 || TARGET_CMPB
5196 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5197 {
5198 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5199 {
5200 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5201 operands[2]));
5202 DONE;
5203 }
5204
5205 operands[3] = gen_reg_rtx (<MODE>mode);
5206 operands[4] = gen_reg_rtx (<MODE>mode);
5207 operands[5] = CONST0_RTX (<MODE>mode);
5208 })
5209
5210 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5211 ;; compiler from optimizing -0.0
5212 (define_insn "copysign<mode>3_fcpsgn"
5213 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5214 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
5215 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
5216 UNSPEC_COPYSIGN))]
5217 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5218 "fcpsgn %0,%2,%1"
5219 [(set_attr "type" "fp")])
5220
5221 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5222 ;; fsel instruction and some auxiliary computations. Then we just have a
5223 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5224 ;; combine.
5225 (define_expand "smaxsf3"
5226 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5227 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5228 (match_operand:SF 2 "gpc_reg_operand" ""))
5229 (match_dup 1)
5230 (match_dup 2)))]
5231 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5232 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5233 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5234
5235 (define_expand "sminsf3"
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5237 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5238 (match_operand:SF 2 "gpc_reg_operand" ""))
5239 (match_dup 2)
5240 (match_dup 1)))]
5241 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5242 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5243 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5244
5245 (define_split
5246 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5247 (match_operator:SF 3 "min_max_operator"
5248 [(match_operand:SF 1 "gpc_reg_operand" "")
5249 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5250 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5251 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5252 [(const_int 0)]
5253 "
5254 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5255 operands[1], operands[2]);
5256 DONE;
5257 }")
5258
5259 (define_expand "mov<mode>cc"
5260 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5261 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5262 (match_operand:GPR 2 "gpc_reg_operand" "")
5263 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5264 "TARGET_ISEL<sel>"
5265 "
5266 {
5267 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5268 DONE;
5269 else
5270 FAIL;
5271 }")
5272
5273 ;; We use the BASE_REGS for the isel input operands because, if rA is
5274 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5275 ;; because we may switch the operands and rB may end up being rA.
5276 ;;
5277 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5278 ;; leave out the mode in operand 4 and use one pattern, but reload can
5279 ;; change the mode underneath our feet and then gets confused trying
5280 ;; to reload the value.
5281 (define_insn "isel_signed_<mode>"
5282 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5283 (if_then_else:GPR
5284 (match_operator 1 "scc_comparison_operator"
5285 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5286 (const_int 0)])
5287 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5288 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5289 "TARGET_ISEL<sel>"
5290 "*
5291 { return output_isel (operands); }"
5292 [(set_attr "type" "isel")
5293 (set_attr "length" "4")])
5294
5295 (define_insn "isel_unsigned_<mode>"
5296 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5297 (if_then_else:GPR
5298 (match_operator 1 "scc_comparison_operator"
5299 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5300 (const_int 0)])
5301 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5302 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5303 "TARGET_ISEL<sel>"
5304 "*
5305 { return output_isel (operands); }"
5306 [(set_attr "type" "isel")
5307 (set_attr "length" "4")])
5308
5309 ;; These patterns can be useful for combine; they let combine know that
5310 ;; isel can handle reversed comparisons so long as the operands are
5311 ;; registers.
5312
5313 (define_insn "*isel_reversed_signed_<mode>"
5314 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5315 (if_then_else:GPR
5316 (match_operator 1 "scc_rev_comparison_operator"
5317 [(match_operand:CC 4 "cc_reg_operand" "y")
5318 (const_int 0)])
5319 (match_operand:GPR 2 "gpc_reg_operand" "b")
5320 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5321 "TARGET_ISEL<sel>"
5322 "*
5323 { return output_isel (operands); }"
5324 [(set_attr "type" "isel")
5325 (set_attr "length" "4")])
5326
5327 (define_insn "*isel_reversed_unsigned_<mode>"
5328 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5329 (if_then_else:GPR
5330 (match_operator 1 "scc_rev_comparison_operator"
5331 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5332 (const_int 0)])
5333 (match_operand:GPR 2 "gpc_reg_operand" "b")
5334 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5335 "TARGET_ISEL<sel>"
5336 "*
5337 { return output_isel (operands); }"
5338 [(set_attr "type" "isel")
5339 (set_attr "length" "4")])
5340
5341 (define_expand "movsfcc"
5342 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5343 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5344 (match_operand:SF 2 "gpc_reg_operand" "")
5345 (match_operand:SF 3 "gpc_reg_operand" "")))]
5346 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5347 "
5348 {
5349 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5350 DONE;
5351 else
5352 FAIL;
5353 }")
5354
5355 (define_insn "*fselsfsf4"
5356 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5357 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5358 (match_operand:SF 4 "zero_fp_constant" "F"))
5359 (match_operand:SF 2 "gpc_reg_operand" "f")
5360 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5361 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5362 "fsel %0,%1,%2,%3"
5363 [(set_attr "type" "fp")])
5364
5365 (define_insn "*fseldfsf4"
5366 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5367 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5368 (match_operand:DF 4 "zero_fp_constant" "F"))
5369 (match_operand:SF 2 "gpc_reg_operand" "f")
5370 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5371 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5372 "fsel %0,%1,%2,%3"
5373 [(set_attr "type" "fp")])
5374
5375 (define_expand "negdf2"
5376 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5377 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5378 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5379 "")
5380
5381 (define_insn "*negdf2_fpr"
5382 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5383 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5384 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5385 && !VECTOR_UNIT_VSX_P (DFmode)"
5386 "fneg %0,%1"
5387 [(set_attr "type" "fp")])
5388
5389 (define_expand "absdf2"
5390 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5391 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5392 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5393 "")
5394
5395 (define_insn "*absdf2_fpr"
5396 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5397 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5398 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5399 && !VECTOR_UNIT_VSX_P (DFmode)"
5400 "fabs %0,%1"
5401 [(set_attr "type" "fp")])
5402
5403 (define_insn "*nabsdf2_fpr"
5404 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5405 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5406 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5407 && !VECTOR_UNIT_VSX_P (DFmode)"
5408 "fnabs %0,%1"
5409 [(set_attr "type" "fp")])
5410
5411 (define_expand "adddf3"
5412 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5413 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5414 (match_operand:DF 2 "gpc_reg_operand" "")))]
5415 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5416 "")
5417
5418 (define_insn "*adddf3_fpr"
5419 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5420 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5421 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5422 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5423 && !VECTOR_UNIT_VSX_P (DFmode)"
5424 "fadd %0,%1,%2"
5425 [(set_attr "type" "fp")
5426 (set_attr "fp_type" "fp_addsub_d")])
5427
5428 (define_expand "subdf3"
5429 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5430 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5431 (match_operand:DF 2 "gpc_reg_operand" "")))]
5432 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5433 "")
5434
5435 (define_insn "*subdf3_fpr"
5436 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5437 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5438 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5439 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5440 && !VECTOR_UNIT_VSX_P (DFmode)"
5441 "fsub %0,%1,%2"
5442 [(set_attr "type" "fp")
5443 (set_attr "fp_type" "fp_addsub_d")])
5444
5445 (define_expand "muldf3"
5446 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5447 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5448 (match_operand:DF 2 "gpc_reg_operand" "")))]
5449 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5450 "")
5451
5452 (define_insn "*muldf3_fpr"
5453 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5454 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5455 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5456 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5457 && !VECTOR_UNIT_VSX_P (DFmode)"
5458 "fmul %0,%1,%2"
5459 [(set_attr "type" "dmul")
5460 (set_attr "fp_type" "fp_mul_d")])
5461
5462 (define_expand "divdf3"
5463 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5464 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5465 (match_operand:DF 2 "gpc_reg_operand" "")))]
5466 "TARGET_HARD_FLOAT
5467 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5468 && !TARGET_SIMPLE_FPU"
5469 "")
5470
5471 (define_insn "*divdf3_fpr"
5472 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5473 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5474 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5475 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
5476 && !VECTOR_UNIT_VSX_P (DFmode)"
5477 "fdiv %0,%1,%2"
5478 [(set_attr "type" "ddiv")])
5479
5480 (define_insn "*fred_fpr"
5481 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5482 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5483 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
5484 "fre %0,%1"
5485 [(set_attr "type" "fp")])
5486
5487 (define_insn "*rsqrtdf_internal1"
5488 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5489 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
5490 UNSPEC_RSQRT))]
5491 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
5492 "frsqrte %0,%1"
5493 [(set_attr "type" "fp")])
5494
5495 ; builtin fma support
5496 (define_insn "*fmadf4_fpr"
5497 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5498 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5499 (match_operand:DF 2 "gpc_reg_operand" "f")
5500 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5501 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5502 && VECTOR_UNIT_NONE_P (DFmode)"
5503 "fmadd %0,%1,%2,%3"
5504 [(set_attr "type" "fp")
5505 (set_attr "fp_type" "fp_maddsub_d")])
5506
5507 (define_insn "*fmsdf4_fpr"
5508 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5509 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5510 (match_operand:DF 2 "gpc_reg_operand" "f")
5511 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5512 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5513 && VECTOR_UNIT_NONE_P (DFmode)"
5514 "fmsub %0,%1,%2,%3"
5515 [(set_attr "type" "fp")
5516 (set_attr "fp_type" "fp_maddsub_d")])
5517
5518 (define_insn "*nfmadf4_fpr"
5519 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5520 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5521 (match_operand:DF 2 "gpc_reg_operand" "f")
5522 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5523 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5524 && VECTOR_UNIT_NONE_P (DFmode)"
5525 "fnmadd %0,%1,%2,%3"
5526 [(set_attr "type" "fp")
5527 (set_attr "fp_type" "fp_maddsub_d")])
5528
5529 (define_insn "*nfmsdf4_fpr"
5530 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5531 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5532 (match_operand:DF 2 "gpc_reg_operand" "f")
5533 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5534 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5535 && VECTOR_UNIT_NONE_P (DFmode)"
5536 "fnmsub %0,%1,%2,%3"
5537 [(set_attr "type" "fp")
5538 (set_attr "fp_type" "fp_maddsub_d")])
5539
5540 (define_expand "sqrtdf2"
5541 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5542 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5543 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5544 "")
5545
5546 (define_insn "*sqrtdf2_fpr"
5547 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5548 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5549 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5550 && !VECTOR_UNIT_VSX_P (DFmode)"
5551 "fsqrt %0,%1"
5552 [(set_attr "type" "dsqrt")])
5553
5554 ;; The conditional move instructions allow us to perform max and min
5555 ;; operations even when
5556
5557 (define_expand "smaxdf3"
5558 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5559 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5560 (match_operand:DF 2 "gpc_reg_operand" ""))
5561 (match_dup 1)
5562 (match_dup 2)))]
5563 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5564 && !flag_trapping_math"
5565 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5566
5567 (define_expand "smindf3"
5568 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5569 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5570 (match_operand:DF 2 "gpc_reg_operand" ""))
5571 (match_dup 2)
5572 (match_dup 1)))]
5573 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5574 && !flag_trapping_math"
5575 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5576
5577 (define_split
5578 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5579 (match_operator:DF 3 "min_max_operator"
5580 [(match_operand:DF 1 "gpc_reg_operand" "")
5581 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5582 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5583 && !flag_trapping_math"
5584 [(const_int 0)]
5585 "
5586 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5587 operands[1], operands[2]);
5588 DONE;
5589 }")
5590
5591 (define_expand "movdfcc"
5592 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5593 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5594 (match_operand:DF 2 "gpc_reg_operand" "")
5595 (match_operand:DF 3 "gpc_reg_operand" "")))]
5596 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5597 "
5598 {
5599 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5600 DONE;
5601 else
5602 FAIL;
5603 }")
5604
5605 (define_insn "*fseldfdf4"
5606 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5607 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5608 (match_operand:DF 4 "zero_fp_constant" "F"))
5609 (match_operand:DF 2 "gpc_reg_operand" "d")
5610 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5611 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5612 "fsel %0,%1,%2,%3"
5613 [(set_attr "type" "fp")])
5614
5615 (define_insn "*fselsfdf4"
5616 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5617 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5618 (match_operand:SF 4 "zero_fp_constant" "F"))
5619 (match_operand:DF 2 "gpc_reg_operand" "d")
5620 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5621 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5622 "fsel %0,%1,%2,%3"
5623 [(set_attr "type" "fp")])
5624 \f
5625 ;; Conversions to and from floating-point.
5626
5627 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5628 ; don't want to support putting SImode in FPR registers.
5629 (define_insn "lfiwax"
5630 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5631 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5632 UNSPEC_LFIWAX))]
5633 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5634 "@
5635 lfiwax %0,%y1
5636 lxsiwax %x0,%y1
5637 mtvsrwa %x0,%1"
5638 [(set_attr "type" "fpload,fpload,mffgpr")])
5639
5640 ; This split must be run before register allocation because it allocates the
5641 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5642 ; it earlier to allow for the combiner to merge insns together where it might
5643 ; not be needed and also in case the insns are deleted as dead code.
5644
5645 (define_insn_and_split "floatsi<mode>2_lfiwax"
5646 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5647 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5648 (clobber (match_scratch:DI 2 "=d"))]
5649 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5650 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5651 "#"
5652 ""
5653 [(pc)]
5654 "
5655 {
5656 rtx dest = operands[0];
5657 rtx src = operands[1];
5658 rtx tmp;
5659
5660 if (!MEM_P (src) && TARGET_POWERPC64
5661 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5662 tmp = convert_to_mode (DImode, src, false);
5663 else
5664 {
5665 tmp = operands[2];
5666 if (GET_CODE (tmp) == SCRATCH)
5667 tmp = gen_reg_rtx (DImode);
5668 if (MEM_P (src))
5669 {
5670 src = rs6000_address_for_fpconvert (src);
5671 emit_insn (gen_lfiwax (tmp, src));
5672 }
5673 else
5674 {
5675 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5676 emit_move_insn (stack, src);
5677 emit_insn (gen_lfiwax (tmp, stack));
5678 }
5679 }
5680 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5681 DONE;
5682 }"
5683 [(set_attr "length" "12")
5684 (set_attr "type" "fpload")])
5685
5686 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5687 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5688 (float:SFDF
5689 (sign_extend:DI
5690 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5691 (clobber (match_scratch:DI 2 "=0,d"))]
5692 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5693 && <SI_CONVERT_FP>"
5694 "#"
5695 ""
5696 [(pc)]
5697 "
5698 {
5699 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5700 if (GET_CODE (operands[2]) == SCRATCH)
5701 operands[2] = gen_reg_rtx (DImode);
5702 emit_insn (gen_lfiwax (operands[2], operands[1]));
5703 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5704 DONE;
5705 }"
5706 [(set_attr "length" "8")
5707 (set_attr "type" "fpload")])
5708
5709 (define_insn "lfiwzx"
5710 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5711 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5712 UNSPEC_LFIWZX))]
5713 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5714 "@
5715 lfiwzx %0,%y1
5716 lxsiwzx %x0,%y1
5717 mtvsrwz %x0,%1"
5718 [(set_attr "type" "fpload,fpload,mftgpr")])
5719
5720 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5721 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5722 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5723 (clobber (match_scratch:DI 2 "=d"))]
5724 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5725 && <SI_CONVERT_FP>"
5726 "#"
5727 ""
5728 [(pc)]
5729 "
5730 {
5731 rtx dest = operands[0];
5732 rtx src = operands[1];
5733 rtx tmp;
5734
5735 if (!MEM_P (src) && TARGET_POWERPC64
5736 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5737 tmp = convert_to_mode (DImode, src, true);
5738 else
5739 {
5740 tmp = operands[2];
5741 if (GET_CODE (tmp) == SCRATCH)
5742 tmp = gen_reg_rtx (DImode);
5743 if (MEM_P (src))
5744 {
5745 src = rs6000_address_for_fpconvert (src);
5746 emit_insn (gen_lfiwzx (tmp, src));
5747 }
5748 else
5749 {
5750 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5751 emit_move_insn (stack, src);
5752 emit_insn (gen_lfiwzx (tmp, stack));
5753 }
5754 }
5755 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5756 DONE;
5757 }"
5758 [(set_attr "length" "12")
5759 (set_attr "type" "fpload")])
5760
5761 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5762 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5763 (unsigned_float:SFDF
5764 (zero_extend:DI
5765 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5766 (clobber (match_scratch:DI 2 "=0,d"))]
5767 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5768 && <SI_CONVERT_FP>"
5769 "#"
5770 ""
5771 [(pc)]
5772 "
5773 {
5774 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5775 if (GET_CODE (operands[2]) == SCRATCH)
5776 operands[2] = gen_reg_rtx (DImode);
5777 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5778 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5779 DONE;
5780 }"
5781 [(set_attr "length" "8")
5782 (set_attr "type" "fpload")])
5783
5784 ; For each of these conversions, there is a define_expand, a define_insn
5785 ; with a '#' template, and a define_split (with C code). The idea is
5786 ; to allow constant folding with the template of the define_insn,
5787 ; then to have the insns split later (between sched1 and final).
5788
5789 (define_expand "floatsidf2"
5790 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5791 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5792 (use (match_dup 2))
5793 (use (match_dup 3))
5794 (clobber (match_dup 4))
5795 (clobber (match_dup 5))
5796 (clobber (match_dup 6))])]
5797 "TARGET_HARD_FLOAT
5798 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5799 "
5800 {
5801 if (TARGET_E500_DOUBLE)
5802 {
5803 if (!REG_P (operands[1]))
5804 operands[1] = force_reg (SImode, operands[1]);
5805 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5806 DONE;
5807 }
5808 else if (TARGET_LFIWAX && TARGET_FCFID)
5809 {
5810 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5811 DONE;
5812 }
5813 else if (TARGET_FCFID)
5814 {
5815 rtx dreg = operands[1];
5816 if (!REG_P (dreg))
5817 dreg = force_reg (SImode, dreg);
5818 dreg = convert_to_mode (DImode, dreg, false);
5819 emit_insn (gen_floatdidf2 (operands[0], dreg));
5820 DONE;
5821 }
5822
5823 if (!REG_P (operands[1]))
5824 operands[1] = force_reg (SImode, operands[1]);
5825 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5826 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5827 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5828 operands[5] = gen_reg_rtx (DFmode);
5829 operands[6] = gen_reg_rtx (SImode);
5830 }")
5831
5832 (define_insn_and_split "*floatsidf2_internal"
5833 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5834 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5835 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5836 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5837 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5838 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5839 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5840 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5841 "#"
5842 ""
5843 [(pc)]
5844 "
5845 {
5846 rtx lowword, highword;
5847 gcc_assert (MEM_P (operands[4]));
5848 highword = adjust_address (operands[4], SImode, 0);
5849 lowword = adjust_address (operands[4], SImode, 4);
5850 if (! WORDS_BIG_ENDIAN)
5851 {
5852 rtx tmp;
5853 tmp = highword; highword = lowword; lowword = tmp;
5854 }
5855
5856 emit_insn (gen_xorsi3 (operands[6], operands[1],
5857 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5858 emit_move_insn (lowword, operands[6]);
5859 emit_move_insn (highword, operands[2]);
5860 emit_move_insn (operands[5], operands[4]);
5861 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5862 DONE;
5863 }"
5864 [(set_attr "length" "24")
5865 (set_attr "type" "fp")])
5866
5867 ;; If we don't have a direct conversion to single precision, don't enable this
5868 ;; conversion for 32-bit without fast math, because we don't have the insn to
5869 ;; generate the fixup swizzle to avoid double rounding problems.
5870 (define_expand "floatunssisf2"
5871 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5872 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5873 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5874 && (!TARGET_FPRS
5875 || (TARGET_FPRS
5876 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5877 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5878 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5879 "
5880 {
5881 if (!TARGET_FPRS)
5882 {
5883 if (!REG_P (operands[1]))
5884 operands[1] = force_reg (SImode, operands[1]);
5885 }
5886 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5887 {
5888 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5889 DONE;
5890 }
5891 else
5892 {
5893 rtx dreg = operands[1];
5894 if (!REG_P (dreg))
5895 dreg = force_reg (SImode, dreg);
5896 dreg = convert_to_mode (DImode, dreg, true);
5897 emit_insn (gen_floatdisf2 (operands[0], dreg));
5898 DONE;
5899 }
5900 }")
5901
5902 (define_expand "floatunssidf2"
5903 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5904 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5905 (use (match_dup 2))
5906 (use (match_dup 3))
5907 (clobber (match_dup 4))
5908 (clobber (match_dup 5))])]
5909 "TARGET_HARD_FLOAT
5910 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5911 "
5912 {
5913 if (TARGET_E500_DOUBLE)
5914 {
5915 if (!REG_P (operands[1]))
5916 operands[1] = force_reg (SImode, operands[1]);
5917 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5918 DONE;
5919 }
5920 else if (TARGET_LFIWZX && TARGET_FCFID)
5921 {
5922 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5923 DONE;
5924 }
5925 else if (TARGET_FCFID)
5926 {
5927 rtx dreg = operands[1];
5928 if (!REG_P (dreg))
5929 dreg = force_reg (SImode, dreg);
5930 dreg = convert_to_mode (DImode, dreg, true);
5931 emit_insn (gen_floatdidf2 (operands[0], dreg));
5932 DONE;
5933 }
5934
5935 if (!REG_P (operands[1]))
5936 operands[1] = force_reg (SImode, operands[1]);
5937 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5938 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5939 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5940 operands[5] = gen_reg_rtx (DFmode);
5941 }")
5942
5943 (define_insn_and_split "*floatunssidf2_internal"
5944 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5945 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5946 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5947 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5948 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5949 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5950 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5951 && !(TARGET_FCFID && TARGET_POWERPC64)"
5952 "#"
5953 ""
5954 [(pc)]
5955 "
5956 {
5957 rtx lowword, highword;
5958 gcc_assert (MEM_P (operands[4]));
5959 highword = adjust_address (operands[4], SImode, 0);
5960 lowword = adjust_address (operands[4], SImode, 4);
5961 if (! WORDS_BIG_ENDIAN)
5962 {
5963 rtx tmp;
5964 tmp = highword; highword = lowword; lowword = tmp;
5965 }
5966
5967 emit_move_insn (lowword, operands[1]);
5968 emit_move_insn (highword, operands[2]);
5969 emit_move_insn (operands[5], operands[4]);
5970 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5971 DONE;
5972 }"
5973 [(set_attr "length" "20")
5974 (set_attr "type" "fp")])
5975
5976 (define_expand "fix_trunc<mode>si2"
5977 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5978 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5979 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5980 "
5981 {
5982 if (!<E500_CONVERT>)
5983 {
5984 rtx tmp, stack;
5985
5986 if (TARGET_STFIWX)
5987 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5988 else
5989 {
5990 tmp = gen_reg_rtx (DImode);
5991 stack = rs6000_allocate_stack_temp (DImode, true, false);
5992 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5993 tmp, stack));
5994 }
5995 DONE;
5996 }
5997 }")
5998
5999 ; Like the convert to float patterns, this insn must be split before
6000 ; register allocation so that it can allocate the memory slot if it
6001 ; needed
6002 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6003 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6004 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6005 (clobber (match_scratch:DI 2 "=d"))]
6006 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6007 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6008 && TARGET_STFIWX && can_create_pseudo_p ()"
6009 "#"
6010 ""
6011 [(pc)]
6012 {
6013 rtx dest = operands[0];
6014 rtx src = operands[1];
6015 rtx tmp = operands[2];
6016
6017 if (GET_CODE (tmp) == SCRATCH)
6018 tmp = gen_reg_rtx (DImode);
6019
6020 emit_insn (gen_fctiwz_<mode> (tmp, src));
6021 if (MEM_P (dest))
6022 {
6023 dest = rs6000_address_for_fpconvert (dest);
6024 emit_insn (gen_stfiwx (dest, tmp));
6025 DONE;
6026 }
6027 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6028 {
6029 dest = gen_lowpart (DImode, dest);
6030 emit_move_insn (dest, tmp);
6031 DONE;
6032 }
6033 else
6034 {
6035 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6036 emit_insn (gen_stfiwx (stack, tmp));
6037 emit_move_insn (dest, stack);
6038 DONE;
6039 }
6040 }
6041 [(set_attr "length" "12")
6042 (set_attr "type" "fp")])
6043
6044 (define_insn_and_split "fix_trunc<mode>si2_internal"
6045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6046 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6047 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6048 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6049 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6050 "#"
6051 ""
6052 [(pc)]
6053 "
6054 {
6055 rtx lowword;
6056 gcc_assert (MEM_P (operands[3]));
6057 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6058
6059 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6060 emit_move_insn (operands[3], operands[2]);
6061 emit_move_insn (operands[0], lowword);
6062 DONE;
6063 }"
6064 [(set_attr "length" "16")
6065 (set_attr "type" "fp")])
6066
6067 (define_expand "fix_trunc<mode>di2"
6068 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6069 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6070 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6071 && TARGET_FCFID"
6072 "")
6073
6074 (define_insn "*fix_trunc<mode>di2_fctidz"
6075 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6076 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6077 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6078 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6079 "fctidz %0,%1"
6080 [(set_attr "type" "fp")])
6081
6082 (define_expand "fixuns_trunc<mode>si2"
6083 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6084 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6085 "TARGET_HARD_FLOAT
6086 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6087 || <E500_CONVERT>)"
6088 "
6089 {
6090 if (!<E500_CONVERT>)
6091 {
6092 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6093 DONE;
6094 }
6095 }")
6096
6097 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6098 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6099 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6100 (clobber (match_scratch:DI 2 "=d"))]
6101 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6102 && TARGET_STFIWX && can_create_pseudo_p ()"
6103 "#"
6104 ""
6105 [(pc)]
6106 {
6107 rtx dest = operands[0];
6108 rtx src = operands[1];
6109 rtx tmp = operands[2];
6110
6111 if (GET_CODE (tmp) == SCRATCH)
6112 tmp = gen_reg_rtx (DImode);
6113
6114 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6115 if (MEM_P (dest))
6116 {
6117 dest = rs6000_address_for_fpconvert (dest);
6118 emit_insn (gen_stfiwx (dest, tmp));
6119 DONE;
6120 }
6121 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6122 {
6123 dest = gen_lowpart (DImode, dest);
6124 emit_move_insn (dest, tmp);
6125 DONE;
6126 }
6127 else
6128 {
6129 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6130 emit_insn (gen_stfiwx (stack, tmp));
6131 emit_move_insn (dest, stack);
6132 DONE;
6133 }
6134 }
6135 [(set_attr "length" "12")
6136 (set_attr "type" "fp")])
6137
6138 (define_expand "fixuns_trunc<mode>di2"
6139 [(set (match_operand:DI 0 "register_operand" "")
6140 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6141 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6142 "")
6143
6144 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6145 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6146 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6147 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6148 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6149 "fctiduz %0,%1"
6150 [(set_attr "type" "fp")])
6151
6152 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6153 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6154 ; because the first makes it clear that operand 0 is not live
6155 ; before the instruction.
6156 (define_insn "fctiwz_<mode>"
6157 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6158 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6159 UNSPEC_FCTIWZ))]
6160 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6161 "fctiwz %0,%1"
6162 [(set_attr "type" "fp")])
6163
6164 (define_insn "fctiwuz_<mode>"
6165 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6166 (unspec:DI [(unsigned_fix:SI
6167 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6168 UNSPEC_FCTIWUZ))]
6169 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6170 "fctiwuz %0,%1"
6171 [(set_attr "type" "fp")])
6172
6173 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6174 ;; since the friz instruction does not truncate the value if the floating
6175 ;; point value is < LONG_MIN or > LONG_MAX.
6176 (define_insn "*friz"
6177 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6178 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6179 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6180 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6181 && !flag_trapping_math && TARGET_FRIZ"
6182 "friz %0,%1"
6183 [(set_attr "type" "fp")])
6184
6185 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6186 ;; load to properly sign extend the value, but at least doing a store, load
6187 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6188 ;; if we have 32-bit memory ops
6189 (define_insn_and_split "*round32<mode>2_fprs"
6190 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6191 (float:SFDF
6192 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6193 (clobber (match_scratch:DI 2 "=d"))
6194 (clobber (match_scratch:DI 3 "=d"))]
6195 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6196 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6197 && can_create_pseudo_p ()"
6198 "#"
6199 ""
6200 [(pc)]
6201 {
6202 rtx dest = operands[0];
6203 rtx src = operands[1];
6204 rtx tmp1 = operands[2];
6205 rtx tmp2 = operands[3];
6206 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6207
6208 if (GET_CODE (tmp1) == SCRATCH)
6209 tmp1 = gen_reg_rtx (DImode);
6210 if (GET_CODE (tmp2) == SCRATCH)
6211 tmp2 = gen_reg_rtx (DImode);
6212
6213 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6214 emit_insn (gen_stfiwx (stack, tmp1));
6215 emit_insn (gen_lfiwax (tmp2, stack));
6216 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6217 DONE;
6218 }
6219 [(set_attr "type" "fpload")
6220 (set_attr "length" "16")])
6221
6222 (define_insn_and_split "*roundu32<mode>2_fprs"
6223 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6224 (unsigned_float:SFDF
6225 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6226 (clobber (match_scratch:DI 2 "=d"))
6227 (clobber (match_scratch:DI 3 "=d"))]
6228 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6229 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6230 && can_create_pseudo_p ()"
6231 "#"
6232 ""
6233 [(pc)]
6234 {
6235 rtx dest = operands[0];
6236 rtx src = operands[1];
6237 rtx tmp1 = operands[2];
6238 rtx tmp2 = operands[3];
6239 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6240
6241 if (GET_CODE (tmp1) == SCRATCH)
6242 tmp1 = gen_reg_rtx (DImode);
6243 if (GET_CODE (tmp2) == SCRATCH)
6244 tmp2 = gen_reg_rtx (DImode);
6245
6246 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6247 emit_insn (gen_stfiwx (stack, tmp1));
6248 emit_insn (gen_lfiwzx (tmp2, stack));
6249 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6250 DONE;
6251 }
6252 [(set_attr "type" "fpload")
6253 (set_attr "length" "16")])
6254
6255 ;; No VSX equivalent to fctid
6256 (define_insn "lrint<mode>di2"
6257 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6258 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6259 UNSPEC_FCTID))]
6260 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6261 "fctid %0,%1"
6262 [(set_attr "type" "fp")])
6263
6264 (define_expand "btrunc<mode>2"
6265 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6266 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6267 UNSPEC_FRIZ))]
6268 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6269 "")
6270
6271 (define_insn "*btrunc<mode>2_fpr"
6272 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6273 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6274 UNSPEC_FRIZ))]
6275 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6276 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6277 "friz %0,%1"
6278 [(set_attr "type" "fp")])
6279
6280 (define_expand "ceil<mode>2"
6281 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6282 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6283 UNSPEC_FRIP))]
6284 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6285 "")
6286
6287 (define_insn "*ceil<mode>2_fpr"
6288 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6289 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6290 UNSPEC_FRIP))]
6291 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6292 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6293 "frip %0,%1"
6294 [(set_attr "type" "fp")])
6295
6296 (define_expand "floor<mode>2"
6297 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6298 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6299 UNSPEC_FRIM))]
6300 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6301 "")
6302
6303 (define_insn "*floor<mode>2_fpr"
6304 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6305 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6306 UNSPEC_FRIM))]
6307 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6308 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6309 "frim %0,%1"
6310 [(set_attr "type" "fp")])
6311
6312 ;; No VSX equivalent to frin
6313 (define_insn "round<mode>2"
6314 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6315 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6316 UNSPEC_FRIN))]
6317 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6318 "frin %0,%1"
6319 [(set_attr "type" "fp")])
6320
6321 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6322 (define_insn "stfiwx"
6323 [(set (match_operand:SI 0 "memory_operand" "=Z")
6324 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6325 UNSPEC_STFIWX))]
6326 "TARGET_PPC_GFXOPT"
6327 "stfiwx %1,%y0"
6328 [(set_attr "type" "fpstore")])
6329
6330 ;; If we don't have a direct conversion to single precision, don't enable this
6331 ;; conversion for 32-bit without fast math, because we don't have the insn to
6332 ;; generate the fixup swizzle to avoid double rounding problems.
6333 (define_expand "floatsisf2"
6334 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6335 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6336 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6337 && (!TARGET_FPRS
6338 || (TARGET_FPRS
6339 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6340 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6341 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6342 "
6343 {
6344 if (!TARGET_FPRS)
6345 {
6346 if (!REG_P (operands[1]))
6347 operands[1] = force_reg (SImode, operands[1]);
6348 }
6349 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6350 {
6351 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6352 DONE;
6353 }
6354 else if (TARGET_FCFID && TARGET_LFIWAX)
6355 {
6356 rtx dfreg = gen_reg_rtx (DFmode);
6357 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6358 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6359 DONE;
6360 }
6361 else
6362 {
6363 rtx dreg = operands[1];
6364 if (!REG_P (dreg))
6365 dreg = force_reg (SImode, dreg);
6366 dreg = convert_to_mode (DImode, dreg, false);
6367 emit_insn (gen_floatdisf2 (operands[0], dreg));
6368 DONE;
6369 }
6370 }")
6371
6372 (define_expand "floatdidf2"
6373 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6374 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6375 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6376 "")
6377
6378 (define_insn "*floatdidf2_fpr"
6379 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6380 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6381 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6382 && !VECTOR_UNIT_VSX_P (DFmode)"
6383 "fcfid %0,%1"
6384 [(set_attr "type" "fp")])
6385
6386 ; Allow the combiner to merge source memory operands to the conversion so that
6387 ; the optimizer/register allocator doesn't try to load the value too early in a
6388 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6389 ; hit. We will split after reload to avoid the trip through the GPRs
6390
6391 (define_insn_and_split "*floatdidf2_mem"
6392 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6393 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6394 (clobber (match_scratch:DI 2 "=d"))]
6395 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6396 "#"
6397 "&& reload_completed"
6398 [(set (match_dup 2) (match_dup 1))
6399 (set (match_dup 0) (float:DF (match_dup 2)))]
6400 ""
6401 [(set_attr "length" "8")
6402 (set_attr "type" "fpload")])
6403
6404 (define_expand "floatunsdidf2"
6405 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6406 (unsigned_float:DF
6407 (match_operand:DI 1 "gpc_reg_operand" "")))]
6408 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6409 "")
6410
6411 (define_insn "*floatunsdidf2_fcfidu"
6412 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6413 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6414 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6415 "fcfidu %0,%1"
6416 [(set_attr "type" "fp")
6417 (set_attr "length" "4")])
6418
6419 (define_insn_and_split "*floatunsdidf2_mem"
6420 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6421 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6422 (clobber (match_scratch:DI 2 "=d"))]
6423 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6424 "#"
6425 "&& reload_completed"
6426 [(set (match_dup 2) (match_dup 1))
6427 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6428 ""
6429 [(set_attr "length" "8")
6430 (set_attr "type" "fpload")])
6431
6432 (define_expand "floatdisf2"
6433 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6434 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6435 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6436 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6437 "
6438 {
6439 if (!TARGET_FCFIDS)
6440 {
6441 rtx val = operands[1];
6442 if (!flag_unsafe_math_optimizations)
6443 {
6444 rtx label = gen_label_rtx ();
6445 val = gen_reg_rtx (DImode);
6446 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6447 emit_label (label);
6448 }
6449 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6450 DONE;
6451 }
6452 }")
6453
6454 (define_insn "floatdisf2_fcfids"
6455 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6456 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6457 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6458 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6459 "fcfids %0,%1"
6460 [(set_attr "type" "fp")])
6461
6462 (define_insn_and_split "*floatdisf2_mem"
6463 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6464 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6465 (clobber (match_scratch:DI 2 "=f"))]
6466 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6467 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6468 "#"
6469 "&& reload_completed"
6470 [(pc)]
6471 "
6472 {
6473 emit_move_insn (operands[2], operands[1]);
6474 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6475 DONE;
6476 }"
6477 [(set_attr "length" "8")])
6478
6479 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6480 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6481 ;; from double rounding.
6482 ;; Instead of creating a new cpu type for two FP operations, just use fp
6483 (define_insn_and_split "floatdisf2_internal1"
6484 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6485 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6486 (clobber (match_scratch:DF 2 "=d"))]
6487 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6488 "#"
6489 "&& reload_completed"
6490 [(set (match_dup 2)
6491 (float:DF (match_dup 1)))
6492 (set (match_dup 0)
6493 (float_truncate:SF (match_dup 2)))]
6494 ""
6495 [(set_attr "length" "8")
6496 (set_attr "type" "fp")])
6497
6498 ;; Twiddles bits to avoid double rounding.
6499 ;; Bits that might be truncated when converting to DFmode are replaced
6500 ;; by a bit that won't be lost at that stage, but is below the SFmode
6501 ;; rounding position.
6502 (define_expand "floatdisf2_internal2"
6503 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6504 (const_int 53)))
6505 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6506 (const_int 2047)))
6507 (clobber (scratch:CC))])
6508 (set (match_dup 3) (plus:DI (match_dup 3)
6509 (const_int 1)))
6510 (set (match_dup 0) (plus:DI (match_dup 0)
6511 (const_int 2047)))
6512 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6513 (const_int 2)))
6514 (set (match_dup 0) (ior:DI (match_dup 0)
6515 (match_dup 1)))
6516 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6517 (const_int -2048)))
6518 (clobber (scratch:CC))])
6519 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6520 (label_ref (match_operand:DI 2 "" ""))
6521 (pc)))
6522 (set (match_dup 0) (match_dup 1))]
6523 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6524 "
6525 {
6526 operands[3] = gen_reg_rtx (DImode);
6527 operands[4] = gen_reg_rtx (CCUNSmode);
6528 }")
6529
6530 (define_expand "floatunsdisf2"
6531 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6532 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6533 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6534 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6535 "")
6536
6537 (define_insn "floatunsdisf2_fcfidus"
6538 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6539 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6540 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6541 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6542 "fcfidus %0,%1"
6543 [(set_attr "type" "fp")])
6544
6545 (define_insn_and_split "*floatunsdisf2_mem"
6546 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6547 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6548 (clobber (match_scratch:DI 2 "=f"))]
6549 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6550 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6551 "#"
6552 "&& reload_completed"
6553 [(pc)]
6554 "
6555 {
6556 emit_move_insn (operands[2], operands[1]);
6557 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6558 DONE;
6559 }"
6560 [(set_attr "length" "8")
6561 (set_attr "type" "fpload")])
6562 \f
6563 ;; Define the DImode operations that can be done in a small number
6564 ;; of instructions. The & constraints are to prevent the register
6565 ;; allocator from allocating registers that overlap with the inputs
6566 ;; (for example, having an input in 7,8 and an output in 6,7). We
6567 ;; also allow for the output being the same as one of the inputs.
6568
6569 (define_insn "*adddi3_noppc64"
6570 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6571 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6572 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6573 "! TARGET_POWERPC64"
6574 "*
6575 {
6576 if (WORDS_BIG_ENDIAN)
6577 return (GET_CODE (operands[2])) != CONST_INT
6578 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6579 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6580 else
6581 return (GET_CODE (operands[2])) != CONST_INT
6582 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6583 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6584 }"
6585 [(set_attr "type" "two")
6586 (set_attr "length" "8")])
6587
6588 (define_insn "*subdi3_noppc64"
6589 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6590 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6591 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6592 "! TARGET_POWERPC64"
6593 "*
6594 {
6595 if (WORDS_BIG_ENDIAN)
6596 return (GET_CODE (operands[1]) != CONST_INT)
6597 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6598 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6599 else
6600 return (GET_CODE (operands[1]) != CONST_INT)
6601 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6602 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6603 }"
6604 [(set_attr "type" "two")
6605 (set_attr "length" "8")])
6606
6607 (define_insn "*negdi2_noppc64"
6608 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6609 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6610 "! TARGET_POWERPC64"
6611 "*
6612 {
6613 return (WORDS_BIG_ENDIAN)
6614 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6615 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6616 }"
6617 [(set_attr "type" "two")
6618 (set_attr "length" "8")])
6619
6620 (define_insn "mulsidi3"
6621 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6622 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6623 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6624 "! TARGET_POWERPC64"
6625 {
6626 return (WORDS_BIG_ENDIAN)
6627 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6628 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6629 }
6630 [(set_attr "type" "imul")
6631 (set_attr "length" "8")])
6632
6633 (define_split
6634 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6635 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6636 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6637 "! TARGET_POWERPC64 && reload_completed"
6638 [(set (match_dup 3)
6639 (truncate:SI
6640 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6641 (sign_extend:DI (match_dup 2)))
6642 (const_int 32))))
6643 (set (match_dup 4)
6644 (mult:SI (match_dup 1)
6645 (match_dup 2)))]
6646 "
6647 {
6648 int endian = (WORDS_BIG_ENDIAN == 0);
6649 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6650 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6651 }")
6652
6653 (define_insn "umulsidi3"
6654 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6655 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6656 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6657 "! TARGET_POWERPC64"
6658 "*
6659 {
6660 return (WORDS_BIG_ENDIAN)
6661 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6662 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6663 }"
6664 [(set_attr "type" "imul")
6665 (set_attr "length" "8")])
6666
6667 (define_split
6668 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6669 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6670 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6671 "! TARGET_POWERPC64 && reload_completed"
6672 [(set (match_dup 3)
6673 (truncate:SI
6674 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6675 (zero_extend:DI (match_dup 2)))
6676 (const_int 32))))
6677 (set (match_dup 4)
6678 (mult:SI (match_dup 1)
6679 (match_dup 2)))]
6680 "
6681 {
6682 int endian = (WORDS_BIG_ENDIAN == 0);
6683 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6684 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6685 }")
6686
6687 (define_insn "smulsi3_highpart"
6688 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6689 (truncate:SI
6690 (lshiftrt:DI (mult:DI (sign_extend:DI
6691 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6692 (sign_extend:DI
6693 (match_operand:SI 2 "gpc_reg_operand" "r")))
6694 (const_int 32))))]
6695 ""
6696 "mulhw %0,%1,%2"
6697 [(set_attr "type" "imul")])
6698
6699 (define_insn "umulsi3_highpart"
6700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6701 (truncate:SI
6702 (lshiftrt:DI (mult:DI (zero_extend:DI
6703 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6704 (zero_extend:DI
6705 (match_operand:SI 2 "gpc_reg_operand" "r")))
6706 (const_int 32))))]
6707 ""
6708 "mulhwu %0,%1,%2"
6709 [(set_attr "type" "imul")])
6710
6711 ;; Shift by a variable amount is too complex to be worth open-coding. We
6712 ;; just handle shifts by constants.
6713 (define_insn "ashrdi3_no_power"
6714 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6715 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6716 (match_operand:SI 2 "const_int_operand" "M,i")))]
6717 "!TARGET_POWERPC64"
6718 "*
6719 {
6720 switch (which_alternative)
6721 {
6722 default:
6723 gcc_unreachable ();
6724 case 0:
6725 if (WORDS_BIG_ENDIAN)
6726 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6727 else
6728 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6729 case 1:
6730 if (WORDS_BIG_ENDIAN)
6731 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6732 else
6733 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6734 }
6735 }"
6736 [(set_attr "type" "two,three")
6737 (set_attr "length" "8,12")])
6738
6739 (define_insn "*ashrdisi3_noppc64be"
6740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6741 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6742 (const_int 32)) 4))]
6743 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6744 "*
6745 {
6746 if (REGNO (operands[0]) == REGNO (operands[1]))
6747 return \"\";
6748 else
6749 return \"mr %0,%1\";
6750 }"
6751 [(set_attr "length" "4")])
6752
6753 \f
6754 ;; PowerPC64 DImode operations.
6755
6756 (define_insn "muldi3"
6757 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6758 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6759 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6760 "TARGET_POWERPC64"
6761 "@
6762 mulld %0,%1,%2
6763 mulli %0,%1,%2"
6764 [(set (attr "type")
6765 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6766 (const_string "imul3")
6767 (match_operand:SI 2 "short_cint_operand" "")
6768 (const_string "imul2")]
6769 (const_string "lmul")))])
6770
6771 (define_insn "*muldi3_internal1"
6772 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6773 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6774 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6775 (const_int 0)))
6776 (clobber (match_scratch:DI 3 "=r,r"))]
6777 "TARGET_POWERPC64"
6778 "@
6779 mulld. %3,%1,%2
6780 #"
6781 [(set_attr "type" "lmul_compare")
6782 (set_attr "length" "4,8")])
6783
6784 (define_split
6785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6786 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6787 (match_operand:DI 2 "gpc_reg_operand" ""))
6788 (const_int 0)))
6789 (clobber (match_scratch:DI 3 ""))]
6790 "TARGET_POWERPC64 && reload_completed"
6791 [(set (match_dup 3)
6792 (mult:DI (match_dup 1) (match_dup 2)))
6793 (set (match_dup 0)
6794 (compare:CC (match_dup 3)
6795 (const_int 0)))]
6796 "")
6797
6798 (define_insn "*muldi3_internal2"
6799 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6800 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6801 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6802 (const_int 0)))
6803 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6804 (mult:DI (match_dup 1) (match_dup 2)))]
6805 "TARGET_POWERPC64"
6806 "@
6807 mulld. %0,%1,%2
6808 #"
6809 [(set_attr "type" "lmul_compare")
6810 (set_attr "length" "4,8")])
6811
6812 (define_split
6813 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6814 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6815 (match_operand:DI 2 "gpc_reg_operand" ""))
6816 (const_int 0)))
6817 (set (match_operand:DI 0 "gpc_reg_operand" "")
6818 (mult:DI (match_dup 1) (match_dup 2)))]
6819 "TARGET_POWERPC64 && reload_completed"
6820 [(set (match_dup 0)
6821 (mult:DI (match_dup 1) (match_dup 2)))
6822 (set (match_dup 3)
6823 (compare:CC (match_dup 0)
6824 (const_int 0)))]
6825 "")
6826
6827 (define_insn "smuldi3_highpart"
6828 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6829 (truncate:DI
6830 (lshiftrt:TI (mult:TI (sign_extend:TI
6831 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6832 (sign_extend:TI
6833 (match_operand:DI 2 "gpc_reg_operand" "r")))
6834 (const_int 64))))]
6835 "TARGET_POWERPC64"
6836 "mulhd %0,%1,%2"
6837 [(set_attr "type" "lmul")])
6838
6839 (define_insn "umuldi3_highpart"
6840 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6841 (truncate:DI
6842 (lshiftrt:TI (mult:TI (zero_extend:TI
6843 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6844 (zero_extend:TI
6845 (match_operand:DI 2 "gpc_reg_operand" "r")))
6846 (const_int 64))))]
6847 "TARGET_POWERPC64"
6848 "mulhdu %0,%1,%2"
6849 [(set_attr "type" "lmul")])
6850
6851 (define_expand "mulditi3"
6852 [(set (match_operand:TI 0 "gpc_reg_operand")
6853 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6854 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6855 "TARGET_POWERPC64"
6856 {
6857 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6858 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6859 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6860 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6861 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6862 DONE;
6863 })
6864
6865 (define_expand "umulditi3"
6866 [(set (match_operand:TI 0 "gpc_reg_operand")
6867 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6868 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6869 "TARGET_POWERPC64"
6870 {
6871 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6872 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6873 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6874 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6875 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6876 DONE;
6877 })
6878
6879 (define_insn "rotldi3"
6880 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6881 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6882 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6883 "TARGET_POWERPC64"
6884 "@
6885 rldcl %0,%1,%2,0
6886 rldicl %0,%1,%H2,0"
6887 [(set_attr "type" "var_shift_rotate,integer")])
6888
6889 (define_insn "*rotldi3_internal2"
6890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6891 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6892 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6895 "TARGET_64BIT"
6896 "@
6897 rldcl. %3,%1,%2,0
6898 rldicl. %3,%1,%H2,0
6899 #
6900 #"
6901 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6902 (set_attr "length" "4,4,8,8")])
6903
6904 (define_split
6905 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6906 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6907 (match_operand:DI 2 "reg_or_cint_operand" ""))
6908 (const_int 0)))
6909 (clobber (match_scratch:DI 3 ""))]
6910 "TARGET_POWERPC64 && reload_completed"
6911 [(set (match_dup 3)
6912 (rotate:DI (match_dup 1) (match_dup 2)))
6913 (set (match_dup 0)
6914 (compare:CC (match_dup 3)
6915 (const_int 0)))]
6916 "")
6917
6918 (define_insn "*rotldi3_internal3"
6919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6920 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6921 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6922 (const_int 0)))
6923 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6924 (rotate:DI (match_dup 1) (match_dup 2)))]
6925 "TARGET_64BIT"
6926 "@
6927 rldcl. %0,%1,%2,0
6928 rldicl. %0,%1,%H2,0
6929 #
6930 #"
6931 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6932 (set_attr "length" "4,4,8,8")])
6933
6934 (define_split
6935 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6936 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6937 (match_operand:DI 2 "reg_or_cint_operand" ""))
6938 (const_int 0)))
6939 (set (match_operand:DI 0 "gpc_reg_operand" "")
6940 (rotate:DI (match_dup 1) (match_dup 2)))]
6941 "TARGET_POWERPC64 && reload_completed"
6942 [(set (match_dup 0)
6943 (rotate:DI (match_dup 1) (match_dup 2)))
6944 (set (match_dup 3)
6945 (compare:CC (match_dup 0)
6946 (const_int 0)))]
6947 "")
6948
6949 (define_insn "*rotldi3_internal4"
6950 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6951 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6952 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6953 (match_operand:DI 3 "mask64_operand" "n,n")))]
6954 "TARGET_POWERPC64"
6955 "@
6956 rldc%B3 %0,%1,%2,%S3
6957 rldic%B3 %0,%1,%H2,%S3"
6958 [(set_attr "type" "var_shift_rotate,integer")])
6959
6960 (define_insn "*rotldi3_internal5"
6961 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6962 (compare:CC (and:DI
6963 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6964 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6965 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6966 (const_int 0)))
6967 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6968 "TARGET_64BIT"
6969 "@
6970 rldc%B3. %4,%1,%2,%S3
6971 rldic%B3. %4,%1,%H2,%S3
6972 #
6973 #"
6974 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6975 (set_attr "length" "4,4,8,8")])
6976
6977 (define_split
6978 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6979 (compare:CC (and:DI
6980 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6981 (match_operand:DI 2 "reg_or_cint_operand" ""))
6982 (match_operand:DI 3 "mask64_operand" ""))
6983 (const_int 0)))
6984 (clobber (match_scratch:DI 4 ""))]
6985 "TARGET_POWERPC64 && reload_completed"
6986 [(set (match_dup 4)
6987 (and:DI (rotate:DI (match_dup 1)
6988 (match_dup 2))
6989 (match_dup 3)))
6990 (set (match_dup 0)
6991 (compare:CC (match_dup 4)
6992 (const_int 0)))]
6993 "")
6994
6995 (define_insn "*rotldi3_internal6"
6996 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6997 (compare:CC (and:DI
6998 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6999 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7000 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7001 (const_int 0)))
7002 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7003 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7004 "TARGET_64BIT"
7005 "@
7006 rldc%B3. %0,%1,%2,%S3
7007 rldic%B3. %0,%1,%H2,%S3
7008 #
7009 #"
7010 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7011 (set_attr "length" "4,4,8,8")])
7012
7013 (define_split
7014 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7015 (compare:CC (and:DI
7016 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7017 (match_operand:DI 2 "reg_or_cint_operand" ""))
7018 (match_operand:DI 3 "mask64_operand" ""))
7019 (const_int 0)))
7020 (set (match_operand:DI 0 "gpc_reg_operand" "")
7021 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7022 "TARGET_POWERPC64 && reload_completed"
7023 [(set (match_dup 0)
7024 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7025 (set (match_dup 4)
7026 (compare:CC (match_dup 0)
7027 (const_int 0)))]
7028 "")
7029
7030 (define_insn "*rotldi3_internal7le"
7031 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7032 (zero_extend:DI
7033 (subreg:QI
7034 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7035 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7036 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7037 "@
7038 rldcl %0,%1,%2,56
7039 rldicl %0,%1,%H2,56"
7040 [(set_attr "type" "var_shift_rotate,integer")])
7041
7042 (define_insn "*rotldi3_internal7be"
7043 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7044 (zero_extend:DI
7045 (subreg:QI
7046 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7047 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
7048 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7049 "@
7050 rldcl %0,%1,%2,56
7051 rldicl %0,%1,%H2,56"
7052 [(set_attr "type" "var_shift_rotate,integer")])
7053
7054 (define_insn "*rotldi3_internal8le"
7055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7056 (compare:CC (zero_extend:DI
7057 (subreg:QI
7058 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7059 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7060 (const_int 0)))
7061 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7062 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7063 "@
7064 rldcl. %3,%1,%2,56
7065 rldicl. %3,%1,%H2,56
7066 #
7067 #"
7068 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7069 (set_attr "length" "4,4,8,8")])
7070
7071 (define_insn "*rotldi3_internal8be"
7072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7073 (compare:CC (zero_extend:DI
7074 (subreg:QI
7075 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7076 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7077 (const_int 0)))
7078 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7079 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7080 "@
7081 rldcl. %3,%1,%2,56
7082 rldicl. %3,%1,%H2,56
7083 #
7084 #"
7085 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7086 (set_attr "length" "4,4,8,8")])
7087
7088 (define_split
7089 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7090 (compare:CC (zero_extend:DI
7091 (subreg:QI
7092 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7093 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7094 (const_int 0)))
7095 (clobber (match_scratch:DI 3 ""))]
7096 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7097 [(set (match_dup 3)
7098 (zero_extend:DI (subreg:QI
7099 (rotate:DI (match_dup 1)
7100 (match_dup 2)) 0)))
7101 (set (match_dup 0)
7102 (compare:CC (match_dup 3)
7103 (const_int 0)))]
7104 "")
7105
7106 (define_split
7107 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7108 (compare:CC (zero_extend:DI
7109 (subreg:QI
7110 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7111 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7112 (const_int 0)))
7113 (clobber (match_scratch:DI 3 ""))]
7114 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7115 [(set (match_dup 3)
7116 (zero_extend:DI (subreg:QI
7117 (rotate:DI (match_dup 1)
7118 (match_dup 2)) 7)))
7119 (set (match_dup 0)
7120 (compare:CC (match_dup 3)
7121 (const_int 0)))]
7122 "")
7123
7124 (define_insn "*rotldi3_internal9le"
7125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7126 (compare:CC (zero_extend:DI
7127 (subreg:QI
7128 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7129 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7130 (const_int 0)))
7131 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7132 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7133 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7134 "@
7135 rldcl. %0,%1,%2,56
7136 rldicl. %0,%1,%H2,56
7137 #
7138 #"
7139 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7140 (set_attr "length" "4,4,8,8")])
7141
7142 (define_insn "*rotldi3_internal9be"
7143 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7144 (compare:CC (zero_extend:DI
7145 (subreg:QI
7146 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7147 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7148 (const_int 0)))
7149 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7150 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7151 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7152 "@
7153 rldcl. %0,%1,%2,56
7154 rldicl. %0,%1,%H2,56
7155 #
7156 #"
7157 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7158 (set_attr "length" "4,4,8,8")])
7159
7160 (define_split
7161 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7162 (compare:CC (zero_extend:DI
7163 (subreg:QI
7164 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7165 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7166 (const_int 0)))
7167 (set (match_operand:DI 0 "gpc_reg_operand" "")
7168 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7169 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7170 [(set (match_dup 0)
7171 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7172 (set (match_dup 3)
7173 (compare:CC (match_dup 0)
7174 (const_int 0)))]
7175 "")
7176
7177 (define_split
7178 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7179 (compare:CC (zero_extend:DI
7180 (subreg:QI
7181 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7182 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7183 (const_int 0)))
7184 (set (match_operand:DI 0 "gpc_reg_operand" "")
7185 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7186 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7187 [(set (match_dup 0)
7188 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7189 (set (match_dup 3)
7190 (compare:CC (match_dup 0)
7191 (const_int 0)))]
7192 "")
7193
7194 (define_insn "*rotldi3_internal10le"
7195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7196 (zero_extend:DI
7197 (subreg:HI
7198 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7199 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7200 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7201 "@
7202 rldcl %0,%1,%2,48
7203 rldicl %0,%1,%H2,48"
7204 [(set_attr "type" "var_shift_rotate,integer")])
7205
7206 (define_insn "*rotldi3_internal10be"
7207 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7208 (zero_extend:DI
7209 (subreg:HI
7210 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7211 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
7212 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7213 "@
7214 rldcl %0,%1,%2,48
7215 rldicl %0,%1,%H2,48"
7216 [(set_attr "type" "var_shift_rotate,integer")])
7217
7218 (define_insn "*rotldi3_internal11le"
7219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7220 (compare:CC (zero_extend:DI
7221 (subreg:HI
7222 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7223 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7224 (const_int 0)))
7225 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7226 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7227 "@
7228 rldcl. %3,%1,%2,48
7229 rldicl. %3,%1,%H2,48
7230 #
7231 #"
7232 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7233 (set_attr "length" "4,4,8,8")])
7234
7235 (define_insn "*rotldi3_internal11be"
7236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7237 (compare:CC (zero_extend:DI
7238 (subreg:HI
7239 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7240 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7241 (const_int 0)))
7242 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7243 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7244 "@
7245 rldcl. %3,%1,%2,48
7246 rldicl. %3,%1,%H2,48
7247 #
7248 #"
7249 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7250 (set_attr "length" "4,4,8,8")])
7251
7252 (define_split
7253 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7254 (compare:CC (zero_extend:DI
7255 (subreg:HI
7256 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7257 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7258 (const_int 0)))
7259 (clobber (match_scratch:DI 3 ""))]
7260 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7261 [(set (match_dup 3)
7262 (zero_extend:DI (subreg:HI
7263 (rotate:DI (match_dup 1)
7264 (match_dup 2)) 0)))
7265 (set (match_dup 0)
7266 (compare:CC (match_dup 3)
7267 (const_int 0)))]
7268 "")
7269
7270 (define_split
7271 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7272 (compare:CC (zero_extend:DI
7273 (subreg:HI
7274 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7275 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7276 (const_int 0)))
7277 (clobber (match_scratch:DI 3 ""))]
7278 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7279 [(set (match_dup 3)
7280 (zero_extend:DI (subreg:HI
7281 (rotate:DI (match_dup 1)
7282 (match_dup 2)) 6)))
7283 (set (match_dup 0)
7284 (compare:CC (match_dup 3)
7285 (const_int 0)))]
7286 "")
7287
7288 (define_insn "*rotldi3_internal12le"
7289 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7290 (compare:CC (zero_extend:DI
7291 (subreg:HI
7292 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7293 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7294 (const_int 0)))
7295 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7296 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7297 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7298 "@
7299 rldcl. %0,%1,%2,48
7300 rldicl. %0,%1,%H2,48
7301 #
7302 #"
7303 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7304 (set_attr "length" "4,4,8,8")])
7305
7306 (define_insn "*rotldi3_internal12be"
7307 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7308 (compare:CC (zero_extend:DI
7309 (subreg:HI
7310 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7311 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7312 (const_int 0)))
7313 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7314 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7315 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7316 "@
7317 rldcl. %0,%1,%2,48
7318 rldicl. %0,%1,%H2,48
7319 #
7320 #"
7321 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7322 (set_attr "length" "4,4,8,8")])
7323
7324 (define_split
7325 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7326 (compare:CC (zero_extend:DI
7327 (subreg:HI
7328 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7329 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7330 (const_int 0)))
7331 (set (match_operand:DI 0 "gpc_reg_operand" "")
7332 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7333 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7334 [(set (match_dup 0)
7335 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7336 (set (match_dup 3)
7337 (compare:CC (match_dup 0)
7338 (const_int 0)))]
7339 "")
7340
7341 (define_split
7342 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7343 (compare:CC (zero_extend:DI
7344 (subreg:HI
7345 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7346 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7347 (const_int 0)))
7348 (set (match_operand:DI 0 "gpc_reg_operand" "")
7349 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7350 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7351 [(set (match_dup 0)
7352 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7353 (set (match_dup 3)
7354 (compare:CC (match_dup 0)
7355 (const_int 0)))]
7356 "")
7357
7358 (define_insn "*rotldi3_internal13le"
7359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7360 (zero_extend:DI
7361 (subreg:SI
7362 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7363 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7364 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7365 "@
7366 rldcl %0,%1,%2,32
7367 rldicl %0,%1,%H2,32"
7368 [(set_attr "type" "var_shift_rotate,integer")])
7369
7370 (define_insn "*rotldi3_internal13be"
7371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7372 (zero_extend:DI
7373 (subreg:SI
7374 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7375 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
7376 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7377 "@
7378 rldcl %0,%1,%2,32
7379 rldicl %0,%1,%H2,32"
7380 [(set_attr "type" "var_shift_rotate,integer")])
7381
7382 (define_insn "*rotldi3_internal14le"
7383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7384 (compare:CC (zero_extend:DI
7385 (subreg:SI
7386 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7387 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7388 (const_int 0)))
7389 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7390 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7391 "@
7392 rldcl. %3,%1,%2,32
7393 rldicl. %3,%1,%H2,32
7394 #
7395 #"
7396 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7397 (set_attr "length" "4,4,8,8")])
7398
7399 (define_insn "*rotldi3_internal14be"
7400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7401 (compare:CC (zero_extend:DI
7402 (subreg:SI
7403 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7404 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7405 (const_int 0)))
7406 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7407 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7408 "@
7409 rldcl. %3,%1,%2,32
7410 rldicl. %3,%1,%H2,32
7411 #
7412 #"
7413 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7414 (set_attr "length" "4,4,8,8")])
7415
7416 (define_split
7417 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7418 (compare:CC (zero_extend:DI
7419 (subreg:SI
7420 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7421 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7422 (const_int 0)))
7423 (clobber (match_scratch:DI 3 ""))]
7424 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7425 [(set (match_dup 3)
7426 (zero_extend:DI (subreg:SI
7427 (rotate:DI (match_dup 1)
7428 (match_dup 2)) 0)))
7429 (set (match_dup 0)
7430 (compare:CC (match_dup 3)
7431 (const_int 0)))]
7432 "")
7433
7434 (define_split
7435 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7436 (compare:CC (zero_extend:DI
7437 (subreg:SI
7438 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7439 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7440 (const_int 0)))
7441 (clobber (match_scratch:DI 3 ""))]
7442 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7443 [(set (match_dup 3)
7444 (zero_extend:DI (subreg:SI
7445 (rotate:DI (match_dup 1)
7446 (match_dup 2)) 4)))
7447 (set (match_dup 0)
7448 (compare:CC (match_dup 3)
7449 (const_int 0)))]
7450 "")
7451
7452 (define_insn "*rotldi3_internal15le"
7453 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7454 (compare:CC (zero_extend:DI
7455 (subreg:SI
7456 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7457 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7458 (const_int 0)))
7459 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7460 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7461 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7462 "@
7463 rldcl. %0,%1,%2,32
7464 rldicl. %0,%1,%H2,32
7465 #
7466 #"
7467 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7468 (set_attr "length" "4,4,8,8")])
7469
7470 (define_insn "*rotldi3_internal15be"
7471 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7472 (compare:CC (zero_extend:DI
7473 (subreg:SI
7474 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7475 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7476 (const_int 0)))
7477 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7478 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7479 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7480 "@
7481 rldcl. %0,%1,%2,32
7482 rldicl. %0,%1,%H2,32
7483 #
7484 #"
7485 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7486 (set_attr "length" "4,4,8,8")])
7487
7488 (define_split
7489 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7490 (compare:CC (zero_extend:DI
7491 (subreg:SI
7492 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7493 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7494 (const_int 0)))
7495 (set (match_operand:DI 0 "gpc_reg_operand" "")
7496 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7497 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7498 [(set (match_dup 0)
7499 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7500 (set (match_dup 3)
7501 (compare:CC (match_dup 0)
7502 (const_int 0)))]
7503 "")
7504
7505 (define_split
7506 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7507 (compare:CC (zero_extend:DI
7508 (subreg:SI
7509 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7510 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7511 (const_int 0)))
7512 (set (match_operand:DI 0 "gpc_reg_operand" "")
7513 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7514 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7515 [(set (match_dup 0)
7516 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7517 (set (match_dup 3)
7518 (compare:CC (match_dup 0)
7519 (const_int 0)))]
7520 "")
7521
7522 (define_expand "ashldi3"
7523 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7524 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7525 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7526 "TARGET_POWERPC64"
7527 "")
7528
7529 (define_insn "*ashldi3_internal1"
7530 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7531 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7532 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7533 "TARGET_POWERPC64"
7534 "@
7535 sld %0,%1,%2
7536 sldi %0,%1,%H2"
7537 [(set_attr "type" "var_shift_rotate,shift")])
7538
7539 (define_insn "*ashldi3_internal2"
7540 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7541 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7542 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7543 (const_int 0)))
7544 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7545 "TARGET_64BIT"
7546 "@
7547 sld. %3,%1,%2
7548 sldi. %3,%1,%H2
7549 #
7550 #"
7551 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7552 (set_attr "length" "4,4,8,8")])
7553
7554 (define_split
7555 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7556 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7557 (match_operand:SI 2 "reg_or_cint_operand" ""))
7558 (const_int 0)))
7559 (clobber (match_scratch:DI 3 ""))]
7560 "TARGET_POWERPC64 && reload_completed"
7561 [(set (match_dup 3)
7562 (ashift:DI (match_dup 1) (match_dup 2)))
7563 (set (match_dup 0)
7564 (compare:CC (match_dup 3)
7565 (const_int 0)))]
7566 "")
7567
7568 (define_insn "*ashldi3_internal3"
7569 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7570 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7571 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7572 (const_int 0)))
7573 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7574 (ashift:DI (match_dup 1) (match_dup 2)))]
7575 "TARGET_64BIT"
7576 "@
7577 sld. %0,%1,%2
7578 sldi. %0,%1,%H2
7579 #
7580 #"
7581 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7582 (set_attr "length" "4,4,8,8")])
7583
7584 (define_split
7585 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7586 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7587 (match_operand:SI 2 "reg_or_cint_operand" ""))
7588 (const_int 0)))
7589 (set (match_operand:DI 0 "gpc_reg_operand" "")
7590 (ashift:DI (match_dup 1) (match_dup 2)))]
7591 "TARGET_POWERPC64 && reload_completed"
7592 [(set (match_dup 0)
7593 (ashift:DI (match_dup 1) (match_dup 2)))
7594 (set (match_dup 3)
7595 (compare:CC (match_dup 0)
7596 (const_int 0)))]
7597 "")
7598
7599 (define_insn "*ashldi3_internal4"
7600 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7601 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7602 (match_operand:SI 2 "const_int_operand" "i"))
7603 (match_operand:DI 3 "const_int_operand" "n")))]
7604 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7605 "rldic %0,%1,%H2,%W3")
7606
7607 (define_insn "ashldi3_internal5"
7608 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7609 (compare:CC
7610 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7611 (match_operand:SI 2 "const_int_operand" "i,i"))
7612 (match_operand:DI 3 "const_int_operand" "n,n"))
7613 (const_int 0)))
7614 (clobber (match_scratch:DI 4 "=r,r"))]
7615 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7616 "@
7617 rldic. %4,%1,%H2,%W3
7618 #"
7619 [(set_attr "type" "compare")
7620 (set_attr "length" "4,8")])
7621
7622 (define_split
7623 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7624 (compare:CC
7625 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7626 (match_operand:SI 2 "const_int_operand" ""))
7627 (match_operand:DI 3 "const_int_operand" ""))
7628 (const_int 0)))
7629 (clobber (match_scratch:DI 4 ""))]
7630 "TARGET_POWERPC64 && reload_completed
7631 && includes_rldic_lshift_p (operands[2], operands[3])"
7632 [(set (match_dup 4)
7633 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7634 (match_dup 3)))
7635 (set (match_dup 0)
7636 (compare:CC (match_dup 4)
7637 (const_int 0)))]
7638 "")
7639
7640 (define_insn "*ashldi3_internal6"
7641 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7642 (compare:CC
7643 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7644 (match_operand:SI 2 "const_int_operand" "i,i"))
7645 (match_operand:DI 3 "const_int_operand" "n,n"))
7646 (const_int 0)))
7647 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7648 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7649 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7650 "@
7651 rldic. %0,%1,%H2,%W3
7652 #"
7653 [(set_attr "type" "compare")
7654 (set_attr "length" "4,8")])
7655
7656 (define_split
7657 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7658 (compare:CC
7659 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7660 (match_operand:SI 2 "const_int_operand" ""))
7661 (match_operand:DI 3 "const_int_operand" ""))
7662 (const_int 0)))
7663 (set (match_operand:DI 0 "gpc_reg_operand" "")
7664 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7665 "TARGET_POWERPC64 && reload_completed
7666 && includes_rldic_lshift_p (operands[2], operands[3])"
7667 [(set (match_dup 0)
7668 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7669 (match_dup 3)))
7670 (set (match_dup 4)
7671 (compare:CC (match_dup 0)
7672 (const_int 0)))]
7673 "")
7674
7675 (define_insn "*ashldi3_internal7"
7676 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7677 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7678 (match_operand:SI 2 "const_int_operand" "i"))
7679 (match_operand:DI 3 "mask64_operand" "n")))]
7680 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7681 "rldicr %0,%1,%H2,%S3")
7682
7683 (define_insn "ashldi3_internal8"
7684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7685 (compare:CC
7686 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7687 (match_operand:SI 2 "const_int_operand" "i,i"))
7688 (match_operand:DI 3 "mask64_operand" "n,n"))
7689 (const_int 0)))
7690 (clobber (match_scratch:DI 4 "=r,r"))]
7691 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7692 "@
7693 rldicr. %4,%1,%H2,%S3
7694 #"
7695 [(set_attr "type" "compare")
7696 (set_attr "length" "4,8")])
7697
7698 (define_split
7699 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7700 (compare:CC
7701 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7702 (match_operand:SI 2 "const_int_operand" ""))
7703 (match_operand:DI 3 "mask64_operand" ""))
7704 (const_int 0)))
7705 (clobber (match_scratch:DI 4 ""))]
7706 "TARGET_POWERPC64 && reload_completed
7707 && includes_rldicr_lshift_p (operands[2], operands[3])"
7708 [(set (match_dup 4)
7709 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7710 (match_dup 3)))
7711 (set (match_dup 0)
7712 (compare:CC (match_dup 4)
7713 (const_int 0)))]
7714 "")
7715
7716 (define_insn "*ashldi3_internal9"
7717 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7718 (compare:CC
7719 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7720 (match_operand:SI 2 "const_int_operand" "i,i"))
7721 (match_operand:DI 3 "mask64_operand" "n,n"))
7722 (const_int 0)))
7723 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7724 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7725 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7726 "@
7727 rldicr. %0,%1,%H2,%S3
7728 #"
7729 [(set_attr "type" "compare")
7730 (set_attr "length" "4,8")])
7731
7732 (define_split
7733 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7734 (compare:CC
7735 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7736 (match_operand:SI 2 "const_int_operand" ""))
7737 (match_operand:DI 3 "mask64_operand" ""))
7738 (const_int 0)))
7739 (set (match_operand:DI 0 "gpc_reg_operand" "")
7740 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7741 "TARGET_POWERPC64 && reload_completed
7742 && includes_rldicr_lshift_p (operands[2], operands[3])"
7743 [(set (match_dup 0)
7744 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7745 (match_dup 3)))
7746 (set (match_dup 4)
7747 (compare:CC (match_dup 0)
7748 (const_int 0)))]
7749 "")
7750
7751 (define_expand "lshrdi3"
7752 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7753 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7754 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7755 "TARGET_POWERPC64"
7756 "")
7757
7758 (define_insn "*lshrdi3_internal1"
7759 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7760 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7761 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7762 "TARGET_POWERPC64"
7763 "@
7764 srd %0,%1,%2
7765 srdi %0,%1,%H2"
7766 [(set_attr "type" "var_shift_rotate,shift")])
7767
7768 (define_insn "*lshrdi3_internal2"
7769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7770 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7771 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7772 (const_int 0)))
7773 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7774 "TARGET_64BIT "
7775 "@
7776 srd. %3,%1,%2
7777 srdi. %3,%1,%H2
7778 #
7779 #"
7780 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7781 (set_attr "length" "4,4,8,8")])
7782
7783 (define_split
7784 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7785 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7786 (match_operand:SI 2 "reg_or_cint_operand" ""))
7787 (const_int 0)))
7788 (clobber (match_scratch:DI 3 ""))]
7789 "TARGET_POWERPC64 && reload_completed"
7790 [(set (match_dup 3)
7791 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7792 (set (match_dup 0)
7793 (compare:CC (match_dup 3)
7794 (const_int 0)))]
7795 "")
7796
7797 (define_insn "*lshrdi3_internal3"
7798 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7799 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7800 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7801 (const_int 0)))
7802 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7803 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7804 "TARGET_64BIT"
7805 "@
7806 srd. %0,%1,%2
7807 srdi. %0,%1,%H2
7808 #
7809 #"
7810 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7811 (set_attr "length" "4,4,8,8")])
7812
7813 (define_split
7814 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7815 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7816 (match_operand:SI 2 "reg_or_cint_operand" ""))
7817 (const_int 0)))
7818 (set (match_operand:DI 0 "gpc_reg_operand" "")
7819 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7820 "TARGET_POWERPC64 && reload_completed"
7821 [(set (match_dup 0)
7822 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7823 (set (match_dup 3)
7824 (compare:CC (match_dup 0)
7825 (const_int 0)))]
7826 "")
7827
7828 (define_expand "ashrdi3"
7829 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7830 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7831 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7832 ""
7833 "
7834 {
7835 if (TARGET_POWERPC64)
7836 ;
7837 else if (GET_CODE (operands[2]) == CONST_INT)
7838 {
7839 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7840 DONE;
7841 }
7842 else
7843 FAIL;
7844 }")
7845
7846 (define_insn "*ashrdi3_internal1"
7847 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7848 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7849 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7850 "TARGET_POWERPC64"
7851 "@
7852 srad %0,%1,%2
7853 sradi %0,%1,%H2"
7854 [(set_attr "type" "var_shift_rotate,shift")])
7855
7856 (define_insn "*ashrdi3_internal2"
7857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7858 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7859 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7860 (const_int 0)))
7861 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7862 "TARGET_64BIT"
7863 "@
7864 srad. %3,%1,%2
7865 sradi. %3,%1,%H2
7866 #
7867 #"
7868 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7869 (set_attr "length" "4,4,8,8")])
7870
7871 (define_split
7872 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7873 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7874 (match_operand:SI 2 "reg_or_cint_operand" ""))
7875 (const_int 0)))
7876 (clobber (match_scratch:DI 3 ""))]
7877 "TARGET_POWERPC64 && reload_completed"
7878 [(set (match_dup 3)
7879 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7880 (set (match_dup 0)
7881 (compare:CC (match_dup 3)
7882 (const_int 0)))]
7883 "")
7884
7885 (define_insn "*ashrdi3_internal3"
7886 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7887 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7888 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7889 (const_int 0)))
7890 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7891 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7892 "TARGET_64BIT"
7893 "@
7894 srad. %0,%1,%2
7895 sradi. %0,%1,%H2
7896 #
7897 #"
7898 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7899 (set_attr "length" "4,4,8,8")])
7900
7901 (define_split
7902 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7903 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7904 (match_operand:SI 2 "reg_or_cint_operand" ""))
7905 (const_int 0)))
7906 (set (match_operand:DI 0 "gpc_reg_operand" "")
7907 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7908 "TARGET_POWERPC64 && reload_completed"
7909 [(set (match_dup 0)
7910 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7911 (set (match_dup 3)
7912 (compare:CC (match_dup 0)
7913 (const_int 0)))]
7914 "")
7915
7916 (define_expand "anddi3"
7917 [(parallel
7918 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7919 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7920 (match_operand:DI 2 "and64_2_operand" "")))
7921 (clobber (match_scratch:CC 3 ""))])]
7922 "TARGET_POWERPC64"
7923 "")
7924
7925 (define_insn "anddi3_mc"
7926 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7927 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7928 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7929 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7930 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7931 "@
7932 and %0,%1,%2
7933 rldic%B2 %0,%1,0,%S2
7934 rlwinm %0,%1,0,%m2,%M2
7935 andi. %0,%1,%b2
7936 andis. %0,%1,%u2
7937 #"
7938 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7939 (set_attr "length" "4,4,4,4,4,8")])
7940
7941 (define_insn "anddi3_nomc"
7942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7943 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7944 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7945 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7946 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7947 "@
7948 and %0,%1,%2
7949 rldic%B2 %0,%1,0,%S2
7950 rlwinm %0,%1,0,%m2,%M2
7951 #"
7952 [(set_attr "length" "4,4,4,8")])
7953
7954 (define_split
7955 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7956 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7957 (match_operand:DI 2 "mask64_2_operand" "")))
7958 (clobber (match_scratch:CC 3 ""))]
7959 "TARGET_POWERPC64
7960 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7961 && !mask_operand (operands[2], DImode)
7962 && !mask64_operand (operands[2], DImode)"
7963 [(set (match_dup 0)
7964 (and:DI (rotate:DI (match_dup 1)
7965 (match_dup 4))
7966 (match_dup 5)))
7967 (set (match_dup 0)
7968 (and:DI (rotate:DI (match_dup 0)
7969 (match_dup 6))
7970 (match_dup 7)))]
7971 {
7972 build_mask64_2_operands (operands[2], &operands[4]);
7973 })
7974
7975 (define_insn "*anddi3_internal2_mc"
7976 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7977 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7978 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7979 (const_int 0)))
7980 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7981 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7982 "TARGET_64BIT && rs6000_gen_cell_microcode"
7983 "@
7984 and. %3,%1,%2
7985 rldic%B2. %3,%1,0,%S2
7986 rlwinm. %3,%1,0,%m2,%M2
7987 andi. %3,%1,%b2
7988 andis. %3,%1,%u2
7989 #
7990 #
7991 #
7992 #
7993 #
7994 #
7995 #"
7996 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7997 fast_compare,compare,compare,compare,compare,compare,\
7998 compare,compare")
7999 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8000
8001 (define_split
8002 [(set (match_operand:CC 0 "cc_reg_operand" "")
8003 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8004 (match_operand:DI 2 "mask64_2_operand" ""))
8005 (const_int 0)))
8006 (clobber (match_scratch:DI 3 ""))
8007 (clobber (match_scratch:CC 4 ""))]
8008 "TARGET_64BIT && reload_completed
8009 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8010 && !mask_operand (operands[2], DImode)
8011 && !mask64_operand (operands[2], DImode)"
8012 [(set (match_dup 3)
8013 (and:DI (rotate:DI (match_dup 1)
8014 (match_dup 5))
8015 (match_dup 6)))
8016 (parallel [(set (match_dup 0)
8017 (compare:CC (and:DI (rotate:DI (match_dup 3)
8018 (match_dup 7))
8019 (match_dup 8))
8020 (const_int 0)))
8021 (clobber (match_dup 3))])]
8022 "
8023 {
8024 build_mask64_2_operands (operands[2], &operands[5]);
8025 }")
8026
8027 (define_insn "*anddi3_internal3_mc"
8028 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8029 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8030 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8031 (const_int 0)))
8032 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8033 (and:DI (match_dup 1) (match_dup 2)))
8034 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8035 "TARGET_64BIT && rs6000_gen_cell_microcode"
8036 "@
8037 and. %0,%1,%2
8038 rldic%B2. %0,%1,0,%S2
8039 rlwinm. %0,%1,0,%m2,%M2
8040 andi. %0,%1,%b2
8041 andis. %0,%1,%u2
8042 #
8043 #
8044 #
8045 #
8046 #
8047 #
8048 #"
8049 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8050 fast_compare,compare,compare,compare,compare,compare,\
8051 compare,compare")
8052 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8053
8054 (define_split
8055 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8056 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8057 (match_operand:DI 2 "and64_2_operand" ""))
8058 (const_int 0)))
8059 (set (match_operand:DI 0 "gpc_reg_operand" "")
8060 (and:DI (match_dup 1) (match_dup 2)))
8061 (clobber (match_scratch:CC 4 ""))]
8062 "TARGET_64BIT && reload_completed"
8063 [(parallel [(set (match_dup 0)
8064 (and:DI (match_dup 1) (match_dup 2)))
8065 (clobber (match_dup 4))])
8066 (set (match_dup 3)
8067 (compare:CC (match_dup 0)
8068 (const_int 0)))]
8069 "")
8070
8071 (define_split
8072 [(set (match_operand:CC 3 "cc_reg_operand" "")
8073 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8074 (match_operand:DI 2 "mask64_2_operand" ""))
8075 (const_int 0)))
8076 (set (match_operand:DI 0 "gpc_reg_operand" "")
8077 (and:DI (match_dup 1) (match_dup 2)))
8078 (clobber (match_scratch:CC 4 ""))]
8079 "TARGET_64BIT && reload_completed
8080 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8081 && !mask_operand (operands[2], DImode)
8082 && !mask64_operand (operands[2], DImode)"
8083 [(set (match_dup 0)
8084 (and:DI (rotate:DI (match_dup 1)
8085 (match_dup 5))
8086 (match_dup 6)))
8087 (parallel [(set (match_dup 3)
8088 (compare:CC (and:DI (rotate:DI (match_dup 0)
8089 (match_dup 7))
8090 (match_dup 8))
8091 (const_int 0)))
8092 (set (match_dup 0)
8093 (and:DI (rotate:DI (match_dup 0)
8094 (match_dup 7))
8095 (match_dup 8)))])]
8096 "
8097 {
8098 build_mask64_2_operands (operands[2], &operands[5]);
8099 }")
8100
8101 (define_expand "iordi3"
8102 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8103 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8104 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8105 "TARGET_POWERPC64"
8106 "
8107 {
8108 if (non_logical_cint_operand (operands[2], DImode))
8109 {
8110 HOST_WIDE_INT value;
8111 rtx tmp = ((!can_create_pseudo_p ()
8112 || rtx_equal_p (operands[0], operands[1]))
8113 ? operands[0] : gen_reg_rtx (DImode));
8114
8115 value = INTVAL (operands[2]);
8116 emit_insn (gen_iordi3 (tmp, operands[1],
8117 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8118
8119 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8120 DONE;
8121 }
8122 }")
8123
8124 (define_expand "xordi3"
8125 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8126 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8127 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8128 "TARGET_POWERPC64"
8129 "
8130 {
8131 if (non_logical_cint_operand (operands[2], DImode))
8132 {
8133 HOST_WIDE_INT value;
8134 rtx tmp = ((!can_create_pseudo_p ()
8135 || rtx_equal_p (operands[0], operands[1]))
8136 ? operands[0] : gen_reg_rtx (DImode));
8137
8138 value = INTVAL (operands[2]);
8139 emit_insn (gen_xordi3 (tmp, operands[1],
8140 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8141
8142 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8143 DONE;
8144 }
8145 }")
8146
8147 (define_insn "*booldi3_internal1"
8148 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8149 (match_operator:DI 3 "boolean_or_operator"
8150 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8151 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8152 "TARGET_POWERPC64"
8153 "@
8154 %q3 %0,%1,%2
8155 %q3i %0,%1,%b2
8156 %q3is %0,%1,%u2")
8157
8158 (define_insn "*booldi3_internal2"
8159 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8160 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8161 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8162 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8163 (const_int 0)))
8164 (clobber (match_scratch:DI 3 "=r,r"))]
8165 "TARGET_64BIT"
8166 "@
8167 %q4. %3,%1,%2
8168 #"
8169 [(set_attr "type" "fast_compare,compare")
8170 (set_attr "length" "4,8")])
8171
8172 (define_split
8173 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8174 (compare:CC (match_operator:DI 4 "boolean_operator"
8175 [(match_operand:DI 1 "gpc_reg_operand" "")
8176 (match_operand:DI 2 "gpc_reg_operand" "")])
8177 (const_int 0)))
8178 (clobber (match_scratch:DI 3 ""))]
8179 "TARGET_POWERPC64 && reload_completed"
8180 [(set (match_dup 3) (match_dup 4))
8181 (set (match_dup 0)
8182 (compare:CC (match_dup 3)
8183 (const_int 0)))]
8184 "")
8185
8186 (define_insn "*booldi3_internal3"
8187 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8188 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8189 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8190 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8191 (const_int 0)))
8192 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8193 (match_dup 4))]
8194 "TARGET_64BIT"
8195 "@
8196 %q4. %0,%1,%2
8197 #"
8198 [(set_attr "type" "fast_compare,compare")
8199 (set_attr "length" "4,8")])
8200
8201 (define_split
8202 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8203 (compare:CC (match_operator:DI 4 "boolean_operator"
8204 [(match_operand:DI 1 "gpc_reg_operand" "")
8205 (match_operand:DI 2 "gpc_reg_operand" "")])
8206 (const_int 0)))
8207 (set (match_operand:DI 0 "gpc_reg_operand" "")
8208 (match_dup 4))]
8209 "TARGET_POWERPC64 && reload_completed"
8210 [(set (match_dup 0) (match_dup 4))
8211 (set (match_dup 3)
8212 (compare:CC (match_dup 0)
8213 (const_int 0)))]
8214 "")
8215
8216 ;; Split a logical operation that we can't do in one insn into two insns,
8217 ;; each of which does one 16-bit part. This is used by combine.
8218
8219 (define_split
8220 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8221 (match_operator:DI 3 "boolean_or_operator"
8222 [(match_operand:DI 1 "gpc_reg_operand" "")
8223 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8224 "TARGET_POWERPC64"
8225 [(set (match_dup 0) (match_dup 4))
8226 (set (match_dup 0) (match_dup 5))]
8227 "
8228 {
8229 rtx i3,i4;
8230
8231 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
8232 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8233 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8234 operands[1], i3);
8235 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8236 operands[0], i4);
8237 }")
8238
8239 (define_insn "*boolcdi3_internal1"
8240 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8241 (match_operator:DI 3 "boolean_operator"
8242 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8243 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8244 "TARGET_POWERPC64"
8245 "%q3 %0,%2,%1")
8246
8247 (define_insn "*boolcdi3_internal2"
8248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8249 (compare:CC (match_operator:DI 4 "boolean_operator"
8250 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8251 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8252 (const_int 0)))
8253 (clobber (match_scratch:DI 3 "=r,r"))]
8254 "TARGET_64BIT"
8255 "@
8256 %q4. %3,%2,%1
8257 #"
8258 [(set_attr "type" "fast_compare,compare")
8259 (set_attr "length" "4,8")])
8260
8261 (define_split
8262 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8263 (compare:CC (match_operator:DI 4 "boolean_operator"
8264 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8265 (match_operand:DI 2 "gpc_reg_operand" "")])
8266 (const_int 0)))
8267 (clobber (match_scratch:DI 3 ""))]
8268 "TARGET_POWERPC64 && reload_completed"
8269 [(set (match_dup 3) (match_dup 4))
8270 (set (match_dup 0)
8271 (compare:CC (match_dup 3)
8272 (const_int 0)))]
8273 "")
8274
8275 (define_insn "*boolcdi3_internal3"
8276 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8277 (compare:CC (match_operator:DI 4 "boolean_operator"
8278 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8279 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8280 (const_int 0)))
8281 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8282 (match_dup 4))]
8283 "TARGET_64BIT"
8284 "@
8285 %q4. %0,%2,%1
8286 #"
8287 [(set_attr "type" "fast_compare,compare")
8288 (set_attr "length" "4,8")])
8289
8290 (define_split
8291 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8292 (compare:CC (match_operator:DI 4 "boolean_operator"
8293 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8294 (match_operand:DI 2 "gpc_reg_operand" "")])
8295 (const_int 0)))
8296 (set (match_operand:DI 0 "gpc_reg_operand" "")
8297 (match_dup 4))]
8298 "TARGET_POWERPC64 && reload_completed"
8299 [(set (match_dup 0) (match_dup 4))
8300 (set (match_dup 3)
8301 (compare:CC (match_dup 0)
8302 (const_int 0)))]
8303 "")
8304
8305 (define_insn "*boolccdi3_internal1"
8306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8307 (match_operator:DI 3 "boolean_operator"
8308 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8309 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8310 "TARGET_POWERPC64"
8311 "%q3 %0,%1,%2")
8312
8313 (define_insn "*boolccdi3_internal2"
8314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8315 (compare:CC (match_operator:DI 4 "boolean_operator"
8316 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8317 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8318 (const_int 0)))
8319 (clobber (match_scratch:DI 3 "=r,r"))]
8320 "TARGET_64BIT"
8321 "@
8322 %q4. %3,%1,%2
8323 #"
8324 [(set_attr "type" "fast_compare,compare")
8325 (set_attr "length" "4,8")])
8326
8327 (define_split
8328 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8329 (compare:CC (match_operator:DI 4 "boolean_operator"
8330 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8331 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8332 (const_int 0)))
8333 (clobber (match_scratch:DI 3 ""))]
8334 "TARGET_POWERPC64 && reload_completed"
8335 [(set (match_dup 3) (match_dup 4))
8336 (set (match_dup 0)
8337 (compare:CC (match_dup 3)
8338 (const_int 0)))]
8339 "")
8340
8341 (define_insn "*boolccdi3_internal3"
8342 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8343 (compare:CC (match_operator:DI 4 "boolean_operator"
8344 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8345 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8346 (const_int 0)))
8347 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8348 (match_dup 4))]
8349 "TARGET_64BIT"
8350 "@
8351 %q4. %0,%1,%2
8352 #"
8353 [(set_attr "type" "fast_compare,compare")
8354 (set_attr "length" "4,8")])
8355
8356 (define_split
8357 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8358 (compare:CC (match_operator:DI 4 "boolean_operator"
8359 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8360 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8361 (const_int 0)))
8362 (set (match_operand:DI 0 "gpc_reg_operand" "")
8363 (match_dup 4))]
8364 "TARGET_POWERPC64 && reload_completed"
8365 [(set (match_dup 0) (match_dup 4))
8366 (set (match_dup 3)
8367 (compare:CC (match_dup 0)
8368 (const_int 0)))]
8369 "")
8370
8371 ;; Eqv operation.
8372 (define_insn "*eqv<mode>3"
8373 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
8374 (not:GPR
8375 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
8376 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
8377 ""
8378 "eqv %0,%1,%2"
8379 [(set_attr "type" "integer")
8380 (set_attr "length" "4")])
8381
8382 \f
8383 ;; Now define ways of moving data around.
8384
8385 ;; Set up a register with a value from the GOT table
8386
8387 (define_expand "movsi_got"
8388 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8389 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8390 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8391 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8392 "
8393 {
8394 if (GET_CODE (operands[1]) == CONST)
8395 {
8396 rtx offset = const0_rtx;
8397 HOST_WIDE_INT value;
8398
8399 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8400 value = INTVAL (offset);
8401 if (value != 0)
8402 {
8403 rtx tmp = (!can_create_pseudo_p ()
8404 ? operands[0]
8405 : gen_reg_rtx (Pmode));
8406 emit_insn (gen_movsi_got (tmp, operands[1]));
8407 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8408 DONE;
8409 }
8410 }
8411
8412 operands[2] = rs6000_got_register (operands[1]);
8413 }")
8414
8415 (define_insn "*movsi_got_internal"
8416 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8417 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8418 (match_operand:SI 2 "gpc_reg_operand" "b")]
8419 UNSPEC_MOVSI_GOT))]
8420 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8421 "lwz %0,%a1@got(%2)"
8422 [(set_attr "type" "load")])
8423
8424 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8425 ;; didn't get allocated to a hard register.
8426 (define_split
8427 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8428 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8429 (match_operand:SI 2 "memory_operand" "")]
8430 UNSPEC_MOVSI_GOT))]
8431 "DEFAULT_ABI == ABI_V4
8432 && flag_pic == 1
8433 && (reload_in_progress || reload_completed)"
8434 [(set (match_dup 0) (match_dup 2))
8435 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8436 UNSPEC_MOVSI_GOT))]
8437 "")
8438
8439 ;; For SI, we special-case integers that can't be loaded in one insn. We
8440 ;; do the load 16-bits at a time. We could do this by loading from memory,
8441 ;; and this is even supposed to be faster, but it is simpler not to get
8442 ;; integers in the TOC.
8443 (define_insn "movsi_low"
8444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8445 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8446 (match_operand 2 "" ""))))]
8447 "TARGET_MACHO && ! TARGET_64BIT"
8448 "lwz %0,lo16(%2)(%1)"
8449 [(set_attr "type" "load")
8450 (set_attr "length" "4")])
8451
8452 (define_insn "*movsi_internal1"
8453 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8454 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8455 "!TARGET_SINGLE_FPU &&
8456 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8457 "@
8458 mr %0,%1
8459 la %0,%a1
8460 lwz%U1%X1 %0,%1
8461 stw%U0%X0 %1,%0
8462 li %0,%1
8463 lis %0,%v1
8464 #
8465 mf%1 %0
8466 mt%0 %1
8467 mt%0 %1
8468 nop"
8469 [(set_attr_alternative "type"
8470 [(const_string "*")
8471 (const_string "*")
8472 (if_then_else
8473 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8474 (const_string "load_ux")
8475 (if_then_else
8476 (match_test "update_address_mem (operands[1], VOIDmode)")
8477 (const_string "load_u")
8478 (const_string "load")))
8479 (if_then_else
8480 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8481 (const_string "store_ux")
8482 (if_then_else
8483 (match_test "update_address_mem (operands[0], VOIDmode)")
8484 (const_string "store_u")
8485 (const_string "store")))
8486 (const_string "*")
8487 (const_string "*")
8488 (const_string "*")
8489 (const_string "mfjmpr")
8490 (const_string "mtjmpr")
8491 (const_string "*")
8492 (const_string "*")])
8493
8494 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8495
8496 (define_insn "*movsi_internal1_single"
8497 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8498 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8499 "TARGET_SINGLE_FPU &&
8500 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8501 "@
8502 mr %0,%1
8503 la %0,%a1
8504 lwz%U1%X1 %0,%1
8505 stw%U0%X0 %1,%0
8506 li %0,%1
8507 lis %0,%v1
8508 #
8509 mf%1 %0
8510 mt%0 %1
8511 mt%0 %1
8512 nop
8513 stfs%U0%X0 %1,%0
8514 lfs%U1%X1 %0,%1"
8515 [(set_attr_alternative "type"
8516 [(const_string "*")
8517 (const_string "*")
8518 (if_then_else
8519 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8520 (const_string "load_ux")
8521 (if_then_else
8522 (match_test "update_address_mem (operands[1], VOIDmode)")
8523 (const_string "load_u")
8524 (const_string "load")))
8525 (if_then_else
8526 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8527 (const_string "store_ux")
8528 (if_then_else
8529 (match_test "update_address_mem (operands[0], VOIDmode)")
8530 (const_string "store_u")
8531 (const_string "store")))
8532 (const_string "*")
8533 (const_string "*")
8534 (const_string "*")
8535 (const_string "mfjmpr")
8536 (const_string "mtjmpr")
8537 (const_string "*")
8538 (const_string "*")
8539 (if_then_else
8540 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8541 (const_string "fpstore_ux")
8542 (if_then_else
8543 (match_test "update_address_mem (operands[0], VOIDmode)")
8544 (const_string "fpstore_u")
8545 (const_string "fpstore")))
8546 (if_then_else
8547 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8548 (const_string "fpload_ux")
8549 (if_then_else
8550 (match_test "update_address_mem (operands[1], VOIDmode)")
8551 (const_string "fpload_u")
8552 (const_string "fpload")))])
8553 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8554
8555 ;; Split a load of a large constant into the appropriate two-insn
8556 ;; sequence.
8557
8558 (define_split
8559 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8560 (match_operand:SI 1 "const_int_operand" ""))]
8561 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8562 && (INTVAL (operands[1]) & 0xffff) != 0"
8563 [(set (match_dup 0)
8564 (match_dup 2))
8565 (set (match_dup 0)
8566 (ior:SI (match_dup 0)
8567 (match_dup 3)))]
8568 "
8569 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8570
8571 if (tem == operands[0])
8572 DONE;
8573 else
8574 FAIL;
8575 }")
8576
8577 (define_insn "*mov<mode>_internal2"
8578 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8579 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8580 (const_int 0)))
8581 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8582 ""
8583 "@
8584 cmp<wd>i %2,%0,0
8585 mr. %0,%1
8586 #"
8587 [(set_attr "type" "cmp,fast_compare,cmp")
8588 (set_attr "length" "4,4,8")])
8589
8590 (define_split
8591 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8592 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8593 (const_int 0)))
8594 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8595 "reload_completed"
8596 [(set (match_dup 0) (match_dup 1))
8597 (set (match_dup 2)
8598 (compare:CC (match_dup 0)
8599 (const_int 0)))]
8600 "")
8601 \f
8602 (define_insn "*movhi_internal"
8603 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8604 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8605 "gpc_reg_operand (operands[0], HImode)
8606 || gpc_reg_operand (operands[1], HImode)"
8607 "@
8608 mr %0,%1
8609 lhz%U1%X1 %0,%1
8610 sth%U0%X0 %1,%0
8611 li %0,%w1
8612 mf%1 %0
8613 mt%0 %1
8614 nop"
8615 [(set_attr_alternative "type"
8616 [(const_string "*")
8617 (if_then_else
8618 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8619 (const_string "load_ux")
8620 (if_then_else
8621 (match_test "update_address_mem (operands[1], VOIDmode)")
8622 (const_string "load_u")
8623 (const_string "load")))
8624 (if_then_else
8625 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8626 (const_string "store_ux")
8627 (if_then_else
8628 (match_test "update_address_mem (operands[0], VOIDmode)")
8629 (const_string "store_u")
8630 (const_string "store")))
8631 (const_string "*")
8632 (const_string "mfjmpr")
8633 (const_string "mtjmpr")
8634 (const_string "*")])])
8635
8636 (define_expand "mov<mode>"
8637 [(set (match_operand:INT 0 "general_operand" "")
8638 (match_operand:INT 1 "any_operand" ""))]
8639 ""
8640 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8641
8642 (define_insn "*movqi_internal"
8643 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8644 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8645 "gpc_reg_operand (operands[0], QImode)
8646 || gpc_reg_operand (operands[1], QImode)"
8647 "@
8648 mr %0,%1
8649 lbz%U1%X1 %0,%1
8650 stb%U0%X0 %1,%0
8651 li %0,%1
8652 mf%1 %0
8653 mt%0 %1
8654 nop"
8655 [(set_attr_alternative "type"
8656 [(const_string "*")
8657 (if_then_else
8658 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8659 (const_string "load_ux")
8660 (if_then_else
8661 (match_test "update_address_mem (operands[1], VOIDmode)")
8662 (const_string "load_u")
8663 (const_string "load")))
8664 (if_then_else
8665 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8666 (const_string "store_ux")
8667 (if_then_else
8668 (match_test "update_address_mem (operands[0], VOIDmode)")
8669 (const_string "store_u")
8670 (const_string "store")))
8671 (const_string "*")
8672 (const_string "mfjmpr")
8673 (const_string "mtjmpr")
8674 (const_string "*")])])
8675 \f
8676 ;; Here is how to move condition codes around. When we store CC data in
8677 ;; an integer register or memory, we store just the high-order 4 bits.
8678 ;; This lets us not shift in the most common case of CR0.
8679 (define_expand "movcc"
8680 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8681 (match_operand:CC 1 "nonimmediate_operand" ""))]
8682 ""
8683 "")
8684
8685 (define_insn "*movcc_internal1"
8686 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
8687 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
8688 "register_operand (operands[0], CCmode)
8689 || register_operand (operands[1], CCmode)"
8690 "@
8691 mcrf %0,%1
8692 mtcrf 128,%1
8693 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
8694 crxor %0,%0,%0
8695 mfcr %0%Q1
8696 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
8697 mr %0,%1
8698 li %0,%1
8699 mf%1 %0
8700 mt%0 %1
8701 lwz%U1%X1 %0,%1
8702 stw%U0%X0 %1,%0"
8703 [(set (attr "type")
8704 (cond [(eq_attr "alternative" "0,3")
8705 (const_string "cr_logical")
8706 (eq_attr "alternative" "1,2")
8707 (const_string "mtcr")
8708 (eq_attr "alternative" "6,7")
8709 (const_string "integer")
8710 (eq_attr "alternative" "8")
8711 (const_string "mfjmpr")
8712 (eq_attr "alternative" "9")
8713 (const_string "mtjmpr")
8714 (eq_attr "alternative" "10")
8715 (if_then_else
8716 (match_test "update_indexed_address_mem (operands[1],
8717 VOIDmode)")
8718 (const_string "load_ux")
8719 (if_then_else
8720 (match_test "update_address_mem (operands[1], VOIDmode)")
8721 (const_string "load_u")
8722 (const_string "load")))
8723 (eq_attr "alternative" "11")
8724 (if_then_else
8725 (match_test "update_indexed_address_mem (operands[0],
8726 VOIDmode)")
8727 (const_string "store_ux")
8728 (if_then_else
8729 (match_test "update_address_mem (operands[0], VOIDmode)")
8730 (const_string "store_u")
8731 (const_string "store")))
8732 (match_test "TARGET_MFCRF")
8733 (const_string "mfcrf")
8734 ]
8735 (const_string "mfcr")))
8736 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
8737 \f
8738 ;; For floating-point, we normally deal with the floating-point registers
8739 ;; unless -msoft-float is used. The sole exception is that parameter passing
8740 ;; can produce floating-point values in fixed-point registers. Unless the
8741 ;; value is a simple constant or already in memory, we deal with this by
8742 ;; allocating memory and copying the value explicitly via that memory location.
8743
8744 ;; Move 32-bit binary/decimal floating point
8745 (define_expand "mov<mode>"
8746 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
8747 (match_operand:FMOVE32 1 "any_operand" ""))]
8748 "<fmove_ok>"
8749 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8750
8751 (define_split
8752 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
8753 (match_operand:FMOVE32 1 "const_double_operand" ""))]
8754 "reload_completed
8755 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8756 || (GET_CODE (operands[0]) == SUBREG
8757 && GET_CODE (SUBREG_REG (operands[0])) == REG
8758 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8759 [(set (match_dup 2) (match_dup 3))]
8760 "
8761 {
8762 long l;
8763 REAL_VALUE_TYPE rv;
8764
8765 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8766 <real_value_to_target> (rv, l);
8767
8768 if (! TARGET_POWERPC64)
8769 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
8770 else
8771 operands[2] = gen_lowpart (SImode, operands[0]);
8772
8773 operands[3] = gen_int_mode (l, SImode);
8774 }")
8775
8776 (define_insn "mov<mode>_hardfloat"
8777 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wm,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
8778 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wm,r,<f32_dm>,r,h,0,G,Fn"))]
8779 "(gpc_reg_operand (operands[0], <MODE>mode)
8780 || gpc_reg_operand (operands[1], <MODE>mode))
8781 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8782 "@
8783 mr %0,%1
8784 lwz%U1%X1 %0,%1
8785 stw%U0%X0 %1,%0
8786 fmr %0,%1
8787 xxlor %x0,%x1,%x1
8788 xxlxor %x0,%x0,%x0
8789 <f32_li>
8790 <f32_si>
8791 <f32_lv>
8792 <f32_sv>
8793 mtvsrwz %x0,%1
8794 mfvsrwz %0,%x1
8795 mt%0 %1
8796 mf%1 %0
8797 nop
8798 #
8799 #"
8800 [(set_attr_alternative "type"
8801 [(const_string "*")
8802 (if_then_else
8803 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8804 (const_string "load_ux")
8805 (if_then_else
8806 (match_test "update_address_mem (operands[1], VOIDmode)")
8807 (const_string "load_u")
8808 (const_string "load")))
8809 (if_then_else
8810 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8811 (const_string "store_ux")
8812 (if_then_else
8813 (match_test "update_address_mem (operands[0], VOIDmode)")
8814 (const_string "store_u")
8815 (const_string "store")))
8816 (const_string "fp")
8817 (const_string "vecsimple")
8818 (const_string "vecsimple")
8819 (if_then_else
8820 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8821 (const_string "fpload_ux")
8822 (if_then_else
8823 (match_test "update_address_mem (operands[1], VOIDmode)")
8824 (const_string "fpload_u")
8825 (const_string "fpload")))
8826 (if_then_else
8827 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8828 (const_string "fpstore_ux")
8829 (if_then_else
8830 (match_test "update_address_mem (operands[0], VOIDmode)")
8831 (const_string "fpstore_u")
8832 (const_string "fpstore")))
8833 (const_string "fpload")
8834 (const_string "fpstore")
8835 (const_string "mftgpr")
8836 (const_string "mffgpr")
8837 (const_string "mtjmpr")
8838 (const_string "mfjmpr")
8839 (const_string "*")
8840 (const_string "*")
8841 (const_string "*")])
8842 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
8843
8844 (define_insn "*mov<mode>_softfloat"
8845 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
8846 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
8847 "(gpc_reg_operand (operands[0], <MODE>mode)
8848 || gpc_reg_operand (operands[1], <MODE>mode))
8849 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8850 "@
8851 mr %0,%1
8852 mt%0 %1
8853 mf%1 %0
8854 lwz%U1%X1 %0,%1
8855 stw%U0%X0 %1,%0
8856 li %0,%1
8857 lis %0,%v1
8858 #
8859 #
8860 nop"
8861 [(set_attr_alternative "type"
8862 [(const_string "*")
8863 (const_string "mtjmpr")
8864 (const_string "mfjmpr")
8865 (if_then_else
8866 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8867 (const_string "load_ux")
8868 (if_then_else
8869 (match_test "update_address_mem (operands[1], VOIDmode)")
8870 (const_string "load_u")
8871 (const_string "load")))
8872 (if_then_else
8873 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8874 (const_string "store_ux")
8875 (if_then_else
8876 (match_test "update_address_mem (operands[0], VOIDmode)")
8877 (const_string "store_u")
8878 (const_string "store")))
8879 (const_string "*")
8880 (const_string "*")
8881 (const_string "*")
8882 (const_string "*")
8883 (const_string "*")])
8884 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
8885
8886 \f
8887 ;; Move 64-bit binary/decimal floating point
8888 (define_expand "mov<mode>"
8889 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
8890 (match_operand:FMOVE64 1 "any_operand" ""))]
8891 ""
8892 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8893
8894 (define_split
8895 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8896 (match_operand:FMOVE64 1 "const_int_operand" ""))]
8897 "! TARGET_POWERPC64 && reload_completed
8898 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8899 || (GET_CODE (operands[0]) == SUBREG
8900 && GET_CODE (SUBREG_REG (operands[0])) == REG
8901 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8902 [(set (match_dup 2) (match_dup 4))
8903 (set (match_dup 3) (match_dup 1))]
8904 "
8905 {
8906 int endian = (WORDS_BIG_ENDIAN == 0);
8907 HOST_WIDE_INT value = INTVAL (operands[1]);
8908
8909 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8910 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8911 operands[4] = GEN_INT (value >> 32);
8912 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8913 }")
8914
8915 (define_split
8916 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8917 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8918 "! TARGET_POWERPC64 && reload_completed
8919 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8920 || (GET_CODE (operands[0]) == SUBREG
8921 && GET_CODE (SUBREG_REG (operands[0])) == REG
8922 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8923 [(set (match_dup 2) (match_dup 4))
8924 (set (match_dup 3) (match_dup 5))]
8925 "
8926 {
8927 int endian = (WORDS_BIG_ENDIAN == 0);
8928 long l[2];
8929 REAL_VALUE_TYPE rv;
8930
8931 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8932 <real_value_to_target> (rv, l);
8933
8934 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8935 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8936 operands[4] = gen_int_mode (l[endian], SImode);
8937 operands[5] = gen_int_mode (l[1 - endian], SImode);
8938 }")
8939
8940 (define_split
8941 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8942 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8943 "TARGET_POWERPC64 && reload_completed
8944 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8945 || (GET_CODE (operands[0]) == SUBREG
8946 && GET_CODE (SUBREG_REG (operands[0])) == REG
8947 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8948 [(set (match_dup 2) (match_dup 3))]
8949 "
8950 {
8951 int endian = (WORDS_BIG_ENDIAN == 0);
8952 long l[2];
8953 REAL_VALUE_TYPE rv;
8954 HOST_WIDE_INT val;
8955
8956 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8957 <real_value_to_target> (rv, l);
8958
8959 operands[2] = gen_lowpart (DImode, operands[0]);
8960 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8961 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8962 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8963
8964 operands[3] = gen_int_mode (val, DImode);
8965 }")
8966
8967 ;; Don't have reload use general registers to load a constant. It is
8968 ;; less efficient than loading the constant into an FP register, since
8969 ;; it will probably be used there.
8970
8971 ;; The move constraints are ordered to prefer floating point registers before
8972 ;; general purpose registers to avoid doing a store and a load to get the value
8973 ;; into a floating point register when it is needed for a floating point
8974 ;; operation. Prefer traditional floating point registers over VSX registers,
8975 ;; since the D-form version of the memory instructions does not need a GPR for
8976 ;; reloading.
8977
8978 (define_insn "*mov<mode>_hardfloat32"
8979 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")
8980 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]
8981 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8982 && (gpc_reg_operand (operands[0], <MODE>mode)
8983 || gpc_reg_operand (operands[1], <MODE>mode))"
8984 "@
8985 stfd%U0%X0 %1,%0
8986 lfd%U1%X1 %0,%1
8987 fmr %0,%1
8988 lxsd%U1x %x0,%y1
8989 lxsd%U1x %x0,%y1
8990 stxsd%U0x %x1,%y0
8991 stxsd%U0x %x1,%y0
8992 xxlor %x0,%x1,%x1
8993 xxlor %x0,%x1,%x1
8994 xxlxor %x0,%x0,%x0
8995 #
8996 #
8997 #
8998 #
8999 #
9000 #"
9001 [(set_attr_alternative "type"
9002 [(if_then_else
9003 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9004 (const_string "fpstore_ux")
9005 (if_then_else
9006 (match_test "update_address_mem (operands[0], VOIDmode)")
9007 (const_string "fpstore_u")
9008 (const_string "fpstore")))
9009 (if_then_else
9010 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9011 (const_string "fpload_ux")
9012 (if_then_else
9013 (match_test "update_address_mem (operands[1], VOIDmode)")
9014 (const_string "fpload_u")
9015 (const_string "fpload")))
9016 (const_string "fp")
9017 (if_then_else
9018 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9019 (const_string "fpload_ux")
9020 (const_string "fpload"))
9021 (if_then_else
9022 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9023 (const_string "fpload_ux")
9024 (const_string "fpload"))
9025 (if_then_else
9026 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9027 (const_string "fpstore_ux")
9028 (const_string "fpstore"))
9029 (if_then_else
9030 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9031 (const_string "fpstore_ux")
9032 (const_string "fpstore"))
9033 (const_string "vecsimple")
9034 (const_string "vecsimple")
9035 (const_string "vecsimple")
9036 (const_string "store")
9037 (const_string "load")
9038 (const_string "two")
9039 (const_string "fp")
9040 (const_string "fp")
9041 (const_string "*")])
9042 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])
9043
9044 (define_insn "*mov<mode>_softfloat32"
9045 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
9046 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
9047 "! TARGET_POWERPC64
9048 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9049 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9050 && (gpc_reg_operand (operands[0], <MODE>mode)
9051 || gpc_reg_operand (operands[1], <MODE>mode))"
9052 "#"
9053 [(set_attr "type" "store,load,two,*,*,*")
9054 (set_attr "length" "8,8,8,8,12,16")])
9055
9056 ; ld/std require word-aligned displacements -> 'Y' constraint.
9057 ; List Y->r and r->Y before r->r for reload.
9058 (define_insn "*mov<mode>_hardfloat64"
9059 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
9060 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
9061 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9062 && (gpc_reg_operand (operands[0], <MODE>mode)
9063 || gpc_reg_operand (operands[1], <MODE>mode))"
9064 "@
9065 stfd%U0%X0 %1,%0
9066 lfd%U1%X1 %0,%1
9067 fmr %0,%1
9068 lxsd%U1x %x0,%y1
9069 lxsd%U1x %x0,%y1
9070 stxsd%U0x %x1,%y0
9071 stxsd%U0x %x1,%y0
9072 xxlor %x0,%x1,%x1
9073 xxlor %x0,%x1,%x1
9074 xxlxor %x0,%x0,%x0
9075 std%U0%X0 %1,%0
9076 ld%U1%X1 %0,%1
9077 mr %0,%1
9078 mt%0 %1
9079 mf%1 %0
9080 nop
9081 #
9082 #
9083 #
9084 mftgpr %0,%1
9085 mffgpr %0,%1
9086 mfvsrd %0,%x1
9087 mtvsrd %x0,%1"
9088 [(set_attr_alternative "type"
9089 [(if_then_else
9090 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9091 (const_string "fpstore_ux")
9092 (if_then_else
9093 (match_test "update_address_mem (operands[0], VOIDmode)")
9094 (const_string "fpstore_u")
9095 (const_string "fpstore")))
9096 (if_then_else
9097 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9098 (const_string "fpload_ux")
9099 (if_then_else
9100 (match_test "update_address_mem (operands[1], VOIDmode)")
9101 (const_string "fpload_u")
9102 (const_string "fpload")))
9103 (const_string "fp")
9104 (if_then_else
9105 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9106 (const_string "fpload_ux")
9107 (const_string "fpload"))
9108 (if_then_else
9109 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9110 (const_string "fpload_ux")
9111 (const_string "fpload"))
9112 (if_then_else
9113 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9114 (const_string "fpstore_ux")
9115 (const_string "fpstore"))
9116 (if_then_else
9117 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9118 (const_string "fpstore_ux")
9119 (const_string "fpstore"))
9120 (const_string "vecsimple")
9121 (const_string "vecsimple")
9122 (const_string "vecsimple")
9123 (if_then_else
9124 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9125 (const_string "store_ux")
9126 (if_then_else
9127 (match_test "update_address_mem (operands[0], VOIDmode)")
9128 (const_string "store_u")
9129 (const_string "store")))
9130 (if_then_else
9131 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9132 (const_string "load_ux")
9133 (if_then_else
9134 (match_test "update_address_mem (operands[1], VOIDmode)")
9135 (const_string "load_u")
9136 (const_string "load")))
9137 (const_string "*")
9138 (const_string "mtjmpr")
9139 (const_string "mfjmpr")
9140 (const_string "*")
9141 (const_string "*")
9142 (const_string "*")
9143 (const_string "*")
9144 (const_string "mftgpr")
9145 (const_string "mffgpr")
9146 (const_string "mftgpr")
9147 (const_string "mffgpr")])
9148 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
9149
9150 (define_insn "*mov<mode>_softfloat64"
9151 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9152 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9153 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9154 && (gpc_reg_operand (operands[0], <MODE>mode)
9155 || gpc_reg_operand (operands[1], <MODE>mode))"
9156 "@
9157 std%U0%X0 %1,%0
9158 ld%U1%X1 %0,%1
9159 mr %0,%1
9160 mt%0 %1
9161 mf%1 %0
9162 #
9163 #
9164 #
9165 nop"
9166 [(set_attr_alternative "type"
9167 [(if_then_else
9168 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9169 (const_string "store_ux")
9170 (if_then_else
9171 (match_test "update_address_mem (operands[0], VOIDmode)")
9172 (const_string "store_u")
9173 (const_string "store")))
9174 (if_then_else
9175 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9176 (const_string "load_ux")
9177 (if_then_else
9178 (match_test "update_address_mem (operands[1], VOIDmode)")
9179 (const_string "load_u")
9180 (const_string "load")))
9181 (const_string "*")
9182 (const_string "mtjmpr")
9183 (const_string "mfjmpr")
9184 (const_string "*")
9185 (const_string "*")
9186 (const_string "*")
9187 (const_string "*")])
9188 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9189 \f
9190 (define_expand "mov<mode>"
9191 [(set (match_operand:FMOVE128 0 "general_operand" "")
9192 (match_operand:FMOVE128 1 "any_operand" ""))]
9193 ""
9194 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9195
9196 ;; It's important to list Y->r and r->Y before r->r because otherwise
9197 ;; reload, given m->r, will try to pick r->r and reload it, which
9198 ;; doesn't make progress.
9199 (define_insn_and_split "*mov<mode>_internal"
9200 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9201 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9202 "TARGET_HARD_FLOAT && TARGET_FPRS
9203 && (gpc_reg_operand (operands[0], <MODE>mode)
9204 || gpc_reg_operand (operands[1], <MODE>mode))"
9205 "#"
9206 "&& reload_completed"
9207 [(pc)]
9208 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9209 [(set_attr "length" "8,8,8,20,20,16")])
9210
9211 (define_insn_and_split "*mov<mode>_softfloat"
9212 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9213 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9214 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9215 && (gpc_reg_operand (operands[0], <MODE>mode)
9216 || gpc_reg_operand (operands[1], <MODE>mode))"
9217 "#"
9218 "&& reload_completed"
9219 [(pc)]
9220 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9221 [(set_attr "length" "20,20,16")])
9222
9223 (define_expand "extenddftf2"
9224 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9225 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9226 "!TARGET_IEEEQUAD
9227 && TARGET_HARD_FLOAT
9228 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9229 && TARGET_LONG_DOUBLE_128"
9230 {
9231 if (TARGET_E500_DOUBLE)
9232 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9233 else
9234 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9235 DONE;
9236 })
9237
9238 (define_expand "extenddftf2_fprs"
9239 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9240 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9241 (use (match_dup 2))])]
9242 "!TARGET_IEEEQUAD
9243 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9244 && TARGET_LONG_DOUBLE_128"
9245 {
9246 operands[2] = CONST0_RTX (DFmode);
9247 /* Generate GOT reference early for SVR4 PIC. */
9248 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9249 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9250 })
9251
9252 (define_insn_and_split "*extenddftf2_internal"
9253 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9254 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9255 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9256 "!TARGET_IEEEQUAD
9257 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9258 && TARGET_LONG_DOUBLE_128"
9259 "#"
9260 "&& reload_completed"
9261 [(pc)]
9262 {
9263 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9264 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9265 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9266 operands[1]);
9267 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9268 operands[2]);
9269 DONE;
9270 })
9271
9272 (define_expand "extendsftf2"
9273 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9274 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9275 "!TARGET_IEEEQUAD
9276 && TARGET_HARD_FLOAT
9277 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9278 && TARGET_LONG_DOUBLE_128"
9279 {
9280 rtx tmp = gen_reg_rtx (DFmode);
9281 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9282 emit_insn (gen_extenddftf2 (operands[0], tmp));
9283 DONE;
9284 })
9285
9286 (define_expand "trunctfdf2"
9287 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9288 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9289 "!TARGET_IEEEQUAD
9290 && TARGET_HARD_FLOAT
9291 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9292 && TARGET_LONG_DOUBLE_128"
9293 "")
9294
9295 (define_insn_and_split "trunctfdf2_internal1"
9296 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9297 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9298 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9299 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9300 "@
9301 #
9302 fmr %0,%1"
9303 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9304 [(const_int 0)]
9305 {
9306 emit_note (NOTE_INSN_DELETED);
9307 DONE;
9308 }
9309 [(set_attr "type" "fp")])
9310
9311 (define_insn "trunctfdf2_internal2"
9312 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9313 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9314 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9315 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9316 && TARGET_LONG_DOUBLE_128"
9317 "fadd %0,%1,%L1"
9318 [(set_attr "type" "fp")
9319 (set_attr "fp_type" "fp_addsub_d")])
9320
9321 (define_expand "trunctfsf2"
9322 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9323 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9324 "!TARGET_IEEEQUAD
9325 && TARGET_HARD_FLOAT
9326 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9327 && TARGET_LONG_DOUBLE_128"
9328 {
9329 if (TARGET_E500_DOUBLE)
9330 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9331 else
9332 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9333 DONE;
9334 })
9335
9336 (define_insn_and_split "trunctfsf2_fprs"
9337 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9338 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9339 (clobber (match_scratch:DF 2 "=d"))]
9340 "!TARGET_IEEEQUAD
9341 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9342 && TARGET_LONG_DOUBLE_128"
9343 "#"
9344 "&& reload_completed"
9345 [(set (match_dup 2)
9346 (float_truncate:DF (match_dup 1)))
9347 (set (match_dup 0)
9348 (float_truncate:SF (match_dup 2)))]
9349 "")
9350
9351 (define_expand "floatsitf2"
9352 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9353 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9354 "!TARGET_IEEEQUAD
9355 && TARGET_HARD_FLOAT
9356 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9357 && TARGET_LONG_DOUBLE_128"
9358 {
9359 rtx tmp = gen_reg_rtx (DFmode);
9360 expand_float (tmp, operands[1], false);
9361 emit_insn (gen_extenddftf2 (operands[0], tmp));
9362 DONE;
9363 })
9364
9365 ; fadd, but rounding towards zero.
9366 ; This is probably not the optimal code sequence.
9367 (define_insn "fix_trunc_helper"
9368 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9369 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9370 UNSPEC_FIX_TRUNC_TF))
9371 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9372 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9373 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9374 [(set_attr "type" "fp")
9375 (set_attr "length" "20")])
9376
9377 (define_expand "fix_trunctfsi2"
9378 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9379 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9380 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9381 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9382 {
9383 if (TARGET_E500_DOUBLE)
9384 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9385 else
9386 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9387 DONE;
9388 })
9389
9390 (define_expand "fix_trunctfsi2_fprs"
9391 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9392 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9393 (clobber (match_dup 2))
9394 (clobber (match_dup 3))
9395 (clobber (match_dup 4))
9396 (clobber (match_dup 5))])]
9397 "!TARGET_IEEEQUAD
9398 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9399 {
9400 operands[2] = gen_reg_rtx (DFmode);
9401 operands[3] = gen_reg_rtx (DFmode);
9402 operands[4] = gen_reg_rtx (DImode);
9403 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9404 })
9405
9406 (define_insn_and_split "*fix_trunctfsi2_internal"
9407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9408 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9409 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9410 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9411 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9412 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9413 "!TARGET_IEEEQUAD
9414 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9415 "#"
9416 ""
9417 [(pc)]
9418 {
9419 rtx lowword;
9420 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9421
9422 gcc_assert (MEM_P (operands[5]));
9423 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9424
9425 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9426 emit_move_insn (operands[5], operands[4]);
9427 emit_move_insn (operands[0], lowword);
9428 DONE;
9429 })
9430
9431 (define_expand "negtf2"
9432 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9433 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9434 "!TARGET_IEEEQUAD
9435 && TARGET_HARD_FLOAT
9436 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9437 && TARGET_LONG_DOUBLE_128"
9438 "")
9439
9440 (define_insn "negtf2_internal"
9441 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9442 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9443 "!TARGET_IEEEQUAD
9444 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9445 "*
9446 {
9447 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9448 return \"fneg %L0,%L1\;fneg %0,%1\";
9449 else
9450 return \"fneg %0,%1\;fneg %L0,%L1\";
9451 }"
9452 [(set_attr "type" "fp")
9453 (set_attr "length" "8")])
9454
9455 (define_expand "abstf2"
9456 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9457 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9458 "!TARGET_IEEEQUAD
9459 && TARGET_HARD_FLOAT
9460 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9461 && TARGET_LONG_DOUBLE_128"
9462 "
9463 {
9464 rtx label = gen_label_rtx ();
9465 if (TARGET_E500_DOUBLE)
9466 {
9467 if (flag_finite_math_only && !flag_trapping_math)
9468 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9469 else
9470 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9471 }
9472 else
9473 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9474 emit_label (label);
9475 DONE;
9476 }")
9477
9478 (define_expand "abstf2_internal"
9479 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9480 (match_operand:TF 1 "gpc_reg_operand" ""))
9481 (set (match_dup 3) (match_dup 5))
9482 (set (match_dup 5) (abs:DF (match_dup 5)))
9483 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9484 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9485 (label_ref (match_operand 2 "" ""))
9486 (pc)))
9487 (set (match_dup 6) (neg:DF (match_dup 6)))]
9488 "!TARGET_IEEEQUAD
9489 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9490 && TARGET_LONG_DOUBLE_128"
9491 "
9492 {
9493 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9494 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9495 operands[3] = gen_reg_rtx (DFmode);
9496 operands[4] = gen_reg_rtx (CCFPmode);
9497 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9498 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9499 }")
9500 \f
9501 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9502 ;; must have 3 arguments, and scratch register constraint must be a single
9503 ;; constraint.
9504
9505 ;; Reload patterns to support gpr load/store with misaligned mem.
9506 ;; and multiple gpr load/store at offset >= 0xfffc
9507 (define_expand "reload_<mode>_store"
9508 [(parallel [(match_operand 0 "memory_operand" "=m")
9509 (match_operand 1 "gpc_reg_operand" "r")
9510 (match_operand:GPR 2 "register_operand" "=&b")])]
9511 ""
9512 {
9513 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9514 DONE;
9515 })
9516
9517 (define_expand "reload_<mode>_load"
9518 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9519 (match_operand 1 "memory_operand" "m")
9520 (match_operand:GPR 2 "register_operand" "=b")])]
9521 ""
9522 {
9523 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9524 DONE;
9525 })
9526
9527 \f
9528 ;; Power8 merge instructions to allow direct move to/from floating point
9529 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
9530 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
9531 ;; value, since it is allocated in reload and not all of the flow information
9532 ;; is setup for it. We have two patterns to do the two moves between gprs and
9533 ;; fprs. There isn't a dependancy between the two, but we could potentially
9534 ;; schedule other instructions between the two instructions. TFmode is
9535 ;; currently limited to traditional FPR registers. If/when this is changed, we
9536 ;; will need to revist %L to make sure it works with VSX registers, or add an
9537 ;; %x version of %L.
9538
9539 (define_insn "p8_fmrgow_<mode>"
9540 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
9541 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
9542 UNSPEC_P8V_FMRGOW))]
9543 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9544 "fmrgow %0,%1,%L1"
9545 [(set_attr "type" "vecperm")])
9546
9547 (define_insn "p8_mtvsrwz_1"
9548 [(set (match_operand:TF 0 "register_operand" "=d")
9549 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
9550 UNSPEC_P8V_MTVSRWZ))]
9551 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9552 "mtvsrwz %x0,%1"
9553 [(set_attr "type" "mftgpr")])
9554
9555 (define_insn "p8_mtvsrwz_2"
9556 [(set (match_operand:TF 0 "register_operand" "+d")
9557 (unspec:TF [(match_dup 0)
9558 (match_operand:SI 1 "register_operand" "r")]
9559 UNSPEC_P8V_MTVSRWZ))]
9560 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9561 "mtvsrwz %L0,%1"
9562 [(set_attr "type" "mftgpr")])
9563
9564 (define_insn_and_split "reload_fpr_from_gpr<mode>"
9565 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
9566 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
9567 UNSPEC_P8V_RELOAD_FROM_GPR))
9568 (clobber (match_operand:TF 2 "register_operand" "=d"))]
9569 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9570 "#"
9571 "&& reload_completed"
9572 [(const_int 0)]
9573 {
9574 rtx dest = operands[0];
9575 rtx src = operands[1];
9576 rtx tmp = operands[2];
9577 rtx gpr_hi_reg = gen_highpart (SImode, src);
9578 rtx gpr_lo_reg = gen_lowpart (SImode, src);
9579
9580 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
9581 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
9582 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
9583 DONE;
9584 }
9585 [(set_attr "length" "12")
9586 (set_attr "type" "three")])
9587
9588 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
9589 (define_insn "p8_mtvsrd_1"
9590 [(set (match_operand:TF 0 "register_operand" "=ws")
9591 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
9592 UNSPEC_P8V_MTVSRD))]
9593 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9594 "mtvsrd %0,%1"
9595 [(set_attr "type" "mftgpr")])
9596
9597 (define_insn "p8_mtvsrd_2"
9598 [(set (match_operand:TF 0 "register_operand" "+ws")
9599 (unspec:TF [(match_dup 0)
9600 (match_operand:DI 1 "register_operand" "r")]
9601 UNSPEC_P8V_MTVSRD))]
9602 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9603 "mtvsrd %L0,%1"
9604 [(set_attr "type" "mftgpr")])
9605
9606 (define_insn "p8_xxpermdi_<mode>"
9607 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9608 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
9609 UNSPEC_P8V_XXPERMDI))]
9610 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9611 "xxpermdi %x0,%1,%L1,0"
9612 [(set_attr "type" "vecperm")])
9613
9614 (define_insn_and_split "reload_vsx_from_gpr<mode>"
9615 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9616 (unspec:FMOVE128_GPR
9617 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
9618 UNSPEC_P8V_RELOAD_FROM_GPR))
9619 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
9620 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9621 "#"
9622 "&& reload_completed"
9623 [(const_int 0)]
9624 {
9625 rtx dest = operands[0];
9626 rtx src = operands[1];
9627 rtx tmp = operands[2];
9628 rtx gpr_hi_reg = gen_highpart (DImode, src);
9629 rtx gpr_lo_reg = gen_lowpart (DImode, src);
9630
9631 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
9632 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
9633 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
9634 }
9635 [(set_attr "length" "12")
9636 (set_attr "type" "three")])
9637
9638 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
9639 ;; type is stored internally as double precision in the VSX registers, we have
9640 ;; to convert it from the vector format.
9641
9642 (define_insn_and_split "reload_vsx_from_gprsf"
9643 [(set (match_operand:SF 0 "register_operand" "=wa")
9644 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
9645 UNSPEC_P8V_RELOAD_FROM_GPR))
9646 (clobber (match_operand:DI 2 "register_operand" "=r"))]
9647 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
9648 "#"
9649 "&& reload_completed"
9650 [(const_int 0)]
9651 {
9652 rtx op0 = operands[0];
9653 rtx op1 = operands[1];
9654 rtx op2 = operands[2];
9655 rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
9656 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
9657
9658 /* Move SF value to upper 32-bits for xscvspdpn. */
9659 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
9660 emit_move_insn (op0_di, op2);
9661 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
9662 DONE;
9663 }
9664 [(set_attr "length" "8")
9665 (set_attr "type" "two")])
9666
9667 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
9668 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
9669 ;; and then doing a move of that.
9670 (define_insn "p8_mfvsrd_3_<mode>"
9671 [(set (match_operand:DF 0 "register_operand" "=r")
9672 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9673 UNSPEC_P8V_RELOAD_FROM_VSX))]
9674 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
9675 "mfvsrd %0,%x1"
9676 [(set_attr "type" "mftgpr")])
9677
9678 (define_insn_and_split "reload_gpr_from_vsx<mode>"
9679 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
9680 (unspec:FMOVE128_GPR
9681 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9682 UNSPEC_P8V_RELOAD_FROM_VSX))
9683 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
9684 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
9685 "#"
9686 "&& reload_completed"
9687 [(const_int 0)]
9688 {
9689 rtx dest = operands[0];
9690 rtx src = operands[1];
9691 rtx tmp = operands[2];
9692 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
9693 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
9694
9695 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
9696 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
9697 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
9698 }
9699 [(set_attr "length" "12")
9700 (set_attr "type" "three")])
9701
9702 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
9703 ;; type is stored internally as double precision, we have to convert it to the
9704 ;; vector format.
9705
9706 (define_insn_and_split "reload_gpr_from_vsxsf"
9707 [(set (match_operand:SF 0 "register_operand" "=r")
9708 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
9709 UNSPEC_P8V_RELOAD_FROM_VSX))
9710 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
9711 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
9712 "#"
9713 "&& reload_completed"
9714 [(const_int 0)]
9715 {
9716 rtx op0 = operands[0];
9717 rtx op1 = operands[1];
9718 rtx op2 = operands[2];
9719 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
9720
9721 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
9722 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
9723 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
9724 DONE;
9725 }
9726 [(set_attr "length" "12")
9727 (set_attr "type" "three")])
9728
9729 (define_insn "p8_mfvsrd_4_disf"
9730 [(set (match_operand:DI 0 "register_operand" "=r")
9731 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
9732 UNSPEC_P8V_RELOAD_FROM_VSX))]
9733 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
9734 "mfvsrd %0,%x1"
9735 [(set_attr "type" "mftgpr")])
9736
9737 \f
9738 ;; Next come the multi-word integer load and store and the load and store
9739 ;; multiple insns.
9740
9741 ;; List r->r after r->Y, otherwise reload will try to reload a
9742 ;; non-offsettable address by using r->r which won't make progress.
9743 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9744 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9745 (define_insn "*movdi_internal32"
9746 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
9747 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
9748 "! TARGET_POWERPC64
9749 && (gpc_reg_operand (operands[0], DImode)
9750 || gpc_reg_operand (operands[1], DImode))"
9751 "@
9752 #
9753 #
9754 #
9755 stfd%U0%X0 %1,%0
9756 lfd%U1%X1 %0,%1
9757 fmr %0,%1
9758 #
9759 xxlxor %x0,%x0,%x0"
9760 [(set_attr_alternative "type"
9761 [(const_string "store")
9762 (const_string "load")
9763 (const_string "*")
9764 (if_then_else
9765 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9766 (const_string "fpstore_ux")
9767 (if_then_else
9768 (match_test "update_address_mem (operands[0], VOIDmode)")
9769 (const_string "fpstore_u")
9770 (const_string "fpstore")))
9771 (if_then_else
9772 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9773 (const_string "fpload_ux")
9774 (if_then_else
9775 (match_test "update_address_mem (operands[1], VOIDmode)")
9776 (const_string "fpload_u")
9777 (const_string "fpload")))
9778 (const_string "fp")
9779 (const_string "*")
9780 (const_string "vecsimple")])])
9781
9782 (define_split
9783 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9784 (match_operand:DI 1 "const_int_operand" ""))]
9785 "! TARGET_POWERPC64 && reload_completed
9786 && gpr_or_gpr_p (operands[0], operands[1])
9787 && !direct_move_p (operands[0], operands[1])"
9788 [(set (match_dup 2) (match_dup 4))
9789 (set (match_dup 3) (match_dup 1))]
9790 "
9791 {
9792 HOST_WIDE_INT value = INTVAL (operands[1]);
9793 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9794 DImode);
9795 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9796 DImode);
9797 operands[4] = GEN_INT (value >> 32);
9798 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9799 }")
9800
9801 (define_split
9802 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9803 (match_operand:DIFD 1 "input_operand" ""))]
9804 "reload_completed && !TARGET_POWERPC64
9805 && gpr_or_gpr_p (operands[0], operands[1])
9806 && !direct_move_p (operands[0], operands[1])"
9807 [(pc)]
9808 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9809
9810 (define_insn "*movdi_internal64"
9811 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,?Z,?wa,?wa,r,*h,*h,?wa,r,?*wg,r,?*wm")
9812 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,wa,Z,wa,*h,r,0,O,*wg,r,*wm,r"))]
9813 "TARGET_POWERPC64
9814 && (gpc_reg_operand (operands[0], DImode)
9815 || gpc_reg_operand (operands[1], DImode))"
9816 "@
9817 std%U0%X0 %1,%0
9818 ld%U1%X1 %0,%1
9819 mr %0,%1
9820 li %0,%1
9821 lis %0,%v1
9822 #
9823 stfd%U0%X0 %1,%0
9824 lfd%U1%X1 %0,%1
9825 fmr %0,%1
9826 stxsd%U0x %x1,%y0
9827 lxsd%U1x %x0,%y1
9828 xxlor %x0,%x1,%x1
9829 mf%1 %0
9830 mt%0 %1
9831 nop
9832 xxlxor %x0,%x0,%x0
9833 mftgpr %0,%1
9834 mffgpr %0,%1
9835 mfvsrd %0,%x1
9836 mtvsrd %x0,%1"
9837 [(set_attr_alternative "type"
9838 [(if_then_else
9839 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9840 (const_string "store_ux")
9841 (if_then_else
9842 (match_test "update_address_mem (operands[0], VOIDmode)")
9843 (const_string "store_u")
9844 (const_string "store")))
9845 (if_then_else
9846 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9847 (const_string "load_ux")
9848 (if_then_else
9849 (match_test "update_address_mem (operands[1], VOIDmode)")
9850 (const_string "load_u")
9851 (const_string "load")))
9852 (const_string "*")
9853 (const_string "*")
9854 (const_string "*")
9855 (const_string "*")
9856 (if_then_else
9857 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9858 (const_string "fpstore_ux")
9859 (if_then_else
9860 (match_test "update_address_mem (operands[0], VOIDmode)")
9861 (const_string "fpstore_u")
9862 (const_string "fpstore")))
9863 (if_then_else
9864 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9865 (const_string "fpload_ux")
9866 (if_then_else
9867 (match_test "update_address_mem (operands[1], VOIDmode)")
9868 (const_string "fpload_u")
9869 (const_string "fpload")))
9870 (const_string "fp")
9871 (if_then_else
9872 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9873 (const_string "fpstore_ux")
9874 (const_string "fpstore"))
9875 (if_then_else
9876 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9877 (const_string "fpload_ux")
9878 (const_string "fpload"))
9879 (const_string "vecsimple")
9880 (const_string "mfjmpr")
9881 (const_string "mtjmpr")
9882 (const_string "*")
9883 (const_string "vecsimple")
9884 (const_string "mftgpr")
9885 (const_string "mffgpr")
9886 (const_string "mftgpr")
9887 (const_string "mffgpr")])
9888 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4,4,4")])
9889
9890 ;; Generate all one-bits and clear left or right.
9891 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9892 (define_split
9893 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9894 (match_operand:DI 1 "mask64_operand" ""))]
9895 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9896 [(set (match_dup 0) (const_int -1))
9897 (set (match_dup 0)
9898 (and:DI (rotate:DI (match_dup 0)
9899 (const_int 0))
9900 (match_dup 1)))]
9901 "")
9902
9903 ;; Split a load of a large constant into the appropriate five-instruction
9904 ;; sequence. Handle anything in a constant number of insns.
9905 ;; When non-easy constants can go in the TOC, this should use
9906 ;; easy_fp_constant predicate.
9907 (define_split
9908 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9909 (match_operand:DI 1 "const_int_operand" ""))]
9910 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9911 [(set (match_dup 0) (match_dup 2))
9912 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9913 "
9914 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9915
9916 if (tem == operands[0])
9917 DONE;
9918 else
9919 FAIL;
9920 }")
9921
9922 (define_split
9923 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9924 (match_operand:DI 1 "const_double_operand" ""))]
9925 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9926 [(set (match_dup 0) (match_dup 2))
9927 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9928 "
9929 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9930
9931 if (tem == operands[0])
9932 DONE;
9933 else
9934 FAIL;
9935 }")
9936 \f
9937 ;; TImode/PTImode is similar, except that we usually want to compute the
9938 ;; address into a register and use lsi/stsi (the exception is during reload).
9939
9940 (define_insn "*mov<mode>_string"
9941 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9942 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
9943 "! TARGET_POWERPC64
9944 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9945 && (gpc_reg_operand (operands[0], <MODE>mode)
9946 || gpc_reg_operand (operands[1], <MODE>mode))"
9947 "*
9948 {
9949 switch (which_alternative)
9950 {
9951 default:
9952 gcc_unreachable ();
9953 case 0:
9954 if (TARGET_STRING)
9955 return \"stswi %1,%P0,16\";
9956 case 1:
9957 return \"#\";
9958 case 2:
9959 /* If the address is not used in the output, we can use lsi. Otherwise,
9960 fall through to generating four loads. */
9961 if (TARGET_STRING
9962 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9963 return \"lswi %0,%P1,16\";
9964 /* ... fall through ... */
9965 case 3:
9966 case 4:
9967 case 5:
9968 return \"#\";
9969 }
9970 }"
9971 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
9972 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9973 (const_string "always")
9974 (const_string "conditional")))])
9975
9976 (define_insn "*mov<mode>_ppc64"
9977 [(set (match_operand:TI2 0 "nonimmediate_operand" "=Y,r,r,r")
9978 (match_operand:TI2 1 "input_operand" "r,Y,r,F"))]
9979 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
9980 && (gpc_reg_operand (operands[0], <MODE>mode)
9981 || gpc_reg_operand (operands[1], <MODE>mode)))"
9982 "#"
9983 [(set_attr "type" "store,load,*,*")])
9984
9985 (define_split
9986 [(set (match_operand:TI2 0 "int_reg_operand" "")
9987 (match_operand:TI2 1 "const_double_operand" ""))]
9988 "TARGET_POWERPC64
9989 && (VECTOR_MEM_NONE_P (<MODE>mode)
9990 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
9991 [(set (match_dup 2) (match_dup 4))
9992 (set (match_dup 3) (match_dup 5))]
9993 "
9994 {
9995 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9996 <MODE>mode);
9997 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9998 <MODE>mode);
9999 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10000 {
10001 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10002 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10003 }
10004 else if (GET_CODE (operands[1]) == CONST_INT)
10005 {
10006 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10007 operands[5] = operands[1];
10008 }
10009 else
10010 FAIL;
10011 }")
10012
10013 (define_split
10014 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
10015 (match_operand:TI2 1 "input_operand" ""))]
10016 "reload_completed
10017 && gpr_or_gpr_p (operands[0], operands[1])
10018 && !direct_move_p (operands[0], operands[1])
10019 && !quad_load_store_p (operands[0], operands[1])"
10020 [(pc)]
10021 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10022 \f
10023 (define_expand "load_multiple"
10024 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10025 (match_operand:SI 1 "" ""))
10026 (use (match_operand:SI 2 "" ""))])]
10027 "TARGET_STRING && !TARGET_POWERPC64"
10028 "
10029 {
10030 int regno;
10031 int count;
10032 rtx op1;
10033 int i;
10034
10035 /* Support only loading a constant number of fixed-point registers from
10036 memory and only bother with this if more than two; the machine
10037 doesn't support more than eight. */
10038 if (GET_CODE (operands[2]) != CONST_INT
10039 || INTVAL (operands[2]) <= 2
10040 || INTVAL (operands[2]) > 8
10041 || GET_CODE (operands[1]) != MEM
10042 || GET_CODE (operands[0]) != REG
10043 || REGNO (operands[0]) >= 32)
10044 FAIL;
10045
10046 count = INTVAL (operands[2]);
10047 regno = REGNO (operands[0]);
10048
10049 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10050 op1 = replace_equiv_address (operands[1],
10051 force_reg (SImode, XEXP (operands[1], 0)));
10052
10053 for (i = 0; i < count; i++)
10054 XVECEXP (operands[3], 0, i)
10055 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10056 adjust_address_nv (op1, SImode, i * 4));
10057 }")
10058
10059 (define_insn "*ldmsi8"
10060 [(match_parallel 0 "load_multiple_operation"
10061 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10062 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10063 (set (match_operand:SI 3 "gpc_reg_operand" "")
10064 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10065 (set (match_operand:SI 4 "gpc_reg_operand" "")
10066 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10067 (set (match_operand:SI 5 "gpc_reg_operand" "")
10068 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10069 (set (match_operand:SI 6 "gpc_reg_operand" "")
10070 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10071 (set (match_operand:SI 7 "gpc_reg_operand" "")
10072 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10073 (set (match_operand:SI 8 "gpc_reg_operand" "")
10074 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10075 (set (match_operand:SI 9 "gpc_reg_operand" "")
10076 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10077 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10078 "*
10079 { return rs6000_output_load_multiple (operands); }"
10080 [(set_attr "type" "load_ux")
10081 (set_attr "length" "32")])
10082
10083 (define_insn "*ldmsi7"
10084 [(match_parallel 0 "load_multiple_operation"
10085 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10086 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10087 (set (match_operand:SI 3 "gpc_reg_operand" "")
10088 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10089 (set (match_operand:SI 4 "gpc_reg_operand" "")
10090 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10091 (set (match_operand:SI 5 "gpc_reg_operand" "")
10092 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10093 (set (match_operand:SI 6 "gpc_reg_operand" "")
10094 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10095 (set (match_operand:SI 7 "gpc_reg_operand" "")
10096 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10097 (set (match_operand:SI 8 "gpc_reg_operand" "")
10098 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10099 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10100 "*
10101 { return rs6000_output_load_multiple (operands); }"
10102 [(set_attr "type" "load_ux")
10103 (set_attr "length" "32")])
10104
10105 (define_insn "*ldmsi6"
10106 [(match_parallel 0 "load_multiple_operation"
10107 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10108 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10109 (set (match_operand:SI 3 "gpc_reg_operand" "")
10110 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10111 (set (match_operand:SI 4 "gpc_reg_operand" "")
10112 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10113 (set (match_operand:SI 5 "gpc_reg_operand" "")
10114 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10115 (set (match_operand:SI 6 "gpc_reg_operand" "")
10116 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10117 (set (match_operand:SI 7 "gpc_reg_operand" "")
10118 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10119 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10120 "*
10121 { return rs6000_output_load_multiple (operands); }"
10122 [(set_attr "type" "load_ux")
10123 (set_attr "length" "32")])
10124
10125 (define_insn "*ldmsi5"
10126 [(match_parallel 0 "load_multiple_operation"
10127 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10128 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10129 (set (match_operand:SI 3 "gpc_reg_operand" "")
10130 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10131 (set (match_operand:SI 4 "gpc_reg_operand" "")
10132 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10133 (set (match_operand:SI 5 "gpc_reg_operand" "")
10134 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10135 (set (match_operand:SI 6 "gpc_reg_operand" "")
10136 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10137 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10138 "*
10139 { return rs6000_output_load_multiple (operands); }"
10140 [(set_attr "type" "load_ux")
10141 (set_attr "length" "32")])
10142
10143 (define_insn "*ldmsi4"
10144 [(match_parallel 0 "load_multiple_operation"
10145 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10146 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10147 (set (match_operand:SI 3 "gpc_reg_operand" "")
10148 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10149 (set (match_operand:SI 4 "gpc_reg_operand" "")
10150 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10151 (set (match_operand:SI 5 "gpc_reg_operand" "")
10152 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10153 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10154 "*
10155 { return rs6000_output_load_multiple (operands); }"
10156 [(set_attr "type" "load_ux")
10157 (set_attr "length" "32")])
10158
10159 (define_insn "*ldmsi3"
10160 [(match_parallel 0 "load_multiple_operation"
10161 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10162 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10163 (set (match_operand:SI 3 "gpc_reg_operand" "")
10164 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10165 (set (match_operand:SI 4 "gpc_reg_operand" "")
10166 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10167 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10168 "*
10169 { return rs6000_output_load_multiple (operands); }"
10170 [(set_attr "type" "load_ux")
10171 (set_attr "length" "32")])
10172
10173 (define_expand "store_multiple"
10174 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10175 (match_operand:SI 1 "" ""))
10176 (clobber (scratch:SI))
10177 (use (match_operand:SI 2 "" ""))])]
10178 "TARGET_STRING && !TARGET_POWERPC64"
10179 "
10180 {
10181 int regno;
10182 int count;
10183 rtx to;
10184 rtx op0;
10185 int i;
10186
10187 /* Support only storing a constant number of fixed-point registers to
10188 memory and only bother with this if more than two; the machine
10189 doesn't support more than eight. */
10190 if (GET_CODE (operands[2]) != CONST_INT
10191 || INTVAL (operands[2]) <= 2
10192 || INTVAL (operands[2]) > 8
10193 || GET_CODE (operands[0]) != MEM
10194 || GET_CODE (operands[1]) != REG
10195 || REGNO (operands[1]) >= 32)
10196 FAIL;
10197
10198 count = INTVAL (operands[2]);
10199 regno = REGNO (operands[1]);
10200
10201 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10202 to = force_reg (SImode, XEXP (operands[0], 0));
10203 op0 = replace_equiv_address (operands[0], to);
10204
10205 XVECEXP (operands[3], 0, 0)
10206 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10207 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10208 gen_rtx_SCRATCH (SImode));
10209
10210 for (i = 1; i < count; i++)
10211 XVECEXP (operands[3], 0, i + 1)
10212 = gen_rtx_SET (VOIDmode,
10213 adjust_address_nv (op0, SImode, i * 4),
10214 gen_rtx_REG (SImode, regno + i));
10215 }")
10216
10217 (define_insn "*stmsi8"
10218 [(match_parallel 0 "store_multiple_operation"
10219 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10220 (match_operand:SI 2 "gpc_reg_operand" "r"))
10221 (clobber (match_scratch:SI 3 "=X"))
10222 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10223 (match_operand:SI 4 "gpc_reg_operand" "r"))
10224 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10225 (match_operand:SI 5 "gpc_reg_operand" "r"))
10226 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10227 (match_operand:SI 6 "gpc_reg_operand" "r"))
10228 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10229 (match_operand:SI 7 "gpc_reg_operand" "r"))
10230 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10231 (match_operand:SI 8 "gpc_reg_operand" "r"))
10232 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10233 (match_operand:SI 9 "gpc_reg_operand" "r"))
10234 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10235 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10236 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
10237 "stswi %2,%1,%O0"
10238 [(set_attr "type" "store_ux")
10239 (set_attr "cell_micro" "always")])
10240
10241 (define_insn "*stmsi7"
10242 [(match_parallel 0 "store_multiple_operation"
10243 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10244 (match_operand:SI 2 "gpc_reg_operand" "r"))
10245 (clobber (match_scratch:SI 3 "=X"))
10246 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10247 (match_operand:SI 4 "gpc_reg_operand" "r"))
10248 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10249 (match_operand:SI 5 "gpc_reg_operand" "r"))
10250 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10251 (match_operand:SI 6 "gpc_reg_operand" "r"))
10252 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10253 (match_operand:SI 7 "gpc_reg_operand" "r"))
10254 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10255 (match_operand:SI 8 "gpc_reg_operand" "r"))
10256 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10257 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10258 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10259 "stswi %2,%1,%O0"
10260 [(set_attr "type" "store_ux")
10261 (set_attr "cell_micro" "always")])
10262
10263 (define_insn "*stmsi6"
10264 [(match_parallel 0 "store_multiple_operation"
10265 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10266 (match_operand:SI 2 "gpc_reg_operand" "r"))
10267 (clobber (match_scratch:SI 3 "=X"))
10268 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10269 (match_operand:SI 4 "gpc_reg_operand" "r"))
10270 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10271 (match_operand:SI 5 "gpc_reg_operand" "r"))
10272 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10273 (match_operand:SI 6 "gpc_reg_operand" "r"))
10274 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10275 (match_operand:SI 7 "gpc_reg_operand" "r"))
10276 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10277 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10278 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10279 "stswi %2,%1,%O0"
10280 [(set_attr "type" "store_ux")
10281 (set_attr "cell_micro" "always")])
10282
10283 (define_insn "*stmsi5"
10284 [(match_parallel 0 "store_multiple_operation"
10285 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10286 (match_operand:SI 2 "gpc_reg_operand" "r"))
10287 (clobber (match_scratch:SI 3 "=X"))
10288 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10289 (match_operand:SI 4 "gpc_reg_operand" "r"))
10290 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10291 (match_operand:SI 5 "gpc_reg_operand" "r"))
10292 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10293 (match_operand:SI 6 "gpc_reg_operand" "r"))
10294 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10295 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10296 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10297 "stswi %2,%1,%O0"
10298 [(set_attr "type" "store_ux")
10299 (set_attr "cell_micro" "always")])
10300
10301 (define_insn "*stmsi4"
10302 [(match_parallel 0 "store_multiple_operation"
10303 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10304 (match_operand:SI 2 "gpc_reg_operand" "r"))
10305 (clobber (match_scratch:SI 3 "=X"))
10306 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10307 (match_operand:SI 4 "gpc_reg_operand" "r"))
10308 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10309 (match_operand:SI 5 "gpc_reg_operand" "r"))
10310 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10311 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10312 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10313 "stswi %2,%1,%O0"
10314 [(set_attr "type" "store_ux")
10315 (set_attr "cell_micro" "always")])
10316
10317 (define_insn "*stmsi3"
10318 [(match_parallel 0 "store_multiple_operation"
10319 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10320 (match_operand:SI 2 "gpc_reg_operand" "r"))
10321 (clobber (match_scratch:SI 3 "=X"))
10322 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10323 (match_operand:SI 4 "gpc_reg_operand" "r"))
10324 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10325 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10326 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10327 "stswi %2,%1,%O0"
10328 [(set_attr "type" "store_ux")
10329 (set_attr "cell_micro" "always")])
10330 \f
10331 (define_expand "setmemsi"
10332 [(parallel [(set (match_operand:BLK 0 "" "")
10333 (match_operand 2 "const_int_operand" ""))
10334 (use (match_operand:SI 1 "" ""))
10335 (use (match_operand:SI 3 "" ""))])]
10336 ""
10337 "
10338 {
10339 /* If value to set is not zero, use the library routine. */
10340 if (operands[2] != const0_rtx)
10341 FAIL;
10342
10343 if (expand_block_clear (operands))
10344 DONE;
10345 else
10346 FAIL;
10347 }")
10348
10349 ;; String/block move insn.
10350 ;; Argument 0 is the destination
10351 ;; Argument 1 is the source
10352 ;; Argument 2 is the length
10353 ;; Argument 3 is the alignment
10354
10355 (define_expand "movmemsi"
10356 [(parallel [(set (match_operand:BLK 0 "" "")
10357 (match_operand:BLK 1 "" ""))
10358 (use (match_operand:SI 2 "" ""))
10359 (use (match_operand:SI 3 "" ""))])]
10360 ""
10361 "
10362 {
10363 if (expand_block_move (operands))
10364 DONE;
10365 else
10366 FAIL;
10367 }")
10368
10369 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10370 ;; register allocator doesn't have a clue about allocating 8 word registers.
10371 ;; rD/rS = r5 is preferred, efficient form.
10372 (define_expand "movmemsi_8reg"
10373 [(parallel [(set (match_operand 0 "" "")
10374 (match_operand 1 "" ""))
10375 (use (match_operand 2 "" ""))
10376 (use (match_operand 3 "" ""))
10377 (clobber (reg:SI 5))
10378 (clobber (reg:SI 6))
10379 (clobber (reg:SI 7))
10380 (clobber (reg:SI 8))
10381 (clobber (reg:SI 9))
10382 (clobber (reg:SI 10))
10383 (clobber (reg:SI 11))
10384 (clobber (reg:SI 12))
10385 (clobber (match_scratch:SI 4 ""))])]
10386 "TARGET_STRING"
10387 "")
10388
10389 (define_insn ""
10390 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10391 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10392 (use (match_operand:SI 2 "immediate_operand" "i"))
10393 (use (match_operand:SI 3 "immediate_operand" "i"))
10394 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10395 (clobber (reg:SI 6))
10396 (clobber (reg:SI 7))
10397 (clobber (reg:SI 8))
10398 (clobber (reg:SI 9))
10399 (clobber (reg:SI 10))
10400 (clobber (reg:SI 11))
10401 (clobber (reg:SI 12))
10402 (clobber (match_scratch:SI 5 "=X"))]
10403 "TARGET_STRING
10404 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10405 || INTVAL (operands[2]) == 0)
10406 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10407 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10408 && REGNO (operands[4]) == 5"
10409 "lswi %4,%1,%2\;stswi %4,%0,%2"
10410 [(set_attr "type" "store_ux")
10411 (set_attr "cell_micro" "always")
10412 (set_attr "length" "8")])
10413
10414 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10415 ;; register allocator doesn't have a clue about allocating 6 word registers.
10416 ;; rD/rS = r5 is preferred, efficient form.
10417 (define_expand "movmemsi_6reg"
10418 [(parallel [(set (match_operand 0 "" "")
10419 (match_operand 1 "" ""))
10420 (use (match_operand 2 "" ""))
10421 (use (match_operand 3 "" ""))
10422 (clobber (reg:SI 5))
10423 (clobber (reg:SI 6))
10424 (clobber (reg:SI 7))
10425 (clobber (reg:SI 8))
10426 (clobber (reg:SI 9))
10427 (clobber (reg:SI 10))
10428 (clobber (match_scratch:SI 4 ""))])]
10429 "TARGET_STRING"
10430 "")
10431
10432 (define_insn ""
10433 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10434 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10435 (use (match_operand:SI 2 "immediate_operand" "i"))
10436 (use (match_operand:SI 3 "immediate_operand" "i"))
10437 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10438 (clobber (reg:SI 6))
10439 (clobber (reg:SI 7))
10440 (clobber (reg:SI 8))
10441 (clobber (reg:SI 9))
10442 (clobber (reg:SI 10))
10443 (clobber (match_scratch:SI 5 "=X"))]
10444 "TARGET_STRING
10445 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10446 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10447 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10448 && REGNO (operands[4]) == 5"
10449 "lswi %4,%1,%2\;stswi %4,%0,%2"
10450 [(set_attr "type" "store_ux")
10451 (set_attr "cell_micro" "always")
10452 (set_attr "length" "8")])
10453
10454 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10455 ;; problems with TImode.
10456 ;; rD/rS = r5 is preferred, efficient form.
10457 (define_expand "movmemsi_4reg"
10458 [(parallel [(set (match_operand 0 "" "")
10459 (match_operand 1 "" ""))
10460 (use (match_operand 2 "" ""))
10461 (use (match_operand 3 "" ""))
10462 (clobber (reg:SI 5))
10463 (clobber (reg:SI 6))
10464 (clobber (reg:SI 7))
10465 (clobber (reg:SI 8))
10466 (clobber (match_scratch:SI 4 ""))])]
10467 "TARGET_STRING"
10468 "")
10469
10470 (define_insn ""
10471 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10472 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10473 (use (match_operand:SI 2 "immediate_operand" "i"))
10474 (use (match_operand:SI 3 "immediate_operand" "i"))
10475 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10476 (clobber (reg:SI 6))
10477 (clobber (reg:SI 7))
10478 (clobber (reg:SI 8))
10479 (clobber (match_scratch:SI 5 "=X"))]
10480 "TARGET_STRING
10481 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10482 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10483 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10484 && REGNO (operands[4]) == 5"
10485 "lswi %4,%1,%2\;stswi %4,%0,%2"
10486 [(set_attr "type" "store_ux")
10487 (set_attr "cell_micro" "always")
10488 (set_attr "length" "8")])
10489
10490 ;; Move up to 8 bytes at a time.
10491 (define_expand "movmemsi_2reg"
10492 [(parallel [(set (match_operand 0 "" "")
10493 (match_operand 1 "" ""))
10494 (use (match_operand 2 "" ""))
10495 (use (match_operand 3 "" ""))
10496 (clobber (match_scratch:DI 4 ""))
10497 (clobber (match_scratch:SI 5 ""))])]
10498 "TARGET_STRING && ! TARGET_POWERPC64"
10499 "")
10500
10501 (define_insn ""
10502 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10503 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10504 (use (match_operand:SI 2 "immediate_operand" "i"))
10505 (use (match_operand:SI 3 "immediate_operand" "i"))
10506 (clobber (match_scratch:DI 4 "=&r"))
10507 (clobber (match_scratch:SI 5 "=X"))]
10508 "TARGET_STRING && ! TARGET_POWERPC64
10509 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10510 "lswi %4,%1,%2\;stswi %4,%0,%2"
10511 [(set_attr "type" "store_ux")
10512 (set_attr "cell_micro" "always")
10513 (set_attr "length" "8")])
10514
10515 ;; Move up to 4 bytes at a time.
10516 (define_expand "movmemsi_1reg"
10517 [(parallel [(set (match_operand 0 "" "")
10518 (match_operand 1 "" ""))
10519 (use (match_operand 2 "" ""))
10520 (use (match_operand 3 "" ""))
10521 (clobber (match_scratch:SI 4 ""))
10522 (clobber (match_scratch:SI 5 ""))])]
10523 "TARGET_STRING"
10524 "")
10525
10526 (define_insn ""
10527 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10528 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10529 (use (match_operand:SI 2 "immediate_operand" "i"))
10530 (use (match_operand:SI 3 "immediate_operand" "i"))
10531 (clobber (match_scratch:SI 4 "=&r"))
10532 (clobber (match_scratch:SI 5 "=X"))]
10533 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10534 "lswi %4,%1,%2\;stswi %4,%0,%2"
10535 [(set_attr "type" "store_ux")
10536 (set_attr "cell_micro" "always")
10537 (set_attr "length" "8")])
10538 \f
10539 ;; Define insns that do load or store with update. Some of these we can
10540 ;; get by using pre-decrement or pre-increment, but the hardware can also
10541 ;; do cases where the increment is not the size of the object.
10542 ;;
10543 ;; In all these cases, we use operands 0 and 1 for the register being
10544 ;; incremented because those are the operands that local-alloc will
10545 ;; tie and these are the pair most likely to be tieable (and the ones
10546 ;; that will benefit the most).
10547
10548 (define_insn "*movdi_update1"
10549 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10550 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10551 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10552 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10553 (plus:DI (match_dup 1) (match_dup 2)))]
10554 "TARGET_POWERPC64 && TARGET_UPDATE
10555 && (!avoiding_indexed_address_p (DImode)
10556 || !gpc_reg_operand (operands[2], DImode))"
10557 "@
10558 ldux %3,%0,%2
10559 ldu %3,%2(%0)"
10560 [(set_attr "type" "load_ux,load_u")])
10561
10562 (define_insn "movdi_<mode>_update"
10563 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10564 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10565 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10566 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10567 (plus:P (match_dup 1) (match_dup 2)))]
10568 "TARGET_POWERPC64 && TARGET_UPDATE
10569 && (!avoiding_indexed_address_p (Pmode)
10570 || !gpc_reg_operand (operands[2], Pmode)
10571 || (REG_P (operands[0])
10572 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10573 "@
10574 stdux %3,%0,%2
10575 stdu %3,%2(%0)"
10576 [(set_attr "type" "store_ux,store_u")])
10577
10578 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10579 ;; needed for stack allocation, even if the user passes -mno-update.
10580 (define_insn "movdi_<mode>_update_stack"
10581 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10582 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10583 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10584 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10585 (plus:P (match_dup 1) (match_dup 2)))]
10586 "TARGET_POWERPC64"
10587 "@
10588 stdux %3,%0,%2
10589 stdu %3,%2(%0)"
10590 [(set_attr "type" "store_ux,store_u")])
10591
10592 (define_insn "*movsi_update1"
10593 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10594 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10595 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10596 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10597 (plus:SI (match_dup 1) (match_dup 2)))]
10598 "TARGET_UPDATE
10599 && (!avoiding_indexed_address_p (SImode)
10600 || !gpc_reg_operand (operands[2], SImode))"
10601 "@
10602 lwzux %3,%0,%2
10603 lwzu %3,%2(%0)"
10604 [(set_attr "type" "load_ux,load_u")])
10605
10606 (define_insn "*movsi_update2"
10607 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10608 (sign_extend:DI
10609 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10610 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10611 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10612 (plus:DI (match_dup 1) (match_dup 2)))]
10613 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10614 && !avoiding_indexed_address_p (DImode)"
10615 "lwaux %3,%0,%2"
10616 [(set_attr "type" "load_ext_ux")])
10617
10618 (define_insn "movsi_update"
10619 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10620 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10621 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10622 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10623 (plus:SI (match_dup 1) (match_dup 2)))]
10624 "TARGET_UPDATE
10625 && (!avoiding_indexed_address_p (SImode)
10626 || !gpc_reg_operand (operands[2], SImode)
10627 || (REG_P (operands[0])
10628 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10629 "@
10630 stwux %3,%0,%2
10631 stwu %3,%2(%0)"
10632 [(set_attr "type" "store_ux,store_u")])
10633
10634 ;; This is an unconditional pattern; needed for stack allocation, even
10635 ;; if the user passes -mno-update.
10636 (define_insn "movsi_update_stack"
10637 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10638 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10639 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10640 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10641 (plus:SI (match_dup 1) (match_dup 2)))]
10642 ""
10643 "@
10644 stwux %3,%0,%2
10645 stwu %3,%2(%0)"
10646 [(set_attr "type" "store_ux,store_u")])
10647
10648 (define_insn "*movhi_update1"
10649 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10650 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10651 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10652 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10653 (plus:SI (match_dup 1) (match_dup 2)))]
10654 "TARGET_UPDATE
10655 && (!avoiding_indexed_address_p (SImode)
10656 || !gpc_reg_operand (operands[2], SImode))"
10657 "@
10658 lhzux %3,%0,%2
10659 lhzu %3,%2(%0)"
10660 [(set_attr "type" "load_ux,load_u")])
10661
10662 (define_insn "*movhi_update2"
10663 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10664 (zero_extend:SI
10665 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10666 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10667 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10668 (plus:SI (match_dup 1) (match_dup 2)))]
10669 "TARGET_UPDATE
10670 && (!avoiding_indexed_address_p (SImode)
10671 || !gpc_reg_operand (operands[2], SImode))"
10672 "@
10673 lhzux %3,%0,%2
10674 lhzu %3,%2(%0)"
10675 [(set_attr "type" "load_ux,load_u")])
10676
10677 (define_insn "*movhi_update3"
10678 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10679 (sign_extend:SI
10680 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10681 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10682 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10683 (plus:SI (match_dup 1) (match_dup 2)))]
10684 "TARGET_UPDATE && rs6000_gen_cell_microcode
10685 && (!avoiding_indexed_address_p (SImode)
10686 || !gpc_reg_operand (operands[2], SImode))"
10687 "@
10688 lhaux %3,%0,%2
10689 lhau %3,%2(%0)"
10690 [(set_attr "type" "load_ext_ux,load_ext_u")])
10691
10692 (define_insn "*movhi_update4"
10693 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10694 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10695 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10696 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10697 (plus:SI (match_dup 1) (match_dup 2)))]
10698 "TARGET_UPDATE
10699 && (!avoiding_indexed_address_p (SImode)
10700 || !gpc_reg_operand (operands[2], SImode))"
10701 "@
10702 sthux %3,%0,%2
10703 sthu %3,%2(%0)"
10704 [(set_attr "type" "store_ux,store_u")])
10705
10706 (define_insn "*movqi_update1"
10707 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10708 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10709 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10710 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10711 (plus:SI (match_dup 1) (match_dup 2)))]
10712 "TARGET_UPDATE
10713 && (!avoiding_indexed_address_p (SImode)
10714 || !gpc_reg_operand (operands[2], SImode))"
10715 "@
10716 lbzux %3,%0,%2
10717 lbzu %3,%2(%0)"
10718 [(set_attr "type" "load_ux,load_u")])
10719
10720 (define_insn "*movqi_update2"
10721 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10722 (zero_extend:SI
10723 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10724 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10725 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10726 (plus:SI (match_dup 1) (match_dup 2)))]
10727 "TARGET_UPDATE
10728 && (!avoiding_indexed_address_p (SImode)
10729 || !gpc_reg_operand (operands[2], SImode))"
10730 "@
10731 lbzux %3,%0,%2
10732 lbzu %3,%2(%0)"
10733 [(set_attr "type" "load_ux,load_u")])
10734
10735 (define_insn "*movqi_update3"
10736 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10737 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10738 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10739 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10740 (plus:SI (match_dup 1) (match_dup 2)))]
10741 "TARGET_UPDATE
10742 && (!avoiding_indexed_address_p (SImode)
10743 || !gpc_reg_operand (operands[2], SImode))"
10744 "@
10745 stbux %3,%0,%2
10746 stbu %3,%2(%0)"
10747 [(set_attr "type" "store_ux,store_u")])
10748
10749 (define_insn "*movsf_update1"
10750 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10751 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10752 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10753 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10754 (plus:SI (match_dup 1) (match_dup 2)))]
10755 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10756 && (!avoiding_indexed_address_p (SImode)
10757 || !gpc_reg_operand (operands[2], SImode))"
10758 "@
10759 lfsux %3,%0,%2
10760 lfsu %3,%2(%0)"
10761 [(set_attr "type" "fpload_ux,fpload_u")])
10762
10763 (define_insn "*movsf_update2"
10764 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10765 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10766 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10767 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10768 (plus:SI (match_dup 1) (match_dup 2)))]
10769 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10770 && (!avoiding_indexed_address_p (SImode)
10771 || !gpc_reg_operand (operands[2], SImode))"
10772 "@
10773 stfsux %3,%0,%2
10774 stfsu %3,%2(%0)"
10775 [(set_attr "type" "fpstore_ux,fpstore_u")])
10776
10777 (define_insn "*movsf_update3"
10778 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10779 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10780 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10781 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10782 (plus:SI (match_dup 1) (match_dup 2)))]
10783 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10784 && (!avoiding_indexed_address_p (SImode)
10785 || !gpc_reg_operand (operands[2], SImode))"
10786 "@
10787 lwzux %3,%0,%2
10788 lwzu %3,%2(%0)"
10789 [(set_attr "type" "load_ux,load_u")])
10790
10791 (define_insn "*movsf_update4"
10792 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10793 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10794 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10795 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10796 (plus:SI (match_dup 1) (match_dup 2)))]
10797 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10798 && (!avoiding_indexed_address_p (SImode)
10799 || !gpc_reg_operand (operands[2], SImode))"
10800 "@
10801 stwux %3,%0,%2
10802 stwu %3,%2(%0)"
10803 [(set_attr "type" "store_ux,store_u")])
10804
10805 (define_insn "*movdf_update1"
10806 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10807 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10808 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10809 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10810 (plus:SI (match_dup 1) (match_dup 2)))]
10811 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10812 && (!avoiding_indexed_address_p (SImode)
10813 || !gpc_reg_operand (operands[2], SImode))"
10814 "@
10815 lfdux %3,%0,%2
10816 lfdu %3,%2(%0)"
10817 [(set_attr "type" "fpload_ux,fpload_u")])
10818
10819 (define_insn "*movdf_update2"
10820 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10821 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10822 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10823 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10824 (plus:SI (match_dup 1) (match_dup 2)))]
10825 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10826 && (!avoiding_indexed_address_p (SImode)
10827 || !gpc_reg_operand (operands[2], SImode))"
10828 "@
10829 stfdux %3,%0,%2
10830 stfdu %3,%2(%0)"
10831 [(set_attr "type" "fpstore_ux,fpstore_u")])
10832
10833
10834 ;; After inserting conditional returns we can sometimes have
10835 ;; unnecessary register moves. Unfortunately we cannot have a
10836 ;; modeless peephole here, because some single SImode sets have early
10837 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10838 ;; sequences, using get_attr_length here will smash the operands
10839 ;; array. Neither is there an early_cobbler_p predicate.
10840 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10841 (define_peephole2
10842 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10843 (match_operand:DF 1 "any_operand" ""))
10844 (set (match_operand:DF 2 "gpc_reg_operand" "")
10845 (match_dup 0))]
10846 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10847 && peep2_reg_dead_p (2, operands[0])"
10848 [(set (match_dup 2) (match_dup 1))])
10849
10850 (define_peephole2
10851 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10852 (match_operand:SF 1 "any_operand" ""))
10853 (set (match_operand:SF 2 "gpc_reg_operand" "")
10854 (match_dup 0))]
10855 "peep2_reg_dead_p (2, operands[0])"
10856 [(set (match_dup 2) (match_dup 1))])
10857
10858 \f
10859 ;; TLS support.
10860
10861 ;; Mode attributes for different ABIs.
10862 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10863 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10864 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10865 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10866
10867 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10868 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10869 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10870 (match_operand 4 "" "g")))
10871 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10872 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10873 UNSPEC_TLSGD)
10874 (clobber (reg:SI LR_REGNO))]
10875 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10876 {
10877 if (TARGET_CMODEL != CMODEL_SMALL)
10878 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
10879 "bl %z3\;nop";
10880 else
10881 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
10882 }
10883 "&& TARGET_TLS_MARKERS"
10884 [(set (match_dup 0)
10885 (unspec:TLSmode [(match_dup 1)
10886 (match_dup 2)]
10887 UNSPEC_TLSGD))
10888 (parallel [(set (match_dup 0)
10889 (call (mem:TLSmode (match_dup 3))
10890 (match_dup 4)))
10891 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10892 (clobber (reg:SI LR_REGNO))])]
10893 ""
10894 [(set_attr "type" "two")
10895 (set (attr "length")
10896 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10897 (const_int 16)
10898 (const_int 12)))])
10899
10900 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10901 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10902 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10903 (match_operand 4 "" "g")))
10904 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10905 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10906 UNSPEC_TLSGD)
10907 (clobber (reg:SI LR_REGNO))]
10908 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10909 {
10910 if (flag_pic)
10911 {
10912 if (TARGET_SECURE_PLT && flag_pic == 2)
10913 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10914 else
10915 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10916 }
10917 else
10918 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10919 }
10920 "&& TARGET_TLS_MARKERS"
10921 [(set (match_dup 0)
10922 (unspec:TLSmode [(match_dup 1)
10923 (match_dup 2)]
10924 UNSPEC_TLSGD))
10925 (parallel [(set (match_dup 0)
10926 (call (mem:TLSmode (match_dup 3))
10927 (match_dup 4)))
10928 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10929 (clobber (reg:SI LR_REGNO))])]
10930 ""
10931 [(set_attr "type" "two")
10932 (set_attr "length" "8")])
10933
10934 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
10935 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10936 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10937 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10938 UNSPEC_TLSGD))]
10939 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10940 "addi %0,%1,%2@got@tlsgd"
10941 "&& TARGET_CMODEL != CMODEL_SMALL"
10942 [(set (match_dup 3)
10943 (high:TLSmode
10944 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
10945 (set (match_dup 0)
10946 (lo_sum:TLSmode (match_dup 3)
10947 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
10948 "
10949 {
10950 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10951 }"
10952 [(set (attr "length")
10953 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10954 (const_int 8)
10955 (const_int 4)))])
10956
10957 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
10958 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10959 (high:TLSmode
10960 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10961 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10962 UNSPEC_TLSGD)))]
10963 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10964 "addis %0,%1,%2@got@tlsgd@ha"
10965 [(set_attr "length" "4")])
10966
10967 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
10968 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10969 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10970 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10971 UNSPEC_TLSGD)))]
10972 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10973 "addi %0,%1,%2@got@tlsgd@l"
10974 [(set_attr "length" "4")])
10975
10976 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10977 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10978 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10979 (match_operand 2 "" "g")))
10980 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10981 UNSPEC_TLSGD)
10982 (clobber (reg:SI LR_REGNO))]
10983 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10984 "bl %z1(%3@tlsgd)\;nop"
10985 [(set_attr "type" "branch")
10986 (set_attr "length" "8")])
10987
10988 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10989 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10990 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10991 (match_operand 2 "" "g")))
10992 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10993 UNSPEC_TLSGD)
10994 (clobber (reg:SI LR_REGNO))]
10995 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10996 {
10997 if (flag_pic)
10998 {
10999 if (TARGET_SECURE_PLT && flag_pic == 2)
11000 return "bl %z1+32768(%3@tlsgd)@plt";
11001 return "bl %z1(%3@tlsgd)@plt";
11002 }
11003 return "bl %z1(%3@tlsgd)";
11004 }
11005 [(set_attr "type" "branch")
11006 (set_attr "length" "4")])
11007
11008 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11009 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11010 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11011 (match_operand 3 "" "g")))
11012 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11013 UNSPEC_TLSLD)
11014 (clobber (reg:SI LR_REGNO))]
11015 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11016 {
11017 if (TARGET_CMODEL != CMODEL_SMALL)
11018 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
11019 "bl %z2\;nop";
11020 else
11021 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
11022 }
11023 "&& TARGET_TLS_MARKERS"
11024 [(set (match_dup 0)
11025 (unspec:TLSmode [(match_dup 1)]
11026 UNSPEC_TLSLD))
11027 (parallel [(set (match_dup 0)
11028 (call (mem:TLSmode (match_dup 2))
11029 (match_dup 3)))
11030 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11031 (clobber (reg:SI LR_REGNO))])]
11032 ""
11033 [(set_attr "type" "two")
11034 (set (attr "length")
11035 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11036 (const_int 16)
11037 (const_int 12)))])
11038
11039 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11040 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11041 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11042 (match_operand 3 "" "g")))
11043 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11044 UNSPEC_TLSLD)
11045 (clobber (reg:SI LR_REGNO))]
11046 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11047 {
11048 if (flag_pic)
11049 {
11050 if (TARGET_SECURE_PLT && flag_pic == 2)
11051 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11052 else
11053 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11054 }
11055 else
11056 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11057 }
11058 "&& TARGET_TLS_MARKERS"
11059 [(set (match_dup 0)
11060 (unspec:TLSmode [(match_dup 1)]
11061 UNSPEC_TLSLD))
11062 (parallel [(set (match_dup 0)
11063 (call (mem:TLSmode (match_dup 2))
11064 (match_dup 3)))
11065 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11066 (clobber (reg:SI LR_REGNO))])]
11067 ""
11068 [(set_attr "length" "8")])
11069
11070 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11071 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11072 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11073 UNSPEC_TLSLD))]
11074 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11075 "addi %0,%1,%&@got@tlsld"
11076 "&& TARGET_CMODEL != CMODEL_SMALL"
11077 [(set (match_dup 2)
11078 (high:TLSmode
11079 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
11080 (set (match_dup 0)
11081 (lo_sum:TLSmode (match_dup 2)
11082 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11083 "
11084 {
11085 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11086 }"
11087 [(set (attr "length")
11088 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11089 (const_int 8)
11090 (const_int 4)))])
11091
11092 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11093 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11094 (high:TLSmode
11095 (unspec:TLSmode [(const_int 0)
11096 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11097 UNSPEC_TLSLD)))]
11098 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11099 "addis %0,%1,%&@got@tlsld@ha"
11100 [(set_attr "length" "4")])
11101
11102 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11103 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11104 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11105 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11106 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11107 "addi %0,%1,%&@got@tlsld@l"
11108 [(set_attr "length" "4")])
11109
11110 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11111 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11112 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11113 (match_operand 2 "" "g")))
11114 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11115 (clobber (reg:SI LR_REGNO))]
11116 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11117 "bl %z1(%&@tlsld)\;nop"
11118 [(set_attr "type" "branch")
11119 (set_attr "length" "8")])
11120
11121 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11122 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11123 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11124 (match_operand 2 "" "g")))
11125 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11126 (clobber (reg:SI LR_REGNO))]
11127 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11128 {
11129 if (flag_pic)
11130 {
11131 if (TARGET_SECURE_PLT && flag_pic == 2)
11132 return "bl %z1+32768(%&@tlsld)@plt";
11133 return "bl %z1(%&@tlsld)@plt";
11134 }
11135 return "bl %z1(%&@tlsld)";
11136 }
11137 [(set_attr "type" "branch")
11138 (set_attr "length" "4")])
11139
11140 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11141 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11142 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11143 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11144 UNSPEC_TLSDTPREL))]
11145 "HAVE_AS_TLS"
11146 "addi %0,%1,%2@dtprel")
11147
11148 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11149 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11150 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11151 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11152 UNSPEC_TLSDTPRELHA))]
11153 "HAVE_AS_TLS"
11154 "addis %0,%1,%2@dtprel@ha")
11155
11156 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11157 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11158 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11159 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11160 UNSPEC_TLSDTPRELLO))]
11161 "HAVE_AS_TLS"
11162 "addi %0,%1,%2@dtprel@l")
11163
11164 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11165 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11166 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11167 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11168 UNSPEC_TLSGOTDTPREL))]
11169 "HAVE_AS_TLS"
11170 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11171 "&& TARGET_CMODEL != CMODEL_SMALL"
11172 [(set (match_dup 3)
11173 (high:TLSmode
11174 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
11175 (set (match_dup 0)
11176 (lo_sum:TLSmode (match_dup 3)
11177 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11178 "
11179 {
11180 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11181 }"
11182 [(set (attr "length")
11183 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11184 (const_int 8)
11185 (const_int 4)))])
11186
11187 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11188 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11189 (high:TLSmode
11190 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11191 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11192 UNSPEC_TLSGOTDTPREL)))]
11193 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11194 "addis %0,%1,%2@got@dtprel@ha"
11195 [(set_attr "length" "4")])
11196
11197 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11198 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11199 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11200 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11201 UNSPEC_TLSGOTDTPREL)))]
11202 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11203 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11204 [(set_attr "length" "4")])
11205
11206 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11208 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11209 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11210 UNSPEC_TLSTPREL))]
11211 "HAVE_AS_TLS"
11212 "addi %0,%1,%2@tprel")
11213
11214 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11215 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11216 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11217 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11218 UNSPEC_TLSTPRELHA))]
11219 "HAVE_AS_TLS"
11220 "addis %0,%1,%2@tprel@ha")
11221
11222 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11223 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11224 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11225 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11226 UNSPEC_TLSTPRELLO))]
11227 "HAVE_AS_TLS"
11228 "addi %0,%1,%2@tprel@l")
11229
11230 ;; "b" output constraint here and on tls_tls input to support linker tls
11231 ;; optimization. The linker may edit the instructions emitted by a
11232 ;; tls_got_tprel/tls_tls pair to addis,addi.
11233 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11234 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11235 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11236 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11237 UNSPEC_TLSGOTTPREL))]
11238 "HAVE_AS_TLS"
11239 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11240 "&& TARGET_CMODEL != CMODEL_SMALL"
11241 [(set (match_dup 3)
11242 (high:TLSmode
11243 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
11244 (set (match_dup 0)
11245 (lo_sum:TLSmode (match_dup 3)
11246 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11247 "
11248 {
11249 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11250 }"
11251 [(set (attr "length")
11252 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11253 (const_int 8)
11254 (const_int 4)))])
11255
11256 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11257 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11258 (high:TLSmode
11259 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11260 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11261 UNSPEC_TLSGOTTPREL)))]
11262 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11263 "addis %0,%1,%2@got@tprel@ha"
11264 [(set_attr "length" "4")])
11265
11266 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11267 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11268 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11269 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11270 UNSPEC_TLSGOTTPREL)))]
11271 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11272 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11273 [(set_attr "length" "4")])
11274
11275 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11276 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11277 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11278 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11279 UNSPEC_TLSTLS))]
11280 "TARGET_ELF && HAVE_AS_TLS"
11281 "add %0,%1,%2@tls")
11282
11283 (define_expand "tls_get_tpointer"
11284 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11285 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
11286 "TARGET_XCOFF && HAVE_AS_TLS"
11287 "
11288 {
11289 emit_insn (gen_tls_get_tpointer_internal ());
11290 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
11291 DONE;
11292 }")
11293
11294 (define_insn "tls_get_tpointer_internal"
11295 [(set (reg:SI 3)
11296 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
11297 (clobber (reg:SI LR_REGNO))]
11298 "TARGET_XCOFF && HAVE_AS_TLS"
11299 "bla __get_tpointer")
11300
11301 (define_expand "tls_get_addr<mode>"
11302 [(set (match_operand:P 0 "gpc_reg_operand" "")
11303 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
11304 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
11305 "TARGET_XCOFF && HAVE_AS_TLS"
11306 "
11307 {
11308 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
11309 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
11310 emit_insn (gen_tls_get_addr_internal<mode> ());
11311 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
11312 DONE;
11313 }")
11314
11315 (define_insn "tls_get_addr_internal<mode>"
11316 [(set (reg:P 3)
11317 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
11318 (clobber (reg:P 0))
11319 (clobber (reg:P 4))
11320 (clobber (reg:P 5))
11321 (clobber (reg:P 11))
11322 (clobber (reg:CC CR0_REGNO))
11323 (clobber (reg:P LR_REGNO))]
11324 "TARGET_XCOFF && HAVE_AS_TLS"
11325 "bla __tls_get_addr")
11326 \f
11327 ;; Next come insns related to the calling sequence.
11328 ;;
11329 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11330 ;; We move the back-chain and decrement the stack pointer.
11331
11332 (define_expand "allocate_stack"
11333 [(set (match_operand 0 "gpc_reg_operand" "")
11334 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11335 (set (reg 1)
11336 (minus (reg 1) (match_dup 1)))]
11337 ""
11338 "
11339 { rtx chain = gen_reg_rtx (Pmode);
11340 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11341 rtx neg_op0;
11342 rtx insn, par, set, mem;
11343
11344 emit_move_insn (chain, stack_bot);
11345
11346 /* Check stack bounds if necessary. */
11347 if (crtl->limit_stack)
11348 {
11349 rtx available;
11350 available = expand_binop (Pmode, sub_optab,
11351 stack_pointer_rtx, stack_limit_rtx,
11352 NULL_RTX, 1, OPTAB_WIDEN);
11353 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11354 }
11355
11356 if (GET_CODE (operands[1]) != CONST_INT
11357 || INTVAL (operands[1]) < -32767
11358 || INTVAL (operands[1]) > 32768)
11359 {
11360 neg_op0 = gen_reg_rtx (Pmode);
11361 if (TARGET_32BIT)
11362 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11363 else
11364 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11365 }
11366 else
11367 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11368
11369 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11370 : gen_movdi_di_update_stack))
11371 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11372 chain));
11373 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11374 it now and set the alias set/attributes. The above gen_*_update
11375 calls will generate a PARALLEL with the MEM set being the first
11376 operation. */
11377 par = PATTERN (insn);
11378 gcc_assert (GET_CODE (par) == PARALLEL);
11379 set = XVECEXP (par, 0, 0);
11380 gcc_assert (GET_CODE (set) == SET);
11381 mem = SET_DEST (set);
11382 gcc_assert (MEM_P (mem));
11383 MEM_NOTRAP_P (mem) = 1;
11384 set_mem_alias_set (mem, get_frame_alias_set ());
11385
11386 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11387 DONE;
11388 }")
11389
11390 ;; These patterns say how to save and restore the stack pointer. We need not
11391 ;; save the stack pointer at function level since we are careful to
11392 ;; preserve the backchain. At block level, we have to restore the backchain
11393 ;; when we restore the stack pointer.
11394 ;;
11395 ;; For nonlocal gotos, we must save both the stack pointer and its
11396 ;; backchain and restore both. Note that in the nonlocal case, the
11397 ;; save area is a memory location.
11398
11399 (define_expand "save_stack_function"
11400 [(match_operand 0 "any_operand" "")
11401 (match_operand 1 "any_operand" "")]
11402 ""
11403 "DONE;")
11404
11405 (define_expand "restore_stack_function"
11406 [(match_operand 0 "any_operand" "")
11407 (match_operand 1 "any_operand" "")]
11408 ""
11409 "DONE;")
11410
11411 ;; Adjust stack pointer (op0) to a new value (op1).
11412 ;; First copy old stack backchain to new location, and ensure that the
11413 ;; scheduler won't reorder the sp assignment before the backchain write.
11414 (define_expand "restore_stack_block"
11415 [(set (match_dup 2) (match_dup 3))
11416 (set (match_dup 4) (match_dup 2))
11417 (match_dup 5)
11418 (set (match_operand 0 "register_operand" "")
11419 (match_operand 1 "register_operand" ""))]
11420 ""
11421 "
11422 {
11423 rtvec p;
11424
11425 operands[1] = force_reg (Pmode, operands[1]);
11426 operands[2] = gen_reg_rtx (Pmode);
11427 operands[3] = gen_frame_mem (Pmode, operands[0]);
11428 operands[4] = gen_frame_mem (Pmode, operands[1]);
11429 p = rtvec_alloc (1);
11430 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11431 gen_frame_mem (BLKmode, operands[0]),
11432 const0_rtx);
11433 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11434 }")
11435
11436 (define_expand "save_stack_nonlocal"
11437 [(set (match_dup 3) (match_dup 4))
11438 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11439 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11440 ""
11441 "
11442 {
11443 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11444
11445 /* Copy the backchain to the first word, sp to the second. */
11446 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11447 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11448 operands[3] = gen_reg_rtx (Pmode);
11449 operands[4] = gen_frame_mem (Pmode, operands[1]);
11450 }")
11451
11452 (define_expand "restore_stack_nonlocal"
11453 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11454 (set (match_dup 3) (match_dup 4))
11455 (set (match_dup 5) (match_dup 2))
11456 (match_dup 6)
11457 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11458 ""
11459 "
11460 {
11461 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11462 rtvec p;
11463
11464 /* Restore the backchain from the first word, sp from the second. */
11465 operands[2] = gen_reg_rtx (Pmode);
11466 operands[3] = gen_reg_rtx (Pmode);
11467 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11468 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11469 operands[5] = gen_frame_mem (Pmode, operands[3]);
11470 p = rtvec_alloc (1);
11471 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11472 gen_frame_mem (BLKmode, operands[0]),
11473 const0_rtx);
11474 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11475 }")
11476 \f
11477 ;; TOC register handling.
11478
11479 ;; Code to initialize the TOC register...
11480
11481 (define_insn "load_toc_aix_si"
11482 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11483 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11484 (use (reg:SI 2))])]
11485 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11486 "*
11487 {
11488 char buf[30];
11489 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11490 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11491 operands[2] = gen_rtx_REG (Pmode, 2);
11492 return \"lwz %0,%1(%2)\";
11493 }"
11494 [(set_attr "type" "load")])
11495
11496 (define_insn "load_toc_aix_di"
11497 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11498 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11499 (use (reg:DI 2))])]
11500 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11501 "*
11502 {
11503 char buf[30];
11504 #ifdef TARGET_RELOCATABLE
11505 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11506 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11507 #else
11508 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11509 #endif
11510 if (TARGET_ELF)
11511 strcat (buf, \"@toc\");
11512 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11513 operands[2] = gen_rtx_REG (Pmode, 2);
11514 return \"ld %0,%1(%2)\";
11515 }"
11516 [(set_attr "type" "load")])
11517
11518 (define_insn "load_toc_v4_pic_si"
11519 [(set (reg:SI LR_REGNO)
11520 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11521 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11522 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11523 [(set_attr "type" "branch")
11524 (set_attr "length" "4")])
11525
11526 (define_expand "load_toc_v4_PIC_1"
11527 [(parallel [(set (reg:SI LR_REGNO)
11528 (match_operand:SI 0 "immediate_operand" "s"))
11529 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11530 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11531 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11532 "")
11533
11534 (define_insn "load_toc_v4_PIC_1_normal"
11535 [(set (reg:SI LR_REGNO)
11536 (match_operand:SI 0 "immediate_operand" "s"))
11537 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11538 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
11539 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11540 "bcl 20,31,%0\\n%0:"
11541 [(set_attr "type" "branch")
11542 (set_attr "length" "4")])
11543
11544 (define_insn "load_toc_v4_PIC_1_476"
11545 [(set (reg:SI LR_REGNO)
11546 (match_operand:SI 0 "immediate_operand" "s"))
11547 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11548 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
11549 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11550 "*
11551 {
11552 char name[32];
11553 static char templ[32];
11554
11555 get_ppc476_thunk_name (name);
11556 sprintf (templ, \"bl %s\\n%%0:\", name);
11557 return templ;
11558 }"
11559 [(set_attr "type" "branch")
11560 (set_attr "length" "4")])
11561
11562 (define_expand "load_toc_v4_PIC_1b"
11563 [(parallel [(set (reg:SI LR_REGNO)
11564 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11565 (label_ref (match_operand 1 "" ""))]
11566 UNSPEC_TOCPTR))
11567 (match_dup 1)])]
11568 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11569 "")
11570
11571 (define_insn "load_toc_v4_PIC_1b_normal"
11572 [(set (reg:SI LR_REGNO)
11573 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11574 (label_ref (match_operand 1 "" ""))]
11575 UNSPEC_TOCPTR))
11576 (match_dup 1)]
11577 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11578 "bcl 20,31,$+8\;.long %0-$"
11579 [(set_attr "type" "branch")
11580 (set_attr "length" "8")])
11581
11582 (define_insn "load_toc_v4_PIC_1b_476"
11583 [(set (reg:SI LR_REGNO)
11584 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11585 (label_ref (match_operand 1 "" ""))]
11586 UNSPEC_TOCPTR))
11587 (match_dup 1)]
11588 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11589 "*
11590 {
11591 char name[32];
11592 static char templ[32];
11593
11594 get_ppc476_thunk_name (name);
11595 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11596 return templ;
11597 }"
11598 [(set_attr "type" "branch")
11599 (set_attr "length" "16")])
11600
11601 (define_insn "load_toc_v4_PIC_2"
11602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11603 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11604 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11605 (match_operand:SI 3 "immediate_operand" "s")))))]
11606 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11607 "lwz %0,%2-%3(%1)"
11608 [(set_attr "type" "load")])
11609
11610 (define_insn "load_toc_v4_PIC_3b"
11611 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11612 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11613 (high:SI
11614 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11615 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11616 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11617 "addis %0,%1,%2-%3@ha")
11618
11619 (define_insn "load_toc_v4_PIC_3c"
11620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11621 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11622 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11623 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11624 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11625 "addi %0,%1,%2-%3@l")
11626
11627 ;; If the TOC is shared over a translation unit, as happens with all
11628 ;; the kinds of PIC that we support, we need to restore the TOC
11629 ;; pointer only when jumping over units of translation.
11630 ;; On Darwin, we need to reload the picbase.
11631
11632 (define_expand "builtin_setjmp_receiver"
11633 [(use (label_ref (match_operand 0 "" "")))]
11634 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11635 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11636 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11637 "
11638 {
11639 #if TARGET_MACHO
11640 if (DEFAULT_ABI == ABI_DARWIN)
11641 {
11642 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11643 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11644 rtx tmplabrtx;
11645 char tmplab[20];
11646
11647 crtl->uses_pic_offset_table = 1;
11648 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11649 CODE_LABEL_NUMBER (operands[0]));
11650 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11651
11652 emit_insn (gen_load_macho_picbase (tmplabrtx));
11653 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11654 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11655 }
11656 else
11657 #endif
11658 rs6000_emit_load_toc_table (FALSE);
11659 DONE;
11660 }")
11661
11662 ;; Largetoc support
11663 (define_insn "*largetoc_high"
11664 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11665 (high:DI
11666 (unspec [(match_operand:DI 1 "" "")
11667 (match_operand:DI 2 "gpc_reg_operand" "b")]
11668 UNSPEC_TOCREL)))]
11669 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11670 "addis %0,%2,%1@toc@ha")
11671
11672 (define_insn "*largetoc_high_aix<mode>"
11673 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11674 (high:P
11675 (unspec [(match_operand:P 1 "" "")
11676 (match_operand:P 2 "gpc_reg_operand" "b")]
11677 UNSPEC_TOCREL)))]
11678 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11679 "addis %0,%1@u(%2)")
11680
11681 (define_insn "*largetoc_high_plus"
11682 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11683 (high:DI
11684 (plus:DI
11685 (unspec [(match_operand:DI 1 "" "")
11686 (match_operand:DI 2 "gpc_reg_operand" "b")]
11687 UNSPEC_TOCREL)
11688 (match_operand 3 "const_int_operand" "n"))))]
11689 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11690 "addis %0,%2,%1+%3@toc@ha")
11691
11692 (define_insn "*largetoc_high_plus_aix<mode>"
11693 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11694 (high:P
11695 (plus:P
11696 (unspec [(match_operand:P 1 "" "")
11697 (match_operand:P 2 "gpc_reg_operand" "b")]
11698 UNSPEC_TOCREL)
11699 (match_operand 3 "const_int_operand" "n"))))]
11700 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11701 "addis %0,%1+%3@u(%2)")
11702
11703 (define_insn "*largetoc_low"
11704 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11705 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
11706 (match_operand:DI 2 "" "")))]
11707 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11708 "@
11709 addi %0,%1,%2@l
11710 addic %0,%1,%2@l")
11711
11712 (define_insn "*largetoc_low_aix<mode>"
11713 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11714 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
11715 (match_operand:P 2 "" "")))]
11716 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11717 "la %0,%2@l(%1)")
11718
11719 (define_insn_and_split "*tocref<mode>"
11720 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11721 (match_operand:P 1 "small_toc_ref" "R"))]
11722 "TARGET_TOC"
11723 "la %0,%a1"
11724 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
11725 [(set (match_dup 0) (high:P (match_dup 1)))
11726 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
11727
11728 ;; Elf specific ways of loading addresses for non-PIC code.
11729 ;; The output of this could be r0, but we make a very strong
11730 ;; preference for a base register because it will usually
11731 ;; be needed there.
11732 (define_insn "elf_high"
11733 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11734 (high:SI (match_operand 1 "" "")))]
11735 "TARGET_ELF && ! TARGET_64BIT"
11736 "lis %0,%1@ha")
11737
11738 (define_insn "elf_low"
11739 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11740 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11741 (match_operand 2 "" "")))]
11742 "TARGET_ELF && ! TARGET_64BIT"
11743 "@
11744 la %0,%2@l(%1)
11745 addic %0,%1,%K2")
11746 \f
11747 ;; Call and call_value insns
11748 (define_expand "call"
11749 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11750 (match_operand 1 "" ""))
11751 (use (match_operand 2 "" ""))
11752 (clobber (reg:SI LR_REGNO))])]
11753 ""
11754 "
11755 {
11756 #if TARGET_MACHO
11757 if (MACHOPIC_INDIRECT)
11758 operands[0] = machopic_indirect_call_target (operands[0]);
11759 #endif
11760
11761 gcc_assert (GET_CODE (operands[0]) == MEM);
11762 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11763
11764 operands[0] = XEXP (operands[0], 0);
11765
11766 if (GET_CODE (operands[0]) != SYMBOL_REF
11767 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11768 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11769 {
11770 if (INTVAL (operands[2]) & CALL_LONG)
11771 operands[0] = rs6000_longcall_ref (operands[0]);
11772
11773 switch (DEFAULT_ABI)
11774 {
11775 case ABI_V4:
11776 case ABI_DARWIN:
11777 operands[0] = force_reg (Pmode, operands[0]);
11778 break;
11779
11780 case ABI_AIX:
11781 /* AIX function pointers are really pointers to a three word
11782 area. */
11783 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
11784 DONE;
11785
11786 default:
11787 gcc_unreachable ();
11788 }
11789 }
11790 }")
11791
11792 (define_expand "call_value"
11793 [(parallel [(set (match_operand 0 "" "")
11794 (call (mem:SI (match_operand 1 "address_operand" ""))
11795 (match_operand 2 "" "")))
11796 (use (match_operand 3 "" ""))
11797 (clobber (reg:SI LR_REGNO))])]
11798 ""
11799 "
11800 {
11801 #if TARGET_MACHO
11802 if (MACHOPIC_INDIRECT)
11803 operands[1] = machopic_indirect_call_target (operands[1]);
11804 #endif
11805
11806 gcc_assert (GET_CODE (operands[1]) == MEM);
11807 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11808
11809 operands[1] = XEXP (operands[1], 0);
11810
11811 if (GET_CODE (operands[1]) != SYMBOL_REF
11812 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11813 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11814 {
11815 if (INTVAL (operands[3]) & CALL_LONG)
11816 operands[1] = rs6000_longcall_ref (operands[1]);
11817
11818 switch (DEFAULT_ABI)
11819 {
11820 case ABI_V4:
11821 case ABI_DARWIN:
11822 operands[1] = force_reg (Pmode, operands[1]);
11823 break;
11824
11825 case ABI_AIX:
11826 /* AIX function pointers are really pointers to a three word
11827 area. */
11828 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
11829 DONE;
11830
11831 default:
11832 gcc_unreachable ();
11833 }
11834 }
11835 }")
11836
11837 ;; Call to function in current module. No TOC pointer reload needed.
11838 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11839 ;; either the function was not prototyped, or it was prototyped as a
11840 ;; variable argument function. It is > 0 if FP registers were passed
11841 ;; and < 0 if they were not.
11842
11843 (define_insn "*call_local32"
11844 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11845 (match_operand 1 "" "g,g"))
11846 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11847 (clobber (reg:SI LR_REGNO))]
11848 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11849 "*
11850 {
11851 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11852 output_asm_insn (\"crxor 6,6,6\", operands);
11853
11854 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11855 output_asm_insn (\"creqv 6,6,6\", operands);
11856
11857 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11858 }"
11859 [(set_attr "type" "branch")
11860 (set_attr "length" "4,8")])
11861
11862 (define_insn "*call_local64"
11863 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11864 (match_operand 1 "" "g,g"))
11865 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11866 (clobber (reg:SI LR_REGNO))]
11867 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11868 "*
11869 {
11870 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11871 output_asm_insn (\"crxor 6,6,6\", operands);
11872
11873 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11874 output_asm_insn (\"creqv 6,6,6\", operands);
11875
11876 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11877 }"
11878 [(set_attr "type" "branch")
11879 (set_attr "length" "4,8")])
11880
11881 (define_insn "*call_value_local32"
11882 [(set (match_operand 0 "" "")
11883 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11884 (match_operand 2 "" "g,g")))
11885 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11886 (clobber (reg:SI LR_REGNO))]
11887 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11888 "*
11889 {
11890 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11891 output_asm_insn (\"crxor 6,6,6\", operands);
11892
11893 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11894 output_asm_insn (\"creqv 6,6,6\", operands);
11895
11896 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11897 }"
11898 [(set_attr "type" "branch")
11899 (set_attr "length" "4,8")])
11900
11901
11902 (define_insn "*call_value_local64"
11903 [(set (match_operand 0 "" "")
11904 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11905 (match_operand 2 "" "g,g")))
11906 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11907 (clobber (reg:SI LR_REGNO))]
11908 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11909 "*
11910 {
11911 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11912 output_asm_insn (\"crxor 6,6,6\", operands);
11913
11914 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11915 output_asm_insn (\"creqv 6,6,6\", operands);
11916
11917 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11918 }"
11919 [(set_attr "type" "branch")
11920 (set_attr "length" "4,8")])
11921
11922 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11923 ;; Operand0 is the addresss of the function to call
11924 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11925 ;; Operand2 is the location in the function descriptor to load r2 from
11926 ;; Operand3 is the stack location to hold the current TOC pointer
11927
11928 (define_insn "call_indirect_aix<ptrsize>"
11929 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11930 (match_operand 1 "" "g,g"))
11931 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11932 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11933 (use (reg:P STATIC_CHAIN_REGNUM))
11934 (clobber (reg:P LR_REGNO))]
11935 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11936 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11937 [(set_attr "type" "jmpreg")
11938 (set_attr "length" "12")])
11939
11940 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
11941 ;; Operand0 is the addresss of the function to call
11942 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11943 ;; Operand2 is the location in the function descriptor to load r2 from
11944 ;; Operand3 is the stack location to hold the current TOC pointer
11945
11946 (define_insn "call_indirect_aix<ptrsize>_nor11"
11947 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11948 (match_operand 1 "" "g,g"))
11949 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11950 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11951 (clobber (reg:P LR_REGNO))]
11952 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11953 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11954 [(set_attr "type" "jmpreg")
11955 (set_attr "length" "12")])
11956
11957 ;; Operand0 is the return result of the function
11958 ;; Operand1 is the addresss of the function to call
11959 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11960 ;; Operand3 is the location in the function descriptor to load r2 from
11961 ;; Operand4 is the stack location to hold the current TOC pointer
11962
11963 (define_insn "call_value_indirect_aix<ptrsize>"
11964 [(set (match_operand 0 "" "")
11965 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11966 (match_operand 2 "" "g,g")))
11967 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11968 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11969 (use (reg:P STATIC_CHAIN_REGNUM))
11970 (clobber (reg:P LR_REGNO))]
11971 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11972 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11973 [(set_attr "type" "jmpreg")
11974 (set_attr "length" "12")])
11975
11976 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
11977 ;; Operand0 is the return result of the function
11978 ;; Operand1 is the addresss of the function to call
11979 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11980 ;; Operand3 is the location in the function descriptor to load r2 from
11981 ;; Operand4 is the stack location to hold the current TOC pointer
11982
11983 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
11984 [(set (match_operand 0 "" "")
11985 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11986 (match_operand 2 "" "g,g")))
11987 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11988 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11989 (clobber (reg:P LR_REGNO))]
11990 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11991 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11992 [(set_attr "type" "jmpreg")
11993 (set_attr "length" "12")])
11994
11995 ;; Call to function which may be in another module. Restore the TOC
11996 ;; pointer (r2) after the call unless this is System V.
11997 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11998 ;; either the function was not prototyped, or it was prototyped as a
11999 ;; variable argument function. It is > 0 if FP registers were passed
12000 ;; and < 0 if they were not.
12001
12002 (define_insn "*call_nonlocal_aix32"
12003 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12004 (match_operand 1 "" "g"))
12005 (use (match_operand:SI 2 "immediate_operand" "O"))
12006 (clobber (reg:SI LR_REGNO))]
12007 "TARGET_32BIT
12008 && DEFAULT_ABI == ABI_AIX
12009 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12010 "bl %z0\;nop"
12011 [(set_attr "type" "branch")
12012 (set_attr "length" "8")])
12013
12014 (define_insn "*call_nonlocal_aix64"
12015 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12016 (match_operand 1 "" "g"))
12017 (use (match_operand:SI 2 "immediate_operand" "O"))
12018 (clobber (reg:SI LR_REGNO))]
12019 "TARGET_64BIT
12020 && DEFAULT_ABI == ABI_AIX
12021 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12022 "bl %z0\;nop"
12023 [(set_attr "type" "branch")
12024 (set_attr "length" "8")])
12025
12026 (define_insn "*call_value_nonlocal_aix32"
12027 [(set (match_operand 0 "" "")
12028 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12029 (match_operand 2 "" "g")))
12030 (use (match_operand:SI 3 "immediate_operand" "O"))
12031 (clobber (reg:SI LR_REGNO))]
12032 "TARGET_32BIT
12033 && DEFAULT_ABI == ABI_AIX
12034 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12035 "bl %z1\;nop"
12036 [(set_attr "type" "branch")
12037 (set_attr "length" "8")])
12038
12039 (define_insn "*call_value_nonlocal_aix64"
12040 [(set (match_operand 0 "" "")
12041 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12042 (match_operand 2 "" "g")))
12043 (use (match_operand:SI 3 "immediate_operand" "O"))
12044 (clobber (reg:SI LR_REGNO))]
12045 "TARGET_64BIT
12046 && DEFAULT_ABI == ABI_AIX
12047 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12048 "bl %z1\;nop"
12049 [(set_attr "type" "branch")
12050 (set_attr "length" "8")])
12051
12052 ;; A function pointer under System V is just a normal pointer
12053 ;; operands[0] is the function pointer
12054 ;; operands[1] is the stack size to clean up
12055 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12056 ;; which indicates how to set cr1
12057
12058 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12059 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12060 (match_operand 1 "" "g,g,g,g"))
12061 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12062 (clobber (reg:SI LR_REGNO))]
12063 "DEFAULT_ABI == ABI_V4
12064 || DEFAULT_ABI == ABI_DARWIN"
12065 {
12066 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12067 output_asm_insn ("crxor 6,6,6", operands);
12068
12069 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12070 output_asm_insn ("creqv 6,6,6", operands);
12071
12072 return "b%T0l";
12073 }
12074 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12075 (set_attr "length" "4,4,8,8")])
12076
12077 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12078 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12079 (match_operand 1 "" "g,g"))
12080 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12081 (clobber (reg:SI LR_REGNO))]
12082 "(DEFAULT_ABI == ABI_DARWIN
12083 || (DEFAULT_ABI == ABI_V4
12084 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12085 {
12086 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12087 output_asm_insn ("crxor 6,6,6", operands);
12088
12089 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12090 output_asm_insn ("creqv 6,6,6", operands);
12091
12092 #if TARGET_MACHO
12093 return output_call(insn, operands, 0, 2);
12094 #else
12095 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12096 {
12097 gcc_assert (!TARGET_SECURE_PLT);
12098 return "bl %z0@plt";
12099 }
12100 else
12101 return "bl %z0";
12102 #endif
12103 }
12104 "DEFAULT_ABI == ABI_V4
12105 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12106 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12107 [(parallel [(call (mem:SI (match_dup 0))
12108 (match_dup 1))
12109 (use (match_dup 2))
12110 (use (match_dup 3))
12111 (clobber (reg:SI LR_REGNO))])]
12112 {
12113 operands[3] = pic_offset_table_rtx;
12114 }
12115 [(set_attr "type" "branch,branch")
12116 (set_attr "length" "4,8")])
12117
12118 (define_insn "*call_nonlocal_sysv_secure<mode>"
12119 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12120 (match_operand 1 "" "g,g"))
12121 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12122 (use (match_operand:SI 3 "register_operand" "r,r"))
12123 (clobber (reg:SI LR_REGNO))]
12124 "(DEFAULT_ABI == ABI_V4
12125 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12126 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12127 {
12128 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12129 output_asm_insn ("crxor 6,6,6", operands);
12130
12131 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12132 output_asm_insn ("creqv 6,6,6", operands);
12133
12134 if (flag_pic == 2)
12135 /* The magic 32768 offset here and in the other sysv call insns
12136 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12137 See sysv4.h:toc_section. */
12138 return "bl %z0+32768@plt";
12139 else
12140 return "bl %z0@plt";
12141 }
12142 [(set_attr "type" "branch,branch")
12143 (set_attr "length" "4,8")])
12144
12145 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12146 [(set (match_operand 0 "" "")
12147 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12148 (match_operand 2 "" "g,g,g,g")))
12149 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12150 (clobber (reg:SI LR_REGNO))]
12151 "DEFAULT_ABI == ABI_V4
12152 || DEFAULT_ABI == ABI_DARWIN"
12153 {
12154 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12155 output_asm_insn ("crxor 6,6,6", operands);
12156
12157 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12158 output_asm_insn ("creqv 6,6,6", operands);
12159
12160 return "b%T1l";
12161 }
12162 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12163 (set_attr "length" "4,4,8,8")])
12164
12165 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12166 [(set (match_operand 0 "" "")
12167 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12168 (match_operand 2 "" "g,g")))
12169 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12170 (clobber (reg:SI LR_REGNO))]
12171 "(DEFAULT_ABI == ABI_DARWIN
12172 || (DEFAULT_ABI == ABI_V4
12173 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12174 {
12175 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12176 output_asm_insn ("crxor 6,6,6", operands);
12177
12178 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12179 output_asm_insn ("creqv 6,6,6", operands);
12180
12181 #if TARGET_MACHO
12182 return output_call(insn, operands, 1, 3);
12183 #else
12184 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12185 {
12186 gcc_assert (!TARGET_SECURE_PLT);
12187 return "bl %z1@plt";
12188 }
12189 else
12190 return "bl %z1";
12191 #endif
12192 }
12193 "DEFAULT_ABI == ABI_V4
12194 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12195 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12196 [(parallel [(set (match_dup 0)
12197 (call (mem:SI (match_dup 1))
12198 (match_dup 2)))
12199 (use (match_dup 3))
12200 (use (match_dup 4))
12201 (clobber (reg:SI LR_REGNO))])]
12202 {
12203 operands[4] = pic_offset_table_rtx;
12204 }
12205 [(set_attr "type" "branch,branch")
12206 (set_attr "length" "4,8")])
12207
12208 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12209 [(set (match_operand 0 "" "")
12210 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12211 (match_operand 2 "" "g,g")))
12212 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12213 (use (match_operand:SI 4 "register_operand" "r,r"))
12214 (clobber (reg:SI LR_REGNO))]
12215 "(DEFAULT_ABI == ABI_V4
12216 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12217 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12218 {
12219 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12220 output_asm_insn ("crxor 6,6,6", operands);
12221
12222 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12223 output_asm_insn ("creqv 6,6,6", operands);
12224
12225 if (flag_pic == 2)
12226 return "bl %z1+32768@plt";
12227 else
12228 return "bl %z1@plt";
12229 }
12230 [(set_attr "type" "branch,branch")
12231 (set_attr "length" "4,8")])
12232
12233 ;; Call subroutine returning any type.
12234 (define_expand "untyped_call"
12235 [(parallel [(call (match_operand 0 "" "")
12236 (const_int 0))
12237 (match_operand 1 "" "")
12238 (match_operand 2 "" "")])]
12239 ""
12240 "
12241 {
12242 int i;
12243
12244 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12245
12246 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12247 {
12248 rtx set = XVECEXP (operands[2], 0, i);
12249 emit_move_insn (SET_DEST (set), SET_SRC (set));
12250 }
12251
12252 /* The optimizer does not know that the call sets the function value
12253 registers we stored in the result block. We avoid problems by
12254 claiming that all hard registers are used and clobbered at this
12255 point. */
12256 emit_insn (gen_blockage ());
12257
12258 DONE;
12259 }")
12260
12261 ;; sibling call patterns
12262 (define_expand "sibcall"
12263 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12264 (match_operand 1 "" ""))
12265 (use (match_operand 2 "" ""))
12266 (use (reg:SI LR_REGNO))
12267 (simple_return)])]
12268 ""
12269 "
12270 {
12271 #if TARGET_MACHO
12272 if (MACHOPIC_INDIRECT)
12273 operands[0] = machopic_indirect_call_target (operands[0]);
12274 #endif
12275
12276 gcc_assert (GET_CODE (operands[0]) == MEM);
12277 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12278
12279 operands[0] = XEXP (operands[0], 0);
12280 }")
12281
12282 ;; this and similar patterns must be marked as using LR, otherwise
12283 ;; dataflow will try to delete the store into it. This is true
12284 ;; even when the actual reg to jump to is in CTR, when LR was
12285 ;; saved and restored around the PIC-setting BCL.
12286 (define_insn "*sibcall_local32"
12287 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12288 (match_operand 1 "" "g,g"))
12289 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12290 (use (reg:SI LR_REGNO))
12291 (simple_return)]
12292 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12293 "*
12294 {
12295 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12296 output_asm_insn (\"crxor 6,6,6\", operands);
12297
12298 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12299 output_asm_insn (\"creqv 6,6,6\", operands);
12300
12301 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12302 }"
12303 [(set_attr "type" "branch")
12304 (set_attr "length" "4,8")])
12305
12306 (define_insn "*sibcall_local64"
12307 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12308 (match_operand 1 "" "g,g"))
12309 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12310 (use (reg:SI LR_REGNO))
12311 (simple_return)]
12312 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12313 "*
12314 {
12315 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12316 output_asm_insn (\"crxor 6,6,6\", operands);
12317
12318 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12319 output_asm_insn (\"creqv 6,6,6\", operands);
12320
12321 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12322 }"
12323 [(set_attr "type" "branch")
12324 (set_attr "length" "4,8")])
12325
12326 (define_insn "*sibcall_value_local32"
12327 [(set (match_operand 0 "" "")
12328 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12329 (match_operand 2 "" "g,g")))
12330 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12331 (use (reg:SI LR_REGNO))
12332 (simple_return)]
12333 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12334 "*
12335 {
12336 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12337 output_asm_insn (\"crxor 6,6,6\", operands);
12338
12339 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12340 output_asm_insn (\"creqv 6,6,6\", operands);
12341
12342 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12343 }"
12344 [(set_attr "type" "branch")
12345 (set_attr "length" "4,8")])
12346
12347
12348 (define_insn "*sibcall_value_local64"
12349 [(set (match_operand 0 "" "")
12350 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12351 (match_operand 2 "" "g,g")))
12352 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12353 (use (reg:SI LR_REGNO))
12354 (simple_return)]
12355 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12356 "*
12357 {
12358 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12359 output_asm_insn (\"crxor 6,6,6\", operands);
12360
12361 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12362 output_asm_insn (\"creqv 6,6,6\", operands);
12363
12364 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12365 }"
12366 [(set_attr "type" "branch")
12367 (set_attr "length" "4,8")])
12368
12369 (define_insn "*sibcall_nonlocal_aix<mode>"
12370 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12371 (match_operand 1 "" "g,g"))
12372 (use (match_operand:SI 2 "immediate_operand" "O,O"))
12373 (use (reg:SI LR_REGNO))
12374 (simple_return)]
12375 "DEFAULT_ABI == ABI_AIX
12376 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12377 "@
12378 b %z0
12379 b%T0"
12380 [(set_attr "type" "branch")
12381 (set_attr "length" "4")])
12382
12383 (define_insn "*sibcall_value_nonlocal_aix<mode>"
12384 [(set (match_operand 0 "" "")
12385 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12386 (match_operand 2 "" "g,g")))
12387 (use (match_operand:SI 3 "immediate_operand" "O,O"))
12388 (use (reg:SI LR_REGNO))
12389 (simple_return)]
12390 "DEFAULT_ABI == ABI_AIX
12391 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12392 "@
12393 b %z1
12394 b%T1"
12395 [(set_attr "type" "branch")
12396 (set_attr "length" "4")])
12397
12398 (define_insn "*sibcall_nonlocal_sysv<mode>"
12399 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12400 (match_operand 1 "" ""))
12401 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12402 (use (reg:SI LR_REGNO))
12403 (simple_return)]
12404 "(DEFAULT_ABI == ABI_DARWIN
12405 || DEFAULT_ABI == ABI_V4)
12406 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12407 "*
12408 {
12409 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12410 output_asm_insn (\"crxor 6,6,6\", operands);
12411
12412 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12413 output_asm_insn (\"creqv 6,6,6\", operands);
12414
12415 if (which_alternative >= 2)
12416 return \"b%T0\";
12417 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12418 {
12419 gcc_assert (!TARGET_SECURE_PLT);
12420 return \"b %z0@plt\";
12421 }
12422 else
12423 return \"b %z0\";
12424 }"
12425 [(set_attr "type" "branch")
12426 (set_attr "length" "4,8,4,8")])
12427
12428 (define_expand "sibcall_value"
12429 [(parallel [(set (match_operand 0 "register_operand" "")
12430 (call (mem:SI (match_operand 1 "address_operand" ""))
12431 (match_operand 2 "" "")))
12432 (use (match_operand 3 "" ""))
12433 (use (reg:SI LR_REGNO))
12434 (simple_return)])]
12435 ""
12436 "
12437 {
12438 #if TARGET_MACHO
12439 if (MACHOPIC_INDIRECT)
12440 operands[1] = machopic_indirect_call_target (operands[1]);
12441 #endif
12442
12443 gcc_assert (GET_CODE (operands[1]) == MEM);
12444 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12445
12446 operands[1] = XEXP (operands[1], 0);
12447 }")
12448
12449 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12450 [(set (match_operand 0 "" "")
12451 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12452 (match_operand 2 "" "")))
12453 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12454 (use (reg:SI LR_REGNO))
12455 (simple_return)]
12456 "(DEFAULT_ABI == ABI_DARWIN
12457 || DEFAULT_ABI == ABI_V4)
12458 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12459 "*
12460 {
12461 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12462 output_asm_insn (\"crxor 6,6,6\", operands);
12463
12464 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12465 output_asm_insn (\"creqv 6,6,6\", operands);
12466
12467 if (which_alternative >= 2)
12468 return \"b%T1\";
12469 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12470 {
12471 gcc_assert (!TARGET_SECURE_PLT);
12472 return \"b %z1@plt\";
12473 }
12474 else
12475 return \"b %z1\";
12476 }"
12477 [(set_attr "type" "branch")
12478 (set_attr "length" "4,8,4,8")])
12479
12480 (define_expand "sibcall_epilogue"
12481 [(use (const_int 0))]
12482 ""
12483 {
12484 if (!TARGET_SCHED_PROLOG)
12485 emit_insn (gen_blockage ());
12486 rs6000_emit_epilogue (TRUE);
12487 DONE;
12488 })
12489
12490 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12491 ;; all of memory. This blocks insns from being moved across this point.
12492
12493 (define_insn "blockage"
12494 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12495 ""
12496 "")
12497
12498 (define_expand "probe_stack"
12499 [(set (match_operand 0 "memory_operand" "=m")
12500 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12501 ""
12502 {
12503 if (TARGET_64BIT)
12504 emit_insn (gen_probe_stack_di (operands[0]));
12505 else
12506 emit_insn (gen_probe_stack_si (operands[0]));
12507 DONE;
12508 })
12509
12510 (define_insn "probe_stack_<mode>"
12511 [(set (match_operand:P 0 "memory_operand" "=m")
12512 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12513 ""
12514 {
12515 operands[1] = gen_rtx_REG (Pmode, 0);
12516 return "st<wd>%U0%X0 %1,%0";
12517 }
12518 [(set (attr "type")
12519 (if_then_else
12520 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
12521 (const_string "store_ux")
12522 (if_then_else
12523 (match_test "update_address_mem (operands[0], VOIDmode)")
12524 (const_string "store_u")
12525 (const_string "store"))))
12526 (set_attr "length" "4")])
12527
12528 (define_insn "probe_stack_range<P:mode>"
12529 [(set (match_operand:P 0 "register_operand" "=r")
12530 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12531 (match_operand:P 2 "register_operand" "r")]
12532 UNSPECV_PROBE_STACK_RANGE))]
12533 ""
12534 "* return output_probe_stack_range (operands[0], operands[2]);"
12535 [(set_attr "type" "three")])
12536 \f
12537 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12538 ;; signed & unsigned, and one type of branch.
12539 ;;
12540 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12541 ;; insns, and branches.
12542
12543 (define_expand "cbranch<mode>4"
12544 [(use (match_operator 0 "rs6000_cbranch_operator"
12545 [(match_operand:GPR 1 "gpc_reg_operand" "")
12546 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12547 (use (match_operand 3 ""))]
12548 ""
12549 "
12550 {
12551 /* Take care of the possibility that operands[2] might be negative but
12552 this might be a logical operation. That insn doesn't exist. */
12553 if (GET_CODE (operands[2]) == CONST_INT
12554 && INTVAL (operands[2]) < 0)
12555 {
12556 operands[2] = force_reg (<MODE>mode, operands[2]);
12557 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12558 GET_MODE (operands[0]),
12559 operands[1], operands[2]);
12560 }
12561
12562 rs6000_emit_cbranch (<MODE>mode, operands);
12563 DONE;
12564 }")
12565
12566 (define_expand "cbranch<mode>4"
12567 [(use (match_operator 0 "rs6000_cbranch_operator"
12568 [(match_operand:FP 1 "gpc_reg_operand" "")
12569 (match_operand:FP 2 "gpc_reg_operand" "")]))
12570 (use (match_operand 3 ""))]
12571 ""
12572 "
12573 {
12574 rs6000_emit_cbranch (<MODE>mode, operands);
12575 DONE;
12576 }")
12577
12578 (define_expand "cstore<mode>4"
12579 [(use (match_operator 1 "rs6000_cbranch_operator"
12580 [(match_operand:GPR 2 "gpc_reg_operand" "")
12581 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12582 (clobber (match_operand:SI 0 "register_operand"))]
12583 ""
12584 "
12585 {
12586 /* Take care of the possibility that operands[3] might be negative but
12587 this might be a logical operation. That insn doesn't exist. */
12588 if (GET_CODE (operands[3]) == CONST_INT
12589 && INTVAL (operands[3]) < 0)
12590 {
12591 operands[3] = force_reg (<MODE>mode, operands[3]);
12592 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12593 GET_MODE (operands[1]),
12594 operands[2], operands[3]);
12595 }
12596
12597 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12598 For SEQ, likewise, except that comparisons with zero should be done
12599 with an scc insns. However, due to the order that combine see the
12600 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12601 the cases we don't want to handle or are best handled by portable
12602 code. */
12603 if (GET_CODE (operands[1]) == NE)
12604 FAIL;
12605 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12606 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12607 && operands[3] == const0_rtx)
12608 FAIL;
12609 rs6000_emit_sCOND (<MODE>mode, operands);
12610 DONE;
12611 }")
12612
12613 (define_expand "cstore<mode>4"
12614 [(use (match_operator 1 "rs6000_cbranch_operator"
12615 [(match_operand:FP 2 "gpc_reg_operand" "")
12616 (match_operand:FP 3 "gpc_reg_operand" "")]))
12617 (clobber (match_operand:SI 0 "register_operand"))]
12618 ""
12619 "
12620 {
12621 rs6000_emit_sCOND (<MODE>mode, operands);
12622 DONE;
12623 }")
12624
12625
12626 (define_expand "stack_protect_set"
12627 [(match_operand 0 "memory_operand" "")
12628 (match_operand 1 "memory_operand" "")]
12629 ""
12630 {
12631 #ifdef TARGET_THREAD_SSP_OFFSET
12632 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12633 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12634 operands[1] = gen_rtx_MEM (Pmode, addr);
12635 #endif
12636 if (TARGET_64BIT)
12637 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12638 else
12639 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12640 DONE;
12641 })
12642
12643 (define_insn "stack_protect_setsi"
12644 [(set (match_operand:SI 0 "memory_operand" "=m")
12645 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12646 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12647 "TARGET_32BIT"
12648 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12649 [(set_attr "type" "three")
12650 (set_attr "length" "12")])
12651
12652 (define_insn "stack_protect_setdi"
12653 [(set (match_operand:DI 0 "memory_operand" "=Y")
12654 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12655 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12656 "TARGET_64BIT"
12657 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12658 [(set_attr "type" "three")
12659 (set_attr "length" "12")])
12660
12661 (define_expand "stack_protect_test"
12662 [(match_operand 0 "memory_operand" "")
12663 (match_operand 1 "memory_operand" "")
12664 (match_operand 2 "" "")]
12665 ""
12666 {
12667 rtx test, op0, op1;
12668 #ifdef TARGET_THREAD_SSP_OFFSET
12669 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12670 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12671 operands[1] = gen_rtx_MEM (Pmode, addr);
12672 #endif
12673 op0 = operands[0];
12674 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12675 test = gen_rtx_EQ (VOIDmode, op0, op1);
12676 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12677 DONE;
12678 })
12679
12680 (define_insn "stack_protect_testsi"
12681 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12682 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12683 (match_operand:SI 2 "memory_operand" "m,m")]
12684 UNSPEC_SP_TEST))
12685 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12686 (clobber (match_scratch:SI 3 "=&r,&r"))]
12687 "TARGET_32BIT"
12688 "@
12689 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12690 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
12691 [(set_attr "length" "16,20")])
12692
12693 (define_insn "stack_protect_testdi"
12694 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12695 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
12696 (match_operand:DI 2 "memory_operand" "Y,Y")]
12697 UNSPEC_SP_TEST))
12698 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12699 (clobber (match_scratch:DI 3 "=&r,&r"))]
12700 "TARGET_64BIT"
12701 "@
12702 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12703 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
12704 [(set_attr "length" "16,20")])
12705
12706 \f
12707 ;; Here are the actual compare insns.
12708 (define_insn "*cmp<mode>_internal1"
12709 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12710 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12711 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12712 ""
12713 "cmp<wd>%I2 %0,%1,%2"
12714 [(set_attr "type" "cmp")])
12715
12716 ;; If we are comparing a register for equality with a large constant,
12717 ;; we can do this with an XOR followed by a compare. But this is profitable
12718 ;; only if the large constant is only used for the comparison (and in this
12719 ;; case we already have a register to reuse as scratch).
12720 ;;
12721 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12722 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12723
12724 (define_peephole2
12725 [(set (match_operand:SI 0 "register_operand")
12726 (match_operand:SI 1 "logical_const_operand" ""))
12727 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12728 [(match_dup 0)
12729 (match_operand:SI 2 "logical_const_operand" "")]))
12730 (set (match_operand:CC 4 "cc_reg_operand" "")
12731 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12732 (match_dup 0)))
12733 (set (pc)
12734 (if_then_else (match_operator 6 "equality_operator"
12735 [(match_dup 4) (const_int 0)])
12736 (match_operand 7 "" "")
12737 (match_operand 8 "" "")))]
12738 "peep2_reg_dead_p (3, operands[0])
12739 && peep2_reg_dead_p (4, operands[4])"
12740 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12741 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12742 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12743
12744 {
12745 /* Get the constant we are comparing against, and see what it looks like
12746 when sign-extended from 16 to 32 bits. Then see what constant we could
12747 XOR with SEXTC to get the sign-extended value. */
12748 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12749 SImode,
12750 operands[1], operands[2]);
12751 HOST_WIDE_INT c = INTVAL (cnst);
12752 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12753 HOST_WIDE_INT xorv = c ^ sextc;
12754
12755 operands[9] = GEN_INT (xorv);
12756 operands[10] = GEN_INT (sextc);
12757 })
12758
12759 (define_insn "*cmpsi_internal2"
12760 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12761 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12762 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12763 ""
12764 "cmplw%I2 %0,%1,%b2"
12765 [(set_attr "type" "cmp")])
12766
12767 (define_insn "*cmpdi_internal2"
12768 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12769 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12770 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12771 ""
12772 "cmpld%I2 %0,%1,%b2"
12773 [(set_attr "type" "cmp")])
12774
12775 ;; The following two insns don't exist as single insns, but if we provide
12776 ;; them, we can swap an add and compare, which will enable us to overlap more
12777 ;; of the required delay between a compare and branch. We generate code for
12778 ;; them by splitting.
12779
12780 (define_insn ""
12781 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12782 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12783 (match_operand:SI 2 "short_cint_operand" "i")))
12784 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12785 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12786 ""
12787 "#"
12788 [(set_attr "length" "8")])
12789
12790 (define_insn ""
12791 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12792 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12793 (match_operand:SI 2 "u_short_cint_operand" "i")))
12794 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12795 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12796 ""
12797 "#"
12798 [(set_attr "length" "8")])
12799
12800 (define_split
12801 [(set (match_operand:CC 3 "cc_reg_operand" "")
12802 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12803 (match_operand:SI 2 "short_cint_operand" "")))
12804 (set (match_operand:SI 0 "gpc_reg_operand" "")
12805 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12806 ""
12807 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12808 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12809
12810 (define_split
12811 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12812 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12813 (match_operand:SI 2 "u_short_cint_operand" "")))
12814 (set (match_operand:SI 0 "gpc_reg_operand" "")
12815 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12816 ""
12817 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12818 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12819
12820 (define_insn "*cmpsf_internal1"
12821 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12822 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12823 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12824 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12825 "fcmpu %0,%1,%2"
12826 [(set_attr "type" "fpcompare")])
12827
12828 (define_insn "*cmpdf_internal1"
12829 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12830 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12831 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12832 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12833 && !VECTOR_UNIT_VSX_P (DFmode)"
12834 "fcmpu %0,%1,%2"
12835 [(set_attr "type" "fpcompare")])
12836
12837 ;; Only need to compare second words if first words equal
12838 (define_insn "*cmptf_internal1"
12839 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12840 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12841 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12842 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12843 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12844 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12845 [(set_attr "type" "fpcompare")
12846 (set_attr "length" "12")])
12847
12848 (define_insn_and_split "*cmptf_internal2"
12849 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12850 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12851 (match_operand:TF 2 "gpc_reg_operand" "d")))
12852 (clobber (match_scratch:DF 3 "=d"))
12853 (clobber (match_scratch:DF 4 "=d"))
12854 (clobber (match_scratch:DF 5 "=d"))
12855 (clobber (match_scratch:DF 6 "=d"))
12856 (clobber (match_scratch:DF 7 "=d"))
12857 (clobber (match_scratch:DF 8 "=d"))
12858 (clobber (match_scratch:DF 9 "=d"))
12859 (clobber (match_scratch:DF 10 "=d"))
12860 (clobber (match_scratch:GPR 11 "=b"))]
12861 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12862 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12863 "#"
12864 "&& reload_completed"
12865 [(set (match_dup 3) (match_dup 14))
12866 (set (match_dup 4) (match_dup 15))
12867 (set (match_dup 9) (abs:DF (match_dup 5)))
12868 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12869 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12870 (label_ref (match_dup 12))
12871 (pc)))
12872 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12873 (set (pc) (label_ref (match_dup 13)))
12874 (match_dup 12)
12875 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12876 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12877 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12878 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12879 (match_dup 13)]
12880 {
12881 REAL_VALUE_TYPE rv;
12882 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12883 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12884
12885 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12886 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12887 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12888 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12889 operands[12] = gen_label_rtx ();
12890 operands[13] = gen_label_rtx ();
12891 real_inf (&rv);
12892 operands[14] = force_const_mem (DFmode,
12893 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12894 operands[15] = force_const_mem (DFmode,
12895 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12896 DFmode));
12897 if (TARGET_TOC)
12898 {
12899 rtx tocref;
12900 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12901 operands[14] = gen_const_mem (DFmode, tocref);
12902 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12903 operands[15] = gen_const_mem (DFmode, tocref);
12904 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12905 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12906 }
12907 })
12908 \f
12909 ;; Now we have the scc insns. We can do some combinations because of the
12910 ;; way the machine works.
12911 ;;
12912 ;; Note that this is probably faster if we can put an insn between the
12913 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12914 ;; cases the insns below which don't use an intermediate CR field will
12915 ;; be used instead.
12916 (define_insn ""
12917 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12918 (match_operator:SI 1 "scc_comparison_operator"
12919 [(match_operand 2 "cc_reg_operand" "y")
12920 (const_int 0)]))]
12921 ""
12922 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12923 [(set (attr "type")
12924 (cond [(match_test "TARGET_MFCRF")
12925 (const_string "mfcrf")
12926 ]
12927 (const_string "mfcr")))
12928 (set_attr "length" "8")])
12929
12930 ;; Same as above, but get the GT bit.
12931 (define_insn "move_from_CR_gt_bit"
12932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12933 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12934 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12935 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
12936 [(set_attr "type" "mfcr")
12937 (set_attr "length" "8")])
12938
12939 ;; Same as above, but get the OV/ORDERED bit.
12940 (define_insn "move_from_CR_ov_bit"
12941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12942 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
12943 UNSPEC_MV_CR_OV))]
12944 "TARGET_ISEL"
12945 "mfcr %0\;rlwinm %0,%0,%t1,1"
12946 [(set_attr "type" "mfcr")
12947 (set_attr "length" "8")])
12948
12949 (define_insn ""
12950 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12951 (match_operator:DI 1 "scc_comparison_operator"
12952 [(match_operand 2 "cc_reg_operand" "y")
12953 (const_int 0)]))]
12954 "TARGET_POWERPC64"
12955 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12956 [(set (attr "type")
12957 (cond [(match_test "TARGET_MFCRF")
12958 (const_string "mfcrf")
12959 ]
12960 (const_string "mfcr")))
12961 (set_attr "length" "8")])
12962
12963 (define_insn ""
12964 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12965 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12966 [(match_operand 2 "cc_reg_operand" "y,y")
12967 (const_int 0)])
12968 (const_int 0)))
12969 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12970 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12971 "TARGET_32BIT"
12972 "@
12973 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
12974 #"
12975 [(set_attr "type" "delayed_compare")
12976 (set_attr "length" "8,16")])
12977
12978 (define_split
12979 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12980 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12981 [(match_operand 2 "cc_reg_operand" "")
12982 (const_int 0)])
12983 (const_int 0)))
12984 (set (match_operand:SI 3 "gpc_reg_operand" "")
12985 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12986 "TARGET_32BIT && reload_completed"
12987 [(set (match_dup 3)
12988 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12989 (set (match_dup 0)
12990 (compare:CC (match_dup 3)
12991 (const_int 0)))]
12992 "")
12993
12994 (define_insn ""
12995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12996 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12997 [(match_operand 2 "cc_reg_operand" "y")
12998 (const_int 0)])
12999 (match_operand:SI 3 "const_int_operand" "n")))]
13000 ""
13001 "*
13002 {
13003 int is_bit = ccr_bit (operands[1], 1);
13004 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13005 int count;
13006
13007 if (is_bit >= put_bit)
13008 count = is_bit - put_bit;
13009 else
13010 count = 32 - (put_bit - is_bit);
13011
13012 operands[4] = GEN_INT (count);
13013 operands[5] = GEN_INT (put_bit);
13014
13015 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
13016 }"
13017 [(set (attr "type")
13018 (cond [(match_test "TARGET_MFCRF")
13019 (const_string "mfcrf")
13020 ]
13021 (const_string "mfcr")))
13022 (set_attr "length" "8")])
13023
13024 (define_insn ""
13025 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13026 (compare:CC
13027 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13028 [(match_operand 2 "cc_reg_operand" "y,y")
13029 (const_int 0)])
13030 (match_operand:SI 3 "const_int_operand" "n,n"))
13031 (const_int 0)))
13032 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13033 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13034 (match_dup 3)))]
13035 ""
13036 "*
13037 {
13038 int is_bit = ccr_bit (operands[1], 1);
13039 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13040 int count;
13041
13042 /* Force split for non-cc0 compare. */
13043 if (which_alternative == 1)
13044 return \"#\";
13045
13046 if (is_bit >= put_bit)
13047 count = is_bit - put_bit;
13048 else
13049 count = 32 - (put_bit - is_bit);
13050
13051 operands[5] = GEN_INT (count);
13052 operands[6] = GEN_INT (put_bit);
13053
13054 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
13055 }"
13056 [(set_attr "type" "delayed_compare")
13057 (set_attr "length" "8,16")])
13058
13059 (define_split
13060 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13061 (compare:CC
13062 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13063 [(match_operand 2 "cc_reg_operand" "")
13064 (const_int 0)])
13065 (match_operand:SI 3 "const_int_operand" ""))
13066 (const_int 0)))
13067 (set (match_operand:SI 4 "gpc_reg_operand" "")
13068 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13069 (match_dup 3)))]
13070 "reload_completed"
13071 [(set (match_dup 4)
13072 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13073 (match_dup 3)))
13074 (set (match_dup 0)
13075 (compare:CC (match_dup 4)
13076 (const_int 0)))]
13077 "")
13078
13079 ;; There is a 3 cycle delay between consecutive mfcr instructions
13080 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13081
13082 (define_peephole
13083 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13084 (match_operator:SI 1 "scc_comparison_operator"
13085 [(match_operand 2 "cc_reg_operand" "y")
13086 (const_int 0)]))
13087 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13088 (match_operator:SI 4 "scc_comparison_operator"
13089 [(match_operand 5 "cc_reg_operand" "y")
13090 (const_int 0)]))]
13091 "REGNO (operands[2]) != REGNO (operands[5])"
13092 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13093 [(set_attr "type" "mfcr")
13094 (set_attr "length" "12")])
13095
13096 (define_peephole
13097 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13098 (match_operator:DI 1 "scc_comparison_operator"
13099 [(match_operand 2 "cc_reg_operand" "y")
13100 (const_int 0)]))
13101 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13102 (match_operator:DI 4 "scc_comparison_operator"
13103 [(match_operand 5 "cc_reg_operand" "y")
13104 (const_int 0)]))]
13105 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13106 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13107 [(set_attr "type" "mfcr")
13108 (set_attr "length" "12")])
13109
13110 ;; There are some scc insns that can be done directly, without a compare.
13111 ;; These are faster because they don't involve the communications between
13112 ;; the FXU and branch units. In fact, we will be replacing all of the
13113 ;; integer scc insns here or in the portable methods in emit_store_flag.
13114 ;;
13115 ;; Also support (neg (scc ..)) since that construct is used to replace
13116 ;; branches, (plus (scc ..) ..) since that construct is common and
13117 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13118 ;; cases where it is no more expensive than (neg (scc ..)).
13119
13120 ;; Have reload force a constant into a register for the simple insns that
13121 ;; otherwise won't accept constants. We do this because it is faster than
13122 ;; the cmp/mfcr sequence we would otherwise generate.
13123
13124 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13125 (DI "rKJI")])
13126
13127 (define_insn_and_split "*eq<mode>"
13128 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13129 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13130 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13131 ""
13132 "#"
13133 ""
13134 [(set (match_dup 0)
13135 (clz:GPR (match_dup 3)))
13136 (set (match_dup 0)
13137 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13138 {
13139 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13140 {
13141 /* Use output operand as intermediate. */
13142 operands[3] = operands[0];
13143
13144 if (logical_operand (operands[2], <MODE>mode))
13145 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13146 gen_rtx_XOR (<MODE>mode,
13147 operands[1], operands[2])));
13148 else
13149 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13150 gen_rtx_PLUS (<MODE>mode, operands[1],
13151 negate_rtx (<MODE>mode,
13152 operands[2]))));
13153 }
13154 else
13155 operands[3] = operands[1];
13156
13157 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13158 })
13159
13160 (define_insn_and_split "*eq<mode>_compare"
13161 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13162 (compare:CC
13163 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13164 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13165 (const_int 0)))
13166 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13167 (eq:P (match_dup 1) (match_dup 2)))]
13168 "optimize_size"
13169 "#"
13170 "optimize_size"
13171 [(set (match_dup 0)
13172 (clz:P (match_dup 4)))
13173 (parallel [(set (match_dup 3)
13174 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13175 (const_int 0)))
13176 (set (match_dup 0)
13177 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13178 {
13179 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13180 {
13181 /* Use output operand as intermediate. */
13182 operands[4] = operands[0];
13183
13184 if (logical_operand (operands[2], <MODE>mode))
13185 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13186 gen_rtx_XOR (<MODE>mode,
13187 operands[1], operands[2])));
13188 else
13189 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13190 gen_rtx_PLUS (<MODE>mode, operands[1],
13191 negate_rtx (<MODE>mode,
13192 operands[2]))));
13193 }
13194 else
13195 operands[4] = operands[1];
13196
13197 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13198 })
13199
13200 ;; We have insns of the form shown by the first define_insn below. If
13201 ;; there is something inside the comparison operation, we must split it.
13202 (define_split
13203 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13204 (plus:SI (match_operator 1 "comparison_operator"
13205 [(match_operand:SI 2 "" "")
13206 (match_operand:SI 3
13207 "reg_or_cint_operand" "")])
13208 (match_operand:SI 4 "gpc_reg_operand" "")))
13209 (clobber (match_operand:SI 5 "register_operand" ""))]
13210 "! gpc_reg_operand (operands[2], SImode)"
13211 [(set (match_dup 5) (match_dup 2))
13212 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
13213 (match_dup 4)))])
13214
13215 (define_insn "*plus_eqsi"
13216 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13217 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13218 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13219 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13220 "TARGET_32BIT"
13221 "@
13222 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
13223 subfic %0,%1,0\;addze %0,%3
13224 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
13225 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
13226 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
13227 [(set_attr "type" "three,two,three,three,three")
13228 (set_attr "length" "12,8,12,12,12")])
13229
13230 (define_insn "*compare_plus_eqsi"
13231 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13232 (compare:CC
13233 (plus:SI
13234 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13235 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13236 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13237 (const_int 0)))
13238 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13239 "TARGET_32BIT && optimize_size"
13240 "@
13241 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13242 subfic %4,%1,0\;addze. %4,%3
13243 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
13244 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
13245 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13246 #
13247 #
13248 #
13249 #
13250 #"
13251 [(set_attr "type" "compare")
13252 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13253
13254 (define_split
13255 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13256 (compare:CC
13257 (plus:SI
13258 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13259 (match_operand:SI 2 "scc_eq_operand" ""))
13260 (match_operand:SI 3 "gpc_reg_operand" ""))
13261 (const_int 0)))
13262 (clobber (match_scratch:SI 4 ""))]
13263 "TARGET_32BIT && optimize_size && reload_completed"
13264 [(set (match_dup 4)
13265 (plus:SI (eq:SI (match_dup 1)
13266 (match_dup 2))
13267 (match_dup 3)))
13268 (set (match_dup 0)
13269 (compare:CC (match_dup 4)
13270 (const_int 0)))]
13271 "")
13272
13273 (define_insn "*plus_eqsi_compare"
13274 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13275 (compare:CC
13276 (plus:SI
13277 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13278 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13279 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13280 (const_int 0)))
13281 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13282 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13283 "TARGET_32BIT && optimize_size"
13284 "@
13285 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13286 subfic %0,%1,0\;addze. %0,%3
13287 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
13288 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
13289 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13290 #
13291 #
13292 #
13293 #
13294 #"
13295 [(set_attr "type" "compare")
13296 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13297
13298 (define_split
13299 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13300 (compare:CC
13301 (plus:SI
13302 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13303 (match_operand:SI 2 "scc_eq_operand" ""))
13304 (match_operand:SI 3 "gpc_reg_operand" ""))
13305 (const_int 0)))
13306 (set (match_operand:SI 0 "gpc_reg_operand" "")
13307 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13308 "TARGET_32BIT && optimize_size && reload_completed"
13309 [(set (match_dup 0)
13310 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13311 (set (match_dup 4)
13312 (compare:CC (match_dup 0)
13313 (const_int 0)))]
13314 "")
13315
13316 (define_insn "*neg_eq0<mode>"
13317 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13318 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13319 (const_int 0))))]
13320 ""
13321 "addic %0,%1,-1\;subfe %0,%0,%0"
13322 [(set_attr "type" "two")
13323 (set_attr "length" "8")])
13324
13325 (define_insn_and_split "*neg_eq<mode>"
13326 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13327 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13328 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13329 ""
13330 "#"
13331 ""
13332 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13333 {
13334 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13335 {
13336 /* Use output operand as intermediate. */
13337 operands[3] = operands[0];
13338
13339 if (logical_operand (operands[2], <MODE>mode))
13340 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13341 gen_rtx_XOR (<MODE>mode,
13342 operands[1], operands[2])));
13343 else
13344 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13345 gen_rtx_PLUS (<MODE>mode, operands[1],
13346 negate_rtx (<MODE>mode,
13347 operands[2]))));
13348 }
13349 else
13350 operands[3] = operands[1];
13351 })
13352
13353 (define_insn "*ne0_<mode>"
13354 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13355 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13356 (const_int 0)))
13357 (clobber (match_scratch:P 2 "=&r"))]
13358 "!(TARGET_32BIT && TARGET_ISEL)"
13359 "addic %2,%1,-1\;subfe %0,%2,%1"
13360 [(set_attr "type" "two")
13361 (set_attr "length" "8")])
13362
13363 (define_insn "*plus_ne0_<mode>"
13364 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13365 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13366 (const_int 0))
13367 (match_operand:P 2 "gpc_reg_operand" "r")))
13368 (clobber (match_scratch:P 3 "=&r"))]
13369 ""
13370 "addic %3,%1,-1\;addze %0,%2"
13371 [(set_attr "type" "two")
13372 (set_attr "length" "8")])
13373
13374 (define_insn "*compare_plus_ne0_<mode>"
13375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13376 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13377 (const_int 0))
13378 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13379 (const_int 0)))
13380 (clobber (match_scratch:P 3 "=&r,&r"))
13381 (clobber (match_scratch:P 4 "=X,&r"))]
13382 ""
13383 "@
13384 addic %3,%1,-1\;addze. %3,%2
13385 #"
13386 [(set_attr "type" "compare")
13387 (set_attr "length" "8,12")])
13388
13389 (define_split
13390 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13391 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13392 (const_int 0))
13393 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13394 (clobber (match_scratch:P 3 ""))
13395 (clobber (match_scratch:P 4 ""))]
13396 "reload_completed"
13397 [(parallel [(set (match_dup 3)
13398 (plus:P (ne:P (match_dup 1)
13399 (const_int 0))
13400 (match_dup 2)))
13401 (clobber (match_dup 4))])
13402 (set (match_dup 0)
13403 (compare:CC (match_dup 3)
13404 (const_int 0)))]
13405 "")
13406
13407 ; For combine.
13408 (define_insn "*compare_plus_ne0_<mode>_1"
13409 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13410 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13411 (const_int 0))
13412 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13413 (clobber (match_scratch:P 3 "=&r,&r"))
13414 (clobber (match_scratch:P 4 "=X,&r"))]
13415 ""
13416 "@
13417 addic %3,%1,-1\;addze. %3,%2
13418 #"
13419 [(set_attr "type" "compare")
13420 (set_attr "length" "8,12")])
13421
13422 (define_split
13423 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13424 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13425 (const_int 0))
13426 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13427 (clobber (match_scratch:P 3 ""))
13428 (clobber (match_scratch:P 4 ""))]
13429 "reload_completed"
13430 [(parallel [(set (match_dup 3)
13431 (plus:P (ne:P (match_dup 1)
13432 (const_int 0))
13433 (match_dup 2)))
13434 (clobber (match_dup 4))])
13435 (set (match_dup 0)
13436 (compare:CC (match_dup 3)
13437 (const_int 0)))]
13438 "")
13439
13440 (define_insn "*plus_ne0_<mode>_compare"
13441 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13442 (compare:CC
13443 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13444 (const_int 0))
13445 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13446 (const_int 0)))
13447 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13448 (plus:P (ne:P (match_dup 1)
13449 (const_int 0))
13450 (match_dup 2)))
13451 (clobber (match_scratch:P 3 "=&r,&r"))]
13452 ""
13453 "@
13454 addic %3,%1,-1\;addze. %0,%2
13455 #"
13456 [(set_attr "type" "compare")
13457 (set_attr "length" "8,12")])
13458
13459 (define_split
13460 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13461 (compare:CC
13462 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13463 (const_int 0))
13464 (match_operand:P 2 "gpc_reg_operand" ""))
13465 (const_int 0)))
13466 (set (match_operand:P 0 "gpc_reg_operand" "")
13467 (plus:P (ne:P (match_dup 1)
13468 (const_int 0))
13469 (match_dup 2)))
13470 (clobber (match_scratch:P 3 ""))]
13471 "reload_completed"
13472 [(parallel [(set (match_dup 0)
13473 (plus:P (ne:P (match_dup 1)
13474 (const_int 0))
13475 (match_dup 2)))
13476 (clobber (match_dup 3))])
13477 (set (match_dup 4)
13478 (compare:CC (match_dup 0)
13479 (const_int 0)))]
13480 "")
13481
13482 (define_insn "*leu<mode>"
13483 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13484 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13485 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13486 ""
13487 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13488 [(set_attr "type" "three")
13489 (set_attr "length" "12")])
13490
13491 (define_insn "*leu<mode>_compare"
13492 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13493 (compare:CC
13494 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13495 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13496 (const_int 0)))
13497 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13498 (leu:P (match_dup 1) (match_dup 2)))]
13499 ""
13500 "@
13501 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13502 #"
13503 [(set_attr "type" "compare")
13504 (set_attr "length" "12,16")])
13505
13506 (define_split
13507 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13508 (compare:CC
13509 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13510 (match_operand:P 2 "reg_or_short_operand" ""))
13511 (const_int 0)))
13512 (set (match_operand:P 0 "gpc_reg_operand" "")
13513 (leu:P (match_dup 1) (match_dup 2)))]
13514 "reload_completed"
13515 [(set (match_dup 0)
13516 (leu:P (match_dup 1) (match_dup 2)))
13517 (set (match_dup 3)
13518 (compare:CC (match_dup 0)
13519 (const_int 0)))]
13520 "")
13521
13522 (define_insn "*plus_leu<mode>"
13523 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13524 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13525 (match_operand:P 2 "reg_or_short_operand" "rI"))
13526 (match_operand:P 3 "gpc_reg_operand" "r")))]
13527 ""
13528 "subf%I2c %0,%1,%2\;addze %0,%3"
13529 [(set_attr "type" "two")
13530 (set_attr "length" "8")])
13531
13532 (define_insn ""
13533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13534 (compare:CC
13535 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13536 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13537 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13538 (const_int 0)))
13539 (clobber (match_scratch:SI 4 "=&r,&r"))]
13540 "TARGET_32BIT"
13541 "@
13542 subf%I2c %4,%1,%2\;addze. %4,%3
13543 #"
13544 [(set_attr "type" "compare")
13545 (set_attr "length" "8,12")])
13546
13547 (define_split
13548 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13549 (compare:CC
13550 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13551 (match_operand:SI 2 "reg_or_short_operand" ""))
13552 (match_operand:SI 3 "gpc_reg_operand" ""))
13553 (const_int 0)))
13554 (clobber (match_scratch:SI 4 ""))]
13555 "TARGET_32BIT && reload_completed"
13556 [(set (match_dup 4)
13557 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13558 (match_dup 3)))
13559 (set (match_dup 0)
13560 (compare:CC (match_dup 4)
13561 (const_int 0)))]
13562 "")
13563
13564 (define_insn ""
13565 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13566 (compare:CC
13567 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13568 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13569 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13570 (const_int 0)))
13571 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13572 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13573 "TARGET_32BIT"
13574 "@
13575 subf%I2c %0,%1,%2\;addze. %0,%3
13576 #"
13577 [(set_attr "type" "compare")
13578 (set_attr "length" "8,12")])
13579
13580 (define_split
13581 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13582 (compare:CC
13583 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13584 (match_operand:SI 2 "reg_or_short_operand" ""))
13585 (match_operand:SI 3 "gpc_reg_operand" ""))
13586 (const_int 0)))
13587 (set (match_operand:SI 0 "gpc_reg_operand" "")
13588 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13589 "TARGET_32BIT && reload_completed"
13590 [(set (match_dup 0)
13591 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13592 (set (match_dup 4)
13593 (compare:CC (match_dup 0)
13594 (const_int 0)))]
13595 "")
13596
13597 (define_insn "*neg_leu<mode>"
13598 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13599 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13600 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13601 ""
13602 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13603 [(set_attr "type" "three")
13604 (set_attr "length" "12")])
13605
13606 (define_insn "*and_neg_leu<mode>"
13607 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13608 (and:P (neg:P
13609 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13610 (match_operand:P 2 "reg_or_short_operand" "rI")))
13611 (match_operand:P 3 "gpc_reg_operand" "r")))]
13612 ""
13613 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13614 [(set_attr "type" "three")
13615 (set_attr "length" "12")])
13616
13617 (define_insn ""
13618 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13619 (compare:CC
13620 (and:SI (neg:SI
13621 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13622 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13623 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13624 (const_int 0)))
13625 (clobber (match_scratch:SI 4 "=&r,&r"))]
13626 "TARGET_32BIT"
13627 "@
13628 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13629 #"
13630 [(set_attr "type" "compare")
13631 (set_attr "length" "12,16")])
13632
13633 (define_split
13634 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13635 (compare:CC
13636 (and:SI (neg:SI
13637 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13638 (match_operand:SI 2 "reg_or_short_operand" "")))
13639 (match_operand:SI 3 "gpc_reg_operand" ""))
13640 (const_int 0)))
13641 (clobber (match_scratch:SI 4 ""))]
13642 "TARGET_32BIT && reload_completed"
13643 [(set (match_dup 4)
13644 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13645 (match_dup 3)))
13646 (set (match_dup 0)
13647 (compare:CC (match_dup 4)
13648 (const_int 0)))]
13649 "")
13650
13651 (define_insn ""
13652 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13653 (compare:CC
13654 (and:SI (neg:SI
13655 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13656 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13657 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13658 (const_int 0)))
13659 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13660 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13661 "TARGET_32BIT"
13662 "@
13663 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13664 #"
13665 [(set_attr "type" "compare")
13666 (set_attr "length" "12,16")])
13667
13668 (define_split
13669 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13670 (compare:CC
13671 (and:SI (neg:SI
13672 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13673 (match_operand:SI 2 "reg_or_short_operand" "")))
13674 (match_operand:SI 3 "gpc_reg_operand" ""))
13675 (const_int 0)))
13676 (set (match_operand:SI 0 "gpc_reg_operand" "")
13677 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13678 "TARGET_32BIT && reload_completed"
13679 [(set (match_dup 0)
13680 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13681 (match_dup 3)))
13682 (set (match_dup 4)
13683 (compare:CC (match_dup 0)
13684 (const_int 0)))]
13685 "")
13686
13687 (define_insn_and_split "*ltu<mode>"
13688 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13689 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13690 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13691 ""
13692 "#"
13693 ""
13694 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13695 (set (match_dup 0) (neg:P (match_dup 0)))]
13696 "")
13697
13698 (define_insn_and_split "*ltu<mode>_compare"
13699 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13700 (compare:CC
13701 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13702 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13703 (const_int 0)))
13704 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13705 (ltu:P (match_dup 1) (match_dup 2)))]
13706 ""
13707 "#"
13708 ""
13709 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13710 (parallel [(set (match_dup 3)
13711 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13712 (set (match_dup 0) (neg:P (match_dup 0)))])]
13713 "")
13714
13715 (define_insn_and_split "*plus_ltu<mode>"
13716 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13717 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13718 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13719 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13720 ""
13721 "#"
13722 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13723 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13724 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13725 "")
13726
13727 (define_insn_and_split "*plus_ltu<mode>_compare"
13728 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13729 (compare:CC
13730 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13731 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13732 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13733 (const_int 0)))
13734 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13735 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13736 ""
13737 "#"
13738 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13739 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13740 (parallel [(set (match_dup 4)
13741 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13742 (const_int 0)))
13743 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13744 "")
13745
13746 (define_insn "*neg_ltu<mode>"
13747 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13748 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13749 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13750 ""
13751 "@
13752 subfc %0,%2,%1\;subfe %0,%0,%0
13753 addic %0,%1,%n2\;subfe %0,%0,%0"
13754 [(set_attr "type" "two")
13755 (set_attr "length" "8")])
13756
13757 (define_insn "*geu<mode>"
13758 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13759 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13760 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13761 ""
13762 "@
13763 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
13764 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
13765 [(set_attr "type" "three")
13766 (set_attr "length" "12")])
13767
13768 (define_insn "*geu<mode>_compare"
13769 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13770 (compare:CC
13771 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13772 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13773 (const_int 0)))
13774 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13775 (geu:P (match_dup 1) (match_dup 2)))]
13776 ""
13777 "@
13778 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13779 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13780 #
13781 #"
13782 [(set_attr "type" "compare")
13783 (set_attr "length" "12,12,16,16")])
13784
13785 (define_split
13786 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13787 (compare:CC
13788 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13789 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13790 (const_int 0)))
13791 (set (match_operand:P 0 "gpc_reg_operand" "")
13792 (geu:P (match_dup 1) (match_dup 2)))]
13793 "reload_completed"
13794 [(set (match_dup 0)
13795 (geu:P (match_dup 1) (match_dup 2)))
13796 (set (match_dup 3)
13797 (compare:CC (match_dup 0)
13798 (const_int 0)))]
13799 "")
13800
13801 (define_insn "*plus_geu<mode>"
13802 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13803 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13804 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13805 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13806 ""
13807 "@
13808 subfc %0,%2,%1\;addze %0,%3
13809 addic %0,%1,%n2\;addze %0,%3"
13810 [(set_attr "type" "two")
13811 (set_attr "length" "8")])
13812
13813 (define_insn ""
13814 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13815 (compare:CC
13816 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13817 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13818 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13819 (const_int 0)))
13820 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13821 "TARGET_32BIT"
13822 "@
13823 subfc %4,%2,%1\;addze. %4,%3
13824 addic %4,%1,%n2\;addze. %4,%3
13825 #
13826 #"
13827 [(set_attr "type" "compare")
13828 (set_attr "length" "8,8,12,12")])
13829
13830 (define_split
13831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13832 (compare:CC
13833 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13834 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13835 (match_operand:SI 3 "gpc_reg_operand" ""))
13836 (const_int 0)))
13837 (clobber (match_scratch:SI 4 ""))]
13838 "TARGET_32BIT && reload_completed"
13839 [(set (match_dup 4)
13840 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13841 (match_dup 3)))
13842 (set (match_dup 0)
13843 (compare:CC (match_dup 4)
13844 (const_int 0)))]
13845 "")
13846
13847 (define_insn ""
13848 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13849 (compare:CC
13850 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13851 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13852 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13853 (const_int 0)))
13854 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13855 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13856 "TARGET_32BIT"
13857 "@
13858 subfc %0,%2,%1\;addze. %0,%3
13859 addic %0,%1,%n2\;addze. %0,%3
13860 #
13861 #"
13862 [(set_attr "type" "compare")
13863 (set_attr "length" "8,8,12,12")])
13864
13865 (define_split
13866 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13867 (compare:CC
13868 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13869 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13870 (match_operand:SI 3 "gpc_reg_operand" ""))
13871 (const_int 0)))
13872 (set (match_operand:SI 0 "gpc_reg_operand" "")
13873 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13874 "TARGET_32BIT && reload_completed"
13875 [(set (match_dup 0)
13876 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13877 (set (match_dup 4)
13878 (compare:CC (match_dup 0)
13879 (const_int 0)))]
13880 "")
13881
13882 (define_insn "*neg_geu<mode>"
13883 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13884 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13885 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13886 ""
13887 "@
13888 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
13889 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
13890 [(set_attr "type" "three")
13891 (set_attr "length" "12")])
13892
13893 (define_insn "*and_neg_geu<mode>"
13894 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13895 (and:P (neg:P
13896 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13897 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13898 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13899 ""
13900 "@
13901 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
13902 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
13903 [(set_attr "type" "three")
13904 (set_attr "length" "12")])
13905
13906 (define_insn ""
13907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13908 (compare:CC
13909 (and:SI (neg:SI
13910 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13911 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13912 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13913 (const_int 0)))
13914 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13915 "TARGET_32BIT"
13916 "@
13917 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
13918 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
13919 #
13920 #"
13921 [(set_attr "type" "compare")
13922 (set_attr "length" "12,12,16,16")])
13923
13924 (define_split
13925 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13926 (compare:CC
13927 (and:SI (neg:SI
13928 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13929 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13930 (match_operand:SI 3 "gpc_reg_operand" ""))
13931 (const_int 0)))
13932 (clobber (match_scratch:SI 4 ""))]
13933 "TARGET_32BIT && reload_completed"
13934 [(set (match_dup 4)
13935 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13936 (match_dup 3)))
13937 (set (match_dup 0)
13938 (compare:CC (match_dup 4)
13939 (const_int 0)))]
13940 "")
13941
13942 (define_insn ""
13943 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13944 (compare:CC
13945 (and:SI (neg:SI
13946 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13947 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13948 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13949 (const_int 0)))
13950 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13951 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13952 "TARGET_32BIT"
13953 "@
13954 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
13955 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
13956 #
13957 #"
13958 [(set_attr "type" "compare")
13959 (set_attr "length" "12,12,16,16")])
13960
13961 (define_split
13962 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13963 (compare:CC
13964 (and:SI (neg:SI
13965 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13966 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13967 (match_operand:SI 3 "gpc_reg_operand" ""))
13968 (const_int 0)))
13969 (set (match_operand:SI 0 "gpc_reg_operand" "")
13970 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13971 "TARGET_32BIT && reload_completed"
13972 [(set (match_dup 0)
13973 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13974 (set (match_dup 4)
13975 (compare:CC (match_dup 0)
13976 (const_int 0)))]
13977 "")
13978
13979 (define_insn "*plus_gt0<mode>"
13980 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13981 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13982 (const_int 0))
13983 (match_operand:P 2 "gpc_reg_operand" "r")))]
13984 ""
13985 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13986 [(set_attr "type" "three")
13987 (set_attr "length" "12")])
13988
13989 (define_insn ""
13990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13991 (compare:CC
13992 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13993 (const_int 0))
13994 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13995 (const_int 0)))
13996 (clobber (match_scratch:SI 3 "=&r,&r"))]
13997 "TARGET_32BIT"
13998 "@
13999 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14000 #"
14001 [(set_attr "type" "compare")
14002 (set_attr "length" "12,16")])
14003
14004 (define_split
14005 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14006 (compare:CC
14007 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14008 (const_int 0))
14009 (match_operand:SI 2 "gpc_reg_operand" ""))
14010 (const_int 0)))
14011 (clobber (match_scratch:SI 3 ""))]
14012 "TARGET_32BIT && reload_completed"
14013 [(set (match_dup 3)
14014 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14015 (match_dup 2)))
14016 (set (match_dup 0)
14017 (compare:CC (match_dup 3)
14018 (const_int 0)))]
14019 "")
14020
14021 (define_insn ""
14022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14023 (compare:CC
14024 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14025 (const_int 0))
14026 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14027 (const_int 0)))
14028 (clobber (match_scratch:DI 3 "=&r,&r"))]
14029 "TARGET_64BIT"
14030 "@
14031 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14032 #"
14033 [(set_attr "type" "compare")
14034 (set_attr "length" "12,16")])
14035
14036 (define_split
14037 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14038 (compare:CC
14039 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14040 (const_int 0))
14041 (match_operand:DI 2 "gpc_reg_operand" ""))
14042 (const_int 0)))
14043 (clobber (match_scratch:DI 3 ""))]
14044 "TARGET_64BIT && reload_completed"
14045 [(set (match_dup 3)
14046 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14047 (match_dup 2)))
14048 (set (match_dup 0)
14049 (compare:CC (match_dup 3)
14050 (const_int 0)))]
14051 "")
14052
14053 (define_insn ""
14054 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14055 (compare:CC
14056 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14057 (const_int 0))
14058 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14059 (const_int 0)))
14060 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14061 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14062 "TARGET_32BIT"
14063 "@
14064 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14065 #"
14066 [(set_attr "type" "compare")
14067 (set_attr "length" "12,16")])
14068
14069 (define_split
14070 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14071 (compare:CC
14072 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14073 (const_int 0))
14074 (match_operand:SI 2 "gpc_reg_operand" ""))
14075 (const_int 0)))
14076 (set (match_operand:SI 0 "gpc_reg_operand" "")
14077 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14078 "TARGET_32BIT && reload_completed"
14079 [(set (match_dup 0)
14080 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14081 (set (match_dup 3)
14082 (compare:CC (match_dup 0)
14083 (const_int 0)))]
14084 "")
14085
14086 (define_insn ""
14087 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14088 (compare:CC
14089 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14090 (const_int 0))
14091 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14092 (const_int 0)))
14093 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14094 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14095 "TARGET_64BIT"
14096 "@
14097 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14098 #"
14099 [(set_attr "type" "compare")
14100 (set_attr "length" "12,16")])
14101
14102 (define_split
14103 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14104 (compare:CC
14105 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14106 (const_int 0))
14107 (match_operand:DI 2 "gpc_reg_operand" ""))
14108 (const_int 0)))
14109 (set (match_operand:DI 0 "gpc_reg_operand" "")
14110 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14111 "TARGET_64BIT && reload_completed"
14112 [(set (match_dup 0)
14113 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14114 (set (match_dup 3)
14115 (compare:CC (match_dup 0)
14116 (const_int 0)))]
14117 "")
14118
14119 (define_insn_and_split "*gtu<mode>"
14120 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14121 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14122 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14123 ""
14124 "#"
14125 ""
14126 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14127 (set (match_dup 0) (neg:P (match_dup 0)))]
14128 "")
14129
14130 (define_insn_and_split "*gtu<mode>_compare"
14131 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14132 (compare:CC
14133 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14134 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14135 (const_int 0)))
14136 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14137 (gtu:P (match_dup 1) (match_dup 2)))]
14138 ""
14139 "#"
14140 ""
14141 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14142 (parallel [(set (match_dup 3)
14143 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14144 (set (match_dup 0) (neg:P (match_dup 0)))])]
14145 "")
14146
14147 (define_insn_and_split "*plus_gtu<mode>"
14148 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14149 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14150 (match_operand:P 2 "reg_or_short_operand" "rI"))
14151 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14152 ""
14153 "#"
14154 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14155 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14156 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14157 "")
14158
14159 (define_insn_and_split "*plus_gtu<mode>_compare"
14160 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14161 (compare:CC
14162 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14163 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14164 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14165 (const_int 0)))
14166 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14167 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14168 ""
14169 "#"
14170 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14171 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14172 (parallel [(set (match_dup 4)
14173 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14174 (const_int 0)))
14175 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14176 "")
14177
14178 (define_insn "*neg_gtu<mode>"
14179 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14180 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14181 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14182 ""
14183 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
14184 [(set_attr "type" "two")
14185 (set_attr "length" "8")])
14186
14187 \f
14188 ;; Define both directions of branch and return. If we need a reload
14189 ;; register, we'd rather use CR0 since it is much easier to copy a
14190 ;; register CC value to there.
14191
14192 (define_insn ""
14193 [(set (pc)
14194 (if_then_else (match_operator 1 "branch_comparison_operator"
14195 [(match_operand 2
14196 "cc_reg_operand" "y")
14197 (const_int 0)])
14198 (label_ref (match_operand 0 "" ""))
14199 (pc)))]
14200 ""
14201 "*
14202 {
14203 return output_cbranch (operands[1], \"%l0\", 0, insn);
14204 }"
14205 [(set_attr "type" "branch")])
14206
14207 (define_insn ""
14208 [(set (pc)
14209 (if_then_else (match_operator 0 "branch_comparison_operator"
14210 [(match_operand 1
14211 "cc_reg_operand" "y")
14212 (const_int 0)])
14213 (any_return)
14214 (pc)))]
14215 "<return_pred>"
14216 "*
14217 {
14218 return output_cbranch (operands[0], NULL, 0, insn);
14219 }"
14220 [(set_attr "type" "jmpreg")
14221 (set_attr "length" "4")])
14222
14223 (define_insn ""
14224 [(set (pc)
14225 (if_then_else (match_operator 1 "branch_comparison_operator"
14226 [(match_operand 2
14227 "cc_reg_operand" "y")
14228 (const_int 0)])
14229 (pc)
14230 (label_ref (match_operand 0 "" ""))))]
14231 ""
14232 "*
14233 {
14234 return output_cbranch (operands[1], \"%l0\", 1, insn);
14235 }"
14236 [(set_attr "type" "branch")])
14237
14238 (define_insn ""
14239 [(set (pc)
14240 (if_then_else (match_operator 0 "branch_comparison_operator"
14241 [(match_operand 1
14242 "cc_reg_operand" "y")
14243 (const_int 0)])
14244 (pc)
14245 (any_return)))]
14246 "<return_pred>"
14247 "*
14248 {
14249 return output_cbranch (operands[0], NULL, 1, insn);
14250 }"
14251 [(set_attr "type" "jmpreg")
14252 (set_attr "length" "4")])
14253
14254 ;; Logic on condition register values.
14255
14256 ; This pattern matches things like
14257 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14258 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14259 ; (const_int 1)))
14260 ; which are generated by the branch logic.
14261 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14262
14263 (define_insn "*cceq_ior_compare"
14264 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14265 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14266 [(match_operator:SI 2
14267 "branch_positive_comparison_operator"
14268 [(match_operand 3
14269 "cc_reg_operand" "y,y")
14270 (const_int 0)])
14271 (match_operator:SI 4
14272 "branch_positive_comparison_operator"
14273 [(match_operand 5
14274 "cc_reg_operand" "0,y")
14275 (const_int 0)])])
14276 (const_int 1)))]
14277 ""
14278 "cr%q1 %E0,%j2,%j4"
14279 [(set_attr "type" "cr_logical,delayed_cr")])
14280
14281 ; Why is the constant -1 here, but 1 in the previous pattern?
14282 ; Because ~1 has all but the low bit set.
14283 (define_insn ""
14284 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14285 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14286 [(not:SI (match_operator:SI 2
14287 "branch_positive_comparison_operator"
14288 [(match_operand 3
14289 "cc_reg_operand" "y,y")
14290 (const_int 0)]))
14291 (match_operator:SI 4
14292 "branch_positive_comparison_operator"
14293 [(match_operand 5
14294 "cc_reg_operand" "0,y")
14295 (const_int 0)])])
14296 (const_int -1)))]
14297 ""
14298 "cr%q1 %E0,%j2,%j4"
14299 [(set_attr "type" "cr_logical,delayed_cr")])
14300
14301 (define_insn "*cceq_rev_compare"
14302 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14303 (compare:CCEQ (match_operator:SI 1
14304 "branch_positive_comparison_operator"
14305 [(match_operand 2
14306 "cc_reg_operand" "0,y")
14307 (const_int 0)])
14308 (const_int 0)))]
14309 ""
14310 "crnot %E0,%j1"
14311 [(set_attr "type" "cr_logical,delayed_cr")])
14312
14313 ;; If we are comparing the result of two comparisons, this can be done
14314 ;; using creqv or crxor.
14315
14316 (define_insn_and_split ""
14317 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14318 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14319 [(match_operand 2 "cc_reg_operand" "y")
14320 (const_int 0)])
14321 (match_operator 3 "branch_comparison_operator"
14322 [(match_operand 4 "cc_reg_operand" "y")
14323 (const_int 0)])))]
14324 ""
14325 "#"
14326 ""
14327 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14328 (match_dup 5)))]
14329 "
14330 {
14331 int positive_1, positive_2;
14332
14333 positive_1 = branch_positive_comparison_operator (operands[1],
14334 GET_MODE (operands[1]));
14335 positive_2 = branch_positive_comparison_operator (operands[3],
14336 GET_MODE (operands[3]));
14337
14338 if (! positive_1)
14339 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14340 GET_CODE (operands[1])),
14341 SImode,
14342 operands[2], const0_rtx);
14343 else if (GET_MODE (operands[1]) != SImode)
14344 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14345 operands[2], const0_rtx);
14346
14347 if (! positive_2)
14348 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14349 GET_CODE (operands[3])),
14350 SImode,
14351 operands[4], const0_rtx);
14352 else if (GET_MODE (operands[3]) != SImode)
14353 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14354 operands[4], const0_rtx);
14355
14356 if (positive_1 == positive_2)
14357 {
14358 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14359 operands[5] = constm1_rtx;
14360 }
14361 else
14362 {
14363 operands[5] = const1_rtx;
14364 }
14365 }")
14366
14367 ;; Unconditional branch and return.
14368
14369 (define_insn "jump"
14370 [(set (pc)
14371 (label_ref (match_operand 0 "" "")))]
14372 ""
14373 "b %l0"
14374 [(set_attr "type" "branch")])
14375
14376 (define_insn "<return_str>return"
14377 [(any_return)]
14378 "<return_pred>"
14379 "blr"
14380 [(set_attr "type" "jmpreg")])
14381
14382 (define_expand "indirect_jump"
14383 [(set (pc) (match_operand 0 "register_operand" ""))])
14384
14385 (define_insn "*indirect_jump<mode>"
14386 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14387 ""
14388 "@
14389 bctr
14390 blr"
14391 [(set_attr "type" "jmpreg")])
14392
14393 ;; Table jump for switch statements:
14394 (define_expand "tablejump"
14395 [(use (match_operand 0 "" ""))
14396 (use (label_ref (match_operand 1 "" "")))]
14397 ""
14398 "
14399 {
14400 if (TARGET_32BIT)
14401 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14402 else
14403 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14404 DONE;
14405 }")
14406
14407 (define_expand "tablejumpsi"
14408 [(set (match_dup 3)
14409 (plus:SI (match_operand:SI 0 "" "")
14410 (match_dup 2)))
14411 (parallel [(set (pc) (match_dup 3))
14412 (use (label_ref (match_operand 1 "" "")))])]
14413 "TARGET_32BIT"
14414 "
14415 { operands[0] = force_reg (SImode, operands[0]);
14416 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14417 operands[3] = gen_reg_rtx (SImode);
14418 }")
14419
14420 (define_expand "tablejumpdi"
14421 [(set (match_dup 4)
14422 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14423 (set (match_dup 3)
14424 (plus:DI (match_dup 4)
14425 (match_dup 2)))
14426 (parallel [(set (pc) (match_dup 3))
14427 (use (label_ref (match_operand 1 "" "")))])]
14428 "TARGET_64BIT"
14429 "
14430 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14431 operands[3] = gen_reg_rtx (DImode);
14432 operands[4] = gen_reg_rtx (DImode);
14433 }")
14434
14435 (define_insn "*tablejump<mode>_internal1"
14436 [(set (pc)
14437 (match_operand:P 0 "register_operand" "c,*l"))
14438 (use (label_ref (match_operand 1 "" "")))]
14439 ""
14440 "@
14441 bctr
14442 blr"
14443 [(set_attr "type" "jmpreg")])
14444
14445 (define_insn "nop"
14446 [(const_int 0)]
14447 ""
14448 "nop")
14449
14450 (define_insn "group_ending_nop"
14451 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14452 ""
14453 "*
14454 {
14455 if (rs6000_cpu_attr == CPU_POWER6)
14456 return \"ori 1,1,0\";
14457 return \"ori 2,2,0\";
14458 }")
14459 \f
14460 ;; Define the subtract-one-and-jump insns, starting with the template
14461 ;; so loop.c knows what to generate.
14462
14463 (define_expand "doloop_end"
14464 [(use (match_operand 0 "" "")) ; loop pseudo
14465 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14466 (use (match_operand 2 "" "")) ; max iterations
14467 (use (match_operand 3 "" "")) ; loop level
14468 (use (match_operand 4 "" "")) ; label
14469 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
14470 ""
14471 "
14472 {
14473 /* Only use this on innermost loops. */
14474 if (INTVAL (operands[3]) > 1)
14475 FAIL;
14476 if (TARGET_64BIT)
14477 {
14478 if (GET_MODE (operands[0]) != DImode)
14479 FAIL;
14480 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14481 }
14482 else
14483 {
14484 if (GET_MODE (operands[0]) != SImode)
14485 FAIL;
14486 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14487 }
14488 DONE;
14489 }")
14490
14491 (define_expand "ctr<mode>"
14492 [(parallel [(set (pc)
14493 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14494 (const_int 1))
14495 (label_ref (match_operand 1 "" ""))
14496 (pc)))
14497 (set (match_dup 0)
14498 (plus:P (match_dup 0)
14499 (const_int -1)))
14500 (clobber (match_scratch:CC 2 ""))
14501 (clobber (match_scratch:P 3 ""))])]
14502 ""
14503 "")
14504
14505 ;; We need to be able to do this for any operand, including MEM, or we
14506 ;; will cause reload to blow up since we don't allow output reloads on
14507 ;; JUMP_INSNs.
14508 ;; For the length attribute to be calculated correctly, the
14509 ;; label MUST be operand 0.
14510
14511 (define_insn "*ctr<mode>_internal1"
14512 [(set (pc)
14513 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14514 (const_int 1))
14515 (label_ref (match_operand 0 "" ""))
14516 (pc)))
14517 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14518 (plus:P (match_dup 1)
14519 (const_int -1)))
14520 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14521 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14522 ""
14523 "*
14524 {
14525 if (which_alternative != 0)
14526 return \"#\";
14527 else if (get_attr_length (insn) == 4)
14528 return \"bdnz %l0\";
14529 else
14530 return \"bdz $+8\;b %l0\";
14531 }"
14532 [(set_attr "type" "branch")
14533 (set_attr "length" "*,12,16,16")])
14534
14535 (define_insn "*ctr<mode>_internal2"
14536 [(set (pc)
14537 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14538 (const_int 1))
14539 (pc)
14540 (label_ref (match_operand 0 "" ""))))
14541 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14542 (plus:P (match_dup 1)
14543 (const_int -1)))
14544 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14545 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14546 ""
14547 "*
14548 {
14549 if (which_alternative != 0)
14550 return \"#\";
14551 else if (get_attr_length (insn) == 4)
14552 return \"bdz %l0\";
14553 else
14554 return \"bdnz $+8\;b %l0\";
14555 }"
14556 [(set_attr "type" "branch")
14557 (set_attr "length" "*,12,16,16")])
14558
14559 ;; Similar but use EQ
14560
14561 (define_insn "*ctr<mode>_internal5"
14562 [(set (pc)
14563 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14564 (const_int 1))
14565 (label_ref (match_operand 0 "" ""))
14566 (pc)))
14567 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14568 (plus:P (match_dup 1)
14569 (const_int -1)))
14570 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14571 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14572 ""
14573 "*
14574 {
14575 if (which_alternative != 0)
14576 return \"#\";
14577 else if (get_attr_length (insn) == 4)
14578 return \"bdz %l0\";
14579 else
14580 return \"bdnz $+8\;b %l0\";
14581 }"
14582 [(set_attr "type" "branch")
14583 (set_attr "length" "*,12,16,16")])
14584
14585 (define_insn "*ctr<mode>_internal6"
14586 [(set (pc)
14587 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14588 (const_int 1))
14589 (pc)
14590 (label_ref (match_operand 0 "" ""))))
14591 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14592 (plus:P (match_dup 1)
14593 (const_int -1)))
14594 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14595 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14596 ""
14597 "*
14598 {
14599 if (which_alternative != 0)
14600 return \"#\";
14601 else if (get_attr_length (insn) == 4)
14602 return \"bdnz %l0\";
14603 else
14604 return \"bdz $+8\;b %l0\";
14605 }"
14606 [(set_attr "type" "branch")
14607 (set_attr "length" "*,12,16,16")])
14608
14609 ;; Now the splitters if we could not allocate the CTR register
14610
14611 (define_split
14612 [(set (pc)
14613 (if_then_else (match_operator 2 "comparison_operator"
14614 [(match_operand:P 1 "gpc_reg_operand" "")
14615 (const_int 1)])
14616 (match_operand 5 "" "")
14617 (match_operand 6 "" "")))
14618 (set (match_operand:P 0 "gpc_reg_operand" "")
14619 (plus:P (match_dup 1) (const_int -1)))
14620 (clobber (match_scratch:CC 3 ""))
14621 (clobber (match_scratch:P 4 ""))]
14622 "reload_completed"
14623 [(parallel [(set (match_dup 3)
14624 (compare:CC (plus:P (match_dup 1)
14625 (const_int -1))
14626 (const_int 0)))
14627 (set (match_dup 0)
14628 (plus:P (match_dup 1)
14629 (const_int -1)))])
14630 (set (pc) (if_then_else (match_dup 7)
14631 (match_dup 5)
14632 (match_dup 6)))]
14633 "
14634 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14635 operands[3], const0_rtx); }")
14636
14637 (define_split
14638 [(set (pc)
14639 (if_then_else (match_operator 2 "comparison_operator"
14640 [(match_operand:P 1 "gpc_reg_operand" "")
14641 (const_int 1)])
14642 (match_operand 5 "" "")
14643 (match_operand 6 "" "")))
14644 (set (match_operand:P 0 "nonimmediate_operand" "")
14645 (plus:P (match_dup 1) (const_int -1)))
14646 (clobber (match_scratch:CC 3 ""))
14647 (clobber (match_scratch:P 4 ""))]
14648 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14649 [(parallel [(set (match_dup 3)
14650 (compare:CC (plus:P (match_dup 1)
14651 (const_int -1))
14652 (const_int 0)))
14653 (set (match_dup 4)
14654 (plus:P (match_dup 1)
14655 (const_int -1)))])
14656 (set (match_dup 0)
14657 (match_dup 4))
14658 (set (pc) (if_then_else (match_dup 7)
14659 (match_dup 5)
14660 (match_dup 6)))]
14661 "
14662 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14663 operands[3], const0_rtx); }")
14664 \f
14665 (define_insn "trap"
14666 [(trap_if (const_int 1) (const_int 0))]
14667 ""
14668 "trap"
14669 [(set_attr "type" "trap")])
14670
14671 (define_expand "ctrap<mode>4"
14672 [(trap_if (match_operator 0 "ordered_comparison_operator"
14673 [(match_operand:GPR 1 "register_operand")
14674 (match_operand:GPR 2 "reg_or_short_operand")])
14675 (match_operand 3 "zero_constant" ""))]
14676 ""
14677 "")
14678
14679 (define_insn ""
14680 [(trap_if (match_operator 0 "ordered_comparison_operator"
14681 [(match_operand:GPR 1 "register_operand" "r")
14682 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14683 (const_int 0))]
14684 ""
14685 "t<wd>%V0%I2 %1,%2"
14686 [(set_attr "type" "trap")])
14687 \f
14688 ;; Insns related to generating the function prologue and epilogue.
14689
14690 (define_expand "prologue"
14691 [(use (const_int 0))]
14692 ""
14693 {
14694 rs6000_emit_prologue ();
14695 if (!TARGET_SCHED_PROLOG)
14696 emit_insn (gen_blockage ());
14697 DONE;
14698 })
14699
14700 (define_insn "*movesi_from_cr_one"
14701 [(match_parallel 0 "mfcr_operation"
14702 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14703 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14704 (match_operand 3 "immediate_operand" "n")]
14705 UNSPEC_MOVESI_FROM_CR))])]
14706 "TARGET_MFCRF"
14707 "*
14708 {
14709 int mask = 0;
14710 int i;
14711 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14712 {
14713 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14714 operands[4] = GEN_INT (mask);
14715 output_asm_insn (\"mfcr %1,%4\", operands);
14716 }
14717 return \"\";
14718 }"
14719 [(set_attr "type" "mfcrf")])
14720
14721 (define_insn "movesi_from_cr"
14722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14723 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14724 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14725 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14726 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14727 UNSPEC_MOVESI_FROM_CR))]
14728 ""
14729 "mfcr %0"
14730 [(set_attr "type" "mfcr")])
14731
14732 (define_insn "*stmw"
14733 [(match_parallel 0 "stmw_operation"
14734 [(set (match_operand:SI 1 "memory_operand" "=m")
14735 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14736 "TARGET_MULTIPLE"
14737 "stmw %2,%1"
14738 [(set_attr "type" "store_ux")])
14739
14740 ; The following comment applies to:
14741 ; save_gpregs_*
14742 ; save_fpregs_*
14743 ; restore_gpregs*
14744 ; return_and_restore_gpregs*
14745 ; return_and_restore_fpregs*
14746 ; return_and_restore_fpregs_aix*
14747 ;
14748 ; The out-of-line save / restore functions expects one input argument.
14749 ; Since those are not standard call_insn's, we must avoid using
14750 ; MATCH_OPERAND for that argument. That way the register rename
14751 ; optimization will not try to rename this register.
14752 ; Each pattern is repeated for each possible register number used in
14753 ; various ABIs (r11, r1, and for some functions r12)
14754
14755 (define_insn "*save_gpregs_<mode>_r11"
14756 [(match_parallel 0 "any_parallel_operand"
14757 [(clobber (reg:P 65))
14758 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14759 (use (reg:P 11))
14760 (set (match_operand:P 2 "memory_operand" "=m")
14761 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14762 ""
14763 "bl %1"
14764 [(set_attr "type" "branch")
14765 (set_attr "length" "4")])
14766
14767 (define_insn "*save_gpregs_<mode>_r12"
14768 [(match_parallel 0 "any_parallel_operand"
14769 [(clobber (reg:P 65))
14770 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14771 (use (reg:P 12))
14772 (set (match_operand:P 2 "memory_operand" "=m")
14773 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14774 ""
14775 "bl %1"
14776 [(set_attr "type" "branch")
14777 (set_attr "length" "4")])
14778
14779 (define_insn "*save_gpregs_<mode>_r1"
14780 [(match_parallel 0 "any_parallel_operand"
14781 [(clobber (reg:P 65))
14782 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14783 (use (reg:P 1))
14784 (set (match_operand:P 2 "memory_operand" "=m")
14785 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14786 ""
14787 "bl %1"
14788 [(set_attr "type" "branch")
14789 (set_attr "length" "4")])
14790
14791 (define_insn "*save_fpregs_<mode>_r11"
14792 [(match_parallel 0 "any_parallel_operand"
14793 [(clobber (reg:P 65))
14794 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14795 (use (reg:P 11))
14796 (set (match_operand:DF 2 "memory_operand" "=m")
14797 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14798 ""
14799 "bl %1"
14800 [(set_attr "type" "branch")
14801 (set_attr "length" "4")])
14802
14803 (define_insn "*save_fpregs_<mode>_r12"
14804 [(match_parallel 0 "any_parallel_operand"
14805 [(clobber (reg:P 65))
14806 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14807 (use (reg:P 12))
14808 (set (match_operand:DF 2 "memory_operand" "=m")
14809 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14810 ""
14811 "bl %1"
14812 [(set_attr "type" "branch")
14813 (set_attr "length" "4")])
14814
14815 (define_insn "*save_fpregs_<mode>_r1"
14816 [(match_parallel 0 "any_parallel_operand"
14817 [(clobber (reg:P 65))
14818 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14819 (use (reg:P 1))
14820 (set (match_operand:DF 2 "memory_operand" "=m")
14821 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14822 ""
14823 "bl %1"
14824 [(set_attr "type" "branch")
14825 (set_attr "length" "4")])
14826
14827 ; This is to explain that changes to the stack pointer should
14828 ; not be moved over loads from or stores to stack memory.
14829 (define_insn "stack_tie"
14830 [(match_parallel 0 "tie_operand"
14831 [(set (mem:BLK (reg 1)) (const_int 0))])]
14832 ""
14833 ""
14834 [(set_attr "length" "0")])
14835
14836 (define_expand "epilogue"
14837 [(use (const_int 0))]
14838 ""
14839 {
14840 if (!TARGET_SCHED_PROLOG)
14841 emit_insn (gen_blockage ());
14842 rs6000_emit_epilogue (FALSE);
14843 DONE;
14844 })
14845
14846 ; On some processors, doing the mtcrf one CC register at a time is
14847 ; faster (like on the 604e). On others, doing them all at once is
14848 ; faster; for instance, on the 601 and 750.
14849
14850 (define_expand "movsi_to_cr_one"
14851 [(set (match_operand:CC 0 "cc_reg_operand" "")
14852 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14853 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14854 ""
14855 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14856
14857 (define_insn "*movsi_to_cr"
14858 [(match_parallel 0 "mtcrf_operation"
14859 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14860 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14861 (match_operand 3 "immediate_operand" "n")]
14862 UNSPEC_MOVESI_TO_CR))])]
14863 ""
14864 "*
14865 {
14866 int mask = 0;
14867 int i;
14868 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14869 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14870 operands[4] = GEN_INT (mask);
14871 return \"mtcrf %4,%2\";
14872 }"
14873 [(set_attr "type" "mtcr")])
14874
14875 (define_insn "*mtcrfsi"
14876 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14877 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14878 (match_operand 2 "immediate_operand" "n")]
14879 UNSPEC_MOVESI_TO_CR))]
14880 "GET_CODE (operands[0]) == REG
14881 && CR_REGNO_P (REGNO (operands[0]))
14882 && GET_CODE (operands[2]) == CONST_INT
14883 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14884 "mtcrf %R0,%1"
14885 [(set_attr "type" "mtcr")])
14886
14887 ; The load-multiple instructions have similar properties.
14888 ; Note that "load_multiple" is a name known to the machine-independent
14889 ; code that actually corresponds to the PowerPC load-string.
14890
14891 (define_insn "*lmw"
14892 [(match_parallel 0 "lmw_operation"
14893 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14894 (match_operand:SI 2 "memory_operand" "m"))])]
14895 "TARGET_MULTIPLE"
14896 "lmw %1,%2"
14897 [(set_attr "type" "load_ux")
14898 (set_attr "cell_micro" "always")])
14899
14900 (define_insn "*return_internal_<mode>"
14901 [(simple_return)
14902 (use (match_operand:P 0 "register_operand" "lc"))]
14903 ""
14904 "b%T0"
14905 [(set_attr "type" "jmpreg")])
14906
14907 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14908 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14909
14910 ; The following comment applies to:
14911 ; save_gpregs_*
14912 ; save_fpregs_*
14913 ; restore_gpregs*
14914 ; return_and_restore_gpregs*
14915 ; return_and_restore_fpregs*
14916 ; return_and_restore_fpregs_aix*
14917 ;
14918 ; The out-of-line save / restore functions expects one input argument.
14919 ; Since those are not standard call_insn's, we must avoid using
14920 ; MATCH_OPERAND for that argument. That way the register rename
14921 ; optimization will not try to rename this register.
14922 ; Each pattern is repeated for each possible register number used in
14923 ; various ABIs (r11, r1, and for some functions r12)
14924
14925 (define_insn "*restore_gpregs_<mode>_r11"
14926 [(match_parallel 0 "any_parallel_operand"
14927 [(clobber (match_operand:P 1 "register_operand" "=l"))
14928 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14929 (use (reg:P 11))
14930 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14931 (match_operand:P 4 "memory_operand" "m"))])]
14932 ""
14933 "bl %2"
14934 [(set_attr "type" "branch")
14935 (set_attr "length" "4")])
14936
14937 (define_insn "*restore_gpregs_<mode>_r12"
14938 [(match_parallel 0 "any_parallel_operand"
14939 [(clobber (match_operand:P 1 "register_operand" "=l"))
14940 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14941 (use (reg:P 12))
14942 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14943 (match_operand:P 4 "memory_operand" "m"))])]
14944 ""
14945 "bl %2"
14946 [(set_attr "type" "branch")
14947 (set_attr "length" "4")])
14948
14949 (define_insn "*restore_gpregs_<mode>_r1"
14950 [(match_parallel 0 "any_parallel_operand"
14951 [(clobber (match_operand:P 1 "register_operand" "=l"))
14952 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14953 (use (reg:P 1))
14954 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14955 (match_operand:P 4 "memory_operand" "m"))])]
14956 ""
14957 "bl %2"
14958 [(set_attr "type" "branch")
14959 (set_attr "length" "4")])
14960
14961 (define_insn "*return_and_restore_gpregs_<mode>_r11"
14962 [(match_parallel 0 "any_parallel_operand"
14963 [(return)
14964 (clobber (match_operand:P 1 "register_operand" "=l"))
14965 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14966 (use (reg:P 11))
14967 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14968 (match_operand:P 4 "memory_operand" "m"))])]
14969 ""
14970 "b %2"
14971 [(set_attr "type" "branch")
14972 (set_attr "length" "4")])
14973
14974 (define_insn "*return_and_restore_gpregs_<mode>_r12"
14975 [(match_parallel 0 "any_parallel_operand"
14976 [(return)
14977 (clobber (match_operand:P 1 "register_operand" "=l"))
14978 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14979 (use (reg:P 12))
14980 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14981 (match_operand:P 4 "memory_operand" "m"))])]
14982 ""
14983 "b %2"
14984 [(set_attr "type" "branch")
14985 (set_attr "length" "4")])
14986
14987 (define_insn "*return_and_restore_gpregs_<mode>_r1"
14988 [(match_parallel 0 "any_parallel_operand"
14989 [(return)
14990 (clobber (match_operand:P 1 "register_operand" "=l"))
14991 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14992 (use (reg:P 1))
14993 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14994 (match_operand:P 4 "memory_operand" "m"))])]
14995 ""
14996 "b %2"
14997 [(set_attr "type" "branch")
14998 (set_attr "length" "4")])
14999
15000 (define_insn "*return_and_restore_fpregs_<mode>_r11"
15001 [(match_parallel 0 "any_parallel_operand"
15002 [(return)
15003 (clobber (match_operand:P 1 "register_operand" "=l"))
15004 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15005 (use (reg:P 11))
15006 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15007 (match_operand:DF 4 "memory_operand" "m"))])]
15008 ""
15009 "b %2"
15010 [(set_attr "type" "branch")
15011 (set_attr "length" "4")])
15012
15013 (define_insn "*return_and_restore_fpregs_<mode>_r12"
15014 [(match_parallel 0 "any_parallel_operand"
15015 [(return)
15016 (clobber (match_operand:P 1 "register_operand" "=l"))
15017 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15018 (use (reg:P 12))
15019 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15020 (match_operand:DF 4 "memory_operand" "m"))])]
15021 ""
15022 "b %2"
15023 [(set_attr "type" "branch")
15024 (set_attr "length" "4")])
15025
15026 (define_insn "*return_and_restore_fpregs_<mode>_r1"
15027 [(match_parallel 0 "any_parallel_operand"
15028 [(return)
15029 (clobber (match_operand:P 1 "register_operand" "=l"))
15030 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15031 (use (reg:P 1))
15032 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15033 (match_operand:DF 4 "memory_operand" "m"))])]
15034 ""
15035 "b %2"
15036 [(set_attr "type" "branch")
15037 (set_attr "length" "4")])
15038
15039 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
15040 [(match_parallel 0 "any_parallel_operand"
15041 [(return)
15042 (use (match_operand:P 1 "register_operand" "l"))
15043 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15044 (use (reg:P 11))
15045 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15046 (match_operand:DF 4 "memory_operand" "m"))])]
15047 ""
15048 "b %2"
15049 [(set_attr "type" "branch")
15050 (set_attr "length" "4")])
15051
15052 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
15053 [(match_parallel 0 "any_parallel_operand"
15054 [(return)
15055 (use (match_operand:P 1 "register_operand" "l"))
15056 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15057 (use (reg:P 1))
15058 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15059 (match_operand:DF 4 "memory_operand" "m"))])]
15060 ""
15061 "b %2"
15062 [(set_attr "type" "branch")
15063 (set_attr "length" "4")])
15064
15065 ; This is used in compiling the unwind routines.
15066 (define_expand "eh_return"
15067 [(use (match_operand 0 "general_operand" ""))]
15068 ""
15069 "
15070 {
15071 if (TARGET_32BIT)
15072 emit_insn (gen_eh_set_lr_si (operands[0]));
15073 else
15074 emit_insn (gen_eh_set_lr_di (operands[0]));
15075 DONE;
15076 }")
15077
15078 ; We can't expand this before we know where the link register is stored.
15079 (define_insn "eh_set_lr_<mode>"
15080 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15081 UNSPECV_EH_RR)
15082 (clobber (match_scratch:P 1 "=&b"))]
15083 ""
15084 "#")
15085
15086 (define_split
15087 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15088 (clobber (match_scratch 1 ""))]
15089 "reload_completed"
15090 [(const_int 0)]
15091 "
15092 {
15093 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15094 DONE;
15095 }")
15096
15097 (define_insn "prefetch"
15098 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15099 (match_operand:SI 1 "const_int_operand" "n")
15100 (match_operand:SI 2 "const_int_operand" "n"))]
15101 ""
15102 "*
15103 {
15104 if (GET_CODE (operands[0]) == REG)
15105 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15106 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15107 }"
15108 [(set_attr "type" "load")])
15109 \f
15110 (define_insn "bpermd_<mode>"
15111 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15112 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15113 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15114 "TARGET_POPCNTD"
15115 "bpermd %0,%1,%2"
15116 [(set_attr "type" "popcnt")])
15117
15118 \f
15119 ;; Builtin fma support. Handle
15120 ;; Note that the conditions for expansion are in the FMA_F iterator.
15121
15122 (define_expand "fma<mode>4"
15123 [(set (match_operand:FMA_F 0 "register_operand" "")
15124 (fma:FMA_F
15125 (match_operand:FMA_F 1 "register_operand" "")
15126 (match_operand:FMA_F 2 "register_operand" "")
15127 (match_operand:FMA_F 3 "register_operand" "")))]
15128 ""
15129 "")
15130
15131 ; Altivec only has fma and nfms.
15132 (define_expand "fms<mode>4"
15133 [(set (match_operand:FMA_F 0 "register_operand" "")
15134 (fma:FMA_F
15135 (match_operand:FMA_F 1 "register_operand" "")
15136 (match_operand:FMA_F 2 "register_operand" "")
15137 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
15138 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15139 "")
15140
15141 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
15142 (define_expand "fnma<mode>4"
15143 [(set (match_operand:FMA_F 0 "register_operand" "")
15144 (neg:FMA_F
15145 (fma:FMA_F
15146 (match_operand:FMA_F 1 "register_operand" "")
15147 (match_operand:FMA_F 2 "register_operand" "")
15148 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15149 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
15150 "")
15151
15152 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
15153 (define_expand "fnms<mode>4"
15154 [(set (match_operand:FMA_F 0 "register_operand" "")
15155 (neg:FMA_F
15156 (fma:FMA_F
15157 (match_operand:FMA_F 1 "register_operand" "")
15158 (match_operand:FMA_F 2 "register_operand" "")
15159 (match_operand:FMA_F 3 "register_operand" ""))))]
15160 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15161 "")
15162
15163 ; Not an official optab name, but used from builtins.
15164 (define_expand "nfma<mode>4"
15165 [(set (match_operand:FMA_F 0 "register_operand" "")
15166 (neg:FMA_F
15167 (fma:FMA_F
15168 (match_operand:FMA_F 1 "register_operand" "")
15169 (match_operand:FMA_F 2 "register_operand" "")
15170 (match_operand:FMA_F 3 "register_operand" ""))))]
15171 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15172 "")
15173
15174 ; Not an official optab name, but used from builtins.
15175 (define_expand "nfms<mode>4"
15176 [(set (match_operand:FMA_F 0 "register_operand" "")
15177 (neg:FMA_F
15178 (fma:FMA_F
15179 (match_operand:FMA_F 1 "register_operand" "")
15180 (match_operand:FMA_F 2 "register_operand" "")
15181 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15182 ""
15183 "")
15184
15185 (define_expand "rs6000_get_timebase"
15186 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
15187 ""
15188 {
15189 if (TARGET_POWERPC64)
15190 emit_insn (gen_rs6000_mftb_di (operands[0]));
15191 else
15192 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
15193 DONE;
15194 })
15195
15196 (define_insn "rs6000_get_timebase_ppc32"
15197 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
15198 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
15199 (clobber (match_scratch:SI 1 "=r"))
15200 (clobber (match_scratch:CC 2 "=y"))]
15201 "!TARGET_POWERPC64"
15202 {
15203 if (WORDS_BIG_ENDIAN)
15204 if (TARGET_MFCRF)
15205 {
15206 return "mfspr %0,269\;"
15207 "mfspr %L0,268\;"
15208 "mfspr %1,269\;"
15209 "cmpw %2,%0,%1\;"
15210 "bne- %2,$-16";
15211 }
15212 else
15213 {
15214 return "mftbu %0\;"
15215 "mftb %L0\;"
15216 "mftbu %1\;"
15217 "cmpw %2,%0,%1\;"
15218 "bne- %2,$-16";
15219 }
15220 else
15221 if (TARGET_MFCRF)
15222 {
15223 return "mfspr %L0,269\;"
15224 "mfspr %0,268\;"
15225 "mfspr %1,269\;"
15226 "cmpw %2,%L0,%1\;"
15227 "bne- %2,$-16";
15228 }
15229 else
15230 {
15231 return "mftbu %L0\;"
15232 "mftb %0\;"
15233 "mftbu %1\;"
15234 "cmpw %2,%L0,%1\;"
15235 "bne- %2,$-16";
15236 }
15237 })
15238
15239 (define_insn "rs6000_mftb_<mode>"
15240 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15241 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
15242 ""
15243 {
15244 if (TARGET_MFCRF)
15245 return "mfspr %0,268";
15246 else
15247 return "mftb %0";
15248 })
15249
15250 \f
15251
15252 (include "sync.md")
15253 (include "vector.md")
15254 (include "vsx.md")
15255 (include "altivec.md")
15256 (include "spe.md")
15257 (include "dfp.md")
15258 (include "paired.md")
15259 (include "crypto.md")