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[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; REGNOS
27 ;;
28
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (CA_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
52 ;;
53 ;; UNSPEC usage
54 ;;
55
56 (define_c_enum "unspec"
57 [UNSPEC_FRSP ; frsp for POWER machines
58 UNSPEC_PROBE_STACK ; probe stack memory reference
59 UNSPEC_TIE ; tie stack contents and stack pointer
60 UNSPEC_TOCPTR ; address of a word pointing to the TOC
61 UNSPEC_TOC ; address of the TOC (more-or-less)
62 UNSPEC_MOVSI_GOT
63 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
64 UNSPEC_FCTIWZ
65 UNSPEC_FRIM
66 UNSPEC_FRIN
67 UNSPEC_FRIP
68 UNSPEC_FRIZ
69 UNSPEC_LD_MPIC ; load_macho_picbase
70 UNSPEC_MPIC_CORRECT ; macho_correct_pic
71 UNSPEC_TLSGD
72 UNSPEC_TLSLD
73 UNSPEC_MOVESI_FROM_CR
74 UNSPEC_MOVESI_TO_CR
75 UNSPEC_TLSDTPREL
76 UNSPEC_TLSDTPRELHA
77 UNSPEC_TLSDTPRELLO
78 UNSPEC_TLSGOTDTPREL
79 UNSPEC_TLSTPREL
80 UNSPEC_TLSTPRELHA
81 UNSPEC_TLSTPRELLO
82 UNSPEC_TLSGOTTPREL
83 UNSPEC_TLSTLS
84 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
85 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
86 UNSPEC_STFIWX
87 UNSPEC_POPCNTB
88 UNSPEC_FRES
89 UNSPEC_SP_SET
90 UNSPEC_SP_TEST
91 UNSPEC_SYNC
92 UNSPEC_SYNC_OP
93 UNSPEC_ATOMIC
94 UNSPEC_CMPXCHG
95 UNSPEC_XCHG
96 UNSPEC_AND
97 UNSPEC_DLMZB
98 UNSPEC_DLMZB_CR
99 UNSPEC_DLMZB_STRLEN
100 UNSPEC_RSQRT
101 UNSPEC_TOCREL
102 UNSPEC_MACHOPIC_OFFSET
103 UNSPEC_BPERM
104 UNSPEC_COPYSIGN
105 UNSPEC_PARITY
106 UNSPEC_FCTIW
107 UNSPEC_FCTID
108 UNSPEC_LFIWAX
109 UNSPEC_LFIWZX
110 UNSPEC_FCTIWUZ
111 ])
112
113 ;;
114 ;; UNSPEC_VOLATILE usage
115 ;;
116
117 (define_c_enum "unspecv"
118 [UNSPECV_BLOCK
119 UNSPECV_LL ; load-locked
120 UNSPECV_SC ; store-conditional
121 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
122 UNSPECV_EH_RR ; eh_reg_restore
123 UNSPECV_ISYNC ; isync instruction
124 UNSPECV_LWSYNC ; lwsync
125 ])
126
127 \f
128 ;; Define an insn type attribute. This is used in function unit delay
129 ;; computations.
130 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
131 (const_string "integer"))
132
133 ;; Define floating point instruction sub-types for use with Xfpu.md
134 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
135
136 ;; Length (in bytes).
137 ; '(pc)' in the following doesn't include the instruction itself; it is
138 ; calculated as if the instruction had zero size.
139 (define_attr "length" ""
140 (if_then_else (eq_attr "type" "branch")
141 (if_then_else (and (ge (minus (match_dup 0) (pc))
142 (const_int -32768))
143 (lt (minus (match_dup 0) (pc))
144 (const_int 32764)))
145 (const_int 4)
146 (const_int 8))
147 (const_int 4)))
148
149 ;; Processor type -- this attribute must exactly match the processor_type
150 ;; enumeration in rs6000.h.
151
152 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
153 (const (symbol_ref "rs6000_cpu_attr")))
154
155
156 ;; If this instruction is microcoded on the CELL processor
157 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
158 (define_attr "cell_micro" "not,conditional,always"
159 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
160 (const_string "always")
161 (const_string "not")))
162
163 (automata_option "ndfa")
164
165 (include "rios1.md")
166 (include "rios2.md")
167 (include "rs64.md")
168 (include "mpc.md")
169 (include "40x.md")
170 (include "440.md")
171 (include "476.md")
172 (include "603.md")
173 (include "6xx.md")
174 (include "7xx.md")
175 (include "7450.md")
176 (include "8540.md")
177 (include "e300c2c3.md")
178 (include "e500mc.md")
179 (include "e500mc64.md")
180 (include "power4.md")
181 (include "power5.md")
182 (include "power6.md")
183 (include "power7.md")
184 (include "cell.md")
185 (include "xfpu.md")
186 (include "a2.md")
187 (include "titan.md")
188
189 (include "predicates.md")
190 (include "constraints.md")
191
192 (include "darwin.md")
193
194 \f
195 ;; Mode iterators
196
197 ; This mode iterator allows :GPR to be used to indicate the allowable size
198 ; of whole values in GPRs.
199 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
200
201 ; Any supported integer mode.
202 (define_mode_iterator INT [QI HI SI DI TI])
203
204 ; Any supported integer mode that fits in one register.
205 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
206
207 ; extend modes for DImode
208 (define_mode_iterator QHSI [QI HI SI])
209
210 ; SImode or DImode, even if DImode doesn't fit in GPRs.
211 (define_mode_iterator SDI [SI DI])
212
213 ; The size of a pointer. Also, the size of the value that a record-condition
214 ; (one with a '.') will compare; and the size used for arithmetic carries.
215 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
216
217 ; Any hardware-supported floating-point mode
218 (define_mode_iterator FP [
219 (SF "TARGET_HARD_FLOAT
220 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
221 (DF "TARGET_HARD_FLOAT
222 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
223 (TF "!TARGET_IEEEQUAD
224 && TARGET_HARD_FLOAT
225 && (TARGET_FPRS || TARGET_E500_DOUBLE)
226 && TARGET_LONG_DOUBLE_128")
227 (DD "TARGET_DFP")
228 (TD "TARGET_DFP")])
229
230 ; Any fma capable floating-point mode.
231 (define_mode_iterator FMA_F [
232 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
233 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
234 || VECTOR_UNIT_VSX_P (DFmode)")
235 (V2SF "TARGET_PAIRED_FLOAT")
236 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
237 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
238 ])
239
240 ; These modes do not fit in integer registers in 32-bit mode.
241 ; but on e500v2, the gpr are 64 bit registers
242 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
243
244 ; Iterator for reciprocal estimate instructions
245 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
246
247 ; Iterator for just SF/DF
248 (define_mode_iterator SFDF [SF DF])
249
250 ; Various instructions that come in SI and DI forms.
251 ; A generic w/d attribute, for things like cmpw/cmpd.
252 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
253
254 ; DImode bits
255 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
256
257 ;; ISEL/ISEL64 target selection
258 (define_mode_attr sel [(SI "") (DI "64")])
259
260 ;; Suffix for reload patterns
261 (define_mode_attr ptrsize [(SI "32bit")
262 (DI "64bit")])
263
264 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
265 (DI "TARGET_64BIT")])
266
267 (define_mode_attr mptrsize [(SI "si")
268 (DI "di")])
269
270 (define_mode_attr rreg [(SF "f")
271 (DF "ws")
272 (V4SF "wf")
273 (V2DF "wd")])
274
275 (define_mode_attr rreg2 [(SF "f")
276 (DF "d")])
277
278 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
279 (DF "TARGET_FCFID")])
280
281 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
282 (DF "TARGET_E500_DOUBLE")])
283
284 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
285 (DF "TARGET_DOUBLE_FLOAT")])
286 \f
287 ;; Start with fixed-point load and store insns. Here we put only the more
288 ;; complex forms. Basic data transfer is done later.
289
290 (define_expand "zero_extend<mode>di2"
291 [(set (match_operand:DI 0 "gpc_reg_operand" "")
292 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
293 "TARGET_POWERPC64"
294 "")
295
296 (define_insn "*zero_extend<mode>di2_internal1"
297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
298 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
299 "TARGET_POWERPC64"
300 "@
301 l<wd>z%U1%X1 %0,%1
302 rldicl %0,%1,0,<dbits>"
303 [(set_attr "type" "load,*")])
304
305 (define_insn "*zero_extend<mode>di2_internal2"
306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
307 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
308 (const_int 0)))
309 (clobber (match_scratch:DI 2 "=r,r"))]
310 "TARGET_64BIT"
311 "@
312 rldicl. %2,%1,0,<dbits>
313 #"
314 [(set_attr "type" "compare")
315 (set_attr "length" "4,8")])
316
317 (define_split
318 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
319 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
320 (const_int 0)))
321 (clobber (match_scratch:DI 2 ""))]
322 "TARGET_POWERPC64 && reload_completed"
323 [(set (match_dup 2)
324 (zero_extend:DI (match_dup 1)))
325 (set (match_dup 0)
326 (compare:CC (match_dup 2)
327 (const_int 0)))]
328 "")
329
330 (define_insn "*zero_extend<mode>di2_internal3"
331 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
332 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
333 (const_int 0)))
334 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
335 (zero_extend:DI (match_dup 1)))]
336 "TARGET_64BIT"
337 "@
338 rldicl. %0,%1,0,<dbits>
339 #"
340 [(set_attr "type" "compare")
341 (set_attr "length" "4,8")])
342
343 (define_split
344 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
345 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
346 (const_int 0)))
347 (set (match_operand:DI 0 "gpc_reg_operand" "")
348 (zero_extend:DI (match_dup 1)))]
349 "TARGET_POWERPC64 && reload_completed"
350 [(set (match_dup 0)
351 (zero_extend:DI (match_dup 1)))
352 (set (match_dup 2)
353 (compare:CC (match_dup 0)
354 (const_int 0)))]
355 "")
356
357 (define_insn "extendqidi2"
358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
359 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
360 "TARGET_POWERPC64"
361 "extsb %0,%1"
362 [(set_attr "type" "exts")])
363
364 (define_insn ""
365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
366 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
367 (const_int 0)))
368 (clobber (match_scratch:DI 2 "=r,r"))]
369 "TARGET_64BIT"
370 "@
371 extsb. %2,%1
372 #"
373 [(set_attr "type" "compare")
374 (set_attr "length" "4,8")])
375
376 (define_split
377 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
378 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
379 (const_int 0)))
380 (clobber (match_scratch:DI 2 ""))]
381 "TARGET_POWERPC64 && reload_completed"
382 [(set (match_dup 2)
383 (sign_extend:DI (match_dup 1)))
384 (set (match_dup 0)
385 (compare:CC (match_dup 2)
386 (const_int 0)))]
387 "")
388
389 (define_insn ""
390 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
394 (sign_extend:DI (match_dup 1)))]
395 "TARGET_64BIT"
396 "@
397 extsb. %0,%1
398 #"
399 [(set_attr "type" "compare")
400 (set_attr "length" "4,8")])
401
402 (define_split
403 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
404 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
405 (const_int 0)))
406 (set (match_operand:DI 0 "gpc_reg_operand" "")
407 (sign_extend:DI (match_dup 1)))]
408 "TARGET_POWERPC64 && reload_completed"
409 [(set (match_dup 0)
410 (sign_extend:DI (match_dup 1)))
411 (set (match_dup 2)
412 (compare:CC (match_dup 0)
413 (const_int 0)))]
414 "")
415
416 (define_expand "extendhidi2"
417 [(set (match_operand:DI 0 "gpc_reg_operand" "")
418 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
419 "TARGET_POWERPC64"
420 "")
421
422 (define_insn ""
423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
424 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
425 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
426 "@
427 lha%U1%X1 %0,%1
428 extsh %0,%1"
429 [(set_attr "type" "load_ext,exts")])
430
431 (define_insn ""
432 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
433 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
434 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
435 "extsh %0,%1"
436 [(set_attr "type" "exts")])
437
438 (define_insn ""
439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
440 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
441 (const_int 0)))
442 (clobber (match_scratch:DI 2 "=r,r"))]
443 "TARGET_64BIT"
444 "@
445 extsh. %2,%1
446 #"
447 [(set_attr "type" "compare")
448 (set_attr "length" "4,8")])
449
450 (define_split
451 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
452 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
453 (const_int 0)))
454 (clobber (match_scratch:DI 2 ""))]
455 "TARGET_POWERPC64 && reload_completed"
456 [(set (match_dup 2)
457 (sign_extend:DI (match_dup 1)))
458 (set (match_dup 0)
459 (compare:CC (match_dup 2)
460 (const_int 0)))]
461 "")
462
463 (define_insn ""
464 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
465 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
468 (sign_extend:DI (match_dup 1)))]
469 "TARGET_64BIT"
470 "@
471 extsh. %0,%1
472 #"
473 [(set_attr "type" "compare")
474 (set_attr "length" "4,8")])
475
476 (define_split
477 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
478 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
479 (const_int 0)))
480 (set (match_operand:DI 0 "gpc_reg_operand" "")
481 (sign_extend:DI (match_dup 1)))]
482 "TARGET_POWERPC64 && reload_completed"
483 [(set (match_dup 0)
484 (sign_extend:DI (match_dup 1)))
485 (set (match_dup 2)
486 (compare:CC (match_dup 0)
487 (const_int 0)))]
488 "")
489
490 (define_expand "extendsidi2"
491 [(set (match_operand:DI 0 "gpc_reg_operand" "")
492 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
493 "TARGET_POWERPC64"
494 "")
495
496 (define_insn ""
497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
498 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
499 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
500 "@
501 lwa%U1%X1 %0,%1
502 extsw %0,%1"
503 [(set_attr "type" "load_ext,exts")])
504
505 (define_insn ""
506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
507 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
508 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
509 "extsw %0,%1"
510 [(set_attr "type" "exts")])
511
512 (define_insn ""
513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
514 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
515 (const_int 0)))
516 (clobber (match_scratch:DI 2 "=r,r"))]
517 "TARGET_64BIT"
518 "@
519 extsw. %2,%1
520 #"
521 [(set_attr "type" "compare")
522 (set_attr "length" "4,8")])
523
524 (define_split
525 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
526 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
527 (const_int 0)))
528 (clobber (match_scratch:DI 2 ""))]
529 "TARGET_POWERPC64 && reload_completed"
530 [(set (match_dup 2)
531 (sign_extend:DI (match_dup 1)))
532 (set (match_dup 0)
533 (compare:CC (match_dup 2)
534 (const_int 0)))]
535 "")
536
537 (define_insn ""
538 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
540 (const_int 0)))
541 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
542 (sign_extend:DI (match_dup 1)))]
543 "TARGET_64BIT"
544 "@
545 extsw. %0,%1
546 #"
547 [(set_attr "type" "compare")
548 (set_attr "length" "4,8")])
549
550 (define_split
551 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
552 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
553 (const_int 0)))
554 (set (match_operand:DI 0 "gpc_reg_operand" "")
555 (sign_extend:DI (match_dup 1)))]
556 "TARGET_POWERPC64 && reload_completed"
557 [(set (match_dup 0)
558 (sign_extend:DI (match_dup 1)))
559 (set (match_dup 2)
560 (compare:CC (match_dup 0)
561 (const_int 0)))]
562 "")
563
564 (define_expand "zero_extendqisi2"
565 [(set (match_operand:SI 0 "gpc_reg_operand" "")
566 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
567 ""
568 "")
569
570 (define_insn ""
571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
572 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
573 ""
574 "@
575 lbz%U1%X1 %0,%1
576 {rlinm|rlwinm} %0,%1,0,0xff"
577 [(set_attr "type" "load,*")])
578
579 (define_insn ""
580 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
581 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
582 (const_int 0)))
583 (clobber (match_scratch:SI 2 "=r,r"))]
584 ""
585 "@
586 {andil.|andi.} %2,%1,0xff
587 #"
588 [(set_attr "type" "fast_compare,compare")
589 (set_attr "length" "4,8")])
590
591 (define_split
592 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
593 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
594 (const_int 0)))
595 (clobber (match_scratch:SI 2 ""))]
596 "reload_completed"
597 [(set (match_dup 2)
598 (zero_extend:SI (match_dup 1)))
599 (set (match_dup 0)
600 (compare:CC (match_dup 2)
601 (const_int 0)))]
602 "")
603
604 (define_insn ""
605 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
609 (zero_extend:SI (match_dup 1)))]
610 ""
611 "@
612 {andil.|andi.} %0,%1,0xff
613 #"
614 [(set_attr "type" "fast_compare,compare")
615 (set_attr "length" "4,8")])
616
617 (define_split
618 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
619 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
620 (const_int 0)))
621 (set (match_operand:SI 0 "gpc_reg_operand" "")
622 (zero_extend:SI (match_dup 1)))]
623 "reload_completed"
624 [(set (match_dup 0)
625 (zero_extend:SI (match_dup 1)))
626 (set (match_dup 2)
627 (compare:CC (match_dup 0)
628 (const_int 0)))]
629 "")
630
631 (define_expand "extendqisi2"
632 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
633 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
634 ""
635 "
636 {
637 if (TARGET_POWERPC)
638 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
639 else if (TARGET_POWER)
640 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
641 else
642 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
643 DONE;
644 }")
645
646 (define_insn "extendqisi2_ppc"
647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
648 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
649 "TARGET_POWERPC"
650 "extsb %0,%1"
651 [(set_attr "type" "exts")])
652
653 (define_insn ""
654 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
655 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
656 (const_int 0)))
657 (clobber (match_scratch:SI 2 "=r,r"))]
658 "TARGET_POWERPC"
659 "@
660 extsb. %2,%1
661 #"
662 [(set_attr "type" "compare")
663 (set_attr "length" "4,8")])
664
665 (define_split
666 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
667 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
668 (const_int 0)))
669 (clobber (match_scratch:SI 2 ""))]
670 "TARGET_POWERPC && reload_completed"
671 [(set (match_dup 2)
672 (sign_extend:SI (match_dup 1)))
673 (set (match_dup 0)
674 (compare:CC (match_dup 2)
675 (const_int 0)))]
676 "")
677
678 (define_insn ""
679 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
680 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
681 (const_int 0)))
682 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
683 (sign_extend:SI (match_dup 1)))]
684 "TARGET_POWERPC"
685 "@
686 extsb. %0,%1
687 #"
688 [(set_attr "type" "compare")
689 (set_attr "length" "4,8")])
690
691 (define_split
692 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
693 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
694 (const_int 0)))
695 (set (match_operand:SI 0 "gpc_reg_operand" "")
696 (sign_extend:SI (match_dup 1)))]
697 "TARGET_POWERPC && reload_completed"
698 [(set (match_dup 0)
699 (sign_extend:SI (match_dup 1)))
700 (set (match_dup 2)
701 (compare:CC (match_dup 0)
702 (const_int 0)))]
703 "")
704
705 (define_expand "extendqisi2_power"
706 [(parallel [(set (match_dup 2)
707 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
708 (const_int 24)))
709 (clobber (scratch:SI))])
710 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
711 (ashiftrt:SI (match_dup 2)
712 (const_int 24)))
713 (clobber (scratch:SI))])]
714 "TARGET_POWER"
715 "
716 { operands[1] = gen_lowpart (SImode, operands[1]);
717 operands[2] = gen_reg_rtx (SImode); }")
718
719 (define_expand "extendqisi2_no_power"
720 [(set (match_dup 2)
721 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
722 (const_int 24)))
723 (set (match_operand:SI 0 "gpc_reg_operand" "")
724 (ashiftrt:SI (match_dup 2)
725 (const_int 24)))]
726 "! TARGET_POWER && ! TARGET_POWERPC"
727 "
728 { operands[1] = gen_lowpart (SImode, operands[1]);
729 operands[2] = gen_reg_rtx (SImode); }")
730
731 (define_expand "zero_extendqihi2"
732 [(set (match_operand:HI 0 "gpc_reg_operand" "")
733 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
734 ""
735 "")
736
737 (define_insn ""
738 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
739 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
740 ""
741 "@
742 lbz%U1%X1 %0,%1
743 {rlinm|rlwinm} %0,%1,0,0xff"
744 [(set_attr "type" "load,*")])
745
746 (define_insn ""
747 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
748 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
749 (const_int 0)))
750 (clobber (match_scratch:HI 2 "=r,r"))]
751 ""
752 "@
753 {andil.|andi.} %2,%1,0xff
754 #"
755 [(set_attr "type" "fast_compare,compare")
756 (set_attr "length" "4,8")])
757
758 (define_split
759 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
760 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
761 (const_int 0)))
762 (clobber (match_scratch:HI 2 ""))]
763 "reload_completed"
764 [(set (match_dup 2)
765 (zero_extend:HI (match_dup 1)))
766 (set (match_dup 0)
767 (compare:CC (match_dup 2)
768 (const_int 0)))]
769 "")
770
771 (define_insn ""
772 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
773 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
774 (const_int 0)))
775 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
776 (zero_extend:HI (match_dup 1)))]
777 ""
778 "@
779 {andil.|andi.} %0,%1,0xff
780 #"
781 [(set_attr "type" "fast_compare,compare")
782 (set_attr "length" "4,8")])
783
784 (define_split
785 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
786 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
787 (const_int 0)))
788 (set (match_operand:HI 0 "gpc_reg_operand" "")
789 (zero_extend:HI (match_dup 1)))]
790 "reload_completed"
791 [(set (match_dup 0)
792 (zero_extend:HI (match_dup 1)))
793 (set (match_dup 2)
794 (compare:CC (match_dup 0)
795 (const_int 0)))]
796 "")
797
798 (define_expand "extendqihi2"
799 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
800 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
801 ""
802 "
803 {
804 if (TARGET_POWERPC)
805 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
806 else if (TARGET_POWER)
807 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
808 else
809 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
810 DONE;
811 }")
812
813 (define_insn "extendqihi2_ppc"
814 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
815 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
816 "TARGET_POWERPC"
817 "extsb %0,%1"
818 [(set_attr "type" "exts")])
819
820 (define_insn ""
821 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
822 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
823 (const_int 0)))
824 (clobber (match_scratch:HI 2 "=r,r"))]
825 "TARGET_POWERPC"
826 "@
827 extsb. %2,%1
828 #"
829 [(set_attr "type" "compare")
830 (set_attr "length" "4,8")])
831
832 (define_split
833 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
834 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
835 (const_int 0)))
836 (clobber (match_scratch:HI 2 ""))]
837 "TARGET_POWERPC && reload_completed"
838 [(set (match_dup 2)
839 (sign_extend:HI (match_dup 1)))
840 (set (match_dup 0)
841 (compare:CC (match_dup 2)
842 (const_int 0)))]
843 "")
844
845 (define_insn ""
846 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
847 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
848 (const_int 0)))
849 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
850 (sign_extend:HI (match_dup 1)))]
851 "TARGET_POWERPC"
852 "@
853 extsb. %0,%1
854 #"
855 [(set_attr "type" "compare")
856 (set_attr "length" "4,8")])
857
858 (define_split
859 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
860 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
861 (const_int 0)))
862 (set (match_operand:HI 0 "gpc_reg_operand" "")
863 (sign_extend:HI (match_dup 1)))]
864 "TARGET_POWERPC && reload_completed"
865 [(set (match_dup 0)
866 (sign_extend:HI (match_dup 1)))
867 (set (match_dup 2)
868 (compare:CC (match_dup 0)
869 (const_int 0)))]
870 "")
871
872 (define_expand "extendqihi2_power"
873 [(parallel [(set (match_dup 2)
874 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
875 (const_int 24)))
876 (clobber (scratch:SI))])
877 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
878 (ashiftrt:SI (match_dup 2)
879 (const_int 24)))
880 (clobber (scratch:SI))])]
881 "TARGET_POWER"
882 "
883 { operands[0] = gen_lowpart (SImode, operands[0]);
884 operands[1] = gen_lowpart (SImode, operands[1]);
885 operands[2] = gen_reg_rtx (SImode); }")
886
887 (define_expand "extendqihi2_no_power"
888 [(set (match_dup 2)
889 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
890 (const_int 24)))
891 (set (match_operand:HI 0 "gpc_reg_operand" "")
892 (ashiftrt:SI (match_dup 2)
893 (const_int 24)))]
894 "! TARGET_POWER && ! TARGET_POWERPC"
895 "
896 { operands[0] = gen_lowpart (SImode, operands[0]);
897 operands[1] = gen_lowpart (SImode, operands[1]);
898 operands[2] = gen_reg_rtx (SImode); }")
899
900 (define_expand "zero_extendhisi2"
901 [(set (match_operand:SI 0 "gpc_reg_operand" "")
902 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
903 ""
904 "")
905
906 (define_insn ""
907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
908 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
909 ""
910 "@
911 lhz%U1%X1 %0,%1
912 {rlinm|rlwinm} %0,%1,0,0xffff"
913 [(set_attr "type" "load,*")])
914
915 (define_insn ""
916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
917 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
918 (const_int 0)))
919 (clobber (match_scratch:SI 2 "=r,r"))]
920 ""
921 "@
922 {andil.|andi.} %2,%1,0xffff
923 #"
924 [(set_attr "type" "fast_compare,compare")
925 (set_attr "length" "4,8")])
926
927 (define_split
928 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
929 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
930 (const_int 0)))
931 (clobber (match_scratch:SI 2 ""))]
932 "reload_completed"
933 [(set (match_dup 2)
934 (zero_extend:SI (match_dup 1)))
935 (set (match_dup 0)
936 (compare:CC (match_dup 2)
937 (const_int 0)))]
938 "")
939
940 (define_insn ""
941 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
942 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
943 (const_int 0)))
944 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
945 (zero_extend:SI (match_dup 1)))]
946 ""
947 "@
948 {andil.|andi.} %0,%1,0xffff
949 #"
950 [(set_attr "type" "fast_compare,compare")
951 (set_attr "length" "4,8")])
952
953 (define_split
954 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
955 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
956 (const_int 0)))
957 (set (match_operand:SI 0 "gpc_reg_operand" "")
958 (zero_extend:SI (match_dup 1)))]
959 "reload_completed"
960 [(set (match_dup 0)
961 (zero_extend:SI (match_dup 1)))
962 (set (match_dup 2)
963 (compare:CC (match_dup 0)
964 (const_int 0)))]
965 "")
966
967 (define_expand "extendhisi2"
968 [(set (match_operand:SI 0 "gpc_reg_operand" "")
969 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
970 ""
971 "")
972
973 (define_insn ""
974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
975 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
976 "rs6000_gen_cell_microcode"
977 "@
978 lha%U1%X1 %0,%1
979 {exts|extsh} %0,%1"
980 [(set_attr "type" "load_ext,exts")])
981
982 (define_insn ""
983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
984 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
985 "!rs6000_gen_cell_microcode"
986 "{exts|extsh} %0,%1"
987 [(set_attr "type" "exts")])
988
989 (define_insn ""
990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
991 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
992 (const_int 0)))
993 (clobber (match_scratch:SI 2 "=r,r"))]
994 ""
995 "@
996 {exts.|extsh.} %2,%1
997 #"
998 [(set_attr "type" "compare")
999 (set_attr "length" "4,8")])
1000
1001 (define_split
1002 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1003 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1004 (const_int 0)))
1005 (clobber (match_scratch:SI 2 ""))]
1006 "reload_completed"
1007 [(set (match_dup 2)
1008 (sign_extend:SI (match_dup 1)))
1009 (set (match_dup 0)
1010 (compare:CC (match_dup 2)
1011 (const_int 0)))]
1012 "")
1013
1014 (define_insn ""
1015 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1016 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1017 (const_int 0)))
1018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1019 (sign_extend:SI (match_dup 1)))]
1020 ""
1021 "@
1022 {exts.|extsh.} %0,%1
1023 #"
1024 [(set_attr "type" "compare")
1025 (set_attr "length" "4,8")])
1026 \f
1027 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1028
1029 (define_insn "*macchwc"
1030 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1031 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1032 (match_operand:SI 2 "gpc_reg_operand" "r")
1033 (const_int 16))
1034 (sign_extend:SI
1035 (match_operand:HI 1 "gpc_reg_operand" "r")))
1036 (match_operand:SI 4 "gpc_reg_operand" "0"))
1037 (const_int 0)))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1039 (plus:SI (mult:SI (ashiftrt:SI
1040 (match_dup 2)
1041 (const_int 16))
1042 (sign_extend:SI
1043 (match_dup 1)))
1044 (match_dup 4)))]
1045 "TARGET_MULHW"
1046 "macchw. %0, %1, %2"
1047 [(set_attr "type" "imul3")])
1048
1049 (define_insn "*macchw"
1050 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1051 (plus:SI (mult:SI (ashiftrt:SI
1052 (match_operand:SI 2 "gpc_reg_operand" "r")
1053 (const_int 16))
1054 (sign_extend:SI
1055 (match_operand:HI 1 "gpc_reg_operand" "r")))
1056 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1057 "TARGET_MULHW"
1058 "macchw %0, %1, %2"
1059 [(set_attr "type" "imul3")])
1060
1061 (define_insn "*macchwuc"
1062 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1063 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1064 (match_operand:SI 2 "gpc_reg_operand" "r")
1065 (const_int 16))
1066 (zero_extend:SI
1067 (match_operand:HI 1 "gpc_reg_operand" "r")))
1068 (match_operand:SI 4 "gpc_reg_operand" "0"))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (lshiftrt:SI
1072 (match_dup 2)
1073 (const_int 16))
1074 (zero_extend:SI
1075 (match_dup 1)))
1076 (match_dup 4)))]
1077 "TARGET_MULHW"
1078 "macchwu. %0, %1, %2"
1079 [(set_attr "type" "imul3")])
1080
1081 (define_insn "*macchwu"
1082 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1083 (plus:SI (mult:SI (lshiftrt:SI
1084 (match_operand:SI 2 "gpc_reg_operand" "r")
1085 (const_int 16))
1086 (zero_extend:SI
1087 (match_operand:HI 1 "gpc_reg_operand" "r")))
1088 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1089 "TARGET_MULHW"
1090 "macchwu %0, %1, %2"
1091 [(set_attr "type" "imul3")])
1092
1093 (define_insn "*machhwc"
1094 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1095 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1096 (match_operand:SI 1 "gpc_reg_operand" "%r")
1097 (const_int 16))
1098 (ashiftrt:SI
1099 (match_operand:SI 2 "gpc_reg_operand" "r")
1100 (const_int 16)))
1101 (match_operand:SI 4 "gpc_reg_operand" "0"))
1102 (const_int 0)))
1103 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1104 (plus:SI (mult:SI (ashiftrt:SI
1105 (match_dup 1)
1106 (const_int 16))
1107 (ashiftrt:SI
1108 (match_dup 2)
1109 (const_int 16)))
1110 (match_dup 4)))]
1111 "TARGET_MULHW"
1112 "machhw. %0, %1, %2"
1113 [(set_attr "type" "imul3")])
1114
1115 (define_insn "*machhw"
1116 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1117 (plus:SI (mult:SI (ashiftrt:SI
1118 (match_operand:SI 1 "gpc_reg_operand" "%r")
1119 (const_int 16))
1120 (ashiftrt:SI
1121 (match_operand:SI 2 "gpc_reg_operand" "r")
1122 (const_int 16)))
1123 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1124 "TARGET_MULHW"
1125 "machhw %0, %1, %2"
1126 [(set_attr "type" "imul3")])
1127
1128 (define_insn "*machhwuc"
1129 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1130 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1131 (match_operand:SI 1 "gpc_reg_operand" "%r")
1132 (const_int 16))
1133 (lshiftrt:SI
1134 (match_operand:SI 2 "gpc_reg_operand" "r")
1135 (const_int 16)))
1136 (match_operand:SI 4 "gpc_reg_operand" "0"))
1137 (const_int 0)))
1138 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1139 (plus:SI (mult:SI (lshiftrt:SI
1140 (match_dup 1)
1141 (const_int 16))
1142 (lshiftrt:SI
1143 (match_dup 2)
1144 (const_int 16)))
1145 (match_dup 4)))]
1146 "TARGET_MULHW"
1147 "machhwu. %0, %1, %2"
1148 [(set_attr "type" "imul3")])
1149
1150 (define_insn "*machhwu"
1151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1152 (plus:SI (mult:SI (lshiftrt:SI
1153 (match_operand:SI 1 "gpc_reg_operand" "%r")
1154 (const_int 16))
1155 (lshiftrt:SI
1156 (match_operand:SI 2 "gpc_reg_operand" "r")
1157 (const_int 16)))
1158 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1159 "TARGET_MULHW"
1160 "machhwu %0, %1, %2"
1161 [(set_attr "type" "imul3")])
1162
1163 (define_insn "*maclhwc"
1164 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1165 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1166 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1167 (sign_extend:SI
1168 (match_operand:HI 2 "gpc_reg_operand" "r")))
1169 (match_operand:SI 4 "gpc_reg_operand" "0"))
1170 (const_int 0)))
1171 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1172 (plus:SI (mult:SI (sign_extend:SI
1173 (match_dup 1))
1174 (sign_extend:SI
1175 (match_dup 2)))
1176 (match_dup 4)))]
1177 "TARGET_MULHW"
1178 "maclhw. %0, %1, %2"
1179 [(set_attr "type" "imul3")])
1180
1181 (define_insn "*maclhw"
1182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1183 (plus:SI (mult:SI (sign_extend:SI
1184 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1185 (sign_extend:SI
1186 (match_operand:HI 2 "gpc_reg_operand" "r")))
1187 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1188 "TARGET_MULHW"
1189 "maclhw %0, %1, %2"
1190 [(set_attr "type" "imul3")])
1191
1192 (define_insn "*maclhwuc"
1193 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1194 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1195 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1196 (zero_extend:SI
1197 (match_operand:HI 2 "gpc_reg_operand" "r")))
1198 (match_operand:SI 4 "gpc_reg_operand" "0"))
1199 (const_int 0)))
1200 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1201 (plus:SI (mult:SI (zero_extend:SI
1202 (match_dup 1))
1203 (zero_extend:SI
1204 (match_dup 2)))
1205 (match_dup 4)))]
1206 "TARGET_MULHW"
1207 "maclhwu. %0, %1, %2"
1208 [(set_attr "type" "imul3")])
1209
1210 (define_insn "*maclhwu"
1211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1212 (plus:SI (mult:SI (zero_extend:SI
1213 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1214 (zero_extend:SI
1215 (match_operand:HI 2 "gpc_reg_operand" "r")))
1216 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1217 "TARGET_MULHW"
1218 "maclhwu %0, %1, %2"
1219 [(set_attr "type" "imul3")])
1220
1221 (define_insn "*nmacchwc"
1222 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1223 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1224 (mult:SI (ashiftrt:SI
1225 (match_operand:SI 2 "gpc_reg_operand" "r")
1226 (const_int 16))
1227 (sign_extend:SI
1228 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1229 (const_int 0)))
1230 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1231 (minus:SI (match_dup 4)
1232 (mult:SI (ashiftrt:SI
1233 (match_dup 2)
1234 (const_int 16))
1235 (sign_extend:SI
1236 (match_dup 1)))))]
1237 "TARGET_MULHW"
1238 "nmacchw. %0, %1, %2"
1239 [(set_attr "type" "imul3")])
1240
1241 (define_insn "*nmacchw"
1242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1244 (mult:SI (ashiftrt:SI
1245 (match_operand:SI 2 "gpc_reg_operand" "r")
1246 (const_int 16))
1247 (sign_extend:SI
1248 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1249 "TARGET_MULHW"
1250 "nmacchw %0, %1, %2"
1251 [(set_attr "type" "imul3")])
1252
1253 (define_insn "*nmachhwc"
1254 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1255 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1256 (mult:SI (ashiftrt:SI
1257 (match_operand:SI 1 "gpc_reg_operand" "%r")
1258 (const_int 16))
1259 (ashiftrt:SI
1260 (match_operand:SI 2 "gpc_reg_operand" "r")
1261 (const_int 16))))
1262 (const_int 0)))
1263 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1264 (minus:SI (match_dup 4)
1265 (mult:SI (ashiftrt:SI
1266 (match_dup 1)
1267 (const_int 16))
1268 (ashiftrt:SI
1269 (match_dup 2)
1270 (const_int 16)))))]
1271 "TARGET_MULHW"
1272 "nmachhw. %0, %1, %2"
1273 [(set_attr "type" "imul3")])
1274
1275 (define_insn "*nmachhw"
1276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1277 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1278 (mult:SI (ashiftrt:SI
1279 (match_operand:SI 1 "gpc_reg_operand" "%r")
1280 (const_int 16))
1281 (ashiftrt:SI
1282 (match_operand:SI 2 "gpc_reg_operand" "r")
1283 (const_int 16)))))]
1284 "TARGET_MULHW"
1285 "nmachhw %0, %1, %2"
1286 [(set_attr "type" "imul3")])
1287
1288 (define_insn "*nmaclhwc"
1289 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1290 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1291 (mult:SI (sign_extend:SI
1292 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1293 (sign_extend:SI
1294 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1295 (const_int 0)))
1296 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (minus:SI (match_dup 4)
1298 (mult:SI (sign_extend:SI
1299 (match_dup 1))
1300 (sign_extend:SI
1301 (match_dup 2)))))]
1302 "TARGET_MULHW"
1303 "nmaclhw. %0, %1, %2"
1304 [(set_attr "type" "imul3")])
1305
1306 (define_insn "*nmaclhw"
1307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1308 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1309 (mult:SI (sign_extend:SI
1310 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1311 (sign_extend:SI
1312 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1313 "TARGET_MULHW"
1314 "nmaclhw %0, %1, %2"
1315 [(set_attr "type" "imul3")])
1316
1317 (define_insn "*mulchwc"
1318 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1319 (compare:CC (mult:SI (ashiftrt:SI
1320 (match_operand:SI 2 "gpc_reg_operand" "r")
1321 (const_int 16))
1322 (sign_extend:SI
1323 (match_operand:HI 1 "gpc_reg_operand" "r")))
1324 (const_int 0)))
1325 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1326 (mult:SI (ashiftrt:SI
1327 (match_dup 2)
1328 (const_int 16))
1329 (sign_extend:SI
1330 (match_dup 1))))]
1331 "TARGET_MULHW"
1332 "mulchw. %0, %1, %2"
1333 [(set_attr "type" "imul3")])
1334
1335 (define_insn "*mulchw"
1336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1337 (mult:SI (ashiftrt:SI
1338 (match_operand:SI 2 "gpc_reg_operand" "r")
1339 (const_int 16))
1340 (sign_extend:SI
1341 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1342 "TARGET_MULHW"
1343 "mulchw %0, %1, %2"
1344 [(set_attr "type" "imul3")])
1345
1346 (define_insn "*mulchwuc"
1347 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1348 (compare:CC (mult:SI (lshiftrt:SI
1349 (match_operand:SI 2 "gpc_reg_operand" "r")
1350 (const_int 16))
1351 (zero_extend:SI
1352 (match_operand:HI 1 "gpc_reg_operand" "r")))
1353 (const_int 0)))
1354 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1355 (mult:SI (lshiftrt:SI
1356 (match_dup 2)
1357 (const_int 16))
1358 (zero_extend:SI
1359 (match_dup 1))))]
1360 "TARGET_MULHW"
1361 "mulchwu. %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1363
1364 (define_insn "*mulchwu"
1365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (lshiftrt:SI
1367 (match_operand:SI 2 "gpc_reg_operand" "r")
1368 (const_int 16))
1369 (zero_extend:SI
1370 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1371 "TARGET_MULHW"
1372 "mulchwu %0, %1, %2"
1373 [(set_attr "type" "imul3")])
1374
1375 (define_insn "*mulhhwc"
1376 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1377 (compare:CC (mult:SI (ashiftrt:SI
1378 (match_operand:SI 1 "gpc_reg_operand" "%r")
1379 (const_int 16))
1380 (ashiftrt:SI
1381 (match_operand:SI 2 "gpc_reg_operand" "r")
1382 (const_int 16)))
1383 (const_int 0)))
1384 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1385 (mult:SI (ashiftrt:SI
1386 (match_dup 1)
1387 (const_int 16))
1388 (ashiftrt:SI
1389 (match_dup 2)
1390 (const_int 16))))]
1391 "TARGET_MULHW"
1392 "mulhhw. %0, %1, %2"
1393 [(set_attr "type" "imul3")])
1394
1395 (define_insn "*mulhhw"
1396 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1397 (mult:SI (ashiftrt:SI
1398 (match_operand:SI 1 "gpc_reg_operand" "%r")
1399 (const_int 16))
1400 (ashiftrt:SI
1401 (match_operand:SI 2 "gpc_reg_operand" "r")
1402 (const_int 16))))]
1403 "TARGET_MULHW"
1404 "mulhhw %0, %1, %2"
1405 [(set_attr "type" "imul3")])
1406
1407 (define_insn "*mulhhwuc"
1408 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1409 (compare:CC (mult:SI (lshiftrt:SI
1410 (match_operand:SI 1 "gpc_reg_operand" "%r")
1411 (const_int 16))
1412 (lshiftrt:SI
1413 (match_operand:SI 2 "gpc_reg_operand" "r")
1414 (const_int 16)))
1415 (const_int 0)))
1416 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1417 (mult:SI (lshiftrt:SI
1418 (match_dup 1)
1419 (const_int 16))
1420 (lshiftrt:SI
1421 (match_dup 2)
1422 (const_int 16))))]
1423 "TARGET_MULHW"
1424 "mulhhwu. %0, %1, %2"
1425 [(set_attr "type" "imul3")])
1426
1427 (define_insn "*mulhhwu"
1428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1429 (mult:SI (lshiftrt:SI
1430 (match_operand:SI 1 "gpc_reg_operand" "%r")
1431 (const_int 16))
1432 (lshiftrt:SI
1433 (match_operand:SI 2 "gpc_reg_operand" "r")
1434 (const_int 16))))]
1435 "TARGET_MULHW"
1436 "mulhhwu %0, %1, %2"
1437 [(set_attr "type" "imul3")])
1438
1439 (define_insn "*mullhwc"
1440 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1441 (compare:CC (mult:SI (sign_extend:SI
1442 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1443 (sign_extend:SI
1444 (match_operand:HI 2 "gpc_reg_operand" "r")))
1445 (const_int 0)))
1446 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1447 (mult:SI (sign_extend:SI
1448 (match_dup 1))
1449 (sign_extend:SI
1450 (match_dup 2))))]
1451 "TARGET_MULHW"
1452 "mullhw. %0, %1, %2"
1453 [(set_attr "type" "imul3")])
1454
1455 (define_insn "*mullhw"
1456 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1457 (mult:SI (sign_extend:SI
1458 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1459 (sign_extend:SI
1460 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1461 "TARGET_MULHW"
1462 "mullhw %0, %1, %2"
1463 [(set_attr "type" "imul3")])
1464
1465 (define_insn "*mullhwuc"
1466 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1467 (compare:CC (mult:SI (zero_extend:SI
1468 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1469 (zero_extend:SI
1470 (match_operand:HI 2 "gpc_reg_operand" "r")))
1471 (const_int 0)))
1472 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1473 (mult:SI (zero_extend:SI
1474 (match_dup 1))
1475 (zero_extend:SI
1476 (match_dup 2))))]
1477 "TARGET_MULHW"
1478 "mullhwu. %0, %1, %2"
1479 [(set_attr "type" "imul3")])
1480
1481 (define_insn "*mullhwu"
1482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1483 (mult:SI (zero_extend:SI
1484 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1485 (zero_extend:SI
1486 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1487 "TARGET_MULHW"
1488 "mullhwu %0, %1, %2"
1489 [(set_attr "type" "imul3")])
1490 \f
1491 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1492 (define_insn "dlmzb"
1493 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1494 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1495 (match_operand:SI 2 "gpc_reg_operand" "r")]
1496 UNSPEC_DLMZB_CR))
1497 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1498 (unspec:SI [(match_dup 1)
1499 (match_dup 2)]
1500 UNSPEC_DLMZB))]
1501 "TARGET_DLMZB"
1502 "dlmzb. %0, %1, %2")
1503
1504 (define_expand "strlensi"
1505 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1506 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1507 (match_operand:QI 2 "const_int_operand" "")
1508 (match_operand 3 "const_int_operand" "")]
1509 UNSPEC_DLMZB_STRLEN))
1510 (clobber (match_scratch:CC 4 "=x"))]
1511 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1512 {
1513 rtx result = operands[0];
1514 rtx src = operands[1];
1515 rtx search_char = operands[2];
1516 rtx align = operands[3];
1517 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1518 rtx loop_label, end_label, mem, cr0, cond;
1519 if (search_char != const0_rtx
1520 || GET_CODE (align) != CONST_INT
1521 || INTVAL (align) < 8)
1522 FAIL;
1523 word1 = gen_reg_rtx (SImode);
1524 word2 = gen_reg_rtx (SImode);
1525 scratch_dlmzb = gen_reg_rtx (SImode);
1526 scratch_string = gen_reg_rtx (Pmode);
1527 loop_label = gen_label_rtx ();
1528 end_label = gen_label_rtx ();
1529 addr = force_reg (Pmode, XEXP (src, 0));
1530 emit_move_insn (scratch_string, addr);
1531 emit_label (loop_label);
1532 mem = change_address (src, SImode, scratch_string);
1533 emit_move_insn (word1, mem);
1534 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1535 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1536 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1537 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1538 emit_jump_insn (gen_rtx_SET (VOIDmode,
1539 pc_rtx,
1540 gen_rtx_IF_THEN_ELSE (VOIDmode,
1541 cond,
1542 gen_rtx_LABEL_REF
1543 (VOIDmode,
1544 end_label),
1545 pc_rtx)));
1546 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1547 emit_jump_insn (gen_rtx_SET (VOIDmode,
1548 pc_rtx,
1549 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1550 emit_barrier ();
1551 emit_label (end_label);
1552 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1553 emit_insn (gen_subsi3 (result, scratch_string, addr));
1554 emit_insn (gen_subsi3 (result, result, const1_rtx));
1555 DONE;
1556 })
1557 \f
1558 (define_split
1559 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1560 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1561 (const_int 0)))
1562 (set (match_operand:SI 0 "gpc_reg_operand" "")
1563 (sign_extend:SI (match_dup 1)))]
1564 "reload_completed"
1565 [(set (match_dup 0)
1566 (sign_extend:SI (match_dup 1)))
1567 (set (match_dup 2)
1568 (compare:CC (match_dup 0)
1569 (const_int 0)))]
1570 "")
1571
1572 ;; Fixed-point arithmetic insns.
1573
1574 (define_expand "add<mode>3"
1575 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1576 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1577 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1578 ""
1579 {
1580 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1581 {
1582 if (non_short_cint_operand (operands[2], DImode))
1583 FAIL;
1584 }
1585 else if (GET_CODE (operands[2]) == CONST_INT
1586 && ! add_operand (operands[2], <MODE>mode))
1587 {
1588 rtx tmp = ((!can_create_pseudo_p ()
1589 || rtx_equal_p (operands[0], operands[1]))
1590 ? operands[0] : gen_reg_rtx (<MODE>mode));
1591
1592 HOST_WIDE_INT val = INTVAL (operands[2]);
1593 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1594 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1595
1596 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1597 FAIL;
1598
1599 /* The ordering here is important for the prolog expander.
1600 When space is allocated from the stack, adding 'low' first may
1601 produce a temporary deallocation (which would be bad). */
1602 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1603 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1604 DONE;
1605 }
1606 })
1607
1608 ;; Discourage ai/addic because of carry but provide it in an alternative
1609 ;; allowing register zero as source.
1610 (define_insn "*add<mode>3_internal1"
1611 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1612 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1613 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1614 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1615 "@
1616 {cax|add} %0,%1,%2
1617 {cal %0,%2(%1)|addi %0,%1,%2}
1618 {ai|addic} %0,%1,%2
1619 {cau|addis} %0,%1,%v2"
1620 [(set_attr "length" "4,4,4,4")])
1621
1622 (define_insn "addsi3_high"
1623 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1624 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1625 (high:SI (match_operand 2 "" ""))))]
1626 "TARGET_MACHO && !TARGET_64BIT"
1627 "{cau|addis} %0,%1,ha16(%2)"
1628 [(set_attr "length" "4")])
1629
1630 (define_insn "*add<mode>3_internal2"
1631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1632 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1633 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1634 (const_int 0)))
1635 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1636 ""
1637 "@
1638 {cax.|add.} %3,%1,%2
1639 {ai.|addic.} %3,%1,%2
1640 #
1641 #"
1642 [(set_attr "type" "fast_compare,compare,compare,compare")
1643 (set_attr "length" "4,4,8,8")])
1644
1645 (define_split
1646 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1647 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1648 (match_operand:GPR 2 "reg_or_short_operand" ""))
1649 (const_int 0)))
1650 (clobber (match_scratch:GPR 3 ""))]
1651 "reload_completed"
1652 [(set (match_dup 3)
1653 (plus:GPR (match_dup 1)
1654 (match_dup 2)))
1655 (set (match_dup 0)
1656 (compare:CC (match_dup 3)
1657 (const_int 0)))]
1658 "")
1659
1660 (define_insn "*add<mode>3_internal3"
1661 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1662 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1663 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1664 (const_int 0)))
1665 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1666 (plus:P (match_dup 1)
1667 (match_dup 2)))]
1668 ""
1669 "@
1670 {cax.|add.} %0,%1,%2
1671 {ai.|addic.} %0,%1,%2
1672 #
1673 #"
1674 [(set_attr "type" "fast_compare,compare,compare,compare")
1675 (set_attr "length" "4,4,8,8")])
1676
1677 (define_split
1678 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1679 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1680 (match_operand:P 2 "reg_or_short_operand" ""))
1681 (const_int 0)))
1682 (set (match_operand:P 0 "gpc_reg_operand" "")
1683 (plus:P (match_dup 1) (match_dup 2)))]
1684 "reload_completed"
1685 [(set (match_dup 0)
1686 (plus:P (match_dup 1)
1687 (match_dup 2)))
1688 (set (match_dup 3)
1689 (compare:CC (match_dup 0)
1690 (const_int 0)))]
1691 "")
1692
1693 ;; Split an add that we can't do in one insn into two insns, each of which
1694 ;; does one 16-bit part. This is used by combine. Note that the low-order
1695 ;; add should be last in case the result gets used in an address.
1696
1697 (define_split
1698 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1699 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1700 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1701 ""
1702 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1703 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1704 {
1705 HOST_WIDE_INT val = INTVAL (operands[2]);
1706 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1707 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1708
1709 operands[4] = GEN_INT (low);
1710 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1711 operands[3] = GEN_INT (rest);
1712 else if (can_create_pseudo_p ())
1713 {
1714 operands[3] = gen_reg_rtx (DImode);
1715 emit_move_insn (operands[3], operands[2]);
1716 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1717 DONE;
1718 }
1719 else
1720 FAIL;
1721 })
1722
1723 (define_insn "one_cmpl<mode>2"
1724 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1725 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1726 ""
1727 "nor %0,%1,%1")
1728
1729 (define_insn ""
1730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1731 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1732 (const_int 0)))
1733 (clobber (match_scratch:P 2 "=r,r"))]
1734 ""
1735 "@
1736 nor. %2,%1,%1
1737 #"
1738 [(set_attr "type" "fast_compare,compare")
1739 (set_attr "length" "4,8")])
1740
1741 (define_split
1742 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1743 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1744 (const_int 0)))
1745 (clobber (match_scratch:P 2 ""))]
1746 "reload_completed"
1747 [(set (match_dup 2)
1748 (not:P (match_dup 1)))
1749 (set (match_dup 0)
1750 (compare:CC (match_dup 2)
1751 (const_int 0)))]
1752 "")
1753
1754 (define_insn ""
1755 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1756 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1757 (const_int 0)))
1758 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1759 (not:P (match_dup 1)))]
1760 ""
1761 "@
1762 nor. %0,%1,%1
1763 #"
1764 [(set_attr "type" "fast_compare,compare")
1765 (set_attr "length" "4,8")])
1766
1767 (define_split
1768 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1769 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1770 (const_int 0)))
1771 (set (match_operand:P 0 "gpc_reg_operand" "")
1772 (not:P (match_dup 1)))]
1773 "reload_completed"
1774 [(set (match_dup 0)
1775 (not:P (match_dup 1)))
1776 (set (match_dup 2)
1777 (compare:CC (match_dup 0)
1778 (const_int 0)))]
1779 "")
1780
1781 (define_insn ""
1782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1783 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1784 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1785 "! TARGET_POWERPC"
1786 "{sf%I1|subf%I1c} %0,%2,%1")
1787
1788 (define_insn ""
1789 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1790 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1791 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1792 "TARGET_POWERPC"
1793 "@
1794 subf %0,%2,%1
1795 subfic %0,%2,%1")
1796
1797 (define_insn ""
1798 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1799 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1800 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1801 (const_int 0)))
1802 (clobber (match_scratch:SI 3 "=r,r"))]
1803 "! TARGET_POWERPC"
1804 "@
1805 {sf.|subfc.} %3,%2,%1
1806 #"
1807 [(set_attr "type" "compare")
1808 (set_attr "length" "4,8")])
1809
1810 (define_insn ""
1811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1812 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1813 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1814 (const_int 0)))
1815 (clobber (match_scratch:P 3 "=r,r"))]
1816 "TARGET_POWERPC"
1817 "@
1818 subf. %3,%2,%1
1819 #"
1820 [(set_attr "type" "fast_compare")
1821 (set_attr "length" "4,8")])
1822
1823 (define_split
1824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1825 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1826 (match_operand:P 2 "gpc_reg_operand" ""))
1827 (const_int 0)))
1828 (clobber (match_scratch:P 3 ""))]
1829 "reload_completed"
1830 [(set (match_dup 3)
1831 (minus:P (match_dup 1)
1832 (match_dup 2)))
1833 (set (match_dup 0)
1834 (compare:CC (match_dup 3)
1835 (const_int 0)))]
1836 "")
1837
1838 (define_insn ""
1839 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1840 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1841 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1842 (const_int 0)))
1843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1844 (minus:SI (match_dup 1) (match_dup 2)))]
1845 "! TARGET_POWERPC"
1846 "@
1847 {sf.|subfc.} %0,%2,%1
1848 #"
1849 [(set_attr "type" "compare")
1850 (set_attr "length" "4,8")])
1851
1852 (define_insn ""
1853 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1854 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1855 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1856 (const_int 0)))
1857 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1858 (minus:P (match_dup 1)
1859 (match_dup 2)))]
1860 "TARGET_POWERPC"
1861 "@
1862 subf. %0,%2,%1
1863 #"
1864 [(set_attr "type" "fast_compare")
1865 (set_attr "length" "4,8")])
1866
1867 (define_split
1868 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1869 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1870 (match_operand:P 2 "gpc_reg_operand" ""))
1871 (const_int 0)))
1872 (set (match_operand:P 0 "gpc_reg_operand" "")
1873 (minus:P (match_dup 1)
1874 (match_dup 2)))]
1875 "reload_completed"
1876 [(set (match_dup 0)
1877 (minus:P (match_dup 1)
1878 (match_dup 2)))
1879 (set (match_dup 3)
1880 (compare:CC (match_dup 0)
1881 (const_int 0)))]
1882 "")
1883
1884 (define_expand "sub<mode>3"
1885 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1886 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1887 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1888 ""
1889 "
1890 {
1891 if (GET_CODE (operands[2]) == CONST_INT)
1892 {
1893 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1894 negate_rtx (<MODE>mode, operands[2])));
1895 DONE;
1896 }
1897 }")
1898
1899 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1900 ;; instruction and some auxiliary computations. Then we just have a single
1901 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1902 ;; combine.
1903
1904 (define_expand "sminsi3"
1905 [(set (match_dup 3)
1906 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1907 (match_operand:SI 2 "reg_or_short_operand" ""))
1908 (const_int 0)
1909 (minus:SI (match_dup 2) (match_dup 1))))
1910 (set (match_operand:SI 0 "gpc_reg_operand" "")
1911 (minus:SI (match_dup 2) (match_dup 3)))]
1912 "TARGET_POWER || TARGET_ISEL"
1913 "
1914 {
1915 if (TARGET_ISEL)
1916 {
1917 operands[2] = force_reg (SImode, operands[2]);
1918 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1919 DONE;
1920 }
1921
1922 operands[3] = gen_reg_rtx (SImode);
1923 }")
1924
1925 (define_split
1926 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1927 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1928 (match_operand:SI 2 "reg_or_short_operand" "")))
1929 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1930 "TARGET_POWER"
1931 [(set (match_dup 3)
1932 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1933 (const_int 0)
1934 (minus:SI (match_dup 2) (match_dup 1))))
1935 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1936 "")
1937
1938 (define_expand "smaxsi3"
1939 [(set (match_dup 3)
1940 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1941 (match_operand:SI 2 "reg_or_short_operand" ""))
1942 (const_int 0)
1943 (minus:SI (match_dup 2) (match_dup 1))))
1944 (set (match_operand:SI 0 "gpc_reg_operand" "")
1945 (plus:SI (match_dup 3) (match_dup 1)))]
1946 "TARGET_POWER || TARGET_ISEL"
1947 "
1948 {
1949 if (TARGET_ISEL)
1950 {
1951 operands[2] = force_reg (SImode, operands[2]);
1952 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1953 DONE;
1954 }
1955 operands[3] = gen_reg_rtx (SImode);
1956 }")
1957
1958 (define_split
1959 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1960 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1961 (match_operand:SI 2 "reg_or_short_operand" "")))
1962 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1963 "TARGET_POWER"
1964 [(set (match_dup 3)
1965 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1966 (const_int 0)
1967 (minus:SI (match_dup 2) (match_dup 1))))
1968 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1969 "")
1970
1971 (define_expand "uminsi3"
1972 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1973 (match_dup 5)))
1974 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1975 (match_dup 5)))
1976 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1977 (const_int 0)
1978 (minus:SI (match_dup 4) (match_dup 3))))
1979 (set (match_operand:SI 0 "gpc_reg_operand" "")
1980 (minus:SI (match_dup 2) (match_dup 3)))]
1981 "TARGET_POWER || TARGET_ISEL"
1982 "
1983 {
1984 if (TARGET_ISEL)
1985 {
1986 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1987 DONE;
1988 }
1989 operands[3] = gen_reg_rtx (SImode);
1990 operands[4] = gen_reg_rtx (SImode);
1991 operands[5] = GEN_INT (-2147483647 - 1);
1992 }")
1993
1994 (define_expand "umaxsi3"
1995 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1996 (match_dup 5)))
1997 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1998 (match_dup 5)))
1999 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2000 (const_int 0)
2001 (minus:SI (match_dup 4) (match_dup 3))))
2002 (set (match_operand:SI 0 "gpc_reg_operand" "")
2003 (plus:SI (match_dup 3) (match_dup 1)))]
2004 "TARGET_POWER || TARGET_ISEL"
2005 "
2006 {
2007 if (TARGET_ISEL)
2008 {
2009 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
2010 DONE;
2011 }
2012 operands[3] = gen_reg_rtx (SImode);
2013 operands[4] = gen_reg_rtx (SImode);
2014 operands[5] = GEN_INT (-2147483647 - 1);
2015 }")
2016
2017 (define_insn ""
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2019 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2020 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2021 (const_int 0)
2022 (minus:SI (match_dup 2) (match_dup 1))))]
2023 "TARGET_POWER"
2024 "doz%I2 %0,%1,%2")
2025
2026 (define_insn ""
2027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2028 (compare:CC
2029 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2030 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2031 (const_int 0)
2032 (minus:SI (match_dup 2) (match_dup 1)))
2033 (const_int 0)))
2034 (clobber (match_scratch:SI 3 "=r,r"))]
2035 "TARGET_POWER"
2036 "@
2037 doz%I2. %3,%1,%2
2038 #"
2039 [(set_attr "type" "delayed_compare")
2040 (set_attr "length" "4,8")])
2041
2042 (define_split
2043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2044 (compare:CC
2045 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2046 (match_operand:SI 2 "reg_or_short_operand" ""))
2047 (const_int 0)
2048 (minus:SI (match_dup 2) (match_dup 1)))
2049 (const_int 0)))
2050 (clobber (match_scratch:SI 3 ""))]
2051 "TARGET_POWER && reload_completed"
2052 [(set (match_dup 3)
2053 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2054 (const_int 0)
2055 (minus:SI (match_dup 2) (match_dup 1))))
2056 (set (match_dup 0)
2057 (compare:CC (match_dup 3)
2058 (const_int 0)))]
2059 "")
2060
2061 (define_insn ""
2062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2063 (compare:CC
2064 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2065 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2066 (const_int 0)
2067 (minus:SI (match_dup 2) (match_dup 1)))
2068 (const_int 0)))
2069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2070 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2071 (const_int 0)
2072 (minus:SI (match_dup 2) (match_dup 1))))]
2073 "TARGET_POWER"
2074 "@
2075 doz%I2. %0,%1,%2
2076 #"
2077 [(set_attr "type" "delayed_compare")
2078 (set_attr "length" "4,8")])
2079
2080 (define_split
2081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2082 (compare:CC
2083 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2084 (match_operand:SI 2 "reg_or_short_operand" ""))
2085 (const_int 0)
2086 (minus:SI (match_dup 2) (match_dup 1)))
2087 (const_int 0)))
2088 (set (match_operand:SI 0 "gpc_reg_operand" "")
2089 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2090 (const_int 0)
2091 (minus:SI (match_dup 2) (match_dup 1))))]
2092 "TARGET_POWER && reload_completed"
2093 [(set (match_dup 0)
2094 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2095 (const_int 0)
2096 (minus:SI (match_dup 2) (match_dup 1))))
2097 (set (match_dup 3)
2098 (compare:CC (match_dup 0)
2099 (const_int 0)))]
2100 "")
2101
2102 ;; We don't need abs with condition code because such comparisons should
2103 ;; never be done.
2104 (define_expand "abssi2"
2105 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2106 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2107 ""
2108 "
2109 {
2110 if (TARGET_ISEL)
2111 {
2112 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2113 DONE;
2114 }
2115 else if (! TARGET_POWER)
2116 {
2117 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2118 DONE;
2119 }
2120 }")
2121
2122 (define_insn "*abssi2_power"
2123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2124 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2125 "TARGET_POWER"
2126 "abs %0,%1")
2127
2128 (define_insn_and_split "abs<mode>2_isel"
2129 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2130 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2131 (clobber (match_scratch:GPR 2 "=&b"))
2132 (clobber (match_scratch:CC 3 "=y"))]
2133 "TARGET_ISEL"
2134 "#"
2135 "&& reload_completed"
2136 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2137 (set (match_dup 3)
2138 (compare:CC (match_dup 1)
2139 (const_int 0)))
2140 (set (match_dup 0)
2141 (if_then_else:GPR (lt (match_dup 3)
2142 (const_int 0))
2143 (match_dup 2)
2144 (match_dup 1)))]
2145 "")
2146
2147 (define_insn_and_split "nabs<mode>2_isel"
2148 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2149 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2150 (clobber (match_scratch:GPR 2 "=&b"))
2151 (clobber (match_scratch:CC 3 "=y"))]
2152 "TARGET_ISEL"
2153 "#"
2154 "&& reload_completed"
2155 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2156 (set (match_dup 3)
2157 (compare:CC (match_dup 1)
2158 (const_int 0)))
2159 (set (match_dup 0)
2160 (if_then_else:GPR (lt (match_dup 3)
2161 (const_int 0))
2162 (match_dup 1)
2163 (match_dup 2)))]
2164 "")
2165
2166 (define_insn_and_split "abssi2_nopower"
2167 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2168 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2169 (clobber (match_scratch:SI 2 "=&r,&r"))]
2170 "! TARGET_POWER && ! TARGET_ISEL"
2171 "#"
2172 "&& reload_completed"
2173 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2174 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2175 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2176 "")
2177
2178 (define_insn "*nabs_power"
2179 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2180 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2181 "TARGET_POWER"
2182 "nabs %0,%1")
2183
2184 (define_insn_and_split "*nabs_nopower"
2185 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2186 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2187 (clobber (match_scratch:SI 2 "=&r,&r"))]
2188 "! TARGET_POWER"
2189 "#"
2190 "&& reload_completed"
2191 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2192 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2193 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2194 "")
2195
2196 (define_expand "neg<mode>2"
2197 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2198 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2199 ""
2200 "")
2201
2202 (define_insn "*neg<mode>2_internal"
2203 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2204 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2205 ""
2206 "neg %0,%1")
2207
2208 (define_insn ""
2209 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2210 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2211 (const_int 0)))
2212 (clobber (match_scratch:P 2 "=r,r"))]
2213 ""
2214 "@
2215 neg. %2,%1
2216 #"
2217 [(set_attr "type" "fast_compare")
2218 (set_attr "length" "4,8")])
2219
2220 (define_split
2221 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2222 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2223 (const_int 0)))
2224 (clobber (match_scratch:P 2 ""))]
2225 "reload_completed"
2226 [(set (match_dup 2)
2227 (neg:P (match_dup 1)))
2228 (set (match_dup 0)
2229 (compare:CC (match_dup 2)
2230 (const_int 0)))]
2231 "")
2232
2233 (define_insn ""
2234 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2235 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2236 (const_int 0)))
2237 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2238 (neg:P (match_dup 1)))]
2239 ""
2240 "@
2241 neg. %0,%1
2242 #"
2243 [(set_attr "type" "fast_compare")
2244 (set_attr "length" "4,8")])
2245
2246 (define_split
2247 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2248 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2249 (const_int 0)))
2250 (set (match_operand:P 0 "gpc_reg_operand" "")
2251 (neg:P (match_dup 1)))]
2252 "reload_completed"
2253 [(set (match_dup 0)
2254 (neg:P (match_dup 1)))
2255 (set (match_dup 2)
2256 (compare:CC (match_dup 0)
2257 (const_int 0)))]
2258 "")
2259
2260 (define_insn "clz<mode>2"
2261 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2262 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2263 ""
2264 "{cntlz|cntlz<wd>} %0,%1"
2265 [(set_attr "type" "cntlz")])
2266
2267 (define_expand "ctz<mode>2"
2268 [(set (match_dup 2)
2269 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2270 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2271 (match_dup 2)))
2272 (clobber (scratch:CC))])
2273 (set (match_dup 4) (clz:GPR (match_dup 3)))
2274 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2275 (minus:GPR (match_dup 5) (match_dup 4)))]
2276 ""
2277 {
2278 operands[2] = gen_reg_rtx (<MODE>mode);
2279 operands[3] = gen_reg_rtx (<MODE>mode);
2280 operands[4] = gen_reg_rtx (<MODE>mode);
2281 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2282 })
2283
2284 (define_expand "ffs<mode>2"
2285 [(set (match_dup 2)
2286 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2287 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2288 (match_dup 2)))
2289 (clobber (scratch:CC))])
2290 (set (match_dup 4) (clz:GPR (match_dup 3)))
2291 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2292 (minus:GPR (match_dup 5) (match_dup 4)))]
2293 ""
2294 {
2295 operands[2] = gen_reg_rtx (<MODE>mode);
2296 operands[3] = gen_reg_rtx (<MODE>mode);
2297 operands[4] = gen_reg_rtx (<MODE>mode);
2298 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2299 })
2300
2301 (define_insn "popcntb<mode>2"
2302 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2303 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2304 UNSPEC_POPCNTB))]
2305 "TARGET_POPCNTB"
2306 "popcntb %0,%1")
2307
2308 (define_insn "popcntd<mode>2"
2309 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2310 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2311 "TARGET_POPCNTD"
2312 "popcnt<wd> %0,%1")
2313
2314 (define_expand "popcount<mode>2"
2315 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2316 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2317 "TARGET_POPCNTB || TARGET_POPCNTD"
2318 {
2319 rs6000_emit_popcount (operands[0], operands[1]);
2320 DONE;
2321 })
2322
2323 (define_insn "parity<mode>2_cmpb"
2324 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2325 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2326 "TARGET_CMPB && TARGET_POPCNTB"
2327 "prty<wd> %0,%1")
2328
2329 (define_expand "parity<mode>2"
2330 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2331 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2332 "TARGET_POPCNTB"
2333 {
2334 rs6000_emit_parity (operands[0], operands[1]);
2335 DONE;
2336 })
2337
2338 ;; Since the hardware zeros the upper part of the register, save generating the
2339 ;; AND immediate if we are converting to unsigned
2340 (define_insn "*bswaphi2_extenddi"
2341 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2342 (zero_extend:DI
2343 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2344 "TARGET_POWERPC64"
2345 "lhbrx %0,%y1"
2346 [(set_attr "length" "4")
2347 (set_attr "type" "load")])
2348
2349 (define_insn "*bswaphi2_extendsi"
2350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2351 (zero_extend:SI
2352 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2353 "TARGET_POWERPC"
2354 "lhbrx %0,%y1"
2355 [(set_attr "length" "4")
2356 (set_attr "type" "load")])
2357
2358 (define_expand "bswaphi2"
2359 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2360 (bswap:HI
2361 (match_operand:HI 1 "reg_or_mem_operand" "")))
2362 (clobber (match_scratch:SI 2 ""))])]
2363 ""
2364 {
2365 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2366 operands[1] = force_reg (HImode, operands[1]);
2367 })
2368
2369 (define_insn "bswaphi2_internal"
2370 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2371 (bswap:HI
2372 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2373 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2374 "TARGET_POWERPC"
2375 "@
2376 lhbrx %0,%y1
2377 sthbrx %1,%y0
2378 #"
2379 [(set_attr "length" "4,4,12")
2380 (set_attr "type" "load,store,*")])
2381
2382 (define_split
2383 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2384 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2385 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2386 "TARGET_POWERPC && reload_completed"
2387 [(set (match_dup 3)
2388 (zero_extract:SI (match_dup 4)
2389 (const_int 8)
2390 (const_int 16)))
2391 (set (match_dup 2)
2392 (and:SI (ashift:SI (match_dup 4)
2393 (const_int 8))
2394 (const_int 65280))) ;; 0xff00
2395 (set (match_dup 3)
2396 (ior:SI (match_dup 3)
2397 (match_dup 2)))]
2398 "
2399 {
2400 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2401 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2402 }")
2403
2404 (define_insn "*bswapsi2_extenddi"
2405 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2406 (zero_extend:DI
2407 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2408 "TARGET_POWERPC64"
2409 "lwbrx %0,%y1"
2410 [(set_attr "length" "4")
2411 (set_attr "type" "load")])
2412
2413 (define_expand "bswapsi2"
2414 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2415 (bswap:SI
2416 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2417 ""
2418 {
2419 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2420 operands[1] = force_reg (SImode, operands[1]);
2421 })
2422
2423 (define_insn "*bswapsi2_internal"
2424 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2425 (bswap:SI
2426 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2427 ""
2428 "@
2429 {lbrx|lwbrx} %0,%y1
2430 {stbrx|stwbrx} %1,%y0
2431 #"
2432 [(set_attr "length" "4,4,12")
2433 (set_attr "type" "load,store,*")])
2434
2435 (define_split
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2437 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2438 "reload_completed"
2439 [(set (match_dup 0)
2440 (rotate:SI (match_dup 1) (const_int 8)))
2441 (set (zero_extract:SI (match_dup 0)
2442 (const_int 8)
2443 (const_int 0))
2444 (match_dup 1))
2445 (set (zero_extract:SI (match_dup 0)
2446 (const_int 8)
2447 (const_int 16))
2448 (rotate:SI (match_dup 1)
2449 (const_int 16)))]
2450 "")
2451
2452 (define_expand "bswapdi2"
2453 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2454 (bswap:DI
2455 (match_operand:DI 1 "reg_or_mem_operand" "")))
2456 (clobber (match_scratch:DI 2 ""))
2457 (clobber (match_scratch:DI 3 ""))
2458 (clobber (match_scratch:DI 4 ""))])]
2459 ""
2460 {
2461 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2462 operands[1] = force_reg (DImode, operands[1]);
2463
2464 if (!TARGET_POWERPC64)
2465 {
2466 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2467 that uses 64-bit registers needs the same scratch registers as 64-bit
2468 mode. */
2469 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2470 DONE;
2471 }
2472 })
2473
2474 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2475 (define_insn "*bswapdi2_ldbrx"
2476 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2477 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2478 (clobber (match_scratch:DI 2 "=X,X,&r"))
2479 (clobber (match_scratch:DI 3 "=X,X,&r"))
2480 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2481 "TARGET_POWERPC64 && TARGET_LDBRX
2482 && (REG_P (operands[0]) || REG_P (operands[1]))"
2483 "@
2484 ldbrx %0,%y1
2485 stdbrx %1,%y0
2486 #"
2487 [(set_attr "length" "4,4,36")
2488 (set_attr "type" "load,store,*")])
2489
2490 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2491 (define_insn "*bswapdi2_64bit"
2492 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2493 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2494 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2495 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2496 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2497 "TARGET_POWERPC64 && !TARGET_LDBRX
2498 && (REG_P (operands[0]) || REG_P (operands[1]))"
2499 "#"
2500 [(set_attr "length" "16,12,36")])
2501
2502 (define_split
2503 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2504 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2505 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2506 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2507 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2508 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2509 [(const_int 0)]
2510 "
2511 {
2512 rtx dest = operands[0];
2513 rtx src = operands[1];
2514 rtx op2 = operands[2];
2515 rtx op3 = operands[3];
2516 rtx op4 = operands[4];
2517 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2518 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2519 rtx addr1;
2520 rtx addr2;
2521 rtx word_high;
2522 rtx word_low;
2523
2524 addr1 = XEXP (src, 0);
2525 if (GET_CODE (addr1) == PLUS)
2526 {
2527 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2528 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2529 }
2530 else
2531 {
2532 emit_move_insn (op2, GEN_INT (4));
2533 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2534 }
2535
2536 if (BYTES_BIG_ENDIAN)
2537 {
2538 word_high = change_address (src, SImode, addr1);
2539 word_low = change_address (src, SImode, addr2);
2540 }
2541 else
2542 {
2543 word_high = change_address (src, SImode, addr2);
2544 word_low = change_address (src, SImode, addr1);
2545 }
2546
2547 emit_insn (gen_bswapsi2 (op3_32, word_low));
2548 emit_insn (gen_bswapsi2 (op4_32, word_high));
2549 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2550 emit_insn (gen_iordi3 (dest, dest, op4));
2551 }")
2552
2553 (define_split
2554 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2555 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2556 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2557 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2558 (clobber (match_operand:DI 4 "" ""))]
2559 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2560 [(const_int 0)]
2561 "
2562 {
2563 rtx dest = operands[0];
2564 rtx src = operands[1];
2565 rtx op2 = operands[2];
2566 rtx op3 = operands[3];
2567 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2568 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2569 rtx addr1;
2570 rtx addr2;
2571 rtx word_high;
2572 rtx word_low;
2573
2574 addr1 = XEXP (dest, 0);
2575 if (GET_CODE (addr1) == PLUS)
2576 {
2577 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2578 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2579 }
2580 else
2581 {
2582 emit_move_insn (op2, GEN_INT (4));
2583 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2584 }
2585
2586 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2587 if (BYTES_BIG_ENDIAN)
2588 {
2589 word_high = change_address (dest, SImode, addr1);
2590 word_low = change_address (dest, SImode, addr2);
2591 emit_insn (gen_bswapsi2 (word_high, src_si));
2592 emit_insn (gen_bswapsi2 (word_low, op3_si));
2593 }
2594 else
2595 {
2596 word_high = change_address (dest, SImode, addr2);
2597 word_low = change_address (dest, SImode, addr1);
2598 emit_insn (gen_bswapsi2 (word_low, src_si));
2599 emit_insn (gen_bswapsi2 (word_high, op3_si));
2600 }
2601 }")
2602
2603 (define_split
2604 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2605 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2606 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2607 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2608 (clobber (match_operand:DI 4 "" ""))]
2609 "TARGET_POWERPC64 && reload_completed"
2610 [(const_int 0)]
2611 "
2612 {
2613 rtx dest = operands[0];
2614 rtx src = operands[1];
2615 rtx op2 = operands[2];
2616 rtx op3 = operands[3];
2617 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2618 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2619 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2620 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2621
2622 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2623 emit_insn (gen_bswapsi2 (dest_si, src_si));
2624 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2625 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2626 emit_insn (gen_iordi3 (dest, dest, op3));
2627 }")
2628
2629 (define_insn "bswapdi2_32bit"
2630 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2631 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2632 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2633 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2634 "#"
2635 [(set_attr "length" "16,12,36")])
2636
2637 (define_split
2638 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2639 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2640 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2641 "!TARGET_POWERPC64 && reload_completed"
2642 [(const_int 0)]
2643 "
2644 {
2645 rtx dest = operands[0];
2646 rtx src = operands[1];
2647 rtx op2 = operands[2];
2648 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2649 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2650 rtx addr1;
2651 rtx addr2;
2652 rtx word_high;
2653 rtx word_low;
2654
2655 addr1 = XEXP (src, 0);
2656 if (GET_CODE (addr1) == PLUS)
2657 {
2658 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2659 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2660 }
2661 else
2662 {
2663 emit_move_insn (op2, GEN_INT (4));
2664 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2665 }
2666
2667 if (BYTES_BIG_ENDIAN)
2668 {
2669 word_high = change_address (src, SImode, addr1);
2670 word_low = change_address (src, SImode, addr2);
2671 }
2672 else
2673 {
2674 word_high = change_address (src, SImode, addr2);
2675 word_low = change_address (src, SImode, addr1);
2676 }
2677
2678 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2679 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2680 }")
2681
2682 (define_split
2683 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2684 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2685 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2686 "!TARGET_POWERPC64 && reload_completed"
2687 [(const_int 0)]
2688 "
2689 {
2690 rtx dest = operands[0];
2691 rtx src = operands[1];
2692 rtx op2 = operands[2];
2693 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2694 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2695 rtx addr1;
2696 rtx addr2;
2697 rtx word_high;
2698 rtx word_low;
2699
2700 addr1 = XEXP (dest, 0);
2701 if (GET_CODE (addr1) == PLUS)
2702 {
2703 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2704 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2705 }
2706 else
2707 {
2708 emit_move_insn (op2, GEN_INT (4));
2709 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2710 }
2711
2712 if (BYTES_BIG_ENDIAN)
2713 {
2714 word_high = change_address (dest, SImode, addr1);
2715 word_low = change_address (dest, SImode, addr2);
2716 }
2717 else
2718 {
2719 word_high = change_address (dest, SImode, addr2);
2720 word_low = change_address (dest, SImode, addr1);
2721 }
2722
2723 emit_insn (gen_bswapsi2 (word_high, src_low));
2724 emit_insn (gen_bswapsi2 (word_low, src_high));
2725 }")
2726
2727 (define_split
2728 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2729 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2730 (clobber (match_operand:SI 2 "" ""))]
2731 "!TARGET_POWERPC64 && reload_completed"
2732 [(const_int 0)]
2733 "
2734 {
2735 rtx dest = operands[0];
2736 rtx src = operands[1];
2737 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2738 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2739 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2740 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2741
2742 emit_insn (gen_bswapsi2 (dest_high, src_low));
2743 emit_insn (gen_bswapsi2 (dest_low, src_high));
2744 }")
2745
2746 (define_expand "mulsi3"
2747 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2748 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2749 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2750 ""
2751 "
2752 {
2753 if (TARGET_POWER)
2754 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2755 else
2756 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2757 DONE;
2758 }")
2759
2760 (define_insn "mulsi3_mq"
2761 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2762 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2763 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2764 (clobber (match_scratch:SI 3 "=q,q"))]
2765 "TARGET_POWER"
2766 "@
2767 {muls|mullw} %0,%1,%2
2768 {muli|mulli} %0,%1,%2"
2769 [(set (attr "type")
2770 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2771 (const_string "imul3")
2772 (match_operand:SI 2 "short_cint_operand" "")
2773 (const_string "imul2")]
2774 (const_string "imul")))])
2775
2776 (define_insn "mulsi3_no_mq"
2777 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2778 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2779 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2780 "! TARGET_POWER"
2781 "@
2782 {muls|mullw} %0,%1,%2
2783 {muli|mulli} %0,%1,%2"
2784 [(set (attr "type")
2785 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2786 (const_string "imul3")
2787 (match_operand:SI 2 "short_cint_operand" "")
2788 (const_string "imul2")]
2789 (const_string "imul")))])
2790
2791 (define_insn "*mulsi3_mq_internal1"
2792 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2793 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2794 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2795 (const_int 0)))
2796 (clobber (match_scratch:SI 3 "=r,r"))
2797 (clobber (match_scratch:SI 4 "=q,q"))]
2798 "TARGET_POWER"
2799 "@
2800 {muls.|mullw.} %3,%1,%2
2801 #"
2802 [(set_attr "type" "imul_compare")
2803 (set_attr "length" "4,8")])
2804
2805 (define_split
2806 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2807 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2808 (match_operand:SI 2 "gpc_reg_operand" ""))
2809 (const_int 0)))
2810 (clobber (match_scratch:SI 3 ""))
2811 (clobber (match_scratch:SI 4 ""))]
2812 "TARGET_POWER && reload_completed"
2813 [(parallel [(set (match_dup 3)
2814 (mult:SI (match_dup 1) (match_dup 2)))
2815 (clobber (match_dup 4))])
2816 (set (match_dup 0)
2817 (compare:CC (match_dup 3)
2818 (const_int 0)))]
2819 "")
2820
2821 (define_insn "*mulsi3_no_mq_internal1"
2822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2823 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2824 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2825 (const_int 0)))
2826 (clobber (match_scratch:SI 3 "=r,r"))]
2827 "! TARGET_POWER"
2828 "@
2829 {muls.|mullw.} %3,%1,%2
2830 #"
2831 [(set_attr "type" "imul_compare")
2832 (set_attr "length" "4,8")])
2833
2834 (define_split
2835 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2836 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2837 (match_operand:SI 2 "gpc_reg_operand" ""))
2838 (const_int 0)))
2839 (clobber (match_scratch:SI 3 ""))]
2840 "! TARGET_POWER && reload_completed"
2841 [(set (match_dup 3)
2842 (mult:SI (match_dup 1) (match_dup 2)))
2843 (set (match_dup 0)
2844 (compare:CC (match_dup 3)
2845 (const_int 0)))]
2846 "")
2847
2848 (define_insn "*mulsi3_mq_internal2"
2849 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2850 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2851 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2852 (const_int 0)))
2853 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2854 (mult:SI (match_dup 1) (match_dup 2)))
2855 (clobber (match_scratch:SI 4 "=q,q"))]
2856 "TARGET_POWER"
2857 "@
2858 {muls.|mullw.} %0,%1,%2
2859 #"
2860 [(set_attr "type" "imul_compare")
2861 (set_attr "length" "4,8")])
2862
2863 (define_split
2864 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2865 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2866 (match_operand:SI 2 "gpc_reg_operand" ""))
2867 (const_int 0)))
2868 (set (match_operand:SI 0 "gpc_reg_operand" "")
2869 (mult:SI (match_dup 1) (match_dup 2)))
2870 (clobber (match_scratch:SI 4 ""))]
2871 "TARGET_POWER && reload_completed"
2872 [(parallel [(set (match_dup 0)
2873 (mult:SI (match_dup 1) (match_dup 2)))
2874 (clobber (match_dup 4))])
2875 (set (match_dup 3)
2876 (compare:CC (match_dup 0)
2877 (const_int 0)))]
2878 "")
2879
2880 (define_insn "*mulsi3_no_mq_internal2"
2881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2882 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2883 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2884 (const_int 0)))
2885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2886 (mult:SI (match_dup 1) (match_dup 2)))]
2887 "! TARGET_POWER"
2888 "@
2889 {muls.|mullw.} %0,%1,%2
2890 #"
2891 [(set_attr "type" "imul_compare")
2892 (set_attr "length" "4,8")])
2893
2894 (define_split
2895 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2896 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2897 (match_operand:SI 2 "gpc_reg_operand" ""))
2898 (const_int 0)))
2899 (set (match_operand:SI 0 "gpc_reg_operand" "")
2900 (mult:SI (match_dup 1) (match_dup 2)))]
2901 "! TARGET_POWER && reload_completed"
2902 [(set (match_dup 0)
2903 (mult:SI (match_dup 1) (match_dup 2)))
2904 (set (match_dup 3)
2905 (compare:CC (match_dup 0)
2906 (const_int 0)))]
2907 "")
2908
2909 ;; Operand 1 is divided by operand 2; quotient goes to operand
2910 ;; 0 and remainder to operand 3.
2911 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2912
2913 (define_expand "divmodsi4"
2914 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2915 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2916 (match_operand:SI 2 "gpc_reg_operand" "")))
2917 (set (match_operand:SI 3 "register_operand" "")
2918 (mod:SI (match_dup 1) (match_dup 2)))])]
2919 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2920 "
2921 {
2922 if (! TARGET_POWER && ! TARGET_POWERPC)
2923 {
2924 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2925 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2926 emit_insn (gen_divss_call ());
2927 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2928 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2929 DONE;
2930 }
2931 }")
2932
2933 (define_insn "*divmodsi4_internal"
2934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2935 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2936 (match_operand:SI 2 "gpc_reg_operand" "r")))
2937 (set (match_operand:SI 3 "register_operand" "=q")
2938 (mod:SI (match_dup 1) (match_dup 2)))]
2939 "TARGET_POWER"
2940 "divs %0,%1,%2"
2941 [(set_attr "type" "idiv")])
2942
2943 (define_expand "udiv<mode>3"
2944 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2945 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2946 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2947 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2948 "
2949 {
2950 if (! TARGET_POWER && ! TARGET_POWERPC)
2951 {
2952 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2953 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2954 emit_insn (gen_quous_call ());
2955 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2956 DONE;
2957 }
2958 else if (TARGET_POWER)
2959 {
2960 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2961 DONE;
2962 }
2963 }")
2964
2965 (define_insn "udivsi3_mq"
2966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2967 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2968 (match_operand:SI 2 "gpc_reg_operand" "r")))
2969 (clobber (match_scratch:SI 3 "=q"))]
2970 "TARGET_POWERPC && TARGET_POWER"
2971 "divwu %0,%1,%2"
2972 [(set_attr "type" "idiv")])
2973
2974 (define_insn "*udivsi3_no_mq"
2975 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2976 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2977 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2978 "TARGET_POWERPC && ! TARGET_POWER"
2979 "div<wd>u %0,%1,%2"
2980 [(set (attr "type")
2981 (cond [(match_operand:SI 0 "" "")
2982 (const_string "idiv")]
2983 (const_string "ldiv")))])
2984
2985
2986 ;; For powers of two we can do srai/aze for divide and then adjust for
2987 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2988 ;; used; for PowerPC, force operands into register and do a normal divide;
2989 ;; for AIX common-mode, use quoss call on register operands.
2990 (define_expand "div<mode>3"
2991 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2992 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2993 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2994 ""
2995 "
2996 {
2997 if (GET_CODE (operands[2]) == CONST_INT
2998 && INTVAL (operands[2]) > 0
2999 && exact_log2 (INTVAL (operands[2])) >= 0)
3000 ;
3001 else if (TARGET_POWERPC)
3002 {
3003 operands[2] = force_reg (<MODE>mode, operands[2]);
3004 if (TARGET_POWER)
3005 {
3006 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
3007 DONE;
3008 }
3009 }
3010 else if (TARGET_POWER)
3011 FAIL;
3012 else
3013 {
3014 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3015 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3016 emit_insn (gen_quoss_call ());
3017 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3018 DONE;
3019 }
3020 }")
3021
3022 (define_insn "divsi3_mq"
3023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3024 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3025 (match_operand:SI 2 "gpc_reg_operand" "r")))
3026 (clobber (match_scratch:SI 3 "=q"))]
3027 "TARGET_POWERPC && TARGET_POWER"
3028 "divw %0,%1,%2"
3029 [(set_attr "type" "idiv")])
3030
3031 (define_insn "*div<mode>3_no_mq"
3032 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3033 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3034 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3035 "TARGET_POWERPC && ! TARGET_POWER"
3036 "div<wd> %0,%1,%2"
3037 [(set (attr "type")
3038 (cond [(match_operand:SI 0 "" "")
3039 (const_string "idiv")]
3040 (const_string "ldiv")))])
3041
3042 (define_expand "mod<mode>3"
3043 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3044 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3045 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3046 ""
3047 "
3048 {
3049 int i;
3050 rtx temp1;
3051 rtx temp2;
3052
3053 if (GET_CODE (operands[2]) != CONST_INT
3054 || INTVAL (operands[2]) <= 0
3055 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3056 FAIL;
3057
3058 temp1 = gen_reg_rtx (<MODE>mode);
3059 temp2 = gen_reg_rtx (<MODE>mode);
3060
3061 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3062 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3063 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3064 DONE;
3065 }")
3066
3067 (define_insn ""
3068 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3069 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3070 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3071 ""
3072 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3073 [(set_attr "type" "two")
3074 (set_attr "length" "8")])
3075
3076 (define_insn ""
3077 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3078 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3079 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3080 (const_int 0)))
3081 (clobber (match_scratch:P 3 "=r,r"))]
3082 ""
3083 "@
3084 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3085 #"
3086 [(set_attr "type" "compare")
3087 (set_attr "length" "8,12")
3088 (set_attr "cell_micro" "not")])
3089
3090 (define_split
3091 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3092 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3093 (match_operand:GPR 2 "exact_log2_cint_operand"
3094 ""))
3095 (const_int 0)))
3096 (clobber (match_scratch:GPR 3 ""))]
3097 "reload_completed"
3098 [(set (match_dup 3)
3099 (div:<MODE> (match_dup 1) (match_dup 2)))
3100 (set (match_dup 0)
3101 (compare:CC (match_dup 3)
3102 (const_int 0)))]
3103 "")
3104
3105 (define_insn ""
3106 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3107 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3108 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3109 (const_int 0)))
3110 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3111 (div:P (match_dup 1) (match_dup 2)))]
3112 ""
3113 "@
3114 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3115 #"
3116 [(set_attr "type" "compare")
3117 (set_attr "length" "8,12")
3118 (set_attr "cell_micro" "not")])
3119
3120 (define_split
3121 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3122 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3123 (match_operand:GPR 2 "exact_log2_cint_operand"
3124 ""))
3125 (const_int 0)))
3126 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3127 (div:GPR (match_dup 1) (match_dup 2)))]
3128 "reload_completed"
3129 [(set (match_dup 0)
3130 (div:<MODE> (match_dup 1) (match_dup 2)))
3131 (set (match_dup 3)
3132 (compare:CC (match_dup 0)
3133 (const_int 0)))]
3134 "")
3135
3136 (define_insn ""
3137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3138 (udiv:SI
3139 (plus:DI (ashift:DI
3140 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3141 (const_int 32))
3142 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3143 (match_operand:SI 3 "gpc_reg_operand" "r")))
3144 (set (match_operand:SI 2 "register_operand" "=*q")
3145 (umod:SI
3146 (plus:DI (ashift:DI
3147 (zero_extend:DI (match_dup 1)) (const_int 32))
3148 (zero_extend:DI (match_dup 4)))
3149 (match_dup 3)))]
3150 "TARGET_POWER"
3151 "div %0,%1,%3"
3152 [(set_attr "type" "idiv")])
3153
3154 ;; To do unsigned divide we handle the cases of the divisor looking like a
3155 ;; negative number. If it is a constant that is less than 2**31, we don't
3156 ;; have to worry about the branches. So make a few subroutines here.
3157 ;;
3158 ;; First comes the normal case.
3159 (define_expand "udivmodsi4_normal"
3160 [(set (match_dup 4) (const_int 0))
3161 (parallel [(set (match_operand:SI 0 "" "")
3162 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3163 (const_int 32))
3164 (zero_extend:DI (match_operand:SI 1 "" "")))
3165 (match_operand:SI 2 "" "")))
3166 (set (match_operand:SI 3 "" "")
3167 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3168 (const_int 32))
3169 (zero_extend:DI (match_dup 1)))
3170 (match_dup 2)))])]
3171 "TARGET_POWER"
3172 "
3173 { operands[4] = gen_reg_rtx (SImode); }")
3174
3175 ;; This handles the branches.
3176 (define_expand "udivmodsi4_tests"
3177 [(set (match_operand:SI 0 "" "") (const_int 0))
3178 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3179 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3180 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3181 (label_ref (match_operand:SI 4 "" "")) (pc)))
3182 (set (match_dup 0) (const_int 1))
3183 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3184 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3185 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3186 (label_ref (match_dup 4)) (pc)))]
3187 "TARGET_POWER"
3188 "
3189 { operands[5] = gen_reg_rtx (CCUNSmode);
3190 operands[6] = gen_reg_rtx (CCmode);
3191 }")
3192
3193 (define_expand "udivmodsi4"
3194 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3195 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3196 (match_operand:SI 2 "reg_or_cint_operand" "")))
3197 (set (match_operand:SI 3 "gpc_reg_operand" "")
3198 (umod:SI (match_dup 1) (match_dup 2)))])]
3199 ""
3200 "
3201 {
3202 rtx label = 0;
3203
3204 if (! TARGET_POWER)
3205 {
3206 if (! TARGET_POWERPC)
3207 {
3208 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3209 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3210 emit_insn (gen_divus_call ());
3211 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3212 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3213 DONE;
3214 }
3215 else
3216 FAIL;
3217 }
3218
3219 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3220 {
3221 operands[2] = force_reg (SImode, operands[2]);
3222 label = gen_label_rtx ();
3223 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3224 operands[3], label));
3225 }
3226 else
3227 operands[2] = force_reg (SImode, operands[2]);
3228
3229 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3230 operands[3]));
3231 if (label)
3232 emit_label (label);
3233
3234 DONE;
3235 }")
3236
3237 ;; AIX architecture-independent common-mode multiply (DImode),
3238 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3239 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3240 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3241 ;; assumed unused if generating common-mode, so ignore.
3242 (define_insn "mulh_call"
3243 [(set (reg:SI 3)
3244 (truncate:SI
3245 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3246 (sign_extend:DI (reg:SI 4)))
3247 (const_int 32))))
3248 (clobber (reg:SI LR_REGNO))]
3249 "! TARGET_POWER && ! TARGET_POWERPC"
3250 "bla __mulh"
3251 [(set_attr "type" "imul")])
3252
3253 (define_insn "mull_call"
3254 [(set (reg:DI 3)
3255 (mult:DI (sign_extend:DI (reg:SI 3))
3256 (sign_extend:DI (reg:SI 4))))
3257 (clobber (reg:SI LR_REGNO))
3258 (clobber (reg:SI 0))]
3259 "! TARGET_POWER && ! TARGET_POWERPC"
3260 "bla __mull"
3261 [(set_attr "type" "imul")])
3262
3263 (define_insn "divss_call"
3264 [(set (reg:SI 3)
3265 (div:SI (reg:SI 3) (reg:SI 4)))
3266 (set (reg:SI 4)
3267 (mod:SI (reg:SI 3) (reg:SI 4)))
3268 (clobber (reg:SI LR_REGNO))
3269 (clobber (reg:SI 0))]
3270 "! TARGET_POWER && ! TARGET_POWERPC"
3271 "bla __divss"
3272 [(set_attr "type" "idiv")])
3273
3274 (define_insn "divus_call"
3275 [(set (reg:SI 3)
3276 (udiv:SI (reg:SI 3) (reg:SI 4)))
3277 (set (reg:SI 4)
3278 (umod:SI (reg:SI 3) (reg:SI 4)))
3279 (clobber (reg:SI LR_REGNO))
3280 (clobber (reg:SI 0))
3281 (clobber (match_scratch:CC 0 "=x"))
3282 (clobber (reg:CC CR1_REGNO))]
3283 "! TARGET_POWER && ! TARGET_POWERPC"
3284 "bla __divus"
3285 [(set_attr "type" "idiv")])
3286
3287 (define_insn "quoss_call"
3288 [(set (reg:SI 3)
3289 (div:SI (reg:SI 3) (reg:SI 4)))
3290 (clobber (reg:SI LR_REGNO))]
3291 "! TARGET_POWER && ! TARGET_POWERPC"
3292 "bla __quoss"
3293 [(set_attr "type" "idiv")])
3294
3295 (define_insn "quous_call"
3296 [(set (reg:SI 3)
3297 (udiv:SI (reg:SI 3) (reg:SI 4)))
3298 (clobber (reg:SI LR_REGNO))
3299 (clobber (reg:SI 0))
3300 (clobber (match_scratch:CC 0 "=x"))
3301 (clobber (reg:CC CR1_REGNO))]
3302 "! TARGET_POWER && ! TARGET_POWERPC"
3303 "bla __quous"
3304 [(set_attr "type" "idiv")])
3305 \f
3306 ;; Logical instructions
3307 ;; The logical instructions are mostly combined by using match_operator,
3308 ;; but the plain AND insns are somewhat different because there is no
3309 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3310 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3311
3312 (define_expand "andsi3"
3313 [(parallel
3314 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3315 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3316 (match_operand:SI 2 "and_operand" "")))
3317 (clobber (match_scratch:CC 3 ""))])]
3318 ""
3319 "")
3320
3321 (define_insn "andsi3_mc"
3322 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3323 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3324 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3325 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3326 "rs6000_gen_cell_microcode"
3327 "@
3328 and %0,%1,%2
3329 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3330 {andil.|andi.} %0,%1,%b2
3331 {andiu.|andis.} %0,%1,%u2"
3332 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3333
3334 (define_insn "andsi3_nomc"
3335 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3336 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3337 (match_operand:SI 2 "and_operand" "?r,T")))
3338 (clobber (match_scratch:CC 3 "=X,X"))]
3339 "!rs6000_gen_cell_microcode"
3340 "@
3341 and %0,%1,%2
3342 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3343
3344 (define_insn "andsi3_internal0_nomc"
3345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3346 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3347 (match_operand:SI 2 "and_operand" "?r,T")))]
3348 "!rs6000_gen_cell_microcode"
3349 "@
3350 and %0,%1,%2
3351 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3352
3353
3354 ;; Note to set cr's other than cr0 we do the and immediate and then
3355 ;; the test again -- this avoids a mfcr which on the higher end
3356 ;; machines causes an execution serialization
3357
3358 (define_insn "*andsi3_internal2_mc"
3359 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3360 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3361 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3362 (const_int 0)))
3363 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3364 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3365 "TARGET_32BIT && rs6000_gen_cell_microcode"
3366 "@
3367 and. %3,%1,%2
3368 {andil.|andi.} %3,%1,%b2
3369 {andiu.|andis.} %3,%1,%u2
3370 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3371 #
3372 #
3373 #
3374 #"
3375 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3376 compare,compare,compare,compare")
3377 (set_attr "length" "4,4,4,4,8,8,8,8")])
3378
3379 (define_insn "*andsi3_internal3_mc"
3380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3381 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3382 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3383 (const_int 0)))
3384 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3385 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3386 "TARGET_64BIT && rs6000_gen_cell_microcode"
3387 "@
3388 #
3389 {andil.|andi.} %3,%1,%b2
3390 {andiu.|andis.} %3,%1,%u2
3391 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3392 #
3393 #
3394 #
3395 #"
3396 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3397 compare,compare,compare")
3398 (set_attr "length" "8,4,4,4,8,8,8,8")])
3399
3400 (define_split
3401 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3402 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3403 (match_operand:GPR 2 "and_operand" ""))
3404 (const_int 0)))
3405 (clobber (match_scratch:GPR 3 ""))
3406 (clobber (match_scratch:CC 4 ""))]
3407 "reload_completed"
3408 [(parallel [(set (match_dup 3)
3409 (and:<MODE> (match_dup 1)
3410 (match_dup 2)))
3411 (clobber (match_dup 4))])
3412 (set (match_dup 0)
3413 (compare:CC (match_dup 3)
3414 (const_int 0)))]
3415 "")
3416
3417 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3418 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3419
3420 (define_split
3421 [(set (match_operand:CC 0 "cc_reg_operand" "")
3422 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3423 (match_operand:SI 2 "gpc_reg_operand" ""))
3424 (const_int 0)))
3425 (clobber (match_scratch:SI 3 ""))
3426 (clobber (match_scratch:CC 4 ""))]
3427 "TARGET_POWERPC64 && reload_completed"
3428 [(parallel [(set (match_dup 3)
3429 (and:SI (match_dup 1)
3430 (match_dup 2)))
3431 (clobber (match_dup 4))])
3432 (set (match_dup 0)
3433 (compare:CC (match_dup 3)
3434 (const_int 0)))]
3435 "")
3436
3437 (define_insn "*andsi3_internal4"
3438 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3439 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3440 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3441 (const_int 0)))
3442 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3443 (and:SI (match_dup 1)
3444 (match_dup 2)))
3445 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3446 "TARGET_32BIT && rs6000_gen_cell_microcode"
3447 "@
3448 and. %0,%1,%2
3449 {andil.|andi.} %0,%1,%b2
3450 {andiu.|andis.} %0,%1,%u2
3451 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3452 #
3453 #
3454 #
3455 #"
3456 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3457 compare,compare,compare,compare")
3458 (set_attr "length" "4,4,4,4,8,8,8,8")])
3459
3460 (define_insn "*andsi3_internal5_mc"
3461 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3462 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3463 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3464 (const_int 0)))
3465 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3466 (and:SI (match_dup 1)
3467 (match_dup 2)))
3468 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3469 "TARGET_64BIT && rs6000_gen_cell_microcode"
3470 "@
3471 #
3472 {andil.|andi.} %0,%1,%b2
3473 {andiu.|andis.} %0,%1,%u2
3474 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3475 #
3476 #
3477 #
3478 #"
3479 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3480 compare,compare,compare")
3481 (set_attr "length" "8,4,4,4,8,8,8,8")])
3482
3483 (define_split
3484 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3485 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3486 (match_operand:SI 2 "and_operand" ""))
3487 (const_int 0)))
3488 (set (match_operand:SI 0 "gpc_reg_operand" "")
3489 (and:SI (match_dup 1)
3490 (match_dup 2)))
3491 (clobber (match_scratch:CC 4 ""))]
3492 "reload_completed"
3493 [(parallel [(set (match_dup 0)
3494 (and:SI (match_dup 1)
3495 (match_dup 2)))
3496 (clobber (match_dup 4))])
3497 (set (match_dup 3)
3498 (compare:CC (match_dup 0)
3499 (const_int 0)))]
3500 "")
3501
3502 (define_split
3503 [(set (match_operand:CC 3 "cc_reg_operand" "")
3504 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3505 (match_operand:SI 2 "gpc_reg_operand" ""))
3506 (const_int 0)))
3507 (set (match_operand:SI 0 "gpc_reg_operand" "")
3508 (and:SI (match_dup 1)
3509 (match_dup 2)))
3510 (clobber (match_scratch:CC 4 ""))]
3511 "TARGET_POWERPC64 && reload_completed"
3512 [(parallel [(set (match_dup 0)
3513 (and:SI (match_dup 1)
3514 (match_dup 2)))
3515 (clobber (match_dup 4))])
3516 (set (match_dup 3)
3517 (compare:CC (match_dup 0)
3518 (const_int 0)))]
3519 "")
3520
3521 ;; Handle the PowerPC64 rlwinm corner case
3522
3523 (define_insn_and_split "*andsi3_internal6"
3524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3525 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3526 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3527 "TARGET_POWERPC64"
3528 "#"
3529 "TARGET_POWERPC64"
3530 [(set (match_dup 0)
3531 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3532 (match_dup 4)))
3533 (set (match_dup 0)
3534 (rotate:SI (match_dup 0) (match_dup 5)))]
3535 "
3536 {
3537 int mb = extract_MB (operands[2]);
3538 int me = extract_ME (operands[2]);
3539 operands[3] = GEN_INT (me + 1);
3540 operands[5] = GEN_INT (32 - (me + 1));
3541 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3542 }"
3543 [(set_attr "length" "8")])
3544
3545 (define_expand "iorsi3"
3546 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3547 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3548 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3549 ""
3550 "
3551 {
3552 if (GET_CODE (operands[2]) == CONST_INT
3553 && ! logical_operand (operands[2], SImode))
3554 {
3555 HOST_WIDE_INT value = INTVAL (operands[2]);
3556 rtx tmp = ((!can_create_pseudo_p ()
3557 || rtx_equal_p (operands[0], operands[1]))
3558 ? operands[0] : gen_reg_rtx (SImode));
3559
3560 emit_insn (gen_iorsi3 (tmp, operands[1],
3561 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3562 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3563 DONE;
3564 }
3565 }")
3566
3567 (define_expand "xorsi3"
3568 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3569 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3570 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3571 ""
3572 "
3573 {
3574 if (GET_CODE (operands[2]) == CONST_INT
3575 && ! logical_operand (operands[2], SImode))
3576 {
3577 HOST_WIDE_INT value = INTVAL (operands[2]);
3578 rtx tmp = ((!can_create_pseudo_p ()
3579 || rtx_equal_p (operands[0], operands[1]))
3580 ? operands[0] : gen_reg_rtx (SImode));
3581
3582 emit_insn (gen_xorsi3 (tmp, operands[1],
3583 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3584 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3585 DONE;
3586 }
3587 }")
3588
3589 (define_insn "*boolsi3_internal1"
3590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3591 (match_operator:SI 3 "boolean_or_operator"
3592 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3593 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3594 ""
3595 "@
3596 %q3 %0,%1,%2
3597 {%q3il|%q3i} %0,%1,%b2
3598 {%q3iu|%q3is} %0,%1,%u2")
3599
3600 (define_insn "*boolsi3_internal2"
3601 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3602 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3603 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3604 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3605 (const_int 0)))
3606 (clobber (match_scratch:SI 3 "=r,r"))]
3607 "TARGET_32BIT"
3608 "@
3609 %q4. %3,%1,%2
3610 #"
3611 [(set_attr "type" "fast_compare,compare")
3612 (set_attr "length" "4,8")])
3613
3614 (define_split
3615 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3616 (compare:CC (match_operator:SI 4 "boolean_operator"
3617 [(match_operand:SI 1 "gpc_reg_operand" "")
3618 (match_operand:SI 2 "gpc_reg_operand" "")])
3619 (const_int 0)))
3620 (clobber (match_scratch:SI 3 ""))]
3621 "TARGET_32BIT && reload_completed"
3622 [(set (match_dup 3) (match_dup 4))
3623 (set (match_dup 0)
3624 (compare:CC (match_dup 3)
3625 (const_int 0)))]
3626 "")
3627
3628 (define_insn "*boolsi3_internal3"
3629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3630 (compare:CC (match_operator:SI 4 "boolean_operator"
3631 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3632 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3633 (const_int 0)))
3634 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3635 (match_dup 4))]
3636 "TARGET_32BIT"
3637 "@
3638 %q4. %0,%1,%2
3639 #"
3640 [(set_attr "type" "fast_compare,compare")
3641 (set_attr "length" "4,8")])
3642
3643 (define_split
3644 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3645 (compare:CC (match_operator:SI 4 "boolean_operator"
3646 [(match_operand:SI 1 "gpc_reg_operand" "")
3647 (match_operand:SI 2 "gpc_reg_operand" "")])
3648 (const_int 0)))
3649 (set (match_operand:SI 0 "gpc_reg_operand" "")
3650 (match_dup 4))]
3651 "TARGET_32BIT && reload_completed"
3652 [(set (match_dup 0) (match_dup 4))
3653 (set (match_dup 3)
3654 (compare:CC (match_dup 0)
3655 (const_int 0)))]
3656 "")
3657
3658 ;; Split a logical operation that we can't do in one insn into two insns,
3659 ;; each of which does one 16-bit part. This is used by combine.
3660
3661 (define_split
3662 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3663 (match_operator:SI 3 "boolean_or_operator"
3664 [(match_operand:SI 1 "gpc_reg_operand" "")
3665 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3666 ""
3667 [(set (match_dup 0) (match_dup 4))
3668 (set (match_dup 0) (match_dup 5))]
3669 "
3670 {
3671 rtx i;
3672 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3673 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3674 operands[1], i);
3675 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3676 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3677 operands[0], i);
3678 }")
3679
3680 (define_insn "*boolcsi3_internal1"
3681 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3682 (match_operator:SI 3 "boolean_operator"
3683 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3684 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3685 ""
3686 "%q3 %0,%2,%1")
3687
3688 (define_insn "*boolcsi3_internal2"
3689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3690 (compare:CC (match_operator:SI 4 "boolean_operator"
3691 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3692 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3693 (const_int 0)))
3694 (clobber (match_scratch:SI 3 "=r,r"))]
3695 "TARGET_32BIT"
3696 "@
3697 %q4. %3,%2,%1
3698 #"
3699 [(set_attr "type" "compare")
3700 (set_attr "length" "4,8")])
3701
3702 (define_split
3703 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3704 (compare:CC (match_operator:SI 4 "boolean_operator"
3705 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3706 (match_operand:SI 2 "gpc_reg_operand" "")])
3707 (const_int 0)))
3708 (clobber (match_scratch:SI 3 ""))]
3709 "TARGET_32BIT && reload_completed"
3710 [(set (match_dup 3) (match_dup 4))
3711 (set (match_dup 0)
3712 (compare:CC (match_dup 3)
3713 (const_int 0)))]
3714 "")
3715
3716 (define_insn "*boolcsi3_internal3"
3717 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3718 (compare:CC (match_operator:SI 4 "boolean_operator"
3719 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3720 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3721 (const_int 0)))
3722 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3723 (match_dup 4))]
3724 "TARGET_32BIT"
3725 "@
3726 %q4. %0,%2,%1
3727 #"
3728 [(set_attr "type" "compare")
3729 (set_attr "length" "4,8")])
3730
3731 (define_split
3732 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3733 (compare:CC (match_operator:SI 4 "boolean_operator"
3734 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3735 (match_operand:SI 2 "gpc_reg_operand" "")])
3736 (const_int 0)))
3737 (set (match_operand:SI 0 "gpc_reg_operand" "")
3738 (match_dup 4))]
3739 "TARGET_32BIT && reload_completed"
3740 [(set (match_dup 0) (match_dup 4))
3741 (set (match_dup 3)
3742 (compare:CC (match_dup 0)
3743 (const_int 0)))]
3744 "")
3745
3746 (define_insn "*boolccsi3_internal1"
3747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3748 (match_operator:SI 3 "boolean_operator"
3749 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3750 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3751 ""
3752 "%q3 %0,%1,%2")
3753
3754 (define_insn "*boolccsi3_internal2"
3755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3756 (compare:CC (match_operator:SI 4 "boolean_operator"
3757 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3758 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3759 (const_int 0)))
3760 (clobber (match_scratch:SI 3 "=r,r"))]
3761 "TARGET_32BIT"
3762 "@
3763 %q4. %3,%1,%2
3764 #"
3765 [(set_attr "type" "fast_compare,compare")
3766 (set_attr "length" "4,8")])
3767
3768 (define_split
3769 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3770 (compare:CC (match_operator:SI 4 "boolean_operator"
3771 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3772 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3773 (const_int 0)))
3774 (clobber (match_scratch:SI 3 ""))]
3775 "TARGET_32BIT && reload_completed"
3776 [(set (match_dup 3) (match_dup 4))
3777 (set (match_dup 0)
3778 (compare:CC (match_dup 3)
3779 (const_int 0)))]
3780 "")
3781
3782 (define_insn "*boolccsi3_internal3"
3783 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3784 (compare:CC (match_operator:SI 4 "boolean_operator"
3785 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3786 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3787 (const_int 0)))
3788 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3789 (match_dup 4))]
3790 "TARGET_32BIT"
3791 "@
3792 %q4. %0,%1,%2
3793 #"
3794 [(set_attr "type" "fast_compare,compare")
3795 (set_attr "length" "4,8")])
3796
3797 (define_split
3798 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3799 (compare:CC (match_operator:SI 4 "boolean_operator"
3800 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3801 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3802 (const_int 0)))
3803 (set (match_operand:SI 0 "gpc_reg_operand" "")
3804 (match_dup 4))]
3805 "TARGET_32BIT && reload_completed"
3806 [(set (match_dup 0) (match_dup 4))
3807 (set (match_dup 3)
3808 (compare:CC (match_dup 0)
3809 (const_int 0)))]
3810 "")
3811
3812 ;; maskir insn. We need four forms because things might be in arbitrary
3813 ;; orders. Don't define forms that only set CR fields because these
3814 ;; would modify an input register.
3815
3816 (define_insn "*maskir_internal1"
3817 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3818 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3819 (match_operand:SI 1 "gpc_reg_operand" "0"))
3820 (and:SI (match_dup 2)
3821 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3822 "TARGET_POWER"
3823 "maskir %0,%3,%2")
3824
3825 (define_insn "*maskir_internal2"
3826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3827 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3828 (match_operand:SI 1 "gpc_reg_operand" "0"))
3829 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3830 (match_dup 2))))]
3831 "TARGET_POWER"
3832 "maskir %0,%3,%2")
3833
3834 (define_insn "*maskir_internal3"
3835 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3836 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3837 (match_operand:SI 3 "gpc_reg_operand" "r"))
3838 (and:SI (not:SI (match_dup 2))
3839 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3840 "TARGET_POWER"
3841 "maskir %0,%3,%2")
3842
3843 (define_insn "*maskir_internal4"
3844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3845 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3846 (match_operand:SI 2 "gpc_reg_operand" "r"))
3847 (and:SI (not:SI (match_dup 2))
3848 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3849 "TARGET_POWER"
3850 "maskir %0,%3,%2")
3851
3852 (define_insn "*maskir_internal5"
3853 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3854 (compare:CC
3855 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3856 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3857 (and:SI (match_dup 2)
3858 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3859 (const_int 0)))
3860 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3861 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3862 (and:SI (match_dup 2) (match_dup 3))))]
3863 "TARGET_POWER"
3864 "@
3865 maskir. %0,%3,%2
3866 #"
3867 [(set_attr "type" "compare")
3868 (set_attr "length" "4,8")])
3869
3870 (define_split
3871 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3872 (compare:CC
3873 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3874 (match_operand:SI 1 "gpc_reg_operand" ""))
3875 (and:SI (match_dup 2)
3876 (match_operand:SI 3 "gpc_reg_operand" "")))
3877 (const_int 0)))
3878 (set (match_operand:SI 0 "gpc_reg_operand" "")
3879 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3880 (and:SI (match_dup 2) (match_dup 3))))]
3881 "TARGET_POWER && reload_completed"
3882 [(set (match_dup 0)
3883 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3884 (and:SI (match_dup 2) (match_dup 3))))
3885 (set (match_dup 4)
3886 (compare:CC (match_dup 0)
3887 (const_int 0)))]
3888 "")
3889
3890 (define_insn "*maskir_internal6"
3891 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3892 (compare:CC
3893 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3894 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3895 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3896 (match_dup 2)))
3897 (const_int 0)))
3898 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3899 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3900 (and:SI (match_dup 3) (match_dup 2))))]
3901 "TARGET_POWER"
3902 "@
3903 maskir. %0,%3,%2
3904 #"
3905 [(set_attr "type" "compare")
3906 (set_attr "length" "4,8")])
3907
3908 (define_split
3909 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3910 (compare:CC
3911 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3912 (match_operand:SI 1 "gpc_reg_operand" ""))
3913 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3914 (match_dup 2)))
3915 (const_int 0)))
3916 (set (match_operand:SI 0 "gpc_reg_operand" "")
3917 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3918 (and:SI (match_dup 3) (match_dup 2))))]
3919 "TARGET_POWER && reload_completed"
3920 [(set (match_dup 0)
3921 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3922 (and:SI (match_dup 3) (match_dup 2))))
3923 (set (match_dup 4)
3924 (compare:CC (match_dup 0)
3925 (const_int 0)))]
3926 "")
3927
3928 (define_insn "*maskir_internal7"
3929 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3930 (compare:CC
3931 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3932 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3933 (and:SI (not:SI (match_dup 2))
3934 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3935 (const_int 0)))
3936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3937 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3938 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3939 "TARGET_POWER"
3940 "@
3941 maskir. %0,%3,%2
3942 #"
3943 [(set_attr "type" "compare")
3944 (set_attr "length" "4,8")])
3945
3946 (define_split
3947 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3948 (compare:CC
3949 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3950 (match_operand:SI 3 "gpc_reg_operand" ""))
3951 (and:SI (not:SI (match_dup 2))
3952 (match_operand:SI 1 "gpc_reg_operand" "")))
3953 (const_int 0)))
3954 (set (match_operand:SI 0 "gpc_reg_operand" "")
3955 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3956 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3957 "TARGET_POWER && reload_completed"
3958 [(set (match_dup 0)
3959 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3960 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3961 (set (match_dup 4)
3962 (compare:CC (match_dup 0)
3963 (const_int 0)))]
3964 "")
3965
3966 (define_insn "*maskir_internal8"
3967 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3968 (compare:CC
3969 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3970 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3971 (and:SI (not:SI (match_dup 2))
3972 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3973 (const_int 0)))
3974 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3975 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3976 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3977 "TARGET_POWER"
3978 "@
3979 maskir. %0,%3,%2
3980 #"
3981 [(set_attr "type" "compare")
3982 (set_attr "length" "4,8")])
3983
3984 (define_split
3985 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3986 (compare:CC
3987 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3988 (match_operand:SI 2 "gpc_reg_operand" ""))
3989 (and:SI (not:SI (match_dup 2))
3990 (match_operand:SI 1 "gpc_reg_operand" "")))
3991 (const_int 0)))
3992 (set (match_operand:SI 0 "gpc_reg_operand" "")
3993 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3994 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3995 "TARGET_POWER && reload_completed"
3996 [(set (match_dup 0)
3997 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3998 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3999 (set (match_dup 4)
4000 (compare:CC (match_dup 0)
4001 (const_int 0)))]
4002 "")
4003 \f
4004 ;; Rotate and shift insns, in all their variants. These support shifts,
4005 ;; field inserts and extracts, and various combinations thereof.
4006 (define_expand "insv"
4007 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
4008 (match_operand:SI 1 "const_int_operand" "")
4009 (match_operand:SI 2 "const_int_operand" ""))
4010 (match_operand 3 "gpc_reg_operand" ""))]
4011 ""
4012 "
4013 {
4014 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4015 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4016 compiler if the address of the structure is taken later. Likewise, do
4017 not handle invalid E500 subregs. */
4018 if (GET_CODE (operands[0]) == SUBREG
4019 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
4020 || ((TARGET_E500_DOUBLE || TARGET_SPE)
4021 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
4022 FAIL;
4023
4024 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
4025 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
4026 else
4027 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
4028 DONE;
4029 }")
4030
4031 (define_insn "insvsi"
4032 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4033 (match_operand:SI 1 "const_int_operand" "i")
4034 (match_operand:SI 2 "const_int_operand" "i"))
4035 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4036 ""
4037 "*
4038 {
4039 int start = INTVAL (operands[2]) & 31;
4040 int size = INTVAL (operands[1]) & 31;
4041
4042 operands[4] = GEN_INT (32 - start - size);
4043 operands[1] = GEN_INT (start + size - 1);
4044 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4045 }"
4046 [(set_attr "type" "insert_word")])
4047
4048 (define_insn "*insvsi_internal1"
4049 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4050 (match_operand:SI 1 "const_int_operand" "i")
4051 (match_operand:SI 2 "const_int_operand" "i"))
4052 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4053 (match_operand:SI 4 "const_int_operand" "i")))]
4054 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4055 "*
4056 {
4057 int shift = INTVAL (operands[4]) & 31;
4058 int start = INTVAL (operands[2]) & 31;
4059 int size = INTVAL (operands[1]) & 31;
4060
4061 operands[4] = GEN_INT (shift - start - size);
4062 operands[1] = GEN_INT (start + size - 1);
4063 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4064 }"
4065 [(set_attr "type" "insert_word")])
4066
4067 (define_insn "*insvsi_internal2"
4068 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4069 (match_operand:SI 1 "const_int_operand" "i")
4070 (match_operand:SI 2 "const_int_operand" "i"))
4071 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4072 (match_operand:SI 4 "const_int_operand" "i")))]
4073 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4074 "*
4075 {
4076 int shift = INTVAL (operands[4]) & 31;
4077 int start = INTVAL (operands[2]) & 31;
4078 int size = INTVAL (operands[1]) & 31;
4079
4080 operands[4] = GEN_INT (32 - shift - start - size);
4081 operands[1] = GEN_INT (start + size - 1);
4082 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4083 }"
4084 [(set_attr "type" "insert_word")])
4085
4086 (define_insn "*insvsi_internal3"
4087 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4088 (match_operand:SI 1 "const_int_operand" "i")
4089 (match_operand:SI 2 "const_int_operand" "i"))
4090 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4091 (match_operand:SI 4 "const_int_operand" "i")))]
4092 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4093 "*
4094 {
4095 int shift = INTVAL (operands[4]) & 31;
4096 int start = INTVAL (operands[2]) & 31;
4097 int size = INTVAL (operands[1]) & 31;
4098
4099 operands[4] = GEN_INT (32 - shift - start - size);
4100 operands[1] = GEN_INT (start + size - 1);
4101 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4102 }"
4103 [(set_attr "type" "insert_word")])
4104
4105 (define_insn "*insvsi_internal4"
4106 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4107 (match_operand:SI 1 "const_int_operand" "i")
4108 (match_operand:SI 2 "const_int_operand" "i"))
4109 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4110 (match_operand:SI 4 "const_int_operand" "i")
4111 (match_operand:SI 5 "const_int_operand" "i")))]
4112 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4113 "*
4114 {
4115 int extract_start = INTVAL (operands[5]) & 31;
4116 int extract_size = INTVAL (operands[4]) & 31;
4117 int insert_start = INTVAL (operands[2]) & 31;
4118 int insert_size = INTVAL (operands[1]) & 31;
4119
4120 /* Align extract field with insert field */
4121 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4122 operands[1] = GEN_INT (insert_start + insert_size - 1);
4123 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4124 }"
4125 [(set_attr "type" "insert_word")])
4126
4127 ;; combine patterns for rlwimi
4128 (define_insn "*insvsi_internal5"
4129 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4130 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4131 (match_operand:SI 1 "mask_operand" "i"))
4132 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4133 (match_operand:SI 2 "const_int_operand" "i"))
4134 (match_operand:SI 5 "mask_operand" "i"))))]
4135 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4136 "*
4137 {
4138 int me = extract_ME(operands[5]);
4139 int mb = extract_MB(operands[5]);
4140 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4141 operands[2] = GEN_INT(mb);
4142 operands[1] = GEN_INT(me);
4143 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4144 }"
4145 [(set_attr "type" "insert_word")])
4146
4147 (define_insn "*insvsi_internal6"
4148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4149 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4150 (match_operand:SI 2 "const_int_operand" "i"))
4151 (match_operand:SI 5 "mask_operand" "i"))
4152 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4153 (match_operand:SI 1 "mask_operand" "i"))))]
4154 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4155 "*
4156 {
4157 int me = extract_ME(operands[5]);
4158 int mb = extract_MB(operands[5]);
4159 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4160 operands[2] = GEN_INT(mb);
4161 operands[1] = GEN_INT(me);
4162 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4163 }"
4164 [(set_attr "type" "insert_word")])
4165
4166 (define_insn "insvdi"
4167 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4168 (match_operand:SI 1 "const_int_operand" "i")
4169 (match_operand:SI 2 "const_int_operand" "i"))
4170 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4171 "TARGET_POWERPC64"
4172 "*
4173 {
4174 int start = INTVAL (operands[2]) & 63;
4175 int size = INTVAL (operands[1]) & 63;
4176
4177 operands[1] = GEN_INT (64 - start - size);
4178 return \"rldimi %0,%3,%H1,%H2\";
4179 }"
4180 [(set_attr "type" "insert_dword")])
4181
4182 (define_insn "*insvdi_internal2"
4183 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4184 (match_operand:SI 1 "const_int_operand" "i")
4185 (match_operand:SI 2 "const_int_operand" "i"))
4186 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4187 (match_operand:SI 4 "const_int_operand" "i")))]
4188 "TARGET_POWERPC64
4189 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4190 "*
4191 {
4192 int shift = INTVAL (operands[4]) & 63;
4193 int start = (INTVAL (operands[2]) & 63) - 32;
4194 int size = INTVAL (operands[1]) & 63;
4195
4196 operands[4] = GEN_INT (64 - shift - start - size);
4197 operands[2] = GEN_INT (start);
4198 operands[1] = GEN_INT (start + size - 1);
4199 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4200 }")
4201
4202 (define_insn "*insvdi_internal3"
4203 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4204 (match_operand:SI 1 "const_int_operand" "i")
4205 (match_operand:SI 2 "const_int_operand" "i"))
4206 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4207 (match_operand:SI 4 "const_int_operand" "i")))]
4208 "TARGET_POWERPC64
4209 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4210 "*
4211 {
4212 int shift = INTVAL (operands[4]) & 63;
4213 int start = (INTVAL (operands[2]) & 63) - 32;
4214 int size = INTVAL (operands[1]) & 63;
4215
4216 operands[4] = GEN_INT (64 - shift - start - size);
4217 operands[2] = GEN_INT (start);
4218 operands[1] = GEN_INT (start + size - 1);
4219 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4220 }")
4221
4222 (define_expand "extzv"
4223 [(set (match_operand 0 "gpc_reg_operand" "")
4224 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4225 (match_operand:SI 2 "const_int_operand" "")
4226 (match_operand:SI 3 "const_int_operand" "")))]
4227 ""
4228 "
4229 {
4230 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4231 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4232 compiler if the address of the structure is taken later. */
4233 if (GET_CODE (operands[0]) == SUBREG
4234 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4235 FAIL;
4236
4237 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4238 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4239 else
4240 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4241 DONE;
4242 }")
4243
4244 (define_insn "extzvsi"
4245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4246 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4247 (match_operand:SI 2 "const_int_operand" "i")
4248 (match_operand:SI 3 "const_int_operand" "i")))]
4249 ""
4250 "*
4251 {
4252 int start = INTVAL (operands[3]) & 31;
4253 int size = INTVAL (operands[2]) & 31;
4254
4255 if (start + size >= 32)
4256 operands[3] = const0_rtx;
4257 else
4258 operands[3] = GEN_INT (start + size);
4259 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4260 }")
4261
4262 (define_insn "*extzvsi_internal1"
4263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4264 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4265 (match_operand:SI 2 "const_int_operand" "i,i")
4266 (match_operand:SI 3 "const_int_operand" "i,i"))
4267 (const_int 0)))
4268 (clobber (match_scratch:SI 4 "=r,r"))]
4269 ""
4270 "*
4271 {
4272 int start = INTVAL (operands[3]) & 31;
4273 int size = INTVAL (operands[2]) & 31;
4274
4275 /* Force split for non-cc0 compare. */
4276 if (which_alternative == 1)
4277 return \"#\";
4278
4279 /* If the bit-field being tested fits in the upper or lower half of a
4280 word, it is possible to use andiu. or andil. to test it. This is
4281 useful because the condition register set-use delay is smaller for
4282 andi[ul]. than for rlinm. This doesn't work when the starting bit
4283 position is 0 because the LT and GT bits may be set wrong. */
4284
4285 if ((start > 0 && start + size <= 16) || start >= 16)
4286 {
4287 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4288 - (1 << (16 - (start & 15) - size))));
4289 if (start < 16)
4290 return \"{andiu.|andis.} %4,%1,%3\";
4291 else
4292 return \"{andil.|andi.} %4,%1,%3\";
4293 }
4294
4295 if (start + size >= 32)
4296 operands[3] = const0_rtx;
4297 else
4298 operands[3] = GEN_INT (start + size);
4299 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4300 }"
4301 [(set_attr "type" "delayed_compare")
4302 (set_attr "length" "4,8")])
4303
4304 (define_split
4305 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4306 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4307 (match_operand:SI 2 "const_int_operand" "")
4308 (match_operand:SI 3 "const_int_operand" ""))
4309 (const_int 0)))
4310 (clobber (match_scratch:SI 4 ""))]
4311 "reload_completed"
4312 [(set (match_dup 4)
4313 (zero_extract:SI (match_dup 1) (match_dup 2)
4314 (match_dup 3)))
4315 (set (match_dup 0)
4316 (compare:CC (match_dup 4)
4317 (const_int 0)))]
4318 "")
4319
4320 (define_insn "*extzvsi_internal2"
4321 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4322 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4323 (match_operand:SI 2 "const_int_operand" "i,i")
4324 (match_operand:SI 3 "const_int_operand" "i,i"))
4325 (const_int 0)))
4326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4327 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4328 ""
4329 "*
4330 {
4331 int start = INTVAL (operands[3]) & 31;
4332 int size = INTVAL (operands[2]) & 31;
4333
4334 /* Force split for non-cc0 compare. */
4335 if (which_alternative == 1)
4336 return \"#\";
4337
4338 /* Since we are using the output value, we can't ignore any need for
4339 a shift. The bit-field must end at the LSB. */
4340 if (start >= 16 && start + size == 32)
4341 {
4342 operands[3] = GEN_INT ((1 << size) - 1);
4343 return \"{andil.|andi.} %0,%1,%3\";
4344 }
4345
4346 if (start + size >= 32)
4347 operands[3] = const0_rtx;
4348 else
4349 operands[3] = GEN_INT (start + size);
4350 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4351 }"
4352 [(set_attr "type" "delayed_compare")
4353 (set_attr "length" "4,8")])
4354
4355 (define_split
4356 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4357 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4358 (match_operand:SI 2 "const_int_operand" "")
4359 (match_operand:SI 3 "const_int_operand" ""))
4360 (const_int 0)))
4361 (set (match_operand:SI 0 "gpc_reg_operand" "")
4362 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4363 "reload_completed"
4364 [(set (match_dup 0)
4365 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4366 (set (match_dup 4)
4367 (compare:CC (match_dup 0)
4368 (const_int 0)))]
4369 "")
4370
4371 (define_insn "extzvdi"
4372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4373 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4374 (match_operand:SI 2 "const_int_operand" "i")
4375 (match_operand:SI 3 "const_int_operand" "i")))]
4376 "TARGET_POWERPC64"
4377 "*
4378 {
4379 int start = INTVAL (operands[3]) & 63;
4380 int size = INTVAL (operands[2]) & 63;
4381
4382 if (start + size >= 64)
4383 operands[3] = const0_rtx;
4384 else
4385 operands[3] = GEN_INT (start + size);
4386 operands[2] = GEN_INT (64 - size);
4387 return \"rldicl %0,%1,%3,%2\";
4388 }")
4389
4390 (define_insn "*extzvdi_internal1"
4391 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4392 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4393 (match_operand:SI 2 "const_int_operand" "i")
4394 (match_operand:SI 3 "const_int_operand" "i"))
4395 (const_int 0)))
4396 (clobber (match_scratch:DI 4 "=r"))]
4397 "TARGET_64BIT && rs6000_gen_cell_microcode"
4398 "*
4399 {
4400 int start = INTVAL (operands[3]) & 63;
4401 int size = INTVAL (operands[2]) & 63;
4402
4403 if (start + size >= 64)
4404 operands[3] = const0_rtx;
4405 else
4406 operands[3] = GEN_INT (start + size);
4407 operands[2] = GEN_INT (64 - size);
4408 return \"rldicl. %4,%1,%3,%2\";
4409 }"
4410 [(set_attr "type" "compare")])
4411
4412 (define_insn "*extzvdi_internal2"
4413 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4414 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4415 (match_operand:SI 2 "const_int_operand" "i")
4416 (match_operand:SI 3 "const_int_operand" "i"))
4417 (const_int 0)))
4418 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4419 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4420 "TARGET_64BIT && rs6000_gen_cell_microcode"
4421 "*
4422 {
4423 int start = INTVAL (operands[3]) & 63;
4424 int size = INTVAL (operands[2]) & 63;
4425
4426 if (start + size >= 64)
4427 operands[3] = const0_rtx;
4428 else
4429 operands[3] = GEN_INT (start + size);
4430 operands[2] = GEN_INT (64 - size);
4431 return \"rldicl. %0,%1,%3,%2\";
4432 }"
4433 [(set_attr "type" "compare")])
4434
4435 (define_insn "rotlsi3"
4436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4437 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4438 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4439 ""
4440 "@
4441 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4442 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4443 [(set_attr "type" "var_shift_rotate,integer")])
4444
4445 (define_insn "*rotlsi3_64"
4446 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4447 (zero_extend:DI
4448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4449 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4450 "TARGET_64BIT"
4451 "@
4452 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4453 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4454 [(set_attr "type" "var_shift_rotate,integer")])
4455
4456 (define_insn "*rotlsi3_internal2"
4457 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4458 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4459 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4460 (const_int 0)))
4461 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4462 ""
4463 "@
4464 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4465 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4466 #
4467 #"
4468 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4469 (set_attr "length" "4,4,8,8")])
4470
4471 (define_split
4472 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4473 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4474 (match_operand:SI 2 "reg_or_cint_operand" ""))
4475 (const_int 0)))
4476 (clobber (match_scratch:SI 3 ""))]
4477 "reload_completed"
4478 [(set (match_dup 3)
4479 (rotate:SI (match_dup 1) (match_dup 2)))
4480 (set (match_dup 0)
4481 (compare:CC (match_dup 3)
4482 (const_int 0)))]
4483 "")
4484
4485 (define_insn "*rotlsi3_internal3"
4486 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4487 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4488 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4489 (const_int 0)))
4490 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4491 (rotate:SI (match_dup 1) (match_dup 2)))]
4492 ""
4493 "@
4494 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4495 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4496 #
4497 #"
4498 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4499 (set_attr "length" "4,4,8,8")])
4500
4501 (define_split
4502 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4503 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4504 (match_operand:SI 2 "reg_or_cint_operand" ""))
4505 (const_int 0)))
4506 (set (match_operand:SI 0 "gpc_reg_operand" "")
4507 (rotate:SI (match_dup 1) (match_dup 2)))]
4508 "reload_completed"
4509 [(set (match_dup 0)
4510 (rotate:SI (match_dup 1) (match_dup 2)))
4511 (set (match_dup 3)
4512 (compare:CC (match_dup 0)
4513 (const_int 0)))]
4514 "")
4515
4516 (define_insn "*rotlsi3_internal4"
4517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4518 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4519 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4520 (match_operand:SI 3 "mask_operand" "n,n")))]
4521 ""
4522 "@
4523 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4524 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4525 [(set_attr "type" "var_shift_rotate,integer")])
4526
4527 (define_insn "*rotlsi3_internal5"
4528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4529 (compare:CC (and:SI
4530 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4531 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4532 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4533 (const_int 0)))
4534 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4535 ""
4536 "@
4537 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4538 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4539 #
4540 #"
4541 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4542 (set_attr "length" "4,4,8,8")])
4543
4544 (define_split
4545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4546 (compare:CC (and:SI
4547 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4548 (match_operand:SI 2 "reg_or_cint_operand" ""))
4549 (match_operand:SI 3 "mask_operand" ""))
4550 (const_int 0)))
4551 (clobber (match_scratch:SI 4 ""))]
4552 "reload_completed"
4553 [(set (match_dup 4)
4554 (and:SI (rotate:SI (match_dup 1)
4555 (match_dup 2))
4556 (match_dup 3)))
4557 (set (match_dup 0)
4558 (compare:CC (match_dup 4)
4559 (const_int 0)))]
4560 "")
4561
4562 (define_insn "*rotlsi3_internal6"
4563 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4564 (compare:CC (and:SI
4565 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4566 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4567 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4568 (const_int 0)))
4569 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4570 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4571 ""
4572 "@
4573 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4574 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4575 #
4576 #"
4577 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4578 (set_attr "length" "4,4,8,8")])
4579
4580 (define_split
4581 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4582 (compare:CC (and:SI
4583 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4584 (match_operand:SI 2 "reg_or_cint_operand" ""))
4585 (match_operand:SI 3 "mask_operand" ""))
4586 (const_int 0)))
4587 (set (match_operand:SI 0 "gpc_reg_operand" "")
4588 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4589 "reload_completed"
4590 [(set (match_dup 0)
4591 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4592 (set (match_dup 4)
4593 (compare:CC (match_dup 0)
4594 (const_int 0)))]
4595 "")
4596
4597 (define_insn "*rotlsi3_internal7"
4598 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4599 (zero_extend:SI
4600 (subreg:QI
4601 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4602 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4603 ""
4604 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4605 [(set (attr "cell_micro")
4606 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4607 (const_string "not")
4608 (const_string "always")))])
4609
4610 (define_insn "*rotlsi3_internal8"
4611 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4612 (compare:CC (zero_extend:SI
4613 (subreg:QI
4614 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4615 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4616 (const_int 0)))
4617 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4618 ""
4619 "@
4620 {rlnm.|rlwnm.} %3,%1,%2,0xff
4621 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4622 #
4623 #"
4624 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4625 (set_attr "length" "4,4,8,8")])
4626
4627 (define_split
4628 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4629 (compare:CC (zero_extend:SI
4630 (subreg:QI
4631 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4632 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4633 (const_int 0)))
4634 (clobber (match_scratch:SI 3 ""))]
4635 "reload_completed"
4636 [(set (match_dup 3)
4637 (zero_extend:SI (subreg:QI
4638 (rotate:SI (match_dup 1)
4639 (match_dup 2)) 0)))
4640 (set (match_dup 0)
4641 (compare:CC (match_dup 3)
4642 (const_int 0)))]
4643 "")
4644
4645 (define_insn "*rotlsi3_internal9"
4646 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4647 (compare:CC (zero_extend:SI
4648 (subreg:QI
4649 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4650 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4651 (const_int 0)))
4652 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4653 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4654 ""
4655 "@
4656 {rlnm.|rlwnm.} %0,%1,%2,0xff
4657 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4658 #
4659 #"
4660 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4661 (set_attr "length" "4,4,8,8")])
4662
4663 (define_split
4664 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4665 (compare:CC (zero_extend:SI
4666 (subreg:QI
4667 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4668 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4669 (const_int 0)))
4670 (set (match_operand:SI 0 "gpc_reg_operand" "")
4671 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4672 "reload_completed"
4673 [(set (match_dup 0)
4674 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4675 (set (match_dup 3)
4676 (compare:CC (match_dup 0)
4677 (const_int 0)))]
4678 "")
4679
4680 (define_insn "*rotlsi3_internal10"
4681 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4682 (zero_extend:SI
4683 (subreg:HI
4684 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4685 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4686 ""
4687 "@
4688 {rlnm|rlwnm} %0,%1,%2,0xffff
4689 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4690 [(set_attr "type" "var_shift_rotate,integer")])
4691
4692
4693 (define_insn "*rotlsi3_internal11"
4694 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4695 (compare:CC (zero_extend:SI
4696 (subreg:HI
4697 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4698 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4699 (const_int 0)))
4700 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4701 ""
4702 "@
4703 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4704 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4705 #
4706 #"
4707 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4708 (set_attr "length" "4,4,8,8")])
4709
4710 (define_split
4711 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4712 (compare:CC (zero_extend:SI
4713 (subreg:HI
4714 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4715 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4716 (const_int 0)))
4717 (clobber (match_scratch:SI 3 ""))]
4718 "reload_completed"
4719 [(set (match_dup 3)
4720 (zero_extend:SI (subreg:HI
4721 (rotate:SI (match_dup 1)
4722 (match_dup 2)) 0)))
4723 (set (match_dup 0)
4724 (compare:CC (match_dup 3)
4725 (const_int 0)))]
4726 "")
4727
4728 (define_insn "*rotlsi3_internal12"
4729 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4730 (compare:CC (zero_extend:SI
4731 (subreg:HI
4732 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4733 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4734 (const_int 0)))
4735 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4736 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4737 ""
4738 "@
4739 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4740 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4741 #
4742 #"
4743 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4744 (set_attr "length" "4,4,8,8")])
4745
4746 (define_split
4747 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4748 (compare:CC (zero_extend:SI
4749 (subreg:HI
4750 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4751 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4752 (const_int 0)))
4753 (set (match_operand:SI 0 "gpc_reg_operand" "")
4754 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4755 "reload_completed"
4756 [(set (match_dup 0)
4757 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4758 (set (match_dup 3)
4759 (compare:CC (match_dup 0)
4760 (const_int 0)))]
4761 "")
4762
4763 ;; Note that we use "sle." instead of "sl." so that we can set
4764 ;; SHIFT_COUNT_TRUNCATED.
4765
4766 (define_expand "ashlsi3"
4767 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4768 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4769 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4770 ""
4771 "
4772 {
4773 if (TARGET_POWER)
4774 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4775 else
4776 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4777 DONE;
4778 }")
4779
4780 (define_insn "ashlsi3_power"
4781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4782 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4783 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4784 (clobber (match_scratch:SI 3 "=q,X"))]
4785 "TARGET_POWER"
4786 "@
4787 sle %0,%1,%2
4788 {sli|slwi} %0,%1,%h2")
4789
4790 (define_insn "ashlsi3_no_power"
4791 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4792 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4793 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4794 "! TARGET_POWER"
4795 "@
4796 {sl|slw} %0,%1,%2
4797 {sli|slwi} %0,%1,%h2"
4798 [(set_attr "type" "var_shift_rotate,shift")])
4799
4800 (define_insn "*ashlsi3_64"
4801 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4802 (zero_extend:DI
4803 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4804 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4805 "TARGET_POWERPC64"
4806 "@
4807 {sl|slw} %0,%1,%2
4808 {sli|slwi} %0,%1,%h2"
4809 [(set_attr "type" "var_shift_rotate,shift")])
4810
4811 (define_insn ""
4812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4813 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4814 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4815 (const_int 0)))
4816 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4817 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4818 "TARGET_POWER"
4819 "@
4820 sle. %3,%1,%2
4821 {sli.|slwi.} %3,%1,%h2
4822 #
4823 #"
4824 [(set_attr "type" "delayed_compare")
4825 (set_attr "length" "4,4,8,8")])
4826
4827 (define_split
4828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4829 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4830 (match_operand:SI 2 "reg_or_cint_operand" ""))
4831 (const_int 0)))
4832 (clobber (match_scratch:SI 3 ""))
4833 (clobber (match_scratch:SI 4 ""))]
4834 "TARGET_POWER && reload_completed"
4835 [(parallel [(set (match_dup 3)
4836 (ashift:SI (match_dup 1) (match_dup 2)))
4837 (clobber (match_dup 4))])
4838 (set (match_dup 0)
4839 (compare:CC (match_dup 3)
4840 (const_int 0)))]
4841 "")
4842
4843 (define_insn ""
4844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4845 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4846 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4847 (const_int 0)))
4848 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4849 "! TARGET_POWER && TARGET_32BIT"
4850 "@
4851 {sl.|slw.} %3,%1,%2
4852 {sli.|slwi.} %3,%1,%h2
4853 #
4854 #"
4855 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4856 (set_attr "length" "4,4,8,8")])
4857
4858 (define_split
4859 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4860 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4861 (match_operand:SI 2 "reg_or_cint_operand" ""))
4862 (const_int 0)))
4863 (clobber (match_scratch:SI 3 ""))]
4864 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4865 [(set (match_dup 3)
4866 (ashift:SI (match_dup 1) (match_dup 2)))
4867 (set (match_dup 0)
4868 (compare:CC (match_dup 3)
4869 (const_int 0)))]
4870 "")
4871
4872 (define_insn ""
4873 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4874 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4875 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4876 (const_int 0)))
4877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4878 (ashift:SI (match_dup 1) (match_dup 2)))
4879 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4880 "TARGET_POWER"
4881 "@
4882 sle. %0,%1,%2
4883 {sli.|slwi.} %0,%1,%h2
4884 #
4885 #"
4886 [(set_attr "type" "delayed_compare")
4887 (set_attr "length" "4,4,8,8")])
4888
4889 (define_split
4890 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4891 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4892 (match_operand:SI 2 "reg_or_cint_operand" ""))
4893 (const_int 0)))
4894 (set (match_operand:SI 0 "gpc_reg_operand" "")
4895 (ashift:SI (match_dup 1) (match_dup 2)))
4896 (clobber (match_scratch:SI 4 ""))]
4897 "TARGET_POWER && reload_completed"
4898 [(parallel [(set (match_dup 0)
4899 (ashift:SI (match_dup 1) (match_dup 2)))
4900 (clobber (match_dup 4))])
4901 (set (match_dup 3)
4902 (compare:CC (match_dup 0)
4903 (const_int 0)))]
4904 "")
4905
4906 (define_insn ""
4907 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4908 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4909 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4910 (const_int 0)))
4911 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4912 (ashift:SI (match_dup 1) (match_dup 2)))]
4913 "! TARGET_POWER && TARGET_32BIT"
4914 "@
4915 {sl.|slw.} %0,%1,%2
4916 {sli.|slwi.} %0,%1,%h2
4917 #
4918 #"
4919 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4920 (set_attr "length" "4,4,8,8")])
4921
4922 (define_split
4923 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4924 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4925 (match_operand:SI 2 "reg_or_cint_operand" ""))
4926 (const_int 0)))
4927 (set (match_operand:SI 0 "gpc_reg_operand" "")
4928 (ashift:SI (match_dup 1) (match_dup 2)))]
4929 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4930 [(set (match_dup 0)
4931 (ashift:SI (match_dup 1) (match_dup 2)))
4932 (set (match_dup 3)
4933 (compare:CC (match_dup 0)
4934 (const_int 0)))]
4935 "")
4936
4937 (define_insn "rlwinm"
4938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4939 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4940 (match_operand:SI 2 "const_int_operand" "i"))
4941 (match_operand:SI 3 "mask_operand" "n")))]
4942 "includes_lshift_p (operands[2], operands[3])"
4943 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4944
4945 (define_insn ""
4946 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4947 (compare:CC
4948 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4949 (match_operand:SI 2 "const_int_operand" "i,i"))
4950 (match_operand:SI 3 "mask_operand" "n,n"))
4951 (const_int 0)))
4952 (clobber (match_scratch:SI 4 "=r,r"))]
4953 "includes_lshift_p (operands[2], operands[3])"
4954 "@
4955 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4956 #"
4957 [(set_attr "type" "delayed_compare")
4958 (set_attr "length" "4,8")])
4959
4960 (define_split
4961 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4962 (compare:CC
4963 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4964 (match_operand:SI 2 "const_int_operand" ""))
4965 (match_operand:SI 3 "mask_operand" ""))
4966 (const_int 0)))
4967 (clobber (match_scratch:SI 4 ""))]
4968 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4969 [(set (match_dup 4)
4970 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4971 (match_dup 3)))
4972 (set (match_dup 0)
4973 (compare:CC (match_dup 4)
4974 (const_int 0)))]
4975 "")
4976
4977 (define_insn ""
4978 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4979 (compare:CC
4980 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4981 (match_operand:SI 2 "const_int_operand" "i,i"))
4982 (match_operand:SI 3 "mask_operand" "n,n"))
4983 (const_int 0)))
4984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4985 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4986 "includes_lshift_p (operands[2], operands[3])"
4987 "@
4988 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4989 #"
4990 [(set_attr "type" "delayed_compare")
4991 (set_attr "length" "4,8")])
4992
4993 (define_split
4994 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4995 (compare:CC
4996 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4997 (match_operand:SI 2 "const_int_operand" ""))
4998 (match_operand:SI 3 "mask_operand" ""))
4999 (const_int 0)))
5000 (set (match_operand:SI 0 "gpc_reg_operand" "")
5001 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5002 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
5003 [(set (match_dup 0)
5004 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5005 (set (match_dup 4)
5006 (compare:CC (match_dup 0)
5007 (const_int 0)))]
5008 "")
5009
5010 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5011 ;; "sli x,x,0".
5012 (define_expand "lshrsi3"
5013 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
5014 (use (match_operand:SI 1 "gpc_reg_operand" ""))
5015 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
5016 ""
5017 "
5018 {
5019 if (TARGET_POWER)
5020 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
5021 else
5022 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
5023 DONE;
5024 }")
5025
5026 (define_insn "lshrsi3_power"
5027 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5028 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5029 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
5030 (clobber (match_scratch:SI 3 "=q,X,X"))]
5031 "TARGET_POWER"
5032 "@
5033 sre %0,%1,%2
5034 mr %0,%1
5035 {s%A2i|s%A2wi} %0,%1,%h2")
5036
5037 (define_insn "lshrsi3_no_power"
5038 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5039 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5040 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5041 "! TARGET_POWER"
5042 "@
5043 mr %0,%1
5044 {sr|srw} %0,%1,%2
5045 {sri|srwi} %0,%1,%h2"
5046 [(set_attr "type" "integer,var_shift_rotate,shift")])
5047
5048 (define_insn "*lshrsi3_64"
5049 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5050 (zero_extend:DI
5051 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5052 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5053 "TARGET_POWERPC64"
5054 "@
5055 {sr|srw} %0,%1,%2
5056 {sri|srwi} %0,%1,%h2"
5057 [(set_attr "type" "var_shift_rotate,shift")])
5058
5059 (define_insn ""
5060 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5061 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5062 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5063 (const_int 0)))
5064 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5065 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5066 "TARGET_POWER"
5067 "@
5068 sre. %3,%1,%2
5069 mr. %1,%1
5070 {s%A2i.|s%A2wi.} %3,%1,%h2
5071 #
5072 #
5073 #"
5074 [(set_attr "type" "delayed_compare")
5075 (set_attr "length" "4,4,4,8,8,8")])
5076
5077 (define_split
5078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5079 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5080 (match_operand:SI 2 "reg_or_cint_operand" ""))
5081 (const_int 0)))
5082 (clobber (match_scratch:SI 3 ""))
5083 (clobber (match_scratch:SI 4 ""))]
5084 "TARGET_POWER && reload_completed"
5085 [(parallel [(set (match_dup 3)
5086 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5087 (clobber (match_dup 4))])
5088 (set (match_dup 0)
5089 (compare:CC (match_dup 3)
5090 (const_int 0)))]
5091 "")
5092
5093 (define_insn ""
5094 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5095 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5096 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5097 (const_int 0)))
5098 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5099 "! TARGET_POWER && TARGET_32BIT"
5100 "@
5101 mr. %1,%1
5102 {sr.|srw.} %3,%1,%2
5103 {sri.|srwi.} %3,%1,%h2
5104 #
5105 #
5106 #"
5107 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5108 (set_attr "length" "4,4,4,8,8,8")])
5109
5110 (define_split
5111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5112 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5113 (match_operand:SI 2 "reg_or_cint_operand" ""))
5114 (const_int 0)))
5115 (clobber (match_scratch:SI 3 ""))]
5116 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5117 [(set (match_dup 3)
5118 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5119 (set (match_dup 0)
5120 (compare:CC (match_dup 3)
5121 (const_int 0)))]
5122 "")
5123
5124 (define_insn ""
5125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5126 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5127 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5128 (const_int 0)))
5129 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5130 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5131 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5132 "TARGET_POWER"
5133 "@
5134 sre. %0,%1,%2
5135 mr. %0,%1
5136 {s%A2i.|s%A2wi.} %0,%1,%h2
5137 #
5138 #
5139 #"
5140 [(set_attr "type" "delayed_compare")
5141 (set_attr "length" "4,4,4,8,8,8")])
5142
5143 (define_split
5144 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5145 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5146 (match_operand:SI 2 "reg_or_cint_operand" ""))
5147 (const_int 0)))
5148 (set (match_operand:SI 0 "gpc_reg_operand" "")
5149 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5150 (clobber (match_scratch:SI 4 ""))]
5151 "TARGET_POWER && reload_completed"
5152 [(parallel [(set (match_dup 0)
5153 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5154 (clobber (match_dup 4))])
5155 (set (match_dup 3)
5156 (compare:CC (match_dup 0)
5157 (const_int 0)))]
5158 "")
5159
5160 (define_insn ""
5161 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5162 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5163 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5164 (const_int 0)))
5165 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5166 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5167 "! TARGET_POWER && TARGET_32BIT"
5168 "@
5169 mr. %0,%1
5170 {sr.|srw.} %0,%1,%2
5171 {sri.|srwi.} %0,%1,%h2
5172 #
5173 #
5174 #"
5175 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5176 (set_attr "length" "4,4,4,8,8,8")])
5177
5178 (define_split
5179 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5180 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5181 (match_operand:SI 2 "reg_or_cint_operand" ""))
5182 (const_int 0)))
5183 (set (match_operand:SI 0 "gpc_reg_operand" "")
5184 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5185 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5186 [(set (match_dup 0)
5187 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5188 (set (match_dup 3)
5189 (compare:CC (match_dup 0)
5190 (const_int 0)))]
5191 "")
5192
5193 (define_insn ""
5194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5195 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5196 (match_operand:SI 2 "const_int_operand" "i"))
5197 (match_operand:SI 3 "mask_operand" "n")))]
5198 "includes_rshift_p (operands[2], operands[3])"
5199 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5200
5201 (define_insn ""
5202 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5203 (compare:CC
5204 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5205 (match_operand:SI 2 "const_int_operand" "i,i"))
5206 (match_operand:SI 3 "mask_operand" "n,n"))
5207 (const_int 0)))
5208 (clobber (match_scratch:SI 4 "=r,r"))]
5209 "includes_rshift_p (operands[2], operands[3])"
5210 "@
5211 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5212 #"
5213 [(set_attr "type" "delayed_compare")
5214 (set_attr "length" "4,8")])
5215
5216 (define_split
5217 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5218 (compare:CC
5219 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5220 (match_operand:SI 2 "const_int_operand" ""))
5221 (match_operand:SI 3 "mask_operand" ""))
5222 (const_int 0)))
5223 (clobber (match_scratch:SI 4 ""))]
5224 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5225 [(set (match_dup 4)
5226 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5227 (match_dup 3)))
5228 (set (match_dup 0)
5229 (compare:CC (match_dup 4)
5230 (const_int 0)))]
5231 "")
5232
5233 (define_insn ""
5234 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5235 (compare:CC
5236 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5237 (match_operand:SI 2 "const_int_operand" "i,i"))
5238 (match_operand:SI 3 "mask_operand" "n,n"))
5239 (const_int 0)))
5240 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5241 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5242 "includes_rshift_p (operands[2], operands[3])"
5243 "@
5244 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5245 #"
5246 [(set_attr "type" "delayed_compare")
5247 (set_attr "length" "4,8")])
5248
5249 (define_split
5250 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5251 (compare:CC
5252 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5253 (match_operand:SI 2 "const_int_operand" ""))
5254 (match_operand:SI 3 "mask_operand" ""))
5255 (const_int 0)))
5256 (set (match_operand:SI 0 "gpc_reg_operand" "")
5257 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5258 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5259 [(set (match_dup 0)
5260 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5261 (set (match_dup 4)
5262 (compare:CC (match_dup 0)
5263 (const_int 0)))]
5264 "")
5265
5266 (define_insn ""
5267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5268 (zero_extend:SI
5269 (subreg:QI
5270 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5271 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5272 "includes_rshift_p (operands[2], GEN_INT (255))"
5273 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5274
5275 (define_insn ""
5276 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5277 (compare:CC
5278 (zero_extend:SI
5279 (subreg:QI
5280 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5281 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5282 (const_int 0)))
5283 (clobber (match_scratch:SI 3 "=r,r"))]
5284 "includes_rshift_p (operands[2], GEN_INT (255))"
5285 "@
5286 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5287 #"
5288 [(set_attr "type" "delayed_compare")
5289 (set_attr "length" "4,8")])
5290
5291 (define_split
5292 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5293 (compare:CC
5294 (zero_extend:SI
5295 (subreg:QI
5296 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5297 (match_operand:SI 2 "const_int_operand" "")) 0))
5298 (const_int 0)))
5299 (clobber (match_scratch:SI 3 ""))]
5300 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5301 [(set (match_dup 3)
5302 (zero_extend:SI (subreg:QI
5303 (lshiftrt:SI (match_dup 1)
5304 (match_dup 2)) 0)))
5305 (set (match_dup 0)
5306 (compare:CC (match_dup 3)
5307 (const_int 0)))]
5308 "")
5309
5310 (define_insn ""
5311 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5312 (compare:CC
5313 (zero_extend:SI
5314 (subreg:QI
5315 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5316 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5317 (const_int 0)))
5318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5319 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5320 "includes_rshift_p (operands[2], GEN_INT (255))"
5321 "@
5322 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5323 #"
5324 [(set_attr "type" "delayed_compare")
5325 (set_attr "length" "4,8")])
5326
5327 (define_split
5328 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5329 (compare:CC
5330 (zero_extend:SI
5331 (subreg:QI
5332 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5333 (match_operand:SI 2 "const_int_operand" "")) 0))
5334 (const_int 0)))
5335 (set (match_operand:SI 0 "gpc_reg_operand" "")
5336 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5337 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5338 [(set (match_dup 0)
5339 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5340 (set (match_dup 3)
5341 (compare:CC (match_dup 0)
5342 (const_int 0)))]
5343 "")
5344
5345 (define_insn ""
5346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5347 (zero_extend:SI
5348 (subreg:HI
5349 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5350 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5351 "includes_rshift_p (operands[2], GEN_INT (65535))"
5352 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5353
5354 (define_insn ""
5355 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5356 (compare:CC
5357 (zero_extend:SI
5358 (subreg:HI
5359 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5360 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5361 (const_int 0)))
5362 (clobber (match_scratch:SI 3 "=r,r"))]
5363 "includes_rshift_p (operands[2], GEN_INT (65535))"
5364 "@
5365 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5366 #"
5367 [(set_attr "type" "delayed_compare")
5368 (set_attr "length" "4,8")])
5369
5370 (define_split
5371 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5372 (compare:CC
5373 (zero_extend:SI
5374 (subreg:HI
5375 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5376 (match_operand:SI 2 "const_int_operand" "")) 0))
5377 (const_int 0)))
5378 (clobber (match_scratch:SI 3 ""))]
5379 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5380 [(set (match_dup 3)
5381 (zero_extend:SI (subreg:HI
5382 (lshiftrt:SI (match_dup 1)
5383 (match_dup 2)) 0)))
5384 (set (match_dup 0)
5385 (compare:CC (match_dup 3)
5386 (const_int 0)))]
5387 "")
5388
5389 (define_insn ""
5390 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5391 (compare:CC
5392 (zero_extend:SI
5393 (subreg:HI
5394 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5395 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5396 (const_int 0)))
5397 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5398 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5399 "includes_rshift_p (operands[2], GEN_INT (65535))"
5400 "@
5401 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5402 #"
5403 [(set_attr "type" "delayed_compare")
5404 (set_attr "length" "4,8")])
5405
5406 (define_split
5407 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5408 (compare:CC
5409 (zero_extend:SI
5410 (subreg:HI
5411 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5412 (match_operand:SI 2 "const_int_operand" "")) 0))
5413 (const_int 0)))
5414 (set (match_operand:SI 0 "gpc_reg_operand" "")
5415 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5416 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5417 [(set (match_dup 0)
5418 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5419 (set (match_dup 3)
5420 (compare:CC (match_dup 0)
5421 (const_int 0)))]
5422 "")
5423
5424 (define_insn ""
5425 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5426 (const_int 1)
5427 (match_operand:SI 1 "gpc_reg_operand" "r"))
5428 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5429 (const_int 31)))]
5430 "TARGET_POWER"
5431 "rrib %0,%1,%2")
5432
5433 (define_insn ""
5434 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5435 (const_int 1)
5436 (match_operand:SI 1 "gpc_reg_operand" "r"))
5437 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5438 (const_int 31)))]
5439 "TARGET_POWER"
5440 "rrib %0,%1,%2")
5441
5442 (define_insn ""
5443 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5444 (const_int 1)
5445 (match_operand:SI 1 "gpc_reg_operand" "r"))
5446 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5447 (const_int 1)
5448 (const_int 0)))]
5449 "TARGET_POWER"
5450 "rrib %0,%1,%2")
5451
5452 (define_expand "ashrsi3"
5453 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5454 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5455 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5456 ""
5457 "
5458 {
5459 if (TARGET_POWER)
5460 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5461 else
5462 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5463 DONE;
5464 }")
5465
5466 (define_insn "ashrsi3_power"
5467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5468 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5469 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5470 (clobber (match_scratch:SI 3 "=q,X"))]
5471 "TARGET_POWER"
5472 "@
5473 srea %0,%1,%2
5474 {srai|srawi} %0,%1,%h2"
5475 [(set_attr "type" "shift")])
5476
5477 (define_insn "ashrsi3_no_power"
5478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5479 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5480 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5481 "! TARGET_POWER"
5482 "@
5483 {sra|sraw} %0,%1,%2
5484 {srai|srawi} %0,%1,%h2"
5485 [(set_attr "type" "var_shift_rotate,shift")])
5486
5487 (define_insn "*ashrsi3_64"
5488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5489 (sign_extend:DI
5490 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5491 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5492 "TARGET_POWERPC64"
5493 "@
5494 {sra|sraw} %0,%1,%2
5495 {srai|srawi} %0,%1,%h2"
5496 [(set_attr "type" "var_shift_rotate,shift")])
5497
5498 (define_insn ""
5499 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5500 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5501 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5502 (const_int 0)))
5503 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5504 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5505 "TARGET_POWER"
5506 "@
5507 srea. %3,%1,%2
5508 {srai.|srawi.} %3,%1,%h2
5509 #
5510 #"
5511 [(set_attr "type" "delayed_compare")
5512 (set_attr "length" "4,4,8,8")])
5513
5514 (define_split
5515 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5516 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5517 (match_operand:SI 2 "reg_or_cint_operand" ""))
5518 (const_int 0)))
5519 (clobber (match_scratch:SI 3 ""))
5520 (clobber (match_scratch:SI 4 ""))]
5521 "TARGET_POWER && reload_completed"
5522 [(parallel [(set (match_dup 3)
5523 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5524 (clobber (match_dup 4))])
5525 (set (match_dup 0)
5526 (compare:CC (match_dup 3)
5527 (const_int 0)))]
5528 "")
5529
5530 (define_insn ""
5531 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5532 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5533 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5534 (const_int 0)))
5535 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5536 "! TARGET_POWER"
5537 "@
5538 {sra.|sraw.} %3,%1,%2
5539 {srai.|srawi.} %3,%1,%h2
5540 #
5541 #"
5542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5543 (set_attr "length" "4,4,8,8")])
5544
5545 (define_split
5546 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5547 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5548 (match_operand:SI 2 "reg_or_cint_operand" ""))
5549 (const_int 0)))
5550 (clobber (match_scratch:SI 3 ""))]
5551 "! TARGET_POWER && reload_completed"
5552 [(set (match_dup 3)
5553 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5554 (set (match_dup 0)
5555 (compare:CC (match_dup 3)
5556 (const_int 0)))]
5557 "")
5558
5559 (define_insn ""
5560 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5561 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5562 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5563 (const_int 0)))
5564 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5565 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5566 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5567 "TARGET_POWER"
5568 "@
5569 srea. %0,%1,%2
5570 {srai.|srawi.} %0,%1,%h2
5571 #
5572 #"
5573 [(set_attr "type" "delayed_compare")
5574 (set_attr "length" "4,4,8,8")])
5575
5576 (define_split
5577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5578 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5579 (match_operand:SI 2 "reg_or_cint_operand" ""))
5580 (const_int 0)))
5581 (set (match_operand:SI 0 "gpc_reg_operand" "")
5582 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5583 (clobber (match_scratch:SI 4 ""))]
5584 "TARGET_POWER && reload_completed"
5585 [(parallel [(set (match_dup 0)
5586 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5587 (clobber (match_dup 4))])
5588 (set (match_dup 3)
5589 (compare:CC (match_dup 0)
5590 (const_int 0)))]
5591 "")
5592
5593 (define_insn ""
5594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5595 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5596 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5597 (const_int 0)))
5598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5599 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5600 "! TARGET_POWER"
5601 "@
5602 {sra.|sraw.} %0,%1,%2
5603 {srai.|srawi.} %0,%1,%h2
5604 #
5605 #"
5606 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5607 (set_attr "length" "4,4,8,8")])
5608 \f
5609 ;; Builtins to replace a division to generate FRE reciprocal estimate
5610 ;; instructions and the necessary fixup instructions
5611 (define_expand "recip<mode>3"
5612 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5613 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5614 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5615 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5616 {
5617 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5618 DONE;
5619 })
5620
5621 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5622 ;; hardware division. This is only done before register allocation and with
5623 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5624 (define_split
5625 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5626 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5627 (match_operand 2 "gpc_reg_operand" "")))]
5628 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5629 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5630 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5631 [(const_int 0)]
5632 {
5633 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5634 DONE;
5635 })
5636
5637 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5638 ;; appropriate fixup.
5639 (define_expand "rsqrt<mode>2"
5640 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5641 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5642 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5643 {
5644 rs6000_emit_swrsqrt (operands[0], operands[1]);
5645 DONE;
5646 })
5647 \f
5648 (define_split
5649 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5650 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5651 (match_operand:SI 2 "reg_or_cint_operand" ""))
5652 (const_int 0)))
5653 (set (match_operand:SI 0 "gpc_reg_operand" "")
5654 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5655 "! TARGET_POWER && reload_completed"
5656 [(set (match_dup 0)
5657 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5658 (set (match_dup 3)
5659 (compare:CC (match_dup 0)
5660 (const_int 0)))]
5661 "")
5662
5663 ;; Floating-point insns, excluding normal data motion.
5664 ;;
5665 ;; PowerPC has a full set of single-precision floating point instructions.
5666 ;;
5667 ;; For the POWER architecture, we pretend that we have both SFmode and
5668 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5669 ;; The only conversions we will do will be when storing to memory. In that
5670 ;; case, we will use the "frsp" instruction before storing.
5671 ;;
5672 ;; Note that when we store into a single-precision memory location, we need to
5673 ;; use the frsp insn first. If the register being stored isn't dead, we
5674 ;; need a scratch register for the frsp. But this is difficult when the store
5675 ;; is done by reload. It is not incorrect to do the frsp on the register in
5676 ;; this case, we just lose precision that we would have otherwise gotten but
5677 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5678
5679 (define_expand "extendsfdf2"
5680 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5681 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5682 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5683 "")
5684
5685 (define_insn_and_split "*extendsfdf2_fpr"
5686 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5687 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5688 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5689 "@
5690 #
5691 fmr %0,%1
5692 lfs%U1%X1 %0,%1"
5693 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5694 [(const_int 0)]
5695 {
5696 emit_note (NOTE_INSN_DELETED);
5697 DONE;
5698 }
5699 [(set_attr "type" "fp,fp,fpload")])
5700
5701 (define_expand "truncdfsf2"
5702 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5703 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5704 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5705 "")
5706
5707 (define_insn "*truncdfsf2_fpr"
5708 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5709 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5710 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5711 "frsp %0,%1"
5712 [(set_attr "type" "fp")])
5713
5714 (define_insn "aux_truncdfsf2"
5715 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5716 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5717 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5718 "frsp %0,%1"
5719 [(set_attr "type" "fp")])
5720
5721 (define_expand "negsf2"
5722 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5723 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5724 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5725 "")
5726
5727 (define_insn "*negsf2"
5728 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5729 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5730 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5731 "fneg %0,%1"
5732 [(set_attr "type" "fp")])
5733
5734 (define_expand "abssf2"
5735 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5736 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5737 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5738 "")
5739
5740 (define_insn "*abssf2"
5741 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5742 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5743 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5744 "fabs %0,%1"
5745 [(set_attr "type" "fp")])
5746
5747 (define_insn ""
5748 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5749 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5750 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5751 "fnabs %0,%1"
5752 [(set_attr "type" "fp")])
5753
5754 (define_expand "addsf3"
5755 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5756 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5757 (match_operand:SF 2 "gpc_reg_operand" "")))]
5758 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5759 "")
5760
5761 (define_insn ""
5762 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5763 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5764 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5765 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5766 "fadds %0,%1,%2"
5767 [(set_attr "type" "fp")
5768 (set_attr "fp_type" "fp_addsub_s")])
5769
5770 (define_insn ""
5771 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5772 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5773 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5774 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5775 "{fa|fadd} %0,%1,%2"
5776 [(set_attr "type" "fp")])
5777
5778 (define_expand "subsf3"
5779 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5780 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5781 (match_operand:SF 2 "gpc_reg_operand" "")))]
5782 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5783 "")
5784
5785 (define_insn ""
5786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5787 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5788 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5789 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5790 "fsubs %0,%1,%2"
5791 [(set_attr "type" "fp")
5792 (set_attr "fp_type" "fp_addsub_s")])
5793
5794 (define_insn ""
5795 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5796 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5797 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5798 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5799 "{fs|fsub} %0,%1,%2"
5800 [(set_attr "type" "fp")])
5801
5802 (define_expand "mulsf3"
5803 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5804 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5805 (match_operand:SF 2 "gpc_reg_operand" "")))]
5806 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5807 "")
5808
5809 (define_insn ""
5810 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5811 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5812 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5813 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5814 "fmuls %0,%1,%2"
5815 [(set_attr "type" "fp")
5816 (set_attr "fp_type" "fp_mul_s")])
5817
5818 (define_insn ""
5819 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5820 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5821 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5822 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5823 "{fm|fmul} %0,%1,%2"
5824 [(set_attr "type" "dmul")])
5825
5826 (define_expand "divsf3"
5827 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5828 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5829 (match_operand:SF 2 "gpc_reg_operand" "")))]
5830 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5831 "")
5832
5833 (define_insn ""
5834 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5835 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5836 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5837 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5838 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5839 "fdivs %0,%1,%2"
5840 [(set_attr "type" "sdiv")])
5841
5842 (define_insn ""
5843 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5844 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5845 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5846 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5847 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5848 "{fd|fdiv} %0,%1,%2"
5849 [(set_attr "type" "ddiv")])
5850
5851 (define_insn "fres"
5852 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5853 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5854 "TARGET_FRES"
5855 "fres %0,%1"
5856 [(set_attr "type" "fp")])
5857
5858 ; builtin fmaf support
5859 (define_insn "*fmasf4_fpr"
5860 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5861 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5862 (match_operand:SF 2 "gpc_reg_operand" "f")
5863 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5864 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5865 {
5866 return (TARGET_POWERPC
5867 ? "fmadds %0,%1,%2,%3"
5868 : "{fma|fmadd} %0,%1,%2,%3");
5869 }
5870 [(set_attr "type" "fp")
5871 (set_attr "fp_type" "fp_maddsub_s")])
5872
5873 (define_insn "*fmssf4_fpr"
5874 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5875 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5876 (match_operand:SF 2 "gpc_reg_operand" "f")
5877 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5878 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5879 {
5880 return (TARGET_POWERPC
5881 ? "fmsubs %0,%1,%2,%3"
5882 : "{fms|fmsub} %0,%1,%2,%3");
5883 }
5884 [(set_attr "type" "fp")
5885 (set_attr "fp_type" "fp_maddsub_s")])
5886
5887 (define_insn "*nfmasf4_fpr"
5888 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5889 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5890 (match_operand:SF 2 "gpc_reg_operand" "f")
5891 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5892 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5893 {
5894 return (TARGET_POWERPC
5895 ? "fnmadds %0,%1,%2,%3"
5896 : "{fnma|fnmadd} %0,%1,%2,%3");
5897 }
5898 [(set_attr "type" "fp")
5899 (set_attr "fp_type" "fp_maddsub_s")])
5900
5901 (define_insn "*nfmssf4_fpr"
5902 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5903 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5904 (match_operand:SF 2 "gpc_reg_operand" "f")
5905 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5906 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5907 {
5908 return (TARGET_POWERPC
5909 ? "fnmsubs %0,%1,%2,%3"
5910 : "{fnms|fnmsub} %0,%1,%2,%3");
5911 }
5912 [(set_attr "type" "fp")
5913 (set_attr "fp_type" "fp_maddsub_s")])
5914
5915 (define_expand "sqrtsf2"
5916 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5917 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5918 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5919 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5920 && !TARGET_SIMPLE_FPU"
5921 "")
5922
5923 (define_insn ""
5924 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5925 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5926 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5927 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5928 "fsqrts %0,%1"
5929 [(set_attr "type" "ssqrt")])
5930
5931 (define_insn ""
5932 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5933 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5934 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5935 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5936 "fsqrt %0,%1"
5937 [(set_attr "type" "dsqrt")])
5938
5939 (define_insn "*rsqrtsf_internal1"
5940 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5941 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5942 UNSPEC_RSQRT))]
5943 "TARGET_FRSQRTES"
5944 "frsqrtes %0,%1"
5945 [(set_attr "type" "fp")])
5946
5947 (define_expand "copysign<mode>3"
5948 [(set (match_dup 3)
5949 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5950 (set (match_dup 4)
5951 (neg:SFDF (abs:SFDF (match_dup 1))))
5952 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5953 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5954 (match_dup 5))
5955 (match_dup 3)
5956 (match_dup 4)))]
5957 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5958 && ((TARGET_PPC_GFXOPT
5959 && !HONOR_NANS (<MODE>mode)
5960 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5961 || TARGET_CMPB
5962 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5963 {
5964 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5965 {
5966 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5967 operands[2]));
5968 DONE;
5969 }
5970
5971 operands[3] = gen_reg_rtx (<MODE>mode);
5972 operands[4] = gen_reg_rtx (<MODE>mode);
5973 operands[5] = CONST0_RTX (<MODE>mode);
5974 })
5975
5976 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5977 ;; compiler from optimizing -0.0
5978 (define_insn "copysign<mode>3_fcpsgn"
5979 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5980 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
5981 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
5982 UNSPEC_COPYSIGN))]
5983 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5984 "fcpsgn %0,%2,%1"
5985 [(set_attr "type" "fp")])
5986
5987 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5988 ;; fsel instruction and some auxiliary computations. Then we just have a
5989 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5990 ;; combine.
5991 (define_expand "smaxsf3"
5992 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5993 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5994 (match_operand:SF 2 "gpc_reg_operand" ""))
5995 (match_dup 1)
5996 (match_dup 2)))]
5997 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5998 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5999 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6000
6001 (define_expand "sminsf3"
6002 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6003 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6004 (match_operand:SF 2 "gpc_reg_operand" ""))
6005 (match_dup 2)
6006 (match_dup 1)))]
6007 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6008 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6009 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6010
6011 (define_split
6012 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6013 (match_operator:SF 3 "min_max_operator"
6014 [(match_operand:SF 1 "gpc_reg_operand" "")
6015 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6016 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6017 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6018 [(const_int 0)]
6019 "
6020 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6021 operands[1], operands[2]);
6022 DONE;
6023 }")
6024
6025 (define_expand "mov<mode>cc"
6026 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6027 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6028 (match_operand:GPR 2 "gpc_reg_operand" "")
6029 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6030 "TARGET_ISEL<sel>"
6031 "
6032 {
6033 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6034 DONE;
6035 else
6036 FAIL;
6037 }")
6038
6039 ;; We use the BASE_REGS for the isel input operands because, if rA is
6040 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6041 ;; because we may switch the operands and rB may end up being rA.
6042 ;;
6043 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6044 ;; leave out the mode in operand 4 and use one pattern, but reload can
6045 ;; change the mode underneath our feet and then gets confused trying
6046 ;; to reload the value.
6047 (define_insn "isel_signed_<mode>"
6048 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6049 (if_then_else:GPR
6050 (match_operator 1 "scc_comparison_operator"
6051 [(match_operand:CC 4 "cc_reg_operand" "y,y")
6052 (const_int 0)])
6053 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6054 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6055 "TARGET_ISEL<sel>"
6056 "*
6057 { return output_isel (operands); }"
6058 [(set_attr "type" "isel")
6059 (set_attr "length" "4")])
6060
6061 (define_insn "isel_unsigned_<mode>"
6062 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6063 (if_then_else:GPR
6064 (match_operator 1 "scc_comparison_operator"
6065 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
6066 (const_int 0)])
6067 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6068 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6069 "TARGET_ISEL<sel>"
6070 "*
6071 { return output_isel (operands); }"
6072 [(set_attr "type" "isel")
6073 (set_attr "length" "4")])
6074
6075 ;; These patterns can be useful for combine; they let combine know that
6076 ;; isel can handle reversed comparisons so long as the operands are
6077 ;; registers.
6078
6079 (define_insn "*isel_reversed_signed_<mode>"
6080 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6081 (if_then_else:GPR
6082 (match_operator 1 "scc_rev_comparison_operator"
6083 [(match_operand:CC 4 "cc_reg_operand" "y")
6084 (const_int 0)])
6085 (match_operand:GPR 2 "gpc_reg_operand" "b")
6086 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6087 "TARGET_ISEL<sel>"
6088 "*
6089 { return output_isel (operands); }"
6090 [(set_attr "type" "isel")
6091 (set_attr "length" "4")])
6092
6093 (define_insn "*isel_reversed_unsigned_<mode>"
6094 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6095 (if_then_else:GPR
6096 (match_operator 1 "scc_rev_comparison_operator"
6097 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6098 (const_int 0)])
6099 (match_operand:GPR 2 "gpc_reg_operand" "b")
6100 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6101 "TARGET_ISEL<sel>"
6102 "*
6103 { return output_isel (operands); }"
6104 [(set_attr "type" "isel")
6105 (set_attr "length" "4")])
6106
6107 (define_expand "movsfcc"
6108 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6109 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6110 (match_operand:SF 2 "gpc_reg_operand" "")
6111 (match_operand:SF 3 "gpc_reg_operand" "")))]
6112 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6113 "
6114 {
6115 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6116 DONE;
6117 else
6118 FAIL;
6119 }")
6120
6121 (define_insn "*fselsfsf4"
6122 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6123 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6124 (match_operand:SF 4 "zero_fp_constant" "F"))
6125 (match_operand:SF 2 "gpc_reg_operand" "f")
6126 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6127 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6128 "fsel %0,%1,%2,%3"
6129 [(set_attr "type" "fp")])
6130
6131 (define_insn "*fseldfsf4"
6132 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6133 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6134 (match_operand:DF 4 "zero_fp_constant" "F"))
6135 (match_operand:SF 2 "gpc_reg_operand" "f")
6136 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6137 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6138 "fsel %0,%1,%2,%3"
6139 [(set_attr "type" "fp")])
6140
6141 (define_expand "negdf2"
6142 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6143 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6144 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6145 "")
6146
6147 (define_insn "*negdf2_fpr"
6148 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6149 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6150 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6151 && !VECTOR_UNIT_VSX_P (DFmode)"
6152 "fneg %0,%1"
6153 [(set_attr "type" "fp")])
6154
6155 (define_expand "absdf2"
6156 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6157 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6158 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6159 "")
6160
6161 (define_insn "*absdf2_fpr"
6162 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6163 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6164 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6165 && !VECTOR_UNIT_VSX_P (DFmode)"
6166 "fabs %0,%1"
6167 [(set_attr "type" "fp")])
6168
6169 (define_insn "*nabsdf2_fpr"
6170 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6171 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6172 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6173 && !VECTOR_UNIT_VSX_P (DFmode)"
6174 "fnabs %0,%1"
6175 [(set_attr "type" "fp")])
6176
6177 (define_expand "adddf3"
6178 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6179 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6180 (match_operand:DF 2 "gpc_reg_operand" "")))]
6181 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6182 "")
6183
6184 (define_insn "*adddf3_fpr"
6185 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6186 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6187 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6188 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6189 && !VECTOR_UNIT_VSX_P (DFmode)"
6190 "{fa|fadd} %0,%1,%2"
6191 [(set_attr "type" "fp")
6192 (set_attr "fp_type" "fp_addsub_d")])
6193
6194 (define_expand "subdf3"
6195 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6196 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6197 (match_operand:DF 2 "gpc_reg_operand" "")))]
6198 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6199 "")
6200
6201 (define_insn "*subdf3_fpr"
6202 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6203 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6204 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6205 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6206 && !VECTOR_UNIT_VSX_P (DFmode)"
6207 "{fs|fsub} %0,%1,%2"
6208 [(set_attr "type" "fp")
6209 (set_attr "fp_type" "fp_addsub_d")])
6210
6211 (define_expand "muldf3"
6212 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6213 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6214 (match_operand:DF 2 "gpc_reg_operand" "")))]
6215 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6216 "")
6217
6218 (define_insn "*muldf3_fpr"
6219 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6220 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6221 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6222 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6223 && !VECTOR_UNIT_VSX_P (DFmode)"
6224 "{fm|fmul} %0,%1,%2"
6225 [(set_attr "type" "dmul")
6226 (set_attr "fp_type" "fp_mul_d")])
6227
6228 (define_expand "divdf3"
6229 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6230 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6231 (match_operand:DF 2 "gpc_reg_operand" "")))]
6232 "TARGET_HARD_FLOAT
6233 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6234 && !TARGET_SIMPLE_FPU"
6235 "")
6236
6237 (define_insn "*divdf3_fpr"
6238 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6239 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6240 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6241 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6242 && !VECTOR_UNIT_VSX_P (DFmode)"
6243 "{fd|fdiv} %0,%1,%2"
6244 [(set_attr "type" "ddiv")])
6245
6246 (define_insn "*fred_fpr"
6247 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6248 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6249 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6250 "fre %0,%1"
6251 [(set_attr "type" "fp")])
6252
6253 (define_insn "*rsqrtdf_internal1"
6254 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6255 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6256 UNSPEC_RSQRT))]
6257 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6258 "frsqrte %0,%1"
6259 [(set_attr "type" "fp")])
6260
6261 ; builtin fma support
6262 (define_insn "*fmadf4_fpr"
6263 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6264 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6265 (match_operand:DF 2 "gpc_reg_operand" "f")
6266 (match_operand:DF 3 "gpc_reg_operand" "f")))]
6267 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6268 && VECTOR_UNIT_NONE_P (DFmode)"
6269 "{fma|fmadd} %0,%1,%2,%3"
6270 [(set_attr "type" "fp")
6271 (set_attr "fp_type" "fp_maddsub_s")])
6272
6273 (define_insn "*fmsdf4_fpr"
6274 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6275 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6276 (match_operand:DF 2 "gpc_reg_operand" "f")
6277 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6278 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6279 && VECTOR_UNIT_NONE_P (DFmode)"
6280 "{fms|fmsub} %0,%1,%2,%3"
6281 [(set_attr "type" "fp")
6282 (set_attr "fp_type" "fp_maddsub_s")])
6283
6284 (define_insn "*nfmadf4_fpr"
6285 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6286 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6287 (match_operand:DF 2 "gpc_reg_operand" "f")
6288 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6289 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6290 && VECTOR_UNIT_NONE_P (DFmode)"
6291 "{fnma|fnmadd} %0,%1,%2,%3"
6292 [(set_attr "type" "fp")
6293 (set_attr "fp_type" "fp_maddsub_s")])
6294
6295 (define_insn "*nfmsdf4_fpr"
6296 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6297 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6298 (match_operand:DF 2 "gpc_reg_operand" "f")
6299 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
6300 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6301 && VECTOR_UNIT_NONE_P (DFmode)"
6302 "{fnms|fnmsub} %0,%1,%2,%3"
6303 [(set_attr "type" "fp")
6304 (set_attr "fp_type" "fp_maddsub_s")])
6305
6306 (define_expand "sqrtdf2"
6307 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6308 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6309 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6310 && TARGET_DOUBLE_FLOAT"
6311 "")
6312
6313 (define_insn "*sqrtdf2_fpr"
6314 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6315 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6316 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6317 && TARGET_DOUBLE_FLOAT
6318 && !VECTOR_UNIT_VSX_P (DFmode)"
6319 "fsqrt %0,%1"
6320 [(set_attr "type" "dsqrt")])
6321
6322 ;; The conditional move instructions allow us to perform max and min
6323 ;; operations even when
6324
6325 (define_expand "smaxdf3"
6326 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6327 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6328 (match_operand:DF 2 "gpc_reg_operand" ""))
6329 (match_dup 1)
6330 (match_dup 2)))]
6331 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6332 && !flag_trapping_math"
6333 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6334
6335 (define_expand "smindf3"
6336 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6337 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6338 (match_operand:DF 2 "gpc_reg_operand" ""))
6339 (match_dup 2)
6340 (match_dup 1)))]
6341 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6342 && !flag_trapping_math"
6343 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6344
6345 (define_split
6346 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6347 (match_operator:DF 3 "min_max_operator"
6348 [(match_operand:DF 1 "gpc_reg_operand" "")
6349 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6350 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6351 && !flag_trapping_math"
6352 [(const_int 0)]
6353 "
6354 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6355 operands[1], operands[2]);
6356 DONE;
6357 }")
6358
6359 (define_expand "movdfcc"
6360 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6361 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6362 (match_operand:DF 2 "gpc_reg_operand" "")
6363 (match_operand:DF 3 "gpc_reg_operand" "")))]
6364 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6365 "
6366 {
6367 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6368 DONE;
6369 else
6370 FAIL;
6371 }")
6372
6373 (define_insn "*fseldfdf4"
6374 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6375 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6376 (match_operand:DF 4 "zero_fp_constant" "F"))
6377 (match_operand:DF 2 "gpc_reg_operand" "d")
6378 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6379 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6380 "fsel %0,%1,%2,%3"
6381 [(set_attr "type" "fp")])
6382
6383 (define_insn "*fselsfdf4"
6384 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6385 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6386 (match_operand:SF 4 "zero_fp_constant" "F"))
6387 (match_operand:DF 2 "gpc_reg_operand" "d")
6388 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6389 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6390 "fsel %0,%1,%2,%3"
6391 [(set_attr "type" "fp")])
6392 \f
6393 ;; Conversions to and from floating-point.
6394
6395 ; We don't define lfiwax/lfiwzx with the normal definition, because we
6396 ; don't want to support putting SImode in FPR registers.
6397 (define_insn "lfiwax"
6398 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6399 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6400 UNSPEC_LFIWAX))]
6401 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
6402 "lfiwax %0,%y1"
6403 [(set_attr "type" "fpload")])
6404
6405 ; This split must be run before register allocation because it allocates the
6406 ; memory slot that is needed to move values to/from the FPR. We don't allocate
6407 ; it earlier to allow for the combiner to merge insns together where it might
6408 ; not be needed and also in case the insns are deleted as dead code.
6409
6410 (define_insn_and_split "floatsi<mode>2_lfiwax"
6411 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6412 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6413 (clobber (match_scratch:DI 2 "=d"))]
6414 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6415 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
6416 "#"
6417 ""
6418 [(pc)]
6419 "
6420 {
6421 rtx dest = operands[0];
6422 rtx src = operands[1];
6423 rtx tmp;
6424
6425 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6426 tmp = convert_to_mode (DImode, src, false);
6427 else
6428 {
6429 tmp = operands[2];
6430 if (GET_CODE (tmp) == SCRATCH)
6431 tmp = gen_reg_rtx (DImode);
6432 if (MEM_P (src))
6433 {
6434 src = rs6000_address_for_fpconvert (src);
6435 emit_insn (gen_lfiwax (tmp, src));
6436 }
6437 else
6438 {
6439 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6440 emit_move_insn (stack, src);
6441 emit_insn (gen_lfiwax (tmp, stack));
6442 }
6443 }
6444 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6445 DONE;
6446 }"
6447 [(set_attr "length" "12")
6448 (set_attr "type" "fpload")])
6449
6450 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
6451 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6452 (float:SFDF
6453 (sign_extend:DI
6454 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6455 (clobber (match_scratch:DI 2 "=0,d"))]
6456 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6457 && <SI_CONVERT_FP>"
6458 "#"
6459 ""
6460 [(pc)]
6461 "
6462 {
6463 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6464 if (GET_CODE (operands[2]) == SCRATCH)
6465 operands[2] = gen_reg_rtx (DImode);
6466 emit_insn (gen_lfiwax (operands[2], operands[1]));
6467 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6468 DONE;
6469 }"
6470 [(set_attr "length" "8")
6471 (set_attr "type" "fpload")])
6472
6473 (define_insn "lfiwzx"
6474 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6475 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6476 UNSPEC_LFIWZX))]
6477 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
6478 "lfiwzx %0,%y1"
6479 [(set_attr "type" "fpload")])
6480
6481 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
6482 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6483 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6484 (clobber (match_scratch:DI 2 "=d"))]
6485 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6486 && <SI_CONVERT_FP>"
6487 "#"
6488 ""
6489 [(pc)]
6490 "
6491 {
6492 rtx dest = operands[0];
6493 rtx src = operands[1];
6494 rtx tmp;
6495
6496 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6497 tmp = convert_to_mode (DImode, src, true);
6498 else
6499 {
6500 tmp = operands[2];
6501 if (GET_CODE (tmp) == SCRATCH)
6502 tmp = gen_reg_rtx (DImode);
6503 if (MEM_P (src))
6504 {
6505 src = rs6000_address_for_fpconvert (src);
6506 emit_insn (gen_lfiwzx (tmp, src));
6507 }
6508 else
6509 {
6510 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6511 emit_move_insn (stack, src);
6512 emit_insn (gen_lfiwzx (tmp, stack));
6513 }
6514 }
6515 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6516 DONE;
6517 }"
6518 [(set_attr "length" "12")
6519 (set_attr "type" "fpload")])
6520
6521 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
6522 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6523 (unsigned_float:SFDF
6524 (zero_extend:DI
6525 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6526 (clobber (match_scratch:DI 2 "=0,d"))]
6527 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6528 && <SI_CONVERT_FP>"
6529 "#"
6530 ""
6531 [(pc)]
6532 "
6533 {
6534 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6535 if (GET_CODE (operands[2]) == SCRATCH)
6536 operands[2] = gen_reg_rtx (DImode);
6537 emit_insn (gen_lfiwzx (operands[2], operands[1]));
6538 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6539 DONE;
6540 }"
6541 [(set_attr "length" "8")
6542 (set_attr "type" "fpload")])
6543
6544 ; For each of these conversions, there is a define_expand, a define_insn
6545 ; with a '#' template, and a define_split (with C code). The idea is
6546 ; to allow constant folding with the template of the define_insn,
6547 ; then to have the insns split later (between sched1 and final).
6548
6549 (define_expand "floatsidf2"
6550 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6551 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6552 (use (match_dup 2))
6553 (use (match_dup 3))
6554 (clobber (match_dup 4))
6555 (clobber (match_dup 5))
6556 (clobber (match_dup 6))])]
6557 "TARGET_HARD_FLOAT
6558 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6559 "
6560 {
6561 if (TARGET_E500_DOUBLE)
6562 {
6563 if (!REG_P (operands[1]))
6564 operands[1] = force_reg (SImode, operands[1]);
6565 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6566 DONE;
6567 }
6568 else if (TARGET_LFIWAX && TARGET_FCFID)
6569 {
6570 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
6571 DONE;
6572 }
6573 else if (TARGET_FCFID)
6574 {
6575 rtx dreg = operands[1];
6576 if (!REG_P (dreg))
6577 dreg = force_reg (SImode, dreg);
6578 dreg = convert_to_mode (DImode, dreg, false);
6579 emit_insn (gen_floatdidf2 (operands[0], dreg));
6580 DONE;
6581 }
6582
6583 if (!REG_P (operands[1]))
6584 operands[1] = force_reg (SImode, operands[1]);
6585 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6586 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6587 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6588 operands[5] = gen_reg_rtx (DFmode);
6589 operands[6] = gen_reg_rtx (SImode);
6590 }")
6591
6592 (define_insn_and_split "*floatsidf2_internal"
6593 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6594 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6595 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6596 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6597 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6598 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6599 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6600 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6601 "#"
6602 ""
6603 [(pc)]
6604 "
6605 {
6606 rtx lowword, highword;
6607 gcc_assert (MEM_P (operands[4]));
6608 highword = adjust_address (operands[4], SImode, 0);
6609 lowword = adjust_address (operands[4], SImode, 4);
6610 if (! WORDS_BIG_ENDIAN)
6611 {
6612 rtx tmp;
6613 tmp = highword; highword = lowword; lowword = tmp;
6614 }
6615
6616 emit_insn (gen_xorsi3 (operands[6], operands[1],
6617 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6618 emit_move_insn (lowword, operands[6]);
6619 emit_move_insn (highword, operands[2]);
6620 emit_move_insn (operands[5], operands[4]);
6621 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6622 DONE;
6623 }"
6624 [(set_attr "length" "24")
6625 (set_attr "type" "fp")])
6626
6627 ;; If we don't have a direct conversion to single precision, don't enable this
6628 ;; conversion for 32-bit without fast math, because we don't have the insn to
6629 ;; generate the fixup swizzle to avoid double rounding problems.
6630 (define_expand "floatunssisf2"
6631 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6632 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6633 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6634 && (!TARGET_FPRS
6635 || (TARGET_FPRS
6636 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6637 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6638 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6639 "
6640 {
6641 if (!TARGET_FPRS)
6642 {
6643 if (!REG_P (operands[1]))
6644 operands[1] = force_reg (SImode, operands[1]);
6645 }
6646 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
6647 {
6648 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
6649 DONE;
6650 }
6651 else
6652 {
6653 rtx dreg = operands[1];
6654 if (!REG_P (dreg))
6655 dreg = force_reg (SImode, dreg);
6656 dreg = convert_to_mode (DImode, dreg, true);
6657 emit_insn (gen_floatdisf2 (operands[0], dreg));
6658 DONE;
6659 }
6660 }")
6661
6662 (define_expand "floatunssidf2"
6663 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6664 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6665 (use (match_dup 2))
6666 (use (match_dup 3))
6667 (clobber (match_dup 4))
6668 (clobber (match_dup 5))])]
6669 "TARGET_HARD_FLOAT
6670 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6671 "
6672 {
6673 if (TARGET_E500_DOUBLE)
6674 {
6675 if (!REG_P (operands[1]))
6676 operands[1] = force_reg (SImode, operands[1]);
6677 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6678 DONE;
6679 }
6680 else if (TARGET_LFIWZX && TARGET_FCFID)
6681 {
6682 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
6683 DONE;
6684 }
6685 else if (TARGET_FCFID)
6686 {
6687 rtx dreg = operands[1];
6688 if (!REG_P (dreg))
6689 dreg = force_reg (SImode, dreg);
6690 dreg = convert_to_mode (DImode, dreg, true);
6691 emit_insn (gen_floatdidf2 (operands[0], dreg));
6692 DONE;
6693 }
6694
6695 if (!REG_P (operands[1]))
6696 operands[1] = force_reg (SImode, operands[1]);
6697 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6698 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6699 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6700 operands[5] = gen_reg_rtx (DFmode);
6701 }")
6702
6703 (define_insn_and_split "*floatunssidf2_internal"
6704 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6705 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6706 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6707 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6708 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6709 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6710 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6711 && !(TARGET_FCFID && TARGET_POWERPC64)"
6712 "#"
6713 ""
6714 [(pc)]
6715 "
6716 {
6717 rtx lowword, highword;
6718 gcc_assert (MEM_P (operands[4]));
6719 highword = adjust_address (operands[4], SImode, 0);
6720 lowword = adjust_address (operands[4], SImode, 4);
6721 if (! WORDS_BIG_ENDIAN)
6722 {
6723 rtx tmp;
6724 tmp = highword; highword = lowword; lowword = tmp;
6725 }
6726
6727 emit_move_insn (lowword, operands[1]);
6728 emit_move_insn (highword, operands[2]);
6729 emit_move_insn (operands[5], operands[4]);
6730 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6731 DONE;
6732 }"
6733 [(set_attr "length" "20")
6734 (set_attr "type" "fp")])
6735
6736 (define_expand "fix_trunc<mode>si2"
6737 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6738 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6739 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
6740 && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
6741 "
6742 {
6743 if (!<E500_CONVERT>)
6744 {
6745 rtx tmp, stack;
6746
6747 if (TARGET_STFIWX)
6748 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6749 else
6750 {
6751 tmp = gen_reg_rtx (DImode);
6752 stack = rs6000_allocate_stack_temp (DImode, true, false);
6753 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6754 tmp, stack));
6755 }
6756 DONE;
6757 }
6758 }")
6759
6760 ; Like the convert to float patterns, this insn must be split before
6761 ; register allocation so that it can allocate the memory slot if it
6762 ; needed
6763 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6764 [(set (match_operand:SI 0 "general_operand" "=rm")
6765 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6766 (clobber (match_scratch:DI 2 "=d"))]
6767 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6768 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6769 && TARGET_STFIWX && can_create_pseudo_p ()"
6770 "#"
6771 ""
6772 [(pc)]
6773 {
6774 rtx dest = operands[0];
6775 rtx src = operands[1];
6776 rtx tmp = operands[2];
6777
6778 if (GET_CODE (tmp) == SCRATCH)
6779 tmp = gen_reg_rtx (DImode);
6780
6781 emit_insn (gen_fctiwz_<mode> (tmp, src));
6782 if (MEM_P (dest))
6783 {
6784 dest = rs6000_address_for_fpconvert (dest);
6785 emit_insn (gen_stfiwx (dest, tmp));
6786 DONE;
6787 }
6788 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6789 {
6790 dest = gen_lowpart (DImode, dest);
6791 emit_move_insn (dest, tmp);
6792 DONE;
6793 }
6794 else
6795 {
6796 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6797 emit_insn (gen_stfiwx (stack, tmp));
6798 emit_move_insn (dest, stack);
6799 DONE;
6800 }
6801 }
6802 [(set_attr "length" "12")
6803 (set_attr "type" "fp")])
6804
6805 (define_insn_and_split "fix_trunc<mode>si2_internal"
6806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6807 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6808 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6809 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6810 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6811 && TARGET_DOUBLE_FLOAT"
6812 "#"
6813 ""
6814 [(pc)]
6815 "
6816 {
6817 rtx lowword;
6818 gcc_assert (MEM_P (operands[3]));
6819 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6820
6821 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6822 emit_move_insn (operands[3], operands[2]);
6823 emit_move_insn (operands[0], lowword);
6824 DONE;
6825 }"
6826 [(set_attr "length" "16")
6827 (set_attr "type" "fp")])
6828
6829 (define_expand "fix_trunc<mode>di2"
6830 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6831 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6832 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6833 && TARGET_FCFID"
6834 "")
6835
6836 (define_insn "*fix_trunc<mode>di2_fctidz"
6837 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6838 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6839 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6840 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6841 "fctidz %0,%1"
6842 [(set_attr "type" "fp")])
6843
6844 (define_expand "fixuns_trunc<mode>si2"
6845 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6846 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6847 "TARGET_HARD_FLOAT
6848 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6849 || <E500_CONVERT>)"
6850 "
6851 {
6852 if (!<E500_CONVERT>)
6853 {
6854 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6855 DONE;
6856 }
6857 }")
6858
6859 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6860 [(set (match_operand:SI 0 "general_operand" "=rm")
6861 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6862 (clobber (match_scratch:DI 2 "=d"))]
6863 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6864 && TARGET_STFIWX && can_create_pseudo_p ()"
6865 "#"
6866 ""
6867 [(pc)]
6868 {
6869 rtx dest = operands[0];
6870 rtx src = operands[1];
6871 rtx tmp = operands[2];
6872
6873 if (GET_CODE (tmp) == SCRATCH)
6874 tmp = gen_reg_rtx (DImode);
6875
6876 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6877 if (MEM_P (dest))
6878 {
6879 dest = rs6000_address_for_fpconvert (dest);
6880 emit_insn (gen_stfiwx (dest, tmp));
6881 DONE;
6882 }
6883 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6884 {
6885 dest = gen_lowpart (DImode, dest);
6886 emit_move_insn (dest, tmp);
6887 DONE;
6888 }
6889 else
6890 {
6891 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6892 emit_insn (gen_stfiwx (stack, tmp));
6893 emit_move_insn (dest, stack);
6894 DONE;
6895 }
6896 }
6897 [(set_attr "length" "12")
6898 (set_attr "type" "fp")])
6899
6900 (define_expand "fixuns_trunc<mode>di2"
6901 [(set (match_operand:DI 0 "register_operand" "")
6902 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6903 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6904 "")
6905
6906 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6907 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6908 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6909 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6910 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6911 "fctiduz %0,%1"
6912 [(set_attr "type" "fp")])
6913
6914 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6915 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6916 ; because the first makes it clear that operand 0 is not live
6917 ; before the instruction.
6918 (define_insn "fctiwz_<mode>"
6919 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6920 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6921 UNSPEC_FCTIWZ))]
6922 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6923 && TARGET_DOUBLE_FLOAT"
6924 "{fcirz|fctiwz} %0,%1"
6925 [(set_attr "type" "fp")])
6926
6927 (define_insn "fctiwuz_<mode>"
6928 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6929 (unspec:DI [(unsigned_fix:SI
6930 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6931 UNSPEC_FCTIWUZ))]
6932 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6933 "fctiwuz %0,%1"
6934 [(set_attr "type" "fp")])
6935
6936 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6937 ;; since the friz instruction does not truncate the value if the floating
6938 ;; point value is < LONG_MIN or > LONG_MAX.
6939 (define_insn "*friz"
6940 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6941 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6942 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6943 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6944 && !flag_trapping_math && TARGET_FRIZ"
6945 "friz %0,%1"
6946 [(set_attr "type" "fp")])
6947
6948 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6949 ;; load to properly sign extend the value, but at least doing a store, load
6950 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6951 ;; if we have 32-bit memory ops
6952 (define_insn_and_split "*round32<mode>2_fprs"
6953 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6954 (float:SFDF
6955 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6956 (clobber (match_scratch:DI 2 "=d"))
6957 (clobber (match_scratch:DI 3 "=d"))]
6958 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6959 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6960 && can_create_pseudo_p ()"
6961 "#"
6962 ""
6963 [(pc)]
6964 {
6965 rtx dest = operands[0];
6966 rtx src = operands[1];
6967 rtx tmp1 = operands[2];
6968 rtx tmp2 = operands[3];
6969 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6970
6971 if (GET_CODE (tmp1) == SCRATCH)
6972 tmp1 = gen_reg_rtx (DImode);
6973 if (GET_CODE (tmp2) == SCRATCH)
6974 tmp2 = gen_reg_rtx (DImode);
6975
6976 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6977 emit_insn (gen_stfiwx (stack, tmp1));
6978 emit_insn (gen_lfiwax (tmp2, stack));
6979 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6980 DONE;
6981 }
6982 [(set_attr "type" "fpload")
6983 (set_attr "length" "16")])
6984
6985 (define_insn_and_split "*roundu32<mode>2_fprs"
6986 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6987 (unsigned_float:SFDF
6988 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6989 (clobber (match_scratch:DI 2 "=d"))
6990 (clobber (match_scratch:DI 3 "=d"))]
6991 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6992 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6993 && can_create_pseudo_p ()"
6994 "#"
6995 ""
6996 [(pc)]
6997 {
6998 rtx dest = operands[0];
6999 rtx src = operands[1];
7000 rtx tmp1 = operands[2];
7001 rtx tmp2 = operands[3];
7002 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
7003
7004 if (GET_CODE (tmp1) == SCRATCH)
7005 tmp1 = gen_reg_rtx (DImode);
7006 if (GET_CODE (tmp2) == SCRATCH)
7007 tmp2 = gen_reg_rtx (DImode);
7008
7009 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
7010 emit_insn (gen_stfiwx (stack, tmp1));
7011 emit_insn (gen_lfiwzx (tmp2, stack));
7012 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7013 DONE;
7014 }
7015 [(set_attr "type" "fpload")
7016 (set_attr "length" "16")])
7017
7018 ;; No VSX equivalent to fctid
7019 (define_insn "lrint<mode>di2"
7020 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
7021 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7022 UNSPEC_FCTID))]
7023 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7024 "fctid %0,%1"
7025 [(set_attr "type" "fp")])
7026
7027 (define_expand "btrunc<mode>2"
7028 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7029 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7030 UNSPEC_FRIZ))]
7031 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7032 "")
7033
7034 (define_insn "*btrunc<mode>2_fpr"
7035 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7036 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7037 UNSPEC_FRIZ))]
7038 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7039 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7040 "friz %0,%1"
7041 [(set_attr "type" "fp")])
7042
7043 (define_expand "ceil<mode>2"
7044 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7045 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7046 UNSPEC_FRIP))]
7047 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7048 "")
7049
7050 (define_insn "*ceil<mode>2_fpr"
7051 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7052 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7053 UNSPEC_FRIP))]
7054 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7055 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7056 "frip %0,%1"
7057 [(set_attr "type" "fp")])
7058
7059 (define_expand "floor<mode>2"
7060 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7061 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7062 UNSPEC_FRIM))]
7063 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7064 "")
7065
7066 (define_insn "*floor<mode>2_fpr"
7067 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7068 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7069 UNSPEC_FRIM))]
7070 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7071 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7072 "frim %0,%1"
7073 [(set_attr "type" "fp")])
7074
7075 ;; No VSX equivalent to frin
7076 (define_insn "round<mode>2"
7077 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7078 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7079 UNSPEC_FRIN))]
7080 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7081 "frin %0,%1"
7082 [(set_attr "type" "fp")])
7083
7084 ; An UNSPEC is used so we don't have to support SImode in FP registers.
7085 (define_insn "stfiwx"
7086 [(set (match_operand:SI 0 "memory_operand" "=Z")
7087 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
7088 UNSPEC_STFIWX))]
7089 "TARGET_PPC_GFXOPT"
7090 "stfiwx %1,%y0"
7091 [(set_attr "type" "fpstore")])
7092
7093 ;; If we don't have a direct conversion to single precision, don't enable this
7094 ;; conversion for 32-bit without fast math, because we don't have the insn to
7095 ;; generate the fixup swizzle to avoid double rounding problems.
7096 (define_expand "floatsisf2"
7097 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7098 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
7099 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
7100 && (!TARGET_FPRS
7101 || (TARGET_FPRS
7102 && ((TARGET_FCFIDS && TARGET_LFIWAX)
7103 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
7104 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
7105 "
7106 {
7107 if (!TARGET_FPRS)
7108 {
7109 if (!REG_P (operands[1]))
7110 operands[1] = force_reg (SImode, operands[1]);
7111 }
7112 else if (TARGET_FCFIDS && TARGET_LFIWAX)
7113 {
7114 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
7115 DONE;
7116 }
7117 else if (TARGET_FCFID && TARGET_LFIWAX)
7118 {
7119 rtx dfreg = gen_reg_rtx (DFmode);
7120 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
7121 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
7122 DONE;
7123 }
7124 else
7125 {
7126 rtx dreg = operands[1];
7127 if (!REG_P (dreg))
7128 dreg = force_reg (SImode, dreg);
7129 dreg = convert_to_mode (DImode, dreg, false);
7130 emit_insn (gen_floatdisf2 (operands[0], dreg));
7131 DONE;
7132 }
7133 }")
7134
7135 (define_expand "floatdidf2"
7136 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7137 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
7138 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
7139 "")
7140
7141 (define_insn "*floatdidf2_fpr"
7142 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7143 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7144 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
7145 && !VECTOR_UNIT_VSX_P (DFmode)"
7146 "fcfid %0,%1"
7147 [(set_attr "type" "fp")])
7148
7149 ; Allow the combiner to merge source memory operands to the conversion so that
7150 ; the optimizer/register allocator doesn't try to load the value too early in a
7151 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
7152 ; hit. We will split after reload to avoid the trip through the GPRs
7153
7154 (define_insn_and_split "*floatdidf2_mem"
7155 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7156 (float:DF (match_operand:DI 1 "memory_operand" "m")))
7157 (clobber (match_scratch:DI 2 "=d"))]
7158 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
7159 "#"
7160 "&& reload_completed"
7161 [(set (match_dup 2) (match_dup 1))
7162 (set (match_dup 0) (float:DF (match_dup 2)))]
7163 ""
7164 [(set_attr "length" "8")
7165 (set_attr "type" "fpload")])
7166
7167 (define_expand "floatunsdidf2"
7168 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7169 (unsigned_float:DF
7170 (match_operand:DI 1 "gpc_reg_operand" "")))]
7171 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7172 "")
7173
7174 (define_insn "*floatunsdidf2_fcfidu"
7175 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7176 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7177 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
7178 "fcfidu %0,%1"
7179 [(set_attr "type" "fp")
7180 (set_attr "length" "4")])
7181
7182 (define_insn_and_split "*floatunsdidf2_mem"
7183 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7184 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
7185 (clobber (match_scratch:DI 2 "=d"))]
7186 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7187 "#"
7188 "&& reload_completed"
7189 [(set (match_dup 2) (match_dup 1))
7190 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
7191 ""
7192 [(set_attr "length" "8")
7193 (set_attr "type" "fpload")])
7194
7195 (define_expand "floatdisf2"
7196 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7197 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7198 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7199 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
7200 "
7201 {
7202 if (!TARGET_FCFIDS)
7203 {
7204 rtx val = operands[1];
7205 if (!flag_unsafe_math_optimizations)
7206 {
7207 rtx label = gen_label_rtx ();
7208 val = gen_reg_rtx (DImode);
7209 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
7210 emit_label (label);
7211 }
7212 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
7213 DONE;
7214 }
7215 }")
7216
7217 (define_insn "floatdisf2_fcfids"
7218 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7219 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7220 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7221 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7222 "fcfids %0,%1"
7223 [(set_attr "type" "fp")])
7224
7225 (define_insn_and_split "*floatdisf2_mem"
7226 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7227 (float:SF (match_operand:DI 1 "memory_operand" "m")))
7228 (clobber (match_scratch:DI 2 "=f"))]
7229 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7230 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7231 "#"
7232 "&& reload_completed"
7233 [(pc)]
7234 "
7235 {
7236 emit_move_insn (operands[2], operands[1]);
7237 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
7238 DONE;
7239 }"
7240 [(set_attr "length" "8")])
7241
7242 ;; This is not IEEE compliant if rounding mode is "round to nearest".
7243 ;; If the DI->DF conversion is inexact, then it's possible to suffer
7244 ;; from double rounding.
7245 ;; Instead of creating a new cpu type for two FP operations, just use fp
7246 (define_insn_and_split "floatdisf2_internal1"
7247 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7248 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
7249 (clobber (match_scratch:DF 2 "=d"))]
7250 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7251 "#"
7252 "&& reload_completed"
7253 [(set (match_dup 2)
7254 (float:DF (match_dup 1)))
7255 (set (match_dup 0)
7256 (float_truncate:SF (match_dup 2)))]
7257 ""
7258 [(set_attr "length" "8")
7259 (set_attr "type" "fp")])
7260
7261 ;; Twiddles bits to avoid double rounding.
7262 ;; Bits that might be truncated when converting to DFmode are replaced
7263 ;; by a bit that won't be lost at that stage, but is below the SFmode
7264 ;; rounding position.
7265 (define_expand "floatdisf2_internal2"
7266 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
7267 (const_int 53)))
7268 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
7269 (const_int 2047)))
7270 (clobber (scratch:CC))])
7271 (set (match_dup 3) (plus:DI (match_dup 3)
7272 (const_int 1)))
7273 (set (match_dup 0) (plus:DI (match_dup 0)
7274 (const_int 2047)))
7275 (set (match_dup 4) (compare:CCUNS (match_dup 3)
7276 (const_int 2)))
7277 (set (match_dup 0) (ior:DI (match_dup 0)
7278 (match_dup 1)))
7279 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
7280 (const_int -2048)))
7281 (clobber (scratch:CC))])
7282 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
7283 (label_ref (match_operand:DI 2 "" ""))
7284 (pc)))
7285 (set (match_dup 0) (match_dup 1))]
7286 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7287 "
7288 {
7289 operands[3] = gen_reg_rtx (DImode);
7290 operands[4] = gen_reg_rtx (CCUNSmode);
7291 }")
7292
7293 (define_expand "floatunsdisf2"
7294 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7295 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7296 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7297 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7298 "")
7299
7300 (define_insn "floatunsdisf2_fcfidus"
7301 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7302 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7303 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7304 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7305 "fcfidus %0,%1"
7306 [(set_attr "type" "fp")])
7307
7308 (define_insn_and_split "*floatunsdisf2_mem"
7309 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7310 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
7311 (clobber (match_scratch:DI 2 "=f"))]
7312 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7313 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7314 "#"
7315 "&& reload_completed"
7316 [(pc)]
7317 "
7318 {
7319 emit_move_insn (operands[2], operands[1]);
7320 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
7321 DONE;
7322 }"
7323 [(set_attr "length" "8")
7324 (set_attr "type" "fpload")])
7325 \f
7326 ;; Define the DImode operations that can be done in a small number
7327 ;; of instructions. The & constraints are to prevent the register
7328 ;; allocator from allocating registers that overlap with the inputs
7329 ;; (for example, having an input in 7,8 and an output in 6,7). We
7330 ;; also allow for the output being the same as one of the inputs.
7331
7332 (define_insn "*adddi3_noppc64"
7333 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
7334 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
7335 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
7336 "! TARGET_POWERPC64"
7337 "*
7338 {
7339 if (WORDS_BIG_ENDIAN)
7340 return (GET_CODE (operands[2])) != CONST_INT
7341 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
7342 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
7343 else
7344 return (GET_CODE (operands[2])) != CONST_INT
7345 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
7346 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
7347 }"
7348 [(set_attr "type" "two")
7349 (set_attr "length" "8")])
7350
7351 (define_insn "*subdi3_noppc64"
7352 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
7353 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
7354 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
7355 "! TARGET_POWERPC64"
7356 "*
7357 {
7358 if (WORDS_BIG_ENDIAN)
7359 return (GET_CODE (operands[1]) != CONST_INT)
7360 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
7361 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
7362 else
7363 return (GET_CODE (operands[1]) != CONST_INT)
7364 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
7365 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
7366 }"
7367 [(set_attr "type" "two")
7368 (set_attr "length" "8")])
7369
7370 (define_insn "*negdi2_noppc64"
7371 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7372 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
7373 "! TARGET_POWERPC64"
7374 "*
7375 {
7376 return (WORDS_BIG_ENDIAN)
7377 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
7378 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
7379 }"
7380 [(set_attr "type" "two")
7381 (set_attr "length" "8")])
7382
7383 (define_expand "mulsidi3"
7384 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7385 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7386 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7387 "! TARGET_POWERPC64"
7388 "
7389 {
7390 if (! TARGET_POWER && ! TARGET_POWERPC)
7391 {
7392 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7393 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7394 emit_insn (gen_mull_call ());
7395 if (WORDS_BIG_ENDIAN)
7396 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
7397 else
7398 {
7399 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
7400 gen_rtx_REG (SImode, 3));
7401 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
7402 gen_rtx_REG (SImode, 4));
7403 }
7404 DONE;
7405 }
7406 else if (TARGET_POWER)
7407 {
7408 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
7409 DONE;
7410 }
7411 }")
7412
7413 (define_insn "mulsidi3_mq"
7414 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7415 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7416 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7417 (clobber (match_scratch:SI 3 "=q"))]
7418 "TARGET_POWER"
7419 "mul %0,%1,%2\;mfmq %L0"
7420 [(set_attr "type" "imul")
7421 (set_attr "length" "8")])
7422
7423 (define_insn "*mulsidi3_no_mq"
7424 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7425 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7426 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7427 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7428 "*
7429 {
7430 return (WORDS_BIG_ENDIAN)
7431 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7432 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7433 }"
7434 [(set_attr "type" "imul")
7435 (set_attr "length" "8")])
7436
7437 (define_split
7438 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7439 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7440 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7441 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7442 [(set (match_dup 3)
7443 (truncate:SI
7444 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7445 (sign_extend:DI (match_dup 2)))
7446 (const_int 32))))
7447 (set (match_dup 4)
7448 (mult:SI (match_dup 1)
7449 (match_dup 2)))]
7450 "
7451 {
7452 int endian = (WORDS_BIG_ENDIAN == 0);
7453 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7454 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7455 }")
7456
7457 (define_expand "umulsidi3"
7458 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7459 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7460 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7461 "TARGET_POWERPC && ! TARGET_POWERPC64"
7462 "
7463 {
7464 if (TARGET_POWER)
7465 {
7466 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7467 DONE;
7468 }
7469 }")
7470
7471 (define_insn "umulsidi3_mq"
7472 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7473 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7474 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7475 (clobber (match_scratch:SI 3 "=q"))]
7476 "TARGET_POWERPC && TARGET_POWER"
7477 "*
7478 {
7479 return (WORDS_BIG_ENDIAN)
7480 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7481 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7482 }"
7483 [(set_attr "type" "imul")
7484 (set_attr "length" "8")])
7485
7486 (define_insn "*umulsidi3_no_mq"
7487 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7488 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7489 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7490 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7491 "*
7492 {
7493 return (WORDS_BIG_ENDIAN)
7494 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7495 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7496 }"
7497 [(set_attr "type" "imul")
7498 (set_attr "length" "8")])
7499
7500 (define_split
7501 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7502 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7503 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7504 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7505 [(set (match_dup 3)
7506 (truncate:SI
7507 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7508 (zero_extend:DI (match_dup 2)))
7509 (const_int 32))))
7510 (set (match_dup 4)
7511 (mult:SI (match_dup 1)
7512 (match_dup 2)))]
7513 "
7514 {
7515 int endian = (WORDS_BIG_ENDIAN == 0);
7516 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7517 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7518 }")
7519
7520 (define_expand "smulsi3_highpart"
7521 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7522 (truncate:SI
7523 (lshiftrt:DI (mult:DI (sign_extend:DI
7524 (match_operand:SI 1 "gpc_reg_operand" ""))
7525 (sign_extend:DI
7526 (match_operand:SI 2 "gpc_reg_operand" "")))
7527 (const_int 32))))]
7528 ""
7529 "
7530 {
7531 if (! TARGET_POWER && ! TARGET_POWERPC)
7532 {
7533 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7534 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7535 emit_insn (gen_mulh_call ());
7536 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7537 DONE;
7538 }
7539 else if (TARGET_POWER)
7540 {
7541 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7542 DONE;
7543 }
7544 }")
7545
7546 (define_insn "smulsi3_highpart_mq"
7547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7548 (truncate:SI
7549 (lshiftrt:DI (mult:DI (sign_extend:DI
7550 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7551 (sign_extend:DI
7552 (match_operand:SI 2 "gpc_reg_operand" "r")))
7553 (const_int 32))))
7554 (clobber (match_scratch:SI 3 "=q"))]
7555 "TARGET_POWER"
7556 "mul %0,%1,%2"
7557 [(set_attr "type" "imul")])
7558
7559 (define_insn "*smulsi3_highpart_no_mq"
7560 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7561 (truncate:SI
7562 (lshiftrt:DI (mult:DI (sign_extend:DI
7563 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7564 (sign_extend:DI
7565 (match_operand:SI 2 "gpc_reg_operand" "r")))
7566 (const_int 32))))]
7567 "TARGET_POWERPC && ! TARGET_POWER"
7568 "mulhw %0,%1,%2"
7569 [(set_attr "type" "imul")])
7570
7571 (define_expand "umulsi3_highpart"
7572 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7573 (truncate:SI
7574 (lshiftrt:DI (mult:DI (zero_extend:DI
7575 (match_operand:SI 1 "gpc_reg_operand" ""))
7576 (zero_extend:DI
7577 (match_operand:SI 2 "gpc_reg_operand" "")))
7578 (const_int 32))))]
7579 "TARGET_POWERPC"
7580 "
7581 {
7582 if (TARGET_POWER)
7583 {
7584 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7585 DONE;
7586 }
7587 }")
7588
7589 (define_insn "umulsi3_highpart_mq"
7590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7591 (truncate:SI
7592 (lshiftrt:DI (mult:DI (zero_extend:DI
7593 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7594 (zero_extend:DI
7595 (match_operand:SI 2 "gpc_reg_operand" "r")))
7596 (const_int 32))))
7597 (clobber (match_scratch:SI 3 "=q"))]
7598 "TARGET_POWERPC && TARGET_POWER"
7599 "mulhwu %0,%1,%2"
7600 [(set_attr "type" "imul")])
7601
7602 (define_insn "*umulsi3_highpart_no_mq"
7603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7604 (truncate:SI
7605 (lshiftrt:DI (mult:DI (zero_extend:DI
7606 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7607 (zero_extend:DI
7608 (match_operand:SI 2 "gpc_reg_operand" "r")))
7609 (const_int 32))))]
7610 "TARGET_POWERPC && ! TARGET_POWER"
7611 "mulhwu %0,%1,%2"
7612 [(set_attr "type" "imul")])
7613
7614 ;; If operands 0 and 2 are in the same register, we have a problem. But
7615 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7616 ;; why we have the strange constraints below.
7617 (define_insn "ashldi3_power"
7618 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7619 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7620 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7621 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7622 "TARGET_POWER"
7623 "@
7624 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7625 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7626 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7627 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7628 [(set_attr "length" "8")])
7629
7630 (define_insn "lshrdi3_power"
7631 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7632 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7633 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7634 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7635 "TARGET_POWER"
7636 "@
7637 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7638 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7639 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7640 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7641 [(set_attr "length" "8")])
7642
7643 ;; Shift by a variable amount is too complex to be worth open-coding. We
7644 ;; just handle shifts by constants.
7645 (define_insn "ashrdi3_power"
7646 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7647 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7648 (match_operand:SI 2 "const_int_operand" "M,i")))
7649 (clobber (match_scratch:SI 3 "=X,q"))]
7650 "TARGET_POWER"
7651 "@
7652 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7653 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7654 [(set_attr "type" "shift")
7655 (set_attr "length" "8")])
7656
7657 (define_insn "ashrdi3_no_power"
7658 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7659 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7660 (match_operand:SI 2 "const_int_operand" "M,i")))]
7661 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7662 "@
7663 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7664 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7665 [(set_attr "type" "two,three")
7666 (set_attr "length" "8,12")])
7667
7668 (define_insn "*ashrdisi3_noppc64"
7669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7670 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7671 (const_int 32)) 4))]
7672 "TARGET_32BIT && !TARGET_POWERPC64"
7673 "*
7674 {
7675 if (REGNO (operands[0]) == REGNO (operands[1]))
7676 return \"\";
7677 else
7678 return \"mr %0,%1\";
7679 }"
7680 [(set_attr "length" "4")])
7681
7682 \f
7683 ;; PowerPC64 DImode operations.
7684
7685 (define_expand "absdi2"
7686 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7687 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7688 "TARGET_POWERPC64"
7689 "
7690 {
7691 if (TARGET_ISEL)
7692 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7693 else
7694 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7695 DONE;
7696 }")
7697
7698 (define_insn_and_split "absdi2_internal"
7699 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7700 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7701 (clobber (match_scratch:DI 2 "=&r,&r"))]
7702 "TARGET_POWERPC64 && !TARGET_ISEL"
7703 "#"
7704 "&& reload_completed"
7705 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7706 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7707 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7708 "")
7709
7710 (define_insn_and_split "*nabsdi2"
7711 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7712 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7713 (clobber (match_scratch:DI 2 "=&r,&r"))]
7714 "TARGET_POWERPC64 && !TARGET_ISEL"
7715 "#"
7716 "&& reload_completed"
7717 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7718 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7719 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7720 "")
7721
7722 (define_insn "muldi3"
7723 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7724 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7725 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7726 "TARGET_POWERPC64"
7727 "@
7728 mulld %0,%1,%2
7729 mulli %0,%1,%2"
7730 [(set (attr "type")
7731 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7732 (const_string "imul3")
7733 (match_operand:SI 2 "short_cint_operand" "")
7734 (const_string "imul2")]
7735 (const_string "lmul")))])
7736
7737 (define_insn "*muldi3_internal1"
7738 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7739 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7740 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7741 (const_int 0)))
7742 (clobber (match_scratch:DI 3 "=r,r"))]
7743 "TARGET_POWERPC64"
7744 "@
7745 mulld. %3,%1,%2
7746 #"
7747 [(set_attr "type" "lmul_compare")
7748 (set_attr "length" "4,8")])
7749
7750 (define_split
7751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7752 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7753 (match_operand:DI 2 "gpc_reg_operand" ""))
7754 (const_int 0)))
7755 (clobber (match_scratch:DI 3 ""))]
7756 "TARGET_POWERPC64 && reload_completed"
7757 [(set (match_dup 3)
7758 (mult:DI (match_dup 1) (match_dup 2)))
7759 (set (match_dup 0)
7760 (compare:CC (match_dup 3)
7761 (const_int 0)))]
7762 "")
7763
7764 (define_insn "*muldi3_internal2"
7765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7766 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7767 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7768 (const_int 0)))
7769 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7770 (mult:DI (match_dup 1) (match_dup 2)))]
7771 "TARGET_POWERPC64"
7772 "@
7773 mulld. %0,%1,%2
7774 #"
7775 [(set_attr "type" "lmul_compare")
7776 (set_attr "length" "4,8")])
7777
7778 (define_split
7779 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7780 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7781 (match_operand:DI 2 "gpc_reg_operand" ""))
7782 (const_int 0)))
7783 (set (match_operand:DI 0 "gpc_reg_operand" "")
7784 (mult:DI (match_dup 1) (match_dup 2)))]
7785 "TARGET_POWERPC64 && reload_completed"
7786 [(set (match_dup 0)
7787 (mult:DI (match_dup 1) (match_dup 2)))
7788 (set (match_dup 3)
7789 (compare:CC (match_dup 0)
7790 (const_int 0)))]
7791 "")
7792
7793 (define_insn "smuldi3_highpart"
7794 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7795 (truncate:DI
7796 (lshiftrt:TI (mult:TI (sign_extend:TI
7797 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7798 (sign_extend:TI
7799 (match_operand:DI 2 "gpc_reg_operand" "r")))
7800 (const_int 64))))]
7801 "TARGET_POWERPC64"
7802 "mulhd %0,%1,%2"
7803 [(set_attr "type" "lmul")])
7804
7805 (define_insn "umuldi3_highpart"
7806 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7807 (truncate:DI
7808 (lshiftrt:TI (mult:TI (zero_extend:TI
7809 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7810 (zero_extend:TI
7811 (match_operand:DI 2 "gpc_reg_operand" "r")))
7812 (const_int 64))))]
7813 "TARGET_POWERPC64"
7814 "mulhdu %0,%1,%2"
7815 [(set_attr "type" "lmul")])
7816
7817 (define_insn "rotldi3"
7818 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7819 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7820 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7821 "TARGET_POWERPC64"
7822 "@
7823 rldcl %0,%1,%2,0
7824 rldicl %0,%1,%H2,0"
7825 [(set_attr "type" "var_shift_rotate,integer")])
7826
7827 (define_insn "*rotldi3_internal2"
7828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7829 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7830 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7831 (const_int 0)))
7832 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7833 "TARGET_64BIT"
7834 "@
7835 rldcl. %3,%1,%2,0
7836 rldicl. %3,%1,%H2,0
7837 #
7838 #"
7839 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7840 (set_attr "length" "4,4,8,8")])
7841
7842 (define_split
7843 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7844 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7845 (match_operand:DI 2 "reg_or_cint_operand" ""))
7846 (const_int 0)))
7847 (clobber (match_scratch:DI 3 ""))]
7848 "TARGET_POWERPC64 && reload_completed"
7849 [(set (match_dup 3)
7850 (rotate:DI (match_dup 1) (match_dup 2)))
7851 (set (match_dup 0)
7852 (compare:CC (match_dup 3)
7853 (const_int 0)))]
7854 "")
7855
7856 (define_insn "*rotldi3_internal3"
7857 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7858 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7859 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7860 (const_int 0)))
7861 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7862 (rotate:DI (match_dup 1) (match_dup 2)))]
7863 "TARGET_64BIT"
7864 "@
7865 rldcl. %0,%1,%2,0
7866 rldicl. %0,%1,%H2,0
7867 #
7868 #"
7869 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7870 (set_attr "length" "4,4,8,8")])
7871
7872 (define_split
7873 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7874 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7875 (match_operand:DI 2 "reg_or_cint_operand" ""))
7876 (const_int 0)))
7877 (set (match_operand:DI 0 "gpc_reg_operand" "")
7878 (rotate:DI (match_dup 1) (match_dup 2)))]
7879 "TARGET_POWERPC64 && reload_completed"
7880 [(set (match_dup 0)
7881 (rotate:DI (match_dup 1) (match_dup 2)))
7882 (set (match_dup 3)
7883 (compare:CC (match_dup 0)
7884 (const_int 0)))]
7885 "")
7886
7887 (define_insn "*rotldi3_internal4"
7888 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7889 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7890 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7891 (match_operand:DI 3 "mask64_operand" "n,n")))]
7892 "TARGET_POWERPC64"
7893 "@
7894 rldc%B3 %0,%1,%2,%S3
7895 rldic%B3 %0,%1,%H2,%S3"
7896 [(set_attr "type" "var_shift_rotate,integer")])
7897
7898 (define_insn "*rotldi3_internal5"
7899 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7900 (compare:CC (and:DI
7901 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7902 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7903 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7904 (const_int 0)))
7905 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7906 "TARGET_64BIT"
7907 "@
7908 rldc%B3. %4,%1,%2,%S3
7909 rldic%B3. %4,%1,%H2,%S3
7910 #
7911 #"
7912 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7913 (set_attr "length" "4,4,8,8")])
7914
7915 (define_split
7916 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7917 (compare:CC (and:DI
7918 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7919 (match_operand:DI 2 "reg_or_cint_operand" ""))
7920 (match_operand:DI 3 "mask64_operand" ""))
7921 (const_int 0)))
7922 (clobber (match_scratch:DI 4 ""))]
7923 "TARGET_POWERPC64 && reload_completed"
7924 [(set (match_dup 4)
7925 (and:DI (rotate:DI (match_dup 1)
7926 (match_dup 2))
7927 (match_dup 3)))
7928 (set (match_dup 0)
7929 (compare:CC (match_dup 4)
7930 (const_int 0)))]
7931 "")
7932
7933 (define_insn "*rotldi3_internal6"
7934 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7935 (compare:CC (and:DI
7936 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7937 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7938 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7939 (const_int 0)))
7940 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7941 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7942 "TARGET_64BIT"
7943 "@
7944 rldc%B3. %0,%1,%2,%S3
7945 rldic%B3. %0,%1,%H2,%S3
7946 #
7947 #"
7948 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7949 (set_attr "length" "4,4,8,8")])
7950
7951 (define_split
7952 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7953 (compare:CC (and:DI
7954 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7955 (match_operand:DI 2 "reg_or_cint_operand" ""))
7956 (match_operand:DI 3 "mask64_operand" ""))
7957 (const_int 0)))
7958 (set (match_operand:DI 0 "gpc_reg_operand" "")
7959 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7960 "TARGET_POWERPC64 && reload_completed"
7961 [(set (match_dup 0)
7962 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7963 (set (match_dup 4)
7964 (compare:CC (match_dup 0)
7965 (const_int 0)))]
7966 "")
7967
7968 (define_insn "*rotldi3_internal7"
7969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7970 (zero_extend:DI
7971 (subreg:QI
7972 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7973 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7974 "TARGET_POWERPC64"
7975 "@
7976 rldcl %0,%1,%2,56
7977 rldicl %0,%1,%H2,56"
7978 [(set_attr "type" "var_shift_rotate,integer")])
7979
7980 (define_insn "*rotldi3_internal8"
7981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7982 (compare:CC (zero_extend:DI
7983 (subreg:QI
7984 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7985 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7986 (const_int 0)))
7987 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7988 "TARGET_64BIT"
7989 "@
7990 rldcl. %3,%1,%2,56
7991 rldicl. %3,%1,%H2,56
7992 #
7993 #"
7994 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7995 (set_attr "length" "4,4,8,8")])
7996
7997 (define_split
7998 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7999 (compare:CC (zero_extend:DI
8000 (subreg:QI
8001 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8002 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8003 (const_int 0)))
8004 (clobber (match_scratch:DI 3 ""))]
8005 "TARGET_POWERPC64 && reload_completed"
8006 [(set (match_dup 3)
8007 (zero_extend:DI (subreg:QI
8008 (rotate:DI (match_dup 1)
8009 (match_dup 2)) 0)))
8010 (set (match_dup 0)
8011 (compare:CC (match_dup 3)
8012 (const_int 0)))]
8013 "")
8014
8015 (define_insn "*rotldi3_internal9"
8016 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8017 (compare:CC (zero_extend:DI
8018 (subreg:QI
8019 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8020 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8021 (const_int 0)))
8022 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8023 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8024 "TARGET_64BIT"
8025 "@
8026 rldcl. %0,%1,%2,56
8027 rldicl. %0,%1,%H2,56
8028 #
8029 #"
8030 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8031 (set_attr "length" "4,4,8,8")])
8032
8033 (define_split
8034 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8035 (compare:CC (zero_extend:DI
8036 (subreg:QI
8037 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8038 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8039 (const_int 0)))
8040 (set (match_operand:DI 0 "gpc_reg_operand" "")
8041 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8042 "TARGET_POWERPC64 && reload_completed"
8043 [(set (match_dup 0)
8044 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8045 (set (match_dup 3)
8046 (compare:CC (match_dup 0)
8047 (const_int 0)))]
8048 "")
8049
8050 (define_insn "*rotldi3_internal10"
8051 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8052 (zero_extend:DI
8053 (subreg:HI
8054 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8055 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8056 "TARGET_POWERPC64"
8057 "@
8058 rldcl %0,%1,%2,48
8059 rldicl %0,%1,%H2,48"
8060 [(set_attr "type" "var_shift_rotate,integer")])
8061
8062 (define_insn "*rotldi3_internal11"
8063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8064 (compare:CC (zero_extend:DI
8065 (subreg:HI
8066 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8067 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8068 (const_int 0)))
8069 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8070 "TARGET_64BIT"
8071 "@
8072 rldcl. %3,%1,%2,48
8073 rldicl. %3,%1,%H2,48
8074 #
8075 #"
8076 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8077 (set_attr "length" "4,4,8,8")])
8078
8079 (define_split
8080 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8081 (compare:CC (zero_extend:DI
8082 (subreg:HI
8083 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8084 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8085 (const_int 0)))
8086 (clobber (match_scratch:DI 3 ""))]
8087 "TARGET_POWERPC64 && reload_completed"
8088 [(set (match_dup 3)
8089 (zero_extend:DI (subreg:HI
8090 (rotate:DI (match_dup 1)
8091 (match_dup 2)) 0)))
8092 (set (match_dup 0)
8093 (compare:CC (match_dup 3)
8094 (const_int 0)))]
8095 "")
8096
8097 (define_insn "*rotldi3_internal12"
8098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8099 (compare:CC (zero_extend:DI
8100 (subreg:HI
8101 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8102 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8103 (const_int 0)))
8104 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8105 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8106 "TARGET_64BIT"
8107 "@
8108 rldcl. %0,%1,%2,48
8109 rldicl. %0,%1,%H2,48
8110 #
8111 #"
8112 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8113 (set_attr "length" "4,4,8,8")])
8114
8115 (define_split
8116 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8117 (compare:CC (zero_extend:DI
8118 (subreg:HI
8119 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8120 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8121 (const_int 0)))
8122 (set (match_operand:DI 0 "gpc_reg_operand" "")
8123 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8124 "TARGET_POWERPC64 && reload_completed"
8125 [(set (match_dup 0)
8126 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8127 (set (match_dup 3)
8128 (compare:CC (match_dup 0)
8129 (const_int 0)))]
8130 "")
8131
8132 (define_insn "*rotldi3_internal13"
8133 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8134 (zero_extend:DI
8135 (subreg:SI
8136 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8137 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8138 "TARGET_POWERPC64"
8139 "@
8140 rldcl %0,%1,%2,32
8141 rldicl %0,%1,%H2,32"
8142 [(set_attr "type" "var_shift_rotate,integer")])
8143
8144 (define_insn "*rotldi3_internal14"
8145 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8146 (compare:CC (zero_extend:DI
8147 (subreg:SI
8148 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8149 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8150 (const_int 0)))
8151 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8152 "TARGET_64BIT"
8153 "@
8154 rldcl. %3,%1,%2,32
8155 rldicl. %3,%1,%H2,32
8156 #
8157 #"
8158 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8159 (set_attr "length" "4,4,8,8")])
8160
8161 (define_split
8162 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8163 (compare:CC (zero_extend:DI
8164 (subreg:SI
8165 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8166 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8167 (const_int 0)))
8168 (clobber (match_scratch:DI 3 ""))]
8169 "TARGET_POWERPC64 && reload_completed"
8170 [(set (match_dup 3)
8171 (zero_extend:DI (subreg:SI
8172 (rotate:DI (match_dup 1)
8173 (match_dup 2)) 0)))
8174 (set (match_dup 0)
8175 (compare:CC (match_dup 3)
8176 (const_int 0)))]
8177 "")
8178
8179 (define_insn "*rotldi3_internal15"
8180 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8181 (compare:CC (zero_extend:DI
8182 (subreg:SI
8183 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8184 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8185 (const_int 0)))
8186 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8187 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8188 "TARGET_64BIT"
8189 "@
8190 rldcl. %0,%1,%2,32
8191 rldicl. %0,%1,%H2,32
8192 #
8193 #"
8194 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8195 (set_attr "length" "4,4,8,8")])
8196
8197 (define_split
8198 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8199 (compare:CC (zero_extend:DI
8200 (subreg:SI
8201 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8202 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8203 (const_int 0)))
8204 (set (match_operand:DI 0 "gpc_reg_operand" "")
8205 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8206 "TARGET_POWERPC64 && reload_completed"
8207 [(set (match_dup 0)
8208 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8209 (set (match_dup 3)
8210 (compare:CC (match_dup 0)
8211 (const_int 0)))]
8212 "")
8213
8214 (define_expand "ashldi3"
8215 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8216 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8217 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8218 "TARGET_POWERPC64 || TARGET_POWER"
8219 "
8220 {
8221 if (TARGET_POWERPC64)
8222 ;
8223 else if (TARGET_POWER)
8224 {
8225 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
8226 DONE;
8227 }
8228 else
8229 FAIL;
8230 }")
8231
8232 (define_insn "*ashldi3_internal1"
8233 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8234 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8235 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8236 "TARGET_POWERPC64"
8237 "@
8238 sld %0,%1,%2
8239 sldi %0,%1,%H2"
8240 [(set_attr "type" "var_shift_rotate,shift")])
8241
8242 (define_insn "*ashldi3_internal2"
8243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8244 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8245 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8246 (const_int 0)))
8247 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8248 "TARGET_64BIT"
8249 "@
8250 sld. %3,%1,%2
8251 sldi. %3,%1,%H2
8252 #
8253 #"
8254 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8255 (set_attr "length" "4,4,8,8")])
8256
8257 (define_split
8258 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8259 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8260 (match_operand:SI 2 "reg_or_cint_operand" ""))
8261 (const_int 0)))
8262 (clobber (match_scratch:DI 3 ""))]
8263 "TARGET_POWERPC64 && reload_completed"
8264 [(set (match_dup 3)
8265 (ashift:DI (match_dup 1) (match_dup 2)))
8266 (set (match_dup 0)
8267 (compare:CC (match_dup 3)
8268 (const_int 0)))]
8269 "")
8270
8271 (define_insn "*ashldi3_internal3"
8272 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8273 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8274 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8275 (const_int 0)))
8276 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8277 (ashift:DI (match_dup 1) (match_dup 2)))]
8278 "TARGET_64BIT"
8279 "@
8280 sld. %0,%1,%2
8281 sldi. %0,%1,%H2
8282 #
8283 #"
8284 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8285 (set_attr "length" "4,4,8,8")])
8286
8287 (define_split
8288 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8289 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8290 (match_operand:SI 2 "reg_or_cint_operand" ""))
8291 (const_int 0)))
8292 (set (match_operand:DI 0 "gpc_reg_operand" "")
8293 (ashift:DI (match_dup 1) (match_dup 2)))]
8294 "TARGET_POWERPC64 && reload_completed"
8295 [(set (match_dup 0)
8296 (ashift:DI (match_dup 1) (match_dup 2)))
8297 (set (match_dup 3)
8298 (compare:CC (match_dup 0)
8299 (const_int 0)))]
8300 "")
8301
8302 (define_insn "*ashldi3_internal4"
8303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8304 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8305 (match_operand:SI 2 "const_int_operand" "i"))
8306 (match_operand:DI 3 "const_int_operand" "n")))]
8307 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
8308 "rldic %0,%1,%H2,%W3")
8309
8310 (define_insn "ashldi3_internal5"
8311 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8312 (compare:CC
8313 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8314 (match_operand:SI 2 "const_int_operand" "i,i"))
8315 (match_operand:DI 3 "const_int_operand" "n,n"))
8316 (const_int 0)))
8317 (clobber (match_scratch:DI 4 "=r,r"))]
8318 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8319 "@
8320 rldic. %4,%1,%H2,%W3
8321 #"
8322 [(set_attr "type" "compare")
8323 (set_attr "length" "4,8")])
8324
8325 (define_split
8326 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8327 (compare:CC
8328 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8329 (match_operand:SI 2 "const_int_operand" ""))
8330 (match_operand:DI 3 "const_int_operand" ""))
8331 (const_int 0)))
8332 (clobber (match_scratch:DI 4 ""))]
8333 "TARGET_POWERPC64 && reload_completed
8334 && includes_rldic_lshift_p (operands[2], operands[3])"
8335 [(set (match_dup 4)
8336 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8337 (match_dup 3)))
8338 (set (match_dup 0)
8339 (compare:CC (match_dup 4)
8340 (const_int 0)))]
8341 "")
8342
8343 (define_insn "*ashldi3_internal6"
8344 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8345 (compare:CC
8346 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8347 (match_operand:SI 2 "const_int_operand" "i,i"))
8348 (match_operand:DI 3 "const_int_operand" "n,n"))
8349 (const_int 0)))
8350 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8351 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8352 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8353 "@
8354 rldic. %0,%1,%H2,%W3
8355 #"
8356 [(set_attr "type" "compare")
8357 (set_attr "length" "4,8")])
8358
8359 (define_split
8360 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8361 (compare:CC
8362 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8363 (match_operand:SI 2 "const_int_operand" ""))
8364 (match_operand:DI 3 "const_int_operand" ""))
8365 (const_int 0)))
8366 (set (match_operand:DI 0 "gpc_reg_operand" "")
8367 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8368 "TARGET_POWERPC64 && reload_completed
8369 && includes_rldic_lshift_p (operands[2], operands[3])"
8370 [(set (match_dup 0)
8371 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8372 (match_dup 3)))
8373 (set (match_dup 4)
8374 (compare:CC (match_dup 0)
8375 (const_int 0)))]
8376 "")
8377
8378 (define_insn "*ashldi3_internal7"
8379 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8380 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8381 (match_operand:SI 2 "const_int_operand" "i"))
8382 (match_operand:DI 3 "mask64_operand" "n")))]
8383 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
8384 "rldicr %0,%1,%H2,%S3")
8385
8386 (define_insn "ashldi3_internal8"
8387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8388 (compare:CC
8389 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8390 (match_operand:SI 2 "const_int_operand" "i,i"))
8391 (match_operand:DI 3 "mask64_operand" "n,n"))
8392 (const_int 0)))
8393 (clobber (match_scratch:DI 4 "=r,r"))]
8394 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8395 "@
8396 rldicr. %4,%1,%H2,%S3
8397 #"
8398 [(set_attr "type" "compare")
8399 (set_attr "length" "4,8")])
8400
8401 (define_split
8402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8403 (compare:CC
8404 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8405 (match_operand:SI 2 "const_int_operand" ""))
8406 (match_operand:DI 3 "mask64_operand" ""))
8407 (const_int 0)))
8408 (clobber (match_scratch:DI 4 ""))]
8409 "TARGET_POWERPC64 && reload_completed
8410 && includes_rldicr_lshift_p (operands[2], operands[3])"
8411 [(set (match_dup 4)
8412 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8413 (match_dup 3)))
8414 (set (match_dup 0)
8415 (compare:CC (match_dup 4)
8416 (const_int 0)))]
8417 "")
8418
8419 (define_insn "*ashldi3_internal9"
8420 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8421 (compare:CC
8422 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8423 (match_operand:SI 2 "const_int_operand" "i,i"))
8424 (match_operand:DI 3 "mask64_operand" "n,n"))
8425 (const_int 0)))
8426 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8427 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8428 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8429 "@
8430 rldicr. %0,%1,%H2,%S3
8431 #"
8432 [(set_attr "type" "compare")
8433 (set_attr "length" "4,8")])
8434
8435 (define_split
8436 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8437 (compare:CC
8438 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8439 (match_operand:SI 2 "const_int_operand" ""))
8440 (match_operand:DI 3 "mask64_operand" ""))
8441 (const_int 0)))
8442 (set (match_operand:DI 0 "gpc_reg_operand" "")
8443 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8444 "TARGET_POWERPC64 && reload_completed
8445 && includes_rldicr_lshift_p (operands[2], operands[3])"
8446 [(set (match_dup 0)
8447 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8448 (match_dup 3)))
8449 (set (match_dup 4)
8450 (compare:CC (match_dup 0)
8451 (const_int 0)))]
8452 "")
8453
8454 (define_expand "lshrdi3"
8455 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8456 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8457 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8458 "TARGET_POWERPC64 || TARGET_POWER"
8459 "
8460 {
8461 if (TARGET_POWERPC64)
8462 ;
8463 else if (TARGET_POWER)
8464 {
8465 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8466 DONE;
8467 }
8468 else
8469 FAIL;
8470 }")
8471
8472 (define_insn "*lshrdi3_internal1"
8473 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8474 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8475 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8476 "TARGET_POWERPC64"
8477 "@
8478 srd %0,%1,%2
8479 srdi %0,%1,%H2"
8480 [(set_attr "type" "var_shift_rotate,shift")])
8481
8482 (define_insn "*lshrdi3_internal2"
8483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8484 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8485 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8486 (const_int 0)))
8487 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8488 "TARGET_64BIT "
8489 "@
8490 srd. %3,%1,%2
8491 srdi. %3,%1,%H2
8492 #
8493 #"
8494 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8495 (set_attr "length" "4,4,8,8")])
8496
8497 (define_split
8498 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8499 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8500 (match_operand:SI 2 "reg_or_cint_operand" ""))
8501 (const_int 0)))
8502 (clobber (match_scratch:DI 3 ""))]
8503 "TARGET_POWERPC64 && reload_completed"
8504 [(set (match_dup 3)
8505 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8506 (set (match_dup 0)
8507 (compare:CC (match_dup 3)
8508 (const_int 0)))]
8509 "")
8510
8511 (define_insn "*lshrdi3_internal3"
8512 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8513 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8514 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8515 (const_int 0)))
8516 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8517 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8518 "TARGET_64BIT"
8519 "@
8520 srd. %0,%1,%2
8521 srdi. %0,%1,%H2
8522 #
8523 #"
8524 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8525 (set_attr "length" "4,4,8,8")])
8526
8527 (define_split
8528 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8529 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8530 (match_operand:SI 2 "reg_or_cint_operand" ""))
8531 (const_int 0)))
8532 (set (match_operand:DI 0 "gpc_reg_operand" "")
8533 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8534 "TARGET_POWERPC64 && reload_completed"
8535 [(set (match_dup 0)
8536 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8537 (set (match_dup 3)
8538 (compare:CC (match_dup 0)
8539 (const_int 0)))]
8540 "")
8541
8542 (define_expand "ashrdi3"
8543 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8544 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8545 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8546 "WORDS_BIG_ENDIAN"
8547 "
8548 {
8549 if (TARGET_POWERPC64)
8550 ;
8551 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8552 {
8553 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8554 DONE;
8555 }
8556 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8557 && WORDS_BIG_ENDIAN)
8558 {
8559 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8560 DONE;
8561 }
8562 else
8563 FAIL;
8564 }")
8565
8566 (define_insn "*ashrdi3_internal1"
8567 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8568 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8569 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8570 "TARGET_POWERPC64"
8571 "@
8572 srad %0,%1,%2
8573 sradi %0,%1,%H2"
8574 [(set_attr "type" "var_shift_rotate,shift")])
8575
8576 (define_insn "*ashrdi3_internal2"
8577 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8578 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8579 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8580 (const_int 0)))
8581 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8582 "TARGET_64BIT"
8583 "@
8584 srad. %3,%1,%2
8585 sradi. %3,%1,%H2
8586 #
8587 #"
8588 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8589 (set_attr "length" "4,4,8,8")])
8590
8591 (define_split
8592 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8593 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8594 (match_operand:SI 2 "reg_or_cint_operand" ""))
8595 (const_int 0)))
8596 (clobber (match_scratch:DI 3 ""))]
8597 "TARGET_POWERPC64 && reload_completed"
8598 [(set (match_dup 3)
8599 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8600 (set (match_dup 0)
8601 (compare:CC (match_dup 3)
8602 (const_int 0)))]
8603 "")
8604
8605 (define_insn "*ashrdi3_internal3"
8606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8607 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8608 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8609 (const_int 0)))
8610 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8611 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8612 "TARGET_64BIT"
8613 "@
8614 srad. %0,%1,%2
8615 sradi. %0,%1,%H2
8616 #
8617 #"
8618 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8619 (set_attr "length" "4,4,8,8")])
8620
8621 (define_split
8622 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8623 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8624 (match_operand:SI 2 "reg_or_cint_operand" ""))
8625 (const_int 0)))
8626 (set (match_operand:DI 0 "gpc_reg_operand" "")
8627 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8628 "TARGET_POWERPC64 && reload_completed"
8629 [(set (match_dup 0)
8630 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8631 (set (match_dup 3)
8632 (compare:CC (match_dup 0)
8633 (const_int 0)))]
8634 "")
8635
8636 (define_expand "anddi3"
8637 [(parallel
8638 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8639 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8640 (match_operand:DI 2 "and64_2_operand" "")))
8641 (clobber (match_scratch:CC 3 ""))])]
8642 "TARGET_POWERPC64"
8643 "")
8644
8645 (define_insn "anddi3_mc"
8646 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8647 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8648 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8649 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8650 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8651 "@
8652 and %0,%1,%2
8653 rldic%B2 %0,%1,0,%S2
8654 rlwinm %0,%1,0,%m2,%M2
8655 andi. %0,%1,%b2
8656 andis. %0,%1,%u2
8657 #"
8658 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8659 (set_attr "length" "4,4,4,4,4,8")])
8660
8661 (define_insn "anddi3_nomc"
8662 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8663 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8664 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8665 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8666 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8667 "@
8668 and %0,%1,%2
8669 rldic%B2 %0,%1,0,%S2
8670 rlwinm %0,%1,0,%m2,%M2
8671 #"
8672 [(set_attr "length" "4,4,4,8")])
8673
8674 (define_split
8675 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8676 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8677 (match_operand:DI 2 "mask64_2_operand" "")))
8678 (clobber (match_scratch:CC 3 ""))]
8679 "TARGET_POWERPC64
8680 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8681 && !mask_operand (operands[2], DImode)
8682 && !mask64_operand (operands[2], DImode)"
8683 [(set (match_dup 0)
8684 (and:DI (rotate:DI (match_dup 1)
8685 (match_dup 4))
8686 (match_dup 5)))
8687 (set (match_dup 0)
8688 (and:DI (rotate:DI (match_dup 0)
8689 (match_dup 6))
8690 (match_dup 7)))]
8691 {
8692 build_mask64_2_operands (operands[2], &operands[4]);
8693 })
8694
8695 (define_insn "*anddi3_internal2_mc"
8696 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8697 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8698 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8699 (const_int 0)))
8700 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8701 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8702 "TARGET_64BIT && rs6000_gen_cell_microcode"
8703 "@
8704 and. %3,%1,%2
8705 rldic%B2. %3,%1,0,%S2
8706 rlwinm. %3,%1,0,%m2,%M2
8707 andi. %3,%1,%b2
8708 andis. %3,%1,%u2
8709 #
8710 #
8711 #
8712 #
8713 #
8714 #
8715 #"
8716 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8717 fast_compare,compare,compare,compare,compare,compare,\
8718 compare,compare")
8719 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8720
8721 (define_split
8722 [(set (match_operand:CC 0 "cc_reg_operand" "")
8723 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8724 (match_operand:DI 2 "mask64_2_operand" ""))
8725 (const_int 0)))
8726 (clobber (match_scratch:DI 3 ""))
8727 (clobber (match_scratch:CC 4 ""))]
8728 "TARGET_64BIT && reload_completed
8729 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8730 && !mask_operand (operands[2], DImode)
8731 && !mask64_operand (operands[2], DImode)"
8732 [(set (match_dup 3)
8733 (and:DI (rotate:DI (match_dup 1)
8734 (match_dup 5))
8735 (match_dup 6)))
8736 (parallel [(set (match_dup 0)
8737 (compare:CC (and:DI (rotate:DI (match_dup 3)
8738 (match_dup 7))
8739 (match_dup 8))
8740 (const_int 0)))
8741 (clobber (match_dup 3))])]
8742 "
8743 {
8744 build_mask64_2_operands (operands[2], &operands[5]);
8745 }")
8746
8747 (define_insn "*anddi3_internal3_mc"
8748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8749 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8750 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8751 (const_int 0)))
8752 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8753 (and:DI (match_dup 1) (match_dup 2)))
8754 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8755 "TARGET_64BIT && rs6000_gen_cell_microcode"
8756 "@
8757 and. %0,%1,%2
8758 rldic%B2. %0,%1,0,%S2
8759 rlwinm. %0,%1,0,%m2,%M2
8760 andi. %0,%1,%b2
8761 andis. %0,%1,%u2
8762 #
8763 #
8764 #
8765 #
8766 #
8767 #
8768 #"
8769 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8770 fast_compare,compare,compare,compare,compare,compare,\
8771 compare,compare")
8772 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8773
8774 (define_split
8775 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8776 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8777 (match_operand:DI 2 "and64_2_operand" ""))
8778 (const_int 0)))
8779 (set (match_operand:DI 0 "gpc_reg_operand" "")
8780 (and:DI (match_dup 1) (match_dup 2)))
8781 (clobber (match_scratch:CC 4 ""))]
8782 "TARGET_64BIT && reload_completed"
8783 [(parallel [(set (match_dup 0)
8784 (and:DI (match_dup 1) (match_dup 2)))
8785 (clobber (match_dup 4))])
8786 (set (match_dup 3)
8787 (compare:CC (match_dup 0)
8788 (const_int 0)))]
8789 "")
8790
8791 (define_split
8792 [(set (match_operand:CC 3 "cc_reg_operand" "")
8793 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8794 (match_operand:DI 2 "mask64_2_operand" ""))
8795 (const_int 0)))
8796 (set (match_operand:DI 0 "gpc_reg_operand" "")
8797 (and:DI (match_dup 1) (match_dup 2)))
8798 (clobber (match_scratch:CC 4 ""))]
8799 "TARGET_64BIT && reload_completed
8800 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8801 && !mask_operand (operands[2], DImode)
8802 && !mask64_operand (operands[2], DImode)"
8803 [(set (match_dup 0)
8804 (and:DI (rotate:DI (match_dup 1)
8805 (match_dup 5))
8806 (match_dup 6)))
8807 (parallel [(set (match_dup 3)
8808 (compare:CC (and:DI (rotate:DI (match_dup 0)
8809 (match_dup 7))
8810 (match_dup 8))
8811 (const_int 0)))
8812 (set (match_dup 0)
8813 (and:DI (rotate:DI (match_dup 0)
8814 (match_dup 7))
8815 (match_dup 8)))])]
8816 "
8817 {
8818 build_mask64_2_operands (operands[2], &operands[5]);
8819 }")
8820
8821 (define_expand "iordi3"
8822 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8823 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8824 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8825 "TARGET_POWERPC64"
8826 "
8827 {
8828 if (non_logical_cint_operand (operands[2], DImode))
8829 {
8830 HOST_WIDE_INT value;
8831 rtx tmp = ((!can_create_pseudo_p ()
8832 || rtx_equal_p (operands[0], operands[1]))
8833 ? operands[0] : gen_reg_rtx (DImode));
8834
8835 if (GET_CODE (operands[2]) == CONST_INT)
8836 {
8837 value = INTVAL (operands[2]);
8838 emit_insn (gen_iordi3 (tmp, operands[1],
8839 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8840 }
8841 else
8842 {
8843 value = CONST_DOUBLE_LOW (operands[2]);
8844 emit_insn (gen_iordi3 (tmp, operands[1],
8845 immed_double_const (value
8846 & (~ (HOST_WIDE_INT) 0xffff),
8847 0, DImode)));
8848 }
8849
8850 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8851 DONE;
8852 }
8853 }")
8854
8855 (define_expand "xordi3"
8856 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8857 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8858 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8859 "TARGET_POWERPC64"
8860 "
8861 {
8862 if (non_logical_cint_operand (operands[2], DImode))
8863 {
8864 HOST_WIDE_INT value;
8865 rtx tmp = ((!can_create_pseudo_p ()
8866 || rtx_equal_p (operands[0], operands[1]))
8867 ? operands[0] : gen_reg_rtx (DImode));
8868
8869 if (GET_CODE (operands[2]) == CONST_INT)
8870 {
8871 value = INTVAL (operands[2]);
8872 emit_insn (gen_xordi3 (tmp, operands[1],
8873 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8874 }
8875 else
8876 {
8877 value = CONST_DOUBLE_LOW (operands[2]);
8878 emit_insn (gen_xordi3 (tmp, operands[1],
8879 immed_double_const (value
8880 & (~ (HOST_WIDE_INT) 0xffff),
8881 0, DImode)));
8882 }
8883
8884 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8885 DONE;
8886 }
8887 }")
8888
8889 (define_insn "*booldi3_internal1"
8890 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8891 (match_operator:DI 3 "boolean_or_operator"
8892 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8893 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8894 "TARGET_POWERPC64"
8895 "@
8896 %q3 %0,%1,%2
8897 %q3i %0,%1,%b2
8898 %q3is %0,%1,%u2")
8899
8900 (define_insn "*booldi3_internal2"
8901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8902 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8903 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8904 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8905 (const_int 0)))
8906 (clobber (match_scratch:DI 3 "=r,r"))]
8907 "TARGET_64BIT"
8908 "@
8909 %q4. %3,%1,%2
8910 #"
8911 [(set_attr "type" "fast_compare,compare")
8912 (set_attr "length" "4,8")])
8913
8914 (define_split
8915 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8916 (compare:CC (match_operator:DI 4 "boolean_operator"
8917 [(match_operand:DI 1 "gpc_reg_operand" "")
8918 (match_operand:DI 2 "gpc_reg_operand" "")])
8919 (const_int 0)))
8920 (clobber (match_scratch:DI 3 ""))]
8921 "TARGET_POWERPC64 && reload_completed"
8922 [(set (match_dup 3) (match_dup 4))
8923 (set (match_dup 0)
8924 (compare:CC (match_dup 3)
8925 (const_int 0)))]
8926 "")
8927
8928 (define_insn "*booldi3_internal3"
8929 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8930 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8931 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8932 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8933 (const_int 0)))
8934 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8935 (match_dup 4))]
8936 "TARGET_64BIT"
8937 "@
8938 %q4. %0,%1,%2
8939 #"
8940 [(set_attr "type" "fast_compare,compare")
8941 (set_attr "length" "4,8")])
8942
8943 (define_split
8944 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8945 (compare:CC (match_operator:DI 4 "boolean_operator"
8946 [(match_operand:DI 1 "gpc_reg_operand" "")
8947 (match_operand:DI 2 "gpc_reg_operand" "")])
8948 (const_int 0)))
8949 (set (match_operand:DI 0 "gpc_reg_operand" "")
8950 (match_dup 4))]
8951 "TARGET_POWERPC64 && reload_completed"
8952 [(set (match_dup 0) (match_dup 4))
8953 (set (match_dup 3)
8954 (compare:CC (match_dup 0)
8955 (const_int 0)))]
8956 "")
8957
8958 ;; Split a logical operation that we can't do in one insn into two insns,
8959 ;; each of which does one 16-bit part. This is used by combine.
8960
8961 (define_split
8962 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8963 (match_operator:DI 3 "boolean_or_operator"
8964 [(match_operand:DI 1 "gpc_reg_operand" "")
8965 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8966 "TARGET_POWERPC64"
8967 [(set (match_dup 0) (match_dup 4))
8968 (set (match_dup 0) (match_dup 5))]
8969 "
8970 {
8971 rtx i3,i4;
8972
8973 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8974 {
8975 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8976 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8977 0, DImode);
8978 i4 = GEN_INT (value & 0xffff);
8979 }
8980 else
8981 {
8982 i3 = GEN_INT (INTVAL (operands[2])
8983 & (~ (HOST_WIDE_INT) 0xffff));
8984 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8985 }
8986 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8987 operands[1], i3);
8988 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8989 operands[0], i4);
8990 }")
8991
8992 (define_insn "*boolcdi3_internal1"
8993 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8994 (match_operator:DI 3 "boolean_operator"
8995 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8996 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8997 "TARGET_POWERPC64"
8998 "%q3 %0,%2,%1")
8999
9000 (define_insn "*boolcdi3_internal2"
9001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9002 (compare:CC (match_operator:DI 4 "boolean_operator"
9003 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9004 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9005 (const_int 0)))
9006 (clobber (match_scratch:DI 3 "=r,r"))]
9007 "TARGET_64BIT"
9008 "@
9009 %q4. %3,%2,%1
9010 #"
9011 [(set_attr "type" "fast_compare,compare")
9012 (set_attr "length" "4,8")])
9013
9014 (define_split
9015 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9016 (compare:CC (match_operator:DI 4 "boolean_operator"
9017 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9018 (match_operand:DI 2 "gpc_reg_operand" "")])
9019 (const_int 0)))
9020 (clobber (match_scratch:DI 3 ""))]
9021 "TARGET_POWERPC64 && reload_completed"
9022 [(set (match_dup 3) (match_dup 4))
9023 (set (match_dup 0)
9024 (compare:CC (match_dup 3)
9025 (const_int 0)))]
9026 "")
9027
9028 (define_insn "*boolcdi3_internal3"
9029 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9030 (compare:CC (match_operator:DI 4 "boolean_operator"
9031 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9032 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9033 (const_int 0)))
9034 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9035 (match_dup 4))]
9036 "TARGET_64BIT"
9037 "@
9038 %q4. %0,%2,%1
9039 #"
9040 [(set_attr "type" "fast_compare,compare")
9041 (set_attr "length" "4,8")])
9042
9043 (define_split
9044 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9045 (compare:CC (match_operator:DI 4 "boolean_operator"
9046 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9047 (match_operand:DI 2 "gpc_reg_operand" "")])
9048 (const_int 0)))
9049 (set (match_operand:DI 0 "gpc_reg_operand" "")
9050 (match_dup 4))]
9051 "TARGET_POWERPC64 && reload_completed"
9052 [(set (match_dup 0) (match_dup 4))
9053 (set (match_dup 3)
9054 (compare:CC (match_dup 0)
9055 (const_int 0)))]
9056 "")
9057
9058 (define_insn "*boolccdi3_internal1"
9059 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9060 (match_operator:DI 3 "boolean_operator"
9061 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9062 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
9063 "TARGET_POWERPC64"
9064 "%q3 %0,%1,%2")
9065
9066 (define_insn "*boolccdi3_internal2"
9067 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9068 (compare:CC (match_operator:DI 4 "boolean_operator"
9069 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9070 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9071 (const_int 0)))
9072 (clobber (match_scratch:DI 3 "=r,r"))]
9073 "TARGET_64BIT"
9074 "@
9075 %q4. %3,%1,%2
9076 #"
9077 [(set_attr "type" "fast_compare,compare")
9078 (set_attr "length" "4,8")])
9079
9080 (define_split
9081 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9082 (compare:CC (match_operator:DI 4 "boolean_operator"
9083 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9084 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9085 (const_int 0)))
9086 (clobber (match_scratch:DI 3 ""))]
9087 "TARGET_POWERPC64 && reload_completed"
9088 [(set (match_dup 3) (match_dup 4))
9089 (set (match_dup 0)
9090 (compare:CC (match_dup 3)
9091 (const_int 0)))]
9092 "")
9093
9094 (define_insn "*boolccdi3_internal3"
9095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9096 (compare:CC (match_operator:DI 4 "boolean_operator"
9097 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9098 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9099 (const_int 0)))
9100 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9101 (match_dup 4))]
9102 "TARGET_64BIT"
9103 "@
9104 %q4. %0,%1,%2
9105 #"
9106 [(set_attr "type" "fast_compare,compare")
9107 (set_attr "length" "4,8")])
9108
9109 (define_split
9110 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9111 (compare:CC (match_operator:DI 4 "boolean_operator"
9112 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9113 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9114 (const_int 0)))
9115 (set (match_operand:DI 0 "gpc_reg_operand" "")
9116 (match_dup 4))]
9117 "TARGET_POWERPC64 && reload_completed"
9118 [(set (match_dup 0) (match_dup 4))
9119 (set (match_dup 3)
9120 (compare:CC (match_dup 0)
9121 (const_int 0)))]
9122 "")
9123
9124 (define_expand "smindi3"
9125 [(match_operand:DI 0 "gpc_reg_operand" "")
9126 (match_operand:DI 1 "gpc_reg_operand" "")
9127 (match_operand:DI 2 "gpc_reg_operand" "")]
9128 "TARGET_ISEL64"
9129 "
9130 {
9131 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
9132 DONE;
9133 }")
9134
9135 (define_expand "smaxdi3"
9136 [(match_operand:DI 0 "gpc_reg_operand" "")
9137 (match_operand:DI 1 "gpc_reg_operand" "")
9138 (match_operand:DI 2 "gpc_reg_operand" "")]
9139 "TARGET_ISEL64"
9140 "
9141 {
9142 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
9143 DONE;
9144 }")
9145
9146 (define_expand "umindi3"
9147 [(match_operand:DI 0 "gpc_reg_operand" "")
9148 (match_operand:DI 1 "gpc_reg_operand" "")
9149 (match_operand:DI 2 "gpc_reg_operand" "")]
9150 "TARGET_ISEL64"
9151 "
9152 {
9153 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
9154 DONE;
9155 }")
9156
9157 (define_expand "umaxdi3"
9158 [(match_operand:DI 0 "gpc_reg_operand" "")
9159 (match_operand:DI 1 "gpc_reg_operand" "")
9160 (match_operand:DI 2 "gpc_reg_operand" "")]
9161 "TARGET_ISEL64"
9162 "
9163 {
9164 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
9165 DONE;
9166 }")
9167
9168 \f
9169 ;; Now define ways of moving data around.
9170
9171 ;; Set up a register with a value from the GOT table
9172
9173 (define_expand "movsi_got"
9174 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9175 (unspec:SI [(match_operand:SI 1 "got_operand" "")
9176 (match_dup 2)] UNSPEC_MOVSI_GOT))]
9177 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9178 "
9179 {
9180 if (GET_CODE (operands[1]) == CONST)
9181 {
9182 rtx offset = const0_rtx;
9183 HOST_WIDE_INT value;
9184
9185 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
9186 value = INTVAL (offset);
9187 if (value != 0)
9188 {
9189 rtx tmp = (!can_create_pseudo_p ()
9190 ? operands[0]
9191 : gen_reg_rtx (Pmode));
9192 emit_insn (gen_movsi_got (tmp, operands[1]));
9193 emit_insn (gen_addsi3 (operands[0], tmp, offset));
9194 DONE;
9195 }
9196 }
9197
9198 operands[2] = rs6000_got_register (operands[1]);
9199 }")
9200
9201 (define_insn "*movsi_got_internal"
9202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9203 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9204 (match_operand:SI 2 "gpc_reg_operand" "b")]
9205 UNSPEC_MOVSI_GOT))]
9206 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9207 "{l|lwz} %0,%a1@got(%2)"
9208 [(set_attr "type" "load")])
9209
9210 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
9211 ;; didn't get allocated to a hard register.
9212 (define_split
9213 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9214 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9215 (match_operand:SI 2 "memory_operand" "")]
9216 UNSPEC_MOVSI_GOT))]
9217 "DEFAULT_ABI == ABI_V4
9218 && flag_pic == 1
9219 && (reload_in_progress || reload_completed)"
9220 [(set (match_dup 0) (match_dup 2))
9221 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
9222 UNSPEC_MOVSI_GOT))]
9223 "")
9224
9225 ;; For SI, we special-case integers that can't be loaded in one insn. We
9226 ;; do the load 16-bits at a time. We could do this by loading from memory,
9227 ;; and this is even supposed to be faster, but it is simpler not to get
9228 ;; integers in the TOC.
9229 (define_insn "movsi_low"
9230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9231 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9232 (match_operand 2 "" ""))))]
9233 "TARGET_MACHO && ! TARGET_64BIT"
9234 "{l|lwz} %0,lo16(%2)(%1)"
9235 [(set_attr "type" "load")
9236 (set_attr "length" "4")])
9237
9238 (define_insn "*movsi_internal1"
9239 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
9240 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
9241 "!TARGET_SINGLE_FPU &&
9242 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9243 "@
9244 mr %0,%1
9245 {cal|la} %0,%a1
9246 {l%U1%X1|lwz%U1%X1} %0,%1
9247 {st%U0%X0|stw%U0%X0} %1,%0
9248 {lil|li} %0,%1
9249 {liu|lis} %0,%v1
9250 #
9251 {cal|la} %0,%a1
9252 mf%1 %0
9253 mt%0 %1
9254 mt%0 %1
9255 mt%0 %1
9256 {cror 0,0,0|nop}"
9257 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
9258 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
9259
9260 (define_insn "*movsi_internal1_single"
9261 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
9262 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
9263 "TARGET_SINGLE_FPU &&
9264 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9265 "@
9266 mr %0,%1
9267 {cal|la} %0,%a1
9268 {l%U1%X1|lwz%U1%X1} %0,%1
9269 {st%U0%X0|stw%U0%X0} %1,%0
9270 {lil|li} %0,%1
9271 {liu|lis} %0,%v1
9272 #
9273 {cal|la} %0,%a1
9274 mf%1 %0
9275 mt%0 %1
9276 mt%0 %1
9277 mt%0 %1
9278 {cror 0,0,0|nop}
9279 stfs%U0%X0 %1, %0
9280 lfs%U1%X1 %0, %1"
9281 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
9282 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
9283
9284 ;; Split a load of a large constant into the appropriate two-insn
9285 ;; sequence.
9286
9287 (define_split
9288 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9289 (match_operand:SI 1 "const_int_operand" ""))]
9290 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
9291 && (INTVAL (operands[1]) & 0xffff) != 0"
9292 [(set (match_dup 0)
9293 (match_dup 2))
9294 (set (match_dup 0)
9295 (ior:SI (match_dup 0)
9296 (match_dup 3)))]
9297 "
9298 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
9299
9300 if (tem == operands[0])
9301 DONE;
9302 else
9303 FAIL;
9304 }")
9305
9306 (define_insn "*mov<mode>_internal2"
9307 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
9308 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
9309 (const_int 0)))
9310 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
9311 ""
9312 "@
9313 {cmpi|cmp<wd>i} %2,%0,0
9314 mr. %0,%1
9315 #"
9316 [(set_attr "type" "cmp,compare,cmp")
9317 (set_attr "length" "4,4,8")])
9318
9319 (define_split
9320 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9321 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9322 (const_int 0)))
9323 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
9324 "reload_completed"
9325 [(set (match_dup 0) (match_dup 1))
9326 (set (match_dup 2)
9327 (compare:CC (match_dup 0)
9328 (const_int 0)))]
9329 "")
9330 \f
9331 (define_insn "*movhi_internal"
9332 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9333 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9334 "gpc_reg_operand (operands[0], HImode)
9335 || gpc_reg_operand (operands[1], HImode)"
9336 "@
9337 mr %0,%1
9338 lhz%U1%X1 %0,%1
9339 sth%U0%X0 %1,%0
9340 {lil|li} %0,%w1
9341 mf%1 %0
9342 mt%0 %1
9343 mt%0 %1
9344 {cror 0,0,0|nop}"
9345 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9346
9347 (define_expand "mov<mode>"
9348 [(set (match_operand:INT 0 "general_operand" "")
9349 (match_operand:INT 1 "any_operand" ""))]
9350 ""
9351 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9352
9353 (define_insn "*movqi_internal"
9354 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9355 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9356 "gpc_reg_operand (operands[0], QImode)
9357 || gpc_reg_operand (operands[1], QImode)"
9358 "@
9359 mr %0,%1
9360 lbz%U1%X1 %0,%1
9361 stb%U0%X0 %1,%0
9362 {lil|li} %0,%1
9363 mf%1 %0
9364 mt%0 %1
9365 mt%0 %1
9366 {cror 0,0,0|nop}"
9367 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9368 \f
9369 ;; Here is how to move condition codes around. When we store CC data in
9370 ;; an integer register or memory, we store just the high-order 4 bits.
9371 ;; This lets us not shift in the most common case of CR0.
9372 (define_expand "movcc"
9373 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9374 (match_operand:CC 1 "nonimmediate_operand" ""))]
9375 ""
9376 "")
9377
9378 (define_insn "*movcc_internal1"
9379 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
9380 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
9381 "register_operand (operands[0], CCmode)
9382 || register_operand (operands[1], CCmode)"
9383 "@
9384 mcrf %0,%1
9385 mtcrf 128,%1
9386 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
9387 crxor %0,%0,%0
9388 mfcr %0%Q1
9389 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
9390 mr %0,%1
9391 {lil|li} %0,%1
9392 mf%1 %0
9393 mt%0 %1
9394 mt%0 %1
9395 {l%U1%X1|lwz%U1%X1} %0,%1
9396 {st%U0%U1|stw%U0%U1} %1,%0"
9397 [(set (attr "type")
9398 (cond [(eq_attr "alternative" "0,3")
9399 (const_string "cr_logical")
9400 (eq_attr "alternative" "1,2")
9401 (const_string "mtcr")
9402 (eq_attr "alternative" "6,7,9")
9403 (const_string "integer")
9404 (eq_attr "alternative" "8")
9405 (const_string "mfjmpr")
9406 (eq_attr "alternative" "10")
9407 (const_string "mtjmpr")
9408 (eq_attr "alternative" "11")
9409 (const_string "load")
9410 (eq_attr "alternative" "12")
9411 (const_string "store")
9412 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
9413 (const_string "mfcrf")
9414 ]
9415 (const_string "mfcr")))
9416 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
9417 \f
9418 ;; For floating-point, we normally deal with the floating-point registers
9419 ;; unless -msoft-float is used. The sole exception is that parameter passing
9420 ;; can produce floating-point values in fixed-point registers. Unless the
9421 ;; value is a simple constant or already in memory, we deal with this by
9422 ;; allocating memory and copying the value explicitly via that memory location.
9423 (define_expand "movsf"
9424 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9425 (match_operand:SF 1 "any_operand" ""))]
9426 ""
9427 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
9428
9429 (define_split
9430 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9431 (match_operand:SF 1 "const_double_operand" ""))]
9432 "reload_completed
9433 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9434 || (GET_CODE (operands[0]) == SUBREG
9435 && GET_CODE (SUBREG_REG (operands[0])) == REG
9436 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9437 [(set (match_dup 2) (match_dup 3))]
9438 "
9439 {
9440 long l;
9441 REAL_VALUE_TYPE rv;
9442
9443 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9444 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9445
9446 if (! TARGET_POWERPC64)
9447 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9448 else
9449 operands[2] = gen_lowpart (SImode, operands[0]);
9450
9451 operands[3] = gen_int_mode (l, SImode);
9452 }")
9453
9454 (define_insn "*movsf_hardfloat"
9455 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9456 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9457 "(gpc_reg_operand (operands[0], SFmode)
9458 || gpc_reg_operand (operands[1], SFmode))
9459 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9460 "@
9461 mr %0,%1
9462 {l%U1%X1|lwz%U1%X1} %0,%1
9463 {st%U0%X0|stw%U0%X0} %1,%0
9464 fmr %0,%1
9465 lfs%U1%X1 %0,%1
9466 stfs%U0%X0 %1,%0
9467 mt%0 %1
9468 mt%0 %1
9469 mf%1 %0
9470 {cror 0,0,0|nop}
9471 #
9472 #"
9473 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9474 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9475
9476 (define_insn "*movsf_softfloat"
9477 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9478 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9479 "(gpc_reg_operand (operands[0], SFmode)
9480 || gpc_reg_operand (operands[1], SFmode))
9481 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9482 "@
9483 mr %0,%1
9484 mt%0 %1
9485 mt%0 %1
9486 mf%1 %0
9487 {l%U1%X1|lwz%U1%X1} %0,%1
9488 {st%U0%X0|stw%U0%X0} %1,%0
9489 {lil|li} %0,%1
9490 {liu|lis} %0,%v1
9491 {cal|la} %0,%a1
9492 #
9493 #
9494 {cror 0,0,0|nop}"
9495 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9496 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9497
9498 \f
9499 (define_expand "movdf"
9500 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9501 (match_operand:DF 1 "any_operand" ""))]
9502 ""
9503 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9504
9505 (define_split
9506 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9507 (match_operand:DF 1 "const_int_operand" ""))]
9508 "! TARGET_POWERPC64 && reload_completed
9509 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9510 || (GET_CODE (operands[0]) == SUBREG
9511 && GET_CODE (SUBREG_REG (operands[0])) == REG
9512 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9513 [(set (match_dup 2) (match_dup 4))
9514 (set (match_dup 3) (match_dup 1))]
9515 "
9516 {
9517 int endian = (WORDS_BIG_ENDIAN == 0);
9518 HOST_WIDE_INT value = INTVAL (operands[1]);
9519
9520 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9521 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9522 #if HOST_BITS_PER_WIDE_INT == 32
9523 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9524 #else
9525 operands[4] = GEN_INT (value >> 32);
9526 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9527 #endif
9528 }")
9529
9530 (define_split
9531 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9532 (match_operand:DF 1 "const_double_operand" ""))]
9533 "! TARGET_POWERPC64 && reload_completed
9534 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9535 || (GET_CODE (operands[0]) == SUBREG
9536 && GET_CODE (SUBREG_REG (operands[0])) == REG
9537 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9538 [(set (match_dup 2) (match_dup 4))
9539 (set (match_dup 3) (match_dup 5))]
9540 "
9541 {
9542 int endian = (WORDS_BIG_ENDIAN == 0);
9543 long l[2];
9544 REAL_VALUE_TYPE rv;
9545
9546 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9547 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9548
9549 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9550 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9551 operands[4] = gen_int_mode (l[endian], SImode);
9552 operands[5] = gen_int_mode (l[1 - endian], SImode);
9553 }")
9554
9555 (define_split
9556 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9557 (match_operand:DF 1 "const_double_operand" ""))]
9558 "TARGET_POWERPC64 && reload_completed
9559 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9560 || (GET_CODE (operands[0]) == SUBREG
9561 && GET_CODE (SUBREG_REG (operands[0])) == REG
9562 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9563 [(set (match_dup 2) (match_dup 3))]
9564 "
9565 {
9566 int endian = (WORDS_BIG_ENDIAN == 0);
9567 long l[2];
9568 REAL_VALUE_TYPE rv;
9569 #if HOST_BITS_PER_WIDE_INT >= 64
9570 HOST_WIDE_INT val;
9571 #endif
9572
9573 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9574 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9575
9576 operands[2] = gen_lowpart (DImode, operands[0]);
9577 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9578 #if HOST_BITS_PER_WIDE_INT >= 64
9579 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9580 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9581
9582 operands[3] = gen_int_mode (val, DImode);
9583 #else
9584 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9585 #endif
9586 }")
9587
9588 ;; Don't have reload use general registers to load a constant. First,
9589 ;; it might not work if the output operand is the equivalent of
9590 ;; a non-offsettable memref, but also it is less efficient than loading
9591 ;; the constant into an FP register, since it will probably be used there.
9592 ;; The "??" is a kludge until we can figure out a more reasonable way
9593 ;; of handling these non-offsettable values.
9594 (define_insn "*movdf_hardfloat32"
9595 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9596 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9597 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9598 && (gpc_reg_operand (operands[0], DFmode)
9599 || gpc_reg_operand (operands[1], DFmode))"
9600 "*
9601 {
9602 switch (which_alternative)
9603 {
9604 default:
9605 gcc_unreachable ();
9606 case 0:
9607 case 1:
9608 case 2:
9609 return \"#\";
9610 case 3:
9611 case 4:
9612 return \"xxlor %x0,%x1,%x1\";
9613 case 5:
9614 case 6:
9615 return \"lxsd%U1x %x0,%y1\";
9616 case 7:
9617 case 8:
9618 return \"stxsd%U0x %x1,%y0\";
9619 case 9:
9620 return \"fmr %0,%1\";
9621 case 10:
9622 return \"lfd%U1%X1 %0,%1\";
9623 case 11:
9624 return \"stfd%U0%X0 %1,%0\";
9625 case 12:
9626 return \"xxlxor %x0,%x0,%x0\";
9627 case 13:
9628 case 14:
9629 case 15:
9630 return \"#\";
9631 }
9632 }"
9633 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9634 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9635
9636 (define_insn "*movdf_softfloat32"
9637 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9638 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9639 "! TARGET_POWERPC64
9640 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9641 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9642 && (gpc_reg_operand (operands[0], DFmode)
9643 || gpc_reg_operand (operands[1], DFmode))"
9644 "#"
9645 [(set_attr "type" "two,load,store,*,*,*")
9646 (set_attr "length" "8,8,8,8,12,16")])
9647
9648 ; ld/std require word-aligned displacements -> 'Y' constraint.
9649 ; List Y->r and r->Y before r->r for reload.
9650 (define_insn "*movdf_hardfloat64_mfpgpr"
9651 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9652 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9653 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9654 && TARGET_DOUBLE_FLOAT
9655 && (gpc_reg_operand (operands[0], DFmode)
9656 || gpc_reg_operand (operands[1], DFmode))"
9657 "@
9658 std%U0%X0 %1,%0
9659 ld%U1%X1 %0,%1
9660 mr %0,%1
9661 xxlor %x0,%x1,%x1
9662 xxlor %x0,%x1,%x1
9663 lxsd%U1x %x0,%y1
9664 lxsd%U1x %x0,%y1
9665 stxsd%U0x %x1,%y0
9666 stxsd%U0x %x1,%y0
9667 fmr %0,%1
9668 lfd%U1%X1 %0,%1
9669 stfd%U0%X0 %1,%0
9670 xxlxor %x0,%x0,%x0
9671 mt%0 %1
9672 mf%1 %0
9673 {cror 0,0,0|nop}
9674 #
9675 #
9676 #
9677 mftgpr %0,%1
9678 mffgpr %0,%1"
9679 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9680 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9681
9682 ; ld/std require word-aligned displacements -> 'Y' constraint.
9683 ; List Y->r and r->Y before r->r for reload.
9684 (define_insn "*movdf_hardfloat64"
9685 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9686 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9687 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9688 && TARGET_DOUBLE_FLOAT
9689 && (gpc_reg_operand (operands[0], DFmode)
9690 || gpc_reg_operand (operands[1], DFmode))"
9691 "@
9692 std%U0%X0 %1,%0
9693 ld%U1%X1 %0,%1
9694 mr %0,%1
9695 xxlor %x0,%x1,%x1
9696 xxlor %x0,%x1,%x1
9697 lxsd%U1x %x0,%y1
9698 lxsd%U1x %x0,%y1
9699 stxsd%U0x %x1,%y0
9700 stxsd%U0x %x1,%y0
9701 fmr %0,%1
9702 lfd%U1%X1 %0,%1
9703 stfd%U0%X0 %1,%0
9704 xxlxor %x0,%x0,%x0
9705 mt%0 %1
9706 mf%1 %0
9707 {cror 0,0,0|nop}
9708 #
9709 #
9710 #"
9711 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9712 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9713
9714 (define_insn "*movdf_softfloat64"
9715 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9716 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9717 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9718 && (gpc_reg_operand (operands[0], DFmode)
9719 || gpc_reg_operand (operands[1], DFmode))"
9720 "@
9721 ld%U1%X1 %0,%1
9722 std%U0%X0 %1,%0
9723 mr %0,%1
9724 mt%0 %1
9725 mf%1 %0
9726 #
9727 #
9728 #
9729 {cror 0,0,0|nop}"
9730 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9731 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9732 \f
9733 (define_expand "movtf"
9734 [(set (match_operand:TF 0 "general_operand" "")
9735 (match_operand:TF 1 "any_operand" ""))]
9736 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9737 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9738
9739 ; It's important to list the o->f and f->o moves before f->f because
9740 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9741 ; which doesn't make progress. Likewise r->Y must be before r->r.
9742 (define_insn_and_split "*movtf_internal"
9743 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9744 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9745 "!TARGET_IEEEQUAD
9746 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9747 && (gpc_reg_operand (operands[0], TFmode)
9748 || gpc_reg_operand (operands[1], TFmode))"
9749 "#"
9750 "&& reload_completed"
9751 [(pc)]
9752 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9753 [(set_attr "length" "8,8,8,20,20,16")])
9754
9755 (define_insn_and_split "*movtf_softfloat"
9756 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9757 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9758 "!TARGET_IEEEQUAD
9759 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9760 && (gpc_reg_operand (operands[0], TFmode)
9761 || gpc_reg_operand (operands[1], TFmode))"
9762 "#"
9763 "&& reload_completed"
9764 [(pc)]
9765 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9766 [(set_attr "length" "20,20,16")])
9767
9768 (define_expand "extenddftf2"
9769 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9770 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9771 "!TARGET_IEEEQUAD
9772 && TARGET_HARD_FLOAT
9773 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9774 && TARGET_LONG_DOUBLE_128"
9775 {
9776 if (TARGET_E500_DOUBLE)
9777 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9778 else
9779 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9780 DONE;
9781 })
9782
9783 (define_expand "extenddftf2_fprs"
9784 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9785 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9786 (use (match_dup 2))])]
9787 "!TARGET_IEEEQUAD
9788 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9789 && TARGET_LONG_DOUBLE_128"
9790 {
9791 operands[2] = CONST0_RTX (DFmode);
9792 /* Generate GOT reference early for SVR4 PIC. */
9793 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9794 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9795 })
9796
9797 (define_insn_and_split "*extenddftf2_internal"
9798 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9799 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9800 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9801 "!TARGET_IEEEQUAD
9802 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9803 && TARGET_LONG_DOUBLE_128"
9804 "#"
9805 "&& reload_completed"
9806 [(pc)]
9807 {
9808 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9809 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9810 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9811 operands[1]);
9812 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9813 operands[2]);
9814 DONE;
9815 })
9816
9817 (define_expand "extendsftf2"
9818 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9819 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9820 "!TARGET_IEEEQUAD
9821 && TARGET_HARD_FLOAT
9822 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9823 && TARGET_LONG_DOUBLE_128"
9824 {
9825 rtx tmp = gen_reg_rtx (DFmode);
9826 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9827 emit_insn (gen_extenddftf2 (operands[0], tmp));
9828 DONE;
9829 })
9830
9831 (define_expand "trunctfdf2"
9832 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9833 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9834 "!TARGET_IEEEQUAD
9835 && TARGET_HARD_FLOAT
9836 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9837 && TARGET_LONG_DOUBLE_128"
9838 "")
9839
9840 (define_insn_and_split "trunctfdf2_internal1"
9841 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9842 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9843 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9844 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9845 "@
9846 #
9847 fmr %0,%1"
9848 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9849 [(const_int 0)]
9850 {
9851 emit_note (NOTE_INSN_DELETED);
9852 DONE;
9853 }
9854 [(set_attr "type" "fp")])
9855
9856 (define_insn "trunctfdf2_internal2"
9857 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9858 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9859 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9860 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9861 && TARGET_LONG_DOUBLE_128"
9862 "fadd %0,%1,%L1"
9863 [(set_attr "type" "fp")
9864 (set_attr "fp_type" "fp_addsub_d")])
9865
9866 (define_expand "trunctfsf2"
9867 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9868 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9869 "!TARGET_IEEEQUAD
9870 && TARGET_HARD_FLOAT
9871 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9872 && TARGET_LONG_DOUBLE_128"
9873 {
9874 if (TARGET_E500_DOUBLE)
9875 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9876 else
9877 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9878 DONE;
9879 })
9880
9881 (define_insn_and_split "trunctfsf2_fprs"
9882 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9883 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9884 (clobber (match_scratch:DF 2 "=d"))]
9885 "!TARGET_IEEEQUAD
9886 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9887 && TARGET_LONG_DOUBLE_128"
9888 "#"
9889 "&& reload_completed"
9890 [(set (match_dup 2)
9891 (float_truncate:DF (match_dup 1)))
9892 (set (match_dup 0)
9893 (float_truncate:SF (match_dup 2)))]
9894 "")
9895
9896 (define_expand "floatsitf2"
9897 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9898 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9899 "!TARGET_IEEEQUAD
9900 && TARGET_HARD_FLOAT
9901 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9902 && TARGET_LONG_DOUBLE_128"
9903 {
9904 rtx tmp = gen_reg_rtx (DFmode);
9905 expand_float (tmp, operands[1], false);
9906 emit_insn (gen_extenddftf2 (operands[0], tmp));
9907 DONE;
9908 })
9909
9910 ; fadd, but rounding towards zero.
9911 ; This is probably not the optimal code sequence.
9912 (define_insn "fix_trunc_helper"
9913 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9914 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9915 UNSPEC_FIX_TRUNC_TF))
9916 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9917 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9918 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9919 [(set_attr "type" "fp")
9920 (set_attr "length" "20")])
9921
9922 (define_expand "fix_trunctfsi2"
9923 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9924 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9925 "!TARGET_IEEEQUAD
9926 && (TARGET_POWER2 || TARGET_POWERPC)
9927 && TARGET_HARD_FLOAT
9928 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9929 && TARGET_LONG_DOUBLE_128"
9930 {
9931 if (TARGET_E500_DOUBLE)
9932 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9933 else
9934 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9935 DONE;
9936 })
9937
9938 (define_expand "fix_trunctfsi2_fprs"
9939 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9940 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9941 (clobber (match_dup 2))
9942 (clobber (match_dup 3))
9943 (clobber (match_dup 4))
9944 (clobber (match_dup 5))])]
9945 "!TARGET_IEEEQUAD
9946 && (TARGET_POWER2 || TARGET_POWERPC)
9947 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9948 {
9949 operands[2] = gen_reg_rtx (DFmode);
9950 operands[3] = gen_reg_rtx (DFmode);
9951 operands[4] = gen_reg_rtx (DImode);
9952 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9953 })
9954
9955 (define_insn_and_split "*fix_trunctfsi2_internal"
9956 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9957 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9958 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9959 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9960 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9961 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9962 "!TARGET_IEEEQUAD
9963 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9964 "#"
9965 ""
9966 [(pc)]
9967 {
9968 rtx lowword;
9969 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9970
9971 gcc_assert (MEM_P (operands[5]));
9972 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9973
9974 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9975 emit_move_insn (operands[5], operands[4]);
9976 emit_move_insn (operands[0], lowword);
9977 DONE;
9978 })
9979
9980 (define_expand "negtf2"
9981 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9982 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9983 "!TARGET_IEEEQUAD
9984 && TARGET_HARD_FLOAT
9985 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9986 && TARGET_LONG_DOUBLE_128"
9987 "")
9988
9989 (define_insn "negtf2_internal"
9990 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9991 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9992 "!TARGET_IEEEQUAD
9993 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9994 "*
9995 {
9996 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9997 return \"fneg %L0,%L1\;fneg %0,%1\";
9998 else
9999 return \"fneg %0,%1\;fneg %L0,%L1\";
10000 }"
10001 [(set_attr "type" "fp")
10002 (set_attr "length" "8")])
10003
10004 (define_expand "abstf2"
10005 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10006 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10007 "!TARGET_IEEEQUAD
10008 && TARGET_HARD_FLOAT
10009 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10010 && TARGET_LONG_DOUBLE_128"
10011 "
10012 {
10013 rtx label = gen_label_rtx ();
10014 if (TARGET_E500_DOUBLE)
10015 {
10016 if (flag_finite_math_only && !flag_trapping_math)
10017 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
10018 else
10019 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
10020 }
10021 else
10022 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
10023 emit_label (label);
10024 DONE;
10025 }")
10026
10027 (define_expand "abstf2_internal"
10028 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10029 (match_operand:TF 1 "gpc_reg_operand" ""))
10030 (set (match_dup 3) (match_dup 5))
10031 (set (match_dup 5) (abs:DF (match_dup 5)))
10032 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
10033 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
10034 (label_ref (match_operand 2 "" ""))
10035 (pc)))
10036 (set (match_dup 6) (neg:DF (match_dup 6)))]
10037 "!TARGET_IEEEQUAD
10038 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10039 && TARGET_LONG_DOUBLE_128"
10040 "
10041 {
10042 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10043 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10044 operands[3] = gen_reg_rtx (DFmode);
10045 operands[4] = gen_reg_rtx (CCFPmode);
10046 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
10047 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
10048 }")
10049 \f
10050 ;; Next come the multi-word integer load and store and the load and store
10051 ;; multiple insns.
10052
10053 ; List r->r after r->"o<>", otherwise reload will try to reload a
10054 ; non-offsettable address by using r->r which won't make progress.
10055 (define_insn "*movdi_internal32"
10056 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r,?wa")
10057 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF,O"))]
10058 "! TARGET_POWERPC64
10059 && (gpc_reg_operand (operands[0], DImode)
10060 || gpc_reg_operand (operands[1], DImode))"
10061 "@
10062 #
10063 #
10064 #
10065 fmr %0,%1
10066 lfd%U1%X1 %0,%1
10067 stfd%U0%X0 %1,%0
10068 #
10069 xxlxor %x0,%x0,%x0"
10070 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*,vecsimple")])
10071
10072 (define_split
10073 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10074 (match_operand:DI 1 "const_int_operand" ""))]
10075 "! TARGET_POWERPC64 && reload_completed
10076 && gpr_or_gpr_p (operands[0], operands[1])"
10077 [(set (match_dup 2) (match_dup 4))
10078 (set (match_dup 3) (match_dup 1))]
10079 "
10080 {
10081 HOST_WIDE_INT value = INTVAL (operands[1]);
10082 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10083 DImode);
10084 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10085 DImode);
10086 #if HOST_BITS_PER_WIDE_INT == 32
10087 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
10088 #else
10089 operands[4] = GEN_INT (value >> 32);
10090 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10091 #endif
10092 }")
10093
10094 (define_split
10095 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10096 (match_operand:DIFD 1 "input_operand" ""))]
10097 "reload_completed && !TARGET_POWERPC64
10098 && gpr_or_gpr_p (operands[0], operands[1])"
10099 [(pc)]
10100 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10101
10102 (define_insn "*movdi_mfpgpr"
10103 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
10104 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
10105 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
10106 && (gpc_reg_operand (operands[0], DImode)
10107 || gpc_reg_operand (operands[1], DImode))"
10108 "@
10109 mr %0,%1
10110 ld%U1%X1 %0,%1
10111 std%U0%X0 %1,%0
10112 li %0,%1
10113 lis %0,%v1
10114 #
10115 {cal|la} %0,%a1
10116 fmr %0,%1
10117 lfd%U1%X1 %0,%1
10118 stfd%U0%X0 %1,%0
10119 mf%1 %0
10120 mt%0 %1
10121 {cror 0,0,0|nop}
10122 mftgpr %0,%1
10123 mffgpr %0,%1"
10124 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
10125 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
10126
10127 (define_insn "*movdi_internal64"
10128 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,?wa")
10129 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,O"))]
10130 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
10131 && (gpc_reg_operand (operands[0], DImode)
10132 || gpc_reg_operand (operands[1], DImode))"
10133 "@
10134 mr %0,%1
10135 ld%U1%X1 %0,%1
10136 std%U0%X0 %1,%0
10137 li %0,%1
10138 lis %0,%v1
10139 #
10140 {cal|la} %0,%a1
10141 fmr %0,%1
10142 lfd%U1%X1 %0,%1
10143 stfd%U0%X0 %1,%0
10144 mf%1 %0
10145 mt%0 %1
10146 {cror 0,0,0|nop}
10147 xxlxor %x0,%x0,%x0"
10148 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,vecsimple")
10149 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
10150
10151 ;; immediate value valid for a single instruction hiding in a const_double
10152 (define_insn ""
10153 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10154 (match_operand:DI 1 "const_double_operand" "F"))]
10155 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
10156 && GET_CODE (operands[1]) == CONST_DOUBLE
10157 && num_insns_constant (operands[1], DImode) == 1"
10158 "*
10159 {
10160 return ((unsigned HOST_WIDE_INT)
10161 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
10162 ? \"li %0,%1\" : \"lis %0,%v1\";
10163 }")
10164
10165 ;; Generate all one-bits and clear left or right.
10166 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10167 (define_split
10168 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10169 (match_operand:DI 1 "mask64_operand" ""))]
10170 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10171 [(set (match_dup 0) (const_int -1))
10172 (set (match_dup 0)
10173 (and:DI (rotate:DI (match_dup 0)
10174 (const_int 0))
10175 (match_dup 1)))]
10176 "")
10177
10178 ;; Split a load of a large constant into the appropriate five-instruction
10179 ;; sequence. Handle anything in a constant number of insns.
10180 ;; When non-easy constants can go in the TOC, this should use
10181 ;; easy_fp_constant predicate.
10182 (define_split
10183 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10184 (match_operand:DI 1 "const_int_operand" ""))]
10185 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10186 [(set (match_dup 0) (match_dup 2))
10187 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10188 "
10189 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10190
10191 if (tem == operands[0])
10192 DONE;
10193 else
10194 FAIL;
10195 }")
10196
10197 (define_split
10198 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10199 (match_operand:DI 1 "const_double_operand" ""))]
10200 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10201 [(set (match_dup 0) (match_dup 2))
10202 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10203 "
10204 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10205
10206 if (tem == operands[0])
10207 DONE;
10208 else
10209 FAIL;
10210 }")
10211 \f
10212 ;; TImode is similar, except that we usually want to compute the address into
10213 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
10214 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
10215
10216 ;; We say that MQ is clobbered in the last alternative because the first
10217 ;; alternative would never get used otherwise since it would need a reload
10218 ;; while the 2nd alternative would not. We put memory cases first so they
10219 ;; are preferred. Otherwise, we'd try to reload the output instead of
10220 ;; giving the SCRATCH mq.
10221
10222 (define_insn "*movti_power"
10223 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
10224 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
10225 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
10226 "TARGET_POWER && ! TARGET_POWERPC64
10227 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10228 "*
10229 {
10230 switch (which_alternative)
10231 {
10232 default:
10233 gcc_unreachable ();
10234
10235 case 0:
10236 if (TARGET_STRING)
10237 return \"{stsi|stswi} %1,%P0,16\";
10238 case 1:
10239 case 2:
10240 return \"#\";
10241 case 3:
10242 /* If the address is not used in the output, we can use lsi. Otherwise,
10243 fall through to generating four loads. */
10244 if (TARGET_STRING
10245 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10246 return \"{lsi|lswi} %0,%P1,16\";
10247 /* ... fall through ... */
10248 case 4:
10249 case 5:
10250 return \"#\";
10251 }
10252 }"
10253 [(set_attr "type" "store,store,*,load,load,*")])
10254
10255 (define_insn "*movti_string"
10256 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
10257 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
10258 "! TARGET_POWER && ! TARGET_POWERPC64
10259 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10260 "*
10261 {
10262 switch (which_alternative)
10263 {
10264 default:
10265 gcc_unreachable ();
10266 case 0:
10267 if (TARGET_STRING)
10268 return \"{stsi|stswi} %1,%P0,16\";
10269 case 1:
10270 case 2:
10271 return \"#\";
10272 case 3:
10273 /* If the address is not used in the output, we can use lsi. Otherwise,
10274 fall through to generating four loads. */
10275 if (TARGET_STRING
10276 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10277 return \"{lsi|lswi} %0,%P1,16\";
10278 /* ... fall through ... */
10279 case 4:
10280 case 5:
10281 return \"#\";
10282 }
10283 }"
10284 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
10285 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
10286 (const_string "always")
10287 (const_string "conditional")))])
10288
10289 (define_insn "*movti_ppc64"
10290 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
10291 (match_operand:TI 1 "input_operand" "r,r,m"))]
10292 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
10293 || gpc_reg_operand (operands[1], TImode)))
10294 && VECTOR_MEM_NONE_P (TImode)"
10295 "#"
10296 [(set_attr "type" "*,store,load")])
10297
10298 (define_split
10299 [(set (match_operand:TI 0 "gpc_reg_operand" "")
10300 (match_operand:TI 1 "const_double_operand" ""))]
10301 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
10302 [(set (match_dup 2) (match_dup 4))
10303 (set (match_dup 3) (match_dup 5))]
10304 "
10305 {
10306 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10307 TImode);
10308 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10309 TImode);
10310 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10311 {
10312 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10313 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10314 }
10315 else if (GET_CODE (operands[1]) == CONST_INT)
10316 {
10317 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10318 operands[5] = operands[1];
10319 }
10320 else
10321 FAIL;
10322 }")
10323
10324 (define_split
10325 [(set (match_operand:TI 0 "nonimmediate_operand" "")
10326 (match_operand:TI 1 "input_operand" ""))]
10327 "reload_completed && VECTOR_MEM_NONE_P (TImode)
10328 && gpr_or_gpr_p (operands[0], operands[1])"
10329 [(pc)]
10330 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10331 \f
10332 (define_expand "load_multiple"
10333 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10334 (match_operand:SI 1 "" ""))
10335 (use (match_operand:SI 2 "" ""))])]
10336 "TARGET_STRING && !TARGET_POWERPC64"
10337 "
10338 {
10339 int regno;
10340 int count;
10341 rtx op1;
10342 int i;
10343
10344 /* Support only loading a constant number of fixed-point registers from
10345 memory and only bother with this if more than two; the machine
10346 doesn't support more than eight. */
10347 if (GET_CODE (operands[2]) != CONST_INT
10348 || INTVAL (operands[2]) <= 2
10349 || INTVAL (operands[2]) > 8
10350 || GET_CODE (operands[1]) != MEM
10351 || GET_CODE (operands[0]) != REG
10352 || REGNO (operands[0]) >= 32)
10353 FAIL;
10354
10355 count = INTVAL (operands[2]);
10356 regno = REGNO (operands[0]);
10357
10358 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10359 op1 = replace_equiv_address (operands[1],
10360 force_reg (SImode, XEXP (operands[1], 0)));
10361
10362 for (i = 0; i < count; i++)
10363 XVECEXP (operands[3], 0, i)
10364 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10365 adjust_address_nv (op1, SImode, i * 4));
10366 }")
10367
10368 (define_insn "*ldmsi8"
10369 [(match_parallel 0 "load_multiple_operation"
10370 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10371 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10372 (set (match_operand:SI 3 "gpc_reg_operand" "")
10373 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10374 (set (match_operand:SI 4 "gpc_reg_operand" "")
10375 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10376 (set (match_operand:SI 5 "gpc_reg_operand" "")
10377 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10378 (set (match_operand:SI 6 "gpc_reg_operand" "")
10379 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10380 (set (match_operand:SI 7 "gpc_reg_operand" "")
10381 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10382 (set (match_operand:SI 8 "gpc_reg_operand" "")
10383 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10384 (set (match_operand:SI 9 "gpc_reg_operand" "")
10385 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10386 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10387 "*
10388 { return rs6000_output_load_multiple (operands); }"
10389 [(set_attr "type" "load_ux")
10390 (set_attr "length" "32")])
10391
10392 (define_insn "*ldmsi7"
10393 [(match_parallel 0 "load_multiple_operation"
10394 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10395 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10396 (set (match_operand:SI 3 "gpc_reg_operand" "")
10397 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10398 (set (match_operand:SI 4 "gpc_reg_operand" "")
10399 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10400 (set (match_operand:SI 5 "gpc_reg_operand" "")
10401 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10402 (set (match_operand:SI 6 "gpc_reg_operand" "")
10403 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10404 (set (match_operand:SI 7 "gpc_reg_operand" "")
10405 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10406 (set (match_operand:SI 8 "gpc_reg_operand" "")
10407 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10408 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10409 "*
10410 { return rs6000_output_load_multiple (operands); }"
10411 [(set_attr "type" "load_ux")
10412 (set_attr "length" "32")])
10413
10414 (define_insn "*ldmsi6"
10415 [(match_parallel 0 "load_multiple_operation"
10416 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10417 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10418 (set (match_operand:SI 3 "gpc_reg_operand" "")
10419 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10420 (set (match_operand:SI 4 "gpc_reg_operand" "")
10421 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10422 (set (match_operand:SI 5 "gpc_reg_operand" "")
10423 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10424 (set (match_operand:SI 6 "gpc_reg_operand" "")
10425 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10426 (set (match_operand:SI 7 "gpc_reg_operand" "")
10427 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10428 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10429 "*
10430 { return rs6000_output_load_multiple (operands); }"
10431 [(set_attr "type" "load_ux")
10432 (set_attr "length" "32")])
10433
10434 (define_insn "*ldmsi5"
10435 [(match_parallel 0 "load_multiple_operation"
10436 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10437 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10438 (set (match_operand:SI 3 "gpc_reg_operand" "")
10439 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10440 (set (match_operand:SI 4 "gpc_reg_operand" "")
10441 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10442 (set (match_operand:SI 5 "gpc_reg_operand" "")
10443 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10444 (set (match_operand:SI 6 "gpc_reg_operand" "")
10445 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10446 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10447 "*
10448 { return rs6000_output_load_multiple (operands); }"
10449 [(set_attr "type" "load_ux")
10450 (set_attr "length" "32")])
10451
10452 (define_insn "*ldmsi4"
10453 [(match_parallel 0 "load_multiple_operation"
10454 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10455 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10456 (set (match_operand:SI 3 "gpc_reg_operand" "")
10457 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10458 (set (match_operand:SI 4 "gpc_reg_operand" "")
10459 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10460 (set (match_operand:SI 5 "gpc_reg_operand" "")
10461 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10462 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10463 "*
10464 { return rs6000_output_load_multiple (operands); }"
10465 [(set_attr "type" "load_ux")
10466 (set_attr "length" "32")])
10467
10468 (define_insn "*ldmsi3"
10469 [(match_parallel 0 "load_multiple_operation"
10470 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10471 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10472 (set (match_operand:SI 3 "gpc_reg_operand" "")
10473 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10474 (set (match_operand:SI 4 "gpc_reg_operand" "")
10475 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10476 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10477 "*
10478 { return rs6000_output_load_multiple (operands); }"
10479 [(set_attr "type" "load_ux")
10480 (set_attr "length" "32")])
10481
10482 (define_expand "store_multiple"
10483 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10484 (match_operand:SI 1 "" ""))
10485 (clobber (scratch:SI))
10486 (use (match_operand:SI 2 "" ""))])]
10487 "TARGET_STRING && !TARGET_POWERPC64"
10488 "
10489 {
10490 int regno;
10491 int count;
10492 rtx to;
10493 rtx op0;
10494 int i;
10495
10496 /* Support only storing a constant number of fixed-point registers to
10497 memory and only bother with this if more than two; the machine
10498 doesn't support more than eight. */
10499 if (GET_CODE (operands[2]) != CONST_INT
10500 || INTVAL (operands[2]) <= 2
10501 || INTVAL (operands[2]) > 8
10502 || GET_CODE (operands[0]) != MEM
10503 || GET_CODE (operands[1]) != REG
10504 || REGNO (operands[1]) >= 32)
10505 FAIL;
10506
10507 count = INTVAL (operands[2]);
10508 regno = REGNO (operands[1]);
10509
10510 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10511 to = force_reg (SImode, XEXP (operands[0], 0));
10512 op0 = replace_equiv_address (operands[0], to);
10513
10514 XVECEXP (operands[3], 0, 0)
10515 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10516 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10517 gen_rtx_SCRATCH (SImode));
10518
10519 for (i = 1; i < count; i++)
10520 XVECEXP (operands[3], 0, i + 1)
10521 = gen_rtx_SET (VOIDmode,
10522 adjust_address_nv (op0, SImode, i * 4),
10523 gen_rtx_REG (SImode, regno + i));
10524 }")
10525
10526 (define_insn "*stmsi8"
10527 [(match_parallel 0 "store_multiple_operation"
10528 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10529 (match_operand:SI 2 "gpc_reg_operand" "r"))
10530 (clobber (match_scratch:SI 3 "=X"))
10531 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10532 (match_operand:SI 4 "gpc_reg_operand" "r"))
10533 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10534 (match_operand:SI 5 "gpc_reg_operand" "r"))
10535 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10536 (match_operand:SI 6 "gpc_reg_operand" "r"))
10537 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10538 (match_operand:SI 7 "gpc_reg_operand" "r"))
10539 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10540 (match_operand:SI 8 "gpc_reg_operand" "r"))
10541 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10542 (match_operand:SI 9 "gpc_reg_operand" "r"))
10543 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10544 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10545 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10546 "{stsi|stswi} %2,%1,%O0"
10547 [(set_attr "type" "store_ux")
10548 (set_attr "cell_micro" "always")])
10549
10550 (define_insn "*stmsi7"
10551 [(match_parallel 0 "store_multiple_operation"
10552 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10553 (match_operand:SI 2 "gpc_reg_operand" "r"))
10554 (clobber (match_scratch:SI 3 "=X"))
10555 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10556 (match_operand:SI 4 "gpc_reg_operand" "r"))
10557 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10558 (match_operand:SI 5 "gpc_reg_operand" "r"))
10559 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10560 (match_operand:SI 6 "gpc_reg_operand" "r"))
10561 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10562 (match_operand:SI 7 "gpc_reg_operand" "r"))
10563 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10564 (match_operand:SI 8 "gpc_reg_operand" "r"))
10565 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10566 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10567 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10568 "{stsi|stswi} %2,%1,%O0"
10569 [(set_attr "type" "store_ux")
10570 (set_attr "cell_micro" "always")])
10571
10572 (define_insn "*stmsi6"
10573 [(match_parallel 0 "store_multiple_operation"
10574 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10575 (match_operand:SI 2 "gpc_reg_operand" "r"))
10576 (clobber (match_scratch:SI 3 "=X"))
10577 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10578 (match_operand:SI 4 "gpc_reg_operand" "r"))
10579 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10580 (match_operand:SI 5 "gpc_reg_operand" "r"))
10581 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10582 (match_operand:SI 6 "gpc_reg_operand" "r"))
10583 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10584 (match_operand:SI 7 "gpc_reg_operand" "r"))
10585 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10586 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10587 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10588 "{stsi|stswi} %2,%1,%O0"
10589 [(set_attr "type" "store_ux")
10590 (set_attr "cell_micro" "always")])
10591
10592 (define_insn "*stmsi5"
10593 [(match_parallel 0 "store_multiple_operation"
10594 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10595 (match_operand:SI 2 "gpc_reg_operand" "r"))
10596 (clobber (match_scratch:SI 3 "=X"))
10597 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10598 (match_operand:SI 4 "gpc_reg_operand" "r"))
10599 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10600 (match_operand:SI 5 "gpc_reg_operand" "r"))
10601 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10602 (match_operand:SI 6 "gpc_reg_operand" "r"))
10603 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10604 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10605 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10606 "{stsi|stswi} %2,%1,%O0"
10607 [(set_attr "type" "store_ux")
10608 (set_attr "cell_micro" "always")])
10609
10610 (define_insn "*stmsi4"
10611 [(match_parallel 0 "store_multiple_operation"
10612 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10613 (match_operand:SI 2 "gpc_reg_operand" "r"))
10614 (clobber (match_scratch:SI 3 "=X"))
10615 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10616 (match_operand:SI 4 "gpc_reg_operand" "r"))
10617 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10618 (match_operand:SI 5 "gpc_reg_operand" "r"))
10619 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10620 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10621 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10622 "{stsi|stswi} %2,%1,%O0"
10623 [(set_attr "type" "store_ux")
10624 (set_attr "cell_micro" "always")])
10625
10626 (define_insn "*stmsi3"
10627 [(match_parallel 0 "store_multiple_operation"
10628 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10629 (match_operand:SI 2 "gpc_reg_operand" "r"))
10630 (clobber (match_scratch:SI 3 "=X"))
10631 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10632 (match_operand:SI 4 "gpc_reg_operand" "r"))
10633 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10634 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10635 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10636 "{stsi|stswi} %2,%1,%O0"
10637 [(set_attr "type" "store_ux")
10638 (set_attr "cell_micro" "always")])
10639
10640 (define_insn "*stmsi8_power"
10641 [(match_parallel 0 "store_multiple_operation"
10642 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10643 (match_operand:SI 2 "gpc_reg_operand" "r"))
10644 (clobber (match_scratch:SI 3 "=q"))
10645 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10646 (match_operand:SI 4 "gpc_reg_operand" "r"))
10647 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10648 (match_operand:SI 5 "gpc_reg_operand" "r"))
10649 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10650 (match_operand:SI 6 "gpc_reg_operand" "r"))
10651 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10652 (match_operand:SI 7 "gpc_reg_operand" "r"))
10653 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10654 (match_operand:SI 8 "gpc_reg_operand" "r"))
10655 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10656 (match_operand:SI 9 "gpc_reg_operand" "r"))
10657 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10658 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10659 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10660 "{stsi|stswi} %2,%1,%O0"
10661 [(set_attr "type" "store_ux")
10662 (set_attr "cell_micro" "always")])
10663
10664 (define_insn "*stmsi7_power"
10665 [(match_parallel 0 "store_multiple_operation"
10666 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10667 (match_operand:SI 2 "gpc_reg_operand" "r"))
10668 (clobber (match_scratch:SI 3 "=q"))
10669 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10670 (match_operand:SI 4 "gpc_reg_operand" "r"))
10671 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10672 (match_operand:SI 5 "gpc_reg_operand" "r"))
10673 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10674 (match_operand:SI 6 "gpc_reg_operand" "r"))
10675 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10676 (match_operand:SI 7 "gpc_reg_operand" "r"))
10677 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10678 (match_operand:SI 8 "gpc_reg_operand" "r"))
10679 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10680 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10681 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10682 "{stsi|stswi} %2,%1,%O0"
10683 [(set_attr "type" "store_ux")
10684 (set_attr "cell_micro" "always")])
10685
10686 (define_insn "*stmsi6_power"
10687 [(match_parallel 0 "store_multiple_operation"
10688 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10689 (match_operand:SI 2 "gpc_reg_operand" "r"))
10690 (clobber (match_scratch:SI 3 "=q"))
10691 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10692 (match_operand:SI 4 "gpc_reg_operand" "r"))
10693 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10694 (match_operand:SI 5 "gpc_reg_operand" "r"))
10695 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10696 (match_operand:SI 6 "gpc_reg_operand" "r"))
10697 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10698 (match_operand:SI 7 "gpc_reg_operand" "r"))
10699 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10700 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10701 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10702 "{stsi|stswi} %2,%1,%O0"
10703 [(set_attr "type" "store_ux")
10704 (set_attr "cell_micro" "always")])
10705
10706 (define_insn "*stmsi5_power"
10707 [(match_parallel 0 "store_multiple_operation"
10708 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10709 (match_operand:SI 2 "gpc_reg_operand" "r"))
10710 (clobber (match_scratch:SI 3 "=q"))
10711 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10712 (match_operand:SI 4 "gpc_reg_operand" "r"))
10713 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10714 (match_operand:SI 5 "gpc_reg_operand" "r"))
10715 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10716 (match_operand:SI 6 "gpc_reg_operand" "r"))
10717 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10718 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10719 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10720 "{stsi|stswi} %2,%1,%O0"
10721 [(set_attr "type" "store_ux")
10722 (set_attr "cell_micro" "always")])
10723
10724 (define_insn "*stmsi4_power"
10725 [(match_parallel 0 "store_multiple_operation"
10726 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10727 (match_operand:SI 2 "gpc_reg_operand" "r"))
10728 (clobber (match_scratch:SI 3 "=q"))
10729 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10730 (match_operand:SI 4 "gpc_reg_operand" "r"))
10731 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10732 (match_operand:SI 5 "gpc_reg_operand" "r"))
10733 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10734 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10735 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10736 "{stsi|stswi} %2,%1,%O0"
10737 [(set_attr "type" "store_ux")
10738 (set_attr "cell_micro" "always")])
10739
10740 (define_insn "*stmsi3_power"
10741 [(match_parallel 0 "store_multiple_operation"
10742 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10743 (match_operand:SI 2 "gpc_reg_operand" "r"))
10744 (clobber (match_scratch:SI 3 "=q"))
10745 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10746 (match_operand:SI 4 "gpc_reg_operand" "r"))
10747 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10748 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10749 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10750 "{stsi|stswi} %2,%1,%O0"
10751 [(set_attr "type" "store_ux")
10752 (set_attr "cell_micro" "always")])
10753 \f
10754 (define_expand "setmemsi"
10755 [(parallel [(set (match_operand:BLK 0 "" "")
10756 (match_operand 2 "const_int_operand" ""))
10757 (use (match_operand:SI 1 "" ""))
10758 (use (match_operand:SI 3 "" ""))])]
10759 ""
10760 "
10761 {
10762 /* If value to set is not zero, use the library routine. */
10763 if (operands[2] != const0_rtx)
10764 FAIL;
10765
10766 if (expand_block_clear (operands))
10767 DONE;
10768 else
10769 FAIL;
10770 }")
10771
10772 ;; String/block move insn.
10773 ;; Argument 0 is the destination
10774 ;; Argument 1 is the source
10775 ;; Argument 2 is the length
10776 ;; Argument 3 is the alignment
10777
10778 (define_expand "movmemsi"
10779 [(parallel [(set (match_operand:BLK 0 "" "")
10780 (match_operand:BLK 1 "" ""))
10781 (use (match_operand:SI 2 "" ""))
10782 (use (match_operand:SI 3 "" ""))])]
10783 ""
10784 "
10785 {
10786 if (expand_block_move (operands))
10787 DONE;
10788 else
10789 FAIL;
10790 }")
10791
10792 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10793 ;; register allocator doesn't have a clue about allocating 8 word registers.
10794 ;; rD/rS = r5 is preferred, efficient form.
10795 (define_expand "movmemsi_8reg"
10796 [(parallel [(set (match_operand 0 "" "")
10797 (match_operand 1 "" ""))
10798 (use (match_operand 2 "" ""))
10799 (use (match_operand 3 "" ""))
10800 (clobber (reg:SI 5))
10801 (clobber (reg:SI 6))
10802 (clobber (reg:SI 7))
10803 (clobber (reg:SI 8))
10804 (clobber (reg:SI 9))
10805 (clobber (reg:SI 10))
10806 (clobber (reg:SI 11))
10807 (clobber (reg:SI 12))
10808 (clobber (match_scratch:SI 4 ""))])]
10809 "TARGET_STRING"
10810 "")
10811
10812 (define_insn ""
10813 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10814 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10815 (use (match_operand:SI 2 "immediate_operand" "i"))
10816 (use (match_operand:SI 3 "immediate_operand" "i"))
10817 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10818 (clobber (reg:SI 6))
10819 (clobber (reg:SI 7))
10820 (clobber (reg:SI 8))
10821 (clobber (reg:SI 9))
10822 (clobber (reg:SI 10))
10823 (clobber (reg:SI 11))
10824 (clobber (reg:SI 12))
10825 (clobber (match_scratch:SI 5 "=q"))]
10826 "TARGET_STRING && TARGET_POWER
10827 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10828 || INTVAL (operands[2]) == 0)
10829 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10830 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10831 && REGNO (operands[4]) == 5"
10832 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10833 [(set_attr "type" "store_ux")
10834 (set_attr "cell_micro" "always")
10835 (set_attr "length" "8")])
10836
10837 (define_insn ""
10838 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10839 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10840 (use (match_operand:SI 2 "immediate_operand" "i"))
10841 (use (match_operand:SI 3 "immediate_operand" "i"))
10842 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10843 (clobber (reg:SI 6))
10844 (clobber (reg:SI 7))
10845 (clobber (reg:SI 8))
10846 (clobber (reg:SI 9))
10847 (clobber (reg:SI 10))
10848 (clobber (reg:SI 11))
10849 (clobber (reg:SI 12))
10850 (clobber (match_scratch:SI 5 "=X"))]
10851 "TARGET_STRING && ! TARGET_POWER
10852 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10853 || INTVAL (operands[2]) == 0)
10854 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10855 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10856 && REGNO (operands[4]) == 5"
10857 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10858 [(set_attr "type" "store_ux")
10859 (set_attr "cell_micro" "always")
10860 (set_attr "length" "8")])
10861
10862 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10863 ;; register allocator doesn't have a clue about allocating 6 word registers.
10864 ;; rD/rS = r5 is preferred, efficient form.
10865 (define_expand "movmemsi_6reg"
10866 [(parallel [(set (match_operand 0 "" "")
10867 (match_operand 1 "" ""))
10868 (use (match_operand 2 "" ""))
10869 (use (match_operand 3 "" ""))
10870 (clobber (reg:SI 5))
10871 (clobber (reg:SI 6))
10872 (clobber (reg:SI 7))
10873 (clobber (reg:SI 8))
10874 (clobber (reg:SI 9))
10875 (clobber (reg:SI 10))
10876 (clobber (match_scratch:SI 4 ""))])]
10877 "TARGET_STRING"
10878 "")
10879
10880 (define_insn ""
10881 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10882 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10883 (use (match_operand:SI 2 "immediate_operand" "i"))
10884 (use (match_operand:SI 3 "immediate_operand" "i"))
10885 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10886 (clobber (reg:SI 6))
10887 (clobber (reg:SI 7))
10888 (clobber (reg:SI 8))
10889 (clobber (reg:SI 9))
10890 (clobber (reg:SI 10))
10891 (clobber (match_scratch:SI 5 "=q"))]
10892 "TARGET_STRING && TARGET_POWER
10893 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10894 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10895 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10896 && REGNO (operands[4]) == 5"
10897 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10898 [(set_attr "type" "store_ux")
10899 (set_attr "cell_micro" "always")
10900 (set_attr "length" "8")])
10901
10902 (define_insn ""
10903 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10904 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10905 (use (match_operand:SI 2 "immediate_operand" "i"))
10906 (use (match_operand:SI 3 "immediate_operand" "i"))
10907 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10908 (clobber (reg:SI 6))
10909 (clobber (reg:SI 7))
10910 (clobber (reg:SI 8))
10911 (clobber (reg:SI 9))
10912 (clobber (reg:SI 10))
10913 (clobber (match_scratch:SI 5 "=X"))]
10914 "TARGET_STRING && ! TARGET_POWER
10915 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10916 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10917 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10918 && REGNO (operands[4]) == 5"
10919 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10920 [(set_attr "type" "store_ux")
10921 (set_attr "cell_micro" "always")
10922 (set_attr "length" "8")])
10923
10924 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10925 ;; problems with TImode.
10926 ;; rD/rS = r5 is preferred, efficient form.
10927 (define_expand "movmemsi_4reg"
10928 [(parallel [(set (match_operand 0 "" "")
10929 (match_operand 1 "" ""))
10930 (use (match_operand 2 "" ""))
10931 (use (match_operand 3 "" ""))
10932 (clobber (reg:SI 5))
10933 (clobber (reg:SI 6))
10934 (clobber (reg:SI 7))
10935 (clobber (reg:SI 8))
10936 (clobber (match_scratch:SI 4 ""))])]
10937 "TARGET_STRING"
10938 "")
10939
10940 (define_insn ""
10941 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10942 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10943 (use (match_operand:SI 2 "immediate_operand" "i"))
10944 (use (match_operand:SI 3 "immediate_operand" "i"))
10945 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10946 (clobber (reg:SI 6))
10947 (clobber (reg:SI 7))
10948 (clobber (reg:SI 8))
10949 (clobber (match_scratch:SI 5 "=q"))]
10950 "TARGET_STRING && TARGET_POWER
10951 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10952 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10953 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10954 && REGNO (operands[4]) == 5"
10955 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10956 [(set_attr "type" "store_ux")
10957 (set_attr "cell_micro" "always")
10958 (set_attr "length" "8")])
10959
10960 (define_insn ""
10961 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10962 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10963 (use (match_operand:SI 2 "immediate_operand" "i"))
10964 (use (match_operand:SI 3 "immediate_operand" "i"))
10965 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10966 (clobber (reg:SI 6))
10967 (clobber (reg:SI 7))
10968 (clobber (reg:SI 8))
10969 (clobber (match_scratch:SI 5 "=X"))]
10970 "TARGET_STRING && ! TARGET_POWER
10971 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10972 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10973 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10974 && REGNO (operands[4]) == 5"
10975 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10976 [(set_attr "type" "store_ux")
10977 (set_attr "cell_micro" "always")
10978 (set_attr "length" "8")])
10979
10980 ;; Move up to 8 bytes at a time.
10981 (define_expand "movmemsi_2reg"
10982 [(parallel [(set (match_operand 0 "" "")
10983 (match_operand 1 "" ""))
10984 (use (match_operand 2 "" ""))
10985 (use (match_operand 3 "" ""))
10986 (clobber (match_scratch:DI 4 ""))
10987 (clobber (match_scratch:SI 5 ""))])]
10988 "TARGET_STRING && ! TARGET_POWERPC64"
10989 "")
10990
10991 (define_insn ""
10992 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10993 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10994 (use (match_operand:SI 2 "immediate_operand" "i"))
10995 (use (match_operand:SI 3 "immediate_operand" "i"))
10996 (clobber (match_scratch:DI 4 "=&r"))
10997 (clobber (match_scratch:SI 5 "=q"))]
10998 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10999 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11000 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11001 [(set_attr "type" "store_ux")
11002 (set_attr "cell_micro" "always")
11003 (set_attr "length" "8")])
11004
11005 (define_insn ""
11006 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11007 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11008 (use (match_operand:SI 2 "immediate_operand" "i"))
11009 (use (match_operand:SI 3 "immediate_operand" "i"))
11010 (clobber (match_scratch:DI 4 "=&r"))
11011 (clobber (match_scratch:SI 5 "=X"))]
11012 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
11013 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11014 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11015 [(set_attr "type" "store_ux")
11016 (set_attr "cell_micro" "always")
11017 (set_attr "length" "8")])
11018
11019 ;; Move up to 4 bytes at a time.
11020 (define_expand "movmemsi_1reg"
11021 [(parallel [(set (match_operand 0 "" "")
11022 (match_operand 1 "" ""))
11023 (use (match_operand 2 "" ""))
11024 (use (match_operand 3 "" ""))
11025 (clobber (match_scratch:SI 4 ""))
11026 (clobber (match_scratch:SI 5 ""))])]
11027 "TARGET_STRING"
11028 "")
11029
11030 (define_insn ""
11031 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11032 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11033 (use (match_operand:SI 2 "immediate_operand" "i"))
11034 (use (match_operand:SI 3 "immediate_operand" "i"))
11035 (clobber (match_scratch:SI 4 "=&r"))
11036 (clobber (match_scratch:SI 5 "=q"))]
11037 "TARGET_STRING && TARGET_POWER
11038 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11039 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11040 [(set_attr "type" "store_ux")
11041 (set_attr "cell_micro" "always")
11042 (set_attr "length" "8")])
11043
11044 (define_insn ""
11045 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11046 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11047 (use (match_operand:SI 2 "immediate_operand" "i"))
11048 (use (match_operand:SI 3 "immediate_operand" "i"))
11049 (clobber (match_scratch:SI 4 "=&r"))
11050 (clobber (match_scratch:SI 5 "=X"))]
11051 "TARGET_STRING && ! TARGET_POWER
11052 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11053 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11054 [(set_attr "type" "store_ux")
11055 (set_attr "cell_micro" "always")
11056 (set_attr "length" "8")])
11057 \f
11058 ;; Define insns that do load or store with update. Some of these we can
11059 ;; get by using pre-decrement or pre-increment, but the hardware can also
11060 ;; do cases where the increment is not the size of the object.
11061 ;;
11062 ;; In all these cases, we use operands 0 and 1 for the register being
11063 ;; incremented because those are the operands that local-alloc will
11064 ;; tie and these are the pair most likely to be tieable (and the ones
11065 ;; that will benefit the most).
11066
11067 (define_insn "*movdi_update1"
11068 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
11069 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
11070 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
11071 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
11072 (plus:DI (match_dup 1) (match_dup 2)))]
11073 "TARGET_POWERPC64 && TARGET_UPDATE
11074 && (!avoiding_indexed_address_p (DImode)
11075 || !gpc_reg_operand (operands[2], DImode))"
11076 "@
11077 ldux %3,%0,%2
11078 ldu %3,%2(%0)"
11079 [(set_attr "type" "load_ux,load_u")])
11080
11081 (define_insn "movdi_<mode>_update"
11082 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11083 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11084 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11085 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11086 (plus:P (match_dup 1) (match_dup 2)))]
11087 "TARGET_POWERPC64 && TARGET_UPDATE
11088 && (!avoiding_indexed_address_p (Pmode)
11089 || !gpc_reg_operand (operands[2], Pmode)
11090 || (REG_P (operands[0])
11091 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11092 "@
11093 stdux %3,%0,%2
11094 stdu %3,%2(%0)"
11095 [(set_attr "type" "store_ux,store_u")])
11096
11097 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
11098 ;; needed for stack allocation, even if the user passes -mno-update.
11099 (define_insn "movdi_<mode>_update_stack"
11100 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11101 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11102 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11103 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11104 (plus:P (match_dup 1) (match_dup 2)))]
11105 "TARGET_POWERPC64"
11106 "@
11107 stdux %3,%0,%2
11108 stdu %3,%2(%0)"
11109 [(set_attr "type" "store_ux,store_u")])
11110
11111 (define_insn "*movsi_update1"
11112 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11113 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11114 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11115 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11116 (plus:SI (match_dup 1) (match_dup 2)))]
11117 "TARGET_UPDATE
11118 && (!avoiding_indexed_address_p (SImode)
11119 || !gpc_reg_operand (operands[2], SImode))"
11120 "@
11121 {lux|lwzux} %3,%0,%2
11122 {lu|lwzu} %3,%2(%0)"
11123 [(set_attr "type" "load_ux,load_u")])
11124
11125 (define_insn "*movsi_update2"
11126 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
11127 (sign_extend:DI
11128 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
11129 (match_operand:DI 2 "gpc_reg_operand" "r")))))
11130 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
11131 (plus:DI (match_dup 1) (match_dup 2)))]
11132 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
11133 && !avoiding_indexed_address_p (DImode)"
11134 "lwaux %3,%0,%2"
11135 [(set_attr "type" "load_ext_ux")])
11136
11137 (define_insn "movsi_update"
11138 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11139 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11140 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11141 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11142 (plus:SI (match_dup 1) (match_dup 2)))]
11143 "TARGET_UPDATE
11144 && (!avoiding_indexed_address_p (SImode)
11145 || !gpc_reg_operand (operands[2], SImode)
11146 || (REG_P (operands[0])
11147 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11148 "@
11149 {stux|stwux} %3,%0,%2
11150 {stu|stwu} %3,%2(%0)"
11151 [(set_attr "type" "store_ux,store_u")])
11152
11153 ;; This is an unconditional pattern; needed for stack allocation, even
11154 ;; if the user passes -mno-update.
11155 (define_insn "movsi_update_stack"
11156 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11157 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11158 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11159 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11160 (plus:SI (match_dup 1) (match_dup 2)))]
11161 ""
11162 "@
11163 {stux|stwux} %3,%0,%2
11164 {stu|stwu} %3,%2(%0)"
11165 [(set_attr "type" "store_ux,store_u")])
11166
11167 (define_insn "*movhi_update1"
11168 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
11169 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11170 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11171 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11172 (plus:SI (match_dup 1) (match_dup 2)))]
11173 "TARGET_UPDATE
11174 && (!avoiding_indexed_address_p (SImode)
11175 || !gpc_reg_operand (operands[2], SImode))"
11176 "@
11177 lhzux %3,%0,%2
11178 lhzu %3,%2(%0)"
11179 [(set_attr "type" "load_ux,load_u")])
11180
11181 (define_insn "*movhi_update2"
11182 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11183 (zero_extend:SI
11184 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11185 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11186 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11187 (plus:SI (match_dup 1) (match_dup 2)))]
11188 "TARGET_UPDATE
11189 && (!avoiding_indexed_address_p (SImode)
11190 || !gpc_reg_operand (operands[2], SImode))"
11191 "@
11192 lhzux %3,%0,%2
11193 lhzu %3,%2(%0)"
11194 [(set_attr "type" "load_ux,load_u")])
11195
11196 (define_insn "*movhi_update3"
11197 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11198 (sign_extend:SI
11199 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11200 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11201 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11202 (plus:SI (match_dup 1) (match_dup 2)))]
11203 "TARGET_UPDATE && rs6000_gen_cell_microcode
11204 && (!avoiding_indexed_address_p (SImode)
11205 || !gpc_reg_operand (operands[2], SImode))"
11206 "@
11207 lhaux %3,%0,%2
11208 lhau %3,%2(%0)"
11209 [(set_attr "type" "load_ext_ux,load_ext_u")])
11210
11211 (define_insn "*movhi_update4"
11212 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11213 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11214 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11215 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11216 (plus:SI (match_dup 1) (match_dup 2)))]
11217 "TARGET_UPDATE
11218 && (!avoiding_indexed_address_p (SImode)
11219 || !gpc_reg_operand (operands[2], SImode))"
11220 "@
11221 sthux %3,%0,%2
11222 sthu %3,%2(%0)"
11223 [(set_attr "type" "store_ux,store_u")])
11224
11225 (define_insn "*movqi_update1"
11226 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11227 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11228 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11229 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11230 (plus:SI (match_dup 1) (match_dup 2)))]
11231 "TARGET_UPDATE
11232 && (!avoiding_indexed_address_p (SImode)
11233 || !gpc_reg_operand (operands[2], SImode))"
11234 "@
11235 lbzux %3,%0,%2
11236 lbzu %3,%2(%0)"
11237 [(set_attr "type" "load_ux,load_u")])
11238
11239 (define_insn "*movqi_update2"
11240 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11241 (zero_extend:SI
11242 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11243 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11244 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11245 (plus:SI (match_dup 1) (match_dup 2)))]
11246 "TARGET_UPDATE
11247 && (!avoiding_indexed_address_p (SImode)
11248 || !gpc_reg_operand (operands[2], SImode))"
11249 "@
11250 lbzux %3,%0,%2
11251 lbzu %3,%2(%0)"
11252 [(set_attr "type" "load_ux,load_u")])
11253
11254 (define_insn "*movqi_update3"
11255 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11256 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11257 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11258 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11259 (plus:SI (match_dup 1) (match_dup 2)))]
11260 "TARGET_UPDATE
11261 && (!avoiding_indexed_address_p (SImode)
11262 || !gpc_reg_operand (operands[2], SImode))"
11263 "@
11264 stbux %3,%0,%2
11265 stbu %3,%2(%0)"
11266 [(set_attr "type" "store_ux,store_u")])
11267
11268 (define_insn "*movsf_update1"
11269 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11270 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11271 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11272 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11273 (plus:SI (match_dup 1) (match_dup 2)))]
11274 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11275 && (!avoiding_indexed_address_p (SImode)
11276 || !gpc_reg_operand (operands[2], SImode))"
11277 "@
11278 lfsux %3,%0,%2
11279 lfsu %3,%2(%0)"
11280 [(set_attr "type" "fpload_ux,fpload_u")])
11281
11282 (define_insn "*movsf_update2"
11283 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11284 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11285 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11286 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11287 (plus:SI (match_dup 1) (match_dup 2)))]
11288 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11289 && (!avoiding_indexed_address_p (SImode)
11290 || !gpc_reg_operand (operands[2], SImode))"
11291 "@
11292 stfsux %3,%0,%2
11293 stfsu %3,%2(%0)"
11294 [(set_attr "type" "fpstore_ux,fpstore_u")])
11295
11296 (define_insn "*movsf_update3"
11297 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11298 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11299 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11300 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11301 (plus:SI (match_dup 1) (match_dup 2)))]
11302 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11303 && (!avoiding_indexed_address_p (SImode)
11304 || !gpc_reg_operand (operands[2], SImode))"
11305 "@
11306 {lux|lwzux} %3,%0,%2
11307 {lu|lwzu} %3,%2(%0)"
11308 [(set_attr "type" "load_ux,load_u")])
11309
11310 (define_insn "*movsf_update4"
11311 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11312 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11313 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11314 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11315 (plus:SI (match_dup 1) (match_dup 2)))]
11316 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11317 && (!avoiding_indexed_address_p (SImode)
11318 || !gpc_reg_operand (operands[2], SImode))"
11319 "@
11320 {stux|stwux} %3,%0,%2
11321 {stu|stwu} %3,%2(%0)"
11322 [(set_attr "type" "store_ux,store_u")])
11323
11324 (define_insn "*movdf_update1"
11325 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11326 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11327 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11328 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11329 (plus:SI (match_dup 1) (match_dup 2)))]
11330 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11331 && (!avoiding_indexed_address_p (SImode)
11332 || !gpc_reg_operand (operands[2], SImode))"
11333 "@
11334 lfdux %3,%0,%2
11335 lfdu %3,%2(%0)"
11336 [(set_attr "type" "fpload_ux,fpload_u")])
11337
11338 (define_insn "*movdf_update2"
11339 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11340 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11341 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11342 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11343 (plus:SI (match_dup 1) (match_dup 2)))]
11344 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11345 && (!avoiding_indexed_address_p (SImode)
11346 || !gpc_reg_operand (operands[2], SImode))"
11347 "@
11348 stfdux %3,%0,%2
11349 stfdu %3,%2(%0)"
11350 [(set_attr "type" "fpstore_ux,fpstore_u")])
11351
11352 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
11353
11354 (define_insn "*lfq_power2"
11355 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
11356 (match_operand:V2DF 1 "memory_operand" ""))]
11357 "TARGET_POWER2
11358 && TARGET_HARD_FLOAT && TARGET_FPRS"
11359 "lfq%U1%X1 %0,%1")
11360
11361 (define_peephole2
11362 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11363 (match_operand:DF 1 "memory_operand" ""))
11364 (set (match_operand:DF 2 "gpc_reg_operand" "")
11365 (match_operand:DF 3 "memory_operand" ""))]
11366 "TARGET_POWER2
11367 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11368 && registers_ok_for_quad_peep (operands[0], operands[2])
11369 && mems_ok_for_quad_peep (operands[1], operands[3])"
11370 [(set (match_dup 0)
11371 (match_dup 1))]
11372 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
11373 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
11374
11375 (define_insn "*stfq_power2"
11376 [(set (match_operand:V2DF 0 "memory_operand" "")
11377 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
11378 "TARGET_POWER2
11379 && TARGET_HARD_FLOAT && TARGET_FPRS"
11380 "stfq%U0%X0 %1,%0")
11381
11382
11383 (define_peephole2
11384 [(set (match_operand:DF 0 "memory_operand" "")
11385 (match_operand:DF 1 "gpc_reg_operand" ""))
11386 (set (match_operand:DF 2 "memory_operand" "")
11387 (match_operand:DF 3 "gpc_reg_operand" ""))]
11388 "TARGET_POWER2
11389 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11390 && registers_ok_for_quad_peep (operands[1], operands[3])
11391 && mems_ok_for_quad_peep (operands[0], operands[2])"
11392 [(set (match_dup 0)
11393 (match_dup 1))]
11394 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
11395 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
11396
11397 ;; After inserting conditional returns we can sometimes have
11398 ;; unnecessary register moves. Unfortunately we cannot have a
11399 ;; modeless peephole here, because some single SImode sets have early
11400 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11401 ;; sequences, using get_attr_length here will smash the operands
11402 ;; array. Neither is there an early_cobbler_p predicate.
11403 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11404 (define_peephole2
11405 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11406 (match_operand:DF 1 "any_operand" ""))
11407 (set (match_operand:DF 2 "gpc_reg_operand" "")
11408 (match_dup 0))]
11409 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11410 && peep2_reg_dead_p (2, operands[0])"
11411 [(set (match_dup 2) (match_dup 1))])
11412
11413 (define_peephole2
11414 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11415 (match_operand:SF 1 "any_operand" ""))
11416 (set (match_operand:SF 2 "gpc_reg_operand" "")
11417 (match_dup 0))]
11418 "peep2_reg_dead_p (2, operands[0])"
11419 [(set (match_dup 2) (match_dup 1))])
11420
11421 \f
11422 ;; TLS support.
11423
11424 ;; Mode attributes for different ABIs.
11425 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11426 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11427 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11428 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11429
11430 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11431 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11432 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11433 (match_operand 4 "" "g")))
11434 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11435 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11436 UNSPEC_TLSGD)
11437 (clobber (reg:SI LR_REGNO))]
11438 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11439 {
11440 if (TARGET_CMODEL != CMODEL_SMALL)
11441 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
11442 else
11443 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
11444 }
11445 "&& TARGET_TLS_MARKERS"
11446 [(set (match_dup 0)
11447 (unspec:TLSmode [(match_dup 1)
11448 (match_dup 2)]
11449 UNSPEC_TLSGD))
11450 (parallel [(set (match_dup 0)
11451 (call (mem:TLSmode (match_dup 3))
11452 (match_dup 4)))
11453 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11454 (clobber (reg:SI LR_REGNO))])]
11455 ""
11456 [(set_attr "type" "two")
11457 (set (attr "length")
11458 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11459 (const_int 16)
11460 (const_int 12)))])
11461
11462 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11463 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11464 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11465 (match_operand 4 "" "g")))
11466 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11467 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11468 UNSPEC_TLSGD)
11469 (clobber (reg:SI LR_REGNO))]
11470 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11471 {
11472 if (flag_pic)
11473 {
11474 if (TARGET_SECURE_PLT && flag_pic == 2)
11475 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11476 else
11477 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11478 }
11479 else
11480 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11481 }
11482 "&& TARGET_TLS_MARKERS"
11483 [(set (match_dup 0)
11484 (unspec:TLSmode [(match_dup 1)
11485 (match_dup 2)]
11486 UNSPEC_TLSGD))
11487 (parallel [(set (match_dup 0)
11488 (call (mem:TLSmode (match_dup 3))
11489 (match_dup 4)))
11490 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11491 (clobber (reg:SI LR_REGNO))])]
11492 ""
11493 [(set_attr "type" "two")
11494 (set_attr "length" "8")])
11495
11496 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11497 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11498 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11499 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11500 UNSPEC_TLSGD))]
11501 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11502 "addi %0,%1,%2@got@tlsgd"
11503 "&& TARGET_CMODEL != CMODEL_SMALL"
11504 [(set (match_dup 3)
11505 (plus:TLSmode (match_dup 1)
11506 (high:TLSmode
11507 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD))))
11508 (set (match_dup 0)
11509 (lo_sum:TLSmode (match_dup 3)
11510 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
11511 "
11512 {
11513 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11514 }"
11515 [(set (attr "length")
11516 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11517 (const_int 8)
11518 (const_int 4)))])
11519
11520 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11521 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11522 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11523 (high:TLSmode
11524 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11525 UNSPEC_TLSGD))))]
11526 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11527 "addis %0,%1,%2@got@tlsgd@ha"
11528 [(set_attr "length" "4")])
11529
11530 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11531 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11532 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11533 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11534 UNSPEC_TLSGD)))]
11535 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11536 "addi %0,%1,%2@got@tlsgd@l"
11537 [(set_attr "length" "4")])
11538
11539 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11540 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11541 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11542 (match_operand 2 "" "g")))
11543 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11544 UNSPEC_TLSGD)
11545 (clobber (reg:SI LR_REGNO))]
11546 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11547 "bl %z1(%3@tlsgd)\;%."
11548 [(set_attr "type" "branch")
11549 (set_attr "length" "8")])
11550
11551 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11552 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11553 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11554 (match_operand 2 "" "g")))
11555 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11556 UNSPEC_TLSGD)
11557 (clobber (reg:SI LR_REGNO))]
11558 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11559 {
11560 if (flag_pic)
11561 {
11562 if (TARGET_SECURE_PLT && flag_pic == 2)
11563 return "bl %z1+32768(%3@tlsgd)@plt";
11564 return "bl %z1(%3@tlsgd)@plt";
11565 }
11566 return "bl %z1(%3@tlsgd)";
11567 }
11568 [(set_attr "type" "branch")
11569 (set_attr "length" "4")])
11570
11571 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11572 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11573 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11574 (match_operand 3 "" "g")))
11575 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11576 UNSPEC_TLSLD)
11577 (clobber (reg:SI LR_REGNO))]
11578 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11579 {
11580 if (TARGET_CMODEL != CMODEL_SMALL)
11581 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
11582 else
11583 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
11584 }
11585 "&& TARGET_TLS_MARKERS"
11586 [(set (match_dup 0)
11587 (unspec:TLSmode [(match_dup 1)]
11588 UNSPEC_TLSLD))
11589 (parallel [(set (match_dup 0)
11590 (call (mem:TLSmode (match_dup 2))
11591 (match_dup 3)))
11592 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11593 (clobber (reg:SI LR_REGNO))])]
11594 ""
11595 [(set_attr "type" "two")
11596 (set (attr "length")
11597 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11598 (const_int 16)
11599 (const_int 12)))])
11600
11601 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11602 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11603 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11604 (match_operand 3 "" "g")))
11605 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11606 UNSPEC_TLSLD)
11607 (clobber (reg:SI LR_REGNO))]
11608 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11609 {
11610 if (flag_pic)
11611 {
11612 if (TARGET_SECURE_PLT && flag_pic == 2)
11613 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11614 else
11615 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11616 }
11617 else
11618 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11619 }
11620 "&& TARGET_TLS_MARKERS"
11621 [(set (match_dup 0)
11622 (unspec:TLSmode [(match_dup 1)]
11623 UNSPEC_TLSLD))
11624 (parallel [(set (match_dup 0)
11625 (call (mem:TLSmode (match_dup 2))
11626 (match_dup 3)))
11627 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11628 (clobber (reg:SI LR_REGNO))])]
11629 ""
11630 [(set_attr "length" "8")])
11631
11632 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11633 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11634 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11635 UNSPEC_TLSLD))]
11636 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11637 "addi %0,%1,%&@got@tlsld"
11638 "&& TARGET_CMODEL != CMODEL_SMALL"
11639 [(set (match_dup 2)
11640 (plus:TLSmode (match_dup 1)
11641 (high:TLSmode
11642 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))
11643 (set (match_dup 0)
11644 (lo_sum:TLSmode (match_dup 2)
11645 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11646 "
11647 {
11648 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11649 }"
11650 [(set (attr "length")
11651 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11652 (const_int 8)
11653 (const_int 4)))])
11654
11655 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11656 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11657 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11658 (high:TLSmode
11659 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))]
11660 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11661 "addis %0,%1,%&@got@tlsld@ha"
11662 [(set_attr "length" "4")])
11663
11664 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11665 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11666 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11667 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11668 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11669 "addi %0,%1,%&@got@tlsld@l"
11670 [(set_attr "length" "4")])
11671
11672 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11673 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11674 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11675 (match_operand 2 "" "g")))
11676 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11677 (clobber (reg:SI LR_REGNO))]
11678 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11679 "bl %z1(%&@tlsld)\;%."
11680 [(set_attr "type" "branch")
11681 (set_attr "length" "8")])
11682
11683 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11684 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11685 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11686 (match_operand 2 "" "g")))
11687 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11688 (clobber (reg:SI LR_REGNO))]
11689 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11690 {
11691 if (flag_pic)
11692 {
11693 if (TARGET_SECURE_PLT && flag_pic == 2)
11694 return "bl %z1+32768(%&@tlsld)@plt";
11695 return "bl %z1(%&@tlsld)@plt";
11696 }
11697 return "bl %z1(%&@tlsld)";
11698 }
11699 [(set_attr "type" "branch")
11700 (set_attr "length" "4")])
11701
11702 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11703 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11704 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11705 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11706 UNSPEC_TLSDTPREL))]
11707 "HAVE_AS_TLS"
11708 "addi %0,%1,%2@dtprel")
11709
11710 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11711 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11712 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11713 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11714 UNSPEC_TLSDTPRELHA))]
11715 "HAVE_AS_TLS"
11716 "addis %0,%1,%2@dtprel@ha")
11717
11718 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11719 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11720 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11721 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11722 UNSPEC_TLSDTPRELLO))]
11723 "HAVE_AS_TLS"
11724 "addi %0,%1,%2@dtprel@l")
11725
11726 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11727 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11728 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11729 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11730 UNSPEC_TLSGOTDTPREL))]
11731 "HAVE_AS_TLS"
11732 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11733 "&& TARGET_CMODEL != CMODEL_SMALL"
11734 [(set (match_dup 3)
11735 (plus:TLSmode (match_dup 1)
11736 (high:TLSmode
11737 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL))))
11738 (set (match_dup 0)
11739 (lo_sum:TLSmode (match_dup 3)
11740 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11741 "
11742 {
11743 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11744 }"
11745 [(set (attr "length")
11746 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11747 (const_int 8)
11748 (const_int 4)))])
11749
11750 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11751 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11752 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11753 (high:TLSmode
11754 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11755 UNSPEC_TLSGOTDTPREL))))]
11756 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11757 "addis %0,%1,%2@got@dtprel@ha"
11758 [(set_attr "length" "4")])
11759
11760 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11761 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11762 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11763 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11764 UNSPEC_TLSGOTDTPREL)))]
11765 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11766 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11767 [(set_attr "length" "4")])
11768
11769 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11770 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11771 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11772 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11773 UNSPEC_TLSTPREL))]
11774 "HAVE_AS_TLS"
11775 "addi %0,%1,%2@tprel")
11776
11777 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11778 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11779 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11780 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11781 UNSPEC_TLSTPRELHA))]
11782 "HAVE_AS_TLS"
11783 "addis %0,%1,%2@tprel@ha")
11784
11785 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11786 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11787 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11788 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11789 UNSPEC_TLSTPRELLO))]
11790 "HAVE_AS_TLS"
11791 "addi %0,%1,%2@tprel@l")
11792
11793 ;; "b" output constraint here and on tls_tls input to support linker tls
11794 ;; optimization. The linker may edit the instructions emitted by a
11795 ;; tls_got_tprel/tls_tls pair to addis,addi.
11796 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11797 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11798 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11799 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11800 UNSPEC_TLSGOTTPREL))]
11801 "HAVE_AS_TLS"
11802 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11803 "&& TARGET_CMODEL != CMODEL_SMALL"
11804 [(set (match_dup 3)
11805 (plus:TLSmode (match_dup 1)
11806 (high:TLSmode
11807 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL))))
11808 (set (match_dup 0)
11809 (lo_sum:TLSmode (match_dup 3)
11810 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11811 "
11812 {
11813 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11814 }"
11815 [(set (attr "length")
11816 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11817 (const_int 8)
11818 (const_int 4)))])
11819
11820 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11821 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11822 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11823 (high:TLSmode
11824 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11825 UNSPEC_TLSGOTTPREL))))]
11826 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11827 "addis %0,%1,%2@got@tprel@ha"
11828 [(set_attr "length" "4")])
11829
11830 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11831 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11832 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11833 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11834 UNSPEC_TLSGOTTPREL)))]
11835 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11836 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11837 [(set_attr "length" "4")])
11838
11839 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11840 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11841 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11842 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11843 UNSPEC_TLSTLS))]
11844 "HAVE_AS_TLS"
11845 "add %0,%1,%2@tls")
11846 \f
11847 ;; Next come insns related to the calling sequence.
11848 ;;
11849 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11850 ;; We move the back-chain and decrement the stack pointer.
11851
11852 (define_expand "allocate_stack"
11853 [(set (match_operand 0 "gpc_reg_operand" "")
11854 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11855 (set (reg 1)
11856 (minus (reg 1) (match_dup 1)))]
11857 ""
11858 "
11859 { rtx chain = gen_reg_rtx (Pmode);
11860 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11861 rtx neg_op0;
11862 rtx insn, par, set, mem;
11863
11864 emit_move_insn (chain, stack_bot);
11865
11866 /* Check stack bounds if necessary. */
11867 if (crtl->limit_stack)
11868 {
11869 rtx available;
11870 available = expand_binop (Pmode, sub_optab,
11871 stack_pointer_rtx, stack_limit_rtx,
11872 NULL_RTX, 1, OPTAB_WIDEN);
11873 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11874 }
11875
11876 if (GET_CODE (operands[1]) != CONST_INT
11877 || INTVAL (operands[1]) < -32767
11878 || INTVAL (operands[1]) > 32768)
11879 {
11880 neg_op0 = gen_reg_rtx (Pmode);
11881 if (TARGET_32BIT)
11882 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11883 else
11884 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11885 }
11886 else
11887 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11888
11889 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11890 : gen_movdi_di_update_stack))
11891 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11892 chain));
11893 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11894 it now and set the alias set/attributes. The above gen_*_update
11895 calls will generate a PARALLEL with the MEM set being the first
11896 operation. */
11897 par = PATTERN (insn);
11898 gcc_assert (GET_CODE (par) == PARALLEL);
11899 set = XVECEXP (par, 0, 0);
11900 gcc_assert (GET_CODE (set) == SET);
11901 mem = SET_DEST (set);
11902 gcc_assert (MEM_P (mem));
11903 MEM_NOTRAP_P (mem) = 1;
11904 set_mem_alias_set (mem, get_frame_alias_set ());
11905
11906 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11907 DONE;
11908 }")
11909
11910 ;; These patterns say how to save and restore the stack pointer. We need not
11911 ;; save the stack pointer at function level since we are careful to
11912 ;; preserve the backchain. At block level, we have to restore the backchain
11913 ;; when we restore the stack pointer.
11914 ;;
11915 ;; For nonlocal gotos, we must save both the stack pointer and its
11916 ;; backchain and restore both. Note that in the nonlocal case, the
11917 ;; save area is a memory location.
11918
11919 (define_expand "save_stack_function"
11920 [(match_operand 0 "any_operand" "")
11921 (match_operand 1 "any_operand" "")]
11922 ""
11923 "DONE;")
11924
11925 (define_expand "restore_stack_function"
11926 [(match_operand 0 "any_operand" "")
11927 (match_operand 1 "any_operand" "")]
11928 ""
11929 "DONE;")
11930
11931 ;; Adjust stack pointer (op0) to a new value (op1).
11932 ;; First copy old stack backchain to new location, and ensure that the
11933 ;; scheduler won't reorder the sp assignment before the backchain write.
11934 (define_expand "restore_stack_block"
11935 [(set (match_dup 2) (match_dup 3))
11936 (set (match_dup 4) (match_dup 2))
11937 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11938 (set (match_operand 0 "register_operand" "")
11939 (match_operand 1 "register_operand" ""))]
11940 ""
11941 "
11942 {
11943 operands[1] = force_reg (Pmode, operands[1]);
11944 operands[2] = gen_reg_rtx (Pmode);
11945 operands[3] = gen_frame_mem (Pmode, operands[0]);
11946 operands[4] = gen_frame_mem (Pmode, operands[1]);
11947 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11948 }")
11949
11950 (define_expand "save_stack_nonlocal"
11951 [(set (match_dup 3) (match_dup 4))
11952 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11953 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11954 ""
11955 "
11956 {
11957 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11958
11959 /* Copy the backchain to the first word, sp to the second. */
11960 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11961 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11962 operands[3] = gen_reg_rtx (Pmode);
11963 operands[4] = gen_frame_mem (Pmode, operands[1]);
11964 }")
11965
11966 (define_expand "restore_stack_nonlocal"
11967 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11968 (set (match_dup 3) (match_dup 4))
11969 (set (match_dup 5) (match_dup 2))
11970 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11971 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11972 ""
11973 "
11974 {
11975 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11976
11977 /* Restore the backchain from the first word, sp from the second. */
11978 operands[2] = gen_reg_rtx (Pmode);
11979 operands[3] = gen_reg_rtx (Pmode);
11980 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11981 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11982 operands[5] = gen_frame_mem (Pmode, operands[3]);
11983 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11984 }")
11985 \f
11986 ;; TOC register handling.
11987
11988 ;; Code to initialize the TOC register...
11989
11990 (define_insn "load_toc_aix_si"
11991 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11992 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11993 (use (reg:SI 2))])]
11994 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11995 "*
11996 {
11997 char buf[30];
11998 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11999 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12000 operands[2] = gen_rtx_REG (Pmode, 2);
12001 return \"{l|lwz} %0,%1(%2)\";
12002 }"
12003 [(set_attr "type" "load")])
12004
12005 (define_insn "load_toc_aix_di"
12006 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12007 (unspec:DI [(const_int 0)] UNSPEC_TOC))
12008 (use (reg:DI 2))])]
12009 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
12010 "*
12011 {
12012 char buf[30];
12013 #ifdef TARGET_RELOCATABLE
12014 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
12015 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
12016 #else
12017 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12018 #endif
12019 if (TARGET_ELF)
12020 strcat (buf, \"@toc\");
12021 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12022 operands[2] = gen_rtx_REG (Pmode, 2);
12023 return \"ld %0,%1(%2)\";
12024 }"
12025 [(set_attr "type" "load")])
12026
12027 (define_insn "load_toc_v4_pic_si"
12028 [(set (reg:SI LR_REGNO)
12029 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
12030 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
12031 "bl _GLOBAL_OFFSET_TABLE_@local-4"
12032 [(set_attr "type" "branch")
12033 (set_attr "length" "4")])
12034
12035 (define_insn "load_toc_v4_PIC_1"
12036 [(set (reg:SI LR_REGNO)
12037 (match_operand:SI 0 "immediate_operand" "s"))
12038 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12039 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
12040 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12041 "bcl 20,31,%0\\n%0:"
12042 [(set_attr "type" "branch")
12043 (set_attr "length" "4")])
12044
12045 (define_insn "load_toc_v4_PIC_1b"
12046 [(set (reg:SI LR_REGNO)
12047 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12048 (label_ref (match_operand 1 "" ""))]
12049 UNSPEC_TOCPTR))
12050 (match_dup 1)]
12051 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12052 "bcl 20,31,$+8\;.long %0-$"
12053 [(set_attr "type" "branch")
12054 (set_attr "length" "8")])
12055
12056 (define_insn "load_toc_v4_PIC_2"
12057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12058 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12059 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
12060 (match_operand:SI 3 "immediate_operand" "s")))))]
12061 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12062 "{l|lwz} %0,%2-%3(%1)"
12063 [(set_attr "type" "load")])
12064
12065 (define_insn "load_toc_v4_PIC_3b"
12066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12067 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12068 (high:SI
12069 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12070 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
12071 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12072 "{cau|addis} %0,%1,%2-%3@ha")
12073
12074 (define_insn "load_toc_v4_PIC_3c"
12075 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12076 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12077 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12078 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
12079 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12080 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
12081
12082 ;; If the TOC is shared over a translation unit, as happens with all
12083 ;; the kinds of PIC that we support, we need to restore the TOC
12084 ;; pointer only when jumping over units of translation.
12085 ;; On Darwin, we need to reload the picbase.
12086
12087 (define_expand "builtin_setjmp_receiver"
12088 [(use (label_ref (match_operand 0 "" "")))]
12089 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12090 || (TARGET_TOC && TARGET_MINIMAL_TOC)
12091 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
12092 "
12093 {
12094 #if TARGET_MACHO
12095 if (DEFAULT_ABI == ABI_DARWIN)
12096 {
12097 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
12098 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12099 rtx tmplabrtx;
12100 char tmplab[20];
12101
12102 crtl->uses_pic_offset_table = 1;
12103 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
12104 CODE_LABEL_NUMBER (operands[0]));
12105 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
12106
12107 emit_insn (gen_load_macho_picbase (tmplabrtx));
12108 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
12109 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12110 }
12111 else
12112 #endif
12113 rs6000_emit_load_toc_table (FALSE);
12114 DONE;
12115 }")
12116
12117 ;; Elf specific ways of loading addresses for non-PIC code.
12118 ;; The output of this could be r0, but we make a very strong
12119 ;; preference for a base register because it will usually
12120 ;; be needed there.
12121 (define_insn "elf_high"
12122 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12123 (high:SI (match_operand 1 "" "")))]
12124 "TARGET_ELF && ! TARGET_64BIT"
12125 "{liu|lis} %0,%1@ha")
12126
12127 (define_insn "elf_low"
12128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12129 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12130 (match_operand 2 "" "")))]
12131 "TARGET_ELF && ! TARGET_64BIT"
12132 "@
12133 {cal|la} %0,%2@l(%1)
12134 {ai|addic} %0,%1,%K2")
12135
12136 ;; Largetoc support
12137 (define_insn "largetoc_high"
12138 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
12139 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12140 (high:DI (match_operand:DI 2 "" ""))))]
12141 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12142 "{cau|addis} %0,%1,%2@ha")
12143
12144 (define_insn "largetoc_low"
12145 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12146 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12147 (match_operand:DI 2 "" "")))]
12148 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12149 "{cal %0,%2@l(%1)|addi %0,%1,%2@l}")
12150 \f
12151 ;; A function pointer under AIX is a pointer to a data area whose first word
12152 ;; contains the actual address of the function, whose second word contains a
12153 ;; pointer to its TOC, and whose third word contains a value to place in the
12154 ;; static chain register (r11). Note that if we load the static chain, our
12155 ;; "trampoline" need not have any executable code.
12156
12157 (define_expand "call_indirect_aix32"
12158 [(set (match_dup 2)
12159 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
12160 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
12161 (reg:SI 2))
12162 (set (reg:SI 11)
12163 (mem:SI (plus:SI (match_dup 0)
12164 (const_int 8))))
12165 (parallel [(call (mem:SI (match_dup 2))
12166 (match_operand 1 "" ""))
12167 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
12168 (use (reg:SI 11))
12169 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12170 (clobber (reg:SI LR_REGNO))])]
12171 "TARGET_32BIT"
12172 "
12173 { operands[2] = gen_reg_rtx (SImode); }")
12174
12175 (define_expand "call_indirect_aix64"
12176 [(set (match_dup 2)
12177 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
12178 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
12179 (reg:DI 2))
12180 (set (reg:DI 11)
12181 (mem:DI (plus:DI (match_dup 0)
12182 (const_int 16))))
12183 (parallel [(call (mem:SI (match_dup 2))
12184 (match_operand 1 "" ""))
12185 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
12186 (use (reg:DI 11))
12187 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12188 (clobber (reg:SI LR_REGNO))])]
12189 "TARGET_64BIT"
12190 "
12191 { operands[2] = gen_reg_rtx (DImode); }")
12192
12193 (define_expand "call_value_indirect_aix32"
12194 [(set (match_dup 3)
12195 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12196 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
12197 (reg:SI 2))
12198 (set (reg:SI 11)
12199 (mem:SI (plus:SI (match_dup 1)
12200 (const_int 8))))
12201 (parallel [(set (match_operand 0 "" "")
12202 (call (mem:SI (match_dup 3))
12203 (match_operand 2 "" "")))
12204 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
12205 (use (reg:SI 11))
12206 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12207 (clobber (reg:SI LR_REGNO))])]
12208 "TARGET_32BIT"
12209 "
12210 { operands[3] = gen_reg_rtx (SImode); }")
12211
12212 (define_expand "call_value_indirect_aix64"
12213 [(set (match_dup 3)
12214 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12215 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
12216 (reg:DI 2))
12217 (set (reg:DI 11)
12218 (mem:DI (plus:DI (match_dup 1)
12219 (const_int 16))))
12220 (parallel [(set (match_operand 0 "" "")
12221 (call (mem:SI (match_dup 3))
12222 (match_operand 2 "" "")))
12223 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
12224 (use (reg:DI 11))
12225 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12226 (clobber (reg:SI LR_REGNO))])]
12227 "TARGET_64BIT"
12228 "
12229 { operands[3] = gen_reg_rtx (DImode); }")
12230
12231 ;; Now the definitions for the call and call_value insns
12232 (define_expand "call"
12233 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12234 (match_operand 1 "" ""))
12235 (use (match_operand 2 "" ""))
12236 (clobber (reg:SI LR_REGNO))])]
12237 ""
12238 "
12239 {
12240 #if TARGET_MACHO
12241 if (MACHOPIC_INDIRECT)
12242 operands[0] = machopic_indirect_call_target (operands[0]);
12243 #endif
12244
12245 gcc_assert (GET_CODE (operands[0]) == MEM);
12246 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12247
12248 operands[0] = XEXP (operands[0], 0);
12249
12250 if (GET_CODE (operands[0]) != SYMBOL_REF
12251 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
12252 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12253 {
12254 if (INTVAL (operands[2]) & CALL_LONG)
12255 operands[0] = rs6000_longcall_ref (operands[0]);
12256
12257 switch (DEFAULT_ABI)
12258 {
12259 case ABI_V4:
12260 case ABI_DARWIN:
12261 operands[0] = force_reg (Pmode, operands[0]);
12262 break;
12263
12264 case ABI_AIX:
12265 /* AIX function pointers are really pointers to a three word
12266 area. */
12267 emit_call_insn (TARGET_32BIT
12268 ? gen_call_indirect_aix32 (force_reg (SImode,
12269 operands[0]),
12270 operands[1])
12271 : gen_call_indirect_aix64 (force_reg (DImode,
12272 operands[0]),
12273 operands[1]));
12274 DONE;
12275
12276 default:
12277 gcc_unreachable ();
12278 }
12279 }
12280 }")
12281
12282 (define_expand "call_value"
12283 [(parallel [(set (match_operand 0 "" "")
12284 (call (mem:SI (match_operand 1 "address_operand" ""))
12285 (match_operand 2 "" "")))
12286 (use (match_operand 3 "" ""))
12287 (clobber (reg:SI LR_REGNO))])]
12288 ""
12289 "
12290 {
12291 #if TARGET_MACHO
12292 if (MACHOPIC_INDIRECT)
12293 operands[1] = machopic_indirect_call_target (operands[1]);
12294 #endif
12295
12296 gcc_assert (GET_CODE (operands[1]) == MEM);
12297 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12298
12299 operands[1] = XEXP (operands[1], 0);
12300
12301 if (GET_CODE (operands[1]) != SYMBOL_REF
12302 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
12303 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12304 {
12305 if (INTVAL (operands[3]) & CALL_LONG)
12306 operands[1] = rs6000_longcall_ref (operands[1]);
12307
12308 switch (DEFAULT_ABI)
12309 {
12310 case ABI_V4:
12311 case ABI_DARWIN:
12312 operands[1] = force_reg (Pmode, operands[1]);
12313 break;
12314
12315 case ABI_AIX:
12316 /* AIX function pointers are really pointers to a three word
12317 area. */
12318 emit_call_insn (TARGET_32BIT
12319 ? gen_call_value_indirect_aix32 (operands[0],
12320 force_reg (SImode,
12321 operands[1]),
12322 operands[2])
12323 : gen_call_value_indirect_aix64 (operands[0],
12324 force_reg (DImode,
12325 operands[1]),
12326 operands[2]));
12327 DONE;
12328
12329 default:
12330 gcc_unreachable ();
12331 }
12332 }
12333 }")
12334
12335 ;; Call to function in current module. No TOC pointer reload needed.
12336 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12337 ;; either the function was not prototyped, or it was prototyped as a
12338 ;; variable argument function. It is > 0 if FP registers were passed
12339 ;; and < 0 if they were not.
12340
12341 (define_insn "*call_local32"
12342 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12343 (match_operand 1 "" "g,g"))
12344 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12345 (clobber (reg:SI LR_REGNO))]
12346 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12347 "*
12348 {
12349 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12350 output_asm_insn (\"crxor 6,6,6\", operands);
12351
12352 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12353 output_asm_insn (\"creqv 6,6,6\", operands);
12354
12355 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12356 }"
12357 [(set_attr "type" "branch")
12358 (set_attr "length" "4,8")])
12359
12360 (define_insn "*call_local64"
12361 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12362 (match_operand 1 "" "g,g"))
12363 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12364 (clobber (reg:SI LR_REGNO))]
12365 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12366 "*
12367 {
12368 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12369 output_asm_insn (\"crxor 6,6,6\", operands);
12370
12371 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12372 output_asm_insn (\"creqv 6,6,6\", operands);
12373
12374 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12375 }"
12376 [(set_attr "type" "branch")
12377 (set_attr "length" "4,8")])
12378
12379 (define_insn "*call_value_local32"
12380 [(set (match_operand 0 "" "")
12381 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12382 (match_operand 2 "" "g,g")))
12383 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12384 (clobber (reg:SI LR_REGNO))]
12385 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12386 "*
12387 {
12388 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12389 output_asm_insn (\"crxor 6,6,6\", operands);
12390
12391 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12392 output_asm_insn (\"creqv 6,6,6\", operands);
12393
12394 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12395 }"
12396 [(set_attr "type" "branch")
12397 (set_attr "length" "4,8")])
12398
12399
12400 (define_insn "*call_value_local64"
12401 [(set (match_operand 0 "" "")
12402 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12403 (match_operand 2 "" "g,g")))
12404 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12405 (clobber (reg:SI LR_REGNO))]
12406 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12407 "*
12408 {
12409 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12410 output_asm_insn (\"crxor 6,6,6\", operands);
12411
12412 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12413 output_asm_insn (\"creqv 6,6,6\", operands);
12414
12415 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12416 }"
12417 [(set_attr "type" "branch")
12418 (set_attr "length" "4,8")])
12419
12420 ;; Call to function which may be in another module. Restore the TOC
12421 ;; pointer (r2) after the call unless this is System V.
12422 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12423 ;; either the function was not prototyped, or it was prototyped as a
12424 ;; variable argument function. It is > 0 if FP registers were passed
12425 ;; and < 0 if they were not.
12426
12427 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
12428 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
12429 (match_operand 1 "" "g,g"))
12430 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
12431 (use (reg:SI 11))
12432 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12433 (clobber (reg:SI LR_REGNO))]
12434 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12435 "#"
12436 "&& reload_completed"
12437 [(set (reg:SI 2)
12438 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
12439 (parallel [(call (mem:SI (match_dup 0))
12440 (match_dup 1))
12441 (use (reg:SI 2))
12442 (use (reg:SI 11))
12443 (set (reg:SI 2)
12444 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12445 (clobber (reg:SI LR_REGNO))])]
12446 ""
12447 [(set_attr "type" "jmpreg")
12448 (set_attr "length" "12")])
12449
12450 (define_insn "*call_indirect_nonlocal_aix32"
12451 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
12452 (match_operand 1 "" "g,g"))
12453 (use (reg:SI 2))
12454 (use (reg:SI 11))
12455 (set (reg:SI 2)
12456 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12457 (clobber (reg:SI LR_REGNO))]
12458 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12459 "b%T0l\;{l|lwz} 2,20(1)"
12460 [(set_attr "type" "jmpreg")
12461 (set_attr "length" "8")])
12462
12463 (define_insn "*call_nonlocal_aix32"
12464 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12465 (match_operand 1 "" "g"))
12466 (use (match_operand:SI 2 "immediate_operand" "O"))
12467 (clobber (reg:SI LR_REGNO))]
12468 "TARGET_32BIT
12469 && DEFAULT_ABI == ABI_AIX
12470 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12471 "bl %z0\;%."
12472 [(set_attr "type" "branch")
12473 (set_attr "length" "8")])
12474
12475 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
12476 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12477 (match_operand 1 "" "g,g"))
12478 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
12479 (const_int 8))))
12480 (use (reg:DI 11))
12481 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12482 (clobber (reg:SI LR_REGNO))]
12483 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12484 "#"
12485 "&& reload_completed"
12486 [(set (reg:DI 2)
12487 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
12488 (parallel [(call (mem:SI (match_dup 0))
12489 (match_dup 1))
12490 (use (reg:DI 2))
12491 (use (reg:DI 11))
12492 (set (reg:DI 2)
12493 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12494 (clobber (reg:SI LR_REGNO))])]
12495 ""
12496 [(set_attr "type" "jmpreg")
12497 (set_attr "length" "12")])
12498
12499 (define_insn "*call_indirect_nonlocal_aix64"
12500 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12501 (match_operand 1 "" "g,g"))
12502 (use (reg:DI 2))
12503 (use (reg:DI 11))
12504 (set (reg:DI 2)
12505 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12506 (clobber (reg:SI LR_REGNO))]
12507 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12508 "b%T0l\;ld 2,40(1)"
12509 [(set_attr "type" "jmpreg")
12510 (set_attr "length" "8")])
12511
12512 (define_insn "*call_nonlocal_aix64"
12513 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12514 (match_operand 1 "" "g"))
12515 (use (match_operand:SI 2 "immediate_operand" "O"))
12516 (clobber (reg:SI LR_REGNO))]
12517 "TARGET_64BIT
12518 && DEFAULT_ABI == ABI_AIX
12519 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12520 "bl %z0\;%."
12521 [(set_attr "type" "branch")
12522 (set_attr "length" "8")])
12523
12524 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
12525 [(set (match_operand 0 "" "")
12526 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12527 (match_operand 2 "" "g,g")))
12528 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
12529 (const_int 4))))
12530 (use (reg:SI 11))
12531 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12532 (clobber (reg:SI LR_REGNO))]
12533 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12534 "#"
12535 "&& reload_completed"
12536 [(set (reg:SI 2)
12537 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
12538 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12539 (match_dup 2)))
12540 (use (reg:SI 2))
12541 (use (reg:SI 11))
12542 (set (reg:SI 2)
12543 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12544 (clobber (reg:SI LR_REGNO))])]
12545 ""
12546 [(set_attr "type" "jmpreg")
12547 (set_attr "length" "12")])
12548
12549 (define_insn "*call_value_indirect_nonlocal_aix32"
12550 [(set (match_operand 0 "" "")
12551 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12552 (match_operand 2 "" "g,g")))
12553 (use (reg:SI 2))
12554 (use (reg:SI 11))
12555 (set (reg:SI 2)
12556 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12557 (clobber (reg:SI LR_REGNO))]
12558 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12559 "b%T1l\;{l|lwz} 2,20(1)"
12560 [(set_attr "type" "jmpreg")
12561 (set_attr "length" "8")])
12562
12563 (define_insn "*call_value_nonlocal_aix32"
12564 [(set (match_operand 0 "" "")
12565 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12566 (match_operand 2 "" "g")))
12567 (use (match_operand:SI 3 "immediate_operand" "O"))
12568 (clobber (reg:SI LR_REGNO))]
12569 "TARGET_32BIT
12570 && DEFAULT_ABI == ABI_AIX
12571 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12572 "bl %z1\;%."
12573 [(set_attr "type" "branch")
12574 (set_attr "length" "8")])
12575
12576 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
12577 [(set (match_operand 0 "" "")
12578 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12579 (match_operand 2 "" "g,g")))
12580 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
12581 (const_int 8))))
12582 (use (reg:DI 11))
12583 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12584 (clobber (reg:SI LR_REGNO))]
12585 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12586 "#"
12587 "&& reload_completed"
12588 [(set (reg:DI 2)
12589 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
12590 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12591 (match_dup 2)))
12592 (use (reg:DI 2))
12593 (use (reg:DI 11))
12594 (set (reg:DI 2)
12595 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12596 (clobber (reg:SI LR_REGNO))])]
12597 ""
12598 [(set_attr "type" "jmpreg")
12599 (set_attr "length" "12")])
12600
12601 (define_insn "*call_value_indirect_nonlocal_aix64"
12602 [(set (match_operand 0 "" "")
12603 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12604 (match_operand 2 "" "g,g")))
12605 (use (reg:DI 2))
12606 (use (reg:DI 11))
12607 (set (reg:DI 2)
12608 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12609 (clobber (reg:SI LR_REGNO))]
12610 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12611 "b%T1l\;ld 2,40(1)"
12612 [(set_attr "type" "jmpreg")
12613 (set_attr "length" "8")])
12614
12615 (define_insn "*call_value_nonlocal_aix64"
12616 [(set (match_operand 0 "" "")
12617 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12618 (match_operand 2 "" "g")))
12619 (use (match_operand:SI 3 "immediate_operand" "O"))
12620 (clobber (reg:SI LR_REGNO))]
12621 "TARGET_64BIT
12622 && DEFAULT_ABI == ABI_AIX
12623 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12624 "bl %z1\;%."
12625 [(set_attr "type" "branch")
12626 (set_attr "length" "8")])
12627
12628 ;; A function pointer under System V is just a normal pointer
12629 ;; operands[0] is the function pointer
12630 ;; operands[1] is the stack size to clean up
12631 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12632 ;; which indicates how to set cr1
12633
12634 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12635 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12636 (match_operand 1 "" "g,g,g,g"))
12637 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12638 (clobber (reg:SI LR_REGNO))]
12639 "DEFAULT_ABI == ABI_V4
12640 || DEFAULT_ABI == ABI_DARWIN"
12641 {
12642 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12643 output_asm_insn ("crxor 6,6,6", operands);
12644
12645 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12646 output_asm_insn ("creqv 6,6,6", operands);
12647
12648 return "b%T0l";
12649 }
12650 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12651 (set_attr "length" "4,4,8,8")])
12652
12653 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12654 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12655 (match_operand 1 "" "g,g"))
12656 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12657 (clobber (reg:SI LR_REGNO))]
12658 "(DEFAULT_ABI == ABI_DARWIN
12659 || (DEFAULT_ABI == ABI_V4
12660 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12661 {
12662 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12663 output_asm_insn ("crxor 6,6,6", operands);
12664
12665 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12666 output_asm_insn ("creqv 6,6,6", operands);
12667
12668 #if TARGET_MACHO
12669 return output_call(insn, operands, 0, 2);
12670 #else
12671 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12672 {
12673 gcc_assert (!TARGET_SECURE_PLT);
12674 return "bl %z0@plt";
12675 }
12676 else
12677 return "bl %z0";
12678 #endif
12679 }
12680 "DEFAULT_ABI == ABI_V4
12681 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12682 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12683 [(parallel [(call (mem:SI (match_dup 0))
12684 (match_dup 1))
12685 (use (match_dup 2))
12686 (use (match_dup 3))
12687 (clobber (reg:SI LR_REGNO))])]
12688 {
12689 operands[3] = pic_offset_table_rtx;
12690 }
12691 [(set_attr "type" "branch,branch")
12692 (set_attr "length" "4,8")])
12693
12694 (define_insn "*call_nonlocal_sysv_secure<mode>"
12695 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12696 (match_operand 1 "" "g,g"))
12697 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12698 (use (match_operand:SI 3 "register_operand" "r,r"))
12699 (clobber (reg:SI LR_REGNO))]
12700 "(DEFAULT_ABI == ABI_V4
12701 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12702 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12703 {
12704 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12705 output_asm_insn ("crxor 6,6,6", operands);
12706
12707 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12708 output_asm_insn ("creqv 6,6,6", operands);
12709
12710 if (flag_pic == 2)
12711 /* The magic 32768 offset here and in the other sysv call insns
12712 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12713 See sysv4.h:toc_section. */
12714 return "bl %z0+32768@plt";
12715 else
12716 return "bl %z0@plt";
12717 }
12718 [(set_attr "type" "branch,branch")
12719 (set_attr "length" "4,8")])
12720
12721 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12722 [(set (match_operand 0 "" "")
12723 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12724 (match_operand 2 "" "g,g,g,g")))
12725 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12726 (clobber (reg:SI LR_REGNO))]
12727 "DEFAULT_ABI == ABI_V4
12728 || DEFAULT_ABI == ABI_DARWIN"
12729 {
12730 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12731 output_asm_insn ("crxor 6,6,6", operands);
12732
12733 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12734 output_asm_insn ("creqv 6,6,6", operands);
12735
12736 return "b%T1l";
12737 }
12738 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12739 (set_attr "length" "4,4,8,8")])
12740
12741 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12742 [(set (match_operand 0 "" "")
12743 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12744 (match_operand 2 "" "g,g")))
12745 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12746 (clobber (reg:SI LR_REGNO))]
12747 "(DEFAULT_ABI == ABI_DARWIN
12748 || (DEFAULT_ABI == ABI_V4
12749 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12750 {
12751 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12752 output_asm_insn ("crxor 6,6,6", operands);
12753
12754 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12755 output_asm_insn ("creqv 6,6,6", operands);
12756
12757 #if TARGET_MACHO
12758 return output_call(insn, operands, 1, 3);
12759 #else
12760 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12761 {
12762 gcc_assert (!TARGET_SECURE_PLT);
12763 return "bl %z1@plt";
12764 }
12765 else
12766 return "bl %z1";
12767 #endif
12768 }
12769 "DEFAULT_ABI == ABI_V4
12770 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12771 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12772 [(parallel [(set (match_dup 0)
12773 (call (mem:SI (match_dup 1))
12774 (match_dup 2)))
12775 (use (match_dup 3))
12776 (use (match_dup 4))
12777 (clobber (reg:SI LR_REGNO))])]
12778 {
12779 operands[4] = pic_offset_table_rtx;
12780 }
12781 [(set_attr "type" "branch,branch")
12782 (set_attr "length" "4,8")])
12783
12784 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12785 [(set (match_operand 0 "" "")
12786 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12787 (match_operand 2 "" "g,g")))
12788 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12789 (use (match_operand:SI 4 "register_operand" "r,r"))
12790 (clobber (reg:SI LR_REGNO))]
12791 "(DEFAULT_ABI == ABI_V4
12792 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12793 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12794 {
12795 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12796 output_asm_insn ("crxor 6,6,6", operands);
12797
12798 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12799 output_asm_insn ("creqv 6,6,6", operands);
12800
12801 if (flag_pic == 2)
12802 return "bl %z1+32768@plt";
12803 else
12804 return "bl %z1@plt";
12805 }
12806 [(set_attr "type" "branch,branch")
12807 (set_attr "length" "4,8")])
12808
12809 ;; Call subroutine returning any type.
12810 (define_expand "untyped_call"
12811 [(parallel [(call (match_operand 0 "" "")
12812 (const_int 0))
12813 (match_operand 1 "" "")
12814 (match_operand 2 "" "")])]
12815 ""
12816 "
12817 {
12818 int i;
12819
12820 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12821
12822 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12823 {
12824 rtx set = XVECEXP (operands[2], 0, i);
12825 emit_move_insn (SET_DEST (set), SET_SRC (set));
12826 }
12827
12828 /* The optimizer does not know that the call sets the function value
12829 registers we stored in the result block. We avoid problems by
12830 claiming that all hard registers are used and clobbered at this
12831 point. */
12832 emit_insn (gen_blockage ());
12833
12834 DONE;
12835 }")
12836
12837 ;; sibling call patterns
12838 (define_expand "sibcall"
12839 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12840 (match_operand 1 "" ""))
12841 (use (match_operand 2 "" ""))
12842 (use (reg:SI LR_REGNO))
12843 (return)])]
12844 ""
12845 "
12846 {
12847 #if TARGET_MACHO
12848 if (MACHOPIC_INDIRECT)
12849 operands[0] = machopic_indirect_call_target (operands[0]);
12850 #endif
12851
12852 gcc_assert (GET_CODE (operands[0]) == MEM);
12853 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12854
12855 operands[0] = XEXP (operands[0], 0);
12856 }")
12857
12858 ;; this and similar patterns must be marked as using LR, otherwise
12859 ;; dataflow will try to delete the store into it. This is true
12860 ;; even when the actual reg to jump to is in CTR, when LR was
12861 ;; saved and restored around the PIC-setting BCL.
12862 (define_insn "*sibcall_local32"
12863 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12864 (match_operand 1 "" "g,g"))
12865 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12866 (use (reg:SI LR_REGNO))
12867 (return)]
12868 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12869 "*
12870 {
12871 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12872 output_asm_insn (\"crxor 6,6,6\", operands);
12873
12874 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12875 output_asm_insn (\"creqv 6,6,6\", operands);
12876
12877 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12878 }"
12879 [(set_attr "type" "branch")
12880 (set_attr "length" "4,8")])
12881
12882 (define_insn "*sibcall_local64"
12883 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12884 (match_operand 1 "" "g,g"))
12885 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12886 (use (reg:SI LR_REGNO))
12887 (return)]
12888 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12889 "*
12890 {
12891 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12892 output_asm_insn (\"crxor 6,6,6\", operands);
12893
12894 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12895 output_asm_insn (\"creqv 6,6,6\", operands);
12896
12897 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12898 }"
12899 [(set_attr "type" "branch")
12900 (set_attr "length" "4,8")])
12901
12902 (define_insn "*sibcall_value_local32"
12903 [(set (match_operand 0 "" "")
12904 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12905 (match_operand 2 "" "g,g")))
12906 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12907 (use (reg:SI LR_REGNO))
12908 (return)]
12909 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12910 "*
12911 {
12912 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12913 output_asm_insn (\"crxor 6,6,6\", operands);
12914
12915 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12916 output_asm_insn (\"creqv 6,6,6\", operands);
12917
12918 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12919 }"
12920 [(set_attr "type" "branch")
12921 (set_attr "length" "4,8")])
12922
12923
12924 (define_insn "*sibcall_value_local64"
12925 [(set (match_operand 0 "" "")
12926 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12927 (match_operand 2 "" "g,g")))
12928 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12929 (use (reg:SI LR_REGNO))
12930 (return)]
12931 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12932 "*
12933 {
12934 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12935 output_asm_insn (\"crxor 6,6,6\", operands);
12936
12937 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12938 output_asm_insn (\"creqv 6,6,6\", operands);
12939
12940 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12941 }"
12942 [(set_attr "type" "branch")
12943 (set_attr "length" "4,8")])
12944
12945 (define_insn "*sibcall_nonlocal_aix32"
12946 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12947 (match_operand 1 "" "g"))
12948 (use (match_operand:SI 2 "immediate_operand" "O"))
12949 (use (reg:SI LR_REGNO))
12950 (return)]
12951 "TARGET_32BIT
12952 && DEFAULT_ABI == ABI_AIX
12953 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12954 "b %z0"
12955 [(set_attr "type" "branch")
12956 (set_attr "length" "4")])
12957
12958 (define_insn "*sibcall_nonlocal_aix64"
12959 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12960 (match_operand 1 "" "g"))
12961 (use (match_operand:SI 2 "immediate_operand" "O"))
12962 (use (reg:SI LR_REGNO))
12963 (return)]
12964 "TARGET_64BIT
12965 && DEFAULT_ABI == ABI_AIX
12966 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12967 "b %z0"
12968 [(set_attr "type" "branch")
12969 (set_attr "length" "4")])
12970
12971 (define_insn "*sibcall_value_nonlocal_aix32"
12972 [(set (match_operand 0 "" "")
12973 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12974 (match_operand 2 "" "g")))
12975 (use (match_operand:SI 3 "immediate_operand" "O"))
12976 (use (reg:SI LR_REGNO))
12977 (return)]
12978 "TARGET_32BIT
12979 && DEFAULT_ABI == ABI_AIX
12980 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12981 "b %z1"
12982 [(set_attr "type" "branch")
12983 (set_attr "length" "4")])
12984
12985 (define_insn "*sibcall_value_nonlocal_aix64"
12986 [(set (match_operand 0 "" "")
12987 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12988 (match_operand 2 "" "g")))
12989 (use (match_operand:SI 3 "immediate_operand" "O"))
12990 (use (reg:SI LR_REGNO))
12991 (return)]
12992 "TARGET_64BIT
12993 && DEFAULT_ABI == ABI_AIX
12994 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12995 "b %z1"
12996 [(set_attr "type" "branch")
12997 (set_attr "length" "4")])
12998
12999 (define_insn "*sibcall_nonlocal_sysv<mode>"
13000 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
13001 (match_operand 1 "" ""))
13002 (use (match_operand 2 "immediate_operand" "O,n"))
13003 (use (reg:SI LR_REGNO))
13004 (return)]
13005 "(DEFAULT_ABI == ABI_DARWIN
13006 || DEFAULT_ABI == ABI_V4)
13007 && (INTVAL (operands[2]) & CALL_LONG) == 0"
13008 "*
13009 {
13010 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
13011 output_asm_insn (\"crxor 6,6,6\", operands);
13012
13013 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
13014 output_asm_insn (\"creqv 6,6,6\", operands);
13015
13016 if (DEFAULT_ABI == ABI_V4 && flag_pic)
13017 {
13018 gcc_assert (!TARGET_SECURE_PLT);
13019 return \"b %z0@plt\";
13020 }
13021 else
13022 return \"b %z0\";
13023 }"
13024 [(set_attr "type" "branch,branch")
13025 (set_attr "length" "4,8")])
13026
13027 (define_expand "sibcall_value"
13028 [(parallel [(set (match_operand 0 "register_operand" "")
13029 (call (mem:SI (match_operand 1 "address_operand" ""))
13030 (match_operand 2 "" "")))
13031 (use (match_operand 3 "" ""))
13032 (use (reg:SI LR_REGNO))
13033 (return)])]
13034 ""
13035 "
13036 {
13037 #if TARGET_MACHO
13038 if (MACHOPIC_INDIRECT)
13039 operands[1] = machopic_indirect_call_target (operands[1]);
13040 #endif
13041
13042 gcc_assert (GET_CODE (operands[1]) == MEM);
13043 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
13044
13045 operands[1] = XEXP (operands[1], 0);
13046 }")
13047
13048 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
13049 [(set (match_operand 0 "" "")
13050 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
13051 (match_operand 2 "" "")))
13052 (use (match_operand:SI 3 "immediate_operand" "O,n"))
13053 (use (reg:SI LR_REGNO))
13054 (return)]
13055 "(DEFAULT_ABI == ABI_DARWIN
13056 || DEFAULT_ABI == ABI_V4)
13057 && (INTVAL (operands[3]) & CALL_LONG) == 0"
13058 "*
13059 {
13060 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
13061 output_asm_insn (\"crxor 6,6,6\", operands);
13062
13063 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
13064 output_asm_insn (\"creqv 6,6,6\", operands);
13065
13066 if (DEFAULT_ABI == ABI_V4 && flag_pic)
13067 {
13068 gcc_assert (!TARGET_SECURE_PLT);
13069 return \"b %z1@plt\";
13070 }
13071 else
13072 return \"b %z1\";
13073 }"
13074 [(set_attr "type" "branch,branch")
13075 (set_attr "length" "4,8")])
13076
13077 (define_expand "sibcall_epilogue"
13078 [(use (const_int 0))]
13079 "TARGET_SCHED_PROLOG"
13080 "
13081 {
13082 rs6000_emit_epilogue (TRUE);
13083 DONE;
13084 }")
13085
13086 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13087 ;; all of memory. This blocks insns from being moved across this point.
13088
13089 (define_insn "blockage"
13090 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
13091 ""
13092 "")
13093
13094 (define_insn "probe_stack"
13095 [(set (match_operand 0 "memory_operand" "=m")
13096 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
13097 ""
13098 "{st%U0%X0|stw%U0%X0} 0,%0"
13099 [(set_attr "type" "store")
13100 (set_attr "length" "4")])
13101
13102 (define_insn "probe_stack_range<P:mode>"
13103 [(set (match_operand:P 0 "register_operand" "=r")
13104 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
13105 (match_operand:P 2 "register_operand" "r")]
13106 UNSPECV_PROBE_STACK_RANGE))]
13107 ""
13108 "* return output_probe_stack_range (operands[0], operands[2]);"
13109 [(set_attr "type" "three")])
13110 \f
13111 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
13112 ;; signed & unsigned, and one type of branch.
13113 ;;
13114 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
13115 ;; insns, and branches.
13116
13117 (define_expand "cbranch<mode>4"
13118 [(use (match_operator 0 "rs6000_cbranch_operator"
13119 [(match_operand:GPR 1 "gpc_reg_operand" "")
13120 (match_operand:GPR 2 "reg_or_short_operand" "")]))
13121 (use (match_operand 3 ""))]
13122 ""
13123 "
13124 {
13125 /* Take care of the possibility that operands[2] might be negative but
13126 this might be a logical operation. That insn doesn't exist. */
13127 if (GET_CODE (operands[2]) == CONST_INT
13128 && INTVAL (operands[2]) < 0)
13129 {
13130 operands[2] = force_reg (<MODE>mode, operands[2]);
13131 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
13132 GET_MODE (operands[0]),
13133 operands[1], operands[2]);
13134 }
13135
13136 rs6000_emit_cbranch (<MODE>mode, operands);
13137 DONE;
13138 }")
13139
13140 (define_expand "cbranch<mode>4"
13141 [(use (match_operator 0 "rs6000_cbranch_operator"
13142 [(match_operand:FP 1 "gpc_reg_operand" "")
13143 (match_operand:FP 2 "gpc_reg_operand" "")]))
13144 (use (match_operand 3 ""))]
13145 ""
13146 "
13147 {
13148 rs6000_emit_cbranch (<MODE>mode, operands);
13149 DONE;
13150 }")
13151
13152 (define_expand "cstore<mode>4"
13153 [(use (match_operator 1 "rs6000_cbranch_operator"
13154 [(match_operand:GPR 2 "gpc_reg_operand" "")
13155 (match_operand:GPR 3 "reg_or_short_operand" "")]))
13156 (clobber (match_operand:SI 0 "register_operand"))]
13157 ""
13158 "
13159 {
13160 /* Take care of the possibility that operands[3] might be negative but
13161 this might be a logical operation. That insn doesn't exist. */
13162 if (GET_CODE (operands[3]) == CONST_INT
13163 && INTVAL (operands[3]) < 0)
13164 {
13165 operands[3] = force_reg (<MODE>mode, operands[3]);
13166 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
13167 GET_MODE (operands[1]),
13168 operands[2], operands[3]);
13169 }
13170
13171 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
13172 For SEQ, likewise, except that comparisons with zero should be done
13173 with an scc insns. However, due to the order that combine see the
13174 resulting insns, we must, in fact, allow SEQ for integers. Fail in
13175 the cases we don't want to handle or are best handled by portable
13176 code. */
13177 if (GET_CODE (operands[1]) == NE)
13178 FAIL;
13179 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
13180 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
13181 && operands[3] == const0_rtx)
13182 FAIL;
13183 rs6000_emit_sCOND (<MODE>mode, operands);
13184 DONE;
13185 }")
13186
13187 (define_expand "cstore<mode>4"
13188 [(use (match_operator 1 "rs6000_cbranch_operator"
13189 [(match_operand:FP 2 "gpc_reg_operand" "")
13190 (match_operand:FP 3 "gpc_reg_operand" "")]))
13191 (clobber (match_operand:SI 0 "register_operand"))]
13192 ""
13193 "
13194 {
13195 rs6000_emit_sCOND (<MODE>mode, operands);
13196 DONE;
13197 }")
13198
13199
13200 (define_expand "stack_protect_set"
13201 [(match_operand 0 "memory_operand" "")
13202 (match_operand 1 "memory_operand" "")]
13203 ""
13204 {
13205 #ifdef TARGET_THREAD_SSP_OFFSET
13206 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13207 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13208 operands[1] = gen_rtx_MEM (Pmode, addr);
13209 #endif
13210 if (TARGET_64BIT)
13211 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
13212 else
13213 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
13214 DONE;
13215 })
13216
13217 (define_insn "stack_protect_setsi"
13218 [(set (match_operand:SI 0 "memory_operand" "=m")
13219 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13220 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13221 "TARGET_32BIT"
13222 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
13223 [(set_attr "type" "three")
13224 (set_attr "length" "12")])
13225
13226 (define_insn "stack_protect_setdi"
13227 [(set (match_operand:DI 0 "memory_operand" "=m")
13228 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13229 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13230 "TARGET_64BIT"
13231 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
13232 [(set_attr "type" "three")
13233 (set_attr "length" "12")])
13234
13235 (define_expand "stack_protect_test"
13236 [(match_operand 0 "memory_operand" "")
13237 (match_operand 1 "memory_operand" "")
13238 (match_operand 2 "" "")]
13239 ""
13240 {
13241 rtx test, op0, op1;
13242 #ifdef TARGET_THREAD_SSP_OFFSET
13243 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13244 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13245 operands[1] = gen_rtx_MEM (Pmode, addr);
13246 #endif
13247 op0 = operands[0];
13248 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
13249 test = gen_rtx_EQ (VOIDmode, op0, op1);
13250 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
13251 DONE;
13252 })
13253
13254 (define_insn "stack_protect_testsi"
13255 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13256 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13257 (match_operand:SI 2 "memory_operand" "m,m")]
13258 UNSPEC_SP_TEST))
13259 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13260 (clobber (match_scratch:SI 3 "=&r,&r"))]
13261 "TARGET_32BIT"
13262 "@
13263 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13264 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13265 [(set_attr "length" "16,20")])
13266
13267 (define_insn "stack_protect_testdi"
13268 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13269 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
13270 (match_operand:DI 2 "memory_operand" "m,m")]
13271 UNSPEC_SP_TEST))
13272 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13273 (clobber (match_scratch:DI 3 "=&r,&r"))]
13274 "TARGET_64BIT"
13275 "@
13276 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13277 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13278 [(set_attr "length" "16,20")])
13279
13280 \f
13281 ;; Here are the actual compare insns.
13282 (define_insn "*cmp<mode>_internal1"
13283 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13284 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13285 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13286 ""
13287 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
13288 [(set_attr "type" "cmp")])
13289
13290 ;; If we are comparing a register for equality with a large constant,
13291 ;; we can do this with an XOR followed by a compare. But this is profitable
13292 ;; only if the large constant is only used for the comparison (and in this
13293 ;; case we already have a register to reuse as scratch).
13294 ;;
13295 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13296 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13297
13298 (define_peephole2
13299 [(set (match_operand:SI 0 "register_operand")
13300 (match_operand:SI 1 "logical_const_operand" ""))
13301 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13302 [(match_dup 0)
13303 (match_operand:SI 2 "logical_const_operand" "")]))
13304 (set (match_operand:CC 4 "cc_reg_operand" "")
13305 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13306 (match_dup 0)))
13307 (set (pc)
13308 (if_then_else (match_operator 6 "equality_operator"
13309 [(match_dup 4) (const_int 0)])
13310 (match_operand 7 "" "")
13311 (match_operand 8 "" "")))]
13312 "peep2_reg_dead_p (3, operands[0])
13313 && peep2_reg_dead_p (4, operands[4])"
13314 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13315 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13316 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13317
13318 {
13319 /* Get the constant we are comparing against, and see what it looks like
13320 when sign-extended from 16 to 32 bits. Then see what constant we could
13321 XOR with SEXTC to get the sign-extended value. */
13322 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13323 SImode,
13324 operands[1], operands[2]);
13325 HOST_WIDE_INT c = INTVAL (cnst);
13326 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13327 HOST_WIDE_INT xorv = c ^ sextc;
13328
13329 operands[9] = GEN_INT (xorv);
13330 operands[10] = GEN_INT (sextc);
13331 })
13332
13333 (define_insn "*cmpsi_internal2"
13334 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13335 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13336 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13337 ""
13338 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
13339 [(set_attr "type" "cmp")])
13340
13341 (define_insn "*cmpdi_internal2"
13342 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13343 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13344 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13345 ""
13346 "cmpld%I2 %0,%1,%b2"
13347 [(set_attr "type" "cmp")])
13348
13349 ;; The following two insns don't exist as single insns, but if we provide
13350 ;; them, we can swap an add and compare, which will enable us to overlap more
13351 ;; of the required delay between a compare and branch. We generate code for
13352 ;; them by splitting.
13353
13354 (define_insn ""
13355 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13356 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13357 (match_operand:SI 2 "short_cint_operand" "i")))
13358 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13359 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13360 ""
13361 "#"
13362 [(set_attr "length" "8")])
13363
13364 (define_insn ""
13365 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13366 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13367 (match_operand:SI 2 "u_short_cint_operand" "i")))
13368 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13369 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13370 ""
13371 "#"
13372 [(set_attr "length" "8")])
13373
13374 (define_split
13375 [(set (match_operand:CC 3 "cc_reg_operand" "")
13376 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13377 (match_operand:SI 2 "short_cint_operand" "")))
13378 (set (match_operand:SI 0 "gpc_reg_operand" "")
13379 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13380 ""
13381 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13382 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13383
13384 (define_split
13385 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13386 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13387 (match_operand:SI 2 "u_short_cint_operand" "")))
13388 (set (match_operand:SI 0 "gpc_reg_operand" "")
13389 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13390 ""
13391 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13392 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13393
13394 (define_insn "*cmpsf_internal1"
13395 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13396 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
13397 (match_operand:SF 2 "gpc_reg_operand" "f")))]
13398 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
13399 "fcmpu %0,%1,%2"
13400 [(set_attr "type" "fpcompare")])
13401
13402 (define_insn "*cmpdf_internal1"
13403 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13404 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
13405 (match_operand:DF 2 "gpc_reg_operand" "d")))]
13406 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
13407 && !VECTOR_UNIT_VSX_P (DFmode)"
13408 "fcmpu %0,%1,%2"
13409 [(set_attr "type" "fpcompare")])
13410
13411 ;; Only need to compare second words if first words equal
13412 (define_insn "*cmptf_internal1"
13413 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13414 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13415 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13416 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13417 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13418 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13419 [(set_attr "type" "fpcompare")
13420 (set_attr "length" "12")])
13421
13422 (define_insn_and_split "*cmptf_internal2"
13423 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13424 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13425 (match_operand:TF 2 "gpc_reg_operand" "d")))
13426 (clobber (match_scratch:DF 3 "=d"))
13427 (clobber (match_scratch:DF 4 "=d"))
13428 (clobber (match_scratch:DF 5 "=d"))
13429 (clobber (match_scratch:DF 6 "=d"))
13430 (clobber (match_scratch:DF 7 "=d"))
13431 (clobber (match_scratch:DF 8 "=d"))
13432 (clobber (match_scratch:DF 9 "=d"))
13433 (clobber (match_scratch:DF 10 "=d"))
13434 (clobber (match_scratch:GPR 11 "=b"))]
13435 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13436 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13437 "#"
13438 "&& reload_completed"
13439 [(set (match_dup 3) (match_dup 14))
13440 (set (match_dup 4) (match_dup 15))
13441 (set (match_dup 9) (abs:DF (match_dup 5)))
13442 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13443 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13444 (label_ref (match_dup 12))
13445 (pc)))
13446 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13447 (set (pc) (label_ref (match_dup 13)))
13448 (match_dup 12)
13449 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13450 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13451 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13452 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13453 (match_dup 13)]
13454 {
13455 REAL_VALUE_TYPE rv;
13456 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
13457 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
13458
13459 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13460 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13461 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13462 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13463 operands[12] = gen_label_rtx ();
13464 operands[13] = gen_label_rtx ();
13465 real_inf (&rv);
13466 operands[14] = force_const_mem (DFmode,
13467 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13468 operands[15] = force_const_mem (DFmode,
13469 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13470 DFmode));
13471 if (TARGET_TOC)
13472 {
13473 rtx tocref;
13474 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13475 operands[14] = gen_const_mem (DFmode, tocref);
13476 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13477 operands[15] = gen_const_mem (DFmode, tocref);
13478 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13479 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13480 }
13481 })
13482 \f
13483 ;; Now we have the scc insns. We can do some combinations because of the
13484 ;; way the machine works.
13485 ;;
13486 ;; Note that this is probably faster if we can put an insn between the
13487 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13488 ;; cases the insns below which don't use an intermediate CR field will
13489 ;; be used instead.
13490 (define_insn ""
13491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13492 (match_operator:SI 1 "scc_comparison_operator"
13493 [(match_operand 2 "cc_reg_operand" "y")
13494 (const_int 0)]))]
13495 ""
13496 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13497 [(set (attr "type")
13498 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13499 (const_string "mfcrf")
13500 ]
13501 (const_string "mfcr")))
13502 (set_attr "length" "8")])
13503
13504 ;; Same as above, but get the GT bit.
13505 (define_insn "move_from_CR_gt_bit"
13506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13507 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13508 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13509 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
13510 [(set_attr "type" "mfcr")
13511 (set_attr "length" "8")])
13512
13513 ;; Same as above, but get the OV/ORDERED bit.
13514 (define_insn "move_from_CR_ov_bit"
13515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13516 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
13517 "TARGET_ISEL"
13518 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
13519 [(set_attr "type" "mfcr")
13520 (set_attr "length" "8")])
13521
13522 (define_insn ""
13523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13524 (match_operator:DI 1 "scc_comparison_operator"
13525 [(match_operand 2 "cc_reg_operand" "y")
13526 (const_int 0)]))]
13527 "TARGET_POWERPC64"
13528 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13529 [(set (attr "type")
13530 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13531 (const_string "mfcrf")
13532 ]
13533 (const_string "mfcr")))
13534 (set_attr "length" "8")])
13535
13536 (define_insn ""
13537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13538 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13539 [(match_operand 2 "cc_reg_operand" "y,y")
13540 (const_int 0)])
13541 (const_int 0)))
13542 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13543 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13544 "TARGET_32BIT"
13545 "@
13546 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13547 #"
13548 [(set_attr "type" "delayed_compare")
13549 (set_attr "length" "8,16")])
13550
13551 (define_split
13552 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13553 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13554 [(match_operand 2 "cc_reg_operand" "")
13555 (const_int 0)])
13556 (const_int 0)))
13557 (set (match_operand:SI 3 "gpc_reg_operand" "")
13558 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13559 "TARGET_32BIT && reload_completed"
13560 [(set (match_dup 3)
13561 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13562 (set (match_dup 0)
13563 (compare:CC (match_dup 3)
13564 (const_int 0)))]
13565 "")
13566
13567 (define_insn ""
13568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13569 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13570 [(match_operand 2 "cc_reg_operand" "y")
13571 (const_int 0)])
13572 (match_operand:SI 3 "const_int_operand" "n")))]
13573 ""
13574 "*
13575 {
13576 int is_bit = ccr_bit (operands[1], 1);
13577 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13578 int count;
13579
13580 if (is_bit >= put_bit)
13581 count = is_bit - put_bit;
13582 else
13583 count = 32 - (put_bit - is_bit);
13584
13585 operands[4] = GEN_INT (count);
13586 operands[5] = GEN_INT (put_bit);
13587
13588 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13589 }"
13590 [(set (attr "type")
13591 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13592 (const_string "mfcrf")
13593 ]
13594 (const_string "mfcr")))
13595 (set_attr "length" "8")])
13596
13597 (define_insn ""
13598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13599 (compare:CC
13600 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13601 [(match_operand 2 "cc_reg_operand" "y,y")
13602 (const_int 0)])
13603 (match_operand:SI 3 "const_int_operand" "n,n"))
13604 (const_int 0)))
13605 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13606 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13607 (match_dup 3)))]
13608 ""
13609 "*
13610 {
13611 int is_bit = ccr_bit (operands[1], 1);
13612 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13613 int count;
13614
13615 /* Force split for non-cc0 compare. */
13616 if (which_alternative == 1)
13617 return \"#\";
13618
13619 if (is_bit >= put_bit)
13620 count = is_bit - put_bit;
13621 else
13622 count = 32 - (put_bit - is_bit);
13623
13624 operands[5] = GEN_INT (count);
13625 operands[6] = GEN_INT (put_bit);
13626
13627 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13628 }"
13629 [(set_attr "type" "delayed_compare")
13630 (set_attr "length" "8,16")])
13631
13632 (define_split
13633 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13634 (compare:CC
13635 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13636 [(match_operand 2 "cc_reg_operand" "")
13637 (const_int 0)])
13638 (match_operand:SI 3 "const_int_operand" ""))
13639 (const_int 0)))
13640 (set (match_operand:SI 4 "gpc_reg_operand" "")
13641 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13642 (match_dup 3)))]
13643 "reload_completed"
13644 [(set (match_dup 4)
13645 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13646 (match_dup 3)))
13647 (set (match_dup 0)
13648 (compare:CC (match_dup 4)
13649 (const_int 0)))]
13650 "")
13651
13652 ;; There is a 3 cycle delay between consecutive mfcr instructions
13653 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13654
13655 (define_peephole
13656 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13657 (match_operator:SI 1 "scc_comparison_operator"
13658 [(match_operand 2 "cc_reg_operand" "y")
13659 (const_int 0)]))
13660 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13661 (match_operator:SI 4 "scc_comparison_operator"
13662 [(match_operand 5 "cc_reg_operand" "y")
13663 (const_int 0)]))]
13664 "REGNO (operands[2]) != REGNO (operands[5])"
13665 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13666 [(set_attr "type" "mfcr")
13667 (set_attr "length" "12")])
13668
13669 (define_peephole
13670 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13671 (match_operator:DI 1 "scc_comparison_operator"
13672 [(match_operand 2 "cc_reg_operand" "y")
13673 (const_int 0)]))
13674 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13675 (match_operator:DI 4 "scc_comparison_operator"
13676 [(match_operand 5 "cc_reg_operand" "y")
13677 (const_int 0)]))]
13678 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13679 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13680 [(set_attr "type" "mfcr")
13681 (set_attr "length" "12")])
13682
13683 ;; There are some scc insns that can be done directly, without a compare.
13684 ;; These are faster because they don't involve the communications between
13685 ;; the FXU and branch units. In fact, we will be replacing all of the
13686 ;; integer scc insns here or in the portable methods in emit_store_flag.
13687 ;;
13688 ;; Also support (neg (scc ..)) since that construct is used to replace
13689 ;; branches, (plus (scc ..) ..) since that construct is common and
13690 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13691 ;; cases where it is no more expensive than (neg (scc ..)).
13692
13693 ;; Have reload force a constant into a register for the simple insns that
13694 ;; otherwise won't accept constants. We do this because it is faster than
13695 ;; the cmp/mfcr sequence we would otherwise generate.
13696
13697 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13698 (DI "rKJI")])
13699
13700 (define_insn_and_split "*eq<mode>"
13701 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13702 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13703 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13704 "!TARGET_POWER"
13705 "#"
13706 "!TARGET_POWER"
13707 [(set (match_dup 0)
13708 (clz:GPR (match_dup 3)))
13709 (set (match_dup 0)
13710 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13711 {
13712 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13713 {
13714 /* Use output operand as intermediate. */
13715 operands[3] = operands[0];
13716
13717 if (logical_operand (operands[2], <MODE>mode))
13718 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13719 gen_rtx_XOR (<MODE>mode,
13720 operands[1], operands[2])));
13721 else
13722 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13723 gen_rtx_PLUS (<MODE>mode, operands[1],
13724 negate_rtx (<MODE>mode,
13725 operands[2]))));
13726 }
13727 else
13728 operands[3] = operands[1];
13729
13730 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13731 })
13732
13733 (define_insn_and_split "*eq<mode>_compare"
13734 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13735 (compare:CC
13736 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13737 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13738 (const_int 0)))
13739 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13740 (eq:P (match_dup 1) (match_dup 2)))]
13741 "!TARGET_POWER && optimize_size"
13742 "#"
13743 "!TARGET_POWER && optimize_size"
13744 [(set (match_dup 0)
13745 (clz:P (match_dup 4)))
13746 (parallel [(set (match_dup 3)
13747 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13748 (const_int 0)))
13749 (set (match_dup 0)
13750 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13751 {
13752 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13753 {
13754 /* Use output operand as intermediate. */
13755 operands[4] = operands[0];
13756
13757 if (logical_operand (operands[2], <MODE>mode))
13758 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13759 gen_rtx_XOR (<MODE>mode,
13760 operands[1], operands[2])));
13761 else
13762 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13763 gen_rtx_PLUS (<MODE>mode, operands[1],
13764 negate_rtx (<MODE>mode,
13765 operands[2]))));
13766 }
13767 else
13768 operands[4] = operands[1];
13769
13770 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13771 })
13772
13773 (define_insn "*eqsi_power"
13774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13775 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13776 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13777 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13778 "TARGET_POWER"
13779 "@
13780 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13781 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13782 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13783 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13784 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13785 [(set_attr "type" "three,two,three,three,three")
13786 (set_attr "length" "12,8,12,12,12")])
13787
13788 ;; We have insns of the form shown by the first define_insn below. If
13789 ;; there is something inside the comparison operation, we must split it.
13790 (define_split
13791 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13792 (plus:SI (match_operator 1 "comparison_operator"
13793 [(match_operand:SI 2 "" "")
13794 (match_operand:SI 3
13795 "reg_or_cint_operand" "")])
13796 (match_operand:SI 4 "gpc_reg_operand" "")))
13797 (clobber (match_operand:SI 5 "register_operand" ""))]
13798 "! gpc_reg_operand (operands[2], SImode)"
13799 [(set (match_dup 5) (match_dup 2))
13800 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13801 (match_dup 4)))])
13802
13803 (define_insn "*plus_eqsi"
13804 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13805 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13806 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13807 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13808 "TARGET_32BIT"
13809 "@
13810 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13811 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13812 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13813 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13814 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13815 [(set_attr "type" "three,two,three,three,three")
13816 (set_attr "length" "12,8,12,12,12")])
13817
13818 (define_insn "*compare_plus_eqsi"
13819 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13820 (compare:CC
13821 (plus:SI
13822 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13823 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13824 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13825 (const_int 0)))
13826 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13827 "TARGET_32BIT && optimize_size"
13828 "@
13829 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13830 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13831 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13832 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13833 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13834 #
13835 #
13836 #
13837 #
13838 #"
13839 [(set_attr "type" "compare")
13840 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13841
13842 (define_split
13843 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13844 (compare:CC
13845 (plus:SI
13846 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13847 (match_operand:SI 2 "scc_eq_operand" ""))
13848 (match_operand:SI 3 "gpc_reg_operand" ""))
13849 (const_int 0)))
13850 (clobber (match_scratch:SI 4 ""))]
13851 "TARGET_32BIT && optimize_size && reload_completed"
13852 [(set (match_dup 4)
13853 (plus:SI (eq:SI (match_dup 1)
13854 (match_dup 2))
13855 (match_dup 3)))
13856 (set (match_dup 0)
13857 (compare:CC (match_dup 4)
13858 (const_int 0)))]
13859 "")
13860
13861 (define_insn "*plus_eqsi_compare"
13862 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13863 (compare:CC
13864 (plus:SI
13865 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13866 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13867 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13868 (const_int 0)))
13869 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13870 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13871 "TARGET_32BIT && optimize_size"
13872 "@
13873 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13874 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13875 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13876 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13877 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13878 #
13879 #
13880 #
13881 #
13882 #"
13883 [(set_attr "type" "compare")
13884 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13885
13886 (define_split
13887 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13888 (compare:CC
13889 (plus:SI
13890 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13891 (match_operand:SI 2 "scc_eq_operand" ""))
13892 (match_operand:SI 3 "gpc_reg_operand" ""))
13893 (const_int 0)))
13894 (set (match_operand:SI 0 "gpc_reg_operand" "")
13895 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13896 "TARGET_32BIT && optimize_size && reload_completed"
13897 [(set (match_dup 0)
13898 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13899 (set (match_dup 4)
13900 (compare:CC (match_dup 0)
13901 (const_int 0)))]
13902 "")
13903
13904 (define_insn "*neg_eq0<mode>"
13905 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13906 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13907 (const_int 0))))]
13908 ""
13909 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13910 [(set_attr "type" "two")
13911 (set_attr "length" "8")])
13912
13913 (define_insn_and_split "*neg_eq<mode>"
13914 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13915 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13916 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13917 ""
13918 "#"
13919 ""
13920 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13921 {
13922 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13923 {
13924 /* Use output operand as intermediate. */
13925 operands[3] = operands[0];
13926
13927 if (logical_operand (operands[2], <MODE>mode))
13928 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13929 gen_rtx_XOR (<MODE>mode,
13930 operands[1], operands[2])));
13931 else
13932 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13933 gen_rtx_PLUS (<MODE>mode, operands[1],
13934 negate_rtx (<MODE>mode,
13935 operands[2]))));
13936 }
13937 else
13938 operands[3] = operands[1];
13939 })
13940
13941 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13942 ;; since it nabs/sr is just as fast.
13943 (define_insn "*ne0si"
13944 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13945 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13946 (const_int 31)))
13947 (clobber (match_scratch:SI 2 "=&r"))]
13948 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13949 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13950 [(set_attr "type" "two")
13951 (set_attr "length" "8")])
13952
13953 (define_insn "*ne0di"
13954 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13955 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13956 (const_int 63)))
13957 (clobber (match_scratch:DI 2 "=&r"))]
13958 "TARGET_64BIT"
13959 "addic %2,%1,-1\;subfe %0,%2,%1"
13960 [(set_attr "type" "two")
13961 (set_attr "length" "8")])
13962
13963 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13964 (define_insn "*plus_ne0si"
13965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13966 (plus:SI (lshiftrt:SI
13967 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13968 (const_int 31))
13969 (match_operand:SI 2 "gpc_reg_operand" "r")))
13970 (clobber (match_scratch:SI 3 "=&r"))]
13971 "TARGET_32BIT"
13972 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13973 [(set_attr "type" "two")
13974 (set_attr "length" "8")])
13975
13976 (define_insn "*plus_ne0di"
13977 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13978 (plus:DI (lshiftrt:DI
13979 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13980 (const_int 63))
13981 (match_operand:DI 2 "gpc_reg_operand" "r")))
13982 (clobber (match_scratch:DI 3 "=&r"))]
13983 "TARGET_64BIT"
13984 "addic %3,%1,-1\;addze %0,%2"
13985 [(set_attr "type" "two")
13986 (set_attr "length" "8")])
13987
13988 (define_insn "*compare_plus_ne0si"
13989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13990 (compare:CC
13991 (plus:SI (lshiftrt:SI
13992 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13993 (const_int 31))
13994 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13995 (const_int 0)))
13996 (clobber (match_scratch:SI 3 "=&r,&r"))
13997 (clobber (match_scratch:SI 4 "=X,&r"))]
13998 "TARGET_32BIT"
13999 "@
14000 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
14001 #"
14002 [(set_attr "type" "compare")
14003 (set_attr "length" "8,12")])
14004
14005 (define_split
14006 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14007 (compare:CC
14008 (plus:SI (lshiftrt:SI
14009 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14010 (const_int 31))
14011 (match_operand:SI 2 "gpc_reg_operand" ""))
14012 (const_int 0)))
14013 (clobber (match_scratch:SI 3 ""))
14014 (clobber (match_scratch:SI 4 ""))]
14015 "TARGET_32BIT && reload_completed"
14016 [(parallel [(set (match_dup 3)
14017 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
14018 (const_int 31))
14019 (match_dup 2)))
14020 (clobber (match_dup 4))])
14021 (set (match_dup 0)
14022 (compare:CC (match_dup 3)
14023 (const_int 0)))]
14024 "")
14025
14026 (define_insn "*compare_plus_ne0di"
14027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14028 (compare:CC
14029 (plus:DI (lshiftrt:DI
14030 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14031 (const_int 63))
14032 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14033 (const_int 0)))
14034 (clobber (match_scratch:DI 3 "=&r,&r"))]
14035 "TARGET_64BIT"
14036 "@
14037 addic %3,%1,-1\;addze. %3,%2
14038 #"
14039 [(set_attr "type" "compare")
14040 (set_attr "length" "8,12")])
14041
14042 (define_split
14043 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14044 (compare:CC
14045 (plus:DI (lshiftrt:DI
14046 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14047 (const_int 63))
14048 (match_operand:DI 2 "gpc_reg_operand" ""))
14049 (const_int 0)))
14050 (clobber (match_scratch:DI 3 ""))]
14051 "TARGET_64BIT && reload_completed"
14052 [(set (match_dup 3)
14053 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
14054 (const_int 63))
14055 (match_dup 2)))
14056 (set (match_dup 0)
14057 (compare:CC (match_dup 3)
14058 (const_int 0)))]
14059 "")
14060
14061 (define_insn "*plus_ne0si_compare"
14062 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14063 (compare:CC
14064 (plus:SI (lshiftrt:SI
14065 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
14066 (const_int 31))
14067 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14068 (const_int 0)))
14069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14070 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14071 (match_dup 2)))
14072 (clobber (match_scratch:SI 3 "=&r,&r"))]
14073 "TARGET_32BIT"
14074 "@
14075 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
14076 #"
14077 [(set_attr "type" "compare")
14078 (set_attr "length" "8,12")])
14079
14080 (define_split
14081 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14082 (compare:CC
14083 (plus:SI (lshiftrt:SI
14084 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14085 (const_int 31))
14086 (match_operand:SI 2 "gpc_reg_operand" ""))
14087 (const_int 0)))
14088 (set (match_operand:SI 0 "gpc_reg_operand" "")
14089 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14090 (match_dup 2)))
14091 (clobber (match_scratch:SI 3 ""))]
14092 "TARGET_32BIT && reload_completed"
14093 [(parallel [(set (match_dup 0)
14094 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14095 (match_dup 2)))
14096 (clobber (match_dup 3))])
14097 (set (match_dup 4)
14098 (compare:CC (match_dup 0)
14099 (const_int 0)))]
14100 "")
14101
14102 (define_insn "*plus_ne0di_compare"
14103 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14104 (compare:CC
14105 (plus:DI (lshiftrt:DI
14106 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14107 (const_int 63))
14108 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14109 (const_int 0)))
14110 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
14111 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14112 (match_dup 2)))
14113 (clobber (match_scratch:DI 3 "=&r,&r"))]
14114 "TARGET_64BIT"
14115 "@
14116 addic %3,%1,-1\;addze. %0,%2
14117 #"
14118 [(set_attr "type" "compare")
14119 (set_attr "length" "8,12")])
14120
14121 (define_split
14122 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
14123 (compare:CC
14124 (plus:DI (lshiftrt:DI
14125 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14126 (const_int 63))
14127 (match_operand:DI 2 "gpc_reg_operand" ""))
14128 (const_int 0)))
14129 (set (match_operand:DI 0 "gpc_reg_operand" "")
14130 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14131 (match_dup 2)))
14132 (clobber (match_scratch:DI 3 ""))]
14133 "TARGET_64BIT && reload_completed"
14134 [(parallel [(set (match_dup 0)
14135 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14136 (match_dup 2)))
14137 (clobber (match_dup 3))])
14138 (set (match_dup 4)
14139 (compare:CC (match_dup 0)
14140 (const_int 0)))]
14141 "")
14142
14143 (define_insn ""
14144 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14145 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14146 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
14147 (clobber (match_scratch:SI 3 "=r,X"))]
14148 "TARGET_POWER"
14149 "@
14150 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
14151 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
14152 [(set_attr "length" "12")])
14153
14154 (define_insn ""
14155 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14156 (compare:CC
14157 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14158 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14159 (const_int 0)))
14160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
14161 (le:SI (match_dup 1) (match_dup 2)))
14162 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
14163 "TARGET_POWER"
14164 "@
14165 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14166 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
14167 #
14168 #"
14169 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
14170 (set_attr "length" "12,12,16,16")])
14171
14172 (define_split
14173 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14174 (compare:CC
14175 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14176 (match_operand:SI 2 "reg_or_short_operand" ""))
14177 (const_int 0)))
14178 (set (match_operand:SI 0 "gpc_reg_operand" "")
14179 (le:SI (match_dup 1) (match_dup 2)))
14180 (clobber (match_scratch:SI 3 ""))]
14181 "TARGET_POWER && reload_completed"
14182 [(parallel [(set (match_dup 0)
14183 (le:SI (match_dup 1) (match_dup 2)))
14184 (clobber (match_dup 3))])
14185 (set (match_dup 4)
14186 (compare:CC (match_dup 0)
14187 (const_int 0)))]
14188 "")
14189
14190 (define_insn ""
14191 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14192 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14193 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
14194 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
14195 "TARGET_POWER"
14196 "@
14197 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
14198 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
14199 [(set_attr "length" "12")])
14200
14201 (define_insn ""
14202 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14203 (compare:CC
14204 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14205 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14206 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14207 (const_int 0)))
14208 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14209 "TARGET_POWER"
14210 "@
14211 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14212 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
14213 #
14214 #"
14215 [(set_attr "type" "compare")
14216 (set_attr "length" "12,12,16,16")])
14217
14218 (define_split
14219 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14220 (compare:CC
14221 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14222 (match_operand:SI 2 "reg_or_short_operand" ""))
14223 (match_operand:SI 3 "gpc_reg_operand" ""))
14224 (const_int 0)))
14225 (clobber (match_scratch:SI 4 ""))]
14226 "TARGET_POWER && reload_completed"
14227 [(set (match_dup 4)
14228 (plus:SI (le:SI (match_dup 1) (match_dup 2))
14229 (match_dup 3)))
14230 (set (match_dup 0)
14231 (compare:CC (match_dup 4)
14232 (const_int 0)))]
14233 "")
14234
14235 (define_insn ""
14236 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14237 (compare:CC
14238 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14239 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14240 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14241 (const_int 0)))
14242 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14243 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14244 "TARGET_POWER"
14245 "@
14246 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14247 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
14248 #
14249 #"
14250 [(set_attr "type" "compare")
14251 (set_attr "length" "12,12,16,16")])
14252
14253 (define_split
14254 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14255 (compare:CC
14256 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14257 (match_operand:SI 2 "reg_or_short_operand" ""))
14258 (match_operand:SI 3 "gpc_reg_operand" ""))
14259 (const_int 0)))
14260 (set (match_operand:SI 0 "gpc_reg_operand" "")
14261 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14262 "TARGET_POWER && reload_completed"
14263 [(set (match_dup 0)
14264 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14265 (set (match_dup 4)
14266 (compare:CC (match_dup 0)
14267 (const_int 0)))]
14268 "")
14269
14270 (define_insn ""
14271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14272 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14273 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
14274 "TARGET_POWER"
14275 "@
14276 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
14277 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
14278 [(set_attr "length" "12")])
14279
14280 (define_insn "*leu<mode>"
14281 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14282 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14283 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14284 ""
14285 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14286 [(set_attr "type" "three")
14287 (set_attr "length" "12")])
14288
14289 (define_insn "*leu<mode>_compare"
14290 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14291 (compare:CC
14292 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14293 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14294 (const_int 0)))
14295 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14296 (leu:P (match_dup 1) (match_dup 2)))]
14297 ""
14298 "@
14299 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14300 #"
14301 [(set_attr "type" "compare")
14302 (set_attr "length" "12,16")])
14303
14304 (define_split
14305 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14306 (compare:CC
14307 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
14308 (match_operand:P 2 "reg_or_short_operand" ""))
14309 (const_int 0)))
14310 (set (match_operand:P 0 "gpc_reg_operand" "")
14311 (leu:P (match_dup 1) (match_dup 2)))]
14312 "reload_completed"
14313 [(set (match_dup 0)
14314 (leu:P (match_dup 1) (match_dup 2)))
14315 (set (match_dup 3)
14316 (compare:CC (match_dup 0)
14317 (const_int 0)))]
14318 "")
14319
14320 (define_insn "*plus_leu<mode>"
14321 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14322 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14323 (match_operand:P 2 "reg_or_short_operand" "rI"))
14324 (match_operand:P 3 "gpc_reg_operand" "r")))]
14325 ""
14326 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
14327 [(set_attr "type" "two")
14328 (set_attr "length" "8")])
14329
14330 (define_insn ""
14331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14332 (compare:CC
14333 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14334 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14335 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14336 (const_int 0)))
14337 (clobber (match_scratch:SI 4 "=&r,&r"))]
14338 "TARGET_32BIT"
14339 "@
14340 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
14341 #"
14342 [(set_attr "type" "compare")
14343 (set_attr "length" "8,12")])
14344
14345 (define_split
14346 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14347 (compare:CC
14348 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14349 (match_operand:SI 2 "reg_or_short_operand" ""))
14350 (match_operand:SI 3 "gpc_reg_operand" ""))
14351 (const_int 0)))
14352 (clobber (match_scratch:SI 4 ""))]
14353 "TARGET_32BIT && reload_completed"
14354 [(set (match_dup 4)
14355 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
14356 (match_dup 3)))
14357 (set (match_dup 0)
14358 (compare:CC (match_dup 4)
14359 (const_int 0)))]
14360 "")
14361
14362 (define_insn ""
14363 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14364 (compare:CC
14365 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14366 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14367 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14368 (const_int 0)))
14369 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14370 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14371 "TARGET_32BIT"
14372 "@
14373 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
14374 #"
14375 [(set_attr "type" "compare")
14376 (set_attr "length" "8,12")])
14377
14378 (define_split
14379 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14380 (compare:CC
14381 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14382 (match_operand:SI 2 "reg_or_short_operand" ""))
14383 (match_operand:SI 3 "gpc_reg_operand" ""))
14384 (const_int 0)))
14385 (set (match_operand:SI 0 "gpc_reg_operand" "")
14386 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14387 "TARGET_32BIT && reload_completed"
14388 [(set (match_dup 0)
14389 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14390 (set (match_dup 4)
14391 (compare:CC (match_dup 0)
14392 (const_int 0)))]
14393 "")
14394
14395 (define_insn "*neg_leu<mode>"
14396 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14397 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14398 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14399 ""
14400 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
14401 [(set_attr "type" "three")
14402 (set_attr "length" "12")])
14403
14404 (define_insn "*and_neg_leu<mode>"
14405 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14406 (and:P (neg:P
14407 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14408 (match_operand:P 2 "reg_or_short_operand" "rI")))
14409 (match_operand:P 3 "gpc_reg_operand" "r")))]
14410 ""
14411 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14412 [(set_attr "type" "three")
14413 (set_attr "length" "12")])
14414
14415 (define_insn ""
14416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14417 (compare:CC
14418 (and:SI (neg:SI
14419 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14420 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14421 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14422 (const_int 0)))
14423 (clobber (match_scratch:SI 4 "=&r,&r"))]
14424 "TARGET_32BIT"
14425 "@
14426 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14427 #"
14428 [(set_attr "type" "compare")
14429 (set_attr "length" "12,16")])
14430
14431 (define_split
14432 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14433 (compare:CC
14434 (and:SI (neg:SI
14435 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14436 (match_operand:SI 2 "reg_or_short_operand" "")))
14437 (match_operand:SI 3 "gpc_reg_operand" ""))
14438 (const_int 0)))
14439 (clobber (match_scratch:SI 4 ""))]
14440 "TARGET_32BIT && reload_completed"
14441 [(set (match_dup 4)
14442 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14443 (match_dup 3)))
14444 (set (match_dup 0)
14445 (compare:CC (match_dup 4)
14446 (const_int 0)))]
14447 "")
14448
14449 (define_insn ""
14450 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14451 (compare:CC
14452 (and:SI (neg:SI
14453 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14454 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14455 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14456 (const_int 0)))
14457 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14458 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14459 "TARGET_32BIT"
14460 "@
14461 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14462 #"
14463 [(set_attr "type" "compare")
14464 (set_attr "length" "12,16")])
14465
14466 (define_split
14467 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14468 (compare:CC
14469 (and:SI (neg:SI
14470 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14471 (match_operand:SI 2 "reg_or_short_operand" "")))
14472 (match_operand:SI 3 "gpc_reg_operand" ""))
14473 (const_int 0)))
14474 (set (match_operand:SI 0 "gpc_reg_operand" "")
14475 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14476 "TARGET_32BIT && reload_completed"
14477 [(set (match_dup 0)
14478 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14479 (match_dup 3)))
14480 (set (match_dup 4)
14481 (compare:CC (match_dup 0)
14482 (const_int 0)))]
14483 "")
14484
14485 (define_insn ""
14486 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14487 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14488 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
14489 "TARGET_POWER"
14490 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14491 [(set_attr "length" "12")])
14492
14493 (define_insn ""
14494 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14495 (compare:CC
14496 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14497 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14498 (const_int 0)))
14499 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14500 (lt:SI (match_dup 1) (match_dup 2)))]
14501 "TARGET_POWER"
14502 "@
14503 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14504 #"
14505 [(set_attr "type" "delayed_compare")
14506 (set_attr "length" "12,16")])
14507
14508 (define_split
14509 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14510 (compare:CC
14511 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14512 (match_operand:SI 2 "reg_or_short_operand" ""))
14513 (const_int 0)))
14514 (set (match_operand:SI 0 "gpc_reg_operand" "")
14515 (lt:SI (match_dup 1) (match_dup 2)))]
14516 "TARGET_POWER && reload_completed"
14517 [(set (match_dup 0)
14518 (lt:SI (match_dup 1) (match_dup 2)))
14519 (set (match_dup 3)
14520 (compare:CC (match_dup 0)
14521 (const_int 0)))]
14522 "")
14523
14524 (define_insn ""
14525 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14526 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14527 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14528 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14529 "TARGET_POWER"
14530 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14531 [(set_attr "length" "12")])
14532
14533 (define_insn ""
14534 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14535 (compare:CC
14536 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14537 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14538 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14539 (const_int 0)))
14540 (clobber (match_scratch:SI 4 "=&r,&r"))]
14541 "TARGET_POWER"
14542 "@
14543 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14544 #"
14545 [(set_attr "type" "compare")
14546 (set_attr "length" "12,16")])
14547
14548 (define_split
14549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14550 (compare:CC
14551 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14552 (match_operand:SI 2 "reg_or_short_operand" ""))
14553 (match_operand:SI 3 "gpc_reg_operand" ""))
14554 (const_int 0)))
14555 (clobber (match_scratch:SI 4 ""))]
14556 "TARGET_POWER && reload_completed"
14557 [(set (match_dup 4)
14558 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14559 (match_dup 3)))
14560 (set (match_dup 0)
14561 (compare:CC (match_dup 4)
14562 (const_int 0)))]
14563 "")
14564
14565 (define_insn ""
14566 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14567 (compare:CC
14568 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14569 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14570 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14571 (const_int 0)))
14572 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14573 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14574 "TARGET_POWER"
14575 "@
14576 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14577 #"
14578 [(set_attr "type" "compare")
14579 (set_attr "length" "12,16")])
14580
14581 (define_split
14582 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14583 (compare:CC
14584 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14585 (match_operand:SI 2 "reg_or_short_operand" ""))
14586 (match_operand:SI 3 "gpc_reg_operand" ""))
14587 (const_int 0)))
14588 (set (match_operand:SI 0 "gpc_reg_operand" "")
14589 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14590 "TARGET_POWER && reload_completed"
14591 [(set (match_dup 0)
14592 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14593 (set (match_dup 4)
14594 (compare:CC (match_dup 0)
14595 (const_int 0)))]
14596 "")
14597
14598 (define_insn ""
14599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14600 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14601 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14602 "TARGET_POWER"
14603 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14604 [(set_attr "length" "12")])
14605
14606 (define_insn_and_split "*ltu<mode>"
14607 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14608 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14609 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14610 ""
14611 "#"
14612 ""
14613 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14614 (set (match_dup 0) (neg:P (match_dup 0)))]
14615 "")
14616
14617 (define_insn_and_split "*ltu<mode>_compare"
14618 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14619 (compare:CC
14620 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14621 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14622 (const_int 0)))
14623 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14624 (ltu:P (match_dup 1) (match_dup 2)))]
14625 ""
14626 "#"
14627 ""
14628 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14629 (parallel [(set (match_dup 3)
14630 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14631 (set (match_dup 0) (neg:P (match_dup 0)))])]
14632 "")
14633
14634 (define_insn_and_split "*plus_ltu<mode>"
14635 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14636 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14637 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14638 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14639 ""
14640 "#"
14641 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14642 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14643 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14644 "")
14645
14646 (define_insn_and_split "*plus_ltu<mode>_compare"
14647 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14648 (compare:CC
14649 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14650 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14651 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14652 (const_int 0)))
14653 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14654 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14655 ""
14656 "#"
14657 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14658 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14659 (parallel [(set (match_dup 4)
14660 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14661 (const_int 0)))
14662 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14663 "")
14664
14665 (define_insn "*neg_ltu<mode>"
14666 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14667 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14668 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14669 ""
14670 "@
14671 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14672 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14673 [(set_attr "type" "two")
14674 (set_attr "length" "8")])
14675
14676 (define_insn ""
14677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14678 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14679 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14680 (clobber (match_scratch:SI 3 "=r"))]
14681 "TARGET_POWER"
14682 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14683 [(set_attr "length" "12")])
14684
14685 (define_insn ""
14686 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14687 (compare:CC
14688 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14689 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14690 (const_int 0)))
14691 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14692 (ge:SI (match_dup 1) (match_dup 2)))
14693 (clobber (match_scratch:SI 3 "=r,r"))]
14694 "TARGET_POWER"
14695 "@
14696 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14697 #"
14698 [(set_attr "type" "compare")
14699 (set_attr "length" "12,16")])
14700
14701 (define_split
14702 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14703 (compare:CC
14704 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14705 (match_operand:SI 2 "reg_or_short_operand" ""))
14706 (const_int 0)))
14707 (set (match_operand:SI 0 "gpc_reg_operand" "")
14708 (ge:SI (match_dup 1) (match_dup 2)))
14709 (clobber (match_scratch:SI 3 ""))]
14710 "TARGET_POWER && reload_completed"
14711 [(parallel [(set (match_dup 0)
14712 (ge:SI (match_dup 1) (match_dup 2)))
14713 (clobber (match_dup 3))])
14714 (set (match_dup 4)
14715 (compare:CC (match_dup 0)
14716 (const_int 0)))]
14717 "")
14718
14719 (define_insn ""
14720 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14721 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14722 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14723 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14724 "TARGET_POWER"
14725 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14726 [(set_attr "length" "12")])
14727
14728 (define_insn ""
14729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14730 (compare:CC
14731 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14732 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14733 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14734 (const_int 0)))
14735 (clobber (match_scratch:SI 4 "=&r,&r"))]
14736 "TARGET_POWER"
14737 "@
14738 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14739 #"
14740 [(set_attr "type" "compare")
14741 (set_attr "length" "12,16")])
14742
14743 (define_split
14744 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14745 (compare:CC
14746 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14747 (match_operand:SI 2 "reg_or_short_operand" ""))
14748 (match_operand:SI 3 "gpc_reg_operand" ""))
14749 (const_int 0)))
14750 (clobber (match_scratch:SI 4 ""))]
14751 "TARGET_POWER && reload_completed"
14752 [(set (match_dup 4)
14753 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14754 (match_dup 3)))
14755 (set (match_dup 0)
14756 (compare:CC (match_dup 4)
14757 (const_int 0)))]
14758 "")
14759
14760 (define_insn ""
14761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14762 (compare:CC
14763 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14764 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14765 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14766 (const_int 0)))
14767 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14768 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14769 "TARGET_POWER"
14770 "@
14771 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14772 #"
14773 [(set_attr "type" "compare")
14774 (set_attr "length" "12,16")])
14775
14776 (define_split
14777 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14778 (compare:CC
14779 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14780 (match_operand:SI 2 "reg_or_short_operand" ""))
14781 (match_operand:SI 3 "gpc_reg_operand" ""))
14782 (const_int 0)))
14783 (set (match_operand:SI 0 "gpc_reg_operand" "")
14784 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14785 "TARGET_POWER && reload_completed"
14786 [(set (match_dup 0)
14787 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14788 (set (match_dup 4)
14789 (compare:CC (match_dup 0)
14790 (const_int 0)))]
14791 "")
14792
14793 (define_insn ""
14794 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14795 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14796 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14797 "TARGET_POWER"
14798 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14799 [(set_attr "length" "12")])
14800
14801 (define_insn "*geu<mode>"
14802 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14803 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14804 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14805 ""
14806 "@
14807 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14808 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14809 [(set_attr "type" "three")
14810 (set_attr "length" "12")])
14811
14812 (define_insn "*geu<mode>_compare"
14813 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14814 (compare:CC
14815 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14816 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14817 (const_int 0)))
14818 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14819 (geu:P (match_dup 1) (match_dup 2)))]
14820 ""
14821 "@
14822 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14823 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14824 #
14825 #"
14826 [(set_attr "type" "compare")
14827 (set_attr "length" "12,12,16,16")])
14828
14829 (define_split
14830 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14831 (compare:CC
14832 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14833 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14834 (const_int 0)))
14835 (set (match_operand:P 0 "gpc_reg_operand" "")
14836 (geu:P (match_dup 1) (match_dup 2)))]
14837 "reload_completed"
14838 [(set (match_dup 0)
14839 (geu:P (match_dup 1) (match_dup 2)))
14840 (set (match_dup 3)
14841 (compare:CC (match_dup 0)
14842 (const_int 0)))]
14843 "")
14844
14845 (define_insn "*plus_geu<mode>"
14846 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14847 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14848 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14849 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14850 ""
14851 "@
14852 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14853 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14854 [(set_attr "type" "two")
14855 (set_attr "length" "8")])
14856
14857 (define_insn ""
14858 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14859 (compare:CC
14860 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14861 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14862 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14863 (const_int 0)))
14864 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14865 "TARGET_32BIT"
14866 "@
14867 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14868 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14869 #
14870 #"
14871 [(set_attr "type" "compare")
14872 (set_attr "length" "8,8,12,12")])
14873
14874 (define_split
14875 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14876 (compare:CC
14877 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14878 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14879 (match_operand:SI 3 "gpc_reg_operand" ""))
14880 (const_int 0)))
14881 (clobber (match_scratch:SI 4 ""))]
14882 "TARGET_32BIT && reload_completed"
14883 [(set (match_dup 4)
14884 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14885 (match_dup 3)))
14886 (set (match_dup 0)
14887 (compare:CC (match_dup 4)
14888 (const_int 0)))]
14889 "")
14890
14891 (define_insn ""
14892 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14893 (compare:CC
14894 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14895 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14896 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14897 (const_int 0)))
14898 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14899 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14900 "TARGET_32BIT"
14901 "@
14902 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14903 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14904 #
14905 #"
14906 [(set_attr "type" "compare")
14907 (set_attr "length" "8,8,12,12")])
14908
14909 (define_split
14910 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14911 (compare:CC
14912 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14913 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14914 (match_operand:SI 3 "gpc_reg_operand" ""))
14915 (const_int 0)))
14916 (set (match_operand:SI 0 "gpc_reg_operand" "")
14917 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14918 "TARGET_32BIT && reload_completed"
14919 [(set (match_dup 0)
14920 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14921 (set (match_dup 4)
14922 (compare:CC (match_dup 0)
14923 (const_int 0)))]
14924 "")
14925
14926 (define_insn "*neg_geu<mode>"
14927 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14928 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14929 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14930 ""
14931 "@
14932 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14933 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14934 [(set_attr "type" "three")
14935 (set_attr "length" "12")])
14936
14937 (define_insn "*and_neg_geu<mode>"
14938 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14939 (and:P (neg:P
14940 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14941 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14942 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14943 ""
14944 "@
14945 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14946 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14947 [(set_attr "type" "three")
14948 (set_attr "length" "12")])
14949
14950 (define_insn ""
14951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14952 (compare:CC
14953 (and:SI (neg:SI
14954 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14955 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14956 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14957 (const_int 0)))
14958 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14959 "TARGET_32BIT"
14960 "@
14961 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14962 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14963 #
14964 #"
14965 [(set_attr "type" "compare")
14966 (set_attr "length" "12,12,16,16")])
14967
14968 (define_split
14969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14970 (compare:CC
14971 (and:SI (neg:SI
14972 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14973 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14974 (match_operand:SI 3 "gpc_reg_operand" ""))
14975 (const_int 0)))
14976 (clobber (match_scratch:SI 4 ""))]
14977 "TARGET_32BIT && reload_completed"
14978 [(set (match_dup 4)
14979 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14980 (match_dup 3)))
14981 (set (match_dup 0)
14982 (compare:CC (match_dup 4)
14983 (const_int 0)))]
14984 "")
14985
14986 (define_insn ""
14987 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14988 (compare:CC
14989 (and:SI (neg:SI
14990 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14991 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14992 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14993 (const_int 0)))
14994 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14995 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14996 "TARGET_32BIT"
14997 "@
14998 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14999 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
15000 #
15001 #"
15002 [(set_attr "type" "compare")
15003 (set_attr "length" "12,12,16,16")])
15004
15005 (define_split
15006 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15007 (compare:CC
15008 (and:SI (neg:SI
15009 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
15010 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
15011 (match_operand:SI 3 "gpc_reg_operand" ""))
15012 (const_int 0)))
15013 (set (match_operand:SI 0 "gpc_reg_operand" "")
15014 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
15015 "TARGET_32BIT && reload_completed"
15016 [(set (match_dup 0)
15017 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
15018 (set (match_dup 4)
15019 (compare:CC (match_dup 0)
15020 (const_int 0)))]
15021 "")
15022
15023 (define_insn ""
15024 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15025 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15026 (match_operand:SI 2 "reg_or_short_operand" "r")))]
15027 "TARGET_POWER"
15028 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
15029 [(set_attr "length" "12")])
15030
15031 (define_insn ""
15032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15033 (compare:CC
15034 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15035 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15036 (const_int 0)))
15037 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
15038 (gt:SI (match_dup 1) (match_dup 2)))]
15039 "TARGET_POWER"
15040 "@
15041 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
15042 #"
15043 [(set_attr "type" "delayed_compare")
15044 (set_attr "length" "12,16")])
15045
15046 (define_split
15047 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15048 (compare:CC
15049 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15050 (match_operand:SI 2 "reg_or_short_operand" ""))
15051 (const_int 0)))
15052 (set (match_operand:SI 0 "gpc_reg_operand" "")
15053 (gt:SI (match_dup 1) (match_dup 2)))]
15054 "TARGET_POWER && reload_completed"
15055 [(set (match_dup 0)
15056 (gt:SI (match_dup 1) (match_dup 2)))
15057 (set (match_dup 3)
15058 (compare:CC (match_dup 0)
15059 (const_int 0)))]
15060 "")
15061
15062 (define_insn "*plus_gt0<mode>"
15063 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15064 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
15065 (const_int 0))
15066 (match_operand:P 2 "gpc_reg_operand" "r")))]
15067 ""
15068 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
15069 [(set_attr "type" "three")
15070 (set_attr "length" "12")])
15071
15072 (define_insn ""
15073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15074 (compare:CC
15075 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15076 (const_int 0))
15077 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15078 (const_int 0)))
15079 (clobber (match_scratch:SI 3 "=&r,&r"))]
15080 "TARGET_32BIT"
15081 "@
15082 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
15083 #"
15084 [(set_attr "type" "compare")
15085 (set_attr "length" "12,16")])
15086
15087 (define_split
15088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15089 (compare:CC
15090 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15091 (const_int 0))
15092 (match_operand:SI 2 "gpc_reg_operand" ""))
15093 (const_int 0)))
15094 (clobber (match_scratch:SI 3 ""))]
15095 "TARGET_32BIT && reload_completed"
15096 [(set (match_dup 3)
15097 (plus:SI (gt:SI (match_dup 1) (const_int 0))
15098 (match_dup 2)))
15099 (set (match_dup 0)
15100 (compare:CC (match_dup 3)
15101 (const_int 0)))]
15102 "")
15103
15104 (define_insn ""
15105 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15106 (compare:CC
15107 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15108 (const_int 0))
15109 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15110 (const_int 0)))
15111 (clobber (match_scratch:DI 3 "=&r,&r"))]
15112 "TARGET_64BIT"
15113 "@
15114 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
15115 #"
15116 [(set_attr "type" "compare")
15117 (set_attr "length" "12,16")])
15118
15119 (define_split
15120 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
15121 (compare:CC
15122 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15123 (const_int 0))
15124 (match_operand:DI 2 "gpc_reg_operand" ""))
15125 (const_int 0)))
15126 (clobber (match_scratch:DI 3 ""))]
15127 "TARGET_64BIT && reload_completed"
15128 [(set (match_dup 3)
15129 (plus:DI (gt:DI (match_dup 1) (const_int 0))
15130 (match_dup 2)))
15131 (set (match_dup 0)
15132 (compare:CC (match_dup 3)
15133 (const_int 0)))]
15134 "")
15135
15136 (define_insn ""
15137 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15138 (compare:CC
15139 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15140 (const_int 0))
15141 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15142 (const_int 0)))
15143 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15144 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15145 "TARGET_32BIT"
15146 "@
15147 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
15148 #"
15149 [(set_attr "type" "compare")
15150 (set_attr "length" "12,16")])
15151
15152 (define_split
15153 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15154 (compare:CC
15155 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15156 (const_int 0))
15157 (match_operand:SI 2 "gpc_reg_operand" ""))
15158 (const_int 0)))
15159 (set (match_operand:SI 0 "gpc_reg_operand" "")
15160 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15161 "TARGET_32BIT && reload_completed"
15162 [(set (match_dup 0)
15163 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
15164 (set (match_dup 3)
15165 (compare:CC (match_dup 0)
15166 (const_int 0)))]
15167 "")
15168
15169 (define_insn ""
15170 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15171 (compare:CC
15172 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15173 (const_int 0))
15174 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15175 (const_int 0)))
15176 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
15177 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15178 "TARGET_64BIT"
15179 "@
15180 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
15181 #"
15182 [(set_attr "type" "compare")
15183 (set_attr "length" "12,16")])
15184
15185 (define_split
15186 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
15187 (compare:CC
15188 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15189 (const_int 0))
15190 (match_operand:DI 2 "gpc_reg_operand" ""))
15191 (const_int 0)))
15192 (set (match_operand:DI 0 "gpc_reg_operand" "")
15193 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15194 "TARGET_64BIT && reload_completed"
15195 [(set (match_dup 0)
15196 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
15197 (set (match_dup 3)
15198 (compare:CC (match_dup 0)
15199 (const_int 0)))]
15200 "")
15201
15202 (define_insn ""
15203 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
15204 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15205 (match_operand:SI 2 "reg_or_short_operand" "r"))
15206 (match_operand:SI 3 "gpc_reg_operand" "r")))]
15207 "TARGET_POWER"
15208 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
15209 [(set_attr "length" "12")])
15210
15211 (define_insn ""
15212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15213 (compare:CC
15214 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15215 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15216 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15217 (const_int 0)))
15218 (clobber (match_scratch:SI 4 "=&r,&r"))]
15219 "TARGET_POWER"
15220 "@
15221 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
15222 #"
15223 [(set_attr "type" "compare")
15224 (set_attr "length" "12,16")])
15225
15226 (define_split
15227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15228 (compare:CC
15229 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15230 (match_operand:SI 2 "reg_or_short_operand" ""))
15231 (match_operand:SI 3 "gpc_reg_operand" ""))
15232 (const_int 0)))
15233 (clobber (match_scratch:SI 4 ""))]
15234 "TARGET_POWER && reload_completed"
15235 [(set (match_dup 4)
15236 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15237 (set (match_dup 0)
15238 (compare:CC (match_dup 4)
15239 (const_int 0)))]
15240 "")
15241
15242 (define_insn ""
15243 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
15244 (compare:CC
15245 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15246 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15247 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15248 (const_int 0)))
15249 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15250 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15251 "TARGET_POWER"
15252 "@
15253 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
15254 #"
15255 [(set_attr "type" "compare")
15256 (set_attr "length" "12,16")])
15257
15258 (define_split
15259 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15260 (compare:CC
15261 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15262 (match_operand:SI 2 "reg_or_short_operand" ""))
15263 (match_operand:SI 3 "gpc_reg_operand" ""))
15264 (const_int 0)))
15265 (set (match_operand:SI 0 "gpc_reg_operand" "")
15266 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15267 "TARGET_POWER && reload_completed"
15268 [(set (match_dup 0)
15269 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15270 (set (match_dup 4)
15271 (compare:CC (match_dup 0)
15272 (const_int 0)))]
15273 "")
15274
15275 (define_insn ""
15276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15277 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15278 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
15279 "TARGET_POWER"
15280 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
15281 [(set_attr "length" "12")])
15282
15283 (define_insn_and_split "*gtu<mode>"
15284 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15285 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15286 (match_operand:P 2 "reg_or_short_operand" "rI")))]
15287 ""
15288 "#"
15289 ""
15290 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15291 (set (match_dup 0) (neg:P (match_dup 0)))]
15292 "")
15293
15294 (define_insn_and_split "*gtu<mode>_compare"
15295 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15296 (compare:CC
15297 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
15298 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
15299 (const_int 0)))
15300 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
15301 (gtu:P (match_dup 1) (match_dup 2)))]
15302 ""
15303 "#"
15304 ""
15305 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15306 (parallel [(set (match_dup 3)
15307 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
15308 (set (match_dup 0) (neg:P (match_dup 0)))])]
15309 "")
15310
15311 (define_insn_and_split "*plus_gtu<mode>"
15312 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15313 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15314 (match_operand:P 2 "reg_or_short_operand" "rI"))
15315 (match_operand:P 3 "reg_or_short_operand" "rI")))]
15316 ""
15317 "#"
15318 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15319 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15320 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
15321 "")
15322
15323 (define_insn_and_split "*plus_gtu<mode>_compare"
15324 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
15325 (compare:CC
15326 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
15327 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
15328 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
15329 (const_int 0)))
15330 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
15331 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
15332 ""
15333 "#"
15334 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15335 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15336 (parallel [(set (match_dup 4)
15337 (compare:CC (minus:P (match_dup 3) (match_dup 0))
15338 (const_int 0)))
15339 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
15340 "")
15341
15342 (define_insn "*neg_gtu<mode>"
15343 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15344 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15345 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
15346 ""
15347 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
15348 [(set_attr "type" "two")
15349 (set_attr "length" "8")])
15350
15351 \f
15352 ;; Define both directions of branch and return. If we need a reload
15353 ;; register, we'd rather use CR0 since it is much easier to copy a
15354 ;; register CC value to there.
15355
15356 (define_insn ""
15357 [(set (pc)
15358 (if_then_else (match_operator 1 "branch_comparison_operator"
15359 [(match_operand 2
15360 "cc_reg_operand" "y")
15361 (const_int 0)])
15362 (label_ref (match_operand 0 "" ""))
15363 (pc)))]
15364 ""
15365 "*
15366 {
15367 return output_cbranch (operands[1], \"%l0\", 0, insn);
15368 }"
15369 [(set_attr "type" "branch")])
15370
15371 (define_insn ""
15372 [(set (pc)
15373 (if_then_else (match_operator 0 "branch_comparison_operator"
15374 [(match_operand 1
15375 "cc_reg_operand" "y")
15376 (const_int 0)])
15377 (return)
15378 (pc)))]
15379 "direct_return ()"
15380 "*
15381 {
15382 return output_cbranch (operands[0], NULL, 0, insn);
15383 }"
15384 [(set_attr "type" "jmpreg")
15385 (set_attr "length" "4")])
15386
15387 (define_insn ""
15388 [(set (pc)
15389 (if_then_else (match_operator 1 "branch_comparison_operator"
15390 [(match_operand 2
15391 "cc_reg_operand" "y")
15392 (const_int 0)])
15393 (pc)
15394 (label_ref (match_operand 0 "" ""))))]
15395 ""
15396 "*
15397 {
15398 return output_cbranch (operands[1], \"%l0\", 1, insn);
15399 }"
15400 [(set_attr "type" "branch")])
15401
15402 (define_insn ""
15403 [(set (pc)
15404 (if_then_else (match_operator 0 "branch_comparison_operator"
15405 [(match_operand 1
15406 "cc_reg_operand" "y")
15407 (const_int 0)])
15408 (pc)
15409 (return)))]
15410 "direct_return ()"
15411 "*
15412 {
15413 return output_cbranch (operands[0], NULL, 1, insn);
15414 }"
15415 [(set_attr "type" "jmpreg")
15416 (set_attr "length" "4")])
15417
15418 ;; Logic on condition register values.
15419
15420 ; This pattern matches things like
15421 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
15422 ; (eq:SI (reg:CCFP 68) (const_int 0)))
15423 ; (const_int 1)))
15424 ; which are generated by the branch logic.
15425 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
15426
15427 (define_insn "*cceq_ior_compare"
15428 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15429 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
15430 [(match_operator:SI 2
15431 "branch_positive_comparison_operator"
15432 [(match_operand 3
15433 "cc_reg_operand" "y,y")
15434 (const_int 0)])
15435 (match_operator:SI 4
15436 "branch_positive_comparison_operator"
15437 [(match_operand 5
15438 "cc_reg_operand" "0,y")
15439 (const_int 0)])])
15440 (const_int 1)))]
15441 ""
15442 "cr%q1 %E0,%j2,%j4"
15443 [(set_attr "type" "cr_logical,delayed_cr")])
15444
15445 ; Why is the constant -1 here, but 1 in the previous pattern?
15446 ; Because ~1 has all but the low bit set.
15447 (define_insn ""
15448 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15449 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
15450 [(not:SI (match_operator:SI 2
15451 "branch_positive_comparison_operator"
15452 [(match_operand 3
15453 "cc_reg_operand" "y,y")
15454 (const_int 0)]))
15455 (match_operator:SI 4
15456 "branch_positive_comparison_operator"
15457 [(match_operand 5
15458 "cc_reg_operand" "0,y")
15459 (const_int 0)])])
15460 (const_int -1)))]
15461 ""
15462 "cr%q1 %E0,%j2,%j4"
15463 [(set_attr "type" "cr_logical,delayed_cr")])
15464
15465 (define_insn "*cceq_rev_compare"
15466 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15467 (compare:CCEQ (match_operator:SI 1
15468 "branch_positive_comparison_operator"
15469 [(match_operand 2
15470 "cc_reg_operand" "0,y")
15471 (const_int 0)])
15472 (const_int 0)))]
15473 ""
15474 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
15475 [(set_attr "type" "cr_logical,delayed_cr")])
15476
15477 ;; If we are comparing the result of two comparisons, this can be done
15478 ;; using creqv or crxor.
15479
15480 (define_insn_and_split ""
15481 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
15482 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
15483 [(match_operand 2 "cc_reg_operand" "y")
15484 (const_int 0)])
15485 (match_operator 3 "branch_comparison_operator"
15486 [(match_operand 4 "cc_reg_operand" "y")
15487 (const_int 0)])))]
15488 ""
15489 "#"
15490 ""
15491 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
15492 (match_dup 5)))]
15493 "
15494 {
15495 int positive_1, positive_2;
15496
15497 positive_1 = branch_positive_comparison_operator (operands[1],
15498 GET_MODE (operands[1]));
15499 positive_2 = branch_positive_comparison_operator (operands[3],
15500 GET_MODE (operands[3]));
15501
15502 if (! positive_1)
15503 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
15504 GET_CODE (operands[1])),
15505 SImode,
15506 operands[2], const0_rtx);
15507 else if (GET_MODE (operands[1]) != SImode)
15508 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
15509 operands[2], const0_rtx);
15510
15511 if (! positive_2)
15512 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
15513 GET_CODE (operands[3])),
15514 SImode,
15515 operands[4], const0_rtx);
15516 else if (GET_MODE (operands[3]) != SImode)
15517 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
15518 operands[4], const0_rtx);
15519
15520 if (positive_1 == positive_2)
15521 {
15522 operands[1] = gen_rtx_NOT (SImode, operands[1]);
15523 operands[5] = constm1_rtx;
15524 }
15525 else
15526 {
15527 operands[5] = const1_rtx;
15528 }
15529 }")
15530
15531 ;; Unconditional branch and return.
15532
15533 (define_insn "jump"
15534 [(set (pc)
15535 (label_ref (match_operand 0 "" "")))]
15536 ""
15537 "b %l0"
15538 [(set_attr "type" "branch")])
15539
15540 (define_insn "return"
15541 [(return)]
15542 "direct_return ()"
15543 "{br|blr}"
15544 [(set_attr "type" "jmpreg")])
15545
15546 (define_expand "indirect_jump"
15547 [(set (pc) (match_operand 0 "register_operand" ""))])
15548
15549 (define_insn "*indirect_jump<mode>"
15550 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15551 ""
15552 "@
15553 bctr
15554 {br|blr}"
15555 [(set_attr "type" "jmpreg")])
15556
15557 ;; Table jump for switch statements:
15558 (define_expand "tablejump"
15559 [(use (match_operand 0 "" ""))
15560 (use (label_ref (match_operand 1 "" "")))]
15561 ""
15562 "
15563 {
15564 if (TARGET_32BIT)
15565 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15566 else
15567 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15568 DONE;
15569 }")
15570
15571 (define_expand "tablejumpsi"
15572 [(set (match_dup 3)
15573 (plus:SI (match_operand:SI 0 "" "")
15574 (match_dup 2)))
15575 (parallel [(set (pc) (match_dup 3))
15576 (use (label_ref (match_operand 1 "" "")))])]
15577 "TARGET_32BIT"
15578 "
15579 { operands[0] = force_reg (SImode, operands[0]);
15580 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15581 operands[3] = gen_reg_rtx (SImode);
15582 }")
15583
15584 (define_expand "tablejumpdi"
15585 [(set (match_dup 4)
15586 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15587 (set (match_dup 3)
15588 (plus:DI (match_dup 4)
15589 (match_dup 2)))
15590 (parallel [(set (pc) (match_dup 3))
15591 (use (label_ref (match_operand 1 "" "")))])]
15592 "TARGET_64BIT"
15593 "
15594 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15595 operands[3] = gen_reg_rtx (DImode);
15596 operands[4] = gen_reg_rtx (DImode);
15597 }")
15598
15599 (define_insn "*tablejump<mode>_internal1"
15600 [(set (pc)
15601 (match_operand:P 0 "register_operand" "c,*l"))
15602 (use (label_ref (match_operand 1 "" "")))]
15603 ""
15604 "@
15605 bctr
15606 {br|blr}"
15607 [(set_attr "type" "jmpreg")])
15608
15609 (define_insn "nop"
15610 [(const_int 0)]
15611 ""
15612 "{cror 0,0,0|nop}")
15613 \f
15614 ;; Define the subtract-one-and-jump insns, starting with the template
15615 ;; so loop.c knows what to generate.
15616
15617 (define_expand "doloop_end"
15618 [(use (match_operand 0 "" "")) ; loop pseudo
15619 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15620 (use (match_operand 2 "" "")) ; max iterations
15621 (use (match_operand 3 "" "")) ; loop level
15622 (use (match_operand 4 "" ""))] ; label
15623 ""
15624 "
15625 {
15626 /* Only use this on innermost loops. */
15627 if (INTVAL (operands[3]) > 1)
15628 FAIL;
15629 if (TARGET_64BIT)
15630 {
15631 if (GET_MODE (operands[0]) != DImode)
15632 FAIL;
15633 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15634 }
15635 else
15636 {
15637 if (GET_MODE (operands[0]) != SImode)
15638 FAIL;
15639 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15640 }
15641 DONE;
15642 }")
15643
15644 (define_expand "ctr<mode>"
15645 [(parallel [(set (pc)
15646 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15647 (const_int 1))
15648 (label_ref (match_operand 1 "" ""))
15649 (pc)))
15650 (set (match_dup 0)
15651 (plus:P (match_dup 0)
15652 (const_int -1)))
15653 (clobber (match_scratch:CC 2 ""))
15654 (clobber (match_scratch:P 3 ""))])]
15655 ""
15656 "")
15657
15658 ;; We need to be able to do this for any operand, including MEM, or we
15659 ;; will cause reload to blow up since we don't allow output reloads on
15660 ;; JUMP_INSNs.
15661 ;; For the length attribute to be calculated correctly, the
15662 ;; label MUST be operand 0.
15663
15664 (define_insn "*ctr<mode>_internal1"
15665 [(set (pc)
15666 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15667 (const_int 1))
15668 (label_ref (match_operand 0 "" ""))
15669 (pc)))
15670 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15671 (plus:P (match_dup 1)
15672 (const_int -1)))
15673 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15674 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15675 ""
15676 "*
15677 {
15678 if (which_alternative != 0)
15679 return \"#\";
15680 else if (get_attr_length (insn) == 4)
15681 return \"{bdn|bdnz} %l0\";
15682 else
15683 return \"bdz $+8\;b %l0\";
15684 }"
15685 [(set_attr "type" "branch")
15686 (set_attr "length" "*,12,16,16")])
15687
15688 (define_insn "*ctr<mode>_internal2"
15689 [(set (pc)
15690 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15691 (const_int 1))
15692 (pc)
15693 (label_ref (match_operand 0 "" ""))))
15694 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15695 (plus:P (match_dup 1)
15696 (const_int -1)))
15697 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15698 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15699 ""
15700 "*
15701 {
15702 if (which_alternative != 0)
15703 return \"#\";
15704 else if (get_attr_length (insn) == 4)
15705 return \"bdz %l0\";
15706 else
15707 return \"{bdn|bdnz} $+8\;b %l0\";
15708 }"
15709 [(set_attr "type" "branch")
15710 (set_attr "length" "*,12,16,16")])
15711
15712 ;; Similar but use EQ
15713
15714 (define_insn "*ctr<mode>_internal5"
15715 [(set (pc)
15716 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15717 (const_int 1))
15718 (label_ref (match_operand 0 "" ""))
15719 (pc)))
15720 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15721 (plus:P (match_dup 1)
15722 (const_int -1)))
15723 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15724 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15725 ""
15726 "*
15727 {
15728 if (which_alternative != 0)
15729 return \"#\";
15730 else if (get_attr_length (insn) == 4)
15731 return \"bdz %l0\";
15732 else
15733 return \"{bdn|bdnz} $+8\;b %l0\";
15734 }"
15735 [(set_attr "type" "branch")
15736 (set_attr "length" "*,12,16,16")])
15737
15738 (define_insn "*ctr<mode>_internal6"
15739 [(set (pc)
15740 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15741 (const_int 1))
15742 (pc)
15743 (label_ref (match_operand 0 "" ""))))
15744 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15745 (plus:P (match_dup 1)
15746 (const_int -1)))
15747 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15748 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15749 ""
15750 "*
15751 {
15752 if (which_alternative != 0)
15753 return \"#\";
15754 else if (get_attr_length (insn) == 4)
15755 return \"{bdn|bdnz} %l0\";
15756 else
15757 return \"bdz $+8\;b %l0\";
15758 }"
15759 [(set_attr "type" "branch")
15760 (set_attr "length" "*,12,16,16")])
15761
15762 ;; Now the splitters if we could not allocate the CTR register
15763
15764 (define_split
15765 [(set (pc)
15766 (if_then_else (match_operator 2 "comparison_operator"
15767 [(match_operand:P 1 "gpc_reg_operand" "")
15768 (const_int 1)])
15769 (match_operand 5 "" "")
15770 (match_operand 6 "" "")))
15771 (set (match_operand:P 0 "gpc_reg_operand" "")
15772 (plus:P (match_dup 1) (const_int -1)))
15773 (clobber (match_scratch:CC 3 ""))
15774 (clobber (match_scratch:P 4 ""))]
15775 "reload_completed"
15776 [(parallel [(set (match_dup 3)
15777 (compare:CC (plus:P (match_dup 1)
15778 (const_int -1))
15779 (const_int 0)))
15780 (set (match_dup 0)
15781 (plus:P (match_dup 1)
15782 (const_int -1)))])
15783 (set (pc) (if_then_else (match_dup 7)
15784 (match_dup 5)
15785 (match_dup 6)))]
15786 "
15787 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15788 operands[3], const0_rtx); }")
15789
15790 (define_split
15791 [(set (pc)
15792 (if_then_else (match_operator 2 "comparison_operator"
15793 [(match_operand:P 1 "gpc_reg_operand" "")
15794 (const_int 1)])
15795 (match_operand 5 "" "")
15796 (match_operand 6 "" "")))
15797 (set (match_operand:P 0 "nonimmediate_operand" "")
15798 (plus:P (match_dup 1) (const_int -1)))
15799 (clobber (match_scratch:CC 3 ""))
15800 (clobber (match_scratch:P 4 ""))]
15801 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15802 [(parallel [(set (match_dup 3)
15803 (compare:CC (plus:P (match_dup 1)
15804 (const_int -1))
15805 (const_int 0)))
15806 (set (match_dup 4)
15807 (plus:P (match_dup 1)
15808 (const_int -1)))])
15809 (set (match_dup 0)
15810 (match_dup 4))
15811 (set (pc) (if_then_else (match_dup 7)
15812 (match_dup 5)
15813 (match_dup 6)))]
15814 "
15815 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15816 operands[3], const0_rtx); }")
15817 \f
15818 (define_insn "trap"
15819 [(trap_if (const_int 1) (const_int 0))]
15820 ""
15821 "{t 31,0,0|trap}"
15822 [(set_attr "type" "trap")])
15823
15824 (define_expand "ctrap<mode>4"
15825 [(trap_if (match_operator 0 "ordered_comparison_operator"
15826 [(match_operand:GPR 1 "register_operand")
15827 (match_operand:GPR 2 "reg_or_short_operand")])
15828 (match_operand 3 "zero_constant" ""))]
15829 ""
15830 "")
15831
15832 (define_insn ""
15833 [(trap_if (match_operator 0 "ordered_comparison_operator"
15834 [(match_operand:GPR 1 "register_operand" "r")
15835 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15836 (const_int 0))]
15837 ""
15838 "{t|t<wd>}%V0%I2 %1,%2"
15839 [(set_attr "type" "trap")])
15840 \f
15841 ;; Insns related to generating the function prologue and epilogue.
15842
15843 (define_expand "prologue"
15844 [(use (const_int 0))]
15845 "TARGET_SCHED_PROLOG"
15846 "
15847 {
15848 rs6000_emit_prologue ();
15849 DONE;
15850 }")
15851
15852 (define_insn "*movesi_from_cr_one"
15853 [(match_parallel 0 "mfcr_operation"
15854 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15855 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15856 (match_operand 3 "immediate_operand" "n")]
15857 UNSPEC_MOVESI_FROM_CR))])]
15858 "TARGET_MFCRF"
15859 "*
15860 {
15861 int mask = 0;
15862 int i;
15863 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15864 {
15865 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15866 operands[4] = GEN_INT (mask);
15867 output_asm_insn (\"mfcr %1,%4\", operands);
15868 }
15869 return \"\";
15870 }"
15871 [(set_attr "type" "mfcrf")])
15872
15873 (define_insn "movesi_from_cr"
15874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15875 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15876 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15877 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15878 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15879 UNSPEC_MOVESI_FROM_CR))]
15880 ""
15881 "mfcr %0"
15882 [(set_attr "type" "mfcr")])
15883
15884 (define_insn "*stmw"
15885 [(match_parallel 0 "stmw_operation"
15886 [(set (match_operand:SI 1 "memory_operand" "=m")
15887 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15888 "TARGET_MULTIPLE"
15889 "{stm|stmw} %2,%1"
15890 [(set_attr "type" "store_ux")])
15891
15892 (define_insn "*save_gpregs_<mode>"
15893 [(match_parallel 0 "any_parallel_operand"
15894 [(clobber (reg:P 65))
15895 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15896 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15897 (set (match_operand:P 3 "memory_operand" "=m")
15898 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15899 ""
15900 "bl %1"
15901 [(set_attr "type" "branch")
15902 (set_attr "length" "4")])
15903
15904 (define_insn "*save_fpregs_<mode>"
15905 [(match_parallel 0 "any_parallel_operand"
15906 [(clobber (reg:P 65))
15907 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15908 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15909 (set (match_operand:DF 3 "memory_operand" "=m")
15910 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15911 ""
15912 "bl %1"
15913 [(set_attr "type" "branch")
15914 (set_attr "length" "4")])
15915
15916 ; These are to explain that changes to the stack pointer should
15917 ; not be moved over stores to stack memory.
15918 (define_insn "stack_tie"
15919 [(set (match_operand:BLK 0 "memory_operand" "+m")
15920 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15921 ""
15922 ""
15923 [(set_attr "length" "0")])
15924
15925 ; Like stack_tie, but depend on both fp and sp based memory.
15926 (define_insn "frame_tie"
15927 [(set (match_operand:BLK 0 "memory_operand" "+m")
15928 (unspec:BLK [(match_dup 0)
15929 (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15930 ""
15931 ""
15932 [(set_attr "length" "0")])
15933
15934
15935 (define_expand "epilogue"
15936 [(use (const_int 0))]
15937 "TARGET_SCHED_PROLOG"
15938 "
15939 {
15940 rs6000_emit_epilogue (FALSE);
15941 DONE;
15942 }")
15943
15944 ; On some processors, doing the mtcrf one CC register at a time is
15945 ; faster (like on the 604e). On others, doing them all at once is
15946 ; faster; for instance, on the 601 and 750.
15947
15948 (define_expand "movsi_to_cr_one"
15949 [(set (match_operand:CC 0 "cc_reg_operand" "")
15950 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15951 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15952 ""
15953 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15954
15955 (define_insn "*movsi_to_cr"
15956 [(match_parallel 0 "mtcrf_operation"
15957 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15958 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15959 (match_operand 3 "immediate_operand" "n")]
15960 UNSPEC_MOVESI_TO_CR))])]
15961 ""
15962 "*
15963 {
15964 int mask = 0;
15965 int i;
15966 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15967 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15968 operands[4] = GEN_INT (mask);
15969 return \"mtcrf %4,%2\";
15970 }"
15971 [(set_attr "type" "mtcr")])
15972
15973 (define_insn "*mtcrfsi"
15974 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15975 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15976 (match_operand 2 "immediate_operand" "n")]
15977 UNSPEC_MOVESI_TO_CR))]
15978 "GET_CODE (operands[0]) == REG
15979 && CR_REGNO_P (REGNO (operands[0]))
15980 && GET_CODE (operands[2]) == CONST_INT
15981 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15982 "mtcrf %R0,%1"
15983 [(set_attr "type" "mtcr")])
15984
15985 ; The load-multiple instructions have similar properties.
15986 ; Note that "load_multiple" is a name known to the machine-independent
15987 ; code that actually corresponds to the PowerPC load-string.
15988
15989 (define_insn "*lmw"
15990 [(match_parallel 0 "lmw_operation"
15991 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15992 (match_operand:SI 2 "memory_operand" "m"))])]
15993 "TARGET_MULTIPLE"
15994 "{lm|lmw} %1,%2"
15995 [(set_attr "type" "load_ux")
15996 (set_attr "cell_micro" "always")])
15997
15998 (define_insn "*return_internal_<mode>"
15999 [(return)
16000 (use (match_operand:P 0 "register_operand" "lc"))]
16001 ""
16002 "b%T0"
16003 [(set_attr "type" "jmpreg")])
16004
16005 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
16006 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
16007
16008 (define_insn "*restore_gpregs_<mode>"
16009 [(match_parallel 0 "any_parallel_operand"
16010 [(clobber (match_operand:P 1 "register_operand" "=l"))
16011 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16012 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16013 (set (match_operand:P 4 "gpc_reg_operand" "=r")
16014 (match_operand:P 5 "memory_operand" "m"))])]
16015 ""
16016 "bl %2"
16017 [(set_attr "type" "branch")
16018 (set_attr "length" "4")])
16019
16020 (define_insn "*return_and_restore_gpregs_<mode>"
16021 [(match_parallel 0 "any_parallel_operand"
16022 [(return)
16023 (clobber (match_operand:P 1 "register_operand" "=l"))
16024 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16025 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16026 (set (match_operand:P 4 "gpc_reg_operand" "=r")
16027 (match_operand:P 5 "memory_operand" "m"))])]
16028 ""
16029 "b %2"
16030 [(set_attr "type" "branch")
16031 (set_attr "length" "4")])
16032
16033 (define_insn "*return_and_restore_fpregs_<mode>"
16034 [(match_parallel 0 "any_parallel_operand"
16035 [(return)
16036 (clobber (match_operand:P 1 "register_operand" "=l"))
16037 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16038 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16039 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
16040 (match_operand:DF 5 "memory_operand" "m"))])]
16041 ""
16042 "b %2"
16043 [(set_attr "type" "branch")
16044 (set_attr "length" "4")])
16045
16046 (define_insn "*return_and_restore_fpregs_aix_<mode>"
16047 [(match_parallel 0 "any_parallel_operand"
16048 [(return)
16049 (use (match_operand:P 1 "register_operand" "l"))
16050 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16051 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16052 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
16053 (match_operand:DF 5 "memory_operand" "m"))])]
16054 ""
16055 "b %2"
16056 [(set_attr "type" "branch")
16057 (set_attr "length" "4")])
16058
16059 ; This is used in compiling the unwind routines.
16060 (define_expand "eh_return"
16061 [(use (match_operand 0 "general_operand" ""))]
16062 ""
16063 "
16064 {
16065 if (TARGET_32BIT)
16066 emit_insn (gen_eh_set_lr_si (operands[0]));
16067 else
16068 emit_insn (gen_eh_set_lr_di (operands[0]));
16069 DONE;
16070 }")
16071
16072 ; We can't expand this before we know where the link register is stored.
16073 (define_insn "eh_set_lr_<mode>"
16074 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
16075 UNSPECV_EH_RR)
16076 (clobber (match_scratch:P 1 "=&b"))]
16077 ""
16078 "#")
16079
16080 (define_split
16081 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
16082 (clobber (match_scratch 1 ""))]
16083 "reload_completed"
16084 [(const_int 0)]
16085 "
16086 {
16087 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
16088 DONE;
16089 }")
16090
16091 (define_insn "prefetch"
16092 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
16093 (match_operand:SI 1 "const_int_operand" "n")
16094 (match_operand:SI 2 "const_int_operand" "n"))]
16095 "TARGET_POWERPC"
16096 "*
16097 {
16098 if (GET_CODE (operands[0]) == REG)
16099 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
16100 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
16101 }"
16102 [(set_attr "type" "load")])
16103 \f
16104 (define_insn "bpermd_<mode>"
16105 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
16106 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
16107 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
16108 "TARGET_POPCNTD"
16109 "bpermd %0,%1,%2"
16110 [(set_attr "type" "integer")])
16111
16112 \f
16113 ;; Builtin fma support. Handle
16114 ;; Note that the conditions for expansion are in the FMA_F iterator.
16115
16116 (define_expand "fma<mode>4"
16117 [(set (match_operand:FMA_F 0 "register_operand" "")
16118 (fma:FMA_F
16119 (match_operand:FMA_F 1 "register_operand" "")
16120 (match_operand:FMA_F 2 "register_operand" "")
16121 (match_operand:FMA_F 3 "register_operand" "")))]
16122 ""
16123 "")
16124
16125 ; Altivec only has fma and nfms.
16126 (define_expand "fms<mode>4"
16127 [(set (match_operand:FMA_F 0 "register_operand" "")
16128 (fma:FMA_F
16129 (match_operand:FMA_F 1 "register_operand" "")
16130 (match_operand:FMA_F 2 "register_operand" "")
16131 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
16132 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16133 "")
16134
16135 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
16136 (define_expand "fnma<mode>4"
16137 [(set (match_operand:FMA_F 0 "register_operand" "")
16138 (neg:FMA_F
16139 (fma:FMA_F
16140 (match_operand:FMA_F 1 "register_operand" "")
16141 (match_operand:FMA_F 2 "register_operand" "")
16142 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16143 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
16144 "")
16145
16146 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
16147 (define_expand "fnms<mode>4"
16148 [(set (match_operand:FMA_F 0 "register_operand" "")
16149 (neg:FMA_F
16150 (fma:FMA_F
16151 (match_operand:FMA_F 1 "register_operand" "")
16152 (match_operand:FMA_F 2 "register_operand" "")
16153 (match_operand:FMA_F 3 "register_operand" ""))))]
16154 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16155 "")
16156
16157 ; Not an official optab name, but used from builtins.
16158 (define_expand "nfma<mode>4"
16159 [(set (match_operand:FMA_F 0 "register_operand" "")
16160 (neg:FMA_F
16161 (fma:FMA_F
16162 (match_operand:FMA_F 1 "register_operand" "")
16163 (match_operand:FMA_F 2 "register_operand" "")
16164 (match_operand:FMA_F 3 "register_operand" ""))))]
16165 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16166 "")
16167
16168 ; Not an official optab name, but used from builtins.
16169 (define_expand "nfms<mode>4"
16170 [(set (match_operand:FMA_F 0 "register_operand" "")
16171 (neg:FMA_F
16172 (fma:FMA_F
16173 (match_operand:FMA_F 1 "register_operand" "")
16174 (match_operand:FMA_F 2 "register_operand" "")
16175 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16176 ""
16177 "")
16178
16179 \f
16180
16181 (include "sync.md")
16182 (include "vector.md")
16183 (include "vsx.md")
16184 (include "altivec.md")
16185 (include "spe.md")
16186 (include "dfp.md")
16187 (include "paired.md")