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[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2012 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 ;; This file is part of GCC.
6
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22
23 ;;
24 ;; REGNOS
25 ;;
26
27 (define_constants
28 [(STACK_POINTER_REGNUM 1)
29 (TOC_REGNUM 2)
30 (STATIC_CHAIN_REGNUM 11)
31 (HARD_FRAME_POINTER_REGNUM 31)
32 (LR_REGNO 65)
33 (CTR_REGNO 66)
34 (ARG_POINTER_REGNUM 67)
35 (CR0_REGNO 68)
36 (CR1_REGNO 69)
37 (CR2_REGNO 70)
38 (CR3_REGNO 71)
39 (CR4_REGNO 72)
40 (CR5_REGNO 73)
41 (CR6_REGNO 74)
42 (CR7_REGNO 75)
43 (MAX_CR_REGNO 75)
44 (CA_REGNO 76)
45 (FIRST_ALTIVEC_REGNO 77)
46 (LAST_ALTIVEC_REGNO 108)
47 (VRSAVE_REGNO 109)
48 (VSCR_REGNO 110)
49 (SPE_ACC_REGNO 111)
50 (SPEFSCR_REGNO 112)
51 (FRAME_POINTER_REGNUM 113)
52
53 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
54 (TOC_SAVE_OFFSET_32BIT 20)
55 (TOC_SAVE_OFFSET_64BIT 40)
56
57 ; Function TOC offset in the AIX function descriptor.
58 (AIX_FUNC_DESC_TOC_32BIT 4)
59 (AIX_FUNC_DESC_TOC_64BIT 8)
60
61 ; Static chain offset in the AIX function descriptor.
62 (AIX_FUNC_DESC_SC_32BIT 8)
63 (AIX_FUNC_DESC_SC_64BIT 16)
64 ])
65
66 ;;
67 ;; UNSPEC usage
68 ;;
69
70 (define_c_enum "unspec"
71 [UNSPEC_FRSP ; frsp for POWER machines
72 UNSPEC_PROBE_STACK ; probe stack memory reference
73 UNSPEC_TOCPTR ; address of a word pointing to the TOC
74 UNSPEC_TOC ; address of the TOC (more-or-less)
75 UNSPEC_MOVSI_GOT
76 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
77 UNSPEC_FCTIWZ
78 UNSPEC_FRIM
79 UNSPEC_FRIN
80 UNSPEC_FRIP
81 UNSPEC_FRIZ
82 UNSPEC_LD_MPIC ; load_macho_picbase
83 UNSPEC_MPIC_CORRECT ; macho_correct_pic
84 UNSPEC_TLSGD
85 UNSPEC_TLSLD
86 UNSPEC_MOVESI_FROM_CR
87 UNSPEC_MOVESI_TO_CR
88 UNSPEC_TLSDTPREL
89 UNSPEC_TLSDTPRELHA
90 UNSPEC_TLSDTPRELLO
91 UNSPEC_TLSGOTDTPREL
92 UNSPEC_TLSTPREL
93 UNSPEC_TLSTPRELHA
94 UNSPEC_TLSTPRELLO
95 UNSPEC_TLSGOTTPREL
96 UNSPEC_TLSTLS
97 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
98 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
99 UNSPEC_STFIWX
100 UNSPEC_POPCNTB
101 UNSPEC_FRES
102 UNSPEC_SP_SET
103 UNSPEC_SP_TEST
104 UNSPEC_SYNC
105 UNSPEC_LWSYNC
106 UNSPEC_SYNC_OP
107 UNSPEC_ATOMIC
108 UNSPEC_CMPXCHG
109 UNSPEC_XCHG
110 UNSPEC_AND
111 UNSPEC_DLMZB
112 UNSPEC_DLMZB_CR
113 UNSPEC_DLMZB_STRLEN
114 UNSPEC_RSQRT
115 UNSPEC_TOCREL
116 UNSPEC_MACHOPIC_OFFSET
117 UNSPEC_BPERM
118 UNSPEC_COPYSIGN
119 UNSPEC_PARITY
120 UNSPEC_FCTIW
121 UNSPEC_FCTID
122 UNSPEC_LFIWAX
123 UNSPEC_LFIWZX
124 UNSPEC_FCTIWUZ
125 UNSPEC_GRP_END_NOP
126 ])
127
128 ;;
129 ;; UNSPEC_VOLATILE usage
130 ;;
131
132 (define_c_enum "unspecv"
133 [UNSPECV_BLOCK
134 UNSPECV_LL ; load-locked
135 UNSPECV_SC ; store-conditional
136 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
137 UNSPECV_EH_RR ; eh_reg_restore
138 UNSPECV_ISYNC ; isync instruction
139 UNSPECV_MFTB ; move from time base
140 ])
141
142 \f
143 ;; Define an insn type attribute. This is used in function unit delay
144 ;; computations.
145 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
146 (const_string "integer"))
147
148 ;; Define floating point instruction sub-types for use with Xfpu.md
149 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
150
151 ;; Length (in bytes).
152 ; '(pc)' in the following doesn't include the instruction itself; it is
153 ; calculated as if the instruction had zero size.
154 (define_attr "length" ""
155 (if_then_else (eq_attr "type" "branch")
156 (if_then_else (and (ge (minus (match_dup 0) (pc))
157 (const_int -32768))
158 (lt (minus (match_dup 0) (pc))
159 (const_int 32764)))
160 (const_int 4)
161 (const_int 8))
162 (const_int 4)))
163
164 ;; Processor type -- this attribute must exactly match the processor_type
165 ;; enumeration in rs6000.h.
166
167 (define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
168 (const (symbol_ref "rs6000_cpu_attr")))
169
170
171 ;; If this instruction is microcoded on the CELL processor
172 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
173 (define_attr "cell_micro" "not,conditional,always"
174 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
175 (const_string "always")
176 (const_string "not")))
177
178 (automata_option "ndfa")
179
180 (include "rs64.md")
181 (include "mpc.md")
182 (include "40x.md")
183 (include "440.md")
184 (include "476.md")
185 (include "601.md")
186 (include "603.md")
187 (include "6xx.md")
188 (include "7xx.md")
189 (include "7450.md")
190 (include "8540.md")
191 (include "e300c2c3.md")
192 (include "e500mc.md")
193 (include "e500mc64.md")
194 (include "e5500.md")
195 (include "e6500.md")
196 (include "power4.md")
197 (include "power5.md")
198 (include "power6.md")
199 (include "power7.md")
200 (include "cell.md")
201 (include "xfpu.md")
202 (include "a2.md")
203 (include "titan.md")
204
205 (include "predicates.md")
206 (include "constraints.md")
207
208 (include "darwin.md")
209
210 \f
211 ;; Mode iterators
212
213 ; This mode iterator allows :GPR to be used to indicate the allowable size
214 ; of whole values in GPRs.
215 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
216
217 ; Any supported integer mode.
218 (define_mode_iterator INT [QI HI SI DI TI])
219
220 ; Any supported integer mode that fits in one register.
221 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
222
223 ; extend modes for DImode
224 (define_mode_iterator QHSI [QI HI SI])
225
226 ; SImode or DImode, even if DImode doesn't fit in GPRs.
227 (define_mode_iterator SDI [SI DI])
228
229 ; The size of a pointer. Also, the size of the value that a record-condition
230 ; (one with a '.') will compare; and the size used for arithmetic carries.
231 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
232
233 ; Any hardware-supported floating-point mode
234 (define_mode_iterator FP [
235 (SF "TARGET_HARD_FLOAT
236 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
237 (DF "TARGET_HARD_FLOAT
238 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
239 (TF "!TARGET_IEEEQUAD
240 && TARGET_HARD_FLOAT
241 && (TARGET_FPRS || TARGET_E500_DOUBLE)
242 && TARGET_LONG_DOUBLE_128")
243 (DD "TARGET_DFP")
244 (TD "TARGET_DFP")])
245
246 ; Any fma capable floating-point mode.
247 (define_mode_iterator FMA_F [
248 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
249 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
250 || VECTOR_UNIT_VSX_P (DFmode)")
251 (V2SF "TARGET_PAIRED_FLOAT")
252 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
253 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
254 ])
255
256 ; These modes do not fit in integer registers in 32-bit mode.
257 ; but on e500v2, the gpr are 64 bit registers
258 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
259
260 ; Iterator for reciprocal estimate instructions
261 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
262
263 ; Iterator for just SF/DF
264 (define_mode_iterator SFDF [SF DF])
265
266 ; Conditional returns.
267 (define_code_iterator any_return [return simple_return])
268 (define_code_attr return_pred [(return "direct_return ()")
269 (simple_return "1")])
270 (define_code_attr return_str [(return "") (simple_return "simple_")])
271
272 ; Various instructions that come in SI and DI forms.
273 ; A generic w/d attribute, for things like cmpw/cmpd.
274 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
275
276 ; DImode bits
277 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
278
279 ;; ISEL/ISEL64 target selection
280 (define_mode_attr sel [(SI "") (DI "64")])
281
282 ;; Suffix for reload patterns
283 (define_mode_attr ptrsize [(SI "32bit")
284 (DI "64bit")])
285
286 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
287 (DI "TARGET_64BIT")])
288
289 (define_mode_attr mptrsize [(SI "si")
290 (DI "di")])
291
292 (define_mode_attr ptrload [(SI "lwz")
293 (DI "ld")])
294
295 (define_mode_attr rreg [(SF "f")
296 (DF "ws")
297 (V4SF "wf")
298 (V2DF "wd")])
299
300 (define_mode_attr rreg2 [(SF "f")
301 (DF "d")])
302
303 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
304 (DF "TARGET_FCFID")])
305
306 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
307 (DF "TARGET_E500_DOUBLE")])
308
309 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
310 (DF "TARGET_DOUBLE_FLOAT")])
311 \f
312 ;; Start with fixed-point load and store insns. Here we put only the more
313 ;; complex forms. Basic data transfer is done later.
314
315 (define_expand "zero_extend<mode>di2"
316 [(set (match_operand:DI 0 "gpc_reg_operand" "")
317 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
318 "TARGET_POWERPC64"
319 "")
320
321 (define_insn "*zero_extend<mode>di2_internal1"
322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
323 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
324 "TARGET_POWERPC64"
325 "@
326 l<wd>z%U1%X1 %0,%1
327 rldicl %0,%1,0,<dbits>"
328 [(set_attr "type" "load,*")])
329
330 (define_insn "*zero_extend<mode>di2_internal2"
331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
332 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
333 (const_int 0)))
334 (clobber (match_scratch:DI 2 "=r,r"))]
335 "TARGET_64BIT"
336 "@
337 rldicl. %2,%1,0,<dbits>
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
341
342 (define_split
343 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
344 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (clobber (match_scratch:DI 2 ""))]
347 "TARGET_POWERPC64 && reload_completed"
348 [(set (match_dup 2)
349 (zero_extend:DI (match_dup 1)))
350 (set (match_dup 0)
351 (compare:CC (match_dup 2)
352 (const_int 0)))]
353 "")
354
355 (define_insn "*zero_extend<mode>di2_internal3"
356 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
358 (const_int 0)))
359 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
360 (zero_extend:DI (match_dup 1)))]
361 "TARGET_64BIT"
362 "@
363 rldicl. %0,%1,0,<dbits>
364 #"
365 [(set_attr "type" "compare")
366 (set_attr "length" "4,8")])
367
368 (define_split
369 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
370 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
371 (const_int 0)))
372 (set (match_operand:DI 0 "gpc_reg_operand" "")
373 (zero_extend:DI (match_dup 1)))]
374 "TARGET_POWERPC64 && reload_completed"
375 [(set (match_dup 0)
376 (zero_extend:DI (match_dup 1)))
377 (set (match_dup 2)
378 (compare:CC (match_dup 0)
379 (const_int 0)))]
380 "")
381
382 (define_insn "extendqidi2"
383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
384 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
385 "TARGET_POWERPC64"
386 "extsb %0,%1"
387 [(set_attr "type" "exts")])
388
389 (define_insn ""
390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (clobber (match_scratch:DI 2 "=r,r"))]
394 "TARGET_64BIT"
395 "@
396 extsb. %2,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
400
401 (define_split
402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (clobber (match_scratch:DI 2 ""))]
406 "TARGET_POWERPC64 && reload_completed"
407 [(set (match_dup 2)
408 (sign_extend:DI (match_dup 1)))
409 (set (match_dup 0)
410 (compare:CC (match_dup 2)
411 (const_int 0)))]
412 "")
413
414 (define_insn ""
415 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
416 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
417 (const_int 0)))
418 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
419 (sign_extend:DI (match_dup 1)))]
420 "TARGET_64BIT"
421 "@
422 extsb. %0,%1
423 #"
424 [(set_attr "type" "compare")
425 (set_attr "length" "4,8")])
426
427 (define_split
428 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
429 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_POWERPC64 && reload_completed"
434 [(set (match_dup 0)
435 (sign_extend:DI (match_dup 1)))
436 (set (match_dup 2)
437 (compare:CC (match_dup 0)
438 (const_int 0)))]
439 "")
440
441 (define_expand "extendhidi2"
442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
443 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
444 "TARGET_POWERPC64"
445 "")
446
447 (define_insn ""
448 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
449 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
450 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
451 "@
452 lha%U1%X1 %0,%1
453 extsh %0,%1"
454 [(set_attr "type" "load_ext,exts")])
455
456 (define_insn ""
457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
458 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
459 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
460 "extsh %0,%1"
461 [(set_attr "type" "exts")])
462
463 (define_insn ""
464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
465 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (clobber (match_scratch:DI 2 "=r,r"))]
468 "TARGET_64BIT"
469 "@
470 extsh. %2,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
474
475 (define_split
476 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (clobber (match_scratch:DI 2 ""))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 2)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 0)
484 (compare:CC (match_dup 2)
485 (const_int 0)))]
486 "")
487
488 (define_insn ""
489 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
490 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
491 (const_int 0)))
492 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_64BIT"
495 "@
496 extsh. %0,%1
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
500
501 (define_split
502 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
503 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (set (match_operand:DI 0 "gpc_reg_operand" "")
506 (sign_extend:DI (match_dup 1)))]
507 "TARGET_POWERPC64 && reload_completed"
508 [(set (match_dup 0)
509 (sign_extend:DI (match_dup 1)))
510 (set (match_dup 2)
511 (compare:CC (match_dup 0)
512 (const_int 0)))]
513 "")
514
515 (define_expand "extendsidi2"
516 [(set (match_operand:DI 0 "gpc_reg_operand" "")
517 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
518 "TARGET_POWERPC64"
519 "")
520
521 (define_insn ""
522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
523 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
524 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
525 "@
526 lwa%U1%X1 %0,%1
527 extsw %0,%1"
528 [(set_attr "type" "load_ext,exts")])
529
530 (define_insn ""
531 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
532 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
533 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
534 "extsw %0,%1"
535 [(set_attr "type" "exts")])
536
537 (define_insn ""
538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
540 (const_int 0)))
541 (clobber (match_scratch:DI 2 "=r,r"))]
542 "TARGET_64BIT"
543 "@
544 extsw. %2,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
548
549 (define_split
550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (clobber (match_scratch:DI 2 ""))]
554 "TARGET_POWERPC64 && reload_completed"
555 [(set (match_dup 2)
556 (sign_extend:DI (match_dup 1)))
557 (set (match_dup 0)
558 (compare:CC (match_dup 2)
559 (const_int 0)))]
560 "")
561
562 (define_insn ""
563 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
567 (sign_extend:DI (match_dup 1)))]
568 "TARGET_64BIT"
569 "@
570 extsw. %0,%1
571 #"
572 [(set_attr "type" "compare")
573 (set_attr "length" "4,8")])
574
575 (define_split
576 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
577 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
578 (const_int 0)))
579 (set (match_operand:DI 0 "gpc_reg_operand" "")
580 (sign_extend:DI (match_dup 1)))]
581 "TARGET_POWERPC64 && reload_completed"
582 [(set (match_dup 0)
583 (sign_extend:DI (match_dup 1)))
584 (set (match_dup 2)
585 (compare:CC (match_dup 0)
586 (const_int 0)))]
587 "")
588
589 (define_expand "zero_extendqisi2"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "")
591 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
592 ""
593 "")
594
595 (define_insn ""
596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
601 rlwinm %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
603
604 (define_insn ""
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (clobber (match_scratch:SI 2 "=r,r"))]
609 ""
610 "@
611 andi. %2,%1,0xff
612 #"
613 [(set_attr "type" "fast_compare,compare")
614 (set_attr "length" "4,8")])
615
616 (define_split
617 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
618 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:SI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:SI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
628
629 (define_insn ""
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:SI (match_dup 1)))]
635 ""
636 "@
637 andi. %0,%1,0xff
638 #"
639 [(set_attr "type" "fast_compare,compare")
640 (set_attr "length" "4,8")])
641
642 (define_split
643 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
644 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:SI 0 "gpc_reg_operand" "")
647 (zero_extend:SI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:SI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
655
656 (define_insn "extendqisi2"
657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
658 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
659 ""
660 "extsb %0,%1"
661 [(set_attr "type" "exts")])
662
663 (define_insn ""
664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
665 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
666 (const_int 0)))
667 (clobber (match_scratch:SI 2 "=r,r"))]
668 ""
669 "@
670 extsb. %2,%1
671 #"
672 [(set_attr "type" "compare")
673 (set_attr "length" "4,8")])
674
675 (define_split
676 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
677 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
678 (const_int 0)))
679 (clobber (match_scratch:SI 2 ""))]
680 "reload_completed"
681 [(set (match_dup 2)
682 (sign_extend:SI (match_dup 1)))
683 (set (match_dup 0)
684 (compare:CC (match_dup 2)
685 (const_int 0)))]
686 "")
687
688 (define_insn ""
689 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
690 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
693 (sign_extend:SI (match_dup 1)))]
694 ""
695 "@
696 extsb. %0,%1
697 #"
698 [(set_attr "type" "compare")
699 (set_attr "length" "4,8")])
700
701 (define_split
702 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
703 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
704 (const_int 0)))
705 (set (match_operand:SI 0 "gpc_reg_operand" "")
706 (sign_extend:SI (match_dup 1)))]
707 "reload_completed"
708 [(set (match_dup 0)
709 (sign_extend:SI (match_dup 1)))
710 (set (match_dup 2)
711 (compare:CC (match_dup 0)
712 (const_int 0)))]
713 "")
714
715 (define_insn ""
716 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
717 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
718 ""
719 "@
720 lbz%U1%X1 %0,%1
721 rlwinm %0,%1,0,0xff"
722 [(set_attr "type" "load,*")])
723
724 (define_insn ""
725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
726 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
727 (const_int 0)))
728 (clobber (match_scratch:HI 2 "=r,r"))]
729 ""
730 "@
731 andi. %2,%1,0xff
732 #"
733 [(set_attr "type" "fast_compare,compare")
734 (set_attr "length" "4,8")])
735
736 (define_split
737 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
738 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
739 (const_int 0)))
740 (clobber (match_scratch:HI 2 ""))]
741 "reload_completed"
742 [(set (match_dup 2)
743 (zero_extend:HI (match_dup 1)))
744 (set (match_dup 0)
745 (compare:CC (match_dup 2)
746 (const_int 0)))]
747 "")
748
749 (define_insn ""
750 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
751 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
752 (const_int 0)))
753 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
754 (zero_extend:HI (match_dup 1)))]
755 ""
756 "@
757 andi. %0,%1,0xff
758 #"
759 [(set_attr "type" "fast_compare,compare")
760 (set_attr "length" "4,8")])
761
762 (define_split
763 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
764 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
765 (const_int 0)))
766 (set (match_operand:HI 0 "gpc_reg_operand" "")
767 (zero_extend:HI (match_dup 1)))]
768 "reload_completed"
769 [(set (match_dup 0)
770 (zero_extend:HI (match_dup 1)))
771 (set (match_dup 2)
772 (compare:CC (match_dup 0)
773 (const_int 0)))]
774 "")
775
776 (define_insn "extendqihi2"
777 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
778 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
779 ""
780 "extsb %0,%1"
781 [(set_attr "type" "exts")])
782
783 (define_insn ""
784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
785 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
786 (const_int 0)))
787 (clobber (match_scratch:HI 2 "=r,r"))]
788 ""
789 "@
790 extsb. %2,%1
791 #"
792 [(set_attr "type" "compare")
793 (set_attr "length" "4,8")])
794
795 (define_split
796 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
797 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
798 (const_int 0)))
799 (clobber (match_scratch:HI 2 ""))]
800 "reload_completed"
801 [(set (match_dup 2)
802 (sign_extend:HI (match_dup 1)))
803 (set (match_dup 0)
804 (compare:CC (match_dup 2)
805 (const_int 0)))]
806 "")
807
808 (define_insn ""
809 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
810 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
811 (const_int 0)))
812 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
813 (sign_extend:HI (match_dup 1)))]
814 ""
815 "@
816 extsb. %0,%1
817 #"
818 [(set_attr "type" "compare")
819 (set_attr "length" "4,8")])
820
821 (define_split
822 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
823 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
824 (const_int 0)))
825 (set (match_operand:HI 0 "gpc_reg_operand" "")
826 (sign_extend:HI (match_dup 1)))]
827 "reload_completed"
828 [(set (match_dup 0)
829 (sign_extend:HI (match_dup 1)))
830 (set (match_dup 2)
831 (compare:CC (match_dup 0)
832 (const_int 0)))]
833 "")
834
835 (define_expand "zero_extendhisi2"
836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
838 ""
839 "")
840
841 (define_insn ""
842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
844 ""
845 "@
846 lhz%U1%X1 %0,%1
847 rlwinm %0,%1,0,0xffff"
848 [(set_attr "type" "load,*")])
849
850 (define_insn ""
851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
853 (const_int 0)))
854 (clobber (match_scratch:SI 2 "=r,r"))]
855 ""
856 "@
857 andi. %2,%1,0xffff
858 #"
859 [(set_attr "type" "fast_compare,compare")
860 (set_attr "length" "4,8")])
861
862 (define_split
863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (clobber (match_scratch:SI 2 ""))]
867 "reload_completed"
868 [(set (match_dup 2)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 0)
871 (compare:CC (match_dup 2)
872 (const_int 0)))]
873 "")
874
875 (define_insn ""
876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
878 (const_int 0)))
879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
880 (zero_extend:SI (match_dup 1)))]
881 ""
882 "@
883 andi. %0,%1,0xffff
884 #"
885 [(set_attr "type" "fast_compare,compare")
886 (set_attr "length" "4,8")])
887
888 (define_split
889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
894 "reload_completed"
895 [(set (match_dup 0)
896 (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 "")
901
902 (define_expand "extendhisi2"
903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
905 ""
906 "")
907
908 (define_insn ""
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
911 "rs6000_gen_cell_microcode"
912 "@
913 lha%U1%X1 %0,%1
914 extsh %0,%1"
915 [(set_attr "type" "load_ext,exts")])
916
917 (define_insn ""
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
920 "!rs6000_gen_cell_microcode"
921 "extsh %0,%1"
922 [(set_attr "type" "exts")])
923
924 (define_insn ""
925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
926 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
927 (const_int 0)))
928 (clobber (match_scratch:SI 2 "=r,r"))]
929 ""
930 "@
931 extsh. %2,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
935
936 (define_split
937 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
938 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
939 (const_int 0)))
940 (clobber (match_scratch:SI 2 ""))]
941 "reload_completed"
942 [(set (match_dup 2)
943 (sign_extend:SI (match_dup 1)))
944 (set (match_dup 0)
945 (compare:CC (match_dup 2)
946 (const_int 0)))]
947 "")
948
949 (define_insn ""
950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
954 (sign_extend:SI (match_dup 1)))]
955 ""
956 "@
957 extsh. %0,%1
958 #"
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
961
962 (define_split
963 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
965 (const_int 0)))
966 (set (match_operand:SI 0 "gpc_reg_operand" "")
967 (sign_extend:SI (match_dup 1)))]
968 "reload_completed"
969 [(set (match_dup 0)
970 (sign_extend:SI (match_dup 1)))
971 (set (match_dup 2)
972 (compare:CC (match_dup 0)
973 (const_int 0)))]
974 "")
975 \f
976 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
977
978 (define_insn "*macchwc"
979 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
980 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
981 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (const_int 16))
983 (sign_extend:SI
984 (match_operand:HI 1 "gpc_reg_operand" "r")))
985 (match_operand:SI 4 "gpc_reg_operand" "0"))
986 (const_int 0)))
987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
988 (plus:SI (mult:SI (ashiftrt:SI
989 (match_dup 2)
990 (const_int 16))
991 (sign_extend:SI
992 (match_dup 1)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "macchw. %0,%1,%2"
996 [(set_attr "type" "imul3")])
997
998 (define_insn "*macchw"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (ashiftrt:SI
1001 (match_operand:SI 2 "gpc_reg_operand" "r")
1002 (const_int 16))
1003 (sign_extend:SI
1004 (match_operand:HI 1 "gpc_reg_operand" "r")))
1005 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1006 "TARGET_MULHW"
1007 "macchw %0,%1,%2"
1008 [(set_attr "type" "imul3")])
1009
1010 (define_insn "*macchwuc"
1011 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1012 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1013 (match_operand:SI 2 "gpc_reg_operand" "r")
1014 (const_int 16))
1015 (zero_extend:SI
1016 (match_operand:HI 1 "gpc_reg_operand" "r")))
1017 (match_operand:SI 4 "gpc_reg_operand" "0"))
1018 (const_int 0)))
1019 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1020 (plus:SI (mult:SI (lshiftrt:SI
1021 (match_dup 2)
1022 (const_int 16))
1023 (zero_extend:SI
1024 (match_dup 1)))
1025 (match_dup 4)))]
1026 "TARGET_MULHW"
1027 "macchwu. %0,%1,%2"
1028 [(set_attr "type" "imul3")])
1029
1030 (define_insn "*macchwu"
1031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1032 (plus:SI (mult:SI (lshiftrt:SI
1033 (match_operand:SI 2 "gpc_reg_operand" "r")
1034 (const_int 16))
1035 (zero_extend:SI
1036 (match_operand:HI 1 "gpc_reg_operand" "r")))
1037 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1038 "TARGET_MULHW"
1039 "macchwu %0,%1,%2"
1040 [(set_attr "type" "imul3")])
1041
1042 (define_insn "*machhwc"
1043 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1044 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1045 (match_operand:SI 1 "gpc_reg_operand" "%r")
1046 (const_int 16))
1047 (ashiftrt:SI
1048 (match_operand:SI 2 "gpc_reg_operand" "r")
1049 (const_int 16)))
1050 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (const_int 0)))
1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (ashiftrt:SI
1054 (match_dup 1)
1055 (const_int 16))
1056 (ashiftrt:SI
1057 (match_dup 2)
1058 (const_int 16)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "machhw. %0,%1,%2"
1062 [(set_attr "type" "imul3")])
1063
1064 (define_insn "*machhw"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (ashiftrt:SI
1067 (match_operand:SI 1 "gpc_reg_operand" "%r")
1068 (const_int 16))
1069 (ashiftrt:SI
1070 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (const_int 16)))
1072 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1073 "TARGET_MULHW"
1074 "machhw %0,%1,%2"
1075 [(set_attr "type" "imul3")])
1076
1077 (define_insn "*machhwuc"
1078 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1079 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1080 (match_operand:SI 1 "gpc_reg_operand" "%r")
1081 (const_int 16))
1082 (lshiftrt:SI
1083 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (const_int 16)))
1085 (match_operand:SI 4 "gpc_reg_operand" "0"))
1086 (const_int 0)))
1087 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1088 (plus:SI (mult:SI (lshiftrt:SI
1089 (match_dup 1)
1090 (const_int 16))
1091 (lshiftrt:SI
1092 (match_dup 2)
1093 (const_int 16)))
1094 (match_dup 4)))]
1095 "TARGET_MULHW"
1096 "machhwu. %0,%1,%2"
1097 [(set_attr "type" "imul3")])
1098
1099 (define_insn "*machhwu"
1100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (lshiftrt:SI
1102 (match_operand:SI 1 "gpc_reg_operand" "%r")
1103 (const_int 16))
1104 (lshiftrt:SI
1105 (match_operand:SI 2 "gpc_reg_operand" "r")
1106 (const_int 16)))
1107 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1108 "TARGET_MULHW"
1109 "machhwu %0,%1,%2"
1110 [(set_attr "type" "imul3")])
1111
1112 (define_insn "*maclhwc"
1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1114 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1115 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1116 (sign_extend:SI
1117 (match_operand:HI 2 "gpc_reg_operand" "r")))
1118 (match_operand:SI 4 "gpc_reg_operand" "0"))
1119 (const_int 0)))
1120 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1121 (plus:SI (mult:SI (sign_extend:SI
1122 (match_dup 1))
1123 (sign_extend:SI
1124 (match_dup 2)))
1125 (match_dup 4)))]
1126 "TARGET_MULHW"
1127 "maclhw. %0,%1,%2"
1128 [(set_attr "type" "imul3")])
1129
1130 (define_insn "*maclhw"
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1132 (plus:SI (mult:SI (sign_extend:SI
1133 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1134 (sign_extend:SI
1135 (match_operand:HI 2 "gpc_reg_operand" "r")))
1136 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1137 "TARGET_MULHW"
1138 "maclhw %0,%1,%2"
1139 [(set_attr "type" "imul3")])
1140
1141 (define_insn "*maclhwuc"
1142 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1143 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1144 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1145 (zero_extend:SI
1146 (match_operand:HI 2 "gpc_reg_operand" "r")))
1147 (match_operand:SI 4 "gpc_reg_operand" "0"))
1148 (const_int 0)))
1149 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1150 (plus:SI (mult:SI (zero_extend:SI
1151 (match_dup 1))
1152 (zero_extend:SI
1153 (match_dup 2)))
1154 (match_dup 4)))]
1155 "TARGET_MULHW"
1156 "maclhwu. %0,%1,%2"
1157 [(set_attr "type" "imul3")])
1158
1159 (define_insn "*maclhwu"
1160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (plus:SI (mult:SI (zero_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (zero_extend:SI
1164 (match_operand:HI 2 "gpc_reg_operand" "r")))
1165 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1166 "TARGET_MULHW"
1167 "maclhwu %0,%1,%2"
1168 [(set_attr "type" "imul3")])
1169
1170 (define_insn "*nmacchwc"
1171 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1172 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1173 (mult:SI (ashiftrt:SI
1174 (match_operand:SI 2 "gpc_reg_operand" "r")
1175 (const_int 16))
1176 (sign_extend:SI
1177 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (minus:SI (match_dup 4)
1181 (mult:SI (ashiftrt:SI
1182 (match_dup 2)
1183 (const_int 16))
1184 (sign_extend:SI
1185 (match_dup 1)))))]
1186 "TARGET_MULHW"
1187 "nmacchw. %0,%1,%2"
1188 [(set_attr "type" "imul3")])
1189
1190 (define_insn "*nmacchw"
1191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1192 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1193 (mult:SI (ashiftrt:SI
1194 (match_operand:SI 2 "gpc_reg_operand" "r")
1195 (const_int 16))
1196 (sign_extend:SI
1197 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1198 "TARGET_MULHW"
1199 "nmacchw %0,%1,%2"
1200 [(set_attr "type" "imul3")])
1201
1202 (define_insn "*nmachhwc"
1203 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1204 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1205 (mult:SI (ashiftrt:SI
1206 (match_operand:SI 1 "gpc_reg_operand" "%r")
1207 (const_int 16))
1208 (ashiftrt:SI
1209 (match_operand:SI 2 "gpc_reg_operand" "r")
1210 (const_int 16))))
1211 (const_int 0)))
1212 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 (minus:SI (match_dup 4)
1214 (mult:SI (ashiftrt:SI
1215 (match_dup 1)
1216 (const_int 16))
1217 (ashiftrt:SI
1218 (match_dup 2)
1219 (const_int 16)))))]
1220 "TARGET_MULHW"
1221 "nmachhw. %0,%1,%2"
1222 [(set_attr "type" "imul3")])
1223
1224 (define_insn "*nmachhw"
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1227 (mult:SI (ashiftrt:SI
1228 (match_operand:SI 1 "gpc_reg_operand" "%r")
1229 (const_int 16))
1230 (ashiftrt:SI
1231 (match_operand:SI 2 "gpc_reg_operand" "r")
1232 (const_int 16)))))]
1233 "TARGET_MULHW"
1234 "nmachhw %0,%1,%2"
1235 [(set_attr "type" "imul3")])
1236
1237 (define_insn "*nmaclhwc"
1238 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1239 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1240 (mult:SI (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1242 (sign_extend:SI
1243 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1244 (const_int 0)))
1245 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1246 (minus:SI (match_dup 4)
1247 (mult:SI (sign_extend:SI
1248 (match_dup 1))
1249 (sign_extend:SI
1250 (match_dup 2)))))]
1251 "TARGET_MULHW"
1252 "nmaclhw. %0,%1,%2"
1253 [(set_attr "type" "imul3")])
1254
1255 (define_insn "*nmaclhw"
1256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1257 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1258 (mult:SI (sign_extend:SI
1259 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1260 (sign_extend:SI
1261 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1262 "TARGET_MULHW"
1263 "nmaclhw %0,%1,%2"
1264 [(set_attr "type" "imul3")])
1265
1266 (define_insn "*mulchwc"
1267 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1268 (compare:CC (mult:SI (ashiftrt:SI
1269 (match_operand:SI 2 "gpc_reg_operand" "r")
1270 (const_int 16))
1271 (sign_extend:SI
1272 (match_operand:HI 1 "gpc_reg_operand" "r")))
1273 (const_int 0)))
1274 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (ashiftrt:SI
1276 (match_dup 2)
1277 (const_int 16))
1278 (sign_extend:SI
1279 (match_dup 1))))]
1280 "TARGET_MULHW"
1281 "mulchw. %0,%1,%2"
1282 [(set_attr "type" "imul3")])
1283
1284 (define_insn "*mulchw"
1285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1286 (mult:SI (ashiftrt:SI
1287 (match_operand:SI 2 "gpc_reg_operand" "r")
1288 (const_int 16))
1289 (sign_extend:SI
1290 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1291 "TARGET_MULHW"
1292 "mulchw %0,%1,%2"
1293 [(set_attr "type" "imul3")])
1294
1295 (define_insn "*mulchwuc"
1296 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1297 (compare:CC (mult:SI (lshiftrt:SI
1298 (match_operand:SI 2 "gpc_reg_operand" "r")
1299 (const_int 16))
1300 (zero_extend:SI
1301 (match_operand:HI 1 "gpc_reg_operand" "r")))
1302 (const_int 0)))
1303 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1304 (mult:SI (lshiftrt:SI
1305 (match_dup 2)
1306 (const_int 16))
1307 (zero_extend:SI
1308 (match_dup 1))))]
1309 "TARGET_MULHW"
1310 "mulchwu. %0,%1,%2"
1311 [(set_attr "type" "imul3")])
1312
1313 (define_insn "*mulchwu"
1314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))
1318 (zero_extend:SI
1319 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1320 "TARGET_MULHW"
1321 "mulchwu %0,%1,%2"
1322 [(set_attr "type" "imul3")])
1323
1324 (define_insn "*mulhhwc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (ashiftrt:SI
1327 (match_operand:SI 1 "gpc_reg_operand" "%r")
1328 (const_int 16))
1329 (ashiftrt:SI
1330 (match_operand:SI 2 "gpc_reg_operand" "r")
1331 (const_int 16)))
1332 (const_int 0)))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (mult:SI (ashiftrt:SI
1335 (match_dup 1)
1336 (const_int 16))
1337 (ashiftrt:SI
1338 (match_dup 2)
1339 (const_int 16))))]
1340 "TARGET_MULHW"
1341 "mulhhw. %0,%1,%2"
1342 [(set_attr "type" "imul3")])
1343
1344 (define_insn "*mulhhw"
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (ashiftrt:SI
1347 (match_operand:SI 1 "gpc_reg_operand" "%r")
1348 (const_int 16))
1349 (ashiftrt:SI
1350 (match_operand:SI 2 "gpc_reg_operand" "r")
1351 (const_int 16))))]
1352 "TARGET_MULHW"
1353 "mulhhw %0,%1,%2"
1354 [(set_attr "type" "imul3")])
1355
1356 (define_insn "*mulhhwuc"
1357 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1358 (compare:CC (mult:SI (lshiftrt:SI
1359 (match_operand:SI 1 "gpc_reg_operand" "%r")
1360 (const_int 16))
1361 (lshiftrt:SI
1362 (match_operand:SI 2 "gpc_reg_operand" "r")
1363 (const_int 16)))
1364 (const_int 0)))
1365 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (lshiftrt:SI
1367 (match_dup 1)
1368 (const_int 16))
1369 (lshiftrt:SI
1370 (match_dup 2)
1371 (const_int 16))))]
1372 "TARGET_MULHW"
1373 "mulhhwu. %0,%1,%2"
1374 [(set_attr "type" "imul3")])
1375
1376 (define_insn "*mulhhwu"
1377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1378 (mult:SI (lshiftrt:SI
1379 (match_operand:SI 1 "gpc_reg_operand" "%r")
1380 (const_int 16))
1381 (lshiftrt:SI
1382 (match_operand:SI 2 "gpc_reg_operand" "r")
1383 (const_int 16))))]
1384 "TARGET_MULHW"
1385 "mulhhwu %0,%1,%2"
1386 [(set_attr "type" "imul3")])
1387
1388 (define_insn "*mullhwc"
1389 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1390 (compare:CC (mult:SI (sign_extend:SI
1391 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1392 (sign_extend:SI
1393 (match_operand:HI 2 "gpc_reg_operand" "r")))
1394 (const_int 0)))
1395 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (sign_extend:SI
1397 (match_dup 1))
1398 (sign_extend:SI
1399 (match_dup 2))))]
1400 "TARGET_MULHW"
1401 "mullhw. %0,%1,%2"
1402 [(set_attr "type" "imul3")])
1403
1404 (define_insn "*mullhw"
1405 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1406 (mult:SI (sign_extend:SI
1407 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1408 (sign_extend:SI
1409 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1410 "TARGET_MULHW"
1411 "mullhw %0,%1,%2"
1412 [(set_attr "type" "imul3")])
1413
1414 (define_insn "*mullhwuc"
1415 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1416 (compare:CC (mult:SI (zero_extend:SI
1417 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1418 (zero_extend:SI
1419 (match_operand:HI 2 "gpc_reg_operand" "r")))
1420 (const_int 0)))
1421 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1422 (mult:SI (zero_extend:SI
1423 (match_dup 1))
1424 (zero_extend:SI
1425 (match_dup 2))))]
1426 "TARGET_MULHW"
1427 "mullhwu. %0,%1,%2"
1428 [(set_attr "type" "imul3")])
1429
1430 (define_insn "*mullhwu"
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (mult:SI (zero_extend:SI
1433 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1434 (zero_extend:SI
1435 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1436 "TARGET_MULHW"
1437 "mullhwu %0,%1,%2"
1438 [(set_attr "type" "imul3")])
1439 \f
1440 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1441 (define_insn "dlmzb"
1442 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1443 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1444 (match_operand:SI 2 "gpc_reg_operand" "r")]
1445 UNSPEC_DLMZB_CR))
1446 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1447 (unspec:SI [(match_dup 1)
1448 (match_dup 2)]
1449 UNSPEC_DLMZB))]
1450 "TARGET_DLMZB"
1451 "dlmzb. %0,%1,%2")
1452
1453 (define_expand "strlensi"
1454 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1455 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1456 (match_operand:QI 2 "const_int_operand" "")
1457 (match_operand 3 "const_int_operand" "")]
1458 UNSPEC_DLMZB_STRLEN))
1459 (clobber (match_scratch:CC 4 "=x"))]
1460 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1461 {
1462 rtx result = operands[0];
1463 rtx src = operands[1];
1464 rtx search_char = operands[2];
1465 rtx align = operands[3];
1466 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1467 rtx loop_label, end_label, mem, cr0, cond;
1468 if (search_char != const0_rtx
1469 || GET_CODE (align) != CONST_INT
1470 || INTVAL (align) < 8)
1471 FAIL;
1472 word1 = gen_reg_rtx (SImode);
1473 word2 = gen_reg_rtx (SImode);
1474 scratch_dlmzb = gen_reg_rtx (SImode);
1475 scratch_string = gen_reg_rtx (Pmode);
1476 loop_label = gen_label_rtx ();
1477 end_label = gen_label_rtx ();
1478 addr = force_reg (Pmode, XEXP (src, 0));
1479 emit_move_insn (scratch_string, addr);
1480 emit_label (loop_label);
1481 mem = change_address (src, SImode, scratch_string);
1482 emit_move_insn (word1, mem);
1483 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1484 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1485 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1486 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1487 emit_jump_insn (gen_rtx_SET (VOIDmode,
1488 pc_rtx,
1489 gen_rtx_IF_THEN_ELSE (VOIDmode,
1490 cond,
1491 gen_rtx_LABEL_REF
1492 (VOIDmode,
1493 end_label),
1494 pc_rtx)));
1495 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1496 emit_jump_insn (gen_rtx_SET (VOIDmode,
1497 pc_rtx,
1498 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1499 emit_barrier ();
1500 emit_label (end_label);
1501 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1502 emit_insn (gen_subsi3 (result, scratch_string, addr));
1503 emit_insn (gen_subsi3 (result, result, const1_rtx));
1504 DONE;
1505 })
1506 \f
1507 ;; Fixed-point arithmetic insns.
1508
1509 (define_expand "add<mode>3"
1510 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1511 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1512 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1513 ""
1514 {
1515 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1516 {
1517 if (non_short_cint_operand (operands[2], DImode))
1518 FAIL;
1519 }
1520 else if (GET_CODE (operands[2]) == CONST_INT
1521 && ! add_operand (operands[2], <MODE>mode))
1522 {
1523 rtx tmp = ((!can_create_pseudo_p ()
1524 || rtx_equal_p (operands[0], operands[1]))
1525 ? operands[0] : gen_reg_rtx (<MODE>mode));
1526
1527 HOST_WIDE_INT val = INTVAL (operands[2]);
1528 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1529 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1530
1531 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1532 FAIL;
1533
1534 /* The ordering here is important for the prolog expander.
1535 When space is allocated from the stack, adding 'low' first may
1536 produce a temporary deallocation (which would be bad). */
1537 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1538 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1539 DONE;
1540 }
1541 })
1542
1543 ;; Discourage ai/addic because of carry but provide it in an alternative
1544 ;; allowing register zero as source.
1545 (define_insn "*add<mode>3_internal1"
1546 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1547 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1548 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1549 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1550 "@
1551 add %0,%1,%2
1552 addi %0,%1,%2
1553 addic %0,%1,%2
1554 addis %0,%1,%v2"
1555 [(set_attr "length" "4,4,4,4")])
1556
1557 (define_insn "addsi3_high"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1560 (high:SI (match_operand 2 "" ""))))]
1561 "TARGET_MACHO && !TARGET_64BIT"
1562 "addis %0,%1,ha16(%2)"
1563 [(set_attr "length" "4")])
1564
1565 (define_insn "*add<mode>3_internal2"
1566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1568 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1569 (const_int 0)))
1570 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1571 ""
1572 "@
1573 add. %3,%1,%2
1574 addic. %3,%1,%2
1575 #
1576 #"
1577 [(set_attr "type" "fast_compare,compare,compare,compare")
1578 (set_attr "length" "4,4,8,8")])
1579
1580 (define_split
1581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1582 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1583 (match_operand:GPR 2 "reg_or_short_operand" ""))
1584 (const_int 0)))
1585 (clobber (match_scratch:GPR 3 ""))]
1586 "reload_completed"
1587 [(set (match_dup 3)
1588 (plus:GPR (match_dup 1)
1589 (match_dup 2)))
1590 (set (match_dup 0)
1591 (compare:CC (match_dup 3)
1592 (const_int 0)))]
1593 "")
1594
1595 (define_insn "*add<mode>3_internal3"
1596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1599 (const_int 0)))
1600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1601 (plus:P (match_dup 1)
1602 (match_dup 2)))]
1603 ""
1604 "@
1605 add. %0,%1,%2
1606 addic. %0,%1,%2
1607 #
1608 #"
1609 [(set_attr "type" "fast_compare,compare,compare,compare")
1610 (set_attr "length" "4,4,8,8")])
1611
1612 (define_split
1613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1614 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1615 (match_operand:P 2 "reg_or_short_operand" ""))
1616 (const_int 0)))
1617 (set (match_operand:P 0 "gpc_reg_operand" "")
1618 (plus:P (match_dup 1) (match_dup 2)))]
1619 "reload_completed"
1620 [(set (match_dup 0)
1621 (plus:P (match_dup 1)
1622 (match_dup 2)))
1623 (set (match_dup 3)
1624 (compare:CC (match_dup 0)
1625 (const_int 0)))]
1626 "")
1627
1628 ;; Split an add that we can't do in one insn into two insns, each of which
1629 ;; does one 16-bit part. This is used by combine. Note that the low-order
1630 ;; add should be last in case the result gets used in an address.
1631
1632 (define_split
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1634 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1635 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1636 ""
1637 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1638 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1639 {
1640 HOST_WIDE_INT val = INTVAL (operands[2]);
1641 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1642 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1643
1644 operands[4] = GEN_INT (low);
1645 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1646 operands[3] = GEN_INT (rest);
1647 else if (can_create_pseudo_p ())
1648 {
1649 operands[3] = gen_reg_rtx (DImode);
1650 emit_move_insn (operands[3], operands[2]);
1651 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1652 DONE;
1653 }
1654 else
1655 FAIL;
1656 })
1657
1658 (define_insn "one_cmpl<mode>2"
1659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1660 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1661 ""
1662 "nor %0,%1,%1")
1663
1664 (define_insn ""
1665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1666 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1667 (const_int 0)))
1668 (clobber (match_scratch:P 2 "=r,r"))]
1669 ""
1670 "@
1671 nor. %2,%1,%1
1672 #"
1673 [(set_attr "type" "fast_compare,compare")
1674 (set_attr "length" "4,8")])
1675
1676 (define_split
1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1679 (const_int 0)))
1680 (clobber (match_scratch:P 2 ""))]
1681 "reload_completed"
1682 [(set (match_dup 2)
1683 (not:P (match_dup 1)))
1684 (set (match_dup 0)
1685 (compare:CC (match_dup 2)
1686 (const_int 0)))]
1687 "")
1688
1689 (define_insn ""
1690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1692 (const_int 0)))
1693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1694 (not:P (match_dup 1)))]
1695 ""
1696 "@
1697 nor. %0,%1,%1
1698 #"
1699 [(set_attr "type" "fast_compare,compare")
1700 (set_attr "length" "4,8")])
1701
1702 (define_split
1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1705 (const_int 0)))
1706 (set (match_operand:P 0 "gpc_reg_operand" "")
1707 (not:P (match_dup 1)))]
1708 "reload_completed"
1709 [(set (match_dup 0)
1710 (not:P (match_dup 1)))
1711 (set (match_dup 2)
1712 (compare:CC (match_dup 0)
1713 (const_int 0)))]
1714 "")
1715
1716 (define_insn ""
1717 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1718 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1719 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1720 ""
1721 "@
1722 subf %0,%2,%1
1723 subfic %0,%2,%1")
1724
1725 (define_insn ""
1726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1728 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1729 (const_int 0)))
1730 (clobber (match_scratch:P 3 "=r,r"))]
1731 ""
1732 "@
1733 subf. %3,%2,%1
1734 #"
1735 [(set_attr "type" "fast_compare")
1736 (set_attr "length" "4,8")])
1737
1738 (define_split
1739 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1740 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1741 (match_operand:P 2 "gpc_reg_operand" ""))
1742 (const_int 0)))
1743 (clobber (match_scratch:P 3 ""))]
1744 "reload_completed"
1745 [(set (match_dup 3)
1746 (minus:P (match_dup 1)
1747 (match_dup 2)))
1748 (set (match_dup 0)
1749 (compare:CC (match_dup 3)
1750 (const_int 0)))]
1751 "")
1752
1753 (define_insn ""
1754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1755 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1756 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1757 (const_int 0)))
1758 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1759 (minus:P (match_dup 1)
1760 (match_dup 2)))]
1761 ""
1762 "@
1763 subf. %0,%2,%1
1764 #"
1765 [(set_attr "type" "fast_compare")
1766 (set_attr "length" "4,8")])
1767
1768 (define_split
1769 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1770 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1771 (match_operand:P 2 "gpc_reg_operand" ""))
1772 (const_int 0)))
1773 (set (match_operand:P 0 "gpc_reg_operand" "")
1774 (minus:P (match_dup 1)
1775 (match_dup 2)))]
1776 "reload_completed"
1777 [(set (match_dup 0)
1778 (minus:P (match_dup 1)
1779 (match_dup 2)))
1780 (set (match_dup 3)
1781 (compare:CC (match_dup 0)
1782 (const_int 0)))]
1783 "")
1784
1785 (define_expand "sub<mode>3"
1786 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1787 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1788 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1789 ""
1790 "
1791 {
1792 if (GET_CODE (operands[2]) == CONST_INT)
1793 {
1794 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1795 negate_rtx (<MODE>mode, operands[2])));
1796 DONE;
1797 }
1798 }")
1799
1800 (define_expand "neg<mode>2"
1801 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1802 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1803 ""
1804 "")
1805
1806 (define_insn "*neg<mode>2_internal"
1807 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1808 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1809 ""
1810 "neg %0,%1")
1811
1812 (define_insn ""
1813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1814 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1815 (const_int 0)))
1816 (clobber (match_scratch:P 2 "=r,r"))]
1817 ""
1818 "@
1819 neg. %2,%1
1820 #"
1821 [(set_attr "type" "fast_compare")
1822 (set_attr "length" "4,8")])
1823
1824 (define_split
1825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1826 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1827 (const_int 0)))
1828 (clobber (match_scratch:P 2 ""))]
1829 "reload_completed"
1830 [(set (match_dup 2)
1831 (neg:P (match_dup 1)))
1832 (set (match_dup 0)
1833 (compare:CC (match_dup 2)
1834 (const_int 0)))]
1835 "")
1836
1837 (define_insn ""
1838 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1839 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1840 (const_int 0)))
1841 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1842 (neg:P (match_dup 1)))]
1843 ""
1844 "@
1845 neg. %0,%1
1846 #"
1847 [(set_attr "type" "fast_compare")
1848 (set_attr "length" "4,8")])
1849
1850 (define_split
1851 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1852 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1853 (const_int 0)))
1854 (set (match_operand:P 0 "gpc_reg_operand" "")
1855 (neg:P (match_dup 1)))]
1856 "reload_completed"
1857 [(set (match_dup 0)
1858 (neg:P (match_dup 1)))
1859 (set (match_dup 2)
1860 (compare:CC (match_dup 0)
1861 (const_int 0)))]
1862 "")
1863
1864 (define_insn "clz<mode>2"
1865 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1866 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1867 ""
1868 "cntlz<wd> %0,%1"
1869 [(set_attr "type" "cntlz")])
1870
1871 (define_expand "ctz<mode>2"
1872 [(set (match_dup 2)
1873 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1874 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1875 (match_dup 2)))
1876 (clobber (scratch:CC))])
1877 (set (match_dup 4) (clz:GPR (match_dup 3)))
1878 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1879 (minus:GPR (match_dup 5) (match_dup 4)))]
1880 ""
1881 {
1882 operands[2] = gen_reg_rtx (<MODE>mode);
1883 operands[3] = gen_reg_rtx (<MODE>mode);
1884 operands[4] = gen_reg_rtx (<MODE>mode);
1885 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1886 })
1887
1888 (define_expand "ffs<mode>2"
1889 [(set (match_dup 2)
1890 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1891 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1892 (match_dup 2)))
1893 (clobber (scratch:CC))])
1894 (set (match_dup 4) (clz:GPR (match_dup 3)))
1895 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1896 (minus:GPR (match_dup 5) (match_dup 4)))]
1897 ""
1898 {
1899 operands[2] = gen_reg_rtx (<MODE>mode);
1900 operands[3] = gen_reg_rtx (<MODE>mode);
1901 operands[4] = gen_reg_rtx (<MODE>mode);
1902 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1903 })
1904
1905 (define_insn "popcntb<mode>2"
1906 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1907 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1908 UNSPEC_POPCNTB))]
1909 "TARGET_POPCNTB"
1910 "popcntb %0,%1"
1911 [(set_attr "length" "4")
1912 (set_attr "type" "popcnt")])
1913
1914 (define_insn "popcntd<mode>2"
1915 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1916 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1917 "TARGET_POPCNTD"
1918 "popcnt<wd> %0,%1"
1919 [(set_attr "length" "4")
1920 (set_attr "type" "popcnt")])
1921
1922 (define_expand "popcount<mode>2"
1923 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1924 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1925 "TARGET_POPCNTB || TARGET_POPCNTD"
1926 {
1927 rs6000_emit_popcount (operands[0], operands[1]);
1928 DONE;
1929 })
1930
1931 (define_insn "parity<mode>2_cmpb"
1932 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1933 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1934 "TARGET_CMPB && TARGET_POPCNTB"
1935 "prty<wd> %0,%1")
1936
1937 (define_expand "parity<mode>2"
1938 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1939 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1940 "TARGET_POPCNTB"
1941 {
1942 rs6000_emit_parity (operands[0], operands[1]);
1943 DONE;
1944 })
1945
1946 ;; Since the hardware zeros the upper part of the register, save generating the
1947 ;; AND immediate if we are converting to unsigned
1948 (define_insn "*bswaphi2_extenddi"
1949 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1950 (zero_extend:DI
1951 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1952 "TARGET_POWERPC64"
1953 "lhbrx %0,%y1"
1954 [(set_attr "length" "4")
1955 (set_attr "type" "load")])
1956
1957 (define_insn "*bswaphi2_extendsi"
1958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1959 (zero_extend:SI
1960 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1961 ""
1962 "lhbrx %0,%y1"
1963 [(set_attr "length" "4")
1964 (set_attr "type" "load")])
1965
1966 (define_expand "bswaphi2"
1967 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1968 (bswap:HI
1969 (match_operand:HI 1 "reg_or_mem_operand" "")))
1970 (clobber (match_scratch:SI 2 ""))])]
1971 ""
1972 {
1973 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1974 operands[1] = force_reg (HImode, operands[1]);
1975 })
1976
1977 (define_insn "bswaphi2_internal"
1978 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1979 (bswap:HI
1980 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1981 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1982 ""
1983 "@
1984 lhbrx %0,%y1
1985 sthbrx %1,%y0
1986 #"
1987 [(set_attr "length" "4,4,12")
1988 (set_attr "type" "load,store,*")])
1989
1990 (define_split
1991 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1992 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1993 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1994 "reload_completed"
1995 [(set (match_dup 3)
1996 (zero_extract:SI (match_dup 4)
1997 (const_int 8)
1998 (const_int 16)))
1999 (set (match_dup 2)
2000 (and:SI (ashift:SI (match_dup 4)
2001 (const_int 8))
2002 (const_int 65280))) ;; 0xff00
2003 (set (match_dup 3)
2004 (ior:SI (match_dup 3)
2005 (match_dup 2)))]
2006 "
2007 {
2008 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2009 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2010 }")
2011
2012 (define_insn "*bswapsi2_extenddi"
2013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2014 (zero_extend:DI
2015 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2016 "TARGET_POWERPC64"
2017 "lwbrx %0,%y1"
2018 [(set_attr "length" "4")
2019 (set_attr "type" "load")])
2020
2021 (define_expand "bswapsi2"
2022 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2023 (bswap:SI
2024 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2025 ""
2026 {
2027 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2028 operands[1] = force_reg (SImode, operands[1]);
2029 })
2030
2031 (define_insn "*bswapsi2_internal"
2032 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2033 (bswap:SI
2034 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2035 ""
2036 "@
2037 lwbrx %0,%y1
2038 stwbrx %1,%y0
2039 #"
2040 [(set_attr "length" "4,4,12")
2041 (set_attr "type" "load,store,*")])
2042
2043 (define_split
2044 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2045 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2046 "reload_completed"
2047 [(set (match_dup 0)
2048 (rotate:SI (match_dup 1) (const_int 8)))
2049 (set (zero_extract:SI (match_dup 0)
2050 (const_int 8)
2051 (const_int 0))
2052 (match_dup 1))
2053 (set (zero_extract:SI (match_dup 0)
2054 (const_int 8)
2055 (const_int 16))
2056 (rotate:SI (match_dup 1)
2057 (const_int 16)))]
2058 "")
2059
2060 (define_expand "bswapdi2"
2061 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2062 (bswap:DI
2063 (match_operand:DI 1 "reg_or_mem_operand" "")))
2064 (clobber (match_scratch:DI 2 ""))
2065 (clobber (match_scratch:DI 3 ""))
2066 (clobber (match_scratch:DI 4 ""))])]
2067 ""
2068 {
2069 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2070 operands[1] = force_reg (DImode, operands[1]);
2071
2072 if (!TARGET_POWERPC64)
2073 {
2074 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2075 that uses 64-bit registers needs the same scratch registers as 64-bit
2076 mode. */
2077 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2078 DONE;
2079 }
2080 })
2081
2082 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2083 (define_insn "*bswapdi2_ldbrx"
2084 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2085 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2086 (clobber (match_scratch:DI 2 "=X,X,&r"))
2087 (clobber (match_scratch:DI 3 "=X,X,&r"))
2088 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2089 "TARGET_POWERPC64 && TARGET_LDBRX
2090 && (REG_P (operands[0]) || REG_P (operands[1]))"
2091 "@
2092 ldbrx %0,%y1
2093 stdbrx %1,%y0
2094 #"
2095 [(set_attr "length" "4,4,36")
2096 (set_attr "type" "load,store,*")])
2097
2098 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2099 (define_insn "*bswapdi2_64bit"
2100 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2101 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2102 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2103 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2104 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2105 "TARGET_POWERPC64 && !TARGET_LDBRX
2106 && (REG_P (operands[0]) || REG_P (operands[1]))"
2107 "#"
2108 [(set_attr "length" "16,12,36")])
2109
2110 (define_split
2111 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2112 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2113 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2114 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2115 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2116 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2117 [(const_int 0)]
2118 "
2119 {
2120 rtx dest = operands[0];
2121 rtx src = operands[1];
2122 rtx op2 = operands[2];
2123 rtx op3 = operands[3];
2124 rtx op4 = operands[4];
2125 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2126 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2127 rtx addr1;
2128 rtx addr2;
2129 rtx word_high;
2130 rtx word_low;
2131
2132 addr1 = XEXP (src, 0);
2133 if (GET_CODE (addr1) == PLUS)
2134 {
2135 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2136 if (TARGET_AVOID_XFORM)
2137 {
2138 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2139 addr2 = op2;
2140 }
2141 else
2142 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2143 }
2144 else if (TARGET_AVOID_XFORM)
2145 {
2146 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2147 addr2 = op2;
2148 }
2149 else
2150 {
2151 emit_move_insn (op2, GEN_INT (4));
2152 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2153 }
2154
2155 if (BYTES_BIG_ENDIAN)
2156 {
2157 word_high = change_address (src, SImode, addr1);
2158 word_low = change_address (src, SImode, addr2);
2159 }
2160 else
2161 {
2162 word_high = change_address (src, SImode, addr2);
2163 word_low = change_address (src, SImode, addr1);
2164 }
2165
2166 emit_insn (gen_bswapsi2 (op3_32, word_low));
2167 emit_insn (gen_bswapsi2 (op4_32, word_high));
2168 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2169 emit_insn (gen_iordi3 (dest, dest, op4));
2170 }")
2171
2172 (define_split
2173 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2174 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2175 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2176 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2177 (clobber (match_operand:DI 4 "" ""))]
2178 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2179 [(const_int 0)]
2180 "
2181 {
2182 rtx dest = operands[0];
2183 rtx src = operands[1];
2184 rtx op2 = operands[2];
2185 rtx op3 = operands[3];
2186 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2187 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2188 rtx addr1;
2189 rtx addr2;
2190 rtx word_high;
2191 rtx word_low;
2192
2193 addr1 = XEXP (dest, 0);
2194 if (GET_CODE (addr1) == PLUS)
2195 {
2196 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2197 if (TARGET_AVOID_XFORM)
2198 {
2199 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2200 addr2 = op2;
2201 }
2202 else
2203 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2204 }
2205 else if (TARGET_AVOID_XFORM)
2206 {
2207 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2208 addr2 = op2;
2209 }
2210 else
2211 {
2212 emit_move_insn (op2, GEN_INT (4));
2213 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2214 }
2215
2216 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2217 if (BYTES_BIG_ENDIAN)
2218 {
2219 word_high = change_address (dest, SImode, addr1);
2220 word_low = change_address (dest, SImode, addr2);
2221 emit_insn (gen_bswapsi2 (word_high, src_si));
2222 emit_insn (gen_bswapsi2 (word_low, op3_si));
2223 }
2224 else
2225 {
2226 word_high = change_address (dest, SImode, addr2);
2227 word_low = change_address (dest, SImode, addr1);
2228 emit_insn (gen_bswapsi2 (word_low, src_si));
2229 emit_insn (gen_bswapsi2 (word_high, op3_si));
2230 }
2231 }")
2232
2233 (define_split
2234 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2235 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2236 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2237 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2238 (clobber (match_operand:DI 4 "" ""))]
2239 "TARGET_POWERPC64 && reload_completed"
2240 [(const_int 0)]
2241 "
2242 {
2243 rtx dest = operands[0];
2244 rtx src = operands[1];
2245 rtx op2 = operands[2];
2246 rtx op3 = operands[3];
2247 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2248 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2249 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2250 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2251
2252 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2253 emit_insn (gen_bswapsi2 (dest_si, src_si));
2254 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2255 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2256 emit_insn (gen_iordi3 (dest, dest, op3));
2257 }")
2258
2259 (define_insn "bswapdi2_32bit"
2260 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2261 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2262 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2263 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2264 "#"
2265 [(set_attr "length" "16,12,36")])
2266
2267 (define_split
2268 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2269 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2270 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2271 "!TARGET_POWERPC64 && reload_completed"
2272 [(const_int 0)]
2273 "
2274 {
2275 rtx dest = operands[0];
2276 rtx src = operands[1];
2277 rtx op2 = operands[2];
2278 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2279 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2280 rtx addr1;
2281 rtx addr2;
2282 rtx word_high;
2283 rtx word_low;
2284
2285 addr1 = XEXP (src, 0);
2286 if (GET_CODE (addr1) == PLUS)
2287 {
2288 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2289 if (TARGET_AVOID_XFORM)
2290 {
2291 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2292 addr2 = op2;
2293 }
2294 else
2295 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2296 }
2297 else if (TARGET_AVOID_XFORM)
2298 {
2299 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2300 addr2 = op2;
2301 }
2302 else
2303 {
2304 emit_move_insn (op2, GEN_INT (4));
2305 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2306 }
2307
2308 if (BYTES_BIG_ENDIAN)
2309 {
2310 word_high = change_address (src, SImode, addr1);
2311 word_low = change_address (src, SImode, addr2);
2312 }
2313 else
2314 {
2315 word_high = change_address (src, SImode, addr2);
2316 word_low = change_address (src, SImode, addr1);
2317 }
2318
2319 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2320 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2321 }")
2322
2323 (define_split
2324 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2325 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2326 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2327 "!TARGET_POWERPC64 && reload_completed"
2328 [(const_int 0)]
2329 "
2330 {
2331 rtx dest = operands[0];
2332 rtx src = operands[1];
2333 rtx op2 = operands[2];
2334 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2335 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2336 rtx addr1;
2337 rtx addr2;
2338 rtx word_high;
2339 rtx word_low;
2340
2341 addr1 = XEXP (dest, 0);
2342 if (GET_CODE (addr1) == PLUS)
2343 {
2344 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2345 if (TARGET_AVOID_XFORM)
2346 {
2347 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2348 addr2 = op2;
2349 }
2350 else
2351 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2352 }
2353 else if (TARGET_AVOID_XFORM)
2354 {
2355 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2356 addr2 = op2;
2357 }
2358 else
2359 {
2360 emit_move_insn (op2, GEN_INT (4));
2361 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2362 }
2363
2364 if (BYTES_BIG_ENDIAN)
2365 {
2366 word_high = change_address (dest, SImode, addr1);
2367 word_low = change_address (dest, SImode, addr2);
2368 }
2369 else
2370 {
2371 word_high = change_address (dest, SImode, addr2);
2372 word_low = change_address (dest, SImode, addr1);
2373 }
2374
2375 emit_insn (gen_bswapsi2 (word_high, src_low));
2376 emit_insn (gen_bswapsi2 (word_low, src_high));
2377 }")
2378
2379 (define_split
2380 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2381 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2382 (clobber (match_operand:SI 2 "" ""))]
2383 "!TARGET_POWERPC64 && reload_completed"
2384 [(const_int 0)]
2385 "
2386 {
2387 rtx dest = operands[0];
2388 rtx src = operands[1];
2389 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2390 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2391 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2392 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2393
2394 emit_insn (gen_bswapsi2 (dest_high, src_low));
2395 emit_insn (gen_bswapsi2 (dest_low, src_high));
2396 }")
2397
2398 (define_insn "mulsi3"
2399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2400 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2401 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2402 ""
2403 "@
2404 mullw %0,%1,%2
2405 mulli %0,%1,%2"
2406 [(set (attr "type")
2407 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2408 (const_string "imul3")
2409 (match_operand:SI 2 "short_cint_operand" "")
2410 (const_string "imul2")]
2411 (const_string "imul")))])
2412
2413 (define_insn "*mulsi3_internal1"
2414 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2415 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2416 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2417 (const_int 0)))
2418 (clobber (match_scratch:SI 3 "=r,r"))]
2419 ""
2420 "@
2421 mullw. %3,%1,%2
2422 #"
2423 [(set_attr "type" "imul_compare")
2424 (set_attr "length" "4,8")])
2425
2426 (define_split
2427 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2428 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2429 (match_operand:SI 2 "gpc_reg_operand" ""))
2430 (const_int 0)))
2431 (clobber (match_scratch:SI 3 ""))]
2432 "reload_completed"
2433 [(set (match_dup 3)
2434 (mult:SI (match_dup 1) (match_dup 2)))
2435 (set (match_dup 0)
2436 (compare:CC (match_dup 3)
2437 (const_int 0)))]
2438 "")
2439
2440 (define_insn "*mulsi3_internal2"
2441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2442 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2443 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2444 (const_int 0)))
2445 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2446 (mult:SI (match_dup 1) (match_dup 2)))]
2447 ""
2448 "@
2449 mullw. %0,%1,%2
2450 #"
2451 [(set_attr "type" "imul_compare")
2452 (set_attr "length" "4,8")])
2453
2454 (define_split
2455 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2456 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2457 (match_operand:SI 2 "gpc_reg_operand" ""))
2458 (const_int 0)))
2459 (set (match_operand:SI 0 "gpc_reg_operand" "")
2460 (mult:SI (match_dup 1) (match_dup 2)))]
2461 "reload_completed"
2462 [(set (match_dup 0)
2463 (mult:SI (match_dup 1) (match_dup 2)))
2464 (set (match_dup 3)
2465 (compare:CC (match_dup 0)
2466 (const_int 0)))]
2467 "")
2468
2469
2470 (define_insn "udiv<mode>3"
2471 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2472 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2473 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2474 ""
2475 "div<wd>u %0,%1,%2"
2476 [(set (attr "type")
2477 (cond [(match_operand:SI 0 "" "")
2478 (const_string "idiv")]
2479 (const_string "ldiv")))])
2480
2481
2482 ;; For powers of two we can do srai/aze for divide and then adjust for
2483 ;; modulus. If it isn't a power of two, force operands into register and do
2484 ;; a normal divide.
2485 (define_expand "div<mode>3"
2486 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2487 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2488 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2489 ""
2490 {
2491 if (GET_CODE (operands[2]) != CONST_INT
2492 || INTVAL (operands[2]) <= 0
2493 || exact_log2 (INTVAL (operands[2])) < 0)
2494 operands[2] = force_reg (<MODE>mode, operands[2]);
2495 })
2496
2497 (define_insn "*div<mode>3"
2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2499 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2500 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2501 ""
2502 "div<wd> %0,%1,%2"
2503 [(set (attr "type")
2504 (cond [(match_operand:SI 0 "" "")
2505 (const_string "idiv")]
2506 (const_string "ldiv")))])
2507
2508 (define_expand "mod<mode>3"
2509 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2510 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2511 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2512 ""
2513 "
2514 {
2515 int i;
2516 rtx temp1;
2517 rtx temp2;
2518
2519 if (GET_CODE (operands[2]) != CONST_INT
2520 || INTVAL (operands[2]) <= 0
2521 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2522 FAIL;
2523
2524 temp1 = gen_reg_rtx (<MODE>mode);
2525 temp2 = gen_reg_rtx (<MODE>mode);
2526
2527 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2528 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2529 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2530 DONE;
2531 }")
2532
2533 (define_insn ""
2534 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2535 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2536 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2537 ""
2538 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2539 [(set_attr "type" "two")
2540 (set_attr "length" "8")])
2541
2542 (define_insn ""
2543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2544 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2545 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2546 (const_int 0)))
2547 (clobber (match_scratch:P 3 "=r,r"))]
2548 ""
2549 "@
2550 sra<wd>i %3,%1,%p2\;addze. %3,%3
2551 #"
2552 [(set_attr "type" "compare")
2553 (set_attr "length" "8,12")
2554 (set_attr "cell_micro" "not")])
2555
2556 (define_split
2557 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2558 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2559 (match_operand:GPR 2 "exact_log2_cint_operand"
2560 ""))
2561 (const_int 0)))
2562 (clobber (match_scratch:GPR 3 ""))]
2563 "reload_completed"
2564 [(set (match_dup 3)
2565 (div:<MODE> (match_dup 1) (match_dup 2)))
2566 (set (match_dup 0)
2567 (compare:CC (match_dup 3)
2568 (const_int 0)))]
2569 "")
2570
2571 (define_insn ""
2572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2573 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2574 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2575 (const_int 0)))
2576 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2577 (div:P (match_dup 1) (match_dup 2)))]
2578 ""
2579 "@
2580 sra<wd>i %0,%1,%p2\;addze. %0,%0
2581 #"
2582 [(set_attr "type" "compare")
2583 (set_attr "length" "8,12")
2584 (set_attr "cell_micro" "not")])
2585
2586 (define_split
2587 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2588 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2589 (match_operand:GPR 2 "exact_log2_cint_operand"
2590 ""))
2591 (const_int 0)))
2592 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2593 (div:GPR (match_dup 1) (match_dup 2)))]
2594 "reload_completed"
2595 [(set (match_dup 0)
2596 (div:<MODE> (match_dup 1) (match_dup 2)))
2597 (set (match_dup 3)
2598 (compare:CC (match_dup 0)
2599 (const_int 0)))]
2600 "")
2601 \f
2602 ;; Logical instructions
2603 ;; The logical instructions are mostly combined by using match_operator,
2604 ;; but the plain AND insns are somewhat different because there is no
2605 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2606 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2607
2608 (define_expand "andsi3"
2609 [(parallel
2610 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2611 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2612 (match_operand:SI 2 "and_operand" "")))
2613 (clobber (match_scratch:CC 3 ""))])]
2614 ""
2615 "")
2616
2617 (define_insn "andsi3_mc"
2618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2619 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2620 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2621 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2622 "rs6000_gen_cell_microcode"
2623 "@
2624 and %0,%1,%2
2625 rlwinm %0,%1,0,%m2,%M2
2626 andi. %0,%1,%b2
2627 andis. %0,%1,%u2"
2628 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2629
2630 (define_insn "andsi3_nomc"
2631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2632 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2633 (match_operand:SI 2 "and_operand" "?r,T")))
2634 (clobber (match_scratch:CC 3 "=X,X"))]
2635 "!rs6000_gen_cell_microcode"
2636 "@
2637 and %0,%1,%2
2638 rlwinm %0,%1,0,%m2,%M2")
2639
2640 (define_insn "andsi3_internal0_nomc"
2641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2642 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2643 (match_operand:SI 2 "and_operand" "?r,T")))]
2644 "!rs6000_gen_cell_microcode"
2645 "@
2646 and %0,%1,%2
2647 rlwinm %0,%1,0,%m2,%M2")
2648
2649
2650 ;; Note to set cr's other than cr0 we do the and immediate and then
2651 ;; the test again -- this avoids a mfcr which on the higher end
2652 ;; machines causes an execution serialization
2653
2654 (define_insn "*andsi3_internal2_mc"
2655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2656 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2657 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2658 (const_int 0)))
2659 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2660 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2661 "TARGET_32BIT && rs6000_gen_cell_microcode"
2662 "@
2663 and. %3,%1,%2
2664 andi. %3,%1,%b2
2665 andis. %3,%1,%u2
2666 rlwinm. %3,%1,0,%m2,%M2
2667 #
2668 #
2669 #
2670 #"
2671 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2672 compare,compare,compare,compare")
2673 (set_attr "length" "4,4,4,4,8,8,8,8")])
2674
2675 (define_insn "*andsi3_internal3_mc"
2676 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2677 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2678 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2679 (const_int 0)))
2680 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2681 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2682 "TARGET_64BIT && rs6000_gen_cell_microcode"
2683 "@
2684 #
2685 andi. %3,%1,%b2
2686 andis. %3,%1,%u2
2687 rlwinm. %3,%1,0,%m2,%M2
2688 #
2689 #
2690 #
2691 #"
2692 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2693 compare,compare,compare")
2694 (set_attr "length" "8,4,4,4,8,8,8,8")])
2695
2696 (define_split
2697 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2698 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2699 (match_operand:GPR 2 "and_operand" ""))
2700 (const_int 0)))
2701 (clobber (match_scratch:GPR 3 ""))
2702 (clobber (match_scratch:CC 4 ""))]
2703 "reload_completed"
2704 [(parallel [(set (match_dup 3)
2705 (and:<MODE> (match_dup 1)
2706 (match_dup 2)))
2707 (clobber (match_dup 4))])
2708 (set (match_dup 0)
2709 (compare:CC (match_dup 3)
2710 (const_int 0)))]
2711 "")
2712
2713 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2714 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2715
2716 (define_split
2717 [(set (match_operand:CC 0 "cc_reg_operand" "")
2718 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2719 (match_operand:SI 2 "gpc_reg_operand" ""))
2720 (const_int 0)))
2721 (clobber (match_scratch:SI 3 ""))
2722 (clobber (match_scratch:CC 4 ""))]
2723 "TARGET_POWERPC64 && reload_completed"
2724 [(parallel [(set (match_dup 3)
2725 (and:SI (match_dup 1)
2726 (match_dup 2)))
2727 (clobber (match_dup 4))])
2728 (set (match_dup 0)
2729 (compare:CC (match_dup 3)
2730 (const_int 0)))]
2731 "")
2732
2733 (define_insn "*andsi3_internal4"
2734 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2735 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2736 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2737 (const_int 0)))
2738 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2739 (and:SI (match_dup 1)
2740 (match_dup 2)))
2741 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2742 "TARGET_32BIT && rs6000_gen_cell_microcode"
2743 "@
2744 and. %0,%1,%2
2745 andi. %0,%1,%b2
2746 andis. %0,%1,%u2
2747 rlwinm. %0,%1,0,%m2,%M2
2748 #
2749 #
2750 #
2751 #"
2752 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2753 compare,compare,compare,compare")
2754 (set_attr "length" "4,4,4,4,8,8,8,8")])
2755
2756 (define_insn "*andsi3_internal5_mc"
2757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2758 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2759 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2760 (const_int 0)))
2761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2762 (and:SI (match_dup 1)
2763 (match_dup 2)))
2764 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2765 "TARGET_64BIT && rs6000_gen_cell_microcode"
2766 "@
2767 #
2768 andi. %0,%1,%b2
2769 andis. %0,%1,%u2
2770 rlwinm. %0,%1,0,%m2,%M2
2771 #
2772 #
2773 #
2774 #"
2775 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2776 compare,compare,compare")
2777 (set_attr "length" "8,4,4,4,8,8,8,8")])
2778
2779 (define_split
2780 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2781 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2782 (match_operand:SI 2 "and_operand" ""))
2783 (const_int 0)))
2784 (set (match_operand:SI 0 "gpc_reg_operand" "")
2785 (and:SI (match_dup 1)
2786 (match_dup 2)))
2787 (clobber (match_scratch:CC 4 ""))]
2788 "reload_completed"
2789 [(parallel [(set (match_dup 0)
2790 (and:SI (match_dup 1)
2791 (match_dup 2)))
2792 (clobber (match_dup 4))])
2793 (set (match_dup 3)
2794 (compare:CC (match_dup 0)
2795 (const_int 0)))]
2796 "")
2797
2798 (define_split
2799 [(set (match_operand:CC 3 "cc_reg_operand" "")
2800 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2801 (match_operand:SI 2 "gpc_reg_operand" ""))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "")
2804 (and:SI (match_dup 1)
2805 (match_dup 2)))
2806 (clobber (match_scratch:CC 4 ""))]
2807 "TARGET_POWERPC64 && reload_completed"
2808 [(parallel [(set (match_dup 0)
2809 (and:SI (match_dup 1)
2810 (match_dup 2)))
2811 (clobber (match_dup 4))])
2812 (set (match_dup 3)
2813 (compare:CC (match_dup 0)
2814 (const_int 0)))]
2815 "")
2816
2817 ;; Handle the PowerPC64 rlwinm corner case
2818
2819 (define_insn_and_split "*andsi3_internal6"
2820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2821 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2822 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2823 "TARGET_POWERPC64"
2824 "#"
2825 "TARGET_POWERPC64"
2826 [(set (match_dup 0)
2827 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2828 (match_dup 4)))
2829 (set (match_dup 0)
2830 (rotate:SI (match_dup 0) (match_dup 5)))]
2831 "
2832 {
2833 int mb = extract_MB (operands[2]);
2834 int me = extract_ME (operands[2]);
2835 operands[3] = GEN_INT (me + 1);
2836 operands[5] = GEN_INT (32 - (me + 1));
2837 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2838 }"
2839 [(set_attr "length" "8")])
2840
2841 (define_expand "iorsi3"
2842 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2843 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2844 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2845 ""
2846 "
2847 {
2848 if (GET_CODE (operands[2]) == CONST_INT
2849 && ! logical_operand (operands[2], SImode))
2850 {
2851 HOST_WIDE_INT value = INTVAL (operands[2]);
2852 rtx tmp = ((!can_create_pseudo_p ()
2853 || rtx_equal_p (operands[0], operands[1]))
2854 ? operands[0] : gen_reg_rtx (SImode));
2855
2856 emit_insn (gen_iorsi3 (tmp, operands[1],
2857 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2858 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2859 DONE;
2860 }
2861 }")
2862
2863 (define_expand "xorsi3"
2864 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2865 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2866 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2867 ""
2868 "
2869 {
2870 if (GET_CODE (operands[2]) == CONST_INT
2871 && ! logical_operand (operands[2], SImode))
2872 {
2873 HOST_WIDE_INT value = INTVAL (operands[2]);
2874 rtx tmp = ((!can_create_pseudo_p ()
2875 || rtx_equal_p (operands[0], operands[1]))
2876 ? operands[0] : gen_reg_rtx (SImode));
2877
2878 emit_insn (gen_xorsi3 (tmp, operands[1],
2879 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2880 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2881 DONE;
2882 }
2883 }")
2884
2885 (define_insn "*boolsi3_internal1"
2886 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2887 (match_operator:SI 3 "boolean_or_operator"
2888 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2889 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2890 ""
2891 "@
2892 %q3 %0,%1,%2
2893 %q3i %0,%1,%b2
2894 %q3is %0,%1,%u2")
2895
2896 (define_insn "*boolsi3_internal2"
2897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2898 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2899 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2900 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2901 (const_int 0)))
2902 (clobber (match_scratch:SI 3 "=r,r"))]
2903 "TARGET_32BIT"
2904 "@
2905 %q4. %3,%1,%2
2906 #"
2907 [(set_attr "type" "fast_compare,compare")
2908 (set_attr "length" "4,8")])
2909
2910 (define_split
2911 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2912 (compare:CC (match_operator:SI 4 "boolean_operator"
2913 [(match_operand:SI 1 "gpc_reg_operand" "")
2914 (match_operand:SI 2 "gpc_reg_operand" "")])
2915 (const_int 0)))
2916 (clobber (match_scratch:SI 3 ""))]
2917 "TARGET_32BIT && reload_completed"
2918 [(set (match_dup 3) (match_dup 4))
2919 (set (match_dup 0)
2920 (compare:CC (match_dup 3)
2921 (const_int 0)))]
2922 "")
2923
2924 (define_insn "*boolsi3_internal3"
2925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2926 (compare:CC (match_operator:SI 4 "boolean_operator"
2927 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2928 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2929 (const_int 0)))
2930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2931 (match_dup 4))]
2932 "TARGET_32BIT"
2933 "@
2934 %q4. %0,%1,%2
2935 #"
2936 [(set_attr "type" "fast_compare,compare")
2937 (set_attr "length" "4,8")])
2938
2939 (define_split
2940 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2941 (compare:CC (match_operator:SI 4 "boolean_operator"
2942 [(match_operand:SI 1 "gpc_reg_operand" "")
2943 (match_operand:SI 2 "gpc_reg_operand" "")])
2944 (const_int 0)))
2945 (set (match_operand:SI 0 "gpc_reg_operand" "")
2946 (match_dup 4))]
2947 "TARGET_32BIT && reload_completed"
2948 [(set (match_dup 0) (match_dup 4))
2949 (set (match_dup 3)
2950 (compare:CC (match_dup 0)
2951 (const_int 0)))]
2952 "")
2953
2954 ;; Split a logical operation that we can't do in one insn into two insns,
2955 ;; each of which does one 16-bit part. This is used by combine.
2956
2957 (define_split
2958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2959 (match_operator:SI 3 "boolean_or_operator"
2960 [(match_operand:SI 1 "gpc_reg_operand" "")
2961 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2962 ""
2963 [(set (match_dup 0) (match_dup 4))
2964 (set (match_dup 0) (match_dup 5))]
2965 "
2966 {
2967 rtx i;
2968 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2969 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2970 operands[1], i);
2971 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2972 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2973 operands[0], i);
2974 }")
2975
2976 (define_insn "*boolcsi3_internal1"
2977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2978 (match_operator:SI 3 "boolean_operator"
2979 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2980 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2981 ""
2982 "%q3 %0,%2,%1")
2983
2984 (define_insn "*boolcsi3_internal2"
2985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2986 (compare:CC (match_operator:SI 4 "boolean_operator"
2987 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2988 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2989 (const_int 0)))
2990 (clobber (match_scratch:SI 3 "=r,r"))]
2991 "TARGET_32BIT"
2992 "@
2993 %q4. %3,%2,%1
2994 #"
2995 [(set_attr "type" "compare")
2996 (set_attr "length" "4,8")])
2997
2998 (define_split
2999 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3000 (compare:CC (match_operator:SI 4 "boolean_operator"
3001 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3002 (match_operand:SI 2 "gpc_reg_operand" "")])
3003 (const_int 0)))
3004 (clobber (match_scratch:SI 3 ""))]
3005 "TARGET_32BIT && reload_completed"
3006 [(set (match_dup 3) (match_dup 4))
3007 (set (match_dup 0)
3008 (compare:CC (match_dup 3)
3009 (const_int 0)))]
3010 "")
3011
3012 (define_insn "*boolcsi3_internal3"
3013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3014 (compare:CC (match_operator:SI 4 "boolean_operator"
3015 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3016 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3017 (const_int 0)))
3018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3019 (match_dup 4))]
3020 "TARGET_32BIT"
3021 "@
3022 %q4. %0,%2,%1
3023 #"
3024 [(set_attr "type" "compare")
3025 (set_attr "length" "4,8")])
3026
3027 (define_split
3028 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3029 (compare:CC (match_operator:SI 4 "boolean_operator"
3030 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3031 (match_operand:SI 2 "gpc_reg_operand" "")])
3032 (const_int 0)))
3033 (set (match_operand:SI 0 "gpc_reg_operand" "")
3034 (match_dup 4))]
3035 "TARGET_32BIT && reload_completed"
3036 [(set (match_dup 0) (match_dup 4))
3037 (set (match_dup 3)
3038 (compare:CC (match_dup 0)
3039 (const_int 0)))]
3040 "")
3041
3042 (define_insn "*boolccsi3_internal1"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (match_operator:SI 3 "boolean_operator"
3045 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3046 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3047 ""
3048 "%q3 %0,%1,%2")
3049
3050 (define_insn "*boolccsi3_internal2"
3051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3052 (compare:CC (match_operator:SI 4 "boolean_operator"
3053 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3054 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3055 (const_int 0)))
3056 (clobber (match_scratch:SI 3 "=r,r"))]
3057 "TARGET_32BIT"
3058 "@
3059 %q4. %3,%1,%2
3060 #"
3061 [(set_attr "type" "fast_compare,compare")
3062 (set_attr "length" "4,8")])
3063
3064 (define_split
3065 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3066 (compare:CC (match_operator:SI 4 "boolean_operator"
3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3068 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3069 (const_int 0)))
3070 (clobber (match_scratch:SI 3 ""))]
3071 "TARGET_32BIT && reload_completed"
3072 [(set (match_dup 3) (match_dup 4))
3073 (set (match_dup 0)
3074 (compare:CC (match_dup 3)
3075 (const_int 0)))]
3076 "")
3077
3078 (define_insn "*boolccsi3_internal3"
3079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3082 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3083 (const_int 0)))
3084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3085 (match_dup 4))]
3086 "TARGET_32BIT"
3087 "@
3088 %q4. %0,%1,%2
3089 #"
3090 [(set_attr "type" "fast_compare,compare")
3091 (set_attr "length" "4,8")])
3092
3093 (define_split
3094 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3095 (compare:CC (match_operator:SI 4 "boolean_operator"
3096 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3097 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3098 (const_int 0)))
3099 (set (match_operand:SI 0 "gpc_reg_operand" "")
3100 (match_dup 4))]
3101 "TARGET_32BIT && reload_completed"
3102 [(set (match_dup 0) (match_dup 4))
3103 (set (match_dup 3)
3104 (compare:CC (match_dup 0)
3105 (const_int 0)))]
3106 "")
3107 \f
3108 ;; Rotate and shift insns, in all their variants. These support shifts,
3109 ;; field inserts and extracts, and various combinations thereof.
3110 (define_expand "insv"
3111 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3112 (match_operand:SI 1 "const_int_operand" "")
3113 (match_operand:SI 2 "const_int_operand" ""))
3114 (match_operand 3 "gpc_reg_operand" ""))]
3115 ""
3116 "
3117 {
3118 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3119 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3120 compiler if the address of the structure is taken later. Likewise, do
3121 not handle invalid E500 subregs. */
3122 if (GET_CODE (operands[0]) == SUBREG
3123 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3124 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3125 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3126 FAIL;
3127
3128 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3129 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3130 operands[3]));
3131 else
3132 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3133 operands[3]));
3134 DONE;
3135 }")
3136
3137 (define_insn "insvsi_internal"
3138 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3139 (match_operand:SI 1 "const_int_operand" "i")
3140 (match_operand:SI 2 "const_int_operand" "i"))
3141 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3142 ""
3143 "*
3144 {
3145 int start = INTVAL (operands[2]) & 31;
3146 int size = INTVAL (operands[1]) & 31;
3147
3148 operands[4] = GEN_INT (32 - start - size);
3149 operands[1] = GEN_INT (start + size - 1);
3150 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3151 }"
3152 [(set_attr "type" "insert_word")])
3153
3154 (define_insn "*insvsi_internal1"
3155 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3156 (match_operand:SI 1 "const_int_operand" "i")
3157 (match_operand:SI 2 "const_int_operand" "i"))
3158 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3159 (match_operand:SI 4 "const_int_operand" "i")))]
3160 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3161 "*
3162 {
3163 int shift = INTVAL (operands[4]) & 31;
3164 int start = INTVAL (operands[2]) & 31;
3165 int size = INTVAL (operands[1]) & 31;
3166
3167 operands[4] = GEN_INT (shift - start - size);
3168 operands[1] = GEN_INT (start + size - 1);
3169 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3170 }"
3171 [(set_attr "type" "insert_word")])
3172
3173 (define_insn "*insvsi_internal2"
3174 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3175 (match_operand:SI 1 "const_int_operand" "i")
3176 (match_operand:SI 2 "const_int_operand" "i"))
3177 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3178 (match_operand:SI 4 "const_int_operand" "i")))]
3179 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3180 "*
3181 {
3182 int shift = INTVAL (operands[4]) & 31;
3183 int start = INTVAL (operands[2]) & 31;
3184 int size = INTVAL (operands[1]) & 31;
3185
3186 operands[4] = GEN_INT (32 - shift - start - size);
3187 operands[1] = GEN_INT (start + size - 1);
3188 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3189 }"
3190 [(set_attr "type" "insert_word")])
3191
3192 (define_insn "*insvsi_internal3"
3193 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3194 (match_operand:SI 1 "const_int_operand" "i")
3195 (match_operand:SI 2 "const_int_operand" "i"))
3196 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3197 (match_operand:SI 4 "const_int_operand" "i")))]
3198 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3199 "*
3200 {
3201 int shift = INTVAL (operands[4]) & 31;
3202 int start = INTVAL (operands[2]) & 31;
3203 int size = INTVAL (operands[1]) & 31;
3204
3205 operands[4] = GEN_INT (32 - shift - start - size);
3206 operands[1] = GEN_INT (start + size - 1);
3207 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3208 }"
3209 [(set_attr "type" "insert_word")])
3210
3211 (define_insn "*insvsi_internal4"
3212 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3213 (match_operand:SI 1 "const_int_operand" "i")
3214 (match_operand:SI 2 "const_int_operand" "i"))
3215 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3216 (match_operand:SI 4 "const_int_operand" "i")
3217 (match_operand:SI 5 "const_int_operand" "i")))]
3218 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3219 "*
3220 {
3221 int extract_start = INTVAL (operands[5]) & 31;
3222 int extract_size = INTVAL (operands[4]) & 31;
3223 int insert_start = INTVAL (operands[2]) & 31;
3224 int insert_size = INTVAL (operands[1]) & 31;
3225
3226 /* Align extract field with insert field */
3227 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3228 operands[1] = GEN_INT (insert_start + insert_size - 1);
3229 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3230 }"
3231 [(set_attr "type" "insert_word")])
3232
3233 ;; combine patterns for rlwimi
3234 (define_insn "*insvsi_internal5"
3235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3236 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3237 (match_operand:SI 1 "mask_operand" "i"))
3238 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3239 (match_operand:SI 2 "const_int_operand" "i"))
3240 (match_operand:SI 5 "mask_operand" "i"))))]
3241 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3242 "*
3243 {
3244 int me = extract_ME(operands[5]);
3245 int mb = extract_MB(operands[5]);
3246 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3247 operands[2] = GEN_INT(mb);
3248 operands[1] = GEN_INT(me);
3249 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3250 }"
3251 [(set_attr "type" "insert_word")])
3252
3253 (define_insn "*insvsi_internal6"
3254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3255 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3256 (match_operand:SI 2 "const_int_operand" "i"))
3257 (match_operand:SI 5 "mask_operand" "i"))
3258 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3259 (match_operand:SI 1 "mask_operand" "i"))))]
3260 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3261 "*
3262 {
3263 int me = extract_ME(operands[5]);
3264 int mb = extract_MB(operands[5]);
3265 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3266 operands[2] = GEN_INT(mb);
3267 operands[1] = GEN_INT(me);
3268 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3269 }"
3270 [(set_attr "type" "insert_word")])
3271
3272 (define_insn "insvdi_internal"
3273 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3274 (match_operand:SI 1 "const_int_operand" "i")
3275 (match_operand:SI 2 "const_int_operand" "i"))
3276 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3277 "TARGET_POWERPC64"
3278 "*
3279 {
3280 int start = INTVAL (operands[2]) & 63;
3281 int size = INTVAL (operands[1]) & 63;
3282
3283 operands[1] = GEN_INT (64 - start - size);
3284 return \"rldimi %0,%3,%H1,%H2\";
3285 }"
3286 [(set_attr "type" "insert_dword")])
3287
3288 (define_insn "*insvdi_internal2"
3289 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3290 (match_operand:SI 1 "const_int_operand" "i")
3291 (match_operand:SI 2 "const_int_operand" "i"))
3292 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3293 (match_operand:SI 4 "const_int_operand" "i")))]
3294 "TARGET_POWERPC64
3295 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3296 "*
3297 {
3298 int shift = INTVAL (operands[4]) & 63;
3299 int start = (INTVAL (operands[2]) & 63) - 32;
3300 int size = INTVAL (operands[1]) & 63;
3301
3302 operands[4] = GEN_INT (64 - shift - start - size);
3303 operands[2] = GEN_INT (start);
3304 operands[1] = GEN_INT (start + size - 1);
3305 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3306 }")
3307
3308 (define_insn "*insvdi_internal3"
3309 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3310 (match_operand:SI 1 "const_int_operand" "i")
3311 (match_operand:SI 2 "const_int_operand" "i"))
3312 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3313 (match_operand:SI 4 "const_int_operand" "i")))]
3314 "TARGET_POWERPC64
3315 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3316 "*
3317 {
3318 int shift = INTVAL (operands[4]) & 63;
3319 int start = (INTVAL (operands[2]) & 63) - 32;
3320 int size = INTVAL (operands[1]) & 63;
3321
3322 operands[4] = GEN_INT (64 - shift - start - size);
3323 operands[2] = GEN_INT (start);
3324 operands[1] = GEN_INT (start + size - 1);
3325 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3326 }")
3327
3328 (define_expand "extzv"
3329 [(set (match_operand 0 "gpc_reg_operand" "")
3330 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3331 (match_operand:SI 2 "const_int_operand" "")
3332 (match_operand:SI 3 "const_int_operand" "")))]
3333 ""
3334 "
3335 {
3336 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3337 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3338 compiler if the address of the structure is taken later. */
3339 if (GET_CODE (operands[0]) == SUBREG
3340 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3341 FAIL;
3342
3343 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3344 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3345 operands[3]));
3346 else
3347 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3348 operands[3]));
3349 DONE;
3350 }")
3351
3352 (define_insn "extzvsi_internal"
3353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3354 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3355 (match_operand:SI 2 "const_int_operand" "i")
3356 (match_operand:SI 3 "const_int_operand" "i")))]
3357 ""
3358 "*
3359 {
3360 int start = INTVAL (operands[3]) & 31;
3361 int size = INTVAL (operands[2]) & 31;
3362
3363 if (start + size >= 32)
3364 operands[3] = const0_rtx;
3365 else
3366 operands[3] = GEN_INT (start + size);
3367 return \"rlwinm %0,%1,%3,%s2,31\";
3368 }")
3369
3370 (define_insn "*extzvsi_internal1"
3371 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3372 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3373 (match_operand:SI 2 "const_int_operand" "i,i")
3374 (match_operand:SI 3 "const_int_operand" "i,i"))
3375 (const_int 0)))
3376 (clobber (match_scratch:SI 4 "=r,r"))]
3377 ""
3378 "*
3379 {
3380 int start = INTVAL (operands[3]) & 31;
3381 int size = INTVAL (operands[2]) & 31;
3382
3383 /* Force split for non-cc0 compare. */
3384 if (which_alternative == 1)
3385 return \"#\";
3386
3387 /* If the bit-field being tested fits in the upper or lower half of a
3388 word, it is possible to use andiu. or andil. to test it. This is
3389 useful because the condition register set-use delay is smaller for
3390 andi[ul]. than for rlinm. This doesn't work when the starting bit
3391 position is 0 because the LT and GT bits may be set wrong. */
3392
3393 if ((start > 0 && start + size <= 16) || start >= 16)
3394 {
3395 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3396 - (1 << (16 - (start & 15) - size))));
3397 if (start < 16)
3398 return \"andis. %4,%1,%3\";
3399 else
3400 return \"andi. %4,%1,%3\";
3401 }
3402
3403 if (start + size >= 32)
3404 operands[3] = const0_rtx;
3405 else
3406 operands[3] = GEN_INT (start + size);
3407 return \"rlwinm. %4,%1,%3,%s2,31\";
3408 }"
3409 [(set_attr "type" "delayed_compare")
3410 (set_attr "length" "4,8")])
3411
3412 (define_split
3413 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3414 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3415 (match_operand:SI 2 "const_int_operand" "")
3416 (match_operand:SI 3 "const_int_operand" ""))
3417 (const_int 0)))
3418 (clobber (match_scratch:SI 4 ""))]
3419 "reload_completed"
3420 [(set (match_dup 4)
3421 (zero_extract:SI (match_dup 1) (match_dup 2)
3422 (match_dup 3)))
3423 (set (match_dup 0)
3424 (compare:CC (match_dup 4)
3425 (const_int 0)))]
3426 "")
3427
3428 (define_insn "*extzvsi_internal2"
3429 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3430 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3431 (match_operand:SI 2 "const_int_operand" "i,i")
3432 (match_operand:SI 3 "const_int_operand" "i,i"))
3433 (const_int 0)))
3434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3435 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3436 ""
3437 "*
3438 {
3439 int start = INTVAL (operands[3]) & 31;
3440 int size = INTVAL (operands[2]) & 31;
3441
3442 /* Force split for non-cc0 compare. */
3443 if (which_alternative == 1)
3444 return \"#\";
3445
3446 /* Since we are using the output value, we can't ignore any need for
3447 a shift. The bit-field must end at the LSB. */
3448 if (start >= 16 && start + size == 32)
3449 {
3450 operands[3] = GEN_INT ((1 << size) - 1);
3451 return \"andi. %0,%1,%3\";
3452 }
3453
3454 if (start + size >= 32)
3455 operands[3] = const0_rtx;
3456 else
3457 operands[3] = GEN_INT (start + size);
3458 return \"rlwinm. %0,%1,%3,%s2,31\";
3459 }"
3460 [(set_attr "type" "delayed_compare")
3461 (set_attr "length" "4,8")])
3462
3463 (define_split
3464 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3465 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3466 (match_operand:SI 2 "const_int_operand" "")
3467 (match_operand:SI 3 "const_int_operand" ""))
3468 (const_int 0)))
3469 (set (match_operand:SI 0 "gpc_reg_operand" "")
3470 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3471 "reload_completed"
3472 [(set (match_dup 0)
3473 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3474 (set (match_dup 4)
3475 (compare:CC (match_dup 0)
3476 (const_int 0)))]
3477 "")
3478
3479 (define_insn "extzvdi_internal"
3480 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3481 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3482 (match_operand:SI 2 "const_int_operand" "i")
3483 (match_operand:SI 3 "const_int_operand" "i")))]
3484 "TARGET_POWERPC64"
3485 "*
3486 {
3487 int start = INTVAL (operands[3]) & 63;
3488 int size = INTVAL (operands[2]) & 63;
3489
3490 if (start + size >= 64)
3491 operands[3] = const0_rtx;
3492 else
3493 operands[3] = GEN_INT (start + size);
3494 operands[2] = GEN_INT (64 - size);
3495 return \"rldicl %0,%1,%3,%2\";
3496 }")
3497
3498 (define_insn "*extzvdi_internal1"
3499 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3500 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3501 (match_operand:SI 2 "const_int_operand" "i")
3502 (match_operand:SI 3 "const_int_operand" "i"))
3503 (const_int 0)))
3504 (clobber (match_scratch:DI 4 "=r"))]
3505 "TARGET_64BIT && rs6000_gen_cell_microcode"
3506 "*
3507 {
3508 int start = INTVAL (operands[3]) & 63;
3509 int size = INTVAL (operands[2]) & 63;
3510
3511 if (start + size >= 64)
3512 operands[3] = const0_rtx;
3513 else
3514 operands[3] = GEN_INT (start + size);
3515 operands[2] = GEN_INT (64 - size);
3516 return \"rldicl. %4,%1,%3,%2\";
3517 }"
3518 [(set_attr "type" "compare")])
3519
3520 (define_insn "*extzvdi_internal2"
3521 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3522 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3523 (match_operand:SI 2 "const_int_operand" "i")
3524 (match_operand:SI 3 "const_int_operand" "i"))
3525 (const_int 0)))
3526 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3527 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3528 "TARGET_64BIT && rs6000_gen_cell_microcode"
3529 "*
3530 {
3531 int start = INTVAL (operands[3]) & 63;
3532 int size = INTVAL (operands[2]) & 63;
3533
3534 if (start + size >= 64)
3535 operands[3] = const0_rtx;
3536 else
3537 operands[3] = GEN_INT (start + size);
3538 operands[2] = GEN_INT (64 - size);
3539 return \"rldicl. %0,%1,%3,%2\";
3540 }"
3541 [(set_attr "type" "compare")])
3542
3543 (define_insn "rotlsi3"
3544 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3545 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3546 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3547 ""
3548 "@
3549 rlwnm %0,%1,%2,0xffffffff
3550 rlwinm %0,%1,%h2,0xffffffff"
3551 [(set_attr "type" "var_shift_rotate,integer")])
3552
3553 (define_insn "*rotlsi3_64"
3554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3555 (zero_extend:DI
3556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3557 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3558 "TARGET_64BIT"
3559 "@
3560 rlwnm %0,%1,%2,0xffffffff
3561 rlwinm %0,%1,%h2,0xffffffff"
3562 [(set_attr "type" "var_shift_rotate,integer")])
3563
3564 (define_insn "*rotlsi3_internal2"
3565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3566 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3567 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3568 (const_int 0)))
3569 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3570 ""
3571 "@
3572 rlwnm. %3,%1,%2,0xffffffff
3573 rlwinm. %3,%1,%h2,0xffffffff
3574 #
3575 #"
3576 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3577 (set_attr "length" "4,4,8,8")])
3578
3579 (define_split
3580 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3581 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3582 (match_operand:SI 2 "reg_or_cint_operand" ""))
3583 (const_int 0)))
3584 (clobber (match_scratch:SI 3 ""))]
3585 "reload_completed"
3586 [(set (match_dup 3)
3587 (rotate:SI (match_dup 1) (match_dup 2)))
3588 (set (match_dup 0)
3589 (compare:CC (match_dup 3)
3590 (const_int 0)))]
3591 "")
3592
3593 (define_insn "*rotlsi3_internal3"
3594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3595 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3596 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3597 (const_int 0)))
3598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3599 (rotate:SI (match_dup 1) (match_dup 2)))]
3600 ""
3601 "@
3602 rlwnm. %0,%1,%2,0xffffffff
3603 rlwinm. %0,%1,%h2,0xffffffff
3604 #
3605 #"
3606 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3607 (set_attr "length" "4,4,8,8")])
3608
3609 (define_split
3610 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3611 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3612 (match_operand:SI 2 "reg_or_cint_operand" ""))
3613 (const_int 0)))
3614 (set (match_operand:SI 0 "gpc_reg_operand" "")
3615 (rotate:SI (match_dup 1) (match_dup 2)))]
3616 "reload_completed"
3617 [(set (match_dup 0)
3618 (rotate:SI (match_dup 1) (match_dup 2)))
3619 (set (match_dup 3)
3620 (compare:CC (match_dup 0)
3621 (const_int 0)))]
3622 "")
3623
3624 (define_insn "*rotlsi3_internal4"
3625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3626 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3627 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3628 (match_operand:SI 3 "mask_operand" "n,n")))]
3629 ""
3630 "@
3631 rlwnm %0,%1,%2,%m3,%M3
3632 rlwinm %0,%1,%h2,%m3,%M3"
3633 [(set_attr "type" "var_shift_rotate,integer")])
3634
3635 (define_insn "*rotlsi3_internal5"
3636 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3637 (compare:CC (and:SI
3638 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3639 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3640 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3641 (const_int 0)))
3642 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3643 ""
3644 "@
3645 rlwnm. %4,%1,%2,%m3,%M3
3646 rlwinm. %4,%1,%h2,%m3,%M3
3647 #
3648 #"
3649 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3650 (set_attr "length" "4,4,8,8")])
3651
3652 (define_split
3653 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3654 (compare:CC (and:SI
3655 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3656 (match_operand:SI 2 "reg_or_cint_operand" ""))
3657 (match_operand:SI 3 "mask_operand" ""))
3658 (const_int 0)))
3659 (clobber (match_scratch:SI 4 ""))]
3660 "reload_completed"
3661 [(set (match_dup 4)
3662 (and:SI (rotate:SI (match_dup 1)
3663 (match_dup 2))
3664 (match_dup 3)))
3665 (set (match_dup 0)
3666 (compare:CC (match_dup 4)
3667 (const_int 0)))]
3668 "")
3669
3670 (define_insn "*rotlsi3_internal6"
3671 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3672 (compare:CC (and:SI
3673 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3674 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3675 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3676 (const_int 0)))
3677 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3678 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3679 ""
3680 "@
3681 rlwnm. %0,%1,%2,%m3,%M3
3682 rlwinm. %0,%1,%h2,%m3,%M3
3683 #
3684 #"
3685 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3686 (set_attr "length" "4,4,8,8")])
3687
3688 (define_split
3689 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3690 (compare:CC (and:SI
3691 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3692 (match_operand:SI 2 "reg_or_cint_operand" ""))
3693 (match_operand:SI 3 "mask_operand" ""))
3694 (const_int 0)))
3695 (set (match_operand:SI 0 "gpc_reg_operand" "")
3696 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3697 "reload_completed"
3698 [(set (match_dup 0)
3699 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3700 (set (match_dup 4)
3701 (compare:CC (match_dup 0)
3702 (const_int 0)))]
3703 "")
3704
3705 (define_insn "*rotlsi3_internal7"
3706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3707 (zero_extend:SI
3708 (subreg:QI
3709 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3710 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3711 ""
3712 "rlw%I2nm %0,%1,%h2,0xff"
3713 [(set (attr "cell_micro")
3714 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3715 (const_string "not")
3716 (const_string "always")))])
3717
3718 (define_insn "*rotlsi3_internal8"
3719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3720 (compare:CC (zero_extend:SI
3721 (subreg:QI
3722 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3723 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3724 (const_int 0)))
3725 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3726 ""
3727 "@
3728 rlwnm. %3,%1,%2,0xff
3729 rlwinm. %3,%1,%h2,0xff
3730 #
3731 #"
3732 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3733 (set_attr "length" "4,4,8,8")])
3734
3735 (define_split
3736 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3737 (compare:CC (zero_extend:SI
3738 (subreg:QI
3739 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3740 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3741 (const_int 0)))
3742 (clobber (match_scratch:SI 3 ""))]
3743 "reload_completed"
3744 [(set (match_dup 3)
3745 (zero_extend:SI (subreg:QI
3746 (rotate:SI (match_dup 1)
3747 (match_dup 2)) 0)))
3748 (set (match_dup 0)
3749 (compare:CC (match_dup 3)
3750 (const_int 0)))]
3751 "")
3752
3753 (define_insn "*rotlsi3_internal9"
3754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3755 (compare:CC (zero_extend:SI
3756 (subreg:QI
3757 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3758 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3759 (const_int 0)))
3760 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3761 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3762 ""
3763 "@
3764 rlwnm. %0,%1,%2,0xff
3765 rlwinm. %0,%1,%h2,0xff
3766 #
3767 #"
3768 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3769 (set_attr "length" "4,4,8,8")])
3770
3771 (define_split
3772 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3773 (compare:CC (zero_extend:SI
3774 (subreg:QI
3775 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3776 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3777 (const_int 0)))
3778 (set (match_operand:SI 0 "gpc_reg_operand" "")
3779 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3780 "reload_completed"
3781 [(set (match_dup 0)
3782 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3783 (set (match_dup 3)
3784 (compare:CC (match_dup 0)
3785 (const_int 0)))]
3786 "")
3787
3788 (define_insn "*rotlsi3_internal10"
3789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3790 (zero_extend:SI
3791 (subreg:HI
3792 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3793 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
3794 ""
3795 "@
3796 rlwnm %0,%1,%2,0xffff
3797 rlwinm %0,%1,%h2,0xffff"
3798 [(set_attr "type" "var_shift_rotate,integer")])
3799
3800
3801 (define_insn "*rotlsi3_internal11"
3802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3803 (compare:CC (zero_extend:SI
3804 (subreg:HI
3805 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3806 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3807 (const_int 0)))
3808 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3809 ""
3810 "@
3811 rlwnm. %3,%1,%2,0xffff
3812 rlwinm. %3,%1,%h2,0xffff
3813 #
3814 #"
3815 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3816 (set_attr "length" "4,4,8,8")])
3817
3818 (define_split
3819 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3820 (compare:CC (zero_extend:SI
3821 (subreg:HI
3822 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3823 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3824 (const_int 0)))
3825 (clobber (match_scratch:SI 3 ""))]
3826 "reload_completed"
3827 [(set (match_dup 3)
3828 (zero_extend:SI (subreg:HI
3829 (rotate:SI (match_dup 1)
3830 (match_dup 2)) 0)))
3831 (set (match_dup 0)
3832 (compare:CC (match_dup 3)
3833 (const_int 0)))]
3834 "")
3835
3836 (define_insn "*rotlsi3_internal12"
3837 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3838 (compare:CC (zero_extend:SI
3839 (subreg:HI
3840 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3841 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3842 (const_int 0)))
3843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3844 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3845 ""
3846 "@
3847 rlwnm. %0,%1,%2,0xffff
3848 rlwinm. %0,%1,%h2,0xffff
3849 #
3850 #"
3851 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3852 (set_attr "length" "4,4,8,8")])
3853
3854 (define_split
3855 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3856 (compare:CC (zero_extend:SI
3857 (subreg:HI
3858 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3859 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3860 (const_int 0)))
3861 (set (match_operand:SI 0 "gpc_reg_operand" "")
3862 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3863 "reload_completed"
3864 [(set (match_dup 0)
3865 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3866 (set (match_dup 3)
3867 (compare:CC (match_dup 0)
3868 (const_int 0)))]
3869 "")
3870
3871 (define_insn "ashlsi3"
3872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3873 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3874 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3875 ""
3876 "@
3877 slw %0,%1,%2
3878 slwi %0,%1,%h2"
3879 [(set_attr "type" "var_shift_rotate,shift")])
3880
3881 (define_insn "*ashlsi3_64"
3882 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3883 (zero_extend:DI
3884 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3885 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3886 "TARGET_POWERPC64"
3887 "@
3888 slw %0,%1,%2
3889 slwi %0,%1,%h2"
3890 [(set_attr "type" "var_shift_rotate,shift")])
3891
3892 (define_insn ""
3893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3894 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3895 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3896 (const_int 0)))
3897 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3898 "TARGET_32BIT"
3899 "@
3900 slw. %3,%1,%2
3901 slwi. %3,%1,%h2
3902 #
3903 #"
3904 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3905 (set_attr "length" "4,4,8,8")])
3906
3907 (define_split
3908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3909 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3910 (match_operand:SI 2 "reg_or_cint_operand" ""))
3911 (const_int 0)))
3912 (clobber (match_scratch:SI 3 ""))]
3913 "TARGET_32BIT && reload_completed"
3914 [(set (match_dup 3)
3915 (ashift:SI (match_dup 1) (match_dup 2)))
3916 (set (match_dup 0)
3917 (compare:CC (match_dup 3)
3918 (const_int 0)))]
3919 "")
3920
3921 (define_insn ""
3922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3923 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3924 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3925 (const_int 0)))
3926 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3927 (ashift:SI (match_dup 1) (match_dup 2)))]
3928 "TARGET_32BIT"
3929 "@
3930 slw. %0,%1,%2
3931 slwi. %0,%1,%h2
3932 #
3933 #"
3934 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3935 (set_attr "length" "4,4,8,8")])
3936
3937 (define_split
3938 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3939 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3940 (match_operand:SI 2 "reg_or_cint_operand" ""))
3941 (const_int 0)))
3942 (set (match_operand:SI 0 "gpc_reg_operand" "")
3943 (ashift:SI (match_dup 1) (match_dup 2)))]
3944 "TARGET_32BIT && reload_completed"
3945 [(set (match_dup 0)
3946 (ashift:SI (match_dup 1) (match_dup 2)))
3947 (set (match_dup 3)
3948 (compare:CC (match_dup 0)
3949 (const_int 0)))]
3950 "")
3951
3952 (define_insn "rlwinm"
3953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3954 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3955 (match_operand:SI 2 "const_int_operand" "i"))
3956 (match_operand:SI 3 "mask_operand" "n")))]
3957 "includes_lshift_p (operands[2], operands[3])"
3958 "rlwinm %0,%1,%h2,%m3,%M3")
3959
3960 (define_insn ""
3961 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3962 (compare:CC
3963 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3964 (match_operand:SI 2 "const_int_operand" "i,i"))
3965 (match_operand:SI 3 "mask_operand" "n,n"))
3966 (const_int 0)))
3967 (clobber (match_scratch:SI 4 "=r,r"))]
3968 "includes_lshift_p (operands[2], operands[3])"
3969 "@
3970 rlwinm. %4,%1,%h2,%m3,%M3
3971 #"
3972 [(set_attr "type" "delayed_compare")
3973 (set_attr "length" "4,8")])
3974
3975 (define_split
3976 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3977 (compare:CC
3978 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3979 (match_operand:SI 2 "const_int_operand" ""))
3980 (match_operand:SI 3 "mask_operand" ""))
3981 (const_int 0)))
3982 (clobber (match_scratch:SI 4 ""))]
3983 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3984 [(set (match_dup 4)
3985 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3986 (match_dup 3)))
3987 (set (match_dup 0)
3988 (compare:CC (match_dup 4)
3989 (const_int 0)))]
3990 "")
3991
3992 (define_insn ""
3993 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3994 (compare:CC
3995 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3996 (match_operand:SI 2 "const_int_operand" "i,i"))
3997 (match_operand:SI 3 "mask_operand" "n,n"))
3998 (const_int 0)))
3999 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4000 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4001 "includes_lshift_p (operands[2], operands[3])"
4002 "@
4003 rlwinm. %0,%1,%h2,%m3,%M3
4004 #"
4005 [(set_attr "type" "delayed_compare")
4006 (set_attr "length" "4,8")])
4007
4008 (define_split
4009 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4010 (compare:CC
4011 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "const_int_operand" ""))
4013 (match_operand:SI 3 "mask_operand" ""))
4014 (const_int 0)))
4015 (set (match_operand:SI 0 "gpc_reg_operand" "")
4016 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4017 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4018 [(set (match_dup 0)
4019 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4020 (set (match_dup 4)
4021 (compare:CC (match_dup 0)
4022 (const_int 0)))]
4023 "")
4024
4025 (define_insn "lshrsi3"
4026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4027 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4028 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4029 ""
4030 "@
4031 mr %0,%1
4032 srw %0,%1,%2
4033 srwi %0,%1,%h2"
4034 [(set_attr "type" "integer,var_shift_rotate,shift")])
4035
4036 (define_insn "*lshrsi3_64"
4037 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4038 (zero_extend:DI
4039 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4040 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4041 "TARGET_POWERPC64"
4042 "@
4043 srw %0,%1,%2
4044 srwi %0,%1,%h2"
4045 [(set_attr "type" "var_shift_rotate,shift")])
4046
4047 (define_insn ""
4048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4049 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4050 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4053 "TARGET_32BIT"
4054 "@
4055 mr. %1,%1
4056 srw. %3,%1,%2
4057 srwi. %3,%1,%h2
4058 #
4059 #
4060 #"
4061 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4062 (set_attr "length" "4,4,4,8,8,8")])
4063
4064 (define_split
4065 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4066 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4067 (match_operand:SI 2 "reg_or_cint_operand" ""))
4068 (const_int 0)))
4069 (clobber (match_scratch:SI 3 ""))]
4070 "TARGET_32BIT && reload_completed"
4071 [(set (match_dup 3)
4072 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4073 (set (match_dup 0)
4074 (compare:CC (match_dup 3)
4075 (const_int 0)))]
4076 "")
4077
4078 (define_insn ""
4079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4080 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4081 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4082 (const_int 0)))
4083 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4084 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4085 "TARGET_32BIT"
4086 "@
4087 mr. %0,%1
4088 srw. %0,%1,%2
4089 srwi. %0,%1,%h2
4090 #
4091 #
4092 #"
4093 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4094 (set_attr "length" "4,4,4,8,8,8")])
4095
4096 (define_split
4097 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4098 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4099 (match_operand:SI 2 "reg_or_cint_operand" ""))
4100 (const_int 0)))
4101 (set (match_operand:SI 0 "gpc_reg_operand" "")
4102 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4103 "TARGET_32BIT && reload_completed"
4104 [(set (match_dup 0)
4105 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4106 (set (match_dup 3)
4107 (compare:CC (match_dup 0)
4108 (const_int 0)))]
4109 "")
4110
4111 (define_insn ""
4112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4113 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4114 (match_operand:SI 2 "const_int_operand" "i"))
4115 (match_operand:SI 3 "mask_operand" "n")))]
4116 "includes_rshift_p (operands[2], operands[3])"
4117 "rlwinm %0,%1,%s2,%m3,%M3")
4118
4119 (define_insn ""
4120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4121 (compare:CC
4122 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4123 (match_operand:SI 2 "const_int_operand" "i,i"))
4124 (match_operand:SI 3 "mask_operand" "n,n"))
4125 (const_int 0)))
4126 (clobber (match_scratch:SI 4 "=r,r"))]
4127 "includes_rshift_p (operands[2], operands[3])"
4128 "@
4129 rlwinm. %4,%1,%s2,%m3,%M3
4130 #"
4131 [(set_attr "type" "delayed_compare")
4132 (set_attr "length" "4,8")])
4133
4134 (define_split
4135 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4136 (compare:CC
4137 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4138 (match_operand:SI 2 "const_int_operand" ""))
4139 (match_operand:SI 3 "mask_operand" ""))
4140 (const_int 0)))
4141 (clobber (match_scratch:SI 4 ""))]
4142 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4143 [(set (match_dup 4)
4144 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4145 (match_dup 3)))
4146 (set (match_dup 0)
4147 (compare:CC (match_dup 4)
4148 (const_int 0)))]
4149 "")
4150
4151 (define_insn ""
4152 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4153 (compare:CC
4154 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4155 (match_operand:SI 2 "const_int_operand" "i,i"))
4156 (match_operand:SI 3 "mask_operand" "n,n"))
4157 (const_int 0)))
4158 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4159 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4160 "includes_rshift_p (operands[2], operands[3])"
4161 "@
4162 rlwinm. %0,%1,%s2,%m3,%M3
4163 #"
4164 [(set_attr "type" "delayed_compare")
4165 (set_attr "length" "4,8")])
4166
4167 (define_split
4168 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4169 (compare:CC
4170 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4171 (match_operand:SI 2 "const_int_operand" ""))
4172 (match_operand:SI 3 "mask_operand" ""))
4173 (const_int 0)))
4174 (set (match_operand:SI 0 "gpc_reg_operand" "")
4175 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4176 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4177 [(set (match_dup 0)
4178 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4179 (set (match_dup 4)
4180 (compare:CC (match_dup 0)
4181 (const_int 0)))]
4182 "")
4183
4184 (define_insn ""
4185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4186 (zero_extend:SI
4187 (subreg:QI
4188 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4189 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4190 "includes_rshift_p (operands[2], GEN_INT (255))"
4191 "rlwinm %0,%1,%s2,0xff")
4192
4193 (define_insn ""
4194 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4195 (compare:CC
4196 (zero_extend:SI
4197 (subreg:QI
4198 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4199 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4200 (const_int 0)))
4201 (clobber (match_scratch:SI 3 "=r,r"))]
4202 "includes_rshift_p (operands[2], GEN_INT (255))"
4203 "@
4204 rlwinm. %3,%1,%s2,0xff
4205 #"
4206 [(set_attr "type" "delayed_compare")
4207 (set_attr "length" "4,8")])
4208
4209 (define_split
4210 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4211 (compare:CC
4212 (zero_extend:SI
4213 (subreg:QI
4214 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4215 (match_operand:SI 2 "const_int_operand" "")) 0))
4216 (const_int 0)))
4217 (clobber (match_scratch:SI 3 ""))]
4218 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4219 [(set (match_dup 3)
4220 (zero_extend:SI (subreg:QI
4221 (lshiftrt:SI (match_dup 1)
4222 (match_dup 2)) 0)))
4223 (set (match_dup 0)
4224 (compare:CC (match_dup 3)
4225 (const_int 0)))]
4226 "")
4227
4228 (define_insn ""
4229 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4230 (compare:CC
4231 (zero_extend:SI
4232 (subreg:QI
4233 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4234 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4235 (const_int 0)))
4236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4237 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4238 "includes_rshift_p (operands[2], GEN_INT (255))"
4239 "@
4240 rlwinm. %0,%1,%s2,0xff
4241 #"
4242 [(set_attr "type" "delayed_compare")
4243 (set_attr "length" "4,8")])
4244
4245 (define_split
4246 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4247 (compare:CC
4248 (zero_extend:SI
4249 (subreg:QI
4250 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4251 (match_operand:SI 2 "const_int_operand" "")) 0))
4252 (const_int 0)))
4253 (set (match_operand:SI 0 "gpc_reg_operand" "")
4254 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4255 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4256 [(set (match_dup 0)
4257 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4258 (set (match_dup 3)
4259 (compare:CC (match_dup 0)
4260 (const_int 0)))]
4261 "")
4262
4263 (define_insn ""
4264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4265 (zero_extend:SI
4266 (subreg:HI
4267 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4268 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4269 "includes_rshift_p (operands[2], GEN_INT (65535))"
4270 "rlwinm %0,%1,%s2,0xffff")
4271
4272 (define_insn ""
4273 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4274 (compare:CC
4275 (zero_extend:SI
4276 (subreg:HI
4277 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4278 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4279 (const_int 0)))
4280 (clobber (match_scratch:SI 3 "=r,r"))]
4281 "includes_rshift_p (operands[2], GEN_INT (65535))"
4282 "@
4283 rlwinm. %3,%1,%s2,0xffff
4284 #"
4285 [(set_attr "type" "delayed_compare")
4286 (set_attr "length" "4,8")])
4287
4288 (define_split
4289 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4290 (compare:CC
4291 (zero_extend:SI
4292 (subreg:HI
4293 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4294 (match_operand:SI 2 "const_int_operand" "")) 0))
4295 (const_int 0)))
4296 (clobber (match_scratch:SI 3 ""))]
4297 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4298 [(set (match_dup 3)
4299 (zero_extend:SI (subreg:HI
4300 (lshiftrt:SI (match_dup 1)
4301 (match_dup 2)) 0)))
4302 (set (match_dup 0)
4303 (compare:CC (match_dup 3)
4304 (const_int 0)))]
4305 "")
4306
4307 (define_insn ""
4308 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4309 (compare:CC
4310 (zero_extend:SI
4311 (subreg:HI
4312 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4313 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4314 (const_int 0)))
4315 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4316 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4317 "includes_rshift_p (operands[2], GEN_INT (65535))"
4318 "@
4319 rlwinm. %0,%1,%s2,0xffff
4320 #"
4321 [(set_attr "type" "delayed_compare")
4322 (set_attr "length" "4,8")])
4323
4324 (define_split
4325 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4326 (compare:CC
4327 (zero_extend:SI
4328 (subreg:HI
4329 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4330 (match_operand:SI 2 "const_int_operand" "")) 0))
4331 (const_int 0)))
4332 (set (match_operand:SI 0 "gpc_reg_operand" "")
4333 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4334 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4335 [(set (match_dup 0)
4336 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4337 (set (match_dup 3)
4338 (compare:CC (match_dup 0)
4339 (const_int 0)))]
4340 "")
4341
4342 (define_insn "ashrsi3"
4343 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4344 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4345 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4346 ""
4347 "@
4348 sraw %0,%1,%2
4349 srawi %0,%1,%h2"
4350 [(set_attr "type" "var_shift_rotate,shift")])
4351
4352 (define_insn "*ashrsi3_64"
4353 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4354 (sign_extend:DI
4355 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4357 "TARGET_POWERPC64"
4358 "@
4359 sraw %0,%1,%2
4360 srawi %0,%1,%h2"
4361 [(set_attr "type" "var_shift_rotate,shift")])
4362
4363 (define_insn ""
4364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4365 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4366 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4367 (const_int 0)))
4368 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4369 ""
4370 "@
4371 sraw. %3,%1,%2
4372 srawi. %3,%1,%h2
4373 #
4374 #"
4375 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4376 (set_attr "length" "4,4,8,8")])
4377
4378 (define_split
4379 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4380 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4381 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (const_int 0)))
4383 (clobber (match_scratch:SI 3 ""))]
4384 "reload_completed"
4385 [(set (match_dup 3)
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4387 (set (match_dup 0)
4388 (compare:CC (match_dup 3)
4389 (const_int 0)))]
4390 "")
4391
4392 (define_insn ""
4393 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4394 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4395 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4396 (const_int 0)))
4397 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4398 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4399 ""
4400 "@
4401 sraw. %0,%1,%2
4402 srawi. %0,%1,%h2
4403 #
4404 #"
4405 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4406 (set_attr "length" "4,4,8,8")])
4407 \f
4408 ;; Builtins to replace a division to generate FRE reciprocal estimate
4409 ;; instructions and the necessary fixup instructions
4410 (define_expand "recip<mode>3"
4411 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4412 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4413 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4414 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4415 {
4416 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4417 DONE;
4418 })
4419
4420 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4421 ;; hardware division. This is only done before register allocation and with
4422 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4423 (define_split
4424 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4425 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4426 (match_operand 2 "gpc_reg_operand" "")))]
4427 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4428 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4429 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4430 [(const_int 0)]
4431 {
4432 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4433 DONE;
4434 })
4435
4436 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4437 ;; appropriate fixup.
4438 (define_expand "rsqrt<mode>2"
4439 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4440 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4441 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4442 {
4443 rs6000_emit_swrsqrt (operands[0], operands[1]);
4444 DONE;
4445 })
4446 \f
4447 (define_split
4448 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4449 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4450 (match_operand:SI 2 "reg_or_cint_operand" ""))
4451 (const_int 0)))
4452 (set (match_operand:SI 0 "gpc_reg_operand" "")
4453 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4454 "reload_completed"
4455 [(set (match_dup 0)
4456 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4457 (set (match_dup 3)
4458 (compare:CC (match_dup 0)
4459 (const_int 0)))]
4460 "")
4461
4462 ;; Floating-point insns, excluding normal data motion.
4463 ;;
4464 ;; PowerPC has a full set of single-precision floating point instructions.
4465 ;;
4466 ;; For the POWER architecture, we pretend that we have both SFmode and
4467 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4468 ;; The only conversions we will do will be when storing to memory. In that
4469 ;; case, we will use the "frsp" instruction before storing.
4470 ;;
4471 ;; Note that when we store into a single-precision memory location, we need to
4472 ;; use the frsp insn first. If the register being stored isn't dead, we
4473 ;; need a scratch register for the frsp. But this is difficult when the store
4474 ;; is done by reload. It is not incorrect to do the frsp on the register in
4475 ;; this case, we just lose precision that we would have otherwise gotten but
4476 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4477
4478 (define_expand "extendsfdf2"
4479 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4480 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4481 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4482 "")
4483
4484 (define_insn_and_split "*extendsfdf2_fpr"
4485 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4486 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4487 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4488 "@
4489 #
4490 fmr %0,%1
4491 lfs%U1%X1 %0,%1"
4492 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4493 [(const_int 0)]
4494 {
4495 emit_note (NOTE_INSN_DELETED);
4496 DONE;
4497 }
4498 [(set_attr "type" "fp,fp,fpload")])
4499
4500 (define_expand "truncdfsf2"
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4502 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4503 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4504 "")
4505
4506 (define_insn "*truncdfsf2_fpr"
4507 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4508 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4509 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4510 "frsp %0,%1"
4511 [(set_attr "type" "fp")])
4512
4513 (define_expand "negsf2"
4514 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4515 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4516 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4517 "")
4518
4519 (define_insn "*negsf2"
4520 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4521 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4522 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4523 "fneg %0,%1"
4524 [(set_attr "type" "fp")])
4525
4526 (define_expand "abssf2"
4527 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4528 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4529 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4530 "")
4531
4532 (define_insn "*abssf2"
4533 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4534 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4535 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4536 "fabs %0,%1"
4537 [(set_attr "type" "fp")])
4538
4539 (define_insn ""
4540 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4541 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4543 "fnabs %0,%1"
4544 [(set_attr "type" "fp")])
4545
4546 (define_expand "addsf3"
4547 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4548 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4549 (match_operand:SF 2 "gpc_reg_operand" "")))]
4550 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4551 "")
4552
4553 (define_insn ""
4554 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4555 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4556 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4557 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4558 "fadds %0,%1,%2"
4559 [(set_attr "type" "fp")
4560 (set_attr "fp_type" "fp_addsub_s")])
4561
4562 (define_expand "subsf3"
4563 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4564 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4565 (match_operand:SF 2 "gpc_reg_operand" "")))]
4566 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4567 "")
4568
4569 (define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4573 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4574 "fsubs %0,%1,%2"
4575 [(set_attr "type" "fp")
4576 (set_attr "fp_type" "fp_addsub_s")])
4577
4578 (define_expand "mulsf3"
4579 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4580 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4581 (match_operand:SF 2 "gpc_reg_operand" "")))]
4582 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4583 "")
4584
4585 (define_insn ""
4586 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4587 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4588 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4589 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4590 "fmuls %0,%1,%2"
4591 [(set_attr "type" "fp")
4592 (set_attr "fp_type" "fp_mul_s")])
4593
4594 (define_expand "divsf3"
4595 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4596 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4597 (match_operand:SF 2 "gpc_reg_operand" "")))]
4598 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4599 "")
4600
4601 (define_insn ""
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4604 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4605 "TARGET_HARD_FLOAT && TARGET_FPRS
4606 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4607 "fdivs %0,%1,%2"
4608 [(set_attr "type" "sdiv")])
4609
4610 (define_insn "fres"
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4613 "TARGET_FRES"
4614 "fres %0,%1"
4615 [(set_attr "type" "fp")])
4616
4617 ; builtin fmaf support
4618 (define_insn "*fmasf4_fpr"
4619 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4620 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4621 (match_operand:SF 2 "gpc_reg_operand" "f")
4622 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4623 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4624 "fmadds %0,%1,%2,%3"
4625 [(set_attr "type" "fp")
4626 (set_attr "fp_type" "fp_maddsub_s")])
4627
4628 (define_insn "*fmssf4_fpr"
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4630 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4631 (match_operand:SF 2 "gpc_reg_operand" "f")
4632 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4633 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4634 "fmsubs %0,%1,%2,%3"
4635 [(set_attr "type" "fp")
4636 (set_attr "fp_type" "fp_maddsub_s")])
4637
4638 (define_insn "*nfmasf4_fpr"
4639 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4640 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4641 (match_operand:SF 2 "gpc_reg_operand" "f")
4642 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4644 "fnmadds %0,%1,%2,%3"
4645 [(set_attr "type" "fp")
4646 (set_attr "fp_type" "fp_maddsub_s")])
4647
4648 (define_insn "*nfmssf4_fpr"
4649 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4650 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4651 (match_operand:SF 2 "gpc_reg_operand" "f")
4652 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
4653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4654 "fnmsubs %0,%1,%2,%3"
4655 [(set_attr "type" "fp")
4656 (set_attr "fp_type" "fp_maddsub_s")])
4657
4658 (define_expand "sqrtsf2"
4659 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4660 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4661 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
4662 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
4663 && !TARGET_SIMPLE_FPU"
4664 "")
4665
4666 (define_insn ""
4667 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4668 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4669 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
4670 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4671 "fsqrts %0,%1"
4672 [(set_attr "type" "ssqrt")])
4673
4674 (define_insn "*rsqrtsf_internal1"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4676 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
4677 UNSPEC_RSQRT))]
4678 "TARGET_FRSQRTES"
4679 "frsqrtes %0,%1"
4680 [(set_attr "type" "fp")])
4681
4682 (define_expand "copysign<mode>3"
4683 [(set (match_dup 3)
4684 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
4685 (set (match_dup 4)
4686 (neg:SFDF (abs:SFDF (match_dup 1))))
4687 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
4688 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
4689 (match_dup 5))
4690 (match_dup 3)
4691 (match_dup 4)))]
4692 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
4693 && ((TARGET_PPC_GFXOPT
4694 && !HONOR_NANS (<MODE>mode)
4695 && !HONOR_SIGNED_ZEROS (<MODE>mode))
4696 || TARGET_CMPB
4697 || VECTOR_UNIT_VSX_P (<MODE>mode))"
4698 {
4699 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
4700 {
4701 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
4702 operands[2]));
4703 DONE;
4704 }
4705
4706 operands[3] = gen_reg_rtx (<MODE>mode);
4707 operands[4] = gen_reg_rtx (<MODE>mode);
4708 operands[5] = CONST0_RTX (<MODE>mode);
4709 })
4710
4711 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
4712 ;; compiler from optimizing -0.0
4713 (define_insn "copysign<mode>3_fcpsgn"
4714 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
4715 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
4716 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
4717 UNSPEC_COPYSIGN))]
4718 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
4719 "fcpsgn %0,%2,%1"
4720 [(set_attr "type" "fp")])
4721
4722 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4723 ;; fsel instruction and some auxiliary computations. Then we just have a
4724 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4725 ;; combine.
4726 (define_expand "smaxsf3"
4727 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4728 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4729 (match_operand:SF 2 "gpc_reg_operand" ""))
4730 (match_dup 1)
4731 (match_dup 2)))]
4732 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4733 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4734 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4735
4736 (define_expand "sminsf3"
4737 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4738 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4739 (match_operand:SF 2 "gpc_reg_operand" ""))
4740 (match_dup 2)
4741 (match_dup 1)))]
4742 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4743 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4744 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4745
4746 (define_split
4747 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4748 (match_operator:SF 3 "min_max_operator"
4749 [(match_operand:SF 1 "gpc_reg_operand" "")
4750 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4751 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4752 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4753 [(const_int 0)]
4754 "
4755 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4756 operands[1], operands[2]);
4757 DONE;
4758 }")
4759
4760 (define_expand "mov<mode>cc"
4761 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4762 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
4763 (match_operand:GPR 2 "gpc_reg_operand" "")
4764 (match_operand:GPR 3 "gpc_reg_operand" "")))]
4765 "TARGET_ISEL<sel>"
4766 "
4767 {
4768 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4769 DONE;
4770 else
4771 FAIL;
4772 }")
4773
4774 ;; We use the BASE_REGS for the isel input operands because, if rA is
4775 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4776 ;; because we may switch the operands and rB may end up being rA.
4777 ;;
4778 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4779 ;; leave out the mode in operand 4 and use one pattern, but reload can
4780 ;; change the mode underneath our feet and then gets confused trying
4781 ;; to reload the value.
4782 (define_insn "isel_signed_<mode>"
4783 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4784 (if_then_else:GPR
4785 (match_operator 1 "scc_comparison_operator"
4786 [(match_operand:CC 4 "cc_reg_operand" "y,y")
4787 (const_int 0)])
4788 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4789 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4790 "TARGET_ISEL<sel>"
4791 "*
4792 { return output_isel (operands); }"
4793 [(set_attr "type" "isel")
4794 (set_attr "length" "4")])
4795
4796 (define_insn "isel_unsigned_<mode>"
4797 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4798 (if_then_else:GPR
4799 (match_operator 1 "scc_comparison_operator"
4800 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
4801 (const_int 0)])
4802 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4803 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4804 "TARGET_ISEL<sel>"
4805 "*
4806 { return output_isel (operands); }"
4807 [(set_attr "type" "isel")
4808 (set_attr "length" "4")])
4809
4810 ;; These patterns can be useful for combine; they let combine know that
4811 ;; isel can handle reversed comparisons so long as the operands are
4812 ;; registers.
4813
4814 (define_insn "*isel_reversed_signed_<mode>"
4815 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4816 (if_then_else:GPR
4817 (match_operator 1 "scc_rev_comparison_operator"
4818 [(match_operand:CC 4 "cc_reg_operand" "y")
4819 (const_int 0)])
4820 (match_operand:GPR 2 "gpc_reg_operand" "b")
4821 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4822 "TARGET_ISEL<sel>"
4823 "*
4824 { return output_isel (operands); }"
4825 [(set_attr "type" "isel")
4826 (set_attr "length" "4")])
4827
4828 (define_insn "*isel_reversed_unsigned_<mode>"
4829 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4830 (if_then_else:GPR
4831 (match_operator 1 "scc_rev_comparison_operator"
4832 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4833 (const_int 0)])
4834 (match_operand:GPR 2 "gpc_reg_operand" "b")
4835 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4836 "TARGET_ISEL<sel>"
4837 "*
4838 { return output_isel (operands); }"
4839 [(set_attr "type" "isel")
4840 (set_attr "length" "4")])
4841
4842 (define_expand "movsfcc"
4843 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4844 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4845 (match_operand:SF 2 "gpc_reg_operand" "")
4846 (match_operand:SF 3 "gpc_reg_operand" "")))]
4847 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4848 "
4849 {
4850 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4851 DONE;
4852 else
4853 FAIL;
4854 }")
4855
4856 (define_insn "*fselsfsf4"
4857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4858 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4859 (match_operand:SF 4 "zero_fp_constant" "F"))
4860 (match_operand:SF 2 "gpc_reg_operand" "f")
4861 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4862 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4863 "fsel %0,%1,%2,%3"
4864 [(set_attr "type" "fp")])
4865
4866 (define_insn "*fseldfsf4"
4867 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4868 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
4869 (match_operand:DF 4 "zero_fp_constant" "F"))
4870 (match_operand:SF 2 "gpc_reg_operand" "f")
4871 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4872 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
4873 "fsel %0,%1,%2,%3"
4874 [(set_attr "type" "fp")])
4875
4876 (define_expand "negdf2"
4877 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4878 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4879 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4880 "")
4881
4882 (define_insn "*negdf2_fpr"
4883 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4884 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4885 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4886 && !VECTOR_UNIT_VSX_P (DFmode)"
4887 "fneg %0,%1"
4888 [(set_attr "type" "fp")])
4889
4890 (define_expand "absdf2"
4891 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4892 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4893 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4894 "")
4895
4896 (define_insn "*absdf2_fpr"
4897 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4898 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4899 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4900 && !VECTOR_UNIT_VSX_P (DFmode)"
4901 "fabs %0,%1"
4902 [(set_attr "type" "fp")])
4903
4904 (define_insn "*nabsdf2_fpr"
4905 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4906 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
4907 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4908 && !VECTOR_UNIT_VSX_P (DFmode)"
4909 "fnabs %0,%1"
4910 [(set_attr "type" "fp")])
4911
4912 (define_expand "adddf3"
4913 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4914 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4915 (match_operand:DF 2 "gpc_reg_operand" "")))]
4916 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4917 "")
4918
4919 (define_insn "*adddf3_fpr"
4920 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4921 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4922 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4923 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4924 && !VECTOR_UNIT_VSX_P (DFmode)"
4925 "fadd %0,%1,%2"
4926 [(set_attr "type" "fp")
4927 (set_attr "fp_type" "fp_addsub_d")])
4928
4929 (define_expand "subdf3"
4930 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4931 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4932 (match_operand:DF 2 "gpc_reg_operand" "")))]
4933 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4934 "")
4935
4936 (define_insn "*subdf3_fpr"
4937 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4938 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4939 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4940 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4941 && !VECTOR_UNIT_VSX_P (DFmode)"
4942 "fsub %0,%1,%2"
4943 [(set_attr "type" "fp")
4944 (set_attr "fp_type" "fp_addsub_d")])
4945
4946 (define_expand "muldf3"
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4948 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4949 (match_operand:DF 2 "gpc_reg_operand" "")))]
4950 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4951 "")
4952
4953 (define_insn "*muldf3_fpr"
4954 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4955 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4956 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4957 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4958 && !VECTOR_UNIT_VSX_P (DFmode)"
4959 "fmul %0,%1,%2"
4960 [(set_attr "type" "dmul")
4961 (set_attr "fp_type" "fp_mul_d")])
4962
4963 (define_expand "divdf3"
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4965 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4966 (match_operand:DF 2 "gpc_reg_operand" "")))]
4967 "TARGET_HARD_FLOAT
4968 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
4969 && !TARGET_SIMPLE_FPU"
4970 "")
4971
4972 (define_insn "*divdf3_fpr"
4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4974 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4975 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4976 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
4977 && !VECTOR_UNIT_VSX_P (DFmode)"
4978 "fdiv %0,%1,%2"
4979 [(set_attr "type" "ddiv")])
4980
4981 (define_insn "*fred_fpr"
4982 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4983 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4984 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
4985 "fre %0,%1"
4986 [(set_attr "type" "fp")])
4987
4988 (define_insn "*rsqrtdf_internal1"
4989 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4990 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
4991 UNSPEC_RSQRT))]
4992 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
4993 "frsqrte %0,%1"
4994 [(set_attr "type" "fp")])
4995
4996 ; builtin fma support
4997 (define_insn "*fmadf4_fpr"
4998 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4999 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5000 (match_operand:DF 2 "gpc_reg_operand" "f")
5001 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5002 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5003 && VECTOR_UNIT_NONE_P (DFmode)"
5004 "fmadd %0,%1,%2,%3"
5005 [(set_attr "type" "fp")
5006 (set_attr "fp_type" "fp_maddsub_d")])
5007
5008 (define_insn "*fmsdf4_fpr"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5010 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5011 (match_operand:DF 2 "gpc_reg_operand" "f")
5012 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5013 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5014 && VECTOR_UNIT_NONE_P (DFmode)"
5015 "fmsub %0,%1,%2,%3"
5016 [(set_attr "type" "fp")
5017 (set_attr "fp_type" "fp_maddsub_d")])
5018
5019 (define_insn "*nfmadf4_fpr"
5020 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5021 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5022 (match_operand:DF 2 "gpc_reg_operand" "f")
5023 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5024 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5025 && VECTOR_UNIT_NONE_P (DFmode)"
5026 "fnmadd %0,%1,%2,%3"
5027 [(set_attr "type" "fp")
5028 (set_attr "fp_type" "fp_maddsub_d")])
5029
5030 (define_insn "*nfmsdf4_fpr"
5031 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5032 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5033 (match_operand:DF 2 "gpc_reg_operand" "f")
5034 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5035 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5036 && VECTOR_UNIT_NONE_P (DFmode)"
5037 "fnmsub %0,%1,%2,%3"
5038 [(set_attr "type" "fp")
5039 (set_attr "fp_type" "fp_maddsub_d")])
5040
5041 (define_expand "sqrtdf2"
5042 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5043 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5044 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5045 "")
5046
5047 (define_insn "*sqrtdf2_fpr"
5048 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5049 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5050 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5051 && !VECTOR_UNIT_VSX_P (DFmode)"
5052 "fsqrt %0,%1"
5053 [(set_attr "type" "dsqrt")])
5054
5055 ;; The conditional move instructions allow us to perform max and min
5056 ;; operations even when
5057
5058 (define_expand "smaxdf3"
5059 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5060 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5061 (match_operand:DF 2 "gpc_reg_operand" ""))
5062 (match_dup 1)
5063 (match_dup 2)))]
5064 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5065 && !flag_trapping_math"
5066 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5067
5068 (define_expand "smindf3"
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5070 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5071 (match_operand:DF 2 "gpc_reg_operand" ""))
5072 (match_dup 2)
5073 (match_dup 1)))]
5074 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5075 && !flag_trapping_math"
5076 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5077
5078 (define_split
5079 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5080 (match_operator:DF 3 "min_max_operator"
5081 [(match_operand:DF 1 "gpc_reg_operand" "")
5082 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5083 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5084 && !flag_trapping_math"
5085 [(const_int 0)]
5086 "
5087 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5088 operands[1], operands[2]);
5089 DONE;
5090 }")
5091
5092 (define_expand "movdfcc"
5093 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5094 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5095 (match_operand:DF 2 "gpc_reg_operand" "")
5096 (match_operand:DF 3 "gpc_reg_operand" "")))]
5097 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5098 "
5099 {
5100 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5101 DONE;
5102 else
5103 FAIL;
5104 }")
5105
5106 (define_insn "*fseldfdf4"
5107 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5108 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5109 (match_operand:DF 4 "zero_fp_constant" "F"))
5110 (match_operand:DF 2 "gpc_reg_operand" "d")
5111 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5112 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5113 "fsel %0,%1,%2,%3"
5114 [(set_attr "type" "fp")])
5115
5116 (define_insn "*fselsfdf4"
5117 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5118 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5119 (match_operand:SF 4 "zero_fp_constant" "F"))
5120 (match_operand:DF 2 "gpc_reg_operand" "d")
5121 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5122 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5123 "fsel %0,%1,%2,%3"
5124 [(set_attr "type" "fp")])
5125 \f
5126 ;; Conversions to and from floating-point.
5127
5128 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5129 ; don't want to support putting SImode in FPR registers.
5130 (define_insn "lfiwax"
5131 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5132 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5133 UNSPEC_LFIWAX))]
5134 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5135 "lfiwax %0,%y1"
5136 [(set_attr "type" "fpload")])
5137
5138 ; This split must be run before register allocation because it allocates the
5139 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5140 ; it earlier to allow for the combiner to merge insns together where it might
5141 ; not be needed and also in case the insns are deleted as dead code.
5142
5143 (define_insn_and_split "floatsi<mode>2_lfiwax"
5144 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5145 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5146 (clobber (match_scratch:DI 2 "=d"))]
5147 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5148 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5149 "#"
5150 ""
5151 [(pc)]
5152 "
5153 {
5154 rtx dest = operands[0];
5155 rtx src = operands[1];
5156 rtx tmp;
5157
5158 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5159 tmp = convert_to_mode (DImode, src, false);
5160 else
5161 {
5162 tmp = operands[2];
5163 if (GET_CODE (tmp) == SCRATCH)
5164 tmp = gen_reg_rtx (DImode);
5165 if (MEM_P (src))
5166 {
5167 src = rs6000_address_for_fpconvert (src);
5168 emit_insn (gen_lfiwax (tmp, src));
5169 }
5170 else
5171 {
5172 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5173 emit_move_insn (stack, src);
5174 emit_insn (gen_lfiwax (tmp, stack));
5175 }
5176 }
5177 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5178 DONE;
5179 }"
5180 [(set_attr "length" "12")
5181 (set_attr "type" "fpload")])
5182
5183 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5184 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5185 (float:SFDF
5186 (sign_extend:DI
5187 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5188 (clobber (match_scratch:DI 2 "=0,d"))]
5189 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5190 && <SI_CONVERT_FP>"
5191 "#"
5192 ""
5193 [(pc)]
5194 "
5195 {
5196 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5197 if (GET_CODE (operands[2]) == SCRATCH)
5198 operands[2] = gen_reg_rtx (DImode);
5199 emit_insn (gen_lfiwax (operands[2], operands[1]));
5200 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5201 DONE;
5202 }"
5203 [(set_attr "length" "8")
5204 (set_attr "type" "fpload")])
5205
5206 (define_insn "lfiwzx"
5207 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5208 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5209 UNSPEC_LFIWZX))]
5210 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5211 "lfiwzx %0,%y1"
5212 [(set_attr "type" "fpload")])
5213
5214 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5215 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5216 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5217 (clobber (match_scratch:DI 2 "=d"))]
5218 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5219 && <SI_CONVERT_FP>"
5220 "#"
5221 ""
5222 [(pc)]
5223 "
5224 {
5225 rtx dest = operands[0];
5226 rtx src = operands[1];
5227 rtx tmp;
5228
5229 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5230 tmp = convert_to_mode (DImode, src, true);
5231 else
5232 {
5233 tmp = operands[2];
5234 if (GET_CODE (tmp) == SCRATCH)
5235 tmp = gen_reg_rtx (DImode);
5236 if (MEM_P (src))
5237 {
5238 src = rs6000_address_for_fpconvert (src);
5239 emit_insn (gen_lfiwzx (tmp, src));
5240 }
5241 else
5242 {
5243 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5244 emit_move_insn (stack, src);
5245 emit_insn (gen_lfiwzx (tmp, stack));
5246 }
5247 }
5248 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5249 DONE;
5250 }"
5251 [(set_attr "length" "12")
5252 (set_attr "type" "fpload")])
5253
5254 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5255 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5256 (unsigned_float:SFDF
5257 (zero_extend:DI
5258 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5259 (clobber (match_scratch:DI 2 "=0,d"))]
5260 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5261 && <SI_CONVERT_FP>"
5262 "#"
5263 ""
5264 [(pc)]
5265 "
5266 {
5267 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5268 if (GET_CODE (operands[2]) == SCRATCH)
5269 operands[2] = gen_reg_rtx (DImode);
5270 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5271 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5272 DONE;
5273 }"
5274 [(set_attr "length" "8")
5275 (set_attr "type" "fpload")])
5276
5277 ; For each of these conversions, there is a define_expand, a define_insn
5278 ; with a '#' template, and a define_split (with C code). The idea is
5279 ; to allow constant folding with the template of the define_insn,
5280 ; then to have the insns split later (between sched1 and final).
5281
5282 (define_expand "floatsidf2"
5283 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5284 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5285 (use (match_dup 2))
5286 (use (match_dup 3))
5287 (clobber (match_dup 4))
5288 (clobber (match_dup 5))
5289 (clobber (match_dup 6))])]
5290 "TARGET_HARD_FLOAT
5291 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5292 "
5293 {
5294 if (TARGET_E500_DOUBLE)
5295 {
5296 if (!REG_P (operands[1]))
5297 operands[1] = force_reg (SImode, operands[1]);
5298 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5299 DONE;
5300 }
5301 else if (TARGET_LFIWAX && TARGET_FCFID)
5302 {
5303 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5304 DONE;
5305 }
5306 else if (TARGET_FCFID)
5307 {
5308 rtx dreg = operands[1];
5309 if (!REG_P (dreg))
5310 dreg = force_reg (SImode, dreg);
5311 dreg = convert_to_mode (DImode, dreg, false);
5312 emit_insn (gen_floatdidf2 (operands[0], dreg));
5313 DONE;
5314 }
5315
5316 if (!REG_P (operands[1]))
5317 operands[1] = force_reg (SImode, operands[1]);
5318 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5319 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5320 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5321 operands[5] = gen_reg_rtx (DFmode);
5322 operands[6] = gen_reg_rtx (SImode);
5323 }")
5324
5325 (define_insn_and_split "*floatsidf2_internal"
5326 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5327 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5328 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5329 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5330 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5331 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5332 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5333 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5334 "#"
5335 ""
5336 [(pc)]
5337 "
5338 {
5339 rtx lowword, highword;
5340 gcc_assert (MEM_P (operands[4]));
5341 highword = adjust_address (operands[4], SImode, 0);
5342 lowword = adjust_address (operands[4], SImode, 4);
5343 if (! WORDS_BIG_ENDIAN)
5344 {
5345 rtx tmp;
5346 tmp = highword; highword = lowword; lowword = tmp;
5347 }
5348
5349 emit_insn (gen_xorsi3 (operands[6], operands[1],
5350 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5351 emit_move_insn (lowword, operands[6]);
5352 emit_move_insn (highword, operands[2]);
5353 emit_move_insn (operands[5], operands[4]);
5354 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5355 DONE;
5356 }"
5357 [(set_attr "length" "24")
5358 (set_attr "type" "fp")])
5359
5360 ;; If we don't have a direct conversion to single precision, don't enable this
5361 ;; conversion for 32-bit without fast math, because we don't have the insn to
5362 ;; generate the fixup swizzle to avoid double rounding problems.
5363 (define_expand "floatunssisf2"
5364 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5365 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5366 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5367 && (!TARGET_FPRS
5368 || (TARGET_FPRS
5369 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5370 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5371 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5372 "
5373 {
5374 if (!TARGET_FPRS)
5375 {
5376 if (!REG_P (operands[1]))
5377 operands[1] = force_reg (SImode, operands[1]);
5378 }
5379 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5380 {
5381 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5382 DONE;
5383 }
5384 else
5385 {
5386 rtx dreg = operands[1];
5387 if (!REG_P (dreg))
5388 dreg = force_reg (SImode, dreg);
5389 dreg = convert_to_mode (DImode, dreg, true);
5390 emit_insn (gen_floatdisf2 (operands[0], dreg));
5391 DONE;
5392 }
5393 }")
5394
5395 (define_expand "floatunssidf2"
5396 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5397 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5398 (use (match_dup 2))
5399 (use (match_dup 3))
5400 (clobber (match_dup 4))
5401 (clobber (match_dup 5))])]
5402 "TARGET_HARD_FLOAT
5403 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5404 "
5405 {
5406 if (TARGET_E500_DOUBLE)
5407 {
5408 if (!REG_P (operands[1]))
5409 operands[1] = force_reg (SImode, operands[1]);
5410 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5411 DONE;
5412 }
5413 else if (TARGET_LFIWZX && TARGET_FCFID)
5414 {
5415 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5416 DONE;
5417 }
5418 else if (TARGET_FCFID)
5419 {
5420 rtx dreg = operands[1];
5421 if (!REG_P (dreg))
5422 dreg = force_reg (SImode, dreg);
5423 dreg = convert_to_mode (DImode, dreg, true);
5424 emit_insn (gen_floatdidf2 (operands[0], dreg));
5425 DONE;
5426 }
5427
5428 if (!REG_P (operands[1]))
5429 operands[1] = force_reg (SImode, operands[1]);
5430 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5431 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5432 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5433 operands[5] = gen_reg_rtx (DFmode);
5434 }")
5435
5436 (define_insn_and_split "*floatunssidf2_internal"
5437 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5438 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5439 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5440 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5441 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5442 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5443 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5444 && !(TARGET_FCFID && TARGET_POWERPC64)"
5445 "#"
5446 ""
5447 [(pc)]
5448 "
5449 {
5450 rtx lowword, highword;
5451 gcc_assert (MEM_P (operands[4]));
5452 highword = adjust_address (operands[4], SImode, 0);
5453 lowword = adjust_address (operands[4], SImode, 4);
5454 if (! WORDS_BIG_ENDIAN)
5455 {
5456 rtx tmp;
5457 tmp = highword; highword = lowword; lowword = tmp;
5458 }
5459
5460 emit_move_insn (lowword, operands[1]);
5461 emit_move_insn (highword, operands[2]);
5462 emit_move_insn (operands[5], operands[4]);
5463 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5464 DONE;
5465 }"
5466 [(set_attr "length" "20")
5467 (set_attr "type" "fp")])
5468
5469 (define_expand "fix_trunc<mode>si2"
5470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5471 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5472 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5473 "
5474 {
5475 if (!<E500_CONVERT>)
5476 {
5477 rtx tmp, stack;
5478
5479 if (TARGET_STFIWX)
5480 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5481 else
5482 {
5483 tmp = gen_reg_rtx (DImode);
5484 stack = rs6000_allocate_stack_temp (DImode, true, false);
5485 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5486 tmp, stack));
5487 }
5488 DONE;
5489 }
5490 }")
5491
5492 ; Like the convert to float patterns, this insn must be split before
5493 ; register allocation so that it can allocate the memory slot if it
5494 ; needed
5495 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5496 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5497 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5498 (clobber (match_scratch:DI 2 "=d"))]
5499 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5500 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5501 && TARGET_STFIWX && can_create_pseudo_p ()"
5502 "#"
5503 ""
5504 [(pc)]
5505 {
5506 rtx dest = operands[0];
5507 rtx src = operands[1];
5508 rtx tmp = operands[2];
5509
5510 if (GET_CODE (tmp) == SCRATCH)
5511 tmp = gen_reg_rtx (DImode);
5512
5513 emit_insn (gen_fctiwz_<mode> (tmp, src));
5514 if (MEM_P (dest))
5515 {
5516 dest = rs6000_address_for_fpconvert (dest);
5517 emit_insn (gen_stfiwx (dest, tmp));
5518 DONE;
5519 }
5520 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5521 {
5522 dest = gen_lowpart (DImode, dest);
5523 emit_move_insn (dest, tmp);
5524 DONE;
5525 }
5526 else
5527 {
5528 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5529 emit_insn (gen_stfiwx (stack, tmp));
5530 emit_move_insn (dest, stack);
5531 DONE;
5532 }
5533 }
5534 [(set_attr "length" "12")
5535 (set_attr "type" "fp")])
5536
5537 (define_insn_and_split "fix_trunc<mode>si2_internal"
5538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5539 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5540 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5541 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5543 "#"
5544 ""
5545 [(pc)]
5546 "
5547 {
5548 rtx lowword;
5549 gcc_assert (MEM_P (operands[3]));
5550 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5551
5552 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5553 emit_move_insn (operands[3], operands[2]);
5554 emit_move_insn (operands[0], lowword);
5555 DONE;
5556 }"
5557 [(set_attr "length" "16")
5558 (set_attr "type" "fp")])
5559
5560 (define_expand "fix_trunc<mode>di2"
5561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5562 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5563 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5564 && TARGET_FCFID"
5565 "")
5566
5567 (define_insn "*fix_trunc<mode>di2_fctidz"
5568 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5569 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5570 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5571 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5572 "fctidz %0,%1"
5573 [(set_attr "type" "fp")])
5574
5575 (define_expand "fixuns_trunc<mode>si2"
5576 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5577 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5578 "TARGET_HARD_FLOAT
5579 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5580 || <E500_CONVERT>)"
5581 "
5582 {
5583 if (!<E500_CONVERT>)
5584 {
5585 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5586 DONE;
5587 }
5588 }")
5589
5590 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5591 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5592 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5593 (clobber (match_scratch:DI 2 "=d"))]
5594 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5595 && TARGET_STFIWX && can_create_pseudo_p ()"
5596 "#"
5597 ""
5598 [(pc)]
5599 {
5600 rtx dest = operands[0];
5601 rtx src = operands[1];
5602 rtx tmp = operands[2];
5603
5604 if (GET_CODE (tmp) == SCRATCH)
5605 tmp = gen_reg_rtx (DImode);
5606
5607 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5608 if (MEM_P (dest))
5609 {
5610 dest = rs6000_address_for_fpconvert (dest);
5611 emit_insn (gen_stfiwx (dest, tmp));
5612 DONE;
5613 }
5614 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5615 {
5616 dest = gen_lowpart (DImode, dest);
5617 emit_move_insn (dest, tmp);
5618 DONE;
5619 }
5620 else
5621 {
5622 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5623 emit_insn (gen_stfiwx (stack, tmp));
5624 emit_move_insn (dest, stack);
5625 DONE;
5626 }
5627 }
5628 [(set_attr "length" "12")
5629 (set_attr "type" "fp")])
5630
5631 (define_expand "fixuns_trunc<mode>di2"
5632 [(set (match_operand:DI 0 "register_operand" "")
5633 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5634 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5635 "")
5636
5637 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5638 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5639 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5640 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5641 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5642 "fctiduz %0,%1"
5643 [(set_attr "type" "fp")])
5644
5645 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5646 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5647 ; because the first makes it clear that operand 0 is not live
5648 ; before the instruction.
5649 (define_insn "fctiwz_<mode>"
5650 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5651 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5652 UNSPEC_FCTIWZ))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5654 "fctiwz %0,%1"
5655 [(set_attr "type" "fp")])
5656
5657 (define_insn "fctiwuz_<mode>"
5658 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5659 (unspec:DI [(unsigned_fix:SI
5660 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5661 UNSPEC_FCTIWUZ))]
5662 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5663 "fctiwuz %0,%1"
5664 [(set_attr "type" "fp")])
5665
5666 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5667 ;; since the friz instruction does not truncate the value if the floating
5668 ;; point value is < LONG_MIN or > LONG_MAX.
5669 (define_insn "*friz"
5670 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5671 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5672 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5673 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5674 && !flag_trapping_math && TARGET_FRIZ"
5675 "friz %0,%1"
5676 [(set_attr "type" "fp")])
5677
5678 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5679 ;; load to properly sign extend the value, but at least doing a store, load
5680 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5681 ;; if we have 32-bit memory ops
5682 (define_insn_and_split "*round32<mode>2_fprs"
5683 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5684 (float:SFDF
5685 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5686 (clobber (match_scratch:DI 2 "=d"))
5687 (clobber (match_scratch:DI 3 "=d"))]
5688 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5689 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5690 && can_create_pseudo_p ()"
5691 "#"
5692 ""
5693 [(pc)]
5694 {
5695 rtx dest = operands[0];
5696 rtx src = operands[1];
5697 rtx tmp1 = operands[2];
5698 rtx tmp2 = operands[3];
5699 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5700
5701 if (GET_CODE (tmp1) == SCRATCH)
5702 tmp1 = gen_reg_rtx (DImode);
5703 if (GET_CODE (tmp2) == SCRATCH)
5704 tmp2 = gen_reg_rtx (DImode);
5705
5706 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5707 emit_insn (gen_stfiwx (stack, tmp1));
5708 emit_insn (gen_lfiwax (tmp2, stack));
5709 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5710 DONE;
5711 }
5712 [(set_attr "type" "fpload")
5713 (set_attr "length" "16")])
5714
5715 (define_insn_and_split "*roundu32<mode>2_fprs"
5716 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5717 (unsigned_float:SFDF
5718 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5719 (clobber (match_scratch:DI 2 "=d"))
5720 (clobber (match_scratch:DI 3 "=d"))]
5721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5722 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5723 && can_create_pseudo_p ()"
5724 "#"
5725 ""
5726 [(pc)]
5727 {
5728 rtx dest = operands[0];
5729 rtx src = operands[1];
5730 rtx tmp1 = operands[2];
5731 rtx tmp2 = operands[3];
5732 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5733
5734 if (GET_CODE (tmp1) == SCRATCH)
5735 tmp1 = gen_reg_rtx (DImode);
5736 if (GET_CODE (tmp2) == SCRATCH)
5737 tmp2 = gen_reg_rtx (DImode);
5738
5739 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5740 emit_insn (gen_stfiwx (stack, tmp1));
5741 emit_insn (gen_lfiwzx (tmp2, stack));
5742 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5743 DONE;
5744 }
5745 [(set_attr "type" "fpload")
5746 (set_attr "length" "16")])
5747
5748 ;; No VSX equivalent to fctid
5749 (define_insn "lrint<mode>di2"
5750 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5751 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5752 UNSPEC_FCTID))]
5753 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5754 "fctid %0,%1"
5755 [(set_attr "type" "fp")])
5756
5757 (define_expand "btrunc<mode>2"
5758 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5759 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5760 UNSPEC_FRIZ))]
5761 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5762 "")
5763
5764 (define_insn "*btrunc<mode>2_fpr"
5765 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5766 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5767 UNSPEC_FRIZ))]
5768 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5769 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5770 "friz %0,%1"
5771 [(set_attr "type" "fp")])
5772
5773 (define_expand "ceil<mode>2"
5774 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5775 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5776 UNSPEC_FRIP))]
5777 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5778 "")
5779
5780 (define_insn "*ceil<mode>2_fpr"
5781 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5782 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5783 UNSPEC_FRIP))]
5784 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5785 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5786 "frip %0,%1"
5787 [(set_attr "type" "fp")])
5788
5789 (define_expand "floor<mode>2"
5790 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5791 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5792 UNSPEC_FRIM))]
5793 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5794 "")
5795
5796 (define_insn "*floor<mode>2_fpr"
5797 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5798 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5799 UNSPEC_FRIM))]
5800 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5801 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5802 "frim %0,%1"
5803 [(set_attr "type" "fp")])
5804
5805 ;; No VSX equivalent to frin
5806 (define_insn "round<mode>2"
5807 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5808 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5809 UNSPEC_FRIN))]
5810 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5811 "frin %0,%1"
5812 [(set_attr "type" "fp")])
5813
5814 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5815 (define_insn "stfiwx"
5816 [(set (match_operand:SI 0 "memory_operand" "=Z")
5817 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
5818 UNSPEC_STFIWX))]
5819 "TARGET_PPC_GFXOPT"
5820 "stfiwx %1,%y0"
5821 [(set_attr "type" "fpstore")])
5822
5823 ;; If we don't have a direct conversion to single precision, don't enable this
5824 ;; conversion for 32-bit without fast math, because we don't have the insn to
5825 ;; generate the fixup swizzle to avoid double rounding problems.
5826 (define_expand "floatsisf2"
5827 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5828 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5829 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5830 && (!TARGET_FPRS
5831 || (TARGET_FPRS
5832 && ((TARGET_FCFIDS && TARGET_LFIWAX)
5833 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5834 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5835 "
5836 {
5837 if (!TARGET_FPRS)
5838 {
5839 if (!REG_P (operands[1]))
5840 operands[1] = force_reg (SImode, operands[1]);
5841 }
5842 else if (TARGET_FCFIDS && TARGET_LFIWAX)
5843 {
5844 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
5845 DONE;
5846 }
5847 else if (TARGET_FCFID && TARGET_LFIWAX)
5848 {
5849 rtx dfreg = gen_reg_rtx (DFmode);
5850 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
5851 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
5852 DONE;
5853 }
5854 else
5855 {
5856 rtx dreg = operands[1];
5857 if (!REG_P (dreg))
5858 dreg = force_reg (SImode, dreg);
5859 dreg = convert_to_mode (DImode, dreg, false);
5860 emit_insn (gen_floatdisf2 (operands[0], dreg));
5861 DONE;
5862 }
5863 }")
5864
5865 (define_expand "floatdidf2"
5866 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5867 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
5868 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
5869 "")
5870
5871 (define_insn "*floatdidf2_fpr"
5872 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5873 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5874 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5875 && !VECTOR_UNIT_VSX_P (DFmode)"
5876 "fcfid %0,%1"
5877 [(set_attr "type" "fp")])
5878
5879 ; Allow the combiner to merge source memory operands to the conversion so that
5880 ; the optimizer/register allocator doesn't try to load the value too early in a
5881 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
5882 ; hit. We will split after reload to avoid the trip through the GPRs
5883
5884 (define_insn_and_split "*floatdidf2_mem"
5885 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5886 (float:DF (match_operand:DI 1 "memory_operand" "m")))
5887 (clobber (match_scratch:DI 2 "=d"))]
5888 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
5889 "#"
5890 "&& reload_completed"
5891 [(set (match_dup 2) (match_dup 1))
5892 (set (match_dup 0) (float:DF (match_dup 2)))]
5893 ""
5894 [(set_attr "length" "8")
5895 (set_attr "type" "fpload")])
5896
5897 (define_expand "floatunsdidf2"
5898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5899 (unsigned_float:DF
5900 (match_operand:DI 1 "gpc_reg_operand" "")))]
5901 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5902 "")
5903
5904 (define_insn "*floatunsdidf2_fcfidu"
5905 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5906 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5907 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
5908 "fcfidu %0,%1"
5909 [(set_attr "type" "fp")
5910 (set_attr "length" "4")])
5911
5912 (define_insn_and_split "*floatunsdidf2_mem"
5913 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5914 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
5915 (clobber (match_scratch:DI 2 "=d"))]
5916 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5917 "#"
5918 "&& reload_completed"
5919 [(set (match_dup 2) (match_dup 1))
5920 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
5921 ""
5922 [(set_attr "length" "8")
5923 (set_attr "type" "fpload")])
5924
5925 (define_expand "floatdisf2"
5926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5927 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5928 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5929 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
5930 "
5931 {
5932 if (!TARGET_FCFIDS)
5933 {
5934 rtx val = operands[1];
5935 if (!flag_unsafe_math_optimizations)
5936 {
5937 rtx label = gen_label_rtx ();
5938 val = gen_reg_rtx (DImode);
5939 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5940 emit_label (label);
5941 }
5942 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5943 DONE;
5944 }
5945 }")
5946
5947 (define_insn "floatdisf2_fcfids"
5948 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5949 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5950 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5951 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5952 "fcfids %0,%1"
5953 [(set_attr "type" "fp")])
5954
5955 (define_insn_and_split "*floatdisf2_mem"
5956 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5957 (float:SF (match_operand:DI 1 "memory_operand" "m")))
5958 (clobber (match_scratch:DI 2 "=f"))]
5959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5960 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5961 "#"
5962 "&& reload_completed"
5963 [(pc)]
5964 "
5965 {
5966 emit_move_insn (operands[2], operands[1]);
5967 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
5968 DONE;
5969 }"
5970 [(set_attr "length" "8")])
5971
5972 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5973 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5974 ;; from double rounding.
5975 ;; Instead of creating a new cpu type for two FP operations, just use fp
5976 (define_insn_and_split "floatdisf2_internal1"
5977 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5978 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
5979 (clobber (match_scratch:DF 2 "=d"))]
5980 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5981 "#"
5982 "&& reload_completed"
5983 [(set (match_dup 2)
5984 (float:DF (match_dup 1)))
5985 (set (match_dup 0)
5986 (float_truncate:SF (match_dup 2)))]
5987 ""
5988 [(set_attr "length" "8")
5989 (set_attr "type" "fp")])
5990
5991 ;; Twiddles bits to avoid double rounding.
5992 ;; Bits that might be truncated when converting to DFmode are replaced
5993 ;; by a bit that won't be lost at that stage, but is below the SFmode
5994 ;; rounding position.
5995 (define_expand "floatdisf2_internal2"
5996 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5997 (const_int 53)))
5998 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5999 (const_int 2047)))
6000 (clobber (scratch:CC))])
6001 (set (match_dup 3) (plus:DI (match_dup 3)
6002 (const_int 1)))
6003 (set (match_dup 0) (plus:DI (match_dup 0)
6004 (const_int 2047)))
6005 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6006 (const_int 2)))
6007 (set (match_dup 0) (ior:DI (match_dup 0)
6008 (match_dup 1)))
6009 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6010 (const_int -2048)))
6011 (clobber (scratch:CC))])
6012 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6013 (label_ref (match_operand:DI 2 "" ""))
6014 (pc)))
6015 (set (match_dup 0) (match_dup 1))]
6016 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6017 "
6018 {
6019 operands[3] = gen_reg_rtx (DImode);
6020 operands[4] = gen_reg_rtx (CCUNSmode);
6021 }")
6022
6023 (define_expand "floatunsdisf2"
6024 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6025 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6026 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6027 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6028 "")
6029
6030 (define_insn "floatunsdisf2_fcfidus"
6031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6032 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6033 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6034 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6035 "fcfidus %0,%1"
6036 [(set_attr "type" "fp")])
6037
6038 (define_insn_and_split "*floatunsdisf2_mem"
6039 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6040 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6041 (clobber (match_scratch:DI 2 "=f"))]
6042 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6043 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6044 "#"
6045 "&& reload_completed"
6046 [(pc)]
6047 "
6048 {
6049 emit_move_insn (operands[2], operands[1]);
6050 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6051 DONE;
6052 }"
6053 [(set_attr "length" "8")
6054 (set_attr "type" "fpload")])
6055 \f
6056 ;; Define the DImode operations that can be done in a small number
6057 ;; of instructions. The & constraints are to prevent the register
6058 ;; allocator from allocating registers that overlap with the inputs
6059 ;; (for example, having an input in 7,8 and an output in 6,7). We
6060 ;; also allow for the output being the same as one of the inputs.
6061
6062 (define_insn "*adddi3_noppc64"
6063 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6064 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6065 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6066 "! TARGET_POWERPC64"
6067 "*
6068 {
6069 if (WORDS_BIG_ENDIAN)
6070 return (GET_CODE (operands[2])) != CONST_INT
6071 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6072 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6073 else
6074 return (GET_CODE (operands[2])) != CONST_INT
6075 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6076 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6077 }"
6078 [(set_attr "type" "two")
6079 (set_attr "length" "8")])
6080
6081 (define_insn "*subdi3_noppc64"
6082 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6083 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6084 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6085 "! TARGET_POWERPC64"
6086 "*
6087 {
6088 if (WORDS_BIG_ENDIAN)
6089 return (GET_CODE (operands[1]) != CONST_INT)
6090 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6091 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6092 else
6093 return (GET_CODE (operands[1]) != CONST_INT)
6094 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6095 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6096 }"
6097 [(set_attr "type" "two")
6098 (set_attr "length" "8")])
6099
6100 (define_insn "*negdi2_noppc64"
6101 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6102 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6103 "! TARGET_POWERPC64"
6104 "*
6105 {
6106 return (WORDS_BIG_ENDIAN)
6107 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6108 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6109 }"
6110 [(set_attr "type" "two")
6111 (set_attr "length" "8")])
6112
6113 (define_insn "mulsidi3"
6114 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6115 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6116 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6117 "! TARGET_POWERPC64"
6118 {
6119 return (WORDS_BIG_ENDIAN)
6120 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6121 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6122 }
6123 [(set_attr "type" "imul")
6124 (set_attr "length" "8")])
6125
6126 (define_split
6127 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6128 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6129 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6130 "! TARGET_POWERPC64 && reload_completed"
6131 [(set (match_dup 3)
6132 (truncate:SI
6133 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6134 (sign_extend:DI (match_dup 2)))
6135 (const_int 32))))
6136 (set (match_dup 4)
6137 (mult:SI (match_dup 1)
6138 (match_dup 2)))]
6139 "
6140 {
6141 int endian = (WORDS_BIG_ENDIAN == 0);
6142 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6143 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6144 }")
6145
6146 (define_insn "umulsidi3"
6147 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6148 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6149 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6150 "! TARGET_POWERPC64"
6151 "*
6152 {
6153 return (WORDS_BIG_ENDIAN)
6154 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6155 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6156 }"
6157 [(set_attr "type" "imul")
6158 (set_attr "length" "8")])
6159
6160 (define_split
6161 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6162 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6163 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6164 "! TARGET_POWERPC64 && reload_completed"
6165 [(set (match_dup 3)
6166 (truncate:SI
6167 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6168 (zero_extend:DI (match_dup 2)))
6169 (const_int 32))))
6170 (set (match_dup 4)
6171 (mult:SI (match_dup 1)
6172 (match_dup 2)))]
6173 "
6174 {
6175 int endian = (WORDS_BIG_ENDIAN == 0);
6176 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6177 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6178 }")
6179
6180 (define_insn "smulsi3_highpart"
6181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6182 (truncate:SI
6183 (lshiftrt:DI (mult:DI (sign_extend:DI
6184 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6185 (sign_extend:DI
6186 (match_operand:SI 2 "gpc_reg_operand" "r")))
6187 (const_int 32))))]
6188 ""
6189 "mulhw %0,%1,%2"
6190 [(set_attr "type" "imul")])
6191
6192 (define_insn "umulsi3_highpart"
6193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6194 (truncate:SI
6195 (lshiftrt:DI (mult:DI (zero_extend:DI
6196 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6197 (zero_extend:DI
6198 (match_operand:SI 2 "gpc_reg_operand" "r")))
6199 (const_int 32))))]
6200 ""
6201 "mulhwu %0,%1,%2"
6202 [(set_attr "type" "imul")])
6203
6204 ;; Shift by a variable amount is too complex to be worth open-coding. We
6205 ;; just handle shifts by constants.
6206 (define_insn "ashrdi3_no_power"
6207 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6208 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6209 (match_operand:SI 2 "const_int_operand" "M,i")))]
6210 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6211 "@
6212 srawi %0,%1,31\;srawi %L0,%1,%h2
6213 srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2"
6214 [(set_attr "type" "two,three")
6215 (set_attr "length" "8,12")])
6216
6217 (define_insn "*ashrdisi3_noppc64"
6218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6219 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6220 (const_int 32)) 4))]
6221 "TARGET_32BIT && !TARGET_POWERPC64"
6222 "*
6223 {
6224 if (REGNO (operands[0]) == REGNO (operands[1]))
6225 return \"\";
6226 else
6227 return \"mr %0,%1\";
6228 }"
6229 [(set_attr "length" "4")])
6230
6231 \f
6232 ;; PowerPC64 DImode operations.
6233
6234 (define_insn "muldi3"
6235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6236 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6237 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6238 "TARGET_POWERPC64"
6239 "@
6240 mulld %0,%1,%2
6241 mulli %0,%1,%2"
6242 [(set (attr "type")
6243 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6244 (const_string "imul3")
6245 (match_operand:SI 2 "short_cint_operand" "")
6246 (const_string "imul2")]
6247 (const_string "lmul")))])
6248
6249 (define_insn "*muldi3_internal1"
6250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6251 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6252 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6253 (const_int 0)))
6254 (clobber (match_scratch:DI 3 "=r,r"))]
6255 "TARGET_POWERPC64"
6256 "@
6257 mulld. %3,%1,%2
6258 #"
6259 [(set_attr "type" "lmul_compare")
6260 (set_attr "length" "4,8")])
6261
6262 (define_split
6263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6264 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6265 (match_operand:DI 2 "gpc_reg_operand" ""))
6266 (const_int 0)))
6267 (clobber (match_scratch:DI 3 ""))]
6268 "TARGET_POWERPC64 && reload_completed"
6269 [(set (match_dup 3)
6270 (mult:DI (match_dup 1) (match_dup 2)))
6271 (set (match_dup 0)
6272 (compare:CC (match_dup 3)
6273 (const_int 0)))]
6274 "")
6275
6276 (define_insn "*muldi3_internal2"
6277 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6278 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6279 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6280 (const_int 0)))
6281 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6282 (mult:DI (match_dup 1) (match_dup 2)))]
6283 "TARGET_POWERPC64"
6284 "@
6285 mulld. %0,%1,%2
6286 #"
6287 [(set_attr "type" "lmul_compare")
6288 (set_attr "length" "4,8")])
6289
6290 (define_split
6291 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6292 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6293 (match_operand:DI 2 "gpc_reg_operand" ""))
6294 (const_int 0)))
6295 (set (match_operand:DI 0 "gpc_reg_operand" "")
6296 (mult:DI (match_dup 1) (match_dup 2)))]
6297 "TARGET_POWERPC64 && reload_completed"
6298 [(set (match_dup 0)
6299 (mult:DI (match_dup 1) (match_dup 2)))
6300 (set (match_dup 3)
6301 (compare:CC (match_dup 0)
6302 (const_int 0)))]
6303 "")
6304
6305 (define_insn "smuldi3_highpart"
6306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6307 (truncate:DI
6308 (lshiftrt:TI (mult:TI (sign_extend:TI
6309 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6310 (sign_extend:TI
6311 (match_operand:DI 2 "gpc_reg_operand" "r")))
6312 (const_int 64))))]
6313 "TARGET_POWERPC64"
6314 "mulhd %0,%1,%2"
6315 [(set_attr "type" "lmul")])
6316
6317 (define_insn "umuldi3_highpart"
6318 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6319 (truncate:DI
6320 (lshiftrt:TI (mult:TI (zero_extend:TI
6321 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6322 (zero_extend:TI
6323 (match_operand:DI 2 "gpc_reg_operand" "r")))
6324 (const_int 64))))]
6325 "TARGET_POWERPC64"
6326 "mulhdu %0,%1,%2"
6327 [(set_attr "type" "lmul")])
6328
6329 (define_insn "rotldi3"
6330 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6331 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6332 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6333 "TARGET_POWERPC64"
6334 "@
6335 rldcl %0,%1,%2,0
6336 rldicl %0,%1,%H2,0"
6337 [(set_attr "type" "var_shift_rotate,integer")])
6338
6339 (define_insn "*rotldi3_internal2"
6340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6341 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6342 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6343 (const_int 0)))
6344 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6345 "TARGET_64BIT"
6346 "@
6347 rldcl. %3,%1,%2,0
6348 rldicl. %3,%1,%H2,0
6349 #
6350 #"
6351 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6352 (set_attr "length" "4,4,8,8")])
6353
6354 (define_split
6355 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6356 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6357 (match_operand:DI 2 "reg_or_cint_operand" ""))
6358 (const_int 0)))
6359 (clobber (match_scratch:DI 3 ""))]
6360 "TARGET_POWERPC64 && reload_completed"
6361 [(set (match_dup 3)
6362 (rotate:DI (match_dup 1) (match_dup 2)))
6363 (set (match_dup 0)
6364 (compare:CC (match_dup 3)
6365 (const_int 0)))]
6366 "")
6367
6368 (define_insn "*rotldi3_internal3"
6369 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6370 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6371 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6372 (const_int 0)))
6373 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6374 (rotate:DI (match_dup 1) (match_dup 2)))]
6375 "TARGET_64BIT"
6376 "@
6377 rldcl. %0,%1,%2,0
6378 rldicl. %0,%1,%H2,0
6379 #
6380 #"
6381 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6382 (set_attr "length" "4,4,8,8")])
6383
6384 (define_split
6385 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6386 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6387 (match_operand:DI 2 "reg_or_cint_operand" ""))
6388 (const_int 0)))
6389 (set (match_operand:DI 0 "gpc_reg_operand" "")
6390 (rotate:DI (match_dup 1) (match_dup 2)))]
6391 "TARGET_POWERPC64 && reload_completed"
6392 [(set (match_dup 0)
6393 (rotate:DI (match_dup 1) (match_dup 2)))
6394 (set (match_dup 3)
6395 (compare:CC (match_dup 0)
6396 (const_int 0)))]
6397 "")
6398
6399 (define_insn "*rotldi3_internal4"
6400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6401 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6402 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6403 (match_operand:DI 3 "mask64_operand" "n,n")))]
6404 "TARGET_POWERPC64"
6405 "@
6406 rldc%B3 %0,%1,%2,%S3
6407 rldic%B3 %0,%1,%H2,%S3"
6408 [(set_attr "type" "var_shift_rotate,integer")])
6409
6410 (define_insn "*rotldi3_internal5"
6411 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6412 (compare:CC (and:DI
6413 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6414 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6415 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6416 (const_int 0)))
6417 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6418 "TARGET_64BIT"
6419 "@
6420 rldc%B3. %4,%1,%2,%S3
6421 rldic%B3. %4,%1,%H2,%S3
6422 #
6423 #"
6424 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6425 (set_attr "length" "4,4,8,8")])
6426
6427 (define_split
6428 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6429 (compare:CC (and:DI
6430 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6431 (match_operand:DI 2 "reg_or_cint_operand" ""))
6432 (match_operand:DI 3 "mask64_operand" ""))
6433 (const_int 0)))
6434 (clobber (match_scratch:DI 4 ""))]
6435 "TARGET_POWERPC64 && reload_completed"
6436 [(set (match_dup 4)
6437 (and:DI (rotate:DI (match_dup 1)
6438 (match_dup 2))
6439 (match_dup 3)))
6440 (set (match_dup 0)
6441 (compare:CC (match_dup 4)
6442 (const_int 0)))]
6443 "")
6444
6445 (define_insn "*rotldi3_internal6"
6446 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6447 (compare:CC (and:DI
6448 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6449 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6450 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6451 (const_int 0)))
6452 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6453 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6454 "TARGET_64BIT"
6455 "@
6456 rldc%B3. %0,%1,%2,%S3
6457 rldic%B3. %0,%1,%H2,%S3
6458 #
6459 #"
6460 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6461 (set_attr "length" "4,4,8,8")])
6462
6463 (define_split
6464 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6465 (compare:CC (and:DI
6466 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6467 (match_operand:DI 2 "reg_or_cint_operand" ""))
6468 (match_operand:DI 3 "mask64_operand" ""))
6469 (const_int 0)))
6470 (set (match_operand:DI 0 "gpc_reg_operand" "")
6471 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6472 "TARGET_POWERPC64 && reload_completed"
6473 [(set (match_dup 0)
6474 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6475 (set (match_dup 4)
6476 (compare:CC (match_dup 0)
6477 (const_int 0)))]
6478 "")
6479
6480 (define_insn "*rotldi3_internal7"
6481 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6482 (zero_extend:DI
6483 (subreg:QI
6484 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6485 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6486 "TARGET_POWERPC64"
6487 "@
6488 rldcl %0,%1,%2,56
6489 rldicl %0,%1,%H2,56"
6490 [(set_attr "type" "var_shift_rotate,integer")])
6491
6492 (define_insn "*rotldi3_internal8"
6493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6494 (compare:CC (zero_extend:DI
6495 (subreg:QI
6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6497 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6498 (const_int 0)))
6499 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6500 "TARGET_64BIT"
6501 "@
6502 rldcl. %3,%1,%2,56
6503 rldicl. %3,%1,%H2,56
6504 #
6505 #"
6506 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6507 (set_attr "length" "4,4,8,8")])
6508
6509 (define_split
6510 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6511 (compare:CC (zero_extend:DI
6512 (subreg:QI
6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6514 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6515 (const_int 0)))
6516 (clobber (match_scratch:DI 3 ""))]
6517 "TARGET_POWERPC64 && reload_completed"
6518 [(set (match_dup 3)
6519 (zero_extend:DI (subreg:QI
6520 (rotate:DI (match_dup 1)
6521 (match_dup 2)) 0)))
6522 (set (match_dup 0)
6523 (compare:CC (match_dup 3)
6524 (const_int 0)))]
6525 "")
6526
6527 (define_insn "*rotldi3_internal9"
6528 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6529 (compare:CC (zero_extend:DI
6530 (subreg:QI
6531 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6532 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6533 (const_int 0)))
6534 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6535 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6536 "TARGET_64BIT"
6537 "@
6538 rldcl. %0,%1,%2,56
6539 rldicl. %0,%1,%H2,56
6540 #
6541 #"
6542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6543 (set_attr "length" "4,4,8,8")])
6544
6545 (define_split
6546 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6547 (compare:CC (zero_extend:DI
6548 (subreg:QI
6549 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6550 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6551 (const_int 0)))
6552 (set (match_operand:DI 0 "gpc_reg_operand" "")
6553 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6554 "TARGET_POWERPC64 && reload_completed"
6555 [(set (match_dup 0)
6556 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6557 (set (match_dup 3)
6558 (compare:CC (match_dup 0)
6559 (const_int 0)))]
6560 "")
6561
6562 (define_insn "*rotldi3_internal10"
6563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6564 (zero_extend:DI
6565 (subreg:HI
6566 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6567 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6568 "TARGET_POWERPC64"
6569 "@
6570 rldcl %0,%1,%2,48
6571 rldicl %0,%1,%H2,48"
6572 [(set_attr "type" "var_shift_rotate,integer")])
6573
6574 (define_insn "*rotldi3_internal11"
6575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6576 (compare:CC (zero_extend:DI
6577 (subreg:HI
6578 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6579 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6580 (const_int 0)))
6581 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6582 "TARGET_64BIT"
6583 "@
6584 rldcl. %3,%1,%2,48
6585 rldicl. %3,%1,%H2,48
6586 #
6587 #"
6588 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6589 (set_attr "length" "4,4,8,8")])
6590
6591 (define_split
6592 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6593 (compare:CC (zero_extend:DI
6594 (subreg:HI
6595 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6596 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6597 (const_int 0)))
6598 (clobber (match_scratch:DI 3 ""))]
6599 "TARGET_POWERPC64 && reload_completed"
6600 [(set (match_dup 3)
6601 (zero_extend:DI (subreg:HI
6602 (rotate:DI (match_dup 1)
6603 (match_dup 2)) 0)))
6604 (set (match_dup 0)
6605 (compare:CC (match_dup 3)
6606 (const_int 0)))]
6607 "")
6608
6609 (define_insn "*rotldi3_internal12"
6610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6611 (compare:CC (zero_extend:DI
6612 (subreg:HI
6613 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6614 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6615 (const_int 0)))
6616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6617 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6618 "TARGET_64BIT"
6619 "@
6620 rldcl. %0,%1,%2,48
6621 rldicl. %0,%1,%H2,48
6622 #
6623 #"
6624 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6625 (set_attr "length" "4,4,8,8")])
6626
6627 (define_split
6628 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6629 (compare:CC (zero_extend:DI
6630 (subreg:HI
6631 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6632 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6633 (const_int 0)))
6634 (set (match_operand:DI 0 "gpc_reg_operand" "")
6635 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6636 "TARGET_POWERPC64 && reload_completed"
6637 [(set (match_dup 0)
6638 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6639 (set (match_dup 3)
6640 (compare:CC (match_dup 0)
6641 (const_int 0)))]
6642 "")
6643
6644 (define_insn "*rotldi3_internal13"
6645 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6646 (zero_extend:DI
6647 (subreg:SI
6648 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6649 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6650 "TARGET_POWERPC64"
6651 "@
6652 rldcl %0,%1,%2,32
6653 rldicl %0,%1,%H2,32"
6654 [(set_attr "type" "var_shift_rotate,integer")])
6655
6656 (define_insn "*rotldi3_internal14"
6657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6658 (compare:CC (zero_extend:DI
6659 (subreg:SI
6660 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6661 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6662 (const_int 0)))
6663 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6664 "TARGET_64BIT"
6665 "@
6666 rldcl. %3,%1,%2,32
6667 rldicl. %3,%1,%H2,32
6668 #
6669 #"
6670 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6671 (set_attr "length" "4,4,8,8")])
6672
6673 (define_split
6674 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6675 (compare:CC (zero_extend:DI
6676 (subreg:SI
6677 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6678 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6679 (const_int 0)))
6680 (clobber (match_scratch:DI 3 ""))]
6681 "TARGET_POWERPC64 && reload_completed"
6682 [(set (match_dup 3)
6683 (zero_extend:DI (subreg:SI
6684 (rotate:DI (match_dup 1)
6685 (match_dup 2)) 0)))
6686 (set (match_dup 0)
6687 (compare:CC (match_dup 3)
6688 (const_int 0)))]
6689 "")
6690
6691 (define_insn "*rotldi3_internal15"
6692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6693 (compare:CC (zero_extend:DI
6694 (subreg:SI
6695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6696 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6697 (const_int 0)))
6698 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6699 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6700 "TARGET_64BIT"
6701 "@
6702 rldcl. %0,%1,%2,32
6703 rldicl. %0,%1,%H2,32
6704 #
6705 #"
6706 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6707 (set_attr "length" "4,4,8,8")])
6708
6709 (define_split
6710 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6711 (compare:CC (zero_extend:DI
6712 (subreg:SI
6713 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6714 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6715 (const_int 0)))
6716 (set (match_operand:DI 0 "gpc_reg_operand" "")
6717 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6718 "TARGET_POWERPC64 && reload_completed"
6719 [(set (match_dup 0)
6720 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6721 (set (match_dup 3)
6722 (compare:CC (match_dup 0)
6723 (const_int 0)))]
6724 "")
6725
6726 (define_expand "ashldi3"
6727 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6728 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6729 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6730 "TARGET_POWERPC64"
6731 "")
6732
6733 (define_insn "*ashldi3_internal1"
6734 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6735 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6736 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6737 "TARGET_POWERPC64"
6738 "@
6739 sld %0,%1,%2
6740 sldi %0,%1,%H2"
6741 [(set_attr "type" "var_shift_rotate,shift")])
6742
6743 (define_insn "*ashldi3_internal2"
6744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6745 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6746 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6747 (const_int 0)))
6748 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6749 "TARGET_64BIT"
6750 "@
6751 sld. %3,%1,%2
6752 sldi. %3,%1,%H2
6753 #
6754 #"
6755 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6756 (set_attr "length" "4,4,8,8")])
6757
6758 (define_split
6759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6760 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6761 (match_operand:SI 2 "reg_or_cint_operand" ""))
6762 (const_int 0)))
6763 (clobber (match_scratch:DI 3 ""))]
6764 "TARGET_POWERPC64 && reload_completed"
6765 [(set (match_dup 3)
6766 (ashift:DI (match_dup 1) (match_dup 2)))
6767 (set (match_dup 0)
6768 (compare:CC (match_dup 3)
6769 (const_int 0)))]
6770 "")
6771
6772 (define_insn "*ashldi3_internal3"
6773 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6774 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6775 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6776 (const_int 0)))
6777 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6778 (ashift:DI (match_dup 1) (match_dup 2)))]
6779 "TARGET_64BIT"
6780 "@
6781 sld. %0,%1,%2
6782 sldi. %0,%1,%H2
6783 #
6784 #"
6785 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6786 (set_attr "length" "4,4,8,8")])
6787
6788 (define_split
6789 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6790 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6791 (match_operand:SI 2 "reg_or_cint_operand" ""))
6792 (const_int 0)))
6793 (set (match_operand:DI 0 "gpc_reg_operand" "")
6794 (ashift:DI (match_dup 1) (match_dup 2)))]
6795 "TARGET_POWERPC64 && reload_completed"
6796 [(set (match_dup 0)
6797 (ashift:DI (match_dup 1) (match_dup 2)))
6798 (set (match_dup 3)
6799 (compare:CC (match_dup 0)
6800 (const_int 0)))]
6801 "")
6802
6803 (define_insn "*ashldi3_internal4"
6804 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6805 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6806 (match_operand:SI 2 "const_int_operand" "i"))
6807 (match_operand:DI 3 "const_int_operand" "n")))]
6808 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6809 "rldic %0,%1,%H2,%W3")
6810
6811 (define_insn "ashldi3_internal5"
6812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6813 (compare:CC
6814 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6815 (match_operand:SI 2 "const_int_operand" "i,i"))
6816 (match_operand:DI 3 "const_int_operand" "n,n"))
6817 (const_int 0)))
6818 (clobber (match_scratch:DI 4 "=r,r"))]
6819 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6820 "@
6821 rldic. %4,%1,%H2,%W3
6822 #"
6823 [(set_attr "type" "compare")
6824 (set_attr "length" "4,8")])
6825
6826 (define_split
6827 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6828 (compare:CC
6829 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6830 (match_operand:SI 2 "const_int_operand" ""))
6831 (match_operand:DI 3 "const_int_operand" ""))
6832 (const_int 0)))
6833 (clobber (match_scratch:DI 4 ""))]
6834 "TARGET_POWERPC64 && reload_completed
6835 && includes_rldic_lshift_p (operands[2], operands[3])"
6836 [(set (match_dup 4)
6837 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6838 (match_dup 3)))
6839 (set (match_dup 0)
6840 (compare:CC (match_dup 4)
6841 (const_int 0)))]
6842 "")
6843
6844 (define_insn "*ashldi3_internal6"
6845 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6846 (compare:CC
6847 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6848 (match_operand:SI 2 "const_int_operand" "i,i"))
6849 (match_operand:DI 3 "const_int_operand" "n,n"))
6850 (const_int 0)))
6851 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6852 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6853 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6854 "@
6855 rldic. %0,%1,%H2,%W3
6856 #"
6857 [(set_attr "type" "compare")
6858 (set_attr "length" "4,8")])
6859
6860 (define_split
6861 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6862 (compare:CC
6863 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:SI 2 "const_int_operand" ""))
6865 (match_operand:DI 3 "const_int_operand" ""))
6866 (const_int 0)))
6867 (set (match_operand:DI 0 "gpc_reg_operand" "")
6868 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6869 "TARGET_POWERPC64 && reload_completed
6870 && includes_rldic_lshift_p (operands[2], operands[3])"
6871 [(set (match_dup 0)
6872 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6873 (match_dup 3)))
6874 (set (match_dup 4)
6875 (compare:CC (match_dup 0)
6876 (const_int 0)))]
6877 "")
6878
6879 (define_insn "*ashldi3_internal7"
6880 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6881 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6882 (match_operand:SI 2 "const_int_operand" "i"))
6883 (match_operand:DI 3 "mask64_operand" "n")))]
6884 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6885 "rldicr %0,%1,%H2,%S3")
6886
6887 (define_insn "ashldi3_internal8"
6888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6889 (compare:CC
6890 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6891 (match_operand:SI 2 "const_int_operand" "i,i"))
6892 (match_operand:DI 3 "mask64_operand" "n,n"))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 4 "=r,r"))]
6895 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6896 "@
6897 rldicr. %4,%1,%H2,%S3
6898 #"
6899 [(set_attr "type" "compare")
6900 (set_attr "length" "4,8")])
6901
6902 (define_split
6903 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6904 (compare:CC
6905 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6906 (match_operand:SI 2 "const_int_operand" ""))
6907 (match_operand:DI 3 "mask64_operand" ""))
6908 (const_int 0)))
6909 (clobber (match_scratch:DI 4 ""))]
6910 "TARGET_POWERPC64 && reload_completed
6911 && includes_rldicr_lshift_p (operands[2], operands[3])"
6912 [(set (match_dup 4)
6913 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6914 (match_dup 3)))
6915 (set (match_dup 0)
6916 (compare:CC (match_dup 4)
6917 (const_int 0)))]
6918 "")
6919
6920 (define_insn "*ashldi3_internal9"
6921 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6922 (compare:CC
6923 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6924 (match_operand:SI 2 "const_int_operand" "i,i"))
6925 (match_operand:DI 3 "mask64_operand" "n,n"))
6926 (const_int 0)))
6927 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6928 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6929 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6930 "@
6931 rldicr. %0,%1,%H2,%S3
6932 #"
6933 [(set_attr "type" "compare")
6934 (set_attr "length" "4,8")])
6935
6936 (define_split
6937 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6938 (compare:CC
6939 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6940 (match_operand:SI 2 "const_int_operand" ""))
6941 (match_operand:DI 3 "mask64_operand" ""))
6942 (const_int 0)))
6943 (set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6945 "TARGET_POWERPC64 && reload_completed
6946 && includes_rldicr_lshift_p (operands[2], operands[3])"
6947 [(set (match_dup 0)
6948 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6949 (match_dup 3)))
6950 (set (match_dup 4)
6951 (compare:CC (match_dup 0)
6952 (const_int 0)))]
6953 "")
6954
6955 (define_expand "lshrdi3"
6956 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6957 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6958 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6959 "TARGET_POWERPC64"
6960 "")
6961
6962 (define_insn "*lshrdi3_internal1"
6963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6964 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6965 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6966 "TARGET_POWERPC64"
6967 "@
6968 srd %0,%1,%2
6969 srdi %0,%1,%H2"
6970 [(set_attr "type" "var_shift_rotate,shift")])
6971
6972 (define_insn "*lshrdi3_internal2"
6973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6974 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6975 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6976 (const_int 0)))
6977 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6978 "TARGET_64BIT "
6979 "@
6980 srd. %3,%1,%2
6981 srdi. %3,%1,%H2
6982 #
6983 #"
6984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6985 (set_attr "length" "4,4,8,8")])
6986
6987 (define_split
6988 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6989 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6990 (match_operand:SI 2 "reg_or_cint_operand" ""))
6991 (const_int 0)))
6992 (clobber (match_scratch:DI 3 ""))]
6993 "TARGET_POWERPC64 && reload_completed"
6994 [(set (match_dup 3)
6995 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6996 (set (match_dup 0)
6997 (compare:CC (match_dup 3)
6998 (const_int 0)))]
6999 "")
7000
7001 (define_insn "*lshrdi3_internal3"
7002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7003 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7004 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7005 (const_int 0)))
7006 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7007 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7008 "TARGET_64BIT"
7009 "@
7010 srd. %0,%1,%2
7011 srdi. %0,%1,%H2
7012 #
7013 #"
7014 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7015 (set_attr "length" "4,4,8,8")])
7016
7017 (define_split
7018 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7019 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:SI 2 "reg_or_cint_operand" ""))
7021 (const_int 0)))
7022 (set (match_operand:DI 0 "gpc_reg_operand" "")
7023 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7024 "TARGET_POWERPC64 && reload_completed"
7025 [(set (match_dup 0)
7026 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7027 (set (match_dup 3)
7028 (compare:CC (match_dup 0)
7029 (const_int 0)))]
7030 "")
7031
7032 (define_expand "ashrdi3"
7033 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7034 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7035 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7036 "WORDS_BIG_ENDIAN"
7037 "
7038 {
7039 if (TARGET_POWERPC64)
7040 ;
7041 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7042 && WORDS_BIG_ENDIAN)
7043 {
7044 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7045 DONE;
7046 }
7047 else
7048 FAIL;
7049 }")
7050
7051 (define_insn "*ashrdi3_internal1"
7052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7053 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7054 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7055 "TARGET_POWERPC64"
7056 "@
7057 srad %0,%1,%2
7058 sradi %0,%1,%H2"
7059 [(set_attr "type" "var_shift_rotate,shift")])
7060
7061 (define_insn "*ashrdi3_internal2"
7062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7063 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7064 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7065 (const_int 0)))
7066 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7067 "TARGET_64BIT"
7068 "@
7069 srad. %3,%1,%2
7070 sradi. %3,%1,%H2
7071 #
7072 #"
7073 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7074 (set_attr "length" "4,4,8,8")])
7075
7076 (define_split
7077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7078 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7079 (match_operand:SI 2 "reg_or_cint_operand" ""))
7080 (const_int 0)))
7081 (clobber (match_scratch:DI 3 ""))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 3)
7084 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7085 (set (match_dup 0)
7086 (compare:CC (match_dup 3)
7087 (const_int 0)))]
7088 "")
7089
7090 (define_insn "*ashrdi3_internal3"
7091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7092 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7093 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7094 (const_int 0)))
7095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7096 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7097 "TARGET_64BIT"
7098 "@
7099 srad. %0,%1,%2
7100 sradi. %0,%1,%H2
7101 #
7102 #"
7103 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7104 (set_attr "length" "4,4,8,8")])
7105
7106 (define_split
7107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7108 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7109 (match_operand:SI 2 "reg_or_cint_operand" ""))
7110 (const_int 0)))
7111 (set (match_operand:DI 0 "gpc_reg_operand" "")
7112 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7113 "TARGET_POWERPC64 && reload_completed"
7114 [(set (match_dup 0)
7115 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7116 (set (match_dup 3)
7117 (compare:CC (match_dup 0)
7118 (const_int 0)))]
7119 "")
7120
7121 (define_expand "anddi3"
7122 [(parallel
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7124 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7125 (match_operand:DI 2 "and64_2_operand" "")))
7126 (clobber (match_scratch:CC 3 ""))])]
7127 "TARGET_POWERPC64"
7128 "")
7129
7130 (define_insn "anddi3_mc"
7131 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7132 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7133 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7134 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7135 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7136 "@
7137 and %0,%1,%2
7138 rldic%B2 %0,%1,0,%S2
7139 rlwinm %0,%1,0,%m2,%M2
7140 andi. %0,%1,%b2
7141 andis. %0,%1,%u2
7142 #"
7143 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7144 (set_attr "length" "4,4,4,4,4,8")])
7145
7146 (define_insn "anddi3_nomc"
7147 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7148 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7149 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7150 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7151 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7152 "@
7153 and %0,%1,%2
7154 rldic%B2 %0,%1,0,%S2
7155 rlwinm %0,%1,0,%m2,%M2
7156 #"
7157 [(set_attr "length" "4,4,4,8")])
7158
7159 (define_split
7160 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7161 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7162 (match_operand:DI 2 "mask64_2_operand" "")))
7163 (clobber (match_scratch:CC 3 ""))]
7164 "TARGET_POWERPC64
7165 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7166 && !mask_operand (operands[2], DImode)
7167 && !mask64_operand (operands[2], DImode)"
7168 [(set (match_dup 0)
7169 (and:DI (rotate:DI (match_dup 1)
7170 (match_dup 4))
7171 (match_dup 5)))
7172 (set (match_dup 0)
7173 (and:DI (rotate:DI (match_dup 0)
7174 (match_dup 6))
7175 (match_dup 7)))]
7176 {
7177 build_mask64_2_operands (operands[2], &operands[4]);
7178 })
7179
7180 (define_insn "*anddi3_internal2_mc"
7181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7182 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7183 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7184 (const_int 0)))
7185 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7186 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7187 "TARGET_64BIT && rs6000_gen_cell_microcode"
7188 "@
7189 and. %3,%1,%2
7190 rldic%B2. %3,%1,0,%S2
7191 rlwinm. %3,%1,0,%m2,%M2
7192 andi. %3,%1,%b2
7193 andis. %3,%1,%u2
7194 #
7195 #
7196 #
7197 #
7198 #
7199 #
7200 #"
7201 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7202 fast_compare,compare,compare,compare,compare,compare,\
7203 compare,compare")
7204 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7205
7206 (define_split
7207 [(set (match_operand:CC 0 "cc_reg_operand" "")
7208 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7209 (match_operand:DI 2 "mask64_2_operand" ""))
7210 (const_int 0)))
7211 (clobber (match_scratch:DI 3 ""))
7212 (clobber (match_scratch:CC 4 ""))]
7213 "TARGET_64BIT && reload_completed
7214 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7215 && !mask_operand (operands[2], DImode)
7216 && !mask64_operand (operands[2], DImode)"
7217 [(set (match_dup 3)
7218 (and:DI (rotate:DI (match_dup 1)
7219 (match_dup 5))
7220 (match_dup 6)))
7221 (parallel [(set (match_dup 0)
7222 (compare:CC (and:DI (rotate:DI (match_dup 3)
7223 (match_dup 7))
7224 (match_dup 8))
7225 (const_int 0)))
7226 (clobber (match_dup 3))])]
7227 "
7228 {
7229 build_mask64_2_operands (operands[2], &operands[5]);
7230 }")
7231
7232 (define_insn "*anddi3_internal3_mc"
7233 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7234 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7235 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7236 (const_int 0)))
7237 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7238 (and:DI (match_dup 1) (match_dup 2)))
7239 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7240 "TARGET_64BIT && rs6000_gen_cell_microcode"
7241 "@
7242 and. %0,%1,%2
7243 rldic%B2. %0,%1,0,%S2
7244 rlwinm. %0,%1,0,%m2,%M2
7245 andi. %0,%1,%b2
7246 andis. %0,%1,%u2
7247 #
7248 #
7249 #
7250 #
7251 #
7252 #
7253 #"
7254 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7255 fast_compare,compare,compare,compare,compare,compare,\
7256 compare,compare")
7257 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7258
7259 (define_split
7260 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7261 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7262 (match_operand:DI 2 "and64_2_operand" ""))
7263 (const_int 0)))
7264 (set (match_operand:DI 0 "gpc_reg_operand" "")
7265 (and:DI (match_dup 1) (match_dup 2)))
7266 (clobber (match_scratch:CC 4 ""))]
7267 "TARGET_64BIT && reload_completed"
7268 [(parallel [(set (match_dup 0)
7269 (and:DI (match_dup 1) (match_dup 2)))
7270 (clobber (match_dup 4))])
7271 (set (match_dup 3)
7272 (compare:CC (match_dup 0)
7273 (const_int 0)))]
7274 "")
7275
7276 (define_split
7277 [(set (match_operand:CC 3 "cc_reg_operand" "")
7278 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7279 (match_operand:DI 2 "mask64_2_operand" ""))
7280 (const_int 0)))
7281 (set (match_operand:DI 0 "gpc_reg_operand" "")
7282 (and:DI (match_dup 1) (match_dup 2)))
7283 (clobber (match_scratch:CC 4 ""))]
7284 "TARGET_64BIT && reload_completed
7285 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7286 && !mask_operand (operands[2], DImode)
7287 && !mask64_operand (operands[2], DImode)"
7288 [(set (match_dup 0)
7289 (and:DI (rotate:DI (match_dup 1)
7290 (match_dup 5))
7291 (match_dup 6)))
7292 (parallel [(set (match_dup 3)
7293 (compare:CC (and:DI (rotate:DI (match_dup 0)
7294 (match_dup 7))
7295 (match_dup 8))
7296 (const_int 0)))
7297 (set (match_dup 0)
7298 (and:DI (rotate:DI (match_dup 0)
7299 (match_dup 7))
7300 (match_dup 8)))])]
7301 "
7302 {
7303 build_mask64_2_operands (operands[2], &operands[5]);
7304 }")
7305
7306 (define_expand "iordi3"
7307 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7308 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7309 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7310 "TARGET_POWERPC64"
7311 "
7312 {
7313 if (non_logical_cint_operand (operands[2], DImode))
7314 {
7315 HOST_WIDE_INT value;
7316 rtx tmp = ((!can_create_pseudo_p ()
7317 || rtx_equal_p (operands[0], operands[1]))
7318 ? operands[0] : gen_reg_rtx (DImode));
7319
7320 if (GET_CODE (operands[2]) == CONST_INT)
7321 {
7322 value = INTVAL (operands[2]);
7323 emit_insn (gen_iordi3 (tmp, operands[1],
7324 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7325 }
7326 else
7327 {
7328 value = CONST_DOUBLE_LOW (operands[2]);
7329 emit_insn (gen_iordi3 (tmp, operands[1],
7330 immed_double_const (value
7331 & (~ (HOST_WIDE_INT) 0xffff),
7332 0, DImode)));
7333 }
7334
7335 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7336 DONE;
7337 }
7338 }")
7339
7340 (define_expand "xordi3"
7341 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7342 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7343 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7344 "TARGET_POWERPC64"
7345 "
7346 {
7347 if (non_logical_cint_operand (operands[2], DImode))
7348 {
7349 HOST_WIDE_INT value;
7350 rtx tmp = ((!can_create_pseudo_p ()
7351 || rtx_equal_p (operands[0], operands[1]))
7352 ? operands[0] : gen_reg_rtx (DImode));
7353
7354 if (GET_CODE (operands[2]) == CONST_INT)
7355 {
7356 value = INTVAL (operands[2]);
7357 emit_insn (gen_xordi3 (tmp, operands[1],
7358 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7359 }
7360 else
7361 {
7362 value = CONST_DOUBLE_LOW (operands[2]);
7363 emit_insn (gen_xordi3 (tmp, operands[1],
7364 immed_double_const (value
7365 & (~ (HOST_WIDE_INT) 0xffff),
7366 0, DImode)));
7367 }
7368
7369 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7370 DONE;
7371 }
7372 }")
7373
7374 (define_insn "*booldi3_internal1"
7375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7376 (match_operator:DI 3 "boolean_or_operator"
7377 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7378 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7379 "TARGET_POWERPC64"
7380 "@
7381 %q3 %0,%1,%2
7382 %q3i %0,%1,%b2
7383 %q3is %0,%1,%u2")
7384
7385 (define_insn "*booldi3_internal2"
7386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7387 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7388 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7389 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7390 (const_int 0)))
7391 (clobber (match_scratch:DI 3 "=r,r"))]
7392 "TARGET_64BIT"
7393 "@
7394 %q4. %3,%1,%2
7395 #"
7396 [(set_attr "type" "fast_compare,compare")
7397 (set_attr "length" "4,8")])
7398
7399 (define_split
7400 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7401 (compare:CC (match_operator:DI 4 "boolean_operator"
7402 [(match_operand:DI 1 "gpc_reg_operand" "")
7403 (match_operand:DI 2 "gpc_reg_operand" "")])
7404 (const_int 0)))
7405 (clobber (match_scratch:DI 3 ""))]
7406 "TARGET_POWERPC64 && reload_completed"
7407 [(set (match_dup 3) (match_dup 4))
7408 (set (match_dup 0)
7409 (compare:CC (match_dup 3)
7410 (const_int 0)))]
7411 "")
7412
7413 (define_insn "*booldi3_internal3"
7414 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7415 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7416 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7417 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7418 (const_int 0)))
7419 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7420 (match_dup 4))]
7421 "TARGET_64BIT"
7422 "@
7423 %q4. %0,%1,%2
7424 #"
7425 [(set_attr "type" "fast_compare,compare")
7426 (set_attr "length" "4,8")])
7427
7428 (define_split
7429 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7430 (compare:CC (match_operator:DI 4 "boolean_operator"
7431 [(match_operand:DI 1 "gpc_reg_operand" "")
7432 (match_operand:DI 2 "gpc_reg_operand" "")])
7433 (const_int 0)))
7434 (set (match_operand:DI 0 "gpc_reg_operand" "")
7435 (match_dup 4))]
7436 "TARGET_POWERPC64 && reload_completed"
7437 [(set (match_dup 0) (match_dup 4))
7438 (set (match_dup 3)
7439 (compare:CC (match_dup 0)
7440 (const_int 0)))]
7441 "")
7442
7443 ;; Split a logical operation that we can't do in one insn into two insns,
7444 ;; each of which does one 16-bit part. This is used by combine.
7445
7446 (define_split
7447 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7448 (match_operator:DI 3 "boolean_or_operator"
7449 [(match_operand:DI 1 "gpc_reg_operand" "")
7450 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7451 "TARGET_POWERPC64"
7452 [(set (match_dup 0) (match_dup 4))
7453 (set (match_dup 0) (match_dup 5))]
7454 "
7455 {
7456 rtx i3,i4;
7457
7458 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7459 {
7460 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7461 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7462 0, DImode);
7463 i4 = GEN_INT (value & 0xffff);
7464 }
7465 else
7466 {
7467 i3 = GEN_INT (INTVAL (operands[2])
7468 & (~ (HOST_WIDE_INT) 0xffff));
7469 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7470 }
7471 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7472 operands[1], i3);
7473 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7474 operands[0], i4);
7475 }")
7476
7477 (define_insn "*boolcdi3_internal1"
7478 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7479 (match_operator:DI 3 "boolean_operator"
7480 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7481 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7482 "TARGET_POWERPC64"
7483 "%q3 %0,%2,%1")
7484
7485 (define_insn "*boolcdi3_internal2"
7486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7487 (compare:CC (match_operator:DI 4 "boolean_operator"
7488 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7489 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7490 (const_int 0)))
7491 (clobber (match_scratch:DI 3 "=r,r"))]
7492 "TARGET_64BIT"
7493 "@
7494 %q4. %3,%2,%1
7495 #"
7496 [(set_attr "type" "fast_compare,compare")
7497 (set_attr "length" "4,8")])
7498
7499 (define_split
7500 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7501 (compare:CC (match_operator:DI 4 "boolean_operator"
7502 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7503 (match_operand:DI 2 "gpc_reg_operand" "")])
7504 (const_int 0)))
7505 (clobber (match_scratch:DI 3 ""))]
7506 "TARGET_POWERPC64 && reload_completed"
7507 [(set (match_dup 3) (match_dup 4))
7508 (set (match_dup 0)
7509 (compare:CC (match_dup 3)
7510 (const_int 0)))]
7511 "")
7512
7513 (define_insn "*boolcdi3_internal3"
7514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7515 (compare:CC (match_operator:DI 4 "boolean_operator"
7516 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7517 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7518 (const_int 0)))
7519 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7520 (match_dup 4))]
7521 "TARGET_64BIT"
7522 "@
7523 %q4. %0,%2,%1
7524 #"
7525 [(set_attr "type" "fast_compare,compare")
7526 (set_attr "length" "4,8")])
7527
7528 (define_split
7529 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7530 (compare:CC (match_operator:DI 4 "boolean_operator"
7531 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7532 (match_operand:DI 2 "gpc_reg_operand" "")])
7533 (const_int 0)))
7534 (set (match_operand:DI 0 "gpc_reg_operand" "")
7535 (match_dup 4))]
7536 "TARGET_POWERPC64 && reload_completed"
7537 [(set (match_dup 0) (match_dup 4))
7538 (set (match_dup 3)
7539 (compare:CC (match_dup 0)
7540 (const_int 0)))]
7541 "")
7542
7543 (define_insn "*boolccdi3_internal1"
7544 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7545 (match_operator:DI 3 "boolean_operator"
7546 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7547 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7548 "TARGET_POWERPC64"
7549 "%q3 %0,%1,%2")
7550
7551 (define_insn "*boolccdi3_internal2"
7552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7553 (compare:CC (match_operator:DI 4 "boolean_operator"
7554 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7555 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7556 (const_int 0)))
7557 (clobber (match_scratch:DI 3 "=r,r"))]
7558 "TARGET_64BIT"
7559 "@
7560 %q4. %3,%1,%2
7561 #"
7562 [(set_attr "type" "fast_compare,compare")
7563 (set_attr "length" "4,8")])
7564
7565 (define_split
7566 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7567 (compare:CC (match_operator:DI 4 "boolean_operator"
7568 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7569 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7570 (const_int 0)))
7571 (clobber (match_scratch:DI 3 ""))]
7572 "TARGET_POWERPC64 && reload_completed"
7573 [(set (match_dup 3) (match_dup 4))
7574 (set (match_dup 0)
7575 (compare:CC (match_dup 3)
7576 (const_int 0)))]
7577 "")
7578
7579 (define_insn "*boolccdi3_internal3"
7580 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7581 (compare:CC (match_operator:DI 4 "boolean_operator"
7582 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7583 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7584 (const_int 0)))
7585 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7586 (match_dup 4))]
7587 "TARGET_64BIT"
7588 "@
7589 %q4. %0,%1,%2
7590 #"
7591 [(set_attr "type" "fast_compare,compare")
7592 (set_attr "length" "4,8")])
7593
7594 (define_split
7595 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7596 (compare:CC (match_operator:DI 4 "boolean_operator"
7597 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7598 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7599 (const_int 0)))
7600 (set (match_operand:DI 0 "gpc_reg_operand" "")
7601 (match_dup 4))]
7602 "TARGET_POWERPC64 && reload_completed"
7603 [(set (match_dup 0) (match_dup 4))
7604 (set (match_dup 3)
7605 (compare:CC (match_dup 0)
7606 (const_int 0)))]
7607 "")
7608 \f
7609 ;; Now define ways of moving data around.
7610
7611 ;; Set up a register with a value from the GOT table
7612
7613 (define_expand "movsi_got"
7614 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7615 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7616 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7617 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7618 "
7619 {
7620 if (GET_CODE (operands[1]) == CONST)
7621 {
7622 rtx offset = const0_rtx;
7623 HOST_WIDE_INT value;
7624
7625 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7626 value = INTVAL (offset);
7627 if (value != 0)
7628 {
7629 rtx tmp = (!can_create_pseudo_p ()
7630 ? operands[0]
7631 : gen_reg_rtx (Pmode));
7632 emit_insn (gen_movsi_got (tmp, operands[1]));
7633 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7634 DONE;
7635 }
7636 }
7637
7638 operands[2] = rs6000_got_register (operands[1]);
7639 }")
7640
7641 (define_insn "*movsi_got_internal"
7642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7643 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7644 (match_operand:SI 2 "gpc_reg_operand" "b")]
7645 UNSPEC_MOVSI_GOT))]
7646 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7647 "lwz %0,%a1@got(%2)"
7648 [(set_attr "type" "load")])
7649
7650 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7651 ;; didn't get allocated to a hard register.
7652 (define_split
7653 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7654 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7655 (match_operand:SI 2 "memory_operand" "")]
7656 UNSPEC_MOVSI_GOT))]
7657 "DEFAULT_ABI == ABI_V4
7658 && flag_pic == 1
7659 && (reload_in_progress || reload_completed)"
7660 [(set (match_dup 0) (match_dup 2))
7661 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7662 UNSPEC_MOVSI_GOT))]
7663 "")
7664
7665 ;; For SI, we special-case integers that can't be loaded in one insn. We
7666 ;; do the load 16-bits at a time. We could do this by loading from memory,
7667 ;; and this is even supposed to be faster, but it is simpler not to get
7668 ;; integers in the TOC.
7669 (define_insn "movsi_low"
7670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7671 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7672 (match_operand 2 "" ""))))]
7673 "TARGET_MACHO && ! TARGET_64BIT"
7674 "lwz %0,lo16(%2)(%1)"
7675 [(set_attr "type" "load")
7676 (set_attr "length" "4")])
7677
7678 (define_insn "*movsi_internal1"
7679 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7680 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7681 "!TARGET_SINGLE_FPU &&
7682 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7683 "@
7684 mr %0,%1
7685 la %0,%a1
7686 lwz%U1%X1 %0,%1
7687 stw%U0%X0 %1,%0
7688 li %0,%1
7689 lis %0,%v1
7690 #
7691 mf%1 %0
7692 mt%0 %1
7693 mt%0 %1
7694 nop"
7695 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7696 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7697
7698 (define_insn "*movsi_internal1_single"
7699 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7700 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7701 "TARGET_SINGLE_FPU &&
7702 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7703 "@
7704 mr %0,%1
7705 la %0,%a1
7706 lwz%U1%X1 %0,%1
7707 stw%U0%X0 %1,%0
7708 li %0,%1
7709 lis %0,%v1
7710 #
7711 mf%1 %0
7712 mt%0 %1
7713 mt%0 %1
7714 nop
7715 stfs%U0%X0 %1,%0
7716 lfs%U1%X1 %0,%1"
7717 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
7718 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7719
7720 ;; Split a load of a large constant into the appropriate two-insn
7721 ;; sequence.
7722
7723 (define_split
7724 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7725 (match_operand:SI 1 "const_int_operand" ""))]
7726 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7727 && (INTVAL (operands[1]) & 0xffff) != 0"
7728 [(set (match_dup 0)
7729 (match_dup 2))
7730 (set (match_dup 0)
7731 (ior:SI (match_dup 0)
7732 (match_dup 3)))]
7733 "
7734 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7735
7736 if (tem == operands[0])
7737 DONE;
7738 else
7739 FAIL;
7740 }")
7741
7742 (define_insn "*mov<mode>_internal2"
7743 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7744 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7745 (const_int 0)))
7746 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7747 ""
7748 "@
7749 cmp<wd>i %2,%0,0
7750 mr. %0,%1
7751 #"
7752 [(set_attr "type" "cmp,compare,cmp")
7753 (set_attr "length" "4,4,8")])
7754
7755 (define_split
7756 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7757 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7758 (const_int 0)))
7759 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7760 "reload_completed"
7761 [(set (match_dup 0) (match_dup 1))
7762 (set (match_dup 2)
7763 (compare:CC (match_dup 0)
7764 (const_int 0)))]
7765 "")
7766 \f
7767 (define_insn "*movhi_internal"
7768 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7769 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7770 "gpc_reg_operand (operands[0], HImode)
7771 || gpc_reg_operand (operands[1], HImode)"
7772 "@
7773 mr %0,%1
7774 lhz%U1%X1 %0,%1
7775 sth%U0%X0 %1,%0
7776 li %0,%w1
7777 mf%1 %0
7778 mt%0 %1
7779 nop"
7780 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7781
7782 (define_expand "mov<mode>"
7783 [(set (match_operand:INT 0 "general_operand" "")
7784 (match_operand:INT 1 "any_operand" ""))]
7785 ""
7786 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7787
7788 (define_insn "*movqi_internal"
7789 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7790 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7791 "gpc_reg_operand (operands[0], QImode)
7792 || gpc_reg_operand (operands[1], QImode)"
7793 "@
7794 mr %0,%1
7795 lbz%U1%X1 %0,%1
7796 stb%U0%X0 %1,%0
7797 li %0,%1
7798 mf%1 %0
7799 mt%0 %1
7800 nop"
7801 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7802 \f
7803 ;; Here is how to move condition codes around. When we store CC data in
7804 ;; an integer register or memory, we store just the high-order 4 bits.
7805 ;; This lets us not shift in the most common case of CR0.
7806 (define_expand "movcc"
7807 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7808 (match_operand:CC 1 "nonimmediate_operand" ""))]
7809 ""
7810 "")
7811
7812 (define_insn "*movcc_internal1"
7813 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7814 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7815 "register_operand (operands[0], CCmode)
7816 || register_operand (operands[1], CCmode)"
7817 "@
7818 mcrf %0,%1
7819 mtcrf 128,%1
7820 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7821 crxor %0,%0,%0
7822 mfcr %0%Q1
7823 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7824 mr %0,%1
7825 li %0,%1
7826 mf%1 %0
7827 mt%0 %1
7828 lwz%U1%X1 %0,%1
7829 stw%U0%U1 %1,%0"
7830 [(set (attr "type")
7831 (cond [(eq_attr "alternative" "0,3")
7832 (const_string "cr_logical")
7833 (eq_attr "alternative" "1,2")
7834 (const_string "mtcr")
7835 (eq_attr "alternative" "6,7")
7836 (const_string "integer")
7837 (eq_attr "alternative" "8")
7838 (const_string "mfjmpr")
7839 (eq_attr "alternative" "9")
7840 (const_string "mtjmpr")
7841 (eq_attr "alternative" "10")
7842 (const_string "load")
7843 (eq_attr "alternative" "11")
7844 (const_string "store")
7845 (match_test "TARGET_MFCRF")
7846 (const_string "mfcrf")
7847 ]
7848 (const_string "mfcr")))
7849 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7850 \f
7851 ;; For floating-point, we normally deal with the floating-point registers
7852 ;; unless -msoft-float is used. The sole exception is that parameter passing
7853 ;; can produce floating-point values in fixed-point registers. Unless the
7854 ;; value is a simple constant or already in memory, we deal with this by
7855 ;; allocating memory and copying the value explicitly via that memory location.
7856 (define_expand "movsf"
7857 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7858 (match_operand:SF 1 "any_operand" ""))]
7859 ""
7860 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7861
7862 (define_split
7863 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7864 (match_operand:SF 1 "const_double_operand" ""))]
7865 "reload_completed
7866 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7867 || (GET_CODE (operands[0]) == SUBREG
7868 && GET_CODE (SUBREG_REG (operands[0])) == REG
7869 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7870 [(set (match_dup 2) (match_dup 3))]
7871 "
7872 {
7873 long l;
7874 REAL_VALUE_TYPE rv;
7875
7876 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7877 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7878
7879 if (! TARGET_POWERPC64)
7880 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7881 else
7882 operands[2] = gen_lowpart (SImode, operands[0]);
7883
7884 operands[3] = gen_int_mode (l, SImode);
7885 }")
7886
7887 (define_insn "*movsf_hardfloat"
7888 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")
7889 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]
7890 "(gpc_reg_operand (operands[0], SFmode)
7891 || gpc_reg_operand (operands[1], SFmode))
7892 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7893 "@
7894 mr %0,%1
7895 lwz%U1%X1 %0,%1
7896 stw%U0%X0 %1,%0
7897 fmr %0,%1
7898 lfs%U1%X1 %0,%1
7899 stfs%U0%X0 %1,%0
7900 mt%0 %1
7901 mf%1 %0
7902 nop
7903 #
7904 #"
7905 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")
7906 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7907
7908 (define_insn "*movsf_softfloat"
7909 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7910 (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7911 "(gpc_reg_operand (operands[0], SFmode)
7912 || gpc_reg_operand (operands[1], SFmode))
7913 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7914 "@
7915 mr %0,%1
7916 mt%0 %1
7917 mf%1 %0
7918 lwz%U1%X1 %0,%1
7919 stw%U0%X0 %1,%0
7920 li %0,%1
7921 lis %0,%v1
7922 #
7923 #
7924 nop"
7925 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7926 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7927
7928 \f
7929 (define_expand "movdf"
7930 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7931 (match_operand:DF 1 "any_operand" ""))]
7932 ""
7933 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7934
7935 (define_split
7936 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7937 (match_operand:DF 1 "const_int_operand" ""))]
7938 "! TARGET_POWERPC64 && reload_completed
7939 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7940 || (GET_CODE (operands[0]) == SUBREG
7941 && GET_CODE (SUBREG_REG (operands[0])) == REG
7942 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7943 [(set (match_dup 2) (match_dup 4))
7944 (set (match_dup 3) (match_dup 1))]
7945 "
7946 {
7947 int endian = (WORDS_BIG_ENDIAN == 0);
7948 HOST_WIDE_INT value = INTVAL (operands[1]);
7949
7950 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7951 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7952 #if HOST_BITS_PER_WIDE_INT == 32
7953 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7954 #else
7955 operands[4] = GEN_INT (value >> 32);
7956 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7957 #endif
7958 }")
7959
7960 (define_split
7961 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7962 (match_operand:DF 1 "const_double_operand" ""))]
7963 "! TARGET_POWERPC64 && reload_completed
7964 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7965 || (GET_CODE (operands[0]) == SUBREG
7966 && GET_CODE (SUBREG_REG (operands[0])) == REG
7967 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7968 [(set (match_dup 2) (match_dup 4))
7969 (set (match_dup 3) (match_dup 5))]
7970 "
7971 {
7972 int endian = (WORDS_BIG_ENDIAN == 0);
7973 long l[2];
7974 REAL_VALUE_TYPE rv;
7975
7976 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7977 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7978
7979 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7980 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7981 operands[4] = gen_int_mode (l[endian], SImode);
7982 operands[5] = gen_int_mode (l[1 - endian], SImode);
7983 }")
7984
7985 (define_split
7986 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7987 (match_operand:DF 1 "const_double_operand" ""))]
7988 "TARGET_POWERPC64 && reload_completed
7989 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7990 || (GET_CODE (operands[0]) == SUBREG
7991 && GET_CODE (SUBREG_REG (operands[0])) == REG
7992 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7993 [(set (match_dup 2) (match_dup 3))]
7994 "
7995 {
7996 int endian = (WORDS_BIG_ENDIAN == 0);
7997 long l[2];
7998 REAL_VALUE_TYPE rv;
7999 #if HOST_BITS_PER_WIDE_INT >= 64
8000 HOST_WIDE_INT val;
8001 #endif
8002
8003 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8004 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8005
8006 operands[2] = gen_lowpart (DImode, operands[0]);
8007 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8008 #if HOST_BITS_PER_WIDE_INT >= 64
8009 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8010 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8011
8012 operands[3] = gen_int_mode (val, DImode);
8013 #else
8014 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8015 #endif
8016 }")
8017
8018 ;; Don't have reload use general registers to load a constant. It is
8019 ;; less efficient than loading the constant into an FP register, since
8020 ;; it will probably be used there.
8021 (define_insn "*movdf_hardfloat32"
8022 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")
8023 (match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]
8024 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8025 && (gpc_reg_operand (operands[0], DFmode)
8026 || gpc_reg_operand (operands[1], DFmode))"
8027 "@
8028 stfd%U0%X0 %1,%0
8029 lfd%U1%X1 %0,%1
8030 fmr %0,%1
8031 lxsd%U1x %x0,%y1
8032 lxsd%U1x %x0,%y1
8033 stxsd%U0x %x1,%y0
8034 stxsd%U0x %x1,%y0
8035 xxlor %x0,%x1,%x1
8036 xxlor %x0,%x1,%x1
8037 xxlxor %x0,%x0,%x0
8038 #
8039 #
8040 #
8041 #
8042 #
8043 #"
8044 [(set_attr "type" "fpstore,fpload,fp,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,store,load,two,fp,fp,*")
8045 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])
8046
8047 (define_insn "*movdf_softfloat32"
8048 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8049 (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
8050 "! TARGET_POWERPC64
8051 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8052 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8053 && (gpc_reg_operand (operands[0], DFmode)
8054 || gpc_reg_operand (operands[1], DFmode))"
8055 "#"
8056 [(set_attr "type" "store,load,two,*,*,*")
8057 (set_attr "length" "8,8,8,8,12,16")])
8058
8059 ;; Reload patterns to support gpr load/store with misaligned mem.
8060 ;; and multiple gpr load/store at offset >= 0xfffc
8061 (define_expand "reload_<mode>_store"
8062 [(parallel [(match_operand 0 "memory_operand" "=m")
8063 (match_operand 1 "gpc_reg_operand" "r")
8064 (match_operand:GPR 2 "register_operand" "=&b")])]
8065 ""
8066 {
8067 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8068 DONE;
8069 })
8070
8071 (define_expand "reload_<mode>_load"
8072 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8073 (match_operand 1 "memory_operand" "m")
8074 (match_operand:GPR 2 "register_operand" "=b")])]
8075 ""
8076 {
8077 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8078 DONE;
8079 })
8080
8081 ; ld/std require word-aligned displacements -> 'Y' constraint.
8082 ; List Y->r and r->Y before r->r for reload.
8083 (define_insn "*movdf_hardfloat64_mfpgpr"
8084 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
8085 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
8086 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8087 && TARGET_DOUBLE_FLOAT
8088 && (gpc_reg_operand (operands[0], DFmode)
8089 || gpc_reg_operand (operands[1], DFmode))"
8090 "@
8091 std%U0%X0 %1,%0
8092 ld%U1%X1 %0,%1
8093 mr %0,%1
8094 xxlor %x0,%x1,%x1
8095 xxlor %x0,%x1,%x1
8096 lxsd%U1x %x0,%y1
8097 lxsd%U1x %x0,%y1
8098 stxsd%U0x %x1,%y0
8099 stxsd%U0x %x1,%y0
8100 stfd%U0%X0 %1,%0
8101 lfd%U1%X1 %0,%1
8102 fmr %0,%1
8103 xxlxor %x0,%x0,%x0
8104 mt%0 %1
8105 mf%1 %0
8106 nop
8107 #
8108 #
8109 #
8110 mftgpr %0,%1
8111 mffgpr %0,%1"
8112 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8113 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8114
8115 ; ld/std require word-aligned displacements -> 'Y' constraint.
8116 ; List Y->r and r->Y before r->r for reload.
8117 (define_insn "*movdf_hardfloat64"
8118 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r")
8119 (match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))]
8120 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8121 && TARGET_DOUBLE_FLOAT
8122 && (gpc_reg_operand (operands[0], DFmode)
8123 || gpc_reg_operand (operands[1], DFmode))"
8124 "@
8125 stfd%U0%X0 %1,%0
8126 lfd%U1%X1 %0,%1
8127 fmr %0,%1
8128 std%U0%X0 %1,%0
8129 ld%U1%X1 %0,%1
8130 mr %0,%1
8131 lxsd%U1x %x0,%y1
8132 lxsd%U1x %x0,%y1
8133 stxsd%U0x %x1,%y0
8134 stxsd%U0x %x1,%y0
8135 xxlor %x0,%x1,%x1
8136 xxlor %x0,%x1,%x1
8137 xxlxor %x0,%x0,%x0
8138 mt%0 %1
8139 mf%1 %0
8140 nop
8141 #
8142 #
8143 #"
8144 [(set_attr "type" "fpstore,fpload,fp,store,load,*,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
8145 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8146
8147 (define_insn "*movdf_softfloat64"
8148 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8149 (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8150 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8151 && (gpc_reg_operand (operands[0], DFmode)
8152 || gpc_reg_operand (operands[1], DFmode))"
8153 "@
8154 std%U0%X0 %1,%0
8155 ld%U1%X1 %0,%1
8156 mr %0,%1
8157 mt%0 %1
8158 mf%1 %0
8159 #
8160 #
8161 #
8162 nop"
8163 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8164 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8165 \f
8166 (define_expand "movtf"
8167 [(set (match_operand:TF 0 "general_operand" "")
8168 (match_operand:TF 1 "any_operand" ""))]
8169 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8170 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8171
8172 ;; It's important to list Y->r and r->Y before r->r because otherwise
8173 ;; reload, given m->r, will try to pick r->r and reload it, which
8174 ;; doesn't make progress.
8175 (define_insn_and_split "*movtf_internal"
8176 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8177 (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
8178 "!TARGET_IEEEQUAD
8179 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8180 && (gpc_reg_operand (operands[0], TFmode)
8181 || gpc_reg_operand (operands[1], TFmode))"
8182 "#"
8183 "&& reload_completed"
8184 [(pc)]
8185 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8186 [(set_attr "length" "8,8,8,20,20,16")])
8187
8188 (define_insn_and_split "*movtf_softfloat"
8189 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8190 (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
8191 "!TARGET_IEEEQUAD
8192 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8193 && (gpc_reg_operand (operands[0], TFmode)
8194 || gpc_reg_operand (operands[1], TFmode))"
8195 "#"
8196 "&& reload_completed"
8197 [(pc)]
8198 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8199 [(set_attr "length" "20,20,16")])
8200
8201 (define_expand "extenddftf2"
8202 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8203 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8204 "!TARGET_IEEEQUAD
8205 && TARGET_HARD_FLOAT
8206 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8207 && TARGET_LONG_DOUBLE_128"
8208 {
8209 if (TARGET_E500_DOUBLE)
8210 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8211 else
8212 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8213 DONE;
8214 })
8215
8216 (define_expand "extenddftf2_fprs"
8217 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8218 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8219 (use (match_dup 2))])]
8220 "!TARGET_IEEEQUAD
8221 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8222 && TARGET_LONG_DOUBLE_128"
8223 {
8224 operands[2] = CONST0_RTX (DFmode);
8225 /* Generate GOT reference early for SVR4 PIC. */
8226 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8227 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8228 })
8229
8230 (define_insn_and_split "*extenddftf2_internal"
8231 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8232 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8233 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8234 "!TARGET_IEEEQUAD
8235 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8236 && TARGET_LONG_DOUBLE_128"
8237 "#"
8238 "&& reload_completed"
8239 [(pc)]
8240 {
8241 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8242 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8243 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8244 operands[1]);
8245 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8246 operands[2]);
8247 DONE;
8248 })
8249
8250 (define_expand "extendsftf2"
8251 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8252 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8253 "!TARGET_IEEEQUAD
8254 && TARGET_HARD_FLOAT
8255 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8256 && TARGET_LONG_DOUBLE_128"
8257 {
8258 rtx tmp = gen_reg_rtx (DFmode);
8259 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8260 emit_insn (gen_extenddftf2 (operands[0], tmp));
8261 DONE;
8262 })
8263
8264 (define_expand "trunctfdf2"
8265 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8266 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8267 "!TARGET_IEEEQUAD
8268 && TARGET_HARD_FLOAT
8269 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8270 && TARGET_LONG_DOUBLE_128"
8271 "")
8272
8273 (define_insn_and_split "trunctfdf2_internal1"
8274 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8275 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8276 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8277 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8278 "@
8279 #
8280 fmr %0,%1"
8281 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8282 [(const_int 0)]
8283 {
8284 emit_note (NOTE_INSN_DELETED);
8285 DONE;
8286 }
8287 [(set_attr "type" "fp")])
8288
8289 (define_insn "trunctfdf2_internal2"
8290 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8291 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8292 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8293 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8294 && TARGET_LONG_DOUBLE_128"
8295 "fadd %0,%1,%L1"
8296 [(set_attr "type" "fp")
8297 (set_attr "fp_type" "fp_addsub_d")])
8298
8299 (define_expand "trunctfsf2"
8300 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8301 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8302 "!TARGET_IEEEQUAD
8303 && TARGET_HARD_FLOAT
8304 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8305 && TARGET_LONG_DOUBLE_128"
8306 {
8307 if (TARGET_E500_DOUBLE)
8308 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8309 else
8310 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8311 DONE;
8312 })
8313
8314 (define_insn_and_split "trunctfsf2_fprs"
8315 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8316 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8317 (clobber (match_scratch:DF 2 "=d"))]
8318 "!TARGET_IEEEQUAD
8319 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8320 && TARGET_LONG_DOUBLE_128"
8321 "#"
8322 "&& reload_completed"
8323 [(set (match_dup 2)
8324 (float_truncate:DF (match_dup 1)))
8325 (set (match_dup 0)
8326 (float_truncate:SF (match_dup 2)))]
8327 "")
8328
8329 (define_expand "floatsitf2"
8330 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8331 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8332 "!TARGET_IEEEQUAD
8333 && TARGET_HARD_FLOAT
8334 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8335 && TARGET_LONG_DOUBLE_128"
8336 {
8337 rtx tmp = gen_reg_rtx (DFmode);
8338 expand_float (tmp, operands[1], false);
8339 emit_insn (gen_extenddftf2 (operands[0], tmp));
8340 DONE;
8341 })
8342
8343 ; fadd, but rounding towards zero.
8344 ; This is probably not the optimal code sequence.
8345 (define_insn "fix_trunc_helper"
8346 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8347 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8348 UNSPEC_FIX_TRUNC_TF))
8349 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8350 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8351 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8352 [(set_attr "type" "fp")
8353 (set_attr "length" "20")])
8354
8355 (define_expand "fix_trunctfsi2"
8356 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8357 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8358 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8359 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8360 {
8361 if (TARGET_E500_DOUBLE)
8362 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8363 else
8364 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8365 DONE;
8366 })
8367
8368 (define_expand "fix_trunctfsi2_fprs"
8369 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8370 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8371 (clobber (match_dup 2))
8372 (clobber (match_dup 3))
8373 (clobber (match_dup 4))
8374 (clobber (match_dup 5))])]
8375 "!TARGET_IEEEQUAD
8376 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8377 {
8378 operands[2] = gen_reg_rtx (DFmode);
8379 operands[3] = gen_reg_rtx (DFmode);
8380 operands[4] = gen_reg_rtx (DImode);
8381 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8382 })
8383
8384 (define_insn_and_split "*fix_trunctfsi2_internal"
8385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8386 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8387 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8388 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8389 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8390 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8391 "!TARGET_IEEEQUAD
8392 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8393 "#"
8394 ""
8395 [(pc)]
8396 {
8397 rtx lowword;
8398 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8399
8400 gcc_assert (MEM_P (operands[5]));
8401 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8402
8403 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8404 emit_move_insn (operands[5], operands[4]);
8405 emit_move_insn (operands[0], lowword);
8406 DONE;
8407 })
8408
8409 (define_expand "negtf2"
8410 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8411 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8412 "!TARGET_IEEEQUAD
8413 && TARGET_HARD_FLOAT
8414 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8415 && TARGET_LONG_DOUBLE_128"
8416 "")
8417
8418 (define_insn "negtf2_internal"
8419 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8420 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8421 "!TARGET_IEEEQUAD
8422 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8423 "*
8424 {
8425 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8426 return \"fneg %L0,%L1\;fneg %0,%1\";
8427 else
8428 return \"fneg %0,%1\;fneg %L0,%L1\";
8429 }"
8430 [(set_attr "type" "fp")
8431 (set_attr "length" "8")])
8432
8433 (define_expand "abstf2"
8434 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8435 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8436 "!TARGET_IEEEQUAD
8437 && TARGET_HARD_FLOAT
8438 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8439 && TARGET_LONG_DOUBLE_128"
8440 "
8441 {
8442 rtx label = gen_label_rtx ();
8443 if (TARGET_E500_DOUBLE)
8444 {
8445 if (flag_finite_math_only && !flag_trapping_math)
8446 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8447 else
8448 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8449 }
8450 else
8451 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8452 emit_label (label);
8453 DONE;
8454 }")
8455
8456 (define_expand "abstf2_internal"
8457 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8458 (match_operand:TF 1 "gpc_reg_operand" ""))
8459 (set (match_dup 3) (match_dup 5))
8460 (set (match_dup 5) (abs:DF (match_dup 5)))
8461 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8462 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8463 (label_ref (match_operand 2 "" ""))
8464 (pc)))
8465 (set (match_dup 6) (neg:DF (match_dup 6)))]
8466 "!TARGET_IEEEQUAD
8467 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8468 && TARGET_LONG_DOUBLE_128"
8469 "
8470 {
8471 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8472 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8473 operands[3] = gen_reg_rtx (DFmode);
8474 operands[4] = gen_reg_rtx (CCFPmode);
8475 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8476 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8477 }")
8478 \f
8479 ;; Next come the multi-word integer load and store and the load and store
8480 ;; multiple insns.
8481
8482 ;; List r->r after r->Y, otherwise reload will try to reload a
8483 ;; non-offsettable address by using r->r which won't make progress.
8484 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8485 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8486 (define_insn "*movdi_internal32"
8487 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
8488 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
8489 "! TARGET_POWERPC64
8490 && (gpc_reg_operand (operands[0], DImode)
8491 || gpc_reg_operand (operands[1], DImode))"
8492 "@
8493 #
8494 #
8495 #
8496 stfd%U0%X0 %1,%0
8497 lfd%U1%X1 %0,%1
8498 fmr %0,%1
8499 #
8500 xxlxor %x0,%x0,%x0"
8501 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
8502
8503 (define_split
8504 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8505 (match_operand:DI 1 "const_int_operand" ""))]
8506 "! TARGET_POWERPC64 && reload_completed
8507 && gpr_or_gpr_p (operands[0], operands[1])"
8508 [(set (match_dup 2) (match_dup 4))
8509 (set (match_dup 3) (match_dup 1))]
8510 "
8511 {
8512 HOST_WIDE_INT value = INTVAL (operands[1]);
8513 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8514 DImode);
8515 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8516 DImode);
8517 #if HOST_BITS_PER_WIDE_INT == 32
8518 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8519 #else
8520 operands[4] = GEN_INT (value >> 32);
8521 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8522 #endif
8523 }")
8524
8525 (define_split
8526 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8527 (match_operand:DIFD 1 "input_operand" ""))]
8528 "reload_completed && !TARGET_POWERPC64
8529 && gpr_or_gpr_p (operands[0], operands[1])"
8530 [(pc)]
8531 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8532
8533 (define_insn "*movdi_mfpgpr"
8534 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
8535 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
8536 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8537 && (gpc_reg_operand (operands[0], DImode)
8538 || gpc_reg_operand (operands[1], DImode))"
8539 "@
8540 std%U0%X0 %1,%0
8541 ld%U1%X1 %0,%1
8542 mr %0,%1
8543 li %0,%1
8544 lis %0,%v1
8545 #
8546 stfd%U0%X0 %1,%0
8547 lfd%U1%X1 %0,%1
8548 fmr %0,%1
8549 mf%1 %0
8550 mt%0 %1
8551 nop
8552 mftgpr %0,%1
8553 mffgpr %0,%1"
8554 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8555 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
8556
8557 (define_insn "*movdi_internal64"
8558 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
8559 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
8560 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8561 && (gpc_reg_operand (operands[0], DImode)
8562 || gpc_reg_operand (operands[1], DImode))"
8563 "@
8564 std%U0%X0 %1,%0
8565 ld%U1%X1 %0,%1
8566 mr %0,%1
8567 li %0,%1
8568 lis %0,%v1
8569 #
8570 stfd%U0%X0 %1,%0
8571 lfd%U1%X1 %0,%1
8572 fmr %0,%1
8573 mf%1 %0
8574 mt%0 %1
8575 nop
8576 xxlxor %x0,%x0,%x0"
8577 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
8578 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8579
8580 ;; immediate value valid for a single instruction hiding in a const_double
8581 (define_insn ""
8582 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8583 (match_operand:DI 1 "const_double_operand" "F"))]
8584 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8585 && GET_CODE (operands[1]) == CONST_DOUBLE
8586 && num_insns_constant (operands[1], DImode) == 1"
8587 "*
8588 {
8589 return ((unsigned HOST_WIDE_INT)
8590 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8591 ? \"li %0,%1\" : \"lis %0,%v1\";
8592 }")
8593
8594 ;; Generate all one-bits and clear left or right.
8595 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8596 (define_split
8597 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8598 (match_operand:DI 1 "mask64_operand" ""))]
8599 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8600 [(set (match_dup 0) (const_int -1))
8601 (set (match_dup 0)
8602 (and:DI (rotate:DI (match_dup 0)
8603 (const_int 0))
8604 (match_dup 1)))]
8605 "")
8606
8607 ;; Split a load of a large constant into the appropriate five-instruction
8608 ;; sequence. Handle anything in a constant number of insns.
8609 ;; When non-easy constants can go in the TOC, this should use
8610 ;; easy_fp_constant predicate.
8611 (define_split
8612 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8613 (match_operand:DI 1 "const_int_operand" ""))]
8614 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8615 [(set (match_dup 0) (match_dup 2))
8616 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8617 "
8618 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8619
8620 if (tem == operands[0])
8621 DONE;
8622 else
8623 FAIL;
8624 }")
8625
8626 (define_split
8627 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8628 (match_operand:DI 1 "const_double_operand" ""))]
8629 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8630 [(set (match_dup 0) (match_dup 2))
8631 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8632 "
8633 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8634
8635 if (tem == operands[0])
8636 DONE;
8637 else
8638 FAIL;
8639 }")
8640 \f
8641 ;; TImode is similar, except that we usually want to compute the address into
8642 ;; a register and use lsi/stsi (the exception is during reload).
8643
8644 (define_insn "*movti_string"
8645 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8646 (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
8647 "! TARGET_POWERPC64
8648 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8649 "*
8650 {
8651 switch (which_alternative)
8652 {
8653 default:
8654 gcc_unreachable ();
8655 case 0:
8656 if (TARGET_STRING)
8657 return \"stswi %1,%P0,16\";
8658 case 1:
8659 return \"#\";
8660 case 2:
8661 /* If the address is not used in the output, we can use lsi. Otherwise,
8662 fall through to generating four loads. */
8663 if (TARGET_STRING
8664 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8665 return \"lswi %0,%P1,16\";
8666 /* ... fall through ... */
8667 case 3:
8668 case 4:
8669 case 5:
8670 return \"#\";
8671 }
8672 }"
8673 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
8674 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8675 (const_string "always")
8676 (const_string "conditional")))])
8677
8678 (define_insn "*movti_ppc64"
8679 [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
8680 (match_operand:TI 1 "input_operand" "r,Y,r"))]
8681 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8682 || gpc_reg_operand (operands[1], TImode)))
8683 && VECTOR_MEM_NONE_P (TImode)"
8684 "#"
8685 [(set_attr "type" "store,load,*")])
8686
8687 (define_split
8688 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8689 (match_operand:TI 1 "const_double_operand" ""))]
8690 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
8691 [(set (match_dup 2) (match_dup 4))
8692 (set (match_dup 3) (match_dup 5))]
8693 "
8694 {
8695 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8696 TImode);
8697 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8698 TImode);
8699 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8700 {
8701 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8702 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8703 }
8704 else if (GET_CODE (operands[1]) == CONST_INT)
8705 {
8706 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8707 operands[5] = operands[1];
8708 }
8709 else
8710 FAIL;
8711 }")
8712
8713 (define_split
8714 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8715 (match_operand:TI 1 "input_operand" ""))]
8716 "reload_completed && VECTOR_MEM_NONE_P (TImode)
8717 && gpr_or_gpr_p (operands[0], operands[1])"
8718 [(pc)]
8719 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8720 \f
8721 (define_expand "load_multiple"
8722 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8723 (match_operand:SI 1 "" ""))
8724 (use (match_operand:SI 2 "" ""))])]
8725 "TARGET_STRING && !TARGET_POWERPC64"
8726 "
8727 {
8728 int regno;
8729 int count;
8730 rtx op1;
8731 int i;
8732
8733 /* Support only loading a constant number of fixed-point registers from
8734 memory and only bother with this if more than two; the machine
8735 doesn't support more than eight. */
8736 if (GET_CODE (operands[2]) != CONST_INT
8737 || INTVAL (operands[2]) <= 2
8738 || INTVAL (operands[2]) > 8
8739 || GET_CODE (operands[1]) != MEM
8740 || GET_CODE (operands[0]) != REG
8741 || REGNO (operands[0]) >= 32)
8742 FAIL;
8743
8744 count = INTVAL (operands[2]);
8745 regno = REGNO (operands[0]);
8746
8747 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8748 op1 = replace_equiv_address (operands[1],
8749 force_reg (SImode, XEXP (operands[1], 0)));
8750
8751 for (i = 0; i < count; i++)
8752 XVECEXP (operands[3], 0, i)
8753 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8754 adjust_address_nv (op1, SImode, i * 4));
8755 }")
8756
8757 (define_insn "*ldmsi8"
8758 [(match_parallel 0 "load_multiple_operation"
8759 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8760 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8761 (set (match_operand:SI 3 "gpc_reg_operand" "")
8762 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8763 (set (match_operand:SI 4 "gpc_reg_operand" "")
8764 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8765 (set (match_operand:SI 5 "gpc_reg_operand" "")
8766 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8767 (set (match_operand:SI 6 "gpc_reg_operand" "")
8768 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8769 (set (match_operand:SI 7 "gpc_reg_operand" "")
8770 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8771 (set (match_operand:SI 8 "gpc_reg_operand" "")
8772 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8773 (set (match_operand:SI 9 "gpc_reg_operand" "")
8774 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8775 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8776 "*
8777 { return rs6000_output_load_multiple (operands); }"
8778 [(set_attr "type" "load_ux")
8779 (set_attr "length" "32")])
8780
8781 (define_insn "*ldmsi7"
8782 [(match_parallel 0 "load_multiple_operation"
8783 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8784 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8785 (set (match_operand:SI 3 "gpc_reg_operand" "")
8786 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8787 (set (match_operand:SI 4 "gpc_reg_operand" "")
8788 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8789 (set (match_operand:SI 5 "gpc_reg_operand" "")
8790 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8791 (set (match_operand:SI 6 "gpc_reg_operand" "")
8792 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8793 (set (match_operand:SI 7 "gpc_reg_operand" "")
8794 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8795 (set (match_operand:SI 8 "gpc_reg_operand" "")
8796 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8797 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8798 "*
8799 { return rs6000_output_load_multiple (operands); }"
8800 [(set_attr "type" "load_ux")
8801 (set_attr "length" "32")])
8802
8803 (define_insn "*ldmsi6"
8804 [(match_parallel 0 "load_multiple_operation"
8805 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8806 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8807 (set (match_operand:SI 3 "gpc_reg_operand" "")
8808 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8809 (set (match_operand:SI 4 "gpc_reg_operand" "")
8810 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8811 (set (match_operand:SI 5 "gpc_reg_operand" "")
8812 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8813 (set (match_operand:SI 6 "gpc_reg_operand" "")
8814 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8815 (set (match_operand:SI 7 "gpc_reg_operand" "")
8816 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8817 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8818 "*
8819 { return rs6000_output_load_multiple (operands); }"
8820 [(set_attr "type" "load_ux")
8821 (set_attr "length" "32")])
8822
8823 (define_insn "*ldmsi5"
8824 [(match_parallel 0 "load_multiple_operation"
8825 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8826 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8827 (set (match_operand:SI 3 "gpc_reg_operand" "")
8828 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8829 (set (match_operand:SI 4 "gpc_reg_operand" "")
8830 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8831 (set (match_operand:SI 5 "gpc_reg_operand" "")
8832 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8833 (set (match_operand:SI 6 "gpc_reg_operand" "")
8834 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8835 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8836 "*
8837 { return rs6000_output_load_multiple (operands); }"
8838 [(set_attr "type" "load_ux")
8839 (set_attr "length" "32")])
8840
8841 (define_insn "*ldmsi4"
8842 [(match_parallel 0 "load_multiple_operation"
8843 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8844 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8845 (set (match_operand:SI 3 "gpc_reg_operand" "")
8846 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8847 (set (match_operand:SI 4 "gpc_reg_operand" "")
8848 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8849 (set (match_operand:SI 5 "gpc_reg_operand" "")
8850 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8851 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8852 "*
8853 { return rs6000_output_load_multiple (operands); }"
8854 [(set_attr "type" "load_ux")
8855 (set_attr "length" "32")])
8856
8857 (define_insn "*ldmsi3"
8858 [(match_parallel 0 "load_multiple_operation"
8859 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8860 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8861 (set (match_operand:SI 3 "gpc_reg_operand" "")
8862 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8863 (set (match_operand:SI 4 "gpc_reg_operand" "")
8864 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8865 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8866 "*
8867 { return rs6000_output_load_multiple (operands); }"
8868 [(set_attr "type" "load_ux")
8869 (set_attr "length" "32")])
8870
8871 (define_expand "store_multiple"
8872 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8873 (match_operand:SI 1 "" ""))
8874 (clobber (scratch:SI))
8875 (use (match_operand:SI 2 "" ""))])]
8876 "TARGET_STRING && !TARGET_POWERPC64"
8877 "
8878 {
8879 int regno;
8880 int count;
8881 rtx to;
8882 rtx op0;
8883 int i;
8884
8885 /* Support only storing a constant number of fixed-point registers to
8886 memory and only bother with this if more than two; the machine
8887 doesn't support more than eight. */
8888 if (GET_CODE (operands[2]) != CONST_INT
8889 || INTVAL (operands[2]) <= 2
8890 || INTVAL (operands[2]) > 8
8891 || GET_CODE (operands[0]) != MEM
8892 || GET_CODE (operands[1]) != REG
8893 || REGNO (operands[1]) >= 32)
8894 FAIL;
8895
8896 count = INTVAL (operands[2]);
8897 regno = REGNO (operands[1]);
8898
8899 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8900 to = force_reg (SImode, XEXP (operands[0], 0));
8901 op0 = replace_equiv_address (operands[0], to);
8902
8903 XVECEXP (operands[3], 0, 0)
8904 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8905 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8906 gen_rtx_SCRATCH (SImode));
8907
8908 for (i = 1; i < count; i++)
8909 XVECEXP (operands[3], 0, i + 1)
8910 = gen_rtx_SET (VOIDmode,
8911 adjust_address_nv (op0, SImode, i * 4),
8912 gen_rtx_REG (SImode, regno + i));
8913 }")
8914
8915 (define_insn "*stmsi8"
8916 [(match_parallel 0 "store_multiple_operation"
8917 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8918 (match_operand:SI 2 "gpc_reg_operand" "r"))
8919 (clobber (match_scratch:SI 3 "=X"))
8920 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8921 (match_operand:SI 4 "gpc_reg_operand" "r"))
8922 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8923 (match_operand:SI 5 "gpc_reg_operand" "r"))
8924 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8925 (match_operand:SI 6 "gpc_reg_operand" "r"))
8926 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8927 (match_operand:SI 7 "gpc_reg_operand" "r"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8929 (match_operand:SI 8 "gpc_reg_operand" "r"))
8930 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8931 (match_operand:SI 9 "gpc_reg_operand" "r"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8933 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8934 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
8935 "stswi %2,%1,%O0"
8936 [(set_attr "type" "store_ux")
8937 (set_attr "cell_micro" "always")])
8938
8939 (define_insn "*stmsi7"
8940 [(match_parallel 0 "store_multiple_operation"
8941 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8942 (match_operand:SI 2 "gpc_reg_operand" "r"))
8943 (clobber (match_scratch:SI 3 "=X"))
8944 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8945 (match_operand:SI 4 "gpc_reg_operand" "r"))
8946 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8947 (match_operand:SI 5 "gpc_reg_operand" "r"))
8948 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8949 (match_operand:SI 6 "gpc_reg_operand" "r"))
8950 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8951 (match_operand:SI 7 "gpc_reg_operand" "r"))
8952 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8953 (match_operand:SI 8 "gpc_reg_operand" "r"))
8954 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8955 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8956 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8957 "stswi %2,%1,%O0"
8958 [(set_attr "type" "store_ux")
8959 (set_attr "cell_micro" "always")])
8960
8961 (define_insn "*stmsi6"
8962 [(match_parallel 0 "store_multiple_operation"
8963 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8964 (match_operand:SI 2 "gpc_reg_operand" "r"))
8965 (clobber (match_scratch:SI 3 "=X"))
8966 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8967 (match_operand:SI 4 "gpc_reg_operand" "r"))
8968 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8969 (match_operand:SI 5 "gpc_reg_operand" "r"))
8970 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8971 (match_operand:SI 6 "gpc_reg_operand" "r"))
8972 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8973 (match_operand:SI 7 "gpc_reg_operand" "r"))
8974 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8975 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8976 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8977 "stswi %2,%1,%O0"
8978 [(set_attr "type" "store_ux")
8979 (set_attr "cell_micro" "always")])
8980
8981 (define_insn "*stmsi5"
8982 [(match_parallel 0 "store_multiple_operation"
8983 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8984 (match_operand:SI 2 "gpc_reg_operand" "r"))
8985 (clobber (match_scratch:SI 3 "=X"))
8986 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8987 (match_operand:SI 4 "gpc_reg_operand" "r"))
8988 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8989 (match_operand:SI 5 "gpc_reg_operand" "r"))
8990 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8991 (match_operand:SI 6 "gpc_reg_operand" "r"))
8992 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8993 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8994 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8995 "stswi %2,%1,%O0"
8996 [(set_attr "type" "store_ux")
8997 (set_attr "cell_micro" "always")])
8998
8999 (define_insn "*stmsi4"
9000 [(match_parallel 0 "store_multiple_operation"
9001 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9002 (match_operand:SI 2 "gpc_reg_operand" "r"))
9003 (clobber (match_scratch:SI 3 "=X"))
9004 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9005 (match_operand:SI 4 "gpc_reg_operand" "r"))
9006 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9007 (match_operand:SI 5 "gpc_reg_operand" "r"))
9008 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9009 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9010 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9011 "stswi %2,%1,%O0"
9012 [(set_attr "type" "store_ux")
9013 (set_attr "cell_micro" "always")])
9014
9015 (define_insn "*stmsi3"
9016 [(match_parallel 0 "store_multiple_operation"
9017 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9018 (match_operand:SI 2 "gpc_reg_operand" "r"))
9019 (clobber (match_scratch:SI 3 "=X"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9021 (match_operand:SI 4 "gpc_reg_operand" "r"))
9022 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9023 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9024 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9025 "stswi %2,%1,%O0"
9026 [(set_attr "type" "store_ux")
9027 (set_attr "cell_micro" "always")])
9028 \f
9029 (define_expand "setmemsi"
9030 [(parallel [(set (match_operand:BLK 0 "" "")
9031 (match_operand 2 "const_int_operand" ""))
9032 (use (match_operand:SI 1 "" ""))
9033 (use (match_operand:SI 3 "" ""))])]
9034 ""
9035 "
9036 {
9037 /* If value to set is not zero, use the library routine. */
9038 if (operands[2] != const0_rtx)
9039 FAIL;
9040
9041 if (expand_block_clear (operands))
9042 DONE;
9043 else
9044 FAIL;
9045 }")
9046
9047 ;; String/block move insn.
9048 ;; Argument 0 is the destination
9049 ;; Argument 1 is the source
9050 ;; Argument 2 is the length
9051 ;; Argument 3 is the alignment
9052
9053 (define_expand "movmemsi"
9054 [(parallel [(set (match_operand:BLK 0 "" "")
9055 (match_operand:BLK 1 "" ""))
9056 (use (match_operand:SI 2 "" ""))
9057 (use (match_operand:SI 3 "" ""))])]
9058 ""
9059 "
9060 {
9061 if (expand_block_move (operands))
9062 DONE;
9063 else
9064 FAIL;
9065 }")
9066
9067 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9068 ;; register allocator doesn't have a clue about allocating 8 word registers.
9069 ;; rD/rS = r5 is preferred, efficient form.
9070 (define_expand "movmemsi_8reg"
9071 [(parallel [(set (match_operand 0 "" "")
9072 (match_operand 1 "" ""))
9073 (use (match_operand 2 "" ""))
9074 (use (match_operand 3 "" ""))
9075 (clobber (reg:SI 5))
9076 (clobber (reg:SI 6))
9077 (clobber (reg:SI 7))
9078 (clobber (reg:SI 8))
9079 (clobber (reg:SI 9))
9080 (clobber (reg:SI 10))
9081 (clobber (reg:SI 11))
9082 (clobber (reg:SI 12))
9083 (clobber (match_scratch:SI 4 ""))])]
9084 "TARGET_STRING"
9085 "")
9086
9087 (define_insn ""
9088 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9089 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9090 (use (match_operand:SI 2 "immediate_operand" "i"))
9091 (use (match_operand:SI 3 "immediate_operand" "i"))
9092 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9093 (clobber (reg:SI 6))
9094 (clobber (reg:SI 7))
9095 (clobber (reg:SI 8))
9096 (clobber (reg:SI 9))
9097 (clobber (reg:SI 10))
9098 (clobber (reg:SI 11))
9099 (clobber (reg:SI 12))
9100 (clobber (match_scratch:SI 5 "=X"))]
9101 "TARGET_STRING
9102 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9103 || INTVAL (operands[2]) == 0)
9104 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9105 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9106 && REGNO (operands[4]) == 5"
9107 "lswi %4,%1,%2\;stswi %4,%0,%2"
9108 [(set_attr "type" "store_ux")
9109 (set_attr "cell_micro" "always")
9110 (set_attr "length" "8")])
9111
9112 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9113 ;; register allocator doesn't have a clue about allocating 6 word registers.
9114 ;; rD/rS = r5 is preferred, efficient form.
9115 (define_expand "movmemsi_6reg"
9116 [(parallel [(set (match_operand 0 "" "")
9117 (match_operand 1 "" ""))
9118 (use (match_operand 2 "" ""))
9119 (use (match_operand 3 "" ""))
9120 (clobber (reg:SI 5))
9121 (clobber (reg:SI 6))
9122 (clobber (reg:SI 7))
9123 (clobber (reg:SI 8))
9124 (clobber (reg:SI 9))
9125 (clobber (reg:SI 10))
9126 (clobber (match_scratch:SI 4 ""))])]
9127 "TARGET_STRING"
9128 "")
9129
9130 (define_insn ""
9131 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9132 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9133 (use (match_operand:SI 2 "immediate_operand" "i"))
9134 (use (match_operand:SI 3 "immediate_operand" "i"))
9135 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9136 (clobber (reg:SI 6))
9137 (clobber (reg:SI 7))
9138 (clobber (reg:SI 8))
9139 (clobber (reg:SI 9))
9140 (clobber (reg:SI 10))
9141 (clobber (match_scratch:SI 5 "=X"))]
9142 "TARGET_STRING
9143 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9144 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9145 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9146 && REGNO (operands[4]) == 5"
9147 "lswi %4,%1,%2\;stswi %4,%0,%2"
9148 [(set_attr "type" "store_ux")
9149 (set_attr "cell_micro" "always")
9150 (set_attr "length" "8")])
9151
9152 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9153 ;; problems with TImode.
9154 ;; rD/rS = r5 is preferred, efficient form.
9155 (define_expand "movmemsi_4reg"
9156 [(parallel [(set (match_operand 0 "" "")
9157 (match_operand 1 "" ""))
9158 (use (match_operand 2 "" ""))
9159 (use (match_operand 3 "" ""))
9160 (clobber (reg:SI 5))
9161 (clobber (reg:SI 6))
9162 (clobber (reg:SI 7))
9163 (clobber (reg:SI 8))
9164 (clobber (match_scratch:SI 4 ""))])]
9165 "TARGET_STRING"
9166 "")
9167
9168 (define_insn ""
9169 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9170 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9171 (use (match_operand:SI 2 "immediate_operand" "i"))
9172 (use (match_operand:SI 3 "immediate_operand" "i"))
9173 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9174 (clobber (reg:SI 6))
9175 (clobber (reg:SI 7))
9176 (clobber (reg:SI 8))
9177 (clobber (match_scratch:SI 5 "=X"))]
9178 "TARGET_STRING
9179 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9180 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9181 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9182 && REGNO (operands[4]) == 5"
9183 "lswi %4,%1,%2\;stswi %4,%0,%2"
9184 [(set_attr "type" "store_ux")
9185 (set_attr "cell_micro" "always")
9186 (set_attr "length" "8")])
9187
9188 ;; Move up to 8 bytes at a time.
9189 (define_expand "movmemsi_2reg"
9190 [(parallel [(set (match_operand 0 "" "")
9191 (match_operand 1 "" ""))
9192 (use (match_operand 2 "" ""))
9193 (use (match_operand 3 "" ""))
9194 (clobber (match_scratch:DI 4 ""))
9195 (clobber (match_scratch:SI 5 ""))])]
9196 "TARGET_STRING && ! TARGET_POWERPC64"
9197 "")
9198
9199 (define_insn ""
9200 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9201 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9202 (use (match_operand:SI 2 "immediate_operand" "i"))
9203 (use (match_operand:SI 3 "immediate_operand" "i"))
9204 (clobber (match_scratch:DI 4 "=&r"))
9205 (clobber (match_scratch:SI 5 "=X"))]
9206 "TARGET_STRING && ! TARGET_POWERPC64
9207 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9208 "lswi %4,%1,%2\;stswi %4,%0,%2"
9209 [(set_attr "type" "store_ux")
9210 (set_attr "cell_micro" "always")
9211 (set_attr "length" "8")])
9212
9213 ;; Move up to 4 bytes at a time.
9214 (define_expand "movmemsi_1reg"
9215 [(parallel [(set (match_operand 0 "" "")
9216 (match_operand 1 "" ""))
9217 (use (match_operand 2 "" ""))
9218 (use (match_operand 3 "" ""))
9219 (clobber (match_scratch:SI 4 ""))
9220 (clobber (match_scratch:SI 5 ""))])]
9221 "TARGET_STRING"
9222 "")
9223
9224 (define_insn ""
9225 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9226 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9227 (use (match_operand:SI 2 "immediate_operand" "i"))
9228 (use (match_operand:SI 3 "immediate_operand" "i"))
9229 (clobber (match_scratch:SI 4 "=&r"))
9230 (clobber (match_scratch:SI 5 "=X"))]
9231 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9232 "lswi %4,%1,%2\;stswi %4,%0,%2"
9233 [(set_attr "type" "store_ux")
9234 (set_attr "cell_micro" "always")
9235 (set_attr "length" "8")])
9236 \f
9237 ;; Define insns that do load or store with update. Some of these we can
9238 ;; get by using pre-decrement or pre-increment, but the hardware can also
9239 ;; do cases where the increment is not the size of the object.
9240 ;;
9241 ;; In all these cases, we use operands 0 and 1 for the register being
9242 ;; incremented because those are the operands that local-alloc will
9243 ;; tie and these are the pair most likely to be tieable (and the ones
9244 ;; that will benefit the most).
9245
9246 (define_insn "*movdi_update1"
9247 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9248 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9249 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9250 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9251 (plus:DI (match_dup 1) (match_dup 2)))]
9252 "TARGET_POWERPC64 && TARGET_UPDATE
9253 && (!avoiding_indexed_address_p (DImode)
9254 || !gpc_reg_operand (operands[2], DImode))"
9255 "@
9256 ldux %3,%0,%2
9257 ldu %3,%2(%0)"
9258 [(set_attr "type" "load_ux,load_u")])
9259
9260 (define_insn "movdi_<mode>_update"
9261 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9262 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9263 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9264 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9265 (plus:P (match_dup 1) (match_dup 2)))]
9266 "TARGET_POWERPC64 && TARGET_UPDATE
9267 && (!avoiding_indexed_address_p (Pmode)
9268 || !gpc_reg_operand (operands[2], Pmode)
9269 || (REG_P (operands[0])
9270 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9271 "@
9272 stdux %3,%0,%2
9273 stdu %3,%2(%0)"
9274 [(set_attr "type" "store_ux,store_u")])
9275
9276 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9277 ;; needed for stack allocation, even if the user passes -mno-update.
9278 (define_insn "movdi_<mode>_update_stack"
9279 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9280 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9281 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9282 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9283 (plus:P (match_dup 1) (match_dup 2)))]
9284 "TARGET_POWERPC64"
9285 "@
9286 stdux %3,%0,%2
9287 stdu %3,%2(%0)"
9288 [(set_attr "type" "store_ux,store_u")])
9289
9290 (define_insn "*movsi_update1"
9291 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9292 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9293 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9294 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9295 (plus:SI (match_dup 1) (match_dup 2)))]
9296 "TARGET_UPDATE
9297 && (!avoiding_indexed_address_p (SImode)
9298 || !gpc_reg_operand (operands[2], SImode))"
9299 "@
9300 lwzux %3,%0,%2
9301 lwzu %3,%2(%0)"
9302 [(set_attr "type" "load_ux,load_u")])
9303
9304 (define_insn "*movsi_update2"
9305 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9306 (sign_extend:DI
9307 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9308 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9309 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9310 (plus:DI (match_dup 1) (match_dup 2)))]
9311 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9312 && !avoiding_indexed_address_p (DImode)"
9313 "lwaux %3,%0,%2"
9314 [(set_attr "type" "load_ext_ux")])
9315
9316 (define_insn "movsi_update"
9317 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9318 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9319 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9320 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9321 (plus:SI (match_dup 1) (match_dup 2)))]
9322 "TARGET_UPDATE
9323 && (!avoiding_indexed_address_p (SImode)
9324 || !gpc_reg_operand (operands[2], SImode)
9325 || (REG_P (operands[0])
9326 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9327 "@
9328 stwux %3,%0,%2
9329 stwu %3,%2(%0)"
9330 [(set_attr "type" "store_ux,store_u")])
9331
9332 ;; This is an unconditional pattern; needed for stack allocation, even
9333 ;; if the user passes -mno-update.
9334 (define_insn "movsi_update_stack"
9335 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9336 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9337 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9338 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9339 (plus:SI (match_dup 1) (match_dup 2)))]
9340 ""
9341 "@
9342 stwux %3,%0,%2
9343 stwu %3,%2(%0)"
9344 [(set_attr "type" "store_ux,store_u")])
9345
9346 (define_insn "*movhi_update1"
9347 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9348 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9349 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9350 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9351 (plus:SI (match_dup 1) (match_dup 2)))]
9352 "TARGET_UPDATE
9353 && (!avoiding_indexed_address_p (SImode)
9354 || !gpc_reg_operand (operands[2], SImode))"
9355 "@
9356 lhzux %3,%0,%2
9357 lhzu %3,%2(%0)"
9358 [(set_attr "type" "load_ux,load_u")])
9359
9360 (define_insn "*movhi_update2"
9361 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9362 (zero_extend:SI
9363 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9364 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9365 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9366 (plus:SI (match_dup 1) (match_dup 2)))]
9367 "TARGET_UPDATE
9368 && (!avoiding_indexed_address_p (SImode)
9369 || !gpc_reg_operand (operands[2], SImode))"
9370 "@
9371 lhzux %3,%0,%2
9372 lhzu %3,%2(%0)"
9373 [(set_attr "type" "load_ux,load_u")])
9374
9375 (define_insn "*movhi_update3"
9376 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9377 (sign_extend:SI
9378 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9379 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9380 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9381 (plus:SI (match_dup 1) (match_dup 2)))]
9382 "TARGET_UPDATE && rs6000_gen_cell_microcode
9383 && (!avoiding_indexed_address_p (SImode)
9384 || !gpc_reg_operand (operands[2], SImode))"
9385 "@
9386 lhaux %3,%0,%2
9387 lhau %3,%2(%0)"
9388 [(set_attr "type" "load_ext_ux,load_ext_u")])
9389
9390 (define_insn "*movhi_update4"
9391 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9392 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9393 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9394 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9395 (plus:SI (match_dup 1) (match_dup 2)))]
9396 "TARGET_UPDATE
9397 && (!avoiding_indexed_address_p (SImode)
9398 || !gpc_reg_operand (operands[2], SImode))"
9399 "@
9400 sthux %3,%0,%2
9401 sthu %3,%2(%0)"
9402 [(set_attr "type" "store_ux,store_u")])
9403
9404 (define_insn "*movqi_update1"
9405 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9406 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9407 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9408 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9409 (plus:SI (match_dup 1) (match_dup 2)))]
9410 "TARGET_UPDATE
9411 && (!avoiding_indexed_address_p (SImode)
9412 || !gpc_reg_operand (operands[2], SImode))"
9413 "@
9414 lbzux %3,%0,%2
9415 lbzu %3,%2(%0)"
9416 [(set_attr "type" "load_ux,load_u")])
9417
9418 (define_insn "*movqi_update2"
9419 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9420 (zero_extend:SI
9421 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9422 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9423 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9424 (plus:SI (match_dup 1) (match_dup 2)))]
9425 "TARGET_UPDATE
9426 && (!avoiding_indexed_address_p (SImode)
9427 || !gpc_reg_operand (operands[2], SImode))"
9428 "@
9429 lbzux %3,%0,%2
9430 lbzu %3,%2(%0)"
9431 [(set_attr "type" "load_ux,load_u")])
9432
9433 (define_insn "*movqi_update3"
9434 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9435 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9436 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9437 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9438 (plus:SI (match_dup 1) (match_dup 2)))]
9439 "TARGET_UPDATE
9440 && (!avoiding_indexed_address_p (SImode)
9441 || !gpc_reg_operand (operands[2], SImode))"
9442 "@
9443 stbux %3,%0,%2
9444 stbu %3,%2(%0)"
9445 [(set_attr "type" "store_ux,store_u")])
9446
9447 (define_insn "*movsf_update1"
9448 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9449 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9450 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9451 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9452 (plus:SI (match_dup 1) (match_dup 2)))]
9453 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9454 && (!avoiding_indexed_address_p (SImode)
9455 || !gpc_reg_operand (operands[2], SImode))"
9456 "@
9457 lfsux %3,%0,%2
9458 lfsu %3,%2(%0)"
9459 [(set_attr "type" "fpload_ux,fpload_u")])
9460
9461 (define_insn "*movsf_update2"
9462 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9463 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9464 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9465 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9466 (plus:SI (match_dup 1) (match_dup 2)))]
9467 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9468 && (!avoiding_indexed_address_p (SImode)
9469 || !gpc_reg_operand (operands[2], SImode))"
9470 "@
9471 stfsux %3,%0,%2
9472 stfsu %3,%2(%0)"
9473 [(set_attr "type" "fpstore_ux,fpstore_u")])
9474
9475 (define_insn "*movsf_update3"
9476 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9477 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9478 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9479 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9480 (plus:SI (match_dup 1) (match_dup 2)))]
9481 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9482 && (!avoiding_indexed_address_p (SImode)
9483 || !gpc_reg_operand (operands[2], SImode))"
9484 "@
9485 lwzux %3,%0,%2
9486 lwzu %3,%2(%0)"
9487 [(set_attr "type" "load_ux,load_u")])
9488
9489 (define_insn "*movsf_update4"
9490 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9491 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9492 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9493 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9494 (plus:SI (match_dup 1) (match_dup 2)))]
9495 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9496 && (!avoiding_indexed_address_p (SImode)
9497 || !gpc_reg_operand (operands[2], SImode))"
9498 "@
9499 stwux %3,%0,%2
9500 stwu %3,%2(%0)"
9501 [(set_attr "type" "store_ux,store_u")])
9502
9503 (define_insn "*movdf_update1"
9504 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9505 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9506 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9507 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9508 (plus:SI (match_dup 1) (match_dup 2)))]
9509 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9510 && (!avoiding_indexed_address_p (SImode)
9511 || !gpc_reg_operand (operands[2], SImode))"
9512 "@
9513 lfdux %3,%0,%2
9514 lfdu %3,%2(%0)"
9515 [(set_attr "type" "fpload_ux,fpload_u")])
9516
9517 (define_insn "*movdf_update2"
9518 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9519 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9520 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9521 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9522 (plus:SI (match_dup 1) (match_dup 2)))]
9523 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9524 && (!avoiding_indexed_address_p (SImode)
9525 || !gpc_reg_operand (operands[2], SImode))"
9526 "@
9527 stfdux %3,%0,%2
9528 stfdu %3,%2(%0)"
9529 [(set_attr "type" "fpstore_ux,fpstore_u")])
9530
9531
9532 ;; After inserting conditional returns we can sometimes have
9533 ;; unnecessary register moves. Unfortunately we cannot have a
9534 ;; modeless peephole here, because some single SImode sets have early
9535 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9536 ;; sequences, using get_attr_length here will smash the operands
9537 ;; array. Neither is there an early_cobbler_p predicate.
9538 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9539 (define_peephole2
9540 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9541 (match_operand:DF 1 "any_operand" ""))
9542 (set (match_operand:DF 2 "gpc_reg_operand" "")
9543 (match_dup 0))]
9544 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9545 && peep2_reg_dead_p (2, operands[0])"
9546 [(set (match_dup 2) (match_dup 1))])
9547
9548 (define_peephole2
9549 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9550 (match_operand:SF 1 "any_operand" ""))
9551 (set (match_operand:SF 2 "gpc_reg_operand" "")
9552 (match_dup 0))]
9553 "peep2_reg_dead_p (2, operands[0])"
9554 [(set (match_dup 2) (match_dup 1))])
9555
9556 \f
9557 ;; TLS support.
9558
9559 ;; Mode attributes for different ABIs.
9560 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9561 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9562 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9563 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9564
9565 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9566 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9567 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9568 (match_operand 4 "" "g")))
9569 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9570 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9571 UNSPEC_TLSGD)
9572 (clobber (reg:SI LR_REGNO))]
9573 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9574 {
9575 if (TARGET_CMODEL != CMODEL_SMALL)
9576 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9577 "bl %z3\;nop";
9578 else
9579 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9580 }
9581 "&& TARGET_TLS_MARKERS"
9582 [(set (match_dup 0)
9583 (unspec:TLSmode [(match_dup 1)
9584 (match_dup 2)]
9585 UNSPEC_TLSGD))
9586 (parallel [(set (match_dup 0)
9587 (call (mem:TLSmode (match_dup 3))
9588 (match_dup 4)))
9589 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9590 (clobber (reg:SI LR_REGNO))])]
9591 ""
9592 [(set_attr "type" "two")
9593 (set (attr "length")
9594 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9595 (const_int 16)
9596 (const_int 12)))])
9597
9598 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9599 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9600 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9601 (match_operand 4 "" "g")))
9602 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9603 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9604 UNSPEC_TLSGD)
9605 (clobber (reg:SI LR_REGNO))]
9606 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9607 {
9608 if (flag_pic)
9609 {
9610 if (TARGET_SECURE_PLT && flag_pic == 2)
9611 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9612 else
9613 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9614 }
9615 else
9616 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9617 }
9618 "&& TARGET_TLS_MARKERS"
9619 [(set (match_dup 0)
9620 (unspec:TLSmode [(match_dup 1)
9621 (match_dup 2)]
9622 UNSPEC_TLSGD))
9623 (parallel [(set (match_dup 0)
9624 (call (mem:TLSmode (match_dup 3))
9625 (match_dup 4)))
9626 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9627 (clobber (reg:SI LR_REGNO))])]
9628 ""
9629 [(set_attr "type" "two")
9630 (set_attr "length" "8")])
9631
9632 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9633 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9634 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9635 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9636 UNSPEC_TLSGD))]
9637 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9638 "addi %0,%1,%2@got@tlsgd"
9639 "&& TARGET_CMODEL != CMODEL_SMALL"
9640 [(set (match_dup 3)
9641 (high:TLSmode
9642 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9643 (set (match_dup 0)
9644 (lo_sum:TLSmode (match_dup 3)
9645 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
9646 "
9647 {
9648 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9649 }"
9650 [(set (attr "length")
9651 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9652 (const_int 8)
9653 (const_int 4)))])
9654
9655 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9656 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9657 (high:TLSmode
9658 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9659 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9660 UNSPEC_TLSGD)))]
9661 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9662 "addis %0,%1,%2@got@tlsgd@ha"
9663 [(set_attr "length" "4")])
9664
9665 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9666 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9667 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9668 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9669 UNSPEC_TLSGD)))]
9670 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9671 "addi %0,%1,%2@got@tlsgd@l"
9672 [(set_attr "length" "4")])
9673
9674 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9675 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9676 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9677 (match_operand 2 "" "g")))
9678 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9679 UNSPEC_TLSGD)
9680 (clobber (reg:SI LR_REGNO))]
9681 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9682 "bl %z1(%3@tlsgd)\;nop"
9683 [(set_attr "type" "branch")
9684 (set_attr "length" "8")])
9685
9686 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9687 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9688 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9689 (match_operand 2 "" "g")))
9690 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9691 UNSPEC_TLSGD)
9692 (clobber (reg:SI LR_REGNO))]
9693 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9694 {
9695 if (flag_pic)
9696 {
9697 if (TARGET_SECURE_PLT && flag_pic == 2)
9698 return "bl %z1+32768(%3@tlsgd)@plt";
9699 return "bl %z1(%3@tlsgd)@plt";
9700 }
9701 return "bl %z1(%3@tlsgd)";
9702 }
9703 [(set_attr "type" "branch")
9704 (set_attr "length" "4")])
9705
9706 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9707 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9708 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9709 (match_operand 3 "" "g")))
9710 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9711 UNSPEC_TLSLD)
9712 (clobber (reg:SI LR_REGNO))]
9713 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9714 {
9715 if (TARGET_CMODEL != CMODEL_SMALL)
9716 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9717 "bl %z2\;nop";
9718 else
9719 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9720 }
9721 "&& TARGET_TLS_MARKERS"
9722 [(set (match_dup 0)
9723 (unspec:TLSmode [(match_dup 1)]
9724 UNSPEC_TLSLD))
9725 (parallel [(set (match_dup 0)
9726 (call (mem:TLSmode (match_dup 2))
9727 (match_dup 3)))
9728 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9729 (clobber (reg:SI LR_REGNO))])]
9730 ""
9731 [(set_attr "type" "two")
9732 (set (attr "length")
9733 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9734 (const_int 16)
9735 (const_int 12)))])
9736
9737 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
9738 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9739 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9740 (match_operand 3 "" "g")))
9741 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9742 UNSPEC_TLSLD)
9743 (clobber (reg:SI LR_REGNO))]
9744 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9745 {
9746 if (flag_pic)
9747 {
9748 if (TARGET_SECURE_PLT && flag_pic == 2)
9749 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
9750 else
9751 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
9752 }
9753 else
9754 return "addi %0,%1,%&@got@tlsld\;bl %z2";
9755 }
9756 "&& TARGET_TLS_MARKERS"
9757 [(set (match_dup 0)
9758 (unspec:TLSmode [(match_dup 1)]
9759 UNSPEC_TLSLD))
9760 (parallel [(set (match_dup 0)
9761 (call (mem:TLSmode (match_dup 2))
9762 (match_dup 3)))
9763 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9764 (clobber (reg:SI LR_REGNO))])]
9765 ""
9766 [(set_attr "length" "8")])
9767
9768 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
9769 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9770 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9771 UNSPEC_TLSLD))]
9772 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9773 "addi %0,%1,%&@got@tlsld"
9774 "&& TARGET_CMODEL != CMODEL_SMALL"
9775 [(set (match_dup 2)
9776 (high:TLSmode
9777 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
9778 (set (match_dup 0)
9779 (lo_sum:TLSmode (match_dup 2)
9780 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9781 "
9782 {
9783 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9784 }"
9785 [(set (attr "length")
9786 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9787 (const_int 8)
9788 (const_int 4)))])
9789
9790 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
9791 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9792 (high:TLSmode
9793 (unspec:TLSmode [(const_int 0)
9794 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9795 UNSPEC_TLSLD)))]
9796 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9797 "addis %0,%1,%&@got@tlsld@ha"
9798 [(set_attr "length" "4")])
9799
9800 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
9801 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9802 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9803 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9804 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9805 "addi %0,%1,%&@got@tlsld@l"
9806 [(set_attr "length" "4")])
9807
9808 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
9809 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9810 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9811 (match_operand 2 "" "g")))
9812 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9813 (clobber (reg:SI LR_REGNO))]
9814 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9815 "bl %z1(%&@tlsld)\;nop"
9816 [(set_attr "type" "branch")
9817 (set_attr "length" "8")])
9818
9819 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
9820 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9821 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9822 (match_operand 2 "" "g")))
9823 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9824 (clobber (reg:SI LR_REGNO))]
9825 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9826 {
9827 if (flag_pic)
9828 {
9829 if (TARGET_SECURE_PLT && flag_pic == 2)
9830 return "bl %z1+32768(%&@tlsld)@plt";
9831 return "bl %z1(%&@tlsld)@plt";
9832 }
9833 return "bl %z1(%&@tlsld)";
9834 }
9835 [(set_attr "type" "branch")
9836 (set_attr "length" "4")])
9837
9838 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
9839 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9840 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9841 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9842 UNSPEC_TLSDTPREL))]
9843 "HAVE_AS_TLS"
9844 "addi %0,%1,%2@dtprel")
9845
9846 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
9847 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9848 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9849 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9850 UNSPEC_TLSDTPRELHA))]
9851 "HAVE_AS_TLS"
9852 "addis %0,%1,%2@dtprel@ha")
9853
9854 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
9855 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9856 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9857 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9858 UNSPEC_TLSDTPRELLO))]
9859 "HAVE_AS_TLS"
9860 "addi %0,%1,%2@dtprel@l")
9861
9862 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
9863 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9864 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9865 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9866 UNSPEC_TLSGOTDTPREL))]
9867 "HAVE_AS_TLS"
9868 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
9869 "&& TARGET_CMODEL != CMODEL_SMALL"
9870 [(set (match_dup 3)
9871 (high:TLSmode
9872 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
9873 (set (match_dup 0)
9874 (lo_sum:TLSmode (match_dup 3)
9875 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
9876 "
9877 {
9878 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9879 }"
9880 [(set (attr "length")
9881 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9882 (const_int 8)
9883 (const_int 4)))])
9884
9885 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
9886 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9887 (high:TLSmode
9888 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9889 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9890 UNSPEC_TLSGOTDTPREL)))]
9891 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9892 "addis %0,%1,%2@got@dtprel@ha"
9893 [(set_attr "length" "4")])
9894
9895 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
9896 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9897 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9898 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9899 UNSPEC_TLSGOTDTPREL)))]
9900 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9901 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
9902 [(set_attr "length" "4")])
9903
9904 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
9905 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9906 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9907 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9908 UNSPEC_TLSTPREL))]
9909 "HAVE_AS_TLS"
9910 "addi %0,%1,%2@tprel")
9911
9912 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
9913 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9914 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9915 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9916 UNSPEC_TLSTPRELHA))]
9917 "HAVE_AS_TLS"
9918 "addis %0,%1,%2@tprel@ha")
9919
9920 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
9921 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9922 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9923 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9924 UNSPEC_TLSTPRELLO))]
9925 "HAVE_AS_TLS"
9926 "addi %0,%1,%2@tprel@l")
9927
9928 ;; "b" output constraint here and on tls_tls input to support linker tls
9929 ;; optimization. The linker may edit the instructions emitted by a
9930 ;; tls_got_tprel/tls_tls pair to addis,addi.
9931 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
9932 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9933 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9934 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9935 UNSPEC_TLSGOTTPREL))]
9936 "HAVE_AS_TLS"
9937 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
9938 "&& TARGET_CMODEL != CMODEL_SMALL"
9939 [(set (match_dup 3)
9940 (high:TLSmode
9941 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
9942 (set (match_dup 0)
9943 (lo_sum:TLSmode (match_dup 3)
9944 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
9945 "
9946 {
9947 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9948 }"
9949 [(set (attr "length")
9950 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9951 (const_int 8)
9952 (const_int 4)))])
9953
9954 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
9955 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9956 (high:TLSmode
9957 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9958 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9959 UNSPEC_TLSGOTTPREL)))]
9960 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9961 "addis %0,%1,%2@got@tprel@ha"
9962 [(set_attr "length" "4")])
9963
9964 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
9965 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9966 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9967 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9968 UNSPEC_TLSGOTTPREL)))]
9969 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9970 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
9971 [(set_attr "length" "4")])
9972
9973 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
9974 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9975 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9976 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9977 UNSPEC_TLSTLS))]
9978 "HAVE_AS_TLS"
9979 "add %0,%1,%2@tls")
9980 \f
9981 ;; Next come insns related to the calling sequence.
9982 ;;
9983 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9984 ;; We move the back-chain and decrement the stack pointer.
9985
9986 (define_expand "allocate_stack"
9987 [(set (match_operand 0 "gpc_reg_operand" "")
9988 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9989 (set (reg 1)
9990 (minus (reg 1) (match_dup 1)))]
9991 ""
9992 "
9993 { rtx chain = gen_reg_rtx (Pmode);
9994 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9995 rtx neg_op0;
9996 rtx insn, par, set, mem;
9997
9998 emit_move_insn (chain, stack_bot);
9999
10000 /* Check stack bounds if necessary. */
10001 if (crtl->limit_stack)
10002 {
10003 rtx available;
10004 available = expand_binop (Pmode, sub_optab,
10005 stack_pointer_rtx, stack_limit_rtx,
10006 NULL_RTX, 1, OPTAB_WIDEN);
10007 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10008 }
10009
10010 if (GET_CODE (operands[1]) != CONST_INT
10011 || INTVAL (operands[1]) < -32767
10012 || INTVAL (operands[1]) > 32768)
10013 {
10014 neg_op0 = gen_reg_rtx (Pmode);
10015 if (TARGET_32BIT)
10016 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10017 else
10018 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10019 }
10020 else
10021 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10022
10023 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10024 : gen_movdi_di_update_stack))
10025 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10026 chain));
10027 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10028 it now and set the alias set/attributes. The above gen_*_update
10029 calls will generate a PARALLEL with the MEM set being the first
10030 operation. */
10031 par = PATTERN (insn);
10032 gcc_assert (GET_CODE (par) == PARALLEL);
10033 set = XVECEXP (par, 0, 0);
10034 gcc_assert (GET_CODE (set) == SET);
10035 mem = SET_DEST (set);
10036 gcc_assert (MEM_P (mem));
10037 MEM_NOTRAP_P (mem) = 1;
10038 set_mem_alias_set (mem, get_frame_alias_set ());
10039
10040 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10041 DONE;
10042 }")
10043
10044 ;; These patterns say how to save and restore the stack pointer. We need not
10045 ;; save the stack pointer at function level since we are careful to
10046 ;; preserve the backchain. At block level, we have to restore the backchain
10047 ;; when we restore the stack pointer.
10048 ;;
10049 ;; For nonlocal gotos, we must save both the stack pointer and its
10050 ;; backchain and restore both. Note that in the nonlocal case, the
10051 ;; save area is a memory location.
10052
10053 (define_expand "save_stack_function"
10054 [(match_operand 0 "any_operand" "")
10055 (match_operand 1 "any_operand" "")]
10056 ""
10057 "DONE;")
10058
10059 (define_expand "restore_stack_function"
10060 [(match_operand 0 "any_operand" "")
10061 (match_operand 1 "any_operand" "")]
10062 ""
10063 "DONE;")
10064
10065 ;; Adjust stack pointer (op0) to a new value (op1).
10066 ;; First copy old stack backchain to new location, and ensure that the
10067 ;; scheduler won't reorder the sp assignment before the backchain write.
10068 (define_expand "restore_stack_block"
10069 [(set (match_dup 2) (match_dup 3))
10070 (set (match_dup 4) (match_dup 2))
10071 (match_dup 5)
10072 (set (match_operand 0 "register_operand" "")
10073 (match_operand 1 "register_operand" ""))]
10074 ""
10075 "
10076 {
10077 rtvec p;
10078
10079 operands[1] = force_reg (Pmode, operands[1]);
10080 operands[2] = gen_reg_rtx (Pmode);
10081 operands[3] = gen_frame_mem (Pmode, operands[0]);
10082 operands[4] = gen_frame_mem (Pmode, operands[1]);
10083 p = rtvec_alloc (1);
10084 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10085 gen_frame_mem (BLKmode, operands[0]),
10086 const0_rtx);
10087 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10088 }")
10089
10090 (define_expand "save_stack_nonlocal"
10091 [(set (match_dup 3) (match_dup 4))
10092 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10093 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10094 ""
10095 "
10096 {
10097 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10098
10099 /* Copy the backchain to the first word, sp to the second. */
10100 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10101 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10102 operands[3] = gen_reg_rtx (Pmode);
10103 operands[4] = gen_frame_mem (Pmode, operands[1]);
10104 }")
10105
10106 (define_expand "restore_stack_nonlocal"
10107 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10108 (set (match_dup 3) (match_dup 4))
10109 (set (match_dup 5) (match_dup 2))
10110 (match_dup 6)
10111 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10112 ""
10113 "
10114 {
10115 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10116 rtvec p;
10117
10118 /* Restore the backchain from the first word, sp from the second. */
10119 operands[2] = gen_reg_rtx (Pmode);
10120 operands[3] = gen_reg_rtx (Pmode);
10121 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10122 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10123 operands[5] = gen_frame_mem (Pmode, operands[3]);
10124 p = rtvec_alloc (1);
10125 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10126 gen_frame_mem (BLKmode, operands[0]),
10127 const0_rtx);
10128 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10129 }")
10130 \f
10131 ;; TOC register handling.
10132
10133 ;; Code to initialize the TOC register...
10134
10135 (define_insn "load_toc_aix_si"
10136 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10137 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10138 (use (reg:SI 2))])]
10139 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10140 "*
10141 {
10142 char buf[30];
10143 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10144 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10145 operands[2] = gen_rtx_REG (Pmode, 2);
10146 return \"lwz %0,%1(%2)\";
10147 }"
10148 [(set_attr "type" "load")])
10149
10150 (define_insn "load_toc_aix_di"
10151 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10152 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10153 (use (reg:DI 2))])]
10154 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10155 "*
10156 {
10157 char buf[30];
10158 #ifdef TARGET_RELOCATABLE
10159 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10160 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10161 #else
10162 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10163 #endif
10164 if (TARGET_ELF)
10165 strcat (buf, \"@toc\");
10166 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10167 operands[2] = gen_rtx_REG (Pmode, 2);
10168 return \"ld %0,%1(%2)\";
10169 }"
10170 [(set_attr "type" "load")])
10171
10172 (define_insn "load_toc_v4_pic_si"
10173 [(set (reg:SI LR_REGNO)
10174 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10175 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10176 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10177 [(set_attr "type" "branch")
10178 (set_attr "length" "4")])
10179
10180 (define_expand "load_toc_v4_PIC_1"
10181 [(parallel [(set (reg:SI LR_REGNO)
10182 (match_operand:SI 0 "immediate_operand" "s"))
10183 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10184 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10185 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10186 "")
10187
10188 (define_insn "load_toc_v4_PIC_1_normal"
10189 [(set (reg:SI LR_REGNO)
10190 (match_operand:SI 0 "immediate_operand" "s"))
10191 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10192 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10193 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10194 "bcl 20,31,%0\\n%0:"
10195 [(set_attr "type" "branch")
10196 (set_attr "length" "4")])
10197
10198 (define_insn "load_toc_v4_PIC_1_476"
10199 [(set (reg:SI LR_REGNO)
10200 (match_operand:SI 0 "immediate_operand" "s"))
10201 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10202 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10203 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10204 "*
10205 {
10206 char name[32];
10207 static char templ[32];
10208
10209 get_ppc476_thunk_name (name);
10210 sprintf (templ, \"bl %s\\n%%0:\", name);
10211 return templ;
10212 }"
10213 [(set_attr "type" "branch")
10214 (set_attr "length" "4")])
10215
10216 (define_expand "load_toc_v4_PIC_1b"
10217 [(parallel [(set (reg:SI LR_REGNO)
10218 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10219 (label_ref (match_operand 1 "" ""))]
10220 UNSPEC_TOCPTR))
10221 (match_dup 1)])]
10222 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10223 "")
10224
10225 (define_insn "load_toc_v4_PIC_1b_normal"
10226 [(set (reg:SI LR_REGNO)
10227 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10228 (label_ref (match_operand 1 "" ""))]
10229 UNSPEC_TOCPTR))
10230 (match_dup 1)]
10231 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10232 "bcl 20,31,$+8\;.long %0-$"
10233 [(set_attr "type" "branch")
10234 (set_attr "length" "8")])
10235
10236 (define_insn "load_toc_v4_PIC_1b_476"
10237 [(set (reg:SI LR_REGNO)
10238 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10239 (label_ref (match_operand 1 "" ""))]
10240 UNSPEC_TOCPTR))
10241 (match_dup 1)]
10242 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10243 "*
10244 {
10245 char name[32];
10246 static char templ[32];
10247
10248 get_ppc476_thunk_name (name);
10249 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10250 return templ;
10251 }"
10252 [(set_attr "type" "branch")
10253 (set_attr "length" "16")])
10254
10255 (define_insn "load_toc_v4_PIC_2"
10256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10257 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10258 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10259 (match_operand:SI 3 "immediate_operand" "s")))))]
10260 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10261 "lwz %0,%2-%3(%1)"
10262 [(set_attr "type" "load")])
10263
10264 (define_insn "load_toc_v4_PIC_3b"
10265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10266 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10267 (high:SI
10268 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10269 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10270 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10271 "addis %0,%1,%2-%3@ha")
10272
10273 (define_insn "load_toc_v4_PIC_3c"
10274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10275 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10276 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10277 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10278 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10279 "addi %0,%1,%2-%3@l")
10280
10281 ;; If the TOC is shared over a translation unit, as happens with all
10282 ;; the kinds of PIC that we support, we need to restore the TOC
10283 ;; pointer only when jumping over units of translation.
10284 ;; On Darwin, we need to reload the picbase.
10285
10286 (define_expand "builtin_setjmp_receiver"
10287 [(use (label_ref (match_operand 0 "" "")))]
10288 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10289 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10290 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10291 "
10292 {
10293 #if TARGET_MACHO
10294 if (DEFAULT_ABI == ABI_DARWIN)
10295 {
10296 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10297 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10298 rtx tmplabrtx;
10299 char tmplab[20];
10300
10301 crtl->uses_pic_offset_table = 1;
10302 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10303 CODE_LABEL_NUMBER (operands[0]));
10304 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10305
10306 emit_insn (gen_load_macho_picbase (tmplabrtx));
10307 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10308 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10309 }
10310 else
10311 #endif
10312 rs6000_emit_load_toc_table (FALSE);
10313 DONE;
10314 }")
10315
10316 ;; Largetoc support
10317 (define_insn "*largetoc_high"
10318 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10319 (high:DI
10320 (unspec [(match_operand:DI 1 "" "")
10321 (match_operand:DI 2 "gpc_reg_operand" "b")]
10322 UNSPEC_TOCREL)))]
10323 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10324 "addis %0,%2,%1@toc@ha")
10325
10326 (define_insn "*largetoc_high_aix<mode>"
10327 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10328 (high:P
10329 (unspec [(match_operand:P 1 "" "")
10330 (match_operand:P 2 "gpc_reg_operand" "b")]
10331 UNSPEC_TOCREL)))]
10332 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10333 "addis %0,%1@u(%2)")
10334
10335 (define_insn "*largetoc_high_plus"
10336 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10337 (high:DI
10338 (plus:DI
10339 (unspec [(match_operand:DI 1 "" "")
10340 (match_operand:DI 2 "gpc_reg_operand" "b")]
10341 UNSPEC_TOCREL)
10342 (match_operand 3 "const_int_operand" "n"))))]
10343 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10344 "addis %0,%2,%1+%3@toc@ha")
10345
10346 (define_insn "*largetoc_high_plus_aix<mode>"
10347 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10348 (high:P
10349 (plus:P
10350 (unspec [(match_operand:P 1 "" "")
10351 (match_operand:P 2 "gpc_reg_operand" "b")]
10352 UNSPEC_TOCREL)
10353 (match_operand 3 "const_int_operand" "n"))))]
10354 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10355 "addis %0,%1+%3@u(%2)")
10356
10357 (define_insn "*largetoc_low<mode>"
10358 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
10359 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b,!*r")
10360 (match_operand:P 2 "" "")))]
10361 "TARGET_TOC && TARGET_CMODEL != CMODEL_SMALL"
10362 "@
10363 addi %0,%1,%2@l
10364 addic %0,%1,%2@l")
10365
10366 (define_insn_and_split "*tocref<mode>"
10367 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10368 (match_operand:P 1 "small_toc_ref" "R"))]
10369 "TARGET_TOC"
10370 "la %0,%a1"
10371 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10372 [(set (match_dup 0) (high:P (match_dup 1)))
10373 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10374
10375 ;; Elf specific ways of loading addresses for non-PIC code.
10376 ;; The output of this could be r0, but we make a very strong
10377 ;; preference for a base register because it will usually
10378 ;; be needed there.
10379 (define_insn "elf_high"
10380 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10381 (high:SI (match_operand 1 "" "")))]
10382 "TARGET_ELF && ! TARGET_64BIT"
10383 "lis %0,%1@ha")
10384
10385 (define_insn "elf_low"
10386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10387 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10388 (match_operand 2 "" "")))]
10389 "TARGET_ELF && ! TARGET_64BIT"
10390 "@
10391 la %0,%2@l(%1)
10392 addic %0,%1,%K2")
10393 \f
10394 ;; Call and call_value insns
10395 (define_expand "call"
10396 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10397 (match_operand 1 "" ""))
10398 (use (match_operand 2 "" ""))
10399 (clobber (reg:SI LR_REGNO))])]
10400 ""
10401 "
10402 {
10403 #if TARGET_MACHO
10404 if (MACHOPIC_INDIRECT)
10405 operands[0] = machopic_indirect_call_target (operands[0]);
10406 #endif
10407
10408 gcc_assert (GET_CODE (operands[0]) == MEM);
10409 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10410
10411 operands[0] = XEXP (operands[0], 0);
10412
10413 if (GET_CODE (operands[0]) != SYMBOL_REF
10414 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10415 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10416 {
10417 if (INTVAL (operands[2]) & CALL_LONG)
10418 operands[0] = rs6000_longcall_ref (operands[0]);
10419
10420 switch (DEFAULT_ABI)
10421 {
10422 case ABI_V4:
10423 case ABI_DARWIN:
10424 operands[0] = force_reg (Pmode, operands[0]);
10425 break;
10426
10427 case ABI_AIX:
10428 /* AIX function pointers are really pointers to a three word
10429 area. */
10430 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
10431 DONE;
10432
10433 default:
10434 gcc_unreachable ();
10435 }
10436 }
10437 }")
10438
10439 (define_expand "call_value"
10440 [(parallel [(set (match_operand 0 "" "")
10441 (call (mem:SI (match_operand 1 "address_operand" ""))
10442 (match_operand 2 "" "")))
10443 (use (match_operand 3 "" ""))
10444 (clobber (reg:SI LR_REGNO))])]
10445 ""
10446 "
10447 {
10448 #if TARGET_MACHO
10449 if (MACHOPIC_INDIRECT)
10450 operands[1] = machopic_indirect_call_target (operands[1]);
10451 #endif
10452
10453 gcc_assert (GET_CODE (operands[1]) == MEM);
10454 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10455
10456 operands[1] = XEXP (operands[1], 0);
10457
10458 if (GET_CODE (operands[1]) != SYMBOL_REF
10459 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10460 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10461 {
10462 if (INTVAL (operands[3]) & CALL_LONG)
10463 operands[1] = rs6000_longcall_ref (operands[1]);
10464
10465 switch (DEFAULT_ABI)
10466 {
10467 case ABI_V4:
10468 case ABI_DARWIN:
10469 operands[1] = force_reg (Pmode, operands[1]);
10470 break;
10471
10472 case ABI_AIX:
10473 /* AIX function pointers are really pointers to a three word
10474 area. */
10475 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
10476 DONE;
10477
10478 default:
10479 gcc_unreachable ();
10480 }
10481 }
10482 }")
10483
10484 ;; Call to function in current module. No TOC pointer reload needed.
10485 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10486 ;; either the function was not prototyped, or it was prototyped as a
10487 ;; variable argument function. It is > 0 if FP registers were passed
10488 ;; and < 0 if they were not.
10489
10490 (define_insn "*call_local32"
10491 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10492 (match_operand 1 "" "g,g"))
10493 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10494 (clobber (reg:SI LR_REGNO))]
10495 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10496 "*
10497 {
10498 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10499 output_asm_insn (\"crxor 6,6,6\", operands);
10500
10501 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10502 output_asm_insn (\"creqv 6,6,6\", operands);
10503
10504 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10505 }"
10506 [(set_attr "type" "branch")
10507 (set_attr "length" "4,8")])
10508
10509 (define_insn "*call_local64"
10510 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10511 (match_operand 1 "" "g,g"))
10512 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10513 (clobber (reg:SI LR_REGNO))]
10514 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10515 "*
10516 {
10517 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10518 output_asm_insn (\"crxor 6,6,6\", operands);
10519
10520 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10521 output_asm_insn (\"creqv 6,6,6\", operands);
10522
10523 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10524 }"
10525 [(set_attr "type" "branch")
10526 (set_attr "length" "4,8")])
10527
10528 (define_insn "*call_value_local32"
10529 [(set (match_operand 0 "" "")
10530 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10531 (match_operand 2 "" "g,g")))
10532 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10533 (clobber (reg:SI LR_REGNO))]
10534 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10535 "*
10536 {
10537 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10538 output_asm_insn (\"crxor 6,6,6\", operands);
10539
10540 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10541 output_asm_insn (\"creqv 6,6,6\", operands);
10542
10543 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10544 }"
10545 [(set_attr "type" "branch")
10546 (set_attr "length" "4,8")])
10547
10548
10549 (define_insn "*call_value_local64"
10550 [(set (match_operand 0 "" "")
10551 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10552 (match_operand 2 "" "g,g")))
10553 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10554 (clobber (reg:SI LR_REGNO))]
10555 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10556 "*
10557 {
10558 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10559 output_asm_insn (\"crxor 6,6,6\", operands);
10560
10561 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10562 output_asm_insn (\"creqv 6,6,6\", operands);
10563
10564 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10565 }"
10566 [(set_attr "type" "branch")
10567 (set_attr "length" "4,8")])
10568
10569 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
10570 ;; Operand0 is the addresss of the function to call
10571 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10572 ;; Operand2 is the location in the function descriptor to load r2 from
10573 ;; Operand3 is the stack location to hold the current TOC pointer
10574
10575 (define_insn "call_indirect_aix<ptrsize>"
10576 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10577 (match_operand 1 "" "g,g"))
10578 (use (match_operand:P 2 "memory_operand" "m,m"))
10579 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10580 (use (reg:P STATIC_CHAIN_REGNUM))
10581 (clobber (reg:P LR_REGNO))]
10582 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10583 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10584 [(set_attr "type" "jmpreg")
10585 (set_attr "length" "12")])
10586
10587 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
10588 ;; Operand0 is the addresss of the function to call
10589 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10590 ;; Operand2 is the location in the function descriptor to load r2 from
10591 ;; Operand3 is the stack location to hold the current TOC pointer
10592
10593 (define_insn "call_indirect_aix<ptrsize>_nor11"
10594 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10595 (match_operand 1 "" "g,g"))
10596 (use (match_operand:P 2 "memory_operand" "m,m"))
10597 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10598 (clobber (reg:P LR_REGNO))]
10599 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10600 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10601 [(set_attr "type" "jmpreg")
10602 (set_attr "length" "12")])
10603
10604 ;; Operand0 is the return result of the function
10605 ;; Operand1 is the addresss of the function to call
10606 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10607 ;; Operand3 is the location in the function descriptor to load r2 from
10608 ;; Operand4 is the stack location to hold the current TOC pointer
10609
10610 (define_insn "call_value_indirect_aix<ptrsize>"
10611 [(set (match_operand 0 "" "")
10612 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10613 (match_operand 2 "" "g,g")))
10614 (use (match_operand:P 3 "memory_operand" "m,m"))
10615 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10616 (use (reg:P STATIC_CHAIN_REGNUM))
10617 (clobber (reg:P LR_REGNO))]
10618 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10619 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10620 [(set_attr "type" "jmpreg")
10621 (set_attr "length" "12")])
10622
10623 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
10624 ;; Operand0 is the return result of the function
10625 ;; Operand1 is the addresss of the function to call
10626 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10627 ;; Operand3 is the location in the function descriptor to load r2 from
10628 ;; Operand4 is the stack location to hold the current TOC pointer
10629
10630 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
10631 [(set (match_operand 0 "" "")
10632 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10633 (match_operand 2 "" "g,g")))
10634 (use (match_operand:P 3 "memory_operand" "m,m"))
10635 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10636 (clobber (reg:P LR_REGNO))]
10637 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10638 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10639 [(set_attr "type" "jmpreg")
10640 (set_attr "length" "12")])
10641
10642 ;; Call to function which may be in another module. Restore the TOC
10643 ;; pointer (r2) after the call unless this is System V.
10644 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10645 ;; either the function was not prototyped, or it was prototyped as a
10646 ;; variable argument function. It is > 0 if FP registers were passed
10647 ;; and < 0 if they were not.
10648
10649 (define_insn "*call_nonlocal_aix32"
10650 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10651 (match_operand 1 "" "g"))
10652 (use (match_operand:SI 2 "immediate_operand" "O"))
10653 (clobber (reg:SI LR_REGNO))]
10654 "TARGET_32BIT
10655 && DEFAULT_ABI == ABI_AIX
10656 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10657 "bl %z0\;nop"
10658 [(set_attr "type" "branch")
10659 (set_attr "length" "8")])
10660
10661 (define_insn "*call_nonlocal_aix64"
10662 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10663 (match_operand 1 "" "g"))
10664 (use (match_operand:SI 2 "immediate_operand" "O"))
10665 (clobber (reg:SI LR_REGNO))]
10666 "TARGET_64BIT
10667 && DEFAULT_ABI == ABI_AIX
10668 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10669 "bl %z0\;nop"
10670 [(set_attr "type" "branch")
10671 (set_attr "length" "8")])
10672
10673 (define_insn "*call_value_nonlocal_aix32"
10674 [(set (match_operand 0 "" "")
10675 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10676 (match_operand 2 "" "g")))
10677 (use (match_operand:SI 3 "immediate_operand" "O"))
10678 (clobber (reg:SI LR_REGNO))]
10679 "TARGET_32BIT
10680 && DEFAULT_ABI == ABI_AIX
10681 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10682 "bl %z1\;nop"
10683 [(set_attr "type" "branch")
10684 (set_attr "length" "8")])
10685
10686 (define_insn "*call_value_nonlocal_aix64"
10687 [(set (match_operand 0 "" "")
10688 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10689 (match_operand 2 "" "g")))
10690 (use (match_operand:SI 3 "immediate_operand" "O"))
10691 (clobber (reg:SI LR_REGNO))]
10692 "TARGET_64BIT
10693 && DEFAULT_ABI == ABI_AIX
10694 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10695 "bl %z1\;nop"
10696 [(set_attr "type" "branch")
10697 (set_attr "length" "8")])
10698
10699 ;; A function pointer under System V is just a normal pointer
10700 ;; operands[0] is the function pointer
10701 ;; operands[1] is the stack size to clean up
10702 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10703 ;; which indicates how to set cr1
10704
10705 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10706 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10707 (match_operand 1 "" "g,g,g,g"))
10708 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10709 (clobber (reg:SI LR_REGNO))]
10710 "DEFAULT_ABI == ABI_V4
10711 || DEFAULT_ABI == ABI_DARWIN"
10712 {
10713 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10714 output_asm_insn ("crxor 6,6,6", operands);
10715
10716 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10717 output_asm_insn ("creqv 6,6,6", operands);
10718
10719 return "b%T0l";
10720 }
10721 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10722 (set_attr "length" "4,4,8,8")])
10723
10724 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10725 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10726 (match_operand 1 "" "g,g"))
10727 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10728 (clobber (reg:SI LR_REGNO))]
10729 "(DEFAULT_ABI == ABI_DARWIN
10730 || (DEFAULT_ABI == ABI_V4
10731 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10732 {
10733 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10734 output_asm_insn ("crxor 6,6,6", operands);
10735
10736 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10737 output_asm_insn ("creqv 6,6,6", operands);
10738
10739 #if TARGET_MACHO
10740 return output_call(insn, operands, 0, 2);
10741 #else
10742 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10743 {
10744 gcc_assert (!TARGET_SECURE_PLT);
10745 return "bl %z0@plt";
10746 }
10747 else
10748 return "bl %z0";
10749 #endif
10750 }
10751 "DEFAULT_ABI == ABI_V4
10752 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10753 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10754 [(parallel [(call (mem:SI (match_dup 0))
10755 (match_dup 1))
10756 (use (match_dup 2))
10757 (use (match_dup 3))
10758 (clobber (reg:SI LR_REGNO))])]
10759 {
10760 operands[3] = pic_offset_table_rtx;
10761 }
10762 [(set_attr "type" "branch,branch")
10763 (set_attr "length" "4,8")])
10764
10765 (define_insn "*call_nonlocal_sysv_secure<mode>"
10766 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10767 (match_operand 1 "" "g,g"))
10768 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10769 (use (match_operand:SI 3 "register_operand" "r,r"))
10770 (clobber (reg:SI LR_REGNO))]
10771 "(DEFAULT_ABI == ABI_V4
10772 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10773 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10774 {
10775 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10776 output_asm_insn ("crxor 6,6,6", operands);
10777
10778 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10779 output_asm_insn ("creqv 6,6,6", operands);
10780
10781 if (flag_pic == 2)
10782 /* The magic 32768 offset here and in the other sysv call insns
10783 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10784 See sysv4.h:toc_section. */
10785 return "bl %z0+32768@plt";
10786 else
10787 return "bl %z0@plt";
10788 }
10789 [(set_attr "type" "branch,branch")
10790 (set_attr "length" "4,8")])
10791
10792 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10793 [(set (match_operand 0 "" "")
10794 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10795 (match_operand 2 "" "g,g,g,g")))
10796 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10797 (clobber (reg:SI LR_REGNO))]
10798 "DEFAULT_ABI == ABI_V4
10799 || DEFAULT_ABI == ABI_DARWIN"
10800 {
10801 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10802 output_asm_insn ("crxor 6,6,6", operands);
10803
10804 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10805 output_asm_insn ("creqv 6,6,6", operands);
10806
10807 return "b%T1l";
10808 }
10809 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10810 (set_attr "length" "4,4,8,8")])
10811
10812 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
10813 [(set (match_operand 0 "" "")
10814 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10815 (match_operand 2 "" "g,g")))
10816 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10817 (clobber (reg:SI LR_REGNO))]
10818 "(DEFAULT_ABI == ABI_DARWIN
10819 || (DEFAULT_ABI == ABI_V4
10820 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10821 {
10822 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10823 output_asm_insn ("crxor 6,6,6", operands);
10824
10825 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10826 output_asm_insn ("creqv 6,6,6", operands);
10827
10828 #if TARGET_MACHO
10829 return output_call(insn, operands, 1, 3);
10830 #else
10831 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10832 {
10833 gcc_assert (!TARGET_SECURE_PLT);
10834 return "bl %z1@plt";
10835 }
10836 else
10837 return "bl %z1";
10838 #endif
10839 }
10840 "DEFAULT_ABI == ABI_V4
10841 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10842 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10843 [(parallel [(set (match_dup 0)
10844 (call (mem:SI (match_dup 1))
10845 (match_dup 2)))
10846 (use (match_dup 3))
10847 (use (match_dup 4))
10848 (clobber (reg:SI LR_REGNO))])]
10849 {
10850 operands[4] = pic_offset_table_rtx;
10851 }
10852 [(set_attr "type" "branch,branch")
10853 (set_attr "length" "4,8")])
10854
10855 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
10856 [(set (match_operand 0 "" "")
10857 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10858 (match_operand 2 "" "g,g")))
10859 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10860 (use (match_operand:SI 4 "register_operand" "r,r"))
10861 (clobber (reg:SI LR_REGNO))]
10862 "(DEFAULT_ABI == ABI_V4
10863 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10864 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
10865 {
10866 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10867 output_asm_insn ("crxor 6,6,6", operands);
10868
10869 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10870 output_asm_insn ("creqv 6,6,6", operands);
10871
10872 if (flag_pic == 2)
10873 return "bl %z1+32768@plt";
10874 else
10875 return "bl %z1@plt";
10876 }
10877 [(set_attr "type" "branch,branch")
10878 (set_attr "length" "4,8")])
10879
10880 ;; Call subroutine returning any type.
10881 (define_expand "untyped_call"
10882 [(parallel [(call (match_operand 0 "" "")
10883 (const_int 0))
10884 (match_operand 1 "" "")
10885 (match_operand 2 "" "")])]
10886 ""
10887 "
10888 {
10889 int i;
10890
10891 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10892
10893 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10894 {
10895 rtx set = XVECEXP (operands[2], 0, i);
10896 emit_move_insn (SET_DEST (set), SET_SRC (set));
10897 }
10898
10899 /* The optimizer does not know that the call sets the function value
10900 registers we stored in the result block. We avoid problems by
10901 claiming that all hard registers are used and clobbered at this
10902 point. */
10903 emit_insn (gen_blockage ());
10904
10905 DONE;
10906 }")
10907
10908 ;; sibling call patterns
10909 (define_expand "sibcall"
10910 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10911 (match_operand 1 "" ""))
10912 (use (match_operand 2 "" ""))
10913 (use (reg:SI LR_REGNO))
10914 (simple_return)])]
10915 ""
10916 "
10917 {
10918 #if TARGET_MACHO
10919 if (MACHOPIC_INDIRECT)
10920 operands[0] = machopic_indirect_call_target (operands[0]);
10921 #endif
10922
10923 gcc_assert (GET_CODE (operands[0]) == MEM);
10924 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10925
10926 operands[0] = XEXP (operands[0], 0);
10927 }")
10928
10929 ;; this and similar patterns must be marked as using LR, otherwise
10930 ;; dataflow will try to delete the store into it. This is true
10931 ;; even when the actual reg to jump to is in CTR, when LR was
10932 ;; saved and restored around the PIC-setting BCL.
10933 (define_insn "*sibcall_local32"
10934 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10935 (match_operand 1 "" "g,g"))
10936 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10937 (use (reg:SI LR_REGNO))
10938 (simple_return)]
10939 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10940 "*
10941 {
10942 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10943 output_asm_insn (\"crxor 6,6,6\", operands);
10944
10945 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10946 output_asm_insn (\"creqv 6,6,6\", operands);
10947
10948 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10949 }"
10950 [(set_attr "type" "branch")
10951 (set_attr "length" "4,8")])
10952
10953 (define_insn "*sibcall_local64"
10954 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10955 (match_operand 1 "" "g,g"))
10956 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10957 (use (reg:SI LR_REGNO))
10958 (simple_return)]
10959 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10960 "*
10961 {
10962 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10963 output_asm_insn (\"crxor 6,6,6\", operands);
10964
10965 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10966 output_asm_insn (\"creqv 6,6,6\", operands);
10967
10968 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10969 }"
10970 [(set_attr "type" "branch")
10971 (set_attr "length" "4,8")])
10972
10973 (define_insn "*sibcall_value_local32"
10974 [(set (match_operand 0 "" "")
10975 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10976 (match_operand 2 "" "g,g")))
10977 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10978 (use (reg:SI LR_REGNO))
10979 (simple_return)]
10980 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10981 "*
10982 {
10983 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10984 output_asm_insn (\"crxor 6,6,6\", operands);
10985
10986 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10987 output_asm_insn (\"creqv 6,6,6\", operands);
10988
10989 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10990 }"
10991 [(set_attr "type" "branch")
10992 (set_attr "length" "4,8")])
10993
10994
10995 (define_insn "*sibcall_value_local64"
10996 [(set (match_operand 0 "" "")
10997 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10998 (match_operand 2 "" "g,g")))
10999 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11000 (use (reg:SI LR_REGNO))
11001 (simple_return)]
11002 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11003 "*
11004 {
11005 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11006 output_asm_insn (\"crxor 6,6,6\", operands);
11007
11008 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11009 output_asm_insn (\"creqv 6,6,6\", operands);
11010
11011 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11012 }"
11013 [(set_attr "type" "branch")
11014 (set_attr "length" "4,8")])
11015
11016 (define_insn "*sibcall_nonlocal_aix<mode>"
11017 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11018 (match_operand 1 "" "g,g"))
11019 (use (match_operand:SI 2 "immediate_operand" "O,O"))
11020 (use (reg:SI LR_REGNO))
11021 (simple_return)]
11022 "DEFAULT_ABI == ABI_AIX
11023 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11024 "@
11025 b %z0
11026 b%T0"
11027 [(set_attr "type" "branch")
11028 (set_attr "length" "4")])
11029
11030 (define_insn "*sibcall_value_nonlocal_aix<mode>"
11031 [(set (match_operand 0 "" "")
11032 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11033 (match_operand 2 "" "g,g")))
11034 (use (match_operand:SI 3 "immediate_operand" "O,O"))
11035 (use (reg:SI LR_REGNO))
11036 (simple_return)]
11037 "DEFAULT_ABI == ABI_AIX
11038 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11039 "@
11040 b %z1
11041 b%T1"
11042 [(set_attr "type" "branch")
11043 (set_attr "length" "4")])
11044
11045 (define_insn "*sibcall_nonlocal_sysv<mode>"
11046 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11047 (match_operand 1 "" ""))
11048 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11049 (use (reg:SI LR_REGNO))
11050 (simple_return)]
11051 "(DEFAULT_ABI == ABI_DARWIN
11052 || DEFAULT_ABI == ABI_V4)
11053 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11054 "*
11055 {
11056 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11057 output_asm_insn (\"crxor 6,6,6\", operands);
11058
11059 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11060 output_asm_insn (\"creqv 6,6,6\", operands);
11061
11062 if (which_alternative >= 2)
11063 return \"b%T0\";
11064 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11065 {
11066 gcc_assert (!TARGET_SECURE_PLT);
11067 return \"b %z0@plt\";
11068 }
11069 else
11070 return \"b %z0\";
11071 }"
11072 [(set_attr "type" "branch")
11073 (set_attr "length" "4,8,4,8")])
11074
11075 (define_expand "sibcall_value"
11076 [(parallel [(set (match_operand 0 "register_operand" "")
11077 (call (mem:SI (match_operand 1 "address_operand" ""))
11078 (match_operand 2 "" "")))
11079 (use (match_operand 3 "" ""))
11080 (use (reg:SI LR_REGNO))
11081 (simple_return)])]
11082 ""
11083 "
11084 {
11085 #if TARGET_MACHO
11086 if (MACHOPIC_INDIRECT)
11087 operands[1] = machopic_indirect_call_target (operands[1]);
11088 #endif
11089
11090 gcc_assert (GET_CODE (operands[1]) == MEM);
11091 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11092
11093 operands[1] = XEXP (operands[1], 0);
11094 }")
11095
11096 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11097 [(set (match_operand 0 "" "")
11098 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11099 (match_operand 2 "" "")))
11100 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11101 (use (reg:SI LR_REGNO))
11102 (simple_return)]
11103 "(DEFAULT_ABI == ABI_DARWIN
11104 || DEFAULT_ABI == ABI_V4)
11105 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11106 "*
11107 {
11108 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11109 output_asm_insn (\"crxor 6,6,6\", operands);
11110
11111 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11112 output_asm_insn (\"creqv 6,6,6\", operands);
11113
11114 if (which_alternative >= 2)
11115 return \"b%T1\";
11116 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11117 {
11118 gcc_assert (!TARGET_SECURE_PLT);
11119 return \"b %z1@plt\";
11120 }
11121 else
11122 return \"b %z1\";
11123 }"
11124 [(set_attr "type" "branch")
11125 (set_attr "length" "4,8,4,8")])
11126
11127 (define_expand "sibcall_epilogue"
11128 [(use (const_int 0))]
11129 ""
11130 {
11131 if (!TARGET_SCHED_PROLOG)
11132 emit_insn (gen_blockage ());
11133 rs6000_emit_epilogue (TRUE);
11134 DONE;
11135 })
11136
11137 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11138 ;; all of memory. This blocks insns from being moved across this point.
11139
11140 (define_insn "blockage"
11141 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11142 ""
11143 "")
11144
11145 (define_expand "probe_stack"
11146 [(set (match_operand 0 "memory_operand" "=m")
11147 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11148 ""
11149 {
11150 if (TARGET_64BIT)
11151 emit_insn (gen_probe_stack_di (operands[0]));
11152 else
11153 emit_insn (gen_probe_stack_si (operands[0]));
11154 DONE;
11155 })
11156
11157 (define_insn "probe_stack_<mode>"
11158 [(set (match_operand:P 0 "memory_operand" "=m")
11159 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11160 ""
11161 {
11162 operands[1] = gen_rtx_REG (Pmode, 0);
11163 return "st<wd>%U0%X0 %1,%0";
11164 }
11165 [(set_attr "type" "store")
11166 (set_attr "length" "4")])
11167
11168 (define_insn "probe_stack_range<P:mode>"
11169 [(set (match_operand:P 0 "register_operand" "=r")
11170 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11171 (match_operand:P 2 "register_operand" "r")]
11172 UNSPECV_PROBE_STACK_RANGE))]
11173 ""
11174 "* return output_probe_stack_range (operands[0], operands[2]);"
11175 [(set_attr "type" "three")])
11176 \f
11177 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11178 ;; signed & unsigned, and one type of branch.
11179 ;;
11180 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11181 ;; insns, and branches.
11182
11183 (define_expand "cbranch<mode>4"
11184 [(use (match_operator 0 "rs6000_cbranch_operator"
11185 [(match_operand:GPR 1 "gpc_reg_operand" "")
11186 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11187 (use (match_operand 3 ""))]
11188 ""
11189 "
11190 {
11191 /* Take care of the possibility that operands[2] might be negative but
11192 this might be a logical operation. That insn doesn't exist. */
11193 if (GET_CODE (operands[2]) == CONST_INT
11194 && INTVAL (operands[2]) < 0)
11195 {
11196 operands[2] = force_reg (<MODE>mode, operands[2]);
11197 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11198 GET_MODE (operands[0]),
11199 operands[1], operands[2]);
11200 }
11201
11202 rs6000_emit_cbranch (<MODE>mode, operands);
11203 DONE;
11204 }")
11205
11206 (define_expand "cbranch<mode>4"
11207 [(use (match_operator 0 "rs6000_cbranch_operator"
11208 [(match_operand:FP 1 "gpc_reg_operand" "")
11209 (match_operand:FP 2 "gpc_reg_operand" "")]))
11210 (use (match_operand 3 ""))]
11211 ""
11212 "
11213 {
11214 rs6000_emit_cbranch (<MODE>mode, operands);
11215 DONE;
11216 }")
11217
11218 (define_expand "cstore<mode>4"
11219 [(use (match_operator 1 "rs6000_cbranch_operator"
11220 [(match_operand:GPR 2 "gpc_reg_operand" "")
11221 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11222 (clobber (match_operand:SI 0 "register_operand"))]
11223 ""
11224 "
11225 {
11226 /* Take care of the possibility that operands[3] might be negative but
11227 this might be a logical operation. That insn doesn't exist. */
11228 if (GET_CODE (operands[3]) == CONST_INT
11229 && INTVAL (operands[3]) < 0)
11230 {
11231 operands[3] = force_reg (<MODE>mode, operands[3]);
11232 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11233 GET_MODE (operands[1]),
11234 operands[2], operands[3]);
11235 }
11236
11237 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11238 For SEQ, likewise, except that comparisons with zero should be done
11239 with an scc insns. However, due to the order that combine see the
11240 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11241 the cases we don't want to handle or are best handled by portable
11242 code. */
11243 if (GET_CODE (operands[1]) == NE)
11244 FAIL;
11245 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11246 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11247 && operands[3] == const0_rtx)
11248 FAIL;
11249 rs6000_emit_sCOND (<MODE>mode, operands);
11250 DONE;
11251 }")
11252
11253 (define_expand "cstore<mode>4"
11254 [(use (match_operator 1 "rs6000_cbranch_operator"
11255 [(match_operand:FP 2 "gpc_reg_operand" "")
11256 (match_operand:FP 3 "gpc_reg_operand" "")]))
11257 (clobber (match_operand:SI 0 "register_operand"))]
11258 ""
11259 "
11260 {
11261 rs6000_emit_sCOND (<MODE>mode, operands);
11262 DONE;
11263 }")
11264
11265
11266 (define_expand "stack_protect_set"
11267 [(match_operand 0 "memory_operand" "")
11268 (match_operand 1 "memory_operand" "")]
11269 ""
11270 {
11271 #ifdef TARGET_THREAD_SSP_OFFSET
11272 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11273 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11274 operands[1] = gen_rtx_MEM (Pmode, addr);
11275 #endif
11276 if (TARGET_64BIT)
11277 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11278 else
11279 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11280 DONE;
11281 })
11282
11283 (define_insn "stack_protect_setsi"
11284 [(set (match_operand:SI 0 "memory_operand" "=m")
11285 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11286 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11287 "TARGET_32BIT"
11288 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11289 [(set_attr "type" "three")
11290 (set_attr "length" "12")])
11291
11292 (define_insn "stack_protect_setdi"
11293 [(set (match_operand:DI 0 "memory_operand" "=Y")
11294 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11295 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11296 "TARGET_64BIT"
11297 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11298 [(set_attr "type" "three")
11299 (set_attr "length" "12")])
11300
11301 (define_expand "stack_protect_test"
11302 [(match_operand 0 "memory_operand" "")
11303 (match_operand 1 "memory_operand" "")
11304 (match_operand 2 "" "")]
11305 ""
11306 {
11307 rtx test, op0, op1;
11308 #ifdef TARGET_THREAD_SSP_OFFSET
11309 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11310 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11311 operands[1] = gen_rtx_MEM (Pmode, addr);
11312 #endif
11313 op0 = operands[0];
11314 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11315 test = gen_rtx_EQ (VOIDmode, op0, op1);
11316 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11317 DONE;
11318 })
11319
11320 (define_insn "stack_protect_testsi"
11321 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11322 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11323 (match_operand:SI 2 "memory_operand" "m,m")]
11324 UNSPEC_SP_TEST))
11325 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11326 (clobber (match_scratch:SI 3 "=&r,&r"))]
11327 "TARGET_32BIT"
11328 "@
11329 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11330 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11331 [(set_attr "length" "16,20")])
11332
11333 (define_insn "stack_protect_testdi"
11334 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11335 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11336 (match_operand:DI 2 "memory_operand" "Y,Y")]
11337 UNSPEC_SP_TEST))
11338 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11339 (clobber (match_scratch:DI 3 "=&r,&r"))]
11340 "TARGET_64BIT"
11341 "@
11342 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11343 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11344 [(set_attr "length" "16,20")])
11345
11346 \f
11347 ;; Here are the actual compare insns.
11348 (define_insn "*cmp<mode>_internal1"
11349 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11350 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11351 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11352 ""
11353 "cmp<wd>%I2 %0,%1,%2"
11354 [(set_attr "type" "cmp")])
11355
11356 ;; If we are comparing a register for equality with a large constant,
11357 ;; we can do this with an XOR followed by a compare. But this is profitable
11358 ;; only if the large constant is only used for the comparison (and in this
11359 ;; case we already have a register to reuse as scratch).
11360 ;;
11361 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11362 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11363
11364 (define_peephole2
11365 [(set (match_operand:SI 0 "register_operand")
11366 (match_operand:SI 1 "logical_const_operand" ""))
11367 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11368 [(match_dup 0)
11369 (match_operand:SI 2 "logical_const_operand" "")]))
11370 (set (match_operand:CC 4 "cc_reg_operand" "")
11371 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11372 (match_dup 0)))
11373 (set (pc)
11374 (if_then_else (match_operator 6 "equality_operator"
11375 [(match_dup 4) (const_int 0)])
11376 (match_operand 7 "" "")
11377 (match_operand 8 "" "")))]
11378 "peep2_reg_dead_p (3, operands[0])
11379 && peep2_reg_dead_p (4, operands[4])"
11380 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11381 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11382 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11383
11384 {
11385 /* Get the constant we are comparing against, and see what it looks like
11386 when sign-extended from 16 to 32 bits. Then see what constant we could
11387 XOR with SEXTC to get the sign-extended value. */
11388 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11389 SImode,
11390 operands[1], operands[2]);
11391 HOST_WIDE_INT c = INTVAL (cnst);
11392 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11393 HOST_WIDE_INT xorv = c ^ sextc;
11394
11395 operands[9] = GEN_INT (xorv);
11396 operands[10] = GEN_INT (sextc);
11397 })
11398
11399 (define_insn "*cmpsi_internal2"
11400 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11401 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11402 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11403 ""
11404 "cmplw%I2 %0,%1,%b2"
11405 [(set_attr "type" "cmp")])
11406
11407 (define_insn "*cmpdi_internal2"
11408 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11409 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11410 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11411 ""
11412 "cmpld%I2 %0,%1,%b2"
11413 [(set_attr "type" "cmp")])
11414
11415 ;; The following two insns don't exist as single insns, but if we provide
11416 ;; them, we can swap an add and compare, which will enable us to overlap more
11417 ;; of the required delay between a compare and branch. We generate code for
11418 ;; them by splitting.
11419
11420 (define_insn ""
11421 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11422 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11423 (match_operand:SI 2 "short_cint_operand" "i")))
11424 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11425 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11426 ""
11427 "#"
11428 [(set_attr "length" "8")])
11429
11430 (define_insn ""
11431 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11432 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11433 (match_operand:SI 2 "u_short_cint_operand" "i")))
11434 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11435 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11436 ""
11437 "#"
11438 [(set_attr "length" "8")])
11439
11440 (define_split
11441 [(set (match_operand:CC 3 "cc_reg_operand" "")
11442 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11443 (match_operand:SI 2 "short_cint_operand" "")))
11444 (set (match_operand:SI 0 "gpc_reg_operand" "")
11445 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11446 ""
11447 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11448 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11449
11450 (define_split
11451 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11452 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11453 (match_operand:SI 2 "u_short_cint_operand" "")))
11454 (set (match_operand:SI 0 "gpc_reg_operand" "")
11455 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11456 ""
11457 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11458 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11459
11460 (define_insn "*cmpsf_internal1"
11461 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11462 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11463 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11464 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
11465 "fcmpu %0,%1,%2"
11466 [(set_attr "type" "fpcompare")])
11467
11468 (define_insn "*cmpdf_internal1"
11469 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11470 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
11471 (match_operand:DF 2 "gpc_reg_operand" "d")))]
11472 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11473 && !VECTOR_UNIT_VSX_P (DFmode)"
11474 "fcmpu %0,%1,%2"
11475 [(set_attr "type" "fpcompare")])
11476
11477 ;; Only need to compare second words if first words equal
11478 (define_insn "*cmptf_internal1"
11479 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11480 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11481 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11482 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11483 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11484 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11485 [(set_attr "type" "fpcompare")
11486 (set_attr "length" "12")])
11487
11488 (define_insn_and_split "*cmptf_internal2"
11489 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11490 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11491 (match_operand:TF 2 "gpc_reg_operand" "d")))
11492 (clobber (match_scratch:DF 3 "=d"))
11493 (clobber (match_scratch:DF 4 "=d"))
11494 (clobber (match_scratch:DF 5 "=d"))
11495 (clobber (match_scratch:DF 6 "=d"))
11496 (clobber (match_scratch:DF 7 "=d"))
11497 (clobber (match_scratch:DF 8 "=d"))
11498 (clobber (match_scratch:DF 9 "=d"))
11499 (clobber (match_scratch:DF 10 "=d"))
11500 (clobber (match_scratch:GPR 11 "=b"))]
11501 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11502 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11503 "#"
11504 "&& reload_completed"
11505 [(set (match_dup 3) (match_dup 14))
11506 (set (match_dup 4) (match_dup 15))
11507 (set (match_dup 9) (abs:DF (match_dup 5)))
11508 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11509 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11510 (label_ref (match_dup 12))
11511 (pc)))
11512 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11513 (set (pc) (label_ref (match_dup 13)))
11514 (match_dup 12)
11515 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11516 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11517 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11518 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11519 (match_dup 13)]
11520 {
11521 REAL_VALUE_TYPE rv;
11522 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11523 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11524
11525 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11526 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11527 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11528 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11529 operands[12] = gen_label_rtx ();
11530 operands[13] = gen_label_rtx ();
11531 real_inf (&rv);
11532 operands[14] = force_const_mem (DFmode,
11533 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11534 operands[15] = force_const_mem (DFmode,
11535 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11536 DFmode));
11537 if (TARGET_TOC)
11538 {
11539 rtx tocref;
11540 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11541 operands[14] = gen_const_mem (DFmode, tocref);
11542 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11543 operands[15] = gen_const_mem (DFmode, tocref);
11544 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11545 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11546 }
11547 })
11548 \f
11549 ;; Now we have the scc insns. We can do some combinations because of the
11550 ;; way the machine works.
11551 ;;
11552 ;; Note that this is probably faster if we can put an insn between the
11553 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11554 ;; cases the insns below which don't use an intermediate CR field will
11555 ;; be used instead.
11556 (define_insn ""
11557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11558 (match_operator:SI 1 "scc_comparison_operator"
11559 [(match_operand 2 "cc_reg_operand" "y")
11560 (const_int 0)]))]
11561 ""
11562 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11563 [(set (attr "type")
11564 (cond [(match_test "TARGET_MFCRF")
11565 (const_string "mfcrf")
11566 ]
11567 (const_string "mfcr")))
11568 (set_attr "length" "8")])
11569
11570 ;; Same as above, but get the GT bit.
11571 (define_insn "move_from_CR_gt_bit"
11572 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11573 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11574 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11575 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11576 [(set_attr "type" "mfcr")
11577 (set_attr "length" "8")])
11578
11579 ;; Same as above, but get the OV/ORDERED bit.
11580 (define_insn "move_from_CR_ov_bit"
11581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11582 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11583 UNSPEC_MV_CR_OV))]
11584 "TARGET_ISEL"
11585 "mfcr %0\;rlwinm %0,%0,%t1,1"
11586 [(set_attr "type" "mfcr")
11587 (set_attr "length" "8")])
11588
11589 (define_insn ""
11590 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11591 (match_operator:DI 1 "scc_comparison_operator"
11592 [(match_operand 2 "cc_reg_operand" "y")
11593 (const_int 0)]))]
11594 "TARGET_POWERPC64"
11595 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11596 [(set (attr "type")
11597 (cond [(match_test "TARGET_MFCRF")
11598 (const_string "mfcrf")
11599 ]
11600 (const_string "mfcr")))
11601 (set_attr "length" "8")])
11602
11603 (define_insn ""
11604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11605 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11606 [(match_operand 2 "cc_reg_operand" "y,y")
11607 (const_int 0)])
11608 (const_int 0)))
11609 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11610 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11611 "TARGET_32BIT"
11612 "@
11613 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11614 #"
11615 [(set_attr "type" "delayed_compare")
11616 (set_attr "length" "8,16")])
11617
11618 (define_split
11619 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11620 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11621 [(match_operand 2 "cc_reg_operand" "")
11622 (const_int 0)])
11623 (const_int 0)))
11624 (set (match_operand:SI 3 "gpc_reg_operand" "")
11625 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11626 "TARGET_32BIT && reload_completed"
11627 [(set (match_dup 3)
11628 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11629 (set (match_dup 0)
11630 (compare:CC (match_dup 3)
11631 (const_int 0)))]
11632 "")
11633
11634 (define_insn ""
11635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11636 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11637 [(match_operand 2 "cc_reg_operand" "y")
11638 (const_int 0)])
11639 (match_operand:SI 3 "const_int_operand" "n")))]
11640 ""
11641 "*
11642 {
11643 int is_bit = ccr_bit (operands[1], 1);
11644 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11645 int count;
11646
11647 if (is_bit >= put_bit)
11648 count = is_bit - put_bit;
11649 else
11650 count = 32 - (put_bit - is_bit);
11651
11652 operands[4] = GEN_INT (count);
11653 operands[5] = GEN_INT (put_bit);
11654
11655 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11656 }"
11657 [(set (attr "type")
11658 (cond [(match_test "TARGET_MFCRF")
11659 (const_string "mfcrf")
11660 ]
11661 (const_string "mfcr")))
11662 (set_attr "length" "8")])
11663
11664 (define_insn ""
11665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11666 (compare:CC
11667 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11668 [(match_operand 2 "cc_reg_operand" "y,y")
11669 (const_int 0)])
11670 (match_operand:SI 3 "const_int_operand" "n,n"))
11671 (const_int 0)))
11672 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11673 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11674 (match_dup 3)))]
11675 ""
11676 "*
11677 {
11678 int is_bit = ccr_bit (operands[1], 1);
11679 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11680 int count;
11681
11682 /* Force split for non-cc0 compare. */
11683 if (which_alternative == 1)
11684 return \"#\";
11685
11686 if (is_bit >= put_bit)
11687 count = is_bit - put_bit;
11688 else
11689 count = 32 - (put_bit - is_bit);
11690
11691 operands[5] = GEN_INT (count);
11692 operands[6] = GEN_INT (put_bit);
11693
11694 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11695 }"
11696 [(set_attr "type" "delayed_compare")
11697 (set_attr "length" "8,16")])
11698
11699 (define_split
11700 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
11701 (compare:CC
11702 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11703 [(match_operand 2 "cc_reg_operand" "")
11704 (const_int 0)])
11705 (match_operand:SI 3 "const_int_operand" ""))
11706 (const_int 0)))
11707 (set (match_operand:SI 4 "gpc_reg_operand" "")
11708 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11709 (match_dup 3)))]
11710 "reload_completed"
11711 [(set (match_dup 4)
11712 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11713 (match_dup 3)))
11714 (set (match_dup 0)
11715 (compare:CC (match_dup 4)
11716 (const_int 0)))]
11717 "")
11718
11719 ;; There is a 3 cycle delay between consecutive mfcr instructions
11720 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11721
11722 (define_peephole
11723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11724 (match_operator:SI 1 "scc_comparison_operator"
11725 [(match_operand 2 "cc_reg_operand" "y")
11726 (const_int 0)]))
11727 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11728 (match_operator:SI 4 "scc_comparison_operator"
11729 [(match_operand 5 "cc_reg_operand" "y")
11730 (const_int 0)]))]
11731 "REGNO (operands[2]) != REGNO (operands[5])"
11732 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11733 [(set_attr "type" "mfcr")
11734 (set_attr "length" "12")])
11735
11736 (define_peephole
11737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11738 (match_operator:DI 1 "scc_comparison_operator"
11739 [(match_operand 2 "cc_reg_operand" "y")
11740 (const_int 0)]))
11741 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11742 (match_operator:DI 4 "scc_comparison_operator"
11743 [(match_operand 5 "cc_reg_operand" "y")
11744 (const_int 0)]))]
11745 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11746 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11747 [(set_attr "type" "mfcr")
11748 (set_attr "length" "12")])
11749
11750 ;; There are some scc insns that can be done directly, without a compare.
11751 ;; These are faster because they don't involve the communications between
11752 ;; the FXU and branch units. In fact, we will be replacing all of the
11753 ;; integer scc insns here or in the portable methods in emit_store_flag.
11754 ;;
11755 ;; Also support (neg (scc ..)) since that construct is used to replace
11756 ;; branches, (plus (scc ..) ..) since that construct is common and
11757 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11758 ;; cases where it is no more expensive than (neg (scc ..)).
11759
11760 ;; Have reload force a constant into a register for the simple insns that
11761 ;; otherwise won't accept constants. We do this because it is faster than
11762 ;; the cmp/mfcr sequence we would otherwise generate.
11763
11764 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11765 (DI "rKJI")])
11766
11767 (define_insn_and_split "*eq<mode>"
11768 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11769 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11770 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11771 ""
11772 "#"
11773 ""
11774 [(set (match_dup 0)
11775 (clz:GPR (match_dup 3)))
11776 (set (match_dup 0)
11777 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11778 {
11779 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11780 {
11781 /* Use output operand as intermediate. */
11782 operands[3] = operands[0];
11783
11784 if (logical_operand (operands[2], <MODE>mode))
11785 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11786 gen_rtx_XOR (<MODE>mode,
11787 operands[1], operands[2])));
11788 else
11789 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11790 gen_rtx_PLUS (<MODE>mode, operands[1],
11791 negate_rtx (<MODE>mode,
11792 operands[2]))));
11793 }
11794 else
11795 operands[3] = operands[1];
11796
11797 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11798 })
11799
11800 (define_insn_and_split "*eq<mode>_compare"
11801 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11802 (compare:CC
11803 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11804 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11805 (const_int 0)))
11806 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11807 (eq:P (match_dup 1) (match_dup 2)))]
11808 "optimize_size"
11809 "#"
11810 "optimize_size"
11811 [(set (match_dup 0)
11812 (clz:P (match_dup 4)))
11813 (parallel [(set (match_dup 3)
11814 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11815 (const_int 0)))
11816 (set (match_dup 0)
11817 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11818 {
11819 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11820 {
11821 /* Use output operand as intermediate. */
11822 operands[4] = operands[0];
11823
11824 if (logical_operand (operands[2], <MODE>mode))
11825 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11826 gen_rtx_XOR (<MODE>mode,
11827 operands[1], operands[2])));
11828 else
11829 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11830 gen_rtx_PLUS (<MODE>mode, operands[1],
11831 negate_rtx (<MODE>mode,
11832 operands[2]))));
11833 }
11834 else
11835 operands[4] = operands[1];
11836
11837 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11838 })
11839
11840 ;; We have insns of the form shown by the first define_insn below. If
11841 ;; there is something inside the comparison operation, we must split it.
11842 (define_split
11843 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11844 (plus:SI (match_operator 1 "comparison_operator"
11845 [(match_operand:SI 2 "" "")
11846 (match_operand:SI 3
11847 "reg_or_cint_operand" "")])
11848 (match_operand:SI 4 "gpc_reg_operand" "")))
11849 (clobber (match_operand:SI 5 "register_operand" ""))]
11850 "! gpc_reg_operand (operands[2], SImode)"
11851 [(set (match_dup 5) (match_dup 2))
11852 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
11853 (match_dup 4)))])
11854
11855 (define_insn "*plus_eqsi"
11856 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11857 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11858 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11859 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11860 "TARGET_32BIT"
11861 "@
11862 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
11863 subfic %0,%1,0\;addze %0,%3
11864 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
11865 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
11866 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
11867 [(set_attr "type" "three,two,three,three,three")
11868 (set_attr "length" "12,8,12,12,12")])
11869
11870 (define_insn "*compare_plus_eqsi"
11871 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11872 (compare:CC
11873 (plus:SI
11874 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11875 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11876 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11877 (const_int 0)))
11878 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11879 "TARGET_32BIT && optimize_size"
11880 "@
11881 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11882 subfic %4,%1,0\;addze. %4,%3
11883 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
11884 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
11885 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11886 #
11887 #
11888 #
11889 #
11890 #"
11891 [(set_attr "type" "compare")
11892 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11893
11894 (define_split
11895 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11896 (compare:CC
11897 (plus:SI
11898 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11899 (match_operand:SI 2 "scc_eq_operand" ""))
11900 (match_operand:SI 3 "gpc_reg_operand" ""))
11901 (const_int 0)))
11902 (clobber (match_scratch:SI 4 ""))]
11903 "TARGET_32BIT && optimize_size && reload_completed"
11904 [(set (match_dup 4)
11905 (plus:SI (eq:SI (match_dup 1)
11906 (match_dup 2))
11907 (match_dup 3)))
11908 (set (match_dup 0)
11909 (compare:CC (match_dup 4)
11910 (const_int 0)))]
11911 "")
11912
11913 (define_insn "*plus_eqsi_compare"
11914 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11915 (compare:CC
11916 (plus:SI
11917 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11918 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11919 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11920 (const_int 0)))
11921 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11922 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11923 "TARGET_32BIT && optimize_size"
11924 "@
11925 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11926 subfic %0,%1,0\;addze. %0,%3
11927 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
11928 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
11929 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11930 #
11931 #
11932 #
11933 #
11934 #"
11935 [(set_attr "type" "compare")
11936 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11937
11938 (define_split
11939 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11940 (compare:CC
11941 (plus:SI
11942 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11943 (match_operand:SI 2 "scc_eq_operand" ""))
11944 (match_operand:SI 3 "gpc_reg_operand" ""))
11945 (const_int 0)))
11946 (set (match_operand:SI 0 "gpc_reg_operand" "")
11947 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11948 "TARGET_32BIT && optimize_size && reload_completed"
11949 [(set (match_dup 0)
11950 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11951 (set (match_dup 4)
11952 (compare:CC (match_dup 0)
11953 (const_int 0)))]
11954 "")
11955
11956 (define_insn "*neg_eq0<mode>"
11957 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11958 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11959 (const_int 0))))]
11960 ""
11961 "addic %0,%1,-1\;subfe %0,%0,%0"
11962 [(set_attr "type" "two")
11963 (set_attr "length" "8")])
11964
11965 (define_insn_and_split "*neg_eq<mode>"
11966 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11967 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11968 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11969 ""
11970 "#"
11971 ""
11972 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11973 {
11974 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11975 {
11976 /* Use output operand as intermediate. */
11977 operands[3] = operands[0];
11978
11979 if (logical_operand (operands[2], <MODE>mode))
11980 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11981 gen_rtx_XOR (<MODE>mode,
11982 operands[1], operands[2])));
11983 else
11984 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11985 gen_rtx_PLUS (<MODE>mode, operands[1],
11986 negate_rtx (<MODE>mode,
11987 operands[2]))));
11988 }
11989 else
11990 operands[3] = operands[1];
11991 })
11992
11993 (define_insn "*ne0_<mode>"
11994 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11995 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
11996 (const_int 0)))
11997 (clobber (match_scratch:P 2 "=&r"))]
11998 "!(TARGET_32BIT && TARGET_ISEL)"
11999 "addic %2,%1,-1\;subfe %0,%2,%1"
12000 [(set_attr "type" "two")
12001 (set_attr "length" "8")])
12002
12003 (define_insn "*plus_ne0_<mode>"
12004 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12005 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12006 (const_int 0))
12007 (match_operand:P 2 "gpc_reg_operand" "r")))
12008 (clobber (match_scratch:P 3 "=&r"))]
12009 ""
12010 "addic %3,%1,-1\;addze %0,%2"
12011 [(set_attr "type" "two")
12012 (set_attr "length" "8")])
12013
12014 (define_insn "*compare_plus_ne0_<mode>"
12015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12016 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12017 (const_int 0))
12018 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12019 (const_int 0)))
12020 (clobber (match_scratch:P 3 "=&r,&r"))
12021 (clobber (match_scratch:P 4 "=X,&r"))]
12022 ""
12023 "@
12024 addic %3,%1,-1\;addze. %3,%2
12025 #"
12026 [(set_attr "type" "compare")
12027 (set_attr "length" "8,12")])
12028
12029 (define_split
12030 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12031 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12032 (const_int 0))
12033 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12034 (clobber (match_scratch:P 3 ""))
12035 (clobber (match_scratch:P 4 ""))]
12036 "reload_completed"
12037 [(parallel [(set (match_dup 3)
12038 (plus:P (ne:P (match_dup 1)
12039 (const_int 0))
12040 (match_dup 2)))
12041 (clobber (match_dup 4))])
12042 (set (match_dup 0)
12043 (compare:CC (match_dup 3)
12044 (const_int 0)))]
12045 "")
12046
12047 ; For combine.
12048 (define_insn "*compare_plus_ne0_<mode>_1"
12049 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12050 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12051 (const_int 0))
12052 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12053 (clobber (match_scratch:P 3 "=&r,&r"))
12054 (clobber (match_scratch:P 4 "=X,&r"))]
12055 ""
12056 "@
12057 addic %3,%1,-1\;addze. %3,%2
12058 #"
12059 [(set_attr "type" "compare")
12060 (set_attr "length" "8,12")])
12061
12062 (define_split
12063 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12064 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12065 (const_int 0))
12066 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12067 (clobber (match_scratch:P 3 ""))
12068 (clobber (match_scratch:P 4 ""))]
12069 "reload_completed"
12070 [(parallel [(set (match_dup 3)
12071 (plus:P (ne:P (match_dup 1)
12072 (const_int 0))
12073 (match_dup 2)))
12074 (clobber (match_dup 4))])
12075 (set (match_dup 0)
12076 (compare:CC (match_dup 3)
12077 (const_int 0)))]
12078 "")
12079
12080 (define_insn "*plus_ne0_<mode>_compare"
12081 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12082 (compare:CC
12083 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12084 (const_int 0))
12085 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12086 (const_int 0)))
12087 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12088 (plus:P (ne:P (match_dup 1)
12089 (const_int 0))
12090 (match_dup 2)))
12091 (clobber (match_scratch:P 3 "=&r,&r"))]
12092 ""
12093 "@
12094 addic %3,%1,-1\;addze. %0,%2
12095 #"
12096 [(set_attr "type" "compare")
12097 (set_attr "length" "8,12")])
12098
12099 (define_split
12100 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12101 (compare:CC
12102 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12103 (const_int 0))
12104 (match_operand:P 2 "gpc_reg_operand" ""))
12105 (const_int 0)))
12106 (set (match_operand:P 0 "gpc_reg_operand" "")
12107 (plus:P (ne:P (match_dup 1)
12108 (const_int 0))
12109 (match_dup 2)))
12110 (clobber (match_scratch:P 3 ""))]
12111 "reload_completed"
12112 [(parallel [(set (match_dup 0)
12113 (plus:P (ne:P (match_dup 1)
12114 (const_int 0))
12115 (match_dup 2)))
12116 (clobber (match_dup 3))])
12117 (set (match_dup 4)
12118 (compare:CC (match_dup 0)
12119 (const_int 0)))]
12120 "")
12121
12122 (define_insn "*leu<mode>"
12123 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12124 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12125 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12126 ""
12127 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12128 [(set_attr "type" "three")
12129 (set_attr "length" "12")])
12130
12131 (define_insn "*leu<mode>_compare"
12132 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12133 (compare:CC
12134 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12135 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12136 (const_int 0)))
12137 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12138 (leu:P (match_dup 1) (match_dup 2)))]
12139 ""
12140 "@
12141 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12142 #"
12143 [(set_attr "type" "compare")
12144 (set_attr "length" "12,16")])
12145
12146 (define_split
12147 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12148 (compare:CC
12149 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12150 (match_operand:P 2 "reg_or_short_operand" ""))
12151 (const_int 0)))
12152 (set (match_operand:P 0 "gpc_reg_operand" "")
12153 (leu:P (match_dup 1) (match_dup 2)))]
12154 "reload_completed"
12155 [(set (match_dup 0)
12156 (leu:P (match_dup 1) (match_dup 2)))
12157 (set (match_dup 3)
12158 (compare:CC (match_dup 0)
12159 (const_int 0)))]
12160 "")
12161
12162 (define_insn "*plus_leu<mode>"
12163 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12164 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12165 (match_operand:P 2 "reg_or_short_operand" "rI"))
12166 (match_operand:P 3 "gpc_reg_operand" "r")))]
12167 ""
12168 "subf%I2c %0,%1,%2\;addze %0,%3"
12169 [(set_attr "type" "two")
12170 (set_attr "length" "8")])
12171
12172 (define_insn ""
12173 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12174 (compare:CC
12175 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12176 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12177 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12178 (const_int 0)))
12179 (clobber (match_scratch:SI 4 "=&r,&r"))]
12180 "TARGET_32BIT"
12181 "@
12182 subf%I2c %4,%1,%2\;addze. %4,%3
12183 #"
12184 [(set_attr "type" "compare")
12185 (set_attr "length" "8,12")])
12186
12187 (define_split
12188 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12189 (compare:CC
12190 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12191 (match_operand:SI 2 "reg_or_short_operand" ""))
12192 (match_operand:SI 3 "gpc_reg_operand" ""))
12193 (const_int 0)))
12194 (clobber (match_scratch:SI 4 ""))]
12195 "TARGET_32BIT && reload_completed"
12196 [(set (match_dup 4)
12197 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12198 (match_dup 3)))
12199 (set (match_dup 0)
12200 (compare:CC (match_dup 4)
12201 (const_int 0)))]
12202 "")
12203
12204 (define_insn ""
12205 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12206 (compare:CC
12207 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12208 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12209 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12210 (const_int 0)))
12211 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12212 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12213 "TARGET_32BIT"
12214 "@
12215 subf%I2c %0,%1,%2\;addze. %0,%3
12216 #"
12217 [(set_attr "type" "compare")
12218 (set_attr "length" "8,12")])
12219
12220 (define_split
12221 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12222 (compare:CC
12223 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12224 (match_operand:SI 2 "reg_or_short_operand" ""))
12225 (match_operand:SI 3 "gpc_reg_operand" ""))
12226 (const_int 0)))
12227 (set (match_operand:SI 0 "gpc_reg_operand" "")
12228 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12229 "TARGET_32BIT && reload_completed"
12230 [(set (match_dup 0)
12231 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12232 (set (match_dup 4)
12233 (compare:CC (match_dup 0)
12234 (const_int 0)))]
12235 "")
12236
12237 (define_insn "*neg_leu<mode>"
12238 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12239 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12240 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12241 ""
12242 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12243 [(set_attr "type" "three")
12244 (set_attr "length" "12")])
12245
12246 (define_insn "*and_neg_leu<mode>"
12247 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12248 (and:P (neg:P
12249 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12250 (match_operand:P 2 "reg_or_short_operand" "rI")))
12251 (match_operand:P 3 "gpc_reg_operand" "r")))]
12252 ""
12253 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12254 [(set_attr "type" "three")
12255 (set_attr "length" "12")])
12256
12257 (define_insn ""
12258 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12259 (compare:CC
12260 (and:SI (neg:SI
12261 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12262 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12263 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12264 (const_int 0)))
12265 (clobber (match_scratch:SI 4 "=&r,&r"))]
12266 "TARGET_32BIT"
12267 "@
12268 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12269 #"
12270 [(set_attr "type" "compare")
12271 (set_attr "length" "12,16")])
12272
12273 (define_split
12274 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12275 (compare:CC
12276 (and:SI (neg:SI
12277 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12278 (match_operand:SI 2 "reg_or_short_operand" "")))
12279 (match_operand:SI 3 "gpc_reg_operand" ""))
12280 (const_int 0)))
12281 (clobber (match_scratch:SI 4 ""))]
12282 "TARGET_32BIT && reload_completed"
12283 [(set (match_dup 4)
12284 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12285 (match_dup 3)))
12286 (set (match_dup 0)
12287 (compare:CC (match_dup 4)
12288 (const_int 0)))]
12289 "")
12290
12291 (define_insn ""
12292 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12293 (compare:CC
12294 (and:SI (neg:SI
12295 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12296 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12297 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12298 (const_int 0)))
12299 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12300 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12301 "TARGET_32BIT"
12302 "@
12303 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12304 #"
12305 [(set_attr "type" "compare")
12306 (set_attr "length" "12,16")])
12307
12308 (define_split
12309 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12310 (compare:CC
12311 (and:SI (neg:SI
12312 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12313 (match_operand:SI 2 "reg_or_short_operand" "")))
12314 (match_operand:SI 3 "gpc_reg_operand" ""))
12315 (const_int 0)))
12316 (set (match_operand:SI 0 "gpc_reg_operand" "")
12317 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12318 "TARGET_32BIT && reload_completed"
12319 [(set (match_dup 0)
12320 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12321 (match_dup 3)))
12322 (set (match_dup 4)
12323 (compare:CC (match_dup 0)
12324 (const_int 0)))]
12325 "")
12326
12327 (define_insn_and_split "*ltu<mode>"
12328 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12329 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12330 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12331 ""
12332 "#"
12333 ""
12334 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12335 (set (match_dup 0) (neg:P (match_dup 0)))]
12336 "")
12337
12338 (define_insn_and_split "*ltu<mode>_compare"
12339 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12340 (compare:CC
12341 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12342 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12343 (const_int 0)))
12344 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12345 (ltu:P (match_dup 1) (match_dup 2)))]
12346 ""
12347 "#"
12348 ""
12349 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12350 (parallel [(set (match_dup 3)
12351 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12352 (set (match_dup 0) (neg:P (match_dup 0)))])]
12353 "")
12354
12355 (define_insn_and_split "*plus_ltu<mode>"
12356 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12357 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12358 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12359 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12360 ""
12361 "#"
12362 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12363 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12364 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12365 "")
12366
12367 (define_insn_and_split "*plus_ltu<mode>_compare"
12368 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12369 (compare:CC
12370 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12371 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12372 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12373 (const_int 0)))
12374 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12375 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12376 ""
12377 "#"
12378 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12379 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12380 (parallel [(set (match_dup 4)
12381 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12382 (const_int 0)))
12383 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12384 "")
12385
12386 (define_insn "*neg_ltu<mode>"
12387 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12388 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12389 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12390 ""
12391 "@
12392 subfc %0,%2,%1\;subfe %0,%0,%0
12393 addic %0,%1,%n2\;subfe %0,%0,%0"
12394 [(set_attr "type" "two")
12395 (set_attr "length" "8")])
12396
12397 (define_insn "*geu<mode>"
12398 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12399 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12400 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12401 ""
12402 "@
12403 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12404 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12405 [(set_attr "type" "three")
12406 (set_attr "length" "12")])
12407
12408 (define_insn "*geu<mode>_compare"
12409 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12410 (compare:CC
12411 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12412 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12413 (const_int 0)))
12414 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12415 (geu:P (match_dup 1) (match_dup 2)))]
12416 ""
12417 "@
12418 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12419 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12420 #
12421 #"
12422 [(set_attr "type" "compare")
12423 (set_attr "length" "12,12,16,16")])
12424
12425 (define_split
12426 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12427 (compare:CC
12428 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12429 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12430 (const_int 0)))
12431 (set (match_operand:P 0 "gpc_reg_operand" "")
12432 (geu:P (match_dup 1) (match_dup 2)))]
12433 "reload_completed"
12434 [(set (match_dup 0)
12435 (geu:P (match_dup 1) (match_dup 2)))
12436 (set (match_dup 3)
12437 (compare:CC (match_dup 0)
12438 (const_int 0)))]
12439 "")
12440
12441 (define_insn "*plus_geu<mode>"
12442 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12443 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12444 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12445 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12446 ""
12447 "@
12448 subfc %0,%2,%1\;addze %0,%3
12449 addic %0,%1,%n2\;addze %0,%3"
12450 [(set_attr "type" "two")
12451 (set_attr "length" "8")])
12452
12453 (define_insn ""
12454 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12455 (compare:CC
12456 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12457 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12458 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12459 (const_int 0)))
12460 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12461 "TARGET_32BIT"
12462 "@
12463 subfc %4,%2,%1\;addze. %4,%3
12464 addic %4,%1,%n2\;addze. %4,%3
12465 #
12466 #"
12467 [(set_attr "type" "compare")
12468 (set_attr "length" "8,8,12,12")])
12469
12470 (define_split
12471 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12472 (compare:CC
12473 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12474 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12475 (match_operand:SI 3 "gpc_reg_operand" ""))
12476 (const_int 0)))
12477 (clobber (match_scratch:SI 4 ""))]
12478 "TARGET_32BIT && reload_completed"
12479 [(set (match_dup 4)
12480 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12481 (match_dup 3)))
12482 (set (match_dup 0)
12483 (compare:CC (match_dup 4)
12484 (const_int 0)))]
12485 "")
12486
12487 (define_insn ""
12488 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12489 (compare:CC
12490 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12491 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12492 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12493 (const_int 0)))
12494 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12495 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12496 "TARGET_32BIT"
12497 "@
12498 subfc %0,%2,%1\;addze. %0,%3
12499 addic %0,%1,%n2\;addze. %0,%3
12500 #
12501 #"
12502 [(set_attr "type" "compare")
12503 (set_attr "length" "8,8,12,12")])
12504
12505 (define_split
12506 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12507 (compare:CC
12508 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12509 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12510 (match_operand:SI 3 "gpc_reg_operand" ""))
12511 (const_int 0)))
12512 (set (match_operand:SI 0 "gpc_reg_operand" "")
12513 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12514 "TARGET_32BIT && reload_completed"
12515 [(set (match_dup 0)
12516 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12517 (set (match_dup 4)
12518 (compare:CC (match_dup 0)
12519 (const_int 0)))]
12520 "")
12521
12522 (define_insn "*neg_geu<mode>"
12523 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12524 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12525 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12526 ""
12527 "@
12528 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12529 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12530 [(set_attr "type" "three")
12531 (set_attr "length" "12")])
12532
12533 (define_insn "*and_neg_geu<mode>"
12534 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12535 (and:P (neg:P
12536 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12537 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12538 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12539 ""
12540 "@
12541 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12542 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12543 [(set_attr "type" "three")
12544 (set_attr "length" "12")])
12545
12546 (define_insn ""
12547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12548 (compare:CC
12549 (and:SI (neg:SI
12550 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12551 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12552 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12553 (const_int 0)))
12554 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12555 "TARGET_32BIT"
12556 "@
12557 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12558 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12559 #
12560 #"
12561 [(set_attr "type" "compare")
12562 (set_attr "length" "12,12,16,16")])
12563
12564 (define_split
12565 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12566 (compare:CC
12567 (and:SI (neg:SI
12568 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12569 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12570 (match_operand:SI 3 "gpc_reg_operand" ""))
12571 (const_int 0)))
12572 (clobber (match_scratch:SI 4 ""))]
12573 "TARGET_32BIT && reload_completed"
12574 [(set (match_dup 4)
12575 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12576 (match_dup 3)))
12577 (set (match_dup 0)
12578 (compare:CC (match_dup 4)
12579 (const_int 0)))]
12580 "")
12581
12582 (define_insn ""
12583 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12584 (compare:CC
12585 (and:SI (neg:SI
12586 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12587 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12588 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12589 (const_int 0)))
12590 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12591 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12592 "TARGET_32BIT"
12593 "@
12594 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12595 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12596 #
12597 #"
12598 [(set_attr "type" "compare")
12599 (set_attr "length" "12,12,16,16")])
12600
12601 (define_split
12602 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12603 (compare:CC
12604 (and:SI (neg:SI
12605 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12606 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12607 (match_operand:SI 3 "gpc_reg_operand" ""))
12608 (const_int 0)))
12609 (set (match_operand:SI 0 "gpc_reg_operand" "")
12610 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12611 "TARGET_32BIT && reload_completed"
12612 [(set (match_dup 0)
12613 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12614 (set (match_dup 4)
12615 (compare:CC (match_dup 0)
12616 (const_int 0)))]
12617 "")
12618
12619 (define_insn "*plus_gt0<mode>"
12620 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12621 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12622 (const_int 0))
12623 (match_operand:P 2 "gpc_reg_operand" "r")))]
12624 ""
12625 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12626 [(set_attr "type" "three")
12627 (set_attr "length" "12")])
12628
12629 (define_insn ""
12630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12631 (compare:CC
12632 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12633 (const_int 0))
12634 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12635 (const_int 0)))
12636 (clobber (match_scratch:SI 3 "=&r,&r"))]
12637 "TARGET_32BIT"
12638 "@
12639 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12640 #"
12641 [(set_attr "type" "compare")
12642 (set_attr "length" "12,16")])
12643
12644 (define_split
12645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12646 (compare:CC
12647 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12648 (const_int 0))
12649 (match_operand:SI 2 "gpc_reg_operand" ""))
12650 (const_int 0)))
12651 (clobber (match_scratch:SI 3 ""))]
12652 "TARGET_32BIT && reload_completed"
12653 [(set (match_dup 3)
12654 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12655 (match_dup 2)))
12656 (set (match_dup 0)
12657 (compare:CC (match_dup 3)
12658 (const_int 0)))]
12659 "")
12660
12661 (define_insn ""
12662 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12663 (compare:CC
12664 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12665 (const_int 0))
12666 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12667 (const_int 0)))
12668 (clobber (match_scratch:DI 3 "=&r,&r"))]
12669 "TARGET_64BIT"
12670 "@
12671 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12672 #"
12673 [(set_attr "type" "compare")
12674 (set_attr "length" "12,16")])
12675
12676 (define_split
12677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12678 (compare:CC
12679 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12680 (const_int 0))
12681 (match_operand:DI 2 "gpc_reg_operand" ""))
12682 (const_int 0)))
12683 (clobber (match_scratch:DI 3 ""))]
12684 "TARGET_64BIT && reload_completed"
12685 [(set (match_dup 3)
12686 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12687 (match_dup 2)))
12688 (set (match_dup 0)
12689 (compare:CC (match_dup 3)
12690 (const_int 0)))]
12691 "")
12692
12693 (define_insn ""
12694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12695 (compare:CC
12696 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12697 (const_int 0))
12698 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12699 (const_int 0)))
12700 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12701 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12702 "TARGET_32BIT"
12703 "@
12704 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12705 #"
12706 [(set_attr "type" "compare")
12707 (set_attr "length" "12,16")])
12708
12709 (define_split
12710 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12711 (compare:CC
12712 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12713 (const_int 0))
12714 (match_operand:SI 2 "gpc_reg_operand" ""))
12715 (const_int 0)))
12716 (set (match_operand:SI 0 "gpc_reg_operand" "")
12717 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12718 "TARGET_32BIT && reload_completed"
12719 [(set (match_dup 0)
12720 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12721 (set (match_dup 3)
12722 (compare:CC (match_dup 0)
12723 (const_int 0)))]
12724 "")
12725
12726 (define_insn ""
12727 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12728 (compare:CC
12729 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12730 (const_int 0))
12731 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12732 (const_int 0)))
12733 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12734 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12735 "TARGET_64BIT"
12736 "@
12737 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12738 #"
12739 [(set_attr "type" "compare")
12740 (set_attr "length" "12,16")])
12741
12742 (define_split
12743 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12744 (compare:CC
12745 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12746 (const_int 0))
12747 (match_operand:DI 2 "gpc_reg_operand" ""))
12748 (const_int 0)))
12749 (set (match_operand:DI 0 "gpc_reg_operand" "")
12750 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12751 "TARGET_64BIT && reload_completed"
12752 [(set (match_dup 0)
12753 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12754 (set (match_dup 3)
12755 (compare:CC (match_dup 0)
12756 (const_int 0)))]
12757 "")
12758
12759 (define_insn_and_split "*gtu<mode>"
12760 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12761 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12762 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12763 ""
12764 "#"
12765 ""
12766 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12767 (set (match_dup 0) (neg:P (match_dup 0)))]
12768 "")
12769
12770 (define_insn_and_split "*gtu<mode>_compare"
12771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12772 (compare:CC
12773 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12774 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12775 (const_int 0)))
12776 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12777 (gtu:P (match_dup 1) (match_dup 2)))]
12778 ""
12779 "#"
12780 ""
12781 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12782 (parallel [(set (match_dup 3)
12783 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12784 (set (match_dup 0) (neg:P (match_dup 0)))])]
12785 "")
12786
12787 (define_insn_and_split "*plus_gtu<mode>"
12788 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12789 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12790 (match_operand:P 2 "reg_or_short_operand" "rI"))
12791 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12792 ""
12793 "#"
12794 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12795 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12796 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12797 "")
12798
12799 (define_insn_and_split "*plus_gtu<mode>_compare"
12800 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12801 (compare:CC
12802 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12803 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12804 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12805 (const_int 0)))
12806 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12807 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12808 ""
12809 "#"
12810 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12811 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12812 (parallel [(set (match_dup 4)
12813 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12814 (const_int 0)))
12815 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12816 "")
12817
12818 (define_insn "*neg_gtu<mode>"
12819 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12820 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12821 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12822 ""
12823 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12824 [(set_attr "type" "two")
12825 (set_attr "length" "8")])
12826
12827 \f
12828 ;; Define both directions of branch and return. If we need a reload
12829 ;; register, we'd rather use CR0 since it is much easier to copy a
12830 ;; register CC value to there.
12831
12832 (define_insn ""
12833 [(set (pc)
12834 (if_then_else (match_operator 1 "branch_comparison_operator"
12835 [(match_operand 2
12836 "cc_reg_operand" "y")
12837 (const_int 0)])
12838 (label_ref (match_operand 0 "" ""))
12839 (pc)))]
12840 ""
12841 "*
12842 {
12843 return output_cbranch (operands[1], \"%l0\", 0, insn);
12844 }"
12845 [(set_attr "type" "branch")])
12846
12847 (define_insn ""
12848 [(set (pc)
12849 (if_then_else (match_operator 0 "branch_comparison_operator"
12850 [(match_operand 1
12851 "cc_reg_operand" "y")
12852 (const_int 0)])
12853 (any_return)
12854 (pc)))]
12855 "<return_pred>"
12856 "*
12857 {
12858 return output_cbranch (operands[0], NULL, 0, insn);
12859 }"
12860 [(set_attr "type" "jmpreg")
12861 (set_attr "length" "4")])
12862
12863 (define_insn ""
12864 [(set (pc)
12865 (if_then_else (match_operator 1 "branch_comparison_operator"
12866 [(match_operand 2
12867 "cc_reg_operand" "y")
12868 (const_int 0)])
12869 (pc)
12870 (label_ref (match_operand 0 "" ""))))]
12871 ""
12872 "*
12873 {
12874 return output_cbranch (operands[1], \"%l0\", 1, insn);
12875 }"
12876 [(set_attr "type" "branch")])
12877
12878 (define_insn ""
12879 [(set (pc)
12880 (if_then_else (match_operator 0 "branch_comparison_operator"
12881 [(match_operand 1
12882 "cc_reg_operand" "y")
12883 (const_int 0)])
12884 (pc)
12885 (any_return)))]
12886 "<return_pred>"
12887 "*
12888 {
12889 return output_cbranch (operands[0], NULL, 1, insn);
12890 }"
12891 [(set_attr "type" "jmpreg")
12892 (set_attr "length" "4")])
12893
12894 ;; Logic on condition register values.
12895
12896 ; This pattern matches things like
12897 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12898 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12899 ; (const_int 1)))
12900 ; which are generated by the branch logic.
12901 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12902
12903 (define_insn "*cceq_ior_compare"
12904 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12905 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12906 [(match_operator:SI 2
12907 "branch_positive_comparison_operator"
12908 [(match_operand 3
12909 "cc_reg_operand" "y,y")
12910 (const_int 0)])
12911 (match_operator:SI 4
12912 "branch_positive_comparison_operator"
12913 [(match_operand 5
12914 "cc_reg_operand" "0,y")
12915 (const_int 0)])])
12916 (const_int 1)))]
12917 ""
12918 "cr%q1 %E0,%j2,%j4"
12919 [(set_attr "type" "cr_logical,delayed_cr")])
12920
12921 ; Why is the constant -1 here, but 1 in the previous pattern?
12922 ; Because ~1 has all but the low bit set.
12923 (define_insn ""
12924 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12925 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12926 [(not:SI (match_operator:SI 2
12927 "branch_positive_comparison_operator"
12928 [(match_operand 3
12929 "cc_reg_operand" "y,y")
12930 (const_int 0)]))
12931 (match_operator:SI 4
12932 "branch_positive_comparison_operator"
12933 [(match_operand 5
12934 "cc_reg_operand" "0,y")
12935 (const_int 0)])])
12936 (const_int -1)))]
12937 ""
12938 "cr%q1 %E0,%j2,%j4"
12939 [(set_attr "type" "cr_logical,delayed_cr")])
12940
12941 (define_insn "*cceq_rev_compare"
12942 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12943 (compare:CCEQ (match_operator:SI 1
12944 "branch_positive_comparison_operator"
12945 [(match_operand 2
12946 "cc_reg_operand" "0,y")
12947 (const_int 0)])
12948 (const_int 0)))]
12949 ""
12950 "crnot %E0,%j1"
12951 [(set_attr "type" "cr_logical,delayed_cr")])
12952
12953 ;; If we are comparing the result of two comparisons, this can be done
12954 ;; using creqv or crxor.
12955
12956 (define_insn_and_split ""
12957 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12958 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12959 [(match_operand 2 "cc_reg_operand" "y")
12960 (const_int 0)])
12961 (match_operator 3 "branch_comparison_operator"
12962 [(match_operand 4 "cc_reg_operand" "y")
12963 (const_int 0)])))]
12964 ""
12965 "#"
12966 ""
12967 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12968 (match_dup 5)))]
12969 "
12970 {
12971 int positive_1, positive_2;
12972
12973 positive_1 = branch_positive_comparison_operator (operands[1],
12974 GET_MODE (operands[1]));
12975 positive_2 = branch_positive_comparison_operator (operands[3],
12976 GET_MODE (operands[3]));
12977
12978 if (! positive_1)
12979 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
12980 GET_CODE (operands[1])),
12981 SImode,
12982 operands[2], const0_rtx);
12983 else if (GET_MODE (operands[1]) != SImode)
12984 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12985 operands[2], const0_rtx);
12986
12987 if (! positive_2)
12988 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
12989 GET_CODE (operands[3])),
12990 SImode,
12991 operands[4], const0_rtx);
12992 else if (GET_MODE (operands[3]) != SImode)
12993 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12994 operands[4], const0_rtx);
12995
12996 if (positive_1 == positive_2)
12997 {
12998 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12999 operands[5] = constm1_rtx;
13000 }
13001 else
13002 {
13003 operands[5] = const1_rtx;
13004 }
13005 }")
13006
13007 ;; Unconditional branch and return.
13008
13009 (define_insn "jump"
13010 [(set (pc)
13011 (label_ref (match_operand 0 "" "")))]
13012 ""
13013 "b %l0"
13014 [(set_attr "type" "branch")])
13015
13016 (define_insn "<return_str>return"
13017 [(any_return)]
13018 "<return_pred>"
13019 "blr"
13020 [(set_attr "type" "jmpreg")])
13021
13022 (define_expand "indirect_jump"
13023 [(set (pc) (match_operand 0 "register_operand" ""))])
13024
13025 (define_insn "*indirect_jump<mode>"
13026 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13027 ""
13028 "@
13029 bctr
13030 blr"
13031 [(set_attr "type" "jmpreg")])
13032
13033 ;; Table jump for switch statements:
13034 (define_expand "tablejump"
13035 [(use (match_operand 0 "" ""))
13036 (use (label_ref (match_operand 1 "" "")))]
13037 ""
13038 "
13039 {
13040 if (TARGET_32BIT)
13041 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13042 else
13043 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13044 DONE;
13045 }")
13046
13047 (define_expand "tablejumpsi"
13048 [(set (match_dup 3)
13049 (plus:SI (match_operand:SI 0 "" "")
13050 (match_dup 2)))
13051 (parallel [(set (pc) (match_dup 3))
13052 (use (label_ref (match_operand 1 "" "")))])]
13053 "TARGET_32BIT"
13054 "
13055 { operands[0] = force_reg (SImode, operands[0]);
13056 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13057 operands[3] = gen_reg_rtx (SImode);
13058 }")
13059
13060 (define_expand "tablejumpdi"
13061 [(set (match_dup 4)
13062 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13063 (set (match_dup 3)
13064 (plus:DI (match_dup 4)
13065 (match_dup 2)))
13066 (parallel [(set (pc) (match_dup 3))
13067 (use (label_ref (match_operand 1 "" "")))])]
13068 "TARGET_64BIT"
13069 "
13070 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13071 operands[3] = gen_reg_rtx (DImode);
13072 operands[4] = gen_reg_rtx (DImode);
13073 }")
13074
13075 (define_insn "*tablejump<mode>_internal1"
13076 [(set (pc)
13077 (match_operand:P 0 "register_operand" "c,*l"))
13078 (use (label_ref (match_operand 1 "" "")))]
13079 ""
13080 "@
13081 bctr
13082 blr"
13083 [(set_attr "type" "jmpreg")])
13084
13085 (define_insn "nop"
13086 [(const_int 0)]
13087 ""
13088 "nop")
13089
13090 (define_insn "group_ending_nop"
13091 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13092 ""
13093 "*
13094 {
13095 if (rs6000_cpu_attr == CPU_POWER6)
13096 return \"ori 1,1,0\";
13097 return \"ori 2,2,0\";
13098 }")
13099 \f
13100 ;; Define the subtract-one-and-jump insns, starting with the template
13101 ;; so loop.c knows what to generate.
13102
13103 (define_expand "doloop_end"
13104 [(use (match_operand 0 "" "")) ; loop pseudo
13105 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13106 (use (match_operand 2 "" "")) ; max iterations
13107 (use (match_operand 3 "" "")) ; loop level
13108 (use (match_operand 4 "" "")) ; label
13109 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
13110 ""
13111 "
13112 {
13113 /* Only use this on innermost loops. */
13114 if (INTVAL (operands[3]) > 1)
13115 FAIL;
13116 if (TARGET_64BIT)
13117 {
13118 if (GET_MODE (operands[0]) != DImode)
13119 FAIL;
13120 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13121 }
13122 else
13123 {
13124 if (GET_MODE (operands[0]) != SImode)
13125 FAIL;
13126 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13127 }
13128 DONE;
13129 }")
13130
13131 (define_expand "ctr<mode>"
13132 [(parallel [(set (pc)
13133 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13134 (const_int 1))
13135 (label_ref (match_operand 1 "" ""))
13136 (pc)))
13137 (set (match_dup 0)
13138 (plus:P (match_dup 0)
13139 (const_int -1)))
13140 (clobber (match_scratch:CC 2 ""))
13141 (clobber (match_scratch:P 3 ""))])]
13142 ""
13143 "")
13144
13145 ;; We need to be able to do this for any operand, including MEM, or we
13146 ;; will cause reload to blow up since we don't allow output reloads on
13147 ;; JUMP_INSNs.
13148 ;; For the length attribute to be calculated correctly, the
13149 ;; label MUST be operand 0.
13150
13151 (define_insn "*ctr<mode>_internal1"
13152 [(set (pc)
13153 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13154 (const_int 1))
13155 (label_ref (match_operand 0 "" ""))
13156 (pc)))
13157 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13158 (plus:P (match_dup 1)
13159 (const_int -1)))
13160 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13161 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13162 ""
13163 "*
13164 {
13165 if (which_alternative != 0)
13166 return \"#\";
13167 else if (get_attr_length (insn) == 4)
13168 return \"bdnz %l0\";
13169 else
13170 return \"bdz $+8\;b %l0\";
13171 }"
13172 [(set_attr "type" "branch")
13173 (set_attr "length" "*,12,16,16")])
13174
13175 (define_insn "*ctr<mode>_internal2"
13176 [(set (pc)
13177 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13178 (const_int 1))
13179 (pc)
13180 (label_ref (match_operand 0 "" ""))))
13181 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13182 (plus:P (match_dup 1)
13183 (const_int -1)))
13184 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13185 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13186 ""
13187 "*
13188 {
13189 if (which_alternative != 0)
13190 return \"#\";
13191 else if (get_attr_length (insn) == 4)
13192 return \"bdz %l0\";
13193 else
13194 return \"bdnz $+8\;b %l0\";
13195 }"
13196 [(set_attr "type" "branch")
13197 (set_attr "length" "*,12,16,16")])
13198
13199 ;; Similar but use EQ
13200
13201 (define_insn "*ctr<mode>_internal5"
13202 [(set (pc)
13203 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13204 (const_int 1))
13205 (label_ref (match_operand 0 "" ""))
13206 (pc)))
13207 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13208 (plus:P (match_dup 1)
13209 (const_int -1)))
13210 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13211 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13212 ""
13213 "*
13214 {
13215 if (which_alternative != 0)
13216 return \"#\";
13217 else if (get_attr_length (insn) == 4)
13218 return \"bdz %l0\";
13219 else
13220 return \"bdnz $+8\;b %l0\";
13221 }"
13222 [(set_attr "type" "branch")
13223 (set_attr "length" "*,12,16,16")])
13224
13225 (define_insn "*ctr<mode>_internal6"
13226 [(set (pc)
13227 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13228 (const_int 1))
13229 (pc)
13230 (label_ref (match_operand 0 "" ""))))
13231 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13232 (plus:P (match_dup 1)
13233 (const_int -1)))
13234 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13235 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13236 ""
13237 "*
13238 {
13239 if (which_alternative != 0)
13240 return \"#\";
13241 else if (get_attr_length (insn) == 4)
13242 return \"bdnz %l0\";
13243 else
13244 return \"bdz $+8\;b %l0\";
13245 }"
13246 [(set_attr "type" "branch")
13247 (set_attr "length" "*,12,16,16")])
13248
13249 ;; Now the splitters if we could not allocate the CTR register
13250
13251 (define_split
13252 [(set (pc)
13253 (if_then_else (match_operator 2 "comparison_operator"
13254 [(match_operand:P 1 "gpc_reg_operand" "")
13255 (const_int 1)])
13256 (match_operand 5 "" "")
13257 (match_operand 6 "" "")))
13258 (set (match_operand:P 0 "gpc_reg_operand" "")
13259 (plus:P (match_dup 1) (const_int -1)))
13260 (clobber (match_scratch:CC 3 ""))
13261 (clobber (match_scratch:P 4 ""))]
13262 "reload_completed"
13263 [(parallel [(set (match_dup 3)
13264 (compare:CC (plus:P (match_dup 1)
13265 (const_int -1))
13266 (const_int 0)))
13267 (set (match_dup 0)
13268 (plus:P (match_dup 1)
13269 (const_int -1)))])
13270 (set (pc) (if_then_else (match_dup 7)
13271 (match_dup 5)
13272 (match_dup 6)))]
13273 "
13274 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13275 operands[3], const0_rtx); }")
13276
13277 (define_split
13278 [(set (pc)
13279 (if_then_else (match_operator 2 "comparison_operator"
13280 [(match_operand:P 1 "gpc_reg_operand" "")
13281 (const_int 1)])
13282 (match_operand 5 "" "")
13283 (match_operand 6 "" "")))
13284 (set (match_operand:P 0 "nonimmediate_operand" "")
13285 (plus:P (match_dup 1) (const_int -1)))
13286 (clobber (match_scratch:CC 3 ""))
13287 (clobber (match_scratch:P 4 ""))]
13288 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13289 [(parallel [(set (match_dup 3)
13290 (compare:CC (plus:P (match_dup 1)
13291 (const_int -1))
13292 (const_int 0)))
13293 (set (match_dup 4)
13294 (plus:P (match_dup 1)
13295 (const_int -1)))])
13296 (set (match_dup 0)
13297 (match_dup 4))
13298 (set (pc) (if_then_else (match_dup 7)
13299 (match_dup 5)
13300 (match_dup 6)))]
13301 "
13302 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13303 operands[3], const0_rtx); }")
13304 \f
13305 (define_insn "trap"
13306 [(trap_if (const_int 1) (const_int 0))]
13307 ""
13308 "trap"
13309 [(set_attr "type" "trap")])
13310
13311 (define_expand "ctrap<mode>4"
13312 [(trap_if (match_operator 0 "ordered_comparison_operator"
13313 [(match_operand:GPR 1 "register_operand")
13314 (match_operand:GPR 2 "reg_or_short_operand")])
13315 (match_operand 3 "zero_constant" ""))]
13316 ""
13317 "")
13318
13319 (define_insn ""
13320 [(trap_if (match_operator 0 "ordered_comparison_operator"
13321 [(match_operand:GPR 1 "register_operand" "r")
13322 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13323 (const_int 0))]
13324 ""
13325 "t<wd>%V0%I2 %1,%2"
13326 [(set_attr "type" "trap")])
13327 \f
13328 ;; Insns related to generating the function prologue and epilogue.
13329
13330 (define_expand "prologue"
13331 [(use (const_int 0))]
13332 ""
13333 {
13334 rs6000_emit_prologue ();
13335 if (!TARGET_SCHED_PROLOG)
13336 emit_insn (gen_blockage ());
13337 DONE;
13338 })
13339
13340 (define_insn "*movesi_from_cr_one"
13341 [(match_parallel 0 "mfcr_operation"
13342 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13343 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13344 (match_operand 3 "immediate_operand" "n")]
13345 UNSPEC_MOVESI_FROM_CR))])]
13346 "TARGET_MFCRF"
13347 "*
13348 {
13349 int mask = 0;
13350 int i;
13351 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13352 {
13353 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13354 operands[4] = GEN_INT (mask);
13355 output_asm_insn (\"mfcr %1,%4\", operands);
13356 }
13357 return \"\";
13358 }"
13359 [(set_attr "type" "mfcrf")])
13360
13361 (define_insn "movesi_from_cr"
13362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13363 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13364 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13365 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13366 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13367 UNSPEC_MOVESI_FROM_CR))]
13368 ""
13369 "mfcr %0"
13370 [(set_attr "type" "mfcr")])
13371
13372 (define_insn "*stmw"
13373 [(match_parallel 0 "stmw_operation"
13374 [(set (match_operand:SI 1 "memory_operand" "=m")
13375 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13376 "TARGET_MULTIPLE"
13377 "stmw %2,%1"
13378 [(set_attr "type" "store_ux")])
13379
13380 ; The following comment applies to:
13381 ; save_gpregs_*
13382 ; save_fpregs_*
13383 ; restore_gpregs*
13384 ; return_and_restore_gpregs*
13385 ; return_and_restore_fpregs*
13386 ; return_and_restore_fpregs_aix*
13387 ;
13388 ; The out-of-line save / restore functions expects one input argument.
13389 ; Since those are not standard call_insn's, we must avoid using
13390 ; MATCH_OPERAND for that argument. That way the register rename
13391 ; optimization will not try to rename this register.
13392 ; Each pattern is repeated for each possible register number used in
13393 ; various ABIs (r11, r1, and for some functions r12)
13394
13395 (define_insn "*save_gpregs_<mode>_r11"
13396 [(match_parallel 0 "any_parallel_operand"
13397 [(clobber (reg:P 65))
13398 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13399 (use (reg:P 11))
13400 (set (match_operand:P 2 "memory_operand" "=m")
13401 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13402 ""
13403 "bl %1"
13404 [(set_attr "type" "branch")
13405 (set_attr "length" "4")])
13406
13407 (define_insn "*save_gpregs_<mode>_r12"
13408 [(match_parallel 0 "any_parallel_operand"
13409 [(clobber (reg:P 65))
13410 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13411 (use (reg:P 12))
13412 (set (match_operand:P 2 "memory_operand" "=m")
13413 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13414 ""
13415 "bl %1"
13416 [(set_attr "type" "branch")
13417 (set_attr "length" "4")])
13418
13419 (define_insn "*save_gpregs_<mode>_r1"
13420 [(match_parallel 0 "any_parallel_operand"
13421 [(clobber (reg:P 65))
13422 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13423 (use (reg:P 1))
13424 (set (match_operand:P 2 "memory_operand" "=m")
13425 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13426 ""
13427 "bl %1"
13428 [(set_attr "type" "branch")
13429 (set_attr "length" "4")])
13430
13431 (define_insn "*save_fpregs_<mode>_r11"
13432 [(match_parallel 0 "any_parallel_operand"
13433 [(clobber (reg:P 65))
13434 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13435 (use (reg:P 11))
13436 (set (match_operand:DF 2 "memory_operand" "=m")
13437 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13438 ""
13439 "bl %1"
13440 [(set_attr "type" "branch")
13441 (set_attr "length" "4")])
13442
13443 (define_insn "*save_fpregs_<mode>_r12"
13444 [(match_parallel 0 "any_parallel_operand"
13445 [(clobber (reg:P 65))
13446 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13447 (use (reg:P 12))
13448 (set (match_operand:DF 2 "memory_operand" "=m")
13449 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13450 ""
13451 "bl %1"
13452 [(set_attr "type" "branch")
13453 (set_attr "length" "4")])
13454
13455 (define_insn "*save_fpregs_<mode>_r1"
13456 [(match_parallel 0 "any_parallel_operand"
13457 [(clobber (reg:P 65))
13458 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13459 (use (reg:P 1))
13460 (set (match_operand:DF 2 "memory_operand" "=m")
13461 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13462 ""
13463 "bl %1"
13464 [(set_attr "type" "branch")
13465 (set_attr "length" "4")])
13466
13467 ; This is to explain that changes to the stack pointer should
13468 ; not be moved over loads from or stores to stack memory.
13469 (define_insn "stack_tie"
13470 [(match_parallel 0 "tie_operand"
13471 [(set (mem:BLK (reg 1)) (const_int 0))])]
13472 ""
13473 ""
13474 [(set_attr "length" "0")])
13475
13476 (define_expand "epilogue"
13477 [(use (const_int 0))]
13478 ""
13479 {
13480 if (!TARGET_SCHED_PROLOG)
13481 emit_insn (gen_blockage ());
13482 rs6000_emit_epilogue (FALSE);
13483 DONE;
13484 })
13485
13486 ; On some processors, doing the mtcrf one CC register at a time is
13487 ; faster (like on the 604e). On others, doing them all at once is
13488 ; faster; for instance, on the 601 and 750.
13489
13490 (define_expand "movsi_to_cr_one"
13491 [(set (match_operand:CC 0 "cc_reg_operand" "")
13492 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13493 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13494 ""
13495 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13496
13497 (define_insn "*movsi_to_cr"
13498 [(match_parallel 0 "mtcrf_operation"
13499 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13500 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13501 (match_operand 3 "immediate_operand" "n")]
13502 UNSPEC_MOVESI_TO_CR))])]
13503 ""
13504 "*
13505 {
13506 int mask = 0;
13507 int i;
13508 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13509 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13510 operands[4] = GEN_INT (mask);
13511 return \"mtcrf %4,%2\";
13512 }"
13513 [(set_attr "type" "mtcr")])
13514
13515 (define_insn "*mtcrfsi"
13516 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13517 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13518 (match_operand 2 "immediate_operand" "n")]
13519 UNSPEC_MOVESI_TO_CR))]
13520 "GET_CODE (operands[0]) == REG
13521 && CR_REGNO_P (REGNO (operands[0]))
13522 && GET_CODE (operands[2]) == CONST_INT
13523 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13524 "mtcrf %R0,%1"
13525 [(set_attr "type" "mtcr")])
13526
13527 ; The load-multiple instructions have similar properties.
13528 ; Note that "load_multiple" is a name known to the machine-independent
13529 ; code that actually corresponds to the PowerPC load-string.
13530
13531 (define_insn "*lmw"
13532 [(match_parallel 0 "lmw_operation"
13533 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13534 (match_operand:SI 2 "memory_operand" "m"))])]
13535 "TARGET_MULTIPLE"
13536 "lmw %1,%2"
13537 [(set_attr "type" "load_ux")
13538 (set_attr "cell_micro" "always")])
13539
13540 (define_insn "*return_internal_<mode>"
13541 [(simple_return)
13542 (use (match_operand:P 0 "register_operand" "lc"))]
13543 ""
13544 "b%T0"
13545 [(set_attr "type" "jmpreg")])
13546
13547 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13548 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13549
13550 ; The following comment applies to:
13551 ; save_gpregs_*
13552 ; save_fpregs_*
13553 ; restore_gpregs*
13554 ; return_and_restore_gpregs*
13555 ; return_and_restore_fpregs*
13556 ; return_and_restore_fpregs_aix*
13557 ;
13558 ; The out-of-line save / restore functions expects one input argument.
13559 ; Since those are not standard call_insn's, we must avoid using
13560 ; MATCH_OPERAND for that argument. That way the register rename
13561 ; optimization will not try to rename this register.
13562 ; Each pattern is repeated for each possible register number used in
13563 ; various ABIs (r11, r1, and for some functions r12)
13564
13565 (define_insn "*restore_gpregs_<mode>_r11"
13566 [(match_parallel 0 "any_parallel_operand"
13567 [(clobber (match_operand:P 1 "register_operand" "=l"))
13568 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13569 (use (reg:P 11))
13570 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13571 (match_operand:P 4 "memory_operand" "m"))])]
13572 ""
13573 "bl %2"
13574 [(set_attr "type" "branch")
13575 (set_attr "length" "4")])
13576
13577 (define_insn "*restore_gpregs_<mode>_r12"
13578 [(match_parallel 0 "any_parallel_operand"
13579 [(clobber (match_operand:P 1 "register_operand" "=l"))
13580 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13581 (use (reg:P 12))
13582 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13583 (match_operand:P 4 "memory_operand" "m"))])]
13584 ""
13585 "bl %2"
13586 [(set_attr "type" "branch")
13587 (set_attr "length" "4")])
13588
13589 (define_insn "*restore_gpregs_<mode>_r1"
13590 [(match_parallel 0 "any_parallel_operand"
13591 [(clobber (match_operand:P 1 "register_operand" "=l"))
13592 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13593 (use (reg:P 1))
13594 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13595 (match_operand:P 4 "memory_operand" "m"))])]
13596 ""
13597 "bl %2"
13598 [(set_attr "type" "branch")
13599 (set_attr "length" "4")])
13600
13601 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13602 [(match_parallel 0 "any_parallel_operand"
13603 [(return)
13604 (clobber (match_operand:P 1 "register_operand" "=l"))
13605 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13606 (use (reg:P 11))
13607 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13608 (match_operand:P 4 "memory_operand" "m"))])]
13609 ""
13610 "b %2"
13611 [(set_attr "type" "branch")
13612 (set_attr "length" "4")])
13613
13614 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13615 [(match_parallel 0 "any_parallel_operand"
13616 [(return)
13617 (clobber (match_operand:P 1 "register_operand" "=l"))
13618 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13619 (use (reg:P 12))
13620 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13621 (match_operand:P 4 "memory_operand" "m"))])]
13622 ""
13623 "b %2"
13624 [(set_attr "type" "branch")
13625 (set_attr "length" "4")])
13626
13627 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13628 [(match_parallel 0 "any_parallel_operand"
13629 [(return)
13630 (clobber (match_operand:P 1 "register_operand" "=l"))
13631 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13632 (use (reg:P 1))
13633 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13634 (match_operand:P 4 "memory_operand" "m"))])]
13635 ""
13636 "b %2"
13637 [(set_attr "type" "branch")
13638 (set_attr "length" "4")])
13639
13640 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13641 [(match_parallel 0 "any_parallel_operand"
13642 [(return)
13643 (clobber (match_operand:P 1 "register_operand" "=l"))
13644 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13645 (use (reg:P 11))
13646 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13647 (match_operand:DF 4 "memory_operand" "m"))])]
13648 ""
13649 "b %2"
13650 [(set_attr "type" "branch")
13651 (set_attr "length" "4")])
13652
13653 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13654 [(match_parallel 0 "any_parallel_operand"
13655 [(return)
13656 (clobber (match_operand:P 1 "register_operand" "=l"))
13657 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13658 (use (reg:P 12))
13659 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13660 (match_operand:DF 4 "memory_operand" "m"))])]
13661 ""
13662 "b %2"
13663 [(set_attr "type" "branch")
13664 (set_attr "length" "4")])
13665
13666 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13667 [(match_parallel 0 "any_parallel_operand"
13668 [(return)
13669 (clobber (match_operand:P 1 "register_operand" "=l"))
13670 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13671 (use (reg:P 1))
13672 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13673 (match_operand:DF 4 "memory_operand" "m"))])]
13674 ""
13675 "b %2"
13676 [(set_attr "type" "branch")
13677 (set_attr "length" "4")])
13678
13679 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13680 [(match_parallel 0 "any_parallel_operand"
13681 [(return)
13682 (use (match_operand:P 1 "register_operand" "l"))
13683 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13684 (use (reg:P 11))
13685 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13686 (match_operand:DF 4 "memory_operand" "m"))])]
13687 ""
13688 "b %2"
13689 [(set_attr "type" "branch")
13690 (set_attr "length" "4")])
13691
13692 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
13693 [(match_parallel 0 "any_parallel_operand"
13694 [(return)
13695 (use (match_operand:P 1 "register_operand" "l"))
13696 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13697 (use (reg:P 1))
13698 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13699 (match_operand:DF 4 "memory_operand" "m"))])]
13700 ""
13701 "b %2"
13702 [(set_attr "type" "branch")
13703 (set_attr "length" "4")])
13704
13705 ; This is used in compiling the unwind routines.
13706 (define_expand "eh_return"
13707 [(use (match_operand 0 "general_operand" ""))]
13708 ""
13709 "
13710 {
13711 if (TARGET_32BIT)
13712 emit_insn (gen_eh_set_lr_si (operands[0]));
13713 else
13714 emit_insn (gen_eh_set_lr_di (operands[0]));
13715 DONE;
13716 }")
13717
13718 ; We can't expand this before we know where the link register is stored.
13719 (define_insn "eh_set_lr_<mode>"
13720 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13721 UNSPECV_EH_RR)
13722 (clobber (match_scratch:P 1 "=&b"))]
13723 ""
13724 "#")
13725
13726 (define_split
13727 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13728 (clobber (match_scratch 1 ""))]
13729 "reload_completed"
13730 [(const_int 0)]
13731 "
13732 {
13733 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13734 DONE;
13735 }")
13736
13737 (define_insn "prefetch"
13738 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13739 (match_operand:SI 1 "const_int_operand" "n")
13740 (match_operand:SI 2 "const_int_operand" "n"))]
13741 ""
13742 "*
13743 {
13744 if (GET_CODE (operands[0]) == REG)
13745 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13746 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13747 }"
13748 [(set_attr "type" "load")])
13749 \f
13750 (define_insn "bpermd_<mode>"
13751 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13752 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
13753 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
13754 "TARGET_POPCNTD"
13755 "bpermd %0,%1,%2"
13756 [(set_attr "type" "integer")])
13757
13758 \f
13759 ;; Builtin fma support. Handle
13760 ;; Note that the conditions for expansion are in the FMA_F iterator.
13761
13762 (define_expand "fma<mode>4"
13763 [(set (match_operand:FMA_F 0 "register_operand" "")
13764 (fma:FMA_F
13765 (match_operand:FMA_F 1 "register_operand" "")
13766 (match_operand:FMA_F 2 "register_operand" "")
13767 (match_operand:FMA_F 3 "register_operand" "")))]
13768 ""
13769 "")
13770
13771 ; Altivec only has fma and nfms.
13772 (define_expand "fms<mode>4"
13773 [(set (match_operand:FMA_F 0 "register_operand" "")
13774 (fma:FMA_F
13775 (match_operand:FMA_F 1 "register_operand" "")
13776 (match_operand:FMA_F 2 "register_operand" "")
13777 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
13778 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13779 "")
13780
13781 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
13782 (define_expand "fnma<mode>4"
13783 [(set (match_operand:FMA_F 0 "register_operand" "")
13784 (neg:FMA_F
13785 (fma:FMA_F
13786 (match_operand:FMA_F 1 "register_operand" "")
13787 (match_operand:FMA_F 2 "register_operand" "")
13788 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13789 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
13790 "")
13791
13792 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
13793 (define_expand "fnms<mode>4"
13794 [(set (match_operand:FMA_F 0 "register_operand" "")
13795 (neg:FMA_F
13796 (fma:FMA_F
13797 (match_operand:FMA_F 1 "register_operand" "")
13798 (match_operand:FMA_F 2 "register_operand" "")
13799 (match_operand:FMA_F 3 "register_operand" ""))))]
13800 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13801 "")
13802
13803 ; Not an official optab name, but used from builtins.
13804 (define_expand "nfma<mode>4"
13805 [(set (match_operand:FMA_F 0 "register_operand" "")
13806 (neg:FMA_F
13807 (fma:FMA_F
13808 (match_operand:FMA_F 1 "register_operand" "")
13809 (match_operand:FMA_F 2 "register_operand" "")
13810 (match_operand:FMA_F 3 "register_operand" ""))))]
13811 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13812 "")
13813
13814 ; Not an official optab name, but used from builtins.
13815 (define_expand "nfms<mode>4"
13816 [(set (match_operand:FMA_F 0 "register_operand" "")
13817 (neg:FMA_F
13818 (fma:FMA_F
13819 (match_operand:FMA_F 1 "register_operand" "")
13820 (match_operand:FMA_F 2 "register_operand" "")
13821 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13822 ""
13823 "")
13824
13825 (define_expand "rs6000_get_timebase"
13826 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
13827 ""
13828 {
13829 if (TARGET_POWERPC64)
13830 emit_insn (gen_rs6000_mftb_di (operands[0]));
13831 else
13832 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
13833 DONE;
13834 })
13835
13836 (define_insn "rs6000_get_timebase_ppc32"
13837 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13838 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
13839 (clobber (match_scratch:SI 1 "=r"))
13840 (clobber (match_scratch:CC 2 "=y"))]
13841 "!TARGET_POWERPC64"
13842 {
13843 if (WORDS_BIG_ENDIAN)
13844 if (TARGET_MFCRF)
13845 {
13846 return "mfspr %0,269\;"
13847 "mfspr %L0,268\;"
13848 "mfspr %1,269\;"
13849 "cmpw %2,%0,%1\;"
13850 "bne- %2,$-16";
13851 }
13852 else
13853 {
13854 return "mftbu %0\;"
13855 "mftb %L0\;"
13856 "mftbu %1\;"
13857 "cmpw %2,%0,%1\;"
13858 "bne- %2,$-16";
13859 }
13860 else
13861 if (TARGET_MFCRF)
13862 {
13863 return "mfspr %L0,269\;"
13864 "mfspr %0,268\;"
13865 "mfspr %1,269\;"
13866 "cmpw %2,%L0,%1\;"
13867 "bne- %2,$-16";
13868 }
13869 else
13870 {
13871 return "mftbu %L0\;"
13872 "mftb %0\;"
13873 "mftbu %1\;"
13874 "cmpw %2,%L0,%1\;"
13875 "bne- %2,$-16";
13876 }
13877 })
13878
13879 (define_insn "rs6000_mftb_<mode>"
13880 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13881 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
13882 ""
13883 {
13884 if (TARGET_MFCRF)
13885 return "mfspr %0,268";
13886 else
13887 return "mftb %0";
13888 })
13889
13890 \f
13891
13892 (include "sync.md")
13893 (include "vector.md")
13894 (include "vsx.md")
13895 (include "altivec.md")
13896 (include "spe.md")
13897 (include "dfp.md")
13898 (include "paired.md")