1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
100 (UNSPEC_DLMZB_STRLEN 47)
103 (UNSPEC_MACHOPIC_OFFSET 50)
108 ;; UNSPEC_VOLATILE usage
113 (UNSPECV_LL 1) ; load-locked
114 (UNSPECV_SC 2) ; store-conditional
115 (UNSPECV_EH_RR 9) ; eh_reg_restore
118 ;; Define an insn type attribute. This is used in function unit delay
120 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
121 (const_string "integer"))
123 ;; Define floating point instruction sub-types for use with Xfpu.md
124 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
126 ;; Length (in bytes).
127 ; '(pc)' in the following doesn't include the instruction itself; it is
128 ; calculated as if the instruction had zero size.
129 (define_attr "length" ""
130 (if_then_else (eq_attr "type" "branch")
131 (if_then_else (and (ge (minus (match_dup 0) (pc))
133 (lt (minus (match_dup 0) (pc))
139 ;; Processor type -- this attribute must exactly match the processor_type
140 ;; enumeration in rs6000.h.
142 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,power7,cell"
143 (const (symbol_ref "rs6000_cpu_attr")))
146 ;; If this instruction is microcoded on the CELL processor
147 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
148 (define_attr "cell_micro" "not,conditional,always"
149 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
150 (const_string "always")
151 (const_string "not")))
153 (automata_option "ndfa")
166 (include "e300c2c3.md")
167 (include "e500mc.md")
168 (include "power4.md")
169 (include "power5.md")
170 (include "power6.md")
171 (include "power7.md")
175 (include "predicates.md")
176 (include "constraints.md")
178 (include "darwin.md")
183 ; This mode iterator allows :GPR to be used to indicate the allowable size
184 ; of whole values in GPRs.
185 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
187 ; Any supported integer mode.
188 (define_mode_iterator INT [QI HI SI DI TI])
190 ; Any supported integer mode that fits in one register.
191 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
193 ; extend modes for DImode
194 (define_mode_iterator QHSI [QI HI SI])
196 ; SImode or DImode, even if DImode doesn't fit in GPRs.
197 (define_mode_iterator SDI [SI DI])
199 ; The size of a pointer. Also, the size of the value that a record-condition
200 ; (one with a '.') will compare.
201 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
203 ; Any hardware-supported floating-point mode
204 (define_mode_iterator FP [
205 (SF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
207 (DF "TARGET_HARD_FLOAT
208 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
209 (TF "!TARGET_IEEEQUAD
211 && (TARGET_FPRS || TARGET_E500_DOUBLE)
212 && TARGET_LONG_DOUBLE_128")
216 ; Various instructions that come in SI and DI forms.
217 ; A generic w/d attribute, for things like cmpw/cmpd.
218 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
221 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
223 ;; ISEL/ISEL64 target selection
224 (define_mode_attr sel [(SI "") (DI "64")])
226 ;; Suffix for reload patterns
227 (define_mode_attr ptrsize [(SI "32bit")
230 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
231 (DI "TARGET_64BIT")])
233 (define_mode_attr mptrsize [(SI "si")
237 ;; Start with fixed-point load and store insns. Here we put only the more
238 ;; complex forms. Basic data transfer is done later.
240 (define_expand "zero_extend<mode>di2"
241 [(set (match_operand:DI 0 "gpc_reg_operand" "")
242 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
246 (define_insn "*zero_extend<mode>di2_internal1"
247 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
248 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
252 rldicl %0,%1,0,<dbits>"
253 [(set_attr "type" "load,*")])
255 (define_insn "*zero_extend<mode>di2_internal2"
256 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
257 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
259 (clobber (match_scratch:DI 2 "=r,r"))]
262 rldicl. %2,%1,0,<dbits>
264 [(set_attr "type" "compare")
265 (set_attr "length" "4,8")])
268 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
269 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
271 (clobber (match_scratch:DI 2 ""))]
272 "TARGET_POWERPC64 && reload_completed"
274 (zero_extend:DI (match_dup 1)))
276 (compare:CC (match_dup 2)
280 (define_insn "*zero_extend<mode>di2_internal3"
281 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
282 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
284 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
285 (zero_extend:DI (match_dup 1)))]
288 rldicl. %0,%1,0,<dbits>
290 [(set_attr "type" "compare")
291 (set_attr "length" "4,8")])
294 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
295 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
297 (set (match_operand:DI 0 "gpc_reg_operand" "")
298 (zero_extend:DI (match_dup 1)))]
299 "TARGET_POWERPC64 && reload_completed"
301 (zero_extend:DI (match_dup 1)))
303 (compare:CC (match_dup 0)
307 (define_insn "extendqidi2"
308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
309 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
312 [(set_attr "type" "exts")])
315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
316 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
318 (clobber (match_scratch:DI 2 "=r,r"))]
323 [(set_attr "type" "compare")
324 (set_attr "length" "4,8")])
327 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
328 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
330 (clobber (match_scratch:DI 2 ""))]
331 "TARGET_POWERPC64 && reload_completed"
333 (sign_extend:DI (match_dup 1)))
335 (compare:CC (match_dup 2)
340 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
341 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
343 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
344 (sign_extend:DI (match_dup 1)))]
349 [(set_attr "type" "compare")
350 (set_attr "length" "4,8")])
353 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
354 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
356 (set (match_operand:DI 0 "gpc_reg_operand" "")
357 (sign_extend:DI (match_dup 1)))]
358 "TARGET_POWERPC64 && reload_completed"
360 (sign_extend:DI (match_dup 1)))
362 (compare:CC (match_dup 0)
366 (define_expand "extendhidi2"
367 [(set (match_operand:DI 0 "gpc_reg_operand" "")
368 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
374 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
375 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
379 [(set_attr "type" "load_ext,exts")])
382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
383 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
384 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
386 [(set_attr "type" "exts")])
389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
390 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
392 (clobber (match_scratch:DI 2 "=r,r"))]
397 [(set_attr "type" "compare")
398 (set_attr "length" "4,8")])
401 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
402 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
404 (clobber (match_scratch:DI 2 ""))]
405 "TARGET_POWERPC64 && reload_completed"
407 (sign_extend:DI (match_dup 1)))
409 (compare:CC (match_dup 2)
414 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
415 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
417 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
418 (sign_extend:DI (match_dup 1)))]
423 [(set_attr "type" "compare")
424 (set_attr "length" "4,8")])
427 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
428 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
430 (set (match_operand:DI 0 "gpc_reg_operand" "")
431 (sign_extend:DI (match_dup 1)))]
432 "TARGET_POWERPC64 && reload_completed"
434 (sign_extend:DI (match_dup 1)))
436 (compare:CC (match_dup 0)
440 (define_expand "extendsidi2"
441 [(set (match_operand:DI 0 "gpc_reg_operand" "")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
447 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
448 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
449 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
453 [(set_attr "type" "load_ext,exts")])
456 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
457 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
458 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
460 [(set_attr "type" "exts")])
463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
464 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
466 (clobber (match_scratch:DI 2 "=r,r"))]
471 [(set_attr "type" "compare")
472 (set_attr "length" "4,8")])
475 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
476 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
478 (clobber (match_scratch:DI 2 ""))]
479 "TARGET_POWERPC64 && reload_completed"
481 (sign_extend:DI (match_dup 1)))
483 (compare:CC (match_dup 2)
488 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
489 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
491 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
492 (sign_extend:DI (match_dup 1)))]
497 [(set_attr "type" "compare")
498 (set_attr "length" "4,8")])
501 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
502 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
504 (set (match_operand:DI 0 "gpc_reg_operand" "")
505 (sign_extend:DI (match_dup 1)))]
506 "TARGET_POWERPC64 && reload_completed"
508 (sign_extend:DI (match_dup 1)))
510 (compare:CC (match_dup 0)
514 (define_expand "zero_extendqisi2"
515 [(set (match_operand:SI 0 "gpc_reg_operand" "")
516 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
522 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
526 {rlinm|rlwinm} %0,%1,0,0xff"
527 [(set_attr "type" "load,*")])
530 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
531 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
533 (clobber (match_scratch:SI 2 "=r,r"))]
536 {andil.|andi.} %2,%1,0xff
538 [(set_attr "type" "fast_compare,compare")
539 (set_attr "length" "4,8")])
542 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
543 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
545 (clobber (match_scratch:SI 2 ""))]
548 (zero_extend:SI (match_dup 1)))
550 (compare:CC (match_dup 2)
555 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
556 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
558 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
559 (zero_extend:SI (match_dup 1)))]
562 {andil.|andi.} %0,%1,0xff
564 [(set_attr "type" "fast_compare,compare")
565 (set_attr "length" "4,8")])
568 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
569 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
571 (set (match_operand:SI 0 "gpc_reg_operand" "")
572 (zero_extend:SI (match_dup 1)))]
575 (zero_extend:SI (match_dup 1)))
577 (compare:CC (match_dup 0)
581 (define_expand "extendqisi2"
582 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
583 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
588 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
589 else if (TARGET_POWER)
590 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
592 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
596 (define_insn "extendqisi2_ppc"
597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
598 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
601 [(set_attr "type" "exts")])
604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
605 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (clobber (match_scratch:SI 2 "=r,r"))]
612 [(set_attr "type" "compare")
613 (set_attr "length" "4,8")])
616 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (clobber (match_scratch:SI 2 ""))]
620 "TARGET_POWERPC && reload_completed"
622 (sign_extend:SI (match_dup 1)))
624 (compare:CC (match_dup 2)
629 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
630 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
633 (sign_extend:SI (match_dup 1)))]
638 [(set_attr "type" "compare")
639 (set_attr "length" "4,8")])
642 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
643 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (set (match_operand:SI 0 "gpc_reg_operand" "")
646 (sign_extend:SI (match_dup 1)))]
647 "TARGET_POWERPC && reload_completed"
649 (sign_extend:SI (match_dup 1)))
651 (compare:CC (match_dup 0)
655 (define_expand "extendqisi2_power"
656 [(parallel [(set (match_dup 2)
657 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
659 (clobber (scratch:SI))])
660 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
661 (ashiftrt:SI (match_dup 2)
663 (clobber (scratch:SI))])]
666 { operands[1] = gen_lowpart (SImode, operands[1]);
667 operands[2] = gen_reg_rtx (SImode); }")
669 (define_expand "extendqisi2_no_power"
671 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
673 (set (match_operand:SI 0 "gpc_reg_operand" "")
674 (ashiftrt:SI (match_dup 2)
676 "! TARGET_POWER && ! TARGET_POWERPC"
678 { operands[1] = gen_lowpart (SImode, operands[1]);
679 operands[2] = gen_reg_rtx (SImode); }")
681 (define_expand "zero_extendqihi2"
682 [(set (match_operand:HI 0 "gpc_reg_operand" "")
683 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
688 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
689 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
693 {rlinm|rlwinm} %0,%1,0,0xff"
694 [(set_attr "type" "load,*")])
697 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
698 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
700 (clobber (match_scratch:HI 2 "=r,r"))]
703 {andil.|andi.} %2,%1,0xff
705 [(set_attr "type" "fast_compare,compare")
706 (set_attr "length" "4,8")])
709 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
712 (clobber (match_scratch:HI 2 ""))]
715 (zero_extend:HI (match_dup 1)))
717 (compare:CC (match_dup 2)
722 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
723 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
725 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
726 (zero_extend:HI (match_dup 1)))]
729 {andil.|andi.} %0,%1,0xff
731 [(set_attr "type" "fast_compare,compare")
732 (set_attr "length" "4,8")])
735 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
736 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
738 (set (match_operand:HI 0 "gpc_reg_operand" "")
739 (zero_extend:HI (match_dup 1)))]
742 (zero_extend:HI (match_dup 1)))
744 (compare:CC (match_dup 0)
748 (define_expand "extendqihi2"
749 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
750 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
755 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
756 else if (TARGET_POWER)
757 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
759 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
763 (define_insn "extendqihi2_ppc"
764 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
765 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
768 [(set_attr "type" "exts")])
771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
772 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
774 (clobber (match_scratch:HI 2 "=r,r"))]
779 [(set_attr "type" "compare")
780 (set_attr "length" "4,8")])
783 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
784 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
786 (clobber (match_scratch:HI 2 ""))]
787 "TARGET_POWERPC && reload_completed"
789 (sign_extend:HI (match_dup 1)))
791 (compare:CC (match_dup 2)
796 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
797 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
799 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
800 (sign_extend:HI (match_dup 1)))]
805 [(set_attr "type" "compare")
806 (set_attr "length" "4,8")])
809 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
810 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
812 (set (match_operand:HI 0 "gpc_reg_operand" "")
813 (sign_extend:HI (match_dup 1)))]
814 "TARGET_POWERPC && reload_completed"
816 (sign_extend:HI (match_dup 1)))
818 (compare:CC (match_dup 0)
822 (define_expand "extendqihi2_power"
823 [(parallel [(set (match_dup 2)
824 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
826 (clobber (scratch:SI))])
827 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
828 (ashiftrt:SI (match_dup 2)
830 (clobber (scratch:SI))])]
833 { operands[0] = gen_lowpart (SImode, operands[0]);
834 operands[1] = gen_lowpart (SImode, operands[1]);
835 operands[2] = gen_reg_rtx (SImode); }")
837 (define_expand "extendqihi2_no_power"
839 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
841 (set (match_operand:HI 0 "gpc_reg_operand" "")
842 (ashiftrt:SI (match_dup 2)
844 "! TARGET_POWER && ! TARGET_POWERPC"
846 { operands[0] = gen_lowpart (SImode, operands[0]);
847 operands[1] = gen_lowpart (SImode, operands[1]);
848 operands[2] = gen_reg_rtx (SImode); }")
850 (define_expand "zero_extendhisi2"
851 [(set (match_operand:SI 0 "gpc_reg_operand" "")
852 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
858 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
862 {rlinm|rlwinm} %0,%1,0,0xffff"
863 [(set_attr "type" "load,*")])
866 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
867 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
869 (clobber (match_scratch:SI 2 "=r,r"))]
872 {andil.|andi.} %2,%1,0xffff
874 [(set_attr "type" "fast_compare,compare")
875 (set_attr "length" "4,8")])
878 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
879 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
881 (clobber (match_scratch:SI 2 ""))]
884 (zero_extend:SI (match_dup 1)))
886 (compare:CC (match_dup 2)
891 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
892 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
894 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
895 (zero_extend:SI (match_dup 1)))]
898 {andil.|andi.} %0,%1,0xffff
900 [(set_attr "type" "fast_compare,compare")
901 (set_attr "length" "4,8")])
904 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
905 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
907 (set (match_operand:SI 0 "gpc_reg_operand" "")
908 (zero_extend:SI (match_dup 1)))]
911 (zero_extend:SI (match_dup 1)))
913 (compare:CC (match_dup 0)
917 (define_expand "extendhisi2"
918 [(set (match_operand:SI 0 "gpc_reg_operand" "")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
925 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
926 "rs6000_gen_cell_microcode"
930 [(set_attr "type" "load_ext,exts")])
933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
934 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
935 "!rs6000_gen_cell_microcode"
937 [(set_attr "type" "exts")])
940 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
941 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
943 (clobber (match_scratch:SI 2 "=r,r"))]
948 [(set_attr "type" "compare")
949 (set_attr "length" "4,8")])
952 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
953 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
955 (clobber (match_scratch:SI 2 ""))]
958 (sign_extend:SI (match_dup 1)))
960 (compare:CC (match_dup 2)
965 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
966 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
968 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
969 (sign_extend:SI (match_dup 1)))]
974 [(set_attr "type" "compare")
975 (set_attr "length" "4,8")])
977 ;; IBM 405, 440 and 464 half-word multiplication operations.
979 (define_insn "*macchwc"
980 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
981 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
982 (match_operand:SI 2 "gpc_reg_operand" "r")
985 (match_operand:HI 1 "gpc_reg_operand" "r")))
986 (match_operand:SI 4 "gpc_reg_operand" "0"))
988 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
989 (plus:SI (mult:SI (ashiftrt:SI
997 [(set_attr "type" "imul3")])
999 (define_insn "*macchw"
1000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1001 (plus:SI (mult:SI (ashiftrt:SI
1002 (match_operand:SI 2 "gpc_reg_operand" "r")
1005 (match_operand:HI 1 "gpc_reg_operand" "r")))
1006 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1009 [(set_attr "type" "imul3")])
1011 (define_insn "*macchwuc"
1012 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1013 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1014 (match_operand:SI 2 "gpc_reg_operand" "r")
1017 (match_operand:HI 1 "gpc_reg_operand" "r")))
1018 (match_operand:SI 4 "gpc_reg_operand" "0"))
1020 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1021 (plus:SI (mult:SI (lshiftrt:SI
1028 "macchwu. %0, %1, %2"
1029 [(set_attr "type" "imul3")])
1031 (define_insn "*macchwu"
1032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1033 (plus:SI (mult:SI (lshiftrt:SI
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1037 (match_operand:HI 1 "gpc_reg_operand" "r")))
1038 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1040 "macchwu %0, %1, %2"
1041 [(set_attr "type" "imul3")])
1043 (define_insn "*machhwc"
1044 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1045 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1046 (match_operand:SI 1 "gpc_reg_operand" "%r")
1049 (match_operand:SI 2 "gpc_reg_operand" "r")
1051 (match_operand:SI 4 "gpc_reg_operand" "0"))
1053 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1054 (plus:SI (mult:SI (ashiftrt:SI
1062 "machhw. %0, %1, %2"
1063 [(set_attr "type" "imul3")])
1065 (define_insn "*machhw"
1066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1067 (plus:SI (mult:SI (ashiftrt:SI
1068 (match_operand:SI 1 "gpc_reg_operand" "%r")
1071 (match_operand:SI 2 "gpc_reg_operand" "r")
1073 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1076 [(set_attr "type" "imul3")])
1078 (define_insn "*machhwuc"
1079 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1080 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1081 (match_operand:SI 1 "gpc_reg_operand" "%r")
1084 (match_operand:SI 2 "gpc_reg_operand" "r")
1086 (match_operand:SI 4 "gpc_reg_operand" "0"))
1088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1089 (plus:SI (mult:SI (lshiftrt:SI
1097 "machhwu. %0, %1, %2"
1098 [(set_attr "type" "imul3")])
1100 (define_insn "*machhwu"
1101 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1102 (plus:SI (mult:SI (lshiftrt:SI
1103 (match_operand:SI 1 "gpc_reg_operand" "%r")
1106 (match_operand:SI 2 "gpc_reg_operand" "r")
1108 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1110 "machhwu %0, %1, %2"
1111 [(set_attr "type" "imul3")])
1113 (define_insn "*maclhwc"
1114 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1115 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1116 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1118 (match_operand:HI 2 "gpc_reg_operand" "r")))
1119 (match_operand:SI 4 "gpc_reg_operand" "0"))
1121 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1122 (plus:SI (mult:SI (sign_extend:SI
1128 "maclhw. %0, %1, %2"
1129 [(set_attr "type" "imul3")])
1131 (define_insn "*maclhw"
1132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1133 (plus:SI (mult:SI (sign_extend:SI
1134 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1136 (match_operand:HI 2 "gpc_reg_operand" "r")))
1137 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1140 [(set_attr "type" "imul3")])
1142 (define_insn "*maclhwuc"
1143 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1144 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1145 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1147 (match_operand:HI 2 "gpc_reg_operand" "r")))
1148 (match_operand:SI 4 "gpc_reg_operand" "0"))
1150 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1151 (plus:SI (mult:SI (zero_extend:SI
1157 "maclhwu. %0, %1, %2"
1158 [(set_attr "type" "imul3")])
1160 (define_insn "*maclhwu"
1161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1162 (plus:SI (mult:SI (zero_extend:SI
1163 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1165 (match_operand:HI 2 "gpc_reg_operand" "r")))
1166 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1168 "maclhwu %0, %1, %2"
1169 [(set_attr "type" "imul3")])
1171 (define_insn "*nmacchwc"
1172 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1173 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1174 (mult:SI (ashiftrt:SI
1175 (match_operand:SI 2 "gpc_reg_operand" "r")
1178 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1180 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1181 (minus:SI (match_dup 4)
1182 (mult:SI (ashiftrt:SI
1188 "nmacchw. %0, %1, %2"
1189 [(set_attr "type" "imul3")])
1191 (define_insn "*nmacchw"
1192 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1193 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1194 (mult:SI (ashiftrt:SI
1195 (match_operand:SI 2 "gpc_reg_operand" "r")
1198 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1200 "nmacchw %0, %1, %2"
1201 [(set_attr "type" "imul3")])
1203 (define_insn "*nmachhwc"
1204 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1205 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1206 (mult:SI (ashiftrt:SI
1207 (match_operand:SI 1 "gpc_reg_operand" "%r")
1210 (match_operand:SI 2 "gpc_reg_operand" "r")
1213 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1214 (minus:SI (match_dup 4)
1215 (mult:SI (ashiftrt:SI
1222 "nmachhw. %0, %1, %2"
1223 [(set_attr "type" "imul3")])
1225 (define_insn "*nmachhw"
1226 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1227 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1228 (mult:SI (ashiftrt:SI
1229 (match_operand:SI 1 "gpc_reg_operand" "%r")
1232 (match_operand:SI 2 "gpc_reg_operand" "r")
1235 "nmachhw %0, %1, %2"
1236 [(set_attr "type" "imul3")])
1238 (define_insn "*nmaclhwc"
1239 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1240 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1241 (mult:SI (sign_extend:SI
1242 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1244 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1246 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1247 (minus:SI (match_dup 4)
1248 (mult:SI (sign_extend:SI
1253 "nmaclhw. %0, %1, %2"
1254 [(set_attr "type" "imul3")])
1256 (define_insn "*nmaclhw"
1257 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1258 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1259 (mult:SI (sign_extend:SI
1260 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1262 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1264 "nmaclhw %0, %1, %2"
1265 [(set_attr "type" "imul3")])
1267 (define_insn "*mulchwc"
1268 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1269 (compare:CC (mult:SI (ashiftrt:SI
1270 (match_operand:SI 2 "gpc_reg_operand" "r")
1273 (match_operand:HI 1 "gpc_reg_operand" "r")))
1275 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1276 (mult:SI (ashiftrt:SI
1282 "mulchw. %0, %1, %2"
1283 [(set_attr "type" "imul3")])
1285 (define_insn "*mulchw"
1286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (mult:SI (ashiftrt:SI
1288 (match_operand:SI 2 "gpc_reg_operand" "r")
1291 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1294 [(set_attr "type" "imul3")])
1296 (define_insn "*mulchwuc"
1297 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1298 (compare:CC (mult:SI (lshiftrt:SI
1299 (match_operand:SI 2 "gpc_reg_operand" "r")
1302 (match_operand:HI 1 "gpc_reg_operand" "r")))
1304 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1305 (mult:SI (lshiftrt:SI
1311 "mulchwu. %0, %1, %2"
1312 [(set_attr "type" "imul3")])
1314 (define_insn "*mulchwu"
1315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1316 (mult:SI (lshiftrt:SI
1317 (match_operand:SI 2 "gpc_reg_operand" "r")
1320 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1322 "mulchwu %0, %1, %2"
1323 [(set_attr "type" "imul3")])
1325 (define_insn "*mulhhwc"
1326 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1327 (compare:CC (mult:SI (ashiftrt:SI
1328 (match_operand:SI 1 "gpc_reg_operand" "%r")
1331 (match_operand:SI 2 "gpc_reg_operand" "r")
1334 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1335 (mult:SI (ashiftrt:SI
1342 "mulhhw. %0, %1, %2"
1343 [(set_attr "type" "imul3")])
1345 (define_insn "*mulhhw"
1346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1347 (mult:SI (ashiftrt:SI
1348 (match_operand:SI 1 "gpc_reg_operand" "%r")
1351 (match_operand:SI 2 "gpc_reg_operand" "r")
1355 [(set_attr "type" "imul3")])
1357 (define_insn "*mulhhwuc"
1358 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1359 (compare:CC (mult:SI (lshiftrt:SI
1360 (match_operand:SI 1 "gpc_reg_operand" "%r")
1363 (match_operand:SI 2 "gpc_reg_operand" "r")
1366 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1367 (mult:SI (lshiftrt:SI
1374 "mulhhwu. %0, %1, %2"
1375 [(set_attr "type" "imul3")])
1377 (define_insn "*mulhhwu"
1378 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1379 (mult:SI (lshiftrt:SI
1380 (match_operand:SI 1 "gpc_reg_operand" "%r")
1383 (match_operand:SI 2 "gpc_reg_operand" "r")
1386 "mulhhwu %0, %1, %2"
1387 [(set_attr "type" "imul3")])
1389 (define_insn "*mullhwc"
1390 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1391 (compare:CC (mult:SI (sign_extend:SI
1392 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1394 (match_operand:HI 2 "gpc_reg_operand" "r")))
1396 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1397 (mult:SI (sign_extend:SI
1402 "mullhw. %0, %1, %2"
1403 [(set_attr "type" "imul3")])
1405 (define_insn "*mullhw"
1406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1407 (mult:SI (sign_extend:SI
1408 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1410 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1413 [(set_attr "type" "imul3")])
1415 (define_insn "*mullhwuc"
1416 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1417 (compare:CC (mult:SI (zero_extend:SI
1418 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1420 (match_operand:HI 2 "gpc_reg_operand" "r")))
1422 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1423 (mult:SI (zero_extend:SI
1428 "mullhwu. %0, %1, %2"
1429 [(set_attr "type" "imul3")])
1431 (define_insn "*mullhwu"
1432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1433 (mult:SI (zero_extend:SI
1434 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1436 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1438 "mullhwu %0, %1, %2"
1439 [(set_attr "type" "imul3")])
1441 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1442 (define_insn "dlmzb"
1443 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1444 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1445 (match_operand:SI 2 "gpc_reg_operand" "r")]
1447 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1448 (unspec:SI [(match_dup 1)
1452 "dlmzb. %0, %1, %2")
1454 (define_expand "strlensi"
1455 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1456 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1457 (match_operand:QI 2 "const_int_operand" "")
1458 (match_operand 3 "const_int_operand" "")]
1459 UNSPEC_DLMZB_STRLEN))
1460 (clobber (match_scratch:CC 4 "=x"))]
1461 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1463 rtx result = operands[0];
1464 rtx src = operands[1];
1465 rtx search_char = operands[2];
1466 rtx align = operands[3];
1467 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1468 rtx loop_label, end_label, mem, cr0, cond;
1469 if (search_char != const0_rtx
1470 || GET_CODE (align) != CONST_INT
1471 || INTVAL (align) < 8)
1473 word1 = gen_reg_rtx (SImode);
1474 word2 = gen_reg_rtx (SImode);
1475 scratch_dlmzb = gen_reg_rtx (SImode);
1476 scratch_string = gen_reg_rtx (Pmode);
1477 loop_label = gen_label_rtx ();
1478 end_label = gen_label_rtx ();
1479 addr = force_reg (Pmode, XEXP (src, 0));
1480 emit_move_insn (scratch_string, addr);
1481 emit_label (loop_label);
1482 mem = change_address (src, SImode, scratch_string);
1483 emit_move_insn (word1, mem);
1484 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1485 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1486 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1487 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1488 emit_jump_insn (gen_rtx_SET (VOIDmode,
1490 gen_rtx_IF_THEN_ELSE (VOIDmode,
1496 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1497 emit_jump_insn (gen_rtx_SET (VOIDmode,
1499 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1501 emit_label (end_label);
1502 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1503 emit_insn (gen_subsi3 (result, scratch_string, addr));
1504 emit_insn (gen_subsi3 (result, result, const1_rtx));
1509 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1510 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1512 (set (match_operand:SI 0 "gpc_reg_operand" "")
1513 (sign_extend:SI (match_dup 1)))]
1516 (sign_extend:SI (match_dup 1)))
1518 (compare:CC (match_dup 0)
1522 ;; Fixed-point arithmetic insns.
1524 (define_expand "add<mode>3"
1525 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1526 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1527 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1530 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1532 if (non_short_cint_operand (operands[2], DImode))
1535 else if (GET_CODE (operands[2]) == CONST_INT
1536 && ! add_operand (operands[2], <MODE>mode))
1538 rtx tmp = ((!can_create_pseudo_p ()
1539 || rtx_equal_p (operands[0], operands[1]))
1540 ? operands[0] : gen_reg_rtx (<MODE>mode));
1542 HOST_WIDE_INT val = INTVAL (operands[2]);
1543 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1544 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1546 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1549 /* The ordering here is important for the prolog expander.
1550 When space is allocated from the stack, adding 'low' first may
1551 produce a temporary deallocation (which would be bad). */
1552 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1553 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1558 ;; Discourage ai/addic because of carry but provide it in an alternative
1559 ;; allowing register zero as source.
1560 (define_insn "*add<mode>3_internal1"
1561 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1562 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1563 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1564 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1567 {cal %0,%2(%1)|addi %0,%1,%2}
1569 {cau|addis} %0,%1,%v2"
1570 [(set_attr "length" "4,4,4,4")])
1572 (define_insn "addsi3_high"
1573 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1574 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1575 (high:SI (match_operand 2 "" ""))))]
1576 "TARGET_MACHO && !TARGET_64BIT"
1577 "{cau|addis} %0,%1,ha16(%2)"
1578 [(set_attr "length" "4")])
1580 (define_insn "*add<mode>3_internal2"
1581 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1582 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1583 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1585 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1588 {cax.|add.} %3,%1,%2
1589 {ai.|addic.} %3,%1,%2
1592 [(set_attr "type" "fast_compare,compare,compare,compare")
1593 (set_attr "length" "4,4,8,8")])
1596 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1597 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1598 (match_operand:GPR 2 "reg_or_short_operand" ""))
1600 (clobber (match_scratch:GPR 3 ""))]
1603 (plus:GPR (match_dup 1)
1606 (compare:CC (match_dup 3)
1610 (define_insn "*add<mode>3_internal3"
1611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1612 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1613 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1615 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1616 (plus:P (match_dup 1)
1620 {cax.|add.} %0,%1,%2
1621 {ai.|addic.} %0,%1,%2
1624 [(set_attr "type" "fast_compare,compare,compare,compare")
1625 (set_attr "length" "4,4,8,8")])
1628 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1629 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1630 (match_operand:P 2 "reg_or_short_operand" ""))
1632 (set (match_operand:P 0 "gpc_reg_operand" "")
1633 (plus:P (match_dup 1) (match_dup 2)))]
1636 (plus:P (match_dup 1)
1639 (compare:CC (match_dup 0)
1643 ;; Split an add that we can't do in one insn into two insns, each of which
1644 ;; does one 16-bit part. This is used by combine. Note that the low-order
1645 ;; add should be last in case the result gets used in an address.
1648 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1649 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1650 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1652 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1653 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1655 HOST_WIDE_INT val = INTVAL (operands[2]);
1656 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1657 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1659 operands[4] = GEN_INT (low);
1660 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1661 operands[3] = GEN_INT (rest);
1662 else if (can_create_pseudo_p ())
1664 operands[3] = gen_reg_rtx (DImode);
1665 emit_move_insn (operands[3], operands[2]);
1666 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1673 (define_insn "one_cmpl<mode>2"
1674 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1675 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1681 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1683 (clobber (match_scratch:P 2 "=r,r"))]
1688 [(set_attr "type" "fast_compare,compare")
1689 (set_attr "length" "4,8")])
1692 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1693 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1695 (clobber (match_scratch:P 2 ""))]
1698 (not:P (match_dup 1)))
1700 (compare:CC (match_dup 2)
1705 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1706 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1708 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1709 (not:P (match_dup 1)))]
1714 [(set_attr "type" "fast_compare,compare")
1715 (set_attr "length" "4,8")])
1718 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1719 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1721 (set (match_operand:P 0 "gpc_reg_operand" "")
1722 (not:P (match_dup 1)))]
1725 (not:P (match_dup 1)))
1727 (compare:CC (match_dup 0)
1732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1733 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1734 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1736 "{sf%I1|subf%I1c} %0,%2,%1")
1739 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1740 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1741 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1748 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1749 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1750 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1752 (clobber (match_scratch:SI 3 "=r,r"))]
1755 {sf.|subfc.} %3,%2,%1
1757 [(set_attr "type" "compare")
1758 (set_attr "length" "4,8")])
1761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1762 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1763 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1765 (clobber (match_scratch:P 3 "=r,r"))]
1770 [(set_attr "type" "fast_compare")
1771 (set_attr "length" "4,8")])
1774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1775 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1776 (match_operand:P 2 "gpc_reg_operand" ""))
1778 (clobber (match_scratch:P 3 ""))]
1781 (minus:P (match_dup 1)
1784 (compare:CC (match_dup 3)
1789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1790 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1794 (minus:SI (match_dup 1) (match_dup 2)))]
1797 {sf.|subfc.} %0,%2,%1
1799 [(set_attr "type" "compare")
1800 (set_attr "length" "4,8")])
1803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1804 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1805 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1807 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1808 (minus:P (match_dup 1)
1814 [(set_attr "type" "fast_compare")
1815 (set_attr "length" "4,8")])
1818 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1819 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1820 (match_operand:P 2 "gpc_reg_operand" ""))
1822 (set (match_operand:P 0 "gpc_reg_operand" "")
1823 (minus:P (match_dup 1)
1827 (minus:P (match_dup 1)
1830 (compare:CC (match_dup 0)
1834 (define_expand "sub<mode>3"
1835 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1836 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1837 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1841 if (GET_CODE (operands[2]) == CONST_INT)
1843 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1844 negate_rtx (<MODE>mode, operands[2])));
1849 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1850 ;; instruction and some auxiliary computations. Then we just have a single
1851 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1854 (define_expand "sminsi3"
1856 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1857 (match_operand:SI 2 "reg_or_short_operand" ""))
1859 (minus:SI (match_dup 2) (match_dup 1))))
1860 (set (match_operand:SI 0 "gpc_reg_operand" "")
1861 (minus:SI (match_dup 2) (match_dup 3)))]
1862 "TARGET_POWER || TARGET_ISEL"
1867 operands[2] = force_reg (SImode, operands[2]);
1868 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1872 operands[3] = gen_reg_rtx (SImode);
1876 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1877 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1878 (match_operand:SI 2 "reg_or_short_operand" "")))
1879 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1882 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1884 (minus:SI (match_dup 2) (match_dup 1))))
1885 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1888 (define_expand "smaxsi3"
1890 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1891 (match_operand:SI 2 "reg_or_short_operand" ""))
1893 (minus:SI (match_dup 2) (match_dup 1))))
1894 (set (match_operand:SI 0 "gpc_reg_operand" "")
1895 (plus:SI (match_dup 3) (match_dup 1)))]
1896 "TARGET_POWER || TARGET_ISEL"
1901 operands[2] = force_reg (SImode, operands[2]);
1902 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1905 operands[3] = gen_reg_rtx (SImode);
1909 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1910 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1911 (match_operand:SI 2 "reg_or_short_operand" "")))
1912 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1915 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1917 (minus:SI (match_dup 2) (match_dup 1))))
1918 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1921 (define_expand "uminsi3"
1922 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1924 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1926 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1928 (minus:SI (match_dup 4) (match_dup 3))))
1929 (set (match_operand:SI 0 "gpc_reg_operand" "")
1930 (minus:SI (match_dup 2) (match_dup 3)))]
1931 "TARGET_POWER || TARGET_ISEL"
1936 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1939 operands[3] = gen_reg_rtx (SImode);
1940 operands[4] = gen_reg_rtx (SImode);
1941 operands[5] = GEN_INT (-2147483647 - 1);
1944 (define_expand "umaxsi3"
1945 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1947 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1949 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1951 (minus:SI (match_dup 4) (match_dup 3))))
1952 (set (match_operand:SI 0 "gpc_reg_operand" "")
1953 (plus:SI (match_dup 3) (match_dup 1)))]
1954 "TARGET_POWER || TARGET_ISEL"
1959 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1962 operands[3] = gen_reg_rtx (SImode);
1963 operands[4] = gen_reg_rtx (SImode);
1964 operands[5] = GEN_INT (-2147483647 - 1);
1968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1969 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1970 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1972 (minus:SI (match_dup 2) (match_dup 1))))]
1977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1979 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1980 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1982 (minus:SI (match_dup 2) (match_dup 1)))
1984 (clobber (match_scratch:SI 3 "=r,r"))]
1989 [(set_attr "type" "delayed_compare")
1990 (set_attr "length" "4,8")])
1993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1995 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1996 (match_operand:SI 2 "reg_or_short_operand" ""))
1998 (minus:SI (match_dup 2) (match_dup 1)))
2000 (clobber (match_scratch:SI 3 ""))]
2001 "TARGET_POWER && reload_completed"
2003 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2005 (minus:SI (match_dup 2) (match_dup 1))))
2007 (compare:CC (match_dup 3)
2012 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2014 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2015 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2017 (minus:SI (match_dup 2) (match_dup 1)))
2019 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2020 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2022 (minus:SI (match_dup 2) (match_dup 1))))]
2027 [(set_attr "type" "delayed_compare")
2028 (set_attr "length" "4,8")])
2031 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2033 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2034 (match_operand:SI 2 "reg_or_short_operand" ""))
2036 (minus:SI (match_dup 2) (match_dup 1)))
2038 (set (match_operand:SI 0 "gpc_reg_operand" "")
2039 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2041 (minus:SI (match_dup 2) (match_dup 1))))]
2042 "TARGET_POWER && reload_completed"
2044 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2046 (minus:SI (match_dup 2) (match_dup 1))))
2048 (compare:CC (match_dup 0)
2052 ;; We don't need abs with condition code because such comparisons should
2054 (define_expand "abssi2"
2055 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2056 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2062 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2065 else if (! TARGET_POWER)
2067 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2072 (define_insn "*abssi2_power"
2073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2074 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2078 (define_insn_and_split "abssi2_isel"
2079 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2080 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2081 (clobber (match_scratch:SI 2 "=&b"))
2082 (clobber (match_scratch:CC 3 "=y"))]
2085 "&& reload_completed"
2086 [(set (match_dup 2) (neg:SI (match_dup 1)))
2088 (compare:CC (match_dup 1)
2091 (if_then_else:SI (ge (match_dup 3)
2097 (define_insn_and_split "abssi2_nopower"
2098 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2099 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2100 (clobber (match_scratch:SI 2 "=&r,&r"))]
2101 "! TARGET_POWER && ! TARGET_ISEL"
2103 "&& reload_completed"
2104 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2105 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2106 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2109 (define_insn "*nabs_power"
2110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2111 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2115 (define_insn_and_split "*nabs_nopower"
2116 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2117 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2118 (clobber (match_scratch:SI 2 "=&r,&r"))]
2121 "&& reload_completed"
2122 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2123 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2124 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2127 (define_expand "neg<mode>2"
2128 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2129 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2133 (define_insn "*neg<mode>2_internal"
2134 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2135 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2141 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2143 (clobber (match_scratch:P 2 "=r,r"))]
2148 [(set_attr "type" "fast_compare")
2149 (set_attr "length" "4,8")])
2152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2153 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2155 (clobber (match_scratch:P 2 ""))]
2158 (neg:P (match_dup 1)))
2160 (compare:CC (match_dup 2)
2165 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2166 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2168 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2169 (neg:P (match_dup 1)))]
2174 [(set_attr "type" "fast_compare")
2175 (set_attr "length" "4,8")])
2178 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2179 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2181 (set (match_operand:P 0 "gpc_reg_operand" "")
2182 (neg:P (match_dup 1)))]
2185 (neg:P (match_dup 1)))
2187 (compare:CC (match_dup 0)
2191 (define_insn "clz<mode>2"
2192 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2193 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2195 "{cntlz|cntlz<wd>} %0,%1"
2196 [(set_attr "type" "cntlz")])
2198 (define_expand "ctz<mode>2"
2200 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2201 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2203 (clobber (scratch:CC))])
2204 (set (match_dup 4) (clz:GPR (match_dup 3)))
2205 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2206 (minus:GPR (match_dup 5) (match_dup 4)))]
2209 operands[2] = gen_reg_rtx (<MODE>mode);
2210 operands[3] = gen_reg_rtx (<MODE>mode);
2211 operands[4] = gen_reg_rtx (<MODE>mode);
2212 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2215 (define_expand "ffs<mode>2"
2217 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2218 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2220 (clobber (scratch:CC))])
2221 (set (match_dup 4) (clz:GPR (match_dup 3)))
2222 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2223 (minus:GPR (match_dup 5) (match_dup 4)))]
2226 operands[2] = gen_reg_rtx (<MODE>mode);
2227 operands[3] = gen_reg_rtx (<MODE>mode);
2228 operands[4] = gen_reg_rtx (<MODE>mode);
2229 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2232 (define_insn "popcntb<mode>2"
2233 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2234 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2239 (define_insn "popcntwsi2"
2240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2241 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2245 (define_insn "popcntddi2"
2246 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2247 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2248 "TARGET_POPCNTD && TARGET_POWERPC64"
2251 (define_expand "popcount<mode>2"
2252 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2253 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2254 "TARGET_POPCNTB || TARGET_POPCNTD"
2256 rs6000_emit_popcount (operands[0], operands[1]);
2260 (define_expand "parity<mode>2"
2261 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2262 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2265 rs6000_emit_parity (operands[0], operands[1]);
2269 ;; Since the hardware zeros the upper part of the register, save generating the
2270 ;; AND immediate if we are converting to unsigned
2271 (define_insn "*bswaphi2_extenddi"
2272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2274 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2277 [(set_attr "length" "4")
2278 (set_attr "type" "load")])
2280 (define_insn "*bswaphi2_extendsi"
2281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2283 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2286 [(set_attr "length" "4")
2287 (set_attr "type" "load")])
2289 (define_expand "bswaphi2"
2290 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2292 (match_operand:HI 1 "reg_or_mem_operand" "")))
2293 (clobber (match_scratch:SI 2 ""))])]
2296 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2297 operands[1] = force_reg (HImode, operands[1]);
2300 (define_insn "bswaphi2_internal"
2301 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2303 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2304 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2310 [(set_attr "length" "4,4,12")
2311 (set_attr "type" "load,store,*")])
2314 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2315 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2316 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2317 "TARGET_POWERPC && reload_completed"
2319 (zero_extract:SI (match_dup 4)
2323 (and:SI (ashift:SI (match_dup 4)
2325 (const_int 65280))) ;; 0xff00
2327 (ior:SI (match_dup 3)
2331 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2332 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2335 (define_insn "*bswapsi2_extenddi"
2336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2338 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2341 [(set_attr "length" "4")
2342 (set_attr "type" "load")])
2344 (define_expand "bswapsi2"
2345 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2347 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2350 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2351 operands[1] = force_reg (SImode, operands[1]);
2354 (define_insn "*bswapsi2_internal"
2355 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2357 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2361 {stbrx|stwbrx} %1,%y0
2363 [(set_attr "length" "4,4,12")
2364 (set_attr "type" "load,store,*")])
2367 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2368 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2371 (rotate:SI (match_dup 1) (const_int 8)))
2372 (set (zero_extract:SI (match_dup 0)
2376 (set (zero_extract:SI (match_dup 0)
2379 (rotate:SI (match_dup 1)
2383 (define_expand "bswapdi2"
2384 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2386 (match_operand:DI 1 "reg_or_mem_operand" "")))
2387 (clobber (match_scratch:DI 2 ""))
2388 (clobber (match_scratch:DI 3 ""))
2389 (clobber (match_scratch:DI 4 ""))])]
2392 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2393 operands[1] = force_reg (DImode, operands[1]);
2397 /* 32-bit needs fewer scratch registers. */
2398 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2403 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2404 (define_insn "*bswapdi2_ldbrx"
2405 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2406 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2407 (clobber (match_scratch:DI 2 "=X,X,&r"))
2408 (clobber (match_scratch:DI 3 "=X,X,&r"))
2409 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2410 "TARGET_POWERPC64 && TARGET_LDBRX
2411 && (REG_P (operands[0]) || REG_P (operands[1]))"
2416 [(set_attr "length" "4,4,36")
2417 (set_attr "type" "load,store,*")])
2419 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2420 (define_insn "*bswapdi2_64bit"
2421 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2422 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2423 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2424 (clobber (match_scratch:DI 3 "=&b,&r,&r"))
2425 (clobber (match_scratch:DI 4 "=&b,X,&r"))]
2426 "TARGET_POWERPC64 && !TARGET_LDBRX
2427 && (REG_P (operands[0]) || REG_P (operands[1]))"
2429 [(set_attr "length" "16,12,36")])
2432 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2433 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2434 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2435 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2436 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2437 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2441 rtx dest = operands[0];
2442 rtx src = operands[1];
2443 rtx op2 = operands[2];
2444 rtx op3 = operands[3];
2445 rtx op4 = operands[4];
2446 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2447 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2453 addr1 = XEXP (src, 0);
2454 if (GET_CODE (addr1) == PLUS)
2456 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2457 addr1 = XEXP (addr1, 1);
2460 emit_move_insn (op2, GEN_INT (4));
2462 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2464 if (BYTES_BIG_ENDIAN)
2466 word_high = change_address (src, SImode, addr1);
2467 word_low = change_address (src, SImode, addr2);
2471 word_high = change_address (src, SImode, addr2);
2472 word_low = change_address (src, SImode, addr1);
2475 emit_insn (gen_bswapsi2 (op3_32, word_low));
2476 emit_insn (gen_bswapsi2 (op4_32, word_high));
2477 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2478 emit_insn (gen_iordi3 (dest, dest, op4));
2482 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2483 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2484 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2485 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2486 (clobber (match_operand:DI 4 "" ""))]
2487 "TARGET_POWERPC64 && reload_completed && !TARGET_LDBRX"
2491 rtx dest = operands[0];
2492 rtx src = operands[1];
2493 rtx op2 = operands[2];
2494 rtx op3 = operands[3];
2495 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2496 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2502 addr1 = XEXP (dest, 0);
2503 if (GET_CODE (addr1) == PLUS)
2505 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2506 addr1 = XEXP (addr1, 1);
2509 emit_move_insn (op2, GEN_INT (4));
2511 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2513 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2514 if (BYTES_BIG_ENDIAN)
2516 word_high = change_address (dest, SImode, addr1);
2517 word_low = change_address (dest, SImode, addr2);
2518 emit_insn (gen_bswapsi2 (word_high, src_si));
2519 emit_insn (gen_bswapsi2 (word_low, op3_si));
2523 word_high = change_address (dest, SImode, addr2);
2524 word_low = change_address (dest, SImode, addr1);
2525 emit_insn (gen_bswapsi2 (word_low, src_si));
2526 emit_insn (gen_bswapsi2 (word_high, op3_si));
2531 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2532 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2533 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2534 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2535 (clobber (match_operand:DI 4 "" ""))]
2536 "TARGET_POWERPC64 && reload_completed"
2540 rtx dest = operands[0];
2541 rtx src = operands[1];
2542 rtx op2 = operands[2];
2543 rtx op3 = operands[3];
2544 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2545 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2546 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2547 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2549 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2550 emit_insn (gen_bswapsi2 (dest_si, src_si));
2551 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2552 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2553 emit_insn (gen_iordi3 (dest, dest, op3));
2556 (define_insn "bswapdi2_32bit"
2557 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2558 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2559 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2560 "TARGET_32BIT && (REG_P (operands[0]) || REG_P (operands[1]))"
2562 [(set_attr "length" "16,12,36")])
2565 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2566 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2567 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2568 "TARGET_32BIT && reload_completed"
2572 rtx dest = operands[0];
2573 rtx src = operands[1];
2574 rtx op2 = operands[2];
2575 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2576 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2582 addr1 = XEXP (src, 0);
2583 if (GET_CODE (addr1) == PLUS)
2585 emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2586 addr1 = XEXP (addr1, 1);
2589 emit_move_insn (op2, GEN_INT (4));
2591 addr2 = gen_rtx_PLUS (DImode, op2, addr1);
2593 if (BYTES_BIG_ENDIAN)
2595 word_high = change_address (src, SImode, addr1);
2596 word_low = change_address (src, SImode, addr2);
2600 word_high = change_address (src, SImode, addr2);
2601 word_low = change_address (src, SImode, addr1);
2604 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2605 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2609 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2610 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2611 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2612 "TARGET_32BIT && reload_completed"
2616 rtx dest = operands[0];
2617 rtx src = operands[1];
2618 rtx op2 = operands[2];
2619 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2620 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2626 addr1 = XEXP (dest, 0);
2627 if (GET_CODE (addr1) == PLUS)
2629 emit_insn (gen_addsi3 (op2, XEXP (addr1, 0), GEN_INT (4)));
2630 addr1 = XEXP (addr1, 1);
2633 emit_move_insn (op2, GEN_INT (4));
2635 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2637 if (BYTES_BIG_ENDIAN)
2639 word_high = change_address (dest, SImode, addr1);
2640 word_low = change_address (dest, SImode, addr2);
2644 word_high = change_address (dest, SImode, addr2);
2645 word_low = change_address (dest, SImode, addr1);
2648 emit_insn (gen_bswapsi2 (word_high, src_low));
2649 emit_insn (gen_bswapsi2 (word_low, src_high));
2653 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2654 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2655 (clobber (match_operand:SI 2 "" ""))]
2656 "TARGET_32BIT && reload_completed"
2660 rtx dest = operands[0];
2661 rtx src = operands[1];
2662 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2663 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2664 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2665 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2667 emit_insn (gen_bswapsi2 (dest_high, src_low));
2668 emit_insn (gen_bswapsi2 (dest_low, src_high));
2671 (define_expand "mulsi3"
2672 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2673 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2674 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2679 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2681 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2685 (define_insn "mulsi3_mq"
2686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2687 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2688 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2689 (clobber (match_scratch:SI 3 "=q,q"))]
2692 {muls|mullw} %0,%1,%2
2693 {muli|mulli} %0,%1,%2"
2695 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2696 (const_string "imul3")
2697 (match_operand:SI 2 "short_cint_operand" "")
2698 (const_string "imul2")]
2699 (const_string "imul")))])
2701 (define_insn "mulsi3_no_mq"
2702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2703 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2704 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2707 {muls|mullw} %0,%1,%2
2708 {muli|mulli} %0,%1,%2"
2710 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2711 (const_string "imul3")
2712 (match_operand:SI 2 "short_cint_operand" "")
2713 (const_string "imul2")]
2714 (const_string "imul")))])
2716 (define_insn "*mulsi3_mq_internal1"
2717 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2718 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2719 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2721 (clobber (match_scratch:SI 3 "=r,r"))
2722 (clobber (match_scratch:SI 4 "=q,q"))]
2725 {muls.|mullw.} %3,%1,%2
2727 [(set_attr "type" "imul_compare")
2728 (set_attr "length" "4,8")])
2731 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2732 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2733 (match_operand:SI 2 "gpc_reg_operand" ""))
2735 (clobber (match_scratch:SI 3 ""))
2736 (clobber (match_scratch:SI 4 ""))]
2737 "TARGET_POWER && reload_completed"
2738 [(parallel [(set (match_dup 3)
2739 (mult:SI (match_dup 1) (match_dup 2)))
2740 (clobber (match_dup 4))])
2742 (compare:CC (match_dup 3)
2746 (define_insn "*mulsi3_no_mq_internal1"
2747 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2748 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2749 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2751 (clobber (match_scratch:SI 3 "=r,r"))]
2754 {muls.|mullw.} %3,%1,%2
2756 [(set_attr "type" "imul_compare")
2757 (set_attr "length" "4,8")])
2760 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2761 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2762 (match_operand:SI 2 "gpc_reg_operand" ""))
2764 (clobber (match_scratch:SI 3 ""))]
2765 "! TARGET_POWER && reload_completed"
2767 (mult:SI (match_dup 1) (match_dup 2)))
2769 (compare:CC (match_dup 3)
2773 (define_insn "*mulsi3_mq_internal2"
2774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2775 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2776 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2778 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2779 (mult:SI (match_dup 1) (match_dup 2)))
2780 (clobber (match_scratch:SI 4 "=q,q"))]
2783 {muls.|mullw.} %0,%1,%2
2785 [(set_attr "type" "imul_compare")
2786 (set_attr "length" "4,8")])
2789 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2791 (match_operand:SI 2 "gpc_reg_operand" ""))
2793 (set (match_operand:SI 0 "gpc_reg_operand" "")
2794 (mult:SI (match_dup 1) (match_dup 2)))
2795 (clobber (match_scratch:SI 4 ""))]
2796 "TARGET_POWER && reload_completed"
2797 [(parallel [(set (match_dup 0)
2798 (mult:SI (match_dup 1) (match_dup 2)))
2799 (clobber (match_dup 4))])
2801 (compare:CC (match_dup 0)
2805 (define_insn "*mulsi3_no_mq_internal2"
2806 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2807 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2808 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2811 (mult:SI (match_dup 1) (match_dup 2)))]
2814 {muls.|mullw.} %0,%1,%2
2816 [(set_attr "type" "imul_compare")
2817 (set_attr "length" "4,8")])
2820 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2821 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2822 (match_operand:SI 2 "gpc_reg_operand" ""))
2824 (set (match_operand:SI 0 "gpc_reg_operand" "")
2825 (mult:SI (match_dup 1) (match_dup 2)))]
2826 "! TARGET_POWER && reload_completed"
2828 (mult:SI (match_dup 1) (match_dup 2)))
2830 (compare:CC (match_dup 0)
2834 ;; Operand 1 is divided by operand 2; quotient goes to operand
2835 ;; 0 and remainder to operand 3.
2836 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2838 (define_expand "divmodsi4"
2839 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2840 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2841 (match_operand:SI 2 "gpc_reg_operand" "")))
2842 (set (match_operand:SI 3 "register_operand" "")
2843 (mod:SI (match_dup 1) (match_dup 2)))])]
2844 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2847 if (! TARGET_POWER && ! TARGET_POWERPC)
2849 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2850 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2851 emit_insn (gen_divss_call ());
2852 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2853 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2858 (define_insn "*divmodsi4_internal"
2859 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2860 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2861 (match_operand:SI 2 "gpc_reg_operand" "r")))
2862 (set (match_operand:SI 3 "register_operand" "=q")
2863 (mod:SI (match_dup 1) (match_dup 2)))]
2866 [(set_attr "type" "idiv")])
2868 (define_expand "udiv<mode>3"
2869 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2870 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2871 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2872 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2875 if (! TARGET_POWER && ! TARGET_POWERPC)
2877 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2878 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2879 emit_insn (gen_quous_call ());
2880 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2883 else if (TARGET_POWER)
2885 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2890 (define_insn "udivsi3_mq"
2891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2892 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2893 (match_operand:SI 2 "gpc_reg_operand" "r")))
2894 (clobber (match_scratch:SI 3 "=q"))]
2895 "TARGET_POWERPC && TARGET_POWER"
2897 [(set_attr "type" "idiv")])
2899 (define_insn "*udivsi3_no_mq"
2900 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2901 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2902 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2903 "TARGET_POWERPC && ! TARGET_POWER"
2906 (cond [(match_operand:SI 0 "" "")
2907 (const_string "idiv")]
2908 (const_string "ldiv")))])
2911 ;; For powers of two we can do srai/aze for divide and then adjust for
2912 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2913 ;; used; for PowerPC, force operands into register and do a normal divide;
2914 ;; for AIX common-mode, use quoss call on register operands.
2915 (define_expand "div<mode>3"
2916 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2917 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2918 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2922 if (GET_CODE (operands[2]) == CONST_INT
2923 && INTVAL (operands[2]) > 0
2924 && exact_log2 (INTVAL (operands[2])) >= 0)
2926 else if (TARGET_POWERPC)
2928 operands[2] = force_reg (<MODE>mode, operands[2]);
2931 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2935 else if (TARGET_POWER)
2939 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2940 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2941 emit_insn (gen_quoss_call ());
2942 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2947 (define_insn "divsi3_mq"
2948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2949 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2950 (match_operand:SI 2 "gpc_reg_operand" "r")))
2951 (clobber (match_scratch:SI 3 "=q"))]
2952 "TARGET_POWERPC && TARGET_POWER"
2954 [(set_attr "type" "idiv")])
2956 (define_insn "*div<mode>3_no_mq"
2957 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2958 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2959 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2960 "TARGET_POWERPC && ! TARGET_POWER"
2963 (cond [(match_operand:SI 0 "" "")
2964 (const_string "idiv")]
2965 (const_string "ldiv")))])
2967 (define_expand "mod<mode>3"
2968 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2969 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2970 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2978 if (GET_CODE (operands[2]) != CONST_INT
2979 || INTVAL (operands[2]) <= 0
2980 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2983 temp1 = gen_reg_rtx (<MODE>mode);
2984 temp2 = gen_reg_rtx (<MODE>mode);
2986 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2987 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2988 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2993 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2994 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2995 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2997 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2998 [(set_attr "type" "two")
2999 (set_attr "length" "8")])
3002 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3003 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3004 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3006 (clobber (match_scratch:P 3 "=r,r"))]
3009 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3011 [(set_attr "type" "compare")
3012 (set_attr "length" "8,12")
3013 (set_attr "cell_micro" "not")])
3016 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3017 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3018 (match_operand:GPR 2 "exact_log2_cint_operand"
3021 (clobber (match_scratch:GPR 3 ""))]
3024 (div:<MODE> (match_dup 1) (match_dup 2)))
3026 (compare:CC (match_dup 3)
3031 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3032 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3033 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3035 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3036 (div:P (match_dup 1) (match_dup 2)))]
3039 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3041 [(set_attr "type" "compare")
3042 (set_attr "length" "8,12")
3043 (set_attr "cell_micro" "not")])
3046 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3047 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3048 (match_operand:GPR 2 "exact_log2_cint_operand"
3051 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3052 (div:GPR (match_dup 1) (match_dup 2)))]
3055 (div:<MODE> (match_dup 1) (match_dup 2)))
3057 (compare:CC (match_dup 0)
3062 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3065 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3067 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3068 (match_operand:SI 3 "gpc_reg_operand" "r")))
3069 (set (match_operand:SI 2 "register_operand" "=*q")
3072 (zero_extend:DI (match_dup 1)) (const_int 32))
3073 (zero_extend:DI (match_dup 4)))
3077 [(set_attr "type" "idiv")])
3079 ;; To do unsigned divide we handle the cases of the divisor looking like a
3080 ;; negative number. If it is a constant that is less than 2**31, we don't
3081 ;; have to worry about the branches. So make a few subroutines here.
3083 ;; First comes the normal case.
3084 (define_expand "udivmodsi4_normal"
3085 [(set (match_dup 4) (const_int 0))
3086 (parallel [(set (match_operand:SI 0 "" "")
3087 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3089 (zero_extend:DI (match_operand:SI 1 "" "")))
3090 (match_operand:SI 2 "" "")))
3091 (set (match_operand:SI 3 "" "")
3092 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3094 (zero_extend:DI (match_dup 1)))
3098 { operands[4] = gen_reg_rtx (SImode); }")
3100 ;; This handles the branches.
3101 (define_expand "udivmodsi4_tests"
3102 [(set (match_operand:SI 0 "" "") (const_int 0))
3103 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3104 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3105 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3106 (label_ref (match_operand:SI 4 "" "")) (pc)))
3107 (set (match_dup 0) (const_int 1))
3108 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3109 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3110 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3111 (label_ref (match_dup 4)) (pc)))]
3114 { operands[5] = gen_reg_rtx (CCUNSmode);
3115 operands[6] = gen_reg_rtx (CCmode);
3118 (define_expand "udivmodsi4"
3119 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3120 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3121 (match_operand:SI 2 "reg_or_cint_operand" "")))
3122 (set (match_operand:SI 3 "gpc_reg_operand" "")
3123 (umod:SI (match_dup 1) (match_dup 2)))])]
3131 if (! TARGET_POWERPC)
3133 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3134 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3135 emit_insn (gen_divus_call ());
3136 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3137 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3144 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3146 operands[2] = force_reg (SImode, operands[2]);
3147 label = gen_label_rtx ();
3148 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3149 operands[3], label));
3152 operands[2] = force_reg (SImode, operands[2]);
3154 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3162 ;; AIX architecture-independent common-mode multiply (DImode),
3163 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3164 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3165 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3166 ;; assumed unused if generating common-mode, so ignore.
3167 (define_insn "mulh_call"
3170 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3171 (sign_extend:DI (reg:SI 4)))
3173 (clobber (reg:SI LR_REGNO))]
3174 "! TARGET_POWER && ! TARGET_POWERPC"
3176 [(set_attr "type" "imul")])
3178 (define_insn "mull_call"
3180 (mult:DI (sign_extend:DI (reg:SI 3))
3181 (sign_extend:DI (reg:SI 4))))
3182 (clobber (reg:SI LR_REGNO))
3183 (clobber (reg:SI 0))]
3184 "! TARGET_POWER && ! TARGET_POWERPC"
3186 [(set_attr "type" "imul")])
3188 (define_insn "divss_call"
3190 (div:SI (reg:SI 3) (reg:SI 4)))
3192 (mod:SI (reg:SI 3) (reg:SI 4)))
3193 (clobber (reg:SI LR_REGNO))
3194 (clobber (reg:SI 0))]
3195 "! TARGET_POWER && ! TARGET_POWERPC"
3197 [(set_attr "type" "idiv")])
3199 (define_insn "divus_call"
3201 (udiv:SI (reg:SI 3) (reg:SI 4)))
3203 (umod:SI (reg:SI 3) (reg:SI 4)))
3204 (clobber (reg:SI LR_REGNO))
3205 (clobber (reg:SI 0))
3206 (clobber (match_scratch:CC 0 "=x"))
3207 (clobber (reg:CC CR1_REGNO))]
3208 "! TARGET_POWER && ! TARGET_POWERPC"
3210 [(set_attr "type" "idiv")])
3212 (define_insn "quoss_call"
3214 (div:SI (reg:SI 3) (reg:SI 4)))
3215 (clobber (reg:SI LR_REGNO))]
3216 "! TARGET_POWER && ! TARGET_POWERPC"
3218 [(set_attr "type" "idiv")])
3220 (define_insn "quous_call"
3222 (udiv:SI (reg:SI 3) (reg:SI 4)))
3223 (clobber (reg:SI LR_REGNO))
3224 (clobber (reg:SI 0))
3225 (clobber (match_scratch:CC 0 "=x"))
3226 (clobber (reg:CC CR1_REGNO))]
3227 "! TARGET_POWER && ! TARGET_POWERPC"
3229 [(set_attr "type" "idiv")])
3231 ;; Logical instructions
3232 ;; The logical instructions are mostly combined by using match_operator,
3233 ;; but the plain AND insns are somewhat different because there is no
3234 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3235 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3237 (define_expand "andsi3"
3239 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3240 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3241 (match_operand:SI 2 "and_operand" "")))
3242 (clobber (match_scratch:CC 3 ""))])]
3246 (define_insn "andsi3_mc"
3247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3248 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3249 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3250 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3251 "rs6000_gen_cell_microcode"
3254 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3255 {andil.|andi.} %0,%1,%b2
3256 {andiu.|andis.} %0,%1,%u2"
3257 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3259 (define_insn "andsi3_nomc"
3260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3261 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3262 (match_operand:SI 2 "and_operand" "?r,T")))
3263 (clobber (match_scratch:CC 3 "=X,X"))]
3264 "!rs6000_gen_cell_microcode"
3267 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3269 (define_insn "andsi3_internal0_nomc"
3270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3271 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3272 (match_operand:SI 2 "and_operand" "?r,T")))]
3273 "!rs6000_gen_cell_microcode"
3276 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3279 ;; Note to set cr's other than cr0 we do the and immediate and then
3280 ;; the test again -- this avoids a mfcr which on the higher end
3281 ;; machines causes an execution serialization
3283 (define_insn "*andsi3_internal2_mc"
3284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3285 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3286 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3288 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3289 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3290 "TARGET_32BIT && rs6000_gen_cell_microcode"
3293 {andil.|andi.} %3,%1,%b2
3294 {andiu.|andis.} %3,%1,%u2
3295 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3300 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3301 compare,compare,compare,compare")
3302 (set_attr "length" "4,4,4,4,8,8,8,8")])
3304 (define_insn "*andsi3_internal3_mc"
3305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3306 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3307 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3309 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3310 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3311 "TARGET_64BIT && rs6000_gen_cell_microcode"
3314 {andil.|andi.} %3,%1,%b2
3315 {andiu.|andis.} %3,%1,%u2
3316 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3321 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3322 compare,compare,compare")
3323 (set_attr "length" "8,4,4,4,8,8,8,8")])
3326 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3327 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3328 (match_operand:GPR 2 "and_operand" ""))
3330 (clobber (match_scratch:GPR 3 ""))
3331 (clobber (match_scratch:CC 4 ""))]
3333 [(parallel [(set (match_dup 3)
3334 (and:<MODE> (match_dup 1)
3336 (clobber (match_dup 4))])
3338 (compare:CC (match_dup 3)
3342 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3343 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3346 [(set (match_operand:CC 0 "cc_reg_operand" "")
3347 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3348 (match_operand:SI 2 "gpc_reg_operand" ""))
3350 (clobber (match_scratch:SI 3 ""))
3351 (clobber (match_scratch:CC 4 ""))]
3352 "TARGET_POWERPC64 && reload_completed"
3353 [(parallel [(set (match_dup 3)
3354 (and:SI (match_dup 1)
3356 (clobber (match_dup 4))])
3358 (compare:CC (match_dup 3)
3362 (define_insn "*andsi3_internal4"
3363 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3364 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3365 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3367 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3368 (and:SI (match_dup 1)
3370 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3371 "TARGET_32BIT && rs6000_gen_cell_microcode"
3374 {andil.|andi.} %0,%1,%b2
3375 {andiu.|andis.} %0,%1,%u2
3376 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3381 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3382 compare,compare,compare,compare")
3383 (set_attr "length" "4,4,4,4,8,8,8,8")])
3385 (define_insn "*andsi3_internal5_mc"
3386 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3387 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3388 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3390 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3391 (and:SI (match_dup 1)
3393 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3394 "TARGET_64BIT && rs6000_gen_cell_microcode"
3397 {andil.|andi.} %0,%1,%b2
3398 {andiu.|andis.} %0,%1,%u2
3399 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3404 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3405 compare,compare,compare")
3406 (set_attr "length" "8,4,4,4,8,8,8,8")])
3409 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3410 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3411 (match_operand:SI 2 "and_operand" ""))
3413 (set (match_operand:SI 0 "gpc_reg_operand" "")
3414 (and:SI (match_dup 1)
3416 (clobber (match_scratch:CC 4 ""))]
3418 [(parallel [(set (match_dup 0)
3419 (and:SI (match_dup 1)
3421 (clobber (match_dup 4))])
3423 (compare:CC (match_dup 0)
3428 [(set (match_operand:CC 3 "cc_reg_operand" "")
3429 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3430 (match_operand:SI 2 "gpc_reg_operand" ""))
3432 (set (match_operand:SI 0 "gpc_reg_operand" "")
3433 (and:SI (match_dup 1)
3435 (clobber (match_scratch:CC 4 ""))]
3436 "TARGET_POWERPC64 && reload_completed"
3437 [(parallel [(set (match_dup 0)
3438 (and:SI (match_dup 1)
3440 (clobber (match_dup 4))])
3442 (compare:CC (match_dup 0)
3446 ;; Handle the PowerPC64 rlwinm corner case
3448 (define_insn_and_split "*andsi3_internal6"
3449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3450 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3451 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3456 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3459 (rotate:SI (match_dup 0) (match_dup 5)))]
3462 int mb = extract_MB (operands[2]);
3463 int me = extract_ME (operands[2]);
3464 operands[3] = GEN_INT (me + 1);
3465 operands[5] = GEN_INT (32 - (me + 1));
3466 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3468 [(set_attr "length" "8")])
3470 (define_expand "iorsi3"
3471 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3472 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3473 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3477 if (GET_CODE (operands[2]) == CONST_INT
3478 && ! logical_operand (operands[2], SImode))
3480 HOST_WIDE_INT value = INTVAL (operands[2]);
3481 rtx tmp = ((!can_create_pseudo_p ()
3482 || rtx_equal_p (operands[0], operands[1]))
3483 ? operands[0] : gen_reg_rtx (SImode));
3485 emit_insn (gen_iorsi3 (tmp, operands[1],
3486 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3487 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3492 (define_expand "xorsi3"
3493 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3494 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3495 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3499 if (GET_CODE (operands[2]) == CONST_INT
3500 && ! logical_operand (operands[2], SImode))
3502 HOST_WIDE_INT value = INTVAL (operands[2]);
3503 rtx tmp = ((!can_create_pseudo_p ()
3504 || rtx_equal_p (operands[0], operands[1]))
3505 ? operands[0] : gen_reg_rtx (SImode));
3507 emit_insn (gen_xorsi3 (tmp, operands[1],
3508 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3509 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3514 (define_insn "*boolsi3_internal1"
3515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3516 (match_operator:SI 3 "boolean_or_operator"
3517 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3518 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3522 {%q3il|%q3i} %0,%1,%b2
3523 {%q3iu|%q3is} %0,%1,%u2")
3525 (define_insn "*boolsi3_internal2"
3526 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3527 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3528 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3529 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3531 (clobber (match_scratch:SI 3 "=r,r"))]
3536 [(set_attr "type" "fast_compare,compare")
3537 (set_attr "length" "4,8")])
3540 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3541 (compare:CC (match_operator:SI 4 "boolean_operator"
3542 [(match_operand:SI 1 "gpc_reg_operand" "")
3543 (match_operand:SI 2 "gpc_reg_operand" "")])
3545 (clobber (match_scratch:SI 3 ""))]
3546 "TARGET_32BIT && reload_completed"
3547 [(set (match_dup 3) (match_dup 4))
3549 (compare:CC (match_dup 3)
3553 (define_insn "*boolsi3_internal3"
3554 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3555 (compare:CC (match_operator:SI 4 "boolean_operator"
3556 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3557 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3559 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3565 [(set_attr "type" "fast_compare,compare")
3566 (set_attr "length" "4,8")])
3569 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3570 (compare:CC (match_operator:SI 4 "boolean_operator"
3571 [(match_operand:SI 1 "gpc_reg_operand" "")
3572 (match_operand:SI 2 "gpc_reg_operand" "")])
3574 (set (match_operand:SI 0 "gpc_reg_operand" "")
3576 "TARGET_32BIT && reload_completed"
3577 [(set (match_dup 0) (match_dup 4))
3579 (compare:CC (match_dup 0)
3583 ;; Split a logical operation that we can't do in one insn into two insns,
3584 ;; each of which does one 16-bit part. This is used by combine.
3587 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3588 (match_operator:SI 3 "boolean_or_operator"
3589 [(match_operand:SI 1 "gpc_reg_operand" "")
3590 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3592 [(set (match_dup 0) (match_dup 4))
3593 (set (match_dup 0) (match_dup 5))]
3597 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3598 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3600 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3601 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3605 (define_insn "*boolcsi3_internal1"
3606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3607 (match_operator:SI 3 "boolean_operator"
3608 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3609 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3613 (define_insn "*boolcsi3_internal2"
3614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3615 (compare:CC (match_operator:SI 4 "boolean_operator"
3616 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3617 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3619 (clobber (match_scratch:SI 3 "=r,r"))]
3624 [(set_attr "type" "compare")
3625 (set_attr "length" "4,8")])
3628 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3629 (compare:CC (match_operator:SI 4 "boolean_operator"
3630 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3631 (match_operand:SI 2 "gpc_reg_operand" "")])
3633 (clobber (match_scratch:SI 3 ""))]
3634 "TARGET_32BIT && reload_completed"
3635 [(set (match_dup 3) (match_dup 4))
3637 (compare:CC (match_dup 3)
3641 (define_insn "*boolcsi3_internal3"
3642 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3643 (compare:CC (match_operator:SI 4 "boolean_operator"
3644 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3645 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3647 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3653 [(set_attr "type" "compare")
3654 (set_attr "length" "4,8")])
3657 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3658 (compare:CC (match_operator:SI 4 "boolean_operator"
3659 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3660 (match_operand:SI 2 "gpc_reg_operand" "")])
3662 (set (match_operand:SI 0 "gpc_reg_operand" "")
3664 "TARGET_32BIT && reload_completed"
3665 [(set (match_dup 0) (match_dup 4))
3667 (compare:CC (match_dup 0)
3671 (define_insn "*boolccsi3_internal1"
3672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3673 (match_operator:SI 3 "boolean_operator"
3674 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3675 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3679 (define_insn "*boolccsi3_internal2"
3680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3681 (compare:CC (match_operator:SI 4 "boolean_operator"
3682 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3683 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3685 (clobber (match_scratch:SI 3 "=r,r"))]
3690 [(set_attr "type" "fast_compare,compare")
3691 (set_attr "length" "4,8")])
3694 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3695 (compare:CC (match_operator:SI 4 "boolean_operator"
3696 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3697 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3699 (clobber (match_scratch:SI 3 ""))]
3700 "TARGET_32BIT && reload_completed"
3701 [(set (match_dup 3) (match_dup 4))
3703 (compare:CC (match_dup 3)
3707 (define_insn "*boolccsi3_internal3"
3708 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3709 (compare:CC (match_operator:SI 4 "boolean_operator"
3710 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3711 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3713 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3719 [(set_attr "type" "fast_compare,compare")
3720 (set_attr "length" "4,8")])
3723 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3724 (compare:CC (match_operator:SI 4 "boolean_operator"
3725 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3726 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3728 (set (match_operand:SI 0 "gpc_reg_operand" "")
3730 "TARGET_32BIT && reload_completed"
3731 [(set (match_dup 0) (match_dup 4))
3733 (compare:CC (match_dup 0)
3737 ;; maskir insn. We need four forms because things might be in arbitrary
3738 ;; orders. Don't define forms that only set CR fields because these
3739 ;; would modify an input register.
3741 (define_insn "*maskir_internal1"
3742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3743 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3744 (match_operand:SI 1 "gpc_reg_operand" "0"))
3745 (and:SI (match_dup 2)
3746 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3750 (define_insn "*maskir_internal2"
3751 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3752 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3753 (match_operand:SI 1 "gpc_reg_operand" "0"))
3754 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3759 (define_insn "*maskir_internal3"
3760 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3761 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3762 (match_operand:SI 3 "gpc_reg_operand" "r"))
3763 (and:SI (not:SI (match_dup 2))
3764 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3768 (define_insn "*maskir_internal4"
3769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3770 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3771 (match_operand:SI 2 "gpc_reg_operand" "r"))
3772 (and:SI (not:SI (match_dup 2))
3773 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3777 (define_insn "*maskir_internal5"
3778 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3780 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3781 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3782 (and:SI (match_dup 2)
3783 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3785 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3786 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3787 (and:SI (match_dup 2) (match_dup 3))))]
3792 [(set_attr "type" "compare")
3793 (set_attr "length" "4,8")])
3796 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3798 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3799 (match_operand:SI 1 "gpc_reg_operand" ""))
3800 (and:SI (match_dup 2)
3801 (match_operand:SI 3 "gpc_reg_operand" "")))
3803 (set (match_operand:SI 0 "gpc_reg_operand" "")
3804 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3805 (and:SI (match_dup 2) (match_dup 3))))]
3806 "TARGET_POWER && reload_completed"
3808 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3809 (and:SI (match_dup 2) (match_dup 3))))
3811 (compare:CC (match_dup 0)
3815 (define_insn "*maskir_internal6"
3816 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3818 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3819 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3820 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3823 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3824 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3825 (and:SI (match_dup 3) (match_dup 2))))]
3830 [(set_attr "type" "compare")
3831 (set_attr "length" "4,8")])
3834 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3836 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3837 (match_operand:SI 1 "gpc_reg_operand" ""))
3838 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3841 (set (match_operand:SI 0 "gpc_reg_operand" "")
3842 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3843 (and:SI (match_dup 3) (match_dup 2))))]
3844 "TARGET_POWER && reload_completed"
3846 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3847 (and:SI (match_dup 3) (match_dup 2))))
3849 (compare:CC (match_dup 0)
3853 (define_insn "*maskir_internal7"
3854 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3856 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3857 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3858 (and:SI (not:SI (match_dup 2))
3859 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3861 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3862 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3863 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3868 [(set_attr "type" "compare")
3869 (set_attr "length" "4,8")])
3872 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3874 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3875 (match_operand:SI 3 "gpc_reg_operand" ""))
3876 (and:SI (not:SI (match_dup 2))
3877 (match_operand:SI 1 "gpc_reg_operand" "")))
3879 (set (match_operand:SI 0 "gpc_reg_operand" "")
3880 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3881 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3882 "TARGET_POWER && reload_completed"
3884 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3885 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3887 (compare:CC (match_dup 0)
3891 (define_insn "*maskir_internal8"
3892 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3894 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3895 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3896 (and:SI (not:SI (match_dup 2))
3897 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3899 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3900 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3901 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3906 [(set_attr "type" "compare")
3907 (set_attr "length" "4,8")])
3910 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3912 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3913 (match_operand:SI 2 "gpc_reg_operand" ""))
3914 (and:SI (not:SI (match_dup 2))
3915 (match_operand:SI 1 "gpc_reg_operand" "")))
3917 (set (match_operand:SI 0 "gpc_reg_operand" "")
3918 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3919 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3920 "TARGET_POWER && reload_completed"
3922 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3923 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3925 (compare:CC (match_dup 0)
3929 ;; Rotate and shift insns, in all their variants. These support shifts,
3930 ;; field inserts and extracts, and various combinations thereof.
3931 (define_expand "insv"
3932 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3933 (match_operand:SI 1 "const_int_operand" "")
3934 (match_operand:SI 2 "const_int_operand" ""))
3935 (match_operand 3 "gpc_reg_operand" ""))]
3939 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3940 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3941 compiler if the address of the structure is taken later. Likewise, do
3942 not handle invalid E500 subregs. */
3943 if (GET_CODE (operands[0]) == SUBREG
3944 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3945 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3946 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3949 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3950 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3952 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3956 (define_insn "insvsi"
3957 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3958 (match_operand:SI 1 "const_int_operand" "i")
3959 (match_operand:SI 2 "const_int_operand" "i"))
3960 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3964 int start = INTVAL (operands[2]) & 31;
3965 int size = INTVAL (operands[1]) & 31;
3967 operands[4] = GEN_INT (32 - start - size);
3968 operands[1] = GEN_INT (start + size - 1);
3969 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3971 [(set_attr "type" "insert_word")])
3973 (define_insn "*insvsi_internal1"
3974 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3975 (match_operand:SI 1 "const_int_operand" "i")
3976 (match_operand:SI 2 "const_int_operand" "i"))
3977 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3978 (match_operand:SI 4 "const_int_operand" "i")))]
3979 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3982 int shift = INTVAL (operands[4]) & 31;
3983 int start = INTVAL (operands[2]) & 31;
3984 int size = INTVAL (operands[1]) & 31;
3986 operands[4] = GEN_INT (shift - start - size);
3987 operands[1] = GEN_INT (start + size - 1);
3988 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3990 [(set_attr "type" "insert_word")])
3992 (define_insn "*insvsi_internal2"
3993 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3994 (match_operand:SI 1 "const_int_operand" "i")
3995 (match_operand:SI 2 "const_int_operand" "i"))
3996 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3997 (match_operand:SI 4 "const_int_operand" "i")))]
3998 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4001 int shift = INTVAL (operands[4]) & 31;
4002 int start = INTVAL (operands[2]) & 31;
4003 int size = INTVAL (operands[1]) & 31;
4005 operands[4] = GEN_INT (32 - shift - start - size);
4006 operands[1] = GEN_INT (start + size - 1);
4007 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4009 [(set_attr "type" "insert_word")])
4011 (define_insn "*insvsi_internal3"
4012 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4013 (match_operand:SI 1 "const_int_operand" "i")
4014 (match_operand:SI 2 "const_int_operand" "i"))
4015 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4016 (match_operand:SI 4 "const_int_operand" "i")))]
4017 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4020 int shift = INTVAL (operands[4]) & 31;
4021 int start = INTVAL (operands[2]) & 31;
4022 int size = INTVAL (operands[1]) & 31;
4024 operands[4] = GEN_INT (32 - shift - start - size);
4025 operands[1] = GEN_INT (start + size - 1);
4026 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4028 [(set_attr "type" "insert_word")])
4030 (define_insn "*insvsi_internal4"
4031 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4032 (match_operand:SI 1 "const_int_operand" "i")
4033 (match_operand:SI 2 "const_int_operand" "i"))
4034 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4035 (match_operand:SI 4 "const_int_operand" "i")
4036 (match_operand:SI 5 "const_int_operand" "i")))]
4037 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4040 int extract_start = INTVAL (operands[5]) & 31;
4041 int extract_size = INTVAL (operands[4]) & 31;
4042 int insert_start = INTVAL (operands[2]) & 31;
4043 int insert_size = INTVAL (operands[1]) & 31;
4045 /* Align extract field with insert field */
4046 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4047 operands[1] = GEN_INT (insert_start + insert_size - 1);
4048 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4050 [(set_attr "type" "insert_word")])
4052 ;; combine patterns for rlwimi
4053 (define_insn "*insvsi_internal5"
4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4055 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4056 (match_operand:SI 1 "mask_operand" "i"))
4057 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4058 (match_operand:SI 2 "const_int_operand" "i"))
4059 (match_operand:SI 5 "mask_operand" "i"))))]
4060 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4063 int me = extract_ME(operands[5]);
4064 int mb = extract_MB(operands[5]);
4065 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4066 operands[2] = GEN_INT(mb);
4067 operands[1] = GEN_INT(me);
4068 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4070 [(set_attr "type" "insert_word")])
4072 (define_insn "*insvsi_internal6"
4073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4074 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4075 (match_operand:SI 2 "const_int_operand" "i"))
4076 (match_operand:SI 5 "mask_operand" "i"))
4077 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4078 (match_operand:SI 1 "mask_operand" "i"))))]
4079 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4082 int me = extract_ME(operands[5]);
4083 int mb = extract_MB(operands[5]);
4084 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4085 operands[2] = GEN_INT(mb);
4086 operands[1] = GEN_INT(me);
4087 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4089 [(set_attr "type" "insert_word")])
4091 (define_insn "insvdi"
4092 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4093 (match_operand:SI 1 "const_int_operand" "i")
4094 (match_operand:SI 2 "const_int_operand" "i"))
4095 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4099 int start = INTVAL (operands[2]) & 63;
4100 int size = INTVAL (operands[1]) & 63;
4102 operands[1] = GEN_INT (64 - start - size);
4103 return \"rldimi %0,%3,%H1,%H2\";
4105 [(set_attr "type" "insert_dword")])
4107 (define_insn "*insvdi_internal2"
4108 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4109 (match_operand:SI 1 "const_int_operand" "i")
4110 (match_operand:SI 2 "const_int_operand" "i"))
4111 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4112 (match_operand:SI 4 "const_int_operand" "i")))]
4114 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4117 int shift = INTVAL (operands[4]) & 63;
4118 int start = (INTVAL (operands[2]) & 63) - 32;
4119 int size = INTVAL (operands[1]) & 63;
4121 operands[4] = GEN_INT (64 - shift - start - size);
4122 operands[2] = GEN_INT (start);
4123 operands[1] = GEN_INT (start + size - 1);
4124 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4127 (define_insn "*insvdi_internal3"
4128 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4129 (match_operand:SI 1 "const_int_operand" "i")
4130 (match_operand:SI 2 "const_int_operand" "i"))
4131 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4132 (match_operand:SI 4 "const_int_operand" "i")))]
4134 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4137 int shift = INTVAL (operands[4]) & 63;
4138 int start = (INTVAL (operands[2]) & 63) - 32;
4139 int size = INTVAL (operands[1]) & 63;
4141 operands[4] = GEN_INT (64 - shift - start - size);
4142 operands[2] = GEN_INT (start);
4143 operands[1] = GEN_INT (start + size - 1);
4144 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4147 (define_expand "extzv"
4148 [(set (match_operand 0 "gpc_reg_operand" "")
4149 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4150 (match_operand:SI 2 "const_int_operand" "")
4151 (match_operand:SI 3 "const_int_operand" "")))]
4155 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4156 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4157 compiler if the address of the structure is taken later. */
4158 if (GET_CODE (operands[0]) == SUBREG
4159 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4162 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4163 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4165 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4169 (define_insn "extzvsi"
4170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4171 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4172 (match_operand:SI 2 "const_int_operand" "i")
4173 (match_operand:SI 3 "const_int_operand" "i")))]
4177 int start = INTVAL (operands[3]) & 31;
4178 int size = INTVAL (operands[2]) & 31;
4180 if (start + size >= 32)
4181 operands[3] = const0_rtx;
4183 operands[3] = GEN_INT (start + size);
4184 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4187 (define_insn "*extzvsi_internal1"
4188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4189 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4190 (match_operand:SI 2 "const_int_operand" "i,i")
4191 (match_operand:SI 3 "const_int_operand" "i,i"))
4193 (clobber (match_scratch:SI 4 "=r,r"))]
4197 int start = INTVAL (operands[3]) & 31;
4198 int size = INTVAL (operands[2]) & 31;
4200 /* Force split for non-cc0 compare. */
4201 if (which_alternative == 1)
4204 /* If the bit-field being tested fits in the upper or lower half of a
4205 word, it is possible to use andiu. or andil. to test it. This is
4206 useful because the condition register set-use delay is smaller for
4207 andi[ul]. than for rlinm. This doesn't work when the starting bit
4208 position is 0 because the LT and GT bits may be set wrong. */
4210 if ((start > 0 && start + size <= 16) || start >= 16)
4212 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4213 - (1 << (16 - (start & 15) - size))));
4215 return \"{andiu.|andis.} %4,%1,%3\";
4217 return \"{andil.|andi.} %4,%1,%3\";
4220 if (start + size >= 32)
4221 operands[3] = const0_rtx;
4223 operands[3] = GEN_INT (start + size);
4224 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4226 [(set_attr "type" "delayed_compare")
4227 (set_attr "length" "4,8")])
4230 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4231 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4232 (match_operand:SI 2 "const_int_operand" "")
4233 (match_operand:SI 3 "const_int_operand" ""))
4235 (clobber (match_scratch:SI 4 ""))]
4238 (zero_extract:SI (match_dup 1) (match_dup 2)
4241 (compare:CC (match_dup 4)
4245 (define_insn "*extzvsi_internal2"
4246 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4247 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4248 (match_operand:SI 2 "const_int_operand" "i,i")
4249 (match_operand:SI 3 "const_int_operand" "i,i"))
4251 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4252 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4256 int start = INTVAL (operands[3]) & 31;
4257 int size = INTVAL (operands[2]) & 31;
4259 /* Force split for non-cc0 compare. */
4260 if (which_alternative == 1)
4263 /* Since we are using the output value, we can't ignore any need for
4264 a shift. The bit-field must end at the LSB. */
4265 if (start >= 16 && start + size == 32)
4267 operands[3] = GEN_INT ((1 << size) - 1);
4268 return \"{andil.|andi.} %0,%1,%3\";
4271 if (start + size >= 32)
4272 operands[3] = const0_rtx;
4274 operands[3] = GEN_INT (start + size);
4275 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4277 [(set_attr "type" "delayed_compare")
4278 (set_attr "length" "4,8")])
4281 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4282 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4283 (match_operand:SI 2 "const_int_operand" "")
4284 (match_operand:SI 3 "const_int_operand" ""))
4286 (set (match_operand:SI 0 "gpc_reg_operand" "")
4287 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4290 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4292 (compare:CC (match_dup 0)
4296 (define_insn "extzvdi"
4297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4298 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4299 (match_operand:SI 2 "const_int_operand" "i")
4300 (match_operand:SI 3 "const_int_operand" "i")))]
4304 int start = INTVAL (operands[3]) & 63;
4305 int size = INTVAL (operands[2]) & 63;
4307 if (start + size >= 64)
4308 operands[3] = const0_rtx;
4310 operands[3] = GEN_INT (start + size);
4311 operands[2] = GEN_INT (64 - size);
4312 return \"rldicl %0,%1,%3,%2\";
4315 (define_insn "*extzvdi_internal1"
4316 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4317 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4318 (match_operand:SI 2 "const_int_operand" "i")
4319 (match_operand:SI 3 "const_int_operand" "i"))
4321 (clobber (match_scratch:DI 4 "=r"))]
4322 "TARGET_64BIT && rs6000_gen_cell_microcode"
4325 int start = INTVAL (operands[3]) & 63;
4326 int size = INTVAL (operands[2]) & 63;
4328 if (start + size >= 64)
4329 operands[3] = const0_rtx;
4331 operands[3] = GEN_INT (start + size);
4332 operands[2] = GEN_INT (64 - size);
4333 return \"rldicl. %4,%1,%3,%2\";
4335 [(set_attr "type" "compare")])
4337 (define_insn "*extzvdi_internal2"
4338 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4339 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4340 (match_operand:SI 2 "const_int_operand" "i")
4341 (match_operand:SI 3 "const_int_operand" "i"))
4343 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4344 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4345 "TARGET_64BIT && rs6000_gen_cell_microcode"
4348 int start = INTVAL (operands[3]) & 63;
4349 int size = INTVAL (operands[2]) & 63;
4351 if (start + size >= 64)
4352 operands[3] = const0_rtx;
4354 operands[3] = GEN_INT (start + size);
4355 operands[2] = GEN_INT (64 - size);
4356 return \"rldicl. %0,%1,%3,%2\";
4358 [(set_attr "type" "compare")])
4360 (define_insn "rotlsi3"
4361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4362 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4363 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4366 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4367 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4368 [(set_attr "type" "var_shift_rotate,integer")])
4370 (define_insn "*rotlsi3_64"
4371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4373 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4374 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4377 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4378 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4379 [(set_attr "type" "var_shift_rotate,integer")])
4381 (define_insn "*rotlsi3_internal2"
4382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4383 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4384 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4386 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4389 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4390 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4393 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4394 (set_attr "length" "4,4,8,8")])
4397 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4398 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4399 (match_operand:SI 2 "reg_or_cint_operand" ""))
4401 (clobber (match_scratch:SI 3 ""))]
4404 (rotate:SI (match_dup 1) (match_dup 2)))
4406 (compare:CC (match_dup 3)
4410 (define_insn "*rotlsi3_internal3"
4411 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4412 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4413 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4415 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4416 (rotate:SI (match_dup 1) (match_dup 2)))]
4419 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4420 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4423 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4424 (set_attr "length" "4,4,8,8")])
4427 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4428 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4429 (match_operand:SI 2 "reg_or_cint_operand" ""))
4431 (set (match_operand:SI 0 "gpc_reg_operand" "")
4432 (rotate:SI (match_dup 1) (match_dup 2)))]
4435 (rotate:SI (match_dup 1) (match_dup 2)))
4437 (compare:CC (match_dup 0)
4441 (define_insn "*rotlsi3_internal4"
4442 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4443 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4444 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4445 (match_operand:SI 3 "mask_operand" "n,n")))]
4448 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4449 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4450 [(set_attr "type" "var_shift_rotate,integer")])
4452 (define_insn "*rotlsi3_internal5"
4453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4455 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4456 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4457 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4459 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4462 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4463 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4466 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4467 (set_attr "length" "4,4,8,8")])
4470 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4472 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4473 (match_operand:SI 2 "reg_or_cint_operand" ""))
4474 (match_operand:SI 3 "mask_operand" ""))
4476 (clobber (match_scratch:SI 4 ""))]
4479 (and:SI (rotate:SI (match_dup 1)
4483 (compare:CC (match_dup 4)
4487 (define_insn "*rotlsi3_internal6"
4488 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4490 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4491 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4492 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4494 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4495 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4498 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4499 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4502 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4503 (set_attr "length" "4,4,8,8")])
4506 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4508 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4509 (match_operand:SI 2 "reg_or_cint_operand" ""))
4510 (match_operand:SI 3 "mask_operand" ""))
4512 (set (match_operand:SI 0 "gpc_reg_operand" "")
4513 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4516 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4518 (compare:CC (match_dup 0)
4522 (define_insn "*rotlsi3_internal7"
4523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4526 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4527 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4529 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4530 [(set (attr "cell_micro")
4531 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4532 (const_string "not")
4533 (const_string "always")))])
4535 (define_insn "*rotlsi3_internal8"
4536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4537 (compare:CC (zero_extend:SI
4539 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4540 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4542 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4545 {rlnm.|rlwnm.} %3,%1,%2,0xff
4546 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4549 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4550 (set_attr "length" "4,4,8,8")])
4553 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4554 (compare:CC (zero_extend:SI
4556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4557 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4559 (clobber (match_scratch:SI 3 ""))]
4562 (zero_extend:SI (subreg:QI
4563 (rotate:SI (match_dup 1)
4566 (compare:CC (match_dup 3)
4570 (define_insn "*rotlsi3_internal9"
4571 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4572 (compare:CC (zero_extend:SI
4574 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4575 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4577 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4578 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4581 {rlnm.|rlwnm.} %0,%1,%2,0xff
4582 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4585 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4586 (set_attr "length" "4,4,8,8")])
4589 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4590 (compare:CC (zero_extend:SI
4592 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4593 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4595 (set (match_operand:SI 0 "gpc_reg_operand" "")
4596 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4599 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4601 (compare:CC (match_dup 0)
4605 (define_insn "*rotlsi3_internal10"
4606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4609 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4610 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4613 {rlnm|rlwnm} %0,%1,%2,0xffff
4614 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4615 [(set_attr "type" "var_shift_rotate,integer")])
4618 (define_insn "*rotlsi3_internal11"
4619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4620 (compare:CC (zero_extend:SI
4622 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4623 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4625 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4628 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4629 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4632 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4633 (set_attr "length" "4,4,8,8")])
4636 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4637 (compare:CC (zero_extend:SI
4639 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4640 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4642 (clobber (match_scratch:SI 3 ""))]
4645 (zero_extend:SI (subreg:HI
4646 (rotate:SI (match_dup 1)
4649 (compare:CC (match_dup 3)
4653 (define_insn "*rotlsi3_internal12"
4654 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4655 (compare:CC (zero_extend:SI
4657 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4658 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4660 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4661 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4664 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4665 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4668 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4669 (set_attr "length" "4,4,8,8")])
4672 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4673 (compare:CC (zero_extend:SI
4675 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4676 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4678 (set (match_operand:SI 0 "gpc_reg_operand" "")
4679 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4682 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4684 (compare:CC (match_dup 0)
4688 ;; Note that we use "sle." instead of "sl." so that we can set
4689 ;; SHIFT_COUNT_TRUNCATED.
4691 (define_expand "ashlsi3"
4692 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4693 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4694 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4699 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4701 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4705 (define_insn "ashlsi3_power"
4706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4707 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4708 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4709 (clobber (match_scratch:SI 3 "=q,X"))]
4713 {sli|slwi} %0,%1,%h2")
4715 (define_insn "ashlsi3_no_power"
4716 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4717 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4718 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4722 {sli|slwi} %0,%1,%h2"
4723 [(set_attr "type" "var_shift_rotate,shift")])
4725 (define_insn "*ashlsi3_64"
4726 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4728 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4729 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4733 {sli|slwi} %0,%1,%h2"
4734 [(set_attr "type" "var_shift_rotate,shift")])
4737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4738 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4739 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4741 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4742 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4746 {sli.|slwi.} %3,%1,%h2
4749 [(set_attr "type" "delayed_compare")
4750 (set_attr "length" "4,4,8,8")])
4753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4754 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4755 (match_operand:SI 2 "reg_or_cint_operand" ""))
4757 (clobber (match_scratch:SI 3 ""))
4758 (clobber (match_scratch:SI 4 ""))]
4759 "TARGET_POWER && reload_completed"
4760 [(parallel [(set (match_dup 3)
4761 (ashift:SI (match_dup 1) (match_dup 2)))
4762 (clobber (match_dup 4))])
4764 (compare:CC (match_dup 3)
4769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4770 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4771 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4773 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4774 "! TARGET_POWER && TARGET_32BIT"
4777 {sli.|slwi.} %3,%1,%h2
4780 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4781 (set_attr "length" "4,4,8,8")])
4784 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4785 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4786 (match_operand:SI 2 "reg_or_cint_operand" ""))
4788 (clobber (match_scratch:SI 3 ""))]
4789 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4791 (ashift:SI (match_dup 1) (match_dup 2)))
4793 (compare:CC (match_dup 3)
4798 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4799 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4800 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4802 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4803 (ashift:SI (match_dup 1) (match_dup 2)))
4804 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4808 {sli.|slwi.} %0,%1,%h2
4811 [(set_attr "type" "delayed_compare")
4812 (set_attr "length" "4,4,8,8")])
4815 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4816 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4817 (match_operand:SI 2 "reg_or_cint_operand" ""))
4819 (set (match_operand:SI 0 "gpc_reg_operand" "")
4820 (ashift:SI (match_dup 1) (match_dup 2)))
4821 (clobber (match_scratch:SI 4 ""))]
4822 "TARGET_POWER && reload_completed"
4823 [(parallel [(set (match_dup 0)
4824 (ashift:SI (match_dup 1) (match_dup 2)))
4825 (clobber (match_dup 4))])
4827 (compare:CC (match_dup 0)
4832 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4833 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4834 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4836 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4837 (ashift:SI (match_dup 1) (match_dup 2)))]
4838 "! TARGET_POWER && TARGET_32BIT"
4841 {sli.|slwi.} %0,%1,%h2
4844 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4845 (set_attr "length" "4,4,8,8")])
4848 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4849 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4850 (match_operand:SI 2 "reg_or_cint_operand" ""))
4852 (set (match_operand:SI 0 "gpc_reg_operand" "")
4853 (ashift:SI (match_dup 1) (match_dup 2)))]
4854 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4856 (ashift:SI (match_dup 1) (match_dup 2)))
4858 (compare:CC (match_dup 0)
4862 (define_insn "rlwinm"
4863 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4864 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4865 (match_operand:SI 2 "const_int_operand" "i"))
4866 (match_operand:SI 3 "mask_operand" "n")))]
4867 "includes_lshift_p (operands[2], operands[3])"
4868 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4871 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4873 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4874 (match_operand:SI 2 "const_int_operand" "i,i"))
4875 (match_operand:SI 3 "mask_operand" "n,n"))
4877 (clobber (match_scratch:SI 4 "=r,r"))]
4878 "includes_lshift_p (operands[2], operands[3])"
4880 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4882 [(set_attr "type" "delayed_compare")
4883 (set_attr "length" "4,8")])
4886 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4888 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4889 (match_operand:SI 2 "const_int_operand" ""))
4890 (match_operand:SI 3 "mask_operand" ""))
4892 (clobber (match_scratch:SI 4 ""))]
4893 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4895 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4898 (compare:CC (match_dup 4)
4903 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4905 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4906 (match_operand:SI 2 "const_int_operand" "i,i"))
4907 (match_operand:SI 3 "mask_operand" "n,n"))
4909 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4910 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4911 "includes_lshift_p (operands[2], operands[3])"
4913 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4915 [(set_attr "type" "delayed_compare")
4916 (set_attr "length" "4,8")])
4919 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4921 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4922 (match_operand:SI 2 "const_int_operand" ""))
4923 (match_operand:SI 3 "mask_operand" ""))
4925 (set (match_operand:SI 0 "gpc_reg_operand" "")
4926 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4927 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4929 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4931 (compare:CC (match_dup 0)
4935 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4937 (define_expand "lshrsi3"
4938 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4939 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4940 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4945 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4947 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4951 (define_insn "lshrsi3_power"
4952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4953 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4954 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4955 (clobber (match_scratch:SI 3 "=q,X,X"))]
4960 {s%A2i|s%A2wi} %0,%1,%h2")
4962 (define_insn "lshrsi3_no_power"
4963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4964 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4965 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4970 {sri|srwi} %0,%1,%h2"
4971 [(set_attr "type" "integer,var_shift_rotate,shift")])
4973 (define_insn "*lshrsi3_64"
4974 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4976 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4977 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4981 {sri|srwi} %0,%1,%h2"
4982 [(set_attr "type" "var_shift_rotate,shift")])
4985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4986 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4987 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4989 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4990 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4995 {s%A2i.|s%A2wi.} %3,%1,%h2
4999 [(set_attr "type" "delayed_compare")
5000 (set_attr "length" "4,4,4,8,8,8")])
5003 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5004 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5005 (match_operand:SI 2 "reg_or_cint_operand" ""))
5007 (clobber (match_scratch:SI 3 ""))
5008 (clobber (match_scratch:SI 4 ""))]
5009 "TARGET_POWER && reload_completed"
5010 [(parallel [(set (match_dup 3)
5011 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5012 (clobber (match_dup 4))])
5014 (compare:CC (match_dup 3)
5019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5020 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5021 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5023 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5024 "! TARGET_POWER && TARGET_32BIT"
5028 {sri.|srwi.} %3,%1,%h2
5032 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5033 (set_attr "length" "4,4,4,8,8,8")])
5036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5037 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5038 (match_operand:SI 2 "reg_or_cint_operand" ""))
5040 (clobber (match_scratch:SI 3 ""))]
5041 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5043 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5045 (compare:CC (match_dup 3)
5050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5051 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5052 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5054 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5055 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5056 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5061 {s%A2i.|s%A2wi.} %0,%1,%h2
5065 [(set_attr "type" "delayed_compare")
5066 (set_attr "length" "4,4,4,8,8,8")])
5069 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5070 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5071 (match_operand:SI 2 "reg_or_cint_operand" ""))
5073 (set (match_operand:SI 0 "gpc_reg_operand" "")
5074 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5075 (clobber (match_scratch:SI 4 ""))]
5076 "TARGET_POWER && reload_completed"
5077 [(parallel [(set (match_dup 0)
5078 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5079 (clobber (match_dup 4))])
5081 (compare:CC (match_dup 0)
5086 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5087 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5088 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5090 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5091 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5092 "! TARGET_POWER && TARGET_32BIT"
5096 {sri.|srwi.} %0,%1,%h2
5100 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5101 (set_attr "length" "4,4,4,8,8,8")])
5104 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5105 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5106 (match_operand:SI 2 "reg_or_cint_operand" ""))
5108 (set (match_operand:SI 0 "gpc_reg_operand" "")
5109 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5110 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5112 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5114 (compare:CC (match_dup 0)
5119 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5120 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5121 (match_operand:SI 2 "const_int_operand" "i"))
5122 (match_operand:SI 3 "mask_operand" "n")))]
5123 "includes_rshift_p (operands[2], operands[3])"
5124 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5127 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5129 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5130 (match_operand:SI 2 "const_int_operand" "i,i"))
5131 (match_operand:SI 3 "mask_operand" "n,n"))
5133 (clobber (match_scratch:SI 4 "=r,r"))]
5134 "includes_rshift_p (operands[2], operands[3])"
5136 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5138 [(set_attr "type" "delayed_compare")
5139 (set_attr "length" "4,8")])
5142 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5144 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5145 (match_operand:SI 2 "const_int_operand" ""))
5146 (match_operand:SI 3 "mask_operand" ""))
5148 (clobber (match_scratch:SI 4 ""))]
5149 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5151 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5154 (compare:CC (match_dup 4)
5159 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5161 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5162 (match_operand:SI 2 "const_int_operand" "i,i"))
5163 (match_operand:SI 3 "mask_operand" "n,n"))
5165 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5166 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5167 "includes_rshift_p (operands[2], operands[3])"
5169 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5171 [(set_attr "type" "delayed_compare")
5172 (set_attr "length" "4,8")])
5175 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5177 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5178 (match_operand:SI 2 "const_int_operand" ""))
5179 (match_operand:SI 3 "mask_operand" ""))
5181 (set (match_operand:SI 0 "gpc_reg_operand" "")
5182 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5183 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5185 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5187 (compare:CC (match_dup 0)
5192 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5195 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5196 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5197 "includes_rshift_p (operands[2], GEN_INT (255))"
5198 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5201 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5205 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5206 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5208 (clobber (match_scratch:SI 3 "=r,r"))]
5209 "includes_rshift_p (operands[2], GEN_INT (255))"
5211 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5213 [(set_attr "type" "delayed_compare")
5214 (set_attr "length" "4,8")])
5217 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5221 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5222 (match_operand:SI 2 "const_int_operand" "")) 0))
5224 (clobber (match_scratch:SI 3 ""))]
5225 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5227 (zero_extend:SI (subreg:QI
5228 (lshiftrt:SI (match_dup 1)
5231 (compare:CC (match_dup 3)
5236 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5240 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5241 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5243 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5244 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5245 "includes_rshift_p (operands[2], GEN_INT (255))"
5247 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5249 [(set_attr "type" "delayed_compare")
5250 (set_attr "length" "4,8")])
5253 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5257 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5258 (match_operand:SI 2 "const_int_operand" "")) 0))
5260 (set (match_operand:SI 0 "gpc_reg_operand" "")
5261 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5262 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5264 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5266 (compare:CC (match_dup 0)
5271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5274 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5275 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5276 "includes_rshift_p (operands[2], GEN_INT (65535))"
5277 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5284 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5285 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5287 (clobber (match_scratch:SI 3 "=r,r"))]
5288 "includes_rshift_p (operands[2], GEN_INT (65535))"
5290 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5292 [(set_attr "type" "delayed_compare")
5293 (set_attr "length" "4,8")])
5296 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5300 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5301 (match_operand:SI 2 "const_int_operand" "")) 0))
5303 (clobber (match_scratch:SI 3 ""))]
5304 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5306 (zero_extend:SI (subreg:HI
5307 (lshiftrt:SI (match_dup 1)
5310 (compare:CC (match_dup 3)
5315 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5319 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5320 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5322 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5323 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5324 "includes_rshift_p (operands[2], GEN_INT (65535))"
5326 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5328 [(set_attr "type" "delayed_compare")
5329 (set_attr "length" "4,8")])
5332 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5336 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5337 (match_operand:SI 2 "const_int_operand" "")) 0))
5339 (set (match_operand:SI 0 "gpc_reg_operand" "")
5340 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5341 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5343 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5345 (compare:CC (match_dup 0)
5350 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5352 (match_operand:SI 1 "gpc_reg_operand" "r"))
5353 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5359 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5361 (match_operand:SI 1 "gpc_reg_operand" "r"))
5362 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5368 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5370 (match_operand:SI 1 "gpc_reg_operand" "r"))
5371 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5377 (define_expand "ashrsi3"
5378 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5379 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5380 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5385 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5387 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5391 (define_insn "ashrsi3_power"
5392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5393 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5394 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5395 (clobber (match_scratch:SI 3 "=q,X"))]
5399 {srai|srawi} %0,%1,%h2"
5400 [(set_attr "type" "shift")])
5402 (define_insn "ashrsi3_no_power"
5403 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5404 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5405 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5409 {srai|srawi} %0,%1,%h2"
5410 [(set_attr "type" "var_shift_rotate,shift")])
5412 (define_insn "*ashrsi3_64"
5413 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5415 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5416 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5420 {srai|srawi} %0,%1,%h2"
5421 [(set_attr "type" "var_shift_rotate,shift")])
5424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5425 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5426 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5428 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5429 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5433 {srai.|srawi.} %3,%1,%h2
5436 [(set_attr "type" "delayed_compare")
5437 (set_attr "length" "4,4,8,8")])
5440 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5441 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5442 (match_operand:SI 2 "reg_or_cint_operand" ""))
5444 (clobber (match_scratch:SI 3 ""))
5445 (clobber (match_scratch:SI 4 ""))]
5446 "TARGET_POWER && reload_completed"
5447 [(parallel [(set (match_dup 3)
5448 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5449 (clobber (match_dup 4))])
5451 (compare:CC (match_dup 3)
5456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5457 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5458 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5460 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5463 {sra.|sraw.} %3,%1,%2
5464 {srai.|srawi.} %3,%1,%h2
5467 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5468 (set_attr "length" "4,4,8,8")])
5471 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5472 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5473 (match_operand:SI 2 "reg_or_cint_operand" ""))
5475 (clobber (match_scratch:SI 3 ""))]
5476 "! TARGET_POWER && reload_completed"
5478 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5480 (compare:CC (match_dup 3)
5485 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5486 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5487 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5489 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5490 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5491 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5495 {srai.|srawi.} %0,%1,%h2
5498 [(set_attr "type" "delayed_compare")
5499 (set_attr "length" "4,4,8,8")])
5502 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5503 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5504 (match_operand:SI 2 "reg_or_cint_operand" ""))
5506 (set (match_operand:SI 0 "gpc_reg_operand" "")
5507 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5508 (clobber (match_scratch:SI 4 ""))]
5509 "TARGET_POWER && reload_completed"
5510 [(parallel [(set (match_dup 0)
5511 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5512 (clobber (match_dup 4))])
5514 (compare:CC (match_dup 0)
5519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5520 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5521 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5523 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5524 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5527 {sra.|sraw.} %0,%1,%2
5528 {srai.|srawi.} %0,%1,%h2
5531 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5532 (set_attr "length" "4,4,8,8")])
5535 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5536 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5537 (match_operand:SI 2 "reg_or_cint_operand" ""))
5539 (set (match_operand:SI 0 "gpc_reg_operand" "")
5540 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5541 "! TARGET_POWER && reload_completed"
5543 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5545 (compare:CC (match_dup 0)
5549 ;; Floating-point insns, excluding normal data motion.
5551 ;; PowerPC has a full set of single-precision floating point instructions.
5553 ;; For the POWER architecture, we pretend that we have both SFmode and
5554 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5555 ;; The only conversions we will do will be when storing to memory. In that
5556 ;; case, we will use the "frsp" instruction before storing.
5558 ;; Note that when we store into a single-precision memory location, we need to
5559 ;; use the frsp insn first. If the register being stored isn't dead, we
5560 ;; need a scratch register for the frsp. But this is difficult when the store
5561 ;; is done by reload. It is not incorrect to do the frsp on the register in
5562 ;; this case, we just lose precision that we would have otherwise gotten but
5563 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5565 (define_expand "extendsfdf2"
5566 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5567 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5568 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5571 (define_insn_and_split "*extendsfdf2_fpr"
5572 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5573 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5574 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5579 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5582 emit_note (NOTE_INSN_DELETED);
5585 [(set_attr "type" "fp,fp,fpload")])
5587 (define_expand "truncdfsf2"
5588 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5589 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5590 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5593 (define_insn "*truncdfsf2_fpr"
5594 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5595 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5596 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5598 [(set_attr "type" "fp")])
5600 (define_insn "aux_truncdfsf2"
5601 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5602 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5603 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5605 [(set_attr "type" "fp")])
5607 (define_expand "negsf2"
5608 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5609 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5610 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5613 (define_insn "*negsf2"
5614 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5615 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5616 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5618 [(set_attr "type" "fp")])
5620 (define_expand "abssf2"
5621 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5622 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5623 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5626 (define_insn "*abssf2"
5627 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5628 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5629 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5631 [(set_attr "type" "fp")])
5634 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5635 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5636 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5638 [(set_attr "type" "fp")])
5640 (define_expand "addsf3"
5641 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5642 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5643 (match_operand:SF 2 "gpc_reg_operand" "")))]
5644 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5648 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5649 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5650 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5651 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5653 [(set_attr "type" "fp")
5654 (set_attr "fp_type" "fp_addsub_s")])
5657 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5658 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5659 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5660 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5661 "{fa|fadd} %0,%1,%2"
5662 [(set_attr "type" "fp")])
5664 (define_expand "subsf3"
5665 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5666 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5667 (match_operand:SF 2 "gpc_reg_operand" "")))]
5668 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5672 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5673 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5674 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5675 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5677 [(set_attr "type" "fp")
5678 (set_attr "fp_type" "fp_addsub_s")])
5681 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5682 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5683 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5684 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5685 "{fs|fsub} %0,%1,%2"
5686 [(set_attr "type" "fp")])
5688 (define_expand "mulsf3"
5689 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5690 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5691 (match_operand:SF 2 "gpc_reg_operand" "")))]
5692 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5696 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5697 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5698 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5699 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5701 [(set_attr "type" "fp")
5702 (set_attr "fp_type" "fp_mul_s")])
5705 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5706 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5707 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5708 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5709 "{fm|fmul} %0,%1,%2"
5710 [(set_attr "type" "dmul")])
5712 (define_expand "divsf3"
5713 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5714 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5715 (match_operand:SF 2 "gpc_reg_operand" "")))]
5716 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5720 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5721 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5722 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5723 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5724 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5726 [(set_attr "type" "sdiv")])
5729 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5730 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5731 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5732 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5733 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5734 "{fd|fdiv} %0,%1,%2"
5735 [(set_attr "type" "ddiv")])
5737 (define_expand "recipsf3"
5738 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5739 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5740 (match_operand:SF 2 "gpc_reg_operand" "f")]
5742 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5743 && flag_finite_math_only && !flag_trapping_math"
5745 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5750 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5751 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5752 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5754 [(set_attr "type" "fp")])
5756 (define_insn "*fmaddsf4_powerpc"
5757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5758 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5759 (match_operand:SF 2 "gpc_reg_operand" "f"))
5760 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5761 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5762 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5763 "fmadds %0,%1,%2,%3"
5764 [(set_attr "type" "fp")
5765 (set_attr "fp_type" "fp_maddsub_s")])
5767 (define_insn "*fmaddsf4_power"
5768 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5769 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5770 (match_operand:SF 2 "gpc_reg_operand" "f"))
5771 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5772 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5773 "{fma|fmadd} %0,%1,%2,%3"
5774 [(set_attr "type" "dmul")])
5776 (define_insn "*fmsubsf4_powerpc"
5777 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5778 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5779 (match_operand:SF 2 "gpc_reg_operand" "f"))
5780 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5781 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5782 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5783 "fmsubs %0,%1,%2,%3"
5784 [(set_attr "type" "fp")
5785 (set_attr "fp_type" "fp_maddsub_s")])
5787 (define_insn "*fmsubsf4_power"
5788 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5789 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5790 (match_operand:SF 2 "gpc_reg_operand" "f"))
5791 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5792 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5793 "{fms|fmsub} %0,%1,%2,%3"
5794 [(set_attr "type" "dmul")])
5796 (define_insn "*fnmaddsf4_powerpc_1"
5797 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5798 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5799 (match_operand:SF 2 "gpc_reg_operand" "f"))
5800 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5801 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5802 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5803 "fnmadds %0,%1,%2,%3"
5804 [(set_attr "type" "fp")
5805 (set_attr "fp_type" "fp_maddsub_s")])
5807 (define_insn "*fnmaddsf4_powerpc_2"
5808 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5809 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5810 (match_operand:SF 2 "gpc_reg_operand" "f"))
5811 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5812 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5813 && ! HONOR_SIGNED_ZEROS (SFmode)"
5814 "fnmadds %0,%1,%2,%3"
5815 [(set_attr "type" "fp")
5816 (set_attr "fp_type" "fp_maddsub_s")])
5818 (define_insn "*fnmaddsf4_power_1"
5819 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5820 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5821 (match_operand:SF 2 "gpc_reg_operand" "f"))
5822 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5823 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5824 "{fnma|fnmadd} %0,%1,%2,%3"
5825 [(set_attr "type" "dmul")])
5827 (define_insn "*fnmaddsf4_power_2"
5828 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5829 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5830 (match_operand:SF 2 "gpc_reg_operand" "f"))
5831 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5832 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5833 && ! HONOR_SIGNED_ZEROS (SFmode)"
5834 "{fnma|fnmadd} %0,%1,%2,%3"
5835 [(set_attr "type" "dmul")])
5837 (define_insn "*fnmsubsf4_powerpc_1"
5838 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5839 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5840 (match_operand:SF 2 "gpc_reg_operand" "f"))
5841 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5842 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5843 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5844 "fnmsubs %0,%1,%2,%3"
5845 [(set_attr "type" "fp")
5846 (set_attr "fp_type" "fp_maddsub_s")])
5848 (define_insn "*fnmsubsf4_powerpc_2"
5849 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5850 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5851 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5852 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5853 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5854 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5855 "fnmsubs %0,%1,%2,%3"
5856 [(set_attr "type" "fp")
5857 (set_attr "fp_type" "fp_maddsub_s")])
5859 (define_insn "*fnmsubsf4_power_1"
5860 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5861 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5862 (match_operand:SF 2 "gpc_reg_operand" "f"))
5863 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5864 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5865 "{fnms|fnmsub} %0,%1,%2,%3"
5866 [(set_attr "type" "dmul")])
5868 (define_insn "*fnmsubsf4_power_2"
5869 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5870 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5871 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5872 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5873 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5874 && ! HONOR_SIGNED_ZEROS (SFmode)"
5875 "{fnms|fnmsub} %0,%1,%2,%3"
5876 [(set_attr "type" "dmul")])
5878 (define_expand "sqrtsf2"
5879 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5880 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5881 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5882 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5883 && !TARGET_SIMPLE_FPU"
5887 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5888 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5889 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5890 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5892 [(set_attr "type" "ssqrt")])
5895 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5896 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5897 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5898 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5900 [(set_attr "type" "dsqrt")])
5902 (define_expand "rsqrtsf2"
5903 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5904 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5906 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5907 && flag_finite_math_only && !flag_trapping_math"
5909 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5913 (define_insn "*rsqrt_internal1"
5914 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5915 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5917 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5919 [(set_attr "type" "fp")])
5921 (define_expand "copysignsf3"
5923 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5925 (neg:SF (abs:SF (match_dup 1))))
5926 (set (match_operand:SF 0 "gpc_reg_operand" "")
5927 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5931 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5932 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5934 operands[3] = gen_reg_rtx (SFmode);
5935 operands[4] = gen_reg_rtx (SFmode);
5936 operands[5] = CONST0_RTX (SFmode);
5939 (define_expand "copysigndf3"
5941 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5943 (neg:DF (abs:DF (match_dup 1))))
5944 (set (match_operand:DF 0 "gpc_reg_operand" "")
5945 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5949 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5950 && ((TARGET_PPC_GFXOPT
5951 && !HONOR_NANS (DFmode)
5952 && !HONOR_SIGNED_ZEROS (DFmode))
5953 || VECTOR_UNIT_VSX_P (DFmode))"
5955 if (VECTOR_UNIT_VSX_P (DFmode))
5957 emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
5958 operands[2], CONST0_RTX (DFmode)));
5961 operands[3] = gen_reg_rtx (DFmode);
5962 operands[4] = gen_reg_rtx (DFmode);
5963 operands[5] = CONST0_RTX (DFmode);
5966 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5967 ;; fsel instruction and some auxiliary computations. Then we just have a
5968 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5970 (define_expand "smaxsf3"
5971 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5972 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5973 (match_operand:SF 2 "gpc_reg_operand" ""))
5976 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5977 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5978 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5980 (define_expand "sminsf3"
5981 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5982 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5983 (match_operand:SF 2 "gpc_reg_operand" ""))
5986 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5987 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5988 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5991 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5992 (match_operator:SF 3 "min_max_operator"
5993 [(match_operand:SF 1 "gpc_reg_operand" "")
5994 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5995 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5996 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5999 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6000 operands[1], operands[2]);
6004 (define_expand "mov<mode>cc"
6005 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6006 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6007 (match_operand:GPR 2 "gpc_reg_operand" "")
6008 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6012 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6018 ;; We use the BASE_REGS for the isel input operands because, if rA is
6019 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6020 ;; because we may switch the operands and rB may end up being rA.
6022 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6023 ;; leave out the mode in operand 4 and use one pattern, but reload can
6024 ;; change the mode underneath our feet and then gets confused trying
6025 ;; to reload the value.
6026 (define_insn "isel_signed_<mode>"
6027 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6029 (match_operator 1 "comparison_operator"
6030 [(match_operand:CC 4 "cc_reg_operand" "y")
6032 (match_operand:GPR 2 "gpc_reg_operand" "b")
6033 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6036 { return output_isel (operands); }"
6037 [(set_attr "length" "4")])
6039 (define_insn "isel_unsigned_<mode>"
6040 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6042 (match_operator 1 "comparison_operator"
6043 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6045 (match_operand:GPR 2 "gpc_reg_operand" "b")
6046 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6049 { return output_isel (operands); }"
6050 [(set_attr "length" "4")])
6052 (define_expand "movsfcc"
6053 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6054 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6055 (match_operand:SF 2 "gpc_reg_operand" "")
6056 (match_operand:SF 3 "gpc_reg_operand" "")))]
6057 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6060 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6066 (define_insn "*fselsfsf4"
6067 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6068 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6069 (match_operand:SF 4 "zero_fp_constant" "F"))
6070 (match_operand:SF 2 "gpc_reg_operand" "f")
6071 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6072 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6074 [(set_attr "type" "fp")])
6076 (define_insn "*fseldfsf4"
6077 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6078 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6079 (match_operand:DF 4 "zero_fp_constant" "F"))
6080 (match_operand:SF 2 "gpc_reg_operand" "f")
6081 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6082 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6084 [(set_attr "type" "fp")])
6086 (define_expand "negdf2"
6087 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6088 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6089 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6092 (define_insn "*negdf2_fpr"
6093 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6094 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6095 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6096 && !VECTOR_UNIT_VSX_P (DFmode)"
6098 [(set_attr "type" "fp")])
6100 (define_expand "absdf2"
6101 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6102 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6103 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6106 (define_insn "*absdf2_fpr"
6107 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6108 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6109 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6110 && !VECTOR_UNIT_VSX_P (DFmode)"
6112 [(set_attr "type" "fp")])
6114 (define_insn "*nabsdf2_fpr"
6115 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6116 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6117 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6118 && !VECTOR_UNIT_VSX_P (DFmode)"
6120 [(set_attr "type" "fp")])
6122 (define_expand "adddf3"
6123 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6124 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6125 (match_operand:DF 2 "gpc_reg_operand" "")))]
6126 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6129 (define_insn "*adddf3_fpr"
6130 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6131 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6132 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6133 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6134 && !VECTOR_UNIT_VSX_P (DFmode)"
6135 "{fa|fadd} %0,%1,%2"
6136 [(set_attr "type" "fp")
6137 (set_attr "fp_type" "fp_addsub_d")])
6139 (define_expand "subdf3"
6140 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6141 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6142 (match_operand:DF 2 "gpc_reg_operand" "")))]
6143 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6146 (define_insn "*subdf3_fpr"
6147 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6148 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6149 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6150 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6151 && !VECTOR_UNIT_VSX_P (DFmode)"
6152 "{fs|fsub} %0,%1,%2"
6153 [(set_attr "type" "fp")
6154 (set_attr "fp_type" "fp_addsub_d")])
6156 (define_expand "muldf3"
6157 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6158 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6159 (match_operand:DF 2 "gpc_reg_operand" "")))]
6160 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6163 (define_insn "*muldf3_fpr"
6164 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6165 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6166 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6167 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6168 && !VECTOR_UNIT_VSX_P (DFmode)"
6169 "{fm|fmul} %0,%1,%2"
6170 [(set_attr "type" "dmul")
6171 (set_attr "fp_type" "fp_mul_d")])
6173 (define_expand "divdf3"
6174 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6175 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6176 (match_operand:DF 2 "gpc_reg_operand" "")))]
6178 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6179 && !TARGET_SIMPLE_FPU"
6182 (define_insn "*divdf3_fpr"
6183 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6184 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6185 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6186 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6187 && !VECTOR_UNIT_VSX_P (DFmode)"
6188 "{fd|fdiv} %0,%1,%2"
6189 [(set_attr "type" "ddiv")])
6191 (define_expand "recipdf3"
6192 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6193 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
6194 (match_operand:DF 2 "gpc_reg_operand" "d")]
6196 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
6197 && flag_finite_math_only && !flag_trapping_math"
6199 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
6203 (define_expand "fred"
6204 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6205 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
6206 "(TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) && flag_finite_math_only"
6209 (define_insn "*fred_fpr"
6210 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6211 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6212 "TARGET_POPCNTB && flag_finite_math_only && !VECTOR_UNIT_VSX_P (DFmode)"
6214 [(set_attr "type" "fp")])
6216 (define_insn "*fmadddf4_fpr"
6217 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6218 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6219 (match_operand:DF 2 "gpc_reg_operand" "d"))
6220 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6221 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6222 && VECTOR_UNIT_NONE_P (DFmode)"
6223 "{fma|fmadd} %0,%1,%2,%3"
6224 [(set_attr "type" "dmul")
6225 (set_attr "fp_type" "fp_maddsub_d")])
6227 (define_insn "*fmsubdf4_fpr"
6228 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6229 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6230 (match_operand:DF 2 "gpc_reg_operand" "d"))
6231 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6232 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6233 && VECTOR_UNIT_NONE_P (DFmode)"
6234 "{fms|fmsub} %0,%1,%2,%3"
6235 [(set_attr "type" "dmul")
6236 (set_attr "fp_type" "fp_maddsub_d")])
6238 (define_insn "*fnmadddf4_fpr_1"
6239 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6240 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6241 (match_operand:DF 2 "gpc_reg_operand" "d"))
6242 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6243 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6244 && HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6245 "{fnma|fnmadd} %0,%1,%2,%3"
6246 [(set_attr "type" "dmul")
6247 (set_attr "fp_type" "fp_maddsub_d")])
6249 (define_insn "*fnmadddf4_fpr_2"
6250 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6251 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6252 (match_operand:DF 2 "gpc_reg_operand" "d"))
6253 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6254 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6255 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6256 "{fnma|fnmadd} %0,%1,%2,%3"
6257 [(set_attr "type" "dmul")
6258 (set_attr "fp_type" "fp_maddsub_d")])
6260 (define_insn "*fnmsubdf4_fpr_1"
6261 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6262 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6263 (match_operand:DF 2 "gpc_reg_operand" "d"))
6264 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6265 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6266 && HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6267 "{fnms|fnmsub} %0,%1,%2,%3"
6268 [(set_attr "type" "dmul")
6269 (set_attr "fp_type" "fp_maddsub_d")])
6271 (define_insn "*fnmsubdf4_fpr_2"
6272 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6273 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6274 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6275 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6276 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6277 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6278 "{fnms|fnmsub} %0,%1,%2,%3"
6279 [(set_attr "type" "dmul")
6280 (set_attr "fp_type" "fp_maddsub_d")])
6282 (define_insn "sqrtdf2"
6283 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6284 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6285 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6286 && TARGET_DOUBLE_FLOAT
6287 && !VECTOR_UNIT_VSX_P (DFmode)"
6289 [(set_attr "type" "dsqrt")])
6291 ;; The conditional move instructions allow us to perform max and min
6292 ;; operations even when
6294 (define_expand "smaxdf3"
6295 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6296 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6297 (match_operand:DF 2 "gpc_reg_operand" ""))
6300 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6301 && !flag_trapping_math"
6302 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6304 (define_expand "smindf3"
6305 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6306 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6307 (match_operand:DF 2 "gpc_reg_operand" ""))
6310 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6311 && !flag_trapping_math"
6312 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6315 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6316 (match_operator:DF 3 "min_max_operator"
6317 [(match_operand:DF 1 "gpc_reg_operand" "")
6318 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6319 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6320 && !flag_trapping_math"
6323 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6324 operands[1], operands[2]);
6328 (define_expand "movdfcc"
6329 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6330 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6331 (match_operand:DF 2 "gpc_reg_operand" "")
6332 (match_operand:DF 3 "gpc_reg_operand" "")))]
6333 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6336 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6342 (define_insn "*fseldfdf4"
6343 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6344 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6345 (match_operand:DF 4 "zero_fp_constant" "F"))
6346 (match_operand:DF 2 "gpc_reg_operand" "d")
6347 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6348 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6350 [(set_attr "type" "fp")])
6352 (define_insn "*fselsfdf4"
6353 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6354 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6355 (match_operand:SF 4 "zero_fp_constant" "F"))
6356 (match_operand:DF 2 "gpc_reg_operand" "d")
6357 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6358 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6360 [(set_attr "type" "fp")])
6362 ;; Conversions to and from floating-point.
6364 (define_expand "fixuns_truncsfsi2"
6365 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6366 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6367 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6370 (define_expand "fix_truncsfsi2"
6371 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6372 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6373 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6376 (define_expand "fixuns_truncdfsi2"
6377 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6378 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6379 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6382 (define_expand "fixuns_truncdfdi2"
6383 [(set (match_operand:DI 0 "register_operand" "")
6384 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6385 "TARGET_HARD_FLOAT && TARGET_VSX"
6388 ; For each of these conversions, there is a define_expand, a define_insn
6389 ; with a '#' template, and a define_split (with C code). The idea is
6390 ; to allow constant folding with the template of the define_insn,
6391 ; then to have the insns split later (between sched1 and final).
6393 (define_expand "floatsidf2"
6394 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6395 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6398 (clobber (match_dup 4))
6399 (clobber (match_dup 5))
6400 (clobber (match_dup 6))])]
6402 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6405 if (TARGET_E500_DOUBLE)
6407 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6410 if (TARGET_POWERPC64)
6412 rtx x = convert_to_mode (DImode, operands[1], 0);
6413 emit_insn (gen_floatdidf2 (operands[0], x));
6417 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6418 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6419 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6420 operands[5] = gen_reg_rtx (DFmode);
6421 operands[6] = gen_reg_rtx (SImode);
6424 (define_insn_and_split "*floatsidf2_internal"
6425 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6426 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6427 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6428 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6429 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6430 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6431 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6432 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6438 rtx lowword, highword;
6439 gcc_assert (MEM_P (operands[4]));
6440 highword = adjust_address (operands[4], SImode, 0);
6441 lowword = adjust_address (operands[4], SImode, 4);
6442 if (! WORDS_BIG_ENDIAN)
6445 tmp = highword; highword = lowword; lowword = tmp;
6448 emit_insn (gen_xorsi3 (operands[6], operands[1],
6449 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6450 emit_move_insn (lowword, operands[6]);
6451 emit_move_insn (highword, operands[2]);
6452 emit_move_insn (operands[5], operands[4]);
6453 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6456 [(set_attr "length" "24")])
6458 (define_expand "floatunssisf2"
6459 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6460 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6461 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6464 (define_expand "floatunssidf2"
6465 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6466 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6469 (clobber (match_dup 4))
6470 (clobber (match_dup 5))])]
6471 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6474 if (TARGET_E500_DOUBLE)
6476 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6479 if (TARGET_POWERPC64)
6481 rtx x = convert_to_mode (DImode, operands[1], 1);
6482 emit_insn (gen_floatdidf2 (operands[0], x));
6486 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6487 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6488 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6489 operands[5] = gen_reg_rtx (DFmode);
6492 (define_insn_and_split "*floatunssidf2_internal"
6493 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6494 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6495 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6496 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6497 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6498 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6499 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6505 rtx lowword, highword;
6506 gcc_assert (MEM_P (operands[4]));
6507 highword = adjust_address (operands[4], SImode, 0);
6508 lowword = adjust_address (operands[4], SImode, 4);
6509 if (! WORDS_BIG_ENDIAN)
6512 tmp = highword; highword = lowword; lowword = tmp;
6515 emit_move_insn (lowword, operands[1]);
6516 emit_move_insn (highword, operands[2]);
6517 emit_move_insn (operands[5], operands[4]);
6518 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6521 [(set_attr "length" "20")])
6523 (define_expand "fix_truncdfsi2"
6524 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6525 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6526 (clobber (match_dup 2))
6527 (clobber (match_dup 3))])]
6528 "(TARGET_POWER2 || TARGET_POWERPC)
6529 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6532 if (TARGET_E500_DOUBLE)
6534 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6537 operands[2] = gen_reg_rtx (DImode);
6538 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6539 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6541 operands[3] = gen_reg_rtx (DImode);
6542 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6543 operands[2], operands[3]));
6546 if (TARGET_PPC_GFXOPT)
6548 rtx orig_dest = operands[0];
6549 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6550 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6551 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6553 if (operands[0] != orig_dest)
6554 emit_move_insn (orig_dest, operands[0]);
6557 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6560 (define_insn_and_split "*fix_truncdfsi2_internal"
6561 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6562 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6563 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6564 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6565 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6566 && TARGET_DOUBLE_FLOAT"
6573 gcc_assert (MEM_P (operands[3]));
6574 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6576 emit_insn (gen_fctiwz (operands[2], operands[1]));
6577 emit_move_insn (operands[3], operands[2]);
6578 emit_move_insn (operands[0], lowword);
6581 [(set_attr "length" "16")])
6583 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6584 [(set (match_operand:SI 0 "memory_operand" "=Z")
6585 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6586 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6587 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6588 && TARGET_DOUBLE_FLOAT
6589 && TARGET_PPC_GFXOPT"
6595 emit_insn (gen_fctiwz (operands[2], operands[1]));
6596 emit_insn (gen_stfiwx (operands[0], operands[2]));
6599 [(set_attr "length" "16")])
6601 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6603 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6604 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6605 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6606 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6607 && TARGET_DOUBLE_FLOAT"
6610 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6611 (set (match_dup 3) (match_dup 2))
6612 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6614 [(set_attr "length" "12")])
6616 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6617 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6618 ; because the first makes it clear that operand 0 is not live
6619 ; before the instruction.
6620 (define_insn "fctiwz"
6621 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6622 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6624 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6625 && TARGET_DOUBLE_FLOAT"
6626 "{fcirz|fctiwz} %0,%1"
6627 [(set_attr "type" "fp")])
6629 (define_expand "btruncdf2"
6630 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6631 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6632 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6635 (define_insn "*btruncdf2_fpr"
6636 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6637 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6638 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6639 && !VECTOR_UNIT_VSX_P (DFmode)"
6641 [(set_attr "type" "fp")])
6643 (define_insn "btruncsf2"
6644 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6645 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6646 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6648 [(set_attr "type" "fp")])
6650 (define_expand "ceildf2"
6651 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6652 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6653 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6656 (define_insn "*ceildf2_fpr"
6657 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6658 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6659 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6660 && !VECTOR_UNIT_VSX_P (DFmode)"
6662 [(set_attr "type" "fp")])
6664 (define_insn "ceilsf2"
6665 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6666 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6667 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6669 [(set_attr "type" "fp")])
6671 (define_expand "floordf2"
6672 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6673 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6674 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6677 (define_insn "*floordf2_fpr"
6678 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6679 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6680 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6681 && !VECTOR_UNIT_VSX_P (DFmode)"
6683 [(set_attr "type" "fp")])
6685 (define_insn "floorsf2"
6686 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6687 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6688 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6690 [(set_attr "type" "fp")])
6692 ;; No VSX equivalent to frin
6693 (define_insn "rounddf2"
6694 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6695 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6696 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6698 [(set_attr "type" "fp")])
6700 (define_insn "roundsf2"
6701 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6702 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6703 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6705 [(set_attr "type" "fp")])
6707 (define_expand "ftruncdf2"
6708 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6709 (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6710 "VECTOR_UNIT_VSX_P (DFmode)"
6713 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6714 (define_insn "stfiwx"
6715 [(set (match_operand:SI 0 "memory_operand" "=Z")
6716 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6720 [(set_attr "type" "fpstore")])
6722 (define_expand "floatsisf2"
6723 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6724 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6725 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6728 (define_expand "floatdidf2"
6729 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6730 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6731 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6732 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6735 (define_insn "*floatdidf2_fpr"
6736 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6737 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6738 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6739 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6740 && !VECTOR_UNIT_VSX_P (DFmode)"
6742 [(set_attr "type" "fp")])
6744 (define_expand "floatunsdidf2"
6745 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6746 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6750 (define_expand "fix_truncdfdi2"
6751 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6752 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6753 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6754 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6757 (define_insn "*fix_truncdfdi2_fpr"
6758 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6759 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6760 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
6761 && TARGET_DOUBLE_FLOAT && TARGET_FPRS && !VECTOR_UNIT_VSX_P (DFmode)"
6763 [(set_attr "type" "fp")])
6765 (define_expand "floatdisf2"
6766 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6767 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6768 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6771 rtx val = operands[1];
6772 if (!flag_unsafe_math_optimizations)
6774 rtx label = gen_label_rtx ();
6775 val = gen_reg_rtx (DImode);
6776 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6779 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6783 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6784 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6785 ;; from double rounding.
6786 (define_insn_and_split "floatdisf2_internal1"
6787 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6788 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6789 (clobber (match_scratch:DF 2 "=d"))]
6790 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6792 "&& reload_completed"
6794 (float:DF (match_dup 1)))
6796 (float_truncate:SF (match_dup 2)))]
6799 ;; Twiddles bits to avoid double rounding.
6800 ;; Bits that might be truncated when converting to DFmode are replaced
6801 ;; by a bit that won't be lost at that stage, but is below the SFmode
6802 ;; rounding position.
6803 (define_expand "floatdisf2_internal2"
6804 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6806 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6808 (clobber (scratch:CC))])
6809 (set (match_dup 3) (plus:DI (match_dup 3)
6811 (set (match_dup 0) (plus:DI (match_dup 0)
6813 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6815 (set (match_dup 0) (ior:DI (match_dup 0)
6817 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6819 (clobber (scratch:CC))])
6820 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6821 (label_ref (match_operand:DI 2 "" ""))
6823 (set (match_dup 0) (match_dup 1))]
6824 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6827 operands[3] = gen_reg_rtx (DImode);
6828 operands[4] = gen_reg_rtx (CCUNSmode);
6831 ;; Define the DImode operations that can be done in a small number
6832 ;; of instructions. The & constraints are to prevent the register
6833 ;; allocator from allocating registers that overlap with the inputs
6834 ;; (for example, having an input in 7,8 and an output in 6,7). We
6835 ;; also allow for the output being the same as one of the inputs.
6837 (define_insn "*adddi3_noppc64"
6838 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6839 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6840 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6841 "! TARGET_POWERPC64"
6844 if (WORDS_BIG_ENDIAN)
6845 return (GET_CODE (operands[2])) != CONST_INT
6846 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6847 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6849 return (GET_CODE (operands[2])) != CONST_INT
6850 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6851 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6853 [(set_attr "type" "two")
6854 (set_attr "length" "8")])
6856 (define_insn "*subdi3_noppc64"
6857 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6858 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6859 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6860 "! TARGET_POWERPC64"
6863 if (WORDS_BIG_ENDIAN)
6864 return (GET_CODE (operands[1]) != CONST_INT)
6865 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6866 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6868 return (GET_CODE (operands[1]) != CONST_INT)
6869 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6870 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6872 [(set_attr "type" "two")
6873 (set_attr "length" "8")])
6875 (define_insn "*negdi2_noppc64"
6876 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6877 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6878 "! TARGET_POWERPC64"
6881 return (WORDS_BIG_ENDIAN)
6882 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6883 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6885 [(set_attr "type" "two")
6886 (set_attr "length" "8")])
6888 (define_expand "mulsidi3"
6889 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6890 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6891 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6892 "! TARGET_POWERPC64"
6895 if (! TARGET_POWER && ! TARGET_POWERPC)
6897 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6898 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6899 emit_insn (gen_mull_call ());
6900 if (WORDS_BIG_ENDIAN)
6901 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6904 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6905 gen_rtx_REG (SImode, 3));
6906 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6907 gen_rtx_REG (SImode, 4));
6911 else if (TARGET_POWER)
6913 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6918 (define_insn "mulsidi3_mq"
6919 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6920 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6921 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6922 (clobber (match_scratch:SI 3 "=q"))]
6924 "mul %0,%1,%2\;mfmq %L0"
6925 [(set_attr "type" "imul")
6926 (set_attr "length" "8")])
6928 (define_insn "*mulsidi3_no_mq"
6929 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6930 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6931 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6932 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6935 return (WORDS_BIG_ENDIAN)
6936 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6937 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6939 [(set_attr "type" "imul")
6940 (set_attr "length" "8")])
6943 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6945 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6946 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6949 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6950 (sign_extend:DI (match_dup 2)))
6953 (mult:SI (match_dup 1)
6957 int endian = (WORDS_BIG_ENDIAN == 0);
6958 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6959 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6962 (define_expand "umulsidi3"
6963 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6964 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6965 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6966 "TARGET_POWERPC && ! TARGET_POWERPC64"
6971 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6976 (define_insn "umulsidi3_mq"
6977 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6978 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6979 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6980 (clobber (match_scratch:SI 3 "=q"))]
6981 "TARGET_POWERPC && TARGET_POWER"
6984 return (WORDS_BIG_ENDIAN)
6985 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6986 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6988 [(set_attr "type" "imul")
6989 (set_attr "length" "8")])
6991 (define_insn "*umulsidi3_no_mq"
6992 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6993 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6994 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6995 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6998 return (WORDS_BIG_ENDIAN)
6999 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7000 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7002 [(set_attr "type" "imul")
7003 (set_attr "length" "8")])
7006 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7007 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7008 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7009 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7012 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7013 (zero_extend:DI (match_dup 2)))
7016 (mult:SI (match_dup 1)
7020 int endian = (WORDS_BIG_ENDIAN == 0);
7021 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7022 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7025 (define_expand "smulsi3_highpart"
7026 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7028 (lshiftrt:DI (mult:DI (sign_extend:DI
7029 (match_operand:SI 1 "gpc_reg_operand" ""))
7031 (match_operand:SI 2 "gpc_reg_operand" "")))
7036 if (! TARGET_POWER && ! TARGET_POWERPC)
7038 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7039 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7040 emit_insn (gen_mulh_call ());
7041 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7044 else if (TARGET_POWER)
7046 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7051 (define_insn "smulsi3_highpart_mq"
7052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7054 (lshiftrt:DI (mult:DI (sign_extend:DI
7055 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7057 (match_operand:SI 2 "gpc_reg_operand" "r")))
7059 (clobber (match_scratch:SI 3 "=q"))]
7062 [(set_attr "type" "imul")])
7064 (define_insn "*smulsi3_highpart_no_mq"
7065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7067 (lshiftrt:DI (mult:DI (sign_extend:DI
7068 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7070 (match_operand:SI 2 "gpc_reg_operand" "r")))
7072 "TARGET_POWERPC && ! TARGET_POWER"
7074 [(set_attr "type" "imul")])
7076 (define_expand "umulsi3_highpart"
7077 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7079 (lshiftrt:DI (mult:DI (zero_extend:DI
7080 (match_operand:SI 1 "gpc_reg_operand" ""))
7082 (match_operand:SI 2 "gpc_reg_operand" "")))
7089 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7094 (define_insn "umulsi3_highpart_mq"
7095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7097 (lshiftrt:DI (mult:DI (zero_extend:DI
7098 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7100 (match_operand:SI 2 "gpc_reg_operand" "r")))
7102 (clobber (match_scratch:SI 3 "=q"))]
7103 "TARGET_POWERPC && TARGET_POWER"
7105 [(set_attr "type" "imul")])
7107 (define_insn "*umulsi3_highpart_no_mq"
7108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7110 (lshiftrt:DI (mult:DI (zero_extend:DI
7111 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7113 (match_operand:SI 2 "gpc_reg_operand" "r")))
7115 "TARGET_POWERPC && ! TARGET_POWER"
7117 [(set_attr "type" "imul")])
7119 ;; If operands 0 and 2 are in the same register, we have a problem. But
7120 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7121 ;; why we have the strange constraints below.
7122 (define_insn "ashldi3_power"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7124 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7125 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7126 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7129 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7130 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7131 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7132 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7133 [(set_attr "length" "8")])
7135 (define_insn "lshrdi3_power"
7136 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7137 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7138 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7139 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7142 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7143 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7144 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7145 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7146 [(set_attr "length" "8")])
7148 ;; Shift by a variable amount is too complex to be worth open-coding. We
7149 ;; just handle shifts by constants.
7150 (define_insn "ashrdi3_power"
7151 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7152 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7153 (match_operand:SI 2 "const_int_operand" "M,i")))
7154 (clobber (match_scratch:SI 3 "=X,q"))]
7157 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7158 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7159 [(set_attr "type" "shift")
7160 (set_attr "length" "8")])
7162 (define_insn "ashrdi3_no_power"
7163 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7164 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7165 (match_operand:SI 2 "const_int_operand" "M,i")))]
7166 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7168 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7169 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7170 [(set_attr "type" "two,three")
7171 (set_attr "length" "8,12")])
7173 (define_insn "*ashrdisi3_noppc64"
7174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7175 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7176 (const_int 32)) 4))]
7177 "TARGET_32BIT && !TARGET_POWERPC64"
7180 if (REGNO (operands[0]) == REGNO (operands[1]))
7183 return \"mr %0,%1\";
7185 [(set_attr "length" "4")])
7188 ;; PowerPC64 DImode operations.
7190 (define_insn_and_split "absdi2"
7191 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7192 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7193 (clobber (match_scratch:DI 2 "=&r,&r"))]
7196 "&& reload_completed"
7197 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7198 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7199 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7202 (define_insn_and_split "*nabsdi2"
7203 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7204 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7205 (clobber (match_scratch:DI 2 "=&r,&r"))]
7208 "&& reload_completed"
7209 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7210 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7211 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7214 (define_insn "muldi3"
7215 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7216 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7217 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7223 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7224 (const_string "imul3")
7225 (match_operand:SI 2 "short_cint_operand" "")
7226 (const_string "imul2")]
7227 (const_string "lmul")))])
7229 (define_insn "*muldi3_internal1"
7230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7231 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7232 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7234 (clobber (match_scratch:DI 3 "=r,r"))]
7239 [(set_attr "type" "lmul_compare")
7240 (set_attr "length" "4,8")])
7243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7244 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7245 (match_operand:DI 2 "gpc_reg_operand" ""))
7247 (clobber (match_scratch:DI 3 ""))]
7248 "TARGET_POWERPC64 && reload_completed"
7250 (mult:DI (match_dup 1) (match_dup 2)))
7252 (compare:CC (match_dup 3)
7256 (define_insn "*muldi3_internal2"
7257 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7258 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7259 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7261 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7262 (mult:DI (match_dup 1) (match_dup 2)))]
7267 [(set_attr "type" "lmul_compare")
7268 (set_attr "length" "4,8")])
7271 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7272 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7273 (match_operand:DI 2 "gpc_reg_operand" ""))
7275 (set (match_operand:DI 0 "gpc_reg_operand" "")
7276 (mult:DI (match_dup 1) (match_dup 2)))]
7277 "TARGET_POWERPC64 && reload_completed"
7279 (mult:DI (match_dup 1) (match_dup 2)))
7281 (compare:CC (match_dup 0)
7285 (define_insn "smuldi3_highpart"
7286 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7288 (lshiftrt:TI (mult:TI (sign_extend:TI
7289 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7291 (match_operand:DI 2 "gpc_reg_operand" "r")))
7295 [(set_attr "type" "lmul")])
7297 (define_insn "umuldi3_highpart"
7298 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7300 (lshiftrt:TI (mult:TI (zero_extend:TI
7301 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7303 (match_operand:DI 2 "gpc_reg_operand" "r")))
7307 [(set_attr "type" "lmul")])
7309 (define_insn "rotldi3"
7310 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7311 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7312 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7317 [(set_attr "type" "var_shift_rotate,integer")])
7319 (define_insn "*rotldi3_internal2"
7320 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7321 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7322 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7324 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7331 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7332 (set_attr "length" "4,4,8,8")])
7335 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7336 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7337 (match_operand:DI 2 "reg_or_cint_operand" ""))
7339 (clobber (match_scratch:DI 3 ""))]
7340 "TARGET_POWERPC64 && reload_completed"
7342 (rotate:DI (match_dup 1) (match_dup 2)))
7344 (compare:CC (match_dup 3)
7348 (define_insn "*rotldi3_internal3"
7349 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7350 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7351 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7353 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7354 (rotate:DI (match_dup 1) (match_dup 2)))]
7361 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7362 (set_attr "length" "4,4,8,8")])
7365 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7366 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7367 (match_operand:DI 2 "reg_or_cint_operand" ""))
7369 (set (match_operand:DI 0 "gpc_reg_operand" "")
7370 (rotate:DI (match_dup 1) (match_dup 2)))]
7371 "TARGET_POWERPC64 && reload_completed"
7373 (rotate:DI (match_dup 1) (match_dup 2)))
7375 (compare:CC (match_dup 0)
7379 (define_insn "*rotldi3_internal4"
7380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7381 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7382 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7383 (match_operand:DI 3 "mask64_operand" "n,n")))]
7386 rldc%B3 %0,%1,%2,%S3
7387 rldic%B3 %0,%1,%H2,%S3"
7388 [(set_attr "type" "var_shift_rotate,integer")])
7390 (define_insn "*rotldi3_internal5"
7391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7393 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7394 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7395 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7397 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7400 rldc%B3. %4,%1,%2,%S3
7401 rldic%B3. %4,%1,%H2,%S3
7404 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7405 (set_attr "length" "4,4,8,8")])
7408 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7410 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7411 (match_operand:DI 2 "reg_or_cint_operand" ""))
7412 (match_operand:DI 3 "mask64_operand" ""))
7414 (clobber (match_scratch:DI 4 ""))]
7415 "TARGET_POWERPC64 && reload_completed"
7417 (and:DI (rotate:DI (match_dup 1)
7421 (compare:CC (match_dup 4)
7425 (define_insn "*rotldi3_internal6"
7426 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7428 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7429 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7430 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7432 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7433 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7436 rldc%B3. %0,%1,%2,%S3
7437 rldic%B3. %0,%1,%H2,%S3
7440 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7441 (set_attr "length" "4,4,8,8")])
7444 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7446 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7447 (match_operand:DI 2 "reg_or_cint_operand" ""))
7448 (match_operand:DI 3 "mask64_operand" ""))
7450 (set (match_operand:DI 0 "gpc_reg_operand" "")
7451 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7452 "TARGET_POWERPC64 && reload_completed"
7454 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7456 (compare:CC (match_dup 0)
7460 (define_insn "*rotldi3_internal7"
7461 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7464 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7465 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7469 rldicl %0,%1,%H2,56"
7470 [(set_attr "type" "var_shift_rotate,integer")])
7472 (define_insn "*rotldi3_internal8"
7473 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7474 (compare:CC (zero_extend:DI
7476 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7477 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7479 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7483 rldicl. %3,%1,%H2,56
7486 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7487 (set_attr "length" "4,4,8,8")])
7490 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7491 (compare:CC (zero_extend:DI
7493 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7494 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7496 (clobber (match_scratch:DI 3 ""))]
7497 "TARGET_POWERPC64 && reload_completed"
7499 (zero_extend:DI (subreg:QI
7500 (rotate:DI (match_dup 1)
7503 (compare:CC (match_dup 3)
7507 (define_insn "*rotldi3_internal9"
7508 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7509 (compare:CC (zero_extend:DI
7511 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7512 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7514 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7515 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7519 rldicl. %0,%1,%H2,56
7522 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7523 (set_attr "length" "4,4,8,8")])
7526 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7527 (compare:CC (zero_extend:DI
7529 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7530 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7532 (set (match_operand:DI 0 "gpc_reg_operand" "")
7533 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7534 "TARGET_POWERPC64 && reload_completed"
7536 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7538 (compare:CC (match_dup 0)
7542 (define_insn "*rotldi3_internal10"
7543 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7546 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7547 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7551 rldicl %0,%1,%H2,48"
7552 [(set_attr "type" "var_shift_rotate,integer")])
7554 (define_insn "*rotldi3_internal11"
7555 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7556 (compare:CC (zero_extend:DI
7558 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7559 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7561 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7565 rldicl. %3,%1,%H2,48
7568 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7569 (set_attr "length" "4,4,8,8")])
7572 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7573 (compare:CC (zero_extend:DI
7575 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7576 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7578 (clobber (match_scratch:DI 3 ""))]
7579 "TARGET_POWERPC64 && reload_completed"
7581 (zero_extend:DI (subreg:HI
7582 (rotate:DI (match_dup 1)
7585 (compare:CC (match_dup 3)
7589 (define_insn "*rotldi3_internal12"
7590 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7591 (compare:CC (zero_extend:DI
7593 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7594 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7596 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7597 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7601 rldicl. %0,%1,%H2,48
7604 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7605 (set_attr "length" "4,4,8,8")])
7608 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7609 (compare:CC (zero_extend:DI
7611 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7612 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7614 (set (match_operand:DI 0 "gpc_reg_operand" "")
7615 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7616 "TARGET_POWERPC64 && reload_completed"
7618 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7620 (compare:CC (match_dup 0)
7624 (define_insn "*rotldi3_internal13"
7625 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7628 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7629 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7633 rldicl %0,%1,%H2,32"
7634 [(set_attr "type" "var_shift_rotate,integer")])
7636 (define_insn "*rotldi3_internal14"
7637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7638 (compare:CC (zero_extend:DI
7640 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7641 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7643 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7647 rldicl. %3,%1,%H2,32
7650 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7651 (set_attr "length" "4,4,8,8")])
7654 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7655 (compare:CC (zero_extend:DI
7657 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7658 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7660 (clobber (match_scratch:DI 3 ""))]
7661 "TARGET_POWERPC64 && reload_completed"
7663 (zero_extend:DI (subreg:SI
7664 (rotate:DI (match_dup 1)
7667 (compare:CC (match_dup 3)
7671 (define_insn "*rotldi3_internal15"
7672 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7673 (compare:CC (zero_extend:DI
7675 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7676 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7678 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7679 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7683 rldicl. %0,%1,%H2,32
7686 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7687 (set_attr "length" "4,4,8,8")])
7690 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7691 (compare:CC (zero_extend:DI
7693 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7694 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7696 (set (match_operand:DI 0 "gpc_reg_operand" "")
7697 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7698 "TARGET_POWERPC64 && reload_completed"
7700 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7702 (compare:CC (match_dup 0)
7706 (define_expand "ashldi3"
7707 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7708 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7709 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7710 "TARGET_POWERPC64 || TARGET_POWER"
7713 if (TARGET_POWERPC64)
7715 else if (TARGET_POWER)
7717 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7724 (define_insn "*ashldi3_internal1"
7725 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7726 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7727 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7732 [(set_attr "type" "var_shift_rotate,shift")])
7734 (define_insn "*ashldi3_internal2"
7735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7736 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7737 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7739 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7746 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7747 (set_attr "length" "4,4,8,8")])
7750 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7751 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7752 (match_operand:SI 2 "reg_or_cint_operand" ""))
7754 (clobber (match_scratch:DI 3 ""))]
7755 "TARGET_POWERPC64 && reload_completed"
7757 (ashift:DI (match_dup 1) (match_dup 2)))
7759 (compare:CC (match_dup 3)
7763 (define_insn "*ashldi3_internal3"
7764 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7765 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7766 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7768 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7769 (ashift:DI (match_dup 1) (match_dup 2)))]
7776 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7777 (set_attr "length" "4,4,8,8")])
7780 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7781 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7782 (match_operand:SI 2 "reg_or_cint_operand" ""))
7784 (set (match_operand:DI 0 "gpc_reg_operand" "")
7785 (ashift:DI (match_dup 1) (match_dup 2)))]
7786 "TARGET_POWERPC64 && reload_completed"
7788 (ashift:DI (match_dup 1) (match_dup 2)))
7790 (compare:CC (match_dup 0)
7794 (define_insn "*ashldi3_internal4"
7795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7796 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7797 (match_operand:SI 2 "const_int_operand" "i"))
7798 (match_operand:DI 3 "const_int_operand" "n")))]
7799 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7800 "rldic %0,%1,%H2,%W3")
7802 (define_insn "ashldi3_internal5"
7803 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7805 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7806 (match_operand:SI 2 "const_int_operand" "i,i"))
7807 (match_operand:DI 3 "const_int_operand" "n,n"))
7809 (clobber (match_scratch:DI 4 "=r,r"))]
7810 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7812 rldic. %4,%1,%H2,%W3
7814 [(set_attr "type" "compare")
7815 (set_attr "length" "4,8")])
7818 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7820 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7821 (match_operand:SI 2 "const_int_operand" ""))
7822 (match_operand:DI 3 "const_int_operand" ""))
7824 (clobber (match_scratch:DI 4 ""))]
7825 "TARGET_POWERPC64 && reload_completed
7826 && includes_rldic_lshift_p (operands[2], operands[3])"
7828 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7831 (compare:CC (match_dup 4)
7835 (define_insn "*ashldi3_internal6"
7836 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7838 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7839 (match_operand:SI 2 "const_int_operand" "i,i"))
7840 (match_operand:DI 3 "const_int_operand" "n,n"))
7842 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7843 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7844 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7846 rldic. %0,%1,%H2,%W3
7848 [(set_attr "type" "compare")
7849 (set_attr "length" "4,8")])
7852 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7854 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7855 (match_operand:SI 2 "const_int_operand" ""))
7856 (match_operand:DI 3 "const_int_operand" ""))
7858 (set (match_operand:DI 0 "gpc_reg_operand" "")
7859 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7860 "TARGET_POWERPC64 && reload_completed
7861 && includes_rldic_lshift_p (operands[2], operands[3])"
7863 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7866 (compare:CC (match_dup 0)
7870 (define_insn "*ashldi3_internal7"
7871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7872 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7873 (match_operand:SI 2 "const_int_operand" "i"))
7874 (match_operand:DI 3 "mask64_operand" "n")))]
7875 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7876 "rldicr %0,%1,%H2,%S3")
7878 (define_insn "ashldi3_internal8"
7879 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7881 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7882 (match_operand:SI 2 "const_int_operand" "i,i"))
7883 (match_operand:DI 3 "mask64_operand" "n,n"))
7885 (clobber (match_scratch:DI 4 "=r,r"))]
7886 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7888 rldicr. %4,%1,%H2,%S3
7890 [(set_attr "type" "compare")
7891 (set_attr "length" "4,8")])
7894 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7896 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7897 (match_operand:SI 2 "const_int_operand" ""))
7898 (match_operand:DI 3 "mask64_operand" ""))
7900 (clobber (match_scratch:DI 4 ""))]
7901 "TARGET_POWERPC64 && reload_completed
7902 && includes_rldicr_lshift_p (operands[2], operands[3])"
7904 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7907 (compare:CC (match_dup 4)
7911 (define_insn "*ashldi3_internal9"
7912 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7914 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7915 (match_operand:SI 2 "const_int_operand" "i,i"))
7916 (match_operand:DI 3 "mask64_operand" "n,n"))
7918 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7919 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7920 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7922 rldicr. %0,%1,%H2,%S3
7924 [(set_attr "type" "compare")
7925 (set_attr "length" "4,8")])
7928 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7930 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7931 (match_operand:SI 2 "const_int_operand" ""))
7932 (match_operand:DI 3 "mask64_operand" ""))
7934 (set (match_operand:DI 0 "gpc_reg_operand" "")
7935 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7936 "TARGET_POWERPC64 && reload_completed
7937 && includes_rldicr_lshift_p (operands[2], operands[3])"
7939 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7942 (compare:CC (match_dup 0)
7946 (define_expand "lshrdi3"
7947 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7948 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7949 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7950 "TARGET_POWERPC64 || TARGET_POWER"
7953 if (TARGET_POWERPC64)
7955 else if (TARGET_POWER)
7957 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7964 (define_insn "*lshrdi3_internal1"
7965 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7966 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7967 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7972 [(set_attr "type" "var_shift_rotate,shift")])
7974 (define_insn "*lshrdi3_internal2"
7975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7976 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7977 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7979 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7986 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7987 (set_attr "length" "4,4,8,8")])
7990 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7991 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7992 (match_operand:SI 2 "reg_or_cint_operand" ""))
7994 (clobber (match_scratch:DI 3 ""))]
7995 "TARGET_POWERPC64 && reload_completed"
7997 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7999 (compare:CC (match_dup 3)
8003 (define_insn "*lshrdi3_internal3"
8004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8005 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8006 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8008 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8009 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8016 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8017 (set_attr "length" "4,4,8,8")])
8020 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8021 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8022 (match_operand:SI 2 "reg_or_cint_operand" ""))
8024 (set (match_operand:DI 0 "gpc_reg_operand" "")
8025 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8026 "TARGET_POWERPC64 && reload_completed"
8028 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8030 (compare:CC (match_dup 0)
8034 (define_expand "ashrdi3"
8035 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8036 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8037 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8041 if (TARGET_POWERPC64)
8043 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8045 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8048 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8049 && WORDS_BIG_ENDIAN)
8051 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8058 (define_insn "*ashrdi3_internal1"
8059 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8060 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8061 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8066 [(set_attr "type" "var_shift_rotate,shift")])
8068 (define_insn "*ashrdi3_internal2"
8069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8070 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8071 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8073 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8080 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8081 (set_attr "length" "4,4,8,8")])
8084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8085 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8086 (match_operand:SI 2 "reg_or_cint_operand" ""))
8088 (clobber (match_scratch:DI 3 ""))]
8089 "TARGET_POWERPC64 && reload_completed"
8091 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8093 (compare:CC (match_dup 3)
8097 (define_insn "*ashrdi3_internal3"
8098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8099 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8100 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8102 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8103 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8110 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8111 (set_attr "length" "4,4,8,8")])
8114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8115 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8116 (match_operand:SI 2 "reg_or_cint_operand" ""))
8118 (set (match_operand:DI 0 "gpc_reg_operand" "")
8119 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8120 "TARGET_POWERPC64 && reload_completed"
8122 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8124 (compare:CC (match_dup 0)
8128 (define_expand "anddi3"
8130 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8131 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8132 (match_operand:DI 2 "and64_2_operand" "")))
8133 (clobber (match_scratch:CC 3 ""))])]
8137 (define_insn "anddi3_mc"
8138 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8139 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8140 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8141 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8142 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8145 rldic%B2 %0,%1,0,%S2
8146 rlwinm %0,%1,0,%m2,%M2
8150 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8151 (set_attr "length" "4,4,4,4,4,8")])
8153 (define_insn "anddi3_nomc"
8154 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8155 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8156 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8157 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8158 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8161 rldic%B2 %0,%1,0,%S2
8162 rlwinm %0,%1,0,%m2,%M2
8164 [(set_attr "length" "4,4,4,8")])
8167 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8168 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8169 (match_operand:DI 2 "mask64_2_operand" "")))
8170 (clobber (match_scratch:CC 3 ""))]
8172 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8173 && !mask_operand (operands[2], DImode)
8174 && !mask64_operand (operands[2], DImode)"
8176 (and:DI (rotate:DI (match_dup 1)
8180 (and:DI (rotate:DI (match_dup 0)
8184 build_mask64_2_operands (operands[2], &operands[4]);
8187 (define_insn "*anddi3_internal2_mc"
8188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8189 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8190 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8192 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8193 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8194 "TARGET_64BIT && rs6000_gen_cell_microcode"
8197 rldic%B2. %3,%1,0,%S2
8198 rlwinm. %3,%1,0,%m2,%M2
8208 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8209 fast_compare,compare,compare,compare,compare,compare,\
8211 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8214 [(set (match_operand:CC 0 "cc_reg_operand" "")
8215 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8216 (match_operand:DI 2 "mask64_2_operand" ""))
8218 (clobber (match_scratch:DI 3 ""))
8219 (clobber (match_scratch:CC 4 ""))]
8220 "TARGET_64BIT && reload_completed
8221 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8222 && !mask_operand (operands[2], DImode)
8223 && !mask64_operand (operands[2], DImode)"
8225 (and:DI (rotate:DI (match_dup 1)
8228 (parallel [(set (match_dup 0)
8229 (compare:CC (and:DI (rotate:DI (match_dup 3)
8233 (clobber (match_dup 3))])]
8236 build_mask64_2_operands (operands[2], &operands[5]);
8239 (define_insn "*anddi3_internal3_mc"
8240 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8241 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8242 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8244 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8245 (and:DI (match_dup 1) (match_dup 2)))
8246 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8247 "TARGET_64BIT && rs6000_gen_cell_microcode"
8250 rldic%B2. %0,%1,0,%S2
8251 rlwinm. %0,%1,0,%m2,%M2
8261 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8262 fast_compare,compare,compare,compare,compare,compare,\
8264 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8267 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8268 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8269 (match_operand:DI 2 "and64_2_operand" ""))
8271 (set (match_operand:DI 0 "gpc_reg_operand" "")
8272 (and:DI (match_dup 1) (match_dup 2)))
8273 (clobber (match_scratch:CC 4 ""))]
8274 "TARGET_64BIT && reload_completed"
8275 [(parallel [(set (match_dup 0)
8276 (and:DI (match_dup 1) (match_dup 2)))
8277 (clobber (match_dup 4))])
8279 (compare:CC (match_dup 0)
8284 [(set (match_operand:CC 3 "cc_reg_operand" "")
8285 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8286 (match_operand:DI 2 "mask64_2_operand" ""))
8288 (set (match_operand:DI 0 "gpc_reg_operand" "")
8289 (and:DI (match_dup 1) (match_dup 2)))
8290 (clobber (match_scratch:CC 4 ""))]
8291 "TARGET_64BIT && reload_completed
8292 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8293 && !mask_operand (operands[2], DImode)
8294 && !mask64_operand (operands[2], DImode)"
8296 (and:DI (rotate:DI (match_dup 1)
8299 (parallel [(set (match_dup 3)
8300 (compare:CC (and:DI (rotate:DI (match_dup 0)
8305 (and:DI (rotate:DI (match_dup 0)
8310 build_mask64_2_operands (operands[2], &operands[5]);
8313 (define_expand "iordi3"
8314 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8315 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8316 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8320 if (non_logical_cint_operand (operands[2], DImode))
8322 HOST_WIDE_INT value;
8323 rtx tmp = ((!can_create_pseudo_p ()
8324 || rtx_equal_p (operands[0], operands[1]))
8325 ? operands[0] : gen_reg_rtx (DImode));
8327 if (GET_CODE (operands[2]) == CONST_INT)
8329 value = INTVAL (operands[2]);
8330 emit_insn (gen_iordi3 (tmp, operands[1],
8331 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8335 value = CONST_DOUBLE_LOW (operands[2]);
8336 emit_insn (gen_iordi3 (tmp, operands[1],
8337 immed_double_const (value
8338 & (~ (HOST_WIDE_INT) 0xffff),
8342 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8347 (define_expand "xordi3"
8348 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8349 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8350 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8354 if (non_logical_cint_operand (operands[2], DImode))
8356 HOST_WIDE_INT value;
8357 rtx tmp = ((!can_create_pseudo_p ()
8358 || rtx_equal_p (operands[0], operands[1]))
8359 ? operands[0] : gen_reg_rtx (DImode));
8361 if (GET_CODE (operands[2]) == CONST_INT)
8363 value = INTVAL (operands[2]);
8364 emit_insn (gen_xordi3 (tmp, operands[1],
8365 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8369 value = CONST_DOUBLE_LOW (operands[2]);
8370 emit_insn (gen_xordi3 (tmp, operands[1],
8371 immed_double_const (value
8372 & (~ (HOST_WIDE_INT) 0xffff),
8376 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8381 (define_insn "*booldi3_internal1"
8382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8383 (match_operator:DI 3 "boolean_or_operator"
8384 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8385 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8392 (define_insn "*booldi3_internal2"
8393 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8394 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8395 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8396 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8398 (clobber (match_scratch:DI 3 "=r,r"))]
8403 [(set_attr "type" "fast_compare,compare")
8404 (set_attr "length" "4,8")])
8407 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8408 (compare:CC (match_operator:DI 4 "boolean_operator"
8409 [(match_operand:DI 1 "gpc_reg_operand" "")
8410 (match_operand:DI 2 "gpc_reg_operand" "")])
8412 (clobber (match_scratch:DI 3 ""))]
8413 "TARGET_POWERPC64 && reload_completed"
8414 [(set (match_dup 3) (match_dup 4))
8416 (compare:CC (match_dup 3)
8420 (define_insn "*booldi3_internal3"
8421 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8422 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8423 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8424 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8426 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8432 [(set_attr "type" "fast_compare,compare")
8433 (set_attr "length" "4,8")])
8436 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8437 (compare:CC (match_operator:DI 4 "boolean_operator"
8438 [(match_operand:DI 1 "gpc_reg_operand" "")
8439 (match_operand:DI 2 "gpc_reg_operand" "")])
8441 (set (match_operand:DI 0 "gpc_reg_operand" "")
8443 "TARGET_POWERPC64 && reload_completed"
8444 [(set (match_dup 0) (match_dup 4))
8446 (compare:CC (match_dup 0)
8450 ;; Split a logical operation that we can't do in one insn into two insns,
8451 ;; each of which does one 16-bit part. This is used by combine.
8454 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8455 (match_operator:DI 3 "boolean_or_operator"
8456 [(match_operand:DI 1 "gpc_reg_operand" "")
8457 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8459 [(set (match_dup 0) (match_dup 4))
8460 (set (match_dup 0) (match_dup 5))]
8465 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8467 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8468 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8470 i4 = GEN_INT (value & 0xffff);
8474 i3 = GEN_INT (INTVAL (operands[2])
8475 & (~ (HOST_WIDE_INT) 0xffff));
8476 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8478 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8480 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8484 (define_insn "*boolcdi3_internal1"
8485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8486 (match_operator:DI 3 "boolean_operator"
8487 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8488 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8492 (define_insn "*boolcdi3_internal2"
8493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8494 (compare:CC (match_operator:DI 4 "boolean_operator"
8495 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8496 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8498 (clobber (match_scratch:DI 3 "=r,r"))]
8503 [(set_attr "type" "fast_compare,compare")
8504 (set_attr "length" "4,8")])
8507 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8508 (compare:CC (match_operator:DI 4 "boolean_operator"
8509 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8510 (match_operand:DI 2 "gpc_reg_operand" "")])
8512 (clobber (match_scratch:DI 3 ""))]
8513 "TARGET_POWERPC64 && reload_completed"
8514 [(set (match_dup 3) (match_dup 4))
8516 (compare:CC (match_dup 3)
8520 (define_insn "*boolcdi3_internal3"
8521 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8522 (compare:CC (match_operator:DI 4 "boolean_operator"
8523 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8524 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8526 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8532 [(set_attr "type" "fast_compare,compare")
8533 (set_attr "length" "4,8")])
8536 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8537 (compare:CC (match_operator:DI 4 "boolean_operator"
8538 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8539 (match_operand:DI 2 "gpc_reg_operand" "")])
8541 (set (match_operand:DI 0 "gpc_reg_operand" "")
8543 "TARGET_POWERPC64 && reload_completed"
8544 [(set (match_dup 0) (match_dup 4))
8546 (compare:CC (match_dup 0)
8550 (define_insn "*boolccdi3_internal1"
8551 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8552 (match_operator:DI 3 "boolean_operator"
8553 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8554 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8558 (define_insn "*boolccdi3_internal2"
8559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8560 (compare:CC (match_operator:DI 4 "boolean_operator"
8561 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8562 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8564 (clobber (match_scratch:DI 3 "=r,r"))]
8569 [(set_attr "type" "fast_compare,compare")
8570 (set_attr "length" "4,8")])
8573 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8574 (compare:CC (match_operator:DI 4 "boolean_operator"
8575 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8576 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8578 (clobber (match_scratch:DI 3 ""))]
8579 "TARGET_POWERPC64 && reload_completed"
8580 [(set (match_dup 3) (match_dup 4))
8582 (compare:CC (match_dup 3)
8586 (define_insn "*boolccdi3_internal3"
8587 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8588 (compare:CC (match_operator:DI 4 "boolean_operator"
8589 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8590 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8592 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8598 [(set_attr "type" "fast_compare,compare")
8599 (set_attr "length" "4,8")])
8602 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8603 (compare:CC (match_operator:DI 4 "boolean_operator"
8604 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8605 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8607 (set (match_operand:DI 0 "gpc_reg_operand" "")
8609 "TARGET_POWERPC64 && reload_completed"
8610 [(set (match_dup 0) (match_dup 4))
8612 (compare:CC (match_dup 0)
8616 (define_expand "smindi3"
8617 [(match_operand:DI 0 "gpc_reg_operand" "")
8618 (match_operand:DI 1 "gpc_reg_operand" "")
8619 (match_operand:DI 2 "gpc_reg_operand" "")]
8623 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8627 (define_expand "smaxdi3"
8628 [(match_operand:DI 0 "gpc_reg_operand" "")
8629 (match_operand:DI 1 "gpc_reg_operand" "")
8630 (match_operand:DI 2 "gpc_reg_operand" "")]
8634 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8638 (define_expand "umindi3"
8639 [(match_operand:DI 0 "gpc_reg_operand" "")
8640 (match_operand:DI 1 "gpc_reg_operand" "")
8641 (match_operand:DI 2 "gpc_reg_operand" "")]
8645 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8649 (define_expand "umaxdi3"
8650 [(match_operand:DI 0 "gpc_reg_operand" "")
8651 (match_operand:DI 1 "gpc_reg_operand" "")
8652 (match_operand:DI 2 "gpc_reg_operand" "")]
8656 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8661 ;; Now define ways of moving data around.
8663 ;; Set up a register with a value from the GOT table
8665 (define_expand "movsi_got"
8666 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8667 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8668 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8669 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8672 if (GET_CODE (operands[1]) == CONST)
8674 rtx offset = const0_rtx;
8675 HOST_WIDE_INT value;
8677 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8678 value = INTVAL (offset);
8681 rtx tmp = (!can_create_pseudo_p ()
8683 : gen_reg_rtx (Pmode));
8684 emit_insn (gen_movsi_got (tmp, operands[1]));
8685 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8690 operands[2] = rs6000_got_register (operands[1]);
8693 (define_insn "*movsi_got_internal"
8694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8695 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8696 (match_operand:SI 2 "gpc_reg_operand" "b")]
8698 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8699 "{l|lwz} %0,%a1@got(%2)"
8700 [(set_attr "type" "load")])
8702 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8703 ;; didn't get allocated to a hard register.
8705 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8706 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8707 (match_operand:SI 2 "memory_operand" "")]
8709 "DEFAULT_ABI == ABI_V4
8711 && (reload_in_progress || reload_completed)"
8712 [(set (match_dup 0) (match_dup 2))
8713 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8717 ;; For SI, we special-case integers that can't be loaded in one insn. We
8718 ;; do the load 16-bits at a time. We could do this by loading from memory,
8719 ;; and this is even supposed to be faster, but it is simpler not to get
8720 ;; integers in the TOC.
8721 (define_insn "movsi_low"
8722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8723 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8724 (match_operand 2 "" ""))))]
8725 "TARGET_MACHO && ! TARGET_64BIT"
8726 "{l|lwz} %0,lo16(%2)(%1)"
8727 [(set_attr "type" "load")
8728 (set_attr "length" "4")])
8730 (define_insn "*movsi_internal1"
8731 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8732 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8733 "!TARGET_SINGLE_FPU &&
8734 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8738 {l%U1%X1|lwz%U1%X1} %0,%1
8739 {st%U0%X0|stw%U0%X0} %1,%0
8749 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8750 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8752 (define_insn "*movsi_internal1_single"
8753 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8754 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8755 "TARGET_SINGLE_FPU &&
8756 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8760 {l%U1%X1|lwz%U1%X1} %0,%1
8761 {st%U0%X0|stw%U0%X0} %1,%0
8773 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8774 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8776 ;; Split a load of a large constant into the appropriate two-insn
8780 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8781 (match_operand:SI 1 "const_int_operand" ""))]
8782 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8783 && (INTVAL (operands[1]) & 0xffff) != 0"
8787 (ior:SI (match_dup 0)
8790 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8792 if (tem == operands[0])
8798 (define_insn "*mov<mode>_internal2"
8799 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8800 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8802 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8805 {cmpi|cmp<wd>i} %2,%0,0
8808 [(set_attr "type" "cmp,compare,cmp")
8809 (set_attr "length" "4,4,8")])
8812 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8813 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8815 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8817 [(set (match_dup 0) (match_dup 1))
8819 (compare:CC (match_dup 0)
8823 (define_insn "*movhi_internal"
8824 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8825 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8826 "gpc_reg_operand (operands[0], HImode)
8827 || gpc_reg_operand (operands[1], HImode)"
8837 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8839 (define_expand "mov<mode>"
8840 [(set (match_operand:INT 0 "general_operand" "")
8841 (match_operand:INT 1 "any_operand" ""))]
8843 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8845 (define_insn "*movqi_internal"
8846 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8847 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8848 "gpc_reg_operand (operands[0], QImode)
8849 || gpc_reg_operand (operands[1], QImode)"
8859 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8861 ;; Here is how to move condition codes around. When we store CC data in
8862 ;; an integer register or memory, we store just the high-order 4 bits.
8863 ;; This lets us not shift in the most common case of CR0.
8864 (define_expand "movcc"
8865 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8866 (match_operand:CC 1 "nonimmediate_operand" ""))]
8870 (define_insn "*movcc_internal1"
8871 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8872 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8873 "register_operand (operands[0], CCmode)
8874 || register_operand (operands[1], CCmode)"
8878 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8881 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8887 {l%U1%X1|lwz%U1%X1} %0,%1
8888 {st%U0%U1|stw%U0%U1} %1,%0"
8890 (cond [(eq_attr "alternative" "0,3")
8891 (const_string "cr_logical")
8892 (eq_attr "alternative" "1,2")
8893 (const_string "mtcr")
8894 (eq_attr "alternative" "6,7,9")
8895 (const_string "integer")
8896 (eq_attr "alternative" "8")
8897 (const_string "mfjmpr")
8898 (eq_attr "alternative" "10")
8899 (const_string "mtjmpr")
8900 (eq_attr "alternative" "11")
8901 (const_string "load")
8902 (eq_attr "alternative" "12")
8903 (const_string "store")
8904 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8905 (const_string "mfcrf")
8907 (const_string "mfcr")))
8908 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8910 ;; For floating-point, we normally deal with the floating-point registers
8911 ;; unless -msoft-float is used. The sole exception is that parameter passing
8912 ;; can produce floating-point values in fixed-point registers. Unless the
8913 ;; value is a simple constant or already in memory, we deal with this by
8914 ;; allocating memory and copying the value explicitly via that memory location.
8915 (define_expand "movsf"
8916 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8917 (match_operand:SF 1 "any_operand" ""))]
8919 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8922 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8923 (match_operand:SF 1 "const_double_operand" ""))]
8925 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8926 || (GET_CODE (operands[0]) == SUBREG
8927 && GET_CODE (SUBREG_REG (operands[0])) == REG
8928 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8929 [(set (match_dup 2) (match_dup 3))]
8935 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8936 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8938 if (! TARGET_POWERPC64)
8939 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8941 operands[2] = gen_lowpart (SImode, operands[0]);
8943 operands[3] = gen_int_mode (l, SImode);
8946 (define_insn "*movsf_hardfloat"
8947 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8948 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8949 "(gpc_reg_operand (operands[0], SFmode)
8950 || gpc_reg_operand (operands[1], SFmode))
8951 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8954 {l%U1%X1|lwz%U1%X1} %0,%1
8955 {st%U0%X0|stw%U0%X0} %1,%0
8965 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8966 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8968 (define_insn "*movsf_softfloat"
8969 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8970 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8971 "(gpc_reg_operand (operands[0], SFmode)
8972 || gpc_reg_operand (operands[1], SFmode))
8973 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8979 {l%U1%X1|lwz%U1%X1} %0,%1
8980 {st%U0%X0|stw%U0%X0} %1,%0
8987 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8988 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8991 (define_expand "movdf"
8992 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8993 (match_operand:DF 1 "any_operand" ""))]
8995 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8998 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8999 (match_operand:DF 1 "const_int_operand" ""))]
9000 "! TARGET_POWERPC64 && reload_completed
9001 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9002 || (GET_CODE (operands[0]) == SUBREG
9003 && GET_CODE (SUBREG_REG (operands[0])) == REG
9004 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9005 [(set (match_dup 2) (match_dup 4))
9006 (set (match_dup 3) (match_dup 1))]
9009 int endian = (WORDS_BIG_ENDIAN == 0);
9010 HOST_WIDE_INT value = INTVAL (operands[1]);
9012 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9013 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9014 #if HOST_BITS_PER_WIDE_INT == 32
9015 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9017 operands[4] = GEN_INT (value >> 32);
9018 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9023 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9024 (match_operand:DF 1 "const_double_operand" ""))]
9025 "! TARGET_POWERPC64 && reload_completed
9026 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9027 || (GET_CODE (operands[0]) == SUBREG
9028 && GET_CODE (SUBREG_REG (operands[0])) == REG
9029 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9030 [(set (match_dup 2) (match_dup 4))
9031 (set (match_dup 3) (match_dup 5))]
9034 int endian = (WORDS_BIG_ENDIAN == 0);
9038 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9039 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9041 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9042 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9043 operands[4] = gen_int_mode (l[endian], SImode);
9044 operands[5] = gen_int_mode (l[1 - endian], SImode);
9048 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9049 (match_operand:DF 1 "const_double_operand" ""))]
9050 "TARGET_POWERPC64 && reload_completed
9051 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9052 || (GET_CODE (operands[0]) == SUBREG
9053 && GET_CODE (SUBREG_REG (operands[0])) == REG
9054 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9055 [(set (match_dup 2) (match_dup 3))]
9058 int endian = (WORDS_BIG_ENDIAN == 0);
9061 #if HOST_BITS_PER_WIDE_INT >= 64
9065 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9066 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9068 operands[2] = gen_lowpart (DImode, operands[0]);
9069 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9070 #if HOST_BITS_PER_WIDE_INT >= 64
9071 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9072 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9074 operands[3] = gen_int_mode (val, DImode);
9076 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9080 ;; Don't have reload use general registers to load a constant. First,
9081 ;; it might not work if the output operand is the equivalent of
9082 ;; a non-offsettable memref, but also it is less efficient than loading
9083 ;; the constant into an FP register, since it will probably be used there.
9084 ;; The "??" is a kludge until we can figure out a more reasonable way
9085 ;; of handling these non-offsettable values.
9086 (define_insn "*movdf_hardfloat32"
9087 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9088 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9089 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9090 && (gpc_reg_operand (operands[0], DFmode)
9091 || gpc_reg_operand (operands[1], DFmode))"
9094 switch (which_alternative)
9099 /* We normally copy the low-numbered register first. However, if
9100 the first register operand 0 is the same as the second register
9101 of operand 1, we must copy in the opposite order. */
9102 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9103 return \"mr %L0,%L1\;mr %0,%1\";
9105 return \"mr %0,%1\;mr %L0,%L1\";
9107 if (rs6000_offsettable_memref_p (operands[1])
9108 || (GET_CODE (operands[1]) == MEM
9109 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
9110 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
9111 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
9112 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
9114 /* If the low-address word is used in the address, we must load
9115 it last. Otherwise, load it first. Note that we cannot have
9116 auto-increment in that case since the address register is
9117 known to be dead. */
9118 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9120 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9122 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
9128 addreg = find_addr_reg (XEXP (operands[1], 0));
9129 if (refers_to_regno_p (REGNO (operands[0]),
9130 REGNO (operands[0]) + 1,
9133 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9134 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9135 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9136 return \"{l%X1|lwz%X1} %0,%1\";
9140 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
9141 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9142 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9143 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9148 if (rs6000_offsettable_memref_p (operands[0])
9149 || (GET_CODE (operands[0]) == MEM
9150 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
9151 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
9152 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
9153 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
9154 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9159 addreg = find_addr_reg (XEXP (operands[0], 0));
9160 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
9161 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9162 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
9163 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9168 return \"xxlor %x0,%x1,%x1\";
9171 return \"lxsd%U1x %x0,%y1\";
9174 return \"stxsd%U0x %x1,%y0\";
9176 return \"fmr %0,%1\";
9178 return \"lfd%U1%X1 %0,%1\";
9180 return \"stfd%U0%X0 %1,%0\";
9182 return \"xxlxor %x0,%x0,%x0\";
9189 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9190 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9192 (define_insn "*movdf_softfloat32"
9193 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9194 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9196 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9197 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9198 && (gpc_reg_operand (operands[0], DFmode)
9199 || gpc_reg_operand (operands[1], DFmode))"
9202 switch (which_alternative)
9207 /* We normally copy the low-numbered register first. However, if
9208 the first register operand 0 is the same as the second register of
9209 operand 1, we must copy in the opposite order. */
9210 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9211 return \"mr %L0,%L1\;mr %0,%1\";
9213 return \"mr %0,%1\;mr %L0,%L1\";
9215 /* If the low-address word is used in the address, we must load
9216 it last. Otherwise, load it first. Note that we cannot have
9217 auto-increment in that case since the address register is
9218 known to be dead. */
9219 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9221 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9223 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
9225 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9232 [(set_attr "type" "two,load,store,*,*,*")
9233 (set_attr "length" "8,8,8,8,12,16")])
9235 ; ld/std require word-aligned displacements -> 'Y' constraint.
9236 ; List Y->r and r->Y before r->r for reload.
9237 (define_insn "*movdf_hardfloat64_mfpgpr"
9238 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9239 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9240 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9241 && TARGET_DOUBLE_FLOAT
9242 && (gpc_reg_operand (operands[0], DFmode)
9243 || gpc_reg_operand (operands[1], DFmode))"
9266 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9267 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9269 ; ld/std require word-aligned displacements -> 'Y' constraint.
9270 ; List Y->r and r->Y before r->r for reload.
9271 (define_insn "*movdf_hardfloat64"
9272 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9273 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9274 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9275 && TARGET_DOUBLE_FLOAT
9276 && (gpc_reg_operand (operands[0], DFmode)
9277 || gpc_reg_operand (operands[1], DFmode))"
9298 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9299 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9301 (define_insn "*movdf_softfloat64"
9302 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9303 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9304 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9305 && (gpc_reg_operand (operands[0], DFmode)
9306 || gpc_reg_operand (operands[1], DFmode))"
9317 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9318 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9320 (define_expand "movtf"
9321 [(set (match_operand:TF 0 "general_operand" "")
9322 (match_operand:TF 1 "any_operand" ""))]
9323 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9324 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9326 ; It's important to list the o->f and f->o moves before f->f because
9327 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9328 ; which doesn't make progress. Likewise r->Y must be before r->r.
9329 (define_insn_and_split "*movtf_internal"
9330 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9331 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9333 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9334 && (gpc_reg_operand (operands[0], TFmode)
9335 || gpc_reg_operand (operands[1], TFmode))"
9337 "&& reload_completed"
9339 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9340 [(set_attr "length" "8,8,8,20,20,16")])
9342 (define_insn_and_split "*movtf_softfloat"
9343 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9344 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9346 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9347 && (gpc_reg_operand (operands[0], TFmode)
9348 || gpc_reg_operand (operands[1], TFmode))"
9350 "&& reload_completed"
9352 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9353 [(set_attr "length" "20,20,16")])
9355 (define_expand "extenddftf2"
9356 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9357 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9359 && TARGET_HARD_FLOAT
9360 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9361 && TARGET_LONG_DOUBLE_128"
9363 if (TARGET_E500_DOUBLE)
9364 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9366 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9370 (define_expand "extenddftf2_fprs"
9371 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9372 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9373 (use (match_dup 2))])]
9375 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9376 && TARGET_LONG_DOUBLE_128"
9378 operands[2] = CONST0_RTX (DFmode);
9379 /* Generate GOT reference early for SVR4 PIC. */
9380 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9381 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9384 (define_insn_and_split "*extenddftf2_internal"
9385 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9386 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9387 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9389 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9390 && TARGET_LONG_DOUBLE_128"
9392 "&& reload_completed"
9395 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9396 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9397 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9399 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9404 (define_expand "extendsftf2"
9405 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9406 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9408 && TARGET_HARD_FLOAT
9409 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9410 && TARGET_LONG_DOUBLE_128"
9412 rtx tmp = gen_reg_rtx (DFmode);
9413 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9414 emit_insn (gen_extenddftf2 (operands[0], tmp));
9418 (define_expand "trunctfdf2"
9419 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9420 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9422 && TARGET_HARD_FLOAT
9423 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9424 && TARGET_LONG_DOUBLE_128"
9427 (define_insn_and_split "trunctfdf2_internal1"
9428 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9429 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9430 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9431 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9435 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9438 emit_note (NOTE_INSN_DELETED);
9441 [(set_attr "type" "fp")])
9443 (define_insn "trunctfdf2_internal2"
9444 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9445 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9446 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9447 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9448 && TARGET_LONG_DOUBLE_128"
9450 [(set_attr "type" "fp")
9451 (set_attr "fp_type" "fp_addsub_d")])
9453 (define_expand "trunctfsf2"
9454 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9455 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9457 && TARGET_HARD_FLOAT
9458 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9459 && TARGET_LONG_DOUBLE_128"
9461 if (TARGET_E500_DOUBLE)
9462 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9464 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9468 (define_insn_and_split "trunctfsf2_fprs"
9469 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9470 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9471 (clobber (match_scratch:DF 2 "=d"))]
9473 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9474 && TARGET_LONG_DOUBLE_128"
9476 "&& reload_completed"
9478 (float_truncate:DF (match_dup 1)))
9480 (float_truncate:SF (match_dup 2)))]
9483 (define_expand "floatsitf2"
9484 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9485 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9487 && TARGET_HARD_FLOAT
9488 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9489 && TARGET_LONG_DOUBLE_128"
9491 rtx tmp = gen_reg_rtx (DFmode);
9492 expand_float (tmp, operands[1], false);
9493 emit_insn (gen_extenddftf2 (operands[0], tmp));
9497 ; fadd, but rounding towards zero.
9498 ; This is probably not the optimal code sequence.
9499 (define_insn "fix_trunc_helper"
9500 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9501 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9502 UNSPEC_FIX_TRUNC_TF))
9503 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9504 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9505 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9506 [(set_attr "type" "fp")
9507 (set_attr "length" "20")])
9509 (define_expand "fix_trunctfsi2"
9510 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9511 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9513 && (TARGET_POWER2 || TARGET_POWERPC)
9514 && TARGET_HARD_FLOAT
9515 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9516 && TARGET_LONG_DOUBLE_128"
9518 if (TARGET_E500_DOUBLE)
9519 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9521 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9525 (define_expand "fix_trunctfsi2_fprs"
9526 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9527 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9528 (clobber (match_dup 2))
9529 (clobber (match_dup 3))
9530 (clobber (match_dup 4))
9531 (clobber (match_dup 5))])]
9533 && (TARGET_POWER2 || TARGET_POWERPC)
9534 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9536 operands[2] = gen_reg_rtx (DFmode);
9537 operands[3] = gen_reg_rtx (DFmode);
9538 operands[4] = gen_reg_rtx (DImode);
9539 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9542 (define_insn_and_split "*fix_trunctfsi2_internal"
9543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9544 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9545 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9546 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9547 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9548 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9550 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9556 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9558 gcc_assert (MEM_P (operands[5]));
9559 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9561 emit_insn (gen_fctiwz (operands[4], operands[2]));
9562 emit_move_insn (operands[5], operands[4]);
9563 emit_move_insn (operands[0], lowword);
9567 (define_expand "negtf2"
9568 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9569 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9571 && TARGET_HARD_FLOAT
9572 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9573 && TARGET_LONG_DOUBLE_128"
9576 (define_insn "negtf2_internal"
9577 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9578 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9580 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9583 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9584 return \"fneg %L0,%L1\;fneg %0,%1\";
9586 return \"fneg %0,%1\;fneg %L0,%L1\";
9588 [(set_attr "type" "fp")
9589 (set_attr "length" "8")])
9591 (define_expand "abstf2"
9592 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9593 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9595 && TARGET_HARD_FLOAT
9596 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9597 && TARGET_LONG_DOUBLE_128"
9600 rtx label = gen_label_rtx ();
9601 if (TARGET_E500_DOUBLE)
9603 if (flag_finite_math_only && !flag_trapping_math)
9604 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9606 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9609 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9614 (define_expand "abstf2_internal"
9615 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9616 (match_operand:TF 1 "gpc_reg_operand" ""))
9617 (set (match_dup 3) (match_dup 5))
9618 (set (match_dup 5) (abs:DF (match_dup 5)))
9619 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9620 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9621 (label_ref (match_operand 2 "" ""))
9623 (set (match_dup 6) (neg:DF (match_dup 6)))]
9625 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9626 && TARGET_LONG_DOUBLE_128"
9629 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9630 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9631 operands[3] = gen_reg_rtx (DFmode);
9632 operands[4] = gen_reg_rtx (CCFPmode);
9633 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9634 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9637 ;; Next come the multi-word integer load and store and the load and store
9640 ; List r->r after r->"o<>", otherwise reload will try to reload a
9641 ; non-offsettable address by using r->r which won't make progress.
9642 (define_insn "*movdi_internal32"
9643 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9644 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9646 && (gpc_reg_operand (operands[0], DImode)
9647 || gpc_reg_operand (operands[1], DImode))"
9656 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9659 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9660 (match_operand:DI 1 "const_int_operand" ""))]
9661 "! TARGET_POWERPC64 && reload_completed"
9662 [(set (match_dup 2) (match_dup 4))
9663 (set (match_dup 3) (match_dup 1))]
9666 HOST_WIDE_INT value = INTVAL (operands[1]);
9667 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9669 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9671 #if HOST_BITS_PER_WIDE_INT == 32
9672 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9674 operands[4] = GEN_INT (value >> 32);
9675 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9680 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
9681 (match_operand:DI 1 "input_operand" ""))]
9682 "reload_completed && !TARGET_POWERPC64
9683 && gpr_or_gpr_p (operands[0], operands[1])"
9685 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9687 (define_insn "*movdi_mfpgpr"
9688 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9689 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9690 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9691 && (gpc_reg_operand (operands[0], DImode)
9692 || gpc_reg_operand (operands[1], DImode))"
9709 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9710 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9712 (define_insn "*movdi_internal64"
9713 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9714 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9715 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9716 && (gpc_reg_operand (operands[0], DImode)
9717 || gpc_reg_operand (operands[1], DImode))"
9732 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9733 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9735 ;; immediate value valid for a single instruction hiding in a const_double
9737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9738 (match_operand:DI 1 "const_double_operand" "F"))]
9739 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9740 && GET_CODE (operands[1]) == CONST_DOUBLE
9741 && num_insns_constant (operands[1], DImode) == 1"
9744 return ((unsigned HOST_WIDE_INT)
9745 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9746 ? \"li %0,%1\" : \"lis %0,%v1\";
9749 ;; Generate all one-bits and clear left or right.
9750 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9752 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9753 (match_operand:DI 1 "mask64_operand" ""))]
9754 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9755 [(set (match_dup 0) (const_int -1))
9757 (and:DI (rotate:DI (match_dup 0)
9762 ;; Split a load of a large constant into the appropriate five-instruction
9763 ;; sequence. Handle anything in a constant number of insns.
9764 ;; When non-easy constants can go in the TOC, this should use
9765 ;; easy_fp_constant predicate.
9767 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9768 (match_operand:DI 1 "const_int_operand" ""))]
9769 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9770 [(set (match_dup 0) (match_dup 2))
9771 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9773 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9775 if (tem == operands[0])
9782 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9783 (match_operand:DI 1 "const_double_operand" ""))]
9784 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9785 [(set (match_dup 0) (match_dup 2))
9786 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9788 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9790 if (tem == operands[0])
9796 ;; TImode is similar, except that we usually want to compute the address into
9797 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9798 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9800 ;; We say that MQ is clobbered in the last alternative because the first
9801 ;; alternative would never get used otherwise since it would need a reload
9802 ;; while the 2nd alternative would not. We put memory cases first so they
9803 ;; are preferred. Otherwise, we'd try to reload the output instead of
9804 ;; giving the SCRATCH mq.
9806 (define_insn "*movti_power"
9807 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9808 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9809 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9810 "TARGET_POWER && ! TARGET_POWERPC64
9811 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9814 switch (which_alternative)
9821 return \"{stsi|stswi} %1,%P0,16\";
9826 /* If the address is not used in the output, we can use lsi. Otherwise,
9827 fall through to generating four loads. */
9829 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9830 return \"{lsi|lswi} %0,%P1,16\";
9831 /* ... fall through ... */
9837 [(set_attr "type" "store,store,*,load,load,*")])
9839 (define_insn "*movti_string"
9840 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9841 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9842 "! TARGET_POWER && ! TARGET_POWERPC64
9843 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9846 switch (which_alternative)
9852 return \"{stsi|stswi} %1,%P0,16\";
9857 /* If the address is not used in the output, we can use lsi. Otherwise,
9858 fall through to generating four loads. */
9860 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9861 return \"{lsi|lswi} %0,%P1,16\";
9862 /* ... fall through ... */
9868 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9869 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9870 (const_string "always")
9871 (const_string "conditional")))])
9873 (define_insn "*movti_ppc64"
9874 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9875 (match_operand:TI 1 "input_operand" "r,r,m"))]
9876 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9877 || gpc_reg_operand (operands[1], TImode)))
9878 && VECTOR_MEM_NONE_P (TImode)"
9880 [(set_attr "type" "*,store,load")])
9883 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9884 (match_operand:TI 1 "const_double_operand" ""))]
9885 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9886 [(set (match_dup 2) (match_dup 4))
9887 (set (match_dup 3) (match_dup 5))]
9890 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9892 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9894 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9896 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9897 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9899 else if (GET_CODE (operands[1]) == CONST_INT)
9901 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9902 operands[5] = operands[1];
9909 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9910 (match_operand:TI 1 "input_operand" ""))]
9911 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9912 && gpr_or_gpr_p (operands[0], operands[1])"
9914 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9916 (define_expand "load_multiple"
9917 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9918 (match_operand:SI 1 "" ""))
9919 (use (match_operand:SI 2 "" ""))])]
9920 "TARGET_STRING && !TARGET_POWERPC64"
9928 /* Support only loading a constant number of fixed-point registers from
9929 memory and only bother with this if more than two; the machine
9930 doesn't support more than eight. */
9931 if (GET_CODE (operands[2]) != CONST_INT
9932 || INTVAL (operands[2]) <= 2
9933 || INTVAL (operands[2]) > 8
9934 || GET_CODE (operands[1]) != MEM
9935 || GET_CODE (operands[0]) != REG
9936 || REGNO (operands[0]) >= 32)
9939 count = INTVAL (operands[2]);
9940 regno = REGNO (operands[0]);
9942 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9943 op1 = replace_equiv_address (operands[1],
9944 force_reg (SImode, XEXP (operands[1], 0)));
9946 for (i = 0; i < count; i++)
9947 XVECEXP (operands[3], 0, i)
9948 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9949 adjust_address_nv (op1, SImode, i * 4));
9952 (define_insn "*ldmsi8"
9953 [(match_parallel 0 "load_multiple_operation"
9954 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9955 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9956 (set (match_operand:SI 3 "gpc_reg_operand" "")
9957 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9958 (set (match_operand:SI 4 "gpc_reg_operand" "")
9959 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9960 (set (match_operand:SI 5 "gpc_reg_operand" "")
9961 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9962 (set (match_operand:SI 6 "gpc_reg_operand" "")
9963 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9964 (set (match_operand:SI 7 "gpc_reg_operand" "")
9965 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9966 (set (match_operand:SI 8 "gpc_reg_operand" "")
9967 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9968 (set (match_operand:SI 9 "gpc_reg_operand" "")
9969 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9970 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9972 { return rs6000_output_load_multiple (operands); }"
9973 [(set_attr "type" "load_ux")
9974 (set_attr "length" "32")])
9976 (define_insn "*ldmsi7"
9977 [(match_parallel 0 "load_multiple_operation"
9978 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9979 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9980 (set (match_operand:SI 3 "gpc_reg_operand" "")
9981 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9982 (set (match_operand:SI 4 "gpc_reg_operand" "")
9983 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9984 (set (match_operand:SI 5 "gpc_reg_operand" "")
9985 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9986 (set (match_operand:SI 6 "gpc_reg_operand" "")
9987 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9988 (set (match_operand:SI 7 "gpc_reg_operand" "")
9989 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9990 (set (match_operand:SI 8 "gpc_reg_operand" "")
9991 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9992 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9994 { return rs6000_output_load_multiple (operands); }"
9995 [(set_attr "type" "load_ux")
9996 (set_attr "length" "32")])
9998 (define_insn "*ldmsi6"
9999 [(match_parallel 0 "load_multiple_operation"
10000 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10001 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10002 (set (match_operand:SI 3 "gpc_reg_operand" "")
10003 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10004 (set (match_operand:SI 4 "gpc_reg_operand" "")
10005 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10006 (set (match_operand:SI 5 "gpc_reg_operand" "")
10007 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10008 (set (match_operand:SI 6 "gpc_reg_operand" "")
10009 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10010 (set (match_operand:SI 7 "gpc_reg_operand" "")
10011 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10012 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10014 { return rs6000_output_load_multiple (operands); }"
10015 [(set_attr "type" "load_ux")
10016 (set_attr "length" "32")])
10018 (define_insn "*ldmsi5"
10019 [(match_parallel 0 "load_multiple_operation"
10020 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10021 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10022 (set (match_operand:SI 3 "gpc_reg_operand" "")
10023 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10024 (set (match_operand:SI 4 "gpc_reg_operand" "")
10025 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10026 (set (match_operand:SI 5 "gpc_reg_operand" "")
10027 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10028 (set (match_operand:SI 6 "gpc_reg_operand" "")
10029 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10030 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10032 { return rs6000_output_load_multiple (operands); }"
10033 [(set_attr "type" "load_ux")
10034 (set_attr "length" "32")])
10036 (define_insn "*ldmsi4"
10037 [(match_parallel 0 "load_multiple_operation"
10038 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10039 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10040 (set (match_operand:SI 3 "gpc_reg_operand" "")
10041 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10042 (set (match_operand:SI 4 "gpc_reg_operand" "")
10043 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10044 (set (match_operand:SI 5 "gpc_reg_operand" "")
10045 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10046 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10048 { return rs6000_output_load_multiple (operands); }"
10049 [(set_attr "type" "load_ux")
10050 (set_attr "length" "32")])
10052 (define_insn "*ldmsi3"
10053 [(match_parallel 0 "load_multiple_operation"
10054 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10055 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10056 (set (match_operand:SI 3 "gpc_reg_operand" "")
10057 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10058 (set (match_operand:SI 4 "gpc_reg_operand" "")
10059 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10060 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10062 { return rs6000_output_load_multiple (operands); }"
10063 [(set_attr "type" "load_ux")
10064 (set_attr "length" "32")])
10066 (define_expand "store_multiple"
10067 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10068 (match_operand:SI 1 "" ""))
10069 (clobber (scratch:SI))
10070 (use (match_operand:SI 2 "" ""))])]
10071 "TARGET_STRING && !TARGET_POWERPC64"
10080 /* Support only storing a constant number of fixed-point registers to
10081 memory and only bother with this if more than two; the machine
10082 doesn't support more than eight. */
10083 if (GET_CODE (operands[2]) != CONST_INT
10084 || INTVAL (operands[2]) <= 2
10085 || INTVAL (operands[2]) > 8
10086 || GET_CODE (operands[0]) != MEM
10087 || GET_CODE (operands[1]) != REG
10088 || REGNO (operands[1]) >= 32)
10091 count = INTVAL (operands[2]);
10092 regno = REGNO (operands[1]);
10094 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10095 to = force_reg (SImode, XEXP (operands[0], 0));
10096 op0 = replace_equiv_address (operands[0], to);
10098 XVECEXP (operands[3], 0, 0)
10099 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10100 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10101 gen_rtx_SCRATCH (SImode));
10103 for (i = 1; i < count; i++)
10104 XVECEXP (operands[3], 0, i + 1)
10105 = gen_rtx_SET (VOIDmode,
10106 adjust_address_nv (op0, SImode, i * 4),
10107 gen_rtx_REG (SImode, regno + i));
10110 (define_insn "*stmsi8"
10111 [(match_parallel 0 "store_multiple_operation"
10112 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10113 (match_operand:SI 2 "gpc_reg_operand" "r"))
10114 (clobber (match_scratch:SI 3 "=X"))
10115 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10116 (match_operand:SI 4 "gpc_reg_operand" "r"))
10117 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10118 (match_operand:SI 5 "gpc_reg_operand" "r"))
10119 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10120 (match_operand:SI 6 "gpc_reg_operand" "r"))
10121 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10122 (match_operand:SI 7 "gpc_reg_operand" "r"))
10123 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10124 (match_operand:SI 8 "gpc_reg_operand" "r"))
10125 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10126 (match_operand:SI 9 "gpc_reg_operand" "r"))
10127 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10128 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10129 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10130 "{stsi|stswi} %2,%1,%O0"
10131 [(set_attr "type" "store_ux")
10132 (set_attr "cell_micro" "always")])
10134 (define_insn "*stmsi7"
10135 [(match_parallel 0 "store_multiple_operation"
10136 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10137 (match_operand:SI 2 "gpc_reg_operand" "r"))
10138 (clobber (match_scratch:SI 3 "=X"))
10139 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10140 (match_operand:SI 4 "gpc_reg_operand" "r"))
10141 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10142 (match_operand:SI 5 "gpc_reg_operand" "r"))
10143 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10144 (match_operand:SI 6 "gpc_reg_operand" "r"))
10145 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10146 (match_operand:SI 7 "gpc_reg_operand" "r"))
10147 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10148 (match_operand:SI 8 "gpc_reg_operand" "r"))
10149 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10150 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10151 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10152 "{stsi|stswi} %2,%1,%O0"
10153 [(set_attr "type" "store_ux")
10154 (set_attr "cell_micro" "always")])
10156 (define_insn "*stmsi6"
10157 [(match_parallel 0 "store_multiple_operation"
10158 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10159 (match_operand:SI 2 "gpc_reg_operand" "r"))
10160 (clobber (match_scratch:SI 3 "=X"))
10161 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10162 (match_operand:SI 4 "gpc_reg_operand" "r"))
10163 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10164 (match_operand:SI 5 "gpc_reg_operand" "r"))
10165 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10166 (match_operand:SI 6 "gpc_reg_operand" "r"))
10167 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10168 (match_operand:SI 7 "gpc_reg_operand" "r"))
10169 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10170 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10171 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10172 "{stsi|stswi} %2,%1,%O0"
10173 [(set_attr "type" "store_ux")
10174 (set_attr "cell_micro" "always")])
10176 (define_insn "*stmsi5"
10177 [(match_parallel 0 "store_multiple_operation"
10178 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10179 (match_operand:SI 2 "gpc_reg_operand" "r"))
10180 (clobber (match_scratch:SI 3 "=X"))
10181 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10182 (match_operand:SI 4 "gpc_reg_operand" "r"))
10183 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10184 (match_operand:SI 5 "gpc_reg_operand" "r"))
10185 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10186 (match_operand:SI 6 "gpc_reg_operand" "r"))
10187 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10188 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10189 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10190 "{stsi|stswi} %2,%1,%O0"
10191 [(set_attr "type" "store_ux")
10192 (set_attr "cell_micro" "always")])
10194 (define_insn "*stmsi4"
10195 [(match_parallel 0 "store_multiple_operation"
10196 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10197 (match_operand:SI 2 "gpc_reg_operand" "r"))
10198 (clobber (match_scratch:SI 3 "=X"))
10199 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10200 (match_operand:SI 4 "gpc_reg_operand" "r"))
10201 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10202 (match_operand:SI 5 "gpc_reg_operand" "r"))
10203 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10204 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10205 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10206 "{stsi|stswi} %2,%1,%O0"
10207 [(set_attr "type" "store_ux")
10208 (set_attr "cell_micro" "always")])
10210 (define_insn "*stmsi3"
10211 [(match_parallel 0 "store_multiple_operation"
10212 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10213 (match_operand:SI 2 "gpc_reg_operand" "r"))
10214 (clobber (match_scratch:SI 3 "=X"))
10215 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10216 (match_operand:SI 4 "gpc_reg_operand" "r"))
10217 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10218 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10219 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10220 "{stsi|stswi} %2,%1,%O0"
10221 [(set_attr "type" "store_ux")
10222 (set_attr "cell_micro" "always")])
10224 (define_insn "*stmsi8_power"
10225 [(match_parallel 0 "store_multiple_operation"
10226 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10227 (match_operand:SI 2 "gpc_reg_operand" "r"))
10228 (clobber (match_scratch:SI 3 "=q"))
10229 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10230 (match_operand:SI 4 "gpc_reg_operand" "r"))
10231 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10232 (match_operand:SI 5 "gpc_reg_operand" "r"))
10233 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10234 (match_operand:SI 6 "gpc_reg_operand" "r"))
10235 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10236 (match_operand:SI 7 "gpc_reg_operand" "r"))
10237 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10238 (match_operand:SI 8 "gpc_reg_operand" "r"))
10239 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10240 (match_operand:SI 9 "gpc_reg_operand" "r"))
10241 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10242 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10243 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10244 "{stsi|stswi} %2,%1,%O0"
10245 [(set_attr "type" "store_ux")
10246 (set_attr "cell_micro" "always")])
10248 (define_insn "*stmsi7_power"
10249 [(match_parallel 0 "store_multiple_operation"
10250 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10251 (match_operand:SI 2 "gpc_reg_operand" "r"))
10252 (clobber (match_scratch:SI 3 "=q"))
10253 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10254 (match_operand:SI 4 "gpc_reg_operand" "r"))
10255 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10256 (match_operand:SI 5 "gpc_reg_operand" "r"))
10257 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10258 (match_operand:SI 6 "gpc_reg_operand" "r"))
10259 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10260 (match_operand:SI 7 "gpc_reg_operand" "r"))
10261 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10262 (match_operand:SI 8 "gpc_reg_operand" "r"))
10263 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10264 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10265 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10266 "{stsi|stswi} %2,%1,%O0"
10267 [(set_attr "type" "store_ux")
10268 (set_attr "cell_micro" "always")])
10270 (define_insn "*stmsi6_power"
10271 [(match_parallel 0 "store_multiple_operation"
10272 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10273 (match_operand:SI 2 "gpc_reg_operand" "r"))
10274 (clobber (match_scratch:SI 3 "=q"))
10275 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10276 (match_operand:SI 4 "gpc_reg_operand" "r"))
10277 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10278 (match_operand:SI 5 "gpc_reg_operand" "r"))
10279 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10280 (match_operand:SI 6 "gpc_reg_operand" "r"))
10281 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10282 (match_operand:SI 7 "gpc_reg_operand" "r"))
10283 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10284 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10285 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10286 "{stsi|stswi} %2,%1,%O0"
10287 [(set_attr "type" "store_ux")
10288 (set_attr "cell_micro" "always")])
10290 (define_insn "*stmsi5_power"
10291 [(match_parallel 0 "store_multiple_operation"
10292 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10293 (match_operand:SI 2 "gpc_reg_operand" "r"))
10294 (clobber (match_scratch:SI 3 "=q"))
10295 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10296 (match_operand:SI 4 "gpc_reg_operand" "r"))
10297 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10298 (match_operand:SI 5 "gpc_reg_operand" "r"))
10299 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10300 (match_operand:SI 6 "gpc_reg_operand" "r"))
10301 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10302 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10303 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10304 "{stsi|stswi} %2,%1,%O0"
10305 [(set_attr "type" "store_ux")
10306 (set_attr "cell_micro" "always")])
10308 (define_insn "*stmsi4_power"
10309 [(match_parallel 0 "store_multiple_operation"
10310 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10311 (match_operand:SI 2 "gpc_reg_operand" "r"))
10312 (clobber (match_scratch:SI 3 "=q"))
10313 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10314 (match_operand:SI 4 "gpc_reg_operand" "r"))
10315 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10316 (match_operand:SI 5 "gpc_reg_operand" "r"))
10317 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10318 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10319 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10320 "{stsi|stswi} %2,%1,%O0"
10321 [(set_attr "type" "store_ux")
10322 (set_attr "cell_micro" "always")])
10324 (define_insn "*stmsi3_power"
10325 [(match_parallel 0 "store_multiple_operation"
10326 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10327 (match_operand:SI 2 "gpc_reg_operand" "r"))
10328 (clobber (match_scratch:SI 3 "=q"))
10329 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10330 (match_operand:SI 4 "gpc_reg_operand" "r"))
10331 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10332 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10333 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10334 "{stsi|stswi} %2,%1,%O0"
10335 [(set_attr "type" "store_ux")
10336 (set_attr "cell_micro" "always")])
10338 (define_expand "setmemsi"
10339 [(parallel [(set (match_operand:BLK 0 "" "")
10340 (match_operand 2 "const_int_operand" ""))
10341 (use (match_operand:SI 1 "" ""))
10342 (use (match_operand:SI 3 "" ""))])]
10346 /* If value to set is not zero, use the library routine. */
10347 if (operands[2] != const0_rtx)
10350 if (expand_block_clear (operands))
10356 ;; String/block move insn.
10357 ;; Argument 0 is the destination
10358 ;; Argument 1 is the source
10359 ;; Argument 2 is the length
10360 ;; Argument 3 is the alignment
10362 (define_expand "movmemsi"
10363 [(parallel [(set (match_operand:BLK 0 "" "")
10364 (match_operand:BLK 1 "" ""))
10365 (use (match_operand:SI 2 "" ""))
10366 (use (match_operand:SI 3 "" ""))])]
10370 if (expand_block_move (operands))
10376 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10377 ;; register allocator doesn't have a clue about allocating 8 word registers.
10378 ;; rD/rS = r5 is preferred, efficient form.
10379 (define_expand "movmemsi_8reg"
10380 [(parallel [(set (match_operand 0 "" "")
10381 (match_operand 1 "" ""))
10382 (use (match_operand 2 "" ""))
10383 (use (match_operand 3 "" ""))
10384 (clobber (reg:SI 5))
10385 (clobber (reg:SI 6))
10386 (clobber (reg:SI 7))
10387 (clobber (reg:SI 8))
10388 (clobber (reg:SI 9))
10389 (clobber (reg:SI 10))
10390 (clobber (reg:SI 11))
10391 (clobber (reg:SI 12))
10392 (clobber (match_scratch:SI 4 ""))])]
10397 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10398 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10399 (use (match_operand:SI 2 "immediate_operand" "i"))
10400 (use (match_operand:SI 3 "immediate_operand" "i"))
10401 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10402 (clobber (reg:SI 6))
10403 (clobber (reg:SI 7))
10404 (clobber (reg:SI 8))
10405 (clobber (reg:SI 9))
10406 (clobber (reg:SI 10))
10407 (clobber (reg:SI 11))
10408 (clobber (reg:SI 12))
10409 (clobber (match_scratch:SI 5 "=q"))]
10410 "TARGET_STRING && TARGET_POWER
10411 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10412 || INTVAL (operands[2]) == 0)
10413 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10414 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10415 && REGNO (operands[4]) == 5"
10416 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10417 [(set_attr "type" "store_ux")
10418 (set_attr "cell_micro" "always")
10419 (set_attr "length" "8")])
10422 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10423 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10424 (use (match_operand:SI 2 "immediate_operand" "i"))
10425 (use (match_operand:SI 3 "immediate_operand" "i"))
10426 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10427 (clobber (reg:SI 6))
10428 (clobber (reg:SI 7))
10429 (clobber (reg:SI 8))
10430 (clobber (reg:SI 9))
10431 (clobber (reg:SI 10))
10432 (clobber (reg:SI 11))
10433 (clobber (reg:SI 12))
10434 (clobber (match_scratch:SI 5 "=X"))]
10435 "TARGET_STRING && ! TARGET_POWER
10436 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10437 || INTVAL (operands[2]) == 0)
10438 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10439 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10440 && REGNO (operands[4]) == 5"
10441 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10442 [(set_attr "type" "store_ux")
10443 (set_attr "cell_micro" "always")
10444 (set_attr "length" "8")])
10446 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10447 ;; register allocator doesn't have a clue about allocating 6 word registers.
10448 ;; rD/rS = r5 is preferred, efficient form.
10449 (define_expand "movmemsi_6reg"
10450 [(parallel [(set (match_operand 0 "" "")
10451 (match_operand 1 "" ""))
10452 (use (match_operand 2 "" ""))
10453 (use (match_operand 3 "" ""))
10454 (clobber (reg:SI 5))
10455 (clobber (reg:SI 6))
10456 (clobber (reg:SI 7))
10457 (clobber (reg:SI 8))
10458 (clobber (reg:SI 9))
10459 (clobber (reg:SI 10))
10460 (clobber (match_scratch:SI 4 ""))])]
10465 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10466 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10467 (use (match_operand:SI 2 "immediate_operand" "i"))
10468 (use (match_operand:SI 3 "immediate_operand" "i"))
10469 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10470 (clobber (reg:SI 6))
10471 (clobber (reg:SI 7))
10472 (clobber (reg:SI 8))
10473 (clobber (reg:SI 9))
10474 (clobber (reg:SI 10))
10475 (clobber (match_scratch:SI 5 "=q"))]
10476 "TARGET_STRING && TARGET_POWER
10477 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10478 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10479 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10480 && REGNO (operands[4]) == 5"
10481 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10482 [(set_attr "type" "store_ux")
10483 (set_attr "cell_micro" "always")
10484 (set_attr "length" "8")])
10487 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10488 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10489 (use (match_operand:SI 2 "immediate_operand" "i"))
10490 (use (match_operand:SI 3 "immediate_operand" "i"))
10491 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10492 (clobber (reg:SI 6))
10493 (clobber (reg:SI 7))
10494 (clobber (reg:SI 8))
10495 (clobber (reg:SI 9))
10496 (clobber (reg:SI 10))
10497 (clobber (match_scratch:SI 5 "=X"))]
10498 "TARGET_STRING && ! TARGET_POWER
10499 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10500 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10501 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10502 && REGNO (operands[4]) == 5"
10503 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10504 [(set_attr "type" "store_ux")
10505 (set_attr "cell_micro" "always")
10506 (set_attr "length" "8")])
10508 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10509 ;; problems with TImode.
10510 ;; rD/rS = r5 is preferred, efficient form.
10511 (define_expand "movmemsi_4reg"
10512 [(parallel [(set (match_operand 0 "" "")
10513 (match_operand 1 "" ""))
10514 (use (match_operand 2 "" ""))
10515 (use (match_operand 3 "" ""))
10516 (clobber (reg:SI 5))
10517 (clobber (reg:SI 6))
10518 (clobber (reg:SI 7))
10519 (clobber (reg:SI 8))
10520 (clobber (match_scratch:SI 4 ""))])]
10525 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10526 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10527 (use (match_operand:SI 2 "immediate_operand" "i"))
10528 (use (match_operand:SI 3 "immediate_operand" "i"))
10529 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10530 (clobber (reg:SI 6))
10531 (clobber (reg:SI 7))
10532 (clobber (reg:SI 8))
10533 (clobber (match_scratch:SI 5 "=q"))]
10534 "TARGET_STRING && TARGET_POWER
10535 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10536 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10537 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10538 && REGNO (operands[4]) == 5"
10539 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10540 [(set_attr "type" "store_ux")
10541 (set_attr "cell_micro" "always")
10542 (set_attr "length" "8")])
10545 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10546 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10547 (use (match_operand:SI 2 "immediate_operand" "i"))
10548 (use (match_operand:SI 3 "immediate_operand" "i"))
10549 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10550 (clobber (reg:SI 6))
10551 (clobber (reg:SI 7))
10552 (clobber (reg:SI 8))
10553 (clobber (match_scratch:SI 5 "=X"))]
10554 "TARGET_STRING && ! TARGET_POWER
10555 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10556 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10557 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10558 && REGNO (operands[4]) == 5"
10559 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10560 [(set_attr "type" "store_ux")
10561 (set_attr "cell_micro" "always")
10562 (set_attr "length" "8")])
10564 ;; Move up to 8 bytes at a time.
10565 (define_expand "movmemsi_2reg"
10566 [(parallel [(set (match_operand 0 "" "")
10567 (match_operand 1 "" ""))
10568 (use (match_operand 2 "" ""))
10569 (use (match_operand 3 "" ""))
10570 (clobber (match_scratch:DI 4 ""))
10571 (clobber (match_scratch:SI 5 ""))])]
10572 "TARGET_STRING && ! TARGET_POWERPC64"
10576 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10577 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10578 (use (match_operand:SI 2 "immediate_operand" "i"))
10579 (use (match_operand:SI 3 "immediate_operand" "i"))
10580 (clobber (match_scratch:DI 4 "=&r"))
10581 (clobber (match_scratch:SI 5 "=q"))]
10582 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10583 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10584 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10585 [(set_attr "type" "store_ux")
10586 (set_attr "cell_micro" "always")
10587 (set_attr "length" "8")])
10590 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10591 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10592 (use (match_operand:SI 2 "immediate_operand" "i"))
10593 (use (match_operand:SI 3 "immediate_operand" "i"))
10594 (clobber (match_scratch:DI 4 "=&r"))
10595 (clobber (match_scratch:SI 5 "=X"))]
10596 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10597 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10598 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10599 [(set_attr "type" "store_ux")
10600 (set_attr "cell_micro" "always")
10601 (set_attr "length" "8")])
10603 ;; Move up to 4 bytes at a time.
10604 (define_expand "movmemsi_1reg"
10605 [(parallel [(set (match_operand 0 "" "")
10606 (match_operand 1 "" ""))
10607 (use (match_operand 2 "" ""))
10608 (use (match_operand 3 "" ""))
10609 (clobber (match_scratch:SI 4 ""))
10610 (clobber (match_scratch:SI 5 ""))])]
10615 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10616 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10617 (use (match_operand:SI 2 "immediate_operand" "i"))
10618 (use (match_operand:SI 3 "immediate_operand" "i"))
10619 (clobber (match_scratch:SI 4 "=&r"))
10620 (clobber (match_scratch:SI 5 "=q"))]
10621 "TARGET_STRING && TARGET_POWER
10622 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10623 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10624 [(set_attr "type" "store_ux")
10625 (set_attr "cell_micro" "always")
10626 (set_attr "length" "8")])
10629 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10630 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10631 (use (match_operand:SI 2 "immediate_operand" "i"))
10632 (use (match_operand:SI 3 "immediate_operand" "i"))
10633 (clobber (match_scratch:SI 4 "=&r"))
10634 (clobber (match_scratch:SI 5 "=X"))]
10635 "TARGET_STRING && ! TARGET_POWER
10636 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10637 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10638 [(set_attr "type" "store_ux")
10639 (set_attr "cell_micro" "always")
10640 (set_attr "length" "8")])
10642 ;; Define insns that do load or store with update. Some of these we can
10643 ;; get by using pre-decrement or pre-increment, but the hardware can also
10644 ;; do cases where the increment is not the size of the object.
10646 ;; In all these cases, we use operands 0 and 1 for the register being
10647 ;; incremented because those are the operands that local-alloc will
10648 ;; tie and these are the pair most likely to be tieable (and the ones
10649 ;; that will benefit the most).
10651 (define_insn "*movdi_update1"
10652 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10653 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10654 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10655 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10656 (plus:DI (match_dup 1) (match_dup 2)))]
10657 "TARGET_POWERPC64 && TARGET_UPDATE
10658 && (!avoiding_indexed_address_p (DImode)
10659 || !gpc_reg_operand (operands[2], DImode))"
10663 [(set_attr "type" "load_ux,load_u")])
10665 (define_insn "movdi_<mode>_update"
10666 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10667 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10668 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10669 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10670 (plus:P (match_dup 1) (match_dup 2)))]
10671 "TARGET_POWERPC64 && TARGET_UPDATE
10672 && (!avoiding_indexed_address_p (Pmode)
10673 || !gpc_reg_operand (operands[2], Pmode)
10674 || (REG_P (operands[0])
10675 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10679 [(set_attr "type" "store_ux,store_u")])
10681 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10682 ;; needed for stack allocation, even if the user passes -mno-update.
10683 (define_insn "movdi_<mode>_update_stack"
10684 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10685 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10686 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10687 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10688 (plus:P (match_dup 1) (match_dup 2)))]
10693 [(set_attr "type" "store_ux,store_u")])
10695 (define_insn "*movsi_update1"
10696 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10697 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10698 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10699 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10700 (plus:SI (match_dup 1) (match_dup 2)))]
10702 && (!avoiding_indexed_address_p (SImode)
10703 || !gpc_reg_operand (operands[2], SImode))"
10705 {lux|lwzux} %3,%0,%2
10706 {lu|lwzu} %3,%2(%0)"
10707 [(set_attr "type" "load_ux,load_u")])
10709 (define_insn "*movsi_update2"
10710 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10712 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10713 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10714 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10715 (plus:DI (match_dup 1) (match_dup 2)))]
10716 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10717 && !avoiding_indexed_address_p (DImode)"
10719 [(set_attr "type" "load_ext_ux")])
10721 (define_insn "movsi_update"
10722 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10723 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10724 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10725 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10726 (plus:SI (match_dup 1) (match_dup 2)))]
10728 && (!avoiding_indexed_address_p (SImode)
10729 || !gpc_reg_operand (operands[2], SImode)
10730 || (REG_P (operands[0])
10731 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10733 {stux|stwux} %3,%0,%2
10734 {stu|stwu} %3,%2(%0)"
10735 [(set_attr "type" "store_ux,store_u")])
10737 ;; This is an unconditional pattern; needed for stack allocation, even
10738 ;; if the user passes -mno-update.
10739 (define_insn "movsi_update_stack"
10740 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10741 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10742 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10743 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10744 (plus:SI (match_dup 1) (match_dup 2)))]
10747 {stux|stwux} %3,%0,%2
10748 {stu|stwu} %3,%2(%0)"
10749 [(set_attr "type" "store_ux,store_u")])
10751 (define_insn "*movhi_update1"
10752 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10753 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10754 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10755 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10756 (plus:SI (match_dup 1) (match_dup 2)))]
10758 && (!avoiding_indexed_address_p (SImode)
10759 || !gpc_reg_operand (operands[2], SImode))"
10763 [(set_attr "type" "load_ux,load_u")])
10765 (define_insn "*movhi_update2"
10766 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10768 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10769 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10770 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10771 (plus:SI (match_dup 1) (match_dup 2)))]
10773 && (!avoiding_indexed_address_p (SImode)
10774 || !gpc_reg_operand (operands[2], SImode))"
10778 [(set_attr "type" "load_ux,load_u")])
10780 (define_insn "*movhi_update3"
10781 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10783 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10784 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10785 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10786 (plus:SI (match_dup 1) (match_dup 2)))]
10787 "TARGET_UPDATE && rs6000_gen_cell_microcode
10788 && (!avoiding_indexed_address_p (SImode)
10789 || !gpc_reg_operand (operands[2], SImode))"
10793 [(set_attr "type" "load_ext_ux,load_ext_u")])
10795 (define_insn "*movhi_update4"
10796 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10797 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10798 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10799 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10800 (plus:SI (match_dup 1) (match_dup 2)))]
10802 && (!avoiding_indexed_address_p (SImode)
10803 || !gpc_reg_operand (operands[2], SImode))"
10807 [(set_attr "type" "store_ux,store_u")])
10809 (define_insn "*movqi_update1"
10810 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10811 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10812 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10813 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10814 (plus:SI (match_dup 1) (match_dup 2)))]
10816 && (!avoiding_indexed_address_p (SImode)
10817 || !gpc_reg_operand (operands[2], SImode))"
10821 [(set_attr "type" "load_ux,load_u")])
10823 (define_insn "*movqi_update2"
10824 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10826 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10827 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10828 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10829 (plus:SI (match_dup 1) (match_dup 2)))]
10831 && (!avoiding_indexed_address_p (SImode)
10832 || !gpc_reg_operand (operands[2], SImode))"
10836 [(set_attr "type" "load_ux,load_u")])
10838 (define_insn "*movqi_update3"
10839 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10840 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10841 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10842 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10843 (plus:SI (match_dup 1) (match_dup 2)))]
10845 && (!avoiding_indexed_address_p (SImode)
10846 || !gpc_reg_operand (operands[2], SImode))"
10850 [(set_attr "type" "store_ux,store_u")])
10852 (define_insn "*movsf_update1"
10853 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10854 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10855 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10856 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10857 (plus:SI (match_dup 1) (match_dup 2)))]
10858 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10859 && (!avoiding_indexed_address_p (SImode)
10860 || !gpc_reg_operand (operands[2], SImode))"
10864 [(set_attr "type" "fpload_ux,fpload_u")])
10866 (define_insn "*movsf_update2"
10867 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10868 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10869 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10870 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10871 (plus:SI (match_dup 1) (match_dup 2)))]
10872 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10873 && (!avoiding_indexed_address_p (SImode)
10874 || !gpc_reg_operand (operands[2], SImode))"
10878 [(set_attr "type" "fpstore_ux,fpstore_u")])
10880 (define_insn "*movsf_update3"
10881 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10882 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10883 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10884 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10885 (plus:SI (match_dup 1) (match_dup 2)))]
10886 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10887 && (!avoiding_indexed_address_p (SImode)
10888 || !gpc_reg_operand (operands[2], SImode))"
10890 {lux|lwzux} %3,%0,%2
10891 {lu|lwzu} %3,%2(%0)"
10892 [(set_attr "type" "load_ux,load_u")])
10894 (define_insn "*movsf_update4"
10895 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10896 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10897 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10898 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10899 (plus:SI (match_dup 1) (match_dup 2)))]
10900 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10901 && (!avoiding_indexed_address_p (SImode)
10902 || !gpc_reg_operand (operands[2], SImode))"
10904 {stux|stwux} %3,%0,%2
10905 {stu|stwu} %3,%2(%0)"
10906 [(set_attr "type" "store_ux,store_u")])
10908 (define_insn "*movdf_update1"
10909 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10910 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10911 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10912 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10913 (plus:SI (match_dup 1) (match_dup 2)))]
10914 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10915 && (!avoiding_indexed_address_p (SImode)
10916 || !gpc_reg_operand (operands[2], SImode))"
10920 [(set_attr "type" "fpload_ux,fpload_u")])
10922 (define_insn "*movdf_update2"
10923 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10924 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10925 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10926 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10927 (plus:SI (match_dup 1) (match_dup 2)))]
10928 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10929 && (!avoiding_indexed_address_p (SImode)
10930 || !gpc_reg_operand (operands[2], SImode))"
10934 [(set_attr "type" "fpstore_ux,fpstore_u")])
10936 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10938 (define_insn "*lfq_power2"
10939 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10940 (match_operand:V2DF 1 "memory_operand" ""))]
10942 && TARGET_HARD_FLOAT && TARGET_FPRS"
10946 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10947 (match_operand:DF 1 "memory_operand" ""))
10948 (set (match_operand:DF 2 "gpc_reg_operand" "")
10949 (match_operand:DF 3 "memory_operand" ""))]
10951 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10952 && registers_ok_for_quad_peep (operands[0], operands[2])
10953 && mems_ok_for_quad_peep (operands[1], operands[3])"
10954 [(set (match_dup 0)
10956 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10957 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10959 (define_insn "*stfq_power2"
10960 [(set (match_operand:V2DF 0 "memory_operand" "")
10961 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10963 && TARGET_HARD_FLOAT && TARGET_FPRS"
10964 "stfq%U0%X0 %1,%0")
10968 [(set (match_operand:DF 0 "memory_operand" "")
10969 (match_operand:DF 1 "gpc_reg_operand" ""))
10970 (set (match_operand:DF 2 "memory_operand" "")
10971 (match_operand:DF 3 "gpc_reg_operand" ""))]
10973 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10974 && registers_ok_for_quad_peep (operands[1], operands[3])
10975 && mems_ok_for_quad_peep (operands[0], operands[2])"
10976 [(set (match_dup 0)
10978 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10979 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10981 ;; After inserting conditional returns we can sometimes have
10982 ;; unnecessary register moves. Unfortunately we cannot have a
10983 ;; modeless peephole here, because some single SImode sets have early
10984 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10985 ;; sequences, using get_attr_length here will smash the operands
10986 ;; array. Neither is there an early_cobbler_p predicate.
10987 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10989 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10990 (match_operand:DF 1 "any_operand" ""))
10991 (set (match_operand:DF 2 "gpc_reg_operand" "")
10993 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10994 && peep2_reg_dead_p (2, operands[0])"
10995 [(set (match_dup 2) (match_dup 1))])
10998 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10999 (match_operand:SF 1 "any_operand" ""))
11000 (set (match_operand:SF 2 "gpc_reg_operand" "")
11002 "peep2_reg_dead_p (2, operands[0])"
11003 [(set (match_dup 2) (match_dup 1))])
11008 ;; Mode attributes for different ABIs.
11009 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11010 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11011 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11012 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11014 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11015 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11016 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11017 (match_operand 4 "" "g")))
11018 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11019 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11021 (clobber (reg:SI LR_REGNO))]
11022 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11023 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
11024 "&& TARGET_TLS_MARKERS"
11025 [(set (match_dup 0)
11026 (unspec:TLSmode [(match_dup 1)
11029 (parallel [(set (match_dup 0)
11030 (call (mem:TLSmode (match_dup 3))
11032 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11033 (clobber (reg:SI LR_REGNO))])]
11035 [(set_attr "type" "two")
11036 (set_attr "length" "12")])
11038 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11039 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11040 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11041 (match_operand 4 "" "g")))
11042 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11043 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11045 (clobber (reg:SI LR_REGNO))]
11046 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11050 if (TARGET_SECURE_PLT && flag_pic == 2)
11051 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11053 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11056 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11058 "&& TARGET_TLS_MARKERS"
11059 [(set (match_dup 0)
11060 (unspec:TLSmode [(match_dup 1)
11063 (parallel [(set (match_dup 0)
11064 (call (mem:TLSmode (match_dup 3))
11066 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11067 (clobber (reg:SI LR_REGNO))])]
11069 [(set_attr "type" "two")
11070 (set_attr "length" "8")])
11072 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
11073 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11074 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11075 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11077 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11078 "addi %0,%1,%2@got@tlsgd"
11079 [(set_attr "length" "4")])
11081 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11082 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11083 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11084 (match_operand 2 "" "g")))
11085 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11087 (clobber (reg:SI LR_REGNO))]
11088 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11089 "bl %z1(%3@tlsgd)\;%."
11090 [(set_attr "type" "branch")
11091 (set_attr "length" "8")])
11093 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11094 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11095 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11096 (match_operand 2 "" "g")))
11097 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11099 (clobber (reg:SI LR_REGNO))]
11100 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11104 if (TARGET_SECURE_PLT && flag_pic == 2)
11105 return "bl %z1+32768(%3@tlsgd)@plt";
11106 return "bl %z1(%3@tlsgd)@plt";
11108 return "bl %z1(%3@tlsgd)";
11110 [(set_attr "type" "branch")
11111 (set_attr "length" "4")])
11113 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11114 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11115 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11116 (match_operand 3 "" "g")))
11117 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11119 (clobber (reg:SI LR_REGNO))]
11120 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11121 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
11122 "&& TARGET_TLS_MARKERS"
11123 [(set (match_dup 0)
11124 (unspec:TLSmode [(match_dup 1)]
11126 (parallel [(set (match_dup 0)
11127 (call (mem:TLSmode (match_dup 2))
11129 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11130 (clobber (reg:SI LR_REGNO))])]
11132 [(set_attr "length" "12")])
11134 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11135 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11136 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11137 (match_operand 3 "" "g")))
11138 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11140 (clobber (reg:SI LR_REGNO))]
11141 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11145 if (TARGET_SECURE_PLT && flag_pic == 2)
11146 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11148 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11151 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11153 "&& TARGET_TLS_MARKERS"
11154 [(set (match_dup 0)
11155 (unspec:TLSmode [(match_dup 1)]
11157 (parallel [(set (match_dup 0)
11158 (call (mem:TLSmode (match_dup 2))
11160 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11161 (clobber (reg:SI LR_REGNO))])]
11163 [(set_attr "length" "8")])
11165 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
11166 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11167 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11169 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11170 "addi %0,%1,%&@got@tlsld"
11171 [(set_attr "length" "4")])
11173 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11174 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11175 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11176 (match_operand 2 "" "g")))
11177 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11178 (clobber (reg:SI LR_REGNO))]
11179 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11180 "bl %z1(%&@tlsld)\;%."
11181 [(set_attr "type" "branch")
11182 (set_attr "length" "8")])
11184 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11185 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11186 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11187 (match_operand 2 "" "g")))
11188 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11189 (clobber (reg:SI LR_REGNO))]
11190 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11194 if (TARGET_SECURE_PLT && flag_pic == 2)
11195 return "bl %z1+32768(%&@tlsld)@plt";
11196 return "bl %z1(%&@tlsld)@plt";
11198 return "bl %z1(%&@tlsld)";
11200 [(set_attr "type" "branch")
11201 (set_attr "length" "4")])
11203 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11204 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11205 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11206 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11207 UNSPEC_TLSDTPREL))]
11209 "addi %0,%1,%2@dtprel")
11211 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11212 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11213 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11214 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11215 UNSPEC_TLSDTPRELHA))]
11217 "addis %0,%1,%2@dtprel@ha")
11219 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11220 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11221 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11222 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11223 UNSPEC_TLSDTPRELLO))]
11225 "addi %0,%1,%2@dtprel@l")
11227 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11228 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11229 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11230 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11231 UNSPEC_TLSGOTDTPREL))]
11233 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
11235 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11236 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11237 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11238 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11241 "addi %0,%1,%2@tprel")
11243 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11244 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11245 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11246 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11247 UNSPEC_TLSTPRELHA))]
11249 "addis %0,%1,%2@tprel@ha")
11251 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11252 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11253 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11254 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11255 UNSPEC_TLSTPRELLO))]
11257 "addi %0,%1,%2@tprel@l")
11259 ;; "b" output constraint here and on tls_tls input to support linker tls
11260 ;; optimization. The linker may edit the instructions emitted by a
11261 ;; tls_got_tprel/tls_tls pair to addis,addi.
11262 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11263 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11264 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11265 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11266 UNSPEC_TLSGOTTPREL))]
11268 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
11270 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11271 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11272 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11273 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11276 "add %0,%1,%2@tls")
11279 ;; Next come insns related to the calling sequence.
11281 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11282 ;; We move the back-chain and decrement the stack pointer.
11284 (define_expand "allocate_stack"
11285 [(set (match_operand 0 "gpc_reg_operand" "")
11286 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11288 (minus (reg 1) (match_dup 1)))]
11291 { rtx chain = gen_reg_rtx (Pmode);
11292 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11294 rtx insn, par, set, mem;
11296 emit_move_insn (chain, stack_bot);
11298 /* Check stack bounds if necessary. */
11299 if (crtl->limit_stack)
11302 available = expand_binop (Pmode, sub_optab,
11303 stack_pointer_rtx, stack_limit_rtx,
11304 NULL_RTX, 1, OPTAB_WIDEN);
11305 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11308 if (GET_CODE (operands[1]) != CONST_INT
11309 || INTVAL (operands[1]) < -32767
11310 || INTVAL (operands[1]) > 32768)
11312 neg_op0 = gen_reg_rtx (Pmode);
11314 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11316 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11319 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11321 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11322 : gen_movdi_di_update_stack))
11323 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11325 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11326 it now and set the alias set/attributes. The above gen_*_update
11327 calls will generate a PARALLEL with the MEM set being the first
11329 par = PATTERN (insn);
11330 gcc_assert (GET_CODE (par) == PARALLEL);
11331 set = XVECEXP (par, 0, 0);
11332 gcc_assert (GET_CODE (set) == SET);
11333 mem = SET_DEST (set);
11334 gcc_assert (MEM_P (mem));
11335 MEM_NOTRAP_P (mem) = 1;
11336 set_mem_alias_set (mem, get_frame_alias_set ());
11338 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11342 ;; These patterns say how to save and restore the stack pointer. We need not
11343 ;; save the stack pointer at function level since we are careful to
11344 ;; preserve the backchain. At block level, we have to restore the backchain
11345 ;; when we restore the stack pointer.
11347 ;; For nonlocal gotos, we must save both the stack pointer and its
11348 ;; backchain and restore both. Note that in the nonlocal case, the
11349 ;; save area is a memory location.
11351 (define_expand "save_stack_function"
11352 [(match_operand 0 "any_operand" "")
11353 (match_operand 1 "any_operand" "")]
11357 (define_expand "restore_stack_function"
11358 [(match_operand 0 "any_operand" "")
11359 (match_operand 1 "any_operand" "")]
11363 ;; Adjust stack pointer (op0) to a new value (op1).
11364 ;; First copy old stack backchain to new location, and ensure that the
11365 ;; scheduler won't reorder the sp assignment before the backchain write.
11366 (define_expand "restore_stack_block"
11367 [(set (match_dup 2) (match_dup 3))
11368 (set (match_dup 4) (match_dup 2))
11369 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11370 (set (match_operand 0 "register_operand" "")
11371 (match_operand 1 "register_operand" ""))]
11375 operands[1] = force_reg (Pmode, operands[1]);
11376 operands[2] = gen_reg_rtx (Pmode);
11377 operands[3] = gen_frame_mem (Pmode, operands[0]);
11378 operands[4] = gen_frame_mem (Pmode, operands[1]);
11379 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11382 (define_expand "save_stack_nonlocal"
11383 [(set (match_dup 3) (match_dup 4))
11384 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11385 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11389 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11391 /* Copy the backchain to the first word, sp to the second. */
11392 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11393 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11394 operands[3] = gen_reg_rtx (Pmode);
11395 operands[4] = gen_frame_mem (Pmode, operands[1]);
11398 (define_expand "restore_stack_nonlocal"
11399 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11400 (set (match_dup 3) (match_dup 4))
11401 (set (match_dup 5) (match_dup 2))
11402 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11403 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11407 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11409 /* Restore the backchain from the first word, sp from the second. */
11410 operands[2] = gen_reg_rtx (Pmode);
11411 operands[3] = gen_reg_rtx (Pmode);
11412 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11413 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11414 operands[5] = gen_frame_mem (Pmode, operands[3]);
11415 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11418 ;; TOC register handling.
11420 ;; Code to initialize the TOC register...
11422 (define_insn "load_toc_aix_si"
11423 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11424 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11425 (use (reg:SI 2))])]
11426 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11430 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11431 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11432 operands[2] = gen_rtx_REG (Pmode, 2);
11433 return \"{l|lwz} %0,%1(%2)\";
11435 [(set_attr "type" "load")])
11437 (define_insn "load_toc_aix_di"
11438 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11439 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11440 (use (reg:DI 2))])]
11441 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11445 #ifdef TARGET_RELOCATABLE
11446 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11447 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11449 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11452 strcat (buf, \"@toc\");
11453 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11454 operands[2] = gen_rtx_REG (Pmode, 2);
11455 return \"ld %0,%1(%2)\";
11457 [(set_attr "type" "load")])
11459 (define_insn "load_toc_v4_pic_si"
11460 [(set (reg:SI LR_REGNO)
11461 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11462 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11463 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11464 [(set_attr "type" "branch")
11465 (set_attr "length" "4")])
11467 (define_insn "load_toc_v4_PIC_1"
11468 [(set (reg:SI LR_REGNO)
11469 (match_operand:SI 0 "immediate_operand" "s"))
11470 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11471 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11472 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11473 "bcl 20,31,%0\\n%0:"
11474 [(set_attr "type" "branch")
11475 (set_attr "length" "4")])
11477 (define_insn "load_toc_v4_PIC_1b"
11478 [(set (reg:SI LR_REGNO)
11479 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
11481 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11482 "bcl 20,31,$+8\\n\\t.long %0-$"
11483 [(set_attr "type" "branch")
11484 (set_attr "length" "8")])
11486 (define_insn "load_toc_v4_PIC_2"
11487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11488 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11489 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11490 (match_operand:SI 3 "immediate_operand" "s")))))]
11491 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11492 "{l|lwz} %0,%2-%3(%1)"
11493 [(set_attr "type" "load")])
11495 (define_insn "load_toc_v4_PIC_3b"
11496 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11497 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11499 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11500 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11501 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11502 "{cau|addis} %0,%1,%2-%3@ha")
11504 (define_insn "load_toc_v4_PIC_3c"
11505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11506 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11507 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11508 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11509 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11510 "{cal|addi} %0,%1,%2-%3@l")
11512 ;; If the TOC is shared over a translation unit, as happens with all
11513 ;; the kinds of PIC that we support, we need to restore the TOC
11514 ;; pointer only when jumping over units of translation.
11515 ;; On Darwin, we need to reload the picbase.
11517 (define_expand "builtin_setjmp_receiver"
11518 [(use (label_ref (match_operand 0 "" "")))]
11519 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11520 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11521 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11525 if (DEFAULT_ABI == ABI_DARWIN)
11527 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11528 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11532 crtl->uses_pic_offset_table = 1;
11533 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11534 CODE_LABEL_NUMBER (operands[0]));
11535 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11537 emit_insn (gen_load_macho_picbase (tmplabrtx));
11538 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11539 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11543 rs6000_emit_load_toc_table (FALSE);
11547 ;; Elf specific ways of loading addresses for non-PIC code.
11548 ;; The output of this could be r0, but we make a very strong
11549 ;; preference for a base register because it will usually
11550 ;; be needed there.
11551 (define_insn "elf_high"
11552 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11553 (high:SI (match_operand 1 "" "")))]
11554 "TARGET_ELF && ! TARGET_64BIT"
11555 "{liu|lis} %0,%1@ha")
11557 (define_insn "elf_low"
11558 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11559 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11560 (match_operand 2 "" "")))]
11561 "TARGET_ELF && ! TARGET_64BIT"
11563 {cal|la} %0,%2@l(%1)
11564 {ai|addic} %0,%1,%K2")
11566 ;; A function pointer under AIX is a pointer to a data area whose first word
11567 ;; contains the actual address of the function, whose second word contains a
11568 ;; pointer to its TOC, and whose third word contains a value to place in the
11569 ;; static chain register (r11). Note that if we load the static chain, our
11570 ;; "trampoline" need not have any executable code.
11572 (define_expand "call_indirect_aix32"
11573 [(set (match_dup 2)
11574 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11575 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11578 (mem:SI (plus:SI (match_dup 0)
11580 (parallel [(call (mem:SI (match_dup 2))
11581 (match_operand 1 "" ""))
11582 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11584 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11585 (clobber (reg:SI LR_REGNO))])]
11588 { operands[2] = gen_reg_rtx (SImode); }")
11590 (define_expand "call_indirect_aix64"
11591 [(set (match_dup 2)
11592 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11593 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11596 (mem:DI (plus:DI (match_dup 0)
11598 (parallel [(call (mem:SI (match_dup 2))
11599 (match_operand 1 "" ""))
11600 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11602 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11603 (clobber (reg:SI LR_REGNO))])]
11606 { operands[2] = gen_reg_rtx (DImode); }")
11608 (define_expand "call_value_indirect_aix32"
11609 [(set (match_dup 3)
11610 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11611 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11614 (mem:SI (plus:SI (match_dup 1)
11616 (parallel [(set (match_operand 0 "" "")
11617 (call (mem:SI (match_dup 3))
11618 (match_operand 2 "" "")))
11619 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11621 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11622 (clobber (reg:SI LR_REGNO))])]
11625 { operands[3] = gen_reg_rtx (SImode); }")
11627 (define_expand "call_value_indirect_aix64"
11628 [(set (match_dup 3)
11629 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11630 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11633 (mem:DI (plus:DI (match_dup 1)
11635 (parallel [(set (match_operand 0 "" "")
11636 (call (mem:SI (match_dup 3))
11637 (match_operand 2 "" "")))
11638 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11640 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11641 (clobber (reg:SI LR_REGNO))])]
11644 { operands[3] = gen_reg_rtx (DImode); }")
11646 ;; Now the definitions for the call and call_value insns
11647 (define_expand "call"
11648 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11649 (match_operand 1 "" ""))
11650 (use (match_operand 2 "" ""))
11651 (clobber (reg:SI LR_REGNO))])]
11656 if (MACHOPIC_INDIRECT)
11657 operands[0] = machopic_indirect_call_target (operands[0]);
11660 gcc_assert (GET_CODE (operands[0]) == MEM);
11661 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11663 operands[0] = XEXP (operands[0], 0);
11665 if (GET_CODE (operands[0]) != SYMBOL_REF
11666 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11667 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11669 if (INTVAL (operands[2]) & CALL_LONG)
11670 operands[0] = rs6000_longcall_ref (operands[0]);
11672 switch (DEFAULT_ABI)
11676 operands[0] = force_reg (Pmode, operands[0]);
11680 /* AIX function pointers are really pointers to a three word
11682 emit_call_insn (TARGET_32BIT
11683 ? gen_call_indirect_aix32 (force_reg (SImode,
11686 : gen_call_indirect_aix64 (force_reg (DImode,
11692 gcc_unreachable ();
11697 (define_expand "call_value"
11698 [(parallel [(set (match_operand 0 "" "")
11699 (call (mem:SI (match_operand 1 "address_operand" ""))
11700 (match_operand 2 "" "")))
11701 (use (match_operand 3 "" ""))
11702 (clobber (reg:SI LR_REGNO))])]
11707 if (MACHOPIC_INDIRECT)
11708 operands[1] = machopic_indirect_call_target (operands[1]);
11711 gcc_assert (GET_CODE (operands[1]) == MEM);
11712 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11714 operands[1] = XEXP (operands[1], 0);
11716 if (GET_CODE (operands[1]) != SYMBOL_REF
11717 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11718 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11720 if (INTVAL (operands[3]) & CALL_LONG)
11721 operands[1] = rs6000_longcall_ref (operands[1]);
11723 switch (DEFAULT_ABI)
11727 operands[1] = force_reg (Pmode, operands[1]);
11731 /* AIX function pointers are really pointers to a three word
11733 emit_call_insn (TARGET_32BIT
11734 ? gen_call_value_indirect_aix32 (operands[0],
11738 : gen_call_value_indirect_aix64 (operands[0],
11745 gcc_unreachable ();
11750 ;; Call to function in current module. No TOC pointer reload needed.
11751 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11752 ;; either the function was not prototyped, or it was prototyped as a
11753 ;; variable argument function. It is > 0 if FP registers were passed
11754 ;; and < 0 if they were not.
11756 (define_insn "*call_local32"
11757 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11758 (match_operand 1 "" "g,g"))
11759 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11760 (clobber (reg:SI LR_REGNO))]
11761 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11764 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11765 output_asm_insn (\"crxor 6,6,6\", operands);
11767 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11768 output_asm_insn (\"creqv 6,6,6\", operands);
11770 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11772 [(set_attr "type" "branch")
11773 (set_attr "length" "4,8")])
11775 (define_insn "*call_local64"
11776 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11777 (match_operand 1 "" "g,g"))
11778 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11779 (clobber (reg:SI LR_REGNO))]
11780 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11783 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11784 output_asm_insn (\"crxor 6,6,6\", operands);
11786 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11787 output_asm_insn (\"creqv 6,6,6\", operands);
11789 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11791 [(set_attr "type" "branch")
11792 (set_attr "length" "4,8")])
11794 (define_insn "*call_value_local32"
11795 [(set (match_operand 0 "" "")
11796 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11797 (match_operand 2 "" "g,g")))
11798 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11799 (clobber (reg:SI LR_REGNO))]
11800 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11803 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11804 output_asm_insn (\"crxor 6,6,6\", operands);
11806 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11807 output_asm_insn (\"creqv 6,6,6\", operands);
11809 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11811 [(set_attr "type" "branch")
11812 (set_attr "length" "4,8")])
11815 (define_insn "*call_value_local64"
11816 [(set (match_operand 0 "" "")
11817 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11818 (match_operand 2 "" "g,g")))
11819 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11820 (clobber (reg:SI LR_REGNO))]
11821 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11824 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11825 output_asm_insn (\"crxor 6,6,6\", operands);
11827 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11828 output_asm_insn (\"creqv 6,6,6\", operands);
11830 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11832 [(set_attr "type" "branch")
11833 (set_attr "length" "4,8")])
11835 ;; Call to function which may be in another module. Restore the TOC
11836 ;; pointer (r2) after the call unless this is System V.
11837 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11838 ;; either the function was not prototyped, or it was prototyped as a
11839 ;; variable argument function. It is > 0 if FP registers were passed
11840 ;; and < 0 if they were not.
11842 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11843 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11844 (match_operand 1 "" "g,g"))
11845 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11847 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11848 (clobber (reg:SI LR_REGNO))]
11849 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11851 "&& reload_completed"
11853 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11854 (parallel [(call (mem:SI (match_dup 0))
11859 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11860 (clobber (reg:SI LR_REGNO))])]
11862 [(set_attr "type" "jmpreg")
11863 (set_attr "length" "12")])
11865 (define_insn "*call_indirect_nonlocal_aix32"
11866 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11867 (match_operand 1 "" "g,g"))
11871 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11872 (clobber (reg:SI LR_REGNO))]
11873 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11874 "b%T0l\;{l|lwz} 2,20(1)"
11875 [(set_attr "type" "jmpreg")
11876 (set_attr "length" "8")])
11878 (define_insn "*call_nonlocal_aix32"
11879 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11880 (match_operand 1 "" "g"))
11881 (use (match_operand:SI 2 "immediate_operand" "O"))
11882 (clobber (reg:SI LR_REGNO))]
11884 && DEFAULT_ABI == ABI_AIX
11885 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11887 [(set_attr "type" "branch")
11888 (set_attr "length" "8")])
11890 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11891 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11892 (match_operand 1 "" "g,g"))
11893 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11896 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11897 (clobber (reg:SI LR_REGNO))]
11898 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11900 "&& reload_completed"
11902 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11903 (parallel [(call (mem:SI (match_dup 0))
11908 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11909 (clobber (reg:SI LR_REGNO))])]
11911 [(set_attr "type" "jmpreg")
11912 (set_attr "length" "12")])
11914 (define_insn "*call_indirect_nonlocal_aix64"
11915 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11916 (match_operand 1 "" "g,g"))
11920 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11921 (clobber (reg:SI LR_REGNO))]
11922 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11923 "b%T0l\;ld 2,40(1)"
11924 [(set_attr "type" "jmpreg")
11925 (set_attr "length" "8")])
11927 (define_insn "*call_nonlocal_aix64"
11928 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11929 (match_operand 1 "" "g"))
11930 (use (match_operand:SI 2 "immediate_operand" "O"))
11931 (clobber (reg:SI LR_REGNO))]
11933 && DEFAULT_ABI == ABI_AIX
11934 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11936 [(set_attr "type" "branch")
11937 (set_attr "length" "8")])
11939 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11940 [(set (match_operand 0 "" "")
11941 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11942 (match_operand 2 "" "g,g")))
11943 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11946 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11947 (clobber (reg:SI LR_REGNO))]
11948 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11950 "&& reload_completed"
11952 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11953 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11958 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11959 (clobber (reg:SI LR_REGNO))])]
11961 [(set_attr "type" "jmpreg")
11962 (set_attr "length" "12")])
11964 (define_insn "*call_value_indirect_nonlocal_aix32"
11965 [(set (match_operand 0 "" "")
11966 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11967 (match_operand 2 "" "g,g")))
11971 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11972 (clobber (reg:SI LR_REGNO))]
11973 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11974 "b%T1l\;{l|lwz} 2,20(1)"
11975 [(set_attr "type" "jmpreg")
11976 (set_attr "length" "8")])
11978 (define_insn "*call_value_nonlocal_aix32"
11979 [(set (match_operand 0 "" "")
11980 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11981 (match_operand 2 "" "g")))
11982 (use (match_operand:SI 3 "immediate_operand" "O"))
11983 (clobber (reg:SI LR_REGNO))]
11985 && DEFAULT_ABI == ABI_AIX
11986 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11988 [(set_attr "type" "branch")
11989 (set_attr "length" "8")])
11991 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11992 [(set (match_operand 0 "" "")
11993 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11994 (match_operand 2 "" "g,g")))
11995 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11998 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11999 (clobber (reg:SI LR_REGNO))]
12000 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12002 "&& reload_completed"
12004 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
12005 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12010 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12011 (clobber (reg:SI LR_REGNO))])]
12013 [(set_attr "type" "jmpreg")
12014 (set_attr "length" "12")])
12016 (define_insn "*call_value_indirect_nonlocal_aix64"
12017 [(set (match_operand 0 "" "")
12018 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12019 (match_operand 2 "" "g,g")))
12023 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12024 (clobber (reg:SI LR_REGNO))]
12025 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12026 "b%T1l\;ld 2,40(1)"
12027 [(set_attr "type" "jmpreg")
12028 (set_attr "length" "8")])
12030 (define_insn "*call_value_nonlocal_aix64"
12031 [(set (match_operand 0 "" "")
12032 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12033 (match_operand 2 "" "g")))
12034 (use (match_operand:SI 3 "immediate_operand" "O"))
12035 (clobber (reg:SI LR_REGNO))]
12037 && DEFAULT_ABI == ABI_AIX
12038 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12040 [(set_attr "type" "branch")
12041 (set_attr "length" "8")])
12043 ;; A function pointer under System V is just a normal pointer
12044 ;; operands[0] is the function pointer
12045 ;; operands[1] is the stack size to clean up
12046 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12047 ;; which indicates how to set cr1
12049 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12050 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12051 (match_operand 1 "" "g,g,g,g"))
12052 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12053 (clobber (reg:SI LR_REGNO))]
12054 "DEFAULT_ABI == ABI_V4
12055 || DEFAULT_ABI == ABI_DARWIN"
12057 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12058 output_asm_insn ("crxor 6,6,6", operands);
12060 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12061 output_asm_insn ("creqv 6,6,6", operands);
12065 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12066 (set_attr "length" "4,4,8,8")])
12068 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12069 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12070 (match_operand 1 "" "g,g"))
12071 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12072 (clobber (reg:SI LR_REGNO))]
12073 "(DEFAULT_ABI == ABI_DARWIN
12074 || (DEFAULT_ABI == ABI_V4
12075 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12077 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12078 output_asm_insn ("crxor 6,6,6", operands);
12080 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12081 output_asm_insn ("creqv 6,6,6", operands);
12084 return output_call(insn, operands, 0, 2);
12086 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12088 gcc_assert (!TARGET_SECURE_PLT);
12089 return "bl %z0@plt";
12095 "DEFAULT_ABI == ABI_V4
12096 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12097 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12098 [(parallel [(call (mem:SI (match_dup 0))
12100 (use (match_dup 2))
12101 (use (match_dup 3))
12102 (clobber (reg:SI LR_REGNO))])]
12104 operands[3] = pic_offset_table_rtx;
12106 [(set_attr "type" "branch,branch")
12107 (set_attr "length" "4,8")])
12109 (define_insn "*call_nonlocal_sysv_secure<mode>"
12110 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12111 (match_operand 1 "" "g,g"))
12112 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12113 (use (match_operand:SI 3 "register_operand" "r,r"))
12114 (clobber (reg:SI LR_REGNO))]
12115 "(DEFAULT_ABI == ABI_V4
12116 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12117 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12119 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12120 output_asm_insn ("crxor 6,6,6", operands);
12122 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12123 output_asm_insn ("creqv 6,6,6", operands);
12126 /* The magic 32768 offset here and in the other sysv call insns
12127 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12128 See sysv4.h:toc_section. */
12129 return "bl %z0+32768@plt";
12131 return "bl %z0@plt";
12133 [(set_attr "type" "branch,branch")
12134 (set_attr "length" "4,8")])
12136 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12137 [(set (match_operand 0 "" "")
12138 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12139 (match_operand 2 "" "g,g,g,g")))
12140 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12141 (clobber (reg:SI LR_REGNO))]
12142 "DEFAULT_ABI == ABI_V4
12143 || DEFAULT_ABI == ABI_DARWIN"
12145 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12146 output_asm_insn ("crxor 6,6,6", operands);
12148 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12149 output_asm_insn ("creqv 6,6,6", operands);
12153 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12154 (set_attr "length" "4,4,8,8")])
12156 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12157 [(set (match_operand 0 "" "")
12158 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12159 (match_operand 2 "" "g,g")))
12160 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12161 (clobber (reg:SI LR_REGNO))]
12162 "(DEFAULT_ABI == ABI_DARWIN
12163 || (DEFAULT_ABI == ABI_V4
12164 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12166 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12167 output_asm_insn ("crxor 6,6,6", operands);
12169 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12170 output_asm_insn ("creqv 6,6,6", operands);
12173 return output_call(insn, operands, 1, 3);
12175 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12177 gcc_assert (!TARGET_SECURE_PLT);
12178 return "bl %z1@plt";
12184 "DEFAULT_ABI == ABI_V4
12185 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12186 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12187 [(parallel [(set (match_dup 0)
12188 (call (mem:SI (match_dup 1))
12190 (use (match_dup 3))
12191 (use (match_dup 4))
12192 (clobber (reg:SI LR_REGNO))])]
12194 operands[4] = pic_offset_table_rtx;
12196 [(set_attr "type" "branch,branch")
12197 (set_attr "length" "4,8")])
12199 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12200 [(set (match_operand 0 "" "")
12201 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12202 (match_operand 2 "" "g,g")))
12203 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12204 (use (match_operand:SI 4 "register_operand" "r,r"))
12205 (clobber (reg:SI LR_REGNO))]
12206 "(DEFAULT_ABI == ABI_V4
12207 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12208 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12210 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12211 output_asm_insn ("crxor 6,6,6", operands);
12213 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12214 output_asm_insn ("creqv 6,6,6", operands);
12217 return "bl %z1+32768@plt";
12219 return "bl %z1@plt";
12221 [(set_attr "type" "branch,branch")
12222 (set_attr "length" "4,8")])
12224 ;; Call subroutine returning any type.
12225 (define_expand "untyped_call"
12226 [(parallel [(call (match_operand 0 "" "")
12228 (match_operand 1 "" "")
12229 (match_operand 2 "" "")])]
12235 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12237 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12239 rtx set = XVECEXP (operands[2], 0, i);
12240 emit_move_insn (SET_DEST (set), SET_SRC (set));
12243 /* The optimizer does not know that the call sets the function value
12244 registers we stored in the result block. We avoid problems by
12245 claiming that all hard registers are used and clobbered at this
12247 emit_insn (gen_blockage ());
12252 ;; sibling call patterns
12253 (define_expand "sibcall"
12254 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12255 (match_operand 1 "" ""))
12256 (use (match_operand 2 "" ""))
12257 (use (reg:SI LR_REGNO))
12263 if (MACHOPIC_INDIRECT)
12264 operands[0] = machopic_indirect_call_target (operands[0]);
12267 gcc_assert (GET_CODE (operands[0]) == MEM);
12268 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12270 operands[0] = XEXP (operands[0], 0);
12273 ;; this and similar patterns must be marked as using LR, otherwise
12274 ;; dataflow will try to delete the store into it. This is true
12275 ;; even when the actual reg to jump to is in CTR, when LR was
12276 ;; saved and restored around the PIC-setting BCL.
12277 (define_insn "*sibcall_local32"
12278 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12279 (match_operand 1 "" "g,g"))
12280 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12281 (use (reg:SI LR_REGNO))
12283 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12286 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12287 output_asm_insn (\"crxor 6,6,6\", operands);
12289 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12290 output_asm_insn (\"creqv 6,6,6\", operands);
12292 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12294 [(set_attr "type" "branch")
12295 (set_attr "length" "4,8")])
12297 (define_insn "*sibcall_local64"
12298 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12299 (match_operand 1 "" "g,g"))
12300 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12301 (use (reg:SI LR_REGNO))
12303 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12306 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12307 output_asm_insn (\"crxor 6,6,6\", operands);
12309 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12310 output_asm_insn (\"creqv 6,6,6\", operands);
12312 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12314 [(set_attr "type" "branch")
12315 (set_attr "length" "4,8")])
12317 (define_insn "*sibcall_value_local32"
12318 [(set (match_operand 0 "" "")
12319 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12320 (match_operand 2 "" "g,g")))
12321 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12322 (use (reg:SI LR_REGNO))
12324 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12327 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12328 output_asm_insn (\"crxor 6,6,6\", operands);
12330 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12331 output_asm_insn (\"creqv 6,6,6\", operands);
12333 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12335 [(set_attr "type" "branch")
12336 (set_attr "length" "4,8")])
12339 (define_insn "*sibcall_value_local64"
12340 [(set (match_operand 0 "" "")
12341 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12342 (match_operand 2 "" "g,g")))
12343 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12344 (use (reg:SI LR_REGNO))
12346 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12349 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12350 output_asm_insn (\"crxor 6,6,6\", operands);
12352 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12353 output_asm_insn (\"creqv 6,6,6\", operands);
12355 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12357 [(set_attr "type" "branch")
12358 (set_attr "length" "4,8")])
12360 (define_insn "*sibcall_nonlocal_aix32"
12361 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12362 (match_operand 1 "" "g"))
12363 (use (match_operand:SI 2 "immediate_operand" "O"))
12364 (use (reg:SI LR_REGNO))
12367 && DEFAULT_ABI == ABI_AIX
12368 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12370 [(set_attr "type" "branch")
12371 (set_attr "length" "4")])
12373 (define_insn "*sibcall_nonlocal_aix64"
12374 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12375 (match_operand 1 "" "g"))
12376 (use (match_operand:SI 2 "immediate_operand" "O"))
12377 (use (reg:SI LR_REGNO))
12380 && DEFAULT_ABI == ABI_AIX
12381 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12383 [(set_attr "type" "branch")
12384 (set_attr "length" "4")])
12386 (define_insn "*sibcall_value_nonlocal_aix32"
12387 [(set (match_operand 0 "" "")
12388 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12389 (match_operand 2 "" "g")))
12390 (use (match_operand:SI 3 "immediate_operand" "O"))
12391 (use (reg:SI LR_REGNO))
12394 && DEFAULT_ABI == ABI_AIX
12395 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12397 [(set_attr "type" "branch")
12398 (set_attr "length" "4")])
12400 (define_insn "*sibcall_value_nonlocal_aix64"
12401 [(set (match_operand 0 "" "")
12402 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12403 (match_operand 2 "" "g")))
12404 (use (match_operand:SI 3 "immediate_operand" "O"))
12405 (use (reg:SI LR_REGNO))
12408 && DEFAULT_ABI == ABI_AIX
12409 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12411 [(set_attr "type" "branch")
12412 (set_attr "length" "4")])
12414 (define_insn "*sibcall_nonlocal_sysv<mode>"
12415 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12416 (match_operand 1 "" ""))
12417 (use (match_operand 2 "immediate_operand" "O,n"))
12418 (use (reg:SI LR_REGNO))
12420 "(DEFAULT_ABI == ABI_DARWIN
12421 || DEFAULT_ABI == ABI_V4)
12422 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12425 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12426 output_asm_insn (\"crxor 6,6,6\", operands);
12428 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12429 output_asm_insn (\"creqv 6,6,6\", operands);
12431 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12433 gcc_assert (!TARGET_SECURE_PLT);
12434 return \"b %z0@plt\";
12439 [(set_attr "type" "branch,branch")
12440 (set_attr "length" "4,8")])
12442 (define_expand "sibcall_value"
12443 [(parallel [(set (match_operand 0 "register_operand" "")
12444 (call (mem:SI (match_operand 1 "address_operand" ""))
12445 (match_operand 2 "" "")))
12446 (use (match_operand 3 "" ""))
12447 (use (reg:SI LR_REGNO))
12453 if (MACHOPIC_INDIRECT)
12454 operands[1] = machopic_indirect_call_target (operands[1]);
12457 gcc_assert (GET_CODE (operands[1]) == MEM);
12458 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12460 operands[1] = XEXP (operands[1], 0);
12463 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12464 [(set (match_operand 0 "" "")
12465 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12466 (match_operand 2 "" "")))
12467 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12468 (use (reg:SI LR_REGNO))
12470 "(DEFAULT_ABI == ABI_DARWIN
12471 || DEFAULT_ABI == ABI_V4)
12472 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12475 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12476 output_asm_insn (\"crxor 6,6,6\", operands);
12478 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12479 output_asm_insn (\"creqv 6,6,6\", operands);
12481 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12483 gcc_assert (!TARGET_SECURE_PLT);
12484 return \"b %z1@plt\";
12489 [(set_attr "type" "branch,branch")
12490 (set_attr "length" "4,8")])
12492 (define_expand "sibcall_epilogue"
12493 [(use (const_int 0))]
12494 "TARGET_SCHED_PROLOG"
12497 rs6000_emit_epilogue (TRUE);
12501 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12502 ;; all of memory. This blocks insns from being moved across this point.
12504 (define_insn "blockage"
12505 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12509 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12510 ;; signed & unsigned, and one type of branch.
12512 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12513 ;; insns, and branches.
12515 (define_expand "cbranch<mode>4"
12516 [(use (match_operator 0 "rs6000_cbranch_operator"
12517 [(match_operand:GPR 1 "gpc_reg_operand" "")
12518 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12519 (use (match_operand 3 ""))]
12523 /* Take care of the possibility that operands[2] might be negative but
12524 this might be a logical operation. That insn doesn't exist. */
12525 if (GET_CODE (operands[2]) == CONST_INT
12526 && INTVAL (operands[2]) < 0)
12528 operands[2] = force_reg (<MODE>mode, operands[2]);
12529 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12530 GET_MODE (operands[0]),
12531 operands[1], operands[2]);
12534 rs6000_emit_cbranch (<MODE>mode, operands);
12538 (define_expand "cbranch<mode>4"
12539 [(use (match_operator 0 "rs6000_cbranch_operator"
12540 [(match_operand:FP 1 "gpc_reg_operand" "")
12541 (match_operand:FP 2 "gpc_reg_operand" "")]))
12542 (use (match_operand 3 ""))]
12546 rs6000_emit_cbranch (<MODE>mode, operands);
12550 (define_expand "cstore<mode>4"
12551 [(use (match_operator 1 "rs6000_cbranch_operator"
12552 [(match_operand:GPR 2 "gpc_reg_operand" "")
12553 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12554 (clobber (match_operand:SI 0 "register_operand"))]
12558 /* Take care of the possibility that operands[3] might be negative but
12559 this might be a logical operation. That insn doesn't exist. */
12560 if (GET_CODE (operands[3]) == CONST_INT
12561 && INTVAL (operands[3]) < 0)
12563 operands[3] = force_reg (<MODE>mode, operands[3]);
12564 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12565 GET_MODE (operands[1]),
12566 operands[2], operands[3]);
12569 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12570 For SEQ, likewise, except that comparisons with zero should be done
12571 with an scc insns. However, due to the order that combine see the
12572 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12573 the cases we don't want to handle or are best handled by portable
12575 if (GET_CODE (operands[1]) == NE)
12577 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12578 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12579 && operands[3] == const0_rtx)
12581 rs6000_emit_sCOND (<MODE>mode, operands);
12585 (define_expand "cstore<mode>4"
12586 [(use (match_operator 1 "rs6000_cbranch_operator"
12587 [(match_operand:FP 2 "gpc_reg_operand" "")
12588 (match_operand:FP 3 "gpc_reg_operand" "")]))
12589 (clobber (match_operand:SI 0 "register_operand"))]
12593 rs6000_emit_sCOND (<MODE>mode, operands);
12598 (define_expand "stack_protect_set"
12599 [(match_operand 0 "memory_operand" "")
12600 (match_operand 1 "memory_operand" "")]
12603 #ifdef TARGET_THREAD_SSP_OFFSET
12604 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12605 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12606 operands[1] = gen_rtx_MEM (Pmode, addr);
12609 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12611 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12615 (define_insn "stack_protect_setsi"
12616 [(set (match_operand:SI 0 "memory_operand" "=m")
12617 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12618 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12620 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12621 [(set_attr "type" "three")
12622 (set_attr "length" "12")])
12624 (define_insn "stack_protect_setdi"
12625 [(set (match_operand:DI 0 "memory_operand" "=m")
12626 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12627 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12629 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12630 [(set_attr "type" "three")
12631 (set_attr "length" "12")])
12633 (define_expand "stack_protect_test"
12634 [(match_operand 0 "memory_operand" "")
12635 (match_operand 1 "memory_operand" "")
12636 (match_operand 2 "" "")]
12639 rtx test, op0, op1;
12640 #ifdef TARGET_THREAD_SSP_OFFSET
12641 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12642 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12643 operands[1] = gen_rtx_MEM (Pmode, addr);
12646 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12647 test = gen_rtx_EQ (VOIDmode, op0, op1);
12648 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12652 (define_insn "stack_protect_testsi"
12653 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12654 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12655 (match_operand:SI 2 "memory_operand" "m,m")]
12657 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12658 (clobber (match_scratch:SI 3 "=&r,&r"))]
12661 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12662 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12663 [(set_attr "length" "16,20")])
12665 (define_insn "stack_protect_testdi"
12666 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12667 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12668 (match_operand:DI 2 "memory_operand" "m,m")]
12670 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12671 (clobber (match_scratch:DI 3 "=&r,&r"))]
12674 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12675 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12676 [(set_attr "length" "16,20")])
12679 ;; Here are the actual compare insns.
12680 (define_insn "*cmp<mode>_internal1"
12681 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12682 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12683 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12685 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12686 [(set_attr "type" "cmp")])
12688 ;; If we are comparing a register for equality with a large constant,
12689 ;; we can do this with an XOR followed by a compare. But this is profitable
12690 ;; only if the large constant is only used for the comparison (and in this
12691 ;; case we already have a register to reuse as scratch).
12693 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12694 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12697 [(set (match_operand:SI 0 "register_operand")
12698 (match_operand:SI 1 "logical_const_operand" ""))
12699 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12701 (match_operand:SI 2 "logical_const_operand" "")]))
12702 (set (match_operand:CC 4 "cc_reg_operand" "")
12703 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12706 (if_then_else (match_operator 6 "equality_operator"
12707 [(match_dup 4) (const_int 0)])
12708 (match_operand 7 "" "")
12709 (match_operand 8 "" "")))]
12710 "peep2_reg_dead_p (3, operands[0])
12711 && peep2_reg_dead_p (4, operands[4])"
12712 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12713 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12714 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12717 /* Get the constant we are comparing against, and see what it looks like
12718 when sign-extended from 16 to 32 bits. Then see what constant we could
12719 XOR with SEXTC to get the sign-extended value. */
12720 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12722 operands[1], operands[2]);
12723 HOST_WIDE_INT c = INTVAL (cnst);
12724 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12725 HOST_WIDE_INT xorv = c ^ sextc;
12727 operands[9] = GEN_INT (xorv);
12728 operands[10] = GEN_INT (sextc);
12731 (define_insn "*cmpsi_internal2"
12732 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12733 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12734 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12736 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12737 [(set_attr "type" "cmp")])
12739 (define_insn "*cmpdi_internal2"
12740 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12741 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12742 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12744 "cmpld%I2 %0,%1,%b2"
12745 [(set_attr "type" "cmp")])
12747 ;; The following two insns don't exist as single insns, but if we provide
12748 ;; them, we can swap an add and compare, which will enable us to overlap more
12749 ;; of the required delay between a compare and branch. We generate code for
12750 ;; them by splitting.
12753 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12754 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12755 (match_operand:SI 2 "short_cint_operand" "i")))
12756 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12757 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12760 [(set_attr "length" "8")])
12763 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12764 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12765 (match_operand:SI 2 "u_short_cint_operand" "i")))
12766 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12767 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12770 [(set_attr "length" "8")])
12773 [(set (match_operand:CC 3 "cc_reg_operand" "")
12774 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12775 (match_operand:SI 2 "short_cint_operand" "")))
12776 (set (match_operand:SI 0 "gpc_reg_operand" "")
12777 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12779 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12780 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12783 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12784 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12785 (match_operand:SI 2 "u_short_cint_operand" "")))
12786 (set (match_operand:SI 0 "gpc_reg_operand" "")
12787 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12789 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12790 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12792 (define_insn "*cmpsf_internal1"
12793 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12794 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12795 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12796 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12798 [(set_attr "type" "fpcompare")])
12800 (define_insn "*cmpdf_internal1"
12801 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12802 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12803 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12804 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12805 && !VECTOR_UNIT_VSX_P (DFmode)"
12807 [(set_attr "type" "fpcompare")])
12809 ;; Only need to compare second words if first words equal
12810 (define_insn "*cmptf_internal1"
12811 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12812 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12813 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12814 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12815 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12816 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12817 [(set_attr "type" "fpcompare")
12818 (set_attr "length" "12")])
12820 (define_insn_and_split "*cmptf_internal2"
12821 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12822 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12823 (match_operand:TF 2 "gpc_reg_operand" "d")))
12824 (clobber (match_scratch:DF 3 "=d"))
12825 (clobber (match_scratch:DF 4 "=d"))
12826 (clobber (match_scratch:DF 5 "=d"))
12827 (clobber (match_scratch:DF 6 "=d"))
12828 (clobber (match_scratch:DF 7 "=d"))
12829 (clobber (match_scratch:DF 8 "=d"))
12830 (clobber (match_scratch:DF 9 "=d"))
12831 (clobber (match_scratch:DF 10 "=d"))]
12832 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12833 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12835 "&& reload_completed"
12836 [(set (match_dup 3) (match_dup 13))
12837 (set (match_dup 4) (match_dup 14))
12838 (set (match_dup 9) (abs:DF (match_dup 5)))
12839 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12840 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12841 (label_ref (match_dup 11))
12843 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12844 (set (pc) (label_ref (match_dup 12)))
12846 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12847 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12848 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12849 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12852 REAL_VALUE_TYPE rv;
12853 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12854 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12856 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12857 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12858 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12859 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12860 operands[11] = gen_label_rtx ();
12861 operands[12] = gen_label_rtx ();
12863 operands[13] = force_const_mem (DFmode,
12864 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12865 operands[14] = force_const_mem (DFmode,
12866 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12870 operands[13] = gen_const_mem (DFmode,
12871 create_TOC_reference (XEXP (operands[13], 0)));
12872 operands[14] = gen_const_mem (DFmode,
12873 create_TOC_reference (XEXP (operands[14], 0)));
12874 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12875 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12879 ;; Now we have the scc insns. We can do some combinations because of the
12880 ;; way the machine works.
12882 ;; Note that this is probably faster if we can put an insn between the
12883 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12884 ;; cases the insns below which don't use an intermediate CR field will
12885 ;; be used instead.
12887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12888 (match_operator:SI 1 "scc_comparison_operator"
12889 [(match_operand 2 "cc_reg_operand" "y")
12892 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12893 [(set (attr "type")
12894 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12895 (const_string "mfcrf")
12897 (const_string "mfcr")))
12898 (set_attr "length" "8")])
12900 ;; Same as above, but get the GT bit.
12901 (define_insn "move_from_CR_gt_bit"
12902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12903 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12904 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12905 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12906 [(set_attr "type" "mfcr")
12907 (set_attr "length" "8")])
12909 ;; Same as above, but get the OV/ORDERED bit.
12910 (define_insn "move_from_CR_ov_bit"
12911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12912 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12914 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12915 [(set_attr "type" "mfcr")
12916 (set_attr "length" "8")])
12919 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12920 (match_operator:DI 1 "scc_comparison_operator"
12921 [(match_operand 2 "cc_reg_operand" "y")
12924 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12925 [(set (attr "type")
12926 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12927 (const_string "mfcrf")
12929 (const_string "mfcr")))
12930 (set_attr "length" "8")])
12933 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12934 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12935 [(match_operand 2 "cc_reg_operand" "y,y")
12938 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12939 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12942 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12944 [(set_attr "type" "delayed_compare")
12945 (set_attr "length" "8,16")])
12948 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12949 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12950 [(match_operand 2 "cc_reg_operand" "")
12953 (set (match_operand:SI 3 "gpc_reg_operand" "")
12954 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12955 "TARGET_32BIT && reload_completed"
12956 [(set (match_dup 3)
12957 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12959 (compare:CC (match_dup 3)
12964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12965 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12966 [(match_operand 2 "cc_reg_operand" "y")
12968 (match_operand:SI 3 "const_int_operand" "n")))]
12972 int is_bit = ccr_bit (operands[1], 1);
12973 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12976 if (is_bit >= put_bit)
12977 count = is_bit - put_bit;
12979 count = 32 - (put_bit - is_bit);
12981 operands[4] = GEN_INT (count);
12982 operands[5] = GEN_INT (put_bit);
12984 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12986 [(set (attr "type")
12987 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12988 (const_string "mfcrf")
12990 (const_string "mfcr")))
12991 (set_attr "length" "8")])
12994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12996 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12997 [(match_operand 2 "cc_reg_operand" "y,y")
12999 (match_operand:SI 3 "const_int_operand" "n,n"))
13001 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13002 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13007 int is_bit = ccr_bit (operands[1], 1);
13008 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13011 /* Force split for non-cc0 compare. */
13012 if (which_alternative == 1)
13015 if (is_bit >= put_bit)
13016 count = is_bit - put_bit;
13018 count = 32 - (put_bit - is_bit);
13020 operands[5] = GEN_INT (count);
13021 operands[6] = GEN_INT (put_bit);
13023 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13025 [(set_attr "type" "delayed_compare")
13026 (set_attr "length" "8,16")])
13029 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13031 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13032 [(match_operand 2 "cc_reg_operand" "")
13034 (match_operand:SI 3 "const_int_operand" ""))
13036 (set (match_operand:SI 4 "gpc_reg_operand" "")
13037 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13040 [(set (match_dup 4)
13041 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13044 (compare:CC (match_dup 4)
13048 ;; There is a 3 cycle delay between consecutive mfcr instructions
13049 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13053 (match_operator:SI 1 "scc_comparison_operator"
13054 [(match_operand 2 "cc_reg_operand" "y")
13056 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13057 (match_operator:SI 4 "scc_comparison_operator"
13058 [(match_operand 5 "cc_reg_operand" "y")
13060 "REGNO (operands[2]) != REGNO (operands[5])"
13061 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13062 [(set_attr "type" "mfcr")
13063 (set_attr "length" "12")])
13066 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13067 (match_operator:DI 1 "scc_comparison_operator"
13068 [(match_operand 2 "cc_reg_operand" "y")
13070 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13071 (match_operator:DI 4 "scc_comparison_operator"
13072 [(match_operand 5 "cc_reg_operand" "y")
13074 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13075 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13076 [(set_attr "type" "mfcr")
13077 (set_attr "length" "12")])
13079 ;; There are some scc insns that can be done directly, without a compare.
13080 ;; These are faster because they don't involve the communications between
13081 ;; the FXU and branch units. In fact, we will be replacing all of the
13082 ;; integer scc insns here or in the portable methods in emit_store_flag.
13084 ;; Also support (neg (scc ..)) since that construct is used to replace
13085 ;; branches, (plus (scc ..) ..) since that construct is common and
13086 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13087 ;; cases where it is no more expensive than (neg (scc ..)).
13089 ;; Have reload force a constant into a register for the simple insns that
13090 ;; otherwise won't accept constants. We do this because it is faster than
13091 ;; the cmp/mfcr sequence we would otherwise generate.
13093 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13096 (define_insn_and_split "*eq<mode>"
13097 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13098 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13099 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13103 [(set (match_dup 0)
13104 (clz:GPR (match_dup 3)))
13106 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13108 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13110 /* Use output operand as intermediate. */
13111 operands[3] = operands[0];
13113 if (logical_operand (operands[2], <MODE>mode))
13114 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13115 gen_rtx_XOR (<MODE>mode,
13116 operands[1], operands[2])));
13118 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13119 gen_rtx_PLUS (<MODE>mode, operands[1],
13120 negate_rtx (<MODE>mode,
13124 operands[3] = operands[1];
13126 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13129 (define_insn_and_split "*eq<mode>_compare"
13130 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13132 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13133 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13135 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13136 (eq:P (match_dup 1) (match_dup 2)))]
13137 "!TARGET_POWER && optimize_size"
13139 "!TARGET_POWER && optimize_size"
13140 [(set (match_dup 0)
13141 (clz:P (match_dup 4)))
13142 (parallel [(set (match_dup 3)
13143 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13146 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13148 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13150 /* Use output operand as intermediate. */
13151 operands[4] = operands[0];
13153 if (logical_operand (operands[2], <MODE>mode))
13154 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13155 gen_rtx_XOR (<MODE>mode,
13156 operands[1], operands[2])));
13158 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13159 gen_rtx_PLUS (<MODE>mode, operands[1],
13160 negate_rtx (<MODE>mode,
13164 operands[4] = operands[1];
13166 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13169 (define_insn "*eqsi_power"
13170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13171 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13172 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13173 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13176 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13177 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13178 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13179 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13180 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13181 [(set_attr "type" "three,two,three,three,three")
13182 (set_attr "length" "12,8,12,12,12")])
13184 ;; We have insns of the form shown by the first define_insn below. If
13185 ;; there is something inside the comparison operation, we must split it.
13187 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13188 (plus:SI (match_operator 1 "comparison_operator"
13189 [(match_operand:SI 2 "" "")
13190 (match_operand:SI 3
13191 "reg_or_cint_operand" "")])
13192 (match_operand:SI 4 "gpc_reg_operand" "")))
13193 (clobber (match_operand:SI 5 "register_operand" ""))]
13194 "! gpc_reg_operand (operands[2], SImode)"
13195 [(set (match_dup 5) (match_dup 2))
13196 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13199 (define_insn "*plus_eqsi"
13200 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13201 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13202 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13203 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13206 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13207 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13208 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13209 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13210 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13211 [(set_attr "type" "three,two,three,three,three")
13212 (set_attr "length" "12,8,12,12,12")])
13214 (define_insn "*compare_plus_eqsi"
13215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13218 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13219 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13220 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13222 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13223 "TARGET_32BIT && optimize_size"
13225 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13226 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13227 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13228 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13229 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13235 [(set_attr "type" "compare")
13236 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13242 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13243 (match_operand:SI 2 "scc_eq_operand" ""))
13244 (match_operand:SI 3 "gpc_reg_operand" ""))
13246 (clobber (match_scratch:SI 4 ""))]
13247 "TARGET_32BIT && optimize_size && reload_completed"
13248 [(set (match_dup 4)
13249 (plus:SI (eq:SI (match_dup 1)
13253 (compare:CC (match_dup 4)
13257 (define_insn "*plus_eqsi_compare"
13258 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13261 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13262 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13263 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13265 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13266 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13267 "TARGET_32BIT && optimize_size"
13269 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13270 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13271 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13272 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13273 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13279 [(set_attr "type" "compare")
13280 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13283 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13286 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13287 (match_operand:SI 2 "scc_eq_operand" ""))
13288 (match_operand:SI 3 "gpc_reg_operand" ""))
13290 (set (match_operand:SI 0 "gpc_reg_operand" "")
13291 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13292 "TARGET_32BIT && optimize_size && reload_completed"
13293 [(set (match_dup 0)
13294 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13296 (compare:CC (match_dup 0)
13300 (define_insn "*neg_eq0<mode>"
13301 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13302 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13305 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13306 [(set_attr "type" "two")
13307 (set_attr "length" "8")])
13309 (define_insn_and_split "*neg_eq<mode>"
13310 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13311 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13312 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13316 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13318 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13320 /* Use output operand as intermediate. */
13321 operands[3] = operands[0];
13323 if (logical_operand (operands[2], <MODE>mode))
13324 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13325 gen_rtx_XOR (<MODE>mode,
13326 operands[1], operands[2])));
13328 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13329 gen_rtx_PLUS (<MODE>mode, operands[1],
13330 negate_rtx (<MODE>mode,
13334 operands[3] = operands[1];
13337 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13338 ;; since it nabs/sr is just as fast.
13339 (define_insn "*ne0si"
13340 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13341 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13343 (clobber (match_scratch:SI 2 "=&r"))]
13344 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13345 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13346 [(set_attr "type" "two")
13347 (set_attr "length" "8")])
13349 (define_insn "*ne0di"
13350 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13351 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13353 (clobber (match_scratch:DI 2 "=&r"))]
13355 "addic %2,%1,-1\;subfe %0,%2,%1"
13356 [(set_attr "type" "two")
13357 (set_attr "length" "8")])
13359 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13360 (define_insn "*plus_ne0si"
13361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13362 (plus:SI (lshiftrt:SI
13363 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13365 (match_operand:SI 2 "gpc_reg_operand" "r")))
13366 (clobber (match_scratch:SI 3 "=&r"))]
13368 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13369 [(set_attr "type" "two")
13370 (set_attr "length" "8")])
13372 (define_insn "*plus_ne0di"
13373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13374 (plus:DI (lshiftrt:DI
13375 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13377 (match_operand:DI 2 "gpc_reg_operand" "r")))
13378 (clobber (match_scratch:DI 3 "=&r"))]
13380 "addic %3,%1,-1\;addze %0,%2"
13381 [(set_attr "type" "two")
13382 (set_attr "length" "8")])
13384 (define_insn "*compare_plus_ne0si"
13385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13387 (plus:SI (lshiftrt:SI
13388 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13390 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13392 (clobber (match_scratch:SI 3 "=&r,&r"))
13393 (clobber (match_scratch:SI 4 "=X,&r"))]
13396 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13398 [(set_attr "type" "compare")
13399 (set_attr "length" "8,12")])
13402 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13404 (plus:SI (lshiftrt:SI
13405 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13407 (match_operand:SI 2 "gpc_reg_operand" ""))
13409 (clobber (match_scratch:SI 3 ""))
13410 (clobber (match_scratch:SI 4 ""))]
13411 "TARGET_32BIT && reload_completed"
13412 [(parallel [(set (match_dup 3)
13413 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13416 (clobber (match_dup 4))])
13418 (compare:CC (match_dup 3)
13422 (define_insn "*compare_plus_ne0di"
13423 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13425 (plus:DI (lshiftrt:DI
13426 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13428 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13430 (clobber (match_scratch:DI 3 "=&r,&r"))]
13433 addic %3,%1,-1\;addze. %3,%2
13435 [(set_attr "type" "compare")
13436 (set_attr "length" "8,12")])
13439 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13441 (plus:DI (lshiftrt:DI
13442 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13444 (match_operand:DI 2 "gpc_reg_operand" ""))
13446 (clobber (match_scratch:DI 3 ""))]
13447 "TARGET_64BIT && reload_completed"
13448 [(set (match_dup 3)
13449 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13453 (compare:CC (match_dup 3)
13457 (define_insn "*plus_ne0si_compare"
13458 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13460 (plus:SI (lshiftrt:SI
13461 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13463 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13465 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13466 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13468 (clobber (match_scratch:SI 3 "=&r,&r"))]
13471 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13473 [(set_attr "type" "compare")
13474 (set_attr "length" "8,12")])
13477 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13479 (plus:SI (lshiftrt:SI
13480 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13482 (match_operand:SI 2 "gpc_reg_operand" ""))
13484 (set (match_operand:SI 0 "gpc_reg_operand" "")
13485 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13487 (clobber (match_scratch:SI 3 ""))]
13488 "TARGET_32BIT && reload_completed"
13489 [(parallel [(set (match_dup 0)
13490 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13492 (clobber (match_dup 3))])
13494 (compare:CC (match_dup 0)
13498 (define_insn "*plus_ne0di_compare"
13499 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13501 (plus:DI (lshiftrt:DI
13502 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13504 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13506 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13507 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13509 (clobber (match_scratch:DI 3 "=&r,&r"))]
13512 addic %3,%1,-1\;addze. %0,%2
13514 [(set_attr "type" "compare")
13515 (set_attr "length" "8,12")])
13518 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13520 (plus:DI (lshiftrt:DI
13521 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13523 (match_operand:DI 2 "gpc_reg_operand" ""))
13525 (set (match_operand:DI 0 "gpc_reg_operand" "")
13526 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13528 (clobber (match_scratch:DI 3 ""))]
13529 "TARGET_64BIT && reload_completed"
13530 [(parallel [(set (match_dup 0)
13531 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13533 (clobber (match_dup 3))])
13535 (compare:CC (match_dup 0)
13540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13541 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13542 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13543 (clobber (match_scratch:SI 3 "=r,X"))]
13546 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13547 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13548 [(set_attr "length" "12")])
13551 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13553 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13554 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13556 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13557 (le:SI (match_dup 1) (match_dup 2)))
13558 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13561 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13562 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13565 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13566 (set_attr "length" "12,12,16,16")])
13569 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13571 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13572 (match_operand:SI 2 "reg_or_short_operand" ""))
13574 (set (match_operand:SI 0 "gpc_reg_operand" "")
13575 (le:SI (match_dup 1) (match_dup 2)))
13576 (clobber (match_scratch:SI 3 ""))]
13577 "TARGET_POWER && reload_completed"
13578 [(parallel [(set (match_dup 0)
13579 (le:SI (match_dup 1) (match_dup 2)))
13580 (clobber (match_dup 3))])
13582 (compare:CC (match_dup 0)
13587 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13588 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13589 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13590 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13593 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13594 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13595 [(set_attr "length" "12")])
13598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13600 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13601 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13602 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13604 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13607 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13608 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13611 [(set_attr "type" "compare")
13612 (set_attr "length" "12,12,16,16")])
13615 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13617 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13618 (match_operand:SI 2 "reg_or_short_operand" ""))
13619 (match_operand:SI 3 "gpc_reg_operand" ""))
13621 (clobber (match_scratch:SI 4 ""))]
13622 "TARGET_POWER && reload_completed"
13623 [(set (match_dup 4)
13624 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13627 (compare:CC (match_dup 4)
13632 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13634 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13635 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13636 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13638 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13639 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13642 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13643 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13646 [(set_attr "type" "compare")
13647 (set_attr "length" "12,12,16,16")])
13650 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13652 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13653 (match_operand:SI 2 "reg_or_short_operand" ""))
13654 (match_operand:SI 3 "gpc_reg_operand" ""))
13656 (set (match_operand:SI 0 "gpc_reg_operand" "")
13657 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13658 "TARGET_POWER && reload_completed"
13659 [(set (match_dup 0)
13660 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13662 (compare:CC (match_dup 0)
13667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13668 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13669 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13672 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13673 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13674 [(set_attr "length" "12")])
13676 (define_insn "*leu<mode>"
13677 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13678 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13679 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13681 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13682 [(set_attr "type" "three")
13683 (set_attr "length" "12")])
13685 (define_insn "*leu<mode>_compare"
13686 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13688 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13689 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13691 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13692 (leu:P (match_dup 1) (match_dup 2)))]
13695 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13697 [(set_attr "type" "compare")
13698 (set_attr "length" "12,16")])
13701 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13703 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13704 (match_operand:P 2 "reg_or_short_operand" ""))
13706 (set (match_operand:P 0 "gpc_reg_operand" "")
13707 (leu:P (match_dup 1) (match_dup 2)))]
13709 [(set (match_dup 0)
13710 (leu:P (match_dup 1) (match_dup 2)))
13712 (compare:CC (match_dup 0)
13716 (define_insn "*plus_leu<mode>"
13717 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13718 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13719 (match_operand:P 2 "reg_or_short_operand" "rI"))
13720 (match_operand:P 3 "gpc_reg_operand" "r")))]
13722 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13723 [(set_attr "type" "two")
13724 (set_attr "length" "8")])
13727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13729 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13730 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13731 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13733 (clobber (match_scratch:SI 4 "=&r,&r"))]
13736 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13738 [(set_attr "type" "compare")
13739 (set_attr "length" "8,12")])
13742 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13744 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13745 (match_operand:SI 2 "reg_or_short_operand" ""))
13746 (match_operand:SI 3 "gpc_reg_operand" ""))
13748 (clobber (match_scratch:SI 4 ""))]
13749 "TARGET_32BIT && reload_completed"
13750 [(set (match_dup 4)
13751 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13754 (compare:CC (match_dup 4)
13759 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13761 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13762 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13763 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13765 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13766 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13769 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13771 [(set_attr "type" "compare")
13772 (set_attr "length" "8,12")])
13775 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13777 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13778 (match_operand:SI 2 "reg_or_short_operand" ""))
13779 (match_operand:SI 3 "gpc_reg_operand" ""))
13781 (set (match_operand:SI 0 "gpc_reg_operand" "")
13782 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13783 "TARGET_32BIT && reload_completed"
13784 [(set (match_dup 0)
13785 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13787 (compare:CC (match_dup 0)
13791 (define_insn "*neg_leu<mode>"
13792 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13793 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13794 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13796 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13797 [(set_attr "type" "three")
13798 (set_attr "length" "12")])
13800 (define_insn "*and_neg_leu<mode>"
13801 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13803 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13804 (match_operand:P 2 "reg_or_short_operand" "rI")))
13805 (match_operand:P 3 "gpc_reg_operand" "r")))]
13807 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13808 [(set_attr "type" "three")
13809 (set_attr "length" "12")])
13812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13815 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13816 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13817 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13819 (clobber (match_scratch:SI 4 "=&r,&r"))]
13822 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13824 [(set_attr "type" "compare")
13825 (set_attr "length" "12,16")])
13828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13831 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13832 (match_operand:SI 2 "reg_or_short_operand" "")))
13833 (match_operand:SI 3 "gpc_reg_operand" ""))
13835 (clobber (match_scratch:SI 4 ""))]
13836 "TARGET_32BIT && reload_completed"
13837 [(set (match_dup 4)
13838 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13841 (compare:CC (match_dup 4)
13846 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13849 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13850 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13851 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13853 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13854 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13857 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13859 [(set_attr "type" "compare")
13860 (set_attr "length" "12,16")])
13863 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13866 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13867 (match_operand:SI 2 "reg_or_short_operand" "")))
13868 (match_operand:SI 3 "gpc_reg_operand" ""))
13870 (set (match_operand:SI 0 "gpc_reg_operand" "")
13871 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13872 "TARGET_32BIT && reload_completed"
13873 [(set (match_dup 0)
13874 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13877 (compare:CC (match_dup 0)
13882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13883 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13884 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13886 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13887 [(set_attr "length" "12")])
13890 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13892 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13893 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13895 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13896 (lt:SI (match_dup 1) (match_dup 2)))]
13899 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13901 [(set_attr "type" "delayed_compare")
13902 (set_attr "length" "12,16")])
13905 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13907 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13908 (match_operand:SI 2 "reg_or_short_operand" ""))
13910 (set (match_operand:SI 0 "gpc_reg_operand" "")
13911 (lt:SI (match_dup 1) (match_dup 2)))]
13912 "TARGET_POWER && reload_completed"
13913 [(set (match_dup 0)
13914 (lt:SI (match_dup 1) (match_dup 2)))
13916 (compare:CC (match_dup 0)
13921 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13922 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13923 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13924 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13926 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13927 [(set_attr "length" "12")])
13930 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13932 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13933 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13934 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13936 (clobber (match_scratch:SI 4 "=&r,&r"))]
13939 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13941 [(set_attr "type" "compare")
13942 (set_attr "length" "12,16")])
13945 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13947 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13948 (match_operand:SI 2 "reg_or_short_operand" ""))
13949 (match_operand:SI 3 "gpc_reg_operand" ""))
13951 (clobber (match_scratch:SI 4 ""))]
13952 "TARGET_POWER && reload_completed"
13953 [(set (match_dup 4)
13954 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13957 (compare:CC (match_dup 4)
13962 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13964 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13965 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13966 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13968 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13969 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13972 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13974 [(set_attr "type" "compare")
13975 (set_attr "length" "12,16")])
13978 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13980 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13981 (match_operand:SI 2 "reg_or_short_operand" ""))
13982 (match_operand:SI 3 "gpc_reg_operand" ""))
13984 (set (match_operand:SI 0 "gpc_reg_operand" "")
13985 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13986 "TARGET_POWER && reload_completed"
13987 [(set (match_dup 0)
13988 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13990 (compare:CC (match_dup 0)
13995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13996 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13997 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13999 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14000 [(set_attr "length" "12")])
14002 (define_insn_and_split "*ltu<mode>"
14003 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14004 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14005 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14009 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14010 (set (match_dup 0) (neg:P (match_dup 0)))]
14013 (define_insn_and_split "*ltu<mode>_compare"
14014 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14016 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14017 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14019 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14020 (ltu:P (match_dup 1) (match_dup 2)))]
14024 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14025 (parallel [(set (match_dup 3)
14026 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14027 (set (match_dup 0) (neg:P (match_dup 0)))])]
14030 (define_insn_and_split "*plus_ltu<mode>"
14031 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14032 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14033 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14034 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14037 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14038 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14039 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14042 (define_insn_and_split "*plus_ltu<mode>_compare"
14043 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14045 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14046 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14047 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14049 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14050 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14053 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14054 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14055 (parallel [(set (match_dup 4)
14056 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14058 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14061 (define_insn "*neg_ltu<mode>"
14062 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14063 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14064 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14067 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14068 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14069 [(set_attr "type" "two")
14070 (set_attr "length" "8")])
14073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14074 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14075 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14076 (clobber (match_scratch:SI 3 "=r"))]
14078 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14079 [(set_attr "length" "12")])
14082 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14084 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14085 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14087 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14088 (ge:SI (match_dup 1) (match_dup 2)))
14089 (clobber (match_scratch:SI 3 "=r,r"))]
14092 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14094 [(set_attr "type" "compare")
14095 (set_attr "length" "12,16")])
14098 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14100 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14101 (match_operand:SI 2 "reg_or_short_operand" ""))
14103 (set (match_operand:SI 0 "gpc_reg_operand" "")
14104 (ge:SI (match_dup 1) (match_dup 2)))
14105 (clobber (match_scratch:SI 3 ""))]
14106 "TARGET_POWER && reload_completed"
14107 [(parallel [(set (match_dup 0)
14108 (ge:SI (match_dup 1) (match_dup 2)))
14109 (clobber (match_dup 3))])
14111 (compare:CC (match_dup 0)
14116 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14117 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14118 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14119 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14121 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14122 [(set_attr "length" "12")])
14125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14127 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14128 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14129 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14131 (clobber (match_scratch:SI 4 "=&r,&r"))]
14134 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14136 [(set_attr "type" "compare")
14137 (set_attr "length" "12,16")])
14140 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14142 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14143 (match_operand:SI 2 "reg_or_short_operand" ""))
14144 (match_operand:SI 3 "gpc_reg_operand" ""))
14146 (clobber (match_scratch:SI 4 ""))]
14147 "TARGET_POWER && reload_completed"
14148 [(set (match_dup 4)
14149 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14152 (compare:CC (match_dup 4)
14157 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14159 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14160 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14161 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14163 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14164 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14167 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14169 [(set_attr "type" "compare")
14170 (set_attr "length" "12,16")])
14173 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14175 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14176 (match_operand:SI 2 "reg_or_short_operand" ""))
14177 (match_operand:SI 3 "gpc_reg_operand" ""))
14179 (set (match_operand:SI 0 "gpc_reg_operand" "")
14180 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14181 "TARGET_POWER && reload_completed"
14182 [(set (match_dup 0)
14183 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14185 (compare:CC (match_dup 0)
14190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14191 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14192 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14194 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14195 [(set_attr "length" "12")])
14197 (define_insn "*geu<mode>"
14198 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14199 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14200 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14203 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14204 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14205 [(set_attr "type" "three")
14206 (set_attr "length" "12")])
14208 (define_insn "*geu<mode>_compare"
14209 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14211 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14212 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14214 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14215 (geu:P (match_dup 1) (match_dup 2)))]
14218 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14219 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14222 [(set_attr "type" "compare")
14223 (set_attr "length" "12,12,16,16")])
14226 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14228 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14229 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14231 (set (match_operand:P 0 "gpc_reg_operand" "")
14232 (geu:P (match_dup 1) (match_dup 2)))]
14234 [(set (match_dup 0)
14235 (geu:P (match_dup 1) (match_dup 2)))
14237 (compare:CC (match_dup 0)
14241 (define_insn "*plus_geu<mode>"
14242 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14243 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14244 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14245 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14248 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14249 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14250 [(set_attr "type" "two")
14251 (set_attr "length" "8")])
14254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14256 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14257 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14258 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14260 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14263 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14264 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14267 [(set_attr "type" "compare")
14268 (set_attr "length" "8,8,12,12")])
14271 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14273 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14274 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14275 (match_operand:SI 3 "gpc_reg_operand" ""))
14277 (clobber (match_scratch:SI 4 ""))]
14278 "TARGET_32BIT && reload_completed"
14279 [(set (match_dup 4)
14280 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14283 (compare:CC (match_dup 4)
14288 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14290 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14291 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14292 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14294 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14295 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14298 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14299 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14302 [(set_attr "type" "compare")
14303 (set_attr "length" "8,8,12,12")])
14306 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14308 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14309 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14310 (match_operand:SI 3 "gpc_reg_operand" ""))
14312 (set (match_operand:SI 0 "gpc_reg_operand" "")
14313 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14314 "TARGET_32BIT && reload_completed"
14315 [(set (match_dup 0)
14316 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14318 (compare:CC (match_dup 0)
14322 (define_insn "*neg_geu<mode>"
14323 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14324 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14325 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14328 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14329 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14330 [(set_attr "type" "three")
14331 (set_attr "length" "12")])
14333 (define_insn "*and_neg_geu<mode>"
14334 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14336 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14337 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14338 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14341 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14342 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14343 [(set_attr "type" "three")
14344 (set_attr "length" "12")])
14347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14350 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14351 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14352 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14354 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14357 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14358 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14361 [(set_attr "type" "compare")
14362 (set_attr "length" "12,12,16,16")])
14365 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14368 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14369 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14370 (match_operand:SI 3 "gpc_reg_operand" ""))
14372 (clobber (match_scratch:SI 4 ""))]
14373 "TARGET_32BIT && reload_completed"
14374 [(set (match_dup 4)
14375 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14378 (compare:CC (match_dup 4)
14383 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14386 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14387 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14388 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14390 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14391 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14394 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14395 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14398 [(set_attr "type" "compare")
14399 (set_attr "length" "12,12,16,16")])
14402 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14405 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14406 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14407 (match_operand:SI 3 "gpc_reg_operand" ""))
14409 (set (match_operand:SI 0 "gpc_reg_operand" "")
14410 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14411 "TARGET_32BIT && reload_completed"
14412 [(set (match_dup 0)
14413 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14415 (compare:CC (match_dup 0)
14420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14421 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14422 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14424 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14425 [(set_attr "length" "12")])
14428 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14430 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14431 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14433 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14434 (gt:SI (match_dup 1) (match_dup 2)))]
14437 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14439 [(set_attr "type" "delayed_compare")
14440 (set_attr "length" "12,16")])
14443 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14445 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14446 (match_operand:SI 2 "reg_or_short_operand" ""))
14448 (set (match_operand:SI 0 "gpc_reg_operand" "")
14449 (gt:SI (match_dup 1) (match_dup 2)))]
14450 "TARGET_POWER && reload_completed"
14451 [(set (match_dup 0)
14452 (gt:SI (match_dup 1) (match_dup 2)))
14454 (compare:CC (match_dup 0)
14458 (define_insn "*plus_gt0<mode>"
14459 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14460 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14462 (match_operand:P 2 "gpc_reg_operand" "r")))]
14464 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14465 [(set_attr "type" "three")
14466 (set_attr "length" "12")])
14469 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14471 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14473 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14475 (clobber (match_scratch:SI 3 "=&r,&r"))]
14478 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14480 [(set_attr "type" "compare")
14481 (set_attr "length" "12,16")])
14484 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14486 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14488 (match_operand:SI 2 "gpc_reg_operand" ""))
14490 (clobber (match_scratch:SI 3 ""))]
14491 "TARGET_32BIT && reload_completed"
14492 [(set (match_dup 3)
14493 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14496 (compare:CC (match_dup 3)
14501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14503 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14505 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14507 (clobber (match_scratch:DI 3 "=&r,&r"))]
14510 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14512 [(set_attr "type" "compare")
14513 (set_attr "length" "12,16")])
14516 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14518 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14520 (match_operand:DI 2 "gpc_reg_operand" ""))
14522 (clobber (match_scratch:DI 3 ""))]
14523 "TARGET_64BIT && reload_completed"
14524 [(set (match_dup 3)
14525 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14528 (compare:CC (match_dup 3)
14533 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14535 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14537 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14539 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14540 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14543 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14545 [(set_attr "type" "compare")
14546 (set_attr "length" "12,16")])
14549 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14551 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14553 (match_operand:SI 2 "gpc_reg_operand" ""))
14555 (set (match_operand:SI 0 "gpc_reg_operand" "")
14556 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14557 "TARGET_32BIT && reload_completed"
14558 [(set (match_dup 0)
14559 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14561 (compare:CC (match_dup 0)
14566 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14568 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14570 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14572 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14573 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14576 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14578 [(set_attr "type" "compare")
14579 (set_attr "length" "12,16")])
14582 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14584 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14586 (match_operand:DI 2 "gpc_reg_operand" ""))
14588 (set (match_operand:DI 0 "gpc_reg_operand" "")
14589 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14590 "TARGET_64BIT && reload_completed"
14591 [(set (match_dup 0)
14592 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14594 (compare:CC (match_dup 0)
14599 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14600 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14601 (match_operand:SI 2 "reg_or_short_operand" "r"))
14602 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14604 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14605 [(set_attr "length" "12")])
14608 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14610 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14611 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14612 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14614 (clobber (match_scratch:SI 4 "=&r,&r"))]
14617 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14619 [(set_attr "type" "compare")
14620 (set_attr "length" "12,16")])
14623 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14625 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14626 (match_operand:SI 2 "reg_or_short_operand" ""))
14627 (match_operand:SI 3 "gpc_reg_operand" ""))
14629 (clobber (match_scratch:SI 4 ""))]
14630 "TARGET_POWER && reload_completed"
14631 [(set (match_dup 4)
14632 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14634 (compare:CC (match_dup 4)
14639 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14641 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14642 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14643 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14645 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14646 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14649 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14651 [(set_attr "type" "compare")
14652 (set_attr "length" "12,16")])
14655 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14657 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14658 (match_operand:SI 2 "reg_or_short_operand" ""))
14659 (match_operand:SI 3 "gpc_reg_operand" ""))
14661 (set (match_operand:SI 0 "gpc_reg_operand" "")
14662 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14663 "TARGET_POWER && reload_completed"
14664 [(set (match_dup 0)
14665 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14667 (compare:CC (match_dup 0)
14672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14673 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14674 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14676 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14677 [(set_attr "length" "12")])
14679 (define_insn_and_split "*gtu<mode>"
14680 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14681 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14682 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14686 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14687 (set (match_dup 0) (neg:P (match_dup 0)))]
14690 (define_insn_and_split "*gtu<mode>_compare"
14691 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14693 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14694 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14696 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14697 (gtu:P (match_dup 1) (match_dup 2)))]
14701 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14702 (parallel [(set (match_dup 3)
14703 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14704 (set (match_dup 0) (neg:P (match_dup 0)))])]
14707 (define_insn_and_split "*plus_gtu<mode>"
14708 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14709 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14710 (match_operand:P 2 "reg_or_short_operand" "rI"))
14711 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14714 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14715 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14716 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14719 (define_insn_and_split "*plus_gtu<mode>_compare"
14720 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14722 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14723 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14724 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14726 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14727 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14730 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14731 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14732 (parallel [(set (match_dup 4)
14733 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14735 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14738 (define_insn "*neg_gtu<mode>"
14739 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14740 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14741 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14743 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14744 [(set_attr "type" "two")
14745 (set_attr "length" "8")])
14748 ;; Define both directions of branch and return. If we need a reload
14749 ;; register, we'd rather use CR0 since it is much easier to copy a
14750 ;; register CC value to there.
14754 (if_then_else (match_operator 1 "branch_comparison_operator"
14756 "cc_reg_operand" "y")
14758 (label_ref (match_operand 0 "" ""))
14763 return output_cbranch (operands[1], \"%l0\", 0, insn);
14765 [(set_attr "type" "branch")])
14769 (if_then_else (match_operator 0 "branch_comparison_operator"
14771 "cc_reg_operand" "y")
14778 return output_cbranch (operands[0], NULL, 0, insn);
14780 [(set_attr "type" "jmpreg")
14781 (set_attr "length" "4")])
14785 (if_then_else (match_operator 1 "branch_comparison_operator"
14787 "cc_reg_operand" "y")
14790 (label_ref (match_operand 0 "" ""))))]
14794 return output_cbranch (operands[1], \"%l0\", 1, insn);
14796 [(set_attr "type" "branch")])
14800 (if_then_else (match_operator 0 "branch_comparison_operator"
14802 "cc_reg_operand" "y")
14809 return output_cbranch (operands[0], NULL, 1, insn);
14811 [(set_attr "type" "jmpreg")
14812 (set_attr "length" "4")])
14814 ;; Logic on condition register values.
14816 ; This pattern matches things like
14817 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14818 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14820 ; which are generated by the branch logic.
14821 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14823 (define_insn "*cceq_ior_compare"
14824 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14825 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14826 [(match_operator:SI 2
14827 "branch_positive_comparison_operator"
14829 "cc_reg_operand" "y,y")
14831 (match_operator:SI 4
14832 "branch_positive_comparison_operator"
14834 "cc_reg_operand" "0,y")
14838 "cr%q1 %E0,%j2,%j4"
14839 [(set_attr "type" "cr_logical,delayed_cr")])
14841 ; Why is the constant -1 here, but 1 in the previous pattern?
14842 ; Because ~1 has all but the low bit set.
14844 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14845 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14846 [(not:SI (match_operator:SI 2
14847 "branch_positive_comparison_operator"
14849 "cc_reg_operand" "y,y")
14851 (match_operator:SI 4
14852 "branch_positive_comparison_operator"
14854 "cc_reg_operand" "0,y")
14858 "cr%q1 %E0,%j2,%j4"
14859 [(set_attr "type" "cr_logical,delayed_cr")])
14861 (define_insn "*cceq_rev_compare"
14862 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14863 (compare:CCEQ (match_operator:SI 1
14864 "branch_positive_comparison_operator"
14866 "cc_reg_operand" "0,y")
14870 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14871 [(set_attr "type" "cr_logical,delayed_cr")])
14873 ;; If we are comparing the result of two comparisons, this can be done
14874 ;; using creqv or crxor.
14876 (define_insn_and_split ""
14877 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14878 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14879 [(match_operand 2 "cc_reg_operand" "y")
14881 (match_operator 3 "branch_comparison_operator"
14882 [(match_operand 4 "cc_reg_operand" "y")
14887 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14891 int positive_1, positive_2;
14893 positive_1 = branch_positive_comparison_operator (operands[1],
14894 GET_MODE (operands[1]));
14895 positive_2 = branch_positive_comparison_operator (operands[3],
14896 GET_MODE (operands[3]));
14899 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14900 GET_CODE (operands[1])),
14902 operands[2], const0_rtx);
14903 else if (GET_MODE (operands[1]) != SImode)
14904 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14905 operands[2], const0_rtx);
14908 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14909 GET_CODE (operands[3])),
14911 operands[4], const0_rtx);
14912 else if (GET_MODE (operands[3]) != SImode)
14913 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14914 operands[4], const0_rtx);
14916 if (positive_1 == positive_2)
14918 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14919 operands[5] = constm1_rtx;
14923 operands[5] = const1_rtx;
14927 ;; Unconditional branch and return.
14929 (define_insn "jump"
14931 (label_ref (match_operand 0 "" "")))]
14934 [(set_attr "type" "branch")])
14936 (define_insn "return"
14940 [(set_attr "type" "jmpreg")])
14942 (define_expand "indirect_jump"
14943 [(set (pc) (match_operand 0 "register_operand" ""))])
14945 (define_insn "*indirect_jump<mode>"
14946 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14951 [(set_attr "type" "jmpreg")])
14953 ;; Table jump for switch statements:
14954 (define_expand "tablejump"
14955 [(use (match_operand 0 "" ""))
14956 (use (label_ref (match_operand 1 "" "")))]
14961 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14963 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14967 (define_expand "tablejumpsi"
14968 [(set (match_dup 3)
14969 (plus:SI (match_operand:SI 0 "" "")
14971 (parallel [(set (pc) (match_dup 3))
14972 (use (label_ref (match_operand 1 "" "")))])]
14975 { operands[0] = force_reg (SImode, operands[0]);
14976 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14977 operands[3] = gen_reg_rtx (SImode);
14980 (define_expand "tablejumpdi"
14981 [(set (match_dup 4)
14982 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14984 (plus:DI (match_dup 4)
14986 (parallel [(set (pc) (match_dup 3))
14987 (use (label_ref (match_operand 1 "" "")))])]
14990 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14991 operands[3] = gen_reg_rtx (DImode);
14992 operands[4] = gen_reg_rtx (DImode);
14995 (define_insn "*tablejump<mode>_internal1"
14997 (match_operand:P 0 "register_operand" "c,*l"))
14998 (use (label_ref (match_operand 1 "" "")))]
15003 [(set_attr "type" "jmpreg")])
15008 "{cror 0,0,0|nop}")
15010 ;; Define the subtract-one-and-jump insns, starting with the template
15011 ;; so loop.c knows what to generate.
15013 (define_expand "doloop_end"
15014 [(use (match_operand 0 "" "")) ; loop pseudo
15015 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15016 (use (match_operand 2 "" "")) ; max iterations
15017 (use (match_operand 3 "" "")) ; loop level
15018 (use (match_operand 4 "" ""))] ; label
15022 /* Only use this on innermost loops. */
15023 if (INTVAL (operands[3]) > 1)
15027 if (GET_MODE (operands[0]) != DImode)
15029 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15033 if (GET_MODE (operands[0]) != SImode)
15035 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15040 (define_expand "ctr<mode>"
15041 [(parallel [(set (pc)
15042 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15044 (label_ref (match_operand 1 "" ""))
15047 (plus:P (match_dup 0)
15049 (clobber (match_scratch:CC 2 ""))
15050 (clobber (match_scratch:P 3 ""))])]
15054 ;; We need to be able to do this for any operand, including MEM, or we
15055 ;; will cause reload to blow up since we don't allow output reloads on
15057 ;; For the length attribute to be calculated correctly, the
15058 ;; label MUST be operand 0.
15060 (define_insn "*ctr<mode>_internal1"
15062 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15064 (label_ref (match_operand 0 "" ""))
15066 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15067 (plus:P (match_dup 1)
15069 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15070 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15074 if (which_alternative != 0)
15076 else if (get_attr_length (insn) == 4)
15077 return \"{bdn|bdnz} %l0\";
15079 return \"bdz $+8\;b %l0\";
15081 [(set_attr "type" "branch")
15082 (set_attr "length" "*,12,16,16")])
15084 (define_insn "*ctr<mode>_internal2"
15086 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15089 (label_ref (match_operand 0 "" ""))))
15090 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15091 (plus:P (match_dup 1)
15093 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15094 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15098 if (which_alternative != 0)
15100 else if (get_attr_length (insn) == 4)
15101 return \"bdz %l0\";
15103 return \"{bdn|bdnz} $+8\;b %l0\";
15105 [(set_attr "type" "branch")
15106 (set_attr "length" "*,12,16,16")])
15108 ;; Similar but use EQ
15110 (define_insn "*ctr<mode>_internal5"
15112 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15114 (label_ref (match_operand 0 "" ""))
15116 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15117 (plus:P (match_dup 1)
15119 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15120 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15124 if (which_alternative != 0)
15126 else if (get_attr_length (insn) == 4)
15127 return \"bdz %l0\";
15129 return \"{bdn|bdnz} $+8\;b %l0\";
15131 [(set_attr "type" "branch")
15132 (set_attr "length" "*,12,16,16")])
15134 (define_insn "*ctr<mode>_internal6"
15136 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15139 (label_ref (match_operand 0 "" ""))))
15140 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15141 (plus:P (match_dup 1)
15143 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15144 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15148 if (which_alternative != 0)
15150 else if (get_attr_length (insn) == 4)
15151 return \"{bdn|bdnz} %l0\";
15153 return \"bdz $+8\;b %l0\";
15155 [(set_attr "type" "branch")
15156 (set_attr "length" "*,12,16,16")])
15158 ;; Now the splitters if we could not allocate the CTR register
15162 (if_then_else (match_operator 2 "comparison_operator"
15163 [(match_operand:P 1 "gpc_reg_operand" "")
15165 (match_operand 5 "" "")
15166 (match_operand 6 "" "")))
15167 (set (match_operand:P 0 "gpc_reg_operand" "")
15168 (plus:P (match_dup 1) (const_int -1)))
15169 (clobber (match_scratch:CC 3 ""))
15170 (clobber (match_scratch:P 4 ""))]
15172 [(parallel [(set (match_dup 3)
15173 (compare:CC (plus:P (match_dup 1)
15177 (plus:P (match_dup 1)
15179 (set (pc) (if_then_else (match_dup 7)
15183 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15184 operands[3], const0_rtx); }")
15188 (if_then_else (match_operator 2 "comparison_operator"
15189 [(match_operand:P 1 "gpc_reg_operand" "")
15191 (match_operand 5 "" "")
15192 (match_operand 6 "" "")))
15193 (set (match_operand:P 0 "nonimmediate_operand" "")
15194 (plus:P (match_dup 1) (const_int -1)))
15195 (clobber (match_scratch:CC 3 ""))
15196 (clobber (match_scratch:P 4 ""))]
15197 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15198 [(parallel [(set (match_dup 3)
15199 (compare:CC (plus:P (match_dup 1)
15203 (plus:P (match_dup 1)
15207 (set (pc) (if_then_else (match_dup 7)
15211 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15212 operands[3], const0_rtx); }")
15214 (define_insn "trap"
15215 [(trap_if (const_int 1) (const_int 0))]
15218 [(set_attr "type" "trap")])
15220 (define_expand "ctrap<mode>4"
15221 [(trap_if (match_operator 0 "ordered_comparison_operator"
15222 [(match_operand:GPR 1 "register_operand")
15223 (match_operand:GPR 2 "reg_or_short_operand")])
15224 (match_operand 3 "zero_constant" ""))]
15229 [(trap_if (match_operator 0 "ordered_comparison_operator"
15230 [(match_operand:GPR 1 "register_operand" "r")
15231 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15234 "{t|t<wd>}%V0%I2 %1,%2"
15235 [(set_attr "type" "trap")])
15237 ;; Insns related to generating the function prologue and epilogue.
15239 (define_expand "prologue"
15240 [(use (const_int 0))]
15241 "TARGET_SCHED_PROLOG"
15244 rs6000_emit_prologue ();
15248 (define_insn "*movesi_from_cr_one"
15249 [(match_parallel 0 "mfcr_operation"
15250 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15251 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15252 (match_operand 3 "immediate_operand" "n")]
15253 UNSPEC_MOVESI_FROM_CR))])]
15259 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15261 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15262 operands[4] = GEN_INT (mask);
15263 output_asm_insn (\"mfcr %1,%4\", operands);
15267 [(set_attr "type" "mfcrf")])
15269 (define_insn "movesi_from_cr"
15270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15271 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15272 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15273 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15274 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15275 UNSPEC_MOVESI_FROM_CR))]
15278 [(set_attr "type" "mfcr")])
15280 (define_insn "*stmw"
15281 [(match_parallel 0 "stmw_operation"
15282 [(set (match_operand:SI 1 "memory_operand" "=m")
15283 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15286 [(set_attr "type" "store_ux")])
15288 (define_insn "*save_gpregs_<mode>"
15289 [(match_parallel 0 "any_parallel_operand"
15290 [(clobber (reg:P 65))
15291 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15292 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15293 (set (match_operand:P 3 "memory_operand" "=m")
15294 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15297 [(set_attr "type" "branch")
15298 (set_attr "length" "4")])
15300 (define_insn "*save_fpregs_<mode>"
15301 [(match_parallel 0 "any_parallel_operand"
15302 [(clobber (reg:P 65))
15303 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15304 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15305 (set (match_operand:DF 3 "memory_operand" "=m")
15306 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15309 [(set_attr "type" "branch")
15310 (set_attr "length" "4")])
15312 ; These are to explain that changes to the stack pointer should
15313 ; not be moved over stores to stack memory.
15314 (define_insn "stack_tie"
15315 [(set (match_operand:BLK 0 "memory_operand" "+m")
15316 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15319 [(set_attr "length" "0")])
15322 (define_expand "epilogue"
15323 [(use (const_int 0))]
15324 "TARGET_SCHED_PROLOG"
15327 rs6000_emit_epilogue (FALSE);
15331 ; On some processors, doing the mtcrf one CC register at a time is
15332 ; faster (like on the 604e). On others, doing them all at once is
15333 ; faster; for instance, on the 601 and 750.
15335 (define_expand "movsi_to_cr_one"
15336 [(set (match_operand:CC 0 "cc_reg_operand" "")
15337 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15338 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15340 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15342 (define_insn "*movsi_to_cr"
15343 [(match_parallel 0 "mtcrf_operation"
15344 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15345 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15346 (match_operand 3 "immediate_operand" "n")]
15347 UNSPEC_MOVESI_TO_CR))])]
15353 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15354 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15355 operands[4] = GEN_INT (mask);
15356 return \"mtcrf %4,%2\";
15358 [(set_attr "type" "mtcr")])
15360 (define_insn "*mtcrfsi"
15361 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15362 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15363 (match_operand 2 "immediate_operand" "n")]
15364 UNSPEC_MOVESI_TO_CR))]
15365 "GET_CODE (operands[0]) == REG
15366 && CR_REGNO_P (REGNO (operands[0]))
15367 && GET_CODE (operands[2]) == CONST_INT
15368 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15370 [(set_attr "type" "mtcr")])
15372 ; The load-multiple instructions have similar properties.
15373 ; Note that "load_multiple" is a name known to the machine-independent
15374 ; code that actually corresponds to the PowerPC load-string.
15376 (define_insn "*lmw"
15377 [(match_parallel 0 "lmw_operation"
15378 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15379 (match_operand:SI 2 "memory_operand" "m"))])]
15382 [(set_attr "type" "load_ux")
15383 (set_attr "cell_micro" "always")])
15385 (define_insn "*return_internal_<mode>"
15387 (use (match_operand:P 0 "register_operand" "lc"))]
15390 [(set_attr "type" "jmpreg")])
15392 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15393 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15395 (define_insn "*restore_gpregs_<mode>"
15396 [(match_parallel 0 "any_parallel_operand"
15397 [(clobber (match_operand:P 1 "register_operand" "=l"))
15398 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15399 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15400 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15401 (match_operand:P 5 "memory_operand" "m"))])]
15404 [(set_attr "type" "branch")
15405 (set_attr "length" "4")])
15407 (define_insn "*return_and_restore_gpregs_<mode>"
15408 [(match_parallel 0 "any_parallel_operand"
15410 (clobber (match_operand:P 1 "register_operand" "=l"))
15411 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15412 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15413 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15414 (match_operand:P 5 "memory_operand" "m"))])]
15417 [(set_attr "type" "branch")
15418 (set_attr "length" "4")])
15420 (define_insn "*return_and_restore_fpregs_<mode>"
15421 [(match_parallel 0 "any_parallel_operand"
15423 (clobber (match_operand:P 1 "register_operand" "=l"))
15424 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15425 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15426 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15427 (match_operand:DF 5 "memory_operand" "m"))])]
15430 [(set_attr "type" "branch")
15431 (set_attr "length" "4")])
15433 ; This is used in compiling the unwind routines.
15434 (define_expand "eh_return"
15435 [(use (match_operand 0 "general_operand" ""))]
15440 emit_insn (gen_eh_set_lr_si (operands[0]));
15442 emit_insn (gen_eh_set_lr_di (operands[0]));
15446 ; We can't expand this before we know where the link register is stored.
15447 (define_insn "eh_set_lr_<mode>"
15448 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15450 (clobber (match_scratch:P 1 "=&b"))]
15455 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15456 (clobber (match_scratch 1 ""))]
15461 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15465 (define_insn "prefetch"
15466 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15467 (match_operand:SI 1 "const_int_operand" "n")
15468 (match_operand:SI 2 "const_int_operand" "n"))]
15472 if (GET_CODE (operands[0]) == REG)
15473 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15474 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15476 [(set_attr "type" "load")])
15478 (define_insn "bpermd_<mode>"
15479 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15480 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15481 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15484 [(set_attr "type" "integer")])
15488 (include "sync.md")
15489 (include "vector.md")
15491 (include "altivec.md")
15494 (include "paired.md")