gcc/config/rs6000/rs6000.opt

   1 ; Options for the rs6000 port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2019 Free Software Foundation, Inc.
   4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
   5 ;
   6 ; This file is part of GCC.
   7 ;
   8 ; GCC is free software; you can redistribute it and/or modify it under
   9 ; the terms of the GNU General Public License as published by the Free
  10 ; Software Foundation; either version 3, or (at your option) any later
  11 ; version.
  12 ;
  13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ; License for more details.
  17 ;
  18 ; You should have received a copy of the GNU General Public License
  19 ; along with GCC; see the file COPYING3.  If not see
  20 ; <http://www.gnu.org/licenses/>.
  21
  22 HeaderInclude
  23 config/rs6000/rs6000-opts.h
  24
  25 ;; ISA flag bits (on/off)
  26 Variable
  27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
  28
  29 TargetSave
  30 HOST_WIDE_INT x_rs6000_isa_flags
  31
  32 ;; Miscellaneous flag bits that were set explicitly by the user
  33 Variable
  34 HOST_WIDE_INT rs6000_isa_flags_explicit
  35
  36 TargetSave
  37 HOST_WIDE_INT x_rs6000_isa_flags_explicit
  38
  39 ;; Current processor
  40 TargetVariable
  41 enum processor_type rs6000_cpu = PROCESSOR_PPC603
  42
  43 ;; Current tuning
  44 TargetVariable
  45 enum processor_type rs6000_tune = PROCESSOR_PPC603
  46
  47 ;; Always emit branch hint bits.
  48 TargetVariable
  49 unsigned char rs6000_always_hint
  50
  51 ;; Schedule instructions for group formation.
  52 TargetVariable
  53 unsigned char rs6000_sched_groups
  54
  55 ;; Align branch targets.
  56 TargetVariable
  57 unsigned char rs6000_align_branch_targets
  58
  59 ;; Support for -msched-costly-dep option.
  60 TargetVariable
  61 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
  62
  63 ;; Support for -minsert-sched-nops option.
  64 TargetVariable
  65 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
  66
  67 ;; Non-zero to allow overriding loop alignment.
  68 TargetVariable
  69 unsigned char can_override_loop_align
  70
  71 ;; Which small data model to use (for System V targets only)
  72 TargetVariable
  73 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
  74
  75 ;; Bit size of immediate TLS offsets and string from which it is decoded.
  76 TargetVariable
  77 int rs6000_tls_size = 32
  78
  79 ;; ABI enumeration available for subtarget to use.
  80 TargetVariable
  81 enum rs6000_abi rs6000_current_abi = ABI_NONE
  82
  83 ;; Type of traceback to use.
  84 TargetVariable
  85 enum rs6000_traceback_type rs6000_traceback = traceback_default
  86
  87 ;; Control alignment for fields within structures.
  88 TargetVariable
  89 unsigned char rs6000_alignment_flags
  90
  91 ;; Code model for 64-bit linux.
  92 TargetVariable
  93 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
  94
  95 ;; What type of reciprocal estimation instructions to generate
  96 TargetVariable
  97 unsigned int rs6000_recip_control
  98
  99 ;; Mask of what builtin functions are allowed
 100 TargetVariable
 101 HOST_WIDE_INT rs6000_builtin_mask
 102
 103 ;; Debug flags
 104 TargetVariable
 105 unsigned int rs6000_debug
 106
 107 ;; Whether to enable the -mfloat128 stuff without necessarily enabling the
 108 ;; __float128 keyword.
 109 TargetSave
 110 unsigned char x_TARGET_FLOAT128_TYPE
 111
 112 Variable
 113 unsigned char TARGET_FLOAT128_TYPE
 114
 115 ;; This option existed in the past, but now is always on.
 116 mpowerpc
 117 Target RejectNegative Undocumented Ignore
 118
 119 mpowerpc64
 120 Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
 121 Use PowerPC-64 instruction set.
 122
 123 mpowerpc-gpopt
 124 Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
 125 Use PowerPC General Purpose group optional instructions.
 126
 127 mpowerpc-gfxopt
 128 Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
 129 Use PowerPC Graphics group optional instructions.
 130
 131 mmfcrf
 132 Target Report Mask(MFCRF) Var(rs6000_isa_flags)
 133 Use PowerPC V2.01 single field mfcr instruction.
 134
 135 mpopcntb
 136 Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
 137 Use PowerPC V2.02 popcntb instruction.
 138
 139 mfprnd
 140 Target Report Mask(FPRND) Var(rs6000_isa_flags)
 141 Use PowerPC V2.02 floating point rounding instructions.
 142
 143 mcmpb
 144 Target Report Mask(CMPB) Var(rs6000_isa_flags)
 145 Use PowerPC V2.05 compare bytes instruction.
 146
 147 mmfpgpr
 148 Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
 149 Use extended PowerPC V2.05 move floating point to/from GPR instructions.
 150
 151 maltivec
 152 Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
 153 Use AltiVec instructions.
 154
 155 mfold-gimple
 156 Target Report Var(rs6000_fold_gimple) Init(1)
 157 Enable early gimple folding of builtins.
 158
 159 mhard-dfp
 160 Target Report Mask(DFP) Var(rs6000_isa_flags)
 161 Use decimal floating point instructions.
 162
 163 mmulhw
 164 Target Report Mask(MULHW) Var(rs6000_isa_flags)
 165 Use 4xx half-word multiply instructions.
 166
 167 mdlmzb
 168 Target Report Mask(DLMZB) Var(rs6000_isa_flags)
 169 Use 4xx string-search dlmzb instruction.
 170
 171 mmultiple
 172 Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
 173 Generate load/store multiple instructions.
 174
 175 ;; This option existed in the past, but now is always off.
 176 mno-string
 177 Target RejectNegative Undocumented Ignore
 178
 179 mstring
 180 Target RejectNegative Undocumented Deprecated
 181
 182 msoft-float
 183 Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
 184 Do not use hardware floating point.
 185
 186 mhard-float
 187 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
 188 Use hardware floating point.
 189
 190 mpopcntd
 191 Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
 192 Use PowerPC V2.06 popcntd instruction.
 193
 194 mfriz
 195 Target Report Var(TARGET_FRIZ) Init(-1) Save
 196 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
 197
 198 mveclibabi=
 199 Target RejectNegative Joined Var(rs6000_veclibabi_name)
 200 Vector library ABI to use.
 201
 202 mvsx
 203 Target Report Mask(VSX) Var(rs6000_isa_flags)
 204 Use vector/scalar (VSX) instructions.
 205
 206 mvsx-align-128
 207 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
 208 ; If -mvsx, set alignment to 128 bits instead of 32/64
 209
 210 mallow-movmisalign
 211 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
 212 ; Allow the movmisalign in DF/DI vectors
 213
 214 mefficient-unaligned-vsx
 215 Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
 216 ; Consider unaligned VSX vector and fp accesses to be efficient
 217
 218 msched-groups
 219 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
 220 ; Explicitly set rs6000_sched_groups
 221
 222 malways-hint
 223 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
 224 ; Explicitly set rs6000_always_hint
 225
 226 malign-branch-targets
 227 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
 228 ; Explicitly set rs6000_align_branch_targets
 229
 230 mno-update
 231 Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
 232 Do not generate load/store with update instructions.
 233
 234 mupdate
 235 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
 236 Generate load/store with update instructions.
 237
 238 msingle-pic-base
 239 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
 240 Do not load the PIC register in function prologues.
 241
 242 mavoid-indexed-addresses
 243 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
 244 Avoid generation of indexed load/store instructions when possible.
 245
 246 mtls-markers
 247 Target Report Var(tls_markers) Init(1) Save
 248 Mark __tls_get_addr calls with argument info.
 249
 250 msched-epilog
 251 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
 252
 253 msched-prolog
 254 Target Report Var(TARGET_SCHED_PROLOG) Save
 255 Schedule the start and end of the procedure.
 256
 257 maix-struct-return
 258 Target Report RejectNegative Var(aix_struct_return) Save
 259 Return all structures in memory (AIX default).
 260
 261 msvr4-struct-return
 262 Target Report RejectNegative Var(aix_struct_return,0) Save
 263 Return small structures in registers (SVR4 default).
 264
 265 mxl-compat
 266 Target Report Var(TARGET_XL_COMPAT) Save
 267 Conform more closely to IBM XLC semantics.
 268
 269 mrecip
 270 Target Report
 271 Generate software reciprocal divide and square root for better throughput.
 272
 273 mrecip=
 274 Target Report RejectNegative Joined Var(rs6000_recip_name)
 275 Generate software reciprocal divide and square root for better throughput.
 276
 277 mrecip-precision
 278 Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
 279 Assume that the reciprocal estimate instructions provide more accuracy.
 280
 281 mno-fp-in-toc
 282 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
 283 Do not place floating point constants in TOC.
 284
 285 mfp-in-toc
 286 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
 287 Place floating point constants in TOC.
 288
 289 mno-sum-in-toc
 290 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
 291 Do not place symbol+offset constants in TOC.
 292
 293 msum-in-toc
 294 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
 295 Place symbol+offset constants in TOC.
 296
 297 ;  Output only one TOC entry per module.  Normally linking fails if
 298 ;   there are more than 16K unique variables/constants in an executable.  With
 299 ;   this option, linking fails only if there are more than 16K modules, or
 300 ;   if there are more than 16K unique variables/constant in a single module.
 301 ;
 302 ;   This is at the cost of having 2 extra loads and one extra store per
 303 ;   function, and one less allocable register.
 304 mminimal-toc
 305 Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
 306 Use only one TOC entry per procedure.
 307
 308 mfull-toc
 309 Target Report
 310 Put everything in the regular TOC.
 311
 312 mvrsave
 313 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
 314 Generate VRSAVE instructions when generating AltiVec code.
 315
 316 mvrsave=no
 317 Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead)
 318 Deprecated option.  Use -mno-vrsave instead.
 319
 320 mvrsave=yes
 321 Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead)
 322 Deprecated option.  Use -mvrsave instead.
 323
 324 mblock-move-inline-limit=
 325 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
 326 Max number of bytes to move inline.
 327
 328 mblock-compare-inline-limit=
 329 Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
 330 Max number of bytes to compare without loops.
 331
 332 mblock-compare-inline-loop-limit=
 333 Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
 334 Max number of bytes to compare with loops.
 335
 336 mstring-compare-inline-limit=
 337 Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
 338 Max number of bytes to compare.
 339
 340 misel
 341 Target Report Mask(ISEL) Var(rs6000_isa_flags)
 342 Generate isel instructions.
 343
 344 mdebug=
 345 Target RejectNegative Joined
 346 -mdebug=        Enable debug output.
 347
 348 mabi=altivec
 349 Target RejectNegative Var(rs6000_altivec_abi) Save
 350 Use the AltiVec ABI extensions.
 351
 352 mabi=no-altivec
 353 Target RejectNegative Var(rs6000_altivec_abi, 0)
 354 Do not use the AltiVec ABI extensions.
 355
 356 mabi=elfv1
 357 Target RejectNegative Var(rs6000_elf_abi, 1) Save
 358 Use the ELFv1 ABI.
 359
 360 mabi=elfv2
 361 Target RejectNegative Var(rs6000_elf_abi, 2)
 362 Use the ELFv2 ABI.
 363
 364 ; These are here for testing during development only, do not document
 365 ; in the manual please.
 366
 367 ; If we want Darwin's struct-by-value-in-regs ABI.
 368 mabi=d64
 369 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
 370
 371 mabi=d32
 372 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
 373
 374 mabi=ieeelongdouble
 375 Target RejectNegative Var(rs6000_ieeequad) Save
 376
 377 mabi=ibmlongdouble
 378 Target RejectNegative Var(rs6000_ieeequad, 0)
 379
 380 mcpu=
 381 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
 382 -mcpu=  Use features of and schedule code for given CPU.
 383
 384 mtune=
 385 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
 386 -mtune= Schedule code for given CPU.
 387
 388 ; Only for use in the testsuite.  This simply overrides -mcpu=.  With older
 389 ; versions of Dejagnu the command line arguments you set in RUNTESTFLAGS
 390 ; override those set in the testcases; with this option, the testcase will
 391 ; always win.
 392 mdejagnu-cpu=
 393 Target Undocumented RejectNegative Joined Var(rs6000_dejagnu_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
 394
 395 mtraceback=
 396 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
 397 -mtraceback=[full,part,no]      Select type of traceback table.
 398
 399 Enum
 400 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
 401
 402 EnumValue
 403 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
 404
 405 EnumValue
 406 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
 407
 408 EnumValue
 409 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
 410
 411 mlongcall
 412 Target Report Var(rs6000_default_long_calls) Save
 413 Avoid all range limits on call instructions.
 414
 415 ; This option existed in the past, but now is always on.
 416 mgen-cell-microcode
 417 Target RejectNegative Undocumented Ignore
 418
 419 mwarn-altivec-long
 420 Target Var(rs6000_warn_altivec_long) Init(1) Save
 421 Warn about deprecated 'vector long ...' AltiVec type usage.
 422
 423 mlong-double-
 424 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
 425 -mlong-double-[64,128]  Specify size of long double.
 426
 427 ; This option existed in the past, but now is always on.
 428 mlra
 429 Target RejectNegative Undocumented Ignore
 430
 431 msched-costly-dep=
 432 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
 433 Determine which dependences between insns are considered costly.
 434
 435 minsert-sched-nops=
 436 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
 437 Specify which post scheduling nop insertion scheme to apply.
 438
 439 malign-
 440 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
 441 Specify alignment of structure fields default/natural.
 442
 443 Enum
 444 Name(rs6000_alignment_flags) Type(unsigned char)
 445 Valid arguments to -malign-:
 446
 447 EnumValue
 448 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
 449
 450 EnumValue
 451 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
 452
 453 mprioritize-restricted-insns=
 454 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
 455 Specify scheduling priority for dispatch slot restricted insns.
 456
 457 mpointers-to-nested-functions
 458 Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
 459 Use r11 to hold the static link in calls to functions via pointers.
 460
 461 msave-toc-indirect
 462 Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
 463 Save the TOC in the prologue for indirect calls rather than inline.
 464
 465 ; This option existed in the past, but now is always the same as -mvsx.
 466 mvsx-timode
 467 Target RejectNegative Undocumented Ignore
 468
 469 mpower8-fusion
 470 Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
 471 Fuse certain integer operations together for better performance on power8.
 472
 473 mpower8-fusion-sign
 474 Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
 475 Allow sign extension in fusion operations.
 476
 477 mpower8-vector
 478 Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
 479 Use vector and scalar instructions added in ISA 2.07.
 480
 481 mcrypto
 482 Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
 483 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
 484
 485 mdirect-move
 486 Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) Deprecated
 487
 488 mhtm
 489 Target Report Mask(HTM) Var(rs6000_isa_flags)
 490 Use ISA 2.07 transactional memory (HTM) instructions.
 491
 492 mquad-memory
 493 Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
 494 Generate the quad word memory instructions (lq/stq).
 495
 496 mquad-memory-atomic
 497 Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
 498 Generate the quad word memory atomic instructions (lqarx/stqcx).
 499
 500 mcompat-align-parm
 501 Target Report Var(rs6000_compat_align_parm) Init(0) Save
 502 Generate aggregate parameter passing code with at most 64-bit alignment.
 503
 504 moptimize-swaps
 505 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
 506 Analyze and remove doubleword swaps from VSX computations.
 507
 508 mpower9-misc
 509 Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
 510 Use certain scalar instructions added in ISA 3.0.
 511
 512 mpower9-vector
 513 Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
 514 Use vector instructions added in ISA 3.0.
 515
 516 mpower9-minmax
 517 Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
 518 Use the new min/max instructions defined in ISA 3.0.
 519
 520 mtoc-fusion
 521 Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
 522 Fuse medium/large code model toc references with the memory instruction.
 523
 524 mmodulo
 525 Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
 526 Generate the integer modulo instructions.
 527
 528 mfloat128
 529 Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
 530 Enable IEEE 128-bit floating point via the __float128 keyword.
 531
 532 mfloat128-hardware
 533 Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
 534 Enable using IEEE 128-bit floating point instructions.
 535
 536 mfloat128-convert
 537 Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
 538 Enable default conversions between __float128 & long double.
 539
 540 mstack-protector-guard=
 541 Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
 542 Use given stack-protector guard.
 543
 544 Enum
 545 Name(stack_protector_guard) Type(enum stack_protector_guard)
 546 Valid arguments to -mstack-protector-guard=:
 547
 548 EnumValue
 549 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
 550
 551 EnumValue
 552 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
 553
 554 mstack-protector-guard-reg=
 555 Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
 556 Use the given base register for addressing the stack-protector guard.
 557
 558 TargetVariable
 559 int rs6000_stack_protector_guard_reg = 0
 560
 561 mstack-protector-guard-offset=
 562 Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
 563 Use the given offset for addressing the stack-protector guard.
 564
 565 TargetVariable
 566 long rs6000_stack_protector_guard_offset = 0
 567
 568 ;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect
 569 ;; branches via the CTR.
 570 mspeculate-indirect-jumps
 571 Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
 572
 573 mfuture
 574 Target Report Mask(FUTURE) Var(rs6000_isa_flags)
 575 Use instructions for a future architecture.