projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
rx.h (PTRDIFF_TYPE): Define.
[gcc.git] / gcc / config / rx / rx.c
1 /* Subroutines used for code generation on Renesas RX processors.
2 Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 /* To Do:
22
23 * Re-enable memory-to-memory copies and fix up reload. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "tree.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "function.h"
39 #include "expr.h"
40 #include "optabs.h"
41 #include "libfuncs.h"
42 #include "recog.h"
43 #include "toplev.h"
44 #include "reload.h"
45 #include "df.h"
46 #include "ggc.h"
47 #include "tm_p.h"
48 #include "debug.h"
49 #include "target.h"
50 #include "target-def.h"
51 #include "langhooks.h"
52 \f
53 static void rx_print_operand (FILE *, rtx, int);
54
55 enum rx_cpu_types rx_cpu_type = RX600;
56 \f
57 /* Return true if OP is a reference to an object in a small data area. */
58
59 static bool
60 rx_small_data_operand (rtx op)
61 {
62 if (rx_small_data_limit == 0)
63 return false;
64
65 if (GET_CODE (op) == SYMBOL_REF)
66 return SYMBOL_REF_SMALL_P (op);
67
68 return false;
69 }
70
71 static bool
72 rx_is_legitimate_address (Mmode mode, rtx x, bool strict ATTRIBUTE_UNUSED)
73 {
74 if (RTX_OK_FOR_BASE (x, strict))
75 /* Register Indirect. */
76 return true;
77
78 if (GET_MODE_SIZE (mode) == 4
79 && (GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC))
80 /* Pre-decrement Register Indirect or
81 Post-increment Register Indirect. */
82 return RTX_OK_FOR_BASE (XEXP (x, 0), strict);
83
84 if (GET_CODE (x) == PLUS)
85 {
86 rtx arg1 = XEXP (x, 0);
87 rtx arg2 = XEXP (x, 1);
88 rtx index = NULL_RTX;
89
90 if (REG_P (arg1) && RTX_OK_FOR_BASE (arg1, strict))
91 index = arg2;
92 else if (REG_P (arg2) && RTX_OK_FOR_BASE (arg2, strict))
93 index = arg1;
94 else
95 return false;
96
97 switch (GET_CODE (index))
98 {
99 case CONST_INT:
100 {
101 /* Register Relative: REG + INT.
102 Only positive, mode-aligned, mode-sized
103 displacements are allowed. */
104 HOST_WIDE_INT val = INTVAL (index);
105 int factor;
106
107 if (val < 0)
108 return false;
109
110 switch (GET_MODE_SIZE (mode))
111 {
112 default:
113 case 4: factor = 4; break;
114 case 2: factor = 2; break;
115 case 1: factor = 1; break;
116 }
117
118 if (val > (65535 * factor))
119 return false;
120 return (val % factor) == 0;
121 }
122
123 case REG:
124 /* Unscaled Indexed Register Indirect: REG + REG
125 Size has to be "QI", REG has to be valid. */
126 return GET_MODE_SIZE (mode) == 1 && RTX_OK_FOR_BASE (index, strict);
127
128 case MULT:
129 {
130 /* Scaled Indexed Register Indirect: REG + (REG * FACTOR)
131 Factor has to equal the mode size, REG has to be valid. */
132 rtx factor;
133
134 factor = XEXP (index, 1);
135 index = XEXP (index, 0);
136
137 return REG_P (index)
138 && RTX_OK_FOR_BASE (index, strict)
139 && CONST_INT_P (factor)
140 && GET_MODE_SIZE (mode) == INTVAL (factor);
141 }
142
143 default:
144 return false;
145 }
146 }
147
148 /* Small data area accesses turn into register relative offsets. */
149 return rx_small_data_operand (x);
150 }
151
152 /* Returns TRUE for simple memory addreses, ie ones
153 that do not involve register indirect addressing
154 or pre/post increment/decrement. */
155
156 bool
157 rx_is_restricted_memory_address (rtx mem, enum machine_mode mode)
158 {
159 rtx base, index;
160
161 if (! rx_is_legitimate_address
162 (mode, mem, reload_in_progress || reload_completed))
163 return false;
164
165 switch (GET_CODE (mem))
166 {
167 case REG:
168 /* Simple memory addresses are OK. */
169 return true;
170
171 case PRE_DEC:
172 case POST_INC:
173 return false;
174
175 case PLUS:
176 /* Only allow REG+INT addressing. */
177 base = XEXP (mem, 0);
178 index = XEXP (mem, 1);
179
180 return RX_REG_P (base) && CONST_INT_P (index);
181
182 case SYMBOL_REF:
183 /* Can happen when small data is being supported.
184 Assume that it will be resolved into GP+INT. */
185 return true;
186
187 default:
188 gcc_unreachable ();
189 }
190 }
191
192 bool
193 rx_is_mode_dependent_addr (rtx addr)
194 {
195 if (GET_CODE (addr) == CONST)
196 addr = XEXP (addr, 0);
197
198 switch (GET_CODE (addr))
199 {
200 /* --REG and REG++ only work in SImode. */
201 case PRE_DEC:
202 case POST_INC:
203 return true;
204
205 case MINUS:
206 case PLUS:
207 if (! REG_P (XEXP (addr, 0)))
208 return true;
209
210 addr = XEXP (addr, 1);
211
212 switch (GET_CODE (addr))
213 {
214 case REG:
215 /* REG+REG only works in SImode. */
216 return true;
217
218 case CONST_INT:
219 /* REG+INT is only mode independent if INT is a
220 multiple of 4, positive and will fit into 8-bits. */
221 if (((INTVAL (addr) & 3) == 0)
222 && IN_RANGE (INTVAL (addr), 4, 252))
223 return false;
224 return true;
225
226 case SYMBOL_REF:
227 case LABEL_REF:
228 return true;
229
230 case MULT:
231 gcc_assert (REG_P (XEXP (addr, 0)));
232 gcc_assert (CONST_INT_P (XEXP (addr, 1)));
233 /* REG+REG*SCALE is always mode dependent. */
234 return true;
235
236 default:
237 /* Not recognized, so treat as mode dependent. */
238 return true;
239 }
240
241 case CONST_INT:
242 case SYMBOL_REF:
243 case LABEL_REF:
244 case REG:
245 /* These are all mode independent. */
246 return false;
247
248 default:
249 /* Everything else is unrecognized,
250 so treat as mode dependent. */
251 return true;
252 }
253 }
254 \f
255 /* A C compound statement to output to stdio stream FILE the
256 assembler syntax for an instruction operand that is a memory
257 reference whose address is ADDR. */
258
259 static void
260 rx_print_operand_address (FILE * file, rtx addr)
261 {
262 switch (GET_CODE (addr))
263 {
264 case REG:
265 fprintf (file, "[");
266 rx_print_operand (file, addr, 0);
267 fprintf (file, "]");
268 break;
269
270 case PRE_DEC:
271 fprintf (file, "[-");
272 rx_print_operand (file, XEXP (addr, 0), 0);
273 fprintf (file, "]");
274 break;
275
276 case POST_INC:
277 fprintf (file, "[");
278 rx_print_operand (file, XEXP (addr, 0), 0);
279 fprintf (file, "+]");
280 break;
281
282 case PLUS:
283 {
284 rtx arg1 = XEXP (addr, 0);
285 rtx arg2 = XEXP (addr, 1);
286 rtx base, index;
287
288 if (REG_P (arg1) && RTX_OK_FOR_BASE (arg1, true))
289 base = arg1, index = arg2;
290 else if (REG_P (arg2) && RTX_OK_FOR_BASE (arg2, true))
291 base = arg2, index = arg1;
292 else
293 {
294 rx_print_operand (file, arg1, 0);
295 fprintf (file, " + ");
296 rx_print_operand (file, arg2, 0);
297 break;
298 }
299
300 if (REG_P (index) || GET_CODE (index) == MULT)
301 {
302 fprintf (file, "[");
303 rx_print_operand (file, index, 'A');
304 fprintf (file, ",");
305 }
306 else /* GET_CODE (index) == CONST_INT */
307 {
308 rx_print_operand (file, index, 'A');
309 fprintf (file, "[");
310 }
311 rx_print_operand (file, base, 0);
312 fprintf (file, "]");
313 break;
314 }
315
316 case LABEL_REF:
317 case SYMBOL_REF:
318 case CONST:
319 fprintf (file, "#");
320 default:
321 output_addr_const (file, addr);
322 break;
323 }
324 }
325
326 static void
327 rx_print_integer (FILE * file, HOST_WIDE_INT val)
328 {
329 if (IN_RANGE (val, -64, 64))
330 fprintf (file, HOST_WIDE_INT_PRINT_DEC, val);
331 else
332 fprintf (file,
333 TARGET_AS100_SYNTAX
334 ? "0%" HOST_WIDE_INT_PRINT "xH" : HOST_WIDE_INT_PRINT_HEX,
335 val);
336 }
337
338 static bool
339 rx_assemble_integer (rtx x, unsigned int size, int is_aligned)
340 {
341 const char * op = integer_asm_op (size, is_aligned);
342
343 if (! CONST_INT_P (x))
344 return default_assemble_integer (x, size, is_aligned);
345
346 if (op == NULL)
347 return false;
348 fputs (op, asm_out_file);
349
350 rx_print_integer (asm_out_file, INTVAL (x));
351 fputc ('\n', asm_out_file);
352 return true;
353 }
354
355
356 int rx_float_compare_mode;
357
358 /* Handles the insertion of a single operand into the assembler output.
359 The %<letter> directives supported are:
360
361 %A Print an operand without a leading # character.
362 %B Print an integer comparison name.
363 %C Print a control register name.
364 %F Print a condition code flag name.
365 %H Print high part of a DImode register, integer or address.
366 %L Print low part of a DImode register, integer or address.
367 %N Print the negation of the immediate value.
368 %Q If the operand is a MEM, then correctly generate
369 register indirect or register relative addressing. */
370
371 static void
372 rx_print_operand (FILE * file, rtx op, int letter)
373 {
374 switch (letter)
375 {
376 case 'A':
377 /* Print an operand without a leading #. */
378 if (MEM_P (op))
379 op = XEXP (op, 0);
380
381 switch (GET_CODE (op))
382 {
383 case LABEL_REF:
384 case SYMBOL_REF:
385 output_addr_const (file, op);
386 break;
387 case CONST_INT:
388 fprintf (file, "%ld", (long) INTVAL (op));
389 break;
390 default:
391 rx_print_operand (file, op, 0);
392 break;
393 }
394 break;
395
396 case 'B':
397 switch (GET_CODE (op))
398 {
399 case LT: fprintf (file, "lt"); break;
400 case GE: fprintf (file, "ge"); break;
401 case GT: fprintf (file, "gt"); break;
402 case LE: fprintf (file, "le"); break;
403 case GEU: fprintf (file, "geu"); break;
404 case LTU: fprintf (file, "ltu"); break;
405 case GTU: fprintf (file, "gtu"); break;
406 case LEU: fprintf (file, "leu"); break;
407 case EQ: fprintf (file, "eq"); break;
408 case NE: fprintf (file, "ne"); break;
409 default: debug_rtx (op); gcc_unreachable ();
410 }
411 break;
412
413 case 'C':
414 gcc_assert (CONST_INT_P (op));
415 switch (INTVAL (op))
416 {
417 case 0: fprintf (file, "psw"); break;
418 case 2: fprintf (file, "usp"); break;
419 case 3: fprintf (file, "fpsw"); break;
420 case 4: fprintf (file, "cpen"); break;
421 case 8: fprintf (file, "bpsw"); break;
422 case 9: fprintf (file, "bpc"); break;
423 case 0xa: fprintf (file, "isp"); break;
424 case 0xb: fprintf (file, "fintv"); break;
425 case 0xc: fprintf (file, "intb"); break;
426 default:
427 warning (0, "unreocgnized control register number: %d - using 'psw'",
428 (int) INTVAL (op));
429 fprintf (file, "psw");
430 break;
431 }
432 break;
433
434 case 'F':
435 gcc_assert (CONST_INT_P (op));
436 switch (INTVAL (op))
437 {
438 case 0: case 'c': case 'C': fprintf (file, "C"); break;
439 case 1: case 'z': case 'Z': fprintf (file, "Z"); break;
440 case 2: case 's': case 'S': fprintf (file, "S"); break;
441 case 3: case 'o': case 'O': fprintf (file, "O"); break;
442 case 8: case 'i': case 'I': fprintf (file, "I"); break;
443 case 9: case 'u': case 'U': fprintf (file, "U"); break;
444 default:
445 gcc_unreachable ();
446 }
447 break;
448
449 case 'H':
450 switch (GET_CODE (op))
451 {
452 case REG:
453 fprintf (file, "%s", reg_names [REGNO (op) + (WORDS_BIG_ENDIAN ? 0 : 1)]);
454 break;
455 case CONST_INT:
456 {
457 HOST_WIDE_INT v = INTVAL (op);
458
459 fprintf (file, "#");
460 /* Trickery to avoid problems with shifting 32 bits at a time. */
461 v = v >> 16;
462 v = v >> 16;
463 rx_print_integer (file, v);
464 break;
465 }
466 case CONST_DOUBLE:
467 fprintf (file, "#");
468 rx_print_integer (file, CONST_DOUBLE_HIGH (op));
469 break;
470 case MEM:
471 if (! WORDS_BIG_ENDIAN)
472 op = adjust_address (op, SImode, 4);
473 output_address (XEXP (op, 0));
474 break;
475 default:
476 gcc_unreachable ();
477 }
478 break;
479
480 case 'L':
481 switch (GET_CODE (op))
482 {
483 case REG:
484 fprintf (file, "%s", reg_names [REGNO (op) + (WORDS_BIG_ENDIAN ? 1 : 0)]);
485 break;
486 case CONST_INT:
487 fprintf (file, "#");
488 rx_print_integer (file, INTVAL (op) & 0xffffffff);
489 break;
490 case CONST_DOUBLE:
491 fprintf (file, "#");
492 rx_print_integer (file, CONST_DOUBLE_LOW (op));
493 break;
494 case MEM:
495 if (WORDS_BIG_ENDIAN)
496 op = adjust_address (op, SImode, 4);
497 output_address (XEXP (op, 0));
498 break;
499 default:
500 gcc_unreachable ();
501 }
502 break;
503
504 case 'N':
505 gcc_assert (CONST_INT_P (op));
506 fprintf (file, "#");
507 rx_print_integer (file, - INTVAL (op));
508 break;
509
510 case 'Q':
511 if (MEM_P (op))
512 {
513 HOST_WIDE_INT offset;
514
515 op = XEXP (op, 0);
516
517 if (REG_P (op))
518 offset = 0;
519 else if (GET_CODE (op) == PLUS)
520 {
521 rtx displacement;
522
523 if (REG_P (XEXP (op, 0)))
524 {
525 displacement = XEXP (op, 1);
526 op = XEXP (op, 0);
527 }
528 else
529 {
530 displacement = XEXP (op, 0);
531 op = XEXP (op, 1);
532 gcc_assert (REG_P (op));
533 }
534
535 gcc_assert (CONST_INT_P (displacement));
536 offset = INTVAL (displacement);
537 gcc_assert (offset >= 0);
538
539 fprintf (file, "%ld", offset);
540 }
541 else
542 gcc_unreachable ();
543
544 fprintf (file, "[");
545 rx_print_operand (file, op, 0);
546 fprintf (file, "].");
547
548 switch (GET_MODE_SIZE (GET_MODE (op)))
549 {
550 case 1:
551 gcc_assert (offset < 65535 * 1);
552 fprintf (file, "B");
553 break;
554 case 2:
555 gcc_assert (offset % 2 == 0);
556 gcc_assert (offset < 65535 * 2);
557 fprintf (file, "W");
558 break;
559 default:
560 gcc_assert (offset % 4 == 0);
561 gcc_assert (offset < 65535 * 4);
562 fprintf (file, "L");
563 break;
564 }
565 break;
566 }
567
568 /* Fall through. */
569
570 default:
571 switch (GET_CODE (op))
572 {
573 case MULT:
574 /* Should be the scaled part of an
575 indexed register indirect address. */
576 {
577 rtx base = XEXP (op, 0);
578 rtx index = XEXP (op, 1);
579
580 /* Check for a swaped index register and scaling factor.
581 Not sure if this can happen, but be prepared to handle it. */
582 if (CONST_INT_P (base) && REG_P (index))
583 {
584 rtx tmp = base;
585 base = index;
586 index = tmp;
587 }
588
589 gcc_assert (REG_P (base));
590 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
591 gcc_assert (CONST_INT_P (index));
592 /* Do not try to verify the value of the scalar as it is based
593 on the mode of the MEM not the mode of the MULT. (Which
594 will always be SImode). */
595 fprintf (file, "%s", reg_names [REGNO (base)]);
596 break;
597 }
598
599 case MEM:
600 output_address (XEXP (op, 0));
601 break;
602
603 case PLUS:
604 output_address (op);
605 break;
606
607 case REG:
608 gcc_assert (REGNO (op) < FIRST_PSEUDO_REGISTER);
609 fprintf (file, "%s", reg_names [REGNO (op)]);
610 break;
611
612 case SUBREG:
613 gcc_assert (subreg_regno (op) < FIRST_PSEUDO_REGISTER);
614 fprintf (file, "%s", reg_names [subreg_regno (op)]);
615 break;
616
617 /* This will only be single precision.... */
618 case CONST_DOUBLE:
619 {
620 unsigned long val;
621 REAL_VALUE_TYPE rv;
622
623 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
624 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
625 fprintf (file, TARGET_AS100_SYNTAX ? "#0%lxH" : "#0x%lx", val);
626 break;
627 }
628
629 case CONST_INT:
630 fprintf (file, "#");
631 rx_print_integer (file, INTVAL (op));
632 break;
633
634 case SYMBOL_REF:
635 case CONST:
636 case LABEL_REF:
637 case CODE_LABEL:
638 case UNSPEC:
639 rx_print_operand_address (file, op);
640 break;
641
642 default:
643 gcc_unreachable ();
644 }
645 break;
646 }
647 }
648
649 /* Returns an assembler template for a move instruction. */
650
651 char *
652 rx_gen_move_template (rtx * operands, bool is_movu)
653 {
654 static char out_template [64];
655 const char * extension = TARGET_AS100_SYNTAX ? ".L" : "";
656 const char * src_template;
657 const char * dst_template;
658 rtx dest = operands[0];
659 rtx src = operands[1];
660
661 /* Decide which extension, if any, should be given to the move instruction. */
662 switch (CONST_INT_P (src) ? GET_MODE (dest) : GET_MODE (src))
663 {
664 case QImode:
665 /* The .B extension is not valid when
666 loading an immediate into a register. */
667 if (! REG_P (dest) || ! CONST_INT_P (src))
668 extension = ".B";
669 break;
670 case HImode:
671 if (! REG_P (dest) || ! CONST_INT_P (src))
672 /* The .W extension is not valid when
673 loading an immediate into a register. */
674 extension = ".W";
675 break;
676 case SFmode:
677 case SImode:
678 extension = ".L";
679 break;
680 case VOIDmode:
681 /* This mode is used by constants. */
682 break;
683 default:
684 debug_rtx (src);
685 gcc_unreachable ();
686 }
687
688 if (MEM_P (src) && rx_small_data_operand (XEXP (src, 0)))
689 src_template = "%%gp(%A1)[r13]";
690 else
691 src_template = "%1";
692
693 if (MEM_P (dest) && rx_small_data_operand (XEXP (dest, 0)))
694 dst_template = "%%gp(%A0)[r13]";
695 else
696 dst_template = "%0";
697
698 sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
699 extension, src_template, dst_template);
700 return out_template;
701 }
702
703 /* Returns an assembler template for a conditional branch instruction. */
704
705 const char *
706 rx_gen_cond_branch_template (rtx condition, bool reversed)
707 {
708 enum rtx_code code = GET_CODE (condition);
709
710 if ((cc_status.flags & CC_NO_OVERFLOW) && ! rx_float_compare_mode)
711 gcc_assert (code != GT && code != GE && code != LE && code != LT);
712
713 if ((cc_status.flags & CC_NO_CARRY) || rx_float_compare_mode)
714 gcc_assert (code != GEU && code != GTU && code != LEU && code != LTU);
715
716 if (reversed)
717 {
718 if (rx_float_compare_mode)
719 code = reverse_condition_maybe_unordered (code);
720 else
721 code = reverse_condition (code);
722 }
723
724 /* We do not worry about encoding the branch length here as GAS knows
725 how to choose the smallest version, and how to expand a branch that
726 is to a destination that is out of range. */
727
728 switch (code)
729 {
730 case UNEQ: return "bo\t1f\n\tbeq\t%0\n1:";
731 case LTGT: return "bo\t1f\n\tbne\t%0\n1:";
732 case UNLT: return "bo\t1f\n\tbn\t%0\n1:";
733 case UNGE: return "bo\t1f\n\tbpz\t%0\n1:";
734 case UNLE: return "bo\t1f\n\tbgt\t1f\n\tbra\t%0\n1:";
735 case UNGT: return "bo\t1f\n\tble\t1f\n\tbra\t%0\n1:";
736 case UNORDERED: return "bo\t%0";
737 case ORDERED: return "bno\t%0";
738
739 case LT: return rx_float_compare_mode ? "bn\t%0" : "blt\t%0";
740 case GE: return rx_float_compare_mode ? "bpz\t%0" : "bge\t%0";
741 case GT: return "bgt\t%0";
742 case LE: return "ble\t%0";
743 case GEU: return "bgeu\t%0";
744 case LTU: return "bltu\t%0";
745 case GTU: return "bgtu\t%0";
746 case LEU: return "bleu\t%0";
747 case EQ: return "beq\t%0";
748 case NE: return "bne\t%0";
749 default:
750 gcc_unreachable ();
751 }
752 }
753 \f
754 /* Return VALUE rounded up to the next ALIGNMENT boundary. */
755
756 static inline unsigned int
757 rx_round_up (unsigned int value, unsigned int alignment)
758 {
759 alignment -= 1;
760 return (value + alignment) & (~ alignment);
761 }
762
763 /* Return the number of bytes in the argument registers
764 occupied by an argument of type TYPE and mode MODE. */
765
766 unsigned int
767 rx_function_arg_size (Mmode mode, const_tree type)
768 {
769 unsigned int num_bytes;
770
771 num_bytes = (mode == BLKmode)
772 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
773 return rx_round_up (num_bytes, UNITS_PER_WORD);
774 }
775
776 #define NUM_ARG_REGS 4
777 #define MAX_NUM_ARG_BYTES (NUM_ARG_REGS * UNITS_PER_WORD)
778
779 /* Return an RTL expression describing the register holding a function
780 parameter of mode MODE and type TYPE or NULL_RTX if the parameter should
781 be passed on the stack. CUM describes the previous parameters to the
782 function and NAMED is false if the parameter is part of a variable
783 parameter list, or the last named parameter before the start of a
784 variable parameter list. */
785
786 rtx
787 rx_function_arg (Fargs * cum, Mmode mode, const_tree type, bool named)
788 {
789 unsigned int next_reg;
790 unsigned int bytes_so_far = *cum;
791 unsigned int size;
792 unsigned int rounded_size;
793
794 /* An exploded version of rx_function_arg_size. */
795 size = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
796 /* If the size is not known it cannot be passed in registers. */
797 if (size < 1)
798 return NULL_RTX;
799
800 rounded_size = rx_round_up (size, UNITS_PER_WORD);
801
802 /* Don't pass this arg via registers if there
803 are insufficient registers to hold all of it. */
804 if (rounded_size + bytes_so_far > MAX_NUM_ARG_BYTES)
805 return NULL_RTX;
806
807 /* Unnamed arguments and the last named argument in a
808 variadic function are always passed on the stack. */
809 if (!named)
810 return NULL_RTX;
811
812 /* Structures must occupy an exact number of registers,
813 otherwise they are passed on the stack. */
814 if ((type == NULL || AGGREGATE_TYPE_P (type))
815 && (size % UNITS_PER_WORD) != 0)
816 return NULL_RTX;
817
818 next_reg = (bytes_so_far / UNITS_PER_WORD) + 1;
819
820 return gen_rtx_REG (mode, next_reg);
821 }
822
823 /* Return an RTL describing where a function return value of type RET_TYPE
824 is held. */
825
826 static rtx
827 rx_function_value (const_tree ret_type,
828 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
829 bool outgoing ATTRIBUTE_UNUSED)
830 {
831 return gen_rtx_REG (TYPE_MODE (ret_type), FUNC_RETURN_REGNUM);
832 }
833
834 static bool
835 rx_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
836 {
837 HOST_WIDE_INT size;
838
839 if (TYPE_MODE (type) != BLKmode
840 && ! AGGREGATE_TYPE_P (type))
841 return false;
842
843 size = int_size_in_bytes (type);
844 /* Large structs and those whose size is not an
845 exact multiple of 4 are returned in memory. */
846 return size < 1
847 || size > 16
848 || (size % UNITS_PER_WORD) != 0;
849 }
850
851 static rtx
852 rx_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
853 int incoming ATTRIBUTE_UNUSED)
854 {
855 return gen_rtx_REG (Pmode, STRUCT_VAL_REGNUM);
856 }
857
858 static bool
859 rx_return_in_msb (const_tree valtype)
860 {
861 return TARGET_BIG_ENDIAN_DATA
862 && (AGGREGATE_TYPE_P (valtype) || TREE_CODE (valtype) == COMPLEX_TYPE);
863 }
864
865 /* Returns true if the provided function has the specified attribute. */
866
867 static inline bool
868 has_func_attr (const_tree decl, const char * func_attr)
869 {
870 if (decl == NULL_TREE)
871 decl = current_function_decl;
872
873 return lookup_attribute (func_attr, DECL_ATTRIBUTES (decl)) != NULL_TREE;
874 }
875
876 /* Returns true if the provided function has the "fast_interrupt" attribute. */
877
878 static inline bool
879 is_fast_interrupt_func (const_tree decl)
880 {
881 return has_func_attr (decl, "fast_interrupt");
882 }
883
884 /* Returns true if the provided function has the "interrupt" attribute. */
885
886 static inline bool
887 is_interrupt_func (const_tree decl)
888 {
889 return has_func_attr (decl, "interrupt");
890 }
891
892 /* Returns true if the provided function has the "naked" attribute. */
893
894 static inline bool
895 is_naked_func (const_tree decl)
896 {
897 return has_func_attr (decl, "naked");
898 }
899 \f
900 static bool use_fixed_regs = false;
901
902 void
903 rx_conditional_register_usage (void)
904 {
905 static bool using_fixed_regs = false;
906
907 if (rx_small_data_limit > 0)
908 fixed_regs[GP_BASE_REGNUM] = call_used_regs [GP_BASE_REGNUM] = 1;
909
910 if (use_fixed_regs != using_fixed_regs)
911 {
912 static char saved_fixed_regs[FIRST_PSEUDO_REGISTER];
913 static char saved_call_used_regs[FIRST_PSEUDO_REGISTER];
914
915 if (use_fixed_regs)
916 {
917 unsigned int r;
918
919 memcpy (saved_fixed_regs, fixed_regs, sizeof fixed_regs);
920 memcpy (saved_call_used_regs, call_used_regs, sizeof call_used_regs);
921
922 /* This is for fast interrupt handlers. Any register in
923 the range r10 to r13 (inclusive) that is currently
924 marked as fixed is now a viable, call-used register. */
925 for (r = 10; r <= 13; r++)
926 if (fixed_regs[r])
927 {
928 fixed_regs[r] = 0;
929 call_used_regs[r] = 1;
930 }
931
932 /* Mark r7 as fixed. This is just a hack to avoid
933 altering the reg_alloc_order array so that the newly
934 freed r10-r13 registers are the preferred registers. */
935 fixed_regs[7] = call_used_regs[7] = 1;
936 }
937 else
938 {
939 /* Restore the normal register masks. */
940 memcpy (fixed_regs, saved_fixed_regs, sizeof fixed_regs);
941 memcpy (call_used_regs, saved_call_used_regs, sizeof call_used_regs);
942 }
943
944 using_fixed_regs = use_fixed_regs;
945 }
946 }
947
948 /* Perform any actions necessary before starting to compile FNDECL.
949 For the RX we use this to make sure that we have the correct
950 set of register masks selected. If FNDECL is NULL then we are
951 compiling top level things. */
952
953 static void
954 rx_set_current_function (tree fndecl)
955 {
956 /* Remember the last target of rx_set_current_function. */
957 static tree rx_previous_fndecl;
958 bool prev_was_fast_interrupt;
959 bool current_is_fast_interrupt;
960
961 /* Only change the context if the function changes. This hook is called
962 several times in the course of compiling a function, and we don't want
963 to slow things down too much or call target_reinit when it isn't safe. */
964 if (fndecl == rx_previous_fndecl)
965 return;
966
967 prev_was_fast_interrupt
968 = rx_previous_fndecl
969 ? is_fast_interrupt_func (rx_previous_fndecl) : false;
970
971 current_is_fast_interrupt
972 = fndecl ? is_fast_interrupt_func (fndecl) : false;
973
974 if (prev_was_fast_interrupt != current_is_fast_interrupt)
975 {
976 use_fixed_regs = current_is_fast_interrupt;
977 target_reinit ();
978 }
979
980 rx_previous_fndecl = fndecl;
981 }
982 \f
983 /* Typical stack layout should looks like this after the function's prologue:
984
985 | |
986 -- ^
987 | | \ |
988 | | arguments saved | Increasing
989 | | on the stack | addresses
990 PARENT arg pointer -> | | /
991 -------------------------- ---- -------------------
992 CHILD |ret | return address
993 --
994 | | \
995 | | call saved
996 | | registers
997 | | /
998 --
999 | | \
1000 | | local
1001 | | variables
1002 frame pointer -> | | /
1003 --
1004 | | \
1005 | | outgoing | Decreasing
1006 | | arguments | addresses
1007 current stack pointer -> | | / |
1008 -------------------------- ---- ------------------ V
1009 | | */
1010
1011 static unsigned int
1012 bit_count (unsigned int x)
1013 {
1014 const unsigned int m1 = 0x55555555;
1015 const unsigned int m2 = 0x33333333;
1016 const unsigned int m4 = 0x0f0f0f0f;
1017
1018 x -= (x >> 1) & m1;
1019 x = (x & m2) + ((x >> 2) & m2);
1020 x = (x + (x >> 4)) & m4;
1021 x += x >> 8;
1022
1023 return (x + (x >> 16)) & 0x3f;
1024 }
1025
1026 #define MUST_SAVE_ACC_REGISTER \
1027 (TARGET_SAVE_ACC_REGISTER \
1028 && (is_interrupt_func (NULL_TREE) \
1029 || is_fast_interrupt_func (NULL_TREE)))
1030
1031 /* Returns either the lowest numbered and highest numbered registers that
1032 occupy the call-saved area of the stack frame, if the registers are
1033 stored as a contiguous block, or else a bitmask of the individual
1034 registers if they are stored piecemeal.
1035
1036 Also computes the size of the frame and the size of the outgoing
1037 arguments block (in bytes). */
1038
1039 static void
1040 rx_get_stack_layout (unsigned int * lowest,
1041 unsigned int * highest,
1042 unsigned int * register_mask,
1043 unsigned int * frame_size,
1044 unsigned int * stack_size)
1045 {
1046 unsigned int reg;
1047 unsigned int low;
1048 unsigned int high;
1049 unsigned int fixed_reg = 0;
1050 unsigned int save_mask;
1051 unsigned int pushed_mask;
1052 unsigned int unneeded_pushes;
1053
1054 if (is_naked_func (NULL_TREE))
1055 {
1056 /* Naked functions do not create their own stack frame.
1057 Instead the programmer must do that for us. */
1058 * lowest = 0;
1059 * highest = 0;
1060 * register_mask = 0;
1061 * frame_size = 0;
1062 * stack_size = 0;
1063 return;
1064 }
1065
1066 for (save_mask = high = low = 0, reg = 1; reg < FIRST_PSEUDO_REGISTER; reg++)
1067 {
1068 if (df_regs_ever_live_p (reg)
1069 && (! call_used_regs[reg]
1070 /* Even call clobbered registered must
1071 be pushed inside interrupt handlers. */
1072 || is_interrupt_func (NULL_TREE)
1073 /* Likewise for fast interrupt handlers, except registers r10 -
1074 r13. These are normally call-saved, but may have been set
1075 to call-used by rx_conditional_register_usage. If so then
1076 they can be used in the fast interrupt handler without
1077 saving them on the stack. */
1078 || (is_fast_interrupt_func (NULL_TREE)
1079 && ! IN_RANGE (reg, 10, 13))))
1080 {
1081 if (low == 0)
1082 low = reg;
1083 high = reg;
1084
1085 save_mask |= 1 << reg;
1086 }
1087
1088 /* Remember if we see a fixed register
1089 after having found the low register. */
1090 if (low != 0 && fixed_reg == 0 && fixed_regs [reg])
1091 fixed_reg = reg;
1092 }
1093
1094 /* If we have to save the accumulator register, make sure
1095 that at least two registers are pushed into the frame. */
1096 if (MUST_SAVE_ACC_REGISTER
1097 && bit_count (save_mask) < 2)
1098 {
1099 save_mask |= (1 << 13) | (1 << 14);
1100 if (low == 0)
1101 low = 13;
1102 if (high == 0 || low == high)
1103 high = low + 1;
1104 }
1105
1106 /* Decide if it would be faster fill in the call-saved area of the stack
1107 frame using multiple PUSH instructions instead of a single PUSHM
1108 instruction.
1109
1110 SAVE_MASK is a bitmask of the registers that must be stored in the
1111 call-save area. PUSHED_MASK is a bitmask of the registers that would
1112 be pushed into the area if we used a PUSHM instruction. UNNEEDED_PUSHES
1113 is a bitmask of those registers in pushed_mask that are not in
1114 save_mask.
1115
1116 We use a simple heuristic that says that it is better to use
1117 multiple PUSH instructions if the number of unnecessary pushes is
1118 greater than the number of necessary pushes.
1119
1120 We also use multiple PUSH instructions if there are any fixed registers
1121 between LOW and HIGH. The only way that this can happen is if the user
1122 has specified --fixed-<reg-name> on the command line and in such
1123 circumstances we do not want to touch the fixed registers at all.
1124
1125 FIXME: Is it worth improving this heuristic ? */
1126 pushed_mask = (-1 << low) & ~(-1 << (high + 1));
1127 unneeded_pushes = (pushed_mask & (~ save_mask)) & pushed_mask;
1128
1129 if ((fixed_reg && fixed_reg <= high)
1130 || (optimize_function_for_speed_p (cfun)
1131 && bit_count (save_mask) < bit_count (unneeded_pushes)))
1132 {
1133 /* Use multiple pushes. */
1134 * lowest = 0;
1135 * highest = 0;
1136 * register_mask = save_mask;
1137 }
1138 else
1139 {
1140 /* Use one push multiple instruction. */
1141 * lowest = low;
1142 * highest = high;
1143 * register_mask = 0;
1144 }
1145
1146 * frame_size = rx_round_up
1147 (get_frame_size (), STACK_BOUNDARY / BITS_PER_UNIT);
1148
1149 if (crtl->args.size > 0)
1150 * frame_size += rx_round_up
1151 (crtl->args.size, STACK_BOUNDARY / BITS_PER_UNIT);
1152
1153 * stack_size = rx_round_up
1154 (crtl->outgoing_args_size, STACK_BOUNDARY / BITS_PER_UNIT);
1155 }
1156
1157 /* Generate a PUSHM instruction that matches the given operands. */
1158
1159 void
1160 rx_emit_stack_pushm (rtx * operands)
1161 {
1162 HOST_WIDE_INT last_reg;
1163 rtx first_push;
1164
1165 gcc_assert (CONST_INT_P (operands[0]));
1166 last_reg = (INTVAL (operands[0]) / UNITS_PER_WORD) - 1;
1167
1168 gcc_assert (GET_CODE (operands[1]) == PARALLEL);
1169 first_push = XVECEXP (operands[1], 0, 1);
1170 gcc_assert (SET_P (first_push));
1171 first_push = SET_SRC (first_push);
1172 gcc_assert (REG_P (first_push));
1173
1174 asm_fprintf (asm_out_file, "\tpushm\t%s-%s\n",
1175 reg_names [REGNO (first_push) - last_reg],
1176 reg_names [REGNO (first_push)]);
1177 }
1178
1179 /* Generate a PARALLEL that will pass the rx_store_multiple_vector predicate. */
1180
1181 static rtx
1182 gen_rx_store_vector (unsigned int low, unsigned int high)
1183 {
1184 unsigned int i;
1185 unsigned int count = (high - low) + 2;
1186 rtx vector;
1187
1188 vector = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1189
1190 XVECEXP (vector, 0, 0) =
1191 gen_rtx_SET (SImode, stack_pointer_rtx,
1192 gen_rtx_MINUS (SImode, stack_pointer_rtx,
1193 GEN_INT ((count - 1) * UNITS_PER_WORD)));
1194
1195 for (i = 0; i < count - 1; i++)
1196 XVECEXP (vector, 0, i + 1) =
1197 gen_rtx_SET (SImode,
1198 gen_rtx_MEM (SImode,
1199 gen_rtx_MINUS (SImode, stack_pointer_rtx,
1200 GEN_INT ((i + 1) * UNITS_PER_WORD))),
1201 gen_rtx_REG (SImode, high - i));
1202 return vector;
1203 }
1204
1205 /* Mark INSN as being frame related. If it is a PARALLEL
1206 then mark each element as being frame related as well. */
1207
1208 static void
1209 mark_frame_related (rtx insn)
1210 {
1211 RTX_FRAME_RELATED_P (insn) = 1;
1212 insn = PATTERN (insn);
1213
1214 if (GET_CODE (insn) == PARALLEL)
1215 {
1216 unsigned int i;
1217
1218 for (i = 0; i < (unsigned) XVECLEN (insn, 0); i++)
1219 RTX_FRAME_RELATED_P (XVECEXP (insn, 0, i)) = 1;
1220 }
1221 }
1222
1223 void
1224 rx_expand_prologue (void)
1225 {
1226 unsigned int stack_size;
1227 unsigned int frame_size;
1228 unsigned int mask;
1229 unsigned int low;
1230 unsigned int high;
1231 unsigned int reg;
1232 rtx insn;
1233
1234 /* Naked functions use their own, programmer provided prologues. */
1235 if (is_naked_func (NULL_TREE))
1236 return;
1237
1238 rx_get_stack_layout (& low, & high, & mask, & frame_size, & stack_size);
1239
1240 /* If we use any of the callee-saved registers, save them now. */
1241 if (mask)
1242 {
1243 /* Push registers in reverse order. */
1244 for (reg = FIRST_PSEUDO_REGISTER; reg --;)
1245 if (mask & (1 << reg))
1246 {
1247 insn = emit_insn (gen_stack_push (gen_rtx_REG (SImode, reg)));
1248 mark_frame_related (insn);
1249 }
1250 }
1251 else if (low)
1252 {
1253 if (high == low)
1254 insn = emit_insn (gen_stack_push (gen_rtx_REG (SImode, low)));
1255 else
1256 insn = emit_insn (gen_stack_pushm (GEN_INT (((high - low) + 1)
1257 * UNITS_PER_WORD),
1258 gen_rx_store_vector (low, high)));
1259 mark_frame_related (insn);
1260 }
1261
1262 if (MUST_SAVE_ACC_REGISTER)
1263 {
1264 unsigned int acc_high, acc_low;
1265
1266 /* Interrupt handlers have to preserve the accumulator
1267 register if so requested by the user. Use the first
1268 two pushed registers as intermediaries. */
1269 if (mask)
1270 {
1271 acc_low = acc_high = 0;
1272
1273 for (reg = 1; reg < FIRST_PSEUDO_REGISTER; reg ++)
1274 if (mask & (1 << reg))
1275 {
1276 if (acc_low == 0)
1277 acc_low = reg;
1278 else
1279 {
1280 acc_high = reg;
1281 break;
1282 }
1283 }
1284
1285 /* We have assumed that there are at least two registers pushed... */
1286 gcc_assert (acc_high != 0);
1287
1288 /* Note - the bottom 16 bits of the accumulator are inaccessible.
1289 We just assume that they are zero. */
1290 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode, acc_low)));
1291 emit_insn (gen_mvfachi (gen_rtx_REG (SImode, acc_high)));
1292 emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_low)));
1293 emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_high)));
1294 }
1295 else
1296 {
1297 acc_low = low;
1298 acc_high = low + 1;
1299
1300 /* We have assumed that there are at least two registers pushed... */
1301 gcc_assert (acc_high <= high);
1302
1303 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode, acc_low)));
1304 emit_insn (gen_mvfachi (gen_rtx_REG (SImode, acc_high)));
1305 emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
1306 gen_rx_store_vector (acc_low, acc_high)));
1307 }
1308
1309 frame_size += 2 * UNITS_PER_WORD;
1310 }
1311
1312 /* If needed, set up the frame pointer. */
1313 if (frame_pointer_needed)
1314 {
1315 if (frame_size)
1316 insn = emit_insn (gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx,
1317 GEN_INT (- (HOST_WIDE_INT) frame_size)));
1318 else
1319 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
1320
1321 RTX_FRAME_RELATED_P (insn) = 1;
1322 }
1323
1324 insn = NULL_RTX;
1325
1326 /* Allocate space for the outgoing args.
1327 If the stack frame has not already been set up then handle this as well. */
1328 if (stack_size)
1329 {
1330 if (frame_size)
1331 {
1332 if (frame_pointer_needed)
1333 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
1334 GEN_INT (- (HOST_WIDE_INT)
1335 stack_size)));
1336 else
1337 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1338 GEN_INT (- (HOST_WIDE_INT)
1339 (frame_size + stack_size))));
1340 }
1341 else
1342 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1343 GEN_INT (- (HOST_WIDE_INT) stack_size)));
1344 }
1345 else if (frame_size)
1346 {
1347 if (! frame_pointer_needed)
1348 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1349 GEN_INT (- (HOST_WIDE_INT) frame_size)));
1350 else
1351 insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1352 }
1353
1354 if (insn != NULL_RTX)
1355 RTX_FRAME_RELATED_P (insn) = 1;
1356 }
1357
1358 static void
1359 rx_output_function_prologue (FILE * file,
1360 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
1361 {
1362 if (is_fast_interrupt_func (NULL_TREE))
1363 asm_fprintf (file, "\t; Note: Fast Interrupt Handler\n");
1364
1365 if (is_interrupt_func (NULL_TREE))
1366 asm_fprintf (file, "\t; Note: Interrupt Handler\n");
1367
1368 if (is_naked_func (NULL_TREE))
1369 asm_fprintf (file, "\t; Note: Naked Function\n");
1370
1371 if (cfun->static_chain_decl != NULL)
1372 asm_fprintf (file, "\t; Note: Nested function declared "
1373 "inside another function.\n");
1374
1375 if (crtl->calls_eh_return)
1376 asm_fprintf (file, "\t; Note: Calls __builtin_eh_return.\n");
1377 }
1378
1379 /* Generate a POPM or RTSD instruction that matches the given operands. */
1380
1381 void
1382 rx_emit_stack_popm (rtx * operands, bool is_popm)
1383 {
1384 HOST_WIDE_INT stack_adjust;
1385 HOST_WIDE_INT last_reg;
1386 rtx first_push;
1387
1388 gcc_assert (CONST_INT_P (operands[0]));
1389 stack_adjust = INTVAL (operands[0]);
1390
1391 gcc_assert (GET_CODE (operands[1]) == PARALLEL);
1392 last_reg = XVECLEN (operands[1], 0) - (is_popm ? 2 : 3);
1393
1394 first_push = XVECEXP (operands[1], 0, 1);
1395 gcc_assert (SET_P (first_push));
1396 first_push = SET_DEST (first_push);
1397 gcc_assert (REG_P (first_push));
1398
1399 if (is_popm)
1400 asm_fprintf (asm_out_file, "\tpopm\t%s-%s\n",
1401 reg_names [REGNO (first_push)],
1402 reg_names [REGNO (first_push) + last_reg]);
1403 else
1404 asm_fprintf (asm_out_file, "\trtsd\t#%d, %s-%s\n",
1405 (int) stack_adjust,
1406 reg_names [REGNO (first_push)],
1407 reg_names [REGNO (first_push) + last_reg]);
1408 }
1409
1410 /* Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate. */
1411
1412 static rtx
1413 gen_rx_rtsd_vector (unsigned int adjust, unsigned int low, unsigned int high)
1414 {
1415 unsigned int i;
1416 unsigned int bias = 3;
1417 unsigned int count = (high - low) + bias;
1418 rtx vector;
1419
1420 vector = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1421
1422 XVECEXP (vector, 0, 0) =
1423 gen_rtx_SET (SImode, stack_pointer_rtx,
1424 plus_constant (stack_pointer_rtx, adjust));
1425
1426 for (i = 0; i < count - 2; i++)
1427 XVECEXP (vector, 0, i + 1) =
1428 gen_rtx_SET (SImode,
1429 gen_rtx_REG (SImode, low + i),
1430 gen_rtx_MEM (SImode,
1431 i == 0 ? stack_pointer_rtx
1432 : plus_constant (stack_pointer_rtx,
1433 i * UNITS_PER_WORD)));
1434
1435 XVECEXP (vector, 0, count - 1) = gen_rtx_RETURN (VOIDmode);
1436
1437 return vector;
1438 }
1439
1440 /* Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate. */
1441
1442 static rtx
1443 gen_rx_popm_vector (unsigned int low, unsigned int high)
1444 {
1445 unsigned int i;
1446 unsigned int count = (high - low) + 2;
1447 rtx vector;
1448
1449 vector = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1450
1451 XVECEXP (vector, 0, 0) =
1452 gen_rtx_SET (SImode, stack_pointer_rtx,
1453 plus_constant (stack_pointer_rtx,
1454 (count - 1) * UNITS_PER_WORD));
1455
1456 for (i = 0; i < count - 1; i++)
1457 XVECEXP (vector, 0, i + 1) =
1458 gen_rtx_SET (SImode,
1459 gen_rtx_REG (SImode, low + i),
1460 gen_rtx_MEM (SImode,
1461 i == 0 ? stack_pointer_rtx
1462 : plus_constant (stack_pointer_rtx,
1463 i * UNITS_PER_WORD)));
1464
1465 return vector;
1466 }
1467
1468 void
1469 rx_expand_epilogue (bool is_sibcall)
1470 {
1471 unsigned int low;
1472 unsigned int high;
1473 unsigned int frame_size;
1474 unsigned int stack_size;
1475 unsigned int register_mask;
1476 unsigned int regs_size;
1477 unsigned int reg;
1478 unsigned HOST_WIDE_INT total_size;
1479
1480 /* FIXME: We do not support indirect sibcalls at the moment becaause we
1481 cannot guarantee that the register holding the function address is a
1482 call-used register. If it is a call-saved register then the stack
1483 pop instructions generated in the epilogue will corrupt the address
1484 before it is used.
1485
1486 Creating a new call-used-only register class works but then the
1487 reload pass gets stuck because it cannot always find a call-used
1488 register for spilling sibcalls.
1489
1490 The other possible solution is for this pass to scan forward for the
1491 sibcall instruction (if it has been generated) and work out if it
1492 is an indirect sibcall using a call-saved register. If it is then
1493 the address can copied into a call-used register in this epilogue
1494 code and the sibcall instruction modified to use that register. */
1495
1496 if (is_naked_func (NULL_TREE))
1497 {
1498 gcc_assert (! is_sibcall);
1499
1500 /* Naked functions use their own, programmer provided epilogues.
1501 But, in order to keep gcc happy we have to generate some kind of
1502 epilogue RTL. */
1503 emit_jump_insn (gen_naked_return ());
1504 return;
1505 }
1506
1507 rx_get_stack_layout (& low, & high, & register_mask,
1508 & frame_size, & stack_size);
1509
1510 total_size = frame_size + stack_size;
1511 regs_size = ((high - low) + 1) * UNITS_PER_WORD;
1512
1513 /* See if we are unable to use the special stack frame deconstruct and
1514 return instructions. In most cases we can use them, but the exceptions
1515 are:
1516
1517 - Sibling calling functions deconstruct the frame but do not return to
1518 their caller. Instead they branch to their sibling and allow their
1519 return instruction to return to this function's parent.
1520
1521 - Fast and normal interrupt handling functions have to use special
1522 return instructions.
1523
1524 - Functions where we have pushed a fragmented set of registers into the
1525 call-save area must have the same set of registers popped. */
1526 if (is_sibcall
1527 || is_fast_interrupt_func (NULL_TREE)
1528 || is_interrupt_func (NULL_TREE)
1529 || register_mask)
1530 {
1531 /* Cannot use the special instructions - deconstruct by hand. */
1532 if (total_size)
1533 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1534 GEN_INT (total_size)));
1535
1536 if (MUST_SAVE_ACC_REGISTER)
1537 {
1538 unsigned int acc_low, acc_high;
1539
1540 /* Reverse the saving of the accumulator register onto the stack.
1541 Note we must adjust the saved "low" accumulator value as it
1542 is really the middle 32-bits of the accumulator. */
1543 if (register_mask)
1544 {
1545 acc_low = acc_high = 0;
1546 for (reg = 1; reg < FIRST_PSEUDO_REGISTER; reg ++)
1547 if (register_mask & (1 << reg))
1548 {
1549 if (acc_low == 0)
1550 acc_low = reg;
1551 else
1552 {
1553 acc_high = reg;
1554 break;
1555 }
1556 }
1557 emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_high)));
1558 emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_low)));
1559 }
1560 else
1561 {
1562 acc_low = low;
1563 acc_high = low + 1;
1564 emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD),
1565 gen_rx_popm_vector (acc_low, acc_high)));
1566 }
1567
1568 emit_insn (gen_ashlsi3 (gen_rtx_REG (SImode, acc_low),
1569 gen_rtx_REG (SImode, acc_low),
1570 GEN_INT (16)));
1571 emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low)));
1572 emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high)));
1573 }
1574
1575 if (register_mask)
1576 {
1577 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg ++)
1578 if (register_mask & (1 << reg))
1579 emit_insn (gen_stack_pop (gen_rtx_REG (SImode, reg)));
1580 }
1581 else if (low)
1582 {
1583 if (high == low)
1584 emit_insn (gen_stack_pop (gen_rtx_REG (SImode, low)));
1585 else
1586 emit_insn (gen_stack_popm (GEN_INT (regs_size),
1587 gen_rx_popm_vector (low, high)));
1588 }
1589
1590 if (is_fast_interrupt_func (NULL_TREE))
1591 {
1592 gcc_assert (! is_sibcall);
1593 emit_jump_insn (gen_fast_interrupt_return ());
1594 }
1595 else if (is_interrupt_func (NULL_TREE))
1596 {
1597 gcc_assert (! is_sibcall);
1598 emit_jump_insn (gen_exception_return ());
1599 }
1600 else if (! is_sibcall)
1601 emit_jump_insn (gen_simple_return ());
1602
1603 return;
1604 }
1605
1606 /* If we allocated space on the stack, free it now. */
1607 if (total_size)
1608 {
1609 unsigned HOST_WIDE_INT rtsd_size;
1610
1611 /* See if we can use the RTSD instruction. */
1612 rtsd_size = total_size + regs_size;
1613 if (rtsd_size < 1024 && (rtsd_size % 4) == 0)
1614 {
1615 if (low)
1616 emit_jump_insn (gen_pop_and_return
1617 (GEN_INT (rtsd_size),
1618 gen_rx_rtsd_vector (rtsd_size, low, high)));
1619 else
1620 emit_jump_insn (gen_deallocate_and_return (GEN_INT (total_size)));
1621
1622 return;
1623 }
1624
1625 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1626 GEN_INT (total_size)));
1627 }
1628
1629 if (low)
1630 emit_jump_insn (gen_pop_and_return (GEN_INT (regs_size),
1631 gen_rx_rtsd_vector (regs_size,
1632 low, high)));
1633 else
1634 emit_jump_insn (gen_simple_return ());
1635 }
1636
1637
1638 /* Compute the offset (in words) between FROM (arg pointer
1639 or frame pointer) and TO (frame pointer or stack pointer).
1640 See ASCII art comment at the start of rx_expand_prologue
1641 for more information. */
1642
1643 int
1644 rx_initial_elimination_offset (int from, int to)
1645 {
1646 unsigned int low;
1647 unsigned int high;
1648 unsigned int frame_size;
1649 unsigned int stack_size;
1650 unsigned int mask;
1651
1652 rx_get_stack_layout (& low, & high, & mask, & frame_size, & stack_size);
1653
1654 if (from == ARG_POINTER_REGNUM)
1655 {
1656 /* Extend the computed size of the stack frame to
1657 include the registers pushed in the prologue. */
1658 if (low)
1659 frame_size += ((high - low) + 1) * UNITS_PER_WORD;
1660 else
1661 frame_size += bit_count (mask) * UNITS_PER_WORD;
1662
1663 /* Remember to include the return address. */
1664 frame_size += 1 * UNITS_PER_WORD;
1665
1666 if (to == FRAME_POINTER_REGNUM)
1667 return frame_size;
1668
1669 gcc_assert (to == STACK_POINTER_REGNUM);
1670 return frame_size + stack_size;
1671 }
1672
1673 gcc_assert (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM);
1674 return stack_size;
1675 }
1676
1677 /* Update the status of the condition
1678 codes (cc0) based on the given INSN. */
1679
1680 void
1681 rx_notice_update_cc (rtx body, rtx insn)
1682 {
1683 switch (get_attr_cc (insn))
1684 {
1685 case CC_NONE:
1686 /* Insn does not affect cc0 at all. */
1687 break;
1688 case CC_CLOBBER:
1689 /* Insn doesn't leave cc0 in a usable state. */
1690 CC_STATUS_INIT;
1691 break;
1692 case CC_SET_ZSOC:
1693 /* The insn sets all the condition code bits. */
1694 CC_STATUS_INIT;
1695 cc_status.value1 = SET_DEST (body);
1696 break;
1697 case CC_SET_ZSO:
1698 /* Insn sets the Z,S and O flags, but not the C flag. */
1699 CC_STATUS_INIT;
1700 cc_status.flags |= CC_NO_CARRY;
1701 /* Do not set the value1 field in this case. The final_scan_insn()
1702 function naively believes that if cc_status.value1 is set then
1703 it can eliminate *any* comparison against that value, even if
1704 the type of comparison cannot be satisfied by the range of flag
1705 bits being set here. See gcc.c-torture/execute/20041210-1.c
1706 for an example of this in action. */
1707 break;
1708 case CC_SET_ZSC:
1709 /* Insn sets the Z,S and C flags, but not the O flag. */
1710 CC_STATUS_INIT;
1711 cc_status.flags |= CC_NO_OVERFLOW;
1712 /* See comment above regarding cc_status.value1. */
1713 break;
1714 case CC_SET_ZS:
1715 /* Insn sets the Z and S flags, but not the O or C flags. */
1716 CC_STATUS_INIT;
1717 cc_status.flags |= (CC_NO_CARRY | CC_NO_OVERFLOW);
1718 /* See comment above regarding cc_status.value1. */
1719 break;
1720 default:
1721 gcc_unreachable ();
1722 }
1723 }
1724
1725 /* Decide if a variable should go into one of the small data sections. */
1726
1727 static bool
1728 rx_in_small_data (const_tree decl)
1729 {
1730 int size;
1731 const_tree section;
1732
1733 if (rx_small_data_limit == 0)
1734 return false;
1735
1736 if (TREE_CODE (decl) != VAR_DECL)
1737 return false;
1738
1739 /* We do not put read-only variables into a small data area because
1740 they would be placed with the other read-only sections, far away
1741 from the read-write data sections, and we only have one small
1742 data area pointer.
1743 Similarly commons are placed in the .bss section which might be
1744 far away (and out of alignment with respect to) the .data section. */
1745 if (TREE_READONLY (decl) || DECL_COMMON (decl))
1746 return false;
1747
1748 section = DECL_SECTION_NAME (decl);
1749 if (section)
1750 {
1751 const char * const name = TREE_STRING_POINTER (section);
1752
1753 return (strcmp (name, "D_2") == 0) || (strcmp (name, "B_2") == 0);
1754 }
1755
1756 size = int_size_in_bytes (TREE_TYPE (decl));
1757
1758 return (size > 0) && (size <= rx_small_data_limit);
1759 }
1760
1761 /* Return a section for X.
1762 The only special thing we do here is to honor small data. */
1763
1764 static section *
1765 rx_select_rtx_section (enum machine_mode mode,
1766 rtx x,
1767 unsigned HOST_WIDE_INT align)
1768 {
1769 if (rx_small_data_limit > 0
1770 && GET_MODE_SIZE (mode) <= rx_small_data_limit
1771 && align <= (unsigned HOST_WIDE_INT) rx_small_data_limit * BITS_PER_UNIT)
1772 return sdata_section;
1773
1774 return default_elf_select_rtx_section (mode, x, align);
1775 }
1776
1777 static section *
1778 rx_select_section (tree decl,
1779 int reloc,
1780 unsigned HOST_WIDE_INT align)
1781 {
1782 if (rx_small_data_limit > 0)
1783 {
1784 switch (categorize_decl_for_section (decl, reloc))
1785 {
1786 case SECCAT_SDATA: return sdata_section;
1787 case SECCAT_SBSS: return sbss_section;
1788 case SECCAT_SRODATA:
1789 /* Fall through. We do not put small, read only
1790 data into the C_2 section because we are not
1791 using the C_2 section. We do not use the C_2
1792 section because it is located with the other
1793 read-only data sections, far away from the read-write
1794 data sections and we only have one small data
1795 pointer (r13). */
1796 default:
1797 break;
1798 }
1799 }
1800
1801 /* If we are supporting the Renesas assembler
1802 we cannot use mergeable sections. */
1803 if (TARGET_AS100_SYNTAX)
1804 switch (categorize_decl_for_section (decl, reloc))
1805 {
1806 case SECCAT_RODATA_MERGE_CONST:
1807 case SECCAT_RODATA_MERGE_STR_INIT:
1808 case SECCAT_RODATA_MERGE_STR:
1809 return readonly_data_section;
1810
1811 default:
1812 break;
1813 }
1814
1815 return default_elf_select_section (decl, reloc, align);
1816 }
1817 \f
1818 enum rx_builtin
1819 {
1820 RX_BUILTIN_BRK,
1821 RX_BUILTIN_CLRPSW,
1822 RX_BUILTIN_INT,
1823 RX_BUILTIN_MACHI,
1824 RX_BUILTIN_MACLO,
1825 RX_BUILTIN_MULHI,
1826 RX_BUILTIN_MULLO,
1827 RX_BUILTIN_MVFACHI,
1828 RX_BUILTIN_MVFACMI,
1829 RX_BUILTIN_MVFC,
1830 RX_BUILTIN_MVTACHI,
1831 RX_BUILTIN_MVTACLO,
1832 RX_BUILTIN_MVTC,
1833 RX_BUILTIN_MVTIPL,
1834 RX_BUILTIN_RACW,
1835 RX_BUILTIN_REVW,
1836 RX_BUILTIN_RMPA,
1837 RX_BUILTIN_ROUND,
1838 RX_BUILTIN_SAT,
1839 RX_BUILTIN_SETPSW,
1840 RX_BUILTIN_WAIT,
1841 RX_BUILTIN_max
1842 };
1843
1844 static void
1845 rx_init_builtins (void)
1846 {
1847 #define ADD_RX_BUILTIN1(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE) \
1848 add_builtin_function ("__builtin_rx_" LC_NAME, \
1849 build_function_type_list (RET_TYPE##_type_node, \
1850 ARG_TYPE##_type_node, \
1851 NULL_TREE), \
1852 RX_BUILTIN_##UC_NAME, \
1853 BUILT_IN_MD, NULL, NULL_TREE)
1854
1855 #define ADD_RX_BUILTIN2(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE1, ARG_TYPE2) \
1856 add_builtin_function ("__builtin_rx_" LC_NAME, \
1857 build_function_type_list (RET_TYPE##_type_node, \
1858 ARG_TYPE1##_type_node,\
1859 ARG_TYPE2##_type_node,\
1860 NULL_TREE), \
1861 RX_BUILTIN_##UC_NAME, \
1862 BUILT_IN_MD, NULL, NULL_TREE)
1863
1864 #define ADD_RX_BUILTIN3(UC_NAME,LC_NAME,RET_TYPE,ARG_TYPE1,ARG_TYPE2,ARG_TYPE3) \
1865 add_builtin_function ("__builtin_rx_" LC_NAME, \
1866 build_function_type_list (RET_TYPE##_type_node, \
1867 ARG_TYPE1##_type_node,\
1868 ARG_TYPE2##_type_node,\
1869 ARG_TYPE3##_type_node,\
1870 NULL_TREE), \
1871 RX_BUILTIN_##UC_NAME, \
1872 BUILT_IN_MD, NULL, NULL_TREE)
1873
1874 ADD_RX_BUILTIN1 (BRK, "brk", void, void);
1875 ADD_RX_BUILTIN1 (CLRPSW, "clrpsw", void, integer);
1876 ADD_RX_BUILTIN1 (SETPSW, "setpsw", void, integer);
1877 ADD_RX_BUILTIN1 (INT, "int", void, integer);
1878 ADD_RX_BUILTIN2 (MACHI, "machi", void, intSI, intSI);
1879 ADD_RX_BUILTIN2 (MACLO, "maclo", void, intSI, intSI);
1880 ADD_RX_BUILTIN2 (MULHI, "mulhi", void, intSI, intSI);
1881 ADD_RX_BUILTIN2 (MULLO, "mullo", void, intSI, intSI);
1882 ADD_RX_BUILTIN1 (MVFACHI, "mvfachi", intSI, void);
1883 ADD_RX_BUILTIN1 (MVFACMI, "mvfacmi", intSI, void);
1884 ADD_RX_BUILTIN1 (MVTACHI, "mvtachi", void, intSI);
1885 ADD_RX_BUILTIN1 (MVTACLO, "mvtaclo", void, intSI);
1886 ADD_RX_BUILTIN1 (RMPA, "rmpa", void, void);
1887 ADD_RX_BUILTIN1 (MVFC, "mvfc", intSI, integer);
1888 ADD_RX_BUILTIN2 (MVTC, "mvtc", void, integer, integer);
1889 ADD_RX_BUILTIN1 (MVTIPL, "mvtipl", void, integer);
1890 ADD_RX_BUILTIN1 (RACW, "racw", void, integer);
1891 ADD_RX_BUILTIN1 (ROUND, "round", intSI, float);
1892 ADD_RX_BUILTIN1 (REVW, "revw", intSI, intSI);
1893 ADD_RX_BUILTIN1 (SAT, "sat", intSI, intSI);
1894 ADD_RX_BUILTIN1 (WAIT, "wait", void, void);
1895 }
1896
1897 static rtx
1898 rx_expand_void_builtin_1_arg (rtx arg, rtx (* gen_func)(rtx), bool reg)
1899 {
1900 if (reg && ! REG_P (arg))
1901 arg = force_reg (SImode, arg);
1902
1903 emit_insn (gen_func (arg));
1904
1905 return NULL_RTX;
1906 }
1907
1908 static rtx
1909 rx_expand_builtin_mvtc (tree exp)
1910 {
1911 rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
1912 rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
1913
1914 if (! CONST_INT_P (arg1))
1915 return NULL_RTX;
1916
1917 if (! REG_P (arg2))
1918 arg2 = force_reg (SImode, arg2);
1919
1920 emit_insn (gen_mvtc (arg1, arg2));
1921
1922 return NULL_RTX;
1923 }
1924
1925 static rtx
1926 rx_expand_builtin_mvfc (tree t_arg, rtx target)
1927 {
1928 rtx arg = expand_normal (t_arg);
1929
1930 if (! CONST_INT_P (arg))
1931 return NULL_RTX;
1932
1933 if (target == NULL_RTX)
1934 return NULL_RTX;
1935
1936 if (! REG_P (target))
1937 target = force_reg (SImode, target);
1938
1939 emit_insn (gen_mvfc (target, arg));
1940
1941 return target;
1942 }
1943
1944 static rtx
1945 rx_expand_builtin_mvtipl (rtx arg)
1946 {
1947 /* The RX610 does not support the MVTIPL instruction. */
1948 if (rx_cpu_type == RX610)
1949 return NULL_RTX;
1950
1951 if (! CONST_INT_P (arg) || ! IN_RANGE (arg, 0, (1 << 4) - 1))
1952 return NULL_RTX;
1953
1954 emit_insn (gen_mvtipl (arg));
1955
1956 return NULL_RTX;
1957 }
1958
1959 static rtx
1960 rx_expand_builtin_mac (tree exp, rtx (* gen_func)(rtx, rtx))
1961 {
1962 rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
1963 rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
1964
1965 if (! REG_P (arg1))
1966 arg1 = force_reg (SImode, arg1);
1967
1968 if (! REG_P (arg2))
1969 arg2 = force_reg (SImode, arg2);
1970
1971 emit_insn (gen_func (arg1, arg2));
1972
1973 return NULL_RTX;
1974 }
1975
1976 static rtx
1977 rx_expand_int_builtin_1_arg (rtx arg,
1978 rtx target,
1979 rtx (* gen_func)(rtx, rtx),
1980 bool mem_ok)
1981 {
1982 if (! REG_P (arg))
1983 if (!mem_ok || ! MEM_P (arg))
1984 arg = force_reg (SImode, arg);
1985
1986 if (target == NULL_RTX || ! REG_P (target))
1987 target = gen_reg_rtx (SImode);
1988
1989 emit_insn (gen_func (target, arg));
1990
1991 return target;
1992 }
1993
1994 static rtx
1995 rx_expand_int_builtin_0_arg (rtx target, rtx (* gen_func)(rtx))
1996 {
1997 if (target == NULL_RTX || ! REG_P (target))
1998 target = gen_reg_rtx (SImode);
1999
2000 emit_insn (gen_func (target));
2001
2002 return target;
2003 }
2004
2005 static rtx
2006 rx_expand_builtin_round (rtx arg, rtx target)
2007 {
2008 if ((! REG_P (arg) && ! MEM_P (arg))
2009 || GET_MODE (arg) != SFmode)
2010 arg = force_reg (SFmode, arg);
2011
2012 if (target == NULL_RTX || ! REG_P (target))
2013 target = gen_reg_rtx (SImode);
2014
2015 emit_insn (gen_lrintsf2 (target, arg));
2016
2017 return target;
2018 }
2019
2020 static rtx
2021 rx_expand_builtin (tree exp,
2022 rtx target,
2023 rtx subtarget ATTRIBUTE_UNUSED,
2024 enum machine_mode mode ATTRIBUTE_UNUSED,
2025 int ignore ATTRIBUTE_UNUSED)
2026 {
2027 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2028 tree arg = call_expr_nargs (exp) >= 1 ? CALL_EXPR_ARG (exp, 0) : NULL_TREE;
2029 rtx op = arg ? expand_normal (arg) : NULL_RTX;
2030 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2031
2032 switch (fcode)
2033 {
2034 case RX_BUILTIN_BRK: emit_insn (gen_brk ()); return NULL_RTX;
2035 case RX_BUILTIN_CLRPSW: return rx_expand_void_builtin_1_arg
2036 (op, gen_clrpsw, false);
2037 case RX_BUILTIN_SETPSW: return rx_expand_void_builtin_1_arg
2038 (op, gen_setpsw, false);
2039 case RX_BUILTIN_INT: return rx_expand_void_builtin_1_arg
2040 (op, gen_int, false);
2041 case RX_BUILTIN_MACHI: return rx_expand_builtin_mac (exp, gen_machi);
2042 case RX_BUILTIN_MACLO: return rx_expand_builtin_mac (exp, gen_maclo);
2043 case RX_BUILTIN_MULHI: return rx_expand_builtin_mac (exp, gen_mulhi);
2044 case RX_BUILTIN_MULLO: return rx_expand_builtin_mac (exp, gen_mullo);
2045 case RX_BUILTIN_MVFACHI: return rx_expand_int_builtin_0_arg
2046 (target, gen_mvfachi);
2047 case RX_BUILTIN_MVFACMI: return rx_expand_int_builtin_0_arg
2048 (target, gen_mvfacmi);
2049 case RX_BUILTIN_MVTACHI: return rx_expand_void_builtin_1_arg
2050 (op, gen_mvtachi, true);
2051 case RX_BUILTIN_MVTACLO: return rx_expand_void_builtin_1_arg
2052 (op, gen_mvtaclo, true);
2053 case RX_BUILTIN_RMPA: emit_insn (gen_rmpa ()); return NULL_RTX;
2054 case RX_BUILTIN_MVFC: return rx_expand_builtin_mvfc (arg, target);
2055 case RX_BUILTIN_MVTC: return rx_expand_builtin_mvtc (exp);
2056 case RX_BUILTIN_MVTIPL: return rx_expand_builtin_mvtipl (op);
2057 case RX_BUILTIN_RACW: return rx_expand_void_builtin_1_arg
2058 (op, gen_racw, false);
2059 case RX_BUILTIN_ROUND: return rx_expand_builtin_round (op, target);
2060 case RX_BUILTIN_REVW: return rx_expand_int_builtin_1_arg
2061 (op, target, gen_revw, false);
2062 case RX_BUILTIN_SAT: return rx_expand_int_builtin_1_arg
2063 (op, target, gen_sat, false);
2064 case RX_BUILTIN_WAIT: emit_insn (gen_wait ()); return NULL_RTX;
2065
2066 default:
2067 internal_error ("bad builtin code");
2068 break;
2069 }
2070
2071 return NULL_RTX;
2072 }
2073 \f
2074 /* Place an element into a constructor or destructor section.
2075 Like default_ctor_section_asm_out_constructor in varasm.c
2076 except that it uses .init_array (or .fini_array) and it
2077 handles constructor priorities. */
2078
2079 static void
2080 rx_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
2081 {
2082 section * s;
2083
2084 if (priority != DEFAULT_INIT_PRIORITY)
2085 {
2086 char buf[18];
2087
2088 sprintf (buf, "%s.%.5u",
2089 is_ctor ? ".init_array" : ".fini_array",
2090 priority);
2091 s = get_section (buf, SECTION_WRITE, NULL_TREE);
2092 }
2093 else if (is_ctor)
2094 s = ctors_section;
2095 else
2096 s = dtors_section;
2097
2098 switch_to_section (s);
2099 assemble_align (POINTER_SIZE);
2100 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
2101 }
2102
2103 static void
2104 rx_elf_asm_constructor (rtx symbol, int priority)
2105 {
2106 rx_elf_asm_cdtor (symbol, priority, /* is_ctor= */true);
2107 }
2108
2109 static void
2110 rx_elf_asm_destructor (rtx symbol, int priority)
2111 {
2112 rx_elf_asm_cdtor (symbol, priority, /* is_ctor= */false);
2113 }
2114 \f
2115 /* Check "fast_interrupt", "interrupt" and "naked" attributes. */
2116
2117 static tree
2118 rx_handle_func_attribute (tree * node,
2119 tree name,
2120 tree args,
2121 int flags ATTRIBUTE_UNUSED,
2122 bool * no_add_attrs)
2123 {
2124 gcc_assert (DECL_P (* node));
2125 gcc_assert (args == NULL_TREE);
2126
2127 if (TREE_CODE (* node) != FUNCTION_DECL)
2128 {
2129 warning (OPT_Wattributes, "%qE attribute only applies to functions",
2130 name);
2131 * no_add_attrs = true;
2132 }
2133
2134 /* FIXME: We ought to check for conflicting attributes. */
2135
2136 /* FIXME: We ought to check that the interrupt and exception
2137 handler attributes have been applied to void functions. */
2138 return NULL_TREE;
2139 }
2140
2141 /* Table of RX specific attributes. */
2142 const struct attribute_spec rx_attribute_table[] =
2143 {
2144 /* Name, min_len, max_len, decl_req, type_req, fn_type_req, handler. */
2145 { "fast_interrupt", 0, 0, true, false, false, rx_handle_func_attribute },
2146 { "interrupt", 0, 0, true, false, false, rx_handle_func_attribute },
2147 { "naked", 0, 0, true, false, false, rx_handle_func_attribute },
2148 { NULL, 0, 0, false, false, false, NULL }
2149 };
2150
2151 /* Extra processing for target specific command line options. */
2152
2153 static bool
2154 rx_handle_option (size_t code, const char * arg ATTRIBUTE_UNUSED, int value)
2155 {
2156 switch (code)
2157 {
2158 case OPT_mint_register_:
2159 switch (value)
2160 {
2161 case 4:
2162 fixed_regs[10] = call_used_regs [10] = 1;
2163 /* Fall through. */
2164 case 3:
2165 fixed_regs[11] = call_used_regs [11] = 1;
2166 /* Fall through. */
2167 case 2:
2168 fixed_regs[12] = call_used_regs [12] = 1;
2169 /* Fall through. */
2170 case 1:
2171 fixed_regs[13] = call_used_regs [13] = 1;
2172 /* Fall through. */
2173 case 0:
2174 return true;
2175 default:
2176 return false;
2177 }
2178 break;
2179
2180 case OPT_mmax_constant_size_:
2181 /* Make sure that the -mmax-constant_size option is in range. */
2182 return value >= 0 && value <= 4;
2183
2184 case OPT_mcpu_:
2185 case OPT_patch_:
2186 if (strcasecmp (arg, "RX610") == 0)
2187 rx_cpu_type = RX610;
2188 else if (strcasecmp (arg, "RX200") == 0)
2189 {
2190 target_flags |= MASK_NO_USE_FPU;
2191 rx_cpu_type = RX200;
2192 }
2193 else if (strcasecmp (arg, "RX600") != 0)
2194 warning (0, "unrecognized argument '%s' to -mcpu= option", arg);
2195 break;
2196
2197 case OPT_fpu:
2198 if (rx_cpu_type == RX200)
2199 error ("The RX200 cpu does not have FPU hardware");
2200 break;
2201
2202 default:
2203 break;
2204 }
2205
2206 return true;
2207 }
2208
2209 void
2210 rx_set_optimization_options (void)
2211 {
2212 static bool first_time = TRUE;
2213 static bool saved_allow_rx_fpu = TRUE;
2214
2215 if (first_time)
2216 {
2217 /* If this is the first time through and the user has not disabled
2218 the use of RX FPU hardware then enable unsafe math optimizations,
2219 since the FPU instructions themselves are unsafe. */
2220 if (TARGET_USE_FPU)
2221 set_fast_math_flags (true);
2222
2223 /* FIXME: For some unknown reason LTO compression is not working,
2224 at least on my local system. So set the default compression
2225 level to none, for now. */
2226 if (flag_lto_compression_level == -1)
2227 flag_lto_compression_level = 0;
2228
2229 saved_allow_rx_fpu = ALLOW_RX_FPU_INSNS;
2230 first_time = FALSE;
2231 }
2232 else
2233 {
2234 /* Alert the user if they are changing the optimization options
2235 to use IEEE compliant floating point arithmetic with RX FPU insns. */
2236 if (TARGET_USE_FPU
2237 && ! fast_math_flags_set_p ())
2238 warning (0, "RX FPU instructions are not IEEE compliant");
2239
2240 if (saved_allow_rx_fpu != ALLOW_RX_FPU_INSNS)
2241 error ("Changing the FPU insns/math optimizations pairing is not supported");
2242 }
2243 }
2244
2245 \f
2246 static bool
2247 rx_allocate_stack_slots_for_args (void)
2248 {
2249 /* Naked functions should not allocate stack slots for arguments. */
2250 return ! is_naked_func (NULL_TREE);
2251 }
2252
2253 static bool
2254 rx_func_attr_inlinable (const_tree decl)
2255 {
2256 return ! is_fast_interrupt_func (decl)
2257 && ! is_interrupt_func (decl)
2258 && ! is_naked_func (decl);
2259 }
2260
2261 /* Return nonzero if it is ok to make a tail-call to DECL,
2262 a function_decl or NULL if this is an indirect call, using EXP */
2263
2264 static bool
2265 rx_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2266 {
2267 /* Do not allow indirect tailcalls. The
2268 sibcall patterns do not support them. */
2269 if (decl == NULL)
2270 return false;
2271
2272 /* Never tailcall from inside interrupt handlers or naked functions. */
2273 if (is_fast_interrupt_func (NULL_TREE)
2274 || is_interrupt_func (NULL_TREE)
2275 || is_naked_func (NULL_TREE))
2276 return false;
2277
2278 return true;
2279 }
2280
2281 static void
2282 rx_file_start (void)
2283 {
2284 if (! TARGET_AS100_SYNTAX)
2285 default_file_start ();
2286 }
2287
2288 static bool
2289 rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED)
2290 {
2291 return TRUE;
2292 }
2293
2294 /* Try to generate code for the "isnv" pattern which inserts bits
2295 into a word.
2296 operands[0] => Location to be altered.
2297 operands[1] => Number of bits to change.
2298 operands[2] => Starting bit.
2299 operands[3] => Value to insert.
2300 Returns TRUE if successful, FALSE otherwise. */
2301
2302 bool
2303 rx_expand_insv (rtx * operands)
2304 {
2305 if (INTVAL (operands[1]) != 1
2306 || ! CONST_INT_P (operands[3]))
2307 return false;
2308
2309 if (MEM_P (operands[0])
2310 && INTVAL (operands[2]) > 7)
2311 return false;
2312
2313 switch (INTVAL (operands[3]))
2314 {
2315 case 0:
2316 if (MEM_P (operands[0]))
2317 emit_insn (gen_bitclr_in_memory (operands[0], operands[0],
2318 operands[2]));
2319 else
2320 emit_insn (gen_bitclr (operands[0], operands[0], operands[2]));
2321 break;
2322 case 1:
2323 case -1:
2324 if (MEM_P (operands[0]))
2325 emit_insn (gen_bitset_in_memory (operands[0], operands[0],
2326 operands[2]));
2327 else
2328 emit_insn (gen_bitset (operands[0], operands[0], operands[2]));
2329 break;
2330 default:
2331 return false;
2332 }
2333 return true;
2334 }
2335 \f
2336 /* Returns true if X a legitimate constant for an immediate
2337 operand on the RX. X is already known to satisfy CONSTANT_P. */
2338
2339 bool
2340 rx_is_legitimate_constant (rtx x)
2341 {
2342 HOST_WIDE_INT val;
2343
2344 switch (GET_CODE (x))
2345 {
2346 case CONST:
2347 x = XEXP (x, 0);
2348
2349 if (GET_CODE (x) == PLUS)
2350 {
2351 if (! CONST_INT_P (XEXP (x, 1)))
2352 return false;
2353
2354 /* GCC would not pass us CONST_INT + CONST_INT so we
2355 know that we have {SYMBOL|LABEL} + CONST_INT. */
2356 x = XEXP (x, 0);
2357 gcc_assert (! CONST_INT_P (x));
2358 }
2359
2360 switch (GET_CODE (x))
2361 {
2362 case LABEL_REF:
2363 case SYMBOL_REF:
2364 return true;
2365
2366 /* One day we may have to handle UNSPEC constants here. */
2367 default:
2368 /* FIXME: Can this ever happen ? */
2369 abort ();
2370 return false;
2371 }
2372 break;
2373
2374 case LABEL_REF:
2375 case SYMBOL_REF:
2376 return true;
2377 case CONST_DOUBLE:
2378 return (rx_max_constant_size == 0 || rx_max_constant_size == 4);
2379 case CONST_VECTOR:
2380 return false;
2381 default:
2382 gcc_assert (CONST_INT_P (x));
2383 break;
2384 }
2385
2386 if (rx_max_constant_size == 0 || rx_max_constant_size == 4)
2387 /* If there is no constraint on the size of constants
2388 used as operands, then any value is legitimate. */
2389 return true;
2390
2391 val = INTVAL (x);
2392
2393 /* rx_max_constant_size specifies the maximum number
2394 of bytes that can be used to hold a signed value. */
2395 return IN_RANGE (val, (-1 << (rx_max_constant_size * 8)),
2396 ( 1 << (rx_max_constant_size * 8)));
2397 }
2398
2399 static int
2400 rx_address_cost (rtx addr, bool speed)
2401 {
2402 rtx a, b;
2403
2404 if (GET_CODE (addr) != PLUS)
2405 return COSTS_N_INSNS (1);
2406
2407 a = XEXP (addr, 0);
2408 b = XEXP (addr, 1);
2409
2410 if (REG_P (a) && REG_P (b))
2411 /* Try to discourage REG+REG addressing as it keeps two registers live. */
2412 return COSTS_N_INSNS (4);
2413
2414 if (speed)
2415 /* [REG+OFF] is just as fast as [REG]. */
2416 return COSTS_N_INSNS (1);
2417
2418 if (CONST_INT_P (b)
2419 && ((INTVAL (b) > 128) || INTVAL (b) < -127))
2420 /* Try to discourage REG + <large OFF> when optimizing for size. */
2421 return COSTS_N_INSNS (2);
2422
2423 return COSTS_N_INSNS (1);
2424 }
2425
2426 static bool
2427 rx_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
2428 {
2429 /* We can always eliminate to the frame pointer.
2430 We can eliminate to the stack pointer unless a frame
2431 pointer is needed. */
2432
2433 return to == FRAME_POINTER_REGNUM
2434 || ( to == STACK_POINTER_REGNUM && ! frame_pointer_needed);
2435 }
2436 \f
2437
2438 static void
2439 rx_trampoline_template (FILE * file)
2440 {
2441 /* Output assembler code for a block containing the constant
2442 part of a trampoline, leaving space for the variable parts.
2443
2444 On the RX, (where r8 is the static chain regnum) the trampoline
2445 looks like:
2446
2447 mov #<static chain value>, r8
2448 mov #<function's address>, r9
2449 jmp r9
2450
2451 In big-endian-data-mode however instructions are read into the CPU
2452 4 bytes at a time. These bytes are then swapped around before being
2453 passed to the decoder. So...we must partition our trampoline into
2454 4 byte packets and swap these packets around so that the instruction
2455 reader will reverse the process. But, in order to avoid splitting
2456 the 32-bit constants across these packet boundaries, (making inserting
2457 them into the constructed trampoline very difficult) we have to pad the
2458 instruction sequence with NOP insns. ie:
2459
2460 nop
2461 nop
2462 mov.l #<...>, r8
2463 nop
2464 nop
2465 mov.l #<...>, r9
2466 jmp r9
2467 nop
2468 nop */
2469
2470 if (! TARGET_BIG_ENDIAN_DATA)
2471 {
2472 asm_fprintf (file, "\tmov.L\t#0deadbeefH, r%d\n", STATIC_CHAIN_REGNUM);
2473 asm_fprintf (file, "\tmov.L\t#0deadbeefH, r%d\n", TRAMPOLINE_TEMP_REGNUM);
2474 asm_fprintf (file, "\tjmp\tr%d\n", TRAMPOLINE_TEMP_REGNUM);
2475 }
2476 else
2477 {
2478 char r8 = '0' + STATIC_CHAIN_REGNUM;
2479 char r9 = '0' + TRAMPOLINE_TEMP_REGNUM;
2480
2481 if (TARGET_AS100_SYNTAX)
2482 {
2483 asm_fprintf (file, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r8);
2484 asm_fprintf (file, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
2485 asm_fprintf (file, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r9);
2486 asm_fprintf (file, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
2487 asm_fprintf (file, "\t.BYTE 003H, 003H, 00%cH, 07fH\n", r9);
2488 }
2489 else
2490 {
2491 asm_fprintf (file, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r8);
2492 asm_fprintf (file, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
2493 asm_fprintf (file, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r9);
2494 asm_fprintf (file, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
2495 asm_fprintf (file, "\t.byte 0x03, 0x03, 0x0%c, 0x7f\n", r9);
2496 }
2497 }
2498 }
2499
2500 static void
2501 rx_trampoline_init (rtx tramp, tree fndecl, rtx chain)
2502 {
2503 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2504
2505 emit_block_move (tramp, assemble_trampoline_template (),
2506 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2507
2508 if (TARGET_BIG_ENDIAN_DATA)
2509 {
2510 emit_move_insn (adjust_address (tramp, SImode, 4), chain);
2511 emit_move_insn (adjust_address (tramp, SImode, 12), fnaddr);
2512 }
2513 else
2514 {
2515 emit_move_insn (adjust_address (tramp, SImode, 2), chain);
2516 emit_move_insn (adjust_address (tramp, SImode, 6 + 2), fnaddr);
2517 }
2518 }
2519 \f
2520 #undef TARGET_FUNCTION_VALUE
2521 #define TARGET_FUNCTION_VALUE rx_function_value
2522
2523 #undef TARGET_RETURN_IN_MSB
2524 #define TARGET_RETURN_IN_MSB rx_return_in_msb
2525
2526 #undef TARGET_IN_SMALL_DATA_P
2527 #define TARGET_IN_SMALL_DATA_P rx_in_small_data
2528
2529 #undef TARGET_RETURN_IN_MEMORY
2530 #define TARGET_RETURN_IN_MEMORY rx_return_in_memory
2531
2532 #undef TARGET_HAVE_SRODATA_SECTION
2533 #define TARGET_HAVE_SRODATA_SECTION true
2534
2535 #undef TARGET_ASM_SELECT_RTX_SECTION
2536 #define TARGET_ASM_SELECT_RTX_SECTION rx_select_rtx_section
2537
2538 #undef TARGET_ASM_SELECT_SECTION
2539 #define TARGET_ASM_SELECT_SECTION rx_select_section
2540
2541 #undef TARGET_INIT_BUILTINS
2542 #define TARGET_INIT_BUILTINS rx_init_builtins
2543
2544 #undef TARGET_EXPAND_BUILTIN
2545 #define TARGET_EXPAND_BUILTIN rx_expand_builtin
2546
2547 #undef TARGET_ASM_CONSTRUCTOR
2548 #define TARGET_ASM_CONSTRUCTOR rx_elf_asm_constructor
2549
2550 #undef TARGET_ASM_DESTRUCTOR
2551 #define TARGET_ASM_DESTRUCTOR rx_elf_asm_destructor
2552
2553 #undef TARGET_STRUCT_VALUE_RTX
2554 #define TARGET_STRUCT_VALUE_RTX rx_struct_value_rtx
2555
2556 #undef TARGET_ATTRIBUTE_TABLE
2557 #define TARGET_ATTRIBUTE_TABLE rx_attribute_table
2558
2559 #undef TARGET_ASM_FILE_START
2560 #define TARGET_ASM_FILE_START rx_file_start
2561
2562 #undef TARGET_MS_BITFIELD_LAYOUT_P
2563 #define TARGET_MS_BITFIELD_LAYOUT_P rx_is_ms_bitfield_layout
2564
2565 #undef TARGET_LEGITIMATE_ADDRESS_P
2566 #define TARGET_LEGITIMATE_ADDRESS_P rx_is_legitimate_address
2567
2568 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
2569 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS rx_allocate_stack_slots_for_args
2570
2571 #undef TARGET_ASM_FUNCTION_PROLOGUE
2572 #define TARGET_ASM_FUNCTION_PROLOGUE rx_output_function_prologue
2573
2574 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
2575 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P rx_func_attr_inlinable
2576
2577 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
2578 #define TARGET_FUNCTION_OK_FOR_SIBCALL rx_function_ok_for_sibcall
2579
2580 #undef TARGET_SET_CURRENT_FUNCTION
2581 #define TARGET_SET_CURRENT_FUNCTION rx_set_current_function
2582
2583 #undef TARGET_HANDLE_OPTION
2584 #define TARGET_HANDLE_OPTION rx_handle_option
2585
2586 #undef TARGET_ASM_INTEGER
2587 #define TARGET_ASM_INTEGER rx_assemble_integer
2588
2589 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
2590 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
2591
2592 #undef TARGET_MAX_ANCHOR_OFFSET
2593 #define TARGET_MAX_ANCHOR_OFFSET 32
2594
2595 #undef TARGET_ADDRESS_COST
2596 #define TARGET_ADDRESS_COST rx_address_cost
2597
2598 #undef TARGET_CAN_ELIMINATE
2599 #define TARGET_CAN_ELIMINATE rx_can_eliminate
2600
2601 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
2602 #define TARGET_ASM_TRAMPOLINE_TEMPLATE rx_trampoline_template
2603
2604 #undef TARGET_TRAMPOLINE_INIT
2605 #define TARGET_TRAMPOLINE_INIT rx_trampoline_init
2606
2607 #undef TARGET_PRINT_OPERAND
2608 #define TARGET_PRINT_OPERAND rx_print_operand
2609
2610 #undef TARGET_PRINT_OPERAND_ADDRESS
2611 #define TARGET_PRINT_OPERAND_ADDRESS rx_print_operand_address
2612
2613 struct gcc_target targetm = TARGET_INITIALIZER;
2614
2615 /* #include "gt-rx.h" */