gcc/config/rx/rx.opt

   1 ; Command line options for the Renesas RX port of GCC.
   2 ; Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
   3 ; Contributed by Red Hat.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 ; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 ; for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20 ;---------------------------------------------------
  21
  22 HeaderInclude
  23 config/rx/rx-opts.h
  24
  25 ; The default is -fpu -m32bit-doubles.
  26
  27 m64bit-doubles
  28 Target RejectNegative Mask(64BIT_DOUBLES) Report
  29 Store doubles in 64 bits.
  30
  31 m32bit-doubles
  32 Target RejectNegative InverseMask(64BIT_DOUBLES) Report
  33 Stores doubles in 32 bits.  This is the default.
  34
  35 nofpu
  36 Target RejectNegative Alias(mnofpu)
  37 Disable the use of RX FPU instructions.
  38
  39 mnofpu
  40 Target RejectNegative Mask(NO_USE_FPU) Report Undocumented
  41
  42 fpu
  43 Target RejectNegative InverseMask(NO_USE_FPU) Report
  44 Enable the use of RX FPU instructions.  This is the default.
  45
  46 ;---------------------------------------------------
  47
  48 mcpu=
  49 Target RejectNegative Joined Var(rx_cpu_type) Report ToLower Enum(rx_cpu_types) Init(RX600)
  50 Specify the target RX cpu type.
  51
  52 Enum
  53 Name(rx_cpu_types) Type(enum rx_cpu_types)
  54
  55 EnumValue
  56 Enum(rx_cpu_types) String(rx610) Value(RX610)
  57
  58 EnumValue
  59 Enum(rx_cpu_types) String(rx200) Value(RX200)
  60
  61 EnumValue
  62 Enum(rx_cpu_types) String(rx600) Value(RX600)
  63
  64 ;---------------------------------------------------
  65
  66 mbig-endian-data
  67 Target RejectNegative Mask(BIG_ENDIAN_DATA) Report
  68 Data is stored in big-endian format.
  69
  70 mlittle-endian-data
  71 Target RejectNegative InverseMask(BIG_ENDIAN_DATA) Report
  72 Data is stored in little-endian format.  (Default).
  73
  74 ;---------------------------------------------------
  75
  76 msmall-data-limit=
  77 Target RejectNegative Joined UInteger Var(rx_small_data_limit) Init(0)
  78 Maximum size of global and static variables which can be placed into the small data area.
  79
  80 ;---------------------------------------------------
  81
  82 msim
  83 Target
  84 Use the simulator runtime.
  85
  86 ;---------------------------------------------------
  87
  88 mas100-syntax
  89 Target Mask(AS100_SYNTAX) Report
  90 Generate assembler output that is compatible with the Renesas AS100 assembler.  This may restrict some of the compiler's capabilities.  The default is to generate GAS compatable syntax.
  91
  92 ;---------------------------------------------------
  93
  94 mrelax
  95 Target
  96 Enable linker relaxation.
  97
  98 ;---------------------------------------------------
  99
 100 mmax-constant-size=
 101 Target RejectNegative Joined UInteger Var(rx_max_constant_size) Init(0)
 102 Maximum size in bytes of constant values allowed as operands.
 103
 104 ;---------------------------------------------------
 105
 106 mint-register=
 107 Target RejectNegative Joined UInteger Var(rx_deferred_options) Defer
 108 Specifies the number of registers to reserve for interrupt handlers.
 109
 110 ;---------------------------------------------------
 111
 112 msave-acc-in-interrupts
 113 Target Mask(SAVE_ACC_REGISTER)
 114 Specifies whether interrupt functions should save and restore the accumulator register.
 115
 116 ;---------------------------------------------------
 117
 118 mpid
 119 Target Mask(PID)
 120 Enables Position-Independent-Data (PID) mode.