1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
31 #include "fold-const.h"
32 #include "print-tree.h"
33 #include "stringpool.h"
34 #include "stor-layout.h"
39 #include "hard-reg-set.h"
40 #include "insn-config.h"
41 #include "conditions.h"
43 #include "insn-attr.h"
55 #include "diagnostic-core.h"
57 #include "dominance.h"
63 #include "cfgcleanup.h"
64 #include "basic-block.h"
67 #include "langhooks.h"
68 #include "insn-codes.h"
70 #include "tree-ssa-alias.h"
71 #include "internal-fn.h"
72 #include "gimple-fold.h"
74 #include "gimple-expr.h"
81 #include "tree-pass.h"
86 #include "plugin-api.h"
90 #include "target-def.h"
92 /* Define the specific costs for a given cpu. */
94 struct processor_costs
97 const int m
; /* cost of an M instruction. */
98 const int mghi
; /* cost of an MGHI instruction. */
99 const int mh
; /* cost of an MH instruction. */
100 const int mhi
; /* cost of an MHI instruction. */
101 const int ml
; /* cost of an ML instruction. */
102 const int mr
; /* cost of an MR instruction. */
103 const int ms
; /* cost of an MS instruction. */
104 const int msg
; /* cost of an MSG instruction. */
105 const int msgf
; /* cost of an MSGF instruction. */
106 const int msgfr
; /* cost of an MSGFR instruction. */
107 const int msgr
; /* cost of an MSGR instruction. */
108 const int msr
; /* cost of an MSR instruction. */
109 const int mult_df
; /* cost of multiplication in DFmode. */
112 const int sqxbr
; /* cost of square root in TFmode. */
113 const int sqdbr
; /* cost of square root in DFmode. */
114 const int sqebr
; /* cost of square root in SFmode. */
115 /* multiply and add */
116 const int madbr
; /* cost of multiply and add in DFmode. */
117 const int maebr
; /* cost of multiply and add in SFmode. */
129 const struct processor_costs
*s390_cost
;
132 struct processor_costs z900_cost
=
134 COSTS_N_INSNS (5), /* M */
135 COSTS_N_INSNS (10), /* MGHI */
136 COSTS_N_INSNS (5), /* MH */
137 COSTS_N_INSNS (4), /* MHI */
138 COSTS_N_INSNS (5), /* ML */
139 COSTS_N_INSNS (5), /* MR */
140 COSTS_N_INSNS (4), /* MS */
141 COSTS_N_INSNS (15), /* MSG */
142 COSTS_N_INSNS (7), /* MSGF */
143 COSTS_N_INSNS (7), /* MSGFR */
144 COSTS_N_INSNS (10), /* MSGR */
145 COSTS_N_INSNS (4), /* MSR */
146 COSTS_N_INSNS (7), /* multiplication in DFmode */
147 COSTS_N_INSNS (13), /* MXBR */
148 COSTS_N_INSNS (136), /* SQXBR */
149 COSTS_N_INSNS (44), /* SQDBR */
150 COSTS_N_INSNS (35), /* SQEBR */
151 COSTS_N_INSNS (18), /* MADBR */
152 COSTS_N_INSNS (13), /* MAEBR */
153 COSTS_N_INSNS (134), /* DXBR */
154 COSTS_N_INSNS (30), /* DDBR */
155 COSTS_N_INSNS (27), /* DEBR */
156 COSTS_N_INSNS (220), /* DLGR */
157 COSTS_N_INSNS (34), /* DLR */
158 COSTS_N_INSNS (34), /* DR */
159 COSTS_N_INSNS (32), /* DSGFR */
160 COSTS_N_INSNS (32), /* DSGR */
164 struct processor_costs z990_cost
=
166 COSTS_N_INSNS (4), /* M */
167 COSTS_N_INSNS (2), /* MGHI */
168 COSTS_N_INSNS (2), /* MH */
169 COSTS_N_INSNS (2), /* MHI */
170 COSTS_N_INSNS (4), /* ML */
171 COSTS_N_INSNS (4), /* MR */
172 COSTS_N_INSNS (5), /* MS */
173 COSTS_N_INSNS (6), /* MSG */
174 COSTS_N_INSNS (4), /* MSGF */
175 COSTS_N_INSNS (4), /* MSGFR */
176 COSTS_N_INSNS (4), /* MSGR */
177 COSTS_N_INSNS (4), /* MSR */
178 COSTS_N_INSNS (1), /* multiplication in DFmode */
179 COSTS_N_INSNS (28), /* MXBR */
180 COSTS_N_INSNS (130), /* SQXBR */
181 COSTS_N_INSNS (66), /* SQDBR */
182 COSTS_N_INSNS (38), /* SQEBR */
183 COSTS_N_INSNS (1), /* MADBR */
184 COSTS_N_INSNS (1), /* MAEBR */
185 COSTS_N_INSNS (60), /* DXBR */
186 COSTS_N_INSNS (40), /* DDBR */
187 COSTS_N_INSNS (26), /* DEBR */
188 COSTS_N_INSNS (176), /* DLGR */
189 COSTS_N_INSNS (31), /* DLR */
190 COSTS_N_INSNS (31), /* DR */
191 COSTS_N_INSNS (31), /* DSGFR */
192 COSTS_N_INSNS (31), /* DSGR */
196 struct processor_costs z9_109_cost
=
198 COSTS_N_INSNS (4), /* M */
199 COSTS_N_INSNS (2), /* MGHI */
200 COSTS_N_INSNS (2), /* MH */
201 COSTS_N_INSNS (2), /* MHI */
202 COSTS_N_INSNS (4), /* ML */
203 COSTS_N_INSNS (4), /* MR */
204 COSTS_N_INSNS (5), /* MS */
205 COSTS_N_INSNS (6), /* MSG */
206 COSTS_N_INSNS (4), /* MSGF */
207 COSTS_N_INSNS (4), /* MSGFR */
208 COSTS_N_INSNS (4), /* MSGR */
209 COSTS_N_INSNS (4), /* MSR */
210 COSTS_N_INSNS (1), /* multiplication in DFmode */
211 COSTS_N_INSNS (28), /* MXBR */
212 COSTS_N_INSNS (130), /* SQXBR */
213 COSTS_N_INSNS (66), /* SQDBR */
214 COSTS_N_INSNS (38), /* SQEBR */
215 COSTS_N_INSNS (1), /* MADBR */
216 COSTS_N_INSNS (1), /* MAEBR */
217 COSTS_N_INSNS (60), /* DXBR */
218 COSTS_N_INSNS (40), /* DDBR */
219 COSTS_N_INSNS (26), /* DEBR */
220 COSTS_N_INSNS (30), /* DLGR */
221 COSTS_N_INSNS (23), /* DLR */
222 COSTS_N_INSNS (23), /* DR */
223 COSTS_N_INSNS (24), /* DSGFR */
224 COSTS_N_INSNS (24), /* DSGR */
228 struct processor_costs z10_cost
=
230 COSTS_N_INSNS (10), /* M */
231 COSTS_N_INSNS (10), /* MGHI */
232 COSTS_N_INSNS (10), /* MH */
233 COSTS_N_INSNS (10), /* MHI */
234 COSTS_N_INSNS (10), /* ML */
235 COSTS_N_INSNS (10), /* MR */
236 COSTS_N_INSNS (10), /* MS */
237 COSTS_N_INSNS (10), /* MSG */
238 COSTS_N_INSNS (10), /* MSGF */
239 COSTS_N_INSNS (10), /* MSGFR */
240 COSTS_N_INSNS (10), /* MSGR */
241 COSTS_N_INSNS (10), /* MSR */
242 COSTS_N_INSNS (1) , /* multiplication in DFmode */
243 COSTS_N_INSNS (50), /* MXBR */
244 COSTS_N_INSNS (120), /* SQXBR */
245 COSTS_N_INSNS (52), /* SQDBR */
246 COSTS_N_INSNS (38), /* SQEBR */
247 COSTS_N_INSNS (1), /* MADBR */
248 COSTS_N_INSNS (1), /* MAEBR */
249 COSTS_N_INSNS (111), /* DXBR */
250 COSTS_N_INSNS (39), /* DDBR */
251 COSTS_N_INSNS (32), /* DEBR */
252 COSTS_N_INSNS (160), /* DLGR */
253 COSTS_N_INSNS (71), /* DLR */
254 COSTS_N_INSNS (71), /* DR */
255 COSTS_N_INSNS (71), /* DSGFR */
256 COSTS_N_INSNS (71), /* DSGR */
260 struct processor_costs z196_cost
=
262 COSTS_N_INSNS (7), /* M */
263 COSTS_N_INSNS (5), /* MGHI */
264 COSTS_N_INSNS (5), /* MH */
265 COSTS_N_INSNS (5), /* MHI */
266 COSTS_N_INSNS (7), /* ML */
267 COSTS_N_INSNS (7), /* MR */
268 COSTS_N_INSNS (6), /* MS */
269 COSTS_N_INSNS (8), /* MSG */
270 COSTS_N_INSNS (6), /* MSGF */
271 COSTS_N_INSNS (6), /* MSGFR */
272 COSTS_N_INSNS (8), /* MSGR */
273 COSTS_N_INSNS (6), /* MSR */
274 COSTS_N_INSNS (1) , /* multiplication in DFmode */
275 COSTS_N_INSNS (40), /* MXBR B+40 */
276 COSTS_N_INSNS (100), /* SQXBR B+100 */
277 COSTS_N_INSNS (42), /* SQDBR B+42 */
278 COSTS_N_INSNS (28), /* SQEBR B+28 */
279 COSTS_N_INSNS (1), /* MADBR B */
280 COSTS_N_INSNS (1), /* MAEBR B */
281 COSTS_N_INSNS (101), /* DXBR B+101 */
282 COSTS_N_INSNS (29), /* DDBR */
283 COSTS_N_INSNS (22), /* DEBR */
284 COSTS_N_INSNS (160), /* DLGR cracked */
285 COSTS_N_INSNS (160), /* DLR cracked */
286 COSTS_N_INSNS (160), /* DR expanded */
287 COSTS_N_INSNS (160), /* DSGFR cracked */
288 COSTS_N_INSNS (160), /* DSGR cracked */
292 struct processor_costs zEC12_cost
=
294 COSTS_N_INSNS (7), /* M */
295 COSTS_N_INSNS (5), /* MGHI */
296 COSTS_N_INSNS (5), /* MH */
297 COSTS_N_INSNS (5), /* MHI */
298 COSTS_N_INSNS (7), /* ML */
299 COSTS_N_INSNS (7), /* MR */
300 COSTS_N_INSNS (6), /* MS */
301 COSTS_N_INSNS (8), /* MSG */
302 COSTS_N_INSNS (6), /* MSGF */
303 COSTS_N_INSNS (6), /* MSGFR */
304 COSTS_N_INSNS (8), /* MSGR */
305 COSTS_N_INSNS (6), /* MSR */
306 COSTS_N_INSNS (1) , /* multiplication in DFmode */
307 COSTS_N_INSNS (40), /* MXBR B+40 */
308 COSTS_N_INSNS (100), /* SQXBR B+100 */
309 COSTS_N_INSNS (42), /* SQDBR B+42 */
310 COSTS_N_INSNS (28), /* SQEBR B+28 */
311 COSTS_N_INSNS (1), /* MADBR B */
312 COSTS_N_INSNS (1), /* MAEBR B */
313 COSTS_N_INSNS (131), /* DXBR B+131 */
314 COSTS_N_INSNS (29), /* DDBR */
315 COSTS_N_INSNS (22), /* DEBR */
316 COSTS_N_INSNS (160), /* DLGR cracked */
317 COSTS_N_INSNS (160), /* DLR cracked */
318 COSTS_N_INSNS (160), /* DR expanded */
319 COSTS_N_INSNS (160), /* DSGFR cracked */
320 COSTS_N_INSNS (160), /* DSGR cracked */
323 extern int reload_completed
;
325 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
326 static rtx_insn
*last_scheduled_insn
;
328 /* Structure used to hold the components of a S/390 memory
329 address. A legitimate address on S/390 is of the general
331 base + index + displacement
332 where any of the components is optional.
334 base and index are registers of the class ADDR_REGS,
335 displacement is an unsigned 12-bit immediate constant. */
346 /* The following structure is embedded in the machine
347 specific part of struct function. */
349 struct GTY (()) s390_frame_layout
351 /* Offset within stack frame. */
352 HOST_WIDE_INT gprs_offset
;
353 HOST_WIDE_INT f0_offset
;
354 HOST_WIDE_INT f4_offset
;
355 HOST_WIDE_INT f8_offset
;
356 HOST_WIDE_INT backchain_offset
;
358 /* Number of first and last gpr where slots in the register
359 save area are reserved for. */
360 int first_save_gpr_slot
;
361 int last_save_gpr_slot
;
363 /* Location (FP register number) where GPRs (r0-r15) should
365 0 - does not need to be saved at all
367 signed char gpr_save_slots
[16];
369 /* Number of first and last gpr to be saved, restored. */
371 int first_restore_gpr
;
373 int last_restore_gpr
;
375 /* Bits standing for floating point registers. Set, if the
376 respective register has to be saved. Starting with reg 16 (f0)
377 at the rightmost bit.
378 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
379 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
380 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
381 unsigned int fpr_bitmap
;
383 /* Number of floating point registers f8-f15 which must be saved. */
386 /* Set if return address needs to be saved.
387 This flag is set by s390_return_addr_rtx if it could not use
388 the initial value of r14 and therefore depends on r14 saved
390 bool save_return_addr_p
;
392 /* Size of stack frame. */
393 HOST_WIDE_INT frame_size
;
396 /* Define the structure for the machine field in struct function. */
398 struct GTY(()) machine_function
400 struct s390_frame_layout frame_layout
;
402 /* Literal pool base register. */
405 /* True if we may need to perform branch splitting. */
406 bool split_branches_pending_p
;
408 bool has_landing_pad_p
;
410 /* True if the current function may contain a tbegin clobbering
415 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
417 #define cfun_frame_layout (cfun->machine->frame_layout)
418 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
419 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
420 ? cfun_frame_layout.fpr_bitmap & 0x0f \
421 : cfun_frame_layout.fpr_bitmap & 0x03))
422 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
423 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
424 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
425 (1 << (REGNO - FPR0_REGNUM)))
426 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
427 (1 << (REGNO - FPR0_REGNUM))))
428 #define cfun_gpr_save_slot(REGNO) \
429 cfun->machine->frame_layout.gpr_save_slots[REGNO]
431 /* Number of GPRs and FPRs used for argument passing. */
432 #define GP_ARG_NUM_REG 5
433 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
434 #define VEC_ARG_NUM_REG 8
436 /* A couple of shortcuts. */
437 #define CONST_OK_FOR_J(x) \
438 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
439 #define CONST_OK_FOR_K(x) \
440 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
441 #define CONST_OK_FOR_Os(x) \
442 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
443 #define CONST_OK_FOR_Op(x) \
444 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
445 #define CONST_OK_FOR_On(x) \
446 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
448 #define REGNO_PAIR_OK(REGNO, MODE) \
449 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
451 /* That's the read ahead of the dynamic branch prediction unit in
452 bytes on a z10 (or higher) CPU. */
453 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
456 /* Indicate which ABI has been used for passing vector args.
457 0 - no vector type arguments have been passed where the ABI is relevant
458 1 - the old ABI has been used
459 2 - a vector type argument has been passed either in a vector register
460 or on the stack by value */
461 static int s390_vector_abi
= 0;
463 /* Set the vector ABI marker if TYPE is subject to the vector ABI
464 switch. The vector ABI affects only vector data types. There are
465 two aspects of the vector ABI relevant here:
467 1. vectors >= 16 bytes have an alignment of 8 bytes with the new
468 ABI and natural alignment with the old.
470 2. vector <= 16 bytes are passed in VRs or by value on the stack
471 with the new ABI but by reference on the stack with the old.
473 If ARG_P is true TYPE is used for a function argument or return
474 value. The ABI marker then is set for all vector data types. If
475 ARG_P is false only type 1 vectors are being checked. */
478 s390_check_type_for_vector_abi (const_tree type
, bool arg_p
, bool in_struct_p
)
480 static hash_set
<const_tree
> visited_types_hash
;
485 if (type
== NULL_TREE
|| TREE_CODE (type
) == ERROR_MARK
)
488 if (visited_types_hash
.contains (type
))
491 visited_types_hash
.add (type
);
493 if (VECTOR_TYPE_P (type
))
495 int type_size
= int_size_in_bytes (type
);
497 /* Outside arguments only the alignment is changing and this
498 only happens for vector types >= 16 bytes. */
499 if (!arg_p
&& type_size
< 16)
502 /* In arguments vector types > 16 are passed as before (GCC
503 never enforced the bigger alignment for arguments which was
504 required by the old vector ABI). However, it might still be
505 ABI relevant due to the changed alignment if it is a struct
507 if (arg_p
&& type_size
> 16 && !in_struct_p
)
510 s390_vector_abi
= TARGET_VX_ABI
? 2 : 1;
512 else if (POINTER_TYPE_P (type
) || TREE_CODE (type
) == ARRAY_TYPE
)
514 /* ARRAY_TYPE: Since with neither of the ABIs we have more than
515 natural alignment there will never be ABI dependent padding
516 in an array type. That's why we do not set in_struct_p to
518 s390_check_type_for_vector_abi (TREE_TYPE (type
), arg_p
, in_struct_p
);
520 else if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
524 /* Check the return type. */
525 s390_check_type_for_vector_abi (TREE_TYPE (type
), true, false);
527 for (arg_chain
= TYPE_ARG_TYPES (type
);
529 arg_chain
= TREE_CHAIN (arg_chain
))
530 s390_check_type_for_vector_abi (TREE_VALUE (arg_chain
), true, false);
532 else if (RECORD_OR_UNION_TYPE_P (type
))
536 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
538 if (TREE_CODE (field
) != FIELD_DECL
)
541 s390_check_type_for_vector_abi (TREE_TYPE (field
), arg_p
, true);
547 /* System z builtins. */
549 #include "s390-builtins.h"
551 const unsigned int bflags_builtin
[S390_BUILTIN_MAX
+ 1] =
556 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, ...) BFLAGS,
558 #define OB_DEF_VAR(...)
559 #include "s390-builtins.def"
563 const unsigned int opflags_builtin
[S390_BUILTIN_MAX
+ 1] =
568 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, ...) OPFLAGS,
570 #define OB_DEF_VAR(...)
571 #include "s390-builtins.def"
575 const unsigned int bflags_overloaded_builtin
[S390_OVERLOADED_BUILTIN_MAX
+ 1] =
581 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, ...) BFLAGS,
582 #define OB_DEF_VAR(...)
583 #include "s390-builtins.def"
588 opflags_overloaded_builtin_var
[S390_OVERLOADED_BUILTIN_VAR_MAX
+ 1] =
595 #define OB_DEF_VAR(NAME, PATTERN, FLAGS, FNTYPE) FLAGS,
596 #include "s390-builtins.def"
600 tree s390_builtin_types
[BT_MAX
];
601 tree s390_builtin_fn_types
[BT_FN_MAX
];
602 tree s390_builtin_decls
[S390_BUILTIN_MAX
+
603 S390_OVERLOADED_BUILTIN_MAX
+
604 S390_OVERLOADED_BUILTIN_VAR_MAX
];
606 static enum insn_code
const code_for_builtin
[S390_BUILTIN_MAX
+ 1] = {
610 #define B_DEF(NAME, PATTERN, ...) CODE_FOR_##PATTERN,
612 #define OB_DEF_VAR(...)
614 #include "s390-builtins.def"
619 s390_init_builtins (void)
621 /* These definitions are being used in s390-builtins.def. */
622 tree returns_twice_attr
= tree_cons (get_identifier ("returns_twice"),
624 tree noreturn_attr
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
625 tree c_uint64_type_node
;
626 unsigned int bflags_mask
= (BFLAGS_MASK_INIT
);
628 bflags_mask
|= (TARGET_VX
) ? B_VX
: 0;
629 bflags_mask
|= (TARGET_HTM
) ? B_HTM
: 0;
631 /* The uint64_type_node from tree.c is not compatible to the C99
632 uint64_t data type. What we want is c_uint64_type_node from
633 c-common.c. But since backend code is not supposed to interface
634 with the frontend we recreate it here. */
636 c_uint64_type_node
= long_unsigned_type_node
;
638 c_uint64_type_node
= long_long_unsigned_type_node
;
641 #define DEF_TYPE(INDEX, BFLAGS, NODE, CONST_P) \
642 if ((BFLAGS) == 0 || ((BFLAGS) & bflags_mask)) \
643 s390_builtin_types[INDEX] = (!CONST_P) ? \
644 (NODE) : build_type_variant ((NODE), 1, 0);
646 #undef DEF_POINTER_TYPE
647 #define DEF_POINTER_TYPE(INDEX, BFLAGS, INDEX_BASE) \
648 if ((BFLAGS) == 0 || ((BFLAGS) & bflags_mask)) \
649 s390_builtin_types[INDEX] = \
650 build_pointer_type (s390_builtin_types[INDEX_BASE]);
652 #undef DEF_DISTINCT_TYPE
653 #define DEF_DISTINCT_TYPE(INDEX, BFLAGS, INDEX_BASE) \
654 if ((BFLAGS) == 0 || ((BFLAGS) & bflags_mask)) \
655 s390_builtin_types[INDEX] = \
656 build_distinct_type_copy (s390_builtin_types[INDEX_BASE]);
658 #undef DEF_VECTOR_TYPE
659 #define DEF_VECTOR_TYPE(INDEX, BFLAGS, INDEX_BASE, ELEMENTS) \
660 if ((BFLAGS) == 0 || ((BFLAGS) & bflags_mask)) \
661 s390_builtin_types[INDEX] = \
662 build_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
664 #undef DEF_OPAQUE_VECTOR_TYPE
665 #define DEF_OPAQUE_VECTOR_TYPE(INDEX, BFLAGS, INDEX_BASE, ELEMENTS) \
666 if ((BFLAGS) == 0 || ((BFLAGS) & bflags_mask)) \
667 s390_builtin_types[INDEX] = \
668 build_opaque_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
671 #define DEF_FN_TYPE(INDEX, BFLAGS, args...) \
672 if ((BFLAGS) == 0 || ((BFLAGS) & bflags_mask)) \
673 s390_builtin_fn_types[INDEX] = \
674 build_function_type_list (args, NULL_TREE);
676 #define DEF_OV_TYPE(...)
677 #include "s390-builtin-types.def"
680 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, FNTYPE) \
681 if (((BFLAGS) & ~bflags_mask) == 0) \
682 s390_builtin_decls[S390_BUILTIN_##NAME] = \
683 add_builtin_function ("__builtin_" #NAME, \
684 s390_builtin_fn_types[FNTYPE], \
685 S390_BUILTIN_##NAME, \
690 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, FNTYPE) \
691 if (((BFLAGS) & ~bflags_mask) == 0) \
692 s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] = \
693 add_builtin_function ("__builtin_" #NAME, \
694 s390_builtin_fn_types[FNTYPE], \
695 S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX, \
700 #define OB_DEF_VAR(...)
701 #include "s390-builtins.def"
705 /* Return true if ARG is appropriate as argument number ARGNUM of
706 builtin DECL. The operand flags from s390-builtins.def have to
707 passed as OP_FLAGS. */
709 s390_const_operand_ok (tree arg
, int argnum
, int op_flags
, tree decl
)
711 if (O_UIMM_P (op_flags
))
713 int bitwidths
[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32 };
714 int bitwidth
= bitwidths
[op_flags
- O_U1
];
716 if (!tree_fits_uhwi_p (arg
)
717 || tree_to_uhwi (arg
) > ((unsigned HOST_WIDE_INT
)1 << bitwidth
) - 1)
719 error("constant argument %d for builtin %qF is out of range (0.."
720 HOST_WIDE_INT_PRINT_UNSIGNED
")",
722 ((unsigned HOST_WIDE_INT
)1 << bitwidth
) - 1);
727 if (O_SIMM_P (op_flags
))
729 int bitwidths
[] = { 2, 3, 4, 5, 8, 12, 16, 32 };
730 int bitwidth
= bitwidths
[op_flags
- O_S2
];
732 if (!tree_fits_shwi_p (arg
)
733 || tree_to_shwi (arg
) < -((HOST_WIDE_INT
)1 << (bitwidth
- 1))
734 || tree_to_shwi (arg
) > (((HOST_WIDE_INT
)1 << (bitwidth
- 1)) - 1))
736 error("constant argument %d for builtin %qF is out of range ("
737 HOST_WIDE_INT_PRINT_DEC
".."
738 HOST_WIDE_INT_PRINT_DEC
")",
740 -(HOST_WIDE_INT
)1 << (bitwidth
- 1),
741 ((HOST_WIDE_INT
)1 << (bitwidth
- 1)) - 1);
748 /* Expand an expression EXP that calls a built-in function,
749 with result going to TARGET if that's convenient
750 (and in mode MODE if that's convenient).
751 SUBTARGET may be used as the target for computing one of EXP's operands.
752 IGNORE is nonzero if the value is to be ignored. */
755 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
756 machine_mode mode ATTRIBUTE_UNUSED
,
757 int ignore ATTRIBUTE_UNUSED
)
761 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
762 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
763 enum insn_code icode
;
764 rtx op
[MAX_ARGS
], pat
;
768 call_expr_arg_iterator iter
;
769 unsigned int all_op_flags
= opflags_for_builtin (fcode
);
770 machine_mode last_vec_mode
= VOIDmode
;
772 if (TARGET_DEBUG_ARG
)
775 "s390_expand_builtin, code = %4d, %s\n",
776 (int)fcode
, IDENTIFIER_POINTER (DECL_NAME (fndecl
)));
779 if (fcode
>= S390_OVERLOADED_BUILTIN_VAR_OFFSET
780 && fcode
< S390_ALL_BUILTIN_MAX
)
784 else if (fcode
< S390_OVERLOADED_BUILTIN_OFFSET
)
786 icode
= code_for_builtin
[fcode
];
787 /* Set a flag in the machine specific cfun part in order to support
788 saving/restoring of FPRs. */
789 if (fcode
== S390_BUILTIN_tbegin
|| fcode
== S390_BUILTIN_tbegin_retry
)
790 cfun
->machine
->tbegin_p
= true;
792 else if (fcode
< S390_OVERLOADED_BUILTIN_VAR_OFFSET
)
794 error ("Unresolved overloaded builtin");
798 internal_error ("bad builtin fcode");
801 internal_error ("bad builtin icode");
803 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
807 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
809 || GET_MODE (target
) != tmode
810 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
811 target
= gen_reg_rtx (tmode
);
813 /* There are builtins (e.g. vec_promote) with no vector
814 arguments but an element selector. So we have to also look
815 at the vector return type when emitting the modulo
817 if (VECTOR_MODE_P (insn_data
[icode
].operand
[0].mode
))
818 last_vec_mode
= insn_data
[icode
].operand
[0].mode
;
822 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
824 const struct insn_operand_data
*insn_op
;
825 unsigned int op_flags
= all_op_flags
& ((1 << O_SHIFT
) - 1);
827 all_op_flags
= all_op_flags
>> O_SHIFT
;
829 if (arg
== error_mark_node
)
831 if (arity
>= MAX_ARGS
)
834 if (O_IMM_P (op_flags
)
835 && TREE_CODE (arg
) != INTEGER_CST
)
837 error ("constant value required for builtin %qF argument %d",
842 if (!s390_const_operand_ok (arg
, arity
+ 1, op_flags
, fndecl
))
845 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
846 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
848 /* Wrap the expanded RTX for pointer types into a MEM expr with
849 the proper mode. This allows us to use e.g. (match_operand
850 "memory_operand"..) in the insn patterns instead of (mem
851 (match_operand "address_operand)). This is helpful for
852 patterns not just accepting MEMs. */
853 if (POINTER_TYPE_P (TREE_TYPE (arg
))
854 && insn_op
->predicate
!= address_operand
)
855 op
[arity
] = gen_rtx_MEM (insn_op
->mode
, op
[arity
]);
857 /* Expand the module operation required on element selectors. */
858 if (op_flags
== O_ELEM
)
860 gcc_assert (last_vec_mode
!= VOIDmode
);
861 op
[arity
] = simplify_expand_binop (SImode
, code_to_optab (AND
),
863 GEN_INT (GET_MODE_NUNITS (last_vec_mode
) - 1),
864 NULL_RTX
, 1, OPTAB_DIRECT
);
867 /* Record the vector mode used for an element selector. This assumes:
868 1. There is no builtin with two different vector modes and an element selector
869 2. The element selector comes after the vector type it is referring to.
870 This currently the true for all the builtins but FIXME we
871 should better check for that. */
872 if (VECTOR_MODE_P (insn_op
->mode
))
873 last_vec_mode
= insn_op
->mode
;
875 if (insn_op
->predicate (op
[arity
], insn_op
->mode
))
881 if (MEM_P (op
[arity
])
882 && insn_op
->predicate
== memory_operand
883 && (GET_MODE (XEXP (op
[arity
], 0)) == Pmode
884 || GET_MODE (XEXP (op
[arity
], 0)) == VOIDmode
))
886 op
[arity
] = replace_equiv_address (op
[arity
],
887 copy_to_mode_reg (Pmode
,
888 XEXP (op
[arity
], 0)));
890 else if (GET_MODE (op
[arity
]) == insn_op
->mode
891 || GET_MODE (op
[arity
]) == VOIDmode
892 || (insn_op
->predicate
== address_operand
893 && GET_MODE (op
[arity
]) == Pmode
))
895 /* An address_operand usually has VOIDmode in the expander
896 so we cannot use this. */
897 machine_mode target_mode
=
898 (insn_op
->predicate
== address_operand
899 ? Pmode
: insn_op
->mode
);
900 op
[arity
] = copy_to_mode_reg (target_mode
, op
[arity
]);
903 if (!insn_op
->predicate (op
[arity
], insn_op
->mode
))
905 error ("Invalid argument %d for builtin %qF", arity
+ 1, fndecl
);
911 if (last_vec_mode
!= VOIDmode
&& !TARGET_VX
)
913 error ("Vector type builtin %qF is not supported without -mvx "
914 "(default with -march=z13).",
922 pat
= GEN_FCN (icode
) (target
);
926 pat
= GEN_FCN (icode
) (target
, op
[0]);
928 pat
= GEN_FCN (icode
) (op
[0]);
932 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
934 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
938 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2]);
940 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
944 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3]);
946 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
950 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4]);
952 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4]);
956 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
958 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
974 static const int s390_hotpatch_hw_max
= 1000000;
975 static int s390_hotpatch_hw_before_label
= 0;
976 static int s390_hotpatch_hw_after_label
= 0;
978 /* Check whether the hotpatch attribute is applied to a function and, if it has
979 an argument, the argument is valid. */
982 s390_handle_hotpatch_attribute (tree
*node
, tree name
, tree args
,
983 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
989 if (TREE_CODE (*node
) != FUNCTION_DECL
)
991 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
993 *no_add_attrs
= true;
995 if (args
!= NULL
&& TREE_CHAIN (args
) != NULL
)
997 expr
= TREE_VALUE (args
);
998 expr2
= TREE_VALUE (TREE_CHAIN (args
));
1000 if (args
== NULL
|| TREE_CHAIN (args
) == NULL
)
1002 else if (TREE_CODE (expr
) != INTEGER_CST
1003 || !INTEGRAL_TYPE_P (TREE_TYPE (expr
))
1004 || wi::gtu_p (expr
, s390_hotpatch_hw_max
))
1006 else if (TREE_CODE (expr2
) != INTEGER_CST
1007 || !INTEGRAL_TYPE_P (TREE_TYPE (expr2
))
1008 || wi::gtu_p (expr2
, s390_hotpatch_hw_max
))
1014 error ("requested %qE attribute is not a comma separated pair of"
1015 " non-negative integer constants or too large (max. %d)", name
,
1016 s390_hotpatch_hw_max
);
1017 *no_add_attrs
= true;
1023 /* Expand the s390_vector_bool type attribute. */
1026 s390_handle_vectorbool_attribute (tree
*node
, tree name ATTRIBUTE_UNUSED
,
1027 tree args ATTRIBUTE_UNUSED
,
1028 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1030 tree type
= *node
, result
= NULL_TREE
;
1033 while (POINTER_TYPE_P (type
)
1034 || TREE_CODE (type
) == FUNCTION_TYPE
1035 || TREE_CODE (type
) == METHOD_TYPE
1036 || TREE_CODE (type
) == ARRAY_TYPE
)
1037 type
= TREE_TYPE (type
);
1039 mode
= TYPE_MODE (type
);
1042 case DImode
: case V2DImode
: result
= s390_builtin_types
[BT_BV2DI
]; break;
1043 case SImode
: case V4SImode
: result
= s390_builtin_types
[BT_BV4SI
]; break;
1044 case HImode
: case V8HImode
: result
= s390_builtin_types
[BT_BV8HI
]; break;
1045 case QImode
: case V16QImode
: result
= s390_builtin_types
[BT_BV16QI
];
1049 *no_add_attrs
= true; /* No need to hang on to the attribute. */
1052 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
1057 static const struct attribute_spec s390_attribute_table
[] = {
1058 { "hotpatch", 2, 2, true, false, false, s390_handle_hotpatch_attribute
, false },
1059 { "s390_vector_bool", 0, 0, false, true, false, s390_handle_vectorbool_attribute
, true },
1061 { NULL
, 0, 0, false, false, false, NULL
, false }
1064 /* Return the alignment for LABEL. We default to the -falign-labels
1065 value except for the literal pool base label. */
1067 s390_label_align (rtx label
)
1069 rtx_insn
*prev_insn
= prev_active_insn (label
);
1072 if (prev_insn
== NULL_RTX
)
1075 set
= single_set (prev_insn
);
1077 if (set
== NULL_RTX
)
1080 src
= SET_SRC (set
);
1082 /* Don't align literal pool base labels. */
1083 if (GET_CODE (src
) == UNSPEC
1084 && XINT (src
, 1) == UNSPEC_MAIN_BASE
)
1088 return align_labels_log
;
1092 s390_libgcc_cmp_return_mode (void)
1094 return TARGET_64BIT
? DImode
: SImode
;
1098 s390_libgcc_shift_count_mode (void)
1100 return TARGET_64BIT
? DImode
: SImode
;
1104 s390_unwind_word_mode (void)
1106 return TARGET_64BIT
? DImode
: SImode
;
1109 /* Return true if the back end supports mode MODE. */
1111 s390_scalar_mode_supported_p (machine_mode mode
)
1113 /* In contrast to the default implementation reject TImode constants on 31bit
1114 TARGET_ZARCH for ABI compliance. */
1115 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
1118 if (DECIMAL_FLOAT_MODE_P (mode
))
1119 return default_decimal_float_supported_p ();
1121 return default_scalar_mode_supported_p (mode
);
1124 /* Return true if the back end supports vector mode MODE. */
1126 s390_vector_mode_supported_p (machine_mode mode
)
1130 if (!VECTOR_MODE_P (mode
)
1132 || GET_MODE_SIZE (mode
) > 16)
1135 inner
= GET_MODE_INNER (mode
);
1153 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
1156 s390_set_has_landing_pad_p (bool value
)
1158 cfun
->machine
->has_landing_pad_p
= value
;
1161 /* If two condition code modes are compatible, return a condition code
1162 mode which is compatible with both. Otherwise, return
1166 s390_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
1174 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
1175 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
1196 /* Return true if SET either doesn't set the CC register, or else
1197 the source and destination have matching CC modes and that
1198 CC mode is at least as constrained as REQ_MODE. */
1201 s390_match_ccmode_set (rtx set
, machine_mode req_mode
)
1203 machine_mode set_mode
;
1205 gcc_assert (GET_CODE (set
) == SET
);
1207 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
1210 set_mode
= GET_MODE (SET_DEST (set
));
1229 if (req_mode
!= set_mode
)
1234 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
1235 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
1241 if (req_mode
!= CCAmode
)
1249 return (GET_MODE (SET_SRC (set
)) == set_mode
);
1252 /* Return true if every SET in INSN that sets the CC register
1253 has source and destination with matching CC modes and that
1254 CC mode is at least as constrained as REQ_MODE.
1255 If REQ_MODE is VOIDmode, always return false. */
1258 s390_match_ccmode (rtx_insn
*insn
, machine_mode req_mode
)
1262 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
1263 if (req_mode
== VOIDmode
)
1266 if (GET_CODE (PATTERN (insn
)) == SET
)
1267 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
1269 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1270 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1272 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
1273 if (GET_CODE (set
) == SET
)
1274 if (!s390_match_ccmode_set (set
, req_mode
))
1281 /* If a test-under-mask instruction can be used to implement
1282 (compare (and ... OP1) OP2), return the CC mode required
1283 to do that. Otherwise, return VOIDmode.
1284 MIXED is true if the instruction can distinguish between
1285 CC1 and CC2 for mixed selected bits (TMxx), it is false
1286 if the instruction cannot (TM). */
1289 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
1293 /* ??? Fixme: should work on CONST_DOUBLE as well. */
1294 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
1297 /* Selected bits all zero: CC0.
1298 e.g.: int a; if ((a & (16 + 128)) == 0) */
1299 if (INTVAL (op2
) == 0)
1302 /* Selected bits all one: CC3.
1303 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
1304 if (INTVAL (op2
) == INTVAL (op1
))
1307 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
1309 if ((a & (16 + 128)) == 16) -> CCT1
1310 if ((a & (16 + 128)) == 128) -> CCT2 */
1313 bit1
= exact_log2 (INTVAL (op2
));
1314 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
1315 if (bit0
!= -1 && bit1
!= -1)
1316 return bit0
> bit1
? CCT1mode
: CCT2mode
;
1322 /* Given a comparison code OP (EQ, NE, etc.) and the operands
1323 OP0 and OP1 of a COMPARE, return the mode to be used for the
1327 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
1330 && register_operand (op0
, DFmode
)
1331 && register_operand (op1
, DFmode
))
1333 /* LT, LE, UNGT, UNGE require swapping OP0 and OP1. Either
1334 s390_emit_compare or s390_canonicalize_comparison will take
1356 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1357 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1359 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1360 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
1362 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1363 || GET_CODE (op1
) == NEG
)
1364 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1367 if (GET_CODE (op0
) == AND
)
1369 /* Check whether we can potentially do it via TM. */
1370 machine_mode ccmode
;
1371 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
1372 if (ccmode
!= VOIDmode
)
1374 /* Relax CCTmode to CCZmode to allow fall-back to AND
1375 if that turns out to be beneficial. */
1376 return ccmode
== CCTmode
? CCZmode
: ccmode
;
1380 if (register_operand (op0
, HImode
)
1381 && GET_CODE (op1
) == CONST_INT
1382 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
1384 if (register_operand (op0
, QImode
)
1385 && GET_CODE (op1
) == CONST_INT
1386 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
1395 /* The only overflow condition of NEG and ABS happens when
1396 -INT_MAX is used as parameter, which stays negative. So
1397 we have an overflow from a positive value to a negative.
1398 Using CCAP mode the resulting cc can be used for comparisons. */
1399 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1400 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1403 /* If constants are involved in an add instruction it is possible to use
1404 the resulting cc for comparisons with zero. Knowing the sign of the
1405 constant the overflow behavior gets predictable. e.g.:
1406 int a, b; if ((b = a + c) > 0)
1407 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
1408 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1409 && (CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1)))
1410 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0
, 1)), 'O', "Os")
1411 /* Avoid INT32_MIN on 32 bit. */
1412 && (!TARGET_ZARCH
|| INTVAL (XEXP (op0
, 1)) != -0x7fffffff - 1))))
1414 if (INTVAL (XEXP((op0
), 1)) < 0)
1428 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1429 && GET_CODE (op1
) != CONST_INT
)
1435 if (GET_CODE (op0
) == PLUS
1436 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1439 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1440 && GET_CODE (op1
) != CONST_INT
)
1446 if (GET_CODE (op0
) == MINUS
1447 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1450 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1451 && GET_CODE (op1
) != CONST_INT
)
1460 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
1461 that we can implement more efficiently. */
1464 s390_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
1465 bool op0_preserve_value
)
1467 if (op0_preserve_value
)
1470 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
1471 if ((*code
== EQ
|| *code
== NE
)
1472 && *op1
== const0_rtx
1473 && GET_CODE (*op0
) == ZERO_EXTRACT
1474 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1475 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
1476 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1478 rtx inner
= XEXP (*op0
, 0);
1479 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
1480 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
1481 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
1483 if (len
> 0 && len
< modesize
1484 && pos
>= 0 && pos
+ len
<= modesize
1485 && modesize
<= HOST_BITS_PER_WIDE_INT
)
1487 unsigned HOST_WIDE_INT block
;
1488 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
1489 block
<<= modesize
- pos
- len
;
1491 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
1492 gen_int_mode (block
, GET_MODE (inner
)));
1496 /* Narrow AND of memory against immediate to enable TM. */
1497 if ((*code
== EQ
|| *code
== NE
)
1498 && *op1
== const0_rtx
1499 && GET_CODE (*op0
) == AND
1500 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1501 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1503 rtx inner
= XEXP (*op0
, 0);
1504 rtx mask
= XEXP (*op0
, 1);
1506 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
1507 if (GET_CODE (inner
) == SUBREG
1508 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
1509 && (GET_MODE_SIZE (GET_MODE (inner
))
1510 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1512 & GET_MODE_MASK (GET_MODE (inner
))
1513 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
1515 inner
= SUBREG_REG (inner
);
1517 /* Do not change volatile MEMs. */
1518 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
1520 int part
= s390_single_part (XEXP (*op0
, 1),
1521 GET_MODE (inner
), QImode
, 0);
1524 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
1525 inner
= adjust_address_nv (inner
, QImode
, part
);
1526 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
1531 /* Narrow comparisons against 0xffff to HImode if possible. */
1532 if ((*code
== EQ
|| *code
== NE
)
1533 && GET_CODE (*op1
) == CONST_INT
1534 && INTVAL (*op1
) == 0xffff
1535 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
1536 && (nonzero_bits (*op0
, GET_MODE (*op0
))
1537 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
1539 *op0
= gen_lowpart (HImode
, *op0
);
1543 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
1544 if (GET_CODE (*op0
) == UNSPEC
1545 && XINT (*op0
, 1) == UNSPEC_STRCMPCC_TO_INT
1546 && XVECLEN (*op0
, 0) == 1
1547 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
1548 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1549 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1550 && *op1
== const0_rtx
)
1552 enum rtx_code new_code
= UNKNOWN
;
1555 case EQ
: new_code
= EQ
; break;
1556 case NE
: new_code
= NE
; break;
1557 case LT
: new_code
= GTU
; break;
1558 case GT
: new_code
= LTU
; break;
1559 case LE
: new_code
= GEU
; break;
1560 case GE
: new_code
= LEU
; break;
1564 if (new_code
!= UNKNOWN
)
1566 *op0
= XVECEXP (*op0
, 0, 0);
1571 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
1572 if (GET_CODE (*op0
) == UNSPEC
1573 && XINT (*op0
, 1) == UNSPEC_CC_TO_INT
1574 && XVECLEN (*op0
, 0) == 1
1575 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1576 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1577 && CONST_INT_P (*op1
))
1579 enum rtx_code new_code
= UNKNOWN
;
1580 switch (GET_MODE (XVECEXP (*op0
, 0, 0)))
1586 case EQ
: new_code
= EQ
; break;
1587 case NE
: new_code
= NE
; break;
1594 if (new_code
!= UNKNOWN
)
1596 /* For CCRAWmode put the required cc mask into the second
1598 if (GET_MODE (XVECEXP (*op0
, 0, 0)) == CCRAWmode
1599 && INTVAL (*op1
) >= 0 && INTVAL (*op1
) <= 3)
1600 *op1
= gen_rtx_CONST_INT (VOIDmode
, 1 << (3 - INTVAL (*op1
)));
1601 *op0
= XVECEXP (*op0
, 0, 0);
1606 /* Simplify cascaded EQ, NE with const0_rtx. */
1607 if ((*code
== NE
|| *code
== EQ
)
1608 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
1609 && GET_MODE (*op0
) == SImode
1610 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
1611 && REG_P (XEXP (*op0
, 0))
1612 && XEXP (*op0
, 1) == const0_rtx
1613 && *op1
== const0_rtx
)
1615 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
1616 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
1620 *op0
= XEXP (*op0
, 0);
1623 /* Prefer register over memory as first operand. */
1624 if (MEM_P (*op0
) && REG_P (*op1
))
1626 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
1627 *code
= (int)swap_condition ((enum rtx_code
)*code
);
1630 /* Using the scalar variants of vector instructions for 64 bit FP
1631 comparisons might require swapping the operands. */
1633 && register_operand (*op0
, DFmode
)
1634 && register_operand (*op1
, DFmode
)
1635 && (*code
== LT
|| *code
== LE
|| *code
== UNGT
|| *code
== UNGE
))
1641 case LT
: *code
= GT
; break;
1642 case LE
: *code
= GE
; break;
1643 case UNGT
: *code
= UNLE
; break;
1644 case UNGE
: *code
= UNLT
; break;
1647 tmp
= *op0
; *op0
= *op1
; *op1
= tmp
;
1651 /* Helper function for s390_emit_compare. If possible emit a 64 bit
1652 FP compare using the single element variant of vector instructions.
1653 Replace CODE with the comparison code to be used in the CC reg
1654 compare and return the condition code register RTX in CC. */
1657 s390_expand_vec_compare_scalar (enum rtx_code
*code
, rtx cmp1
, rtx cmp2
,
1660 machine_mode cmp_mode
;
1661 bool swap_p
= false;
1665 case EQ
: cmp_mode
= CCVEQmode
; break;
1666 case NE
: cmp_mode
= CCVEQmode
; break;
1667 case GT
: cmp_mode
= CCVFHmode
; break;
1668 case GE
: cmp_mode
= CCVFHEmode
; break;
1669 case UNLE
: cmp_mode
= CCVFHmode
; break;
1670 case UNLT
: cmp_mode
= CCVFHEmode
; break;
1671 case LT
: cmp_mode
= CCVFHmode
; *code
= GT
; swap_p
= true; break;
1672 case LE
: cmp_mode
= CCVFHEmode
; *code
= GE
; swap_p
= true; break;
1673 case UNGE
: cmp_mode
= CCVFHmode
; *code
= UNLE
; swap_p
= true; break;
1674 case UNGT
: cmp_mode
= CCVFHEmode
; *code
= UNLT
; swap_p
= true; break;
1675 default: return false;
1684 *cc
= gen_rtx_REG (cmp_mode
, CC_REGNUM
);
1685 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
1688 gen_rtx_COMPARE (cmp_mode
, cmp1
,
1690 gen_rtx_CLOBBER (VOIDmode
,
1691 gen_rtx_SCRATCH (V2DImode
)))));
1696 /* Emit a compare instruction suitable to implement the comparison
1697 OP0 CODE OP1. Return the correct condition RTL to be placed in
1698 the IF_THEN_ELSE of the conditional branch testing the result. */
1701 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
1703 machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
1707 && register_operand (op0
, DFmode
)
1708 && register_operand (op1
, DFmode
)
1709 && s390_expand_vec_compare_scalar (&code
, op0
, op1
, &cc
))
1711 /* Work has been done by s390_expand_vec_compare_scalar already. */
1713 else if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
1715 /* Do not output a redundant compare instruction if a
1716 compare_and_swap pattern already computed the result and the
1717 machine modes are compatible. */
1718 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
1724 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
1725 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
1728 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
1731 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1733 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1734 conditional branch testing the result. */
1737 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
,
1738 rtx cmp
, rtx new_rtx
)
1740 emit_insn (gen_atomic_compare_and_swapsi_internal (old
, mem
, cmp
, new_rtx
));
1741 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
),
1745 /* Emit a jump instruction to TARGET and return it. If COND is
1746 NULL_RTX, emit an unconditional jump, else a conditional jump under
1750 s390_emit_jump (rtx target
, rtx cond
)
1754 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
1756 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
1758 insn
= gen_rtx_SET (pc_rtx
, target
);
1759 return emit_jump_insn (insn
);
1762 /* Return branch condition mask to implement a branch
1763 specified by CODE. Return -1 for invalid comparisons. */
1766 s390_branch_condition_mask (rtx code
)
1768 const int CC0
= 1 << 3;
1769 const int CC1
= 1 << 2;
1770 const int CC2
= 1 << 1;
1771 const int CC3
= 1 << 0;
1773 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
1774 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
1775 gcc_assert (XEXP (code
, 1) == const0_rtx
1776 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1777 && CONST_INT_P (XEXP (code
, 1))));
1780 switch (GET_MODE (XEXP (code
, 0)))
1784 switch (GET_CODE (code
))
1786 case EQ
: return CC0
;
1787 case NE
: return CC1
| CC2
| CC3
;
1793 switch (GET_CODE (code
))
1795 case EQ
: return CC1
;
1796 case NE
: return CC0
| CC2
| CC3
;
1802 switch (GET_CODE (code
))
1804 case EQ
: return CC2
;
1805 case NE
: return CC0
| CC1
| CC3
;
1811 switch (GET_CODE (code
))
1813 case EQ
: return CC3
;
1814 case NE
: return CC0
| CC1
| CC2
;
1820 switch (GET_CODE (code
))
1822 case EQ
: return CC0
| CC2
;
1823 case NE
: return CC1
| CC3
;
1829 switch (GET_CODE (code
))
1831 case LTU
: return CC2
| CC3
; /* carry */
1832 case GEU
: return CC0
| CC1
; /* no carry */
1838 switch (GET_CODE (code
))
1840 case GTU
: return CC0
| CC1
; /* borrow */
1841 case LEU
: return CC2
| CC3
; /* no borrow */
1847 switch (GET_CODE (code
))
1849 case EQ
: return CC0
| CC2
;
1850 case NE
: return CC1
| CC3
;
1851 case LTU
: return CC1
;
1852 case GTU
: return CC3
;
1853 case LEU
: return CC1
| CC2
;
1854 case GEU
: return CC2
| CC3
;
1859 switch (GET_CODE (code
))
1861 case EQ
: return CC0
;
1862 case NE
: return CC1
| CC2
| CC3
;
1863 case LTU
: return CC1
;
1864 case GTU
: return CC2
;
1865 case LEU
: return CC0
| CC1
;
1866 case GEU
: return CC0
| CC2
;
1872 switch (GET_CODE (code
))
1874 case EQ
: return CC0
;
1875 case NE
: return CC2
| CC1
| CC3
;
1876 case LTU
: return CC2
;
1877 case GTU
: return CC1
;
1878 case LEU
: return CC0
| CC2
;
1879 case GEU
: return CC0
| CC1
;
1885 switch (GET_CODE (code
))
1887 case EQ
: return CC0
;
1888 case NE
: return CC1
| CC2
| CC3
;
1889 case LT
: return CC1
| CC3
;
1890 case GT
: return CC2
;
1891 case LE
: return CC0
| CC1
| CC3
;
1892 case GE
: return CC0
| CC2
;
1898 switch (GET_CODE (code
))
1900 case EQ
: return CC0
;
1901 case NE
: return CC1
| CC2
| CC3
;
1902 case LT
: return CC1
;
1903 case GT
: return CC2
| CC3
;
1904 case LE
: return CC0
| CC1
;
1905 case GE
: return CC0
| CC2
| CC3
;
1911 switch (GET_CODE (code
))
1913 case EQ
: return CC0
;
1914 case NE
: return CC1
| CC2
| CC3
;
1915 case LT
: return CC1
;
1916 case GT
: return CC2
;
1917 case LE
: return CC0
| CC1
;
1918 case GE
: return CC0
| CC2
;
1919 case UNORDERED
: return CC3
;
1920 case ORDERED
: return CC0
| CC1
| CC2
;
1921 case UNEQ
: return CC0
| CC3
;
1922 case UNLT
: return CC1
| CC3
;
1923 case UNGT
: return CC2
| CC3
;
1924 case UNLE
: return CC0
| CC1
| CC3
;
1925 case UNGE
: return CC0
| CC2
| CC3
;
1926 case LTGT
: return CC1
| CC2
;
1932 switch (GET_CODE (code
))
1934 case EQ
: return CC0
;
1935 case NE
: return CC2
| CC1
| CC3
;
1936 case LT
: return CC2
;
1937 case GT
: return CC1
;
1938 case LE
: return CC0
| CC2
;
1939 case GE
: return CC0
| CC1
;
1940 case UNORDERED
: return CC3
;
1941 case ORDERED
: return CC0
| CC2
| CC1
;
1942 case UNEQ
: return CC0
| CC3
;
1943 case UNLT
: return CC2
| CC3
;
1944 case UNGT
: return CC1
| CC3
;
1945 case UNLE
: return CC0
| CC2
| CC3
;
1946 case UNGE
: return CC0
| CC1
| CC3
;
1947 case LTGT
: return CC2
| CC1
;
1952 /* Vector comparison modes. */
1955 switch (GET_CODE (code
))
1957 case EQ
: return CC0
;
1958 case NE
: return CC3
;
1963 switch (GET_CODE (code
))
1965 case EQ
: return CC0
| CC1
;
1966 case NE
: return CC3
| CC1
;
1970 /* Integer vector compare modes. */
1973 switch (GET_CODE (code
))
1975 case GT
: return CC0
;
1976 case LE
: return CC3
;
1981 switch (GET_CODE (code
))
1983 case GT
: return CC0
| CC1
;
1984 case LE
: return CC3
| CC1
;
1989 switch (GET_CODE (code
))
1991 case GTU
: return CC0
;
1992 case LEU
: return CC3
;
1997 switch (GET_CODE (code
))
1999 case GTU
: return CC0
| CC1
;
2000 case LEU
: return CC3
| CC1
;
2004 /* FP vector compare modes. */
2007 switch (GET_CODE (code
))
2009 case GT
: return CC0
;
2010 case UNLE
: return CC3
;
2015 switch (GET_CODE (code
))
2017 case GT
: return CC0
| CC1
;
2018 case UNLE
: return CC3
| CC1
;
2023 switch (GET_CODE (code
))
2025 case GE
: return CC0
;
2026 case UNLT
: return CC3
;
2031 switch (GET_CODE (code
))
2033 case GE
: return CC0
| CC1
;
2034 case UNLT
: return CC3
| CC1
;
2040 switch (GET_CODE (code
))
2043 return INTVAL (XEXP (code
, 1));
2045 return (INTVAL (XEXP (code
, 1))) ^ 0xf;
2056 /* Return branch condition mask to implement a compare and branch
2057 specified by CODE. Return -1 for invalid comparisons. */
2060 s390_compare_and_branch_condition_mask (rtx code
)
2062 const int CC0
= 1 << 3;
2063 const int CC1
= 1 << 2;
2064 const int CC2
= 1 << 1;
2066 switch (GET_CODE (code
))
2090 /* If INV is false, return assembler mnemonic string to implement
2091 a branch specified by CODE. If INV is true, return mnemonic
2092 for the corresponding inverted branch. */
2095 s390_branch_condition_mnemonic (rtx code
, int inv
)
2099 static const char *const mnemonic
[16] =
2101 NULL
, "o", "h", "nle",
2102 "l", "nhe", "lh", "ne",
2103 "e", "nlh", "he", "nl",
2104 "le", "nh", "no", NULL
2107 if (GET_CODE (XEXP (code
, 0)) == REG
2108 && REGNO (XEXP (code
, 0)) == CC_REGNUM
2109 && (XEXP (code
, 1) == const0_rtx
2110 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
2111 && CONST_INT_P (XEXP (code
, 1)))))
2112 mask
= s390_branch_condition_mask (code
);
2114 mask
= s390_compare_and_branch_condition_mask (code
);
2116 gcc_assert (mask
>= 0);
2121 gcc_assert (mask
>= 1 && mask
<= 14);
2123 return mnemonic
[mask
];
2126 /* Return the part of op which has a value different from def.
2127 The size of the part is determined by mode.
2128 Use this function only if you already know that op really
2129 contains such a part. */
2131 unsigned HOST_WIDE_INT
2132 s390_extract_part (rtx op
, machine_mode mode
, int def
)
2134 unsigned HOST_WIDE_INT value
= 0;
2135 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
2136 int part_bits
= GET_MODE_BITSIZE (mode
);
2137 unsigned HOST_WIDE_INT part_mask
2138 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
2141 for (i
= 0; i
< max_parts
; i
++)
2144 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
2146 value
>>= part_bits
;
2148 if ((value
& part_mask
) != (def
& part_mask
))
2149 return value
& part_mask
;
2155 /* If OP is an integer constant of mode MODE with exactly one
2156 part of mode PART_MODE unequal to DEF, return the number of that
2157 part. Otherwise, return -1. */
2160 s390_single_part (rtx op
,
2162 machine_mode part_mode
,
2165 unsigned HOST_WIDE_INT value
= 0;
2166 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
2167 unsigned HOST_WIDE_INT part_mask
2168 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
2171 if (GET_CODE (op
) != CONST_INT
)
2174 for (i
= 0; i
< n_parts
; i
++)
2177 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
2179 value
>>= GET_MODE_BITSIZE (part_mode
);
2181 if ((value
& part_mask
) != (def
& part_mask
))
2189 return part
== -1 ? -1 : n_parts
- 1 - part
;
2192 /* Return true if IN contains a contiguous bitfield in the lower SIZE
2193 bits and no other bits are set in IN. POS and LENGTH can be used
2194 to obtain the start position and the length of the bitfield.
2196 POS gives the position of the first bit of the bitfield counting
2197 from the lowest order bit starting with zero. In order to use this
2198 value for S/390 instructions this has to be converted to "bits big
2202 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
2203 int *pos
, int *length
)
2208 unsigned HOST_WIDE_INT mask
= 1ULL;
2209 bool contiguous
= false;
2211 for (i
= 0; i
< size
; mask
<<= 1, i
++)
2235 /* Calculate a mask for all bits beyond the contiguous bits. */
2236 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
2238 if ((unsigned)size
< sizeof (HOST_WIDE_INT
) * BITS_PER_UNIT
)
2239 mask
&= (HOST_WIDE_INT_1U
<< size
) - 1;
2244 if (tmp_length
+ tmp_pos
- 1 > size
)
2248 *length
= tmp_length
;
2256 /* Return true if OP contains the same contiguous bitfield in *all*
2257 its elements. START and END can be used to obtain the start and
2258 end position of the bitfield.
2260 START/STOP give the position of the first/last bit of the bitfield
2261 counting from the lowest order bit starting with zero. In order to
2262 use these values for S/390 instructions this has to be converted to
2263 "bits big endian" style. */
2266 s390_contiguous_bitmask_vector_p (rtx op
, int *start
, int *end
)
2268 unsigned HOST_WIDE_INT mask
;
2271 if (!VECTOR_MODE_P (GET_MODE (op
))
2272 || GET_CODE (op
) != CONST_VECTOR
2273 || !CONST_INT_P (XVECEXP (op
, 0, 0)))
2276 if (GET_MODE_NUNITS (GET_MODE (op
)) > 1)
2280 for (i
= 1; i
< GET_MODE_NUNITS (GET_MODE (op
)); ++i
)
2281 if (!rtx_equal_p (XVECEXP (op
, 0, i
), XVECEXP (op
, 0, 0)))
2285 size
= GET_MODE_UNIT_BITSIZE (GET_MODE (op
));
2286 mask
= UINTVAL (XVECEXP (op
, 0, 0));
2287 if (s390_contiguous_bitmask_p (mask
, size
, start
,
2288 end
!= NULL
? &length
: NULL
))
2291 *end
= *start
+ length
- 1;
2294 /* 0xff00000f style immediates can be covered by swapping start and
2295 end indices in vgm. */
2296 if (s390_contiguous_bitmask_p (~mask
, size
, start
,
2297 end
!= NULL
? &length
: NULL
))
2302 *start
= *start
+ length
;
2308 /* Return true if C consists only of byte chunks being either 0 or
2309 0xff. If MASK is !=NULL a byte mask is generated which is
2310 appropriate for the vector generate byte mask instruction. */
2313 s390_bytemask_vector_p (rtx op
, unsigned *mask
)
2316 unsigned tmp_mask
= 0;
2317 int nunit
, unit_size
;
2319 if (!VECTOR_MODE_P (GET_MODE (op
))
2320 || GET_CODE (op
) != CONST_VECTOR
2321 || !CONST_INT_P (XVECEXP (op
, 0, 0)))
2324 nunit
= GET_MODE_NUNITS (GET_MODE (op
));
2325 unit_size
= GET_MODE_UNIT_SIZE (GET_MODE (op
));
2327 for (i
= 0; i
< nunit
; i
++)
2329 unsigned HOST_WIDE_INT c
;
2332 if (!CONST_INT_P (XVECEXP (op
, 0, i
)))
2335 c
= UINTVAL (XVECEXP (op
, 0, i
));
2336 for (j
= 0; j
< unit_size
; j
++)
2338 if ((c
& 0xff) != 0 && (c
& 0xff) != 0xff)
2340 tmp_mask
|= (c
& 1) << ((nunit
- 1 - i
) * unit_size
+ j
);
2341 c
= c
>> BITS_PER_UNIT
;
2351 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
2352 equivalent to a shift followed by the AND. In particular, CONTIG
2353 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
2354 for ROTL indicate a rotate to the right. */
2357 s390_extzv_shift_ok (int bitsize
, int rotl
, unsigned HOST_WIDE_INT contig
)
2362 ok
= s390_contiguous_bitmask_p (contig
, bitsize
, &pos
, &len
);
2365 return ((rotl
>= 0 && rotl
<= pos
)
2366 || (rotl
< 0 && -rotl
<= bitsize
- len
- pos
));
2369 /* Check whether we can (and want to) split a double-word
2370 move in mode MODE from SRC to DST into two single-word
2371 moves, moving the subword FIRST_SUBWORD first. */
2374 s390_split_ok_p (rtx dst
, rtx src
, machine_mode mode
, int first_subword
)
2376 /* Floating point and vector registers cannot be split. */
2377 if (FP_REG_P (src
) || FP_REG_P (dst
) || VECTOR_REG_P (src
) || VECTOR_REG_P (dst
))
2380 /* We don't need to split if operands are directly accessible. */
2381 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
2384 /* Non-offsettable memory references cannot be split. */
2385 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
2386 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
2389 /* Moving the first subword must not clobber a register
2390 needed to move the second subword. */
2391 if (register_operand (dst
, mode
))
2393 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
2394 if (reg_overlap_mentioned_p (subreg
, src
))
2401 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
2402 and [MEM2, MEM2 + SIZE] do overlap and false
2406 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
2408 rtx addr1
, addr2
, addr_delta
;
2409 HOST_WIDE_INT delta
;
2411 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2417 addr1
= XEXP (mem1
, 0);
2418 addr2
= XEXP (mem2
, 0);
2420 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2422 /* This overlapping check is used by peepholes merging memory block operations.
2423 Overlapping operations would otherwise be recognized by the S/390 hardware
2424 and would fall back to a slower implementation. Allowing overlapping
2425 operations would lead to slow code but not to wrong code. Therefore we are
2426 somewhat optimistic if we cannot prove that the memory blocks are
2428 That's why we return false here although this may accept operations on
2429 overlapping memory areas. */
2430 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
2433 delta
= INTVAL (addr_delta
);
2436 || (delta
> 0 && delta
< size
)
2437 || (delta
< 0 && -delta
< size
))
2443 /* Check whether the address of memory reference MEM2 equals exactly
2444 the address of memory reference MEM1 plus DELTA. Return true if
2445 we can prove this to be the case, false otherwise. */
2448 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
2450 rtx addr1
, addr2
, addr_delta
;
2452 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2455 addr1
= XEXP (mem1
, 0);
2456 addr2
= XEXP (mem2
, 0);
2458 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2459 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
2465 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
2468 s390_expand_logical_operator (enum rtx_code code
, machine_mode mode
,
2471 machine_mode wmode
= mode
;
2472 rtx dst
= operands
[0];
2473 rtx src1
= operands
[1];
2474 rtx src2
= operands
[2];
2477 /* If we cannot handle the operation directly, use a temp register. */
2478 if (!s390_logical_operator_ok_p (operands
))
2479 dst
= gen_reg_rtx (mode
);
2481 /* QImode and HImode patterns make sense only if we have a destination
2482 in memory. Otherwise perform the operation in SImode. */
2483 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
2486 /* Widen operands if required. */
2489 if (GET_CODE (dst
) == SUBREG
2490 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
2492 else if (REG_P (dst
))
2493 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
2495 dst
= gen_reg_rtx (wmode
);
2497 if (GET_CODE (src1
) == SUBREG
2498 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
2500 else if (GET_MODE (src1
) != VOIDmode
)
2501 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
2503 if (GET_CODE (src2
) == SUBREG
2504 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
2506 else if (GET_MODE (src2
) != VOIDmode
)
2507 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
2510 /* Emit the instruction. */
2511 op
= gen_rtx_SET (dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
2512 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
2513 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
2515 /* Fix up the destination if needed. */
2516 if (dst
!= operands
[0])
2517 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
2520 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
2523 s390_logical_operator_ok_p (rtx
*operands
)
2525 /* If the destination operand is in memory, it needs to coincide
2526 with one of the source operands. After reload, it has to be
2527 the first source operand. */
2528 if (GET_CODE (operands
[0]) == MEM
)
2529 return rtx_equal_p (operands
[0], operands
[1])
2530 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
2535 /* Narrow logical operation CODE of memory operand MEMOP with immediate
2536 operand IMMOP to switch from SS to SI type instructions. */
2539 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
2541 int def
= code
== AND
? -1 : 0;
2545 gcc_assert (GET_CODE (*memop
) == MEM
);
2546 gcc_assert (!MEM_VOLATILE_P (*memop
));
2548 mask
= s390_extract_part (*immop
, QImode
, def
);
2549 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
2550 gcc_assert (part
>= 0);
2552 *memop
= adjust_address (*memop
, QImode
, part
);
2553 *immop
= gen_int_mode (mask
, QImode
);
2557 /* How to allocate a 'struct machine_function'. */
2559 static struct machine_function
*
2560 s390_init_machine_status (void)
2562 return ggc_cleared_alloc
<machine_function
> ();
2565 /* Map for smallest class containing reg regno. */
2567 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
2568 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 0 */
2569 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 4 */
2570 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 8 */
2571 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 12 */
2572 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 16 */
2573 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 20 */
2574 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 24 */
2575 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 28 */
2576 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
, /* 32 */
2577 ACCESS_REGS
, ACCESS_REGS
, VEC_REGS
, VEC_REGS
, /* 36 */
2578 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 40 */
2579 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 44 */
2580 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 48 */
2581 VEC_REGS
, VEC_REGS
/* 52 */
2584 /* Return attribute type of insn. */
2586 static enum attr_type
2587 s390_safe_attr_type (rtx_insn
*insn
)
2589 if (recog_memoized (insn
) >= 0)
2590 return get_attr_type (insn
);
2595 /* Return true if DISP is a valid short displacement. */
2598 s390_short_displacement (rtx disp
)
2600 /* No displacement is OK. */
2604 /* Without the long displacement facility we don't need to
2605 distingiush between long and short displacement. */
2606 if (!TARGET_LONG_DISPLACEMENT
)
2609 /* Integer displacement in range. */
2610 if (GET_CODE (disp
) == CONST_INT
)
2611 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
2613 /* GOT offset is not OK, the GOT can be large. */
2614 if (GET_CODE (disp
) == CONST
2615 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
2616 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
2617 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
2620 /* All other symbolic constants are literal pool references,
2621 which are OK as the literal pool must be small. */
2622 if (GET_CODE (disp
) == CONST
)
2628 /* Decompose a RTL expression ADDR for a memory address into
2629 its components, returned in OUT.
2631 Returns false if ADDR is not a valid memory address, true
2632 otherwise. If OUT is NULL, don't return the components,
2633 but check for validity only.
2635 Note: Only addresses in canonical form are recognized.
2636 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
2637 canonical form so that they will be recognized. */
2640 s390_decompose_address (rtx addr
, struct s390_address
*out
)
2642 HOST_WIDE_INT offset
= 0;
2643 rtx base
= NULL_RTX
;
2644 rtx indx
= NULL_RTX
;
2645 rtx disp
= NULL_RTX
;
2647 bool pointer
= false;
2648 bool base_ptr
= false;
2649 bool indx_ptr
= false;
2650 bool literal_pool
= false;
2652 /* We may need to substitute the literal pool base register into the address
2653 below. However, at this point we do not know which register is going to
2654 be used as base, so we substitute the arg pointer register. This is going
2655 to be treated as holding a pointer below -- it shouldn't be used for any
2657 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
2659 /* Decompose address into base + index + displacement. */
2661 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
2664 else if (GET_CODE (addr
) == PLUS
)
2666 rtx op0
= XEXP (addr
, 0);
2667 rtx op1
= XEXP (addr
, 1);
2668 enum rtx_code code0
= GET_CODE (op0
);
2669 enum rtx_code code1
= GET_CODE (op1
);
2671 if (code0
== REG
|| code0
== UNSPEC
)
2673 if (code1
== REG
|| code1
== UNSPEC
)
2675 indx
= op0
; /* index + base */
2681 base
= op0
; /* base + displacement */
2686 else if (code0
== PLUS
)
2688 indx
= XEXP (op0
, 0); /* index + base + disp */
2689 base
= XEXP (op0
, 1);
2700 disp
= addr
; /* displacement */
2702 /* Extract integer part of displacement. */
2706 if (GET_CODE (disp
) == CONST_INT
)
2708 offset
= INTVAL (disp
);
2711 else if (GET_CODE (disp
) == CONST
2712 && GET_CODE (XEXP (disp
, 0)) == PLUS
2713 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
2715 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
2716 disp
= XEXP (XEXP (disp
, 0), 0);
2720 /* Strip off CONST here to avoid special case tests later. */
2721 if (disp
&& GET_CODE (disp
) == CONST
)
2722 disp
= XEXP (disp
, 0);
2724 /* We can convert literal pool addresses to
2725 displacements by basing them off the base register. */
2726 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
2728 /* Either base or index must be free to hold the base register. */
2730 base
= fake_pool_base
, literal_pool
= true;
2732 indx
= fake_pool_base
, literal_pool
= true;
2736 /* Mark up the displacement. */
2737 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
2738 UNSPEC_LTREL_OFFSET
);
2741 /* Validate base register. */
2744 if (GET_CODE (base
) == UNSPEC
)
2745 switch (XINT (base
, 1))
2749 disp
= gen_rtx_UNSPEC (Pmode
,
2750 gen_rtvec (1, XVECEXP (base
, 0, 0)),
2751 UNSPEC_LTREL_OFFSET
);
2755 base
= XVECEXP (base
, 0, 1);
2758 case UNSPEC_LTREL_BASE
:
2759 if (XVECLEN (base
, 0) == 1)
2760 base
= fake_pool_base
, literal_pool
= true;
2762 base
= XVECEXP (base
, 0, 1);
2770 || (GET_MODE (base
) != SImode
2771 && GET_MODE (base
) != Pmode
))
2774 if (REGNO (base
) == STACK_POINTER_REGNUM
2775 || REGNO (base
) == FRAME_POINTER_REGNUM
2776 || ((reload_completed
|| reload_in_progress
)
2777 && frame_pointer_needed
2778 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
2779 || REGNO (base
) == ARG_POINTER_REGNUM
2781 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
2782 pointer
= base_ptr
= true;
2784 if ((reload_completed
|| reload_in_progress
)
2785 && base
== cfun
->machine
->base_reg
)
2786 pointer
= base_ptr
= literal_pool
= true;
2789 /* Validate index register. */
2792 if (GET_CODE (indx
) == UNSPEC
)
2793 switch (XINT (indx
, 1))
2797 disp
= gen_rtx_UNSPEC (Pmode
,
2798 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
2799 UNSPEC_LTREL_OFFSET
);
2803 indx
= XVECEXP (indx
, 0, 1);
2806 case UNSPEC_LTREL_BASE
:
2807 if (XVECLEN (indx
, 0) == 1)
2808 indx
= fake_pool_base
, literal_pool
= true;
2810 indx
= XVECEXP (indx
, 0, 1);
2818 || (GET_MODE (indx
) != SImode
2819 && GET_MODE (indx
) != Pmode
))
2822 if (REGNO (indx
) == STACK_POINTER_REGNUM
2823 || REGNO (indx
) == FRAME_POINTER_REGNUM
2824 || ((reload_completed
|| reload_in_progress
)
2825 && frame_pointer_needed
2826 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
2827 || REGNO (indx
) == ARG_POINTER_REGNUM
2829 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
2830 pointer
= indx_ptr
= true;
2832 if ((reload_completed
|| reload_in_progress
)
2833 && indx
== cfun
->machine
->base_reg
)
2834 pointer
= indx_ptr
= literal_pool
= true;
2837 /* Prefer to use pointer as base, not index. */
2838 if (base
&& indx
&& !base_ptr
2839 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
2846 /* Validate displacement. */
2849 /* If virtual registers are involved, the displacement will change later
2850 anyway as the virtual registers get eliminated. This could make a
2851 valid displacement invalid, but it is more likely to make an invalid
2852 displacement valid, because we sometimes access the register save area
2853 via negative offsets to one of those registers.
2854 Thus we don't check the displacement for validity here. If after
2855 elimination the displacement turns out to be invalid after all,
2856 this is fixed up by reload in any case. */
2857 /* LRA maintains always displacements up to date and we need to
2858 know the displacement is right during all LRA not only at the
2859 final elimination. */
2861 || (base
!= arg_pointer_rtx
2862 && indx
!= arg_pointer_rtx
2863 && base
!= return_address_pointer_rtx
2864 && indx
!= return_address_pointer_rtx
2865 && base
!= frame_pointer_rtx
2866 && indx
!= frame_pointer_rtx
2867 && base
!= virtual_stack_vars_rtx
2868 && indx
!= virtual_stack_vars_rtx
))
2869 if (!DISP_IN_RANGE (offset
))
2874 /* All the special cases are pointers. */
2877 /* In the small-PIC case, the linker converts @GOT
2878 and @GOTNTPOFF offsets to possible displacements. */
2879 if (GET_CODE (disp
) == UNSPEC
2880 && (XINT (disp
, 1) == UNSPEC_GOT
2881 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2887 /* Accept pool label offsets. */
2888 else if (GET_CODE (disp
) == UNSPEC
2889 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2892 /* Accept literal pool references. */
2893 else if (GET_CODE (disp
) == UNSPEC
2894 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2896 /* In case CSE pulled a non literal pool reference out of
2897 the pool we have to reject the address. This is
2898 especially important when loading the GOT pointer on non
2899 zarch CPUs. In this case the literal pool contains an lt
2900 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2901 will most likely exceed the displacement. */
2902 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2903 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
2906 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2909 /* If we have an offset, make sure it does not
2910 exceed the size of the constant pool entry. */
2911 rtx sym
= XVECEXP (disp
, 0, 0);
2912 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2915 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
2930 out
->disp
= orig_disp
;
2931 out
->pointer
= pointer
;
2932 out
->literal_pool
= literal_pool
;
2938 /* Decompose a RTL expression OP for a shift count into its components,
2939 and return the base register in BASE and the offset in OFFSET.
2941 Return true if OP is a valid shift count, false if not. */
2944 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2946 HOST_WIDE_INT off
= 0;
2948 /* We can have an integer constant, an address register,
2949 or a sum of the two. */
2950 if (GET_CODE (op
) == CONST_INT
)
2955 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2957 off
= INTVAL (XEXP (op
, 1));
2960 while (op
&& GET_CODE (op
) == SUBREG
)
2961 op
= SUBREG_REG (op
);
2963 if (op
&& GET_CODE (op
) != REG
)
2975 /* Return true if CODE is a valid address without index. */
2978 s390_legitimate_address_without_index_p (rtx op
)
2980 struct s390_address addr
;
2982 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2991 /* Return TRUE if ADDR is an operand valid for a load/store relative
2992 instruction. Be aware that the alignment of the operand needs to
2993 be checked separately.
2994 Valid addresses are single references or a sum of a reference and a
2995 constant integer. Return these parts in SYMREF and ADDEND. You can
2996 pass NULL in REF and/or ADDEND if you are not interested in these
2997 values. Literal pool references are *not* considered symbol
3001 s390_loadrelative_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
3003 HOST_WIDE_INT tmpaddend
= 0;
3005 if (GET_CODE (addr
) == CONST
)
3006 addr
= XEXP (addr
, 0);
3008 if (GET_CODE (addr
) == PLUS
)
3010 if (!CONST_INT_P (XEXP (addr
, 1)))
3013 tmpaddend
= INTVAL (XEXP (addr
, 1));
3014 addr
= XEXP (addr
, 0);
3017 if ((GET_CODE (addr
) == SYMBOL_REF
&& !CONSTANT_POOL_ADDRESS_P (addr
))
3018 || (GET_CODE (addr
) == UNSPEC
3019 && (XINT (addr
, 1) == UNSPEC_GOTENT
3020 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
3025 *addend
= tmpaddend
;
3032 /* Return true if the address in OP is valid for constraint letter C
3033 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
3034 pool MEMs should be accepted. Only the Q, R, S, T constraint
3035 letters are allowed for C. */
3038 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
3040 struct s390_address addr
;
3041 bool decomposed
= false;
3043 /* This check makes sure that no symbolic address (except literal
3044 pool references) are accepted by the R or T constraints. */
3045 if (s390_loadrelative_operand_p (op
, NULL
, NULL
))
3048 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
3051 if (!s390_decompose_address (op
, &addr
))
3053 if (addr
.literal_pool
)
3060 case 'Q': /* no index short displacement */
3061 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3065 if (!s390_short_displacement (addr
.disp
))
3069 case 'R': /* with index short displacement */
3070 if (TARGET_LONG_DISPLACEMENT
)
3072 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3074 if (!s390_short_displacement (addr
.disp
))
3077 /* Any invalid address here will be fixed up by reload,
3078 so accept it for the most generic constraint. */
3081 case 'S': /* no index long displacement */
3082 if (!TARGET_LONG_DISPLACEMENT
)
3084 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3088 if (s390_short_displacement (addr
.disp
))
3092 case 'T': /* with index long displacement */
3093 if (!TARGET_LONG_DISPLACEMENT
)
3095 /* Any invalid address here will be fixed up by reload,
3096 so accept it for the most generic constraint. */
3097 if ((decomposed
|| s390_decompose_address (op
, &addr
))
3098 && s390_short_displacement (addr
.disp
))
3108 /* Evaluates constraint strings described by the regular expression
3109 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
3110 the constraint given in STR, or 0 else. */
3113 s390_mem_constraint (const char *str
, rtx op
)
3120 /* Check for offsettable variants of memory constraints. */
3121 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
3123 if ((reload_completed
|| reload_in_progress
)
3124 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
3126 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
3128 /* Check for non-literal-pool variants of memory constraints. */
3131 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
3136 if (GET_CODE (op
) != MEM
)
3138 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
3140 return (s390_check_qrst_address ('Q', op
, true)
3141 || s390_check_qrst_address ('R', op
, true));
3143 return (s390_check_qrst_address ('S', op
, true)
3144 || s390_check_qrst_address ('T', op
, true));
3146 /* Simply check for the basic form of a shift count. Reload will
3147 take care of making sure we have a proper base register. */
3148 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
3152 return s390_check_qrst_address (str
[1], op
, true);
3160 /* Evaluates constraint strings starting with letter O. Input
3161 parameter C is the second letter following the "O" in the constraint
3162 string. Returns 1 if VALUE meets the respective constraint and 0
3166 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
3174 return trunc_int_for_mode (value
, SImode
) == value
;
3178 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
3181 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
3189 /* Evaluates constraint strings starting with letter N. Parameter STR
3190 contains the letters following letter "N" in the constraint string.
3191 Returns true if VALUE matches the constraint. */
3194 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
3196 machine_mode mode
, part_mode
;
3198 int part
, part_goal
;
3204 part_goal
= str
[0] - '0';
3248 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
3251 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
3254 if (part_goal
!= -1 && part_goal
!= part
)
3261 /* Returns true if the input parameter VALUE is a float zero. */
3264 s390_float_const_zero_p (rtx value
)
3266 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
3267 && value
== CONST0_RTX (GET_MODE (value
)));
3270 /* Implement TARGET_REGISTER_MOVE_COST. */
3273 s390_register_move_cost (machine_mode mode
,
3274 reg_class_t from
, reg_class_t to
)
3276 /* On s390, copy between fprs and gprs is expensive. */
3278 /* It becomes somewhat faster having ldgr/lgdr. */
3279 if (TARGET_Z10
&& GET_MODE_SIZE (mode
) == 8)
3281 /* ldgr is single cycle. */
3282 if (reg_classes_intersect_p (from
, GENERAL_REGS
)
3283 && reg_classes_intersect_p (to
, FP_REGS
))
3285 /* lgdr needs 3 cycles. */
3286 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
3287 && reg_classes_intersect_p (from
, FP_REGS
))
3291 /* Otherwise copying is done via memory. */
3292 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
3293 && reg_classes_intersect_p (to
, FP_REGS
))
3294 || (reg_classes_intersect_p (from
, FP_REGS
)
3295 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
3301 /* Implement TARGET_MEMORY_MOVE_COST. */
3304 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3305 reg_class_t rclass ATTRIBUTE_UNUSED
,
3306 bool in ATTRIBUTE_UNUSED
)
3311 /* Compute a (partial) cost for rtx X. Return true if the complete
3312 cost has been computed, and false if subexpressions should be
3313 scanned. In either case, *TOTAL contains the cost result.
3314 CODE contains GET_CODE (x), OUTER_CODE contains the code
3315 of the superexpression of x. */
3318 s390_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3319 int *total
, bool speed ATTRIBUTE_UNUSED
)
3342 *total
= COSTS_N_INSNS (1);
3347 *total
= COSTS_N_INSNS (1);
3351 switch (GET_MODE (x
))
3355 rtx left
= XEXP (x
, 0);
3356 rtx right
= XEXP (x
, 1);
3357 if (GET_CODE (right
) == CONST_INT
3358 && CONST_OK_FOR_K (INTVAL (right
)))
3359 *total
= s390_cost
->mhi
;
3360 else if (GET_CODE (left
) == SIGN_EXTEND
)
3361 *total
= s390_cost
->mh
;
3363 *total
= s390_cost
->ms
; /* msr, ms, msy */
3368 rtx left
= XEXP (x
, 0);
3369 rtx right
= XEXP (x
, 1);
3372 if (GET_CODE (right
) == CONST_INT
3373 && CONST_OK_FOR_K (INTVAL (right
)))
3374 *total
= s390_cost
->mghi
;
3375 else if (GET_CODE (left
) == SIGN_EXTEND
)
3376 *total
= s390_cost
->msgf
;
3378 *total
= s390_cost
->msg
; /* msgr, msg */
3380 else /* TARGET_31BIT */
3382 if (GET_CODE (left
) == SIGN_EXTEND
3383 && GET_CODE (right
) == SIGN_EXTEND
)
3384 /* mulsidi case: mr, m */
3385 *total
= s390_cost
->m
;
3386 else if (GET_CODE (left
) == ZERO_EXTEND
3387 && GET_CODE (right
) == ZERO_EXTEND
3388 && TARGET_CPU_ZARCH
)
3389 /* umulsidi case: ml, mlr */
3390 *total
= s390_cost
->ml
;
3392 /* Complex calculation is required. */
3393 *total
= COSTS_N_INSNS (40);
3399 *total
= s390_cost
->mult_df
;
3402 *total
= s390_cost
->mxbr
;
3410 switch (GET_MODE (x
))
3413 *total
= s390_cost
->madbr
;
3416 *total
= s390_cost
->maebr
;
3421 /* Negate in the third argument is free: FMSUB. */
3422 if (GET_CODE (XEXP (x
, 2)) == NEG
)
3424 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, 0, speed
)
3425 + rtx_cost (XEXP (x
, 1), FMA
, 1, speed
)
3426 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, 2, speed
));
3433 if (GET_MODE (x
) == TImode
) /* 128 bit division */
3434 *total
= s390_cost
->dlgr
;
3435 else if (GET_MODE (x
) == DImode
)
3437 rtx right
= XEXP (x
, 1);
3438 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3439 *total
= s390_cost
->dlr
;
3440 else /* 64 by 64 bit division */
3441 *total
= s390_cost
->dlgr
;
3443 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
3444 *total
= s390_cost
->dlr
;
3449 if (GET_MODE (x
) == DImode
)
3451 rtx right
= XEXP (x
, 1);
3452 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3454 *total
= s390_cost
->dsgfr
;
3456 *total
= s390_cost
->dr
;
3457 else /* 64 by 64 bit division */
3458 *total
= s390_cost
->dsgr
;
3460 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
3461 *total
= s390_cost
->dlr
;
3462 else if (GET_MODE (x
) == SFmode
)
3464 *total
= s390_cost
->debr
;
3466 else if (GET_MODE (x
) == DFmode
)
3468 *total
= s390_cost
->ddbr
;
3470 else if (GET_MODE (x
) == TFmode
)
3472 *total
= s390_cost
->dxbr
;
3477 if (GET_MODE (x
) == SFmode
)
3478 *total
= s390_cost
->sqebr
;
3479 else if (GET_MODE (x
) == DFmode
)
3480 *total
= s390_cost
->sqdbr
;
3482 *total
= s390_cost
->sqxbr
;
3487 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
3488 || outer_code
== PLUS
|| outer_code
== MINUS
3489 || outer_code
== COMPARE
)
3494 *total
= COSTS_N_INSNS (1);
3495 if (GET_CODE (XEXP (x
, 0)) == AND
3496 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3497 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
3499 rtx op0
= XEXP (XEXP (x
, 0), 0);
3500 rtx op1
= XEXP (XEXP (x
, 0), 1);
3501 rtx op2
= XEXP (x
, 1);
3503 if (memory_operand (op0
, GET_MODE (op0
))
3504 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
3506 if (register_operand (op0
, GET_MODE (op0
))
3507 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
3517 /* Return the cost of an address rtx ADDR. */
3520 s390_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
3521 addr_space_t as ATTRIBUTE_UNUSED
,
3522 bool speed ATTRIBUTE_UNUSED
)
3524 struct s390_address ad
;
3525 if (!s390_decompose_address (addr
, &ad
))
3528 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
3531 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
3532 otherwise return 0. */
3535 tls_symbolic_operand (rtx op
)
3537 if (GET_CODE (op
) != SYMBOL_REF
)
3539 return SYMBOL_REF_TLS_MODEL (op
);
3542 /* Split DImode access register reference REG (on 64-bit) into its constituent
3543 low and high parts, and store them into LO and HI. Note that gen_lowpart/
3544 gen_highpart cannot be used as they assume all registers are word-sized,
3545 while our access registers have only half that size. */
3548 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
3550 gcc_assert (TARGET_64BIT
);
3551 gcc_assert (ACCESS_REG_P (reg
));
3552 gcc_assert (GET_MODE (reg
) == DImode
);
3553 gcc_assert (!(REGNO (reg
) & 1));
3555 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
3556 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
3559 /* Return true if OP contains a symbol reference */
3562 symbolic_reference_mentioned_p (rtx op
)
3567 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
3570 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3571 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3577 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3578 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3582 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
3589 /* Return true if OP contains a reference to a thread-local symbol. */
3592 tls_symbolic_reference_mentioned_p (rtx op
)
3597 if (GET_CODE (op
) == SYMBOL_REF
)
3598 return tls_symbolic_operand (op
);
3600 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3601 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3607 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3608 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3612 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
3620 /* Return true if OP is a legitimate general operand when
3621 generating PIC code. It is given that flag_pic is on
3622 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
3625 legitimate_pic_operand_p (rtx op
)
3627 /* Accept all non-symbolic constants. */
3628 if (!SYMBOLIC_CONST (op
))
3631 /* Reject everything else; must be handled
3632 via emit_symbolic_move. */
3636 /* Returns true if the constant value OP is a legitimate general operand.
3637 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
3640 s390_legitimate_constant_p (machine_mode mode
, rtx op
)
3642 if (TARGET_VX
&& VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
3644 if (GET_MODE_SIZE (mode
) != 16)
3647 if (!const0_operand (op
, mode
)
3648 && !s390_contiguous_bitmask_vector_p (op
, NULL
, NULL
)
3649 && !s390_bytemask_vector_p (op
, NULL
))
3653 /* Accept all non-symbolic constants. */
3654 if (!SYMBOLIC_CONST (op
))
3657 /* Accept immediate LARL operands. */
3658 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
3661 /* Thread-local symbols are never legal constants. This is
3662 so that emit_call knows that computing such addresses
3663 might require a function call. */
3664 if (TLS_SYMBOLIC_CONST (op
))
3667 /* In the PIC case, symbolic constants must *not* be
3668 forced into the literal pool. We accept them here,
3669 so that they will be handled by emit_symbolic_move. */
3673 /* All remaining non-PIC symbolic constants are
3674 forced into the literal pool. */
3678 /* Determine if it's legal to put X into the constant pool. This
3679 is not possible if X contains the address of a symbol that is
3680 not constant (TLS) or not known at final link time (PIC). */
3683 s390_cannot_force_const_mem (machine_mode mode
, rtx x
)
3685 switch (GET_CODE (x
))
3690 /* Accept all non-symbolic constants. */
3694 /* Labels are OK iff we are non-PIC. */
3695 return flag_pic
!= 0;
3698 /* 'Naked' TLS symbol references are never OK,
3699 non-TLS symbols are OK iff we are non-PIC. */
3700 if (tls_symbolic_operand (x
))
3703 return flag_pic
!= 0;
3706 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
3709 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
3710 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
3713 switch (XINT (x
, 1))
3715 /* Only lt-relative or GOT-relative UNSPECs are OK. */
3716 case UNSPEC_LTREL_OFFSET
:
3724 case UNSPEC_GOTNTPOFF
:
3725 case UNSPEC_INDNTPOFF
:
3728 /* If the literal pool shares the code section, be put
3729 execute template placeholders into the pool as well. */
3731 return TARGET_CPU_ZARCH
;
3743 /* Returns true if the constant value OP is a legitimate general
3744 operand during and after reload. The difference to
3745 legitimate_constant_p is that this function will not accept
3746 a constant that would need to be forced to the literal pool
3747 before it can be used as operand.
3748 This function accepts all constants which can be loaded directly
3752 legitimate_reload_constant_p (rtx op
)
3754 /* Accept la(y) operands. */
3755 if (GET_CODE (op
) == CONST_INT
3756 && DISP_IN_RANGE (INTVAL (op
)))
3759 /* Accept l(g)hi/l(g)fi operands. */
3760 if (GET_CODE (op
) == CONST_INT
3761 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
3764 /* Accept lliXX operands. */
3766 && GET_CODE (op
) == CONST_INT
3767 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
3768 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
3772 && GET_CODE (op
) == CONST_INT
3773 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
3774 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
3777 /* Accept larl operands. */
3778 if (TARGET_CPU_ZARCH
3779 && larl_operand (op
, VOIDmode
))
3782 /* Accept floating-point zero operands that fit into a single GPR. */
3783 if (GET_CODE (op
) == CONST_DOUBLE
3784 && s390_float_const_zero_p (op
)
3785 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
3788 /* Accept double-word operands that can be split. */
3789 if (GET_CODE (op
) == CONST_INT
3790 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
3792 machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
3793 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
3794 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
3795 return legitimate_reload_constant_p (hi
)
3796 && legitimate_reload_constant_p (lo
);
3799 /* Everything else cannot be handled without reload. */
3803 /* Returns true if the constant value OP is a legitimate fp operand
3804 during and after reload.
3805 This function accepts all constants which can be loaded directly
3809 legitimate_reload_fp_constant_p (rtx op
)
3811 /* Accept floating-point zero operands if the load zero instruction
3812 can be used. Prior to z196 the load fp zero instruction caused a
3813 performance penalty if the result is used as BFP number. */
3815 && GET_CODE (op
) == CONST_DOUBLE
3816 && s390_float_const_zero_p (op
))
3822 /* Returns true if the constant value OP is a legitimate vector operand
3823 during and after reload.
3824 This function accepts all constants which can be loaded directly
3828 legitimate_reload_vector_constant_p (rtx op
)
3830 /* FIXME: Support constant vectors with all the same 16 bit unsigned
3831 operands. These can be loaded with vrepi. */
3833 if (TARGET_VX
&& GET_MODE_SIZE (GET_MODE (op
)) == 16
3834 && (const0_operand (op
, GET_MODE (op
))
3835 || constm1_operand (op
, GET_MODE (op
))
3836 || s390_contiguous_bitmask_vector_p (op
, NULL
, NULL
)
3837 || s390_bytemask_vector_p (op
, NULL
)))
3843 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
3844 return the class of reg to actually use. */
3847 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
3849 switch (GET_CODE (op
))
3851 /* Constants we cannot reload into general registers
3852 must be forced into the literal pool. */
3856 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
3857 && legitimate_reload_constant_p (op
))
3858 return GENERAL_REGS
;
3859 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
3860 && legitimate_reload_constant_p (op
))
3862 else if (reg_class_subset_p (FP_REGS
, rclass
)
3863 && legitimate_reload_fp_constant_p (op
))
3865 else if (reg_class_subset_p (VEC_REGS
, rclass
)
3866 && legitimate_reload_vector_constant_p (op
))
3871 /* If a symbolic constant or a PLUS is reloaded,
3872 it is most likely being used as an address, so
3873 prefer ADDR_REGS. If 'class' is not a superset
3874 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
3876 /* Symrefs cannot be pushed into the literal pool with -fPIC
3877 so we *MUST NOT* return NO_REGS for these cases
3878 (s390_cannot_force_const_mem will return true).
3880 On the other hand we MUST return NO_REGS for symrefs with
3881 invalid addend which might have been pushed to the literal
3882 pool (no -fPIC). Usually we would expect them to be
3883 handled via secondary reload but this does not happen if
3884 they are used as literal pool slot replacement in reload
3885 inheritance (see emit_input_reload_insns). */
3886 if (TARGET_CPU_ZARCH
3887 && GET_CODE (XEXP (op
, 0)) == PLUS
3888 && GET_CODE (XEXP (XEXP(op
, 0), 0)) == SYMBOL_REF
3889 && GET_CODE (XEXP (XEXP(op
, 0), 1)) == CONST_INT
)
3891 if (flag_pic
&& reg_class_subset_p (ADDR_REGS
, rclass
))
3899 if (!legitimate_reload_constant_p (op
))
3903 /* load address will be used. */
3904 if (reg_class_subset_p (ADDR_REGS
, rclass
))
3916 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
3917 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3921 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
3923 HOST_WIDE_INT addend
;
3926 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
3929 if (addend
& (alignment
- 1))
3932 if (GET_CODE (symref
) == SYMBOL_REF
3933 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
))
3936 if (GET_CODE (symref
) == UNSPEC
3937 && alignment
<= UNITS_PER_LONG
)
3943 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3944 operand SCRATCH is used to reload the even part of the address and
3948 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
3950 HOST_WIDE_INT addend
;
3953 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
3957 /* Easy case. The addend is even so larl will do fine. */
3958 emit_move_insn (reg
, addr
);
3961 /* We can leave the scratch register untouched if the target
3962 register is a valid base register. */
3963 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
3964 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
3967 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
3968 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
3971 emit_move_insn (scratch
,
3972 gen_rtx_CONST (Pmode
,
3973 gen_rtx_PLUS (Pmode
, symref
,
3974 GEN_INT (addend
- 1))));
3976 emit_move_insn (scratch
, symref
);
3978 /* Increment the address using la in order to avoid clobbering cc. */
3979 s390_load_address (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
3983 /* Generate what is necessary to move between REG and MEM using
3984 SCRATCH. The direction is given by TOMEM. */
3987 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3989 /* Reload might have pulled a constant out of the literal pool.
3990 Force it back in. */
3991 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3992 || GET_CODE (mem
) == CONST_VECTOR
3993 || GET_CODE (mem
) == CONST
)
3994 mem
= force_const_mem (GET_MODE (reg
), mem
);
3996 gcc_assert (MEM_P (mem
));
3998 /* For a load from memory we can leave the scratch register
3999 untouched if the target register is a valid base register. */
4001 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
4002 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
4003 && GET_MODE (reg
) == GET_MODE (scratch
))
4006 /* Load address into scratch register. Since we can't have a
4007 secondary reload for a secondary reload we have to cover the case
4008 where larl would need a secondary reload here as well. */
4009 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
4011 /* Now we can use a standard load/store to do the move. */
4013 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
4015 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
4018 /* Inform reload about cases where moving X with a mode MODE to a register in
4019 RCLASS requires an extra scratch or immediate register. Return the class
4020 needed for the immediate register. */
4023 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
4024 machine_mode mode
, secondary_reload_info
*sri
)
4026 enum reg_class rclass
= (enum reg_class
) rclass_i
;
4028 /* Intermediate register needed. */
4029 if (reg_classes_intersect_p (CC_REGS
, rclass
))
4030 return GENERAL_REGS
;
4034 /* The vst/vl vector move instructions allow only for short
4037 && GET_CODE (XEXP (x
, 0)) == PLUS
4038 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4039 && !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x
, 0), 1)))
4040 && reg_class_subset_p (rclass
, VEC_REGS
)
4041 && (!reg_class_subset_p (rclass
, FP_REGS
)
4042 || (GET_MODE_SIZE (mode
) > 8
4043 && s390_class_max_nregs (FP_REGS
, mode
) == 1)))
4046 sri
->icode
= (TARGET_64BIT
?
4047 CODE_FOR_reloaddi_la_in
:
4048 CODE_FOR_reloadsi_la_in
);
4050 sri
->icode
= (TARGET_64BIT
?
4051 CODE_FOR_reloaddi_la_out
:
4052 CODE_FOR_reloadsi_la_out
);
4058 HOST_WIDE_INT offset
;
4061 /* On z10 several optimizer steps may generate larl operands with
4064 && s390_loadrelative_operand_p (x
, &symref
, &offset
)
4066 && !SYMBOL_REF_ALIGN1_P (symref
)
4067 && (offset
& 1) == 1)
4068 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
4069 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
4071 /* Handle all the (mem (symref)) accesses we cannot use the z10
4072 instructions for. */
4074 && s390_loadrelative_operand_p (XEXP (x
, 0), NULL
, NULL
)
4076 || !reg_class_subset_p (rclass
, GENERAL_REGS
)
4077 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4078 || !s390_check_symref_alignment (XEXP (x
, 0),
4079 GET_MODE_SIZE (mode
))))
4081 #define __SECONDARY_RELOAD_CASE(M,m) \
4084 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
4085 CODE_FOR_reload##m##di_tomem_z10; \
4087 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
4088 CODE_FOR_reload##m##si_tomem_z10; \
4091 switch (GET_MODE (x
))
4093 __SECONDARY_RELOAD_CASE (QI
, qi
);
4094 __SECONDARY_RELOAD_CASE (HI
, hi
);
4095 __SECONDARY_RELOAD_CASE (SI
, si
);
4096 __SECONDARY_RELOAD_CASE (DI
, di
);
4097 __SECONDARY_RELOAD_CASE (TI
, ti
);
4098 __SECONDARY_RELOAD_CASE (SF
, sf
);
4099 __SECONDARY_RELOAD_CASE (DF
, df
);
4100 __SECONDARY_RELOAD_CASE (TF
, tf
);
4101 __SECONDARY_RELOAD_CASE (SD
, sd
);
4102 __SECONDARY_RELOAD_CASE (DD
, dd
);
4103 __SECONDARY_RELOAD_CASE (TD
, td
);
4104 __SECONDARY_RELOAD_CASE (V1QI
, v1qi
);
4105 __SECONDARY_RELOAD_CASE (V2QI
, v2qi
);
4106 __SECONDARY_RELOAD_CASE (V4QI
, v4qi
);
4107 __SECONDARY_RELOAD_CASE (V8QI
, v8qi
);
4108 __SECONDARY_RELOAD_CASE (V16QI
, v16qi
);
4109 __SECONDARY_RELOAD_CASE (V1HI
, v1hi
);
4110 __SECONDARY_RELOAD_CASE (V2HI
, v2hi
);
4111 __SECONDARY_RELOAD_CASE (V4HI
, v4hi
);
4112 __SECONDARY_RELOAD_CASE (V8HI
, v8hi
);
4113 __SECONDARY_RELOAD_CASE (V1SI
, v1si
);
4114 __SECONDARY_RELOAD_CASE (V2SI
, v2si
);
4115 __SECONDARY_RELOAD_CASE (V4SI
, v4si
);
4116 __SECONDARY_RELOAD_CASE (V1DI
, v1di
);
4117 __SECONDARY_RELOAD_CASE (V2DI
, v2di
);
4118 __SECONDARY_RELOAD_CASE (V1TI
, v1ti
);
4119 __SECONDARY_RELOAD_CASE (V1SF
, v1sf
);
4120 __SECONDARY_RELOAD_CASE (V2SF
, v2sf
);
4121 __SECONDARY_RELOAD_CASE (V4SF
, v4sf
);
4122 __SECONDARY_RELOAD_CASE (V1DF
, v1df
);
4123 __SECONDARY_RELOAD_CASE (V2DF
, v2df
);
4124 __SECONDARY_RELOAD_CASE (V1TF
, v1tf
);
4128 #undef __SECONDARY_RELOAD_CASE
4132 /* We need a scratch register when loading a PLUS expression which
4133 is not a legitimate operand of the LOAD ADDRESS instruction. */
4134 /* LRA can deal with transformation of plus op very well -- so we
4135 don't need to prompt LRA in this case. */
4136 if (! lra_in_progress
&& in_p
&& s390_plus_operand (x
, mode
))
4137 sri
->icode
= (TARGET_64BIT
?
4138 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
4140 /* Performing a multiword move from or to memory we have to make sure the
4141 second chunk in memory is addressable without causing a displacement
4142 overflow. If that would be the case we calculate the address in
4143 a scratch register. */
4145 && GET_CODE (XEXP (x
, 0)) == PLUS
4146 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4147 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
4148 + GET_MODE_SIZE (mode
) - 1))
4150 /* For GENERAL_REGS a displacement overflow is no problem if occurring
4151 in a s_operand address since we may fallback to lm/stm. So we only
4152 have to care about overflows in the b+i+d case. */
4153 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
4154 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
4155 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4156 /* For FP_REGS no lm/stm is available so this check is triggered
4157 for displacement overflows in b+i+d and b+d like addresses. */
4158 || (reg_classes_intersect_p (FP_REGS
, rclass
)
4159 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
4162 sri
->icode
= (TARGET_64BIT
?
4163 CODE_FOR_reloaddi_la_in
:
4164 CODE_FOR_reloadsi_la_in
);
4166 sri
->icode
= (TARGET_64BIT
?
4167 CODE_FOR_reloaddi_la_out
:
4168 CODE_FOR_reloadsi_la_out
);
4172 /* A scratch address register is needed when a symbolic constant is
4173 copied to r0 compiling with -fPIC. In other cases the target
4174 register might be used as temporary (see legitimize_pic_address). */
4175 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
4176 sri
->icode
= (TARGET_64BIT
?
4177 CODE_FOR_reloaddi_PIC_addr
:
4178 CODE_FOR_reloadsi_PIC_addr
);
4180 /* Either scratch or no register needed. */
4184 /* Generate code to load SRC, which is PLUS that is not a
4185 legitimate operand for the LA instruction, into TARGET.
4186 SCRATCH may be used as scratch register. */
4189 s390_expand_plus_operand (rtx target
, rtx src
,
4193 struct s390_address ad
;
4195 /* src must be a PLUS; get its two operands. */
4196 gcc_assert (GET_CODE (src
) == PLUS
);
4197 gcc_assert (GET_MODE (src
) == Pmode
);
4199 /* Check if any of the two operands is already scheduled
4200 for replacement by reload. This can happen e.g. when
4201 float registers occur in an address. */
4202 sum1
= find_replacement (&XEXP (src
, 0));
4203 sum2
= find_replacement (&XEXP (src
, 1));
4204 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4206 /* If the address is already strictly valid, there's nothing to do. */
4207 if (!s390_decompose_address (src
, &ad
)
4208 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4209 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
4211 /* Otherwise, one of the operands cannot be an address register;
4212 we reload its value into the scratch register. */
4213 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
4215 emit_move_insn (scratch
, sum1
);
4218 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
4220 emit_move_insn (scratch
, sum2
);
4224 /* According to the way these invalid addresses are generated
4225 in reload.c, it should never happen (at least on s390) that
4226 *neither* of the PLUS components, after find_replacements
4227 was applied, is an address register. */
4228 if (sum1
== scratch
&& sum2
== scratch
)
4234 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4237 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
4238 is only ever performed on addresses, so we can mark the
4239 sum as legitimate for LA in any case. */
4240 s390_load_address (target
, src
);
4244 /* Return true if ADDR is a valid memory address.
4245 STRICT specifies whether strict register checking applies. */
4248 s390_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4250 struct s390_address ad
;
4253 && larl_operand (addr
, VOIDmode
)
4254 && (mode
== VOIDmode
4255 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
4258 if (!s390_decompose_address (addr
, &ad
))
4263 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4266 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
4272 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
4273 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
4277 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
4278 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
4284 /* Return true if OP is a valid operand for the LA instruction.
4285 In 31-bit, we need to prove that the result is used as an
4286 address, as LA performs only a 31-bit addition. */
4289 legitimate_la_operand_p (rtx op
)
4291 struct s390_address addr
;
4292 if (!s390_decompose_address (op
, &addr
))
4295 return (TARGET_64BIT
|| addr
.pointer
);
4298 /* Return true if it is valid *and* preferable to use LA to
4299 compute the sum of OP1 and OP2. */
4302 preferred_la_operand_p (rtx op1
, rtx op2
)
4304 struct s390_address addr
;
4306 if (op2
!= const0_rtx
)
4307 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
4309 if (!s390_decompose_address (op1
, &addr
))
4311 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
4313 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
4316 /* Avoid LA instructions with index register on z196; it is
4317 preferable to use regular add instructions when possible.
4318 Starting with zEC12 the la with index register is "uncracked"
4320 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
4323 if (!TARGET_64BIT
&& !addr
.pointer
)
4329 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
4330 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
4336 /* Emit a forced load-address operation to load SRC into DST.
4337 This will use the LOAD ADDRESS instruction even in situations
4338 where legitimate_la_operand_p (SRC) returns false. */
4341 s390_load_address (rtx dst
, rtx src
)
4344 emit_move_insn (dst
, src
);
4346 emit_insn (gen_force_la_31 (dst
, src
));
4349 /* Return a legitimate reference for ORIG (an address) using the
4350 register REG. If REG is 0, a new pseudo is generated.
4352 There are two types of references that must be handled:
4354 1. Global data references must load the address from the GOT, via
4355 the PIC reg. An insn is emitted to do this load, and the reg is
4358 2. Static data references, constant pool addresses, and code labels
4359 compute the address as an offset from the GOT, whose base is in
4360 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
4361 differentiate them from global data objects. The returned
4362 address is the PIC reg + an unspec constant.
4364 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
4365 reg also appears in the address. */
4368 legitimize_pic_address (rtx orig
, rtx reg
)
4371 rtx addend
= const0_rtx
;
4374 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
4376 if (GET_CODE (addr
) == CONST
)
4377 addr
= XEXP (addr
, 0);
4379 if (GET_CODE (addr
) == PLUS
)
4381 addend
= XEXP (addr
, 1);
4382 addr
= XEXP (addr
, 0);
4385 if ((GET_CODE (addr
) == LABEL_REF
4386 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
))
4387 || (GET_CODE (addr
) == UNSPEC
&&
4388 (XINT (addr
, 1) == UNSPEC_GOTENT
4389 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
4390 && GET_CODE (addend
) == CONST_INT
)
4392 /* This can be locally addressed. */
4394 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
4395 rtx const_addr
= (GET_CODE (addr
) == UNSPEC
?
4396 gen_rtx_CONST (Pmode
, addr
) : addr
);
4398 if (TARGET_CPU_ZARCH
4399 && larl_operand (const_addr
, VOIDmode
)
4400 && INTVAL (addend
) < (HOST_WIDE_INT
)1 << 31
4401 && INTVAL (addend
) >= -((HOST_WIDE_INT
)1 << 31))
4403 if (INTVAL (addend
) & 1)
4405 /* LARL can't handle odd offsets, so emit a pair of LARL
4407 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4409 if (!DISP_IN_RANGE (INTVAL (addend
)))
4411 HOST_WIDE_INT even
= INTVAL (addend
) - 1;
4412 addr
= gen_rtx_PLUS (Pmode
, addr
, GEN_INT (even
));
4413 addr
= gen_rtx_CONST (Pmode
, addr
);
4414 addend
= const1_rtx
;
4417 emit_move_insn (temp
, addr
);
4418 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, addend
);
4422 s390_load_address (reg
, new_rtx
);
4428 /* If the offset is even, we can just use LARL. This
4429 will happen automatically. */
4434 /* No larl - Access local symbols relative to the GOT. */
4436 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4438 if (reload_in_progress
|| reload_completed
)
4439 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4441 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
4442 if (addend
!= const0_rtx
)
4443 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
4444 addr
= gen_rtx_CONST (Pmode
, addr
);
4445 addr
= force_const_mem (Pmode
, addr
);
4446 emit_move_insn (temp
, addr
);
4448 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4451 s390_load_address (reg
, new_rtx
);
4456 else if (GET_CODE (addr
) == SYMBOL_REF
&& addend
== const0_rtx
)
4458 /* A non-local symbol reference without addend.
4460 The symbol ref is wrapped into an UNSPEC to make sure the
4461 proper operand modifier (@GOT or @GOTENT) will be emitted.
4462 This will tell the linker to put the symbol into the GOT.
4464 Additionally the code dereferencing the GOT slot is emitted here.
4466 An addend to the symref needs to be added afterwards.
4467 legitimize_pic_address calls itself recursively to handle
4468 that case. So no need to do it here. */
4471 reg
= gen_reg_rtx (Pmode
);
4475 /* Use load relative if possible.
4476 lgrl <target>, sym@GOTENT */
4477 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4478 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4479 new_rtx
= gen_const_mem (GET_MODE (reg
), new_rtx
);
4481 emit_move_insn (reg
, new_rtx
);
4484 else if (flag_pic
== 1)
4486 /* Assume GOT offset is a valid displacement operand (< 4k
4487 or < 512k with z990). This is handled the same way in
4488 both 31- and 64-bit code (@GOT).
4489 lg <target>, sym@GOT(r12) */
4491 if (reload_in_progress
|| reload_completed
)
4492 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4494 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
4495 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4496 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
4497 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4498 emit_move_insn (reg
, new_rtx
);
4501 else if (TARGET_CPU_ZARCH
)
4503 /* If the GOT offset might be >= 4k, we determine the position
4504 of the GOT entry via a PC-relative LARL (@GOTENT).
4505 larl temp, sym@GOTENT
4506 lg <target>, 0(temp) */
4508 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4510 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
4511 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
4513 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4514 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4515 emit_move_insn (temp
, new_rtx
);
4517 new_rtx
= gen_const_mem (Pmode
, temp
);
4518 emit_move_insn (reg
, new_rtx
);
4524 /* If the GOT offset might be >= 4k, we have to load it
4525 from the literal pool (@GOT).
4527 lg temp, lit-litbase(r13)
4528 lg <target>, 0(temp)
4529 lit: .long sym@GOT */
4531 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4533 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
4534 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
4536 if (reload_in_progress
|| reload_completed
)
4537 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4539 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
4540 addr
= gen_rtx_CONST (Pmode
, addr
);
4541 addr
= force_const_mem (Pmode
, addr
);
4542 emit_move_insn (temp
, addr
);
4544 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4545 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4546 emit_move_insn (reg
, new_rtx
);
4550 else if (GET_CODE (addr
) == UNSPEC
&& GET_CODE (addend
) == CONST_INT
)
4552 gcc_assert (XVECLEN (addr
, 0) == 1);
4553 switch (XINT (addr
, 1))
4555 /* These address symbols (or PLT slots) relative to the GOT
4556 (not GOT slots!). In general this will exceed the
4557 displacement range so these value belong into the literal
4561 new_rtx
= force_const_mem (Pmode
, orig
);
4564 /* For -fPIC the GOT size might exceed the displacement
4565 range so make sure the value is in the literal pool. */
4568 new_rtx
= force_const_mem (Pmode
, orig
);
4571 /* For @GOTENT larl is used. This is handled like local
4577 /* @PLT is OK as is on 64-bit, must be converted to
4578 GOT-relative @PLTOFF on 31-bit. */
4580 if (!TARGET_CPU_ZARCH
)
4582 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4584 if (reload_in_progress
|| reload_completed
)
4585 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4587 addr
= XVECEXP (addr
, 0, 0);
4588 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
4590 if (addend
!= const0_rtx
)
4591 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
4592 addr
= gen_rtx_CONST (Pmode
, addr
);
4593 addr
= force_const_mem (Pmode
, addr
);
4594 emit_move_insn (temp
, addr
);
4596 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4599 s390_load_address (reg
, new_rtx
);
4604 /* On 64 bit larl can be used. This case is handled like
4605 local symbol refs. */
4609 /* Everything else cannot happen. */
4614 else if (addend
!= const0_rtx
)
4616 /* Otherwise, compute the sum. */
4618 rtx base
= legitimize_pic_address (addr
, reg
);
4619 new_rtx
= legitimize_pic_address (addend
,
4620 base
== reg
? NULL_RTX
: reg
);
4621 if (GET_CODE (new_rtx
) == CONST_INT
)
4622 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
4625 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
4627 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
4628 new_rtx
= XEXP (new_rtx
, 1);
4630 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
4633 if (GET_CODE (new_rtx
) == CONST
)
4634 new_rtx
= XEXP (new_rtx
, 0);
4635 new_rtx
= force_operand (new_rtx
, 0);
4641 /* Load the thread pointer into a register. */
4644 s390_get_thread_pointer (void)
4646 rtx tp
= gen_reg_rtx (Pmode
);
4648 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
4649 mark_reg_pointer (tp
, BITS_PER_WORD
);
4654 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
4655 in s390_tls_symbol which always refers to __tls_get_offset.
4656 The returned offset is written to RESULT_REG and an USE rtx is
4657 generated for TLS_CALL. */
4659 static GTY(()) rtx s390_tls_symbol
;
4662 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
4667 emit_insn (s390_load_got ());
4669 if (!s390_tls_symbol
)
4670 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
4672 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
4673 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
4675 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
4676 RTL_CONST_CALL_P (insn
) = 1;
4679 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4680 this (thread-local) address. REG may be used as temporary. */
4683 legitimize_tls_address (rtx addr
, rtx reg
)
4685 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
4687 if (GET_CODE (addr
) == SYMBOL_REF
)
4688 switch (tls_symbolic_operand (addr
))
4690 case TLS_MODEL_GLOBAL_DYNAMIC
:
4692 r2
= gen_rtx_REG (Pmode
, 2);
4693 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
4694 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
4695 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4696 emit_move_insn (r2
, new_rtx
);
4697 s390_emit_tls_call_insn (r2
, tls_call
);
4698 insn
= get_insns ();
4701 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
4702 temp
= gen_reg_rtx (Pmode
);
4703 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
4705 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4708 s390_load_address (reg
, new_rtx
);
4713 case TLS_MODEL_LOCAL_DYNAMIC
:
4715 r2
= gen_rtx_REG (Pmode
, 2);
4716 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
4717 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
4718 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4719 emit_move_insn (r2
, new_rtx
);
4720 s390_emit_tls_call_insn (r2
, tls_call
);
4721 insn
= get_insns ();
4724 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
4725 temp
= gen_reg_rtx (Pmode
);
4726 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
4728 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4729 base
= gen_reg_rtx (Pmode
);
4730 s390_load_address (base
, new_rtx
);
4732 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
4733 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4734 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4735 temp
= gen_reg_rtx (Pmode
);
4736 emit_move_insn (temp
, new_rtx
);
4738 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
4741 s390_load_address (reg
, new_rtx
);
4746 case TLS_MODEL_INITIAL_EXEC
:
4749 /* Assume GOT offset < 4k. This is handled the same way
4750 in both 31- and 64-bit code. */
4752 if (reload_in_progress
|| reload_completed
)
4753 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4755 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
4756 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4757 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
4758 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4759 temp
= gen_reg_rtx (Pmode
);
4760 emit_move_insn (temp
, new_rtx
);
4762 else if (TARGET_CPU_ZARCH
)
4764 /* If the GOT offset might be >= 4k, we determine the position
4765 of the GOT entry via a PC-relative LARL. */
4767 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
4768 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4769 temp
= gen_reg_rtx (Pmode
);
4770 emit_move_insn (temp
, new_rtx
);
4772 new_rtx
= gen_const_mem (Pmode
, temp
);
4773 temp
= gen_reg_rtx (Pmode
);
4774 emit_move_insn (temp
, new_rtx
);
4778 /* If the GOT offset might be >= 4k, we have to load it
4779 from the literal pool. */
4781 if (reload_in_progress
|| reload_completed
)
4782 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4784 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
4785 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4786 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4787 temp
= gen_reg_rtx (Pmode
);
4788 emit_move_insn (temp
, new_rtx
);
4790 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4791 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4793 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
4794 temp
= gen_reg_rtx (Pmode
);
4795 emit_insn (gen_rtx_SET (temp
, new_rtx
));
4799 /* In position-dependent code, load the absolute address of
4800 the GOT entry from the literal pool. */
4802 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
4803 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4804 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4805 temp
= gen_reg_rtx (Pmode
);
4806 emit_move_insn (temp
, new_rtx
);
4809 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4810 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
4811 temp
= gen_reg_rtx (Pmode
);
4812 emit_insn (gen_rtx_SET (temp
, new_rtx
));
4815 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4818 s390_load_address (reg
, new_rtx
);
4823 case TLS_MODEL_LOCAL_EXEC
:
4824 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
4825 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4826 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4827 temp
= gen_reg_rtx (Pmode
);
4828 emit_move_insn (temp
, new_rtx
);
4830 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4833 s390_load_address (reg
, new_rtx
);
4842 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
4844 switch (XINT (XEXP (addr
, 0), 1))
4846 case UNSPEC_INDNTPOFF
:
4847 gcc_assert (TARGET_CPU_ZARCH
);
4856 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
4857 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
4859 new_rtx
= XEXP (XEXP (addr
, 0), 0);
4860 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
4861 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4863 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
4864 new_rtx
= plus_constant (Pmode
, new_rtx
,
4865 INTVAL (XEXP (XEXP (addr
, 0), 1)));
4866 new_rtx
= force_operand (new_rtx
, 0);
4870 gcc_unreachable (); /* for now ... */
4875 /* Emit insns making the address in operands[1] valid for a standard
4876 move to operands[0]. operands[1] is replaced by an address which
4877 should be used instead of the former RTX to emit the move
4881 emit_symbolic_move (rtx
*operands
)
4883 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
4885 if (GET_CODE (operands
[0]) == MEM
)
4886 operands
[1] = force_reg (Pmode
, operands
[1]);
4887 else if (TLS_SYMBOLIC_CONST (operands
[1]))
4888 operands
[1] = legitimize_tls_address (operands
[1], temp
);
4890 operands
[1] = legitimize_pic_address (operands
[1], temp
);
4893 /* Try machine-dependent ways of modifying an illegitimate address X
4894 to be legitimate. If we find one, return the new, valid address.
4896 OLDX is the address as it was before break_out_memory_refs was called.
4897 In some cases it is useful to look at this to decide what needs to be done.
4899 MODE is the mode of the operand pointed to by X.
4901 When -fpic is used, special handling is needed for symbolic references.
4902 See comments by legitimize_pic_address for details. */
4905 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4906 machine_mode mode ATTRIBUTE_UNUSED
)
4908 rtx constant_term
= const0_rtx
;
4910 if (TLS_SYMBOLIC_CONST (x
))
4912 x
= legitimize_tls_address (x
, 0);
4914 if (s390_legitimate_address_p (mode
, x
, FALSE
))
4917 else if (GET_CODE (x
) == PLUS
4918 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
4919 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
4925 if (SYMBOLIC_CONST (x
)
4926 || (GET_CODE (x
) == PLUS
4927 && (SYMBOLIC_CONST (XEXP (x
, 0))
4928 || SYMBOLIC_CONST (XEXP (x
, 1)))))
4929 x
= legitimize_pic_address (x
, 0);
4931 if (s390_legitimate_address_p (mode
, x
, FALSE
))
4935 x
= eliminate_constant_term (x
, &constant_term
);
4937 /* Optimize loading of large displacements by splitting them
4938 into the multiple of 4K and the rest; this allows the
4939 former to be CSE'd if possible.
4941 Don't do this if the displacement is added to a register
4942 pointing into the stack frame, as the offsets will
4943 change later anyway. */
4945 if (GET_CODE (constant_term
) == CONST_INT
4946 && !TARGET_LONG_DISPLACEMENT
4947 && !DISP_IN_RANGE (INTVAL (constant_term
))
4948 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
4950 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
4951 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
4953 rtx temp
= gen_reg_rtx (Pmode
);
4954 rtx val
= force_operand (GEN_INT (upper
), temp
);
4956 emit_move_insn (temp
, val
);
4958 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
4959 constant_term
= GEN_INT (lower
);
4962 if (GET_CODE (x
) == PLUS
)
4964 if (GET_CODE (XEXP (x
, 0)) == REG
)
4966 rtx temp
= gen_reg_rtx (Pmode
);
4967 rtx val
= force_operand (XEXP (x
, 1), temp
);
4969 emit_move_insn (temp
, val
);
4971 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
4974 else if (GET_CODE (XEXP (x
, 1)) == REG
)
4976 rtx temp
= gen_reg_rtx (Pmode
);
4977 rtx val
= force_operand (XEXP (x
, 0), temp
);
4979 emit_move_insn (temp
, val
);
4981 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
4985 if (constant_term
!= const0_rtx
)
4986 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
4991 /* Try a machine-dependent way of reloading an illegitimate address AD
4992 operand. If we find one, push the reload and return the new address.
4994 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4995 and TYPE is the reload type of the current reload. */
4998 legitimize_reload_address (rtx ad
, machine_mode mode ATTRIBUTE_UNUSED
,
4999 int opnum
, int type
)
5001 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
5004 if (GET_CODE (ad
) == PLUS
)
5006 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
5007 XEXP (ad
, 0), XEXP (ad
, 1));
5012 if (GET_CODE (ad
) == PLUS
5013 && GET_CODE (XEXP (ad
, 0)) == REG
5014 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
5015 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
5017 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
5018 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
5019 rtx cst
, tem
, new_rtx
;
5021 cst
= GEN_INT (upper
);
5022 if (!legitimate_reload_constant_p (cst
))
5023 cst
= force_const_mem (Pmode
, cst
);
5025 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
5026 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
5028 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
5029 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
5030 opnum
, (enum reload_type
) type
);
5037 /* Emit code to move LEN bytes from DST to SRC. */
5040 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
5042 /* When tuning for z10 or higher we rely on the Glibc functions to
5043 do the right thing. Only for constant lengths below 64k we will
5044 generate inline code. */
5045 if (s390_tune
>= PROCESSOR_2097_Z10
5046 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5049 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
5051 if (INTVAL (len
) > 0)
5052 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
5055 else if (TARGET_MVCLE
)
5057 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
5062 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
5063 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5064 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5065 rtx_code_label
*end_label
= gen_label_rtx ();
5068 mode
= GET_MODE (len
);
5069 if (mode
== VOIDmode
)
5072 dst_addr
= gen_reg_rtx (Pmode
);
5073 src_addr
= gen_reg_rtx (Pmode
);
5074 count
= gen_reg_rtx (mode
);
5075 blocks
= gen_reg_rtx (mode
);
5077 convert_move (count
, len
, 1);
5078 emit_cmp_and_jump_insns (count
, const0_rtx
,
5079 EQ
, NULL_RTX
, mode
, 1, end_label
);
5081 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5082 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
5083 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5084 src
= change_address (src
, VOIDmode
, src_addr
);
5086 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5089 emit_move_insn (count
, temp
);
5091 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5094 emit_move_insn (blocks
, temp
);
5096 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5097 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5099 emit_label (loop_start_label
);
5102 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
5106 /* Issue a read prefetch for the +3 cache line. */
5107 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
5108 const0_rtx
, const0_rtx
);
5109 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5110 emit_insn (prefetch
);
5112 /* Issue a write prefetch for the +3 cache line. */
5113 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
5114 const1_rtx
, const0_rtx
);
5115 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5116 emit_insn (prefetch
);
5119 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
5120 s390_load_address (dst_addr
,
5121 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5122 s390_load_address (src_addr
,
5123 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
5125 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5128 emit_move_insn (blocks
, temp
);
5130 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5131 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5133 emit_jump (loop_start_label
);
5134 emit_label (loop_end_label
);
5136 emit_insn (gen_movmem_short (dst
, src
,
5137 convert_to_mode (Pmode
, count
, 1)));
5138 emit_label (end_label
);
5143 /* Emit code to set LEN bytes at DST to VAL.
5144 Make use of clrmem if VAL is zero. */
5147 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
5149 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
5152 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
5154 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
5156 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
5157 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
5160 /* Initialize memory by storing the first byte. */
5161 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5163 if (INTVAL (len
) > 1)
5165 /* Initiate 1 byte overlap move.
5166 The first byte of DST is propagated through DSTP1.
5167 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
5168 DST is set to size 1 so the rest of the memory location
5169 does not count as source operand. */
5170 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
5171 set_mem_size (dst
, 1);
5173 emit_insn (gen_movmem_short (dstp1
, dst
,
5174 GEN_INT (INTVAL (len
) - 2)));
5179 else if (TARGET_MVCLE
)
5181 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
5182 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
5187 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
5188 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5189 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5190 rtx_code_label
*end_label
= gen_label_rtx ();
5193 mode
= GET_MODE (len
);
5194 if (mode
== VOIDmode
)
5197 dst_addr
= gen_reg_rtx (Pmode
);
5198 count
= gen_reg_rtx (mode
);
5199 blocks
= gen_reg_rtx (mode
);
5201 convert_move (count
, len
, 1);
5202 emit_cmp_and_jump_insns (count
, const0_rtx
,
5203 EQ
, NULL_RTX
, mode
, 1, end_label
);
5205 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5206 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5208 if (val
== const0_rtx
)
5209 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5213 dstp1
= adjust_address (dst
, VOIDmode
, 1);
5214 set_mem_size (dst
, 1);
5216 /* Initialize memory by storing the first byte. */
5217 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5219 /* If count is 1 we are done. */
5220 emit_cmp_and_jump_insns (count
, const1_rtx
,
5221 EQ
, NULL_RTX
, mode
, 1, end_label
);
5223 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
5227 emit_move_insn (count
, temp
);
5229 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5232 emit_move_insn (blocks
, temp
);
5234 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5235 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5237 emit_label (loop_start_label
);
5240 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
5242 /* Issue a write prefetch for the +4 cache line. */
5243 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
5245 const1_rtx
, const0_rtx
);
5246 emit_insn (prefetch
);
5247 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5250 if (val
== const0_rtx
)
5251 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
5253 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
5254 s390_load_address (dst_addr
,
5255 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5257 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5260 emit_move_insn (blocks
, temp
);
5262 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5263 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5265 emit_jump (loop_start_label
);
5266 emit_label (loop_end_label
);
5268 if (val
== const0_rtx
)
5269 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
5271 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
5272 emit_label (end_label
);
5276 /* Emit code to compare LEN bytes at OP0 with those at OP1,
5277 and return the result in TARGET. */
5280 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
5282 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
5285 /* When tuning for z10 or higher we rely on the Glibc functions to
5286 do the right thing. Only for constant lengths below 64k we will
5287 generate inline code. */
5288 if (s390_tune
>= PROCESSOR_2097_Z10
5289 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5292 /* As the result of CMPINT is inverted compared to what we need,
5293 we have to swap the operands. */
5294 tmp
= op0
; op0
= op1
; op1
= tmp
;
5296 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
5298 if (INTVAL (len
) > 0)
5300 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
5301 emit_insn (gen_cmpint (target
, ccreg
));
5304 emit_move_insn (target
, const0_rtx
);
5306 else if (TARGET_MVCLE
)
5308 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
5309 emit_insn (gen_cmpint (target
, ccreg
));
5313 rtx addr0
, addr1
, count
, blocks
, temp
;
5314 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5315 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5316 rtx_code_label
*end_label
= gen_label_rtx ();
5319 mode
= GET_MODE (len
);
5320 if (mode
== VOIDmode
)
5323 addr0
= gen_reg_rtx (Pmode
);
5324 addr1
= gen_reg_rtx (Pmode
);
5325 count
= gen_reg_rtx (mode
);
5326 blocks
= gen_reg_rtx (mode
);
5328 convert_move (count
, len
, 1);
5329 emit_cmp_and_jump_insns (count
, const0_rtx
,
5330 EQ
, NULL_RTX
, mode
, 1, end_label
);
5332 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
5333 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
5334 op0
= change_address (op0
, VOIDmode
, addr0
);
5335 op1
= change_address (op1
, VOIDmode
, addr1
);
5337 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5340 emit_move_insn (count
, temp
);
5342 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5345 emit_move_insn (blocks
, temp
);
5347 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5348 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5350 emit_label (loop_start_label
);
5353 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
5357 /* Issue a read prefetch for the +2 cache line of operand 1. */
5358 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
5359 const0_rtx
, const0_rtx
);
5360 emit_insn (prefetch
);
5361 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5363 /* Issue a read prefetch for the +2 cache line of operand 2. */
5364 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
5365 const0_rtx
, const0_rtx
);
5366 emit_insn (prefetch
);
5367 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5370 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
5371 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
5372 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5373 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
5374 temp
= gen_rtx_SET (pc_rtx
, temp
);
5375 emit_jump_insn (temp
);
5377 s390_load_address (addr0
,
5378 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
5379 s390_load_address (addr1
,
5380 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
5382 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5385 emit_move_insn (blocks
, temp
);
5387 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5388 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5390 emit_jump (loop_start_label
);
5391 emit_label (loop_end_label
);
5393 emit_insn (gen_cmpmem_short (op0
, op1
,
5394 convert_to_mode (Pmode
, count
, 1)));
5395 emit_label (end_label
);
5397 emit_insn (gen_cmpint (target
, ccreg
));
5402 /* Emit a conditional jump to LABEL for condition code mask MASK using
5403 comparsion operator COMPARISON. Return the emitted jump insn. */
5406 s390_emit_ccraw_jump (HOST_WIDE_INT mask
, enum rtx_code comparison
, rtx label
)
5410 gcc_assert (comparison
== EQ
|| comparison
== NE
);
5411 gcc_assert (mask
> 0 && mask
< 15);
5413 temp
= gen_rtx_fmt_ee (comparison
, VOIDmode
,
5414 gen_rtx_REG (CCRAWmode
, CC_REGNUM
), GEN_INT (mask
));
5415 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5416 gen_rtx_LABEL_REF (VOIDmode
, label
), pc_rtx
);
5417 temp
= gen_rtx_SET (pc_rtx
, temp
);
5418 return emit_jump_insn (temp
);
5421 /* Emit the instructions to implement strlen of STRING and store the
5422 result in TARGET. The string has the known ALIGNMENT. This
5423 version uses vector instructions and is therefore not appropriate
5424 for targets prior to z13. */
5427 s390_expand_vec_strlen (rtx target
, rtx string
, rtx alignment
)
5429 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
5430 int very_likely
= REG_BR_PROB_BASE
- 1;
5431 rtx highest_index_to_load_reg
= gen_reg_rtx (Pmode
);
5432 rtx str_reg
= gen_reg_rtx (V16QImode
);
5433 rtx str_addr_base_reg
= gen_reg_rtx (Pmode
);
5434 rtx str_idx_reg
= gen_reg_rtx (Pmode
);
5435 rtx result_reg
= gen_reg_rtx (V16QImode
);
5436 rtx is_aligned_label
= gen_label_rtx ();
5437 rtx into_loop_label
= NULL_RTX
;
5438 rtx loop_start_label
= gen_label_rtx ();
5440 rtx len
= gen_reg_rtx (QImode
);
5443 s390_load_address (str_addr_base_reg
, XEXP (string
, 0));
5444 emit_move_insn (str_idx_reg
, const0_rtx
);
5446 if (INTVAL (alignment
) < 16)
5448 /* Check whether the address happens to be aligned properly so
5449 jump directly to the aligned loop. */
5450 emit_cmp_and_jump_insns (gen_rtx_AND (Pmode
,
5451 str_addr_base_reg
, GEN_INT (15)),
5452 const0_rtx
, EQ
, NULL_RTX
,
5453 Pmode
, 1, is_aligned_label
);
5455 temp
= gen_reg_rtx (Pmode
);
5456 temp
= expand_binop (Pmode
, and_optab
, str_addr_base_reg
,
5457 GEN_INT (15), temp
, 1, OPTAB_DIRECT
);
5458 gcc_assert (REG_P (temp
));
5459 highest_index_to_load_reg
=
5460 expand_binop (Pmode
, sub_optab
, GEN_INT (15), temp
,
5461 highest_index_to_load_reg
, 1, OPTAB_DIRECT
);
5462 gcc_assert (REG_P (highest_index_to_load_reg
));
5463 emit_insn (gen_vllv16qi (str_reg
,
5464 convert_to_mode (SImode
, highest_index_to_load_reg
, 1),
5465 gen_rtx_MEM (BLKmode
, str_addr_base_reg
)));
5467 into_loop_label
= gen_label_rtx ();
5468 s390_emit_jump (into_loop_label
, NULL_RTX
);
5472 emit_label (is_aligned_label
);
5473 LABEL_NUSES (is_aligned_label
) = INTVAL (alignment
) < 16 ? 2 : 1;
5475 /* Reaching this point we are only performing 16 bytes aligned
5477 emit_move_insn (highest_index_to_load_reg
, GEN_INT (15));
5479 emit_label (loop_start_label
);
5480 LABEL_NUSES (loop_start_label
) = 1;
5482 /* Load 16 bytes of the string into VR. */
5483 emit_move_insn (str_reg
,
5484 gen_rtx_MEM (V16QImode
,
5485 gen_rtx_PLUS (Pmode
, str_idx_reg
,
5486 str_addr_base_reg
)));
5487 if (into_loop_label
!= NULL_RTX
)
5489 emit_label (into_loop_label
);
5490 LABEL_NUSES (into_loop_label
) = 1;
5493 /* Increment string index by 16 bytes. */
5494 expand_binop (Pmode
, add_optab
, str_idx_reg
, GEN_INT (16),
5495 str_idx_reg
, 1, OPTAB_DIRECT
);
5497 emit_insn (gen_vec_vfenesv16qi (result_reg
, str_reg
, str_reg
,
5498 GEN_INT (VSTRING_FLAG_ZS
| VSTRING_FLAG_CS
)));
5500 add_int_reg_note (s390_emit_ccraw_jump (8, NE
, loop_start_label
),
5501 REG_BR_PROB
, very_likely
);
5502 emit_insn (gen_vec_extractv16qi (len
, result_reg
, GEN_INT (7)));
5504 /* If the string pointer wasn't aligned we have loaded less then 16
5505 bytes and the remaining bytes got filled with zeros (by vll).
5506 Now we have to check whether the resulting index lies within the
5507 bytes actually part of the string. */
5509 cond
= s390_emit_compare (GT
, convert_to_mode (Pmode
, len
, 1),
5510 highest_index_to_load_reg
);
5511 s390_load_address (highest_index_to_load_reg
,
5512 gen_rtx_PLUS (Pmode
, highest_index_to_load_reg
,
5515 emit_insn (gen_movdicc (str_idx_reg
, cond
,
5516 highest_index_to_load_reg
, str_idx_reg
));
5518 emit_insn (gen_movsicc (str_idx_reg
, cond
,
5519 highest_index_to_load_reg
, str_idx_reg
));
5521 add_int_reg_note (s390_emit_jump (is_aligned_label
, cond
), REG_BR_PROB
,
5524 expand_binop (Pmode
, add_optab
, str_idx_reg
,
5525 GEN_INT (-16), str_idx_reg
, 1, OPTAB_DIRECT
);
5526 /* FIXME: len is already zero extended - so avoid the llgcr emitted
5528 temp
= expand_binop (Pmode
, add_optab
, str_idx_reg
,
5529 convert_to_mode (Pmode
, len
, 1),
5530 target
, 1, OPTAB_DIRECT
);
5532 emit_move_insn (target
, temp
);
5535 /* Expand conditional increment or decrement using alc/slb instructions.
5536 Should generate code setting DST to either SRC or SRC + INCREMENT,
5537 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
5538 Returns true if successful, false otherwise.
5540 That makes it possible to implement some if-constructs without jumps e.g.:
5541 (borrow = CC0 | CC1 and carry = CC2 | CC3)
5542 unsigned int a, b, c;
5543 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
5544 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
5545 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
5546 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
5548 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
5549 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
5550 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
5551 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
5552 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
5555 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
5556 rtx dst
, rtx src
, rtx increment
)
5558 machine_mode cmp_mode
;
5559 machine_mode cc_mode
;
5565 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
5566 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
5568 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
5569 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
5574 /* Try ADD LOGICAL WITH CARRY. */
5575 if (increment
== const1_rtx
)
5577 /* Determine CC mode to use. */
5578 if (cmp_code
== EQ
|| cmp_code
== NE
)
5580 if (cmp_op1
!= const0_rtx
)
5582 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
5583 NULL_RTX
, 0, OPTAB_WIDEN
);
5584 cmp_op1
= const0_rtx
;
5587 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
5590 if (cmp_code
== LTU
|| cmp_code
== LEU
)
5595 cmp_code
= swap_condition (cmp_code
);
5612 /* Emit comparison instruction pattern. */
5613 if (!register_operand (cmp_op0
, cmp_mode
))
5614 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
5616 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
5617 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
5618 /* We use insn_invalid_p here to add clobbers if required. */
5619 ret
= insn_invalid_p (emit_insn (insn
), false);
5622 /* Emit ALC instruction pattern. */
5623 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
5624 gen_rtx_REG (cc_mode
, CC_REGNUM
),
5627 if (src
!= const0_rtx
)
5629 if (!register_operand (src
, GET_MODE (dst
)))
5630 src
= force_reg (GET_MODE (dst
), src
);
5632 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
5633 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
5636 p
= rtvec_alloc (2);
5638 gen_rtx_SET (dst
, op_res
);
5640 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5641 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
5646 /* Try SUBTRACT LOGICAL WITH BORROW. */
5647 if (increment
== constm1_rtx
)
5649 /* Determine CC mode to use. */
5650 if (cmp_code
== EQ
|| cmp_code
== NE
)
5652 if (cmp_op1
!= const0_rtx
)
5654 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
5655 NULL_RTX
, 0, OPTAB_WIDEN
);
5656 cmp_op1
= const0_rtx
;
5659 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
5662 if (cmp_code
== GTU
|| cmp_code
== GEU
)
5667 cmp_code
= swap_condition (cmp_code
);
5684 /* Emit comparison instruction pattern. */
5685 if (!register_operand (cmp_op0
, cmp_mode
))
5686 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
5688 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
5689 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
5690 /* We use insn_invalid_p here to add clobbers if required. */
5691 ret
= insn_invalid_p (emit_insn (insn
), false);
5694 /* Emit SLB instruction pattern. */
5695 if (!register_operand (src
, GET_MODE (dst
)))
5696 src
= force_reg (GET_MODE (dst
), src
);
5698 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
5699 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
5700 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
5701 gen_rtx_REG (cc_mode
, CC_REGNUM
),
5703 p
= rtvec_alloc (2);
5705 gen_rtx_SET (dst
, op_res
);
5707 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5708 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
5716 /* Expand code for the insv template. Return true if successful. */
5719 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
5721 int bitsize
= INTVAL (op1
);
5722 int bitpos
= INTVAL (op2
);
5723 machine_mode mode
= GET_MODE (dest
);
5725 int smode_bsize
, mode_bsize
;
5728 if (bitsize
+ bitpos
> GET_MODE_BITSIZE (mode
))
5731 /* Generate INSERT IMMEDIATE (IILL et al). */
5732 /* (set (ze (reg)) (const_int)). */
5734 && register_operand (dest
, word_mode
)
5735 && (bitpos
% 16) == 0
5736 && (bitsize
% 16) == 0
5737 && const_int_operand (src
, VOIDmode
))
5739 HOST_WIDE_INT val
= INTVAL (src
);
5740 int regpos
= bitpos
+ bitsize
;
5742 while (regpos
> bitpos
)
5744 machine_mode putmode
;
5747 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
5752 putsize
= GET_MODE_BITSIZE (putmode
);
5754 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
5757 gen_int_mode (val
, putmode
));
5760 gcc_assert (regpos
== bitpos
);
5764 smode
= smallest_mode_for_size (bitsize
, MODE_INT
);
5765 smode_bsize
= GET_MODE_BITSIZE (smode
);
5766 mode_bsize
= GET_MODE_BITSIZE (mode
);
5768 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
5770 && (bitsize
% BITS_PER_UNIT
) == 0
5772 && (register_operand (src
, word_mode
)
5773 || const_int_operand (src
, VOIDmode
)))
5775 /* Emit standard pattern if possible. */
5776 if (smode_bsize
== bitsize
)
5778 emit_move_insn (adjust_address (dest
, smode
, 0),
5779 gen_lowpart (smode
, src
));
5783 /* (set (ze (mem)) (const_int)). */
5784 else if (const_int_operand (src
, VOIDmode
))
5786 int size
= bitsize
/ BITS_PER_UNIT
;
5787 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
),
5789 UNITS_PER_WORD
- size
);
5791 dest
= adjust_address (dest
, BLKmode
, 0);
5792 set_mem_size (dest
, size
);
5793 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
5797 /* (set (ze (mem)) (reg)). */
5798 else if (register_operand (src
, word_mode
))
5801 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
5805 /* Emit st,stcmh sequence. */
5806 int stcmh_width
= bitsize
- 32;
5807 int size
= stcmh_width
/ BITS_PER_UNIT
;
5809 emit_move_insn (adjust_address (dest
, SImode
, size
),
5810 gen_lowpart (SImode
, src
));
5811 set_mem_size (dest
, size
);
5812 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
5813 GEN_INT (stcmh_width
),
5815 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT (32)));
5821 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
5822 if ((bitpos
% BITS_PER_UNIT
) == 0
5823 && (bitsize
% BITS_PER_UNIT
) == 0
5824 && (bitpos
& 32) == ((bitpos
+ bitsize
- 1) & 32)
5826 && (mode
== DImode
|| mode
== SImode
)
5827 && register_operand (dest
, mode
))
5829 /* Emit a strict_low_part pattern if possible. */
5830 if (smode_bsize
== bitsize
&& bitpos
== mode_bsize
- smode_bsize
)
5832 op
= gen_rtx_STRICT_LOW_PART (VOIDmode
, gen_lowpart (smode
, dest
));
5833 op
= gen_rtx_SET (op
, gen_lowpart (smode
, src
));
5834 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5835 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
5839 /* ??? There are more powerful versions of ICM that are not
5840 completely represented in the md file. */
5843 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
5844 if (TARGET_Z10
&& (mode
== DImode
|| mode
== SImode
))
5846 machine_mode mode_s
= GET_MODE (src
);
5848 if (mode_s
== VOIDmode
)
5850 /* Assume const_int etc already in the proper mode. */
5851 src
= force_reg (mode
, src
);
5853 else if (mode_s
!= mode
)
5855 gcc_assert (GET_MODE_BITSIZE (mode_s
) >= bitsize
);
5856 src
= force_reg (mode_s
, src
);
5857 src
= gen_lowpart (mode
, src
);
5860 op
= gen_rtx_ZERO_EXTRACT (mode
, dest
, op1
, op2
),
5861 op
= gen_rtx_SET (op
, src
);
5865 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5866 op
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
));
5876 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
5877 register that holds VAL of mode MODE shifted by COUNT bits. */
5880 s390_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
5882 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
5883 NULL_RTX
, 1, OPTAB_DIRECT
);
5884 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
5885 NULL_RTX
, 1, OPTAB_DIRECT
);
5888 /* Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store
5889 the result in TARGET. */
5892 s390_expand_vec_compare (rtx target
, enum rtx_code cond
,
5893 rtx cmp_op1
, rtx cmp_op2
)
5895 machine_mode mode
= GET_MODE (target
);
5896 bool neg_p
= false, swap_p
= false;
5899 if (GET_MODE (cmp_op1
) == V2DFmode
)
5903 /* NE a != b -> !(a == b) */
5904 case NE
: cond
= EQ
; neg_p
= true; break;
5905 /* UNGT a u> b -> !(b >= a) */
5906 case UNGT
: cond
= GE
; neg_p
= true; swap_p
= true; break;
5907 /* UNGE a u>= b -> !(b > a) */
5908 case UNGE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
5909 /* LE: a <= b -> b >= a */
5910 case LE
: cond
= GE
; swap_p
= true; break;
5911 /* UNLE: a u<= b -> !(a > b) */
5912 case UNLE
: cond
= GT
; neg_p
= true; break;
5913 /* LT: a < b -> b > a */
5914 case LT
: cond
= GT
; swap_p
= true; break;
5915 /* UNLT: a u< b -> !(a >= b) */
5916 case UNLT
: cond
= GE
; neg_p
= true; break;
5918 emit_insn (gen_vec_cmpuneqv2df (target
, cmp_op1
, cmp_op2
));
5921 emit_insn (gen_vec_cmpltgtv2df (target
, cmp_op1
, cmp_op2
));
5924 emit_insn (gen_vec_orderedv2df (target
, cmp_op1
, cmp_op2
));
5927 emit_insn (gen_vec_unorderedv2df (target
, cmp_op1
, cmp_op2
));
5936 /* NE: a != b -> !(a == b) */
5937 case NE
: cond
= EQ
; neg_p
= true; break;
5938 /* GE: a >= b -> !(b > a) */
5939 case GE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
5940 /* GEU: a >= b -> !(b > a) */
5941 case GEU
: cond
= GTU
; neg_p
= true; swap_p
= true; break;
5942 /* LE: a <= b -> !(a > b) */
5943 case LE
: cond
= GT
; neg_p
= true; break;
5944 /* LEU: a <= b -> !(a > b) */
5945 case LEU
: cond
= GTU
; neg_p
= true; break;
5946 /* LT: a < b -> b > a */
5947 case LT
: cond
= GT
; swap_p
= true; break;
5948 /* LTU: a < b -> b > a */
5949 case LTU
: cond
= GTU
; swap_p
= true; break;
5956 tmp
= cmp_op1
; cmp_op1
= cmp_op2
; cmp_op2
= tmp
;
5959 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (cond
,
5961 cmp_op1
, cmp_op2
)));
5963 emit_insn (gen_rtx_SET (target
, gen_rtx_NOT (mode
, target
)));
5966 /* Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into
5967 TARGET if either all (ALL_P is true) or any (ALL_P is false) of the
5968 elements in CMP1 and CMP2 fulfill the comparison. */
5970 s390_expand_vec_compare_cc (rtx target
, enum rtx_code code
,
5971 rtx cmp1
, rtx cmp2
, bool all_p
)
5973 enum rtx_code new_code
= code
;
5974 machine_mode cmp_mode
, full_cmp_mode
, scratch_mode
;
5975 rtx tmp_reg
= gen_reg_rtx (SImode
);
5976 bool swap_p
= false;
5978 if (GET_MODE_CLASS (GET_MODE (cmp1
)) == MODE_VECTOR_INT
)
5982 case EQ
: cmp_mode
= CCVEQmode
; break;
5983 case NE
: cmp_mode
= CCVEQmode
; break;
5984 case GT
: cmp_mode
= CCVHmode
; break;
5985 case GE
: cmp_mode
= CCVHmode
; new_code
= LE
; swap_p
= true; break;
5986 case LT
: cmp_mode
= CCVHmode
; new_code
= GT
; swap_p
= true; break;
5987 case LE
: cmp_mode
= CCVHmode
; new_code
= LE
; break;
5988 case GTU
: cmp_mode
= CCVHUmode
; break;
5989 case GEU
: cmp_mode
= CCVHUmode
; new_code
= LEU
; swap_p
= true; break;
5990 case LTU
: cmp_mode
= CCVHUmode
; new_code
= GTU
; swap_p
= true; break;
5991 case LEU
: cmp_mode
= CCVHUmode
; new_code
= LEU
; break;
5992 default: gcc_unreachable ();
5994 scratch_mode
= GET_MODE (cmp1
);
5996 else if (GET_MODE (cmp1
) == V2DFmode
)
6000 case EQ
: cmp_mode
= CCVEQmode
; break;
6001 case NE
: cmp_mode
= CCVEQmode
; break;
6002 case GT
: cmp_mode
= CCVFHmode
; break;
6003 case GE
: cmp_mode
= CCVFHEmode
; break;
6004 case UNLE
: cmp_mode
= CCVFHmode
; break;
6005 case UNLT
: cmp_mode
= CCVFHEmode
; break;
6006 case LT
: cmp_mode
= CCVFHmode
; new_code
= GT
; swap_p
= true; break;
6007 case LE
: cmp_mode
= CCVFHEmode
; new_code
= GE
; swap_p
= true; break;
6008 default: gcc_unreachable ();
6010 scratch_mode
= V2DImode
;
6018 case CCVEQmode
: full_cmp_mode
= CCVEQANYmode
; break;
6019 case CCVHmode
: full_cmp_mode
= CCVHANYmode
; break;
6020 case CCVHUmode
: full_cmp_mode
= CCVHUANYmode
; break;
6021 case CCVFHmode
: full_cmp_mode
= CCVFHANYmode
; break;
6022 case CCVFHEmode
: full_cmp_mode
= CCVFHEANYmode
; break;
6023 default: gcc_unreachable ();
6026 /* The modes without ANY match the ALL modes. */
6027 full_cmp_mode
= cmp_mode
;
6036 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6037 gen_rtvec (2, gen_rtx_SET (
6038 gen_rtx_REG (cmp_mode
, CC_REGNUM
),
6039 gen_rtx_COMPARE (cmp_mode
, cmp1
, cmp2
)),
6040 gen_rtx_CLOBBER (VOIDmode
,
6041 gen_rtx_SCRATCH (scratch_mode
)))));
6042 emit_move_insn (target
, const0_rtx
);
6043 emit_move_insn (tmp_reg
, const1_rtx
);
6045 emit_move_insn (target
,
6046 gen_rtx_IF_THEN_ELSE (SImode
,
6047 gen_rtx_fmt_ee (new_code
, VOIDmode
,
6048 gen_rtx_REG (full_cmp_mode
, CC_REGNUM
),
6053 /* Generate a vector comparison expression loading either elements of
6054 THEN or ELS into TARGET depending on the comparison COND of CMP_OP1
6058 s390_expand_vcond (rtx target
, rtx then
, rtx els
,
6059 enum rtx_code cond
, rtx cmp_op1
, rtx cmp_op2
)
6062 machine_mode result_mode
;
6065 /* We always use an integral type vector to hold the comparison
6067 result_mode
= GET_MODE (cmp_op1
) == V2DFmode
? V2DImode
: GET_MODE (cmp_op1
);
6068 result_target
= gen_reg_rtx (result_mode
);
6070 /* Alternatively this could be done by reload by lowering the cmp*
6071 predicates. But it appears to be better for scheduling etc. to
6072 have that in early. */
6073 if (!REG_P (cmp_op1
))
6074 cmp_op1
= force_reg (GET_MODE (target
), cmp_op1
);
6076 if (!REG_P (cmp_op2
))
6077 cmp_op2
= force_reg (GET_MODE (target
), cmp_op2
);
6079 s390_expand_vec_compare (result_target
, cond
,
6082 /* If the results are supposed to be either -1 or 0 we are done
6083 since this is what our compare instructions generate anyway. */
6084 if (constm1_operand (then
, GET_MODE (then
))
6085 && const0_operand (els
, GET_MODE (els
)))
6087 emit_move_insn (target
, gen_rtx_SUBREG (GET_MODE (target
),
6092 /* Otherwise we will do a vsel afterwards. */
6093 /* This gets triggered e.g.
6094 with gcc.c-torture/compile/pr53410-1.c */
6096 then
= force_reg (GET_MODE (target
), then
);
6099 els
= force_reg (GET_MODE (target
), els
);
6101 tmp
= gen_rtx_fmt_ee (EQ
, VOIDmode
,
6103 CONST0_RTX (result_mode
));
6105 /* We compared the result against zero above so we have to swap then
6107 tmp
= gen_rtx_IF_THEN_ELSE (GET_MODE (target
), tmp
, els
, then
);
6109 gcc_assert (GET_MODE (target
) == GET_MODE (then
));
6110 emit_insn (gen_rtx_SET (target
, tmp
));
6113 /* Emit the RTX necessary to initialize the vector TARGET with values
6116 s390_expand_vec_init (rtx target
, rtx vals
)
6118 machine_mode mode
= GET_MODE (target
);
6119 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6120 int n_elts
= GET_MODE_NUNITS (mode
);
6121 bool all_same
= true, all_regs
= true, all_const_int
= true;
6125 for (i
= 0; i
< n_elts
; ++i
)
6127 x
= XVECEXP (vals
, 0, i
);
6129 if (!CONST_INT_P (x
))
6130 all_const_int
= false;
6132 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6139 /* Use vector gen mask or vector gen byte mask if possible. */
6140 if (all_same
&& all_const_int
6141 && (XVECEXP (vals
, 0, 0) == const0_rtx
6142 || s390_contiguous_bitmask_vector_p (XVECEXP (vals
, 0, 0),
6144 || s390_bytemask_vector_p (XVECEXP (vals
, 0, 0), NULL
)))
6146 emit_insn (gen_rtx_SET (target
,
6147 gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0))));
6153 emit_insn (gen_rtx_SET (target
,
6154 gen_rtx_VEC_DUPLICATE (mode
,
6155 XVECEXP (vals
, 0, 0))));
6159 if (all_regs
&& REG_P (target
) && n_elts
== 2 && inner_mode
== DImode
)
6161 /* Use vector load pair. */
6162 emit_insn (gen_rtx_SET (target
,
6163 gen_rtx_VEC_CONCAT (mode
,
6164 XVECEXP (vals
, 0, 0),
6165 XVECEXP (vals
, 0, 1))));
6169 /* We are about to set the vector elements one by one. Zero out the
6170 full register first in order to help the data flow framework to
6171 detect it as full VR set. */
6172 emit_insn (gen_rtx_SET (target
, CONST0_RTX (mode
)));
6174 /* Unfortunately the vec_init expander is not allowed to fail. So
6175 we have to implement the fallback ourselves. */
6176 for (i
= 0; i
< n_elts
; i
++)
6177 emit_insn (gen_rtx_SET (target
,
6178 gen_rtx_UNSPEC (mode
,
6179 gen_rtvec (3, XVECEXP (vals
, 0, i
),
6180 GEN_INT (i
), target
),
6184 /* Structure to hold the initial parameters for a compare_and_swap operation
6185 in HImode and QImode. */
6187 struct alignment_context
6189 rtx memsi
; /* SI aligned memory location. */
6190 rtx shift
; /* Bit offset with regard to lsb. */
6191 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
6192 rtx modemaski
; /* ~modemask */
6193 bool aligned
; /* True if memory is aligned, false else. */
6196 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
6197 structure AC for transparent simplifying, if the memory alignment is known
6198 to be at least 32bit. MEM is the memory location for the actual operation
6199 and MODE its mode. */
6202 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
6205 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
6206 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
6209 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
6212 /* Alignment is unknown. */
6213 rtx byteoffset
, addr
, align
;
6215 /* Force the address into a register. */
6216 addr
= force_reg (Pmode
, XEXP (mem
, 0));
6218 /* Align it to SImode. */
6219 align
= expand_simple_binop (Pmode
, AND
, addr
,
6220 GEN_INT (-GET_MODE_SIZE (SImode
)),
6221 NULL_RTX
, 1, OPTAB_DIRECT
);
6223 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
6224 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
6225 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
6226 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
6228 /* Calculate shiftcount. */
6229 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
6230 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
6231 NULL_RTX
, 1, OPTAB_DIRECT
);
6232 /* As we already have some offset, evaluate the remaining distance. */
6233 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
6234 NULL_RTX
, 1, OPTAB_DIRECT
);
6237 /* Shift is the byte count, but we need the bitcount. */
6238 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
, GEN_INT (3),
6239 NULL_RTX
, 1, OPTAB_DIRECT
);
6241 /* Calculate masks. */
6242 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
6243 GEN_INT (GET_MODE_MASK (mode
)),
6244 ac
->shift
, NULL_RTX
, 1, OPTAB_DIRECT
);
6245 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
,
6249 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
6250 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
6251 perform the merge in SEQ2. */
6254 s390_two_part_insv (struct alignment_context
*ac
, rtx
*seq1
, rtx
*seq2
,
6255 machine_mode mode
, rtx val
, rtx ins
)
6262 tmp
= copy_to_mode_reg (SImode
, val
);
6263 if (s390_expand_insv (tmp
, GEN_INT (GET_MODE_BITSIZE (mode
)),
6267 *seq2
= get_insns ();
6274 /* Failed to use insv. Generate a two part shift and mask. */
6276 tmp
= s390_expand_mask_and_shift (ins
, mode
, ac
->shift
);
6277 *seq1
= get_insns ();
6281 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
, NULL_RTX
, 1, OPTAB_DIRECT
);
6282 *seq2
= get_insns ();
6288 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
6289 the memory location, CMP the old value to compare MEM with and NEW_RTX the
6290 value to set if CMP == MEM. */
6293 s390_expand_cs_hqi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
6294 rtx cmp
, rtx new_rtx
, bool is_weak
)
6296 struct alignment_context ac
;
6297 rtx cmpv
, newv
, val
, cc
, seq0
, seq1
, seq2
, seq3
;
6298 rtx res
= gen_reg_rtx (SImode
);
6299 rtx_code_label
*csloop
= NULL
, *csend
= NULL
;
6301 gcc_assert (MEM_P (mem
));
6303 init_alignment_context (&ac
, mem
, mode
);
6305 /* Load full word. Subsequent loads are performed by CS. */
6306 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
6307 NULL_RTX
, 1, OPTAB_DIRECT
);
6309 /* Prepare insertions of cmp and new_rtx into the loaded value. When
6310 possible, we try to use insv to make this happen efficiently. If
6311 that fails we'll generate code both inside and outside the loop. */
6312 cmpv
= s390_two_part_insv (&ac
, &seq0
, &seq2
, mode
, val
, cmp
);
6313 newv
= s390_two_part_insv (&ac
, &seq1
, &seq3
, mode
, val
, new_rtx
);
6320 /* Start CS loop. */
6323 /* Begin assuming success. */
6324 emit_move_insn (btarget
, const1_rtx
);
6326 csloop
= gen_label_rtx ();
6327 csend
= gen_label_rtx ();
6328 emit_label (csloop
);
6331 /* val = "<mem>00..0<mem>"
6332 * cmp = "00..0<cmp>00..0"
6333 * new = "00..0<new>00..0"
6339 cc
= s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
, cmpv
, newv
);
6341 emit_insn (gen_cstorecc4 (btarget
, cc
, XEXP (cc
, 0), XEXP (cc
, 1)));
6346 /* Jump to end if we're done (likely?). */
6347 s390_emit_jump (csend
, cc
);
6349 /* Check for changes outside mode, and loop internal if so.
6350 Arrange the moves so that the compare is adjacent to the
6351 branch so that we can generate CRJ. */
6352 tmp
= copy_to_reg (val
);
6353 force_expand_binop (SImode
, and_optab
, res
, ac
.modemaski
, val
,
6355 cc
= s390_emit_compare (NE
, val
, tmp
);
6356 s390_emit_jump (csloop
, cc
);
6359 emit_move_insn (btarget
, const0_rtx
);
6363 /* Return the correct part of the bitfield. */
6364 convert_move (vtarget
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
6365 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
6368 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
6369 and VAL the value to play with. If AFTER is true then store the value
6370 MEM holds after the operation, if AFTER is false then store the value MEM
6371 holds before the operation. If TARGET is zero then discard that value, else
6372 store it to TARGET. */
6375 s390_expand_atomic (machine_mode mode
, enum rtx_code code
,
6376 rtx target
, rtx mem
, rtx val
, bool after
)
6378 struct alignment_context ac
;
6380 rtx new_rtx
= gen_reg_rtx (SImode
);
6381 rtx orig
= gen_reg_rtx (SImode
);
6382 rtx_code_label
*csloop
= gen_label_rtx ();
6384 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
6385 gcc_assert (MEM_P (mem
));
6387 init_alignment_context (&ac
, mem
, mode
);
6389 /* Shift val to the correct bit positions.
6390 Preserve "icm", but prevent "ex icm". */
6391 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
6392 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
6394 /* Further preparation insns. */
6395 if (code
== PLUS
|| code
== MINUS
)
6396 emit_move_insn (orig
, val
);
6397 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
6398 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
6399 NULL_RTX
, 1, OPTAB_DIRECT
);
6401 /* Load full word. Subsequent loads are performed by CS. */
6402 cmp
= force_reg (SImode
, ac
.memsi
);
6404 /* Start CS loop. */
6405 emit_label (csloop
);
6406 emit_move_insn (new_rtx
, cmp
);
6408 /* Patch new with val at correct position. */
6413 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
6414 NULL_RTX
, 1, OPTAB_DIRECT
);
6415 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
6416 NULL_RTX
, 1, OPTAB_DIRECT
);
6419 if (ac
.aligned
&& MEM_P (val
))
6420 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
6424 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
6425 NULL_RTX
, 1, OPTAB_DIRECT
);
6426 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
6427 NULL_RTX
, 1, OPTAB_DIRECT
);
6433 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
6434 NULL_RTX
, 1, OPTAB_DIRECT
);
6436 case MULT
: /* NAND */
6437 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
6438 NULL_RTX
, 1, OPTAB_DIRECT
);
6439 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
6440 NULL_RTX
, 1, OPTAB_DIRECT
);
6446 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
6447 ac
.memsi
, cmp
, new_rtx
));
6449 /* Return the correct part of the bitfield. */
6451 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
6452 after
? new_rtx
: cmp
, ac
.shift
,
6453 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
6456 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6457 We need to emit DTP-relative relocations. */
6459 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6462 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6467 fputs ("\t.long\t", file
);
6470 fputs ("\t.quad\t", file
);
6475 output_addr_const (file
, x
);
6476 fputs ("@DTPOFF", file
);
6479 /* Return the proper mode for REGNO being represented in the dwarf
6482 s390_dwarf_frame_reg_mode (int regno
)
6484 machine_mode save_mode
= default_dwarf_frame_reg_mode (regno
);
6486 /* The rightmost 64 bits of vector registers are call-clobbered. */
6487 if (GET_MODE_SIZE (save_mode
) > 8)
6493 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
6494 /* Implement TARGET_MANGLE_TYPE. */
6497 s390_mangle_type (const_tree type
)
6499 type
= TYPE_MAIN_VARIANT (type
);
6501 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
6502 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
6505 if (type
== s390_builtin_types
[BT_BV16QI
]) return "U6__boolc";
6506 if (type
== s390_builtin_types
[BT_BV8HI
]) return "U6__bools";
6507 if (type
== s390_builtin_types
[BT_BV4SI
]) return "U6__booli";
6508 if (type
== s390_builtin_types
[BT_BV2DI
]) return "U6__booll";
6510 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
6511 && TARGET_LONG_DOUBLE_128
)
6514 /* For all other types, use normal C++ mangling. */
6519 /* In the name of slightly smaller debug output, and to cater to
6520 general assembler lossage, recognize various UNSPEC sequences
6521 and turn them back into a direct symbol reference. */
6524 s390_delegitimize_address (rtx orig_x
)
6528 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6531 /* Extract the symbol ref from:
6532 (plus:SI (reg:SI 12 %r12)
6533 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
6534 UNSPEC_GOTOFF/PLTOFF)))
6536 (plus:SI (reg:SI 12 %r12)
6537 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
6538 UNSPEC_GOTOFF/PLTOFF)
6539 (const_int 4 [0x4])))) */
6540 if (GET_CODE (x
) == PLUS
6541 && REG_P (XEXP (x
, 0))
6542 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
6543 && GET_CODE (XEXP (x
, 1)) == CONST
)
6545 HOST_WIDE_INT offset
= 0;
6547 /* The const operand. */
6548 y
= XEXP (XEXP (x
, 1), 0);
6550 if (GET_CODE (y
) == PLUS
6551 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
6553 offset
= INTVAL (XEXP (y
, 1));
6557 if (GET_CODE (y
) == UNSPEC
6558 && (XINT (y
, 1) == UNSPEC_GOTOFF
6559 || XINT (y
, 1) == UNSPEC_PLTOFF
))
6560 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
6563 if (GET_CODE (x
) != MEM
)
6567 if (GET_CODE (x
) == PLUS
6568 && GET_CODE (XEXP (x
, 1)) == CONST
6569 && GET_CODE (XEXP (x
, 0)) == REG
6570 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
6572 y
= XEXP (XEXP (x
, 1), 0);
6573 if (GET_CODE (y
) == UNSPEC
6574 && XINT (y
, 1) == UNSPEC_GOT
)
6575 y
= XVECEXP (y
, 0, 0);
6579 else if (GET_CODE (x
) == CONST
)
6581 /* Extract the symbol ref from:
6582 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
6583 UNSPEC_PLT/GOTENT))) */
6586 if (GET_CODE (y
) == UNSPEC
6587 && (XINT (y
, 1) == UNSPEC_GOTENT
6588 || XINT (y
, 1) == UNSPEC_PLT
))
6589 y
= XVECEXP (y
, 0, 0);
6596 if (GET_MODE (orig_x
) != Pmode
)
6598 if (GET_MODE (orig_x
) == BLKmode
)
6600 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
6607 /* Output operand OP to stdio stream FILE.
6608 OP is an address (register + offset) which is not used to address data;
6609 instead the rightmost bits are interpreted as the value. */
6612 print_shift_count_operand (FILE *file
, rtx op
)
6614 HOST_WIDE_INT offset
;
6617 /* Extract base register and offset. */
6618 if (!s390_decompose_shift_count (op
, &base
, &offset
))
6624 gcc_assert (GET_CODE (base
) == REG
);
6625 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
6626 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
6629 /* Offsets are constricted to twelve bits. */
6630 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
6632 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
6635 /* Assigns the number of NOP halfwords to be emitted before and after the
6636 function label to *HW_BEFORE and *HW_AFTER. Both pointers must not be NULL.
6637 If hotpatching is disabled for the function, the values are set to zero.
6641 s390_function_num_hotpatch_hw (tree decl
,
6647 attr
= lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl
));
6649 /* Handle the arguments of the hotpatch attribute. The values
6650 specified via attribute might override the cmdline argument
6654 tree args
= TREE_VALUE (attr
);
6656 *hw_before
= TREE_INT_CST_LOW (TREE_VALUE (args
));
6657 *hw_after
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (args
)));
6661 /* Use the values specified by the cmdline arguments. */
6662 *hw_before
= s390_hotpatch_hw_before_label
;
6663 *hw_after
= s390_hotpatch_hw_after_label
;
6667 /* Write the extra assembler code needed to declare a function properly. */
6670 s390_asm_output_function_label (FILE *asm_out_file
, const char *fname
,
6673 int hw_before
, hw_after
;
6675 s390_function_num_hotpatch_hw (decl
, &hw_before
, &hw_after
);
6678 unsigned int function_alignment
;
6681 /* Add a trampoline code area before the function label and initialize it
6682 with two-byte nop instructions. This area can be overwritten with code
6683 that jumps to a patched version of the function. */
6684 asm_fprintf (asm_out_file
, "\tnopr\t%%r7"
6685 "\t# pre-label NOPs for hotpatch (%d halfwords)\n",
6687 for (i
= 1; i
< hw_before
; i
++)
6688 fputs ("\tnopr\t%r7\n", asm_out_file
);
6690 /* Note: The function label must be aligned so that (a) the bytes of the
6691 following nop do not cross a cacheline boundary, and (b) a jump address
6692 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
6693 stored directly before the label without crossing a cacheline
6694 boundary. All this is necessary to make sure the trampoline code can
6695 be changed atomically.
6696 This alignment is done automatically using the FOUNCTION_BOUNDARY, but
6697 if there are NOPs before the function label, the alignment is placed
6698 before them. So it is necessary to duplicate the alignment after the
6700 function_alignment
= MAX (8, DECL_ALIGN (decl
) / BITS_PER_UNIT
);
6701 if (! DECL_USER_ALIGN (decl
))
6702 function_alignment
= MAX (function_alignment
,
6703 (unsigned int) align_functions
);
6704 fputs ("\t# alignment for hotpatch\n", asm_out_file
);
6705 ASM_OUTPUT_ALIGN (asm_out_file
, floor_log2 (function_alignment
));
6708 ASM_OUTPUT_LABEL (asm_out_file
, fname
);
6710 asm_fprintf (asm_out_file
,
6711 "\t# post-label NOPs for hotpatch (%d halfwords)\n",
6715 /* Output machine-dependent UNSPECs occurring in address constant X
6716 in assembler syntax to stdio stream FILE. Returns true if the
6717 constant X could be recognized, false otherwise. */
6720 s390_output_addr_const_extra (FILE *file
, rtx x
)
6722 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
6723 switch (XINT (x
, 1))
6726 output_addr_const (file
, XVECEXP (x
, 0, 0));
6727 fprintf (file
, "@GOTENT");
6730 output_addr_const (file
, XVECEXP (x
, 0, 0));
6731 fprintf (file
, "@GOT");
6734 output_addr_const (file
, XVECEXP (x
, 0, 0));
6735 fprintf (file
, "@GOTOFF");
6738 output_addr_const (file
, XVECEXP (x
, 0, 0));
6739 fprintf (file
, "@PLT");
6742 output_addr_const (file
, XVECEXP (x
, 0, 0));
6743 fprintf (file
, "@PLTOFF");
6746 output_addr_const (file
, XVECEXP (x
, 0, 0));
6747 fprintf (file
, "@TLSGD");
6750 assemble_name (file
, get_some_local_dynamic_name ());
6751 fprintf (file
, "@TLSLDM");
6754 output_addr_const (file
, XVECEXP (x
, 0, 0));
6755 fprintf (file
, "@DTPOFF");
6758 output_addr_const (file
, XVECEXP (x
, 0, 0));
6759 fprintf (file
, "@NTPOFF");
6761 case UNSPEC_GOTNTPOFF
:
6762 output_addr_const (file
, XVECEXP (x
, 0, 0));
6763 fprintf (file
, "@GOTNTPOFF");
6765 case UNSPEC_INDNTPOFF
:
6766 output_addr_const (file
, XVECEXP (x
, 0, 0));
6767 fprintf (file
, "@INDNTPOFF");
6771 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
6772 switch (XINT (x
, 1))
6774 case UNSPEC_POOL_OFFSET
:
6775 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
6776 output_addr_const (file
, x
);
6782 /* Output address operand ADDR in assembler syntax to
6783 stdio stream FILE. */
6786 print_operand_address (FILE *file
, rtx addr
)
6788 struct s390_address ad
;
6790 if (s390_loadrelative_operand_p (addr
, NULL
, NULL
))
6794 output_operand_lossage ("symbolic memory references are "
6795 "only supported on z10 or later");
6798 output_addr_const (file
, addr
);
6802 if (!s390_decompose_address (addr
, &ad
)
6803 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
6804 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
6805 output_operand_lossage ("cannot decompose address");
6808 output_addr_const (file
, ad
.disp
);
6810 fprintf (file
, "0");
6812 if (ad
.base
&& ad
.indx
)
6813 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
6814 reg_names
[REGNO (ad
.base
)]);
6816 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
6819 /* Output operand X in assembler syntax to stdio stream FILE.
6820 CODE specified the format flag. The following format flags
6823 'C': print opcode suffix for branch condition.
6824 'D': print opcode suffix for inverse branch condition.
6825 'E': print opcode suffix for branch on index instruction.
6826 'G': print the size of the operand in bytes.
6827 'J': print tls_load/tls_gdcall/tls_ldcall suffix
6828 'M': print the second word of a TImode operand.
6829 'N': print the second word of a DImode operand.
6830 'O': print only the displacement of a memory reference or address.
6831 'R': print only the base register of a memory reference or address.
6832 'S': print S-type memory reference (base+displacement).
6833 'Y': print shift count operand.
6835 'b': print integer X as if it's an unsigned byte.
6836 'c': print integer X as if it's an signed byte.
6837 'e': "end" contiguous bitmask X in either DImode or vector inner mode.
6838 'f': "end" contiguous bitmask X in SImode.
6839 'h': print integer X as if it's a signed halfword.
6840 'i': print the first nonzero HImode part of X.
6841 'j': print the first HImode part unequal to -1 of X.
6842 'k': print the first nonzero SImode part of X.
6843 'm': print the first SImode part unequal to -1 of X.
6844 'o': print integer X as if it's an unsigned 32bit word.
6845 's': "start" of contiguous bitmask X in either DImode or vector inner mode.
6846 't': CONST_INT: "start" of contiguous bitmask X in SImode.
6847 CONST_VECTOR: Generate a bitmask for vgbm instruction.
6848 'x': print integer X as if it's an unsigned halfword.
6849 'v': print register number as vector register (v1 instead of f1).
6853 print_operand (FILE *file
, rtx x
, int code
)
6860 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
6864 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
6868 if (GET_CODE (x
) == LE
)
6869 fprintf (file
, "l");
6870 else if (GET_CODE (x
) == GT
)
6871 fprintf (file
, "h");
6873 output_operand_lossage ("invalid comparison operator "
6874 "for 'E' output modifier");
6878 if (GET_CODE (x
) == SYMBOL_REF
)
6880 fprintf (file
, "%s", ":tls_load:");
6881 output_addr_const (file
, x
);
6883 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
6885 fprintf (file
, "%s", ":tls_gdcall:");
6886 output_addr_const (file
, XVECEXP (x
, 0, 0));
6888 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
6890 fprintf (file
, "%s", ":tls_ldcall:");
6891 const char *name
= get_some_local_dynamic_name ();
6893 assemble_name (file
, name
);
6896 output_operand_lossage ("invalid reference for 'J' output modifier");
6900 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
6905 struct s390_address ad
;
6908 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
6911 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
6914 output_operand_lossage ("invalid address for 'O' output modifier");
6919 output_addr_const (file
, ad
.disp
);
6921 fprintf (file
, "0");
6927 struct s390_address ad
;
6930 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
6933 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
6936 output_operand_lossage ("invalid address for 'R' output modifier");
6941 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
6943 fprintf (file
, "0");
6949 struct s390_address ad
;
6954 output_operand_lossage ("memory reference expected for "
6955 "'S' output modifier");
6958 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
6961 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
6964 output_operand_lossage ("invalid address for 'S' output modifier");
6969 output_addr_const (file
, ad
.disp
);
6971 fprintf (file
, "0");
6974 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
6979 if (GET_CODE (x
) == REG
)
6980 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
6981 else if (GET_CODE (x
) == MEM
)
6982 x
= change_address (x
, VOIDmode
,
6983 plus_constant (Pmode
, XEXP (x
, 0), 4));
6985 output_operand_lossage ("register or memory expression expected "
6986 "for 'N' output modifier");
6990 if (GET_CODE (x
) == REG
)
6991 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
6992 else if (GET_CODE (x
) == MEM
)
6993 x
= change_address (x
, VOIDmode
,
6994 plus_constant (Pmode
, XEXP (x
, 0), 8));
6996 output_operand_lossage ("register or memory expression expected "
6997 "for 'M' output modifier");
7001 print_shift_count_operand (file
, x
);
7005 switch (GET_CODE (x
))
7008 /* Print FP regs as fx instead of vx when they are accessed
7009 through non-vector mode. */
7011 || VECTOR_NOFP_REG_P (x
)
7012 || (FP_REG_P (x
) && VECTOR_MODE_P (GET_MODE (x
)))
7013 || (VECTOR_REG_P (x
)
7014 && (GET_MODE_SIZE (GET_MODE (x
)) /
7015 s390_class_max_nregs (FP_REGS
, GET_MODE (x
))) > 8))
7016 fprintf (file
, "%%v%s", reg_names
[REGNO (x
)] + 2);
7018 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
7022 output_address (XEXP (x
, 0));
7029 output_addr_const (file
, x
);
7042 ival
= ((ival
& 0xff) ^ 0x80) - 0x80;
7048 ival
= ((ival
& 0xffff) ^ 0x8000) - 0x8000;
7051 ival
= s390_extract_part (x
, HImode
, 0);
7054 ival
= s390_extract_part (x
, HImode
, -1);
7057 ival
= s390_extract_part (x
, SImode
, 0);
7060 ival
= s390_extract_part (x
, SImode
, -1);
7071 len
= (code
== 's' || code
== 'e' ? 64 : 32);
7072 ok
= s390_contiguous_bitmask_p (ival
, len
, &pos
, &len
);
7074 if (code
== 's' || code
== 't')
7075 ival
= 64 - pos
- len
;
7077 ival
= 64 - 1 - pos
;
7081 output_operand_lossage ("invalid constant for output modifier '%c'", code
);
7083 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7087 gcc_assert (GET_MODE (x
) == VOIDmode
);
7089 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
7090 else if (code
== 'x')
7091 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
7092 else if (code
== 'h')
7093 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7094 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
7098 output_operand_lossage ("invalid constant - try using "
7099 "an output modifier");
7101 output_operand_lossage ("invalid constant for output modifier '%c'",
7111 int start
, stop
, inner_len
;
7114 inner_len
= GET_MODE_UNIT_BITSIZE (GET_MODE (x
));
7115 ok
= s390_contiguous_bitmask_vector_p (x
, &start
, &stop
);
7117 if (code
== 's' || code
== 't')
7118 ival
= inner_len
- stop
- 1;
7120 ival
= inner_len
- start
- 1;
7121 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7127 bool ok
= s390_bytemask_vector_p (x
, &mask
);
7129 fprintf (file
, "%u", mask
);
7134 output_operand_lossage ("invalid constant vector for output "
7135 "modifier '%c'", code
);
7141 output_operand_lossage ("invalid expression - try using "
7142 "an output modifier");
7144 output_operand_lossage ("invalid expression for output "
7145 "modifier '%c'", code
);
7150 /* Target hook for assembling integer objects. We need to define it
7151 here to work a round a bug in some versions of GAS, which couldn't
7152 handle values smaller than INT_MIN when printed in decimal. */
7155 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
7157 if (size
== 8 && aligned_p
7158 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
7160 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
7164 return default_assemble_integer (x
, size
, aligned_p
);
7167 /* Returns true if register REGNO is used for forming
7168 a memory address in expression X. */
7171 reg_used_in_mem_p (int regno
, rtx x
)
7173 enum rtx_code code
= GET_CODE (x
);
7179 if (refers_to_regno_p (regno
, XEXP (x
, 0)))
7182 else if (code
== SET
7183 && GET_CODE (SET_DEST (x
)) == PC
)
7185 if (refers_to_regno_p (regno
, SET_SRC (x
)))
7189 fmt
= GET_RTX_FORMAT (code
);
7190 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7193 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
7196 else if (fmt
[i
] == 'E')
7197 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7198 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
7204 /* Returns true if expression DEP_RTX sets an address register
7205 used by instruction INSN to address memory. */
7208 addr_generation_dependency_p (rtx dep_rtx
, rtx_insn
*insn
)
7212 if (NONJUMP_INSN_P (dep_rtx
))
7213 dep_rtx
= PATTERN (dep_rtx
);
7215 if (GET_CODE (dep_rtx
) == SET
)
7217 target
= SET_DEST (dep_rtx
);
7218 if (GET_CODE (target
) == STRICT_LOW_PART
)
7219 target
= XEXP (target
, 0);
7220 while (GET_CODE (target
) == SUBREG
)
7221 target
= SUBREG_REG (target
);
7223 if (GET_CODE (target
) == REG
)
7225 int regno
= REGNO (target
);
7227 if (s390_safe_attr_type (insn
) == TYPE_LA
)
7229 pat
= PATTERN (insn
);
7230 if (GET_CODE (pat
) == PARALLEL
)
7232 gcc_assert (XVECLEN (pat
, 0) == 2);
7233 pat
= XVECEXP (pat
, 0, 0);
7235 gcc_assert (GET_CODE (pat
) == SET
);
7236 return refers_to_regno_p (regno
, SET_SRC (pat
));
7238 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
7239 return reg_used_in_mem_p (regno
, PATTERN (insn
));
7245 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
7248 s390_agen_dep_p (rtx_insn
*dep_insn
, rtx_insn
*insn
)
7250 rtx dep_rtx
= PATTERN (dep_insn
);
7253 if (GET_CODE (dep_rtx
) == SET
7254 && addr_generation_dependency_p (dep_rtx
, insn
))
7256 else if (GET_CODE (dep_rtx
) == PARALLEL
)
7258 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
7260 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
7268 /* A C statement (sans semicolon) to update the integer scheduling priority
7269 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
7270 reduce the priority to execute INSN later. Do not define this macro if
7271 you do not need to adjust the scheduling priorities of insns.
7273 A STD instruction should be scheduled earlier,
7274 in order to use the bypass. */
7276 s390_adjust_priority (rtx_insn
*insn
, int priority
)
7278 if (! INSN_P (insn
))
7281 if (s390_tune
!= PROCESSOR_2084_Z990
7282 && s390_tune
!= PROCESSOR_2094_Z9_109
7283 && s390_tune
!= PROCESSOR_2097_Z10
7284 && s390_tune
!= PROCESSOR_2817_Z196
7285 && s390_tune
!= PROCESSOR_2827_ZEC12
7286 && s390_tune
!= PROCESSOR_2964_Z13
)
7289 switch (s390_safe_attr_type (insn
))
7293 priority
= priority
<< 3;
7297 priority
= priority
<< 1;
7306 /* The number of instructions that can be issued per cycle. */
7309 s390_issue_rate (void)
7313 case PROCESSOR_2084_Z990
:
7314 case PROCESSOR_2094_Z9_109
:
7315 case PROCESSOR_2817_Z196
:
7317 case PROCESSOR_2097_Z10
:
7319 /* Starting with EC12 we use the sched_reorder hook to take care
7320 of instruction dispatch constraints. The algorithm only
7321 picks the best instruction and assumes only a single
7322 instruction gets issued per cycle. */
7323 case PROCESSOR_2827_ZEC12
:
7330 s390_first_cycle_multipass_dfa_lookahead (void)
7335 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
7336 Fix up MEMs as required. */
7339 annotate_constant_pool_refs (rtx
*x
)
7344 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
7345 || !CONSTANT_POOL_ADDRESS_P (*x
));
7347 /* Literal pool references can only occur inside a MEM ... */
7348 if (GET_CODE (*x
) == MEM
)
7350 rtx memref
= XEXP (*x
, 0);
7352 if (GET_CODE (memref
) == SYMBOL_REF
7353 && CONSTANT_POOL_ADDRESS_P (memref
))
7355 rtx base
= cfun
->machine
->base_reg
;
7356 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
7359 *x
= replace_equiv_address (*x
, addr
);
7363 if (GET_CODE (memref
) == CONST
7364 && GET_CODE (XEXP (memref
, 0)) == PLUS
7365 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
7366 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
7367 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
7369 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
7370 rtx sym
= XEXP (XEXP (memref
, 0), 0);
7371 rtx base
= cfun
->machine
->base_reg
;
7372 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
7375 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
7380 /* ... or a load-address type pattern. */
7381 if (GET_CODE (*x
) == SET
)
7383 rtx addrref
= SET_SRC (*x
);
7385 if (GET_CODE (addrref
) == SYMBOL_REF
7386 && CONSTANT_POOL_ADDRESS_P (addrref
))
7388 rtx base
= cfun
->machine
->base_reg
;
7389 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
7392 SET_SRC (*x
) = addr
;
7396 if (GET_CODE (addrref
) == CONST
7397 && GET_CODE (XEXP (addrref
, 0)) == PLUS
7398 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
7399 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
7400 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
7402 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
7403 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
7404 rtx base
= cfun
->machine
->base_reg
;
7405 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
7408 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
7413 /* Annotate LTREL_BASE as well. */
7414 if (GET_CODE (*x
) == UNSPEC
7415 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
7417 rtx base
= cfun
->machine
->base_reg
;
7418 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
7423 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
7424 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
7428 annotate_constant_pool_refs (&XEXP (*x
, i
));
7430 else if (fmt
[i
] == 'E')
7432 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
7433 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
7438 /* Split all branches that exceed the maximum distance.
7439 Returns true if this created a new literal pool entry. */
7442 s390_split_branches (void)
7444 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7445 int new_literal
= 0, ret
;
7450 /* We need correct insn addresses. */
7452 shorten_branches (get_insns ());
7454 /* Find all branches that exceed 64KB, and split them. */
7456 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7458 if (! JUMP_P (insn
) || tablejump_p (insn
, NULL
, NULL
))
7461 pat
= PATTERN (insn
);
7462 if (GET_CODE (pat
) == PARALLEL
)
7463 pat
= XVECEXP (pat
, 0, 0);
7464 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
7467 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
7469 label
= &SET_SRC (pat
);
7471 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
7473 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
7474 label
= &XEXP (SET_SRC (pat
), 1);
7475 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
7476 label
= &XEXP (SET_SRC (pat
), 2);
7483 if (get_attr_length (insn
) <= 4)
7486 /* We are going to use the return register as scratch register,
7487 make sure it will be saved/restored by the prologue/epilogue. */
7488 cfun_frame_layout
.save_return_addr_p
= 1;
7493 rtx mem
= force_const_mem (Pmode
, *label
);
7494 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (temp_reg
, mem
),
7496 INSN_ADDRESSES_NEW (set_insn
, -1);
7497 annotate_constant_pool_refs (&PATTERN (set_insn
));
7504 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
7505 UNSPEC_LTREL_OFFSET
);
7506 target
= gen_rtx_CONST (Pmode
, target
);
7507 target
= force_const_mem (Pmode
, target
);
7508 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (temp_reg
, target
),
7510 INSN_ADDRESSES_NEW (set_insn
, -1);
7511 annotate_constant_pool_refs (&PATTERN (set_insn
));
7513 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
7514 cfun
->machine
->base_reg
),
7516 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
7519 ret
= validate_change (insn
, label
, target
, 0);
7527 /* Find an annotated literal pool symbol referenced in RTX X,
7528 and store it at REF. Will abort if X contains references to
7529 more than one such pool symbol; multiple references to the same
7530 symbol are allowed, however.
7532 The rtx pointed to by REF must be initialized to NULL_RTX
7533 by the caller before calling this routine. */
7536 find_constant_pool_ref (rtx x
, rtx
*ref
)
7541 /* Ignore LTREL_BASE references. */
7542 if (GET_CODE (x
) == UNSPEC
7543 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
7545 /* Likewise POOL_ENTRY insns. */
7546 if (GET_CODE (x
) == UNSPEC_VOLATILE
7547 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
7550 gcc_assert (GET_CODE (x
) != SYMBOL_REF
7551 || !CONSTANT_POOL_ADDRESS_P (x
));
7553 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
7555 rtx sym
= XVECEXP (x
, 0, 0);
7556 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
7557 && CONSTANT_POOL_ADDRESS_P (sym
));
7559 if (*ref
== NULL_RTX
)
7562 gcc_assert (*ref
== sym
);
7567 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
7568 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7572 find_constant_pool_ref (XEXP (x
, i
), ref
);
7574 else if (fmt
[i
] == 'E')
7576 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7577 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
7582 /* Replace every reference to the annotated literal pool
7583 symbol REF in X by its base plus OFFSET. */
7586 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
7591 gcc_assert (*x
!= ref
);
7593 if (GET_CODE (*x
) == UNSPEC
7594 && XINT (*x
, 1) == UNSPEC_LTREF
7595 && XVECEXP (*x
, 0, 0) == ref
)
7597 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
7601 if (GET_CODE (*x
) == PLUS
7602 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
7603 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
7604 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
7605 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
7607 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
7608 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
7612 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
7613 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
7617 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
7619 else if (fmt
[i
] == 'E')
7621 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
7622 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
7627 /* Check whether X contains an UNSPEC_LTREL_BASE.
7628 Return its constant pool symbol if found, NULL_RTX otherwise. */
7631 find_ltrel_base (rtx x
)
7636 if (GET_CODE (x
) == UNSPEC
7637 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
7638 return XVECEXP (x
, 0, 0);
7640 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
7641 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7645 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
7649 else if (fmt
[i
] == 'E')
7651 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7653 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
7663 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
7666 replace_ltrel_base (rtx
*x
)
7671 if (GET_CODE (*x
) == UNSPEC
7672 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
7674 *x
= XVECEXP (*x
, 0, 1);
7678 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
7679 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
7683 replace_ltrel_base (&XEXP (*x
, i
));
7685 else if (fmt
[i
] == 'E')
7687 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
7688 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
7694 /* We keep a list of constants which we have to add to internal
7695 constant tables in the middle of large functions. */
7697 #define NR_C_MODES 31
7698 machine_mode constant_modes
[NR_C_MODES
] =
7700 TFmode
, TImode
, TDmode
,
7701 V16QImode
, V8HImode
, V4SImode
, V2DImode
, V4SFmode
, V2DFmode
, V1TFmode
,
7702 DFmode
, DImode
, DDmode
,
7703 V8QImode
, V4HImode
, V2SImode
, V1DImode
, V2SFmode
, V1DFmode
,
7704 SFmode
, SImode
, SDmode
,
7705 V4QImode
, V2HImode
, V1SImode
, V1SFmode
,
7714 struct constant
*next
;
7716 rtx_code_label
*label
;
7719 struct constant_pool
7721 struct constant_pool
*next
;
7722 rtx_insn
*first_insn
;
7723 rtx_insn
*pool_insn
;
7725 rtx_insn
*emit_pool_after
;
7727 struct constant
*constants
[NR_C_MODES
];
7728 struct constant
*execute
;
7729 rtx_code_label
*label
;
7733 /* Allocate new constant_pool structure. */
7735 static struct constant_pool
*
7736 s390_alloc_pool (void)
7738 struct constant_pool
*pool
;
7741 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
7743 for (i
= 0; i
< NR_C_MODES
; i
++)
7744 pool
->constants
[i
] = NULL
;
7746 pool
->execute
= NULL
;
7747 pool
->label
= gen_label_rtx ();
7748 pool
->first_insn
= NULL
;
7749 pool
->pool_insn
= NULL
;
7750 pool
->insns
= BITMAP_ALLOC (NULL
);
7752 pool
->emit_pool_after
= NULL
;
7757 /* Create new constant pool covering instructions starting at INSN
7758 and chain it to the end of POOL_LIST. */
7760 static struct constant_pool
*
7761 s390_start_pool (struct constant_pool
**pool_list
, rtx_insn
*insn
)
7763 struct constant_pool
*pool
, **prev
;
7765 pool
= s390_alloc_pool ();
7766 pool
->first_insn
= insn
;
7768 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
7775 /* End range of instructions covered by POOL at INSN and emit
7776 placeholder insn representing the pool. */
7779 s390_end_pool (struct constant_pool
*pool
, rtx_insn
*insn
)
7781 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
7784 insn
= get_last_insn ();
7786 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
7787 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
7790 /* Add INSN to the list of insns covered by POOL. */
7793 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
7795 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
7798 /* Return pool out of POOL_LIST that covers INSN. */
7800 static struct constant_pool
*
7801 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
7803 struct constant_pool
*pool
;
7805 for (pool
= pool_list
; pool
; pool
= pool
->next
)
7806 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
7812 /* Add constant VAL of mode MODE to the constant pool POOL. */
7815 s390_add_constant (struct constant_pool
*pool
, rtx val
, machine_mode mode
)
7820 for (i
= 0; i
< NR_C_MODES
; i
++)
7821 if (constant_modes
[i
] == mode
)
7823 gcc_assert (i
!= NR_C_MODES
);
7825 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
7826 if (rtx_equal_p (val
, c
->value
))
7831 c
= (struct constant
*) xmalloc (sizeof *c
);
7833 c
->label
= gen_label_rtx ();
7834 c
->next
= pool
->constants
[i
];
7835 pool
->constants
[i
] = c
;
7836 pool
->size
+= GET_MODE_SIZE (mode
);
7840 /* Return an rtx that represents the offset of X from the start of
7844 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
7848 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
7849 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
7850 UNSPEC_POOL_OFFSET
);
7851 return gen_rtx_CONST (GET_MODE (x
), x
);
7854 /* Find constant VAL of mode MODE in the constant pool POOL.
7855 Return an RTX describing the distance from the start of
7856 the pool to the location of the new constant. */
7859 s390_find_constant (struct constant_pool
*pool
, rtx val
,
7865 for (i
= 0; i
< NR_C_MODES
; i
++)
7866 if (constant_modes
[i
] == mode
)
7868 gcc_assert (i
!= NR_C_MODES
);
7870 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
7871 if (rtx_equal_p (val
, c
->value
))
7876 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
7879 /* Check whether INSN is an execute. Return the label_ref to its
7880 execute target template if so, NULL_RTX otherwise. */
7883 s390_execute_label (rtx insn
)
7885 if (NONJUMP_INSN_P (insn
)
7886 && GET_CODE (PATTERN (insn
)) == PARALLEL
7887 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
7888 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
7889 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
7894 /* Add execute target for INSN to the constant pool POOL. */
7897 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
7901 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
7902 if (INSN_UID (insn
) == INSN_UID (c
->value
))
7907 c
= (struct constant
*) xmalloc (sizeof *c
);
7909 c
->label
= gen_label_rtx ();
7910 c
->next
= pool
->execute
;
7916 /* Find execute target for INSN in the constant pool POOL.
7917 Return an RTX describing the distance from the start of
7918 the pool to the location of the execute target. */
7921 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
7925 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
7926 if (INSN_UID (insn
) == INSN_UID (c
->value
))
7931 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
7934 /* For an execute INSN, extract the execute target template. */
7937 s390_execute_target (rtx insn
)
7939 rtx pattern
= PATTERN (insn
);
7940 gcc_assert (s390_execute_label (insn
));
7942 if (XVECLEN (pattern
, 0) == 2)
7944 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
7948 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
7951 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
7952 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
7954 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
7960 /* Indicate that INSN cannot be duplicated. This is the case for
7961 execute insns that carry a unique label. */
7964 s390_cannot_copy_insn_p (rtx_insn
*insn
)
7966 rtx label
= s390_execute_label (insn
);
7967 return label
&& label
!= const0_rtx
;
7970 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
7971 do not emit the pool base label. */
7974 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
7977 rtx_insn
*insn
= pool
->pool_insn
;
7980 /* Switch to rodata section. */
7981 if (TARGET_CPU_ZARCH
)
7983 insn
= emit_insn_after (gen_pool_section_start (), insn
);
7984 INSN_ADDRESSES_NEW (insn
, -1);
7987 /* Ensure minimum pool alignment. */
7988 if (TARGET_CPU_ZARCH
)
7989 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
7991 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
7992 INSN_ADDRESSES_NEW (insn
, -1);
7994 /* Emit pool base label. */
7997 insn
= emit_label_after (pool
->label
, insn
);
7998 INSN_ADDRESSES_NEW (insn
, -1);
8001 /* Dump constants in descending alignment requirement order,
8002 ensuring proper alignment for every constant. */
8003 for (i
= 0; i
< NR_C_MODES
; i
++)
8004 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
8006 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
8007 rtx value
= copy_rtx (c
->value
);
8008 if (GET_CODE (value
) == CONST
8009 && GET_CODE (XEXP (value
, 0)) == UNSPEC
8010 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
8011 && XVECLEN (XEXP (value
, 0), 0) == 1)
8012 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
8014 insn
= emit_label_after (c
->label
, insn
);
8015 INSN_ADDRESSES_NEW (insn
, -1);
8017 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
8018 gen_rtvec (1, value
),
8019 UNSPECV_POOL_ENTRY
);
8020 insn
= emit_insn_after (value
, insn
);
8021 INSN_ADDRESSES_NEW (insn
, -1);
8024 /* Ensure minimum alignment for instructions. */
8025 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
8026 INSN_ADDRESSES_NEW (insn
, -1);
8028 /* Output in-pool execute template insns. */
8029 for (c
= pool
->execute
; c
; c
= c
->next
)
8031 insn
= emit_label_after (c
->label
, insn
);
8032 INSN_ADDRESSES_NEW (insn
, -1);
8034 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
8035 INSN_ADDRESSES_NEW (insn
, -1);
8038 /* Switch back to previous section. */
8039 if (TARGET_CPU_ZARCH
)
8041 insn
= emit_insn_after (gen_pool_section_end (), insn
);
8042 INSN_ADDRESSES_NEW (insn
, -1);
8045 insn
= emit_barrier_after (insn
);
8046 INSN_ADDRESSES_NEW (insn
, -1);
8048 /* Remove placeholder insn. */
8049 remove_insn (pool
->pool_insn
);
8052 /* Free all memory used by POOL. */
8055 s390_free_pool (struct constant_pool
*pool
)
8057 struct constant
*c
, *next
;
8060 for (i
= 0; i
< NR_C_MODES
; i
++)
8061 for (c
= pool
->constants
[i
]; c
; c
= next
)
8067 for (c
= pool
->execute
; c
; c
= next
)
8073 BITMAP_FREE (pool
->insns
);
8078 /* Collect main literal pool. Return NULL on overflow. */
8080 static struct constant_pool
*
8081 s390_mainpool_start (void)
8083 struct constant_pool
*pool
;
8086 pool
= s390_alloc_pool ();
8088 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8090 if (NONJUMP_INSN_P (insn
)
8091 && GET_CODE (PATTERN (insn
)) == SET
8092 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
8093 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
8095 /* There might be two main_pool instructions if base_reg
8096 is call-clobbered; one for shrink-wrapped code and one
8097 for the rest. We want to keep the first. */
8098 if (pool
->pool_insn
)
8100 insn
= PREV_INSN (insn
);
8101 delete_insn (NEXT_INSN (insn
));
8104 pool
->pool_insn
= insn
;
8107 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
8109 s390_add_execute (pool
, insn
);
8111 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8113 rtx pool_ref
= NULL_RTX
;
8114 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8117 rtx constant
= get_pool_constant (pool_ref
);
8118 machine_mode mode
= get_pool_mode (pool_ref
);
8119 s390_add_constant (pool
, constant
, mode
);
8123 /* If hot/cold partitioning is enabled we have to make sure that
8124 the literal pool is emitted in the same section where the
8125 initialization of the literal pool base pointer takes place.
8126 emit_pool_after is only used in the non-overflow case on non
8127 Z cpus where we can emit the literal pool at the end of the
8128 function body within the text section. */
8130 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
8131 && !pool
->emit_pool_after
)
8132 pool
->emit_pool_after
= PREV_INSN (insn
);
8135 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
8137 if (pool
->size
>= 4096)
8139 /* We're going to chunkify the pool, so remove the main
8140 pool placeholder insn. */
8141 remove_insn (pool
->pool_insn
);
8143 s390_free_pool (pool
);
8147 /* If the functions ends with the section where the literal pool
8148 should be emitted set the marker to its end. */
8149 if (pool
&& !pool
->emit_pool_after
)
8150 pool
->emit_pool_after
= get_last_insn ();
8155 /* POOL holds the main literal pool as collected by s390_mainpool_start.
8156 Modify the current function to output the pool constants as well as
8157 the pool register setup instruction. */
8160 s390_mainpool_finish (struct constant_pool
*pool
)
8162 rtx base_reg
= cfun
->machine
->base_reg
;
8164 /* If the pool is empty, we're done. */
8165 if (pool
->size
== 0)
8167 /* We don't actually need a base register after all. */
8168 cfun
->machine
->base_reg
= NULL_RTX
;
8170 if (pool
->pool_insn
)
8171 remove_insn (pool
->pool_insn
);
8172 s390_free_pool (pool
);
8176 /* We need correct insn addresses. */
8177 shorten_branches (get_insns ());
8179 /* On zSeries, we use a LARL to load the pool register. The pool is
8180 located in the .rodata section, so we emit it after the function. */
8181 if (TARGET_CPU_ZARCH
)
8183 rtx set
= gen_main_base_64 (base_reg
, pool
->label
);
8184 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
8185 INSN_ADDRESSES_NEW (insn
, -1);
8186 remove_insn (pool
->pool_insn
);
8188 insn
= get_last_insn ();
8189 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
8190 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8192 s390_dump_pool (pool
, 0);
8195 /* On S/390, if the total size of the function's code plus literal pool
8196 does not exceed 4096 bytes, we use BASR to set up a function base
8197 pointer, and emit the literal pool at the end of the function. */
8198 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
8199 + pool
->size
+ 8 /* alignment slop */ < 4096)
8201 rtx set
= gen_main_base_31_small (base_reg
, pool
->label
);
8202 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
8203 INSN_ADDRESSES_NEW (insn
, -1);
8204 remove_insn (pool
->pool_insn
);
8206 insn
= emit_label_after (pool
->label
, insn
);
8207 INSN_ADDRESSES_NEW (insn
, -1);
8209 /* emit_pool_after will be set by s390_mainpool_start to the
8210 last insn of the section where the literal pool should be
8212 insn
= pool
->emit_pool_after
;
8214 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
8215 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8217 s390_dump_pool (pool
, 1);
8220 /* Otherwise, we emit an inline literal pool and use BASR to branch
8221 over it, setting up the pool register at the same time. */
8224 rtx_code_label
*pool_end
= gen_label_rtx ();
8226 rtx pat
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
8227 rtx_insn
*insn
= emit_jump_insn_after (pat
, pool
->pool_insn
);
8228 JUMP_LABEL (insn
) = pool_end
;
8229 INSN_ADDRESSES_NEW (insn
, -1);
8230 remove_insn (pool
->pool_insn
);
8232 insn
= emit_label_after (pool
->label
, insn
);
8233 INSN_ADDRESSES_NEW (insn
, -1);
8235 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
8236 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8238 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
8239 INSN_ADDRESSES_NEW (insn
, -1);
8241 s390_dump_pool (pool
, 1);
8245 /* Replace all literal pool references. */
8247 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8250 replace_ltrel_base (&PATTERN (insn
));
8252 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8254 rtx addr
, pool_ref
= NULL_RTX
;
8255 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8258 if (s390_execute_label (insn
))
8259 addr
= s390_find_execute (pool
, insn
);
8261 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
8262 get_pool_mode (pool_ref
));
8264 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
8265 INSN_CODE (insn
) = -1;
8271 /* Free the pool. */
8272 s390_free_pool (pool
);
8275 /* POOL holds the main literal pool as collected by s390_mainpool_start.
8276 We have decided we cannot use this pool, so revert all changes
8277 to the current function that were done by s390_mainpool_start. */
8279 s390_mainpool_cancel (struct constant_pool
*pool
)
8281 /* We didn't actually change the instruction stream, so simply
8282 free the pool memory. */
8283 s390_free_pool (pool
);
8287 /* Chunkify the literal pool. */
8289 #define S390_POOL_CHUNK_MIN 0xc00
8290 #define S390_POOL_CHUNK_MAX 0xe00
8292 static struct constant_pool
*
8293 s390_chunkify_start (void)
8295 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
8298 rtx pending_ltrel
= NULL_RTX
;
8301 rtx (*gen_reload_base
) (rtx
, rtx
) =
8302 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
8305 /* We need correct insn addresses. */
8307 shorten_branches (get_insns ());
8309 /* Scan all insns and move literals to pool chunks. */
8311 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8313 bool section_switch_p
= false;
8315 /* Check for pending LTREL_BASE. */
8318 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
8321 gcc_assert (ltrel_base
== pending_ltrel
);
8322 pending_ltrel
= NULL_RTX
;
8326 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
8329 curr_pool
= s390_start_pool (&pool_list
, insn
);
8331 s390_add_execute (curr_pool
, insn
);
8332 s390_add_pool_insn (curr_pool
, insn
);
8334 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8336 rtx pool_ref
= NULL_RTX
;
8337 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8340 rtx constant
= get_pool_constant (pool_ref
);
8341 machine_mode mode
= get_pool_mode (pool_ref
);
8344 curr_pool
= s390_start_pool (&pool_list
, insn
);
8346 s390_add_constant (curr_pool
, constant
, mode
);
8347 s390_add_pool_insn (curr_pool
, insn
);
8349 /* Don't split the pool chunk between a LTREL_OFFSET load
8350 and the corresponding LTREL_BASE. */
8351 if (GET_CODE (constant
) == CONST
8352 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
8353 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
8355 gcc_assert (!pending_ltrel
);
8356 pending_ltrel
= pool_ref
;
8361 if (JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
) || LABEL_P (insn
))
8364 s390_add_pool_insn (curr_pool
, insn
);
8365 /* An LTREL_BASE must follow within the same basic block. */
8366 gcc_assert (!pending_ltrel
);
8370 switch (NOTE_KIND (insn
))
8372 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
8373 section_switch_p
= true;
8375 case NOTE_INSN_VAR_LOCATION
:
8376 case NOTE_INSN_CALL_ARG_LOCATION
:
8383 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
8384 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
8387 if (TARGET_CPU_ZARCH
)
8389 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
8392 s390_end_pool (curr_pool
, NULL
);
8397 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
8398 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
8401 /* We will later have to insert base register reload insns.
8402 Those will have an effect on code size, which we need to
8403 consider here. This calculation makes rather pessimistic
8404 worst-case assumptions. */
8408 if (chunk_size
< S390_POOL_CHUNK_MIN
8409 && curr_pool
->size
< S390_POOL_CHUNK_MIN
8410 && !section_switch_p
)
8413 /* Pool chunks can only be inserted after BARRIERs ... */
8414 if (BARRIER_P (insn
))
8416 s390_end_pool (curr_pool
, insn
);
8421 /* ... so if we don't find one in time, create one. */
8422 else if (chunk_size
> S390_POOL_CHUNK_MAX
8423 || curr_pool
->size
> S390_POOL_CHUNK_MAX
8424 || section_switch_p
)
8426 rtx_insn
*label
, *jump
, *barrier
, *next
, *prev
;
8428 if (!section_switch_p
)
8430 /* We can insert the barrier only after a 'real' insn. */
8431 if (! NONJUMP_INSN_P (insn
) && ! CALL_P (insn
))
8433 if (get_attr_length (insn
) == 0)
8435 /* Don't separate LTREL_BASE from the corresponding
8436 LTREL_OFFSET load. */
8443 next
= NEXT_INSN (insn
);
8447 && (NOTE_KIND (next
) == NOTE_INSN_VAR_LOCATION
8448 || NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
));
8452 gcc_assert (!pending_ltrel
);
8454 /* The old pool has to end before the section switch
8455 note in order to make it part of the current
8457 insn
= PREV_INSN (insn
);
8460 label
= gen_label_rtx ();
8462 if (prev
&& NOTE_P (prev
))
8463 prev
= prev_nonnote_insn (prev
);
8465 jump
= emit_jump_insn_after_setloc (gen_jump (label
), insn
,
8466 INSN_LOCATION (prev
));
8468 jump
= emit_jump_insn_after_noloc (gen_jump (label
), insn
);
8469 barrier
= emit_barrier_after (jump
);
8470 insn
= emit_label_after (label
, barrier
);
8471 JUMP_LABEL (jump
) = label
;
8472 LABEL_NUSES (label
) = 1;
8474 INSN_ADDRESSES_NEW (jump
, -1);
8475 INSN_ADDRESSES_NEW (barrier
, -1);
8476 INSN_ADDRESSES_NEW (insn
, -1);
8478 s390_end_pool (curr_pool
, barrier
);
8486 s390_end_pool (curr_pool
, NULL
);
8487 gcc_assert (!pending_ltrel
);
8489 /* Find all labels that are branched into
8490 from an insn belonging to a different chunk. */
8492 far_labels
= BITMAP_ALLOC (NULL
);
8494 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8496 rtx_jump_table_data
*table
;
8498 /* Labels marked with LABEL_PRESERVE_P can be target
8499 of non-local jumps, so we have to mark them.
8500 The same holds for named labels.
8502 Don't do that, however, if it is the label before
8506 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
8508 rtx_insn
*vec_insn
= NEXT_INSN (insn
);
8509 if (! vec_insn
|| ! JUMP_TABLE_DATA_P (vec_insn
))
8510 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
8512 /* Check potential targets in a table jump (casesi_jump). */
8513 else if (tablejump_p (insn
, NULL
, &table
))
8515 rtx vec_pat
= PATTERN (table
);
8516 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
8518 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
8520 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
8522 if (s390_find_pool (pool_list
, label
)
8523 != s390_find_pool (pool_list
, insn
))
8524 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
8527 /* If we have a direct jump (conditional or unconditional),
8528 check all potential targets. */
8529 else if (JUMP_P (insn
))
8531 rtx pat
= PATTERN (insn
);
8533 if (GET_CODE (pat
) == PARALLEL
)
8534 pat
= XVECEXP (pat
, 0, 0);
8536 if (GET_CODE (pat
) == SET
)
8538 rtx label
= JUMP_LABEL (insn
);
8539 if (label
&& !ANY_RETURN_P (label
))
8541 if (s390_find_pool (pool_list
, label
)
8542 != s390_find_pool (pool_list
, insn
))
8543 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
8549 /* Insert base register reload insns before every pool. */
8551 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
8553 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
8555 rtx_insn
*insn
= curr_pool
->first_insn
;
8556 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
8559 /* Insert base register reload insns at every far label. */
8561 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8563 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
8565 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
8568 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
8570 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
8575 BITMAP_FREE (far_labels
);
8578 /* Recompute insn addresses. */
8580 init_insn_lengths ();
8581 shorten_branches (get_insns ());
8586 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
8587 After we have decided to use this list, finish implementing
8588 all changes to the current function as required. */
8591 s390_chunkify_finish (struct constant_pool
*pool_list
)
8593 struct constant_pool
*curr_pool
= NULL
;
8597 /* Replace all literal pool references. */
8599 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8602 replace_ltrel_base (&PATTERN (insn
));
8604 curr_pool
= s390_find_pool (pool_list
, insn
);
8608 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8610 rtx addr
, pool_ref
= NULL_RTX
;
8611 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8614 if (s390_execute_label (insn
))
8615 addr
= s390_find_execute (curr_pool
, insn
);
8617 addr
= s390_find_constant (curr_pool
,
8618 get_pool_constant (pool_ref
),
8619 get_pool_mode (pool_ref
));
8621 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
8622 INSN_CODE (insn
) = -1;
8627 /* Dump out all literal pools. */
8629 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
8630 s390_dump_pool (curr_pool
, 0);
8632 /* Free pool list. */
8636 struct constant_pool
*next
= pool_list
->next
;
8637 s390_free_pool (pool_list
);
8642 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
8643 We have decided we cannot use this list, so revert all changes
8644 to the current function that were done by s390_chunkify_start. */
8647 s390_chunkify_cancel (struct constant_pool
*pool_list
)
8649 struct constant_pool
*curr_pool
= NULL
;
8652 /* Remove all pool placeholder insns. */
8654 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
8656 /* Did we insert an extra barrier? Remove it. */
8657 rtx_insn
*barrier
= PREV_INSN (curr_pool
->pool_insn
);
8658 rtx_insn
*jump
= barrier
? PREV_INSN (barrier
) : NULL
;
8659 rtx_insn
*label
= NEXT_INSN (curr_pool
->pool_insn
);
8661 if (jump
&& JUMP_P (jump
)
8662 && barrier
&& BARRIER_P (barrier
)
8663 && label
&& LABEL_P (label
)
8664 && GET_CODE (PATTERN (jump
)) == SET
8665 && SET_DEST (PATTERN (jump
)) == pc_rtx
8666 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
8667 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
8670 remove_insn (barrier
);
8671 remove_insn (label
);
8674 remove_insn (curr_pool
->pool_insn
);
8677 /* Remove all base register reload insns. */
8679 for (insn
= get_insns (); insn
; )
8681 rtx_insn
*next_insn
= NEXT_INSN (insn
);
8683 if (NONJUMP_INSN_P (insn
)
8684 && GET_CODE (PATTERN (insn
)) == SET
8685 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
8686 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
8692 /* Free pool list. */
8696 struct constant_pool
*next
= pool_list
->next
;
8697 s390_free_pool (pool_list
);
8702 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
8705 s390_output_pool_entry (rtx exp
, machine_mode mode
, unsigned int align
)
8709 switch (GET_MODE_CLASS (mode
))
8712 case MODE_DECIMAL_FLOAT
:
8713 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
8715 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
8716 assemble_real (r
, mode
, align
);
8720 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
8721 mark_symbol_refs_as_used (exp
);
8724 case MODE_VECTOR_INT
:
8725 case MODE_VECTOR_FLOAT
:
8728 machine_mode inner_mode
;
8729 gcc_assert (GET_CODE (exp
) == CONST_VECTOR
);
8731 inner_mode
= GET_MODE_INNER (GET_MODE (exp
));
8732 for (i
= 0; i
< XVECLEN (exp
, 0); i
++)
8733 s390_output_pool_entry (XVECEXP (exp
, 0, i
),
8737 : GET_MODE_BITSIZE (inner_mode
));
8747 /* Return an RTL expression representing the value of the return address
8748 for the frame COUNT steps up from the current frame. FRAME is the
8749 frame pointer of that frame. */
8752 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
8757 /* Without backchain, we fail for all but the current frame. */
8759 if (!TARGET_BACKCHAIN
&& count
> 0)
8762 /* For the current frame, we need to make sure the initial
8763 value of RETURN_REGNUM is actually saved. */
8767 /* On non-z architectures branch splitting could overwrite r14. */
8768 if (TARGET_CPU_ZARCH
)
8769 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
8772 cfun_frame_layout
.save_return_addr_p
= true;
8773 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
8777 if (TARGET_PACKED_STACK
)
8778 offset
= -2 * UNITS_PER_LONG
;
8780 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
8782 addr
= plus_constant (Pmode
, frame
, offset
);
8783 addr
= memory_address (Pmode
, addr
);
8784 return gen_rtx_MEM (Pmode
, addr
);
8787 /* Return an RTL expression representing the back chain stored in
8788 the current stack frame. */
8791 s390_back_chain_rtx (void)
8795 gcc_assert (TARGET_BACKCHAIN
);
8797 if (TARGET_PACKED_STACK
)
8798 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
8799 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
8801 chain
= stack_pointer_rtx
;
8803 chain
= gen_rtx_MEM (Pmode
, chain
);
8807 /* Find first call clobbered register unused in a function.
8808 This could be used as base register in a leaf function
8809 or for holding the return address before epilogue. */
8812 find_unused_clobbered_reg (void)
8815 for (i
= 0; i
< 6; i
++)
8816 if (!df_regs_ever_live_p (i
))
8822 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
8823 clobbered hard regs in SETREG. */
8826 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
8828 char *regs_ever_clobbered
= (char *)data
;
8829 unsigned int i
, regno
;
8830 machine_mode mode
= GET_MODE (setreg
);
8832 if (GET_CODE (setreg
) == SUBREG
)
8834 rtx inner
= SUBREG_REG (setreg
);
8835 if (!GENERAL_REG_P (inner
) && !FP_REG_P (inner
))
8837 regno
= subreg_regno (setreg
);
8839 else if (GENERAL_REG_P (setreg
) || FP_REG_P (setreg
))
8840 regno
= REGNO (setreg
);
8845 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
8847 regs_ever_clobbered
[i
] = 1;
8850 /* Walks through all basic blocks of the current function looking
8851 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
8852 of the passed integer array REGS_EVER_CLOBBERED are set to one for
8853 each of those regs. */
8856 s390_regs_ever_clobbered (char regs_ever_clobbered
[])
8862 memset (regs_ever_clobbered
, 0, 32);
8864 /* For non-leaf functions we have to consider all call clobbered regs to be
8868 for (i
= 0; i
< 32; i
++)
8869 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
8872 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
8873 this work is done by liveness analysis (mark_regs_live_at_end).
8874 Special care is needed for functions containing landing pads. Landing pads
8875 may use the eh registers, but the code which sets these registers is not
8876 contained in that function. Hence s390_regs_ever_clobbered is not able to
8877 deal with this automatically. */
8878 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
8879 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
8880 if (crtl
->calls_eh_return
8881 || (cfun
->machine
->has_landing_pad_p
8882 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
8883 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
8885 /* For nonlocal gotos all call-saved registers have to be saved.
8886 This flag is also set for the unwinding code in libgcc.
8887 See expand_builtin_unwind_init. For regs_ever_live this is done by
8889 if (crtl
->saves_all_registers
)
8890 for (i
= 0; i
< 32; i
++)
8891 if (!call_really_used_regs
[i
])
8892 regs_ever_clobbered
[i
] = 1;
8894 FOR_EACH_BB_FN (cur_bb
, cfun
)
8896 FOR_BB_INSNS (cur_bb
, cur_insn
)
8900 if (!INSN_P (cur_insn
))
8903 pat
= PATTERN (cur_insn
);
8905 /* Ignore GPR restore insns. */
8906 if (epilogue_completed
&& RTX_FRAME_RELATED_P (cur_insn
))
8908 if (GET_CODE (pat
) == SET
8909 && GENERAL_REG_P (SET_DEST (pat
)))
8912 if (GET_MODE (SET_SRC (pat
)) == DImode
8913 && FP_REG_P (SET_SRC (pat
)))
8917 if (GET_CODE (SET_SRC (pat
)) == MEM
)
8922 if (GET_CODE (pat
) == PARALLEL
8923 && load_multiple_operation (pat
, VOIDmode
))
8928 s390_reg_clobbered_rtx
,
8929 regs_ever_clobbered
);
8934 /* Determine the frame area which actually has to be accessed
8935 in the function epilogue. The values are stored at the
8936 given pointers AREA_BOTTOM (address of the lowest used stack
8937 address) and AREA_TOP (address of the first item which does
8938 not belong to the stack frame). */
8941 s390_frame_area (int *area_bottom
, int *area_top
)
8948 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8950 b
= (cfun_frame_layout
.gprs_offset
8951 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
8952 t
= b
+ (cfun_frame_layout
.last_restore_gpr
8953 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
8956 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
8958 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
8959 t
= MAX (t
, (cfun_frame_layout
.f8_offset
8960 + cfun_frame_layout
.high_fprs
* 8));
8965 if (cfun_fpr_save_p (FPR4_REGNUM
))
8967 b
= MIN (b
, cfun_frame_layout
.f4_offset
);
8968 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 8);
8970 if (cfun_fpr_save_p (FPR6_REGNUM
))
8972 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ 8);
8973 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 16);
8979 /* Update gpr_save_slots in the frame layout trying to make use of
8980 FPRs as GPR save slots.
8981 This is a helper routine of s390_register_info. */
8984 s390_register_info_gprtofpr ()
8986 int save_reg_slot
= FPR0_REGNUM
;
8989 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
8992 for (i
= 15; i
>= 6; i
--)
8994 if (cfun_gpr_save_slot (i
) == 0)
8997 /* Advance to the next FP register which can be used as a
8999 while ((!call_really_used_regs
[save_reg_slot
]
9000 || df_regs_ever_live_p (save_reg_slot
)
9001 || cfun_fpr_save_p (save_reg_slot
))
9002 && FP_REGNO_P (save_reg_slot
))
9004 if (!FP_REGNO_P (save_reg_slot
))
9006 /* We only want to use ldgr/lgdr if we can get rid of
9007 stm/lm entirely. So undo the gpr slot allocation in
9008 case we ran out of FPR save slots. */
9009 for (j
= 6; j
<= 15; j
++)
9010 if (FP_REGNO_P (cfun_gpr_save_slot (j
)))
9011 cfun_gpr_save_slot (j
) = -1;
9014 cfun_gpr_save_slot (i
) = save_reg_slot
++;
9018 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
9020 This is a helper routine for s390_register_info. */
9023 s390_register_info_stdarg_fpr ()
9029 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
9030 f0-f4 for 64 bit. */
9032 || !TARGET_HARD_FLOAT
9033 || !cfun
->va_list_fpr_size
9034 || crtl
->args
.info
.fprs
>= FP_ARG_NUM_REG
)
9037 min_fpr
= crtl
->args
.info
.fprs
;
9038 max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
9039 if (max_fpr
> FP_ARG_NUM_REG
)
9040 max_fpr
= FP_ARG_NUM_REG
;
9042 for (i
= min_fpr
; i
< max_fpr
; i
++)
9043 cfun_set_fpr_save (i
+ FPR0_REGNUM
);
9046 /* Reserve the GPR save slots for GPRs which need to be saved due to
9048 This is a helper routine for s390_register_info. */
9051 s390_register_info_stdarg_gpr ()
9058 || !cfun
->va_list_gpr_size
9059 || crtl
->args
.info
.gprs
>= GP_ARG_NUM_REG
)
9062 min_gpr
= crtl
->args
.info
.gprs
;
9063 max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
9064 if (max_gpr
> GP_ARG_NUM_REG
)
9065 max_gpr
= GP_ARG_NUM_REG
;
9067 for (i
= min_gpr
; i
< max_gpr
; i
++)
9068 cfun_gpr_save_slot (2 + i
) = -1;
9071 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
9072 for registers which need to be saved in function prologue.
9073 This function can be used until the insns emitted for save/restore
9074 of the regs are visible in the RTL stream. */
9077 s390_register_info ()
9080 char clobbered_regs
[32];
9082 gcc_assert (!epilogue_completed
);
9084 if (reload_completed
)
9085 /* After reload we rely on our own routine to determine which
9086 registers need saving. */
9087 s390_regs_ever_clobbered (clobbered_regs
);
9089 /* During reload we use regs_ever_live as a base since reload
9090 does changes in there which we otherwise would not be aware
9092 for (i
= 0; i
< 32; i
++)
9093 clobbered_regs
[i
] = df_regs_ever_live_p (i
);
9095 for (i
= 0; i
< 32; i
++)
9096 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
9098 /* Mark the call-saved FPRs which need to be saved.
9099 This needs to be done before checking the special GPRs since the
9100 stack pointer usage depends on whether high FPRs have to be saved
9102 cfun_frame_layout
.fpr_bitmap
= 0;
9103 cfun_frame_layout
.high_fprs
= 0;
9104 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
9105 if (clobbered_regs
[i
] && !call_really_used_regs
[i
])
9107 cfun_set_fpr_save (i
);
9108 if (i
>= FPR8_REGNUM
)
9109 cfun_frame_layout
.high_fprs
++;
9113 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
9114 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
9116 clobbered_regs
[BASE_REGNUM
]
9117 |= (cfun
->machine
->base_reg
9118 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
9120 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
]
9121 |= !!frame_pointer_needed
;
9123 /* On pre z900 machines this might take until machine dependent
9125 save_return_addr_p will only be set on non-zarch machines so
9126 there is no risk that r14 goes into an FPR instead of a stack
9128 clobbered_regs
[RETURN_REGNUM
]
9130 || TARGET_TPF_PROFILING
9131 || cfun
->machine
->split_branches_pending_p
9132 || cfun_frame_layout
.save_return_addr_p
9133 || crtl
->calls_eh_return
);
9135 clobbered_regs
[STACK_POINTER_REGNUM
]
9137 || TARGET_TPF_PROFILING
9138 || cfun_save_high_fprs_p
9139 || get_frame_size () > 0
9140 || (reload_completed
&& cfun_frame_layout
.frame_size
> 0)
9141 || cfun
->calls_alloca
);
9143 memset (cfun_frame_layout
.gpr_save_slots
, 0, 16);
9145 for (i
= 6; i
< 16; i
++)
9146 if (clobbered_regs
[i
])
9147 cfun_gpr_save_slot (i
) = -1;
9149 s390_register_info_stdarg_fpr ();
9150 s390_register_info_gprtofpr ();
9152 /* First find the range of GPRs to be restored. Vararg regs don't
9153 need to be restored so we do it before assigning slots to the
9155 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
9156 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
9157 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
9158 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
9160 /* stdarg functions might need to save GPRs 2 to 6. This might
9161 override the GPR->FPR save decision made above for r6 since
9162 vararg regs must go to the stack. */
9163 s390_register_info_stdarg_gpr ();
9165 /* Now the range of GPRs which need saving. */
9166 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
9167 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
9168 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
9169 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
9172 /* This function is called by s390_optimize_prologue in order to get
9173 rid of unnecessary GPR save/restore instructions. The register info
9174 for the GPRs is re-computed and the ranges are re-calculated. */
9177 s390_optimize_register_info ()
9179 char clobbered_regs
[32];
9182 gcc_assert (epilogue_completed
);
9183 gcc_assert (!cfun
->machine
->split_branches_pending_p
);
9185 s390_regs_ever_clobbered (clobbered_regs
);
9187 for (i
= 0; i
< 32; i
++)
9188 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
9190 /* There is still special treatment needed for cases invisible to
9191 s390_regs_ever_clobbered. */
9192 clobbered_regs
[RETURN_REGNUM
]
9193 |= (TARGET_TPF_PROFILING
9194 /* When expanding builtin_return_addr in ESA mode we do not
9195 know whether r14 will later be needed as scratch reg when
9196 doing branch splitting. So the builtin always accesses the
9197 r14 save slot and we need to stick to the save/restore
9198 decision for r14 even if it turns out that it didn't get
9200 || cfun_frame_layout
.save_return_addr_p
9201 || crtl
->calls_eh_return
);
9203 memset (cfun_frame_layout
.gpr_save_slots
, 0, 6);
9205 for (i
= 6; i
< 16; i
++)
9206 if (!clobbered_regs
[i
])
9207 cfun_gpr_save_slot (i
) = 0;
9209 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
9210 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
9211 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
9212 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
9214 s390_register_info_stdarg_gpr ();
9216 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != -1; i
++);
9217 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != -1; j
--);
9218 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
9219 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
9222 /* Fill cfun->machine with info about frame of current function. */
9225 s390_frame_info (void)
9227 HOST_WIDE_INT lowest_offset
;
9229 cfun_frame_layout
.first_save_gpr_slot
= cfun_frame_layout
.first_save_gpr
;
9230 cfun_frame_layout
.last_save_gpr_slot
= cfun_frame_layout
.last_save_gpr
;
9232 /* The va_arg builtin uses a constant distance of 16 *
9233 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
9234 pointer. So even if we are going to save the stack pointer in an
9235 FPR we need the stack space in order to keep the offsets
9237 if (cfun
->stdarg
&& cfun_save_arg_fprs_p
)
9239 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
9241 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
9242 cfun_frame_layout
.first_save_gpr_slot
= STACK_POINTER_REGNUM
;
9245 cfun_frame_layout
.frame_size
= get_frame_size ();
9246 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
9247 fatal_error (input_location
,
9248 "total size of local variables exceeds architecture limit");
9250 if (!TARGET_PACKED_STACK
)
9252 /* Fixed stack layout. */
9253 cfun_frame_layout
.backchain_offset
= 0;
9254 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
9255 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
9256 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
9257 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
9260 else if (TARGET_BACKCHAIN
)
9262 /* Kernel stack layout - packed stack, backchain, no float */
9263 gcc_assert (TARGET_SOFT_FLOAT
);
9264 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
9267 /* The distance between the backchain and the return address
9268 save slot must not change. So we always need a slot for the
9269 stack pointer which resides in between. */
9270 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
9272 cfun_frame_layout
.gprs_offset
9273 = cfun_frame_layout
.backchain_offset
- cfun_gprs_save_area_size
;
9275 /* FPRs will not be saved. Nevertheless pick sane values to
9276 keep area calculations valid. */
9277 cfun_frame_layout
.f0_offset
=
9278 cfun_frame_layout
.f4_offset
=
9279 cfun_frame_layout
.f8_offset
= cfun_frame_layout
.gprs_offset
;
9285 /* Packed stack layout without backchain. */
9287 /* With stdarg FPRs need their dedicated slots. */
9288 num_fprs
= (TARGET_64BIT
&& cfun
->stdarg
? 2
9289 : (cfun_fpr_save_p (FPR4_REGNUM
) +
9290 cfun_fpr_save_p (FPR6_REGNUM
)));
9291 cfun_frame_layout
.f4_offset
= STACK_POINTER_OFFSET
- 8 * num_fprs
;
9293 num_fprs
= (cfun
->stdarg
? 2
9294 : (cfun_fpr_save_p (FPR0_REGNUM
)
9295 + cfun_fpr_save_p (FPR2_REGNUM
)));
9296 cfun_frame_layout
.f0_offset
= cfun_frame_layout
.f4_offset
- 8 * num_fprs
;
9298 cfun_frame_layout
.gprs_offset
9299 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
9301 cfun_frame_layout
.f8_offset
= (cfun_frame_layout
.gprs_offset
9302 - cfun_frame_layout
.high_fprs
* 8);
9305 if (cfun_save_high_fprs_p
)
9306 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
9309 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
9311 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
9312 sized area at the bottom of the stack. This is required also for
9313 leaf functions. When GCC generates a local stack reference it
9314 will always add STACK_POINTER_OFFSET to all these references. */
9316 && !TARGET_TPF_PROFILING
9317 && cfun_frame_layout
.frame_size
== 0
9318 && !cfun
->calls_alloca
)
9321 /* Calculate the number of bytes we have used in our own register
9322 save area. With the packed stack layout we can re-use the
9323 remaining bytes for normal stack elements. */
9325 if (TARGET_PACKED_STACK
)
9326 lowest_offset
= MIN (MIN (cfun_frame_layout
.f0_offset
,
9327 cfun_frame_layout
.f4_offset
),
9328 cfun_frame_layout
.gprs_offset
);
9332 if (TARGET_BACKCHAIN
)
9333 lowest_offset
= MIN (lowest_offset
, cfun_frame_layout
.backchain_offset
);
9335 cfun_frame_layout
.frame_size
+= STACK_POINTER_OFFSET
- lowest_offset
;
9337 /* If under 31 bit an odd number of gprs has to be saved we have to
9338 adjust the frame size to sustain 8 byte alignment of stack
9340 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
9341 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
9342 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
9345 /* Generate frame layout. Fills in register and frame data for the current
9346 function in cfun->machine. This routine can be called multiple times;
9347 it will re-do the complete frame layout every time. */
9350 s390_init_frame_layout (void)
9352 HOST_WIDE_INT frame_size
;
9355 gcc_assert (!reload_completed
);
9357 /* On S/390 machines, we may need to perform branch splitting, which
9358 will require both base and return address register. We have no
9359 choice but to assume we're going to need them until right at the
9360 end of the machine dependent reorg phase. */
9361 if (!TARGET_CPU_ZARCH
)
9362 cfun
->machine
->split_branches_pending_p
= true;
9366 frame_size
= cfun_frame_layout
.frame_size
;
9368 /* Try to predict whether we'll need the base register. */
9369 base_used
= cfun
->machine
->split_branches_pending_p
9370 || crtl
->uses_const_pool
9371 || (!DISP_IN_RANGE (frame_size
)
9372 && !CONST_OK_FOR_K (frame_size
));
9374 /* Decide which register to use as literal pool base. In small
9375 leaf functions, try to use an unused call-clobbered register
9376 as base register to avoid save/restore overhead. */
9378 cfun
->machine
->base_reg
= NULL_RTX
;
9379 else if (crtl
->is_leaf
&& !df_regs_ever_live_p (5))
9380 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
9382 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
9384 s390_register_info ();
9387 while (frame_size
!= cfun_frame_layout
.frame_size
);
9390 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
9391 the TX is nonescaping. A transaction is considered escaping if
9392 there is at least one path from tbegin returning CC0 to the
9393 function exit block without an tend.
9395 The check so far has some limitations:
9396 - only single tbegin/tend BBs are supported
9397 - the first cond jump after tbegin must separate the CC0 path from ~CC0
9398 - when CC is copied to a GPR and the CC0 check is done with the GPR
9399 this is not supported
9403 s390_optimize_nonescaping_tx (void)
9405 const unsigned int CC0
= 1 << 3;
9406 basic_block tbegin_bb
= NULL
;
9407 basic_block tend_bb
= NULL
;
9412 rtx_insn
*tbegin_insn
= NULL
;
9414 if (!cfun
->machine
->tbegin_p
)
9417 for (bb_index
= 0; bb_index
< n_basic_blocks_for_fn (cfun
); bb_index
++)
9419 bb
= BASIC_BLOCK_FOR_FN (cfun
, bb_index
);
9424 FOR_BB_INSNS (bb
, insn
)
9426 rtx ite
, cc
, pat
, target
;
9427 unsigned HOST_WIDE_INT mask
;
9429 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
9432 pat
= PATTERN (insn
);
9434 if (GET_CODE (pat
) == PARALLEL
)
9435 pat
= XVECEXP (pat
, 0, 0);
9437 if (GET_CODE (pat
) != SET
9438 || GET_CODE (SET_SRC (pat
)) != UNSPEC_VOLATILE
)
9441 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TBEGIN
)
9447 /* Just return if the tbegin doesn't have clobbers. */
9448 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
9451 if (tbegin_bb
!= NULL
)
9454 /* Find the next conditional jump. */
9455 for (tmp
= NEXT_INSN (insn
);
9457 tmp
= NEXT_INSN (tmp
))
9459 if (reg_set_p (gen_rtx_REG (CCmode
, CC_REGNUM
), tmp
))
9464 ite
= SET_SRC (PATTERN (tmp
));
9465 if (GET_CODE (ite
) != IF_THEN_ELSE
)
9468 cc
= XEXP (XEXP (ite
, 0), 0);
9469 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
))
9470 || GET_MODE (cc
) != CCRAWmode
9471 || GET_CODE (XEXP (XEXP (ite
, 0), 1)) != CONST_INT
)
9474 if (bb
->succs
->length () != 2)
9477 mask
= INTVAL (XEXP (XEXP (ite
, 0), 1));
9478 if (GET_CODE (XEXP (ite
, 0)) == NE
)
9482 target
= XEXP (ite
, 1);
9483 else if (mask
== (CC0
^ 0xf))
9484 target
= XEXP (ite
, 2);
9492 ei
= ei_start (bb
->succs
);
9493 e1
= ei_safe_edge (ei
);
9495 e2
= ei_safe_edge (ei
);
9497 if (e2
->flags
& EDGE_FALLTHRU
)
9500 e1
= ei_safe_edge (ei
);
9503 if (!(e1
->flags
& EDGE_FALLTHRU
))
9506 tbegin_bb
= (target
== pc_rtx
) ? e1
->dest
: e2
->dest
;
9508 if (tmp
== BB_END (bb
))
9513 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TEND
)
9515 if (tend_bb
!= NULL
)
9522 /* Either we successfully remove the FPR clobbers here or we are not
9523 able to do anything for this TX. Both cases don't qualify for
9525 cfun
->machine
->tbegin_p
= false;
9527 if (tbegin_bb
== NULL
|| tend_bb
== NULL
)
9530 calculate_dominance_info (CDI_POST_DOMINATORS
);
9531 result
= dominated_by_p (CDI_POST_DOMINATORS
, tbegin_bb
, tend_bb
);
9532 free_dominance_info (CDI_POST_DOMINATORS
);
9537 PATTERN (tbegin_insn
) = gen_rtx_PARALLEL (VOIDmode
,
9539 XVECEXP (PATTERN (tbegin_insn
), 0, 0),
9540 XVECEXP (PATTERN (tbegin_insn
), 0, 1)));
9541 INSN_CODE (tbegin_insn
) = -1;
9542 df_insn_rescan (tbegin_insn
);
9547 /* Return true if it is legal to put a value with MODE into REGNO. */
9550 s390_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
9552 if (!TARGET_VX
&& VECTOR_NOFP_REGNO_P (regno
))
9555 switch (REGNO_REG_CLASS (regno
))
9558 return ((GET_MODE_CLASS (mode
) == MODE_INT
9559 && s390_class_max_nregs (VEC_REGS
, mode
) == 1)
9561 || s390_vector_mode_supported_p (mode
));
9565 && ((GET_MODE_CLASS (mode
) == MODE_INT
9566 && s390_class_max_nregs (FP_REGS
, mode
) == 1)
9568 || s390_vector_mode_supported_p (mode
)))
9571 if (REGNO_PAIR_OK (regno
, mode
))
9573 if (mode
== SImode
|| mode
== DImode
)
9576 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
9581 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
9586 if (REGNO_PAIR_OK (regno
, mode
))
9589 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
9594 if (GET_MODE_CLASS (mode
) == MODE_CC
)
9598 if (REGNO_PAIR_OK (regno
, mode
))
9600 if (mode
== SImode
|| mode
== Pmode
)
9611 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
9614 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
9616 /* Once we've decided upon a register to use as base register, it must
9617 no longer be used for any other purpose. */
9618 if (cfun
->machine
->base_reg
)
9619 if (REGNO (cfun
->machine
->base_reg
) == old_reg
9620 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
9623 /* Prevent regrename from using call-saved regs which haven't
9624 actually been saved. This is necessary since regrename assumes
9625 the backend save/restore decisions are based on
9626 df_regs_ever_live. Since we have our own routine we have to tell
9627 regrename manually about it. */
9628 if (GENERAL_REGNO_P (new_reg
)
9629 && !call_really_used_regs
[new_reg
]
9630 && cfun_gpr_save_slot (new_reg
) == 0)
9636 /* Return nonzero if register REGNO can be used as a scratch register
9640 s390_hard_regno_scratch_ok (unsigned int regno
)
9642 /* See s390_hard_regno_rename_ok. */
9643 if (GENERAL_REGNO_P (regno
)
9644 && !call_really_used_regs
[regno
]
9645 && cfun_gpr_save_slot (regno
) == 0)
9651 /* Maximum number of registers to represent a value of mode MODE
9652 in a register of class RCLASS. */
9655 s390_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
9658 bool reg_pair_required_p
= false;
9664 reg_size
= TARGET_VX
? 16 : 8;
9666 /* TF and TD modes would fit into a VR but we put them into a
9667 register pair since we do not have 128bit FP instructions on
9670 && SCALAR_FLOAT_MODE_P (mode
)
9671 && GET_MODE_SIZE (mode
) >= 16)
9672 reg_pair_required_p
= true;
9674 /* Even if complex types would fit into a single FPR/VR we force
9675 them into a register pair to deal with the parts more easily.
9676 (FIXME: What about complex ints?) */
9677 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
9678 reg_pair_required_p
= true;
9684 reg_size
= UNITS_PER_WORD
;
9688 if (reg_pair_required_p
)
9689 return 2 * ((GET_MODE_SIZE (mode
) / 2 + reg_size
- 1) / reg_size
);
9691 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
9694 /* Return TRUE if changing mode from FROM to TO should not be allowed
9695 for register class CLASS. */
9698 s390_cannot_change_mode_class (machine_mode from_mode
,
9699 machine_mode to_mode
,
9700 enum reg_class rclass
)
9702 machine_mode small_mode
;
9703 machine_mode big_mode
;
9705 if (GET_MODE_SIZE (from_mode
) == GET_MODE_SIZE (to_mode
))
9708 if (GET_MODE_SIZE (from_mode
) < GET_MODE_SIZE (to_mode
))
9710 small_mode
= from_mode
;
9715 small_mode
= to_mode
;
9716 big_mode
= from_mode
;
9719 /* Values residing in VRs are little-endian style. All modes are
9720 placed left-aligned in an VR. This means that we cannot allow
9721 switching between modes with differing sizes. Also if the vector
9722 facility is available we still place TFmode values in VR register
9723 pairs, since the only instructions we have operating on TFmodes
9724 only deal with register pairs. Therefore we have to allow DFmode
9725 subregs of TFmodes to enable the TFmode splitters. */
9726 if (reg_classes_intersect_p (VEC_REGS
, rclass
)
9727 && (GET_MODE_SIZE (small_mode
) < 8
9728 || s390_class_max_nregs (VEC_REGS
, big_mode
) == 1))
9731 /* Likewise for access registers, since they have only half the
9732 word size on 64-bit. */
9733 if (reg_classes_intersect_p (ACCESS_REGS
, rclass
))
9739 /* Return true if we use LRA instead of reload pass. */
9743 return s390_lra_flag
;
9746 /* Return true if register FROM can be eliminated via register TO. */
9749 s390_can_eliminate (const int from
, const int to
)
9751 /* On zSeries machines, we have not marked the base register as fixed.
9752 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
9753 If a function requires the base register, we say here that this
9754 elimination cannot be performed. This will cause reload to free
9755 up the base register (as if it were fixed). On the other hand,
9756 if the current function does *not* require the base register, we
9757 say here the elimination succeeds, which in turn allows reload
9758 to allocate the base register for any other purpose. */
9759 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
9761 if (TARGET_CPU_ZARCH
)
9763 s390_init_frame_layout ();
9764 return cfun
->machine
->base_reg
== NULL_RTX
;
9770 /* Everything else must point into the stack frame. */
9771 gcc_assert (to
== STACK_POINTER_REGNUM
9772 || to
== HARD_FRAME_POINTER_REGNUM
);
9774 gcc_assert (from
== FRAME_POINTER_REGNUM
9775 || from
== ARG_POINTER_REGNUM
9776 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
9778 /* Make sure we actually saved the return address. */
9779 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
9780 if (!crtl
->calls_eh_return
9782 && !cfun_frame_layout
.save_return_addr_p
)
9788 /* Return offset between register FROM and TO initially after prolog. */
9791 s390_initial_elimination_offset (int from
, int to
)
9793 HOST_WIDE_INT offset
;
9795 /* ??? Why are we called for non-eliminable pairs? */
9796 if (!s390_can_eliminate (from
, to
))
9801 case FRAME_POINTER_REGNUM
:
9802 offset
= (get_frame_size()
9803 + STACK_POINTER_OFFSET
9804 + crtl
->outgoing_args_size
);
9807 case ARG_POINTER_REGNUM
:
9808 s390_init_frame_layout ();
9809 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
9812 case RETURN_ADDRESS_POINTER_REGNUM
:
9813 s390_init_frame_layout ();
9815 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
9817 /* If it turns out that for stdarg nothing went into the reg
9818 save area we also do not need the return address
9820 if (cfun
->stdarg
&& !cfun_save_arg_fprs_p
)
9826 /* In order to make the following work it is not necessary for
9827 r14 to have a save slot. It is sufficient if one other GPR
9828 got one. Since the GPRs are always stored without gaps we
9829 are able to calculate where the r14 save slot would
9831 offset
= (cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
+
9832 (RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
) *
9847 /* Emit insn to save fpr REGNUM at offset OFFSET relative
9848 to register BASE. Return generated insn. */
9851 save_fpr (rtx base
, int offset
, int regnum
)
9854 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
9856 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
9857 set_mem_alias_set (addr
, get_varargs_alias_set ());
9859 set_mem_alias_set (addr
, get_frame_alias_set ());
9861 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
9864 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
9865 to register BASE. Return generated insn. */
9868 restore_fpr (rtx base
, int offset
, int regnum
)
9871 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
9872 set_mem_alias_set (addr
, get_frame_alias_set ());
9874 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
9877 /* Return true if REGNO is a global register, but not one
9878 of the special ones that need to be saved/restored in anyway. */
9881 global_not_special_regno_p (int regno
)
9883 return (global_regs
[regno
]
9884 /* These registers are special and need to be
9885 restored in any case. */
9886 && !(regno
== STACK_POINTER_REGNUM
9887 || regno
== RETURN_REGNUM
9888 || regno
== BASE_REGNUM
9889 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
9892 /* Generate insn to save registers FIRST to LAST into
9893 the register save area located at offset OFFSET
9894 relative to register BASE. */
9897 save_gprs (rtx base
, int offset
, int first
, int last
)
9899 rtx addr
, insn
, note
;
9902 addr
= plus_constant (Pmode
, base
, offset
);
9903 addr
= gen_rtx_MEM (Pmode
, addr
);
9905 set_mem_alias_set (addr
, get_frame_alias_set ());
9907 /* Special-case single register. */
9911 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
9913 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
9915 if (!global_not_special_regno_p (first
))
9916 RTX_FRAME_RELATED_P (insn
) = 1;
9921 insn
= gen_store_multiple (addr
,
9922 gen_rtx_REG (Pmode
, first
),
9923 GEN_INT (last
- first
+ 1));
9925 if (first
<= 6 && cfun
->stdarg
)
9926 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
9928 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
9931 set_mem_alias_set (mem
, get_varargs_alias_set ());
9934 /* We need to set the FRAME_RELATED flag on all SETs
9935 inside the store-multiple pattern.
9937 However, we must not emit DWARF records for registers 2..5
9938 if they are stored for use by variable arguments ...
9940 ??? Unfortunately, it is not enough to simply not the
9941 FRAME_RELATED flags for those SETs, because the first SET
9942 of the PARALLEL is always treated as if it had the flag
9943 set, even if it does not. Therefore we emit a new pattern
9944 without those registers as REG_FRAME_RELATED_EXPR note. */
9946 if (first
>= 6 && !global_not_special_regno_p (first
))
9948 rtx pat
= PATTERN (insn
);
9950 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9951 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
9952 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
9954 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
9956 RTX_FRAME_RELATED_P (insn
) = 1;
9962 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
9963 if (!global_not_special_regno_p (start
))
9969 addr
= plus_constant (Pmode
, base
,
9970 offset
+ (start
- first
) * UNITS_PER_LONG
);
9975 note
= gen_movdi (gen_rtx_MEM (Pmode
, addr
),
9976 gen_rtx_REG (Pmode
, start
));
9978 note
= gen_movsi (gen_rtx_MEM (Pmode
, addr
),
9979 gen_rtx_REG (Pmode
, start
));
9980 note
= PATTERN (note
);
9982 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
9983 RTX_FRAME_RELATED_P (insn
) = 1;
9988 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
9989 gen_rtx_REG (Pmode
, start
),
9990 GEN_INT (last
- start
+ 1));
9991 note
= PATTERN (note
);
9993 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
9995 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
9996 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
9997 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
9999 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
10001 RTX_FRAME_RELATED_P (insn
) = 1;
10007 /* Generate insn to restore registers FIRST to LAST from
10008 the register save area located at offset OFFSET
10009 relative to register BASE. */
10012 restore_gprs (rtx base
, int offset
, int first
, int last
)
10016 addr
= plus_constant (Pmode
, base
, offset
);
10017 addr
= gen_rtx_MEM (Pmode
, addr
);
10018 set_mem_alias_set (addr
, get_frame_alias_set ());
10020 /* Special-case single register. */
10024 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
10026 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
10028 RTX_FRAME_RELATED_P (insn
) = 1;
10032 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
10034 GEN_INT (last
- first
+ 1));
10035 RTX_FRAME_RELATED_P (insn
) = 1;
10039 /* Return insn sequence to load the GOT register. */
10041 static GTY(()) rtx got_symbol
;
10043 s390_load_got (void)
10047 /* We cannot use pic_offset_table_rtx here since we use this
10048 function also for non-pic if __tls_get_offset is called and in
10049 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
10051 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
10055 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
10056 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
10061 if (TARGET_CPU_ZARCH
)
10063 emit_move_insn (got_rtx
, got_symbol
);
10069 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
10070 UNSPEC_LTREL_OFFSET
);
10071 offset
= gen_rtx_CONST (Pmode
, offset
);
10072 offset
= force_const_mem (Pmode
, offset
);
10074 emit_move_insn (got_rtx
, offset
);
10076 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
10077 UNSPEC_LTREL_BASE
);
10078 offset
= gen_rtx_PLUS (Pmode
, got_rtx
, offset
);
10080 emit_move_insn (got_rtx
, offset
);
10083 insns
= get_insns ();
10088 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
10089 and the change to the stack pointer. */
10092 s390_emit_stack_tie (void)
10094 rtx mem
= gen_frame_mem (BLKmode
,
10095 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
10097 emit_insn (gen_stack_tie (mem
));
10100 /* Copy GPRS into FPR save slots. */
10103 s390_save_gprs_to_fprs (void)
10107 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
10110 for (i
= 6; i
< 16; i
++)
10112 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
10115 emit_move_insn (gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)),
10116 gen_rtx_REG (DImode
, i
));
10117 RTX_FRAME_RELATED_P (insn
) = 1;
10122 /* Restore GPRs from FPR save slots. */
10125 s390_restore_gprs_from_fprs (void)
10129 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
10132 for (i
= 6; i
< 16; i
++)
10134 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
10137 emit_move_insn (gen_rtx_REG (DImode
, i
),
10138 gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)));
10139 df_set_regs_ever_live (i
, true);
10140 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (DImode
, i
));
10141 if (i
== STACK_POINTER_REGNUM
)
10142 add_reg_note (insn
, REG_CFA_DEF_CFA
,
10143 plus_constant (Pmode
, stack_pointer_rtx
,
10144 STACK_POINTER_OFFSET
));
10145 RTX_FRAME_RELATED_P (insn
) = 1;
10151 /* A pass run immediately before shrink-wrapping and prologue and epilogue
10156 const pass_data pass_data_s390_early_mach
=
10158 RTL_PASS
, /* type */
10159 "early_mach", /* name */
10160 OPTGROUP_NONE
, /* optinfo_flags */
10161 TV_MACH_DEP
, /* tv_id */
10162 0, /* properties_required */
10163 0, /* properties_provided */
10164 0, /* properties_destroyed */
10165 0, /* todo_flags_start */
10166 ( TODO_df_verify
| TODO_df_finish
), /* todo_flags_finish */
10169 class pass_s390_early_mach
: public rtl_opt_pass
10172 pass_s390_early_mach (gcc::context
*ctxt
)
10173 : rtl_opt_pass (pass_data_s390_early_mach
, ctxt
)
10176 /* opt_pass methods: */
10177 virtual unsigned int execute (function
*);
10179 }; // class pass_s390_early_mach
10182 pass_s390_early_mach::execute (function
*fun
)
10186 /* Try to get rid of the FPR clobbers. */
10187 s390_optimize_nonescaping_tx ();
10189 /* Re-compute register info. */
10190 s390_register_info ();
10192 /* If we're using a base register, ensure that it is always valid for
10193 the first non-prologue instruction. */
10194 if (fun
->machine
->base_reg
)
10195 emit_insn_at_entry (gen_main_pool (fun
->machine
->base_reg
));
10197 /* Annotate all constant pool references to let the scheduler know
10198 they implicitly use the base register. */
10199 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10202 annotate_constant_pool_refs (&PATTERN (insn
));
10203 df_insn_rescan (insn
);
10208 } // anon namespace
10210 /* Expand the prologue into a bunch of separate insns. */
10213 s390_emit_prologue (void)
10221 /* Choose best register to use for temp use within prologue.
10222 See below for why TPF must use the register 1. */
10224 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
10226 && !TARGET_TPF_PROFILING
)
10227 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
10229 temp_reg
= gen_rtx_REG (Pmode
, 1);
10231 s390_save_gprs_to_fprs ();
10233 /* Save call saved gprs. */
10234 if (cfun_frame_layout
.first_save_gpr
!= -1)
10236 insn
= save_gprs (stack_pointer_rtx
,
10237 cfun_frame_layout
.gprs_offset
+
10238 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
10239 - cfun_frame_layout
.first_save_gpr_slot
),
10240 cfun_frame_layout
.first_save_gpr
,
10241 cfun_frame_layout
.last_save_gpr
);
10245 /* Dummy insn to mark literal pool slot. */
10247 if (cfun
->machine
->base_reg
)
10248 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
10250 offset
= cfun_frame_layout
.f0_offset
;
10252 /* Save f0 and f2. */
10253 for (i
= FPR0_REGNUM
; i
<= FPR0_REGNUM
+ 1; i
++)
10255 if (cfun_fpr_save_p (i
))
10257 save_fpr (stack_pointer_rtx
, offset
, i
);
10260 else if (!TARGET_PACKED_STACK
|| cfun
->stdarg
)
10264 /* Save f4 and f6. */
10265 offset
= cfun_frame_layout
.f4_offset
;
10266 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
10268 if (cfun_fpr_save_p (i
))
10270 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
10273 /* If f4 and f6 are call clobbered they are saved due to
10274 stdargs and therefore are not frame related. */
10275 if (!call_really_used_regs
[i
])
10276 RTX_FRAME_RELATED_P (insn
) = 1;
10278 else if (!TARGET_PACKED_STACK
|| call_really_used_regs
[i
])
10282 if (TARGET_PACKED_STACK
10283 && cfun_save_high_fprs_p
10284 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
10286 offset
= (cfun_frame_layout
.f8_offset
10287 + (cfun_frame_layout
.high_fprs
- 1) * 8);
10289 for (i
= FPR15_REGNUM
; i
>= FPR8_REGNUM
&& offset
>= 0; i
--)
10290 if (cfun_fpr_save_p (i
))
10292 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
10294 RTX_FRAME_RELATED_P (insn
) = 1;
10297 if (offset
>= cfun_frame_layout
.f8_offset
)
10301 if (!TARGET_PACKED_STACK
)
10302 next_fpr
= cfun_save_high_fprs_p
? FPR15_REGNUM
: 0;
10304 if (flag_stack_usage_info
)
10305 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
10307 /* Decrement stack pointer. */
10309 if (cfun_frame_layout
.frame_size
> 0)
10311 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
10312 rtx real_frame_off
;
10314 if (s390_stack_size
)
10316 HOST_WIDE_INT stack_guard
;
10318 if (s390_stack_guard
)
10319 stack_guard
= s390_stack_guard
;
10322 /* If no value for stack guard is provided the smallest power of 2
10323 larger than the current frame size is chosen. */
10325 while (stack_guard
< cfun_frame_layout
.frame_size
)
10329 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
10331 warning (0, "frame size of function %qs is %wd"
10332 " bytes exceeding user provided stack limit of "
10334 "An unconditional trap is added.",
10335 current_function_name(), cfun_frame_layout
.frame_size
,
10337 emit_insn (gen_trap ());
10341 /* stack_guard has to be smaller than s390_stack_size.
10342 Otherwise we would emit an AND with zero which would
10343 not match the test under mask pattern. */
10344 if (stack_guard
>= s390_stack_size
)
10346 warning (0, "frame size of function %qs is %wd"
10347 " bytes which is more than half the stack size. "
10348 "The dynamic check would not be reliable. "
10349 "No check emitted for this function.",
10350 current_function_name(),
10351 cfun_frame_layout
.frame_size
);
10355 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
10356 & ~(stack_guard
- 1));
10358 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
10359 GEN_INT (stack_check_mask
));
10361 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
10363 t
, const0_rtx
, const0_rtx
));
10365 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
10367 t
, const0_rtx
, const0_rtx
));
10372 if (s390_warn_framesize
> 0
10373 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
10374 warning (0, "frame size of %qs is %wd bytes",
10375 current_function_name (), cfun_frame_layout
.frame_size
);
10377 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
10378 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
10380 /* Save incoming stack pointer into temp reg. */
10381 if (TARGET_BACKCHAIN
|| next_fpr
)
10382 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
10384 /* Subtract frame size from stack pointer. */
10386 if (DISP_IN_RANGE (INTVAL (frame_off
)))
10388 insn
= gen_rtx_SET (stack_pointer_rtx
,
10389 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
10391 insn
= emit_insn (insn
);
10395 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
10396 frame_off
= force_const_mem (Pmode
, frame_off
);
10398 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
10399 annotate_constant_pool_refs (&PATTERN (insn
));
10402 RTX_FRAME_RELATED_P (insn
) = 1;
10403 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
10404 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
10405 gen_rtx_SET (stack_pointer_rtx
,
10406 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
10409 /* Set backchain. */
10411 if (TARGET_BACKCHAIN
)
10413 if (cfun_frame_layout
.backchain_offset
)
10414 addr
= gen_rtx_MEM (Pmode
,
10415 plus_constant (Pmode
, stack_pointer_rtx
,
10416 cfun_frame_layout
.backchain_offset
));
10418 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
10419 set_mem_alias_set (addr
, get_frame_alias_set ());
10420 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
10423 /* If we support non-call exceptions (e.g. for Java),
10424 we need to make sure the backchain pointer is set up
10425 before any possibly trapping memory access. */
10426 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
10428 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
10429 emit_clobber (addr
);
10433 /* Save fprs 8 - 15 (64 bit ABI). */
10435 if (cfun_save_high_fprs_p
&& next_fpr
)
10437 /* If the stack might be accessed through a different register
10438 we have to make sure that the stack pointer decrement is not
10439 moved below the use of the stack slots. */
10440 s390_emit_stack_tie ();
10442 insn
= emit_insn (gen_add2_insn (temp_reg
,
10443 GEN_INT (cfun_frame_layout
.f8_offset
)));
10447 for (i
= FPR8_REGNUM
; i
<= next_fpr
; i
++)
10448 if (cfun_fpr_save_p (i
))
10450 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
10451 cfun_frame_layout
.frame_size
10452 + cfun_frame_layout
.f8_offset
10455 insn
= save_fpr (temp_reg
, offset
, i
);
10457 RTX_FRAME_RELATED_P (insn
) = 1;
10458 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
10459 gen_rtx_SET (gen_rtx_MEM (DFmode
, addr
),
10460 gen_rtx_REG (DFmode
, i
)));
10464 /* Set frame pointer, if needed. */
10466 if (frame_pointer_needed
)
10468 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10469 RTX_FRAME_RELATED_P (insn
) = 1;
10472 /* Set up got pointer, if needed. */
10474 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
10476 rtx_insn
*insns
= s390_load_got ();
10478 for (rtx_insn
*insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
10479 annotate_constant_pool_refs (&PATTERN (insn
));
10484 if (TARGET_TPF_PROFILING
)
10486 /* Generate a BAS instruction to serve as a function
10487 entry intercept to facilitate the use of tracing
10488 algorithms located at the branch target. */
10489 emit_insn (gen_prologue_tpf ());
10491 /* Emit a blockage here so that all code
10492 lies between the profiling mechanisms. */
10493 emit_insn (gen_blockage ());
10497 /* Expand the epilogue into a bunch of separate insns. */
10500 s390_emit_epilogue (bool sibcall
)
10502 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
10503 int area_bottom
, area_top
, offset
= 0;
10508 if (TARGET_TPF_PROFILING
)
10511 /* Generate a BAS instruction to serve as a function
10512 entry intercept to facilitate the use of tracing
10513 algorithms located at the branch target. */
10515 /* Emit a blockage here so that all code
10516 lies between the profiling mechanisms. */
10517 emit_insn (gen_blockage ());
10519 emit_insn (gen_epilogue_tpf ());
10522 /* Check whether to use frame or stack pointer for restore. */
10524 frame_pointer
= (frame_pointer_needed
10525 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
10527 s390_frame_area (&area_bottom
, &area_top
);
10529 /* Check whether we can access the register save area.
10530 If not, increment the frame pointer as required. */
10532 if (area_top
<= area_bottom
)
10534 /* Nothing to restore. */
10536 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
10537 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
10539 /* Area is in range. */
10540 offset
= cfun_frame_layout
.frame_size
;
10544 rtx insn
, frame_off
, cfa
;
10546 offset
= area_bottom
< 0 ? -area_bottom
: 0;
10547 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
10549 cfa
= gen_rtx_SET (frame_pointer
,
10550 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
10551 if (DISP_IN_RANGE (INTVAL (frame_off
)))
10553 insn
= gen_rtx_SET (frame_pointer
,
10554 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
10555 insn
= emit_insn (insn
);
10559 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
10560 frame_off
= force_const_mem (Pmode
, frame_off
);
10562 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
10563 annotate_constant_pool_refs (&PATTERN (insn
));
10565 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
10566 RTX_FRAME_RELATED_P (insn
) = 1;
10569 /* Restore call saved fprs. */
10573 if (cfun_save_high_fprs_p
)
10575 next_offset
= cfun_frame_layout
.f8_offset
;
10576 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
10578 if (cfun_fpr_save_p (i
))
10580 restore_fpr (frame_pointer
,
10581 offset
+ next_offset
, i
);
10583 = alloc_reg_note (REG_CFA_RESTORE
,
10584 gen_rtx_REG (DFmode
, i
), cfa_restores
);
10593 next_offset
= cfun_frame_layout
.f4_offset
;
10595 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
10597 if (cfun_fpr_save_p (i
))
10599 restore_fpr (frame_pointer
,
10600 offset
+ next_offset
, i
);
10602 = alloc_reg_note (REG_CFA_RESTORE
,
10603 gen_rtx_REG (DFmode
, i
), cfa_restores
);
10606 else if (!TARGET_PACKED_STACK
)
10612 /* Return register. */
10614 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
10616 /* Restore call saved gprs. */
10618 if (cfun_frame_layout
.first_restore_gpr
!= -1)
10623 /* Check for global register and save them
10624 to stack location from where they get restored. */
10626 for (i
= cfun_frame_layout
.first_restore_gpr
;
10627 i
<= cfun_frame_layout
.last_restore_gpr
;
10630 if (global_not_special_regno_p (i
))
10632 addr
= plus_constant (Pmode
, frame_pointer
,
10633 offset
+ cfun_frame_layout
.gprs_offset
10634 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
10636 addr
= gen_rtx_MEM (Pmode
, addr
);
10637 set_mem_alias_set (addr
, get_frame_alias_set ());
10638 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
10642 = alloc_reg_note (REG_CFA_RESTORE
,
10643 gen_rtx_REG (Pmode
, i
), cfa_restores
);
10648 /* Fetch return address from stack before load multiple,
10649 this will do good for scheduling.
10651 Only do this if we already decided that r14 needs to be
10652 saved to a stack slot. (And not just because r14 happens to
10653 be in between two GPRs which need saving.) Otherwise it
10654 would be difficult to take that decision back in
10655 s390_optimize_prologue. */
10656 if (cfun_gpr_save_slot (RETURN_REGNUM
) == -1)
10658 int return_regnum
= find_unused_clobbered_reg();
10659 if (!return_regnum
)
10661 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
10663 addr
= plus_constant (Pmode
, frame_pointer
,
10664 offset
+ cfun_frame_layout
.gprs_offset
10666 - cfun_frame_layout
.first_save_gpr_slot
)
10668 addr
= gen_rtx_MEM (Pmode
, addr
);
10669 set_mem_alias_set (addr
, get_frame_alias_set ());
10670 emit_move_insn (return_reg
, addr
);
10672 /* Once we did that optimization we have to make sure
10673 s390_optimize_prologue does not try to remove the
10674 store of r14 since we will not be able to find the
10675 load issued here. */
10676 cfun_frame_layout
.save_return_addr_p
= true;
10680 insn
= restore_gprs (frame_pointer
,
10681 offset
+ cfun_frame_layout
.gprs_offset
10682 + (cfun_frame_layout
.first_restore_gpr
10683 - cfun_frame_layout
.first_save_gpr_slot
)
10685 cfun_frame_layout
.first_restore_gpr
,
10686 cfun_frame_layout
.last_restore_gpr
);
10687 insn
= emit_insn (insn
);
10688 REG_NOTES (insn
) = cfa_restores
;
10689 add_reg_note (insn
, REG_CFA_DEF_CFA
,
10690 plus_constant (Pmode
, stack_pointer_rtx
,
10691 STACK_POINTER_OFFSET
));
10692 RTX_FRAME_RELATED_P (insn
) = 1;
10695 s390_restore_gprs_from_fprs ();
10700 /* Return to caller. */
10702 p
= rtvec_alloc (2);
10704 RTVEC_ELT (p
, 0) = ret_rtx
;
10705 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
10706 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
10710 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
10713 s300_set_up_by_prologue (hard_reg_set_container
*regs
)
10715 if (cfun
->machine
->base_reg
10716 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
10717 SET_HARD_REG_BIT (regs
->set
, REGNO (cfun
->machine
->base_reg
));
10720 /* Return true if the function can use simple_return to return outside
10721 of a shrink-wrapped region. At present shrink-wrapping is supported
10725 s390_can_use_simple_return_insn (void)
10730 /* Return true if the epilogue is guaranteed to contain only a return
10731 instruction and if a direct return can therefore be used instead.
10732 One of the main advantages of using direct return instructions
10733 is that we can then use conditional returns. */
10736 s390_can_use_return_insn (void)
10740 if (!reload_completed
)
10746 if (TARGET_TPF_PROFILING
)
10749 for (i
= 0; i
< 16; i
++)
10750 if (cfun_gpr_save_slot (i
))
10753 /* For 31 bit this is not covered by the frame_size check below
10754 since f4, f6 are saved in the register save area without needing
10755 additional stack space. */
10757 && (cfun_fpr_save_p (FPR4_REGNUM
) || cfun_fpr_save_p (FPR6_REGNUM
)))
10760 if (cfun
->machine
->base_reg
10761 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
10764 return cfun_frame_layout
.frame_size
== 0;
10767 /* The VX ABI differs for vararg functions. Therefore we need the
10768 prototype of the callee to be available when passing vector type
10770 static const char *
10771 s390_invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
10773 return ((TARGET_VX_ABI
10775 && VECTOR_TYPE_P (TREE_TYPE (val
))
10776 && (funcdecl
== NULL_TREE
10777 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
10778 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
10779 ? N_("Vector argument passed to unprototyped function")
10784 /* Return the size in bytes of a function argument of
10785 type TYPE and/or mode MODE. At least one of TYPE or
10786 MODE must be specified. */
10789 s390_function_arg_size (machine_mode mode
, const_tree type
)
10792 return int_size_in_bytes (type
);
10794 /* No type info available for some library calls ... */
10795 if (mode
!= BLKmode
)
10796 return GET_MODE_SIZE (mode
);
10798 /* If we have neither type nor mode, abort */
10799 gcc_unreachable ();
10802 /* Return true if a function argument of type TYPE and mode MODE
10803 is to be passed in a vector register, if available. */
10806 s390_function_arg_vector (machine_mode mode
, const_tree type
)
10808 if (!TARGET_VX_ABI
)
10811 if (s390_function_arg_size (mode
, type
) > 16)
10814 /* No type info available for some library calls ... */
10816 return VECTOR_MODE_P (mode
);
10818 /* The ABI says that record types with a single member are treated
10819 just like that member would be. */
10820 while (TREE_CODE (type
) == RECORD_TYPE
)
10822 tree field
, single
= NULL_TREE
;
10824 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
10826 if (TREE_CODE (field
) != FIELD_DECL
)
10829 if (single
== NULL_TREE
)
10830 single
= TREE_TYPE (field
);
10835 if (single
== NULL_TREE
)
10839 /* If the field declaration adds extra byte due to
10840 e.g. padding this is not accepted as vector type. */
10841 if (int_size_in_bytes (single
) <= 0
10842 || int_size_in_bytes (single
) != int_size_in_bytes (type
))
10848 return VECTOR_TYPE_P (type
);
10851 /* Return true if a function argument of type TYPE and mode MODE
10852 is to be passed in a floating-point register, if available. */
10855 s390_function_arg_float (machine_mode mode
, const_tree type
)
10857 if (s390_function_arg_size (mode
, type
) > 8)
10860 /* Soft-float changes the ABI: no floating-point registers are used. */
10861 if (TARGET_SOFT_FLOAT
)
10864 /* No type info available for some library calls ... */
10866 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
10868 /* The ABI says that record types with a single member are treated
10869 just like that member would be. */
10870 while (TREE_CODE (type
) == RECORD_TYPE
)
10872 tree field
, single
= NULL_TREE
;
10874 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
10876 if (TREE_CODE (field
) != FIELD_DECL
)
10879 if (single
== NULL_TREE
)
10880 single
= TREE_TYPE (field
);
10885 if (single
== NULL_TREE
)
10891 return TREE_CODE (type
) == REAL_TYPE
;
10894 /* Return true if a function argument of type TYPE and mode MODE
10895 is to be passed in an integer register, or a pair of integer
10896 registers, if available. */
10899 s390_function_arg_integer (machine_mode mode
, const_tree type
)
10901 int size
= s390_function_arg_size (mode
, type
);
10905 /* No type info available for some library calls ... */
10907 return GET_MODE_CLASS (mode
) == MODE_INT
10908 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
10910 /* We accept small integral (and similar) types. */
10911 if (INTEGRAL_TYPE_P (type
)
10912 || POINTER_TYPE_P (type
)
10913 || TREE_CODE (type
) == NULLPTR_TYPE
10914 || TREE_CODE (type
) == OFFSET_TYPE
10915 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
10918 /* We also accept structs of size 1, 2, 4, 8 that are not
10919 passed in floating-point registers. */
10920 if (AGGREGATE_TYPE_P (type
)
10921 && exact_log2 (size
) >= 0
10922 && !s390_function_arg_float (mode
, type
))
10928 /* Return 1 if a function argument of type TYPE and mode MODE
10929 is to be passed by reference. The ABI specifies that only
10930 structures of size 1, 2, 4, or 8 bytes are passed by value,
10931 all other structures (and complex numbers) are passed by
10935 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
10936 machine_mode mode
, const_tree type
,
10937 bool named ATTRIBUTE_UNUSED
)
10939 int size
= s390_function_arg_size (mode
, type
);
10941 if (s390_function_arg_vector (mode
, type
))
10949 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
10952 if (TREE_CODE (type
) == COMPLEX_TYPE
10953 || TREE_CODE (type
) == VECTOR_TYPE
)
10960 /* Update the data in CUM to advance over an argument of mode MODE and
10961 data type TYPE. (TYPE is null for libcalls where that information
10962 may not be available.). The boolean NAMED specifies whether the
10963 argument is a named argument (as opposed to an unnamed argument
10964 matching an ellipsis). */
10967 s390_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
10968 const_tree type
, bool named
)
10970 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10972 if (s390_function_arg_vector (mode
, type
))
10974 /* We are called for unnamed vector stdarg arguments which are
10975 passed on the stack. In this case this hook does not have to
10976 do anything since stack arguments are tracked by common
10982 else if (s390_function_arg_float (mode
, type
))
10986 else if (s390_function_arg_integer (mode
, type
))
10988 int size
= s390_function_arg_size (mode
, type
);
10989 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
10992 gcc_unreachable ();
10995 /* Define where to put the arguments to a function.
10996 Value is zero to push the argument on the stack,
10997 or a hard register in which to store the argument.
10999 MODE is the argument's machine mode.
11000 TYPE is the data type of the argument (as a tree).
11001 This is null for libcalls where that information may
11003 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11004 the preceding args and about the function being called.
11005 NAMED is nonzero if this argument is a named parameter
11006 (otherwise it is an extra parameter matching an ellipsis).
11008 On S/390, we use general purpose registers 2 through 6 to
11009 pass integer, pointer, and certain structure arguments, and
11010 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
11011 to pass floating point arguments. All remaining arguments
11012 are pushed to the stack. */
11015 s390_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
11016 const_tree type
, bool named
)
11018 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11021 s390_check_type_for_vector_abi (type
, true, false);
11023 if (s390_function_arg_vector (mode
, type
))
11025 /* Vector arguments being part of the ellipsis are passed on the
11027 if (!named
|| (cum
->vrs
+ 1 > VEC_ARG_NUM_REG
))
11030 return gen_rtx_REG (mode
, cum
->vrs
+ FIRST_VEC_ARG_REGNO
);
11032 else if (s390_function_arg_float (mode
, type
))
11034 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
11037 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
11039 else if (s390_function_arg_integer (mode
, type
))
11041 int size
= s390_function_arg_size (mode
, type
);
11042 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
11044 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
11046 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
11047 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
11048 else if (n_gprs
== 2)
11050 rtvec p
= rtvec_alloc (2);
11053 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
11056 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
11059 return gen_rtx_PARALLEL (mode
, p
);
11063 /* After the real arguments, expand_call calls us once again
11064 with a void_type_node type. Whatever we return here is
11065 passed as operand 2 to the call expanders.
11067 We don't need this feature ... */
11068 else if (type
== void_type_node
)
11071 gcc_unreachable ();
11074 /* Return true if return values of type TYPE should be returned
11075 in a memory buffer whose address is passed by the caller as
11076 hidden first argument. */
11079 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
11081 /* We accept small integral (and similar) types. */
11082 if (INTEGRAL_TYPE_P (type
)
11083 || POINTER_TYPE_P (type
)
11084 || TREE_CODE (type
) == OFFSET_TYPE
11085 || TREE_CODE (type
) == REAL_TYPE
)
11086 return int_size_in_bytes (type
) > 8;
11088 /* vector types which fit into a VR. */
11090 && VECTOR_TYPE_P (type
)
11091 && int_size_in_bytes (type
) <= 16)
11094 /* Aggregates and similar constructs are always returned
11096 if (AGGREGATE_TYPE_P (type
)
11097 || TREE_CODE (type
) == COMPLEX_TYPE
11098 || VECTOR_TYPE_P (type
))
11101 /* ??? We get called on all sorts of random stuff from
11102 aggregate_value_p. We can't abort, but it's not clear
11103 what's safe to return. Pretend it's a struct I guess. */
11107 /* Function arguments and return values are promoted to word size. */
11109 static machine_mode
11110 s390_promote_function_mode (const_tree type
, machine_mode mode
,
11112 const_tree fntype ATTRIBUTE_UNUSED
,
11113 int for_return ATTRIBUTE_UNUSED
)
11115 if (INTEGRAL_MODE_P (mode
)
11116 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
11118 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
11119 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
11126 /* Define where to return a (scalar) value of type RET_TYPE.
11127 If RET_TYPE is null, define where to return a (scalar)
11128 value of mode MODE from a libcall. */
11131 s390_function_and_libcall_value (machine_mode mode
,
11132 const_tree ret_type
,
11133 const_tree fntype_or_decl
,
11134 bool outgoing ATTRIBUTE_UNUSED
)
11136 /* For vector return types it is important to use the RET_TYPE
11137 argument whenever available since the middle-end might have
11138 changed the mode to a scalar mode. */
11139 bool vector_ret_type_p
= ((ret_type
&& VECTOR_TYPE_P (ret_type
))
11140 || (!ret_type
&& VECTOR_MODE_P (mode
)));
11142 /* For normal functions perform the promotion as
11143 promote_function_mode would do. */
11146 int unsignedp
= TYPE_UNSIGNED (ret_type
);
11147 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
11148 fntype_or_decl
, 1);
11151 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
11152 || SCALAR_FLOAT_MODE_P (mode
)
11153 || (TARGET_VX_ABI
&& vector_ret_type_p
));
11154 gcc_assert (GET_MODE_SIZE (mode
) <= (TARGET_VX_ABI
? 16 : 8));
11156 if (TARGET_VX_ABI
&& vector_ret_type_p
)
11157 return gen_rtx_REG (mode
, FIRST_VEC_ARG_REGNO
);
11158 else if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
11159 return gen_rtx_REG (mode
, 16);
11160 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
11161 || UNITS_PER_LONG
== UNITS_PER_WORD
)
11162 return gen_rtx_REG (mode
, 2);
11163 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
11165 /* This case is triggered when returning a 64 bit value with
11166 -m31 -mzarch. Although the value would fit into a single
11167 register it has to be forced into a 32 bit register pair in
11168 order to match the ABI. */
11169 rtvec p
= rtvec_alloc (2);
11172 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
11174 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
11176 return gen_rtx_PARALLEL (mode
, p
);
11179 gcc_unreachable ();
11182 /* Define where to return a scalar return value of type RET_TYPE. */
11185 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
11188 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
11189 fn_decl_or_type
, outgoing
);
11192 /* Define where to return a scalar libcall return value of mode
11196 s390_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
11198 return s390_function_and_libcall_value (mode
, NULL_TREE
,
11203 /* Create and return the va_list datatype.
11205 On S/390, va_list is an array type equivalent to
11207 typedef struct __va_list_tag
11211 void *__overflow_arg_area;
11212 void *__reg_save_area;
11215 where __gpr and __fpr hold the number of general purpose
11216 or floating point arguments used up to now, respectively,
11217 __overflow_arg_area points to the stack location of the
11218 next argument passed on the stack, and __reg_save_area
11219 always points to the start of the register area in the
11220 call frame of the current function. The function prologue
11221 saves all registers used for argument passing into this
11222 area if the function uses variable arguments. */
11225 s390_build_builtin_va_list (void)
11227 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
11229 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
11232 build_decl (BUILTINS_LOCATION
,
11233 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
11235 f_gpr
= build_decl (BUILTINS_LOCATION
,
11236 FIELD_DECL
, get_identifier ("__gpr"),
11237 long_integer_type_node
);
11238 f_fpr
= build_decl (BUILTINS_LOCATION
,
11239 FIELD_DECL
, get_identifier ("__fpr"),
11240 long_integer_type_node
);
11241 f_ovf
= build_decl (BUILTINS_LOCATION
,
11242 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
11244 f_sav
= build_decl (BUILTINS_LOCATION
,
11245 FIELD_DECL
, get_identifier ("__reg_save_area"),
11248 va_list_gpr_counter_field
= f_gpr
;
11249 va_list_fpr_counter_field
= f_fpr
;
11251 DECL_FIELD_CONTEXT (f_gpr
) = record
;
11252 DECL_FIELD_CONTEXT (f_fpr
) = record
;
11253 DECL_FIELD_CONTEXT (f_ovf
) = record
;
11254 DECL_FIELD_CONTEXT (f_sav
) = record
;
11256 TYPE_STUB_DECL (record
) = type_decl
;
11257 TYPE_NAME (record
) = type_decl
;
11258 TYPE_FIELDS (record
) = f_gpr
;
11259 DECL_CHAIN (f_gpr
) = f_fpr
;
11260 DECL_CHAIN (f_fpr
) = f_ovf
;
11261 DECL_CHAIN (f_ovf
) = f_sav
;
11263 layout_type (record
);
11265 /* The correct type is an array type of one element. */
11266 return build_array_type (record
, build_index_type (size_zero_node
));
11269 /* Implement va_start by filling the va_list structure VALIST.
11270 STDARG_P is always true, and ignored.
11271 NEXTARG points to the first anonymous stack argument.
11273 The following global variables are used to initialize
11274 the va_list structure:
11277 holds number of gprs and fprs used for named arguments.
11278 crtl->args.arg_offset_rtx:
11279 holds the offset of the first anonymous stack argument
11280 (relative to the virtual arg pointer). */
11283 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
11285 HOST_WIDE_INT n_gpr
, n_fpr
;
11287 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
11288 tree gpr
, fpr
, ovf
, sav
, t
;
11290 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11291 f_fpr
= DECL_CHAIN (f_gpr
);
11292 f_ovf
= DECL_CHAIN (f_fpr
);
11293 f_sav
= DECL_CHAIN (f_ovf
);
11295 valist
= build_simple_mem_ref (valist
);
11296 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11297 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
11298 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
11299 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
11301 /* Count number of gp and fp argument registers used. */
11303 n_gpr
= crtl
->args
.info
.gprs
;
11304 n_fpr
= crtl
->args
.info
.fprs
;
11306 if (cfun
->va_list_gpr_size
)
11308 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
11309 build_int_cst (NULL_TREE
, n_gpr
));
11310 TREE_SIDE_EFFECTS (t
) = 1;
11311 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11314 if (cfun
->va_list_fpr_size
)
11316 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
11317 build_int_cst (NULL_TREE
, n_fpr
));
11318 TREE_SIDE_EFFECTS (t
) = 1;
11319 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11322 /* Find the overflow area.
11323 FIXME: This currently is too pessimistic when the vector ABI is
11324 enabled. In that case we *always* set up the overflow area
11326 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
11327 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
11330 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
11332 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
11333 off
= off
< 0 ? 0 : off
;
11334 if (TARGET_DEBUG_ARG
)
11335 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
11336 (int)n_gpr
, (int)n_fpr
, off
);
11338 t
= fold_build_pointer_plus_hwi (t
, off
);
11340 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
11341 TREE_SIDE_EFFECTS (t
) = 1;
11342 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11345 /* Find the register save area. */
11346 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
11347 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
11349 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
11350 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
11352 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
11353 TREE_SIDE_EFFECTS (t
) = 1;
11354 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11358 /* Implement va_arg by updating the va_list structure
11359 VALIST as required to retrieve an argument of type
11360 TYPE, and returning that argument.
11362 Generates code equivalent to:
11364 if (integral value) {
11365 if (size <= 4 && args.gpr < 5 ||
11366 size > 4 && args.gpr < 4 )
11367 ret = args.reg_save_area[args.gpr+8]
11369 ret = *args.overflow_arg_area++;
11370 } else if (vector value) {
11371 ret = *args.overflow_arg_area;
11372 args.overflow_arg_area += size / 8;
11373 } else if (float value) {
11375 ret = args.reg_save_area[args.fpr+64]
11377 ret = *args.overflow_arg_area++;
11378 } else if (aggregate value) {
11380 ret = *args.reg_save_area[args.gpr]
11382 ret = **args.overflow_arg_area++;
11386 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
11387 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
11389 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
11390 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
11391 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
11392 tree lab_false
, lab_over
;
11393 tree addr
= create_tmp_var (ptr_type_node
, "addr");
11394 bool left_align_p
; /* How a value < UNITS_PER_LONG is aligned within
11397 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11398 f_fpr
= DECL_CHAIN (f_gpr
);
11399 f_ovf
= DECL_CHAIN (f_fpr
);
11400 f_sav
= DECL_CHAIN (f_ovf
);
11402 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11403 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
11404 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
11406 /* The tree for args* cannot be shared between gpr/fpr and ovf since
11407 both appear on a lhs. */
11408 valist
= unshare_expr (valist
);
11409 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
11411 size
= int_size_in_bytes (type
);
11413 s390_check_type_for_vector_abi (type
, true, false);
11415 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
11417 if (TARGET_DEBUG_ARG
)
11419 fprintf (stderr
, "va_arg: aggregate type");
11423 /* Aggregates are passed by reference. */
11428 /* kernel stack layout on 31 bit: It is assumed here that no padding
11429 will be added by s390_frame_info because for va_args always an even
11430 number of gprs has to be saved r15-r2 = 14 regs. */
11431 sav_ofs
= 2 * UNITS_PER_LONG
;
11432 sav_scale
= UNITS_PER_LONG
;
11433 size
= UNITS_PER_LONG
;
11434 max_reg
= GP_ARG_NUM_REG
- n_reg
;
11435 left_align_p
= false;
11437 else if (s390_function_arg_vector (TYPE_MODE (type
), type
))
11439 if (TARGET_DEBUG_ARG
)
11441 fprintf (stderr
, "va_arg: vector type");
11451 left_align_p
= true;
11453 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
11455 if (TARGET_DEBUG_ARG
)
11457 fprintf (stderr
, "va_arg: float type");
11461 /* FP args go in FP registers, if present. */
11465 sav_ofs
= 16 * UNITS_PER_LONG
;
11467 max_reg
= FP_ARG_NUM_REG
- n_reg
;
11468 left_align_p
= false;
11472 if (TARGET_DEBUG_ARG
)
11474 fprintf (stderr
, "va_arg: other type");
11478 /* Otherwise into GP registers. */
11481 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
11483 /* kernel stack layout on 31 bit: It is assumed here that no padding
11484 will be added by s390_frame_info because for va_args always an even
11485 number of gprs has to be saved r15-r2 = 14 regs. */
11486 sav_ofs
= 2 * UNITS_PER_LONG
;
11488 if (size
< UNITS_PER_LONG
)
11489 sav_ofs
+= UNITS_PER_LONG
- size
;
11491 sav_scale
= UNITS_PER_LONG
;
11492 max_reg
= GP_ARG_NUM_REG
- n_reg
;
11493 left_align_p
= false;
11496 /* Pull the value out of the saved registers ... */
11498 if (reg
!= NULL_TREE
)
11501 if (reg > ((typeof (reg))max_reg))
11504 addr = sav + sav_ofs + reg * save_scale;
11511 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
11512 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
11514 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
11515 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
11516 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11517 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11518 gimplify_and_add (t
, pre_p
);
11520 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11521 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
11522 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
11523 t
= fold_build_pointer_plus (t
, u
);
11525 gimplify_assign (addr
, t
, pre_p
);
11527 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11529 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
11532 /* ... Otherwise out of the overflow area. */
11535 if (size
< UNITS_PER_LONG
&& !left_align_p
)
11536 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
11538 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11540 gimplify_assign (addr
, t
, pre_p
);
11542 if (size
< UNITS_PER_LONG
&& left_align_p
)
11543 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
);
11545 t
= fold_build_pointer_plus_hwi (t
, size
);
11547 gimplify_assign (ovf
, t
, pre_p
);
11549 if (reg
!= NULL_TREE
)
11550 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
11553 /* Increment register save count. */
11557 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
11558 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
11559 gimplify_and_add (u
, pre_p
);
11564 t
= build_pointer_type_for_mode (build_pointer_type (type
),
11566 addr
= fold_convert (t
, addr
);
11567 addr
= build_va_arg_indirect_ref (addr
);
11571 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
11572 addr
= fold_convert (t
, addr
);
11575 return build_va_arg_indirect_ref (addr
);
11578 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
11580 DEST - Register location where CC will be stored.
11581 TDB - Pointer to a 256 byte area where to store the transaction.
11582 diagnostic block. NULL if TDB is not needed.
11583 RETRY - Retry count value. If non-NULL a retry loop for CC2
11585 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
11586 of the tbegin instruction pattern. */
11589 s390_expand_tbegin (rtx dest
, rtx tdb
, rtx retry
, bool clobber_fprs_p
)
11591 rtx retry_plus_two
= gen_reg_rtx (SImode
);
11592 rtx retry_reg
= gen_reg_rtx (SImode
);
11593 rtx_code_label
*retry_label
= NULL
;
11595 if (retry
!= NULL_RTX
)
11597 emit_move_insn (retry_reg
, retry
);
11598 emit_insn (gen_addsi3 (retry_plus_two
, retry_reg
, const2_rtx
));
11599 emit_insn (gen_addsi3 (retry_reg
, retry_reg
, const1_rtx
));
11600 retry_label
= gen_label_rtx ();
11601 emit_label (retry_label
);
11604 if (clobber_fprs_p
)
11605 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
), tdb
));
11607 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
11610 emit_move_insn (dest
, gen_rtx_UNSPEC (SImode
,
11611 gen_rtvec (1, gen_rtx_REG (CCRAWmode
,
11613 UNSPEC_CC_TO_INT
));
11614 if (retry
!= NULL_RTX
)
11616 const int CC0
= 1 << 3;
11617 const int CC1
= 1 << 2;
11618 const int CC3
= 1 << 0;
11620 rtx count
= gen_reg_rtx (SImode
);
11621 rtx_code_label
*leave_label
= gen_label_rtx ();
11623 /* Exit for success and permanent failures. */
11624 jump
= s390_emit_jump (leave_label
,
11625 gen_rtx_EQ (VOIDmode
,
11626 gen_rtx_REG (CCRAWmode
, CC_REGNUM
),
11627 gen_rtx_CONST_INT (VOIDmode
, CC0
| CC1
| CC3
)));
11628 LABEL_NUSES (leave_label
) = 1;
11630 /* CC2 - transient failure. Perform retry with ppa. */
11631 emit_move_insn (count
, retry_plus_two
);
11632 emit_insn (gen_subsi3 (count
, count
, retry_reg
));
11633 emit_insn (gen_tx_assist (count
));
11634 jump
= emit_jump_insn (gen_doloop_si64 (retry_label
,
11637 JUMP_LABEL (jump
) = retry_label
;
11638 LABEL_NUSES (retry_label
) = 1;
11639 emit_label (leave_label
);
11644 /* Return the decl for the target specific builtin with the function
11648 s390_builtin_decl (unsigned fcode
, bool initialized_p ATTRIBUTE_UNUSED
)
11650 if (fcode
>= S390_BUILTIN_MAX
)
11651 return error_mark_node
;
11653 return s390_builtin_decls
[fcode
];
11656 /* We call mcount before the function prologue. So a profiled leaf
11657 function should stay a leaf function. */
11660 s390_keep_leaf_when_profiled ()
11665 /* Output assembly code for the trampoline template to
11668 On S/390, we use gpr 1 internally in the trampoline code;
11669 gpr 0 is used to hold the static chain. */
11672 s390_asm_trampoline_template (FILE *file
)
11675 op
[0] = gen_rtx_REG (Pmode
, 0);
11676 op
[1] = gen_rtx_REG (Pmode
, 1);
11680 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
11681 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
11682 output_asm_insn ("br\t%1", op
); /* 2 byte */
11683 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
11687 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
11688 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
11689 output_asm_insn ("br\t%1", op
); /* 2 byte */
11690 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
11694 /* Emit RTL insns to initialize the variable parts of a trampoline.
11695 FNADDR is an RTX for the address of the function's pure code.
11696 CXT is an RTX for the static chain value for the function. */
11699 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
11701 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
11704 emit_block_move (m_tramp
, assemble_trampoline_template (),
11705 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
11707 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
11708 emit_move_insn (mem
, cxt
);
11709 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
11710 emit_move_insn (mem
, fnaddr
);
11713 /* Output assembler code to FILE to increment profiler label # LABELNO
11714 for profiling a function entry. */
11717 s390_function_profiler (FILE *file
, int labelno
)
11722 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
11724 fprintf (file
, "# function profiler \n");
11726 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
11727 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
11728 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
11730 op
[2] = gen_rtx_REG (Pmode
, 1);
11731 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
11732 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
11734 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
11737 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
11738 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
11743 output_asm_insn ("stg\t%0,%1", op
);
11744 output_asm_insn ("larl\t%2,%3", op
);
11745 output_asm_insn ("brasl\t%0,%4", op
);
11746 output_asm_insn ("lg\t%0,%1", op
);
11748 else if (!flag_pic
)
11750 op
[6] = gen_label_rtx ();
11752 output_asm_insn ("st\t%0,%1", op
);
11753 output_asm_insn ("bras\t%2,%l6", op
);
11754 output_asm_insn (".long\t%4", op
);
11755 output_asm_insn (".long\t%3", op
);
11756 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
11757 output_asm_insn ("l\t%0,0(%2)", op
);
11758 output_asm_insn ("l\t%2,4(%2)", op
);
11759 output_asm_insn ("basr\t%0,%0", op
);
11760 output_asm_insn ("l\t%0,%1", op
);
11764 op
[5] = gen_label_rtx ();
11765 op
[6] = gen_label_rtx ();
11767 output_asm_insn ("st\t%0,%1", op
);
11768 output_asm_insn ("bras\t%2,%l6", op
);
11769 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
11770 output_asm_insn (".long\t%4-%l5", op
);
11771 output_asm_insn (".long\t%3-%l5", op
);
11772 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
11773 output_asm_insn ("lr\t%0,%2", op
);
11774 output_asm_insn ("a\t%0,0(%2)", op
);
11775 output_asm_insn ("a\t%2,4(%2)", op
);
11776 output_asm_insn ("basr\t%0,%0", op
);
11777 output_asm_insn ("l\t%0,%1", op
);
11781 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
11782 into its SYMBOL_REF_FLAGS. */
11785 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
11787 default_encode_section_info (decl
, rtl
, first
);
11789 if (TREE_CODE (decl
) == VAR_DECL
)
11791 /* If a variable has a forced alignment to < 2 bytes, mark it
11792 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
11794 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
11795 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
11796 if (!DECL_SIZE (decl
)
11797 || !DECL_ALIGN (decl
)
11798 || !tree_fits_shwi_p (DECL_SIZE (decl
))
11799 || (DECL_ALIGN (decl
) <= 64
11800 && DECL_ALIGN (decl
) != tree_to_shwi (DECL_SIZE (decl
))))
11801 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
11804 /* Literal pool references don't have a decl so they are handled
11805 differently here. We rely on the information in the MEM_ALIGN
11806 entry to decide upon natural alignment. */
11808 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
11809 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
11810 && (MEM_ALIGN (rtl
) == 0
11811 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
11812 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
11813 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
11816 /* Output thunk to FILE that implements a C++ virtual function call (with
11817 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
11818 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
11819 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
11820 relative to the resulting this pointer. */
11823 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
11824 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11830 /* Make sure unwind info is emitted for the thunk if needed. */
11831 final_start_function (emit_barrier (), file
, 1);
11833 /* Operand 0 is the target function. */
11834 op
[0] = XEXP (DECL_RTL (function
), 0);
11835 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
11838 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
11839 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
11840 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
11843 /* Operand 1 is the 'this' pointer. */
11844 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11845 op
[1] = gen_rtx_REG (Pmode
, 3);
11847 op
[1] = gen_rtx_REG (Pmode
, 2);
11849 /* Operand 2 is the delta. */
11850 op
[2] = GEN_INT (delta
);
11852 /* Operand 3 is the vcall_offset. */
11853 op
[3] = GEN_INT (vcall_offset
);
11855 /* Operand 4 is the temporary register. */
11856 op
[4] = gen_rtx_REG (Pmode
, 1);
11858 /* Operands 5 to 8 can be used as labels. */
11864 /* Operand 9 can be used for temporary register. */
11867 /* Generate code. */
11870 /* Setup literal pool pointer if required. */
11871 if ((!DISP_IN_RANGE (delta
)
11872 && !CONST_OK_FOR_K (delta
)
11873 && !CONST_OK_FOR_Os (delta
))
11874 || (!DISP_IN_RANGE (vcall_offset
)
11875 && !CONST_OK_FOR_K (vcall_offset
)
11876 && !CONST_OK_FOR_Os (vcall_offset
)))
11878 op
[5] = gen_label_rtx ();
11879 output_asm_insn ("larl\t%4,%5", op
);
11882 /* Add DELTA to this pointer. */
11885 if (CONST_OK_FOR_J (delta
))
11886 output_asm_insn ("la\t%1,%2(%1)", op
);
11887 else if (DISP_IN_RANGE (delta
))
11888 output_asm_insn ("lay\t%1,%2(%1)", op
);
11889 else if (CONST_OK_FOR_K (delta
))
11890 output_asm_insn ("aghi\t%1,%2", op
);
11891 else if (CONST_OK_FOR_Os (delta
))
11892 output_asm_insn ("agfi\t%1,%2", op
);
11895 op
[6] = gen_label_rtx ();
11896 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
11900 /* Perform vcall adjustment. */
11903 if (DISP_IN_RANGE (vcall_offset
))
11905 output_asm_insn ("lg\t%4,0(%1)", op
);
11906 output_asm_insn ("ag\t%1,%3(%4)", op
);
11908 else if (CONST_OK_FOR_K (vcall_offset
))
11910 output_asm_insn ("lghi\t%4,%3", op
);
11911 output_asm_insn ("ag\t%4,0(%1)", op
);
11912 output_asm_insn ("ag\t%1,0(%4)", op
);
11914 else if (CONST_OK_FOR_Os (vcall_offset
))
11916 output_asm_insn ("lgfi\t%4,%3", op
);
11917 output_asm_insn ("ag\t%4,0(%1)", op
);
11918 output_asm_insn ("ag\t%1,0(%4)", op
);
11922 op
[7] = gen_label_rtx ();
11923 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
11924 output_asm_insn ("ag\t%4,0(%1)", op
);
11925 output_asm_insn ("ag\t%1,0(%4)", op
);
11929 /* Jump to target. */
11930 output_asm_insn ("jg\t%0", op
);
11932 /* Output literal pool if required. */
11935 output_asm_insn (".align\t4", op
);
11936 targetm
.asm_out
.internal_label (file
, "L",
11937 CODE_LABEL_NUMBER (op
[5]));
11941 targetm
.asm_out
.internal_label (file
, "L",
11942 CODE_LABEL_NUMBER (op
[6]));
11943 output_asm_insn (".long\t%2", op
);
11947 targetm
.asm_out
.internal_label (file
, "L",
11948 CODE_LABEL_NUMBER (op
[7]));
11949 output_asm_insn (".long\t%3", op
);
11954 /* Setup base pointer if required. */
11956 || (!DISP_IN_RANGE (delta
)
11957 && !CONST_OK_FOR_K (delta
)
11958 && !CONST_OK_FOR_Os (delta
))
11959 || (!DISP_IN_RANGE (delta
)
11960 && !CONST_OK_FOR_K (vcall_offset
)
11961 && !CONST_OK_FOR_Os (vcall_offset
)))
11963 op
[5] = gen_label_rtx ();
11964 output_asm_insn ("basr\t%4,0", op
);
11965 targetm
.asm_out
.internal_label (file
, "L",
11966 CODE_LABEL_NUMBER (op
[5]));
11969 /* Add DELTA to this pointer. */
11972 if (CONST_OK_FOR_J (delta
))
11973 output_asm_insn ("la\t%1,%2(%1)", op
);
11974 else if (DISP_IN_RANGE (delta
))
11975 output_asm_insn ("lay\t%1,%2(%1)", op
);
11976 else if (CONST_OK_FOR_K (delta
))
11977 output_asm_insn ("ahi\t%1,%2", op
);
11978 else if (CONST_OK_FOR_Os (delta
))
11979 output_asm_insn ("afi\t%1,%2", op
);
11982 op
[6] = gen_label_rtx ();
11983 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
11987 /* Perform vcall adjustment. */
11990 if (CONST_OK_FOR_J (vcall_offset
))
11992 output_asm_insn ("l\t%4,0(%1)", op
);
11993 output_asm_insn ("a\t%1,%3(%4)", op
);
11995 else if (DISP_IN_RANGE (vcall_offset
))
11997 output_asm_insn ("l\t%4,0(%1)", op
);
11998 output_asm_insn ("ay\t%1,%3(%4)", op
);
12000 else if (CONST_OK_FOR_K (vcall_offset
))
12002 output_asm_insn ("lhi\t%4,%3", op
);
12003 output_asm_insn ("a\t%4,0(%1)", op
);
12004 output_asm_insn ("a\t%1,0(%4)", op
);
12006 else if (CONST_OK_FOR_Os (vcall_offset
))
12008 output_asm_insn ("iilf\t%4,%3", op
);
12009 output_asm_insn ("a\t%4,0(%1)", op
);
12010 output_asm_insn ("a\t%1,0(%4)", op
);
12014 op
[7] = gen_label_rtx ();
12015 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
12016 output_asm_insn ("a\t%4,0(%1)", op
);
12017 output_asm_insn ("a\t%1,0(%4)", op
);
12020 /* We had to clobber the base pointer register.
12021 Re-setup the base pointer (with a different base). */
12022 op
[5] = gen_label_rtx ();
12023 output_asm_insn ("basr\t%4,0", op
);
12024 targetm
.asm_out
.internal_label (file
, "L",
12025 CODE_LABEL_NUMBER (op
[5]));
12028 /* Jump to target. */
12029 op
[8] = gen_label_rtx ();
12032 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
12033 else if (!nonlocal
)
12034 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12035 /* We cannot call through .plt, since .plt requires %r12 loaded. */
12036 else if (flag_pic
== 1)
12038 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12039 output_asm_insn ("l\t%4,%0(%4)", op
);
12041 else if (flag_pic
== 2)
12043 op
[9] = gen_rtx_REG (Pmode
, 0);
12044 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
12045 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12046 output_asm_insn ("ar\t%4,%9", op
);
12047 output_asm_insn ("l\t%4,0(%4)", op
);
12050 output_asm_insn ("br\t%4", op
);
12052 /* Output literal pool. */
12053 output_asm_insn (".align\t4", op
);
12055 if (nonlocal
&& flag_pic
== 2)
12056 output_asm_insn (".long\t%0", op
);
12059 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
12060 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
12063 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
12065 output_asm_insn (".long\t%0", op
);
12067 output_asm_insn (".long\t%0-%5", op
);
12071 targetm
.asm_out
.internal_label (file
, "L",
12072 CODE_LABEL_NUMBER (op
[6]));
12073 output_asm_insn (".long\t%2", op
);
12077 targetm
.asm_out
.internal_label (file
, "L",
12078 CODE_LABEL_NUMBER (op
[7]));
12079 output_asm_insn (".long\t%3", op
);
12082 final_end_function ();
12086 s390_valid_pointer_mode (machine_mode mode
)
12088 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
12091 /* Checks whether the given CALL_EXPR would use a caller
12092 saved register. This is used to decide whether sibling call
12093 optimization could be performed on the respective function
12097 s390_call_saved_register_used (tree call_expr
)
12099 CUMULATIVE_ARGS cum_v
;
12100 cumulative_args_t cum
;
12107 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
12108 cum
= pack_cumulative_args (&cum_v
);
12110 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
12112 parameter
= CALL_EXPR_ARG (call_expr
, i
);
12113 gcc_assert (parameter
);
12115 /* For an undeclared variable passed as parameter we will get
12116 an ERROR_MARK node here. */
12117 if (TREE_CODE (parameter
) == ERROR_MARK
)
12120 type
= TREE_TYPE (parameter
);
12123 mode
= TYPE_MODE (type
);
12126 /* We assume that in the target function all parameters are
12127 named. This only has an impact on vector argument register
12128 usage none of which is call-saved. */
12129 if (pass_by_reference (&cum_v
, mode
, type
, true))
12132 type
= build_pointer_type (type
);
12135 parm_rtx
= s390_function_arg (cum
, mode
, type
, true);
12137 s390_function_arg_advance (cum
, mode
, type
, true);
12142 if (REG_P (parm_rtx
))
12145 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
12147 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
12151 if (GET_CODE (parm_rtx
) == PARALLEL
)
12155 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
12157 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
12159 gcc_assert (REG_P (r
));
12162 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
12164 if (!call_used_regs
[reg
+ REGNO (r
)])
12173 /* Return true if the given call expression can be
12174 turned into a sibling call.
12175 DECL holds the declaration of the function to be called whereas
12176 EXP is the call expression itself. */
12179 s390_function_ok_for_sibcall (tree decl
, tree exp
)
12181 /* The TPF epilogue uses register 1. */
12182 if (TARGET_TPF_PROFILING
)
12185 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
12186 which would have to be restored before the sibcall. */
12187 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
12190 /* Register 6 on s390 is available as an argument register but unfortunately
12191 "caller saved". This makes functions needing this register for arguments
12192 not suitable for sibcalls. */
12193 return !s390_call_saved_register_used (exp
);
12196 /* Return the fixed registers used for condition codes. */
12199 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
12202 *p2
= INVALID_REGNUM
;
12207 /* This function is used by the call expanders of the machine description.
12208 It emits the call insn itself together with the necessary operations
12209 to adjust the target address and returns the emitted insn.
12210 ADDR_LOCATION is the target address rtx
12211 TLS_CALL the location of the thread-local symbol
12212 RESULT_REG the register where the result of the call should be stored
12213 RETADDR_REG the register where the return address should be stored
12214 If this parameter is NULL_RTX the call is considered
12215 to be a sibling call. */
12218 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
12221 bool plt_call
= false;
12227 /* Direct function calls need special treatment. */
12228 if (GET_CODE (addr_location
) == SYMBOL_REF
)
12230 /* When calling a global routine in PIC mode, we must
12231 replace the symbol itself with the PLT stub. */
12232 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
12234 if (retaddr_reg
!= NULL_RTX
)
12236 addr_location
= gen_rtx_UNSPEC (Pmode
,
12237 gen_rtvec (1, addr_location
),
12239 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
12243 /* For -fpic code the PLT entries might use r12 which is
12244 call-saved. Therefore we cannot do a sibcall when
12245 calling directly using a symbol ref. When reaching
12246 this point we decided (in s390_function_ok_for_sibcall)
12247 to do a sibcall for a function pointer but one of the
12248 optimizers was able to get rid of the function pointer
12249 by propagating the symbol ref into the call. This
12250 optimization is illegal for S/390 so we turn the direct
12251 call into a indirect call again. */
12252 addr_location
= force_reg (Pmode
, addr_location
);
12255 /* Unless we can use the bras(l) insn, force the
12256 routine address into a register. */
12257 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
12260 addr_location
= legitimize_pic_address (addr_location
, 0);
12262 addr_location
= force_reg (Pmode
, addr_location
);
12266 /* If it is already an indirect call or the code above moved the
12267 SYMBOL_REF to somewhere else make sure the address can be found in
12269 if (retaddr_reg
== NULL_RTX
12270 && GET_CODE (addr_location
) != SYMBOL_REF
12273 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
12274 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
12277 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
12278 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
12280 if (result_reg
!= NULL_RTX
)
12281 call
= gen_rtx_SET (result_reg
, call
);
12283 if (retaddr_reg
!= NULL_RTX
)
12285 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
12287 if (tls_call
!= NULL_RTX
)
12288 vec
= gen_rtvec (3, call
, clobber
,
12289 gen_rtx_USE (VOIDmode
, tls_call
));
12291 vec
= gen_rtvec (2, call
, clobber
);
12293 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
12296 insn
= emit_call_insn (call
);
12298 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
12299 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
12301 /* s390_function_ok_for_sibcall should
12302 have denied sibcalls in this case. */
12303 gcc_assert (retaddr_reg
!= NULL_RTX
);
12304 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
12309 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
12312 s390_conditional_register_usage (void)
12318 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12319 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12321 if (TARGET_CPU_ZARCH
)
12323 fixed_regs
[BASE_REGNUM
] = 0;
12324 call_used_regs
[BASE_REGNUM
] = 0;
12325 fixed_regs
[RETURN_REGNUM
] = 0;
12326 call_used_regs
[RETURN_REGNUM
] = 0;
12330 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
12331 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
12335 call_used_regs
[FPR4_REGNUM
] = call_really_used_regs
[FPR4_REGNUM
] = 0;
12336 call_used_regs
[FPR6_REGNUM
] = call_really_used_regs
[FPR6_REGNUM
] = 0;
12339 if (TARGET_SOFT_FLOAT
)
12341 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
12342 call_used_regs
[i
] = fixed_regs
[i
] = 1;
12345 /* Disable v16 - v31 for non-vector target. */
12348 for (i
= VR16_REGNUM
; i
<= VR31_REGNUM
; i
++)
12349 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
12353 /* Corresponding function to eh_return expander. */
12355 static GTY(()) rtx s390_tpf_eh_return_symbol
;
12357 s390_emit_tpf_eh_return (rtx target
)
12362 if (!s390_tpf_eh_return_symbol
)
12363 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
12365 reg
= gen_rtx_REG (Pmode
, 2);
12366 orig_ra
= gen_rtx_REG (Pmode
, 3);
12368 emit_move_insn (reg
, target
);
12369 emit_move_insn (orig_ra
, get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
));
12370 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
12371 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
12372 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
12373 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), orig_ra
);
12375 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
12378 /* Rework the prologue/epilogue to avoid saving/restoring
12379 registers unnecessarily. */
12382 s390_optimize_prologue (void)
12384 rtx_insn
*insn
, *new_insn
, *next_insn
;
12386 /* Do a final recompute of the frame-related data. */
12387 s390_optimize_register_info ();
12389 /* If all special registers are in fact used, there's nothing we
12390 can do, so no point in walking the insn list. */
12392 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
12393 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
12394 && (TARGET_CPU_ZARCH
12395 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
12396 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
12399 /* Search for prologue/epilogue insns and replace them. */
12401 for (insn
= get_insns (); insn
; insn
= next_insn
)
12403 int first
, last
, off
;
12404 rtx set
, base
, offset
;
12407 next_insn
= NEXT_INSN (insn
);
12409 if (! NONJUMP_INSN_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
12412 pat
= PATTERN (insn
);
12414 /* Remove ldgr/lgdr instructions used for saving and restore
12415 GPRs if possible. */
12417 && GET_CODE (pat
) == SET
12418 && GET_MODE (SET_SRC (pat
)) == DImode
12419 && REG_P (SET_SRC (pat
))
12420 && REG_P (SET_DEST (pat
)))
12422 int src_regno
= REGNO (SET_SRC (pat
));
12423 int dest_regno
= REGNO (SET_DEST (pat
));
12427 if (!((GENERAL_REGNO_P (src_regno
) && FP_REGNO_P (dest_regno
))
12428 || (FP_REGNO_P (src_regno
) && GENERAL_REGNO_P (dest_regno
))))
12431 gpr_regno
= GENERAL_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
12432 fpr_regno
= FP_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
12434 /* GPR must be call-saved, FPR must be call-clobbered. */
12435 if (!call_really_used_regs
[fpr_regno
]
12436 || call_really_used_regs
[gpr_regno
])
12439 /* It must not happen that what we once saved in an FPR now
12440 needs a stack slot. */
12441 gcc_assert (cfun_gpr_save_slot (gpr_regno
) != -1);
12443 if (cfun_gpr_save_slot (gpr_regno
) == 0)
12445 remove_insn (insn
);
12450 if (GET_CODE (pat
) == PARALLEL
12451 && store_multiple_operation (pat
, VOIDmode
))
12453 set
= XVECEXP (pat
, 0, 0);
12454 first
= REGNO (SET_SRC (set
));
12455 last
= first
+ XVECLEN (pat
, 0) - 1;
12456 offset
= const0_rtx
;
12457 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
12458 off
= INTVAL (offset
);
12460 if (GET_CODE (base
) != REG
|| off
< 0)
12462 if (cfun_frame_layout
.first_save_gpr
!= -1
12463 && (cfun_frame_layout
.first_save_gpr
< first
12464 || cfun_frame_layout
.last_save_gpr
> last
))
12466 if (REGNO (base
) != STACK_POINTER_REGNUM
12467 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
12469 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
12472 if (cfun_frame_layout
.first_save_gpr
!= -1)
12474 rtx s_pat
= save_gprs (base
,
12475 off
+ (cfun_frame_layout
.first_save_gpr
12476 - first
) * UNITS_PER_LONG
,
12477 cfun_frame_layout
.first_save_gpr
,
12478 cfun_frame_layout
.last_save_gpr
);
12479 new_insn
= emit_insn_before (s_pat
, insn
);
12480 INSN_ADDRESSES_NEW (new_insn
, -1);
12483 remove_insn (insn
);
12487 if (cfun_frame_layout
.first_save_gpr
== -1
12488 && GET_CODE (pat
) == SET
12489 && GENERAL_REG_P (SET_SRC (pat
))
12490 && GET_CODE (SET_DEST (pat
)) == MEM
)
12493 first
= REGNO (SET_SRC (set
));
12494 offset
= const0_rtx
;
12495 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
12496 off
= INTVAL (offset
);
12498 if (GET_CODE (base
) != REG
|| off
< 0)
12500 if (REGNO (base
) != STACK_POINTER_REGNUM
12501 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
12504 remove_insn (insn
);
12508 if (GET_CODE (pat
) == PARALLEL
12509 && load_multiple_operation (pat
, VOIDmode
))
12511 set
= XVECEXP (pat
, 0, 0);
12512 first
= REGNO (SET_DEST (set
));
12513 last
= first
+ XVECLEN (pat
, 0) - 1;
12514 offset
= const0_rtx
;
12515 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
12516 off
= INTVAL (offset
);
12518 if (GET_CODE (base
) != REG
|| off
< 0)
12521 if (cfun_frame_layout
.first_restore_gpr
!= -1
12522 && (cfun_frame_layout
.first_restore_gpr
< first
12523 || cfun_frame_layout
.last_restore_gpr
> last
))
12525 if (REGNO (base
) != STACK_POINTER_REGNUM
12526 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
12528 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
12531 if (cfun_frame_layout
.first_restore_gpr
!= -1)
12533 rtx rpat
= restore_gprs (base
,
12534 off
+ (cfun_frame_layout
.first_restore_gpr
12535 - first
) * UNITS_PER_LONG
,
12536 cfun_frame_layout
.first_restore_gpr
,
12537 cfun_frame_layout
.last_restore_gpr
);
12539 /* Remove REG_CFA_RESTOREs for registers that we no
12540 longer need to save. */
12541 REG_NOTES (rpat
) = REG_NOTES (insn
);
12542 for (rtx
*ptr
= ®_NOTES (rpat
); *ptr
; )
12543 if (REG_NOTE_KIND (*ptr
) == REG_CFA_RESTORE
12544 && ((int) REGNO (XEXP (*ptr
, 0))
12545 < cfun_frame_layout
.first_restore_gpr
))
12546 *ptr
= XEXP (*ptr
, 1);
12548 ptr
= &XEXP (*ptr
, 1);
12549 new_insn
= emit_insn_before (rpat
, insn
);
12550 RTX_FRAME_RELATED_P (new_insn
) = 1;
12551 INSN_ADDRESSES_NEW (new_insn
, -1);
12554 remove_insn (insn
);
12558 if (cfun_frame_layout
.first_restore_gpr
== -1
12559 && GET_CODE (pat
) == SET
12560 && GENERAL_REG_P (SET_DEST (pat
))
12561 && GET_CODE (SET_SRC (pat
)) == MEM
)
12564 first
= REGNO (SET_DEST (set
));
12565 offset
= const0_rtx
;
12566 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
12567 off
= INTVAL (offset
);
12569 if (GET_CODE (base
) != REG
|| off
< 0)
12572 if (REGNO (base
) != STACK_POINTER_REGNUM
12573 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
12576 remove_insn (insn
);
12582 /* On z10 and later the dynamic branch prediction must see the
12583 backward jump within a certain windows. If not it falls back to
12584 the static prediction. This function rearranges the loop backward
12585 branch in a way which makes the static prediction always correct.
12586 The function returns true if it added an instruction. */
12588 s390_fix_long_loop_prediction (rtx_insn
*insn
)
12590 rtx set
= single_set (insn
);
12591 rtx code_label
, label_ref
, new_label
;
12592 rtx_insn
*uncond_jump
;
12593 rtx_insn
*cur_insn
;
12597 /* This will exclude branch on count and branch on index patterns
12598 since these are correctly statically predicted. */
12600 || SET_DEST (set
) != pc_rtx
12601 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
12604 /* Skip conditional returns. */
12605 if (ANY_RETURN_P (XEXP (SET_SRC (set
), 1))
12606 && XEXP (SET_SRC (set
), 2) == pc_rtx
)
12609 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
12610 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
12612 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
12614 code_label
= XEXP (label_ref
, 0);
12616 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
12617 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
12618 || (INSN_ADDRESSES (INSN_UID (insn
))
12619 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
12622 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
12623 distance
< PREDICT_DISTANCE
- 6;
12624 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
12625 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
12628 new_label
= gen_label_rtx ();
12629 uncond_jump
= emit_jump_insn_after (
12630 gen_rtx_SET (pc_rtx
,
12631 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
12633 emit_label_after (new_label
, uncond_jump
);
12635 tmp
= XEXP (SET_SRC (set
), 1);
12636 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
12637 XEXP (SET_SRC (set
), 2) = tmp
;
12638 INSN_CODE (insn
) = -1;
12640 XEXP (label_ref
, 0) = new_label
;
12641 JUMP_LABEL (insn
) = new_label
;
12642 JUMP_LABEL (uncond_jump
) = code_label
;
12647 /* Returns 1 if INSN reads the value of REG for purposes not related
12648 to addressing of memory, and 0 otherwise. */
12650 s390_non_addr_reg_read_p (rtx reg
, rtx_insn
*insn
)
12652 return reg_referenced_p (reg
, PATTERN (insn
))
12653 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
12656 /* Starting from INSN find_cond_jump looks downwards in the insn
12657 stream for a single jump insn which is the last user of the
12658 condition code set in INSN. */
12660 find_cond_jump (rtx_insn
*insn
)
12662 for (; insn
; insn
= NEXT_INSN (insn
))
12666 if (LABEL_P (insn
))
12669 if (!JUMP_P (insn
))
12671 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
12676 /* This will be triggered by a return. */
12677 if (GET_CODE (PATTERN (insn
)) != SET
)
12680 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
12681 ite
= SET_SRC (PATTERN (insn
));
12683 if (GET_CODE (ite
) != IF_THEN_ELSE
)
12686 cc
= XEXP (XEXP (ite
, 0), 0);
12687 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
12690 if (find_reg_note (insn
, REG_DEAD
, cc
))
12698 /* Swap the condition in COND and the operands in OP0 and OP1 so that
12699 the semantics does not change. If NULL_RTX is passed as COND the
12700 function tries to find the conditional jump starting with INSN. */
12702 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx_insn
*insn
)
12706 if (cond
== NULL_RTX
)
12708 rtx_insn
*jump
= find_cond_jump (NEXT_INSN (insn
));
12709 rtx set
= jump
? single_set (jump
) : NULL_RTX
;
12711 if (set
== NULL_RTX
)
12714 cond
= XEXP (SET_SRC (set
), 0);
12719 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
12722 /* On z10, instructions of the compare-and-branch family have the
12723 property to access the register occurring as second operand with
12724 its bits complemented. If such a compare is grouped with a second
12725 instruction that accesses the same register non-complemented, and
12726 if that register's value is delivered via a bypass, then the
12727 pipeline recycles, thereby causing significant performance decline.
12728 This function locates such situations and exchanges the two
12729 operands of the compare. The function return true whenever it
12732 s390_z10_optimize_cmp (rtx_insn
*insn
)
12734 rtx_insn
*prev_insn
, *next_insn
;
12735 bool insn_added_p
= false;
12736 rtx cond
, *op0
, *op1
;
12738 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
12740 /* Handle compare and branch and branch on count
12742 rtx pattern
= single_set (insn
);
12745 || SET_DEST (pattern
) != pc_rtx
12746 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
12749 cond
= XEXP (SET_SRC (pattern
), 0);
12750 op0
= &XEXP (cond
, 0);
12751 op1
= &XEXP (cond
, 1);
12753 else if (GET_CODE (PATTERN (insn
)) == SET
)
12757 /* Handle normal compare instructions. */
12758 src
= SET_SRC (PATTERN (insn
));
12759 dest
= SET_DEST (PATTERN (insn
));
12762 || !CC_REGNO_P (REGNO (dest
))
12763 || GET_CODE (src
) != COMPARE
)
12766 /* s390_swap_cmp will try to find the conditional
12767 jump when passing NULL_RTX as condition. */
12769 op0
= &XEXP (src
, 0);
12770 op1
= &XEXP (src
, 1);
12775 if (!REG_P (*op0
) || !REG_P (*op1
))
12778 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
12781 /* Swap the COMPARE arguments and its mask if there is a
12782 conflicting access in the previous insn. */
12783 prev_insn
= prev_active_insn (insn
);
12784 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
12785 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
12786 s390_swap_cmp (cond
, op0
, op1
, insn
);
12788 /* Check if there is a conflict with the next insn. If there
12789 was no conflict with the previous insn, then swap the
12790 COMPARE arguments and its mask. If we already swapped
12791 the operands, or if swapping them would cause a conflict
12792 with the previous insn, issue a NOP after the COMPARE in
12793 order to separate the two instuctions. */
12794 next_insn
= next_active_insn (insn
);
12795 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
12796 && s390_non_addr_reg_read_p (*op1
, next_insn
))
12798 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
12799 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
12801 if (REGNO (*op1
) == 0)
12802 emit_insn_after (gen_nop1 (), insn
);
12804 emit_insn_after (gen_nop (), insn
);
12805 insn_added_p
= true;
12808 s390_swap_cmp (cond
, op0
, op1
, insn
);
12810 return insn_added_p
;
12813 /* Perform machine-dependent processing. */
12818 bool pool_overflow
= false;
12819 int hw_before
, hw_after
;
12821 /* Make sure all splits have been performed; splits after
12822 machine_dependent_reorg might confuse insn length counts. */
12823 split_all_insns_noflow ();
12825 /* Install the main literal pool and the associated base
12826 register load insns.
12828 In addition, there are two problematic situations we need
12831 - the literal pool might be > 4096 bytes in size, so that
12832 some of its elements cannot be directly accessed
12834 - a branch target might be > 64K away from the branch, so that
12835 it is not possible to use a PC-relative instruction.
12837 To fix those, we split the single literal pool into multiple
12838 pool chunks, reloading the pool base register at various
12839 points throughout the function to ensure it always points to
12840 the pool chunk the following code expects, and / or replace
12841 PC-relative branches by absolute branches.
12843 However, the two problems are interdependent: splitting the
12844 literal pool can move a branch further away from its target,
12845 causing the 64K limit to overflow, and on the other hand,
12846 replacing a PC-relative branch by an absolute branch means
12847 we need to put the branch target address into the literal
12848 pool, possibly causing it to overflow.
12850 So, we loop trying to fix up both problems until we manage
12851 to satisfy both conditions at the same time. Note that the
12852 loop is guaranteed to terminate as every pass of the loop
12853 strictly decreases the total number of PC-relative branches
12854 in the function. (This is not completely true as there
12855 might be branch-over-pool insns introduced by chunkify_start.
12856 Those never need to be split however.) */
12860 struct constant_pool
*pool
= NULL
;
12862 /* Collect the literal pool. */
12863 if (!pool_overflow
)
12865 pool
= s390_mainpool_start ();
12867 pool_overflow
= true;
12870 /* If literal pool overflowed, start to chunkify it. */
12872 pool
= s390_chunkify_start ();
12874 /* Split out-of-range branches. If this has created new
12875 literal pool entries, cancel current chunk list and
12876 recompute it. zSeries machines have large branch
12877 instructions, so we never need to split a branch. */
12878 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
12881 s390_chunkify_cancel (pool
);
12883 s390_mainpool_cancel (pool
);
12888 /* If we made it up to here, both conditions are satisfied.
12889 Finish up literal pool related changes. */
12891 s390_chunkify_finish (pool
);
12893 s390_mainpool_finish (pool
);
12895 /* We're done splitting branches. */
12896 cfun
->machine
->split_branches_pending_p
= false;
12900 /* Generate out-of-pool execute target insns. */
12901 if (TARGET_CPU_ZARCH
)
12903 rtx_insn
*insn
, *target
;
12906 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12908 label
= s390_execute_label (insn
);
12912 gcc_assert (label
!= const0_rtx
);
12914 target
= emit_label (XEXP (label
, 0));
12915 INSN_ADDRESSES_NEW (target
, -1);
12917 target
= emit_insn (s390_execute_target (insn
));
12918 INSN_ADDRESSES_NEW (target
, -1);
12922 /* Try to optimize prologue and epilogue further. */
12923 s390_optimize_prologue ();
12925 /* Walk over the insns and do some >=z10 specific changes. */
12926 if (s390_tune
== PROCESSOR_2097_Z10
12927 || s390_tune
== PROCESSOR_2817_Z196
12928 || s390_tune
== PROCESSOR_2827_ZEC12
12929 || s390_tune
== PROCESSOR_2964_Z13
)
12932 bool insn_added_p
= false;
12934 /* The insn lengths and addresses have to be up to date for the
12935 following manipulations. */
12936 shorten_branches (get_insns ());
12938 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12940 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
12944 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
12946 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
12947 || GET_CODE (PATTERN (insn
)) == SET
)
12948 && s390_tune
== PROCESSOR_2097_Z10
)
12949 insn_added_p
|= s390_z10_optimize_cmp (insn
);
12952 /* Adjust branches if we added new instructions. */
12954 shorten_branches (get_insns ());
12957 s390_function_num_hotpatch_hw (current_function_decl
, &hw_before
, &hw_after
);
12962 /* Insert NOPs for hotpatching. */
12963 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12965 1. inside the area covered by debug information to allow setting
12966 breakpoints at the NOPs,
12967 2. before any insn which results in an asm instruction,
12968 3. before in-function labels to avoid jumping to the NOPs, for
12969 example as part of a loop,
12970 4. before any barrier in case the function is completely empty
12971 (__builtin_unreachable ()) and has neither internal labels nor
12974 if (active_insn_p (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
12976 /* Output a series of NOPs before the first active insn. */
12977 while (insn
&& hw_after
> 0)
12979 if (hw_after
>= 3 && TARGET_CPU_ZARCH
)
12981 emit_insn_before (gen_nop_6_byte (), insn
);
12984 else if (hw_after
>= 2)
12986 emit_insn_before (gen_nop_4_byte (), insn
);
12991 emit_insn_before (gen_nop_2_byte (), insn
);
12998 /* Return true if INSN is a fp load insn writing register REGNO. */
13000 s390_fpload_toreg (rtx_insn
*insn
, unsigned int regno
)
13003 enum attr_type flag
= s390_safe_attr_type (insn
);
13005 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
13008 set
= single_set (insn
);
13010 if (set
== NULL_RTX
)
13013 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
13016 if (REGNO (SET_DEST (set
)) != regno
)
13022 /* This value describes the distance to be avoided between an
13023 aritmetic fp instruction and an fp load writing the same register.
13024 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
13025 fine but the exact value has to be avoided. Otherwise the FP
13026 pipeline will throw an exception causing a major penalty. */
13027 #define Z10_EARLYLOAD_DISTANCE 7
13029 /* Rearrange the ready list in order to avoid the situation described
13030 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
13031 moved to the very end of the ready list. */
13033 s390_z10_prevent_earlyload_conflicts (rtx_insn
**ready
, int *nready_p
)
13035 unsigned int regno
;
13036 int nready
= *nready_p
;
13041 enum attr_type flag
;
13044 /* Skip DISTANCE - 1 active insns. */
13045 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
13046 distance
> 0 && insn
!= NULL_RTX
;
13047 distance
--, insn
= prev_active_insn (insn
))
13048 if (CALL_P (insn
) || JUMP_P (insn
))
13051 if (insn
== NULL_RTX
)
13054 set
= single_set (insn
);
13056 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
13057 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
13060 flag
= s390_safe_attr_type (insn
);
13062 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
13065 regno
= REGNO (SET_DEST (set
));
13068 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
13075 memmove (&ready
[1], &ready
[0], sizeof (rtx_insn
*) * i
);
13080 /* The s390_sched_state variable tracks the state of the current or
13081 the last instruction group.
13083 0,1,2 number of instructions scheduled in the current group
13084 3 the last group is complete - normal insns
13085 4 the last group was a cracked/expanded insn */
13087 static int s390_sched_state
;
13089 #define S390_OOO_SCHED_STATE_NORMAL 3
13090 #define S390_OOO_SCHED_STATE_CRACKED 4
13092 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
13093 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
13094 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
13095 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
13097 static unsigned int
13098 s390_get_sched_attrmask (rtx_insn
*insn
)
13100 unsigned int mask
= 0;
13102 if (get_attr_ooo_cracked (insn
))
13103 mask
|= S390_OOO_SCHED_ATTR_MASK_CRACKED
;
13104 if (get_attr_ooo_expanded (insn
))
13105 mask
|= S390_OOO_SCHED_ATTR_MASK_EXPANDED
;
13106 if (get_attr_ooo_endgroup (insn
))
13107 mask
|= S390_OOO_SCHED_ATTR_MASK_ENDGROUP
;
13108 if (get_attr_ooo_groupalone (insn
))
13109 mask
|= S390_OOO_SCHED_ATTR_MASK_GROUPALONE
;
13113 /* Return the scheduling score for INSN. The higher the score the
13114 better. The score is calculated from the OOO scheduling attributes
13115 of INSN and the scheduling state s390_sched_state. */
13117 s390_sched_score (rtx_insn
*insn
)
13119 unsigned int mask
= s390_get_sched_attrmask (insn
);
13122 switch (s390_sched_state
)
13125 /* Try to put insns into the first slot which would otherwise
13127 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
13128 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
13130 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
13133 /* Prefer not cracked insns while trying to put together a
13135 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
13136 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
13137 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
13139 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) == 0)
13143 /* Prefer not cracked insns while trying to put together a
13145 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
13146 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
13147 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
13149 /* Prefer endgroup insns in the last slot. */
13150 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0)
13153 case S390_OOO_SCHED_STATE_NORMAL
:
13154 /* Prefer not cracked insns if the last was not cracked. */
13155 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
13156 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0)
13158 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
13161 case S390_OOO_SCHED_STATE_CRACKED
:
13162 /* Try to keep cracked insns together to prevent them from
13163 interrupting groups. */
13164 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
13165 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
13172 /* This function is called via hook TARGET_SCHED_REORDER before
13173 issuing one insn from list READY which contains *NREADYP entries.
13174 For target z10 it reorders load instructions to avoid early load
13175 conflicts in the floating point pipeline */
13177 s390_sched_reorder (FILE *file
, int verbose
,
13178 rtx_insn
**ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
13180 if (s390_tune
== PROCESSOR_2097_Z10
)
13181 if (reload_completed
&& *nreadyp
> 1)
13182 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
13184 if ((s390_tune
== PROCESSOR_2827_ZEC12
13185 || s390_tune
== PROCESSOR_2964_Z13
)
13186 && reload_completed
13190 int last_index
= *nreadyp
- 1;
13191 int max_index
= -1;
13192 int max_score
= -1;
13195 /* Just move the insn with the highest score to the top (the
13196 end) of the list. A full sort is not needed since a conflict
13197 in the hazard recognition cannot happen. So the top insn in
13198 the ready list will always be taken. */
13199 for (i
= last_index
; i
>= 0; i
--)
13203 if (recog_memoized (ready
[i
]) < 0)
13206 score
= s390_sched_score (ready
[i
]);
13207 if (score
> max_score
)
13214 if (max_index
!= -1)
13216 if (max_index
!= last_index
)
13218 tmp
= ready
[max_index
];
13219 ready
[max_index
] = ready
[last_index
];
13220 ready
[last_index
] = tmp
;
13224 "move insn %d to the top of list\n",
13225 INSN_UID (ready
[last_index
]));
13227 else if (verbose
> 5)
13229 "best insn %d already on top\n",
13230 INSN_UID (ready
[last_index
]));
13235 fprintf (file
, "ready list ooo attributes - sched state: %d\n",
13238 for (i
= last_index
; i
>= 0; i
--)
13240 if (recog_memoized (ready
[i
]) < 0)
13242 fprintf (file
, "insn %d score: %d: ", INSN_UID (ready
[i
]),
13243 s390_sched_score (ready
[i
]));
13244 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
13245 PRINT_OOO_ATTR (ooo_cracked
);
13246 PRINT_OOO_ATTR (ooo_expanded
);
13247 PRINT_OOO_ATTR (ooo_endgroup
);
13248 PRINT_OOO_ATTR (ooo_groupalone
);
13249 #undef PRINT_OOO_ATTR
13250 fprintf (file
, "\n");
13255 return s390_issue_rate ();
13259 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
13260 the scheduler has issued INSN. It stores the last issued insn into
13261 last_scheduled_insn in order to make it available for
13262 s390_sched_reorder. */
13264 s390_sched_variable_issue (FILE *file
, int verbose
, rtx_insn
*insn
, int more
)
13266 last_scheduled_insn
= insn
;
13268 if ((s390_tune
== PROCESSOR_2827_ZEC12
13269 || s390_tune
== PROCESSOR_2964_Z13
)
13270 && reload_completed
13271 && recog_memoized (insn
) >= 0)
13273 unsigned int mask
= s390_get_sched_attrmask (insn
);
13275 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
13276 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
13277 s390_sched_state
= S390_OOO_SCHED_STATE_CRACKED
;
13278 else if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0
13279 || (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
13280 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
13283 /* Only normal insns are left (mask == 0). */
13284 switch (s390_sched_state
)
13289 case S390_OOO_SCHED_STATE_NORMAL
:
13290 if (s390_sched_state
== S390_OOO_SCHED_STATE_NORMAL
)
13291 s390_sched_state
= 1;
13293 s390_sched_state
++;
13296 case S390_OOO_SCHED_STATE_CRACKED
:
13297 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
13303 fprintf (file
, "insn %d: ", INSN_UID (insn
));
13304 #define PRINT_OOO_ATTR(ATTR) \
13305 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
13306 PRINT_OOO_ATTR (ooo_cracked
);
13307 PRINT_OOO_ATTR (ooo_expanded
);
13308 PRINT_OOO_ATTR (ooo_endgroup
);
13309 PRINT_OOO_ATTR (ooo_groupalone
);
13310 #undef PRINT_OOO_ATTR
13311 fprintf (file
, "\n");
13312 fprintf (file
, "sched state: %d\n", s390_sched_state
);
13316 if (GET_CODE (PATTERN (insn
)) != USE
13317 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
13324 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
13325 int verbose ATTRIBUTE_UNUSED
,
13326 int max_ready ATTRIBUTE_UNUSED
)
13328 last_scheduled_insn
= NULL
;
13329 s390_sched_state
= 0;
13332 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
13333 a new number struct loop *loop should be unrolled if tuned for cpus with
13334 a built-in stride prefetcher.
13335 The loop is analyzed for memory accesses by calling check_dpu for
13336 each rtx of the loop. Depending on the loop_depth and the amount of
13337 memory accesses a new number <=nunroll is returned to improve the
13338 behaviour of the hardware prefetch unit. */
13340 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
13345 unsigned mem_count
= 0;
13347 if (s390_tune
!= PROCESSOR_2097_Z10
13348 && s390_tune
!= PROCESSOR_2817_Z196
13349 && s390_tune
!= PROCESSOR_2827_ZEC12
13350 && s390_tune
!= PROCESSOR_2964_Z13
)
13353 /* Count the number of memory references within the loop body. */
13354 bbs
= get_loop_body (loop
);
13355 subrtx_iterator::array_type array
;
13356 for (i
= 0; i
< loop
->num_nodes
; i
++)
13357 FOR_BB_INSNS (bbs
[i
], insn
)
13358 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
13359 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
13364 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
13365 if (mem_count
== 0)
13368 switch (loop_depth(loop
))
13371 return MIN (nunroll
, 28 / mem_count
);
13373 return MIN (nunroll
, 22 / mem_count
);
13375 return MIN (nunroll
, 16 / mem_count
);
13380 s390_option_override (void)
13383 cl_deferred_option
*opt
;
13384 vec
<cl_deferred_option
> *v
=
13385 (vec
<cl_deferred_option
> *) s390_deferred_options
;
13388 FOR_EACH_VEC_ELT (*v
, i
, opt
)
13390 switch (opt
->opt_index
)
13392 case OPT_mhotpatch_
:
13399 strncpy (s
, opt
->arg
, 256);
13401 t
= strchr (s
, ',');
13406 val1
= integral_argument (s
);
13407 val2
= integral_argument (t
);
13414 if (val1
== -1 || val2
== -1)
13416 /* argument is not a plain number */
13417 error ("arguments to %qs should be non-negative integers",
13421 else if (val1
> s390_hotpatch_hw_max
13422 || val2
> s390_hotpatch_hw_max
)
13424 error ("argument to %qs is too large (max. %d)",
13425 "-mhotpatch=n,m", s390_hotpatch_hw_max
);
13428 s390_hotpatch_hw_before_label
= val1
;
13429 s390_hotpatch_hw_after_label
= val2
;
13433 gcc_unreachable ();
13437 /* Set up function hooks. */
13438 init_machine_status
= s390_init_machine_status
;
13440 /* Architecture mode defaults according to ABI. */
13441 if (!(target_flags_explicit
& MASK_ZARCH
))
13444 target_flags
|= MASK_ZARCH
;
13446 target_flags
&= ~MASK_ZARCH
;
13449 /* Set the march default in case it hasn't been specified on
13451 if (s390_arch
== PROCESSOR_max
)
13453 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
13454 s390_arch
= TARGET_ZARCH
? PROCESSOR_2064_Z900
: PROCESSOR_9672_G5
;
13455 s390_arch_flags
= processor_flags_table
[(int)s390_arch
];
13458 /* Determine processor to tune for. */
13459 if (s390_tune
== PROCESSOR_max
)
13461 s390_tune
= s390_arch
;
13462 s390_tune_flags
= s390_arch_flags
;
13465 /* Sanity checks. */
13466 if (s390_arch
== PROCESSOR_NATIVE
|| s390_tune
== PROCESSOR_NATIVE
)
13467 gcc_unreachable ();
13468 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
13469 error ("z/Architecture mode not supported on %s", s390_arch_string
);
13470 if (TARGET_64BIT
&& !TARGET_ZARCH
)
13471 error ("64-bit ABI not supported in ESA/390 mode");
13473 /* Use hardware DFP if available and not explicitly disabled by
13474 user. E.g. with -m31 -march=z10 -mzarch */
13475 if (!(target_flags_explicit
& MASK_HARD_DFP
) && TARGET_DFP
)
13476 target_flags
|= MASK_HARD_DFP
;
13478 /* Enable hardware transactions if available and not explicitly
13479 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
13480 if (!(target_flags_explicit
& MASK_OPT_HTM
) && TARGET_CPU_HTM
&& TARGET_ZARCH
)
13481 target_flags
|= MASK_OPT_HTM
;
13483 if (target_flags_explicit
& MASK_OPT_VX
)
13487 if (!TARGET_CPU_VX
)
13488 error ("hardware vector support not available on %s",
13490 if (TARGET_SOFT_FLOAT
)
13491 error ("hardware vector support not available with -msoft-float");
13494 else if (TARGET_CPU_VX
)
13495 /* Enable vector support if available and not explicitly disabled
13496 by user. E.g. with -m31 -march=z13 -mzarch */
13497 target_flags
|= MASK_OPT_VX
;
13499 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
13501 if (target_flags_explicit
& MASK_HARD_DFP
)
13503 if (!TARGET_CPU_DFP
)
13504 error ("hardware decimal floating point instructions"
13505 " not available on %s", s390_arch_string
);
13507 error ("hardware decimal floating point instructions"
13508 " not available in ESA/390 mode");
13511 target_flags
&= ~MASK_HARD_DFP
;
13514 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
13516 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
13517 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
13519 target_flags
&= ~MASK_HARD_DFP
;
13522 /* Set processor cost function. */
13525 case PROCESSOR_2084_Z990
:
13526 s390_cost
= &z990_cost
;
13528 case PROCESSOR_2094_Z9_109
:
13529 s390_cost
= &z9_109_cost
;
13531 case PROCESSOR_2097_Z10
:
13532 s390_cost
= &z10_cost
;
13534 case PROCESSOR_2817_Z196
:
13535 s390_cost
= &z196_cost
;
13537 case PROCESSOR_2827_ZEC12
:
13538 case PROCESSOR_2964_Z13
:
13539 s390_cost
= &zEC12_cost
;
13542 s390_cost
= &z900_cost
;
13545 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
13546 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
13549 if (s390_stack_size
)
13551 if (s390_stack_guard
>= s390_stack_size
)
13552 error ("stack size must be greater than the stack guard value");
13553 else if (s390_stack_size
> 1 << 16)
13554 error ("stack size must not be greater than 64k");
13556 else if (s390_stack_guard
)
13557 error ("-mstack-guard implies use of -mstack-size");
13559 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
13560 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
13561 target_flags
|= MASK_LONG_DOUBLE_128
;
13564 if (s390_tune
== PROCESSOR_2097_Z10
13565 || s390_tune
== PROCESSOR_2817_Z196
13566 || s390_tune
== PROCESSOR_2827_ZEC12
13567 || s390_tune
== PROCESSOR_2964_Z13
)
13569 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
13570 global_options
.x_param_values
,
13571 global_options_set
.x_param_values
);
13572 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
13573 global_options
.x_param_values
,
13574 global_options_set
.x_param_values
);
13575 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
13576 global_options
.x_param_values
,
13577 global_options_set
.x_param_values
);
13578 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
13579 global_options
.x_param_values
,
13580 global_options_set
.x_param_values
);
13583 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
13584 global_options
.x_param_values
,
13585 global_options_set
.x_param_values
);
13586 /* values for loop prefetching */
13587 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
13588 global_options
.x_param_values
,
13589 global_options_set
.x_param_values
);
13590 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
13591 global_options
.x_param_values
,
13592 global_options_set
.x_param_values
);
13593 /* s390 has more than 2 levels and the size is much larger. Since
13594 we are always running virtualized assume that we only get a small
13595 part of the caches above l1. */
13596 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
13597 global_options
.x_param_values
,
13598 global_options_set
.x_param_values
);
13599 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
13600 global_options
.x_param_values
,
13601 global_options_set
.x_param_values
);
13602 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
13603 global_options
.x_param_values
,
13604 global_options_set
.x_param_values
);
13606 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
13607 requires the arch flags to be evaluated already. Since prefetching
13608 is beneficial on s390, we enable it if available. */
13609 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
13610 flag_prefetch_loop_arrays
= 1;
13612 /* Use the alternative scheduling-pressure algorithm by default. */
13613 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
13614 global_options
.x_param_values
,
13615 global_options_set
.x_param_values
);
13619 /* Don't emit DWARF3/4 unless specifically selected. The TPF
13620 debuggers do not yet support DWARF 3/4. */
13621 if (!global_options_set
.x_dwarf_strict
)
13623 if (!global_options_set
.x_dwarf_version
)
13627 /* Register a target-specific optimization-and-lowering pass
13628 to run immediately before prologue and epilogue generation.
13630 Registering the pass must be done at start up. It's
13631 convenient to do it here. */
13632 opt_pass
*new_pass
= new pass_s390_early_mach (g
);
13633 struct register_pass_info insert_pass_s390_early_mach
=
13635 new_pass
, /* pass */
13636 "pro_and_epilogue", /* reference_pass_name */
13637 1, /* ref_pass_instance_number */
13638 PASS_POS_INSERT_BEFORE
/* po_op */
13640 register_pass (&insert_pass_s390_early_mach
);
13643 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
13646 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
13647 unsigned int align ATTRIBUTE_UNUSED
,
13648 enum by_pieces_operation op ATTRIBUTE_UNUSED
,
13649 bool speed_p ATTRIBUTE_UNUSED
)
13651 return (size
== 1 || size
== 2
13652 || size
== 4 || (TARGET_ZARCH
&& size
== 8));
13655 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
13658 s390_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
13660 tree sfpc
= s390_builtin_decls
[S390_BUILTIN_s390_sfpc
];
13661 tree efpc
= s390_builtin_decls
[S390_BUILTIN_s390_efpc
];
13662 tree call_efpc
= build_call_expr (efpc
, 0);
13663 tree fenv_var
= create_tmp_var (unsigned_type_node
);
13665 #define FPC_EXCEPTION_MASK HOST_WIDE_INT_UC (0xf8000000)
13666 #define FPC_FLAGS_MASK HOST_WIDE_INT_UC (0x00f80000)
13667 #define FPC_DXC_MASK HOST_WIDE_INT_UC (0x0000ff00)
13668 #define FPC_EXCEPTION_MASK_SHIFT HOST_WIDE_INT_UC (24)
13669 #define FPC_FLAGS_SHIFT HOST_WIDE_INT_UC (16)
13670 #define FPC_DXC_SHIFT HOST_WIDE_INT_UC (8)
13672 /* Generates the equivalent of feholdexcept (&fenv_var)
13674 fenv_var = __builtin_s390_efpc ();
13675 __builtin_s390_sfpc (fenv_var & mask) */
13676 tree old_fpc
= build2 (MODIFY_EXPR
, unsigned_type_node
, fenv_var
, call_efpc
);
13678 build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
13679 build_int_cst (unsigned_type_node
,
13680 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
|
13681 FPC_EXCEPTION_MASK
)));
13682 tree set_new_fpc
= build_call_expr (sfpc
, 1, new_fpc
);
13683 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, old_fpc
, set_new_fpc
);
13685 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT)
13687 __builtin_s390_sfpc (__builtin_s390_efpc () & mask) */
13688 new_fpc
= build2 (BIT_AND_EXPR
, unsigned_type_node
, call_efpc
,
13689 build_int_cst (unsigned_type_node
,
13690 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
)));
13691 *clear
= build_call_expr (sfpc
, 1, new_fpc
);
13693 /* Generates the equivalent of feupdateenv (fenv_var)
13695 old_fpc = __builtin_s390_efpc ();
13696 __builtin_s390_sfpc (fenv_var);
13697 __atomic_feraiseexcept ((old_fpc & FPC_FLAGS_MASK) >> FPC_FLAGS_SHIFT); */
13699 old_fpc
= create_tmp_var (unsigned_type_node
);
13700 tree store_old_fpc
= build2 (MODIFY_EXPR
, void_type_node
,
13701 old_fpc
, call_efpc
);
13703 set_new_fpc
= build_call_expr (sfpc
, 1, fenv_var
);
13705 tree raise_old_except
= build2 (BIT_AND_EXPR
, unsigned_type_node
, old_fpc
,
13706 build_int_cst (unsigned_type_node
,
13708 raise_old_except
= build2 (RSHIFT_EXPR
, unsigned_type_node
, raise_old_except
,
13709 build_int_cst (unsigned_type_node
,
13711 tree atomic_feraiseexcept
13712 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
13713 raise_old_except
= build_call_expr (atomic_feraiseexcept
,
13714 1, raise_old_except
);
13716 *update
= build2 (COMPOUND_EXPR
, void_type_node
,
13717 build2 (COMPOUND_EXPR
, void_type_node
,
13718 store_old_fpc
, set_new_fpc
),
13721 #undef FPC_EXCEPTION_MASK
13722 #undef FPC_FLAGS_MASK
13723 #undef FPC_DXC_MASK
13724 #undef FPC_EXCEPTION_MASK_SHIFT
13725 #undef FPC_FLAGS_SHIFT
13726 #undef FPC_DXC_SHIFT
13729 /* Return the vector mode to be used for inner mode MODE when doing
13731 static machine_mode
13732 s390_preferred_simd_mode (machine_mode mode
)
13752 /* Our hardware does not require vectors to be strictly aligned. */
13754 s390_support_vector_misalignment (machine_mode mode ATTRIBUTE_UNUSED
,
13755 const_tree type ATTRIBUTE_UNUSED
,
13756 int misalignment ATTRIBUTE_UNUSED
,
13757 bool is_packed ATTRIBUTE_UNUSED
)
13762 return default_builtin_support_vector_misalignment (mode
, type
, misalignment
,
13766 /* The vector ABI requires vector types to be aligned on an 8 byte
13767 boundary (our stack alignment). However, we allow this to be
13768 overriden by the user, while this definitely breaks the ABI. */
13769 static HOST_WIDE_INT
13770 s390_vector_alignment (const_tree type
)
13772 if (!TARGET_VX_ABI
)
13773 return default_vector_alignment (type
);
13775 if (TYPE_USER_ALIGN (type
))
13776 return TYPE_ALIGN (type
);
13778 return MIN (64, tree_to_shwi (TYPE_SIZE (type
)));
13781 /* Implement TARGET_ASM_FILE_END. */
13783 s390_asm_file_end (void)
13785 #ifdef HAVE_AS_GNU_ATTRIBUTE
13786 varpool_node
*vnode
;
13787 cgraph_node
*cnode
;
13789 FOR_EACH_VARIABLE (vnode
)
13790 if (TREE_PUBLIC (vnode
->decl
))
13791 s390_check_type_for_vector_abi (TREE_TYPE (vnode
->decl
), false, false);
13793 FOR_EACH_FUNCTION (cnode
)
13794 if (TREE_PUBLIC (cnode
->decl
))
13795 s390_check_type_for_vector_abi (TREE_TYPE (cnode
->decl
), false, false);
13798 if (s390_vector_abi
!= 0)
13799 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
13802 file_end_indicate_exec_stack ();
13805 /* Return true if TYPE is a vector bool type. */
13807 s390_vector_bool_type_p (const_tree type
)
13809 return TYPE_VECTOR_OPAQUE (type
);
13812 /* Return the diagnostic message string if the binary operation OP is
13813 not permitted on TYPE1 and TYPE2, NULL otherwise. */
13815 s390_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
13817 bool bool1_p
, bool2_p
;
13821 machine_mode mode1
, mode2
;
13823 if (!TARGET_ZVECTOR
)
13826 if (!VECTOR_TYPE_P (type1
) || !VECTOR_TYPE_P (type2
))
13829 bool1_p
= s390_vector_bool_type_p (type1
);
13830 bool2_p
= s390_vector_bool_type_p (type2
);
13832 /* Mixing signed and unsigned types is forbidden for all
13834 if (!bool1_p
&& !bool2_p
13835 && TYPE_UNSIGNED (type1
) != TYPE_UNSIGNED (type2
))
13836 return N_("types differ in signess");
13838 plusminus_p
= (op
== PLUS_EXPR
|| op
== MINUS_EXPR
);
13839 muldiv_p
= (op
== MULT_EXPR
|| op
== RDIV_EXPR
|| op
== TRUNC_DIV_EXPR
13840 || op
== CEIL_DIV_EXPR
|| op
== FLOOR_DIV_EXPR
13841 || op
== ROUND_DIV_EXPR
);
13842 compare_p
= (op
== LT_EXPR
|| op
== LE_EXPR
|| op
== GT_EXPR
|| op
== GE_EXPR
13843 || op
== EQ_EXPR
|| op
== NE_EXPR
);
13845 if (bool1_p
&& bool2_p
&& (plusminus_p
|| muldiv_p
))
13846 return N_("binary operator does not support two vector bool operands");
13848 if (bool1_p
!= bool2_p
&& (muldiv_p
|| compare_p
))
13849 return N_("binary operator does not support vector bool operand");
13851 mode1
= TYPE_MODE (type1
);
13852 mode2
= TYPE_MODE (type2
);
13854 if (bool1_p
!= bool2_p
&& plusminus_p
13855 && (GET_MODE_CLASS (mode1
) == MODE_VECTOR_FLOAT
13856 || GET_MODE_CLASS (mode2
) == MODE_VECTOR_FLOAT
))
13857 return N_("binary operator does not support mixing vector "
13858 "bool with floating point vector operands");
13863 /* Initialize GCC target structure. */
13865 #undef TARGET_ASM_ALIGNED_HI_OP
13866 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
13867 #undef TARGET_ASM_ALIGNED_DI_OP
13868 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
13869 #undef TARGET_ASM_INTEGER
13870 #define TARGET_ASM_INTEGER s390_assemble_integer
13872 #undef TARGET_ASM_OPEN_PAREN
13873 #define TARGET_ASM_OPEN_PAREN ""
13875 #undef TARGET_ASM_CLOSE_PAREN
13876 #define TARGET_ASM_CLOSE_PAREN ""
13878 #undef TARGET_OPTION_OVERRIDE
13879 #define TARGET_OPTION_OVERRIDE s390_option_override
13881 #undef TARGET_ENCODE_SECTION_INFO
13882 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
13884 #undef TARGET_SCALAR_MODE_SUPPORTED_P
13885 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
13888 #undef TARGET_HAVE_TLS
13889 #define TARGET_HAVE_TLS true
13891 #undef TARGET_CANNOT_FORCE_CONST_MEM
13892 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
13894 #undef TARGET_DELEGITIMIZE_ADDRESS
13895 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
13897 #undef TARGET_LEGITIMIZE_ADDRESS
13898 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
13900 #undef TARGET_RETURN_IN_MEMORY
13901 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
13903 #undef TARGET_INIT_BUILTINS
13904 #define TARGET_INIT_BUILTINS s390_init_builtins
13905 #undef TARGET_EXPAND_BUILTIN
13906 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
13907 #undef TARGET_BUILTIN_DECL
13908 #define TARGET_BUILTIN_DECL s390_builtin_decl
13910 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
13911 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
13913 #undef TARGET_ASM_OUTPUT_MI_THUNK
13914 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
13915 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
13916 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
13918 #undef TARGET_SCHED_ADJUST_PRIORITY
13919 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
13920 #undef TARGET_SCHED_ISSUE_RATE
13921 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
13922 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
13923 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
13925 #undef TARGET_SCHED_VARIABLE_ISSUE
13926 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
13927 #undef TARGET_SCHED_REORDER
13928 #define TARGET_SCHED_REORDER s390_sched_reorder
13929 #undef TARGET_SCHED_INIT
13930 #define TARGET_SCHED_INIT s390_sched_init
13932 #undef TARGET_CANNOT_COPY_INSN_P
13933 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
13934 #undef TARGET_RTX_COSTS
13935 #define TARGET_RTX_COSTS s390_rtx_costs
13936 #undef TARGET_ADDRESS_COST
13937 #define TARGET_ADDRESS_COST s390_address_cost
13938 #undef TARGET_REGISTER_MOVE_COST
13939 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
13940 #undef TARGET_MEMORY_MOVE_COST
13941 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
13943 #undef TARGET_MACHINE_DEPENDENT_REORG
13944 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
13946 #undef TARGET_VALID_POINTER_MODE
13947 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
13949 #undef TARGET_BUILD_BUILTIN_VA_LIST
13950 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
13951 #undef TARGET_EXPAND_BUILTIN_VA_START
13952 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
13953 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
13954 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
13956 #undef TARGET_PROMOTE_FUNCTION_MODE
13957 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
13958 #undef TARGET_PASS_BY_REFERENCE
13959 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
13961 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
13962 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
13963 #undef TARGET_FUNCTION_ARG
13964 #define TARGET_FUNCTION_ARG s390_function_arg
13965 #undef TARGET_FUNCTION_ARG_ADVANCE
13966 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
13967 #undef TARGET_FUNCTION_VALUE
13968 #define TARGET_FUNCTION_VALUE s390_function_value
13969 #undef TARGET_LIBCALL_VALUE
13970 #define TARGET_LIBCALL_VALUE s390_libcall_value
13971 #undef TARGET_STRICT_ARGUMENT_NAMING
13972 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
13974 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
13975 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
13977 #undef TARGET_FIXED_CONDITION_CODE_REGS
13978 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
13980 #undef TARGET_CC_MODES_COMPATIBLE
13981 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
13983 #undef TARGET_INVALID_WITHIN_DOLOOP
13984 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
13987 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
13988 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
13991 #undef TARGET_DWARF_FRAME_REG_MODE
13992 #define TARGET_DWARF_FRAME_REG_MODE s390_dwarf_frame_reg_mode
13994 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
13995 #undef TARGET_MANGLE_TYPE
13996 #define TARGET_MANGLE_TYPE s390_mangle_type
13999 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14000 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
14002 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14003 #define TARGET_VECTOR_MODE_SUPPORTED_P s390_vector_mode_supported_p
14005 #undef TARGET_PREFERRED_RELOAD_CLASS
14006 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
14008 #undef TARGET_SECONDARY_RELOAD
14009 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
14011 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14012 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
14014 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
14015 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
14017 #undef TARGET_LEGITIMATE_ADDRESS_P
14018 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
14020 #undef TARGET_LEGITIMATE_CONSTANT_P
14021 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
14023 #undef TARGET_LRA_P
14024 #define TARGET_LRA_P s390_lra_p
14026 #undef TARGET_CAN_ELIMINATE
14027 #define TARGET_CAN_ELIMINATE s390_can_eliminate
14029 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14030 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
14032 #undef TARGET_LOOP_UNROLL_ADJUST
14033 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
14035 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14036 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
14037 #undef TARGET_TRAMPOLINE_INIT
14038 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
14040 #undef TARGET_UNWIND_WORD_MODE
14041 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
14043 #undef TARGET_CANONICALIZE_COMPARISON
14044 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
14046 #undef TARGET_HARD_REGNO_SCRATCH_OK
14047 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
14049 #undef TARGET_ATTRIBUTE_TABLE
14050 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
14052 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
14053 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
14055 #undef TARGET_SET_UP_BY_PROLOGUE
14056 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
14058 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14059 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14060 s390_use_by_pieces_infrastructure_p
14062 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14063 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV s390_atomic_assign_expand_fenv
14065 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
14066 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN s390_invalid_arg_for_unprototyped_fn
14068 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14069 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE s390_preferred_simd_mode
14071 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
14072 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT s390_support_vector_misalignment
14074 #undef TARGET_VECTOR_ALIGNMENT
14075 #define TARGET_VECTOR_ALIGNMENT s390_vector_alignment
14077 #undef TARGET_INVALID_BINARY_OP
14078 #define TARGET_INVALID_BINARY_OP s390_invalid_binary_op
14080 #undef TARGET_ASM_FILE_END
14081 #define TARGET_ASM_FILE_END s390_asm_file_end
14083 struct gcc_target targetm
= TARGET_INITIALIZER
;
14085 #include "gt-s390.h"