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s390.c (s390_decompose_address): Reject non-literal pool references in UNSPEC_LTREL_O...
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "integrate.h"
46 #include "ggc.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "debug.h"
50 #include "langhooks.h"
51 #include "optabs.h"
52 #include "gimple.h"
53 #include "df.h"
54 #include "params.h"
55 #include "cfgloop.h"
56
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 static const
226 struct processor_costs z196_cost =
227 {
228 COSTS_N_INSNS (7), /* M */
229 COSTS_N_INSNS (5), /* MGHI */
230 COSTS_N_INSNS (5), /* MH */
231 COSTS_N_INSNS (5), /* MHI */
232 COSTS_N_INSNS (7), /* ML */
233 COSTS_N_INSNS (7), /* MR */
234 COSTS_N_INSNS (6), /* MS */
235 COSTS_N_INSNS (8), /* MSG */
236 COSTS_N_INSNS (6), /* MSGF */
237 COSTS_N_INSNS (6), /* MSGFR */
238 COSTS_N_INSNS (8), /* MSGR */
239 COSTS_N_INSNS (6), /* MSR */
240 COSTS_N_INSNS (1) , /* multiplication in DFmode */
241 COSTS_N_INSNS (40), /* MXBR B+40 */
242 COSTS_N_INSNS (100), /* SQXBR B+100 */
243 COSTS_N_INSNS (42), /* SQDBR B+42 */
244 COSTS_N_INSNS (28), /* SQEBR B+28 */
245 COSTS_N_INSNS (1), /* MADBR B */
246 COSTS_N_INSNS (1), /* MAEBR B */
247 COSTS_N_INSNS (101), /* DXBR B+101 */
248 COSTS_N_INSNS (29), /* DDBR */
249 COSTS_N_INSNS (22), /* DEBR */
250 COSTS_N_INSNS (160), /* DLGR cracked */
251 COSTS_N_INSNS (160), /* DLR cracked */
252 COSTS_N_INSNS (160), /* DR expanded */
253 COSTS_N_INSNS (160), /* DSGFR cracked */
254 COSTS_N_INSNS (160), /* DSGR cracked */
255 };
256
257 extern int reload_completed;
258
259 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
260 static rtx last_scheduled_insn;
261
262 /* Structure used to hold the components of a S/390 memory
263 address. A legitimate address on S/390 is of the general
264 form
265 base + index + displacement
266 where any of the components is optional.
267
268 base and index are registers of the class ADDR_REGS,
269 displacement is an unsigned 12-bit immediate constant. */
270
271 struct s390_address
272 {
273 rtx base;
274 rtx indx;
275 rtx disp;
276 bool pointer;
277 bool literal_pool;
278 };
279
280 /* Which cpu are we tuning for. */
281 enum processor_type s390_tune = PROCESSOR_max;
282 int s390_tune_flags;
283 /* Which instruction set architecture to use. */
284 enum processor_type s390_arch;
285 int s390_arch_flags;
286
287 HOST_WIDE_INT s390_warn_framesize = 0;
288 HOST_WIDE_INT s390_stack_size = 0;
289 HOST_WIDE_INT s390_stack_guard = 0;
290
291 /* The following structure is embedded in the machine
292 specific part of struct function. */
293
294 struct GTY (()) s390_frame_layout
295 {
296 /* Offset within stack frame. */
297 HOST_WIDE_INT gprs_offset;
298 HOST_WIDE_INT f0_offset;
299 HOST_WIDE_INT f4_offset;
300 HOST_WIDE_INT f8_offset;
301 HOST_WIDE_INT backchain_offset;
302
303 /* Number of first and last gpr where slots in the register
304 save area are reserved for. */
305 int first_save_gpr_slot;
306 int last_save_gpr_slot;
307
308 /* Number of first and last gpr to be saved, restored. */
309 int first_save_gpr;
310 int first_restore_gpr;
311 int last_save_gpr;
312 int last_restore_gpr;
313
314 /* Bits standing for floating point registers. Set, if the
315 respective register has to be saved. Starting with reg 16 (f0)
316 at the rightmost bit.
317 Bit 15 - 8 7 6 5 4 3 2 1 0
318 fpr 15 - 8 7 5 3 1 6 4 2 0
319 reg 31 - 24 23 22 21 20 19 18 17 16 */
320 unsigned int fpr_bitmap;
321
322 /* Number of floating point registers f8-f15 which must be saved. */
323 int high_fprs;
324
325 /* Set if return address needs to be saved.
326 This flag is set by s390_return_addr_rtx if it could not use
327 the initial value of r14 and therefore depends on r14 saved
328 to the stack. */
329 bool save_return_addr_p;
330
331 /* Size of stack frame. */
332 HOST_WIDE_INT frame_size;
333 };
334
335 /* Define the structure for the machine field in struct function. */
336
337 struct GTY(()) machine_function
338 {
339 struct s390_frame_layout frame_layout;
340
341 /* Literal pool base register. */
342 rtx base_reg;
343
344 /* True if we may need to perform branch splitting. */
345 bool split_branches_pending_p;
346
347 /* Some local-dynamic TLS symbol name. */
348 const char *some_ld_name;
349
350 bool has_landing_pad_p;
351 };
352
353 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
354
355 #define cfun_frame_layout (cfun->machine->frame_layout)
356 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
357 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
358 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
359 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
360 (1 << (BITNUM)))
361 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
362 (1 << (BITNUM))))
363
364 /* Number of GPRs and FPRs used for argument passing. */
365 #define GP_ARG_NUM_REG 5
366 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
367
368 /* A couple of shortcuts. */
369 #define CONST_OK_FOR_J(x) \
370 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
371 #define CONST_OK_FOR_K(x) \
372 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
373 #define CONST_OK_FOR_Os(x) \
374 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
375 #define CONST_OK_FOR_Op(x) \
376 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
377 #define CONST_OK_FOR_On(x) \
378 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
379
380 #define REGNO_PAIR_OK(REGNO, MODE) \
381 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
382
383 /* That's the read ahead of the dynamic branch prediction unit in
384 bytes on a z10 (or higher) CPU. */
385 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
386
387 static enum machine_mode
388 s390_libgcc_cmp_return_mode (void)
389 {
390 return TARGET_64BIT ? DImode : SImode;
391 }
392
393 static enum machine_mode
394 s390_libgcc_shift_count_mode (void)
395 {
396 return TARGET_64BIT ? DImode : SImode;
397 }
398
399 static enum machine_mode
400 s390_unwind_word_mode (void)
401 {
402 return TARGET_64BIT ? DImode : SImode;
403 }
404
405 /* Return true if the back end supports mode MODE. */
406 static bool
407 s390_scalar_mode_supported_p (enum machine_mode mode)
408 {
409 /* In contrast to the default implementation reject TImode constants on 31bit
410 TARGET_ZARCH for ABI compliance. */
411 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
412 return false;
413
414 if (DECIMAL_FLOAT_MODE_P (mode))
415 return default_decimal_float_supported_p ();
416
417 return default_scalar_mode_supported_p (mode);
418 }
419
420 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
421
422 void
423 s390_set_has_landing_pad_p (bool value)
424 {
425 cfun->machine->has_landing_pad_p = value;
426 }
427
428 /* If two condition code modes are compatible, return a condition code
429 mode which is compatible with both. Otherwise, return
430 VOIDmode. */
431
432 static enum machine_mode
433 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
434 {
435 if (m1 == m2)
436 return m1;
437
438 switch (m1)
439 {
440 case CCZmode:
441 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
442 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
443 return m2;
444 return VOIDmode;
445
446 case CCSmode:
447 case CCUmode:
448 case CCTmode:
449 case CCSRmode:
450 case CCURmode:
451 case CCZ1mode:
452 if (m2 == CCZmode)
453 return m1;
454
455 return VOIDmode;
456
457 default:
458 return VOIDmode;
459 }
460 return VOIDmode;
461 }
462
463 /* Return true if SET either doesn't set the CC register, or else
464 the source and destination have matching CC modes and that
465 CC mode is at least as constrained as REQ_MODE. */
466
467 static bool
468 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
469 {
470 enum machine_mode set_mode;
471
472 gcc_assert (GET_CODE (set) == SET);
473
474 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
475 return 1;
476
477 set_mode = GET_MODE (SET_DEST (set));
478 switch (set_mode)
479 {
480 case CCSmode:
481 case CCSRmode:
482 case CCUmode:
483 case CCURmode:
484 case CCLmode:
485 case CCL1mode:
486 case CCL2mode:
487 case CCL3mode:
488 case CCT1mode:
489 case CCT2mode:
490 case CCT3mode:
491 if (req_mode != set_mode)
492 return 0;
493 break;
494
495 case CCZmode:
496 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
497 && req_mode != CCSRmode && req_mode != CCURmode)
498 return 0;
499 break;
500
501 case CCAPmode:
502 case CCANmode:
503 if (req_mode != CCAmode)
504 return 0;
505 break;
506
507 default:
508 gcc_unreachable ();
509 }
510
511 return (GET_MODE (SET_SRC (set)) == set_mode);
512 }
513
514 /* Return true if every SET in INSN that sets the CC register
515 has source and destination with matching CC modes and that
516 CC mode is at least as constrained as REQ_MODE.
517 If REQ_MODE is VOIDmode, always return false. */
518
519 bool
520 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
521 {
522 int i;
523
524 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
525 if (req_mode == VOIDmode)
526 return false;
527
528 if (GET_CODE (PATTERN (insn)) == SET)
529 return s390_match_ccmode_set (PATTERN (insn), req_mode);
530
531 if (GET_CODE (PATTERN (insn)) == PARALLEL)
532 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
533 {
534 rtx set = XVECEXP (PATTERN (insn), 0, i);
535 if (GET_CODE (set) == SET)
536 if (!s390_match_ccmode_set (set, req_mode))
537 return false;
538 }
539
540 return true;
541 }
542
543 /* If a test-under-mask instruction can be used to implement
544 (compare (and ... OP1) OP2), return the CC mode required
545 to do that. Otherwise, return VOIDmode.
546 MIXED is true if the instruction can distinguish between
547 CC1 and CC2 for mixed selected bits (TMxx), it is false
548 if the instruction cannot (TM). */
549
550 enum machine_mode
551 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
552 {
553 int bit0, bit1;
554
555 /* ??? Fixme: should work on CONST_DOUBLE as well. */
556 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
557 return VOIDmode;
558
559 /* Selected bits all zero: CC0.
560 e.g.: int a; if ((a & (16 + 128)) == 0) */
561 if (INTVAL (op2) == 0)
562 return CCTmode;
563
564 /* Selected bits all one: CC3.
565 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
566 if (INTVAL (op2) == INTVAL (op1))
567 return CCT3mode;
568
569 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
570 int a;
571 if ((a & (16 + 128)) == 16) -> CCT1
572 if ((a & (16 + 128)) == 128) -> CCT2 */
573 if (mixed)
574 {
575 bit1 = exact_log2 (INTVAL (op2));
576 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
577 if (bit0 != -1 && bit1 != -1)
578 return bit0 > bit1 ? CCT1mode : CCT2mode;
579 }
580
581 return VOIDmode;
582 }
583
584 /* Given a comparison code OP (EQ, NE, etc.) and the operands
585 OP0 and OP1 of a COMPARE, return the mode to be used for the
586 comparison. */
587
588 enum machine_mode
589 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
590 {
591 switch (code)
592 {
593 case EQ:
594 case NE:
595 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
596 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
597 return CCAPmode;
598 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
599 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
600 return CCAPmode;
601 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
602 || GET_CODE (op1) == NEG)
603 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
604 return CCLmode;
605
606 if (GET_CODE (op0) == AND)
607 {
608 /* Check whether we can potentially do it via TM. */
609 enum machine_mode ccmode;
610 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
611 if (ccmode != VOIDmode)
612 {
613 /* Relax CCTmode to CCZmode to allow fall-back to AND
614 if that turns out to be beneficial. */
615 return ccmode == CCTmode ? CCZmode : ccmode;
616 }
617 }
618
619 if (register_operand (op0, HImode)
620 && GET_CODE (op1) == CONST_INT
621 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
622 return CCT3mode;
623 if (register_operand (op0, QImode)
624 && GET_CODE (op1) == CONST_INT
625 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
626 return CCT3mode;
627
628 return CCZmode;
629
630 case LE:
631 case LT:
632 case GE:
633 case GT:
634 /* The only overflow condition of NEG and ABS happens when
635 -INT_MAX is used as parameter, which stays negative. So
636 we have an overflow from a positive value to a negative.
637 Using CCAP mode the resulting cc can be used for comparisons. */
638 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
639 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
640 return CCAPmode;
641
642 /* If constants are involved in an add instruction it is possible to use
643 the resulting cc for comparisons with zero. Knowing the sign of the
644 constant the overflow behavior gets predictable. e.g.:
645 int a, b; if ((b = a + c) > 0)
646 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
647 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
648 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
649 {
650 if (INTVAL (XEXP((op0), 1)) < 0)
651 return CCANmode;
652 else
653 return CCAPmode;
654 }
655 /* Fall through. */
656 case UNORDERED:
657 case ORDERED:
658 case UNEQ:
659 case UNLE:
660 case UNLT:
661 case UNGE:
662 case UNGT:
663 case LTGT:
664 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
665 && GET_CODE (op1) != CONST_INT)
666 return CCSRmode;
667 return CCSmode;
668
669 case LTU:
670 case GEU:
671 if (GET_CODE (op0) == PLUS
672 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
673 return CCL1mode;
674
675 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
676 && GET_CODE (op1) != CONST_INT)
677 return CCURmode;
678 return CCUmode;
679
680 case LEU:
681 case GTU:
682 if (GET_CODE (op0) == MINUS
683 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
684 return CCL2mode;
685
686 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
687 && GET_CODE (op1) != CONST_INT)
688 return CCURmode;
689 return CCUmode;
690
691 default:
692 gcc_unreachable ();
693 }
694 }
695
696 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
697 that we can implement more efficiently. */
698
699 void
700 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
701 {
702 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
703 if ((*code == EQ || *code == NE)
704 && *op1 == const0_rtx
705 && GET_CODE (*op0) == ZERO_EXTRACT
706 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
707 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
708 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
709 {
710 rtx inner = XEXP (*op0, 0);
711 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
712 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
713 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
714
715 if (len > 0 && len < modesize
716 && pos >= 0 && pos + len <= modesize
717 && modesize <= HOST_BITS_PER_WIDE_INT)
718 {
719 unsigned HOST_WIDE_INT block;
720 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
721 block <<= modesize - pos - len;
722
723 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
724 gen_int_mode (block, GET_MODE (inner)));
725 }
726 }
727
728 /* Narrow AND of memory against immediate to enable TM. */
729 if ((*code == EQ || *code == NE)
730 && *op1 == const0_rtx
731 && GET_CODE (*op0) == AND
732 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
733 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
734 {
735 rtx inner = XEXP (*op0, 0);
736 rtx mask = XEXP (*op0, 1);
737
738 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
739 if (GET_CODE (inner) == SUBREG
740 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
741 && (GET_MODE_SIZE (GET_MODE (inner))
742 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
743 && ((INTVAL (mask)
744 & GET_MODE_MASK (GET_MODE (inner))
745 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
746 == 0))
747 inner = SUBREG_REG (inner);
748
749 /* Do not change volatile MEMs. */
750 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
751 {
752 int part = s390_single_part (XEXP (*op0, 1),
753 GET_MODE (inner), QImode, 0);
754 if (part >= 0)
755 {
756 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
757 inner = adjust_address_nv (inner, QImode, part);
758 *op0 = gen_rtx_AND (QImode, inner, mask);
759 }
760 }
761 }
762
763 /* Narrow comparisons against 0xffff to HImode if possible. */
764 if ((*code == EQ || *code == NE)
765 && GET_CODE (*op1) == CONST_INT
766 && INTVAL (*op1) == 0xffff
767 && SCALAR_INT_MODE_P (GET_MODE (*op0))
768 && (nonzero_bits (*op0, GET_MODE (*op0))
769 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
770 {
771 *op0 = gen_lowpart (HImode, *op0);
772 *op1 = constm1_rtx;
773 }
774
775 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
776 if (GET_CODE (*op0) == UNSPEC
777 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
778 && XVECLEN (*op0, 0) == 1
779 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
780 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
781 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
782 && *op1 == const0_rtx)
783 {
784 enum rtx_code new_code = UNKNOWN;
785 switch (*code)
786 {
787 case EQ: new_code = EQ; break;
788 case NE: new_code = NE; break;
789 case LT: new_code = GTU; break;
790 case GT: new_code = LTU; break;
791 case LE: new_code = GEU; break;
792 case GE: new_code = LEU; break;
793 default: break;
794 }
795
796 if (new_code != UNKNOWN)
797 {
798 *op0 = XVECEXP (*op0, 0, 0);
799 *code = new_code;
800 }
801 }
802
803 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
804 if (GET_CODE (*op0) == UNSPEC
805 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
806 && XVECLEN (*op0, 0) == 1
807 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
808 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
809 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
810 && *op1 == const0_rtx)
811 {
812 enum rtx_code new_code = UNKNOWN;
813 switch (*code)
814 {
815 case EQ: new_code = EQ; break;
816 case NE: new_code = NE; break;
817 default: break;
818 }
819
820 if (new_code != UNKNOWN)
821 {
822 *op0 = XVECEXP (*op0, 0, 0);
823 *code = new_code;
824 }
825 }
826
827 /* Simplify cascaded EQ, NE with const0_rtx. */
828 if ((*code == NE || *code == EQ)
829 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
830 && GET_MODE (*op0) == SImode
831 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
832 && REG_P (XEXP (*op0, 0))
833 && XEXP (*op0, 1) == const0_rtx
834 && *op1 == const0_rtx)
835 {
836 if ((*code == EQ && GET_CODE (*op0) == NE)
837 || (*code == NE && GET_CODE (*op0) == EQ))
838 *code = EQ;
839 else
840 *code = NE;
841 *op0 = XEXP (*op0, 0);
842 }
843
844 /* Prefer register over memory as first operand. */
845 if (MEM_P (*op0) && REG_P (*op1))
846 {
847 rtx tem = *op0; *op0 = *op1; *op1 = tem;
848 *code = swap_condition (*code);
849 }
850 }
851
852 /* Emit a compare instruction suitable to implement the comparison
853 OP0 CODE OP1. Return the correct condition RTL to be placed in
854 the IF_THEN_ELSE of the conditional branch testing the result. */
855
856 rtx
857 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
858 {
859 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
860 rtx cc;
861
862 /* Do not output a redundant compare instruction if a compare_and_swap
863 pattern already computed the result and the machine modes are compatible. */
864 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
865 {
866 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
867 == GET_MODE (op0));
868 cc = op0;
869 }
870 else
871 {
872 cc = gen_rtx_REG (mode, CC_REGNUM);
873 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
874 }
875
876 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
877 }
878
879 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
880 matches CMP.
881 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
882 conditional branch testing the result. */
883
884 static rtx
885 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
886 {
887 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
888 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
889 }
890
891 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
892 unconditional jump, else a conditional jump under condition COND. */
893
894 void
895 s390_emit_jump (rtx target, rtx cond)
896 {
897 rtx insn;
898
899 target = gen_rtx_LABEL_REF (VOIDmode, target);
900 if (cond)
901 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
902
903 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
904 emit_jump_insn (insn);
905 }
906
907 /* Return branch condition mask to implement a branch
908 specified by CODE. Return -1 for invalid comparisons. */
909
910 int
911 s390_branch_condition_mask (rtx code)
912 {
913 const int CC0 = 1 << 3;
914 const int CC1 = 1 << 2;
915 const int CC2 = 1 << 1;
916 const int CC3 = 1 << 0;
917
918 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
919 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
920 gcc_assert (XEXP (code, 1) == const0_rtx);
921
922 switch (GET_MODE (XEXP (code, 0)))
923 {
924 case CCZmode:
925 case CCZ1mode:
926 switch (GET_CODE (code))
927 {
928 case EQ: return CC0;
929 case NE: return CC1 | CC2 | CC3;
930 default: return -1;
931 }
932 break;
933
934 case CCT1mode:
935 switch (GET_CODE (code))
936 {
937 case EQ: return CC1;
938 case NE: return CC0 | CC2 | CC3;
939 default: return -1;
940 }
941 break;
942
943 case CCT2mode:
944 switch (GET_CODE (code))
945 {
946 case EQ: return CC2;
947 case NE: return CC0 | CC1 | CC3;
948 default: return -1;
949 }
950 break;
951
952 case CCT3mode:
953 switch (GET_CODE (code))
954 {
955 case EQ: return CC3;
956 case NE: return CC0 | CC1 | CC2;
957 default: return -1;
958 }
959 break;
960
961 case CCLmode:
962 switch (GET_CODE (code))
963 {
964 case EQ: return CC0 | CC2;
965 case NE: return CC1 | CC3;
966 default: return -1;
967 }
968 break;
969
970 case CCL1mode:
971 switch (GET_CODE (code))
972 {
973 case LTU: return CC2 | CC3; /* carry */
974 case GEU: return CC0 | CC1; /* no carry */
975 default: return -1;
976 }
977 break;
978
979 case CCL2mode:
980 switch (GET_CODE (code))
981 {
982 case GTU: return CC0 | CC1; /* borrow */
983 case LEU: return CC2 | CC3; /* no borrow */
984 default: return -1;
985 }
986 break;
987
988 case CCL3mode:
989 switch (GET_CODE (code))
990 {
991 case EQ: return CC0 | CC2;
992 case NE: return CC1 | CC3;
993 case LTU: return CC1;
994 case GTU: return CC3;
995 case LEU: return CC1 | CC2;
996 case GEU: return CC2 | CC3;
997 default: return -1;
998 }
999
1000 case CCUmode:
1001 switch (GET_CODE (code))
1002 {
1003 case EQ: return CC0;
1004 case NE: return CC1 | CC2 | CC3;
1005 case LTU: return CC1;
1006 case GTU: return CC2;
1007 case LEU: return CC0 | CC1;
1008 case GEU: return CC0 | CC2;
1009 default: return -1;
1010 }
1011 break;
1012
1013 case CCURmode:
1014 switch (GET_CODE (code))
1015 {
1016 case EQ: return CC0;
1017 case NE: return CC2 | CC1 | CC3;
1018 case LTU: return CC2;
1019 case GTU: return CC1;
1020 case LEU: return CC0 | CC2;
1021 case GEU: return CC0 | CC1;
1022 default: return -1;
1023 }
1024 break;
1025
1026 case CCAPmode:
1027 switch (GET_CODE (code))
1028 {
1029 case EQ: return CC0;
1030 case NE: return CC1 | CC2 | CC3;
1031 case LT: return CC1 | CC3;
1032 case GT: return CC2;
1033 case LE: return CC0 | CC1 | CC3;
1034 case GE: return CC0 | CC2;
1035 default: return -1;
1036 }
1037 break;
1038
1039 case CCANmode:
1040 switch (GET_CODE (code))
1041 {
1042 case EQ: return CC0;
1043 case NE: return CC1 | CC2 | CC3;
1044 case LT: return CC1;
1045 case GT: return CC2 | CC3;
1046 case LE: return CC0 | CC1;
1047 case GE: return CC0 | CC2 | CC3;
1048 default: return -1;
1049 }
1050 break;
1051
1052 case CCSmode:
1053 switch (GET_CODE (code))
1054 {
1055 case EQ: return CC0;
1056 case NE: return CC1 | CC2 | CC3;
1057 case LT: return CC1;
1058 case GT: return CC2;
1059 case LE: return CC0 | CC1;
1060 case GE: return CC0 | CC2;
1061 case UNORDERED: return CC3;
1062 case ORDERED: return CC0 | CC1 | CC2;
1063 case UNEQ: return CC0 | CC3;
1064 case UNLT: return CC1 | CC3;
1065 case UNGT: return CC2 | CC3;
1066 case UNLE: return CC0 | CC1 | CC3;
1067 case UNGE: return CC0 | CC2 | CC3;
1068 case LTGT: return CC1 | CC2;
1069 default: return -1;
1070 }
1071 break;
1072
1073 case CCSRmode:
1074 switch (GET_CODE (code))
1075 {
1076 case EQ: return CC0;
1077 case NE: return CC2 | CC1 | CC3;
1078 case LT: return CC2;
1079 case GT: return CC1;
1080 case LE: return CC0 | CC2;
1081 case GE: return CC0 | CC1;
1082 case UNORDERED: return CC3;
1083 case ORDERED: return CC0 | CC2 | CC1;
1084 case UNEQ: return CC0 | CC3;
1085 case UNLT: return CC2 | CC3;
1086 case UNGT: return CC1 | CC3;
1087 case UNLE: return CC0 | CC2 | CC3;
1088 case UNGE: return CC0 | CC1 | CC3;
1089 case LTGT: return CC2 | CC1;
1090 default: return -1;
1091 }
1092 break;
1093
1094 default:
1095 return -1;
1096 }
1097 }
1098
1099
1100 /* Return branch condition mask to implement a compare and branch
1101 specified by CODE. Return -1 for invalid comparisons. */
1102
1103 int
1104 s390_compare_and_branch_condition_mask (rtx code)
1105 {
1106 const int CC0 = 1 << 3;
1107 const int CC1 = 1 << 2;
1108 const int CC2 = 1 << 1;
1109
1110 switch (GET_CODE (code))
1111 {
1112 case EQ:
1113 return CC0;
1114 case NE:
1115 return CC1 | CC2;
1116 case LT:
1117 case LTU:
1118 return CC1;
1119 case GT:
1120 case GTU:
1121 return CC2;
1122 case LE:
1123 case LEU:
1124 return CC0 | CC1;
1125 case GE:
1126 case GEU:
1127 return CC0 | CC2;
1128 default:
1129 gcc_unreachable ();
1130 }
1131 return -1;
1132 }
1133
1134 /* If INV is false, return assembler mnemonic string to implement
1135 a branch specified by CODE. If INV is true, return mnemonic
1136 for the corresponding inverted branch. */
1137
1138 static const char *
1139 s390_branch_condition_mnemonic (rtx code, int inv)
1140 {
1141 int mask;
1142
1143 static const char *const mnemonic[16] =
1144 {
1145 NULL, "o", "h", "nle",
1146 "l", "nhe", "lh", "ne",
1147 "e", "nlh", "he", "nl",
1148 "le", "nh", "no", NULL
1149 };
1150
1151 if (GET_CODE (XEXP (code, 0)) == REG
1152 && REGNO (XEXP (code, 0)) == CC_REGNUM
1153 && XEXP (code, 1) == const0_rtx)
1154 mask = s390_branch_condition_mask (code);
1155 else
1156 mask = s390_compare_and_branch_condition_mask (code);
1157
1158 gcc_assert (mask >= 0);
1159
1160 if (inv)
1161 mask ^= 15;
1162
1163 gcc_assert (mask >= 1 && mask <= 14);
1164
1165 return mnemonic[mask];
1166 }
1167
1168 /* Return the part of op which has a value different from def.
1169 The size of the part is determined by mode.
1170 Use this function only if you already know that op really
1171 contains such a part. */
1172
1173 unsigned HOST_WIDE_INT
1174 s390_extract_part (rtx op, enum machine_mode mode, int def)
1175 {
1176 unsigned HOST_WIDE_INT value = 0;
1177 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1178 int part_bits = GET_MODE_BITSIZE (mode);
1179 unsigned HOST_WIDE_INT part_mask
1180 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1181 int i;
1182
1183 for (i = 0; i < max_parts; i++)
1184 {
1185 if (i == 0)
1186 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1187 else
1188 value >>= part_bits;
1189
1190 if ((value & part_mask) != (def & part_mask))
1191 return value & part_mask;
1192 }
1193
1194 gcc_unreachable ();
1195 }
1196
1197 /* If OP is an integer constant of mode MODE with exactly one
1198 part of mode PART_MODE unequal to DEF, return the number of that
1199 part. Otherwise, return -1. */
1200
1201 int
1202 s390_single_part (rtx op,
1203 enum machine_mode mode,
1204 enum machine_mode part_mode,
1205 int def)
1206 {
1207 unsigned HOST_WIDE_INT value = 0;
1208 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1209 unsigned HOST_WIDE_INT part_mask
1210 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1211 int i, part = -1;
1212
1213 if (GET_CODE (op) != CONST_INT)
1214 return -1;
1215
1216 for (i = 0; i < n_parts; i++)
1217 {
1218 if (i == 0)
1219 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1220 else
1221 value >>= GET_MODE_BITSIZE (part_mode);
1222
1223 if ((value & part_mask) != (def & part_mask))
1224 {
1225 if (part != -1)
1226 return -1;
1227 else
1228 part = i;
1229 }
1230 }
1231 return part == -1 ? -1 : n_parts - 1 - part;
1232 }
1233
1234 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1235 bits and no other bits are set in IN. POS and LENGTH can be used
1236 to obtain the start position and the length of the bitfield.
1237
1238 POS gives the position of the first bit of the bitfield counting
1239 from the lowest order bit starting with zero. In order to use this
1240 value for S/390 instructions this has to be converted to "bits big
1241 endian" style. */
1242
1243 bool
1244 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1245 int *pos, int *length)
1246 {
1247 int tmp_pos = 0;
1248 int tmp_length = 0;
1249 int i;
1250 unsigned HOST_WIDE_INT mask = 1ULL;
1251 bool contiguous = false;
1252
1253 for (i = 0; i < size; mask <<= 1, i++)
1254 {
1255 if (contiguous)
1256 {
1257 if (mask & in)
1258 tmp_length++;
1259 else
1260 break;
1261 }
1262 else
1263 {
1264 if (mask & in)
1265 {
1266 contiguous = true;
1267 tmp_length++;
1268 }
1269 else
1270 tmp_pos++;
1271 }
1272 }
1273
1274 if (!tmp_length)
1275 return false;
1276
1277 /* Calculate a mask for all bits beyond the contiguous bits. */
1278 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1279
1280 if (mask & in)
1281 return false;
1282
1283 if (tmp_length + tmp_pos - 1 > size)
1284 return false;
1285
1286 if (length)
1287 *length = tmp_length;
1288
1289 if (pos)
1290 *pos = tmp_pos;
1291
1292 return true;
1293 }
1294
1295 /* Check whether we can (and want to) split a double-word
1296 move in mode MODE from SRC to DST into two single-word
1297 moves, moving the subword FIRST_SUBWORD first. */
1298
1299 bool
1300 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1301 {
1302 /* Floating point registers cannot be split. */
1303 if (FP_REG_P (src) || FP_REG_P (dst))
1304 return false;
1305
1306 /* We don't need to split if operands are directly accessible. */
1307 if (s_operand (src, mode) || s_operand (dst, mode))
1308 return false;
1309
1310 /* Non-offsettable memory references cannot be split. */
1311 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1312 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1313 return false;
1314
1315 /* Moving the first subword must not clobber a register
1316 needed to move the second subword. */
1317 if (register_operand (dst, mode))
1318 {
1319 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1320 if (reg_overlap_mentioned_p (subreg, src))
1321 return false;
1322 }
1323
1324 return true;
1325 }
1326
1327 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1328 and [MEM2, MEM2 + SIZE] do overlap and false
1329 otherwise. */
1330
1331 bool
1332 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1333 {
1334 rtx addr1, addr2, addr_delta;
1335 HOST_WIDE_INT delta;
1336
1337 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1338 return true;
1339
1340 if (size == 0)
1341 return false;
1342
1343 addr1 = XEXP (mem1, 0);
1344 addr2 = XEXP (mem2, 0);
1345
1346 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1347
1348 /* This overlapping check is used by peepholes merging memory block operations.
1349 Overlapping operations would otherwise be recognized by the S/390 hardware
1350 and would fall back to a slower implementation. Allowing overlapping
1351 operations would lead to slow code but not to wrong code. Therefore we are
1352 somewhat optimistic if we cannot prove that the memory blocks are
1353 overlapping.
1354 That's why we return false here although this may accept operations on
1355 overlapping memory areas. */
1356 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1357 return false;
1358
1359 delta = INTVAL (addr_delta);
1360
1361 if (delta == 0
1362 || (delta > 0 && delta < size)
1363 || (delta < 0 && -delta < size))
1364 return true;
1365
1366 return false;
1367 }
1368
1369 /* Check whether the address of memory reference MEM2 equals exactly
1370 the address of memory reference MEM1 plus DELTA. Return true if
1371 we can prove this to be the case, false otherwise. */
1372
1373 bool
1374 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1375 {
1376 rtx addr1, addr2, addr_delta;
1377
1378 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1379 return false;
1380
1381 addr1 = XEXP (mem1, 0);
1382 addr2 = XEXP (mem2, 0);
1383
1384 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1385 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1386 return false;
1387
1388 return true;
1389 }
1390
1391 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1392
1393 void
1394 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1395 rtx *operands)
1396 {
1397 enum machine_mode wmode = mode;
1398 rtx dst = operands[0];
1399 rtx src1 = operands[1];
1400 rtx src2 = operands[2];
1401 rtx op, clob, tem;
1402
1403 /* If we cannot handle the operation directly, use a temp register. */
1404 if (!s390_logical_operator_ok_p (operands))
1405 dst = gen_reg_rtx (mode);
1406
1407 /* QImode and HImode patterns make sense only if we have a destination
1408 in memory. Otherwise perform the operation in SImode. */
1409 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1410 wmode = SImode;
1411
1412 /* Widen operands if required. */
1413 if (mode != wmode)
1414 {
1415 if (GET_CODE (dst) == SUBREG
1416 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1417 dst = tem;
1418 else if (REG_P (dst))
1419 dst = gen_rtx_SUBREG (wmode, dst, 0);
1420 else
1421 dst = gen_reg_rtx (wmode);
1422
1423 if (GET_CODE (src1) == SUBREG
1424 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1425 src1 = tem;
1426 else if (GET_MODE (src1) != VOIDmode)
1427 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1428
1429 if (GET_CODE (src2) == SUBREG
1430 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1431 src2 = tem;
1432 else if (GET_MODE (src2) != VOIDmode)
1433 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1434 }
1435
1436 /* Emit the instruction. */
1437 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1438 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1439 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1440
1441 /* Fix up the destination if needed. */
1442 if (dst != operands[0])
1443 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1444 }
1445
1446 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1447
1448 bool
1449 s390_logical_operator_ok_p (rtx *operands)
1450 {
1451 /* If the destination operand is in memory, it needs to coincide
1452 with one of the source operands. After reload, it has to be
1453 the first source operand. */
1454 if (GET_CODE (operands[0]) == MEM)
1455 return rtx_equal_p (operands[0], operands[1])
1456 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1457
1458 return true;
1459 }
1460
1461 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1462 operand IMMOP to switch from SS to SI type instructions. */
1463
1464 void
1465 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1466 {
1467 int def = code == AND ? -1 : 0;
1468 HOST_WIDE_INT mask;
1469 int part;
1470
1471 gcc_assert (GET_CODE (*memop) == MEM);
1472 gcc_assert (!MEM_VOLATILE_P (*memop));
1473
1474 mask = s390_extract_part (*immop, QImode, def);
1475 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1476 gcc_assert (part >= 0);
1477
1478 *memop = adjust_address (*memop, QImode, part);
1479 *immop = gen_int_mode (mask, QImode);
1480 }
1481
1482
1483 /* How to allocate a 'struct machine_function'. */
1484
1485 static struct machine_function *
1486 s390_init_machine_status (void)
1487 {
1488 return ggc_alloc_cleared_machine_function ();
1489 }
1490
1491 /* Change optimizations to be performed, depending on the
1492 optimization level. */
1493
1494 static const struct default_options s390_option_optimization_table[] =
1495 {
1496 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
1497
1498 /* ??? There are apparently still problems with -fcaller-saves. */
1499 { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 },
1500
1501 /* Use MVCLE instructions to decrease code size if requested. */
1502 { OPT_LEVELS_SIZE, OPT_mmvcle, NULL, 1 },
1503
1504 { OPT_LEVELS_NONE, 0, NULL, 0 }
1505 };
1506
1507 /* Implement TARGET_OPTION_INIT_STRUCT. */
1508
1509 static void
1510 s390_option_init_struct (struct gcc_options *opts)
1511 {
1512 /* By default, always emit DWARF-2 unwind info. This allows debugging
1513 without maintaining a stack frame back-chain. */
1514 opts->x_flag_asynchronous_unwind_tables = 1;
1515 }
1516
1517 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1518 to the associated processor_type and processor_flags if so. */
1519
1520 static bool
1521 s390_handle_arch_option (const char *arg,
1522 enum processor_type *type,
1523 int *flags)
1524 {
1525 static struct pta
1526 {
1527 const char *const name; /* processor name or nickname. */
1528 const enum processor_type processor;
1529 const int flags; /* From enum processor_flags. */
1530 }
1531 const processor_alias_table[] =
1532 {
1533 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1534 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1535 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1536 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1537 | PF_LONG_DISPLACEMENT},
1538 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1539 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1540 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1541 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1542 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1543 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1544 {"z196", PROCESSOR_2817_Z196, PF_IEEE_FLOAT | PF_ZARCH
1545 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 },
1546 };
1547 size_t i;
1548
1549 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1550 if (strcmp (arg, processor_alias_table[i].name) == 0)
1551 {
1552 *type = processor_alias_table[i].processor;
1553 *flags = processor_alias_table[i].flags;
1554 return true;
1555 }
1556
1557 *type = PROCESSOR_max;
1558 *flags = 0;
1559 return false;
1560 }
1561
1562 /* Implement TARGET_HANDLE_OPTION. */
1563
1564 static bool
1565 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1566 {
1567 switch (code)
1568 {
1569 case OPT_march_:
1570 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1571
1572 case OPT_mstack_guard_:
1573 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1574 return false;
1575 if (exact_log2 (s390_stack_guard) == -1)
1576 error ("stack guard value must be an exact power of 2");
1577 return true;
1578
1579 case OPT_mstack_size_:
1580 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1581 return false;
1582 if (exact_log2 (s390_stack_size) == -1)
1583 error ("stack size must be an exact power of 2");
1584 return true;
1585
1586 case OPT_mtune_:
1587 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1588
1589 case OPT_mwarn_framesize_:
1590 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1591
1592 default:
1593 return true;
1594 }
1595 }
1596
1597 static void
1598 s390_option_override (void)
1599 {
1600 /* Set up function hooks. */
1601 init_machine_status = s390_init_machine_status;
1602
1603 /* Architecture mode defaults according to ABI. */
1604 if (!(target_flags_explicit & MASK_ZARCH))
1605 {
1606 if (TARGET_64BIT)
1607 target_flags |= MASK_ZARCH;
1608 else
1609 target_flags &= ~MASK_ZARCH;
1610 }
1611
1612 /* Determine processor architectural level. */
1613 if (!s390_arch_string)
1614 {
1615 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1616 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1617 }
1618
1619 /* This check is triggered when the user specified a wrong -march=
1620 string and prevents subsequent error messages from being
1621 issued. */
1622 if (s390_arch == PROCESSOR_max)
1623 return;
1624
1625 /* Determine processor to tune for. */
1626 if (s390_tune == PROCESSOR_max)
1627 {
1628 s390_tune = s390_arch;
1629 s390_tune_flags = s390_arch_flags;
1630 }
1631
1632 /* Sanity checks. */
1633 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1634 error ("z/Architecture mode not supported on %s", s390_arch_string);
1635 if (TARGET_64BIT && !TARGET_ZARCH)
1636 error ("64-bit ABI not supported in ESA/390 mode");
1637
1638 if (TARGET_HARD_DFP && !TARGET_DFP)
1639 {
1640 if (target_flags_explicit & MASK_HARD_DFP)
1641 {
1642 if (!TARGET_CPU_DFP)
1643 error ("hardware decimal floating point instructions"
1644 " not available on %s", s390_arch_string);
1645 if (!TARGET_ZARCH)
1646 error ("hardware decimal floating point instructions"
1647 " not available in ESA/390 mode");
1648 }
1649 else
1650 target_flags &= ~MASK_HARD_DFP;
1651 }
1652
1653 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1654 {
1655 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1656 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1657
1658 target_flags &= ~MASK_HARD_DFP;
1659 }
1660
1661 /* Set processor cost function. */
1662 switch (s390_tune)
1663 {
1664 case PROCESSOR_2084_Z990:
1665 s390_cost = &z990_cost;
1666 break;
1667 case PROCESSOR_2094_Z9_109:
1668 s390_cost = &z9_109_cost;
1669 break;
1670 case PROCESSOR_2097_Z10:
1671 s390_cost = &z10_cost;
1672 case PROCESSOR_2817_Z196:
1673 s390_cost = &z196_cost;
1674 break;
1675 default:
1676 s390_cost = &z900_cost;
1677 }
1678
1679 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1680 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1681 "in combination");
1682
1683 if (s390_stack_size)
1684 {
1685 if (s390_stack_guard >= s390_stack_size)
1686 error ("stack size must be greater than the stack guard value");
1687 else if (s390_stack_size > 1 << 16)
1688 error ("stack size must not be greater than 64k");
1689 }
1690 else if (s390_stack_guard)
1691 error ("-mstack-guard implies use of -mstack-size");
1692
1693 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1694 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1695 target_flags |= MASK_LONG_DOUBLE_128;
1696 #endif
1697
1698 if (s390_tune == PROCESSOR_2097_Z10
1699 || s390_tune == PROCESSOR_2817_Z196)
1700 {
1701 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1702 global_options.x_param_values,
1703 global_options_set.x_param_values);
1704 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1705 global_options.x_param_values,
1706 global_options_set.x_param_values);
1707 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1708 global_options.x_param_values,
1709 global_options_set.x_param_values);
1710 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1711 global_options.x_param_values,
1712 global_options_set.x_param_values);
1713 }
1714
1715 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1716 global_options.x_param_values,
1717 global_options_set.x_param_values);
1718 /* values for loop prefetching */
1719 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1720 global_options.x_param_values,
1721 global_options_set.x_param_values);
1722 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1723 global_options.x_param_values,
1724 global_options_set.x_param_values);
1725 /* s390 has more than 2 levels and the size is much larger. Since
1726 we are always running virtualized assume that we only get a small
1727 part of the caches above l1. */
1728 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1729 global_options.x_param_values,
1730 global_options_set.x_param_values);
1731 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1732 global_options.x_param_values,
1733 global_options_set.x_param_values);
1734 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1735 global_options.x_param_values,
1736 global_options_set.x_param_values);
1737
1738 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1739 requires the arch flags to be evaluated already. Since prefetching
1740 is beneficial on s390, we enable it if available. */
1741 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1742 flag_prefetch_loop_arrays = 1;
1743 }
1744
1745 /* Map for smallest class containing reg regno. */
1746
1747 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1748 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1749 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1750 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1751 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1752 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1753 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1754 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1755 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1756 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1757 ACCESS_REGS, ACCESS_REGS
1758 };
1759
1760 /* Return attribute type of insn. */
1761
1762 static enum attr_type
1763 s390_safe_attr_type (rtx insn)
1764 {
1765 if (recog_memoized (insn) >= 0)
1766 return get_attr_type (insn);
1767 else
1768 return TYPE_NONE;
1769 }
1770
1771 /* Return true if DISP is a valid short displacement. */
1772
1773 static bool
1774 s390_short_displacement (rtx disp)
1775 {
1776 /* No displacement is OK. */
1777 if (!disp)
1778 return true;
1779
1780 /* Without the long displacement facility we don't need to
1781 distingiush between long and short displacement. */
1782 if (!TARGET_LONG_DISPLACEMENT)
1783 return true;
1784
1785 /* Integer displacement in range. */
1786 if (GET_CODE (disp) == CONST_INT)
1787 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1788
1789 /* GOT offset is not OK, the GOT can be large. */
1790 if (GET_CODE (disp) == CONST
1791 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1792 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1793 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1794 return false;
1795
1796 /* All other symbolic constants are literal pool references,
1797 which are OK as the literal pool must be small. */
1798 if (GET_CODE (disp) == CONST)
1799 return true;
1800
1801 return false;
1802 }
1803
1804 /* Decompose a RTL expression ADDR for a memory address into
1805 its components, returned in OUT.
1806
1807 Returns false if ADDR is not a valid memory address, true
1808 otherwise. If OUT is NULL, don't return the components,
1809 but check for validity only.
1810
1811 Note: Only addresses in canonical form are recognized.
1812 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1813 canonical form so that they will be recognized. */
1814
1815 static int
1816 s390_decompose_address (rtx addr, struct s390_address *out)
1817 {
1818 HOST_WIDE_INT offset = 0;
1819 rtx base = NULL_RTX;
1820 rtx indx = NULL_RTX;
1821 rtx disp = NULL_RTX;
1822 rtx orig_disp;
1823 bool pointer = false;
1824 bool base_ptr = false;
1825 bool indx_ptr = false;
1826 bool literal_pool = false;
1827
1828 /* We may need to substitute the literal pool base register into the address
1829 below. However, at this point we do not know which register is going to
1830 be used as base, so we substitute the arg pointer register. This is going
1831 to be treated as holding a pointer below -- it shouldn't be used for any
1832 other purpose. */
1833 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1834
1835 /* Decompose address into base + index + displacement. */
1836
1837 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1838 base = addr;
1839
1840 else if (GET_CODE (addr) == PLUS)
1841 {
1842 rtx op0 = XEXP (addr, 0);
1843 rtx op1 = XEXP (addr, 1);
1844 enum rtx_code code0 = GET_CODE (op0);
1845 enum rtx_code code1 = GET_CODE (op1);
1846
1847 if (code0 == REG || code0 == UNSPEC)
1848 {
1849 if (code1 == REG || code1 == UNSPEC)
1850 {
1851 indx = op0; /* index + base */
1852 base = op1;
1853 }
1854
1855 else
1856 {
1857 base = op0; /* base + displacement */
1858 disp = op1;
1859 }
1860 }
1861
1862 else if (code0 == PLUS)
1863 {
1864 indx = XEXP (op0, 0); /* index + base + disp */
1865 base = XEXP (op0, 1);
1866 disp = op1;
1867 }
1868
1869 else
1870 {
1871 return false;
1872 }
1873 }
1874
1875 else
1876 disp = addr; /* displacement */
1877
1878 /* Extract integer part of displacement. */
1879 orig_disp = disp;
1880 if (disp)
1881 {
1882 if (GET_CODE (disp) == CONST_INT)
1883 {
1884 offset = INTVAL (disp);
1885 disp = NULL_RTX;
1886 }
1887 else if (GET_CODE (disp) == CONST
1888 && GET_CODE (XEXP (disp, 0)) == PLUS
1889 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1890 {
1891 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1892 disp = XEXP (XEXP (disp, 0), 0);
1893 }
1894 }
1895
1896 /* Strip off CONST here to avoid special case tests later. */
1897 if (disp && GET_CODE (disp) == CONST)
1898 disp = XEXP (disp, 0);
1899
1900 /* We can convert literal pool addresses to
1901 displacements by basing them off the base register. */
1902 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1903 {
1904 /* Either base or index must be free to hold the base register. */
1905 if (!base)
1906 base = fake_pool_base, literal_pool = true;
1907 else if (!indx)
1908 indx = fake_pool_base, literal_pool = true;
1909 else
1910 return false;
1911
1912 /* Mark up the displacement. */
1913 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1914 UNSPEC_LTREL_OFFSET);
1915 }
1916
1917 /* Validate base register. */
1918 if (base)
1919 {
1920 if (GET_CODE (base) == UNSPEC)
1921 switch (XINT (base, 1))
1922 {
1923 case UNSPEC_LTREF:
1924 if (!disp)
1925 disp = gen_rtx_UNSPEC (Pmode,
1926 gen_rtvec (1, XVECEXP (base, 0, 0)),
1927 UNSPEC_LTREL_OFFSET);
1928 else
1929 return false;
1930
1931 base = XVECEXP (base, 0, 1);
1932 break;
1933
1934 case UNSPEC_LTREL_BASE:
1935 if (XVECLEN (base, 0) == 1)
1936 base = fake_pool_base, literal_pool = true;
1937 else
1938 base = XVECEXP (base, 0, 1);
1939 break;
1940
1941 default:
1942 return false;
1943 }
1944
1945 if (!REG_P (base)
1946 || (GET_MODE (base) != SImode
1947 && GET_MODE (base) != Pmode))
1948 return false;
1949
1950 if (REGNO (base) == STACK_POINTER_REGNUM
1951 || REGNO (base) == FRAME_POINTER_REGNUM
1952 || ((reload_completed || reload_in_progress)
1953 && frame_pointer_needed
1954 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1955 || REGNO (base) == ARG_POINTER_REGNUM
1956 || (flag_pic
1957 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1958 pointer = base_ptr = true;
1959
1960 if ((reload_completed || reload_in_progress)
1961 && base == cfun->machine->base_reg)
1962 pointer = base_ptr = literal_pool = true;
1963 }
1964
1965 /* Validate index register. */
1966 if (indx)
1967 {
1968 if (GET_CODE (indx) == UNSPEC)
1969 switch (XINT (indx, 1))
1970 {
1971 case UNSPEC_LTREF:
1972 if (!disp)
1973 disp = gen_rtx_UNSPEC (Pmode,
1974 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1975 UNSPEC_LTREL_OFFSET);
1976 else
1977 return false;
1978
1979 indx = XVECEXP (indx, 0, 1);
1980 break;
1981
1982 case UNSPEC_LTREL_BASE:
1983 if (XVECLEN (indx, 0) == 1)
1984 indx = fake_pool_base, literal_pool = true;
1985 else
1986 indx = XVECEXP (indx, 0, 1);
1987 break;
1988
1989 default:
1990 return false;
1991 }
1992
1993 if (!REG_P (indx)
1994 || (GET_MODE (indx) != SImode
1995 && GET_MODE (indx) != Pmode))
1996 return false;
1997
1998 if (REGNO (indx) == STACK_POINTER_REGNUM
1999 || REGNO (indx) == FRAME_POINTER_REGNUM
2000 || ((reload_completed || reload_in_progress)
2001 && frame_pointer_needed
2002 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
2003 || REGNO (indx) == ARG_POINTER_REGNUM
2004 || (flag_pic
2005 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
2006 pointer = indx_ptr = true;
2007
2008 if ((reload_completed || reload_in_progress)
2009 && indx == cfun->machine->base_reg)
2010 pointer = indx_ptr = literal_pool = true;
2011 }
2012
2013 /* Prefer to use pointer as base, not index. */
2014 if (base && indx && !base_ptr
2015 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
2016 {
2017 rtx tmp = base;
2018 base = indx;
2019 indx = tmp;
2020 }
2021
2022 /* Validate displacement. */
2023 if (!disp)
2024 {
2025 /* If virtual registers are involved, the displacement will change later
2026 anyway as the virtual registers get eliminated. This could make a
2027 valid displacement invalid, but it is more likely to make an invalid
2028 displacement valid, because we sometimes access the register save area
2029 via negative offsets to one of those registers.
2030 Thus we don't check the displacement for validity here. If after
2031 elimination the displacement turns out to be invalid after all,
2032 this is fixed up by reload in any case. */
2033 if (base != arg_pointer_rtx
2034 && indx != arg_pointer_rtx
2035 && base != return_address_pointer_rtx
2036 && indx != return_address_pointer_rtx
2037 && base != frame_pointer_rtx
2038 && indx != frame_pointer_rtx
2039 && base != virtual_stack_vars_rtx
2040 && indx != virtual_stack_vars_rtx)
2041 if (!DISP_IN_RANGE (offset))
2042 return false;
2043 }
2044 else
2045 {
2046 /* All the special cases are pointers. */
2047 pointer = true;
2048
2049 /* In the small-PIC case, the linker converts @GOT
2050 and @GOTNTPOFF offsets to possible displacements. */
2051 if (GET_CODE (disp) == UNSPEC
2052 && (XINT (disp, 1) == UNSPEC_GOT
2053 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2054 && flag_pic == 1)
2055 {
2056 ;
2057 }
2058
2059 /* Accept pool label offsets. */
2060 else if (GET_CODE (disp) == UNSPEC
2061 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2062 ;
2063
2064 /* Accept literal pool references. */
2065 else if (GET_CODE (disp) == UNSPEC
2066 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2067 {
2068 /* In case CSE pulled a non literal pool reference out of
2069 the pool we have to reject the address. This is
2070 especially important when loading the GOT pointer on non
2071 zarch CPUs. In this case the literal pool contains an lt
2072 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2073 will most likely exceed the displacement. */
2074 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2075 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2076 return false;
2077
2078 orig_disp = gen_rtx_CONST (Pmode, disp);
2079 if (offset)
2080 {
2081 /* If we have an offset, make sure it does not
2082 exceed the size of the constant pool entry. */
2083 rtx sym = XVECEXP (disp, 0, 0);
2084 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2085 return false;
2086
2087 orig_disp = plus_constant (orig_disp, offset);
2088 }
2089 }
2090
2091 else
2092 return false;
2093 }
2094
2095 if (!base && !indx)
2096 pointer = true;
2097
2098 if (out)
2099 {
2100 out->base = base;
2101 out->indx = indx;
2102 out->disp = orig_disp;
2103 out->pointer = pointer;
2104 out->literal_pool = literal_pool;
2105 }
2106
2107 return true;
2108 }
2109
2110 /* Decompose a RTL expression OP for a shift count into its components,
2111 and return the base register in BASE and the offset in OFFSET.
2112
2113 Return true if OP is a valid shift count, false if not. */
2114
2115 bool
2116 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2117 {
2118 HOST_WIDE_INT off = 0;
2119
2120 /* We can have an integer constant, an address register,
2121 or a sum of the two. */
2122 if (GET_CODE (op) == CONST_INT)
2123 {
2124 off = INTVAL (op);
2125 op = NULL_RTX;
2126 }
2127 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2128 {
2129 off = INTVAL (XEXP (op, 1));
2130 op = XEXP (op, 0);
2131 }
2132 while (op && GET_CODE (op) == SUBREG)
2133 op = SUBREG_REG (op);
2134
2135 if (op && GET_CODE (op) != REG)
2136 return false;
2137
2138 if (offset)
2139 *offset = off;
2140 if (base)
2141 *base = op;
2142
2143 return true;
2144 }
2145
2146
2147 /* Return true if CODE is a valid address without index. */
2148
2149 bool
2150 s390_legitimate_address_without_index_p (rtx op)
2151 {
2152 struct s390_address addr;
2153
2154 if (!s390_decompose_address (XEXP (op, 0), &addr))
2155 return false;
2156 if (addr.indx)
2157 return false;
2158
2159 return true;
2160 }
2161
2162
2163 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2164 and return these parts in SYMREF and ADDEND. You can pass NULL in
2165 SYMREF and/or ADDEND if you are not interested in these values.
2166 Literal pool references are *not* considered symbol references. */
2167
2168 static bool
2169 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2170 {
2171 HOST_WIDE_INT tmpaddend = 0;
2172
2173 if (GET_CODE (addr) == CONST)
2174 addr = XEXP (addr, 0);
2175
2176 if (GET_CODE (addr) == PLUS)
2177 {
2178 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2179 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2180 && CONST_INT_P (XEXP (addr, 1)))
2181 {
2182 tmpaddend = INTVAL (XEXP (addr, 1));
2183 addr = XEXP (addr, 0);
2184 }
2185 else
2186 return false;
2187 }
2188 else
2189 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2190 return false;
2191
2192 if (symref)
2193 *symref = addr;
2194 if (addend)
2195 *addend = tmpaddend;
2196
2197 return true;
2198 }
2199
2200
2201 /* Return true if the address in OP is valid for constraint letter C
2202 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2203 pool MEMs should be accepted. Only the Q, R, S, T constraint
2204 letters are allowed for C. */
2205
2206 static int
2207 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2208 {
2209 struct s390_address addr;
2210 bool decomposed = false;
2211
2212 /* This check makes sure that no symbolic address (except literal
2213 pool references) are accepted by the R or T constraints. */
2214 if (s390_symref_operand_p (op, NULL, NULL))
2215 return 0;
2216
2217 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2218 if (!lit_pool_ok)
2219 {
2220 if (!s390_decompose_address (op, &addr))
2221 return 0;
2222 if (addr.literal_pool)
2223 return 0;
2224 decomposed = true;
2225 }
2226
2227 switch (c)
2228 {
2229 case 'Q': /* no index short displacement */
2230 if (!decomposed && !s390_decompose_address (op, &addr))
2231 return 0;
2232 if (addr.indx)
2233 return 0;
2234 if (!s390_short_displacement (addr.disp))
2235 return 0;
2236 break;
2237
2238 case 'R': /* with index short displacement */
2239 if (TARGET_LONG_DISPLACEMENT)
2240 {
2241 if (!decomposed && !s390_decompose_address (op, &addr))
2242 return 0;
2243 if (!s390_short_displacement (addr.disp))
2244 return 0;
2245 }
2246 /* Any invalid address here will be fixed up by reload,
2247 so accept it for the most generic constraint. */
2248 break;
2249
2250 case 'S': /* no index long displacement */
2251 if (!TARGET_LONG_DISPLACEMENT)
2252 return 0;
2253 if (!decomposed && !s390_decompose_address (op, &addr))
2254 return 0;
2255 if (addr.indx)
2256 return 0;
2257 if (s390_short_displacement (addr.disp))
2258 return 0;
2259 break;
2260
2261 case 'T': /* with index long displacement */
2262 if (!TARGET_LONG_DISPLACEMENT)
2263 return 0;
2264 /* Any invalid address here will be fixed up by reload,
2265 so accept it for the most generic constraint. */
2266 if ((decomposed || s390_decompose_address (op, &addr))
2267 && s390_short_displacement (addr.disp))
2268 return 0;
2269 break;
2270 default:
2271 return 0;
2272 }
2273 return 1;
2274 }
2275
2276
2277 /* Evaluates constraint strings described by the regular expression
2278 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2279 the constraint given in STR, or 0 else. */
2280
2281 int
2282 s390_mem_constraint (const char *str, rtx op)
2283 {
2284 char c = str[0];
2285
2286 switch (c)
2287 {
2288 case 'A':
2289 /* Check for offsettable variants of memory constraints. */
2290 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2291 return 0;
2292 if ((reload_completed || reload_in_progress)
2293 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2294 return 0;
2295 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2296 case 'B':
2297 /* Check for non-literal-pool variants of memory constraints. */
2298 if (!MEM_P (op))
2299 return 0;
2300 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2301 case 'Q':
2302 case 'R':
2303 case 'S':
2304 case 'T':
2305 if (GET_CODE (op) != MEM)
2306 return 0;
2307 return s390_check_qrst_address (c, XEXP (op, 0), true);
2308 case 'U':
2309 return (s390_check_qrst_address ('Q', op, true)
2310 || s390_check_qrst_address ('R', op, true));
2311 case 'W':
2312 return (s390_check_qrst_address ('S', op, true)
2313 || s390_check_qrst_address ('T', op, true));
2314 case 'Y':
2315 /* Simply check for the basic form of a shift count. Reload will
2316 take care of making sure we have a proper base register. */
2317 if (!s390_decompose_shift_count (op, NULL, NULL))
2318 return 0;
2319 break;
2320 case 'Z':
2321 return s390_check_qrst_address (str[1], op, true);
2322 default:
2323 return 0;
2324 }
2325 return 1;
2326 }
2327
2328
2329 /* Evaluates constraint strings starting with letter O. Input
2330 parameter C is the second letter following the "O" in the constraint
2331 string. Returns 1 if VALUE meets the respective constraint and 0
2332 otherwise. */
2333
2334 int
2335 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2336 {
2337 if (!TARGET_EXTIMM)
2338 return 0;
2339
2340 switch (c)
2341 {
2342 case 's':
2343 return trunc_int_for_mode (value, SImode) == value;
2344
2345 case 'p':
2346 return value == 0
2347 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2348
2349 case 'n':
2350 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2351
2352 default:
2353 gcc_unreachable ();
2354 }
2355 }
2356
2357
2358 /* Evaluates constraint strings starting with letter N. Parameter STR
2359 contains the letters following letter "N" in the constraint string.
2360 Returns true if VALUE matches the constraint. */
2361
2362 int
2363 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2364 {
2365 enum machine_mode mode, part_mode;
2366 int def;
2367 int part, part_goal;
2368
2369
2370 if (str[0] == 'x')
2371 part_goal = -1;
2372 else
2373 part_goal = str[0] - '0';
2374
2375 switch (str[1])
2376 {
2377 case 'Q':
2378 part_mode = QImode;
2379 break;
2380 case 'H':
2381 part_mode = HImode;
2382 break;
2383 case 'S':
2384 part_mode = SImode;
2385 break;
2386 default:
2387 return 0;
2388 }
2389
2390 switch (str[2])
2391 {
2392 case 'H':
2393 mode = HImode;
2394 break;
2395 case 'S':
2396 mode = SImode;
2397 break;
2398 case 'D':
2399 mode = DImode;
2400 break;
2401 default:
2402 return 0;
2403 }
2404
2405 switch (str[3])
2406 {
2407 case '0':
2408 def = 0;
2409 break;
2410 case 'F':
2411 def = -1;
2412 break;
2413 default:
2414 return 0;
2415 }
2416
2417 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2418 return 0;
2419
2420 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2421 if (part < 0)
2422 return 0;
2423 if (part_goal != -1 && part_goal != part)
2424 return 0;
2425
2426 return 1;
2427 }
2428
2429
2430 /* Returns true if the input parameter VALUE is a float zero. */
2431
2432 int
2433 s390_float_const_zero_p (rtx value)
2434 {
2435 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2436 && value == CONST0_RTX (GET_MODE (value)));
2437 }
2438
2439 /* Implement TARGET_REGISTER_MOVE_COST. */
2440
2441 static int
2442 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2443 reg_class_t from, reg_class_t to)
2444 {
2445 /* On s390, copy between fprs and gprs is expensive. */
2446 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2447 && reg_classes_intersect_p (to, FP_REGS))
2448 || (reg_classes_intersect_p (from, FP_REGS)
2449 && reg_classes_intersect_p (to, GENERAL_REGS)))
2450 return 10;
2451
2452 return 1;
2453 }
2454
2455 /* Implement TARGET_MEMORY_MOVE_COST. */
2456
2457 static int
2458 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2459 reg_class_t rclass ATTRIBUTE_UNUSED,
2460 bool in ATTRIBUTE_UNUSED)
2461 {
2462 return 1;
2463 }
2464
2465 /* Compute a (partial) cost for rtx X. Return true if the complete
2466 cost has been computed, and false if subexpressions should be
2467 scanned. In either case, *TOTAL contains the cost result.
2468 CODE contains GET_CODE (x), OUTER_CODE contains the code
2469 of the superexpression of x. */
2470
2471 static bool
2472 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2473 bool speed ATTRIBUTE_UNUSED)
2474 {
2475 switch (code)
2476 {
2477 case CONST:
2478 case CONST_INT:
2479 case LABEL_REF:
2480 case SYMBOL_REF:
2481 case CONST_DOUBLE:
2482 case MEM:
2483 *total = 0;
2484 return true;
2485
2486 case ASHIFT:
2487 case ASHIFTRT:
2488 case LSHIFTRT:
2489 case ROTATE:
2490 case ROTATERT:
2491 case AND:
2492 case IOR:
2493 case XOR:
2494 case NEG:
2495 case NOT:
2496 *total = COSTS_N_INSNS (1);
2497 return false;
2498
2499 case PLUS:
2500 case MINUS:
2501 *total = COSTS_N_INSNS (1);
2502 return false;
2503
2504 case MULT:
2505 switch (GET_MODE (x))
2506 {
2507 case SImode:
2508 {
2509 rtx left = XEXP (x, 0);
2510 rtx right = XEXP (x, 1);
2511 if (GET_CODE (right) == CONST_INT
2512 && CONST_OK_FOR_K (INTVAL (right)))
2513 *total = s390_cost->mhi;
2514 else if (GET_CODE (left) == SIGN_EXTEND)
2515 *total = s390_cost->mh;
2516 else
2517 *total = s390_cost->ms; /* msr, ms, msy */
2518 break;
2519 }
2520 case DImode:
2521 {
2522 rtx left = XEXP (x, 0);
2523 rtx right = XEXP (x, 1);
2524 if (TARGET_ZARCH)
2525 {
2526 if (GET_CODE (right) == CONST_INT
2527 && CONST_OK_FOR_K (INTVAL (right)))
2528 *total = s390_cost->mghi;
2529 else if (GET_CODE (left) == SIGN_EXTEND)
2530 *total = s390_cost->msgf;
2531 else
2532 *total = s390_cost->msg; /* msgr, msg */
2533 }
2534 else /* TARGET_31BIT */
2535 {
2536 if (GET_CODE (left) == SIGN_EXTEND
2537 && GET_CODE (right) == SIGN_EXTEND)
2538 /* mulsidi case: mr, m */
2539 *total = s390_cost->m;
2540 else if (GET_CODE (left) == ZERO_EXTEND
2541 && GET_CODE (right) == ZERO_EXTEND
2542 && TARGET_CPU_ZARCH)
2543 /* umulsidi case: ml, mlr */
2544 *total = s390_cost->ml;
2545 else
2546 /* Complex calculation is required. */
2547 *total = COSTS_N_INSNS (40);
2548 }
2549 break;
2550 }
2551 case SFmode:
2552 case DFmode:
2553 *total = s390_cost->mult_df;
2554 break;
2555 case TFmode:
2556 *total = s390_cost->mxbr;
2557 break;
2558 default:
2559 return false;
2560 }
2561 return false;
2562
2563 case FMA:
2564 switch (GET_MODE (x))
2565 {
2566 case DFmode:
2567 *total = s390_cost->madbr;
2568 break;
2569 case SFmode:
2570 *total = s390_cost->maebr;
2571 break;
2572 default:
2573 return false;
2574 }
2575 /* Negate in the third argument is free: FMSUB. */
2576 if (GET_CODE (XEXP (x, 2)) == NEG)
2577 {
2578 *total += (rtx_cost (XEXP (x, 0), FMA, speed)
2579 + rtx_cost (XEXP (x, 1), FMA, speed)
2580 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, speed));
2581 return true;
2582 }
2583 return false;
2584
2585 case UDIV:
2586 case UMOD:
2587 if (GET_MODE (x) == TImode) /* 128 bit division */
2588 *total = s390_cost->dlgr;
2589 else if (GET_MODE (x) == DImode)
2590 {
2591 rtx right = XEXP (x, 1);
2592 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2593 *total = s390_cost->dlr;
2594 else /* 64 by 64 bit division */
2595 *total = s390_cost->dlgr;
2596 }
2597 else if (GET_MODE (x) == SImode) /* 32 bit division */
2598 *total = s390_cost->dlr;
2599 return false;
2600
2601 case DIV:
2602 case MOD:
2603 if (GET_MODE (x) == DImode)
2604 {
2605 rtx right = XEXP (x, 1);
2606 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2607 if (TARGET_ZARCH)
2608 *total = s390_cost->dsgfr;
2609 else
2610 *total = s390_cost->dr;
2611 else /* 64 by 64 bit division */
2612 *total = s390_cost->dsgr;
2613 }
2614 else if (GET_MODE (x) == SImode) /* 32 bit division */
2615 *total = s390_cost->dlr;
2616 else if (GET_MODE (x) == SFmode)
2617 {
2618 *total = s390_cost->debr;
2619 }
2620 else if (GET_MODE (x) == DFmode)
2621 {
2622 *total = s390_cost->ddbr;
2623 }
2624 else if (GET_MODE (x) == TFmode)
2625 {
2626 *total = s390_cost->dxbr;
2627 }
2628 return false;
2629
2630 case SQRT:
2631 if (GET_MODE (x) == SFmode)
2632 *total = s390_cost->sqebr;
2633 else if (GET_MODE (x) == DFmode)
2634 *total = s390_cost->sqdbr;
2635 else /* TFmode */
2636 *total = s390_cost->sqxbr;
2637 return false;
2638
2639 case SIGN_EXTEND:
2640 case ZERO_EXTEND:
2641 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2642 || outer_code == PLUS || outer_code == MINUS
2643 || outer_code == COMPARE)
2644 *total = 0;
2645 return false;
2646
2647 case COMPARE:
2648 *total = COSTS_N_INSNS (1);
2649 if (GET_CODE (XEXP (x, 0)) == AND
2650 && GET_CODE (XEXP (x, 1)) == CONST_INT
2651 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2652 {
2653 rtx op0 = XEXP (XEXP (x, 0), 0);
2654 rtx op1 = XEXP (XEXP (x, 0), 1);
2655 rtx op2 = XEXP (x, 1);
2656
2657 if (memory_operand (op0, GET_MODE (op0))
2658 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2659 return true;
2660 if (register_operand (op0, GET_MODE (op0))
2661 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2662 return true;
2663 }
2664 return false;
2665
2666 default:
2667 return false;
2668 }
2669 }
2670
2671 /* Return the cost of an address rtx ADDR. */
2672
2673 static int
2674 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2675 {
2676 struct s390_address ad;
2677 if (!s390_decompose_address (addr, &ad))
2678 return 1000;
2679
2680 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2681 }
2682
2683 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2684 otherwise return 0. */
2685
2686 int
2687 tls_symbolic_operand (rtx op)
2688 {
2689 if (GET_CODE (op) != SYMBOL_REF)
2690 return 0;
2691 return SYMBOL_REF_TLS_MODEL (op);
2692 }
2693 \f
2694 /* Split DImode access register reference REG (on 64-bit) into its constituent
2695 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2696 gen_highpart cannot be used as they assume all registers are word-sized,
2697 while our access registers have only half that size. */
2698
2699 void
2700 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2701 {
2702 gcc_assert (TARGET_64BIT);
2703 gcc_assert (ACCESS_REG_P (reg));
2704 gcc_assert (GET_MODE (reg) == DImode);
2705 gcc_assert (!(REGNO (reg) & 1));
2706
2707 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2708 *hi = gen_rtx_REG (SImode, REGNO (reg));
2709 }
2710
2711 /* Return true if OP contains a symbol reference */
2712
2713 bool
2714 symbolic_reference_mentioned_p (rtx op)
2715 {
2716 const char *fmt;
2717 int i;
2718
2719 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2720 return 1;
2721
2722 fmt = GET_RTX_FORMAT (GET_CODE (op));
2723 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2724 {
2725 if (fmt[i] == 'E')
2726 {
2727 int j;
2728
2729 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2730 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2731 return 1;
2732 }
2733
2734 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2735 return 1;
2736 }
2737
2738 return 0;
2739 }
2740
2741 /* Return true if OP contains a reference to a thread-local symbol. */
2742
2743 bool
2744 tls_symbolic_reference_mentioned_p (rtx op)
2745 {
2746 const char *fmt;
2747 int i;
2748
2749 if (GET_CODE (op) == SYMBOL_REF)
2750 return tls_symbolic_operand (op);
2751
2752 fmt = GET_RTX_FORMAT (GET_CODE (op));
2753 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2754 {
2755 if (fmt[i] == 'E')
2756 {
2757 int j;
2758
2759 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2760 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2761 return true;
2762 }
2763
2764 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2765 return true;
2766 }
2767
2768 return false;
2769 }
2770
2771
2772 /* Return true if OP is a legitimate general operand when
2773 generating PIC code. It is given that flag_pic is on
2774 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2775
2776 int
2777 legitimate_pic_operand_p (rtx op)
2778 {
2779 /* Accept all non-symbolic constants. */
2780 if (!SYMBOLIC_CONST (op))
2781 return 1;
2782
2783 /* Reject everything else; must be handled
2784 via emit_symbolic_move. */
2785 return 0;
2786 }
2787
2788 /* Returns true if the constant value OP is a legitimate general operand.
2789 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2790
2791 int
2792 legitimate_constant_p (rtx op)
2793 {
2794 /* Accept all non-symbolic constants. */
2795 if (!SYMBOLIC_CONST (op))
2796 return 1;
2797
2798 /* Accept immediate LARL operands. */
2799 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2800 return 1;
2801
2802 /* Thread-local symbols are never legal constants. This is
2803 so that emit_call knows that computing such addresses
2804 might require a function call. */
2805 if (TLS_SYMBOLIC_CONST (op))
2806 return 0;
2807
2808 /* In the PIC case, symbolic constants must *not* be
2809 forced into the literal pool. We accept them here,
2810 so that they will be handled by emit_symbolic_move. */
2811 if (flag_pic)
2812 return 1;
2813
2814 /* All remaining non-PIC symbolic constants are
2815 forced into the literal pool. */
2816 return 0;
2817 }
2818
2819 /* Determine if it's legal to put X into the constant pool. This
2820 is not possible if X contains the address of a symbol that is
2821 not constant (TLS) or not known at final link time (PIC). */
2822
2823 static bool
2824 s390_cannot_force_const_mem (rtx x)
2825 {
2826 switch (GET_CODE (x))
2827 {
2828 case CONST_INT:
2829 case CONST_DOUBLE:
2830 /* Accept all non-symbolic constants. */
2831 return false;
2832
2833 case LABEL_REF:
2834 /* Labels are OK iff we are non-PIC. */
2835 return flag_pic != 0;
2836
2837 case SYMBOL_REF:
2838 /* 'Naked' TLS symbol references are never OK,
2839 non-TLS symbols are OK iff we are non-PIC. */
2840 if (tls_symbolic_operand (x))
2841 return true;
2842 else
2843 return flag_pic != 0;
2844
2845 case CONST:
2846 return s390_cannot_force_const_mem (XEXP (x, 0));
2847 case PLUS:
2848 case MINUS:
2849 return s390_cannot_force_const_mem (XEXP (x, 0))
2850 || s390_cannot_force_const_mem (XEXP (x, 1));
2851
2852 case UNSPEC:
2853 switch (XINT (x, 1))
2854 {
2855 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2856 case UNSPEC_LTREL_OFFSET:
2857 case UNSPEC_GOT:
2858 case UNSPEC_GOTOFF:
2859 case UNSPEC_PLTOFF:
2860 case UNSPEC_TLSGD:
2861 case UNSPEC_TLSLDM:
2862 case UNSPEC_NTPOFF:
2863 case UNSPEC_DTPOFF:
2864 case UNSPEC_GOTNTPOFF:
2865 case UNSPEC_INDNTPOFF:
2866 return false;
2867
2868 /* If the literal pool shares the code section, be put
2869 execute template placeholders into the pool as well. */
2870 case UNSPEC_INSN:
2871 return TARGET_CPU_ZARCH;
2872
2873 default:
2874 return true;
2875 }
2876 break;
2877
2878 default:
2879 gcc_unreachable ();
2880 }
2881 }
2882
2883 /* Returns true if the constant value OP is a legitimate general
2884 operand during and after reload. The difference to
2885 legitimate_constant_p is that this function will not accept
2886 a constant that would need to be forced to the literal pool
2887 before it can be used as operand.
2888 This function accepts all constants which can be loaded directly
2889 into a GPR. */
2890
2891 bool
2892 legitimate_reload_constant_p (rtx op)
2893 {
2894 /* Accept la(y) operands. */
2895 if (GET_CODE (op) == CONST_INT
2896 && DISP_IN_RANGE (INTVAL (op)))
2897 return true;
2898
2899 /* Accept l(g)hi/l(g)fi operands. */
2900 if (GET_CODE (op) == CONST_INT
2901 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2902 return true;
2903
2904 /* Accept lliXX operands. */
2905 if (TARGET_ZARCH
2906 && GET_CODE (op) == CONST_INT
2907 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2908 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2909 return true;
2910
2911 if (TARGET_EXTIMM
2912 && GET_CODE (op) == CONST_INT
2913 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2914 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2915 return true;
2916
2917 /* Accept larl operands. */
2918 if (TARGET_CPU_ZARCH
2919 && larl_operand (op, VOIDmode))
2920 return true;
2921
2922 /* Accept floating-point zero operands that fit into a single GPR. */
2923 if (GET_CODE (op) == CONST_DOUBLE
2924 && s390_float_const_zero_p (op)
2925 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2926 return true;
2927
2928 /* Accept double-word operands that can be split. */
2929 if (GET_CODE (op) == CONST_INT
2930 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2931 {
2932 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2933 rtx hi = operand_subword (op, 0, 0, dword_mode);
2934 rtx lo = operand_subword (op, 1, 0, dword_mode);
2935 return legitimate_reload_constant_p (hi)
2936 && legitimate_reload_constant_p (lo);
2937 }
2938
2939 /* Everything else cannot be handled without reload. */
2940 return false;
2941 }
2942
2943 /* Returns true if the constant value OP is a legitimate fp operand
2944 during and after reload.
2945 This function accepts all constants which can be loaded directly
2946 into an FPR. */
2947
2948 static bool
2949 legitimate_reload_fp_constant_p (rtx op)
2950 {
2951 /* Accept floating-point zero operands if the load zero instruction
2952 can be used. */
2953 if (TARGET_Z196
2954 && GET_CODE (op) == CONST_DOUBLE
2955 && s390_float_const_zero_p (op))
2956 return true;
2957
2958 return false;
2959 }
2960
2961 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2962 return the class of reg to actually use. */
2963
2964 static reg_class_t
2965 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2966 {
2967 switch (GET_CODE (op))
2968 {
2969 /* Constants we cannot reload into general registers
2970 must be forced into the literal pool. */
2971 case CONST_DOUBLE:
2972 case CONST_INT:
2973 if (reg_class_subset_p (GENERAL_REGS, rclass)
2974 && legitimate_reload_constant_p (op))
2975 return GENERAL_REGS;
2976 else if (reg_class_subset_p (ADDR_REGS, rclass)
2977 && legitimate_reload_constant_p (op))
2978 return ADDR_REGS;
2979 else if (reg_class_subset_p (FP_REGS, rclass)
2980 && legitimate_reload_fp_constant_p (op))
2981 return FP_REGS;
2982 return NO_REGS;
2983
2984 /* If a symbolic constant or a PLUS is reloaded,
2985 it is most likely being used as an address, so
2986 prefer ADDR_REGS. If 'class' is not a superset
2987 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2988 case PLUS:
2989 case LABEL_REF:
2990 case SYMBOL_REF:
2991 case CONST:
2992 if (reg_class_subset_p (ADDR_REGS, rclass))
2993 return ADDR_REGS;
2994 else
2995 return NO_REGS;
2996
2997 default:
2998 break;
2999 }
3000
3001 return rclass;
3002 }
3003
3004 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
3005 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3006 aligned. */
3007
3008 bool
3009 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
3010 {
3011 HOST_WIDE_INT addend;
3012 rtx symref;
3013
3014 if (!s390_symref_operand_p (addr, &symref, &addend))
3015 return false;
3016
3017 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
3018 && !(addend & (alignment - 1)));
3019 }
3020
3021 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3022 operand SCRATCH is used to reload the even part of the address and
3023 adding one. */
3024
3025 void
3026 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3027 {
3028 HOST_WIDE_INT addend;
3029 rtx symref;
3030
3031 if (!s390_symref_operand_p (addr, &symref, &addend))
3032 gcc_unreachable ();
3033
3034 if (!(addend & 1))
3035 /* Easy case. The addend is even so larl will do fine. */
3036 emit_move_insn (reg, addr);
3037 else
3038 {
3039 /* We can leave the scratch register untouched if the target
3040 register is a valid base register. */
3041 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3042 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3043 scratch = reg;
3044
3045 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3046 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3047
3048 if (addend != 1)
3049 emit_move_insn (scratch,
3050 gen_rtx_CONST (Pmode,
3051 gen_rtx_PLUS (Pmode, symref,
3052 GEN_INT (addend - 1))));
3053 else
3054 emit_move_insn (scratch, symref);
3055
3056 /* Increment the address using la in order to avoid clobbering cc. */
3057 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3058 }
3059 }
3060
3061 /* Generate what is necessary to move between REG and MEM using
3062 SCRATCH. The direction is given by TOMEM. */
3063
3064 void
3065 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3066 {
3067 /* Reload might have pulled a constant out of the literal pool.
3068 Force it back in. */
3069 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3070 || GET_CODE (mem) == CONST)
3071 mem = force_const_mem (GET_MODE (reg), mem);
3072
3073 gcc_assert (MEM_P (mem));
3074
3075 /* For a load from memory we can leave the scratch register
3076 untouched if the target register is a valid base register. */
3077 if (!tomem
3078 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3079 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3080 && GET_MODE (reg) == GET_MODE (scratch))
3081 scratch = reg;
3082
3083 /* Load address into scratch register. Since we can't have a
3084 secondary reload for a secondary reload we have to cover the case
3085 where larl would need a secondary reload here as well. */
3086 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3087
3088 /* Now we can use a standard load/store to do the move. */
3089 if (tomem)
3090 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3091 else
3092 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3093 }
3094
3095 /* Inform reload about cases where moving X with a mode MODE to a register in
3096 RCLASS requires an extra scratch or immediate register. Return the class
3097 needed for the immediate register. */
3098
3099 static reg_class_t
3100 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3101 enum machine_mode mode, secondary_reload_info *sri)
3102 {
3103 enum reg_class rclass = (enum reg_class) rclass_i;
3104
3105 /* Intermediate register needed. */
3106 if (reg_classes_intersect_p (CC_REGS, rclass))
3107 return GENERAL_REGS;
3108
3109 if (TARGET_Z10)
3110 {
3111 /* On z10 several optimizer steps may generate larl operands with
3112 an odd addend. */
3113 if (in_p
3114 && s390_symref_operand_p (x, NULL, NULL)
3115 && mode == Pmode
3116 && !s390_check_symref_alignment (x, 2))
3117 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3118 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3119
3120 /* On z10 we need a scratch register when moving QI, TI or floating
3121 point mode values from or to a memory location with a SYMBOL_REF
3122 or if the symref addend of a SI or DI move is not aligned to the
3123 width of the access. */
3124 if (MEM_P (x)
3125 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3126 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3127 || (!TARGET_ZARCH && mode == DImode)
3128 || ((mode == HImode || mode == SImode || mode == DImode)
3129 && (!s390_check_symref_alignment (XEXP (x, 0),
3130 GET_MODE_SIZE (mode))))))
3131 {
3132 #define __SECONDARY_RELOAD_CASE(M,m) \
3133 case M##mode: \
3134 if (TARGET_64BIT) \
3135 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3136 CODE_FOR_reload##m##di_tomem_z10; \
3137 else \
3138 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3139 CODE_FOR_reload##m##si_tomem_z10; \
3140 break;
3141
3142 switch (GET_MODE (x))
3143 {
3144 __SECONDARY_RELOAD_CASE (QI, qi);
3145 __SECONDARY_RELOAD_CASE (HI, hi);
3146 __SECONDARY_RELOAD_CASE (SI, si);
3147 __SECONDARY_RELOAD_CASE (DI, di);
3148 __SECONDARY_RELOAD_CASE (TI, ti);
3149 __SECONDARY_RELOAD_CASE (SF, sf);
3150 __SECONDARY_RELOAD_CASE (DF, df);
3151 __SECONDARY_RELOAD_CASE (TF, tf);
3152 __SECONDARY_RELOAD_CASE (SD, sd);
3153 __SECONDARY_RELOAD_CASE (DD, dd);
3154 __SECONDARY_RELOAD_CASE (TD, td);
3155
3156 default:
3157 gcc_unreachable ();
3158 }
3159 #undef __SECONDARY_RELOAD_CASE
3160 }
3161 }
3162
3163 /* We need a scratch register when loading a PLUS expression which
3164 is not a legitimate operand of the LOAD ADDRESS instruction. */
3165 if (in_p && s390_plus_operand (x, mode))
3166 sri->icode = (TARGET_64BIT ?
3167 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3168
3169 /* Performing a multiword move from or to memory we have to make sure the
3170 second chunk in memory is addressable without causing a displacement
3171 overflow. If that would be the case we calculate the address in
3172 a scratch register. */
3173 if (MEM_P (x)
3174 && GET_CODE (XEXP (x, 0)) == PLUS
3175 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3176 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3177 + GET_MODE_SIZE (mode) - 1))
3178 {
3179 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3180 in a s_operand address since we may fallback to lm/stm. So we only
3181 have to care about overflows in the b+i+d case. */
3182 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3183 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3184 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3185 /* For FP_REGS no lm/stm is available so this check is triggered
3186 for displacement overflows in b+i+d and b+d like addresses. */
3187 || (reg_classes_intersect_p (FP_REGS, rclass)
3188 && s390_class_max_nregs (FP_REGS, mode) > 1))
3189 {
3190 if (in_p)
3191 sri->icode = (TARGET_64BIT ?
3192 CODE_FOR_reloaddi_nonoffmem_in :
3193 CODE_FOR_reloadsi_nonoffmem_in);
3194 else
3195 sri->icode = (TARGET_64BIT ?
3196 CODE_FOR_reloaddi_nonoffmem_out :
3197 CODE_FOR_reloadsi_nonoffmem_out);
3198 }
3199 }
3200
3201 /* A scratch address register is needed when a symbolic constant is
3202 copied to r0 compiling with -fPIC. In other cases the target
3203 register might be used as temporary (see legitimize_pic_address). */
3204 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3205 sri->icode = (TARGET_64BIT ?
3206 CODE_FOR_reloaddi_PIC_addr :
3207 CODE_FOR_reloadsi_PIC_addr);
3208
3209 /* Either scratch or no register needed. */
3210 return NO_REGS;
3211 }
3212
3213 /* Generate code to load SRC, which is PLUS that is not a
3214 legitimate operand for the LA instruction, into TARGET.
3215 SCRATCH may be used as scratch register. */
3216
3217 void
3218 s390_expand_plus_operand (rtx target, rtx src,
3219 rtx scratch)
3220 {
3221 rtx sum1, sum2;
3222 struct s390_address ad;
3223
3224 /* src must be a PLUS; get its two operands. */
3225 gcc_assert (GET_CODE (src) == PLUS);
3226 gcc_assert (GET_MODE (src) == Pmode);
3227
3228 /* Check if any of the two operands is already scheduled
3229 for replacement by reload. This can happen e.g. when
3230 float registers occur in an address. */
3231 sum1 = find_replacement (&XEXP (src, 0));
3232 sum2 = find_replacement (&XEXP (src, 1));
3233 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3234
3235 /* If the address is already strictly valid, there's nothing to do. */
3236 if (!s390_decompose_address (src, &ad)
3237 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3238 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3239 {
3240 /* Otherwise, one of the operands cannot be an address register;
3241 we reload its value into the scratch register. */
3242 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3243 {
3244 emit_move_insn (scratch, sum1);
3245 sum1 = scratch;
3246 }
3247 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3248 {
3249 emit_move_insn (scratch, sum2);
3250 sum2 = scratch;
3251 }
3252
3253 /* According to the way these invalid addresses are generated
3254 in reload.c, it should never happen (at least on s390) that
3255 *neither* of the PLUS components, after find_replacements
3256 was applied, is an address register. */
3257 if (sum1 == scratch && sum2 == scratch)
3258 {
3259 debug_rtx (src);
3260 gcc_unreachable ();
3261 }
3262
3263 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3264 }
3265
3266 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3267 is only ever performed on addresses, so we can mark the
3268 sum as legitimate for LA in any case. */
3269 s390_load_address (target, src);
3270 }
3271
3272
3273 /* Return true if ADDR is a valid memory address.
3274 STRICT specifies whether strict register checking applies. */
3275
3276 static bool
3277 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3278 {
3279 struct s390_address ad;
3280
3281 if (TARGET_Z10
3282 && larl_operand (addr, VOIDmode)
3283 && (mode == VOIDmode
3284 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3285 return true;
3286
3287 if (!s390_decompose_address (addr, &ad))
3288 return false;
3289
3290 if (strict)
3291 {
3292 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3293 return false;
3294
3295 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3296 return false;
3297 }
3298 else
3299 {
3300 if (ad.base
3301 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3302 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3303 return false;
3304
3305 if (ad.indx
3306 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3307 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3308 return false;
3309 }
3310 return true;
3311 }
3312
3313 /* Return true if OP is a valid operand for the LA instruction.
3314 In 31-bit, we need to prove that the result is used as an
3315 address, as LA performs only a 31-bit addition. */
3316
3317 bool
3318 legitimate_la_operand_p (rtx op)
3319 {
3320 struct s390_address addr;
3321 if (!s390_decompose_address (op, &addr))
3322 return false;
3323
3324 return (TARGET_64BIT || addr.pointer);
3325 }
3326
3327 /* Return true if it is valid *and* preferable to use LA to
3328 compute the sum of OP1 and OP2. */
3329
3330 bool
3331 preferred_la_operand_p (rtx op1, rtx op2)
3332 {
3333 struct s390_address addr;
3334
3335 if (op2 != const0_rtx)
3336 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3337
3338 if (!s390_decompose_address (op1, &addr))
3339 return false;
3340 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3341 return false;
3342 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3343 return false;
3344
3345 /* Avoid LA instructions with index register on z196; it is
3346 preferable to use regular add instructions when possible. */
3347 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3348 return false;
3349
3350 if (!TARGET_64BIT && !addr.pointer)
3351 return false;
3352
3353 if (addr.pointer)
3354 return true;
3355
3356 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3357 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3358 return true;
3359
3360 return false;
3361 }
3362
3363 /* Emit a forced load-address operation to load SRC into DST.
3364 This will use the LOAD ADDRESS instruction even in situations
3365 where legitimate_la_operand_p (SRC) returns false. */
3366
3367 void
3368 s390_load_address (rtx dst, rtx src)
3369 {
3370 if (TARGET_64BIT)
3371 emit_move_insn (dst, src);
3372 else
3373 emit_insn (gen_force_la_31 (dst, src));
3374 }
3375
3376 /* Return a legitimate reference for ORIG (an address) using the
3377 register REG. If REG is 0, a new pseudo is generated.
3378
3379 There are two types of references that must be handled:
3380
3381 1. Global data references must load the address from the GOT, via
3382 the PIC reg. An insn is emitted to do this load, and the reg is
3383 returned.
3384
3385 2. Static data references, constant pool addresses, and code labels
3386 compute the address as an offset from the GOT, whose base is in
3387 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3388 differentiate them from global data objects. The returned
3389 address is the PIC reg + an unspec constant.
3390
3391 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3392 reg also appears in the address. */
3393
3394 rtx
3395 legitimize_pic_address (rtx orig, rtx reg)
3396 {
3397 rtx addr = orig;
3398 rtx new_rtx = orig;
3399 rtx base;
3400
3401 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3402
3403 if (GET_CODE (addr) == LABEL_REF
3404 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3405 {
3406 /* This is a local symbol. */
3407 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3408 {
3409 /* Access local symbols PC-relative via LARL.
3410 This is the same as in the non-PIC case, so it is
3411 handled automatically ... */
3412 }
3413 else
3414 {
3415 /* Access local symbols relative to the GOT. */
3416
3417 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3418
3419 if (reload_in_progress || reload_completed)
3420 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3421
3422 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3423 addr = gen_rtx_CONST (Pmode, addr);
3424 addr = force_const_mem (Pmode, addr);
3425 emit_move_insn (temp, addr);
3426
3427 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3428 if (reg != 0)
3429 {
3430 s390_load_address (reg, new_rtx);
3431 new_rtx = reg;
3432 }
3433 }
3434 }
3435 else if (GET_CODE (addr) == SYMBOL_REF)
3436 {
3437 if (reg == 0)
3438 reg = gen_reg_rtx (Pmode);
3439
3440 if (flag_pic == 1)
3441 {
3442 /* Assume GOT offset < 4k. This is handled the same way
3443 in both 31- and 64-bit code (@GOT). */
3444
3445 if (reload_in_progress || reload_completed)
3446 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3447
3448 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3449 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3450 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3451 new_rtx = gen_const_mem (Pmode, new_rtx);
3452 emit_move_insn (reg, new_rtx);
3453 new_rtx = reg;
3454 }
3455 else if (TARGET_CPU_ZARCH)
3456 {
3457 /* If the GOT offset might be >= 4k, we determine the position
3458 of the GOT entry via a PC-relative LARL (@GOTENT). */
3459
3460 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3461
3462 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3463 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3464
3465 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3466 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3467 emit_move_insn (temp, new_rtx);
3468
3469 new_rtx = gen_const_mem (Pmode, temp);
3470 emit_move_insn (reg, new_rtx);
3471 new_rtx = reg;
3472 }
3473 else
3474 {
3475 /* If the GOT offset might be >= 4k, we have to load it
3476 from the literal pool (@GOT). */
3477
3478 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3479
3480 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3481 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3482
3483 if (reload_in_progress || reload_completed)
3484 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3485
3486 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3487 addr = gen_rtx_CONST (Pmode, addr);
3488 addr = force_const_mem (Pmode, addr);
3489 emit_move_insn (temp, addr);
3490
3491 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3492 new_rtx = gen_const_mem (Pmode, new_rtx);
3493 emit_move_insn (reg, new_rtx);
3494 new_rtx = reg;
3495 }
3496 }
3497 else
3498 {
3499 if (GET_CODE (addr) == CONST)
3500 {
3501 addr = XEXP (addr, 0);
3502 if (GET_CODE (addr) == UNSPEC)
3503 {
3504 gcc_assert (XVECLEN (addr, 0) == 1);
3505 switch (XINT (addr, 1))
3506 {
3507 /* If someone moved a GOT-relative UNSPEC
3508 out of the literal pool, force them back in. */
3509 case UNSPEC_GOTOFF:
3510 case UNSPEC_PLTOFF:
3511 new_rtx = force_const_mem (Pmode, orig);
3512 break;
3513
3514 /* @GOT is OK as is if small. */
3515 case UNSPEC_GOT:
3516 if (flag_pic == 2)
3517 new_rtx = force_const_mem (Pmode, orig);
3518 break;
3519
3520 /* @GOTENT is OK as is. */
3521 case UNSPEC_GOTENT:
3522 break;
3523
3524 /* @PLT is OK as is on 64-bit, must be converted to
3525 GOT-relative @PLTOFF on 31-bit. */
3526 case UNSPEC_PLT:
3527 if (!TARGET_CPU_ZARCH)
3528 {
3529 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3530
3531 if (reload_in_progress || reload_completed)
3532 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3533
3534 addr = XVECEXP (addr, 0, 0);
3535 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3536 UNSPEC_PLTOFF);
3537 addr = gen_rtx_CONST (Pmode, addr);
3538 addr = force_const_mem (Pmode, addr);
3539 emit_move_insn (temp, addr);
3540
3541 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3542 if (reg != 0)
3543 {
3544 s390_load_address (reg, new_rtx);
3545 new_rtx = reg;
3546 }
3547 }
3548 break;
3549
3550 /* Everything else cannot happen. */
3551 default:
3552 gcc_unreachable ();
3553 }
3554 }
3555 else
3556 gcc_assert (GET_CODE (addr) == PLUS);
3557 }
3558 if (GET_CODE (addr) == PLUS)
3559 {
3560 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3561
3562 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3563 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3564
3565 /* Check first to see if this is a constant offset
3566 from a local symbol reference. */
3567 if ((GET_CODE (op0) == LABEL_REF
3568 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3569 && GET_CODE (op1) == CONST_INT)
3570 {
3571 if (TARGET_CPU_ZARCH
3572 && larl_operand (op0, VOIDmode)
3573 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3574 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3575 {
3576 if (INTVAL (op1) & 1)
3577 {
3578 /* LARL can't handle odd offsets, so emit a
3579 pair of LARL and LA. */
3580 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3581
3582 if (!DISP_IN_RANGE (INTVAL (op1)))
3583 {
3584 HOST_WIDE_INT even = INTVAL (op1) - 1;
3585 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3586 op0 = gen_rtx_CONST (Pmode, op0);
3587 op1 = const1_rtx;
3588 }
3589
3590 emit_move_insn (temp, op0);
3591 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3592
3593 if (reg != 0)
3594 {
3595 s390_load_address (reg, new_rtx);
3596 new_rtx = reg;
3597 }
3598 }
3599 else
3600 {
3601 /* If the offset is even, we can just use LARL.
3602 This will happen automatically. */
3603 }
3604 }
3605 else
3606 {
3607 /* Access local symbols relative to the GOT. */
3608
3609 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3610
3611 if (reload_in_progress || reload_completed)
3612 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3613
3614 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3615 UNSPEC_GOTOFF);
3616 addr = gen_rtx_PLUS (Pmode, addr, op1);
3617 addr = gen_rtx_CONST (Pmode, addr);
3618 addr = force_const_mem (Pmode, addr);
3619 emit_move_insn (temp, addr);
3620
3621 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3622 if (reg != 0)
3623 {
3624 s390_load_address (reg, new_rtx);
3625 new_rtx = reg;
3626 }
3627 }
3628 }
3629
3630 /* Now, check whether it is a GOT relative symbol plus offset
3631 that was pulled out of the literal pool. Force it back in. */
3632
3633 else if (GET_CODE (op0) == UNSPEC
3634 && GET_CODE (op1) == CONST_INT
3635 && XINT (op0, 1) == UNSPEC_GOTOFF)
3636 {
3637 gcc_assert (XVECLEN (op0, 0) == 1);
3638
3639 new_rtx = force_const_mem (Pmode, orig);
3640 }
3641
3642 /* Otherwise, compute the sum. */
3643 else
3644 {
3645 base = legitimize_pic_address (XEXP (addr, 0), reg);
3646 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3647 base == reg ? NULL_RTX : reg);
3648 if (GET_CODE (new_rtx) == CONST_INT)
3649 new_rtx = plus_constant (base, INTVAL (new_rtx));
3650 else
3651 {
3652 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3653 {
3654 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3655 new_rtx = XEXP (new_rtx, 1);
3656 }
3657 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3658 }
3659
3660 if (GET_CODE (new_rtx) == CONST)
3661 new_rtx = XEXP (new_rtx, 0);
3662 new_rtx = force_operand (new_rtx, 0);
3663 }
3664 }
3665 }
3666 return new_rtx;
3667 }
3668
3669 /* Load the thread pointer into a register. */
3670
3671 rtx
3672 s390_get_thread_pointer (void)
3673 {
3674 rtx tp = gen_reg_rtx (Pmode);
3675
3676 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3677 mark_reg_pointer (tp, BITS_PER_WORD);
3678
3679 return tp;
3680 }
3681
3682 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3683 in s390_tls_symbol which always refers to __tls_get_offset.
3684 The returned offset is written to RESULT_REG and an USE rtx is
3685 generated for TLS_CALL. */
3686
3687 static GTY(()) rtx s390_tls_symbol;
3688
3689 static void
3690 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3691 {
3692 rtx insn;
3693
3694 gcc_assert (flag_pic);
3695
3696 if (!s390_tls_symbol)
3697 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3698
3699 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3700 gen_rtx_REG (Pmode, RETURN_REGNUM));
3701
3702 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3703 RTL_CONST_CALL_P (insn) = 1;
3704 }
3705
3706 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3707 this (thread-local) address. REG may be used as temporary. */
3708
3709 static rtx
3710 legitimize_tls_address (rtx addr, rtx reg)
3711 {
3712 rtx new_rtx, tls_call, temp, base, r2, insn;
3713
3714 if (GET_CODE (addr) == SYMBOL_REF)
3715 switch (tls_symbolic_operand (addr))
3716 {
3717 case TLS_MODEL_GLOBAL_DYNAMIC:
3718 start_sequence ();
3719 r2 = gen_rtx_REG (Pmode, 2);
3720 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3721 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3722 new_rtx = force_const_mem (Pmode, new_rtx);
3723 emit_move_insn (r2, new_rtx);
3724 s390_emit_tls_call_insn (r2, tls_call);
3725 insn = get_insns ();
3726 end_sequence ();
3727
3728 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3729 temp = gen_reg_rtx (Pmode);
3730 emit_libcall_block (insn, temp, r2, new_rtx);
3731
3732 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3733 if (reg != 0)
3734 {
3735 s390_load_address (reg, new_rtx);
3736 new_rtx = reg;
3737 }
3738 break;
3739
3740 case TLS_MODEL_LOCAL_DYNAMIC:
3741 start_sequence ();
3742 r2 = gen_rtx_REG (Pmode, 2);
3743 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3744 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3745 new_rtx = force_const_mem (Pmode, new_rtx);
3746 emit_move_insn (r2, new_rtx);
3747 s390_emit_tls_call_insn (r2, tls_call);
3748 insn = get_insns ();
3749 end_sequence ();
3750
3751 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3752 temp = gen_reg_rtx (Pmode);
3753 emit_libcall_block (insn, temp, r2, new_rtx);
3754
3755 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3756 base = gen_reg_rtx (Pmode);
3757 s390_load_address (base, new_rtx);
3758
3759 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3760 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3761 new_rtx = force_const_mem (Pmode, new_rtx);
3762 temp = gen_reg_rtx (Pmode);
3763 emit_move_insn (temp, new_rtx);
3764
3765 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3766 if (reg != 0)
3767 {
3768 s390_load_address (reg, new_rtx);
3769 new_rtx = reg;
3770 }
3771 break;
3772
3773 case TLS_MODEL_INITIAL_EXEC:
3774 if (flag_pic == 1)
3775 {
3776 /* Assume GOT offset < 4k. This is handled the same way
3777 in both 31- and 64-bit code. */
3778
3779 if (reload_in_progress || reload_completed)
3780 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3781
3782 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3783 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3784 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3785 new_rtx = gen_const_mem (Pmode, new_rtx);
3786 temp = gen_reg_rtx (Pmode);
3787 emit_move_insn (temp, new_rtx);
3788 }
3789 else if (TARGET_CPU_ZARCH)
3790 {
3791 /* If the GOT offset might be >= 4k, we determine the position
3792 of the GOT entry via a PC-relative LARL. */
3793
3794 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3795 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3796 temp = gen_reg_rtx (Pmode);
3797 emit_move_insn (temp, new_rtx);
3798
3799 new_rtx = gen_const_mem (Pmode, temp);
3800 temp = gen_reg_rtx (Pmode);
3801 emit_move_insn (temp, new_rtx);
3802 }
3803 else if (flag_pic)
3804 {
3805 /* If the GOT offset might be >= 4k, we have to load it
3806 from the literal pool. */
3807
3808 if (reload_in_progress || reload_completed)
3809 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3810
3811 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3812 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3813 new_rtx = force_const_mem (Pmode, new_rtx);
3814 temp = gen_reg_rtx (Pmode);
3815 emit_move_insn (temp, new_rtx);
3816
3817 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3818 new_rtx = gen_const_mem (Pmode, new_rtx);
3819
3820 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3821 temp = gen_reg_rtx (Pmode);
3822 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3823 }
3824 else
3825 {
3826 /* In position-dependent code, load the absolute address of
3827 the GOT entry from the literal pool. */
3828
3829 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3830 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3831 new_rtx = force_const_mem (Pmode, new_rtx);
3832 temp = gen_reg_rtx (Pmode);
3833 emit_move_insn (temp, new_rtx);
3834
3835 new_rtx = temp;
3836 new_rtx = gen_const_mem (Pmode, new_rtx);
3837 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3838 temp = gen_reg_rtx (Pmode);
3839 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3840 }
3841
3842 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3843 if (reg != 0)
3844 {
3845 s390_load_address (reg, new_rtx);
3846 new_rtx = reg;
3847 }
3848 break;
3849
3850 case TLS_MODEL_LOCAL_EXEC:
3851 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3852 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3853 new_rtx = force_const_mem (Pmode, new_rtx);
3854 temp = gen_reg_rtx (Pmode);
3855 emit_move_insn (temp, new_rtx);
3856
3857 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3858 if (reg != 0)
3859 {
3860 s390_load_address (reg, new_rtx);
3861 new_rtx = reg;
3862 }
3863 break;
3864
3865 default:
3866 gcc_unreachable ();
3867 }
3868
3869 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3870 {
3871 switch (XINT (XEXP (addr, 0), 1))
3872 {
3873 case UNSPEC_INDNTPOFF:
3874 gcc_assert (TARGET_CPU_ZARCH);
3875 new_rtx = addr;
3876 break;
3877
3878 default:
3879 gcc_unreachable ();
3880 }
3881 }
3882
3883 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3884 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3885 {
3886 new_rtx = XEXP (XEXP (addr, 0), 0);
3887 if (GET_CODE (new_rtx) != SYMBOL_REF)
3888 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3889
3890 new_rtx = legitimize_tls_address (new_rtx, reg);
3891 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3892 new_rtx = force_operand (new_rtx, 0);
3893 }
3894
3895 else
3896 gcc_unreachable (); /* for now ... */
3897
3898 return new_rtx;
3899 }
3900
3901 /* Emit insns making the address in operands[1] valid for a standard
3902 move to operands[0]. operands[1] is replaced by an address which
3903 should be used instead of the former RTX to emit the move
3904 pattern. */
3905
3906 void
3907 emit_symbolic_move (rtx *operands)
3908 {
3909 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3910
3911 if (GET_CODE (operands[0]) == MEM)
3912 operands[1] = force_reg (Pmode, operands[1]);
3913 else if (TLS_SYMBOLIC_CONST (operands[1]))
3914 operands[1] = legitimize_tls_address (operands[1], temp);
3915 else if (flag_pic)
3916 operands[1] = legitimize_pic_address (operands[1], temp);
3917 }
3918
3919 /* Try machine-dependent ways of modifying an illegitimate address X
3920 to be legitimate. If we find one, return the new, valid address.
3921
3922 OLDX is the address as it was before break_out_memory_refs was called.
3923 In some cases it is useful to look at this to decide what needs to be done.
3924
3925 MODE is the mode of the operand pointed to by X.
3926
3927 When -fpic is used, special handling is needed for symbolic references.
3928 See comments by legitimize_pic_address for details. */
3929
3930 static rtx
3931 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3932 enum machine_mode mode ATTRIBUTE_UNUSED)
3933 {
3934 rtx constant_term = const0_rtx;
3935
3936 if (TLS_SYMBOLIC_CONST (x))
3937 {
3938 x = legitimize_tls_address (x, 0);
3939
3940 if (s390_legitimate_address_p (mode, x, FALSE))
3941 return x;
3942 }
3943 else if (GET_CODE (x) == PLUS
3944 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3945 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3946 {
3947 return x;
3948 }
3949 else if (flag_pic)
3950 {
3951 if (SYMBOLIC_CONST (x)
3952 || (GET_CODE (x) == PLUS
3953 && (SYMBOLIC_CONST (XEXP (x, 0))
3954 || SYMBOLIC_CONST (XEXP (x, 1)))))
3955 x = legitimize_pic_address (x, 0);
3956
3957 if (s390_legitimate_address_p (mode, x, FALSE))
3958 return x;
3959 }
3960
3961 x = eliminate_constant_term (x, &constant_term);
3962
3963 /* Optimize loading of large displacements by splitting them
3964 into the multiple of 4K and the rest; this allows the
3965 former to be CSE'd if possible.
3966
3967 Don't do this if the displacement is added to a register
3968 pointing into the stack frame, as the offsets will
3969 change later anyway. */
3970
3971 if (GET_CODE (constant_term) == CONST_INT
3972 && !TARGET_LONG_DISPLACEMENT
3973 && !DISP_IN_RANGE (INTVAL (constant_term))
3974 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3975 {
3976 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3977 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3978
3979 rtx temp = gen_reg_rtx (Pmode);
3980 rtx val = force_operand (GEN_INT (upper), temp);
3981 if (val != temp)
3982 emit_move_insn (temp, val);
3983
3984 x = gen_rtx_PLUS (Pmode, x, temp);
3985 constant_term = GEN_INT (lower);
3986 }
3987
3988 if (GET_CODE (x) == PLUS)
3989 {
3990 if (GET_CODE (XEXP (x, 0)) == REG)
3991 {
3992 rtx temp = gen_reg_rtx (Pmode);
3993 rtx val = force_operand (XEXP (x, 1), temp);
3994 if (val != temp)
3995 emit_move_insn (temp, val);
3996
3997 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3998 }
3999
4000 else if (GET_CODE (XEXP (x, 1)) == REG)
4001 {
4002 rtx temp = gen_reg_rtx (Pmode);
4003 rtx val = force_operand (XEXP (x, 0), temp);
4004 if (val != temp)
4005 emit_move_insn (temp, val);
4006
4007 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4008 }
4009 }
4010
4011 if (constant_term != const0_rtx)
4012 x = gen_rtx_PLUS (Pmode, x, constant_term);
4013
4014 return x;
4015 }
4016
4017 /* Try a machine-dependent way of reloading an illegitimate address AD
4018 operand. If we find one, push the reload and and return the new address.
4019
4020 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4021 and TYPE is the reload type of the current reload. */
4022
4023 rtx
4024 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
4025 int opnum, int type)
4026 {
4027 if (!optimize || TARGET_LONG_DISPLACEMENT)
4028 return NULL_RTX;
4029
4030 if (GET_CODE (ad) == PLUS)
4031 {
4032 rtx tem = simplify_binary_operation (PLUS, Pmode,
4033 XEXP (ad, 0), XEXP (ad, 1));
4034 if (tem)
4035 ad = tem;
4036 }
4037
4038 if (GET_CODE (ad) == PLUS
4039 && GET_CODE (XEXP (ad, 0)) == REG
4040 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4041 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4042 {
4043 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4044 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4045 rtx cst, tem, new_rtx;
4046
4047 cst = GEN_INT (upper);
4048 if (!legitimate_reload_constant_p (cst))
4049 cst = force_const_mem (Pmode, cst);
4050
4051 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4052 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4053
4054 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4055 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4056 opnum, (enum reload_type) type);
4057 return new_rtx;
4058 }
4059
4060 return NULL_RTX;
4061 }
4062
4063 /* Emit code to move LEN bytes from DST to SRC. */
4064
4065 void
4066 s390_expand_movmem (rtx dst, rtx src, rtx len)
4067 {
4068 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4069 {
4070 if (INTVAL (len) > 0)
4071 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4072 }
4073
4074 else if (TARGET_MVCLE)
4075 {
4076 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4077 }
4078
4079 else
4080 {
4081 rtx dst_addr, src_addr, count, blocks, temp;
4082 rtx loop_start_label = gen_label_rtx ();
4083 rtx loop_end_label = gen_label_rtx ();
4084 rtx end_label = gen_label_rtx ();
4085 enum machine_mode mode;
4086
4087 mode = GET_MODE (len);
4088 if (mode == VOIDmode)
4089 mode = Pmode;
4090
4091 dst_addr = gen_reg_rtx (Pmode);
4092 src_addr = gen_reg_rtx (Pmode);
4093 count = gen_reg_rtx (mode);
4094 blocks = gen_reg_rtx (mode);
4095
4096 convert_move (count, len, 1);
4097 emit_cmp_and_jump_insns (count, const0_rtx,
4098 EQ, NULL_RTX, mode, 1, end_label);
4099
4100 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4101 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4102 dst = change_address (dst, VOIDmode, dst_addr);
4103 src = change_address (src, VOIDmode, src_addr);
4104
4105 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4106 OPTAB_DIRECT);
4107 if (temp != count)
4108 emit_move_insn (count, temp);
4109
4110 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4111 OPTAB_DIRECT);
4112 if (temp != blocks)
4113 emit_move_insn (blocks, temp);
4114
4115 emit_cmp_and_jump_insns (blocks, const0_rtx,
4116 EQ, NULL_RTX, mode, 1, loop_end_label);
4117
4118 emit_label (loop_start_label);
4119
4120 if (TARGET_Z10
4121 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4122 {
4123 rtx prefetch;
4124
4125 /* Issue a read prefetch for the +3 cache line. */
4126 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4127 const0_rtx, const0_rtx);
4128 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4129 emit_insn (prefetch);
4130
4131 /* Issue a write prefetch for the +3 cache line. */
4132 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4133 const1_rtx, const0_rtx);
4134 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4135 emit_insn (prefetch);
4136 }
4137
4138 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4139 s390_load_address (dst_addr,
4140 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4141 s390_load_address (src_addr,
4142 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4143
4144 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4145 OPTAB_DIRECT);
4146 if (temp != blocks)
4147 emit_move_insn (blocks, temp);
4148
4149 emit_cmp_and_jump_insns (blocks, const0_rtx,
4150 EQ, NULL_RTX, mode, 1, loop_end_label);
4151
4152 emit_jump (loop_start_label);
4153 emit_label (loop_end_label);
4154
4155 emit_insn (gen_movmem_short (dst, src,
4156 convert_to_mode (Pmode, count, 1)));
4157 emit_label (end_label);
4158 }
4159 }
4160
4161 /* Emit code to set LEN bytes at DST to VAL.
4162 Make use of clrmem if VAL is zero. */
4163
4164 void
4165 s390_expand_setmem (rtx dst, rtx len, rtx val)
4166 {
4167 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4168 return;
4169
4170 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4171
4172 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4173 {
4174 if (val == const0_rtx && INTVAL (len) <= 256)
4175 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4176 else
4177 {
4178 /* Initialize memory by storing the first byte. */
4179 emit_move_insn (adjust_address (dst, QImode, 0), val);
4180
4181 if (INTVAL (len) > 1)
4182 {
4183 /* Initiate 1 byte overlap move.
4184 The first byte of DST is propagated through DSTP1.
4185 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4186 DST is set to size 1 so the rest of the memory location
4187 does not count as source operand. */
4188 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4189 set_mem_size (dst, const1_rtx);
4190
4191 emit_insn (gen_movmem_short (dstp1, dst,
4192 GEN_INT (INTVAL (len) - 2)));
4193 }
4194 }
4195 }
4196
4197 else if (TARGET_MVCLE)
4198 {
4199 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4200 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4201 }
4202
4203 else
4204 {
4205 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4206 rtx loop_start_label = gen_label_rtx ();
4207 rtx loop_end_label = gen_label_rtx ();
4208 rtx end_label = gen_label_rtx ();
4209 enum machine_mode mode;
4210
4211 mode = GET_MODE (len);
4212 if (mode == VOIDmode)
4213 mode = Pmode;
4214
4215 dst_addr = gen_reg_rtx (Pmode);
4216 count = gen_reg_rtx (mode);
4217 blocks = gen_reg_rtx (mode);
4218
4219 convert_move (count, len, 1);
4220 emit_cmp_and_jump_insns (count, const0_rtx,
4221 EQ, NULL_RTX, mode, 1, end_label);
4222
4223 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4224 dst = change_address (dst, VOIDmode, dst_addr);
4225
4226 if (val == const0_rtx)
4227 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4228 OPTAB_DIRECT);
4229 else
4230 {
4231 dstp1 = adjust_address (dst, VOIDmode, 1);
4232 set_mem_size (dst, const1_rtx);
4233
4234 /* Initialize memory by storing the first byte. */
4235 emit_move_insn (adjust_address (dst, QImode, 0), val);
4236
4237 /* If count is 1 we are done. */
4238 emit_cmp_and_jump_insns (count, const1_rtx,
4239 EQ, NULL_RTX, mode, 1, end_label);
4240
4241 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4242 OPTAB_DIRECT);
4243 }
4244 if (temp != count)
4245 emit_move_insn (count, temp);
4246
4247 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4248 OPTAB_DIRECT);
4249 if (temp != blocks)
4250 emit_move_insn (blocks, temp);
4251
4252 emit_cmp_and_jump_insns (blocks, const0_rtx,
4253 EQ, NULL_RTX, mode, 1, loop_end_label);
4254
4255 emit_label (loop_start_label);
4256
4257 if (TARGET_Z10
4258 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4259 {
4260 /* Issue a write prefetch for the +4 cache line. */
4261 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4262 GEN_INT (1024)),
4263 const1_rtx, const0_rtx);
4264 emit_insn (prefetch);
4265 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4266 }
4267
4268 if (val == const0_rtx)
4269 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4270 else
4271 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4272 s390_load_address (dst_addr,
4273 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4274
4275 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4276 OPTAB_DIRECT);
4277 if (temp != blocks)
4278 emit_move_insn (blocks, temp);
4279
4280 emit_cmp_and_jump_insns (blocks, const0_rtx,
4281 EQ, NULL_RTX, mode, 1, loop_end_label);
4282
4283 emit_jump (loop_start_label);
4284 emit_label (loop_end_label);
4285
4286 if (val == const0_rtx)
4287 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4288 else
4289 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4290 emit_label (end_label);
4291 }
4292 }
4293
4294 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4295 and return the result in TARGET. */
4296
4297 void
4298 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4299 {
4300 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4301 rtx tmp;
4302
4303 /* As the result of CMPINT is inverted compared to what we need,
4304 we have to swap the operands. */
4305 tmp = op0; op0 = op1; op1 = tmp;
4306
4307 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4308 {
4309 if (INTVAL (len) > 0)
4310 {
4311 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4312 emit_insn (gen_cmpint (target, ccreg));
4313 }
4314 else
4315 emit_move_insn (target, const0_rtx);
4316 }
4317 else if (TARGET_MVCLE)
4318 {
4319 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4320 emit_insn (gen_cmpint (target, ccreg));
4321 }
4322 else
4323 {
4324 rtx addr0, addr1, count, blocks, temp;
4325 rtx loop_start_label = gen_label_rtx ();
4326 rtx loop_end_label = gen_label_rtx ();
4327 rtx end_label = gen_label_rtx ();
4328 enum machine_mode mode;
4329
4330 mode = GET_MODE (len);
4331 if (mode == VOIDmode)
4332 mode = Pmode;
4333
4334 addr0 = gen_reg_rtx (Pmode);
4335 addr1 = gen_reg_rtx (Pmode);
4336 count = gen_reg_rtx (mode);
4337 blocks = gen_reg_rtx (mode);
4338
4339 convert_move (count, len, 1);
4340 emit_cmp_and_jump_insns (count, const0_rtx,
4341 EQ, NULL_RTX, mode, 1, end_label);
4342
4343 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4344 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4345 op0 = change_address (op0, VOIDmode, addr0);
4346 op1 = change_address (op1, VOIDmode, addr1);
4347
4348 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4349 OPTAB_DIRECT);
4350 if (temp != count)
4351 emit_move_insn (count, temp);
4352
4353 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4354 OPTAB_DIRECT);
4355 if (temp != blocks)
4356 emit_move_insn (blocks, temp);
4357
4358 emit_cmp_and_jump_insns (blocks, const0_rtx,
4359 EQ, NULL_RTX, mode, 1, loop_end_label);
4360
4361 emit_label (loop_start_label);
4362
4363 if (TARGET_Z10
4364 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4365 {
4366 rtx prefetch;
4367
4368 /* Issue a read prefetch for the +2 cache line of operand 1. */
4369 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4370 const0_rtx, const0_rtx);
4371 emit_insn (prefetch);
4372 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4373
4374 /* Issue a read prefetch for the +2 cache line of operand 2. */
4375 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4376 const0_rtx, const0_rtx);
4377 emit_insn (prefetch);
4378 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4379 }
4380
4381 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4382 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4383 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4384 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4385 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4386 emit_jump_insn (temp);
4387
4388 s390_load_address (addr0,
4389 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4390 s390_load_address (addr1,
4391 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4392
4393 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4394 OPTAB_DIRECT);
4395 if (temp != blocks)
4396 emit_move_insn (blocks, temp);
4397
4398 emit_cmp_and_jump_insns (blocks, const0_rtx,
4399 EQ, NULL_RTX, mode, 1, loop_end_label);
4400
4401 emit_jump (loop_start_label);
4402 emit_label (loop_end_label);
4403
4404 emit_insn (gen_cmpmem_short (op0, op1,
4405 convert_to_mode (Pmode, count, 1)));
4406 emit_label (end_label);
4407
4408 emit_insn (gen_cmpint (target, ccreg));
4409 }
4410 }
4411
4412
4413 /* Expand conditional increment or decrement using alc/slb instructions.
4414 Should generate code setting DST to either SRC or SRC + INCREMENT,
4415 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4416 Returns true if successful, false otherwise.
4417
4418 That makes it possible to implement some if-constructs without jumps e.g.:
4419 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4420 unsigned int a, b, c;
4421 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4422 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4423 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4424 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4425
4426 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4427 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4428 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4429 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4430 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4431
4432 bool
4433 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4434 rtx dst, rtx src, rtx increment)
4435 {
4436 enum machine_mode cmp_mode;
4437 enum machine_mode cc_mode;
4438 rtx op_res;
4439 rtx insn;
4440 rtvec p;
4441 int ret;
4442
4443 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4444 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4445 cmp_mode = SImode;
4446 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4447 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4448 cmp_mode = DImode;
4449 else
4450 return false;
4451
4452 /* Try ADD LOGICAL WITH CARRY. */
4453 if (increment == const1_rtx)
4454 {
4455 /* Determine CC mode to use. */
4456 if (cmp_code == EQ || cmp_code == NE)
4457 {
4458 if (cmp_op1 != const0_rtx)
4459 {
4460 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4461 NULL_RTX, 0, OPTAB_WIDEN);
4462 cmp_op1 = const0_rtx;
4463 }
4464
4465 cmp_code = cmp_code == EQ ? LEU : GTU;
4466 }
4467
4468 if (cmp_code == LTU || cmp_code == LEU)
4469 {
4470 rtx tem = cmp_op0;
4471 cmp_op0 = cmp_op1;
4472 cmp_op1 = tem;
4473 cmp_code = swap_condition (cmp_code);
4474 }
4475
4476 switch (cmp_code)
4477 {
4478 case GTU:
4479 cc_mode = CCUmode;
4480 break;
4481
4482 case GEU:
4483 cc_mode = CCL3mode;
4484 break;
4485
4486 default:
4487 return false;
4488 }
4489
4490 /* Emit comparison instruction pattern. */
4491 if (!register_operand (cmp_op0, cmp_mode))
4492 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4493
4494 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4495 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4496 /* We use insn_invalid_p here to add clobbers if required. */
4497 ret = insn_invalid_p (emit_insn (insn));
4498 gcc_assert (!ret);
4499
4500 /* Emit ALC instruction pattern. */
4501 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4502 gen_rtx_REG (cc_mode, CC_REGNUM),
4503 const0_rtx);
4504
4505 if (src != const0_rtx)
4506 {
4507 if (!register_operand (src, GET_MODE (dst)))
4508 src = force_reg (GET_MODE (dst), src);
4509
4510 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4511 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4512 }
4513
4514 p = rtvec_alloc (2);
4515 RTVEC_ELT (p, 0) =
4516 gen_rtx_SET (VOIDmode, dst, op_res);
4517 RTVEC_ELT (p, 1) =
4518 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4519 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4520
4521 return true;
4522 }
4523
4524 /* Try SUBTRACT LOGICAL WITH BORROW. */
4525 if (increment == constm1_rtx)
4526 {
4527 /* Determine CC mode to use. */
4528 if (cmp_code == EQ || cmp_code == NE)
4529 {
4530 if (cmp_op1 != const0_rtx)
4531 {
4532 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4533 NULL_RTX, 0, OPTAB_WIDEN);
4534 cmp_op1 = const0_rtx;
4535 }
4536
4537 cmp_code = cmp_code == EQ ? LEU : GTU;
4538 }
4539
4540 if (cmp_code == GTU || cmp_code == GEU)
4541 {
4542 rtx tem = cmp_op0;
4543 cmp_op0 = cmp_op1;
4544 cmp_op1 = tem;
4545 cmp_code = swap_condition (cmp_code);
4546 }
4547
4548 switch (cmp_code)
4549 {
4550 case LEU:
4551 cc_mode = CCUmode;
4552 break;
4553
4554 case LTU:
4555 cc_mode = CCL3mode;
4556 break;
4557
4558 default:
4559 return false;
4560 }
4561
4562 /* Emit comparison instruction pattern. */
4563 if (!register_operand (cmp_op0, cmp_mode))
4564 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4565
4566 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4567 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4568 /* We use insn_invalid_p here to add clobbers if required. */
4569 ret = insn_invalid_p (emit_insn (insn));
4570 gcc_assert (!ret);
4571
4572 /* Emit SLB instruction pattern. */
4573 if (!register_operand (src, GET_MODE (dst)))
4574 src = force_reg (GET_MODE (dst), src);
4575
4576 op_res = gen_rtx_MINUS (GET_MODE (dst),
4577 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4578 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4579 gen_rtx_REG (cc_mode, CC_REGNUM),
4580 const0_rtx));
4581 p = rtvec_alloc (2);
4582 RTVEC_ELT (p, 0) =
4583 gen_rtx_SET (VOIDmode, dst, op_res);
4584 RTVEC_ELT (p, 1) =
4585 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4586 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4587
4588 return true;
4589 }
4590
4591 return false;
4592 }
4593
4594 /* Expand code for the insv template. Return true if successful. */
4595
4596 bool
4597 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4598 {
4599 int bitsize = INTVAL (op1);
4600 int bitpos = INTVAL (op2);
4601
4602 /* On z10 we can use the risbg instruction to implement insv. */
4603 if (TARGET_Z10
4604 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4605 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4606 {
4607 rtx op;
4608 rtx clobber;
4609
4610 op = gen_rtx_SET (GET_MODE(src),
4611 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4612 src);
4613 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4614 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4615
4616 return true;
4617 }
4618
4619 /* We need byte alignment. */
4620 if (bitsize % BITS_PER_UNIT)
4621 return false;
4622
4623 if (bitpos == 0
4624 && memory_operand (dest, VOIDmode)
4625 && (register_operand (src, word_mode)
4626 || const_int_operand (src, VOIDmode)))
4627 {
4628 /* Emit standard pattern if possible. */
4629 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4630 if (GET_MODE_BITSIZE (mode) == bitsize)
4631 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4632
4633 /* (set (ze (mem)) (const_int)). */
4634 else if (const_int_operand (src, VOIDmode))
4635 {
4636 int size = bitsize / BITS_PER_UNIT;
4637 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4638 GET_MODE_SIZE (word_mode) - size);
4639
4640 dest = adjust_address (dest, BLKmode, 0);
4641 set_mem_size (dest, GEN_INT (size));
4642 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4643 }
4644
4645 /* (set (ze (mem)) (reg)). */
4646 else if (register_operand (src, word_mode))
4647 {
4648 if (bitsize <= GET_MODE_BITSIZE (SImode))
4649 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4650 const0_rtx), src);
4651 else
4652 {
4653 /* Emit st,stcmh sequence. */
4654 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4655 int size = stcmh_width / BITS_PER_UNIT;
4656
4657 emit_move_insn (adjust_address (dest, SImode, size),
4658 gen_lowpart (SImode, src));
4659 set_mem_size (dest, GEN_INT (size));
4660 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4661 (stcmh_width), const0_rtx),
4662 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4663 (GET_MODE_BITSIZE (SImode))));
4664 }
4665 }
4666 else
4667 return false;
4668
4669 return true;
4670 }
4671
4672 /* (set (ze (reg)) (const_int)). */
4673 if (TARGET_ZARCH
4674 && register_operand (dest, word_mode)
4675 && (bitpos % 16) == 0
4676 && (bitsize % 16) == 0
4677 && const_int_operand (src, VOIDmode))
4678 {
4679 HOST_WIDE_INT val = INTVAL (src);
4680 int regpos = bitpos + bitsize;
4681
4682 while (regpos > bitpos)
4683 {
4684 enum machine_mode putmode;
4685 int putsize;
4686
4687 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4688 putmode = SImode;
4689 else
4690 putmode = HImode;
4691
4692 putsize = GET_MODE_BITSIZE (putmode);
4693 regpos -= putsize;
4694 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4695 GEN_INT (putsize),
4696 GEN_INT (regpos)),
4697 gen_int_mode (val, putmode));
4698 val >>= putsize;
4699 }
4700 gcc_assert (regpos == bitpos);
4701 return true;
4702 }
4703
4704 return false;
4705 }
4706
4707 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4708 register that holds VAL of mode MODE shifted by COUNT bits. */
4709
4710 static inline rtx
4711 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4712 {
4713 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4714 NULL_RTX, 1, OPTAB_DIRECT);
4715 return expand_simple_binop (SImode, ASHIFT, val, count,
4716 NULL_RTX, 1, OPTAB_DIRECT);
4717 }
4718
4719 /* Structure to hold the initial parameters for a compare_and_swap operation
4720 in HImode and QImode. */
4721
4722 struct alignment_context
4723 {
4724 rtx memsi; /* SI aligned memory location. */
4725 rtx shift; /* Bit offset with regard to lsb. */
4726 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4727 rtx modemaski; /* ~modemask */
4728 bool aligned; /* True if memory is aligned, false else. */
4729 };
4730
4731 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4732 structure AC for transparent simplifying, if the memory alignment is known
4733 to be at least 32bit. MEM is the memory location for the actual operation
4734 and MODE its mode. */
4735
4736 static void
4737 init_alignment_context (struct alignment_context *ac, rtx mem,
4738 enum machine_mode mode)
4739 {
4740 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4741 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4742
4743 if (ac->aligned)
4744 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4745 else
4746 {
4747 /* Alignment is unknown. */
4748 rtx byteoffset, addr, align;
4749
4750 /* Force the address into a register. */
4751 addr = force_reg (Pmode, XEXP (mem, 0));
4752
4753 /* Align it to SImode. */
4754 align = expand_simple_binop (Pmode, AND, addr,
4755 GEN_INT (-GET_MODE_SIZE (SImode)),
4756 NULL_RTX, 1, OPTAB_DIRECT);
4757 /* Generate MEM. */
4758 ac->memsi = gen_rtx_MEM (SImode, align);
4759 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4760 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4761 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4762
4763 /* Calculate shiftcount. */
4764 byteoffset = expand_simple_binop (Pmode, AND, addr,
4765 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4766 NULL_RTX, 1, OPTAB_DIRECT);
4767 /* As we already have some offset, evaluate the remaining distance. */
4768 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4769 NULL_RTX, 1, OPTAB_DIRECT);
4770
4771 }
4772 /* Shift is the byte count, but we need the bitcount. */
4773 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4774 NULL_RTX, 1, OPTAB_DIRECT);
4775 /* Calculate masks. */
4776 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4777 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4778 NULL_RTX, 1, OPTAB_DIRECT);
4779 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4780 }
4781
4782 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4783 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4784 to set if CMP == MEM.
4785 CMP is never in memory for compare_and_swap_cc because
4786 expand_bool_compare_and_swap puts it into a register for later compare. */
4787
4788 void
4789 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4790 {
4791 struct alignment_context ac;
4792 rtx cmpv, newv, val, resv, cc;
4793 rtx res = gen_reg_rtx (SImode);
4794 rtx csloop = gen_label_rtx ();
4795 rtx csend = gen_label_rtx ();
4796
4797 gcc_assert (register_operand (target, VOIDmode));
4798 gcc_assert (MEM_P (mem));
4799
4800 init_alignment_context (&ac, mem, mode);
4801
4802 /* Shift the values to the correct bit positions. */
4803 if (!(ac.aligned && MEM_P (cmp)))
4804 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4805 if (!(ac.aligned && MEM_P (new_rtx)))
4806 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4807
4808 /* Load full word. Subsequent loads are performed by CS. */
4809 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4810 NULL_RTX, 1, OPTAB_DIRECT);
4811
4812 /* Start CS loop. */
4813 emit_label (csloop);
4814 /* val = "<mem>00..0<mem>"
4815 * cmp = "00..0<cmp>00..0"
4816 * new = "00..0<new>00..0"
4817 */
4818
4819 /* Patch cmp and new with val at correct position. */
4820 if (ac.aligned && MEM_P (cmp))
4821 {
4822 cmpv = force_reg (SImode, val);
4823 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4824 }
4825 else
4826 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4827 NULL_RTX, 1, OPTAB_DIRECT));
4828 if (ac.aligned && MEM_P (new_rtx))
4829 {
4830 newv = force_reg (SImode, val);
4831 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4832 }
4833 else
4834 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4835 NULL_RTX, 1, OPTAB_DIRECT));
4836
4837 /* Jump to end if we're done (likely?). */
4838 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4839 cmpv, newv));
4840
4841 /* Check for changes outside mode. */
4842 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4843 NULL_RTX, 1, OPTAB_DIRECT);
4844 cc = s390_emit_compare (NE, resv, val);
4845 emit_move_insn (val, resv);
4846 /* Loop internal if so. */
4847 s390_emit_jump (csloop, cc);
4848
4849 emit_label (csend);
4850
4851 /* Return the correct part of the bitfield. */
4852 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4853 NULL_RTX, 1, OPTAB_DIRECT), 1);
4854 }
4855
4856 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4857 and VAL the value to play with. If AFTER is true then store the value
4858 MEM holds after the operation, if AFTER is false then store the value MEM
4859 holds before the operation. If TARGET is zero then discard that value, else
4860 store it to TARGET. */
4861
4862 void
4863 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4864 rtx target, rtx mem, rtx val, bool after)
4865 {
4866 struct alignment_context ac;
4867 rtx cmp;
4868 rtx new_rtx = gen_reg_rtx (SImode);
4869 rtx orig = gen_reg_rtx (SImode);
4870 rtx csloop = gen_label_rtx ();
4871
4872 gcc_assert (!target || register_operand (target, VOIDmode));
4873 gcc_assert (MEM_P (mem));
4874
4875 init_alignment_context (&ac, mem, mode);
4876
4877 /* Shift val to the correct bit positions.
4878 Preserve "icm", but prevent "ex icm". */
4879 if (!(ac.aligned && code == SET && MEM_P (val)))
4880 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4881
4882 /* Further preparation insns. */
4883 if (code == PLUS || code == MINUS)
4884 emit_move_insn (orig, val);
4885 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4886 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4887 NULL_RTX, 1, OPTAB_DIRECT);
4888
4889 /* Load full word. Subsequent loads are performed by CS. */
4890 cmp = force_reg (SImode, ac.memsi);
4891
4892 /* Start CS loop. */
4893 emit_label (csloop);
4894 emit_move_insn (new_rtx, cmp);
4895
4896 /* Patch new with val at correct position. */
4897 switch (code)
4898 {
4899 case PLUS:
4900 case MINUS:
4901 val = expand_simple_binop (SImode, code, new_rtx, orig,
4902 NULL_RTX, 1, OPTAB_DIRECT);
4903 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4904 NULL_RTX, 1, OPTAB_DIRECT);
4905 /* FALLTHRU */
4906 case SET:
4907 if (ac.aligned && MEM_P (val))
4908 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4909 else
4910 {
4911 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4912 NULL_RTX, 1, OPTAB_DIRECT);
4913 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4914 NULL_RTX, 1, OPTAB_DIRECT);
4915 }
4916 break;
4917 case AND:
4918 case IOR:
4919 case XOR:
4920 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4921 NULL_RTX, 1, OPTAB_DIRECT);
4922 break;
4923 case MULT: /* NAND */
4924 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4925 NULL_RTX, 1, OPTAB_DIRECT);
4926 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4927 NULL_RTX, 1, OPTAB_DIRECT);
4928 break;
4929 default:
4930 gcc_unreachable ();
4931 }
4932
4933 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4934 ac.memsi, cmp, new_rtx));
4935
4936 /* Return the correct part of the bitfield. */
4937 if (target)
4938 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4939 after ? new_rtx : cmp, ac.shift,
4940 NULL_RTX, 1, OPTAB_DIRECT), 1);
4941 }
4942
4943 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4944 We need to emit DTP-relative relocations. */
4945
4946 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4947
4948 static void
4949 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4950 {
4951 switch (size)
4952 {
4953 case 4:
4954 fputs ("\t.long\t", file);
4955 break;
4956 case 8:
4957 fputs ("\t.quad\t", file);
4958 break;
4959 default:
4960 gcc_unreachable ();
4961 }
4962 output_addr_const (file, x);
4963 fputs ("@DTPOFF", file);
4964 }
4965
4966 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4967 /* Implement TARGET_MANGLE_TYPE. */
4968
4969 static const char *
4970 s390_mangle_type (const_tree type)
4971 {
4972 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4973 && TARGET_LONG_DOUBLE_128)
4974 return "g";
4975
4976 /* For all other types, use normal C++ mangling. */
4977 return NULL;
4978 }
4979 #endif
4980
4981 /* In the name of slightly smaller debug output, and to cater to
4982 general assembler lossage, recognize various UNSPEC sequences
4983 and turn them back into a direct symbol reference. */
4984
4985 static rtx
4986 s390_delegitimize_address (rtx orig_x)
4987 {
4988 rtx x, y;
4989
4990 orig_x = delegitimize_mem_from_attrs (orig_x);
4991 x = orig_x;
4992 if (GET_CODE (x) != MEM)
4993 return orig_x;
4994
4995 x = XEXP (x, 0);
4996 if (GET_CODE (x) == PLUS
4997 && GET_CODE (XEXP (x, 1)) == CONST
4998 && GET_CODE (XEXP (x, 0)) == REG
4999 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5000 {
5001 y = XEXP (XEXP (x, 1), 0);
5002 if (GET_CODE (y) == UNSPEC
5003 && XINT (y, 1) == UNSPEC_GOT)
5004 return XVECEXP (y, 0, 0);
5005 return orig_x;
5006 }
5007
5008 if (GET_CODE (x) == CONST)
5009 {
5010 y = XEXP (x, 0);
5011 if (GET_CODE (y) == UNSPEC
5012 && XINT (y, 1) == UNSPEC_GOTENT)
5013 return XVECEXP (y, 0, 0);
5014 return orig_x;
5015 }
5016
5017 return orig_x;
5018 }
5019
5020 /* Output operand OP to stdio stream FILE.
5021 OP is an address (register + offset) which is not used to address data;
5022 instead the rightmost bits are interpreted as the value. */
5023
5024 static void
5025 print_shift_count_operand (FILE *file, rtx op)
5026 {
5027 HOST_WIDE_INT offset;
5028 rtx base;
5029
5030 /* Extract base register and offset. */
5031 if (!s390_decompose_shift_count (op, &base, &offset))
5032 gcc_unreachable ();
5033
5034 /* Sanity check. */
5035 if (base)
5036 {
5037 gcc_assert (GET_CODE (base) == REG);
5038 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5039 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5040 }
5041
5042 /* Offsets are constricted to twelve bits. */
5043 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5044 if (base)
5045 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5046 }
5047
5048 /* See 'get_some_local_dynamic_name'. */
5049
5050 static int
5051 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5052 {
5053 rtx x = *px;
5054
5055 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5056 {
5057 x = get_pool_constant (x);
5058 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5059 }
5060
5061 if (GET_CODE (x) == SYMBOL_REF
5062 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5063 {
5064 cfun->machine->some_ld_name = XSTR (x, 0);
5065 return 1;
5066 }
5067
5068 return 0;
5069 }
5070
5071 /* Locate some local-dynamic symbol still in use by this function
5072 so that we can print its name in local-dynamic base patterns. */
5073
5074 static const char *
5075 get_some_local_dynamic_name (void)
5076 {
5077 rtx insn;
5078
5079 if (cfun->machine->some_ld_name)
5080 return cfun->machine->some_ld_name;
5081
5082 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5083 if (INSN_P (insn)
5084 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5085 return cfun->machine->some_ld_name;
5086
5087 gcc_unreachable ();
5088 }
5089
5090 /* Output machine-dependent UNSPECs occurring in address constant X
5091 in assembler syntax to stdio stream FILE. Returns true if the
5092 constant X could be recognized, false otherwise. */
5093
5094 static bool
5095 s390_output_addr_const_extra (FILE *file, rtx x)
5096 {
5097 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5098 switch (XINT (x, 1))
5099 {
5100 case UNSPEC_GOTENT:
5101 output_addr_const (file, XVECEXP (x, 0, 0));
5102 fprintf (file, "@GOTENT");
5103 return true;
5104 case UNSPEC_GOT:
5105 output_addr_const (file, XVECEXP (x, 0, 0));
5106 fprintf (file, "@GOT");
5107 return true;
5108 case UNSPEC_GOTOFF:
5109 output_addr_const (file, XVECEXP (x, 0, 0));
5110 fprintf (file, "@GOTOFF");
5111 return true;
5112 case UNSPEC_PLT:
5113 output_addr_const (file, XVECEXP (x, 0, 0));
5114 fprintf (file, "@PLT");
5115 return true;
5116 case UNSPEC_PLTOFF:
5117 output_addr_const (file, XVECEXP (x, 0, 0));
5118 fprintf (file, "@PLTOFF");
5119 return true;
5120 case UNSPEC_TLSGD:
5121 output_addr_const (file, XVECEXP (x, 0, 0));
5122 fprintf (file, "@TLSGD");
5123 return true;
5124 case UNSPEC_TLSLDM:
5125 assemble_name (file, get_some_local_dynamic_name ());
5126 fprintf (file, "@TLSLDM");
5127 return true;
5128 case UNSPEC_DTPOFF:
5129 output_addr_const (file, XVECEXP (x, 0, 0));
5130 fprintf (file, "@DTPOFF");
5131 return true;
5132 case UNSPEC_NTPOFF:
5133 output_addr_const (file, XVECEXP (x, 0, 0));
5134 fprintf (file, "@NTPOFF");
5135 return true;
5136 case UNSPEC_GOTNTPOFF:
5137 output_addr_const (file, XVECEXP (x, 0, 0));
5138 fprintf (file, "@GOTNTPOFF");
5139 return true;
5140 case UNSPEC_INDNTPOFF:
5141 output_addr_const (file, XVECEXP (x, 0, 0));
5142 fprintf (file, "@INDNTPOFF");
5143 return true;
5144 }
5145
5146 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5147 switch (XINT (x, 1))
5148 {
5149 case UNSPEC_POOL_OFFSET:
5150 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5151 output_addr_const (file, x);
5152 return true;
5153 }
5154 return false;
5155 }
5156
5157 /* Output address operand ADDR in assembler syntax to
5158 stdio stream FILE. */
5159
5160 void
5161 print_operand_address (FILE *file, rtx addr)
5162 {
5163 struct s390_address ad;
5164
5165 if (s390_symref_operand_p (addr, NULL, NULL))
5166 {
5167 if (!TARGET_Z10)
5168 {
5169 output_operand_lossage ("symbolic memory references are "
5170 "only supported on z10 or later");
5171 return;
5172 }
5173 output_addr_const (file, addr);
5174 return;
5175 }
5176
5177 if (!s390_decompose_address (addr, &ad)
5178 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5179 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5180 output_operand_lossage ("cannot decompose address");
5181
5182 if (ad.disp)
5183 output_addr_const (file, ad.disp);
5184 else
5185 fprintf (file, "0");
5186
5187 if (ad.base && ad.indx)
5188 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5189 reg_names[REGNO (ad.base)]);
5190 else if (ad.base)
5191 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5192 }
5193
5194 /* Output operand X in assembler syntax to stdio stream FILE.
5195 CODE specified the format flag. The following format flags
5196 are recognized:
5197
5198 'C': print opcode suffix for branch condition.
5199 'D': print opcode suffix for inverse branch condition.
5200 'E': print opcode suffix for branch on index instruction.
5201 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5202 'G': print the size of the operand in bytes.
5203 'O': print only the displacement of a memory reference.
5204 'R': print only the base register of a memory reference.
5205 'S': print S-type memory reference (base+displacement).
5206 'N': print the second word of a DImode operand.
5207 'M': print the second word of a TImode operand.
5208 'Y': print shift count operand.
5209
5210 'b': print integer X as if it's an unsigned byte.
5211 'c': print integer X as if it's an signed byte.
5212 'x': print integer X as if it's an unsigned halfword.
5213 'h': print integer X as if it's a signed halfword.
5214 'i': print the first nonzero HImode part of X.
5215 'j': print the first HImode part unequal to -1 of X.
5216 'k': print the first nonzero SImode part of X.
5217 'm': print the first SImode part unequal to -1 of X.
5218 'o': print integer X as if it's an unsigned 32bit word. */
5219
5220 void
5221 print_operand (FILE *file, rtx x, int code)
5222 {
5223 switch (code)
5224 {
5225 case 'C':
5226 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5227 return;
5228
5229 case 'D':
5230 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5231 return;
5232
5233 case 'E':
5234 if (GET_CODE (x) == LE)
5235 fprintf (file, "l");
5236 else if (GET_CODE (x) == GT)
5237 fprintf (file, "h");
5238 else
5239 output_operand_lossage ("invalid comparison operator "
5240 "for 'E' output modifier");
5241 return;
5242
5243 case 'J':
5244 if (GET_CODE (x) == SYMBOL_REF)
5245 {
5246 fprintf (file, "%s", ":tls_load:");
5247 output_addr_const (file, x);
5248 }
5249 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5250 {
5251 fprintf (file, "%s", ":tls_gdcall:");
5252 output_addr_const (file, XVECEXP (x, 0, 0));
5253 }
5254 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5255 {
5256 fprintf (file, "%s", ":tls_ldcall:");
5257 assemble_name (file, get_some_local_dynamic_name ());
5258 }
5259 else
5260 output_operand_lossage ("invalid reference for 'J' output modifier");
5261 return;
5262
5263 case 'G':
5264 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5265 return;
5266
5267 case 'O':
5268 {
5269 struct s390_address ad;
5270 int ret;
5271
5272 if (!MEM_P (x))
5273 {
5274 output_operand_lossage ("memory reference expected for "
5275 "'O' output modifier");
5276 return;
5277 }
5278
5279 ret = s390_decompose_address (XEXP (x, 0), &ad);
5280
5281 if (!ret
5282 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5283 || ad.indx)
5284 {
5285 output_operand_lossage ("invalid address for 'O' output modifier");
5286 return;
5287 }
5288
5289 if (ad.disp)
5290 output_addr_const (file, ad.disp);
5291 else
5292 fprintf (file, "0");
5293 }
5294 return;
5295
5296 case 'R':
5297 {
5298 struct s390_address ad;
5299 int ret;
5300
5301 if (!MEM_P (x))
5302 {
5303 output_operand_lossage ("memory reference expected for "
5304 "'R' output modifier");
5305 return;
5306 }
5307
5308 ret = s390_decompose_address (XEXP (x, 0), &ad);
5309
5310 if (!ret
5311 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5312 || ad.indx)
5313 {
5314 output_operand_lossage ("invalid address for 'R' output modifier");
5315 return;
5316 }
5317
5318 if (ad.base)
5319 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5320 else
5321 fprintf (file, "0");
5322 }
5323 return;
5324
5325 case 'S':
5326 {
5327 struct s390_address ad;
5328 int ret;
5329
5330 if (!MEM_P (x))
5331 {
5332 output_operand_lossage ("memory reference expected for "
5333 "'S' output modifier");
5334 return;
5335 }
5336 ret = s390_decompose_address (XEXP (x, 0), &ad);
5337
5338 if (!ret
5339 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5340 || ad.indx)
5341 {
5342 output_operand_lossage ("invalid address for 'S' output modifier");
5343 return;
5344 }
5345
5346 if (ad.disp)
5347 output_addr_const (file, ad.disp);
5348 else
5349 fprintf (file, "0");
5350
5351 if (ad.base)
5352 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5353 }
5354 return;
5355
5356 case 'N':
5357 if (GET_CODE (x) == REG)
5358 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5359 else if (GET_CODE (x) == MEM)
5360 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5361 else
5362 output_operand_lossage ("register or memory expression expected "
5363 "for 'N' output modifier");
5364 break;
5365
5366 case 'M':
5367 if (GET_CODE (x) == REG)
5368 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5369 else if (GET_CODE (x) == MEM)
5370 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5371 else
5372 output_operand_lossage ("register or memory expression expected "
5373 "for 'M' output modifier");
5374 break;
5375
5376 case 'Y':
5377 print_shift_count_operand (file, x);
5378 return;
5379 }
5380
5381 switch (GET_CODE (x))
5382 {
5383 case REG:
5384 fprintf (file, "%s", reg_names[REGNO (x)]);
5385 break;
5386
5387 case MEM:
5388 output_address (XEXP (x, 0));
5389 break;
5390
5391 case CONST:
5392 case CODE_LABEL:
5393 case LABEL_REF:
5394 case SYMBOL_REF:
5395 output_addr_const (file, x);
5396 break;
5397
5398 case CONST_INT:
5399 if (code == 'b')
5400 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5401 else if (code == 'c')
5402 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5403 else if (code == 'x')
5404 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5405 else if (code == 'h')
5406 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5407 else if (code == 'i')
5408 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5409 s390_extract_part (x, HImode, 0));
5410 else if (code == 'j')
5411 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5412 s390_extract_part (x, HImode, -1));
5413 else if (code == 'k')
5414 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5415 s390_extract_part (x, SImode, 0));
5416 else if (code == 'm')
5417 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5418 s390_extract_part (x, SImode, -1));
5419 else if (code == 'o')
5420 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5421 else
5422 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5423 break;
5424
5425 case CONST_DOUBLE:
5426 gcc_assert (GET_MODE (x) == VOIDmode);
5427 if (code == 'b')
5428 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5429 else if (code == 'x')
5430 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5431 else if (code == 'h')
5432 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5433 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5434 else
5435 {
5436 if (code == 0)
5437 output_operand_lossage ("invalid constant - try using "
5438 "an output modifier");
5439 else
5440 output_operand_lossage ("invalid constant for output modifier '%c'",
5441 code);
5442 }
5443 break;
5444
5445 default:
5446 if (code == 0)
5447 output_operand_lossage ("invalid expression - try using "
5448 "an output modifier");
5449 else
5450 output_operand_lossage ("invalid expression for output "
5451 "modifier '%c'", code);
5452 break;
5453 }
5454 }
5455
5456 /* Target hook for assembling integer objects. We need to define it
5457 here to work a round a bug in some versions of GAS, which couldn't
5458 handle values smaller than INT_MIN when printed in decimal. */
5459
5460 static bool
5461 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5462 {
5463 if (size == 8 && aligned_p
5464 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5465 {
5466 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5467 INTVAL (x));
5468 return true;
5469 }
5470 return default_assemble_integer (x, size, aligned_p);
5471 }
5472
5473 /* Returns true if register REGNO is used for forming
5474 a memory address in expression X. */
5475
5476 static bool
5477 reg_used_in_mem_p (int regno, rtx x)
5478 {
5479 enum rtx_code code = GET_CODE (x);
5480 int i, j;
5481 const char *fmt;
5482
5483 if (code == MEM)
5484 {
5485 if (refers_to_regno_p (regno, regno+1,
5486 XEXP (x, 0), 0))
5487 return true;
5488 }
5489 else if (code == SET
5490 && GET_CODE (SET_DEST (x)) == PC)
5491 {
5492 if (refers_to_regno_p (regno, regno+1,
5493 SET_SRC (x), 0))
5494 return true;
5495 }
5496
5497 fmt = GET_RTX_FORMAT (code);
5498 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5499 {
5500 if (fmt[i] == 'e'
5501 && reg_used_in_mem_p (regno, XEXP (x, i)))
5502 return true;
5503
5504 else if (fmt[i] == 'E')
5505 for (j = 0; j < XVECLEN (x, i); j++)
5506 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5507 return true;
5508 }
5509 return false;
5510 }
5511
5512 /* Returns true if expression DEP_RTX sets an address register
5513 used by instruction INSN to address memory. */
5514
5515 static bool
5516 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5517 {
5518 rtx target, pat;
5519
5520 if (GET_CODE (dep_rtx) == INSN)
5521 dep_rtx = PATTERN (dep_rtx);
5522
5523 if (GET_CODE (dep_rtx) == SET)
5524 {
5525 target = SET_DEST (dep_rtx);
5526 if (GET_CODE (target) == STRICT_LOW_PART)
5527 target = XEXP (target, 0);
5528 while (GET_CODE (target) == SUBREG)
5529 target = SUBREG_REG (target);
5530
5531 if (GET_CODE (target) == REG)
5532 {
5533 int regno = REGNO (target);
5534
5535 if (s390_safe_attr_type (insn) == TYPE_LA)
5536 {
5537 pat = PATTERN (insn);
5538 if (GET_CODE (pat) == PARALLEL)
5539 {
5540 gcc_assert (XVECLEN (pat, 0) == 2);
5541 pat = XVECEXP (pat, 0, 0);
5542 }
5543 gcc_assert (GET_CODE (pat) == SET);
5544 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5545 }
5546 else if (get_attr_atype (insn) == ATYPE_AGEN)
5547 return reg_used_in_mem_p (regno, PATTERN (insn));
5548 }
5549 }
5550 return false;
5551 }
5552
5553 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5554
5555 int
5556 s390_agen_dep_p (rtx dep_insn, rtx insn)
5557 {
5558 rtx dep_rtx = PATTERN (dep_insn);
5559 int i;
5560
5561 if (GET_CODE (dep_rtx) == SET
5562 && addr_generation_dependency_p (dep_rtx, insn))
5563 return 1;
5564 else if (GET_CODE (dep_rtx) == PARALLEL)
5565 {
5566 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5567 {
5568 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5569 return 1;
5570 }
5571 }
5572 return 0;
5573 }
5574
5575
5576 /* A C statement (sans semicolon) to update the integer scheduling priority
5577 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5578 reduce the priority to execute INSN later. Do not define this macro if
5579 you do not need to adjust the scheduling priorities of insns.
5580
5581 A STD instruction should be scheduled earlier,
5582 in order to use the bypass. */
5583 static int
5584 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5585 {
5586 if (! INSN_P (insn))
5587 return priority;
5588
5589 if (s390_tune != PROCESSOR_2084_Z990
5590 && s390_tune != PROCESSOR_2094_Z9_109
5591 && s390_tune != PROCESSOR_2097_Z10
5592 && s390_tune != PROCESSOR_2817_Z196)
5593 return priority;
5594
5595 switch (s390_safe_attr_type (insn))
5596 {
5597 case TYPE_FSTOREDF:
5598 case TYPE_FSTORESF:
5599 priority = priority << 3;
5600 break;
5601 case TYPE_STORE:
5602 case TYPE_STM:
5603 priority = priority << 1;
5604 break;
5605 default:
5606 break;
5607 }
5608 return priority;
5609 }
5610
5611
5612 /* The number of instructions that can be issued per cycle. */
5613
5614 static int
5615 s390_issue_rate (void)
5616 {
5617 switch (s390_tune)
5618 {
5619 case PROCESSOR_2084_Z990:
5620 case PROCESSOR_2094_Z9_109:
5621 case PROCESSOR_2817_Z196:
5622 return 3;
5623 case PROCESSOR_2097_Z10:
5624 return 2;
5625 default:
5626 return 1;
5627 }
5628 }
5629
5630 static int
5631 s390_first_cycle_multipass_dfa_lookahead (void)
5632 {
5633 return 4;
5634 }
5635
5636 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5637 Fix up MEMs as required. */
5638
5639 static void
5640 annotate_constant_pool_refs (rtx *x)
5641 {
5642 int i, j;
5643 const char *fmt;
5644
5645 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5646 || !CONSTANT_POOL_ADDRESS_P (*x));
5647
5648 /* Literal pool references can only occur inside a MEM ... */
5649 if (GET_CODE (*x) == MEM)
5650 {
5651 rtx memref = XEXP (*x, 0);
5652
5653 if (GET_CODE (memref) == SYMBOL_REF
5654 && CONSTANT_POOL_ADDRESS_P (memref))
5655 {
5656 rtx base = cfun->machine->base_reg;
5657 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5658 UNSPEC_LTREF);
5659
5660 *x = replace_equiv_address (*x, addr);
5661 return;
5662 }
5663
5664 if (GET_CODE (memref) == CONST
5665 && GET_CODE (XEXP (memref, 0)) == PLUS
5666 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5667 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5668 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5669 {
5670 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5671 rtx sym = XEXP (XEXP (memref, 0), 0);
5672 rtx base = cfun->machine->base_reg;
5673 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5674 UNSPEC_LTREF);
5675
5676 *x = replace_equiv_address (*x, plus_constant (addr, off));
5677 return;
5678 }
5679 }
5680
5681 /* ... or a load-address type pattern. */
5682 if (GET_CODE (*x) == SET)
5683 {
5684 rtx addrref = SET_SRC (*x);
5685
5686 if (GET_CODE (addrref) == SYMBOL_REF
5687 && CONSTANT_POOL_ADDRESS_P (addrref))
5688 {
5689 rtx base = cfun->machine->base_reg;
5690 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5691 UNSPEC_LTREF);
5692
5693 SET_SRC (*x) = addr;
5694 return;
5695 }
5696
5697 if (GET_CODE (addrref) == CONST
5698 && GET_CODE (XEXP (addrref, 0)) == PLUS
5699 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5700 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5701 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5702 {
5703 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5704 rtx sym = XEXP (XEXP (addrref, 0), 0);
5705 rtx base = cfun->machine->base_reg;
5706 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5707 UNSPEC_LTREF);
5708
5709 SET_SRC (*x) = plus_constant (addr, off);
5710 return;
5711 }
5712 }
5713
5714 /* Annotate LTREL_BASE as well. */
5715 if (GET_CODE (*x) == UNSPEC
5716 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5717 {
5718 rtx base = cfun->machine->base_reg;
5719 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5720 UNSPEC_LTREL_BASE);
5721 return;
5722 }
5723
5724 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5725 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5726 {
5727 if (fmt[i] == 'e')
5728 {
5729 annotate_constant_pool_refs (&XEXP (*x, i));
5730 }
5731 else if (fmt[i] == 'E')
5732 {
5733 for (j = 0; j < XVECLEN (*x, i); j++)
5734 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5735 }
5736 }
5737 }
5738
5739 /* Split all branches that exceed the maximum distance.
5740 Returns true if this created a new literal pool entry. */
5741
5742 static int
5743 s390_split_branches (void)
5744 {
5745 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5746 int new_literal = 0, ret;
5747 rtx insn, pat, tmp, target;
5748 rtx *label;
5749
5750 /* We need correct insn addresses. */
5751
5752 shorten_branches (get_insns ());
5753
5754 /* Find all branches that exceed 64KB, and split them. */
5755
5756 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5757 {
5758 if (GET_CODE (insn) != JUMP_INSN)
5759 continue;
5760
5761 pat = PATTERN (insn);
5762 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5763 pat = XVECEXP (pat, 0, 0);
5764 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5765 continue;
5766
5767 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5768 {
5769 label = &SET_SRC (pat);
5770 }
5771 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5772 {
5773 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5774 label = &XEXP (SET_SRC (pat), 1);
5775 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5776 label = &XEXP (SET_SRC (pat), 2);
5777 else
5778 continue;
5779 }
5780 else
5781 continue;
5782
5783 if (get_attr_length (insn) <= 4)
5784 continue;
5785
5786 /* We are going to use the return register as scratch register,
5787 make sure it will be saved/restored by the prologue/epilogue. */
5788 cfun_frame_layout.save_return_addr_p = 1;
5789
5790 if (!flag_pic)
5791 {
5792 new_literal = 1;
5793 tmp = force_const_mem (Pmode, *label);
5794 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5795 INSN_ADDRESSES_NEW (tmp, -1);
5796 annotate_constant_pool_refs (&PATTERN (tmp));
5797
5798 target = temp_reg;
5799 }
5800 else
5801 {
5802 new_literal = 1;
5803 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5804 UNSPEC_LTREL_OFFSET);
5805 target = gen_rtx_CONST (Pmode, target);
5806 target = force_const_mem (Pmode, target);
5807 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5808 INSN_ADDRESSES_NEW (tmp, -1);
5809 annotate_constant_pool_refs (&PATTERN (tmp));
5810
5811 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5812 cfun->machine->base_reg),
5813 UNSPEC_LTREL_BASE);
5814 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5815 }
5816
5817 ret = validate_change (insn, label, target, 0);
5818 gcc_assert (ret);
5819 }
5820
5821 return new_literal;
5822 }
5823
5824
5825 /* Find an annotated literal pool symbol referenced in RTX X,
5826 and store it at REF. Will abort if X contains references to
5827 more than one such pool symbol; multiple references to the same
5828 symbol are allowed, however.
5829
5830 The rtx pointed to by REF must be initialized to NULL_RTX
5831 by the caller before calling this routine. */
5832
5833 static void
5834 find_constant_pool_ref (rtx x, rtx *ref)
5835 {
5836 int i, j;
5837 const char *fmt;
5838
5839 /* Ignore LTREL_BASE references. */
5840 if (GET_CODE (x) == UNSPEC
5841 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5842 return;
5843 /* Likewise POOL_ENTRY insns. */
5844 if (GET_CODE (x) == UNSPEC_VOLATILE
5845 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5846 return;
5847
5848 gcc_assert (GET_CODE (x) != SYMBOL_REF
5849 || !CONSTANT_POOL_ADDRESS_P (x));
5850
5851 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5852 {
5853 rtx sym = XVECEXP (x, 0, 0);
5854 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5855 && CONSTANT_POOL_ADDRESS_P (sym));
5856
5857 if (*ref == NULL_RTX)
5858 *ref = sym;
5859 else
5860 gcc_assert (*ref == sym);
5861
5862 return;
5863 }
5864
5865 fmt = GET_RTX_FORMAT (GET_CODE (x));
5866 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5867 {
5868 if (fmt[i] == 'e')
5869 {
5870 find_constant_pool_ref (XEXP (x, i), ref);
5871 }
5872 else if (fmt[i] == 'E')
5873 {
5874 for (j = 0; j < XVECLEN (x, i); j++)
5875 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5876 }
5877 }
5878 }
5879
5880 /* Replace every reference to the annotated literal pool
5881 symbol REF in X by its base plus OFFSET. */
5882
5883 static void
5884 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5885 {
5886 int i, j;
5887 const char *fmt;
5888
5889 gcc_assert (*x != ref);
5890
5891 if (GET_CODE (*x) == UNSPEC
5892 && XINT (*x, 1) == UNSPEC_LTREF
5893 && XVECEXP (*x, 0, 0) == ref)
5894 {
5895 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5896 return;
5897 }
5898
5899 if (GET_CODE (*x) == PLUS
5900 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5901 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5902 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5903 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5904 {
5905 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5906 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5907 return;
5908 }
5909
5910 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5911 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5912 {
5913 if (fmt[i] == 'e')
5914 {
5915 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5916 }
5917 else if (fmt[i] == 'E')
5918 {
5919 for (j = 0; j < XVECLEN (*x, i); j++)
5920 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5921 }
5922 }
5923 }
5924
5925 /* Check whether X contains an UNSPEC_LTREL_BASE.
5926 Return its constant pool symbol if found, NULL_RTX otherwise. */
5927
5928 static rtx
5929 find_ltrel_base (rtx x)
5930 {
5931 int i, j;
5932 const char *fmt;
5933
5934 if (GET_CODE (x) == UNSPEC
5935 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5936 return XVECEXP (x, 0, 0);
5937
5938 fmt = GET_RTX_FORMAT (GET_CODE (x));
5939 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5940 {
5941 if (fmt[i] == 'e')
5942 {
5943 rtx fnd = find_ltrel_base (XEXP (x, i));
5944 if (fnd)
5945 return fnd;
5946 }
5947 else if (fmt[i] == 'E')
5948 {
5949 for (j = 0; j < XVECLEN (x, i); j++)
5950 {
5951 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5952 if (fnd)
5953 return fnd;
5954 }
5955 }
5956 }
5957
5958 return NULL_RTX;
5959 }
5960
5961 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5962
5963 static void
5964 replace_ltrel_base (rtx *x)
5965 {
5966 int i, j;
5967 const char *fmt;
5968
5969 if (GET_CODE (*x) == UNSPEC
5970 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5971 {
5972 *x = XVECEXP (*x, 0, 1);
5973 return;
5974 }
5975
5976 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5977 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5978 {
5979 if (fmt[i] == 'e')
5980 {
5981 replace_ltrel_base (&XEXP (*x, i));
5982 }
5983 else if (fmt[i] == 'E')
5984 {
5985 for (j = 0; j < XVECLEN (*x, i); j++)
5986 replace_ltrel_base (&XVECEXP (*x, i, j));
5987 }
5988 }
5989 }
5990
5991
5992 /* We keep a list of constants which we have to add to internal
5993 constant tables in the middle of large functions. */
5994
5995 #define NR_C_MODES 11
5996 enum machine_mode constant_modes[NR_C_MODES] =
5997 {
5998 TFmode, TImode, TDmode,
5999 DFmode, DImode, DDmode,
6000 SFmode, SImode, SDmode,
6001 HImode,
6002 QImode
6003 };
6004
6005 struct constant
6006 {
6007 struct constant *next;
6008 rtx value;
6009 rtx label;
6010 };
6011
6012 struct constant_pool
6013 {
6014 struct constant_pool *next;
6015 rtx first_insn;
6016 rtx pool_insn;
6017 bitmap insns;
6018 rtx emit_pool_after;
6019
6020 struct constant *constants[NR_C_MODES];
6021 struct constant *execute;
6022 rtx label;
6023 int size;
6024 };
6025
6026 /* Allocate new constant_pool structure. */
6027
6028 static struct constant_pool *
6029 s390_alloc_pool (void)
6030 {
6031 struct constant_pool *pool;
6032 int i;
6033
6034 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6035 pool->next = NULL;
6036 for (i = 0; i < NR_C_MODES; i++)
6037 pool->constants[i] = NULL;
6038
6039 pool->execute = NULL;
6040 pool->label = gen_label_rtx ();
6041 pool->first_insn = NULL_RTX;
6042 pool->pool_insn = NULL_RTX;
6043 pool->insns = BITMAP_ALLOC (NULL);
6044 pool->size = 0;
6045 pool->emit_pool_after = NULL_RTX;
6046
6047 return pool;
6048 }
6049
6050 /* Create new constant pool covering instructions starting at INSN
6051 and chain it to the end of POOL_LIST. */
6052
6053 static struct constant_pool *
6054 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6055 {
6056 struct constant_pool *pool, **prev;
6057
6058 pool = s390_alloc_pool ();
6059 pool->first_insn = insn;
6060
6061 for (prev = pool_list; *prev; prev = &(*prev)->next)
6062 ;
6063 *prev = pool;
6064
6065 return pool;
6066 }
6067
6068 /* End range of instructions covered by POOL at INSN and emit
6069 placeholder insn representing the pool. */
6070
6071 static void
6072 s390_end_pool (struct constant_pool *pool, rtx insn)
6073 {
6074 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6075
6076 if (!insn)
6077 insn = get_last_insn ();
6078
6079 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6080 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6081 }
6082
6083 /* Add INSN to the list of insns covered by POOL. */
6084
6085 static void
6086 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6087 {
6088 bitmap_set_bit (pool->insns, INSN_UID (insn));
6089 }
6090
6091 /* Return pool out of POOL_LIST that covers INSN. */
6092
6093 static struct constant_pool *
6094 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6095 {
6096 struct constant_pool *pool;
6097
6098 for (pool = pool_list; pool; pool = pool->next)
6099 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6100 break;
6101
6102 return pool;
6103 }
6104
6105 /* Add constant VAL of mode MODE to the constant pool POOL. */
6106
6107 static void
6108 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6109 {
6110 struct constant *c;
6111 int i;
6112
6113 for (i = 0; i < NR_C_MODES; i++)
6114 if (constant_modes[i] == mode)
6115 break;
6116 gcc_assert (i != NR_C_MODES);
6117
6118 for (c = pool->constants[i]; c != NULL; c = c->next)
6119 if (rtx_equal_p (val, c->value))
6120 break;
6121
6122 if (c == NULL)
6123 {
6124 c = (struct constant *) xmalloc (sizeof *c);
6125 c->value = val;
6126 c->label = gen_label_rtx ();
6127 c->next = pool->constants[i];
6128 pool->constants[i] = c;
6129 pool->size += GET_MODE_SIZE (mode);
6130 }
6131 }
6132
6133 /* Return an rtx that represents the offset of X from the start of
6134 pool POOL. */
6135
6136 static rtx
6137 s390_pool_offset (struct constant_pool *pool, rtx x)
6138 {
6139 rtx label;
6140
6141 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6142 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6143 UNSPEC_POOL_OFFSET);
6144 return gen_rtx_CONST (GET_MODE (x), x);
6145 }
6146
6147 /* Find constant VAL of mode MODE in the constant pool POOL.
6148 Return an RTX describing the distance from the start of
6149 the pool to the location of the new constant. */
6150
6151 static rtx
6152 s390_find_constant (struct constant_pool *pool, rtx val,
6153 enum machine_mode mode)
6154 {
6155 struct constant *c;
6156 int i;
6157
6158 for (i = 0; i < NR_C_MODES; i++)
6159 if (constant_modes[i] == mode)
6160 break;
6161 gcc_assert (i != NR_C_MODES);
6162
6163 for (c = pool->constants[i]; c != NULL; c = c->next)
6164 if (rtx_equal_p (val, c->value))
6165 break;
6166
6167 gcc_assert (c);
6168
6169 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6170 }
6171
6172 /* Check whether INSN is an execute. Return the label_ref to its
6173 execute target template if so, NULL_RTX otherwise. */
6174
6175 static rtx
6176 s390_execute_label (rtx insn)
6177 {
6178 if (GET_CODE (insn) == INSN
6179 && GET_CODE (PATTERN (insn)) == PARALLEL
6180 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6181 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6182 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6183
6184 return NULL_RTX;
6185 }
6186
6187 /* Add execute target for INSN to the constant pool POOL. */
6188
6189 static void
6190 s390_add_execute (struct constant_pool *pool, rtx insn)
6191 {
6192 struct constant *c;
6193
6194 for (c = pool->execute; c != NULL; c = c->next)
6195 if (INSN_UID (insn) == INSN_UID (c->value))
6196 break;
6197
6198 if (c == NULL)
6199 {
6200 c = (struct constant *) xmalloc (sizeof *c);
6201 c->value = insn;
6202 c->label = gen_label_rtx ();
6203 c->next = pool->execute;
6204 pool->execute = c;
6205 pool->size += 6;
6206 }
6207 }
6208
6209 /* Find execute target for INSN in the constant pool POOL.
6210 Return an RTX describing the distance from the start of
6211 the pool to the location of the execute target. */
6212
6213 static rtx
6214 s390_find_execute (struct constant_pool *pool, rtx insn)
6215 {
6216 struct constant *c;
6217
6218 for (c = pool->execute; c != NULL; c = c->next)
6219 if (INSN_UID (insn) == INSN_UID (c->value))
6220 break;
6221
6222 gcc_assert (c);
6223
6224 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6225 }
6226
6227 /* For an execute INSN, extract the execute target template. */
6228
6229 static rtx
6230 s390_execute_target (rtx insn)
6231 {
6232 rtx pattern = PATTERN (insn);
6233 gcc_assert (s390_execute_label (insn));
6234
6235 if (XVECLEN (pattern, 0) == 2)
6236 {
6237 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6238 }
6239 else
6240 {
6241 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6242 int i;
6243
6244 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6245 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6246
6247 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6248 }
6249
6250 return pattern;
6251 }
6252
6253 /* Indicate that INSN cannot be duplicated. This is the case for
6254 execute insns that carry a unique label. */
6255
6256 static bool
6257 s390_cannot_copy_insn_p (rtx insn)
6258 {
6259 rtx label = s390_execute_label (insn);
6260 return label && label != const0_rtx;
6261 }
6262
6263 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6264 do not emit the pool base label. */
6265
6266 static void
6267 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6268 {
6269 struct constant *c;
6270 rtx insn = pool->pool_insn;
6271 int i;
6272
6273 /* Switch to rodata section. */
6274 if (TARGET_CPU_ZARCH)
6275 {
6276 insn = emit_insn_after (gen_pool_section_start (), insn);
6277 INSN_ADDRESSES_NEW (insn, -1);
6278 }
6279
6280 /* Ensure minimum pool alignment. */
6281 if (TARGET_CPU_ZARCH)
6282 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6283 else
6284 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6285 INSN_ADDRESSES_NEW (insn, -1);
6286
6287 /* Emit pool base label. */
6288 if (!remote_label)
6289 {
6290 insn = emit_label_after (pool->label, insn);
6291 INSN_ADDRESSES_NEW (insn, -1);
6292 }
6293
6294 /* Dump constants in descending alignment requirement order,
6295 ensuring proper alignment for every constant. */
6296 for (i = 0; i < NR_C_MODES; i++)
6297 for (c = pool->constants[i]; c; c = c->next)
6298 {
6299 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6300 rtx value = copy_rtx (c->value);
6301 if (GET_CODE (value) == CONST
6302 && GET_CODE (XEXP (value, 0)) == UNSPEC
6303 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6304 && XVECLEN (XEXP (value, 0), 0) == 1)
6305 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6306
6307 insn = emit_label_after (c->label, insn);
6308 INSN_ADDRESSES_NEW (insn, -1);
6309
6310 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6311 gen_rtvec (1, value),
6312 UNSPECV_POOL_ENTRY);
6313 insn = emit_insn_after (value, insn);
6314 INSN_ADDRESSES_NEW (insn, -1);
6315 }
6316
6317 /* Ensure minimum alignment for instructions. */
6318 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6319 INSN_ADDRESSES_NEW (insn, -1);
6320
6321 /* Output in-pool execute template insns. */
6322 for (c = pool->execute; c; c = c->next)
6323 {
6324 insn = emit_label_after (c->label, insn);
6325 INSN_ADDRESSES_NEW (insn, -1);
6326
6327 insn = emit_insn_after (s390_execute_target (c->value), insn);
6328 INSN_ADDRESSES_NEW (insn, -1);
6329 }
6330
6331 /* Switch back to previous section. */
6332 if (TARGET_CPU_ZARCH)
6333 {
6334 insn = emit_insn_after (gen_pool_section_end (), insn);
6335 INSN_ADDRESSES_NEW (insn, -1);
6336 }
6337
6338 insn = emit_barrier_after (insn);
6339 INSN_ADDRESSES_NEW (insn, -1);
6340
6341 /* Remove placeholder insn. */
6342 remove_insn (pool->pool_insn);
6343 }
6344
6345 /* Free all memory used by POOL. */
6346
6347 static void
6348 s390_free_pool (struct constant_pool *pool)
6349 {
6350 struct constant *c, *next;
6351 int i;
6352
6353 for (i = 0; i < NR_C_MODES; i++)
6354 for (c = pool->constants[i]; c; c = next)
6355 {
6356 next = c->next;
6357 free (c);
6358 }
6359
6360 for (c = pool->execute; c; c = next)
6361 {
6362 next = c->next;
6363 free (c);
6364 }
6365
6366 BITMAP_FREE (pool->insns);
6367 free (pool);
6368 }
6369
6370
6371 /* Collect main literal pool. Return NULL on overflow. */
6372
6373 static struct constant_pool *
6374 s390_mainpool_start (void)
6375 {
6376 struct constant_pool *pool;
6377 rtx insn;
6378
6379 pool = s390_alloc_pool ();
6380
6381 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6382 {
6383 if (GET_CODE (insn) == INSN
6384 && GET_CODE (PATTERN (insn)) == SET
6385 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6386 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6387 {
6388 gcc_assert (!pool->pool_insn);
6389 pool->pool_insn = insn;
6390 }
6391
6392 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6393 {
6394 s390_add_execute (pool, insn);
6395 }
6396 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6397 {
6398 rtx pool_ref = NULL_RTX;
6399 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6400 if (pool_ref)
6401 {
6402 rtx constant = get_pool_constant (pool_ref);
6403 enum machine_mode mode = get_pool_mode (pool_ref);
6404 s390_add_constant (pool, constant, mode);
6405 }
6406 }
6407
6408 /* If hot/cold partitioning is enabled we have to make sure that
6409 the literal pool is emitted in the same section where the
6410 initialization of the literal pool base pointer takes place.
6411 emit_pool_after is only used in the non-overflow case on non
6412 Z cpus where we can emit the literal pool at the end of the
6413 function body within the text section. */
6414 if (NOTE_P (insn)
6415 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6416 && !pool->emit_pool_after)
6417 pool->emit_pool_after = PREV_INSN (insn);
6418 }
6419
6420 gcc_assert (pool->pool_insn || pool->size == 0);
6421
6422 if (pool->size >= 4096)
6423 {
6424 /* We're going to chunkify the pool, so remove the main
6425 pool placeholder insn. */
6426 remove_insn (pool->pool_insn);
6427
6428 s390_free_pool (pool);
6429 pool = NULL;
6430 }
6431
6432 /* If the functions ends with the section where the literal pool
6433 should be emitted set the marker to its end. */
6434 if (pool && !pool->emit_pool_after)
6435 pool->emit_pool_after = get_last_insn ();
6436
6437 return pool;
6438 }
6439
6440 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6441 Modify the current function to output the pool constants as well as
6442 the pool register setup instruction. */
6443
6444 static void
6445 s390_mainpool_finish (struct constant_pool *pool)
6446 {
6447 rtx base_reg = cfun->machine->base_reg;
6448 rtx insn;
6449
6450 /* If the pool is empty, we're done. */
6451 if (pool->size == 0)
6452 {
6453 /* We don't actually need a base register after all. */
6454 cfun->machine->base_reg = NULL_RTX;
6455
6456 if (pool->pool_insn)
6457 remove_insn (pool->pool_insn);
6458 s390_free_pool (pool);
6459 return;
6460 }
6461
6462 /* We need correct insn addresses. */
6463 shorten_branches (get_insns ());
6464
6465 /* On zSeries, we use a LARL to load the pool register. The pool is
6466 located in the .rodata section, so we emit it after the function. */
6467 if (TARGET_CPU_ZARCH)
6468 {
6469 insn = gen_main_base_64 (base_reg, pool->label);
6470 insn = emit_insn_after (insn, pool->pool_insn);
6471 INSN_ADDRESSES_NEW (insn, -1);
6472 remove_insn (pool->pool_insn);
6473
6474 insn = get_last_insn ();
6475 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6476 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6477
6478 s390_dump_pool (pool, 0);
6479 }
6480
6481 /* On S/390, if the total size of the function's code plus literal pool
6482 does not exceed 4096 bytes, we use BASR to set up a function base
6483 pointer, and emit the literal pool at the end of the function. */
6484 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6485 + pool->size + 8 /* alignment slop */ < 4096)
6486 {
6487 insn = gen_main_base_31_small (base_reg, pool->label);
6488 insn = emit_insn_after (insn, pool->pool_insn);
6489 INSN_ADDRESSES_NEW (insn, -1);
6490 remove_insn (pool->pool_insn);
6491
6492 insn = emit_label_after (pool->label, insn);
6493 INSN_ADDRESSES_NEW (insn, -1);
6494
6495 /* emit_pool_after will be set by s390_mainpool_start to the
6496 last insn of the section where the literal pool should be
6497 emitted. */
6498 insn = pool->emit_pool_after;
6499
6500 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6501 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6502
6503 s390_dump_pool (pool, 1);
6504 }
6505
6506 /* Otherwise, we emit an inline literal pool and use BASR to branch
6507 over it, setting up the pool register at the same time. */
6508 else
6509 {
6510 rtx pool_end = gen_label_rtx ();
6511
6512 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6513 insn = emit_insn_after (insn, pool->pool_insn);
6514 INSN_ADDRESSES_NEW (insn, -1);
6515 remove_insn (pool->pool_insn);
6516
6517 insn = emit_label_after (pool->label, insn);
6518 INSN_ADDRESSES_NEW (insn, -1);
6519
6520 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6521 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6522
6523 insn = emit_label_after (pool_end, pool->pool_insn);
6524 INSN_ADDRESSES_NEW (insn, -1);
6525
6526 s390_dump_pool (pool, 1);
6527 }
6528
6529
6530 /* Replace all literal pool references. */
6531
6532 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6533 {
6534 if (INSN_P (insn))
6535 replace_ltrel_base (&PATTERN (insn));
6536
6537 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6538 {
6539 rtx addr, pool_ref = NULL_RTX;
6540 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6541 if (pool_ref)
6542 {
6543 if (s390_execute_label (insn))
6544 addr = s390_find_execute (pool, insn);
6545 else
6546 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6547 get_pool_mode (pool_ref));
6548
6549 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6550 INSN_CODE (insn) = -1;
6551 }
6552 }
6553 }
6554
6555
6556 /* Free the pool. */
6557 s390_free_pool (pool);
6558 }
6559
6560 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6561 We have decided we cannot use this pool, so revert all changes
6562 to the current function that were done by s390_mainpool_start. */
6563 static void
6564 s390_mainpool_cancel (struct constant_pool *pool)
6565 {
6566 /* We didn't actually change the instruction stream, so simply
6567 free the pool memory. */
6568 s390_free_pool (pool);
6569 }
6570
6571
6572 /* Chunkify the literal pool. */
6573
6574 #define S390_POOL_CHUNK_MIN 0xc00
6575 #define S390_POOL_CHUNK_MAX 0xe00
6576
6577 static struct constant_pool *
6578 s390_chunkify_start (void)
6579 {
6580 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6581 int extra_size = 0;
6582 bitmap far_labels;
6583 rtx pending_ltrel = NULL_RTX;
6584 rtx insn;
6585
6586 rtx (*gen_reload_base) (rtx, rtx) =
6587 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6588
6589
6590 /* We need correct insn addresses. */
6591
6592 shorten_branches (get_insns ());
6593
6594 /* Scan all insns and move literals to pool chunks. */
6595
6596 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6597 {
6598 bool section_switch_p = false;
6599
6600 /* Check for pending LTREL_BASE. */
6601 if (INSN_P (insn))
6602 {
6603 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6604 if (ltrel_base)
6605 {
6606 gcc_assert (ltrel_base == pending_ltrel);
6607 pending_ltrel = NULL_RTX;
6608 }
6609 }
6610
6611 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6612 {
6613 if (!curr_pool)
6614 curr_pool = s390_start_pool (&pool_list, insn);
6615
6616 s390_add_execute (curr_pool, insn);
6617 s390_add_pool_insn (curr_pool, insn);
6618 }
6619 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6620 {
6621 rtx pool_ref = NULL_RTX;
6622 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6623 if (pool_ref)
6624 {
6625 rtx constant = get_pool_constant (pool_ref);
6626 enum machine_mode mode = get_pool_mode (pool_ref);
6627
6628 if (!curr_pool)
6629 curr_pool = s390_start_pool (&pool_list, insn);
6630
6631 s390_add_constant (curr_pool, constant, mode);
6632 s390_add_pool_insn (curr_pool, insn);
6633
6634 /* Don't split the pool chunk between a LTREL_OFFSET load
6635 and the corresponding LTREL_BASE. */
6636 if (GET_CODE (constant) == CONST
6637 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6638 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6639 {
6640 gcc_assert (!pending_ltrel);
6641 pending_ltrel = pool_ref;
6642 }
6643 }
6644 }
6645
6646 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6647 {
6648 if (curr_pool)
6649 s390_add_pool_insn (curr_pool, insn);
6650 /* An LTREL_BASE must follow within the same basic block. */
6651 gcc_assert (!pending_ltrel);
6652 }
6653
6654 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6655 section_switch_p = true;
6656
6657 if (!curr_pool
6658 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6659 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6660 continue;
6661
6662 if (TARGET_CPU_ZARCH)
6663 {
6664 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6665 continue;
6666
6667 s390_end_pool (curr_pool, NULL_RTX);
6668 curr_pool = NULL;
6669 }
6670 else
6671 {
6672 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6673 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6674 + extra_size;
6675
6676 /* We will later have to insert base register reload insns.
6677 Those will have an effect on code size, which we need to
6678 consider here. This calculation makes rather pessimistic
6679 worst-case assumptions. */
6680 if (GET_CODE (insn) == CODE_LABEL)
6681 extra_size += 6;
6682
6683 if (chunk_size < S390_POOL_CHUNK_MIN
6684 && curr_pool->size < S390_POOL_CHUNK_MIN
6685 && !section_switch_p)
6686 continue;
6687
6688 /* Pool chunks can only be inserted after BARRIERs ... */
6689 if (GET_CODE (insn) == BARRIER)
6690 {
6691 s390_end_pool (curr_pool, insn);
6692 curr_pool = NULL;
6693 extra_size = 0;
6694 }
6695
6696 /* ... so if we don't find one in time, create one. */
6697 else if (chunk_size > S390_POOL_CHUNK_MAX
6698 || curr_pool->size > S390_POOL_CHUNK_MAX
6699 || section_switch_p)
6700 {
6701 rtx label, jump, barrier;
6702
6703 if (!section_switch_p)
6704 {
6705 /* We can insert the barrier only after a 'real' insn. */
6706 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6707 continue;
6708 if (get_attr_length (insn) == 0)
6709 continue;
6710 /* Don't separate LTREL_BASE from the corresponding
6711 LTREL_OFFSET load. */
6712 if (pending_ltrel)
6713 continue;
6714 }
6715 else
6716 {
6717 gcc_assert (!pending_ltrel);
6718
6719 /* The old pool has to end before the section switch
6720 note in order to make it part of the current
6721 section. */
6722 insn = PREV_INSN (insn);
6723 }
6724
6725 label = gen_label_rtx ();
6726 jump = emit_jump_insn_after (gen_jump (label), insn);
6727 barrier = emit_barrier_after (jump);
6728 insn = emit_label_after (label, barrier);
6729 JUMP_LABEL (jump) = label;
6730 LABEL_NUSES (label) = 1;
6731
6732 INSN_ADDRESSES_NEW (jump, -1);
6733 INSN_ADDRESSES_NEW (barrier, -1);
6734 INSN_ADDRESSES_NEW (insn, -1);
6735
6736 s390_end_pool (curr_pool, barrier);
6737 curr_pool = NULL;
6738 extra_size = 0;
6739 }
6740 }
6741 }
6742
6743 if (curr_pool)
6744 s390_end_pool (curr_pool, NULL_RTX);
6745 gcc_assert (!pending_ltrel);
6746
6747 /* Find all labels that are branched into
6748 from an insn belonging to a different chunk. */
6749
6750 far_labels = BITMAP_ALLOC (NULL);
6751
6752 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6753 {
6754 /* Labels marked with LABEL_PRESERVE_P can be target
6755 of non-local jumps, so we have to mark them.
6756 The same holds for named labels.
6757
6758 Don't do that, however, if it is the label before
6759 a jump table. */
6760
6761 if (GET_CODE (insn) == CODE_LABEL
6762 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6763 {
6764 rtx vec_insn = next_real_insn (insn);
6765 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6766 PATTERN (vec_insn) : NULL_RTX;
6767 if (!vec_pat
6768 || !(GET_CODE (vec_pat) == ADDR_VEC
6769 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6770 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6771 }
6772
6773 /* If we have a direct jump (conditional or unconditional)
6774 or a casesi jump, check all potential targets. */
6775 else if (GET_CODE (insn) == JUMP_INSN)
6776 {
6777 rtx pat = PATTERN (insn);
6778 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6779 pat = XVECEXP (pat, 0, 0);
6780
6781 if (GET_CODE (pat) == SET)
6782 {
6783 rtx label = JUMP_LABEL (insn);
6784 if (label)
6785 {
6786 if (s390_find_pool (pool_list, label)
6787 != s390_find_pool (pool_list, insn))
6788 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6789 }
6790 }
6791 else if (GET_CODE (pat) == PARALLEL
6792 && XVECLEN (pat, 0) == 2
6793 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6794 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6795 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6796 {
6797 /* Find the jump table used by this casesi jump. */
6798 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6799 rtx vec_insn = next_real_insn (vec_label);
6800 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6801 PATTERN (vec_insn) : NULL_RTX;
6802 if (vec_pat
6803 && (GET_CODE (vec_pat) == ADDR_VEC
6804 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6805 {
6806 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6807
6808 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6809 {
6810 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6811
6812 if (s390_find_pool (pool_list, label)
6813 != s390_find_pool (pool_list, insn))
6814 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6815 }
6816 }
6817 }
6818 }
6819 }
6820
6821 /* Insert base register reload insns before every pool. */
6822
6823 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6824 {
6825 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6826 curr_pool->label);
6827 rtx insn = curr_pool->first_insn;
6828 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6829 }
6830
6831 /* Insert base register reload insns at every far label. */
6832
6833 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6834 if (GET_CODE (insn) == CODE_LABEL
6835 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6836 {
6837 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6838 if (pool)
6839 {
6840 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6841 pool->label);
6842 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6843 }
6844 }
6845
6846
6847 BITMAP_FREE (far_labels);
6848
6849
6850 /* Recompute insn addresses. */
6851
6852 init_insn_lengths ();
6853 shorten_branches (get_insns ());
6854
6855 return pool_list;
6856 }
6857
6858 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6859 After we have decided to use this list, finish implementing
6860 all changes to the current function as required. */
6861
6862 static void
6863 s390_chunkify_finish (struct constant_pool *pool_list)
6864 {
6865 struct constant_pool *curr_pool = NULL;
6866 rtx insn;
6867
6868
6869 /* Replace all literal pool references. */
6870
6871 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6872 {
6873 if (INSN_P (insn))
6874 replace_ltrel_base (&PATTERN (insn));
6875
6876 curr_pool = s390_find_pool (pool_list, insn);
6877 if (!curr_pool)
6878 continue;
6879
6880 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6881 {
6882 rtx addr, pool_ref = NULL_RTX;
6883 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6884 if (pool_ref)
6885 {
6886 if (s390_execute_label (insn))
6887 addr = s390_find_execute (curr_pool, insn);
6888 else
6889 addr = s390_find_constant (curr_pool,
6890 get_pool_constant (pool_ref),
6891 get_pool_mode (pool_ref));
6892
6893 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6894 INSN_CODE (insn) = -1;
6895 }
6896 }
6897 }
6898
6899 /* Dump out all literal pools. */
6900
6901 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6902 s390_dump_pool (curr_pool, 0);
6903
6904 /* Free pool list. */
6905
6906 while (pool_list)
6907 {
6908 struct constant_pool *next = pool_list->next;
6909 s390_free_pool (pool_list);
6910 pool_list = next;
6911 }
6912 }
6913
6914 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6915 We have decided we cannot use this list, so revert all changes
6916 to the current function that were done by s390_chunkify_start. */
6917
6918 static void
6919 s390_chunkify_cancel (struct constant_pool *pool_list)
6920 {
6921 struct constant_pool *curr_pool = NULL;
6922 rtx insn;
6923
6924 /* Remove all pool placeholder insns. */
6925
6926 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6927 {
6928 /* Did we insert an extra barrier? Remove it. */
6929 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6930 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6931 rtx label = NEXT_INSN (curr_pool->pool_insn);
6932
6933 if (jump && GET_CODE (jump) == JUMP_INSN
6934 && barrier && GET_CODE (barrier) == BARRIER
6935 && label && GET_CODE (label) == CODE_LABEL
6936 && GET_CODE (PATTERN (jump)) == SET
6937 && SET_DEST (PATTERN (jump)) == pc_rtx
6938 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6939 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6940 {
6941 remove_insn (jump);
6942 remove_insn (barrier);
6943 remove_insn (label);
6944 }
6945
6946 remove_insn (curr_pool->pool_insn);
6947 }
6948
6949 /* Remove all base register reload insns. */
6950
6951 for (insn = get_insns (); insn; )
6952 {
6953 rtx next_insn = NEXT_INSN (insn);
6954
6955 if (GET_CODE (insn) == INSN
6956 && GET_CODE (PATTERN (insn)) == SET
6957 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6958 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6959 remove_insn (insn);
6960
6961 insn = next_insn;
6962 }
6963
6964 /* Free pool list. */
6965
6966 while (pool_list)
6967 {
6968 struct constant_pool *next = pool_list->next;
6969 s390_free_pool (pool_list);
6970 pool_list = next;
6971 }
6972 }
6973
6974 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6975
6976 void
6977 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6978 {
6979 REAL_VALUE_TYPE r;
6980
6981 switch (GET_MODE_CLASS (mode))
6982 {
6983 case MODE_FLOAT:
6984 case MODE_DECIMAL_FLOAT:
6985 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6986
6987 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6988 assemble_real (r, mode, align);
6989 break;
6990
6991 case MODE_INT:
6992 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6993 mark_symbol_refs_as_used (exp);
6994 break;
6995
6996 default:
6997 gcc_unreachable ();
6998 }
6999 }
7000
7001
7002 /* Return an RTL expression representing the value of the return address
7003 for the frame COUNT steps up from the current frame. FRAME is the
7004 frame pointer of that frame. */
7005
7006 rtx
7007 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7008 {
7009 int offset;
7010 rtx addr;
7011
7012 /* Without backchain, we fail for all but the current frame. */
7013
7014 if (!TARGET_BACKCHAIN && count > 0)
7015 return NULL_RTX;
7016
7017 /* For the current frame, we need to make sure the initial
7018 value of RETURN_REGNUM is actually saved. */
7019
7020 if (count == 0)
7021 {
7022 /* On non-z architectures branch splitting could overwrite r14. */
7023 if (TARGET_CPU_ZARCH)
7024 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7025 else
7026 {
7027 cfun_frame_layout.save_return_addr_p = true;
7028 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7029 }
7030 }
7031
7032 if (TARGET_PACKED_STACK)
7033 offset = -2 * UNITS_PER_LONG;
7034 else
7035 offset = RETURN_REGNUM * UNITS_PER_LONG;
7036
7037 addr = plus_constant (frame, offset);
7038 addr = memory_address (Pmode, addr);
7039 return gen_rtx_MEM (Pmode, addr);
7040 }
7041
7042 /* Return an RTL expression representing the back chain stored in
7043 the current stack frame. */
7044
7045 rtx
7046 s390_back_chain_rtx (void)
7047 {
7048 rtx chain;
7049
7050 gcc_assert (TARGET_BACKCHAIN);
7051
7052 if (TARGET_PACKED_STACK)
7053 chain = plus_constant (stack_pointer_rtx,
7054 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7055 else
7056 chain = stack_pointer_rtx;
7057
7058 chain = gen_rtx_MEM (Pmode, chain);
7059 return chain;
7060 }
7061
7062 /* Find first call clobbered register unused in a function.
7063 This could be used as base register in a leaf function
7064 or for holding the return address before epilogue. */
7065
7066 static int
7067 find_unused_clobbered_reg (void)
7068 {
7069 int i;
7070 for (i = 0; i < 6; i++)
7071 if (!df_regs_ever_live_p (i))
7072 return i;
7073 return 0;
7074 }
7075
7076
7077 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7078 clobbered hard regs in SETREG. */
7079
7080 static void
7081 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7082 {
7083 int *regs_ever_clobbered = (int *)data;
7084 unsigned int i, regno;
7085 enum machine_mode mode = GET_MODE (setreg);
7086
7087 if (GET_CODE (setreg) == SUBREG)
7088 {
7089 rtx inner = SUBREG_REG (setreg);
7090 if (!GENERAL_REG_P (inner))
7091 return;
7092 regno = subreg_regno (setreg);
7093 }
7094 else if (GENERAL_REG_P (setreg))
7095 regno = REGNO (setreg);
7096 else
7097 return;
7098
7099 for (i = regno;
7100 i < regno + HARD_REGNO_NREGS (regno, mode);
7101 i++)
7102 regs_ever_clobbered[i] = 1;
7103 }
7104
7105 /* Walks through all basic blocks of the current function looking
7106 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7107 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7108 each of those regs. */
7109
7110 static void
7111 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7112 {
7113 basic_block cur_bb;
7114 rtx cur_insn;
7115 unsigned int i;
7116
7117 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7118
7119 /* For non-leaf functions we have to consider all call clobbered regs to be
7120 clobbered. */
7121 if (!current_function_is_leaf)
7122 {
7123 for (i = 0; i < 16; i++)
7124 regs_ever_clobbered[i] = call_really_used_regs[i];
7125 }
7126
7127 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7128 this work is done by liveness analysis (mark_regs_live_at_end).
7129 Special care is needed for functions containing landing pads. Landing pads
7130 may use the eh registers, but the code which sets these registers is not
7131 contained in that function. Hence s390_regs_ever_clobbered is not able to
7132 deal with this automatically. */
7133 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7134 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7135 if (crtl->calls_eh_return
7136 || (cfun->machine->has_landing_pad_p
7137 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7138 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7139
7140 /* For nonlocal gotos all call-saved registers have to be saved.
7141 This flag is also set for the unwinding code in libgcc.
7142 See expand_builtin_unwind_init. For regs_ever_live this is done by
7143 reload. */
7144 if (cfun->has_nonlocal_label)
7145 for (i = 0; i < 16; i++)
7146 if (!call_really_used_regs[i])
7147 regs_ever_clobbered[i] = 1;
7148
7149 FOR_EACH_BB (cur_bb)
7150 {
7151 FOR_BB_INSNS (cur_bb, cur_insn)
7152 {
7153 if (INSN_P (cur_insn))
7154 note_stores (PATTERN (cur_insn),
7155 s390_reg_clobbered_rtx,
7156 regs_ever_clobbered);
7157 }
7158 }
7159 }
7160
7161 /* Determine the frame area which actually has to be accessed
7162 in the function epilogue. The values are stored at the
7163 given pointers AREA_BOTTOM (address of the lowest used stack
7164 address) and AREA_TOP (address of the first item which does
7165 not belong to the stack frame). */
7166
7167 static void
7168 s390_frame_area (int *area_bottom, int *area_top)
7169 {
7170 int b, t;
7171 int i;
7172
7173 b = INT_MAX;
7174 t = INT_MIN;
7175
7176 if (cfun_frame_layout.first_restore_gpr != -1)
7177 {
7178 b = (cfun_frame_layout.gprs_offset
7179 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7180 t = b + (cfun_frame_layout.last_restore_gpr
7181 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7182 }
7183
7184 if (TARGET_64BIT && cfun_save_high_fprs_p)
7185 {
7186 b = MIN (b, cfun_frame_layout.f8_offset);
7187 t = MAX (t, (cfun_frame_layout.f8_offset
7188 + cfun_frame_layout.high_fprs * 8));
7189 }
7190
7191 if (!TARGET_64BIT)
7192 for (i = 2; i < 4; i++)
7193 if (cfun_fpr_bit_p (i))
7194 {
7195 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7196 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7197 }
7198
7199 *area_bottom = b;
7200 *area_top = t;
7201 }
7202
7203 /* Fill cfun->machine with info about register usage of current function.
7204 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7205
7206 static void
7207 s390_register_info (int clobbered_regs[])
7208 {
7209 int i, j;
7210
7211 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7212 cfun_frame_layout.fpr_bitmap = 0;
7213 cfun_frame_layout.high_fprs = 0;
7214 if (TARGET_64BIT)
7215 for (i = 24; i < 32; i++)
7216 if (df_regs_ever_live_p (i) && !global_regs[i])
7217 {
7218 cfun_set_fpr_bit (i - 16);
7219 cfun_frame_layout.high_fprs++;
7220 }
7221
7222 /* Find first and last gpr to be saved. We trust regs_ever_live
7223 data, except that we don't save and restore global registers.
7224
7225 Also, all registers with special meaning to the compiler need
7226 to be handled extra. */
7227
7228 s390_regs_ever_clobbered (clobbered_regs);
7229
7230 for (i = 0; i < 16; i++)
7231 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7232
7233 if (frame_pointer_needed)
7234 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7235
7236 if (flag_pic)
7237 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7238 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7239
7240 clobbered_regs[BASE_REGNUM]
7241 |= (cfun->machine->base_reg
7242 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7243
7244 clobbered_regs[RETURN_REGNUM]
7245 |= (!current_function_is_leaf
7246 || TARGET_TPF_PROFILING
7247 || cfun->machine->split_branches_pending_p
7248 || cfun_frame_layout.save_return_addr_p
7249 || crtl->calls_eh_return
7250 || cfun->stdarg);
7251
7252 clobbered_regs[STACK_POINTER_REGNUM]
7253 |= (!current_function_is_leaf
7254 || TARGET_TPF_PROFILING
7255 || cfun_save_high_fprs_p
7256 || get_frame_size () > 0
7257 || cfun->calls_alloca
7258 || cfun->stdarg);
7259
7260 for (i = 6; i < 16; i++)
7261 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7262 break;
7263 for (j = 15; j > i; j--)
7264 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7265 break;
7266
7267 if (i == 16)
7268 {
7269 /* Nothing to save/restore. */
7270 cfun_frame_layout.first_save_gpr_slot = -1;
7271 cfun_frame_layout.last_save_gpr_slot = -1;
7272 cfun_frame_layout.first_save_gpr = -1;
7273 cfun_frame_layout.first_restore_gpr = -1;
7274 cfun_frame_layout.last_save_gpr = -1;
7275 cfun_frame_layout.last_restore_gpr = -1;
7276 }
7277 else
7278 {
7279 /* Save slots for gprs from i to j. */
7280 cfun_frame_layout.first_save_gpr_slot = i;
7281 cfun_frame_layout.last_save_gpr_slot = j;
7282
7283 for (i = cfun_frame_layout.first_save_gpr_slot;
7284 i < cfun_frame_layout.last_save_gpr_slot + 1;
7285 i++)
7286 if (clobbered_regs[i])
7287 break;
7288
7289 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7290 if (clobbered_regs[j])
7291 break;
7292
7293 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7294 {
7295 /* Nothing to save/restore. */
7296 cfun_frame_layout.first_save_gpr = -1;
7297 cfun_frame_layout.first_restore_gpr = -1;
7298 cfun_frame_layout.last_save_gpr = -1;
7299 cfun_frame_layout.last_restore_gpr = -1;
7300 }
7301 else
7302 {
7303 /* Save / Restore from gpr i to j. */
7304 cfun_frame_layout.first_save_gpr = i;
7305 cfun_frame_layout.first_restore_gpr = i;
7306 cfun_frame_layout.last_save_gpr = j;
7307 cfun_frame_layout.last_restore_gpr = j;
7308 }
7309 }
7310
7311 if (cfun->stdarg)
7312 {
7313 /* Varargs functions need to save gprs 2 to 6. */
7314 if (cfun->va_list_gpr_size
7315 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7316 {
7317 int min_gpr = crtl->args.info.gprs;
7318 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7319 if (max_gpr > GP_ARG_NUM_REG)
7320 max_gpr = GP_ARG_NUM_REG;
7321
7322 if (cfun_frame_layout.first_save_gpr == -1
7323 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7324 {
7325 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7326 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7327 }
7328
7329 if (cfun_frame_layout.last_save_gpr == -1
7330 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7331 {
7332 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7333 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7334 }
7335 }
7336
7337 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7338 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7339 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7340 {
7341 int min_fpr = crtl->args.info.fprs;
7342 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7343 if (max_fpr > FP_ARG_NUM_REG)
7344 max_fpr = FP_ARG_NUM_REG;
7345
7346 /* ??? This is currently required to ensure proper location
7347 of the fpr save slots within the va_list save area. */
7348 if (TARGET_PACKED_STACK)
7349 min_fpr = 0;
7350
7351 for (i = min_fpr; i < max_fpr; i++)
7352 cfun_set_fpr_bit (i);
7353 }
7354 }
7355
7356 if (!TARGET_64BIT)
7357 for (i = 2; i < 4; i++)
7358 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7359 cfun_set_fpr_bit (i);
7360 }
7361
7362 /* Fill cfun->machine with info about frame of current function. */
7363
7364 static void
7365 s390_frame_info (void)
7366 {
7367 int i;
7368
7369 cfun_frame_layout.frame_size = get_frame_size ();
7370 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7371 fatal_error ("total size of local variables exceeds architecture limit");
7372
7373 if (!TARGET_PACKED_STACK)
7374 {
7375 cfun_frame_layout.backchain_offset = 0;
7376 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7377 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7378 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7379 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7380 * UNITS_PER_LONG);
7381 }
7382 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7383 {
7384 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7385 - UNITS_PER_LONG);
7386 cfun_frame_layout.gprs_offset
7387 = (cfun_frame_layout.backchain_offset
7388 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7389 * UNITS_PER_LONG);
7390
7391 if (TARGET_64BIT)
7392 {
7393 cfun_frame_layout.f4_offset
7394 = (cfun_frame_layout.gprs_offset
7395 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7396
7397 cfun_frame_layout.f0_offset
7398 = (cfun_frame_layout.f4_offset
7399 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7400 }
7401 else
7402 {
7403 /* On 31 bit we have to care about alignment of the
7404 floating point regs to provide fastest access. */
7405 cfun_frame_layout.f0_offset
7406 = ((cfun_frame_layout.gprs_offset
7407 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7408 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7409
7410 cfun_frame_layout.f4_offset
7411 = (cfun_frame_layout.f0_offset
7412 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7413 }
7414 }
7415 else /* no backchain */
7416 {
7417 cfun_frame_layout.f4_offset
7418 = (STACK_POINTER_OFFSET
7419 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7420
7421 cfun_frame_layout.f0_offset
7422 = (cfun_frame_layout.f4_offset
7423 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7424
7425 cfun_frame_layout.gprs_offset
7426 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7427 }
7428
7429 if (current_function_is_leaf
7430 && !TARGET_TPF_PROFILING
7431 && cfun_frame_layout.frame_size == 0
7432 && !cfun_save_high_fprs_p
7433 && !cfun->calls_alloca
7434 && !cfun->stdarg)
7435 return;
7436
7437 if (!TARGET_PACKED_STACK)
7438 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7439 + crtl->outgoing_args_size
7440 + cfun_frame_layout.high_fprs * 8);
7441 else
7442 {
7443 if (TARGET_BACKCHAIN)
7444 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7445
7446 /* No alignment trouble here because f8-f15 are only saved under
7447 64 bit. */
7448 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7449 cfun_frame_layout.f4_offset),
7450 cfun_frame_layout.gprs_offset)
7451 - cfun_frame_layout.high_fprs * 8);
7452
7453 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7454
7455 for (i = 0; i < 8; i++)
7456 if (cfun_fpr_bit_p (i))
7457 cfun_frame_layout.frame_size += 8;
7458
7459 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7460
7461 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7462 the frame size to sustain 8 byte alignment of stack frames. */
7463 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7464 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7465 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7466
7467 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7468 }
7469 }
7470
7471 /* Generate frame layout. Fills in register and frame data for the current
7472 function in cfun->machine. This routine can be called multiple times;
7473 it will re-do the complete frame layout every time. */
7474
7475 static void
7476 s390_init_frame_layout (void)
7477 {
7478 HOST_WIDE_INT frame_size;
7479 int base_used;
7480 int clobbered_regs[16];
7481
7482 /* On S/390 machines, we may need to perform branch splitting, which
7483 will require both base and return address register. We have no
7484 choice but to assume we're going to need them until right at the
7485 end of the machine dependent reorg phase. */
7486 if (!TARGET_CPU_ZARCH)
7487 cfun->machine->split_branches_pending_p = true;
7488
7489 do
7490 {
7491 frame_size = cfun_frame_layout.frame_size;
7492
7493 /* Try to predict whether we'll need the base register. */
7494 base_used = cfun->machine->split_branches_pending_p
7495 || crtl->uses_const_pool
7496 || (!DISP_IN_RANGE (frame_size)
7497 && !CONST_OK_FOR_K (frame_size));
7498
7499 /* Decide which register to use as literal pool base. In small
7500 leaf functions, try to use an unused call-clobbered register
7501 as base register to avoid save/restore overhead. */
7502 if (!base_used)
7503 cfun->machine->base_reg = NULL_RTX;
7504 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7505 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7506 else
7507 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7508
7509 s390_register_info (clobbered_regs);
7510 s390_frame_info ();
7511 }
7512 while (frame_size != cfun_frame_layout.frame_size);
7513 }
7514
7515 /* Update frame layout. Recompute actual register save data based on
7516 current info and update regs_ever_live for the special registers.
7517 May be called multiple times, but may never cause *more* registers
7518 to be saved than s390_init_frame_layout allocated room for. */
7519
7520 static void
7521 s390_update_frame_layout (void)
7522 {
7523 int clobbered_regs[16];
7524
7525 s390_register_info (clobbered_regs);
7526
7527 df_set_regs_ever_live (BASE_REGNUM,
7528 clobbered_regs[BASE_REGNUM] ? true : false);
7529 df_set_regs_ever_live (RETURN_REGNUM,
7530 clobbered_regs[RETURN_REGNUM] ? true : false);
7531 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7532 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7533
7534 if (cfun->machine->base_reg)
7535 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7536 }
7537
7538 /* Return true if it is legal to put a value with MODE into REGNO. */
7539
7540 bool
7541 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7542 {
7543 switch (REGNO_REG_CLASS (regno))
7544 {
7545 case FP_REGS:
7546 if (REGNO_PAIR_OK (regno, mode))
7547 {
7548 if (mode == SImode || mode == DImode)
7549 return true;
7550
7551 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7552 return true;
7553 }
7554 break;
7555 case ADDR_REGS:
7556 if (FRAME_REGNO_P (regno) && mode == Pmode)
7557 return true;
7558
7559 /* fallthrough */
7560 case GENERAL_REGS:
7561 if (REGNO_PAIR_OK (regno, mode))
7562 {
7563 if (TARGET_ZARCH
7564 || (mode != TFmode && mode != TCmode && mode != TDmode))
7565 return true;
7566 }
7567 break;
7568 case CC_REGS:
7569 if (GET_MODE_CLASS (mode) == MODE_CC)
7570 return true;
7571 break;
7572 case ACCESS_REGS:
7573 if (REGNO_PAIR_OK (regno, mode))
7574 {
7575 if (mode == SImode || mode == Pmode)
7576 return true;
7577 }
7578 break;
7579 default:
7580 return false;
7581 }
7582
7583 return false;
7584 }
7585
7586 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7587
7588 bool
7589 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7590 {
7591 /* Once we've decided upon a register to use as base register, it must
7592 no longer be used for any other purpose. */
7593 if (cfun->machine->base_reg)
7594 if (REGNO (cfun->machine->base_reg) == old_reg
7595 || REGNO (cfun->machine->base_reg) == new_reg)
7596 return false;
7597
7598 return true;
7599 }
7600
7601 /* Maximum number of registers to represent a value of mode MODE
7602 in a register of class RCLASS. */
7603
7604 bool
7605 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7606 {
7607 switch (rclass)
7608 {
7609 case FP_REGS:
7610 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7611 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7612 else
7613 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7614 case ACCESS_REGS:
7615 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7616 default:
7617 break;
7618 }
7619 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7620 }
7621
7622 /* Return true if register FROM can be eliminated via register TO. */
7623
7624 static bool
7625 s390_can_eliminate (const int from, const int to)
7626 {
7627 /* On zSeries machines, we have not marked the base register as fixed.
7628 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7629 If a function requires the base register, we say here that this
7630 elimination cannot be performed. This will cause reload to free
7631 up the base register (as if it were fixed). On the other hand,
7632 if the current function does *not* require the base register, we
7633 say here the elimination succeeds, which in turn allows reload
7634 to allocate the base register for any other purpose. */
7635 if (from == BASE_REGNUM && to == BASE_REGNUM)
7636 {
7637 if (TARGET_CPU_ZARCH)
7638 {
7639 s390_init_frame_layout ();
7640 return cfun->machine->base_reg == NULL_RTX;
7641 }
7642
7643 return false;
7644 }
7645
7646 /* Everything else must point into the stack frame. */
7647 gcc_assert (to == STACK_POINTER_REGNUM
7648 || to == HARD_FRAME_POINTER_REGNUM);
7649
7650 gcc_assert (from == FRAME_POINTER_REGNUM
7651 || from == ARG_POINTER_REGNUM
7652 || from == RETURN_ADDRESS_POINTER_REGNUM);
7653
7654 /* Make sure we actually saved the return address. */
7655 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7656 if (!crtl->calls_eh_return
7657 && !cfun->stdarg
7658 && !cfun_frame_layout.save_return_addr_p)
7659 return false;
7660
7661 return true;
7662 }
7663
7664 /* Return offset between register FROM and TO initially after prolog. */
7665
7666 HOST_WIDE_INT
7667 s390_initial_elimination_offset (int from, int to)
7668 {
7669 HOST_WIDE_INT offset;
7670 int index;
7671
7672 /* ??? Why are we called for non-eliminable pairs? */
7673 if (!s390_can_eliminate (from, to))
7674 return 0;
7675
7676 switch (from)
7677 {
7678 case FRAME_POINTER_REGNUM:
7679 offset = (get_frame_size()
7680 + STACK_POINTER_OFFSET
7681 + crtl->outgoing_args_size);
7682 break;
7683
7684 case ARG_POINTER_REGNUM:
7685 s390_init_frame_layout ();
7686 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7687 break;
7688
7689 case RETURN_ADDRESS_POINTER_REGNUM:
7690 s390_init_frame_layout ();
7691 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7692 gcc_assert (index >= 0);
7693 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7694 offset += index * UNITS_PER_LONG;
7695 break;
7696
7697 case BASE_REGNUM:
7698 offset = 0;
7699 break;
7700
7701 default:
7702 gcc_unreachable ();
7703 }
7704
7705 return offset;
7706 }
7707
7708 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7709 to register BASE. Return generated insn. */
7710
7711 static rtx
7712 save_fpr (rtx base, int offset, int regnum)
7713 {
7714 rtx addr;
7715 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7716
7717 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7718 set_mem_alias_set (addr, get_varargs_alias_set ());
7719 else
7720 set_mem_alias_set (addr, get_frame_alias_set ());
7721
7722 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7723 }
7724
7725 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7726 to register BASE. Return generated insn. */
7727
7728 static rtx
7729 restore_fpr (rtx base, int offset, int regnum)
7730 {
7731 rtx addr;
7732 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7733 set_mem_alias_set (addr, get_frame_alias_set ());
7734
7735 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7736 }
7737
7738 /* Return true if REGNO is a global register, but not one
7739 of the special ones that need to be saved/restored in anyway. */
7740
7741 static inline bool
7742 global_not_special_regno_p (int regno)
7743 {
7744 return (global_regs[regno]
7745 /* These registers are special and need to be
7746 restored in any case. */
7747 && !(regno == STACK_POINTER_REGNUM
7748 || regno == RETURN_REGNUM
7749 || regno == BASE_REGNUM
7750 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7751 }
7752
7753 /* Generate insn to save registers FIRST to LAST into
7754 the register save area located at offset OFFSET
7755 relative to register BASE. */
7756
7757 static rtx
7758 save_gprs (rtx base, int offset, int first, int last)
7759 {
7760 rtx addr, insn, note;
7761 int i;
7762
7763 addr = plus_constant (base, offset);
7764 addr = gen_rtx_MEM (Pmode, addr);
7765
7766 set_mem_alias_set (addr, get_frame_alias_set ());
7767
7768 /* Special-case single register. */
7769 if (first == last)
7770 {
7771 if (TARGET_64BIT)
7772 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7773 else
7774 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7775
7776 if (!global_not_special_regno_p (first))
7777 RTX_FRAME_RELATED_P (insn) = 1;
7778 return insn;
7779 }
7780
7781
7782 insn = gen_store_multiple (addr,
7783 gen_rtx_REG (Pmode, first),
7784 GEN_INT (last - first + 1));
7785
7786 if (first <= 6 && cfun->stdarg)
7787 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7788 {
7789 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7790
7791 if (first + i <= 6)
7792 set_mem_alias_set (mem, get_varargs_alias_set ());
7793 }
7794
7795 /* We need to set the FRAME_RELATED flag on all SETs
7796 inside the store-multiple pattern.
7797
7798 However, we must not emit DWARF records for registers 2..5
7799 if they are stored for use by variable arguments ...
7800
7801 ??? Unfortunately, it is not enough to simply not the
7802 FRAME_RELATED flags for those SETs, because the first SET
7803 of the PARALLEL is always treated as if it had the flag
7804 set, even if it does not. Therefore we emit a new pattern
7805 without those registers as REG_FRAME_RELATED_EXPR note. */
7806
7807 if (first >= 6 && !global_not_special_regno_p (first))
7808 {
7809 rtx pat = PATTERN (insn);
7810
7811 for (i = 0; i < XVECLEN (pat, 0); i++)
7812 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7813 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7814 0, i)))))
7815 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7816
7817 RTX_FRAME_RELATED_P (insn) = 1;
7818 }
7819 else if (last >= 6)
7820 {
7821 int start;
7822
7823 for (start = first >= 6 ? first : 6; start <= last; start++)
7824 if (!global_not_special_regno_p (start))
7825 break;
7826
7827 if (start > last)
7828 return insn;
7829
7830 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7831 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7832 gen_rtx_REG (Pmode, start),
7833 GEN_INT (last - start + 1));
7834 note = PATTERN (note);
7835
7836 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7837
7838 for (i = 0; i < XVECLEN (note, 0); i++)
7839 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7840 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7841 0, i)))))
7842 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7843
7844 RTX_FRAME_RELATED_P (insn) = 1;
7845 }
7846
7847 return insn;
7848 }
7849
7850 /* Generate insn to restore registers FIRST to LAST from
7851 the register save area located at offset OFFSET
7852 relative to register BASE. */
7853
7854 static rtx
7855 restore_gprs (rtx base, int offset, int first, int last)
7856 {
7857 rtx addr, insn;
7858
7859 addr = plus_constant (base, offset);
7860 addr = gen_rtx_MEM (Pmode, addr);
7861 set_mem_alias_set (addr, get_frame_alias_set ());
7862
7863 /* Special-case single register. */
7864 if (first == last)
7865 {
7866 if (TARGET_64BIT)
7867 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7868 else
7869 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7870
7871 return insn;
7872 }
7873
7874 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7875 addr,
7876 GEN_INT (last - first + 1));
7877 return insn;
7878 }
7879
7880 /* Return insn sequence to load the GOT register. */
7881
7882 static GTY(()) rtx got_symbol;
7883 rtx
7884 s390_load_got (void)
7885 {
7886 rtx insns;
7887
7888 if (!got_symbol)
7889 {
7890 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7891 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7892 }
7893
7894 start_sequence ();
7895
7896 if (TARGET_CPU_ZARCH)
7897 {
7898 emit_move_insn (pic_offset_table_rtx, got_symbol);
7899 }
7900 else
7901 {
7902 rtx offset;
7903
7904 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7905 UNSPEC_LTREL_OFFSET);
7906 offset = gen_rtx_CONST (Pmode, offset);
7907 offset = force_const_mem (Pmode, offset);
7908
7909 emit_move_insn (pic_offset_table_rtx, offset);
7910
7911 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7912 UNSPEC_LTREL_BASE);
7913 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7914
7915 emit_move_insn (pic_offset_table_rtx, offset);
7916 }
7917
7918 insns = get_insns ();
7919 end_sequence ();
7920 return insns;
7921 }
7922
7923 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7924 and the change to the stack pointer. */
7925
7926 static void
7927 s390_emit_stack_tie (void)
7928 {
7929 rtx mem = gen_frame_mem (BLKmode,
7930 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7931
7932 emit_insn (gen_stack_tie (mem));
7933 }
7934
7935 /* Expand the prologue into a bunch of separate insns. */
7936
7937 void
7938 s390_emit_prologue (void)
7939 {
7940 rtx insn, addr;
7941 rtx temp_reg;
7942 int i;
7943 int offset;
7944 int next_fpr = 0;
7945
7946 /* Complete frame layout. */
7947
7948 s390_update_frame_layout ();
7949
7950 /* Annotate all constant pool references to let the scheduler know
7951 they implicitly use the base register. */
7952
7953 push_topmost_sequence ();
7954
7955 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7956 if (INSN_P (insn))
7957 {
7958 annotate_constant_pool_refs (&PATTERN (insn));
7959 df_insn_rescan (insn);
7960 }
7961
7962 pop_topmost_sequence ();
7963
7964 /* Choose best register to use for temp use within prologue.
7965 See below for why TPF must use the register 1. */
7966
7967 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7968 && !current_function_is_leaf
7969 && !TARGET_TPF_PROFILING)
7970 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7971 else
7972 temp_reg = gen_rtx_REG (Pmode, 1);
7973
7974 /* Save call saved gprs. */
7975 if (cfun_frame_layout.first_save_gpr != -1)
7976 {
7977 insn = save_gprs (stack_pointer_rtx,
7978 cfun_frame_layout.gprs_offset +
7979 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7980 - cfun_frame_layout.first_save_gpr_slot),
7981 cfun_frame_layout.first_save_gpr,
7982 cfun_frame_layout.last_save_gpr);
7983 emit_insn (insn);
7984 }
7985
7986 /* Dummy insn to mark literal pool slot. */
7987
7988 if (cfun->machine->base_reg)
7989 emit_insn (gen_main_pool (cfun->machine->base_reg));
7990
7991 offset = cfun_frame_layout.f0_offset;
7992
7993 /* Save f0 and f2. */
7994 for (i = 0; i < 2; i++)
7995 {
7996 if (cfun_fpr_bit_p (i))
7997 {
7998 save_fpr (stack_pointer_rtx, offset, i + 16);
7999 offset += 8;
8000 }
8001 else if (!TARGET_PACKED_STACK)
8002 offset += 8;
8003 }
8004
8005 /* Save f4 and f6. */
8006 offset = cfun_frame_layout.f4_offset;
8007 for (i = 2; i < 4; i++)
8008 {
8009 if (cfun_fpr_bit_p (i))
8010 {
8011 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8012 offset += 8;
8013
8014 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8015 therefore are not frame related. */
8016 if (!call_really_used_regs[i + 16])
8017 RTX_FRAME_RELATED_P (insn) = 1;
8018 }
8019 else if (!TARGET_PACKED_STACK)
8020 offset += 8;
8021 }
8022
8023 if (TARGET_PACKED_STACK
8024 && cfun_save_high_fprs_p
8025 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8026 {
8027 offset = (cfun_frame_layout.f8_offset
8028 + (cfun_frame_layout.high_fprs - 1) * 8);
8029
8030 for (i = 15; i > 7 && offset >= 0; i--)
8031 if (cfun_fpr_bit_p (i))
8032 {
8033 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8034
8035 RTX_FRAME_RELATED_P (insn) = 1;
8036 offset -= 8;
8037 }
8038 if (offset >= cfun_frame_layout.f8_offset)
8039 next_fpr = i + 16;
8040 }
8041
8042 if (!TARGET_PACKED_STACK)
8043 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8044
8045 if (flag_stack_usage)
8046 current_function_static_stack_size = cfun_frame_layout.frame_size;
8047
8048 /* Decrement stack pointer. */
8049
8050 if (cfun_frame_layout.frame_size > 0)
8051 {
8052 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8053 rtx real_frame_off;
8054
8055 if (s390_stack_size)
8056 {
8057 HOST_WIDE_INT stack_guard;
8058
8059 if (s390_stack_guard)
8060 stack_guard = s390_stack_guard;
8061 else
8062 {
8063 /* If no value for stack guard is provided the smallest power of 2
8064 larger than the current frame size is chosen. */
8065 stack_guard = 1;
8066 while (stack_guard < cfun_frame_layout.frame_size)
8067 stack_guard <<= 1;
8068 }
8069
8070 if (cfun_frame_layout.frame_size >= s390_stack_size)
8071 {
8072 warning (0, "frame size of function %qs is "
8073 HOST_WIDE_INT_PRINT_DEC
8074 " bytes exceeding user provided stack limit of "
8075 HOST_WIDE_INT_PRINT_DEC " bytes. "
8076 "An unconditional trap is added.",
8077 current_function_name(), cfun_frame_layout.frame_size,
8078 s390_stack_size);
8079 emit_insn (gen_trap ());
8080 }
8081 else
8082 {
8083 /* stack_guard has to be smaller than s390_stack_size.
8084 Otherwise we would emit an AND with zero which would
8085 not match the test under mask pattern. */
8086 if (stack_guard >= s390_stack_size)
8087 {
8088 warning (0, "frame size of function %qs is "
8089 HOST_WIDE_INT_PRINT_DEC
8090 " bytes which is more than half the stack size. "
8091 "The dynamic check would not be reliable. "
8092 "No check emitted for this function.",
8093 current_function_name(),
8094 cfun_frame_layout.frame_size);
8095 }
8096 else
8097 {
8098 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8099 & ~(stack_guard - 1));
8100
8101 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8102 GEN_INT (stack_check_mask));
8103 if (TARGET_64BIT)
8104 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8105 t, const0_rtx),
8106 t, const0_rtx, const0_rtx));
8107 else
8108 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8109 t, const0_rtx),
8110 t, const0_rtx, const0_rtx));
8111 }
8112 }
8113 }
8114
8115 if (s390_warn_framesize > 0
8116 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8117 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
8118 current_function_name (), cfun_frame_layout.frame_size);
8119
8120 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8121 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8122
8123 /* Save incoming stack pointer into temp reg. */
8124 if (TARGET_BACKCHAIN || next_fpr)
8125 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8126
8127 /* Subtract frame size from stack pointer. */
8128
8129 if (DISP_IN_RANGE (INTVAL (frame_off)))
8130 {
8131 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8132 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8133 frame_off));
8134 insn = emit_insn (insn);
8135 }
8136 else
8137 {
8138 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8139 frame_off = force_const_mem (Pmode, frame_off);
8140
8141 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8142 annotate_constant_pool_refs (&PATTERN (insn));
8143 }
8144
8145 RTX_FRAME_RELATED_P (insn) = 1;
8146 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8147 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8148 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8149 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8150 real_frame_off)));
8151
8152 /* Set backchain. */
8153
8154 if (TARGET_BACKCHAIN)
8155 {
8156 if (cfun_frame_layout.backchain_offset)
8157 addr = gen_rtx_MEM (Pmode,
8158 plus_constant (stack_pointer_rtx,
8159 cfun_frame_layout.backchain_offset));
8160 else
8161 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8162 set_mem_alias_set (addr, get_frame_alias_set ());
8163 insn = emit_insn (gen_move_insn (addr, temp_reg));
8164 }
8165
8166 /* If we support non-call exceptions (e.g. for Java),
8167 we need to make sure the backchain pointer is set up
8168 before any possibly trapping memory access. */
8169 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8170 {
8171 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8172 emit_clobber (addr);
8173 }
8174 }
8175
8176 /* Save fprs 8 - 15 (64 bit ABI). */
8177
8178 if (cfun_save_high_fprs_p && next_fpr)
8179 {
8180 /* If the stack might be accessed through a different register
8181 we have to make sure that the stack pointer decrement is not
8182 moved below the use of the stack slots. */
8183 s390_emit_stack_tie ();
8184
8185 insn = emit_insn (gen_add2_insn (temp_reg,
8186 GEN_INT (cfun_frame_layout.f8_offset)));
8187
8188 offset = 0;
8189
8190 for (i = 24; i <= next_fpr; i++)
8191 if (cfun_fpr_bit_p (i - 16))
8192 {
8193 rtx addr = plus_constant (stack_pointer_rtx,
8194 cfun_frame_layout.frame_size
8195 + cfun_frame_layout.f8_offset
8196 + offset);
8197
8198 insn = save_fpr (temp_reg, offset, i);
8199 offset += 8;
8200 RTX_FRAME_RELATED_P (insn) = 1;
8201 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8202 gen_rtx_SET (VOIDmode,
8203 gen_rtx_MEM (DFmode, addr),
8204 gen_rtx_REG (DFmode, i)));
8205 }
8206 }
8207
8208 /* Set frame pointer, if needed. */
8209
8210 if (frame_pointer_needed)
8211 {
8212 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8213 RTX_FRAME_RELATED_P (insn) = 1;
8214 }
8215
8216 /* Set up got pointer, if needed. */
8217
8218 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8219 {
8220 rtx insns = s390_load_got ();
8221
8222 for (insn = insns; insn; insn = NEXT_INSN (insn))
8223 annotate_constant_pool_refs (&PATTERN (insn));
8224
8225 emit_insn (insns);
8226 }
8227
8228 if (TARGET_TPF_PROFILING)
8229 {
8230 /* Generate a BAS instruction to serve as a function
8231 entry intercept to facilitate the use of tracing
8232 algorithms located at the branch target. */
8233 emit_insn (gen_prologue_tpf ());
8234
8235 /* Emit a blockage here so that all code
8236 lies between the profiling mechanisms. */
8237 emit_insn (gen_blockage ());
8238 }
8239 }
8240
8241 /* Expand the epilogue into a bunch of separate insns. */
8242
8243 void
8244 s390_emit_epilogue (bool sibcall)
8245 {
8246 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8247 int area_bottom, area_top, offset = 0;
8248 int next_offset;
8249 rtvec p;
8250 int i;
8251
8252 if (TARGET_TPF_PROFILING)
8253 {
8254
8255 /* Generate a BAS instruction to serve as a function
8256 entry intercept to facilitate the use of tracing
8257 algorithms located at the branch target. */
8258
8259 /* Emit a blockage here so that all code
8260 lies between the profiling mechanisms. */
8261 emit_insn (gen_blockage ());
8262
8263 emit_insn (gen_epilogue_tpf ());
8264 }
8265
8266 /* Check whether to use frame or stack pointer for restore. */
8267
8268 frame_pointer = (frame_pointer_needed
8269 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8270
8271 s390_frame_area (&area_bottom, &area_top);
8272
8273 /* Check whether we can access the register save area.
8274 If not, increment the frame pointer as required. */
8275
8276 if (area_top <= area_bottom)
8277 {
8278 /* Nothing to restore. */
8279 }
8280 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8281 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8282 {
8283 /* Area is in range. */
8284 offset = cfun_frame_layout.frame_size;
8285 }
8286 else
8287 {
8288 rtx insn, frame_off, cfa;
8289
8290 offset = area_bottom < 0 ? -area_bottom : 0;
8291 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8292
8293 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8294 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8295 if (DISP_IN_RANGE (INTVAL (frame_off)))
8296 {
8297 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8298 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8299 insn = emit_insn (insn);
8300 }
8301 else
8302 {
8303 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8304 frame_off = force_const_mem (Pmode, frame_off);
8305
8306 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8307 annotate_constant_pool_refs (&PATTERN (insn));
8308 }
8309 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8310 RTX_FRAME_RELATED_P (insn) = 1;
8311 }
8312
8313 /* Restore call saved fprs. */
8314
8315 if (TARGET_64BIT)
8316 {
8317 if (cfun_save_high_fprs_p)
8318 {
8319 next_offset = cfun_frame_layout.f8_offset;
8320 for (i = 24; i < 32; i++)
8321 {
8322 if (cfun_fpr_bit_p (i - 16))
8323 {
8324 restore_fpr (frame_pointer,
8325 offset + next_offset, i);
8326 cfa_restores
8327 = alloc_reg_note (REG_CFA_RESTORE,
8328 gen_rtx_REG (DFmode, i), cfa_restores);
8329 next_offset += 8;
8330 }
8331 }
8332 }
8333
8334 }
8335 else
8336 {
8337 next_offset = cfun_frame_layout.f4_offset;
8338 for (i = 18; i < 20; i++)
8339 {
8340 if (cfun_fpr_bit_p (i - 16))
8341 {
8342 restore_fpr (frame_pointer,
8343 offset + next_offset, i);
8344 cfa_restores
8345 = alloc_reg_note (REG_CFA_RESTORE,
8346 gen_rtx_REG (DFmode, i), cfa_restores);
8347 next_offset += 8;
8348 }
8349 else if (!TARGET_PACKED_STACK)
8350 next_offset += 8;
8351 }
8352
8353 }
8354
8355 /* Return register. */
8356
8357 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8358
8359 /* Restore call saved gprs. */
8360
8361 if (cfun_frame_layout.first_restore_gpr != -1)
8362 {
8363 rtx insn, addr;
8364 int i;
8365
8366 /* Check for global register and save them
8367 to stack location from where they get restored. */
8368
8369 for (i = cfun_frame_layout.first_restore_gpr;
8370 i <= cfun_frame_layout.last_restore_gpr;
8371 i++)
8372 {
8373 if (global_not_special_regno_p (i))
8374 {
8375 addr = plus_constant (frame_pointer,
8376 offset + cfun_frame_layout.gprs_offset
8377 + (i - cfun_frame_layout.first_save_gpr_slot)
8378 * UNITS_PER_LONG);
8379 addr = gen_rtx_MEM (Pmode, addr);
8380 set_mem_alias_set (addr, get_frame_alias_set ());
8381 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8382 }
8383 else
8384 cfa_restores
8385 = alloc_reg_note (REG_CFA_RESTORE,
8386 gen_rtx_REG (Pmode, i), cfa_restores);
8387 }
8388
8389 if (! sibcall)
8390 {
8391 /* Fetch return address from stack before load multiple,
8392 this will do good for scheduling. */
8393
8394 if (cfun_frame_layout.save_return_addr_p
8395 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8396 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8397 {
8398 int return_regnum = find_unused_clobbered_reg();
8399 if (!return_regnum)
8400 return_regnum = 4;
8401 return_reg = gen_rtx_REG (Pmode, return_regnum);
8402
8403 addr = plus_constant (frame_pointer,
8404 offset + cfun_frame_layout.gprs_offset
8405 + (RETURN_REGNUM
8406 - cfun_frame_layout.first_save_gpr_slot)
8407 * UNITS_PER_LONG);
8408 addr = gen_rtx_MEM (Pmode, addr);
8409 set_mem_alias_set (addr, get_frame_alias_set ());
8410 emit_move_insn (return_reg, addr);
8411 }
8412 }
8413
8414 insn = restore_gprs (frame_pointer,
8415 offset + cfun_frame_layout.gprs_offset
8416 + (cfun_frame_layout.first_restore_gpr
8417 - cfun_frame_layout.first_save_gpr_slot)
8418 * UNITS_PER_LONG,
8419 cfun_frame_layout.first_restore_gpr,
8420 cfun_frame_layout.last_restore_gpr);
8421 insn = emit_insn (insn);
8422 REG_NOTES (insn) = cfa_restores;
8423 add_reg_note (insn, REG_CFA_DEF_CFA,
8424 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8425 RTX_FRAME_RELATED_P (insn) = 1;
8426 }
8427
8428 if (! sibcall)
8429 {
8430
8431 /* Return to caller. */
8432
8433 p = rtvec_alloc (2);
8434
8435 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8436 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8437 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8438 }
8439 }
8440
8441
8442 /* Return the size in bytes of a function argument of
8443 type TYPE and/or mode MODE. At least one of TYPE or
8444 MODE must be specified. */
8445
8446 static int
8447 s390_function_arg_size (enum machine_mode mode, const_tree type)
8448 {
8449 if (type)
8450 return int_size_in_bytes (type);
8451
8452 /* No type info available for some library calls ... */
8453 if (mode != BLKmode)
8454 return GET_MODE_SIZE (mode);
8455
8456 /* If we have neither type nor mode, abort */
8457 gcc_unreachable ();
8458 }
8459
8460 /* Return true if a function argument of type TYPE and mode MODE
8461 is to be passed in a floating-point register, if available. */
8462
8463 static bool
8464 s390_function_arg_float (enum machine_mode mode, const_tree type)
8465 {
8466 int size = s390_function_arg_size (mode, type);
8467 if (size > 8)
8468 return false;
8469
8470 /* Soft-float changes the ABI: no floating-point registers are used. */
8471 if (TARGET_SOFT_FLOAT)
8472 return false;
8473
8474 /* No type info available for some library calls ... */
8475 if (!type)
8476 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8477
8478 /* The ABI says that record types with a single member are treated
8479 just like that member would be. */
8480 while (TREE_CODE (type) == RECORD_TYPE)
8481 {
8482 tree field, single = NULL_TREE;
8483
8484 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8485 {
8486 if (TREE_CODE (field) != FIELD_DECL)
8487 continue;
8488
8489 if (single == NULL_TREE)
8490 single = TREE_TYPE (field);
8491 else
8492 return false;
8493 }
8494
8495 if (single == NULL_TREE)
8496 return false;
8497 else
8498 type = single;
8499 }
8500
8501 return TREE_CODE (type) == REAL_TYPE;
8502 }
8503
8504 /* Return true if a function argument of type TYPE and mode MODE
8505 is to be passed in an integer register, or a pair of integer
8506 registers, if available. */
8507
8508 static bool
8509 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8510 {
8511 int size = s390_function_arg_size (mode, type);
8512 if (size > 8)
8513 return false;
8514
8515 /* No type info available for some library calls ... */
8516 if (!type)
8517 return GET_MODE_CLASS (mode) == MODE_INT
8518 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8519
8520 /* We accept small integral (and similar) types. */
8521 if (INTEGRAL_TYPE_P (type)
8522 || POINTER_TYPE_P (type)
8523 || TREE_CODE (type) == NULLPTR_TYPE
8524 || TREE_CODE (type) == OFFSET_TYPE
8525 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8526 return true;
8527
8528 /* We also accept structs of size 1, 2, 4, 8 that are not
8529 passed in floating-point registers. */
8530 if (AGGREGATE_TYPE_P (type)
8531 && exact_log2 (size) >= 0
8532 && !s390_function_arg_float (mode, type))
8533 return true;
8534
8535 return false;
8536 }
8537
8538 /* Return 1 if a function argument of type TYPE and mode MODE
8539 is to be passed by reference. The ABI specifies that only
8540 structures of size 1, 2, 4, or 8 bytes are passed by value,
8541 all other structures (and complex numbers) are passed by
8542 reference. */
8543
8544 static bool
8545 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8546 enum machine_mode mode, const_tree type,
8547 bool named ATTRIBUTE_UNUSED)
8548 {
8549 int size = s390_function_arg_size (mode, type);
8550 if (size > 8)
8551 return true;
8552
8553 if (type)
8554 {
8555 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8556 return 1;
8557
8558 if (TREE_CODE (type) == COMPLEX_TYPE
8559 || TREE_CODE (type) == VECTOR_TYPE)
8560 return 1;
8561 }
8562
8563 return 0;
8564 }
8565
8566 /* Update the data in CUM to advance over an argument of mode MODE and
8567 data type TYPE. (TYPE is null for libcalls where that information
8568 may not be available.). The boolean NAMED specifies whether the
8569 argument is a named argument (as opposed to an unnamed argument
8570 matching an ellipsis). */
8571
8572 static void
8573 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8574 const_tree type, bool named ATTRIBUTE_UNUSED)
8575 {
8576 if (s390_function_arg_float (mode, type))
8577 {
8578 cum->fprs += 1;
8579 }
8580 else if (s390_function_arg_integer (mode, type))
8581 {
8582 int size = s390_function_arg_size (mode, type);
8583 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8584 }
8585 else
8586 gcc_unreachable ();
8587 }
8588
8589 /* Define where to put the arguments to a function.
8590 Value is zero to push the argument on the stack,
8591 or a hard register in which to store the argument.
8592
8593 MODE is the argument's machine mode.
8594 TYPE is the data type of the argument (as a tree).
8595 This is null for libcalls where that information may
8596 not be available.
8597 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8598 the preceding args and about the function being called.
8599 NAMED is nonzero if this argument is a named parameter
8600 (otherwise it is an extra parameter matching an ellipsis).
8601
8602 On S/390, we use general purpose registers 2 through 6 to
8603 pass integer, pointer, and certain structure arguments, and
8604 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8605 to pass floating point arguments. All remaining arguments
8606 are pushed to the stack. */
8607
8608 static rtx
8609 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8610 const_tree type, bool named ATTRIBUTE_UNUSED)
8611 {
8612 if (s390_function_arg_float (mode, type))
8613 {
8614 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8615 return 0;
8616 else
8617 return gen_rtx_REG (mode, cum->fprs + 16);
8618 }
8619 else if (s390_function_arg_integer (mode, type))
8620 {
8621 int size = s390_function_arg_size (mode, type);
8622 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8623
8624 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8625 return 0;
8626 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8627 return gen_rtx_REG (mode, cum->gprs + 2);
8628 else if (n_gprs == 2)
8629 {
8630 rtvec p = rtvec_alloc (2);
8631
8632 RTVEC_ELT (p, 0)
8633 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8634 const0_rtx);
8635 RTVEC_ELT (p, 1)
8636 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8637 GEN_INT (4));
8638
8639 return gen_rtx_PARALLEL (mode, p);
8640 }
8641 }
8642
8643 /* After the real arguments, expand_call calls us once again
8644 with a void_type_node type. Whatever we return here is
8645 passed as operand 2 to the call expanders.
8646
8647 We don't need this feature ... */
8648 else if (type == void_type_node)
8649 return const0_rtx;
8650
8651 gcc_unreachable ();
8652 }
8653
8654 /* Return true if return values of type TYPE should be returned
8655 in a memory buffer whose address is passed by the caller as
8656 hidden first argument. */
8657
8658 static bool
8659 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8660 {
8661 /* We accept small integral (and similar) types. */
8662 if (INTEGRAL_TYPE_P (type)
8663 || POINTER_TYPE_P (type)
8664 || TREE_CODE (type) == OFFSET_TYPE
8665 || TREE_CODE (type) == REAL_TYPE)
8666 return int_size_in_bytes (type) > 8;
8667
8668 /* Aggregates and similar constructs are always returned
8669 in memory. */
8670 if (AGGREGATE_TYPE_P (type)
8671 || TREE_CODE (type) == COMPLEX_TYPE
8672 || TREE_CODE (type) == VECTOR_TYPE)
8673 return true;
8674
8675 /* ??? We get called on all sorts of random stuff from
8676 aggregate_value_p. We can't abort, but it's not clear
8677 what's safe to return. Pretend it's a struct I guess. */
8678 return true;
8679 }
8680
8681 /* Function arguments and return values are promoted to word size. */
8682
8683 static enum machine_mode
8684 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8685 int *punsignedp,
8686 const_tree fntype ATTRIBUTE_UNUSED,
8687 int for_return ATTRIBUTE_UNUSED)
8688 {
8689 if (INTEGRAL_MODE_P (mode)
8690 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8691 {
8692 if (POINTER_TYPE_P (type))
8693 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8694 return Pmode;
8695 }
8696
8697 return mode;
8698 }
8699
8700 /* Define where to return a (scalar) value of type RET_TYPE.
8701 If RET_TYPE is null, define where to return a (scalar)
8702 value of mode MODE from a libcall. */
8703
8704 static rtx
8705 s390_function_and_libcall_value (enum machine_mode mode,
8706 const_tree ret_type,
8707 const_tree fntype_or_decl,
8708 bool outgoing ATTRIBUTE_UNUSED)
8709 {
8710 /* For normal functions perform the promotion as
8711 promote_function_mode would do. */
8712 if (ret_type)
8713 {
8714 int unsignedp = TYPE_UNSIGNED (ret_type);
8715 mode = promote_function_mode (ret_type, mode, &unsignedp,
8716 fntype_or_decl, 1);
8717 }
8718
8719 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8720 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8721
8722 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8723 return gen_rtx_REG (mode, 16);
8724 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8725 || UNITS_PER_LONG == UNITS_PER_WORD)
8726 return gen_rtx_REG (mode, 2);
8727 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8728 {
8729 /* This case is triggered when returning a 64 bit value with
8730 -m31 -mzarch. Although the value would fit into a single
8731 register it has to be forced into a 32 bit register pair in
8732 order to match the ABI. */
8733 rtvec p = rtvec_alloc (2);
8734
8735 RTVEC_ELT (p, 0)
8736 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8737 RTVEC_ELT (p, 1)
8738 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8739
8740 return gen_rtx_PARALLEL (mode, p);
8741 }
8742
8743 gcc_unreachable ();
8744 }
8745
8746 /* Define where to return a scalar return value of type RET_TYPE. */
8747
8748 static rtx
8749 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8750 bool outgoing)
8751 {
8752 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8753 fn_decl_or_type, outgoing);
8754 }
8755
8756 /* Define where to return a scalar libcall return value of mode
8757 MODE. */
8758
8759 static rtx
8760 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8761 {
8762 return s390_function_and_libcall_value (mode, NULL_TREE,
8763 NULL_TREE, true);
8764 }
8765
8766
8767 /* Create and return the va_list datatype.
8768
8769 On S/390, va_list is an array type equivalent to
8770
8771 typedef struct __va_list_tag
8772 {
8773 long __gpr;
8774 long __fpr;
8775 void *__overflow_arg_area;
8776 void *__reg_save_area;
8777 } va_list[1];
8778
8779 where __gpr and __fpr hold the number of general purpose
8780 or floating point arguments used up to now, respectively,
8781 __overflow_arg_area points to the stack location of the
8782 next argument passed on the stack, and __reg_save_area
8783 always points to the start of the register area in the
8784 call frame of the current function. The function prologue
8785 saves all registers used for argument passing into this
8786 area if the function uses variable arguments. */
8787
8788 static tree
8789 s390_build_builtin_va_list (void)
8790 {
8791 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8792
8793 record = lang_hooks.types.make_type (RECORD_TYPE);
8794
8795 type_decl =
8796 build_decl (BUILTINS_LOCATION,
8797 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8798
8799 f_gpr = build_decl (BUILTINS_LOCATION,
8800 FIELD_DECL, get_identifier ("__gpr"),
8801 long_integer_type_node);
8802 f_fpr = build_decl (BUILTINS_LOCATION,
8803 FIELD_DECL, get_identifier ("__fpr"),
8804 long_integer_type_node);
8805 f_ovf = build_decl (BUILTINS_LOCATION,
8806 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8807 ptr_type_node);
8808 f_sav = build_decl (BUILTINS_LOCATION,
8809 FIELD_DECL, get_identifier ("__reg_save_area"),
8810 ptr_type_node);
8811
8812 va_list_gpr_counter_field = f_gpr;
8813 va_list_fpr_counter_field = f_fpr;
8814
8815 DECL_FIELD_CONTEXT (f_gpr) = record;
8816 DECL_FIELD_CONTEXT (f_fpr) = record;
8817 DECL_FIELD_CONTEXT (f_ovf) = record;
8818 DECL_FIELD_CONTEXT (f_sav) = record;
8819
8820 TYPE_STUB_DECL (record) = type_decl;
8821 TYPE_NAME (record) = type_decl;
8822 TYPE_FIELDS (record) = f_gpr;
8823 DECL_CHAIN (f_gpr) = f_fpr;
8824 DECL_CHAIN (f_fpr) = f_ovf;
8825 DECL_CHAIN (f_ovf) = f_sav;
8826
8827 layout_type (record);
8828
8829 /* The correct type is an array type of one element. */
8830 return build_array_type (record, build_index_type (size_zero_node));
8831 }
8832
8833 /* Implement va_start by filling the va_list structure VALIST.
8834 STDARG_P is always true, and ignored.
8835 NEXTARG points to the first anonymous stack argument.
8836
8837 The following global variables are used to initialize
8838 the va_list structure:
8839
8840 crtl->args.info:
8841 holds number of gprs and fprs used for named arguments.
8842 crtl->args.arg_offset_rtx:
8843 holds the offset of the first anonymous stack argument
8844 (relative to the virtual arg pointer). */
8845
8846 static void
8847 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8848 {
8849 HOST_WIDE_INT n_gpr, n_fpr;
8850 int off;
8851 tree f_gpr, f_fpr, f_ovf, f_sav;
8852 tree gpr, fpr, ovf, sav, t;
8853
8854 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8855 f_fpr = DECL_CHAIN (f_gpr);
8856 f_ovf = DECL_CHAIN (f_fpr);
8857 f_sav = DECL_CHAIN (f_ovf);
8858
8859 valist = build_simple_mem_ref (valist);
8860 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8861 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8862 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8863 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8864
8865 /* Count number of gp and fp argument registers used. */
8866
8867 n_gpr = crtl->args.info.gprs;
8868 n_fpr = crtl->args.info.fprs;
8869
8870 if (cfun->va_list_gpr_size)
8871 {
8872 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8873 build_int_cst (NULL_TREE, n_gpr));
8874 TREE_SIDE_EFFECTS (t) = 1;
8875 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8876 }
8877
8878 if (cfun->va_list_fpr_size)
8879 {
8880 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8881 build_int_cst (NULL_TREE, n_fpr));
8882 TREE_SIDE_EFFECTS (t) = 1;
8883 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8884 }
8885
8886 /* Find the overflow area. */
8887 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8888 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8889 {
8890 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8891
8892 off = INTVAL (crtl->args.arg_offset_rtx);
8893 off = off < 0 ? 0 : off;
8894 if (TARGET_DEBUG_ARG)
8895 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8896 (int)n_gpr, (int)n_fpr, off);
8897
8898 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8899
8900 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8901 TREE_SIDE_EFFECTS (t) = 1;
8902 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8903 }
8904
8905 /* Find the register save area. */
8906 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8907 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8908 {
8909 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8910 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8911 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8912
8913 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8914 TREE_SIDE_EFFECTS (t) = 1;
8915 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8916 }
8917 }
8918
8919 /* Implement va_arg by updating the va_list structure
8920 VALIST as required to retrieve an argument of type
8921 TYPE, and returning that argument.
8922
8923 Generates code equivalent to:
8924
8925 if (integral value) {
8926 if (size <= 4 && args.gpr < 5 ||
8927 size > 4 && args.gpr < 4 )
8928 ret = args.reg_save_area[args.gpr+8]
8929 else
8930 ret = *args.overflow_arg_area++;
8931 } else if (float value) {
8932 if (args.fgpr < 2)
8933 ret = args.reg_save_area[args.fpr+64]
8934 else
8935 ret = *args.overflow_arg_area++;
8936 } else if (aggregate value) {
8937 if (args.gpr < 5)
8938 ret = *args.reg_save_area[args.gpr]
8939 else
8940 ret = **args.overflow_arg_area++;
8941 } */
8942
8943 static tree
8944 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8945 gimple_seq *post_p ATTRIBUTE_UNUSED)
8946 {
8947 tree f_gpr, f_fpr, f_ovf, f_sav;
8948 tree gpr, fpr, ovf, sav, reg, t, u;
8949 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8950 tree lab_false, lab_over, addr;
8951
8952 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8953 f_fpr = DECL_CHAIN (f_gpr);
8954 f_ovf = DECL_CHAIN (f_fpr);
8955 f_sav = DECL_CHAIN (f_ovf);
8956
8957 valist = build_va_arg_indirect_ref (valist);
8958 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8959 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8960 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8961
8962 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8963 both appear on a lhs. */
8964 valist = unshare_expr (valist);
8965 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8966
8967 size = int_size_in_bytes (type);
8968
8969 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8970 {
8971 if (TARGET_DEBUG_ARG)
8972 {
8973 fprintf (stderr, "va_arg: aggregate type");
8974 debug_tree (type);
8975 }
8976
8977 /* Aggregates are passed by reference. */
8978 indirect_p = 1;
8979 reg = gpr;
8980 n_reg = 1;
8981
8982 /* kernel stack layout on 31 bit: It is assumed here that no padding
8983 will be added by s390_frame_info because for va_args always an even
8984 number of gprs has to be saved r15-r2 = 14 regs. */
8985 sav_ofs = 2 * UNITS_PER_LONG;
8986 sav_scale = UNITS_PER_LONG;
8987 size = UNITS_PER_LONG;
8988 max_reg = GP_ARG_NUM_REG - n_reg;
8989 }
8990 else if (s390_function_arg_float (TYPE_MODE (type), type))
8991 {
8992 if (TARGET_DEBUG_ARG)
8993 {
8994 fprintf (stderr, "va_arg: float type");
8995 debug_tree (type);
8996 }
8997
8998 /* FP args go in FP registers, if present. */
8999 indirect_p = 0;
9000 reg = fpr;
9001 n_reg = 1;
9002 sav_ofs = 16 * UNITS_PER_LONG;
9003 sav_scale = 8;
9004 max_reg = FP_ARG_NUM_REG - n_reg;
9005 }
9006 else
9007 {
9008 if (TARGET_DEBUG_ARG)
9009 {
9010 fprintf (stderr, "va_arg: other type");
9011 debug_tree (type);
9012 }
9013
9014 /* Otherwise into GP registers. */
9015 indirect_p = 0;
9016 reg = gpr;
9017 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9018
9019 /* kernel stack layout on 31 bit: It is assumed here that no padding
9020 will be added by s390_frame_info because for va_args always an even
9021 number of gprs has to be saved r15-r2 = 14 regs. */
9022 sav_ofs = 2 * UNITS_PER_LONG;
9023
9024 if (size < UNITS_PER_LONG)
9025 sav_ofs += UNITS_PER_LONG - size;
9026
9027 sav_scale = UNITS_PER_LONG;
9028 max_reg = GP_ARG_NUM_REG - n_reg;
9029 }
9030
9031 /* Pull the value out of the saved registers ... */
9032
9033 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9034 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9035 addr = create_tmp_var (ptr_type_node, "addr");
9036
9037 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9038 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9039 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9040 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9041 gimplify_and_add (t, pre_p);
9042
9043 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
9044 size_int (sav_ofs));
9045 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9046 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9047 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
9048
9049 gimplify_assign (addr, t, pre_p);
9050
9051 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9052
9053 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9054
9055
9056 /* ... Otherwise out of the overflow area. */
9057
9058 t = ovf;
9059 if (size < UNITS_PER_LONG)
9060 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
9061 size_int (UNITS_PER_LONG - size));
9062
9063 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9064
9065 gimplify_assign (addr, t, pre_p);
9066
9067 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
9068 size_int (size));
9069 gimplify_assign (ovf, t, pre_p);
9070
9071 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9072
9073
9074 /* Increment register save count. */
9075
9076 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9077 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9078 gimplify_and_add (u, pre_p);
9079
9080 if (indirect_p)
9081 {
9082 t = build_pointer_type_for_mode (build_pointer_type (type),
9083 ptr_mode, true);
9084 addr = fold_convert (t, addr);
9085 addr = build_va_arg_indirect_ref (addr);
9086 }
9087 else
9088 {
9089 t = build_pointer_type_for_mode (type, ptr_mode, true);
9090 addr = fold_convert (t, addr);
9091 }
9092
9093 return build_va_arg_indirect_ref (addr);
9094 }
9095
9096
9097 /* Builtins. */
9098
9099 enum s390_builtin
9100 {
9101 S390_BUILTIN_THREAD_POINTER,
9102 S390_BUILTIN_SET_THREAD_POINTER,
9103
9104 S390_BUILTIN_max
9105 };
9106
9107 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9108 CODE_FOR_get_tp_64,
9109 CODE_FOR_set_tp_64
9110 };
9111
9112 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9113 CODE_FOR_get_tp_31,
9114 CODE_FOR_set_tp_31
9115 };
9116
9117 static void
9118 s390_init_builtins (void)
9119 {
9120 tree ftype;
9121
9122 ftype = build_function_type (ptr_type_node, void_list_node);
9123 add_builtin_function ("__builtin_thread_pointer", ftype,
9124 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9125 NULL, NULL_TREE);
9126
9127 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9128 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9129 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9130 NULL, NULL_TREE);
9131 }
9132
9133 /* Expand an expression EXP that calls a built-in function,
9134 with result going to TARGET if that's convenient
9135 (and in mode MODE if that's convenient).
9136 SUBTARGET may be used as the target for computing one of EXP's operands.
9137 IGNORE is nonzero if the value is to be ignored. */
9138
9139 static rtx
9140 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9141 enum machine_mode mode ATTRIBUTE_UNUSED,
9142 int ignore ATTRIBUTE_UNUSED)
9143 {
9144 #define MAX_ARGS 2
9145
9146 enum insn_code const *code_for_builtin =
9147 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9148
9149 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9150 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9151 enum insn_code icode;
9152 rtx op[MAX_ARGS], pat;
9153 int arity;
9154 bool nonvoid;
9155 tree arg;
9156 call_expr_arg_iterator iter;
9157
9158 if (fcode >= S390_BUILTIN_max)
9159 internal_error ("bad builtin fcode");
9160 icode = code_for_builtin[fcode];
9161 if (icode == 0)
9162 internal_error ("bad builtin fcode");
9163
9164 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9165
9166 arity = 0;
9167 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9168 {
9169 const struct insn_operand_data *insn_op;
9170
9171 if (arg == error_mark_node)
9172 return NULL_RTX;
9173 if (arity > MAX_ARGS)
9174 return NULL_RTX;
9175
9176 insn_op = &insn_data[icode].operand[arity + nonvoid];
9177
9178 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9179
9180 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9181 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9182 arity++;
9183 }
9184
9185 if (nonvoid)
9186 {
9187 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9188 if (!target
9189 || GET_MODE (target) != tmode
9190 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9191 target = gen_reg_rtx (tmode);
9192 }
9193
9194 switch (arity)
9195 {
9196 case 0:
9197 pat = GEN_FCN (icode) (target);
9198 break;
9199 case 1:
9200 if (nonvoid)
9201 pat = GEN_FCN (icode) (target, op[0]);
9202 else
9203 pat = GEN_FCN (icode) (op[0]);
9204 break;
9205 case 2:
9206 pat = GEN_FCN (icode) (target, op[0], op[1]);
9207 break;
9208 default:
9209 gcc_unreachable ();
9210 }
9211 if (!pat)
9212 return NULL_RTX;
9213 emit_insn (pat);
9214
9215 if (nonvoid)
9216 return target;
9217 else
9218 return const0_rtx;
9219 }
9220
9221
9222 /* Output assembly code for the trampoline template to
9223 stdio stream FILE.
9224
9225 On S/390, we use gpr 1 internally in the trampoline code;
9226 gpr 0 is used to hold the static chain. */
9227
9228 static void
9229 s390_asm_trampoline_template (FILE *file)
9230 {
9231 rtx op[2];
9232 op[0] = gen_rtx_REG (Pmode, 0);
9233 op[1] = gen_rtx_REG (Pmode, 1);
9234
9235 if (TARGET_64BIT)
9236 {
9237 output_asm_insn ("basr\t%1,0", op);
9238 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9239 output_asm_insn ("br\t%1", op);
9240 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9241 }
9242 else
9243 {
9244 output_asm_insn ("basr\t%1,0", op);
9245 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9246 output_asm_insn ("br\t%1", op);
9247 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9248 }
9249 }
9250
9251 /* Emit RTL insns to initialize the variable parts of a trampoline.
9252 FNADDR is an RTX for the address of the function's pure code.
9253 CXT is an RTX for the static chain value for the function. */
9254
9255 static void
9256 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9257 {
9258 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9259 rtx mem;
9260
9261 emit_block_move (m_tramp, assemble_trampoline_template (),
9262 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9263
9264 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9265 emit_move_insn (mem, cxt);
9266 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9267 emit_move_insn (mem, fnaddr);
9268 }
9269
9270 /* Output assembler code to FILE to increment profiler label # LABELNO
9271 for profiling a function entry. */
9272
9273 void
9274 s390_function_profiler (FILE *file, int labelno)
9275 {
9276 rtx op[7];
9277
9278 char label[128];
9279 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9280
9281 fprintf (file, "# function profiler \n");
9282
9283 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9284 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9285 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9286
9287 op[2] = gen_rtx_REG (Pmode, 1);
9288 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9289 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9290
9291 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9292 if (flag_pic)
9293 {
9294 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9295 op[4] = gen_rtx_CONST (Pmode, op[4]);
9296 }
9297
9298 if (TARGET_64BIT)
9299 {
9300 output_asm_insn ("stg\t%0,%1", op);
9301 output_asm_insn ("larl\t%2,%3", op);
9302 output_asm_insn ("brasl\t%0,%4", op);
9303 output_asm_insn ("lg\t%0,%1", op);
9304 }
9305 else if (!flag_pic)
9306 {
9307 op[6] = gen_label_rtx ();
9308
9309 output_asm_insn ("st\t%0,%1", op);
9310 output_asm_insn ("bras\t%2,%l6", op);
9311 output_asm_insn (".long\t%4", op);
9312 output_asm_insn (".long\t%3", op);
9313 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9314 output_asm_insn ("l\t%0,0(%2)", op);
9315 output_asm_insn ("l\t%2,4(%2)", op);
9316 output_asm_insn ("basr\t%0,%0", op);
9317 output_asm_insn ("l\t%0,%1", op);
9318 }
9319 else
9320 {
9321 op[5] = gen_label_rtx ();
9322 op[6] = gen_label_rtx ();
9323
9324 output_asm_insn ("st\t%0,%1", op);
9325 output_asm_insn ("bras\t%2,%l6", op);
9326 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9327 output_asm_insn (".long\t%4-%l5", op);
9328 output_asm_insn (".long\t%3-%l5", op);
9329 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9330 output_asm_insn ("lr\t%0,%2", op);
9331 output_asm_insn ("a\t%0,0(%2)", op);
9332 output_asm_insn ("a\t%2,4(%2)", op);
9333 output_asm_insn ("basr\t%0,%0", op);
9334 output_asm_insn ("l\t%0,%1", op);
9335 }
9336 }
9337
9338 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9339 into its SYMBOL_REF_FLAGS. */
9340
9341 static void
9342 s390_encode_section_info (tree decl, rtx rtl, int first)
9343 {
9344 default_encode_section_info (decl, rtl, first);
9345
9346 if (TREE_CODE (decl) == VAR_DECL)
9347 {
9348 /* If a variable has a forced alignment to < 2 bytes, mark it
9349 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9350 operand. */
9351 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9352 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9353 if (!DECL_SIZE (decl)
9354 || !DECL_ALIGN (decl)
9355 || !host_integerp (DECL_SIZE (decl), 0)
9356 || (DECL_ALIGN (decl) <= 64
9357 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9358 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9359 }
9360
9361 /* Literal pool references don't have a decl so they are handled
9362 differently here. We rely on the information in the MEM_ALIGN
9363 entry to decide upon natural alignment. */
9364 if (MEM_P (rtl)
9365 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9366 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9367 && (MEM_ALIGN (rtl) == 0
9368 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9369 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9370 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9371 }
9372
9373 /* Output thunk to FILE that implements a C++ virtual function call (with
9374 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9375 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9376 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9377 relative to the resulting this pointer. */
9378
9379 static void
9380 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9381 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9382 tree function)
9383 {
9384 rtx op[10];
9385 int nonlocal = 0;
9386
9387 /* Make sure unwind info is emitted for the thunk if needed. */
9388 final_start_function (emit_barrier (), file, 1);
9389
9390 /* Operand 0 is the target function. */
9391 op[0] = XEXP (DECL_RTL (function), 0);
9392 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9393 {
9394 nonlocal = 1;
9395 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9396 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9397 op[0] = gen_rtx_CONST (Pmode, op[0]);
9398 }
9399
9400 /* Operand 1 is the 'this' pointer. */
9401 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9402 op[1] = gen_rtx_REG (Pmode, 3);
9403 else
9404 op[1] = gen_rtx_REG (Pmode, 2);
9405
9406 /* Operand 2 is the delta. */
9407 op[2] = GEN_INT (delta);
9408
9409 /* Operand 3 is the vcall_offset. */
9410 op[3] = GEN_INT (vcall_offset);
9411
9412 /* Operand 4 is the temporary register. */
9413 op[4] = gen_rtx_REG (Pmode, 1);
9414
9415 /* Operands 5 to 8 can be used as labels. */
9416 op[5] = NULL_RTX;
9417 op[6] = NULL_RTX;
9418 op[7] = NULL_RTX;
9419 op[8] = NULL_RTX;
9420
9421 /* Operand 9 can be used for temporary register. */
9422 op[9] = NULL_RTX;
9423
9424 /* Generate code. */
9425 if (TARGET_64BIT)
9426 {
9427 /* Setup literal pool pointer if required. */
9428 if ((!DISP_IN_RANGE (delta)
9429 && !CONST_OK_FOR_K (delta)
9430 && !CONST_OK_FOR_Os (delta))
9431 || (!DISP_IN_RANGE (vcall_offset)
9432 && !CONST_OK_FOR_K (vcall_offset)
9433 && !CONST_OK_FOR_Os (vcall_offset)))
9434 {
9435 op[5] = gen_label_rtx ();
9436 output_asm_insn ("larl\t%4,%5", op);
9437 }
9438
9439 /* Add DELTA to this pointer. */
9440 if (delta)
9441 {
9442 if (CONST_OK_FOR_J (delta))
9443 output_asm_insn ("la\t%1,%2(%1)", op);
9444 else if (DISP_IN_RANGE (delta))
9445 output_asm_insn ("lay\t%1,%2(%1)", op);
9446 else if (CONST_OK_FOR_K (delta))
9447 output_asm_insn ("aghi\t%1,%2", op);
9448 else if (CONST_OK_FOR_Os (delta))
9449 output_asm_insn ("agfi\t%1,%2", op);
9450 else
9451 {
9452 op[6] = gen_label_rtx ();
9453 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9454 }
9455 }
9456
9457 /* Perform vcall adjustment. */
9458 if (vcall_offset)
9459 {
9460 if (DISP_IN_RANGE (vcall_offset))
9461 {
9462 output_asm_insn ("lg\t%4,0(%1)", op);
9463 output_asm_insn ("ag\t%1,%3(%4)", op);
9464 }
9465 else if (CONST_OK_FOR_K (vcall_offset))
9466 {
9467 output_asm_insn ("lghi\t%4,%3", op);
9468 output_asm_insn ("ag\t%4,0(%1)", op);
9469 output_asm_insn ("ag\t%1,0(%4)", op);
9470 }
9471 else if (CONST_OK_FOR_Os (vcall_offset))
9472 {
9473 output_asm_insn ("lgfi\t%4,%3", op);
9474 output_asm_insn ("ag\t%4,0(%1)", op);
9475 output_asm_insn ("ag\t%1,0(%4)", op);
9476 }
9477 else
9478 {
9479 op[7] = gen_label_rtx ();
9480 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9481 output_asm_insn ("ag\t%4,0(%1)", op);
9482 output_asm_insn ("ag\t%1,0(%4)", op);
9483 }
9484 }
9485
9486 /* Jump to target. */
9487 output_asm_insn ("jg\t%0", op);
9488
9489 /* Output literal pool if required. */
9490 if (op[5])
9491 {
9492 output_asm_insn (".align\t4", op);
9493 targetm.asm_out.internal_label (file, "L",
9494 CODE_LABEL_NUMBER (op[5]));
9495 }
9496 if (op[6])
9497 {
9498 targetm.asm_out.internal_label (file, "L",
9499 CODE_LABEL_NUMBER (op[6]));
9500 output_asm_insn (".long\t%2", op);
9501 }
9502 if (op[7])
9503 {
9504 targetm.asm_out.internal_label (file, "L",
9505 CODE_LABEL_NUMBER (op[7]));
9506 output_asm_insn (".long\t%3", op);
9507 }
9508 }
9509 else
9510 {
9511 /* Setup base pointer if required. */
9512 if (!vcall_offset
9513 || (!DISP_IN_RANGE (delta)
9514 && !CONST_OK_FOR_K (delta)
9515 && !CONST_OK_FOR_Os (delta))
9516 || (!DISP_IN_RANGE (delta)
9517 && !CONST_OK_FOR_K (vcall_offset)
9518 && !CONST_OK_FOR_Os (vcall_offset)))
9519 {
9520 op[5] = gen_label_rtx ();
9521 output_asm_insn ("basr\t%4,0", op);
9522 targetm.asm_out.internal_label (file, "L",
9523 CODE_LABEL_NUMBER (op[5]));
9524 }
9525
9526 /* Add DELTA to this pointer. */
9527 if (delta)
9528 {
9529 if (CONST_OK_FOR_J (delta))
9530 output_asm_insn ("la\t%1,%2(%1)", op);
9531 else if (DISP_IN_RANGE (delta))
9532 output_asm_insn ("lay\t%1,%2(%1)", op);
9533 else if (CONST_OK_FOR_K (delta))
9534 output_asm_insn ("ahi\t%1,%2", op);
9535 else if (CONST_OK_FOR_Os (delta))
9536 output_asm_insn ("afi\t%1,%2", op);
9537 else
9538 {
9539 op[6] = gen_label_rtx ();
9540 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9541 }
9542 }
9543
9544 /* Perform vcall adjustment. */
9545 if (vcall_offset)
9546 {
9547 if (CONST_OK_FOR_J (vcall_offset))
9548 {
9549 output_asm_insn ("l\t%4,0(%1)", op);
9550 output_asm_insn ("a\t%1,%3(%4)", op);
9551 }
9552 else if (DISP_IN_RANGE (vcall_offset))
9553 {
9554 output_asm_insn ("l\t%4,0(%1)", op);
9555 output_asm_insn ("ay\t%1,%3(%4)", op);
9556 }
9557 else if (CONST_OK_FOR_K (vcall_offset))
9558 {
9559 output_asm_insn ("lhi\t%4,%3", op);
9560 output_asm_insn ("a\t%4,0(%1)", op);
9561 output_asm_insn ("a\t%1,0(%4)", op);
9562 }
9563 else if (CONST_OK_FOR_Os (vcall_offset))
9564 {
9565 output_asm_insn ("iilf\t%4,%3", op);
9566 output_asm_insn ("a\t%4,0(%1)", op);
9567 output_asm_insn ("a\t%1,0(%4)", op);
9568 }
9569 else
9570 {
9571 op[7] = gen_label_rtx ();
9572 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9573 output_asm_insn ("a\t%4,0(%1)", op);
9574 output_asm_insn ("a\t%1,0(%4)", op);
9575 }
9576
9577 /* We had to clobber the base pointer register.
9578 Re-setup the base pointer (with a different base). */
9579 op[5] = gen_label_rtx ();
9580 output_asm_insn ("basr\t%4,0", op);
9581 targetm.asm_out.internal_label (file, "L",
9582 CODE_LABEL_NUMBER (op[5]));
9583 }
9584
9585 /* Jump to target. */
9586 op[8] = gen_label_rtx ();
9587
9588 if (!flag_pic)
9589 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9590 else if (!nonlocal)
9591 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9592 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9593 else if (flag_pic == 1)
9594 {
9595 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9596 output_asm_insn ("l\t%4,%0(%4)", op);
9597 }
9598 else if (flag_pic == 2)
9599 {
9600 op[9] = gen_rtx_REG (Pmode, 0);
9601 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9602 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9603 output_asm_insn ("ar\t%4,%9", op);
9604 output_asm_insn ("l\t%4,0(%4)", op);
9605 }
9606
9607 output_asm_insn ("br\t%4", op);
9608
9609 /* Output literal pool. */
9610 output_asm_insn (".align\t4", op);
9611
9612 if (nonlocal && flag_pic == 2)
9613 output_asm_insn (".long\t%0", op);
9614 if (nonlocal)
9615 {
9616 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9617 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9618 }
9619
9620 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9621 if (!flag_pic)
9622 output_asm_insn (".long\t%0", op);
9623 else
9624 output_asm_insn (".long\t%0-%5", op);
9625
9626 if (op[6])
9627 {
9628 targetm.asm_out.internal_label (file, "L",
9629 CODE_LABEL_NUMBER (op[6]));
9630 output_asm_insn (".long\t%2", op);
9631 }
9632 if (op[7])
9633 {
9634 targetm.asm_out.internal_label (file, "L",
9635 CODE_LABEL_NUMBER (op[7]));
9636 output_asm_insn (".long\t%3", op);
9637 }
9638 }
9639 final_end_function ();
9640 }
9641
9642 static bool
9643 s390_valid_pointer_mode (enum machine_mode mode)
9644 {
9645 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9646 }
9647
9648 /* Checks whether the given CALL_EXPR would use a caller
9649 saved register. This is used to decide whether sibling call
9650 optimization could be performed on the respective function
9651 call. */
9652
9653 static bool
9654 s390_call_saved_register_used (tree call_expr)
9655 {
9656 CUMULATIVE_ARGS cum;
9657 tree parameter;
9658 enum machine_mode mode;
9659 tree type;
9660 rtx parm_rtx;
9661 int reg, i;
9662
9663 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9664
9665 for (i = 0; i < call_expr_nargs (call_expr); i++)
9666 {
9667 parameter = CALL_EXPR_ARG (call_expr, i);
9668 gcc_assert (parameter);
9669
9670 /* For an undeclared variable passed as parameter we will get
9671 an ERROR_MARK node here. */
9672 if (TREE_CODE (parameter) == ERROR_MARK)
9673 return true;
9674
9675 type = TREE_TYPE (parameter);
9676 gcc_assert (type);
9677
9678 mode = TYPE_MODE (type);
9679 gcc_assert (mode);
9680
9681 if (pass_by_reference (&cum, mode, type, true))
9682 {
9683 mode = Pmode;
9684 type = build_pointer_type (type);
9685 }
9686
9687 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9688
9689 s390_function_arg_advance (&cum, mode, type, 0);
9690
9691 if (!parm_rtx)
9692 continue;
9693
9694 if (REG_P (parm_rtx))
9695 {
9696 for (reg = 0;
9697 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9698 reg++)
9699 if (!call_used_regs[reg + REGNO (parm_rtx)])
9700 return true;
9701 }
9702
9703 if (GET_CODE (parm_rtx) == PARALLEL)
9704 {
9705 int i;
9706
9707 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9708 {
9709 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9710
9711 gcc_assert (REG_P (r));
9712
9713 for (reg = 0;
9714 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9715 reg++)
9716 if (!call_used_regs[reg + REGNO (r)])
9717 return true;
9718 }
9719 }
9720
9721 }
9722 return false;
9723 }
9724
9725 /* Return true if the given call expression can be
9726 turned into a sibling call.
9727 DECL holds the declaration of the function to be called whereas
9728 EXP is the call expression itself. */
9729
9730 static bool
9731 s390_function_ok_for_sibcall (tree decl, tree exp)
9732 {
9733 /* The TPF epilogue uses register 1. */
9734 if (TARGET_TPF_PROFILING)
9735 return false;
9736
9737 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9738 which would have to be restored before the sibcall. */
9739 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9740 return false;
9741
9742 /* Register 6 on s390 is available as an argument register but unfortunately
9743 "caller saved". This makes functions needing this register for arguments
9744 not suitable for sibcalls. */
9745 return !s390_call_saved_register_used (exp);
9746 }
9747
9748 /* Return the fixed registers used for condition codes. */
9749
9750 static bool
9751 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9752 {
9753 *p1 = CC_REGNUM;
9754 *p2 = INVALID_REGNUM;
9755
9756 return true;
9757 }
9758
9759 /* This function is used by the call expanders of the machine description.
9760 It emits the call insn itself together with the necessary operations
9761 to adjust the target address and returns the emitted insn.
9762 ADDR_LOCATION is the target address rtx
9763 TLS_CALL the location of the thread-local symbol
9764 RESULT_REG the register where the result of the call should be stored
9765 RETADDR_REG the register where the return address should be stored
9766 If this parameter is NULL_RTX the call is considered
9767 to be a sibling call. */
9768
9769 rtx
9770 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9771 rtx retaddr_reg)
9772 {
9773 bool plt_call = false;
9774 rtx insn;
9775 rtx call;
9776 rtx clobber;
9777 rtvec vec;
9778
9779 /* Direct function calls need special treatment. */
9780 if (GET_CODE (addr_location) == SYMBOL_REF)
9781 {
9782 /* When calling a global routine in PIC mode, we must
9783 replace the symbol itself with the PLT stub. */
9784 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9785 {
9786 if (retaddr_reg != NULL_RTX)
9787 {
9788 addr_location = gen_rtx_UNSPEC (Pmode,
9789 gen_rtvec (1, addr_location),
9790 UNSPEC_PLT);
9791 addr_location = gen_rtx_CONST (Pmode, addr_location);
9792 plt_call = true;
9793 }
9794 else
9795 /* For -fpic code the PLT entries might use r12 which is
9796 call-saved. Therefore we cannot do a sibcall when
9797 calling directly using a symbol ref. When reaching
9798 this point we decided (in s390_function_ok_for_sibcall)
9799 to do a sibcall for a function pointer but one of the
9800 optimizers was able to get rid of the function pointer
9801 by propagating the symbol ref into the call. This
9802 optimization is illegal for S/390 so we turn the direct
9803 call into a indirect call again. */
9804 addr_location = force_reg (Pmode, addr_location);
9805 }
9806
9807 /* Unless we can use the bras(l) insn, force the
9808 routine address into a register. */
9809 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9810 {
9811 if (flag_pic)
9812 addr_location = legitimize_pic_address (addr_location, 0);
9813 else
9814 addr_location = force_reg (Pmode, addr_location);
9815 }
9816 }
9817
9818 /* If it is already an indirect call or the code above moved the
9819 SYMBOL_REF to somewhere else make sure the address can be found in
9820 register 1. */
9821 if (retaddr_reg == NULL_RTX
9822 && GET_CODE (addr_location) != SYMBOL_REF
9823 && !plt_call)
9824 {
9825 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9826 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9827 }
9828
9829 addr_location = gen_rtx_MEM (QImode, addr_location);
9830 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9831
9832 if (result_reg != NULL_RTX)
9833 call = gen_rtx_SET (VOIDmode, result_reg, call);
9834
9835 if (retaddr_reg != NULL_RTX)
9836 {
9837 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9838
9839 if (tls_call != NULL_RTX)
9840 vec = gen_rtvec (3, call, clobber,
9841 gen_rtx_USE (VOIDmode, tls_call));
9842 else
9843 vec = gen_rtvec (2, call, clobber);
9844
9845 call = gen_rtx_PARALLEL (VOIDmode, vec);
9846 }
9847
9848 insn = emit_call_insn (call);
9849
9850 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9851 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9852 {
9853 /* s390_function_ok_for_sibcall should
9854 have denied sibcalls in this case. */
9855 gcc_assert (retaddr_reg != NULL_RTX);
9856
9857 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9858 }
9859 return insn;
9860 }
9861
9862 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9863
9864 static void
9865 s390_conditional_register_usage (void)
9866 {
9867 int i;
9868
9869 if (flag_pic)
9870 {
9871 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9872 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9873 }
9874 if (TARGET_CPU_ZARCH)
9875 {
9876 fixed_regs[BASE_REGNUM] = 0;
9877 call_used_regs[BASE_REGNUM] = 0;
9878 fixed_regs[RETURN_REGNUM] = 0;
9879 call_used_regs[RETURN_REGNUM] = 0;
9880 }
9881 if (TARGET_64BIT)
9882 {
9883 for (i = 24; i < 32; i++)
9884 call_used_regs[i] = call_really_used_regs[i] = 0;
9885 }
9886 else
9887 {
9888 for (i = 18; i < 20; i++)
9889 call_used_regs[i] = call_really_used_regs[i] = 0;
9890 }
9891
9892 if (TARGET_SOFT_FLOAT)
9893 {
9894 for (i = 16; i < 32; i++)
9895 call_used_regs[i] = fixed_regs[i] = 1;
9896 }
9897 }
9898
9899 /* Corresponding function to eh_return expander. */
9900
9901 static GTY(()) rtx s390_tpf_eh_return_symbol;
9902 void
9903 s390_emit_tpf_eh_return (rtx target)
9904 {
9905 rtx insn, reg;
9906
9907 if (!s390_tpf_eh_return_symbol)
9908 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9909
9910 reg = gen_rtx_REG (Pmode, 2);
9911
9912 emit_move_insn (reg, target);
9913 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9914 gen_rtx_REG (Pmode, RETURN_REGNUM));
9915 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9916
9917 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9918 }
9919
9920 /* Rework the prologue/epilogue to avoid saving/restoring
9921 registers unnecessarily. */
9922
9923 static void
9924 s390_optimize_prologue (void)
9925 {
9926 rtx insn, new_insn, next_insn;
9927
9928 /* Do a final recompute of the frame-related data. */
9929
9930 s390_update_frame_layout ();
9931
9932 /* If all special registers are in fact used, there's nothing we
9933 can do, so no point in walking the insn list. */
9934
9935 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9936 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9937 && (TARGET_CPU_ZARCH
9938 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9939 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9940 return;
9941
9942 /* Search for prologue/epilogue insns and replace them. */
9943
9944 for (insn = get_insns (); insn; insn = next_insn)
9945 {
9946 int first, last, off;
9947 rtx set, base, offset;
9948
9949 next_insn = NEXT_INSN (insn);
9950
9951 if (GET_CODE (insn) != INSN)
9952 continue;
9953
9954 if (GET_CODE (PATTERN (insn)) == PARALLEL
9955 && store_multiple_operation (PATTERN (insn), VOIDmode))
9956 {
9957 set = XVECEXP (PATTERN (insn), 0, 0);
9958 first = REGNO (SET_SRC (set));
9959 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9960 offset = const0_rtx;
9961 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9962 off = INTVAL (offset);
9963
9964 if (GET_CODE (base) != REG || off < 0)
9965 continue;
9966 if (cfun_frame_layout.first_save_gpr != -1
9967 && (cfun_frame_layout.first_save_gpr < first
9968 || cfun_frame_layout.last_save_gpr > last))
9969 continue;
9970 if (REGNO (base) != STACK_POINTER_REGNUM
9971 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9972 continue;
9973 if (first > BASE_REGNUM || last < BASE_REGNUM)
9974 continue;
9975
9976 if (cfun_frame_layout.first_save_gpr != -1)
9977 {
9978 new_insn = save_gprs (base,
9979 off + (cfun_frame_layout.first_save_gpr
9980 - first) * UNITS_PER_LONG,
9981 cfun_frame_layout.first_save_gpr,
9982 cfun_frame_layout.last_save_gpr);
9983 new_insn = emit_insn_before (new_insn, insn);
9984 INSN_ADDRESSES_NEW (new_insn, -1);
9985 }
9986
9987 remove_insn (insn);
9988 continue;
9989 }
9990
9991 if (cfun_frame_layout.first_save_gpr == -1
9992 && GET_CODE (PATTERN (insn)) == SET
9993 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9994 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9995 || (!TARGET_CPU_ZARCH
9996 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9997 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9998 {
9999 set = PATTERN (insn);
10000 first = REGNO (SET_SRC (set));
10001 offset = const0_rtx;
10002 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10003 off = INTVAL (offset);
10004
10005 if (GET_CODE (base) != REG || off < 0)
10006 continue;
10007 if (REGNO (base) != STACK_POINTER_REGNUM
10008 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10009 continue;
10010
10011 remove_insn (insn);
10012 continue;
10013 }
10014
10015 if (GET_CODE (PATTERN (insn)) == PARALLEL
10016 && load_multiple_operation (PATTERN (insn), VOIDmode))
10017 {
10018 set = XVECEXP (PATTERN (insn), 0, 0);
10019 first = REGNO (SET_DEST (set));
10020 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10021 offset = const0_rtx;
10022 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10023 off = INTVAL (offset);
10024
10025 if (GET_CODE (base) != REG || off < 0)
10026 continue;
10027 if (cfun_frame_layout.first_restore_gpr != -1
10028 && (cfun_frame_layout.first_restore_gpr < first
10029 || cfun_frame_layout.last_restore_gpr > last))
10030 continue;
10031 if (REGNO (base) != STACK_POINTER_REGNUM
10032 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10033 continue;
10034 if (first > BASE_REGNUM || last < BASE_REGNUM)
10035 continue;
10036
10037 if (cfun_frame_layout.first_restore_gpr != -1)
10038 {
10039 new_insn = restore_gprs (base,
10040 off + (cfun_frame_layout.first_restore_gpr
10041 - first) * UNITS_PER_LONG,
10042 cfun_frame_layout.first_restore_gpr,
10043 cfun_frame_layout.last_restore_gpr);
10044 new_insn = emit_insn_before (new_insn, insn);
10045 INSN_ADDRESSES_NEW (new_insn, -1);
10046 }
10047
10048 remove_insn (insn);
10049 continue;
10050 }
10051
10052 if (cfun_frame_layout.first_restore_gpr == -1
10053 && GET_CODE (PATTERN (insn)) == SET
10054 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10055 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10056 || (!TARGET_CPU_ZARCH
10057 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10058 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10059 {
10060 set = PATTERN (insn);
10061 first = REGNO (SET_DEST (set));
10062 offset = const0_rtx;
10063 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10064 off = INTVAL (offset);
10065
10066 if (GET_CODE (base) != REG || off < 0)
10067 continue;
10068 if (REGNO (base) != STACK_POINTER_REGNUM
10069 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10070 continue;
10071
10072 remove_insn (insn);
10073 continue;
10074 }
10075 }
10076 }
10077
10078 /* On z10 and later the dynamic branch prediction must see the
10079 backward jump within a certain windows. If not it falls back to
10080 the static prediction. This function rearranges the loop backward
10081 branch in a way which makes the static prediction always correct.
10082 The function returns true if it added an instruction. */
10083 static bool
10084 s390_fix_long_loop_prediction (rtx insn)
10085 {
10086 rtx set = single_set (insn);
10087 rtx code_label, label_ref, new_label;
10088 rtx uncond_jump;
10089 rtx cur_insn;
10090 rtx tmp;
10091 int distance;
10092
10093 /* This will exclude branch on count and branch on index patterns
10094 since these are correctly statically predicted. */
10095 if (!set
10096 || SET_DEST (set) != pc_rtx
10097 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10098 return false;
10099
10100 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10101 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10102
10103 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10104
10105 code_label = XEXP (label_ref, 0);
10106
10107 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10108 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10109 || (INSN_ADDRESSES (INSN_UID (insn))
10110 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10111 return false;
10112
10113 for (distance = 0, cur_insn = PREV_INSN (insn);
10114 distance < PREDICT_DISTANCE - 6;
10115 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10116 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10117 return false;
10118
10119 new_label = gen_label_rtx ();
10120 uncond_jump = emit_jump_insn_after (
10121 gen_rtx_SET (VOIDmode, pc_rtx,
10122 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10123 insn);
10124 emit_label_after (new_label, uncond_jump);
10125
10126 tmp = XEXP (SET_SRC (set), 1);
10127 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10128 XEXP (SET_SRC (set), 2) = tmp;
10129 INSN_CODE (insn) = -1;
10130
10131 XEXP (label_ref, 0) = new_label;
10132 JUMP_LABEL (insn) = new_label;
10133 JUMP_LABEL (uncond_jump) = code_label;
10134
10135 return true;
10136 }
10137
10138 /* Returns 1 if INSN reads the value of REG for purposes not related
10139 to addressing of memory, and 0 otherwise. */
10140 static int
10141 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10142 {
10143 return reg_referenced_p (reg, PATTERN (insn))
10144 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10145 }
10146
10147 /* Starting from INSN find_cond_jump looks downwards in the insn
10148 stream for a single jump insn which is the last user of the
10149 condition code set in INSN. */
10150 static rtx
10151 find_cond_jump (rtx insn)
10152 {
10153 for (; insn; insn = NEXT_INSN (insn))
10154 {
10155 rtx ite, cc;
10156
10157 if (LABEL_P (insn))
10158 break;
10159
10160 if (!JUMP_P (insn))
10161 {
10162 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10163 break;
10164 continue;
10165 }
10166
10167 /* This will be triggered by a return. */
10168 if (GET_CODE (PATTERN (insn)) != SET)
10169 break;
10170
10171 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10172 ite = SET_SRC (PATTERN (insn));
10173
10174 if (GET_CODE (ite) != IF_THEN_ELSE)
10175 break;
10176
10177 cc = XEXP (XEXP (ite, 0), 0);
10178 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10179 break;
10180
10181 if (find_reg_note (insn, REG_DEAD, cc))
10182 return insn;
10183 break;
10184 }
10185
10186 return NULL_RTX;
10187 }
10188
10189 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10190 the semantics does not change. If NULL_RTX is passed as COND the
10191 function tries to find the conditional jump starting with INSN. */
10192 static void
10193 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10194 {
10195 rtx tmp = *op0;
10196
10197 if (cond == NULL_RTX)
10198 {
10199 rtx jump = find_cond_jump (NEXT_INSN (insn));
10200 jump = jump ? single_set (jump) : NULL_RTX;
10201
10202 if (jump == NULL_RTX)
10203 return;
10204
10205 cond = XEXP (XEXP (jump, 1), 0);
10206 }
10207
10208 *op0 = *op1;
10209 *op1 = tmp;
10210 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10211 }
10212
10213 /* On z10, instructions of the compare-and-branch family have the
10214 property to access the register occurring as second operand with
10215 its bits complemented. If such a compare is grouped with a second
10216 instruction that accesses the same register non-complemented, and
10217 if that register's value is delivered via a bypass, then the
10218 pipeline recycles, thereby causing significant performance decline.
10219 This function locates such situations and exchanges the two
10220 operands of the compare. The function return true whenever it
10221 added an insn. */
10222 static bool
10223 s390_z10_optimize_cmp (rtx insn)
10224 {
10225 rtx prev_insn, next_insn;
10226 bool insn_added_p = false;
10227 rtx cond, *op0, *op1;
10228
10229 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10230 {
10231 /* Handle compare and branch and branch on count
10232 instructions. */
10233 rtx pattern = single_set (insn);
10234
10235 if (!pattern
10236 || SET_DEST (pattern) != pc_rtx
10237 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10238 return false;
10239
10240 cond = XEXP (SET_SRC (pattern), 0);
10241 op0 = &XEXP (cond, 0);
10242 op1 = &XEXP (cond, 1);
10243 }
10244 else if (GET_CODE (PATTERN (insn)) == SET)
10245 {
10246 rtx src, dest;
10247
10248 /* Handle normal compare instructions. */
10249 src = SET_SRC (PATTERN (insn));
10250 dest = SET_DEST (PATTERN (insn));
10251
10252 if (!REG_P (dest)
10253 || !CC_REGNO_P (REGNO (dest))
10254 || GET_CODE (src) != COMPARE)
10255 return false;
10256
10257 /* s390_swap_cmp will try to find the conditional
10258 jump when passing NULL_RTX as condition. */
10259 cond = NULL_RTX;
10260 op0 = &XEXP (src, 0);
10261 op1 = &XEXP (src, 1);
10262 }
10263 else
10264 return false;
10265
10266 if (!REG_P (*op0) || !REG_P (*op1))
10267 return false;
10268
10269 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10270 return false;
10271
10272 /* Swap the COMPARE arguments and its mask if there is a
10273 conflicting access in the previous insn. */
10274 prev_insn = prev_active_insn (insn);
10275 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10276 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10277 s390_swap_cmp (cond, op0, op1, insn);
10278
10279 /* Check if there is a conflict with the next insn. If there
10280 was no conflict with the previous insn, then swap the
10281 COMPARE arguments and its mask. If we already swapped
10282 the operands, or if swapping them would cause a conflict
10283 with the previous insn, issue a NOP after the COMPARE in
10284 order to separate the two instuctions. */
10285 next_insn = next_active_insn (insn);
10286 if (next_insn != NULL_RTX && INSN_P (next_insn)
10287 && s390_non_addr_reg_read_p (*op1, next_insn))
10288 {
10289 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10290 && s390_non_addr_reg_read_p (*op0, prev_insn))
10291 {
10292 if (REGNO (*op1) == 0)
10293 emit_insn_after (gen_nop1 (), insn);
10294 else
10295 emit_insn_after (gen_nop (), insn);
10296 insn_added_p = true;
10297 }
10298 else
10299 s390_swap_cmp (cond, op0, op1, insn);
10300 }
10301 return insn_added_p;
10302 }
10303
10304 /* Perform machine-dependent processing. */
10305
10306 static void
10307 s390_reorg (void)
10308 {
10309 bool pool_overflow = false;
10310
10311 /* Make sure all splits have been performed; splits after
10312 machine_dependent_reorg might confuse insn length counts. */
10313 split_all_insns_noflow ();
10314
10315 /* Install the main literal pool and the associated base
10316 register load insns.
10317
10318 In addition, there are two problematic situations we need
10319 to correct:
10320
10321 - the literal pool might be > 4096 bytes in size, so that
10322 some of its elements cannot be directly accessed
10323
10324 - a branch target might be > 64K away from the branch, so that
10325 it is not possible to use a PC-relative instruction.
10326
10327 To fix those, we split the single literal pool into multiple
10328 pool chunks, reloading the pool base register at various
10329 points throughout the function to ensure it always points to
10330 the pool chunk the following code expects, and / or replace
10331 PC-relative branches by absolute branches.
10332
10333 However, the two problems are interdependent: splitting the
10334 literal pool can move a branch further away from its target,
10335 causing the 64K limit to overflow, and on the other hand,
10336 replacing a PC-relative branch by an absolute branch means
10337 we need to put the branch target address into the literal
10338 pool, possibly causing it to overflow.
10339
10340 So, we loop trying to fix up both problems until we manage
10341 to satisfy both conditions at the same time. Note that the
10342 loop is guaranteed to terminate as every pass of the loop
10343 strictly decreases the total number of PC-relative branches
10344 in the function. (This is not completely true as there
10345 might be branch-over-pool insns introduced by chunkify_start.
10346 Those never need to be split however.) */
10347
10348 for (;;)
10349 {
10350 struct constant_pool *pool = NULL;
10351
10352 /* Collect the literal pool. */
10353 if (!pool_overflow)
10354 {
10355 pool = s390_mainpool_start ();
10356 if (!pool)
10357 pool_overflow = true;
10358 }
10359
10360 /* If literal pool overflowed, start to chunkify it. */
10361 if (pool_overflow)
10362 pool = s390_chunkify_start ();
10363
10364 /* Split out-of-range branches. If this has created new
10365 literal pool entries, cancel current chunk list and
10366 recompute it. zSeries machines have large branch
10367 instructions, so we never need to split a branch. */
10368 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10369 {
10370 if (pool_overflow)
10371 s390_chunkify_cancel (pool);
10372 else
10373 s390_mainpool_cancel (pool);
10374
10375 continue;
10376 }
10377
10378 /* If we made it up to here, both conditions are satisfied.
10379 Finish up literal pool related changes. */
10380 if (pool_overflow)
10381 s390_chunkify_finish (pool);
10382 else
10383 s390_mainpool_finish (pool);
10384
10385 /* We're done splitting branches. */
10386 cfun->machine->split_branches_pending_p = false;
10387 break;
10388 }
10389
10390 /* Generate out-of-pool execute target insns. */
10391 if (TARGET_CPU_ZARCH)
10392 {
10393 rtx insn, label, target;
10394
10395 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10396 {
10397 label = s390_execute_label (insn);
10398 if (!label)
10399 continue;
10400
10401 gcc_assert (label != const0_rtx);
10402
10403 target = emit_label (XEXP (label, 0));
10404 INSN_ADDRESSES_NEW (target, -1);
10405
10406 target = emit_insn (s390_execute_target (insn));
10407 INSN_ADDRESSES_NEW (target, -1);
10408 }
10409 }
10410
10411 /* Try to optimize prologue and epilogue further. */
10412 s390_optimize_prologue ();
10413
10414 /* Walk over the insns and do some >=z10 specific changes. */
10415 if (s390_tune == PROCESSOR_2097_Z10
10416 || s390_tune == PROCESSOR_2817_Z196)
10417 {
10418 rtx insn;
10419 bool insn_added_p = false;
10420
10421 /* The insn lengths and addresses have to be up to date for the
10422 following manipulations. */
10423 shorten_branches (get_insns ());
10424
10425 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10426 {
10427 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10428 continue;
10429
10430 if (JUMP_P (insn))
10431 insn_added_p |= s390_fix_long_loop_prediction (insn);
10432
10433 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10434 || GET_CODE (PATTERN (insn)) == SET)
10435 && s390_tune == PROCESSOR_2097_Z10)
10436 insn_added_p |= s390_z10_optimize_cmp (insn);
10437 }
10438
10439 /* Adjust branches if we added new instructions. */
10440 if (insn_added_p)
10441 shorten_branches (get_insns ());
10442 }
10443 }
10444
10445 /* Return true if INSN is a fp load insn writing register REGNO. */
10446 static inline bool
10447 s390_fpload_toreg (rtx insn, unsigned int regno)
10448 {
10449 rtx set;
10450 enum attr_type flag = s390_safe_attr_type (insn);
10451
10452 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10453 return false;
10454
10455 set = single_set (insn);
10456
10457 if (set == NULL_RTX)
10458 return false;
10459
10460 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10461 return false;
10462
10463 if (REGNO (SET_DEST (set)) != regno)
10464 return false;
10465
10466 return true;
10467 }
10468
10469 /* This value describes the distance to be avoided between an
10470 aritmetic fp instruction and an fp load writing the same register.
10471 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10472 fine but the exact value has to be avoided. Otherwise the FP
10473 pipeline will throw an exception causing a major penalty. */
10474 #define Z10_EARLYLOAD_DISTANCE 7
10475
10476 /* Rearrange the ready list in order to avoid the situation described
10477 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10478 moved to the very end of the ready list. */
10479 static void
10480 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10481 {
10482 unsigned int regno;
10483 int nready = *nready_p;
10484 rtx tmp;
10485 int i;
10486 rtx insn;
10487 rtx set;
10488 enum attr_type flag;
10489 int distance;
10490
10491 /* Skip DISTANCE - 1 active insns. */
10492 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10493 distance > 0 && insn != NULL_RTX;
10494 distance--, insn = prev_active_insn (insn))
10495 if (CALL_P (insn) || JUMP_P (insn))
10496 return;
10497
10498 if (insn == NULL_RTX)
10499 return;
10500
10501 set = single_set (insn);
10502
10503 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10504 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10505 return;
10506
10507 flag = s390_safe_attr_type (insn);
10508
10509 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10510 return;
10511
10512 regno = REGNO (SET_DEST (set));
10513 i = nready - 1;
10514
10515 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10516 i--;
10517
10518 if (!i)
10519 return;
10520
10521 tmp = ready[i];
10522 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10523 ready[0] = tmp;
10524 }
10525
10526 /* This function is called via hook TARGET_SCHED_REORDER before
10527 issueing one insn from list READY which contains *NREADYP entries.
10528 For target z10 it reorders load instructions to avoid early load
10529 conflicts in the floating point pipeline */
10530 static int
10531 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10532 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10533 {
10534 if (s390_tune == PROCESSOR_2097_Z10)
10535 if (reload_completed && *nreadyp > 1)
10536 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10537
10538 return s390_issue_rate ();
10539 }
10540
10541 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10542 the scheduler has issued INSN. It stores the last issued insn into
10543 last_scheduled_insn in order to make it available for
10544 s390_sched_reorder. */
10545 static int
10546 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10547 int verbose ATTRIBUTE_UNUSED,
10548 rtx insn, int more)
10549 {
10550 last_scheduled_insn = insn;
10551
10552 if (GET_CODE (PATTERN (insn)) != USE
10553 && GET_CODE (PATTERN (insn)) != CLOBBER)
10554 return more - 1;
10555 else
10556 return more;
10557 }
10558
10559 static void
10560 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10561 int verbose ATTRIBUTE_UNUSED,
10562 int max_ready ATTRIBUTE_UNUSED)
10563 {
10564 last_scheduled_insn = NULL_RTX;
10565 }
10566
10567 /* This function checks the whole of insn X for memory references. The
10568 function always returns zero because the framework it is called
10569 from would stop recursively analyzing the insn upon a return value
10570 other than zero. The real result of this function is updating
10571 counter variable MEM_COUNT. */
10572 static int
10573 check_dpu (rtx *x, unsigned *mem_count)
10574 {
10575 if (*x != NULL_RTX && MEM_P (*x))
10576 (*mem_count)++;
10577 return 0;
10578 }
10579
10580 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10581 a new number struct loop *loop should be unrolled if tuned for cpus with
10582 a built-in stride prefetcher.
10583 The loop is analyzed for memory accesses by calling check_dpu for
10584 each rtx of the loop. Depending on the loop_depth and the amount of
10585 memory accesses a new number <=nunroll is returned to improve the
10586 behaviour of the hardware prefetch unit. */
10587 static unsigned
10588 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10589 {
10590 basic_block *bbs;
10591 rtx insn;
10592 unsigned i;
10593 unsigned mem_count = 0;
10594
10595 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10596 return nunroll;
10597
10598 /* Count the number of memory references within the loop body. */
10599 bbs = get_loop_body (loop);
10600 for (i = 0; i < loop->num_nodes; i++)
10601 {
10602 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10603 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10604 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10605 }
10606 free (bbs);
10607
10608 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10609 if (mem_count == 0)
10610 return nunroll;
10611
10612 switch (loop_depth(loop))
10613 {
10614 case 1:
10615 return MIN (nunroll, 28 / mem_count);
10616 case 2:
10617 return MIN (nunroll, 22 / mem_count);
10618 default:
10619 return MIN (nunroll, 16 / mem_count);
10620 }
10621 }
10622
10623 /* Initialize GCC target structure. */
10624
10625 #undef TARGET_ASM_ALIGNED_HI_OP
10626 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10627 #undef TARGET_ASM_ALIGNED_DI_OP
10628 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10629 #undef TARGET_ASM_INTEGER
10630 #define TARGET_ASM_INTEGER s390_assemble_integer
10631
10632 #undef TARGET_ASM_OPEN_PAREN
10633 #define TARGET_ASM_OPEN_PAREN ""
10634
10635 #undef TARGET_ASM_CLOSE_PAREN
10636 #define TARGET_ASM_CLOSE_PAREN ""
10637
10638 #undef TARGET_DEFAULT_TARGET_FLAGS
10639 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
10640
10641 #undef TARGET_HANDLE_OPTION
10642 #define TARGET_HANDLE_OPTION s390_handle_option
10643
10644 #undef TARGET_OPTION_OVERRIDE
10645 #define TARGET_OPTION_OVERRIDE s390_option_override
10646
10647 #undef TARGET_OPTION_OPTIMIZATION_TABLE
10648 #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table
10649
10650 #undef TARGET_OPTION_INIT_STRUCT
10651 #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct
10652
10653 #undef TARGET_ENCODE_SECTION_INFO
10654 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10655
10656 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10657 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10658
10659 #ifdef HAVE_AS_TLS
10660 #undef TARGET_HAVE_TLS
10661 #define TARGET_HAVE_TLS true
10662 #endif
10663 #undef TARGET_CANNOT_FORCE_CONST_MEM
10664 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10665
10666 #undef TARGET_DELEGITIMIZE_ADDRESS
10667 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10668
10669 #undef TARGET_LEGITIMIZE_ADDRESS
10670 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10671
10672 #undef TARGET_RETURN_IN_MEMORY
10673 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10674
10675 #undef TARGET_INIT_BUILTINS
10676 #define TARGET_INIT_BUILTINS s390_init_builtins
10677 #undef TARGET_EXPAND_BUILTIN
10678 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10679
10680 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10681 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10682
10683 #undef TARGET_ASM_OUTPUT_MI_THUNK
10684 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10685 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10686 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10687
10688 #undef TARGET_SCHED_ADJUST_PRIORITY
10689 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10690 #undef TARGET_SCHED_ISSUE_RATE
10691 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10692 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10693 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10694
10695 #undef TARGET_SCHED_VARIABLE_ISSUE
10696 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10697 #undef TARGET_SCHED_REORDER
10698 #define TARGET_SCHED_REORDER s390_sched_reorder
10699 #undef TARGET_SCHED_INIT
10700 #define TARGET_SCHED_INIT s390_sched_init
10701
10702 #undef TARGET_CANNOT_COPY_INSN_P
10703 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10704 #undef TARGET_RTX_COSTS
10705 #define TARGET_RTX_COSTS s390_rtx_costs
10706 #undef TARGET_ADDRESS_COST
10707 #define TARGET_ADDRESS_COST s390_address_cost
10708 #undef TARGET_REGISTER_MOVE_COST
10709 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10710 #undef TARGET_MEMORY_MOVE_COST
10711 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10712
10713 #undef TARGET_MACHINE_DEPENDENT_REORG
10714 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10715
10716 #undef TARGET_VALID_POINTER_MODE
10717 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10718
10719 #undef TARGET_BUILD_BUILTIN_VA_LIST
10720 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10721 #undef TARGET_EXPAND_BUILTIN_VA_START
10722 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10723 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10724 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10725
10726 #undef TARGET_PROMOTE_FUNCTION_MODE
10727 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10728 #undef TARGET_PASS_BY_REFERENCE
10729 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10730
10731 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10732 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10733 #undef TARGET_FUNCTION_ARG
10734 #define TARGET_FUNCTION_ARG s390_function_arg
10735 #undef TARGET_FUNCTION_ARG_ADVANCE
10736 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10737 #undef TARGET_FUNCTION_VALUE
10738 #define TARGET_FUNCTION_VALUE s390_function_value
10739 #undef TARGET_LIBCALL_VALUE
10740 #define TARGET_LIBCALL_VALUE s390_libcall_value
10741
10742 #undef TARGET_FIXED_CONDITION_CODE_REGS
10743 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10744
10745 #undef TARGET_CC_MODES_COMPATIBLE
10746 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10747
10748 #undef TARGET_INVALID_WITHIN_DOLOOP
10749 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10750
10751 #ifdef HAVE_AS_TLS
10752 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10753 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10754 #endif
10755
10756 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10757 #undef TARGET_MANGLE_TYPE
10758 #define TARGET_MANGLE_TYPE s390_mangle_type
10759 #endif
10760
10761 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10762 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10763
10764 #undef TARGET_PREFERRED_RELOAD_CLASS
10765 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10766
10767 #undef TARGET_SECONDARY_RELOAD
10768 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10769
10770 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10771 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10772
10773 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10774 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10775
10776 #undef TARGET_LEGITIMATE_ADDRESS_P
10777 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10778
10779 #undef TARGET_CAN_ELIMINATE
10780 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10781
10782 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10783 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10784
10785 #undef TARGET_LOOP_UNROLL_ADJUST
10786 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10787
10788 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10789 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10790 #undef TARGET_TRAMPOLINE_INIT
10791 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10792
10793 #undef TARGET_UNWIND_WORD_MODE
10794 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10795
10796 struct gcc_target targetm = TARGET_INITIALIZER;
10797
10798 #include "gt-s390.h"