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[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48 #include "debug.h"
49 #include "langhooks.h"
50 #include "optabs.h"
51 #include "gimple.h"
52 #include "df.h"
53 #include "params.h"
54 #include "cfgloop.h"
55 #include "opts.h"
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 static const
225 struct processor_costs z196_cost =
226 {
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
254 };
255
256 static const
257 struct processor_costs zEC12_cost =
258 {
259 COSTS_N_INSNS (7), /* M */
260 COSTS_N_INSNS (5), /* MGHI */
261 COSTS_N_INSNS (5), /* MH */
262 COSTS_N_INSNS (5), /* MHI */
263 COSTS_N_INSNS (7), /* ML */
264 COSTS_N_INSNS (7), /* MR */
265 COSTS_N_INSNS (6), /* MS */
266 COSTS_N_INSNS (8), /* MSG */
267 COSTS_N_INSNS (6), /* MSGF */
268 COSTS_N_INSNS (6), /* MSGFR */
269 COSTS_N_INSNS (8), /* MSGR */
270 COSTS_N_INSNS (6), /* MSR */
271 COSTS_N_INSNS (1) , /* multiplication in DFmode */
272 COSTS_N_INSNS (40), /* MXBR B+40 */
273 COSTS_N_INSNS (100), /* SQXBR B+100 */
274 COSTS_N_INSNS (42), /* SQDBR B+42 */
275 COSTS_N_INSNS (28), /* SQEBR B+28 */
276 COSTS_N_INSNS (1), /* MADBR B */
277 COSTS_N_INSNS (1), /* MAEBR B */
278 COSTS_N_INSNS (131), /* DXBR B+131 */
279 COSTS_N_INSNS (29), /* DDBR */
280 COSTS_N_INSNS (22), /* DEBR */
281 COSTS_N_INSNS (160), /* DLGR cracked */
282 COSTS_N_INSNS (160), /* DLR cracked */
283 COSTS_N_INSNS (160), /* DR expanded */
284 COSTS_N_INSNS (160), /* DSGFR cracked */
285 COSTS_N_INSNS (160), /* DSGR cracked */
286 };
287
288 extern int reload_completed;
289
290 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
291 static rtx last_scheduled_insn;
292
293 /* Structure used to hold the components of a S/390 memory
294 address. A legitimate address on S/390 is of the general
295 form
296 base + index + displacement
297 where any of the components is optional.
298
299 base and index are registers of the class ADDR_REGS,
300 displacement is an unsigned 12-bit immediate constant. */
301
302 struct s390_address
303 {
304 rtx base;
305 rtx indx;
306 rtx disp;
307 bool pointer;
308 bool literal_pool;
309 };
310
311 /* The following structure is embedded in the machine
312 specific part of struct function. */
313
314 struct GTY (()) s390_frame_layout
315 {
316 /* Offset within stack frame. */
317 HOST_WIDE_INT gprs_offset;
318 HOST_WIDE_INT f0_offset;
319 HOST_WIDE_INT f4_offset;
320 HOST_WIDE_INT f8_offset;
321 HOST_WIDE_INT backchain_offset;
322
323 /* Number of first and last gpr where slots in the register
324 save area are reserved for. */
325 int first_save_gpr_slot;
326 int last_save_gpr_slot;
327
328 /* Number of first and last gpr to be saved, restored. */
329 int first_save_gpr;
330 int first_restore_gpr;
331 int last_save_gpr;
332 int last_restore_gpr;
333
334 /* Bits standing for floating point registers. Set, if the
335 respective register has to be saved. Starting with reg 16 (f0)
336 at the rightmost bit.
337 Bit 15 - 8 7 6 5 4 3 2 1 0
338 fpr 15 - 8 7 5 3 1 6 4 2 0
339 reg 31 - 24 23 22 21 20 19 18 17 16 */
340 unsigned int fpr_bitmap;
341
342 /* Number of floating point registers f8-f15 which must be saved. */
343 int high_fprs;
344
345 /* Set if return address needs to be saved.
346 This flag is set by s390_return_addr_rtx if it could not use
347 the initial value of r14 and therefore depends on r14 saved
348 to the stack. */
349 bool save_return_addr_p;
350
351 /* Size of stack frame. */
352 HOST_WIDE_INT frame_size;
353 };
354
355 /* Define the structure for the machine field in struct function. */
356
357 struct GTY(()) machine_function
358 {
359 struct s390_frame_layout frame_layout;
360
361 /* Literal pool base register. */
362 rtx base_reg;
363
364 /* True if we may need to perform branch splitting. */
365 bool split_branches_pending_p;
366
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name;
369
370 bool has_landing_pad_p;
371 };
372
373 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
374
375 #define cfun_frame_layout (cfun->machine->frame_layout)
376 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
377 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
378 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
379 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
380 (1 << (BITNUM)))
381 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
382 (1 << (BITNUM))))
383
384 /* Number of GPRs and FPRs used for argument passing. */
385 #define GP_ARG_NUM_REG 5
386 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
387
388 /* A couple of shortcuts. */
389 #define CONST_OK_FOR_J(x) \
390 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
391 #define CONST_OK_FOR_K(x) \
392 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
393 #define CONST_OK_FOR_Os(x) \
394 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
395 #define CONST_OK_FOR_Op(x) \
396 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
397 #define CONST_OK_FOR_On(x) \
398 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
399
400 #define REGNO_PAIR_OK(REGNO, MODE) \
401 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
402
403 /* That's the read ahead of the dynamic branch prediction unit in
404 bytes on a z10 (or higher) CPU. */
405 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
406
407 /* Return the alignment for LABEL. We default to the -falign-labels
408 value except for the literal pool base label. */
409 int
410 s390_label_align (rtx label)
411 {
412 rtx prev_insn = prev_active_insn (label);
413
414 if (prev_insn == NULL_RTX)
415 goto old;
416
417 prev_insn = single_set (prev_insn);
418
419 if (prev_insn == NULL_RTX)
420 goto old;
421
422 prev_insn = SET_SRC (prev_insn);
423
424 /* Don't align literal pool base labels. */
425 if (GET_CODE (prev_insn) == UNSPEC
426 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
427 return 0;
428
429 old:
430 return align_labels_log;
431 }
432
433 static enum machine_mode
434 s390_libgcc_cmp_return_mode (void)
435 {
436 return TARGET_64BIT ? DImode : SImode;
437 }
438
439 static enum machine_mode
440 s390_libgcc_shift_count_mode (void)
441 {
442 return TARGET_64BIT ? DImode : SImode;
443 }
444
445 static enum machine_mode
446 s390_unwind_word_mode (void)
447 {
448 return TARGET_64BIT ? DImode : SImode;
449 }
450
451 /* Return true if the back end supports mode MODE. */
452 static bool
453 s390_scalar_mode_supported_p (enum machine_mode mode)
454 {
455 /* In contrast to the default implementation reject TImode constants on 31bit
456 TARGET_ZARCH for ABI compliance. */
457 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
458 return false;
459
460 if (DECIMAL_FLOAT_MODE_P (mode))
461 return default_decimal_float_supported_p ();
462
463 return default_scalar_mode_supported_p (mode);
464 }
465
466 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
467
468 void
469 s390_set_has_landing_pad_p (bool value)
470 {
471 cfun->machine->has_landing_pad_p = value;
472 }
473
474 /* If two condition code modes are compatible, return a condition code
475 mode which is compatible with both. Otherwise, return
476 VOIDmode. */
477
478 static enum machine_mode
479 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
480 {
481 if (m1 == m2)
482 return m1;
483
484 switch (m1)
485 {
486 case CCZmode:
487 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
488 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
489 return m2;
490 return VOIDmode;
491
492 case CCSmode:
493 case CCUmode:
494 case CCTmode:
495 case CCSRmode:
496 case CCURmode:
497 case CCZ1mode:
498 if (m2 == CCZmode)
499 return m1;
500
501 return VOIDmode;
502
503 default:
504 return VOIDmode;
505 }
506 return VOIDmode;
507 }
508
509 /* Return true if SET either doesn't set the CC register, or else
510 the source and destination have matching CC modes and that
511 CC mode is at least as constrained as REQ_MODE. */
512
513 static bool
514 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
515 {
516 enum machine_mode set_mode;
517
518 gcc_assert (GET_CODE (set) == SET);
519
520 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
521 return 1;
522
523 set_mode = GET_MODE (SET_DEST (set));
524 switch (set_mode)
525 {
526 case CCSmode:
527 case CCSRmode:
528 case CCUmode:
529 case CCURmode:
530 case CCLmode:
531 case CCL1mode:
532 case CCL2mode:
533 case CCL3mode:
534 case CCT1mode:
535 case CCT2mode:
536 case CCT3mode:
537 if (req_mode != set_mode)
538 return 0;
539 break;
540
541 case CCZmode:
542 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
543 && req_mode != CCSRmode && req_mode != CCURmode)
544 return 0;
545 break;
546
547 case CCAPmode:
548 case CCANmode:
549 if (req_mode != CCAmode)
550 return 0;
551 break;
552
553 default:
554 gcc_unreachable ();
555 }
556
557 return (GET_MODE (SET_SRC (set)) == set_mode);
558 }
559
560 /* Return true if every SET in INSN that sets the CC register
561 has source and destination with matching CC modes and that
562 CC mode is at least as constrained as REQ_MODE.
563 If REQ_MODE is VOIDmode, always return false. */
564
565 bool
566 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
567 {
568 int i;
569
570 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
571 if (req_mode == VOIDmode)
572 return false;
573
574 if (GET_CODE (PATTERN (insn)) == SET)
575 return s390_match_ccmode_set (PATTERN (insn), req_mode);
576
577 if (GET_CODE (PATTERN (insn)) == PARALLEL)
578 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
579 {
580 rtx set = XVECEXP (PATTERN (insn), 0, i);
581 if (GET_CODE (set) == SET)
582 if (!s390_match_ccmode_set (set, req_mode))
583 return false;
584 }
585
586 return true;
587 }
588
589 /* If a test-under-mask instruction can be used to implement
590 (compare (and ... OP1) OP2), return the CC mode required
591 to do that. Otherwise, return VOIDmode.
592 MIXED is true if the instruction can distinguish between
593 CC1 and CC2 for mixed selected bits (TMxx), it is false
594 if the instruction cannot (TM). */
595
596 enum machine_mode
597 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
598 {
599 int bit0, bit1;
600
601 /* ??? Fixme: should work on CONST_DOUBLE as well. */
602 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
603 return VOIDmode;
604
605 /* Selected bits all zero: CC0.
606 e.g.: int a; if ((a & (16 + 128)) == 0) */
607 if (INTVAL (op2) == 0)
608 return CCTmode;
609
610 /* Selected bits all one: CC3.
611 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
612 if (INTVAL (op2) == INTVAL (op1))
613 return CCT3mode;
614
615 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
616 int a;
617 if ((a & (16 + 128)) == 16) -> CCT1
618 if ((a & (16 + 128)) == 128) -> CCT2 */
619 if (mixed)
620 {
621 bit1 = exact_log2 (INTVAL (op2));
622 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
623 if (bit0 != -1 && bit1 != -1)
624 return bit0 > bit1 ? CCT1mode : CCT2mode;
625 }
626
627 return VOIDmode;
628 }
629
630 /* Given a comparison code OP (EQ, NE, etc.) and the operands
631 OP0 and OP1 of a COMPARE, return the mode to be used for the
632 comparison. */
633
634 enum machine_mode
635 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
636 {
637 switch (code)
638 {
639 case EQ:
640 case NE:
641 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
642 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
643 return CCAPmode;
644 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
645 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
646 return CCAPmode;
647 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
648 || GET_CODE (op1) == NEG)
649 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
650 return CCLmode;
651
652 if (GET_CODE (op0) == AND)
653 {
654 /* Check whether we can potentially do it via TM. */
655 enum machine_mode ccmode;
656 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
657 if (ccmode != VOIDmode)
658 {
659 /* Relax CCTmode to CCZmode to allow fall-back to AND
660 if that turns out to be beneficial. */
661 return ccmode == CCTmode ? CCZmode : ccmode;
662 }
663 }
664
665 if (register_operand (op0, HImode)
666 && GET_CODE (op1) == CONST_INT
667 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
668 return CCT3mode;
669 if (register_operand (op0, QImode)
670 && GET_CODE (op1) == CONST_INT
671 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
672 return CCT3mode;
673
674 return CCZmode;
675
676 case LE:
677 case LT:
678 case GE:
679 case GT:
680 /* The only overflow condition of NEG and ABS happens when
681 -INT_MAX is used as parameter, which stays negative. So
682 we have an overflow from a positive value to a negative.
683 Using CCAP mode the resulting cc can be used for comparisons. */
684 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
685 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
686 return CCAPmode;
687
688 /* If constants are involved in an add instruction it is possible to use
689 the resulting cc for comparisons with zero. Knowing the sign of the
690 constant the overflow behavior gets predictable. e.g.:
691 int a, b; if ((b = a + c) > 0)
692 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
693 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
694 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
695 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
696 /* Avoid INT32_MIN on 32 bit. */
697 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
698 {
699 if (INTVAL (XEXP((op0), 1)) < 0)
700 return CCANmode;
701 else
702 return CCAPmode;
703 }
704 /* Fall through. */
705 case UNORDERED:
706 case ORDERED:
707 case UNEQ:
708 case UNLE:
709 case UNLT:
710 case UNGE:
711 case UNGT:
712 case LTGT:
713 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
714 && GET_CODE (op1) != CONST_INT)
715 return CCSRmode;
716 return CCSmode;
717
718 case LTU:
719 case GEU:
720 if (GET_CODE (op0) == PLUS
721 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
722 return CCL1mode;
723
724 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
725 && GET_CODE (op1) != CONST_INT)
726 return CCURmode;
727 return CCUmode;
728
729 case LEU:
730 case GTU:
731 if (GET_CODE (op0) == MINUS
732 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
733 return CCL2mode;
734
735 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
736 && GET_CODE (op1) != CONST_INT)
737 return CCURmode;
738 return CCUmode;
739
740 default:
741 gcc_unreachable ();
742 }
743 }
744
745 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
746 that we can implement more efficiently. */
747
748 static void
749 s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
750 bool op0_preserve_value)
751 {
752 if (op0_preserve_value)
753 return;
754
755 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
756 if ((*code == EQ || *code == NE)
757 && *op1 == const0_rtx
758 && GET_CODE (*op0) == ZERO_EXTRACT
759 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
760 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
761 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
762 {
763 rtx inner = XEXP (*op0, 0);
764 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
765 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
766 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
767
768 if (len > 0 && len < modesize
769 && pos >= 0 && pos + len <= modesize
770 && modesize <= HOST_BITS_PER_WIDE_INT)
771 {
772 unsigned HOST_WIDE_INT block;
773 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
774 block <<= modesize - pos - len;
775
776 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
777 gen_int_mode (block, GET_MODE (inner)));
778 }
779 }
780
781 /* Narrow AND of memory against immediate to enable TM. */
782 if ((*code == EQ || *code == NE)
783 && *op1 == const0_rtx
784 && GET_CODE (*op0) == AND
785 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
786 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
787 {
788 rtx inner = XEXP (*op0, 0);
789 rtx mask = XEXP (*op0, 1);
790
791 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
792 if (GET_CODE (inner) == SUBREG
793 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
794 && (GET_MODE_SIZE (GET_MODE (inner))
795 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
796 && ((INTVAL (mask)
797 & GET_MODE_MASK (GET_MODE (inner))
798 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
799 == 0))
800 inner = SUBREG_REG (inner);
801
802 /* Do not change volatile MEMs. */
803 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
804 {
805 int part = s390_single_part (XEXP (*op0, 1),
806 GET_MODE (inner), QImode, 0);
807 if (part >= 0)
808 {
809 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
810 inner = adjust_address_nv (inner, QImode, part);
811 *op0 = gen_rtx_AND (QImode, inner, mask);
812 }
813 }
814 }
815
816 /* Narrow comparisons against 0xffff to HImode if possible. */
817 if ((*code == EQ || *code == NE)
818 && GET_CODE (*op1) == CONST_INT
819 && INTVAL (*op1) == 0xffff
820 && SCALAR_INT_MODE_P (GET_MODE (*op0))
821 && (nonzero_bits (*op0, GET_MODE (*op0))
822 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
823 {
824 *op0 = gen_lowpart (HImode, *op0);
825 *op1 = constm1_rtx;
826 }
827
828 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
829 if (GET_CODE (*op0) == UNSPEC
830 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
831 && XVECLEN (*op0, 0) == 1
832 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
833 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
834 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
835 && *op1 == const0_rtx)
836 {
837 enum rtx_code new_code = UNKNOWN;
838 switch (*code)
839 {
840 case EQ: new_code = EQ; break;
841 case NE: new_code = NE; break;
842 case LT: new_code = GTU; break;
843 case GT: new_code = LTU; break;
844 case LE: new_code = GEU; break;
845 case GE: new_code = LEU; break;
846 default: break;
847 }
848
849 if (new_code != UNKNOWN)
850 {
851 *op0 = XVECEXP (*op0, 0, 0);
852 *code = new_code;
853 }
854 }
855
856 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
857 if (GET_CODE (*op0) == UNSPEC
858 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
859 && XVECLEN (*op0, 0) == 1
860 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
861 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
862 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
863 && *op1 == const0_rtx)
864 {
865 enum rtx_code new_code = UNKNOWN;
866 switch (*code)
867 {
868 case EQ: new_code = EQ; break;
869 case NE: new_code = NE; break;
870 default: break;
871 }
872
873 if (new_code != UNKNOWN)
874 {
875 *op0 = XVECEXP (*op0, 0, 0);
876 *code = new_code;
877 }
878 }
879
880 /* Simplify cascaded EQ, NE with const0_rtx. */
881 if ((*code == NE || *code == EQ)
882 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
883 && GET_MODE (*op0) == SImode
884 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
885 && REG_P (XEXP (*op0, 0))
886 && XEXP (*op0, 1) == const0_rtx
887 && *op1 == const0_rtx)
888 {
889 if ((*code == EQ && GET_CODE (*op0) == NE)
890 || (*code == NE && GET_CODE (*op0) == EQ))
891 *code = EQ;
892 else
893 *code = NE;
894 *op0 = XEXP (*op0, 0);
895 }
896
897 /* Prefer register over memory as first operand. */
898 if (MEM_P (*op0) && REG_P (*op1))
899 {
900 rtx tem = *op0; *op0 = *op1; *op1 = tem;
901 *code = (int)swap_condition ((enum rtx_code)*code);
902 }
903 }
904
905 /* Emit a compare instruction suitable to implement the comparison
906 OP0 CODE OP1. Return the correct condition RTL to be placed in
907 the IF_THEN_ELSE of the conditional branch testing the result. */
908
909 rtx
910 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
911 {
912 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
913 rtx cc;
914
915 /* Do not output a redundant compare instruction if a compare_and_swap
916 pattern already computed the result and the machine modes are compatible. */
917 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
918 {
919 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
920 == GET_MODE (op0));
921 cc = op0;
922 }
923 else
924 {
925 cc = gen_rtx_REG (mode, CC_REGNUM);
926 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
927 }
928
929 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
930 }
931
932 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
933 matches CMP.
934 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
935 conditional branch testing the result. */
936
937 static rtx
938 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
939 rtx cmp, rtx new_rtx)
940 {
941 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
942 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
943 const0_rtx);
944 }
945
946 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
947 unconditional jump, else a conditional jump under condition COND. */
948
949 void
950 s390_emit_jump (rtx target, rtx cond)
951 {
952 rtx insn;
953
954 target = gen_rtx_LABEL_REF (VOIDmode, target);
955 if (cond)
956 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
957
958 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
959 emit_jump_insn (insn);
960 }
961
962 /* Return branch condition mask to implement a branch
963 specified by CODE. Return -1 for invalid comparisons. */
964
965 int
966 s390_branch_condition_mask (rtx code)
967 {
968 const int CC0 = 1 << 3;
969 const int CC1 = 1 << 2;
970 const int CC2 = 1 << 1;
971 const int CC3 = 1 << 0;
972
973 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
974 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
975 gcc_assert (XEXP (code, 1) == const0_rtx);
976
977 switch (GET_MODE (XEXP (code, 0)))
978 {
979 case CCZmode:
980 case CCZ1mode:
981 switch (GET_CODE (code))
982 {
983 case EQ: return CC0;
984 case NE: return CC1 | CC2 | CC3;
985 default: return -1;
986 }
987 break;
988
989 case CCT1mode:
990 switch (GET_CODE (code))
991 {
992 case EQ: return CC1;
993 case NE: return CC0 | CC2 | CC3;
994 default: return -1;
995 }
996 break;
997
998 case CCT2mode:
999 switch (GET_CODE (code))
1000 {
1001 case EQ: return CC2;
1002 case NE: return CC0 | CC1 | CC3;
1003 default: return -1;
1004 }
1005 break;
1006
1007 case CCT3mode:
1008 switch (GET_CODE (code))
1009 {
1010 case EQ: return CC3;
1011 case NE: return CC0 | CC1 | CC2;
1012 default: return -1;
1013 }
1014 break;
1015
1016 case CCLmode:
1017 switch (GET_CODE (code))
1018 {
1019 case EQ: return CC0 | CC2;
1020 case NE: return CC1 | CC3;
1021 default: return -1;
1022 }
1023 break;
1024
1025 case CCL1mode:
1026 switch (GET_CODE (code))
1027 {
1028 case LTU: return CC2 | CC3; /* carry */
1029 case GEU: return CC0 | CC1; /* no carry */
1030 default: return -1;
1031 }
1032 break;
1033
1034 case CCL2mode:
1035 switch (GET_CODE (code))
1036 {
1037 case GTU: return CC0 | CC1; /* borrow */
1038 case LEU: return CC2 | CC3; /* no borrow */
1039 default: return -1;
1040 }
1041 break;
1042
1043 case CCL3mode:
1044 switch (GET_CODE (code))
1045 {
1046 case EQ: return CC0 | CC2;
1047 case NE: return CC1 | CC3;
1048 case LTU: return CC1;
1049 case GTU: return CC3;
1050 case LEU: return CC1 | CC2;
1051 case GEU: return CC2 | CC3;
1052 default: return -1;
1053 }
1054
1055 case CCUmode:
1056 switch (GET_CODE (code))
1057 {
1058 case EQ: return CC0;
1059 case NE: return CC1 | CC2 | CC3;
1060 case LTU: return CC1;
1061 case GTU: return CC2;
1062 case LEU: return CC0 | CC1;
1063 case GEU: return CC0 | CC2;
1064 default: return -1;
1065 }
1066 break;
1067
1068 case CCURmode:
1069 switch (GET_CODE (code))
1070 {
1071 case EQ: return CC0;
1072 case NE: return CC2 | CC1 | CC3;
1073 case LTU: return CC2;
1074 case GTU: return CC1;
1075 case LEU: return CC0 | CC2;
1076 case GEU: return CC0 | CC1;
1077 default: return -1;
1078 }
1079 break;
1080
1081 case CCAPmode:
1082 switch (GET_CODE (code))
1083 {
1084 case EQ: return CC0;
1085 case NE: return CC1 | CC2 | CC3;
1086 case LT: return CC1 | CC3;
1087 case GT: return CC2;
1088 case LE: return CC0 | CC1 | CC3;
1089 case GE: return CC0 | CC2;
1090 default: return -1;
1091 }
1092 break;
1093
1094 case CCANmode:
1095 switch (GET_CODE (code))
1096 {
1097 case EQ: return CC0;
1098 case NE: return CC1 | CC2 | CC3;
1099 case LT: return CC1;
1100 case GT: return CC2 | CC3;
1101 case LE: return CC0 | CC1;
1102 case GE: return CC0 | CC2 | CC3;
1103 default: return -1;
1104 }
1105 break;
1106
1107 case CCSmode:
1108 switch (GET_CODE (code))
1109 {
1110 case EQ: return CC0;
1111 case NE: return CC1 | CC2 | CC3;
1112 case LT: return CC1;
1113 case GT: return CC2;
1114 case LE: return CC0 | CC1;
1115 case GE: return CC0 | CC2;
1116 case UNORDERED: return CC3;
1117 case ORDERED: return CC0 | CC1 | CC2;
1118 case UNEQ: return CC0 | CC3;
1119 case UNLT: return CC1 | CC3;
1120 case UNGT: return CC2 | CC3;
1121 case UNLE: return CC0 | CC1 | CC3;
1122 case UNGE: return CC0 | CC2 | CC3;
1123 case LTGT: return CC1 | CC2;
1124 default: return -1;
1125 }
1126 break;
1127
1128 case CCSRmode:
1129 switch (GET_CODE (code))
1130 {
1131 case EQ: return CC0;
1132 case NE: return CC2 | CC1 | CC3;
1133 case LT: return CC2;
1134 case GT: return CC1;
1135 case LE: return CC0 | CC2;
1136 case GE: return CC0 | CC1;
1137 case UNORDERED: return CC3;
1138 case ORDERED: return CC0 | CC2 | CC1;
1139 case UNEQ: return CC0 | CC3;
1140 case UNLT: return CC2 | CC3;
1141 case UNGT: return CC1 | CC3;
1142 case UNLE: return CC0 | CC2 | CC3;
1143 case UNGE: return CC0 | CC1 | CC3;
1144 case LTGT: return CC2 | CC1;
1145 default: return -1;
1146 }
1147 break;
1148
1149 default:
1150 return -1;
1151 }
1152 }
1153
1154
1155 /* Return branch condition mask to implement a compare and branch
1156 specified by CODE. Return -1 for invalid comparisons. */
1157
1158 int
1159 s390_compare_and_branch_condition_mask (rtx code)
1160 {
1161 const int CC0 = 1 << 3;
1162 const int CC1 = 1 << 2;
1163 const int CC2 = 1 << 1;
1164
1165 switch (GET_CODE (code))
1166 {
1167 case EQ:
1168 return CC0;
1169 case NE:
1170 return CC1 | CC2;
1171 case LT:
1172 case LTU:
1173 return CC1;
1174 case GT:
1175 case GTU:
1176 return CC2;
1177 case LE:
1178 case LEU:
1179 return CC0 | CC1;
1180 case GE:
1181 case GEU:
1182 return CC0 | CC2;
1183 default:
1184 gcc_unreachable ();
1185 }
1186 return -1;
1187 }
1188
1189 /* If INV is false, return assembler mnemonic string to implement
1190 a branch specified by CODE. If INV is true, return mnemonic
1191 for the corresponding inverted branch. */
1192
1193 static const char *
1194 s390_branch_condition_mnemonic (rtx code, int inv)
1195 {
1196 int mask;
1197
1198 static const char *const mnemonic[16] =
1199 {
1200 NULL, "o", "h", "nle",
1201 "l", "nhe", "lh", "ne",
1202 "e", "nlh", "he", "nl",
1203 "le", "nh", "no", NULL
1204 };
1205
1206 if (GET_CODE (XEXP (code, 0)) == REG
1207 && REGNO (XEXP (code, 0)) == CC_REGNUM
1208 && XEXP (code, 1) == const0_rtx)
1209 mask = s390_branch_condition_mask (code);
1210 else
1211 mask = s390_compare_and_branch_condition_mask (code);
1212
1213 gcc_assert (mask >= 0);
1214
1215 if (inv)
1216 mask ^= 15;
1217
1218 gcc_assert (mask >= 1 && mask <= 14);
1219
1220 return mnemonic[mask];
1221 }
1222
1223 /* Return the part of op which has a value different from def.
1224 The size of the part is determined by mode.
1225 Use this function only if you already know that op really
1226 contains such a part. */
1227
1228 unsigned HOST_WIDE_INT
1229 s390_extract_part (rtx op, enum machine_mode mode, int def)
1230 {
1231 unsigned HOST_WIDE_INT value = 0;
1232 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1233 int part_bits = GET_MODE_BITSIZE (mode);
1234 unsigned HOST_WIDE_INT part_mask
1235 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1236 int i;
1237
1238 for (i = 0; i < max_parts; i++)
1239 {
1240 if (i == 0)
1241 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1242 else
1243 value >>= part_bits;
1244
1245 if ((value & part_mask) != (def & part_mask))
1246 return value & part_mask;
1247 }
1248
1249 gcc_unreachable ();
1250 }
1251
1252 /* If OP is an integer constant of mode MODE with exactly one
1253 part of mode PART_MODE unequal to DEF, return the number of that
1254 part. Otherwise, return -1. */
1255
1256 int
1257 s390_single_part (rtx op,
1258 enum machine_mode mode,
1259 enum machine_mode part_mode,
1260 int def)
1261 {
1262 unsigned HOST_WIDE_INT value = 0;
1263 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1264 unsigned HOST_WIDE_INT part_mask
1265 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1266 int i, part = -1;
1267
1268 if (GET_CODE (op) != CONST_INT)
1269 return -1;
1270
1271 for (i = 0; i < n_parts; i++)
1272 {
1273 if (i == 0)
1274 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1275 else
1276 value >>= GET_MODE_BITSIZE (part_mode);
1277
1278 if ((value & part_mask) != (def & part_mask))
1279 {
1280 if (part != -1)
1281 return -1;
1282 else
1283 part = i;
1284 }
1285 }
1286 return part == -1 ? -1 : n_parts - 1 - part;
1287 }
1288
1289 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1290 bits and no other bits are set in IN. POS and LENGTH can be used
1291 to obtain the start position and the length of the bitfield.
1292
1293 POS gives the position of the first bit of the bitfield counting
1294 from the lowest order bit starting with zero. In order to use this
1295 value for S/390 instructions this has to be converted to "bits big
1296 endian" style. */
1297
1298 bool
1299 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1300 int *pos, int *length)
1301 {
1302 int tmp_pos = 0;
1303 int tmp_length = 0;
1304 int i;
1305 unsigned HOST_WIDE_INT mask = 1ULL;
1306 bool contiguous = false;
1307
1308 for (i = 0; i < size; mask <<= 1, i++)
1309 {
1310 if (contiguous)
1311 {
1312 if (mask & in)
1313 tmp_length++;
1314 else
1315 break;
1316 }
1317 else
1318 {
1319 if (mask & in)
1320 {
1321 contiguous = true;
1322 tmp_length++;
1323 }
1324 else
1325 tmp_pos++;
1326 }
1327 }
1328
1329 if (!tmp_length)
1330 return false;
1331
1332 /* Calculate a mask for all bits beyond the contiguous bits. */
1333 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1334
1335 if (mask & in)
1336 return false;
1337
1338 if (tmp_length + tmp_pos - 1 > size)
1339 return false;
1340
1341 if (length)
1342 *length = tmp_length;
1343
1344 if (pos)
1345 *pos = tmp_pos;
1346
1347 return true;
1348 }
1349
1350 /* Check whether we can (and want to) split a double-word
1351 move in mode MODE from SRC to DST into two single-word
1352 moves, moving the subword FIRST_SUBWORD first. */
1353
1354 bool
1355 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1356 {
1357 /* Floating point registers cannot be split. */
1358 if (FP_REG_P (src) || FP_REG_P (dst))
1359 return false;
1360
1361 /* We don't need to split if operands are directly accessible. */
1362 if (s_operand (src, mode) || s_operand (dst, mode))
1363 return false;
1364
1365 /* Non-offsettable memory references cannot be split. */
1366 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1367 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1368 return false;
1369
1370 /* Moving the first subword must not clobber a register
1371 needed to move the second subword. */
1372 if (register_operand (dst, mode))
1373 {
1374 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1375 if (reg_overlap_mentioned_p (subreg, src))
1376 return false;
1377 }
1378
1379 return true;
1380 }
1381
1382 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1383 and [MEM2, MEM2 + SIZE] do overlap and false
1384 otherwise. */
1385
1386 bool
1387 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1388 {
1389 rtx addr1, addr2, addr_delta;
1390 HOST_WIDE_INT delta;
1391
1392 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1393 return true;
1394
1395 if (size == 0)
1396 return false;
1397
1398 addr1 = XEXP (mem1, 0);
1399 addr2 = XEXP (mem2, 0);
1400
1401 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1402
1403 /* This overlapping check is used by peepholes merging memory block operations.
1404 Overlapping operations would otherwise be recognized by the S/390 hardware
1405 and would fall back to a slower implementation. Allowing overlapping
1406 operations would lead to slow code but not to wrong code. Therefore we are
1407 somewhat optimistic if we cannot prove that the memory blocks are
1408 overlapping.
1409 That's why we return false here although this may accept operations on
1410 overlapping memory areas. */
1411 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1412 return false;
1413
1414 delta = INTVAL (addr_delta);
1415
1416 if (delta == 0
1417 || (delta > 0 && delta < size)
1418 || (delta < 0 && -delta < size))
1419 return true;
1420
1421 return false;
1422 }
1423
1424 /* Check whether the address of memory reference MEM2 equals exactly
1425 the address of memory reference MEM1 plus DELTA. Return true if
1426 we can prove this to be the case, false otherwise. */
1427
1428 bool
1429 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1430 {
1431 rtx addr1, addr2, addr_delta;
1432
1433 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1434 return false;
1435
1436 addr1 = XEXP (mem1, 0);
1437 addr2 = XEXP (mem2, 0);
1438
1439 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1440 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1441 return false;
1442
1443 return true;
1444 }
1445
1446 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1447
1448 void
1449 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1450 rtx *operands)
1451 {
1452 enum machine_mode wmode = mode;
1453 rtx dst = operands[0];
1454 rtx src1 = operands[1];
1455 rtx src2 = operands[2];
1456 rtx op, clob, tem;
1457
1458 /* If we cannot handle the operation directly, use a temp register. */
1459 if (!s390_logical_operator_ok_p (operands))
1460 dst = gen_reg_rtx (mode);
1461
1462 /* QImode and HImode patterns make sense only if we have a destination
1463 in memory. Otherwise perform the operation in SImode. */
1464 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1465 wmode = SImode;
1466
1467 /* Widen operands if required. */
1468 if (mode != wmode)
1469 {
1470 if (GET_CODE (dst) == SUBREG
1471 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1472 dst = tem;
1473 else if (REG_P (dst))
1474 dst = gen_rtx_SUBREG (wmode, dst, 0);
1475 else
1476 dst = gen_reg_rtx (wmode);
1477
1478 if (GET_CODE (src1) == SUBREG
1479 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1480 src1 = tem;
1481 else if (GET_MODE (src1) != VOIDmode)
1482 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1483
1484 if (GET_CODE (src2) == SUBREG
1485 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1486 src2 = tem;
1487 else if (GET_MODE (src2) != VOIDmode)
1488 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1489 }
1490
1491 /* Emit the instruction. */
1492 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1493 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1494 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1495
1496 /* Fix up the destination if needed. */
1497 if (dst != operands[0])
1498 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1499 }
1500
1501 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1502
1503 bool
1504 s390_logical_operator_ok_p (rtx *operands)
1505 {
1506 /* If the destination operand is in memory, it needs to coincide
1507 with one of the source operands. After reload, it has to be
1508 the first source operand. */
1509 if (GET_CODE (operands[0]) == MEM)
1510 return rtx_equal_p (operands[0], operands[1])
1511 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1512
1513 return true;
1514 }
1515
1516 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1517 operand IMMOP to switch from SS to SI type instructions. */
1518
1519 void
1520 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1521 {
1522 int def = code == AND ? -1 : 0;
1523 HOST_WIDE_INT mask;
1524 int part;
1525
1526 gcc_assert (GET_CODE (*memop) == MEM);
1527 gcc_assert (!MEM_VOLATILE_P (*memop));
1528
1529 mask = s390_extract_part (*immop, QImode, def);
1530 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1531 gcc_assert (part >= 0);
1532
1533 *memop = adjust_address (*memop, QImode, part);
1534 *immop = gen_int_mode (mask, QImode);
1535 }
1536
1537
1538 /* How to allocate a 'struct machine_function'. */
1539
1540 static struct machine_function *
1541 s390_init_machine_status (void)
1542 {
1543 return ggc_alloc_cleared_machine_function ();
1544 }
1545
1546 static void
1547 s390_option_override (void)
1548 {
1549 /* Set up function hooks. */
1550 init_machine_status = s390_init_machine_status;
1551
1552 /* Architecture mode defaults according to ABI. */
1553 if (!(target_flags_explicit & MASK_ZARCH))
1554 {
1555 if (TARGET_64BIT)
1556 target_flags |= MASK_ZARCH;
1557 else
1558 target_flags &= ~MASK_ZARCH;
1559 }
1560
1561 /* Set the march default in case it hasn't been specified on
1562 cmdline. */
1563 if (s390_arch == PROCESSOR_max)
1564 {
1565 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1566 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1567 s390_arch_flags = processor_flags_table[(int)s390_arch];
1568 }
1569
1570 /* Determine processor to tune for. */
1571 if (s390_tune == PROCESSOR_max)
1572 {
1573 s390_tune = s390_arch;
1574 s390_tune_flags = s390_arch_flags;
1575 }
1576
1577 /* Sanity checks. */
1578 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1579 error ("z/Architecture mode not supported on %s", s390_arch_string);
1580 if (TARGET_64BIT && !TARGET_ZARCH)
1581 error ("64-bit ABI not supported in ESA/390 mode");
1582
1583 /* Use hardware DFP if available and not explicitly disabled by
1584 user. E.g. with -m31 -march=z10 -mzarch */
1585 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1586 target_flags |= MASK_HARD_DFP;
1587
1588 if (TARGET_HARD_DFP && !TARGET_DFP)
1589 {
1590 if (target_flags_explicit & MASK_HARD_DFP)
1591 {
1592 if (!TARGET_CPU_DFP)
1593 error ("hardware decimal floating point instructions"
1594 " not available on %s", s390_arch_string);
1595 if (!TARGET_ZARCH)
1596 error ("hardware decimal floating point instructions"
1597 " not available in ESA/390 mode");
1598 }
1599 else
1600 target_flags &= ~MASK_HARD_DFP;
1601 }
1602
1603 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1604 {
1605 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1606 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1607
1608 target_flags &= ~MASK_HARD_DFP;
1609 }
1610
1611 /* Set processor cost function. */
1612 switch (s390_tune)
1613 {
1614 case PROCESSOR_2084_Z990:
1615 s390_cost = &z990_cost;
1616 break;
1617 case PROCESSOR_2094_Z9_109:
1618 s390_cost = &z9_109_cost;
1619 break;
1620 case PROCESSOR_2097_Z10:
1621 s390_cost = &z10_cost;
1622 break;
1623 case PROCESSOR_2817_Z196:
1624 s390_cost = &z196_cost;
1625 break;
1626 case PROCESSOR_2827_ZEC12:
1627 s390_cost = &zEC12_cost;
1628 break;
1629 default:
1630 s390_cost = &z900_cost;
1631 }
1632
1633 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1634 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1635 "in combination");
1636
1637 if (s390_stack_size)
1638 {
1639 if (s390_stack_guard >= s390_stack_size)
1640 error ("stack size must be greater than the stack guard value");
1641 else if (s390_stack_size > 1 << 16)
1642 error ("stack size must not be greater than 64k");
1643 }
1644 else if (s390_stack_guard)
1645 error ("-mstack-guard implies use of -mstack-size");
1646
1647 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1648 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1649 target_flags |= MASK_LONG_DOUBLE_128;
1650 #endif
1651
1652 if (s390_tune == PROCESSOR_2097_Z10
1653 || s390_tune == PROCESSOR_2817_Z196
1654 || s390_tune == PROCESSOR_2827_ZEC12)
1655 {
1656 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1657 global_options.x_param_values,
1658 global_options_set.x_param_values);
1659 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1660 global_options.x_param_values,
1661 global_options_set.x_param_values);
1662 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1663 global_options.x_param_values,
1664 global_options_set.x_param_values);
1665 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1666 global_options.x_param_values,
1667 global_options_set.x_param_values);
1668 }
1669
1670 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1671 global_options.x_param_values,
1672 global_options_set.x_param_values);
1673 /* values for loop prefetching */
1674 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1675 global_options.x_param_values,
1676 global_options_set.x_param_values);
1677 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1678 global_options.x_param_values,
1679 global_options_set.x_param_values);
1680 /* s390 has more than 2 levels and the size is much larger. Since
1681 we are always running virtualized assume that we only get a small
1682 part of the caches above l1. */
1683 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1684 global_options.x_param_values,
1685 global_options_set.x_param_values);
1686 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1687 global_options.x_param_values,
1688 global_options_set.x_param_values);
1689 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1690 global_options.x_param_values,
1691 global_options_set.x_param_values);
1692
1693 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1694 requires the arch flags to be evaluated already. Since prefetching
1695 is beneficial on s390, we enable it if available. */
1696 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1697 flag_prefetch_loop_arrays = 1;
1698
1699 /* Use the alternative scheduling-pressure algorithm by default. */
1700 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
1701 global_options.x_param_values,
1702 global_options_set.x_param_values);
1703
1704 if (TARGET_TPF)
1705 {
1706 /* Don't emit DWARF3/4 unless specifically selected. The TPF
1707 debuggers do not yet support DWARF 3/4. */
1708 if (!global_options_set.x_dwarf_strict)
1709 dwarf_strict = 1;
1710 if (!global_options_set.x_dwarf_version)
1711 dwarf_version = 2;
1712 }
1713 }
1714
1715 /* Map for smallest class containing reg regno. */
1716
1717 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1718 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1719 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1720 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1721 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1722 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1723 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1724 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1725 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1726 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1727 ACCESS_REGS, ACCESS_REGS
1728 };
1729
1730 /* Return attribute type of insn. */
1731
1732 static enum attr_type
1733 s390_safe_attr_type (rtx insn)
1734 {
1735 if (recog_memoized (insn) >= 0)
1736 return get_attr_type (insn);
1737 else
1738 return TYPE_NONE;
1739 }
1740
1741 /* Return true if DISP is a valid short displacement. */
1742
1743 static bool
1744 s390_short_displacement (rtx disp)
1745 {
1746 /* No displacement is OK. */
1747 if (!disp)
1748 return true;
1749
1750 /* Without the long displacement facility we don't need to
1751 distingiush between long and short displacement. */
1752 if (!TARGET_LONG_DISPLACEMENT)
1753 return true;
1754
1755 /* Integer displacement in range. */
1756 if (GET_CODE (disp) == CONST_INT)
1757 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1758
1759 /* GOT offset is not OK, the GOT can be large. */
1760 if (GET_CODE (disp) == CONST
1761 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1762 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1763 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1764 return false;
1765
1766 /* All other symbolic constants are literal pool references,
1767 which are OK as the literal pool must be small. */
1768 if (GET_CODE (disp) == CONST)
1769 return true;
1770
1771 return false;
1772 }
1773
1774 /* Decompose a RTL expression ADDR for a memory address into
1775 its components, returned in OUT.
1776
1777 Returns false if ADDR is not a valid memory address, true
1778 otherwise. If OUT is NULL, don't return the components,
1779 but check for validity only.
1780
1781 Note: Only addresses in canonical form are recognized.
1782 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1783 canonical form so that they will be recognized. */
1784
1785 static int
1786 s390_decompose_address (rtx addr, struct s390_address *out)
1787 {
1788 HOST_WIDE_INT offset = 0;
1789 rtx base = NULL_RTX;
1790 rtx indx = NULL_RTX;
1791 rtx disp = NULL_RTX;
1792 rtx orig_disp;
1793 bool pointer = false;
1794 bool base_ptr = false;
1795 bool indx_ptr = false;
1796 bool literal_pool = false;
1797
1798 /* We may need to substitute the literal pool base register into the address
1799 below. However, at this point we do not know which register is going to
1800 be used as base, so we substitute the arg pointer register. This is going
1801 to be treated as holding a pointer below -- it shouldn't be used for any
1802 other purpose. */
1803 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1804
1805 /* Decompose address into base + index + displacement. */
1806
1807 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1808 base = addr;
1809
1810 else if (GET_CODE (addr) == PLUS)
1811 {
1812 rtx op0 = XEXP (addr, 0);
1813 rtx op1 = XEXP (addr, 1);
1814 enum rtx_code code0 = GET_CODE (op0);
1815 enum rtx_code code1 = GET_CODE (op1);
1816
1817 if (code0 == REG || code0 == UNSPEC)
1818 {
1819 if (code1 == REG || code1 == UNSPEC)
1820 {
1821 indx = op0; /* index + base */
1822 base = op1;
1823 }
1824
1825 else
1826 {
1827 base = op0; /* base + displacement */
1828 disp = op1;
1829 }
1830 }
1831
1832 else if (code0 == PLUS)
1833 {
1834 indx = XEXP (op0, 0); /* index + base + disp */
1835 base = XEXP (op0, 1);
1836 disp = op1;
1837 }
1838
1839 else
1840 {
1841 return false;
1842 }
1843 }
1844
1845 else
1846 disp = addr; /* displacement */
1847
1848 /* Extract integer part of displacement. */
1849 orig_disp = disp;
1850 if (disp)
1851 {
1852 if (GET_CODE (disp) == CONST_INT)
1853 {
1854 offset = INTVAL (disp);
1855 disp = NULL_RTX;
1856 }
1857 else if (GET_CODE (disp) == CONST
1858 && GET_CODE (XEXP (disp, 0)) == PLUS
1859 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1860 {
1861 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1862 disp = XEXP (XEXP (disp, 0), 0);
1863 }
1864 }
1865
1866 /* Strip off CONST here to avoid special case tests later. */
1867 if (disp && GET_CODE (disp) == CONST)
1868 disp = XEXP (disp, 0);
1869
1870 /* We can convert literal pool addresses to
1871 displacements by basing them off the base register. */
1872 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1873 {
1874 /* Either base or index must be free to hold the base register. */
1875 if (!base)
1876 base = fake_pool_base, literal_pool = true;
1877 else if (!indx)
1878 indx = fake_pool_base, literal_pool = true;
1879 else
1880 return false;
1881
1882 /* Mark up the displacement. */
1883 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1884 UNSPEC_LTREL_OFFSET);
1885 }
1886
1887 /* Validate base register. */
1888 if (base)
1889 {
1890 if (GET_CODE (base) == UNSPEC)
1891 switch (XINT (base, 1))
1892 {
1893 case UNSPEC_LTREF:
1894 if (!disp)
1895 disp = gen_rtx_UNSPEC (Pmode,
1896 gen_rtvec (1, XVECEXP (base, 0, 0)),
1897 UNSPEC_LTREL_OFFSET);
1898 else
1899 return false;
1900
1901 base = XVECEXP (base, 0, 1);
1902 break;
1903
1904 case UNSPEC_LTREL_BASE:
1905 if (XVECLEN (base, 0) == 1)
1906 base = fake_pool_base, literal_pool = true;
1907 else
1908 base = XVECEXP (base, 0, 1);
1909 break;
1910
1911 default:
1912 return false;
1913 }
1914
1915 if (!REG_P (base)
1916 || (GET_MODE (base) != SImode
1917 && GET_MODE (base) != Pmode))
1918 return false;
1919
1920 if (REGNO (base) == STACK_POINTER_REGNUM
1921 || REGNO (base) == FRAME_POINTER_REGNUM
1922 || ((reload_completed || reload_in_progress)
1923 && frame_pointer_needed
1924 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1925 || REGNO (base) == ARG_POINTER_REGNUM
1926 || (flag_pic
1927 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1928 pointer = base_ptr = true;
1929
1930 if ((reload_completed || reload_in_progress)
1931 && base == cfun->machine->base_reg)
1932 pointer = base_ptr = literal_pool = true;
1933 }
1934
1935 /* Validate index register. */
1936 if (indx)
1937 {
1938 if (GET_CODE (indx) == UNSPEC)
1939 switch (XINT (indx, 1))
1940 {
1941 case UNSPEC_LTREF:
1942 if (!disp)
1943 disp = gen_rtx_UNSPEC (Pmode,
1944 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1945 UNSPEC_LTREL_OFFSET);
1946 else
1947 return false;
1948
1949 indx = XVECEXP (indx, 0, 1);
1950 break;
1951
1952 case UNSPEC_LTREL_BASE:
1953 if (XVECLEN (indx, 0) == 1)
1954 indx = fake_pool_base, literal_pool = true;
1955 else
1956 indx = XVECEXP (indx, 0, 1);
1957 break;
1958
1959 default:
1960 return false;
1961 }
1962
1963 if (!REG_P (indx)
1964 || (GET_MODE (indx) != SImode
1965 && GET_MODE (indx) != Pmode))
1966 return false;
1967
1968 if (REGNO (indx) == STACK_POINTER_REGNUM
1969 || REGNO (indx) == FRAME_POINTER_REGNUM
1970 || ((reload_completed || reload_in_progress)
1971 && frame_pointer_needed
1972 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1973 || REGNO (indx) == ARG_POINTER_REGNUM
1974 || (flag_pic
1975 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1976 pointer = indx_ptr = true;
1977
1978 if ((reload_completed || reload_in_progress)
1979 && indx == cfun->machine->base_reg)
1980 pointer = indx_ptr = literal_pool = true;
1981 }
1982
1983 /* Prefer to use pointer as base, not index. */
1984 if (base && indx && !base_ptr
1985 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1986 {
1987 rtx tmp = base;
1988 base = indx;
1989 indx = tmp;
1990 }
1991
1992 /* Validate displacement. */
1993 if (!disp)
1994 {
1995 /* If virtual registers are involved, the displacement will change later
1996 anyway as the virtual registers get eliminated. This could make a
1997 valid displacement invalid, but it is more likely to make an invalid
1998 displacement valid, because we sometimes access the register save area
1999 via negative offsets to one of those registers.
2000 Thus we don't check the displacement for validity here. If after
2001 elimination the displacement turns out to be invalid after all,
2002 this is fixed up by reload in any case. */
2003 if (base != arg_pointer_rtx
2004 && indx != arg_pointer_rtx
2005 && base != return_address_pointer_rtx
2006 && indx != return_address_pointer_rtx
2007 && base != frame_pointer_rtx
2008 && indx != frame_pointer_rtx
2009 && base != virtual_stack_vars_rtx
2010 && indx != virtual_stack_vars_rtx)
2011 if (!DISP_IN_RANGE (offset))
2012 return false;
2013 }
2014 else
2015 {
2016 /* All the special cases are pointers. */
2017 pointer = true;
2018
2019 /* In the small-PIC case, the linker converts @GOT
2020 and @GOTNTPOFF offsets to possible displacements. */
2021 if (GET_CODE (disp) == UNSPEC
2022 && (XINT (disp, 1) == UNSPEC_GOT
2023 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2024 && flag_pic == 1)
2025 {
2026 ;
2027 }
2028
2029 /* Accept pool label offsets. */
2030 else if (GET_CODE (disp) == UNSPEC
2031 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2032 ;
2033
2034 /* Accept literal pool references. */
2035 else if (GET_CODE (disp) == UNSPEC
2036 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2037 {
2038 /* In case CSE pulled a non literal pool reference out of
2039 the pool we have to reject the address. This is
2040 especially important when loading the GOT pointer on non
2041 zarch CPUs. In this case the literal pool contains an lt
2042 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2043 will most likely exceed the displacement. */
2044 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2045 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2046 return false;
2047
2048 orig_disp = gen_rtx_CONST (Pmode, disp);
2049 if (offset)
2050 {
2051 /* If we have an offset, make sure it does not
2052 exceed the size of the constant pool entry. */
2053 rtx sym = XVECEXP (disp, 0, 0);
2054 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2055 return false;
2056
2057 orig_disp = plus_constant (Pmode, orig_disp, offset);
2058 }
2059 }
2060
2061 else
2062 return false;
2063 }
2064
2065 if (!base && !indx)
2066 pointer = true;
2067
2068 if (out)
2069 {
2070 out->base = base;
2071 out->indx = indx;
2072 out->disp = orig_disp;
2073 out->pointer = pointer;
2074 out->literal_pool = literal_pool;
2075 }
2076
2077 return true;
2078 }
2079
2080 /* Decompose a RTL expression OP for a shift count into its components,
2081 and return the base register in BASE and the offset in OFFSET.
2082
2083 Return true if OP is a valid shift count, false if not. */
2084
2085 bool
2086 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2087 {
2088 HOST_WIDE_INT off = 0;
2089
2090 /* We can have an integer constant, an address register,
2091 or a sum of the two. */
2092 if (GET_CODE (op) == CONST_INT)
2093 {
2094 off = INTVAL (op);
2095 op = NULL_RTX;
2096 }
2097 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2098 {
2099 off = INTVAL (XEXP (op, 1));
2100 op = XEXP (op, 0);
2101 }
2102 while (op && GET_CODE (op) == SUBREG)
2103 op = SUBREG_REG (op);
2104
2105 if (op && GET_CODE (op) != REG)
2106 return false;
2107
2108 if (offset)
2109 *offset = off;
2110 if (base)
2111 *base = op;
2112
2113 return true;
2114 }
2115
2116
2117 /* Return true if CODE is a valid address without index. */
2118
2119 bool
2120 s390_legitimate_address_without_index_p (rtx op)
2121 {
2122 struct s390_address addr;
2123
2124 if (!s390_decompose_address (XEXP (op, 0), &addr))
2125 return false;
2126 if (addr.indx)
2127 return false;
2128
2129 return true;
2130 }
2131
2132
2133 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2134 and return these parts in SYMREF and ADDEND. You can pass NULL in
2135 SYMREF and/or ADDEND if you are not interested in these values.
2136 Literal pool references are *not* considered symbol references. */
2137
2138 static bool
2139 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2140 {
2141 HOST_WIDE_INT tmpaddend = 0;
2142
2143 if (GET_CODE (addr) == CONST)
2144 addr = XEXP (addr, 0);
2145
2146 if (GET_CODE (addr) == PLUS)
2147 {
2148 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2149 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2150 && CONST_INT_P (XEXP (addr, 1)))
2151 {
2152 tmpaddend = INTVAL (XEXP (addr, 1));
2153 addr = XEXP (addr, 0);
2154 }
2155 else
2156 return false;
2157 }
2158 else
2159 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2160 return false;
2161
2162 if (symref)
2163 *symref = addr;
2164 if (addend)
2165 *addend = tmpaddend;
2166
2167 return true;
2168 }
2169
2170 /* Return TRUE if ADDR is an operand valid for a load/store relative
2171 instructions. Be aware that the alignment of the operand needs to
2172 be checked separately. */
2173 static bool
2174 s390_loadrelative_operand_p (rtx addr)
2175 {
2176 if (GET_CODE (addr) == CONST)
2177 addr = XEXP (addr, 0);
2178
2179 /* Enable load relative for symbol@GOTENT. */
2180 if (GET_CODE (addr) == UNSPEC
2181 && XINT (addr, 1) == UNSPEC_GOTENT)
2182 return true;
2183
2184 return s390_symref_operand_p (addr, NULL, NULL);
2185 }
2186
2187 /* Return true if the address in OP is valid for constraint letter C
2188 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2189 pool MEMs should be accepted. Only the Q, R, S, T constraint
2190 letters are allowed for C. */
2191
2192 static int
2193 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2194 {
2195 struct s390_address addr;
2196 bool decomposed = false;
2197
2198 /* This check makes sure that no symbolic address (except literal
2199 pool references) are accepted by the R or T constraints. */
2200 if (s390_loadrelative_operand_p (op))
2201 return 0;
2202
2203 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2204 if (!lit_pool_ok)
2205 {
2206 if (!s390_decompose_address (op, &addr))
2207 return 0;
2208 if (addr.literal_pool)
2209 return 0;
2210 decomposed = true;
2211 }
2212
2213 switch (c)
2214 {
2215 case 'Q': /* no index short displacement */
2216 if (!decomposed && !s390_decompose_address (op, &addr))
2217 return 0;
2218 if (addr.indx)
2219 return 0;
2220 if (!s390_short_displacement (addr.disp))
2221 return 0;
2222 break;
2223
2224 case 'R': /* with index short displacement */
2225 if (TARGET_LONG_DISPLACEMENT)
2226 {
2227 if (!decomposed && !s390_decompose_address (op, &addr))
2228 return 0;
2229 if (!s390_short_displacement (addr.disp))
2230 return 0;
2231 }
2232 /* Any invalid address here will be fixed up by reload,
2233 so accept it for the most generic constraint. */
2234 break;
2235
2236 case 'S': /* no index long displacement */
2237 if (!TARGET_LONG_DISPLACEMENT)
2238 return 0;
2239 if (!decomposed && !s390_decompose_address (op, &addr))
2240 return 0;
2241 if (addr.indx)
2242 return 0;
2243 if (s390_short_displacement (addr.disp))
2244 return 0;
2245 break;
2246
2247 case 'T': /* with index long displacement */
2248 if (!TARGET_LONG_DISPLACEMENT)
2249 return 0;
2250 /* Any invalid address here will be fixed up by reload,
2251 so accept it for the most generic constraint. */
2252 if ((decomposed || s390_decompose_address (op, &addr))
2253 && s390_short_displacement (addr.disp))
2254 return 0;
2255 break;
2256 default:
2257 return 0;
2258 }
2259 return 1;
2260 }
2261
2262
2263 /* Evaluates constraint strings described by the regular expression
2264 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2265 the constraint given in STR, or 0 else. */
2266
2267 int
2268 s390_mem_constraint (const char *str, rtx op)
2269 {
2270 char c = str[0];
2271
2272 switch (c)
2273 {
2274 case 'A':
2275 /* Check for offsettable variants of memory constraints. */
2276 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2277 return 0;
2278 if ((reload_completed || reload_in_progress)
2279 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2280 return 0;
2281 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2282 case 'B':
2283 /* Check for non-literal-pool variants of memory constraints. */
2284 if (!MEM_P (op))
2285 return 0;
2286 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2287 case 'Q':
2288 case 'R':
2289 case 'S':
2290 case 'T':
2291 if (GET_CODE (op) != MEM)
2292 return 0;
2293 return s390_check_qrst_address (c, XEXP (op, 0), true);
2294 case 'U':
2295 return (s390_check_qrst_address ('Q', op, true)
2296 || s390_check_qrst_address ('R', op, true));
2297 case 'W':
2298 return (s390_check_qrst_address ('S', op, true)
2299 || s390_check_qrst_address ('T', op, true));
2300 case 'Y':
2301 /* Simply check for the basic form of a shift count. Reload will
2302 take care of making sure we have a proper base register. */
2303 if (!s390_decompose_shift_count (op, NULL, NULL))
2304 return 0;
2305 break;
2306 case 'Z':
2307 return s390_check_qrst_address (str[1], op, true);
2308 default:
2309 return 0;
2310 }
2311 return 1;
2312 }
2313
2314
2315 /* Evaluates constraint strings starting with letter O. Input
2316 parameter C is the second letter following the "O" in the constraint
2317 string. Returns 1 if VALUE meets the respective constraint and 0
2318 otherwise. */
2319
2320 int
2321 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2322 {
2323 if (!TARGET_EXTIMM)
2324 return 0;
2325
2326 switch (c)
2327 {
2328 case 's':
2329 return trunc_int_for_mode (value, SImode) == value;
2330
2331 case 'p':
2332 return value == 0
2333 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2334
2335 case 'n':
2336 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2337
2338 default:
2339 gcc_unreachable ();
2340 }
2341 }
2342
2343
2344 /* Evaluates constraint strings starting with letter N. Parameter STR
2345 contains the letters following letter "N" in the constraint string.
2346 Returns true if VALUE matches the constraint. */
2347
2348 int
2349 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2350 {
2351 enum machine_mode mode, part_mode;
2352 int def;
2353 int part, part_goal;
2354
2355
2356 if (str[0] == 'x')
2357 part_goal = -1;
2358 else
2359 part_goal = str[0] - '0';
2360
2361 switch (str[1])
2362 {
2363 case 'Q':
2364 part_mode = QImode;
2365 break;
2366 case 'H':
2367 part_mode = HImode;
2368 break;
2369 case 'S':
2370 part_mode = SImode;
2371 break;
2372 default:
2373 return 0;
2374 }
2375
2376 switch (str[2])
2377 {
2378 case 'H':
2379 mode = HImode;
2380 break;
2381 case 'S':
2382 mode = SImode;
2383 break;
2384 case 'D':
2385 mode = DImode;
2386 break;
2387 default:
2388 return 0;
2389 }
2390
2391 switch (str[3])
2392 {
2393 case '0':
2394 def = 0;
2395 break;
2396 case 'F':
2397 def = -1;
2398 break;
2399 default:
2400 return 0;
2401 }
2402
2403 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2404 return 0;
2405
2406 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2407 if (part < 0)
2408 return 0;
2409 if (part_goal != -1 && part_goal != part)
2410 return 0;
2411
2412 return 1;
2413 }
2414
2415
2416 /* Returns true if the input parameter VALUE is a float zero. */
2417
2418 int
2419 s390_float_const_zero_p (rtx value)
2420 {
2421 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2422 && value == CONST0_RTX (GET_MODE (value)));
2423 }
2424
2425 /* Implement TARGET_REGISTER_MOVE_COST. */
2426
2427 static int
2428 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2429 reg_class_t from, reg_class_t to)
2430 {
2431 /* On s390, copy between fprs and gprs is expensive. */
2432 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2433 && reg_classes_intersect_p (to, FP_REGS))
2434 || (reg_classes_intersect_p (from, FP_REGS)
2435 && reg_classes_intersect_p (to, GENERAL_REGS)))
2436 return 10;
2437
2438 return 1;
2439 }
2440
2441 /* Implement TARGET_MEMORY_MOVE_COST. */
2442
2443 static int
2444 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2445 reg_class_t rclass ATTRIBUTE_UNUSED,
2446 bool in ATTRIBUTE_UNUSED)
2447 {
2448 return 1;
2449 }
2450
2451 /* Compute a (partial) cost for rtx X. Return true if the complete
2452 cost has been computed, and false if subexpressions should be
2453 scanned. In either case, *TOTAL contains the cost result.
2454 CODE contains GET_CODE (x), OUTER_CODE contains the code
2455 of the superexpression of x. */
2456
2457 static bool
2458 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2459 int *total, bool speed ATTRIBUTE_UNUSED)
2460 {
2461 switch (code)
2462 {
2463 case CONST:
2464 case CONST_INT:
2465 case LABEL_REF:
2466 case SYMBOL_REF:
2467 case CONST_DOUBLE:
2468 case MEM:
2469 *total = 0;
2470 return true;
2471
2472 case ASHIFT:
2473 case ASHIFTRT:
2474 case LSHIFTRT:
2475 case ROTATE:
2476 case ROTATERT:
2477 case AND:
2478 case IOR:
2479 case XOR:
2480 case NEG:
2481 case NOT:
2482 *total = COSTS_N_INSNS (1);
2483 return false;
2484
2485 case PLUS:
2486 case MINUS:
2487 *total = COSTS_N_INSNS (1);
2488 return false;
2489
2490 case MULT:
2491 switch (GET_MODE (x))
2492 {
2493 case SImode:
2494 {
2495 rtx left = XEXP (x, 0);
2496 rtx right = XEXP (x, 1);
2497 if (GET_CODE (right) == CONST_INT
2498 && CONST_OK_FOR_K (INTVAL (right)))
2499 *total = s390_cost->mhi;
2500 else if (GET_CODE (left) == SIGN_EXTEND)
2501 *total = s390_cost->mh;
2502 else
2503 *total = s390_cost->ms; /* msr, ms, msy */
2504 break;
2505 }
2506 case DImode:
2507 {
2508 rtx left = XEXP (x, 0);
2509 rtx right = XEXP (x, 1);
2510 if (TARGET_ZARCH)
2511 {
2512 if (GET_CODE (right) == CONST_INT
2513 && CONST_OK_FOR_K (INTVAL (right)))
2514 *total = s390_cost->mghi;
2515 else if (GET_CODE (left) == SIGN_EXTEND)
2516 *total = s390_cost->msgf;
2517 else
2518 *total = s390_cost->msg; /* msgr, msg */
2519 }
2520 else /* TARGET_31BIT */
2521 {
2522 if (GET_CODE (left) == SIGN_EXTEND
2523 && GET_CODE (right) == SIGN_EXTEND)
2524 /* mulsidi case: mr, m */
2525 *total = s390_cost->m;
2526 else if (GET_CODE (left) == ZERO_EXTEND
2527 && GET_CODE (right) == ZERO_EXTEND
2528 && TARGET_CPU_ZARCH)
2529 /* umulsidi case: ml, mlr */
2530 *total = s390_cost->ml;
2531 else
2532 /* Complex calculation is required. */
2533 *total = COSTS_N_INSNS (40);
2534 }
2535 break;
2536 }
2537 case SFmode:
2538 case DFmode:
2539 *total = s390_cost->mult_df;
2540 break;
2541 case TFmode:
2542 *total = s390_cost->mxbr;
2543 break;
2544 default:
2545 return false;
2546 }
2547 return false;
2548
2549 case FMA:
2550 switch (GET_MODE (x))
2551 {
2552 case DFmode:
2553 *total = s390_cost->madbr;
2554 break;
2555 case SFmode:
2556 *total = s390_cost->maebr;
2557 break;
2558 default:
2559 return false;
2560 }
2561 /* Negate in the third argument is free: FMSUB. */
2562 if (GET_CODE (XEXP (x, 2)) == NEG)
2563 {
2564 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2565 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2566 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2567 return true;
2568 }
2569 return false;
2570
2571 case UDIV:
2572 case UMOD:
2573 if (GET_MODE (x) == TImode) /* 128 bit division */
2574 *total = s390_cost->dlgr;
2575 else if (GET_MODE (x) == DImode)
2576 {
2577 rtx right = XEXP (x, 1);
2578 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2579 *total = s390_cost->dlr;
2580 else /* 64 by 64 bit division */
2581 *total = s390_cost->dlgr;
2582 }
2583 else if (GET_MODE (x) == SImode) /* 32 bit division */
2584 *total = s390_cost->dlr;
2585 return false;
2586
2587 case DIV:
2588 case MOD:
2589 if (GET_MODE (x) == DImode)
2590 {
2591 rtx right = XEXP (x, 1);
2592 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2593 if (TARGET_ZARCH)
2594 *total = s390_cost->dsgfr;
2595 else
2596 *total = s390_cost->dr;
2597 else /* 64 by 64 bit division */
2598 *total = s390_cost->dsgr;
2599 }
2600 else if (GET_MODE (x) == SImode) /* 32 bit division */
2601 *total = s390_cost->dlr;
2602 else if (GET_MODE (x) == SFmode)
2603 {
2604 *total = s390_cost->debr;
2605 }
2606 else if (GET_MODE (x) == DFmode)
2607 {
2608 *total = s390_cost->ddbr;
2609 }
2610 else if (GET_MODE (x) == TFmode)
2611 {
2612 *total = s390_cost->dxbr;
2613 }
2614 return false;
2615
2616 case SQRT:
2617 if (GET_MODE (x) == SFmode)
2618 *total = s390_cost->sqebr;
2619 else if (GET_MODE (x) == DFmode)
2620 *total = s390_cost->sqdbr;
2621 else /* TFmode */
2622 *total = s390_cost->sqxbr;
2623 return false;
2624
2625 case SIGN_EXTEND:
2626 case ZERO_EXTEND:
2627 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2628 || outer_code == PLUS || outer_code == MINUS
2629 || outer_code == COMPARE)
2630 *total = 0;
2631 return false;
2632
2633 case COMPARE:
2634 *total = COSTS_N_INSNS (1);
2635 if (GET_CODE (XEXP (x, 0)) == AND
2636 && GET_CODE (XEXP (x, 1)) == CONST_INT
2637 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2638 {
2639 rtx op0 = XEXP (XEXP (x, 0), 0);
2640 rtx op1 = XEXP (XEXP (x, 0), 1);
2641 rtx op2 = XEXP (x, 1);
2642
2643 if (memory_operand (op0, GET_MODE (op0))
2644 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2645 return true;
2646 if (register_operand (op0, GET_MODE (op0))
2647 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2648 return true;
2649 }
2650 return false;
2651
2652 default:
2653 return false;
2654 }
2655 }
2656
2657 /* Return the cost of an address rtx ADDR. */
2658
2659 static int
2660 s390_address_cost (rtx addr, enum machine_mode mode ATTRIBUTE_UNUSED,
2661 addr_space_t as ATTRIBUTE_UNUSED,
2662 bool speed ATTRIBUTE_UNUSED)
2663 {
2664 struct s390_address ad;
2665 if (!s390_decompose_address (addr, &ad))
2666 return 1000;
2667
2668 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2669 }
2670
2671 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2672 otherwise return 0. */
2673
2674 int
2675 tls_symbolic_operand (rtx op)
2676 {
2677 if (GET_CODE (op) != SYMBOL_REF)
2678 return 0;
2679 return SYMBOL_REF_TLS_MODEL (op);
2680 }
2681 \f
2682 /* Split DImode access register reference REG (on 64-bit) into its constituent
2683 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2684 gen_highpart cannot be used as they assume all registers are word-sized,
2685 while our access registers have only half that size. */
2686
2687 void
2688 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2689 {
2690 gcc_assert (TARGET_64BIT);
2691 gcc_assert (ACCESS_REG_P (reg));
2692 gcc_assert (GET_MODE (reg) == DImode);
2693 gcc_assert (!(REGNO (reg) & 1));
2694
2695 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2696 *hi = gen_rtx_REG (SImode, REGNO (reg));
2697 }
2698
2699 /* Return true if OP contains a symbol reference */
2700
2701 bool
2702 symbolic_reference_mentioned_p (rtx op)
2703 {
2704 const char *fmt;
2705 int i;
2706
2707 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2708 return 1;
2709
2710 fmt = GET_RTX_FORMAT (GET_CODE (op));
2711 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2712 {
2713 if (fmt[i] == 'E')
2714 {
2715 int j;
2716
2717 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2718 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2719 return 1;
2720 }
2721
2722 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2723 return 1;
2724 }
2725
2726 return 0;
2727 }
2728
2729 /* Return true if OP contains a reference to a thread-local symbol. */
2730
2731 bool
2732 tls_symbolic_reference_mentioned_p (rtx op)
2733 {
2734 const char *fmt;
2735 int i;
2736
2737 if (GET_CODE (op) == SYMBOL_REF)
2738 return tls_symbolic_operand (op);
2739
2740 fmt = GET_RTX_FORMAT (GET_CODE (op));
2741 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2742 {
2743 if (fmt[i] == 'E')
2744 {
2745 int j;
2746
2747 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2748 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2749 return true;
2750 }
2751
2752 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2753 return true;
2754 }
2755
2756 return false;
2757 }
2758
2759
2760 /* Return true if OP is a legitimate general operand when
2761 generating PIC code. It is given that flag_pic is on
2762 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2763
2764 int
2765 legitimate_pic_operand_p (rtx op)
2766 {
2767 /* Accept all non-symbolic constants. */
2768 if (!SYMBOLIC_CONST (op))
2769 return 1;
2770
2771 /* Reject everything else; must be handled
2772 via emit_symbolic_move. */
2773 return 0;
2774 }
2775
2776 /* Returns true if the constant value OP is a legitimate general operand.
2777 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2778
2779 static bool
2780 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2781 {
2782 /* Accept all non-symbolic constants. */
2783 if (!SYMBOLIC_CONST (op))
2784 return 1;
2785
2786 /* Accept immediate LARL operands. */
2787 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2788 return 1;
2789
2790 /* Thread-local symbols are never legal constants. This is
2791 so that emit_call knows that computing such addresses
2792 might require a function call. */
2793 if (TLS_SYMBOLIC_CONST (op))
2794 return 0;
2795
2796 /* In the PIC case, symbolic constants must *not* be
2797 forced into the literal pool. We accept them here,
2798 so that they will be handled by emit_symbolic_move. */
2799 if (flag_pic)
2800 return 1;
2801
2802 /* All remaining non-PIC symbolic constants are
2803 forced into the literal pool. */
2804 return 0;
2805 }
2806
2807 /* Determine if it's legal to put X into the constant pool. This
2808 is not possible if X contains the address of a symbol that is
2809 not constant (TLS) or not known at final link time (PIC). */
2810
2811 static bool
2812 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2813 {
2814 switch (GET_CODE (x))
2815 {
2816 case CONST_INT:
2817 case CONST_DOUBLE:
2818 /* Accept all non-symbolic constants. */
2819 return false;
2820
2821 case LABEL_REF:
2822 /* Labels are OK iff we are non-PIC. */
2823 return flag_pic != 0;
2824
2825 case SYMBOL_REF:
2826 /* 'Naked' TLS symbol references are never OK,
2827 non-TLS symbols are OK iff we are non-PIC. */
2828 if (tls_symbolic_operand (x))
2829 return true;
2830 else
2831 return flag_pic != 0;
2832
2833 case CONST:
2834 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2835 case PLUS:
2836 case MINUS:
2837 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2838 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2839
2840 case UNSPEC:
2841 switch (XINT (x, 1))
2842 {
2843 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2844 case UNSPEC_LTREL_OFFSET:
2845 case UNSPEC_GOT:
2846 case UNSPEC_GOTOFF:
2847 case UNSPEC_PLTOFF:
2848 case UNSPEC_TLSGD:
2849 case UNSPEC_TLSLDM:
2850 case UNSPEC_NTPOFF:
2851 case UNSPEC_DTPOFF:
2852 case UNSPEC_GOTNTPOFF:
2853 case UNSPEC_INDNTPOFF:
2854 return false;
2855
2856 /* If the literal pool shares the code section, be put
2857 execute template placeholders into the pool as well. */
2858 case UNSPEC_INSN:
2859 return TARGET_CPU_ZARCH;
2860
2861 default:
2862 return true;
2863 }
2864 break;
2865
2866 default:
2867 gcc_unreachable ();
2868 }
2869 }
2870
2871 /* Returns true if the constant value OP is a legitimate general
2872 operand during and after reload. The difference to
2873 legitimate_constant_p is that this function will not accept
2874 a constant that would need to be forced to the literal pool
2875 before it can be used as operand.
2876 This function accepts all constants which can be loaded directly
2877 into a GPR. */
2878
2879 bool
2880 legitimate_reload_constant_p (rtx op)
2881 {
2882 /* Accept la(y) operands. */
2883 if (GET_CODE (op) == CONST_INT
2884 && DISP_IN_RANGE (INTVAL (op)))
2885 return true;
2886
2887 /* Accept l(g)hi/l(g)fi operands. */
2888 if (GET_CODE (op) == CONST_INT
2889 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2890 return true;
2891
2892 /* Accept lliXX operands. */
2893 if (TARGET_ZARCH
2894 && GET_CODE (op) == CONST_INT
2895 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2896 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2897 return true;
2898
2899 if (TARGET_EXTIMM
2900 && GET_CODE (op) == CONST_INT
2901 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2902 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2903 return true;
2904
2905 /* Accept larl operands. */
2906 if (TARGET_CPU_ZARCH
2907 && larl_operand (op, VOIDmode))
2908 return true;
2909
2910 /* Accept floating-point zero operands that fit into a single GPR. */
2911 if (GET_CODE (op) == CONST_DOUBLE
2912 && s390_float_const_zero_p (op)
2913 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2914 return true;
2915
2916 /* Accept double-word operands that can be split. */
2917 if (GET_CODE (op) == CONST_INT
2918 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2919 {
2920 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2921 rtx hi = operand_subword (op, 0, 0, dword_mode);
2922 rtx lo = operand_subword (op, 1, 0, dword_mode);
2923 return legitimate_reload_constant_p (hi)
2924 && legitimate_reload_constant_p (lo);
2925 }
2926
2927 /* Everything else cannot be handled without reload. */
2928 return false;
2929 }
2930
2931 /* Returns true if the constant value OP is a legitimate fp operand
2932 during and after reload.
2933 This function accepts all constants which can be loaded directly
2934 into an FPR. */
2935
2936 static bool
2937 legitimate_reload_fp_constant_p (rtx op)
2938 {
2939 /* Accept floating-point zero operands if the load zero instruction
2940 can be used. Prior to z196 the load fp zero instruction caused a
2941 performance penalty if the result is used as BFP number. */
2942 if (TARGET_Z196
2943 && GET_CODE (op) == CONST_DOUBLE
2944 && s390_float_const_zero_p (op))
2945 return true;
2946
2947 return false;
2948 }
2949
2950 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2951 return the class of reg to actually use. */
2952
2953 static reg_class_t
2954 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2955 {
2956 switch (GET_CODE (op))
2957 {
2958 /* Constants we cannot reload into general registers
2959 must be forced into the literal pool. */
2960 case CONST_DOUBLE:
2961 case CONST_INT:
2962 if (reg_class_subset_p (GENERAL_REGS, rclass)
2963 && legitimate_reload_constant_p (op))
2964 return GENERAL_REGS;
2965 else if (reg_class_subset_p (ADDR_REGS, rclass)
2966 && legitimate_reload_constant_p (op))
2967 return ADDR_REGS;
2968 else if (reg_class_subset_p (FP_REGS, rclass)
2969 && legitimate_reload_fp_constant_p (op))
2970 return FP_REGS;
2971 return NO_REGS;
2972
2973 /* If a symbolic constant or a PLUS is reloaded,
2974 it is most likely being used as an address, so
2975 prefer ADDR_REGS. If 'class' is not a superset
2976 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2977 case LABEL_REF:
2978 case SYMBOL_REF:
2979 case CONST:
2980 if (!legitimate_reload_constant_p (op))
2981 return NO_REGS;
2982 /* fallthrough */
2983 case PLUS:
2984 /* load address will be used. */
2985 if (reg_class_subset_p (ADDR_REGS, rclass))
2986 return ADDR_REGS;
2987 else
2988 return NO_REGS;
2989
2990 default:
2991 break;
2992 }
2993
2994 return rclass;
2995 }
2996
2997 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2998 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2999 aligned. */
3000
3001 bool
3002 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
3003 {
3004 HOST_WIDE_INT addend;
3005 rtx symref;
3006
3007 /* Accept symbol@GOTENT with pointer size alignment. */
3008 if (GET_CODE (addr) == CONST
3009 && GET_CODE (XEXP (addr, 0)) == UNSPEC
3010 && XINT (XEXP (addr, 0), 1) == UNSPEC_GOTENT
3011 && alignment <= UNITS_PER_LONG)
3012 return true;
3013
3014 if (!s390_symref_operand_p (addr, &symref, &addend))
3015 return false;
3016
3017 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
3018 && !(addend & (alignment - 1)));
3019 }
3020
3021 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3022 operand SCRATCH is used to reload the even part of the address and
3023 adding one. */
3024
3025 void
3026 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3027 {
3028 HOST_WIDE_INT addend;
3029 rtx symref;
3030
3031 if (!s390_symref_operand_p (addr, &symref, &addend))
3032 gcc_unreachable ();
3033
3034 if (!(addend & 1))
3035 /* Easy case. The addend is even so larl will do fine. */
3036 emit_move_insn (reg, addr);
3037 else
3038 {
3039 /* We can leave the scratch register untouched if the target
3040 register is a valid base register. */
3041 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3042 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3043 scratch = reg;
3044
3045 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3046 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3047
3048 if (addend != 1)
3049 emit_move_insn (scratch,
3050 gen_rtx_CONST (Pmode,
3051 gen_rtx_PLUS (Pmode, symref,
3052 GEN_INT (addend - 1))));
3053 else
3054 emit_move_insn (scratch, symref);
3055
3056 /* Increment the address using la in order to avoid clobbering cc. */
3057 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3058 }
3059 }
3060
3061 /* Generate what is necessary to move between REG and MEM using
3062 SCRATCH. The direction is given by TOMEM. */
3063
3064 void
3065 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3066 {
3067 /* Reload might have pulled a constant out of the literal pool.
3068 Force it back in. */
3069 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3070 || GET_CODE (mem) == CONST)
3071 mem = force_const_mem (GET_MODE (reg), mem);
3072
3073 gcc_assert (MEM_P (mem));
3074
3075 /* For a load from memory we can leave the scratch register
3076 untouched if the target register is a valid base register. */
3077 if (!tomem
3078 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3079 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3080 && GET_MODE (reg) == GET_MODE (scratch))
3081 scratch = reg;
3082
3083 /* Load address into scratch register. Since we can't have a
3084 secondary reload for a secondary reload we have to cover the case
3085 where larl would need a secondary reload here as well. */
3086 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3087
3088 /* Now we can use a standard load/store to do the move. */
3089 if (tomem)
3090 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3091 else
3092 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3093 }
3094
3095 /* Inform reload about cases where moving X with a mode MODE to a register in
3096 RCLASS requires an extra scratch or immediate register. Return the class
3097 needed for the immediate register. */
3098
3099 static reg_class_t
3100 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3101 enum machine_mode mode, secondary_reload_info *sri)
3102 {
3103 enum reg_class rclass = (enum reg_class) rclass_i;
3104
3105 /* Intermediate register needed. */
3106 if (reg_classes_intersect_p (CC_REGS, rclass))
3107 return GENERAL_REGS;
3108
3109 if (TARGET_Z10)
3110 {
3111 HOST_WIDE_INT offset;
3112 rtx symref;
3113
3114 /* On z10 several optimizer steps may generate larl operands with
3115 an odd addend. */
3116 if (in_p
3117 && s390_symref_operand_p (x, &symref, &offset)
3118 && mode == Pmode
3119 && !SYMBOL_REF_ALIGN1_P (symref)
3120 && (offset & 1) == 1)
3121 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3122 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3123
3124 /* On z10 we need a scratch register when moving QI, TI or floating
3125 point mode values from or to a memory location with a SYMBOL_REF
3126 or if the symref addend of a SI or DI move is not aligned to the
3127 width of the access. */
3128 if (MEM_P (x)
3129 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3130 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3131 || (!TARGET_ZARCH && mode == DImode)
3132 || ((mode == HImode || mode == SImode || mode == DImode)
3133 && (!s390_check_symref_alignment (XEXP (x, 0),
3134 GET_MODE_SIZE (mode))))))
3135 {
3136 #define __SECONDARY_RELOAD_CASE(M,m) \
3137 case M##mode: \
3138 if (TARGET_64BIT) \
3139 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3140 CODE_FOR_reload##m##di_tomem_z10; \
3141 else \
3142 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3143 CODE_FOR_reload##m##si_tomem_z10; \
3144 break;
3145
3146 switch (GET_MODE (x))
3147 {
3148 __SECONDARY_RELOAD_CASE (QI, qi);
3149 __SECONDARY_RELOAD_CASE (HI, hi);
3150 __SECONDARY_RELOAD_CASE (SI, si);
3151 __SECONDARY_RELOAD_CASE (DI, di);
3152 __SECONDARY_RELOAD_CASE (TI, ti);
3153 __SECONDARY_RELOAD_CASE (SF, sf);
3154 __SECONDARY_RELOAD_CASE (DF, df);
3155 __SECONDARY_RELOAD_CASE (TF, tf);
3156 __SECONDARY_RELOAD_CASE (SD, sd);
3157 __SECONDARY_RELOAD_CASE (DD, dd);
3158 __SECONDARY_RELOAD_CASE (TD, td);
3159
3160 default:
3161 gcc_unreachable ();
3162 }
3163 #undef __SECONDARY_RELOAD_CASE
3164 }
3165 }
3166
3167 /* We need a scratch register when loading a PLUS expression which
3168 is not a legitimate operand of the LOAD ADDRESS instruction. */
3169 if (in_p && s390_plus_operand (x, mode))
3170 sri->icode = (TARGET_64BIT ?
3171 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3172
3173 /* Performing a multiword move from or to memory we have to make sure the
3174 second chunk in memory is addressable without causing a displacement
3175 overflow. If that would be the case we calculate the address in
3176 a scratch register. */
3177 if (MEM_P (x)
3178 && GET_CODE (XEXP (x, 0)) == PLUS
3179 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3180 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3181 + GET_MODE_SIZE (mode) - 1))
3182 {
3183 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3184 in a s_operand address since we may fallback to lm/stm. So we only
3185 have to care about overflows in the b+i+d case. */
3186 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3187 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3188 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3189 /* For FP_REGS no lm/stm is available so this check is triggered
3190 for displacement overflows in b+i+d and b+d like addresses. */
3191 || (reg_classes_intersect_p (FP_REGS, rclass)
3192 && s390_class_max_nregs (FP_REGS, mode) > 1))
3193 {
3194 if (in_p)
3195 sri->icode = (TARGET_64BIT ?
3196 CODE_FOR_reloaddi_nonoffmem_in :
3197 CODE_FOR_reloadsi_nonoffmem_in);
3198 else
3199 sri->icode = (TARGET_64BIT ?
3200 CODE_FOR_reloaddi_nonoffmem_out :
3201 CODE_FOR_reloadsi_nonoffmem_out);
3202 }
3203 }
3204
3205 /* A scratch address register is needed when a symbolic constant is
3206 copied to r0 compiling with -fPIC. In other cases the target
3207 register might be used as temporary (see legitimize_pic_address). */
3208 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3209 sri->icode = (TARGET_64BIT ?
3210 CODE_FOR_reloaddi_PIC_addr :
3211 CODE_FOR_reloadsi_PIC_addr);
3212
3213 /* Either scratch or no register needed. */
3214 return NO_REGS;
3215 }
3216
3217 /* Generate code to load SRC, which is PLUS that is not a
3218 legitimate operand for the LA instruction, into TARGET.
3219 SCRATCH may be used as scratch register. */
3220
3221 void
3222 s390_expand_plus_operand (rtx target, rtx src,
3223 rtx scratch)
3224 {
3225 rtx sum1, sum2;
3226 struct s390_address ad;
3227
3228 /* src must be a PLUS; get its two operands. */
3229 gcc_assert (GET_CODE (src) == PLUS);
3230 gcc_assert (GET_MODE (src) == Pmode);
3231
3232 /* Check if any of the two operands is already scheduled
3233 for replacement by reload. This can happen e.g. when
3234 float registers occur in an address. */
3235 sum1 = find_replacement (&XEXP (src, 0));
3236 sum2 = find_replacement (&XEXP (src, 1));
3237 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3238
3239 /* If the address is already strictly valid, there's nothing to do. */
3240 if (!s390_decompose_address (src, &ad)
3241 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3242 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3243 {
3244 /* Otherwise, one of the operands cannot be an address register;
3245 we reload its value into the scratch register. */
3246 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3247 {
3248 emit_move_insn (scratch, sum1);
3249 sum1 = scratch;
3250 }
3251 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3252 {
3253 emit_move_insn (scratch, sum2);
3254 sum2 = scratch;
3255 }
3256
3257 /* According to the way these invalid addresses are generated
3258 in reload.c, it should never happen (at least on s390) that
3259 *neither* of the PLUS components, after find_replacements
3260 was applied, is an address register. */
3261 if (sum1 == scratch && sum2 == scratch)
3262 {
3263 debug_rtx (src);
3264 gcc_unreachable ();
3265 }
3266
3267 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3268 }
3269
3270 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3271 is only ever performed on addresses, so we can mark the
3272 sum as legitimate for LA in any case. */
3273 s390_load_address (target, src);
3274 }
3275
3276
3277 /* Return true if ADDR is a valid memory address.
3278 STRICT specifies whether strict register checking applies. */
3279
3280 static bool
3281 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3282 {
3283 struct s390_address ad;
3284
3285 if (TARGET_Z10
3286 && larl_operand (addr, VOIDmode)
3287 && (mode == VOIDmode
3288 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3289 return true;
3290
3291 if (!s390_decompose_address (addr, &ad))
3292 return false;
3293
3294 if (strict)
3295 {
3296 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3297 return false;
3298
3299 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3300 return false;
3301 }
3302 else
3303 {
3304 if (ad.base
3305 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3306 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3307 return false;
3308
3309 if (ad.indx
3310 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3311 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3312 return false;
3313 }
3314 return true;
3315 }
3316
3317 /* Return true if OP is a valid operand for the LA instruction.
3318 In 31-bit, we need to prove that the result is used as an
3319 address, as LA performs only a 31-bit addition. */
3320
3321 bool
3322 legitimate_la_operand_p (rtx op)
3323 {
3324 struct s390_address addr;
3325 if (!s390_decompose_address (op, &addr))
3326 return false;
3327
3328 return (TARGET_64BIT || addr.pointer);
3329 }
3330
3331 /* Return true if it is valid *and* preferable to use LA to
3332 compute the sum of OP1 and OP2. */
3333
3334 bool
3335 preferred_la_operand_p (rtx op1, rtx op2)
3336 {
3337 struct s390_address addr;
3338
3339 if (op2 != const0_rtx)
3340 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3341
3342 if (!s390_decompose_address (op1, &addr))
3343 return false;
3344 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3345 return false;
3346 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3347 return false;
3348
3349 /* Avoid LA instructions with index register on z196; it is
3350 preferable to use regular add instructions when possible.
3351 Starting with zEC12 the la with index register is "uncracked"
3352 again. */
3353 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3354 return false;
3355
3356 if (!TARGET_64BIT && !addr.pointer)
3357 return false;
3358
3359 if (addr.pointer)
3360 return true;
3361
3362 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3363 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3364 return true;
3365
3366 return false;
3367 }
3368
3369 /* Emit a forced load-address operation to load SRC into DST.
3370 This will use the LOAD ADDRESS instruction even in situations
3371 where legitimate_la_operand_p (SRC) returns false. */
3372
3373 void
3374 s390_load_address (rtx dst, rtx src)
3375 {
3376 if (TARGET_64BIT)
3377 emit_move_insn (dst, src);
3378 else
3379 emit_insn (gen_force_la_31 (dst, src));
3380 }
3381
3382 /* Return a legitimate reference for ORIG (an address) using the
3383 register REG. If REG is 0, a new pseudo is generated.
3384
3385 There are two types of references that must be handled:
3386
3387 1. Global data references must load the address from the GOT, via
3388 the PIC reg. An insn is emitted to do this load, and the reg is
3389 returned.
3390
3391 2. Static data references, constant pool addresses, and code labels
3392 compute the address as an offset from the GOT, whose base is in
3393 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3394 differentiate them from global data objects. The returned
3395 address is the PIC reg + an unspec constant.
3396
3397 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3398 reg also appears in the address. */
3399
3400 rtx
3401 legitimize_pic_address (rtx orig, rtx reg)
3402 {
3403 rtx addr = orig;
3404 rtx new_rtx = orig;
3405 rtx base;
3406
3407 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3408
3409 if (GET_CODE (addr) == LABEL_REF
3410 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3411 {
3412 /* This is a local symbol. */
3413 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3414 {
3415 /* Access local symbols PC-relative via LARL.
3416 This is the same as in the non-PIC case, so it is
3417 handled automatically ... */
3418 }
3419 else
3420 {
3421 /* Access local symbols relative to the GOT. */
3422
3423 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3424
3425 if (reload_in_progress || reload_completed)
3426 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3427
3428 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3429 addr = gen_rtx_CONST (Pmode, addr);
3430 addr = force_const_mem (Pmode, addr);
3431 emit_move_insn (temp, addr);
3432
3433 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3434 if (reg != 0)
3435 {
3436 s390_load_address (reg, new_rtx);
3437 new_rtx = reg;
3438 }
3439 }
3440 }
3441 else if (GET_CODE (addr) == SYMBOL_REF)
3442 {
3443 if (reg == 0)
3444 reg = gen_reg_rtx (Pmode);
3445
3446 if (flag_pic == 1)
3447 {
3448 /* Assume GOT offset < 4k. This is handled the same way
3449 in both 31- and 64-bit code (@GOT). */
3450
3451 if (reload_in_progress || reload_completed)
3452 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3453
3454 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3455 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3456 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3457 new_rtx = gen_const_mem (Pmode, new_rtx);
3458 emit_move_insn (reg, new_rtx);
3459 new_rtx = reg;
3460 }
3461 else if (TARGET_CPU_ZARCH)
3462 {
3463 /* If the GOT offset might be >= 4k, we determine the position
3464 of the GOT entry via a PC-relative LARL (@GOTENT). */
3465
3466 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3467
3468 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3469 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3470
3471 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3472 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3473
3474 if (!TARGET_Z10)
3475 {
3476 emit_move_insn (temp, new_rtx);
3477 new_rtx = gen_const_mem (Pmode, temp);
3478 }
3479 else
3480 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3481 emit_move_insn (reg, new_rtx);
3482 new_rtx = reg;
3483 }
3484 else
3485 {
3486 /* If the GOT offset might be >= 4k, we have to load it
3487 from the literal pool (@GOT). */
3488
3489 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3490
3491 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3492 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3493
3494 if (reload_in_progress || reload_completed)
3495 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3496
3497 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3498 addr = gen_rtx_CONST (Pmode, addr);
3499 addr = force_const_mem (Pmode, addr);
3500 emit_move_insn (temp, addr);
3501
3502 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3503 new_rtx = gen_const_mem (Pmode, new_rtx);
3504 emit_move_insn (reg, new_rtx);
3505 new_rtx = reg;
3506 }
3507 }
3508 else
3509 {
3510 if (GET_CODE (addr) == CONST)
3511 {
3512 addr = XEXP (addr, 0);
3513 if (GET_CODE (addr) == UNSPEC)
3514 {
3515 gcc_assert (XVECLEN (addr, 0) == 1);
3516 switch (XINT (addr, 1))
3517 {
3518 /* If someone moved a GOT-relative UNSPEC
3519 out of the literal pool, force them back in. */
3520 case UNSPEC_GOTOFF:
3521 case UNSPEC_PLTOFF:
3522 new_rtx = force_const_mem (Pmode, orig);
3523 break;
3524
3525 /* @GOT is OK as is if small. */
3526 case UNSPEC_GOT:
3527 if (flag_pic == 2)
3528 new_rtx = force_const_mem (Pmode, orig);
3529 break;
3530
3531 /* @GOTENT is OK as is. */
3532 case UNSPEC_GOTENT:
3533 break;
3534
3535 /* @PLT is OK as is on 64-bit, must be converted to
3536 GOT-relative @PLTOFF on 31-bit. */
3537 case UNSPEC_PLT:
3538 if (!TARGET_CPU_ZARCH)
3539 {
3540 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3541
3542 if (reload_in_progress || reload_completed)
3543 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3544
3545 addr = XVECEXP (addr, 0, 0);
3546 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3547 UNSPEC_PLTOFF);
3548 addr = gen_rtx_CONST (Pmode, addr);
3549 addr = force_const_mem (Pmode, addr);
3550 emit_move_insn (temp, addr);
3551
3552 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3553 if (reg != 0)
3554 {
3555 s390_load_address (reg, new_rtx);
3556 new_rtx = reg;
3557 }
3558 }
3559 break;
3560
3561 /* Everything else cannot happen. */
3562 default:
3563 gcc_unreachable ();
3564 }
3565 }
3566 else
3567 gcc_assert (GET_CODE (addr) == PLUS);
3568 }
3569 if (GET_CODE (addr) == PLUS)
3570 {
3571 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3572
3573 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3574 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3575
3576 /* Check first to see if this is a constant offset
3577 from a local symbol reference. */
3578 if ((GET_CODE (op0) == LABEL_REF
3579 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3580 && GET_CODE (op1) == CONST_INT)
3581 {
3582 if (TARGET_CPU_ZARCH
3583 && larl_operand (op0, VOIDmode)
3584 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3585 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3586 {
3587 if (INTVAL (op1) & 1)
3588 {
3589 /* LARL can't handle odd offsets, so emit a
3590 pair of LARL and LA. */
3591 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3592
3593 if (!DISP_IN_RANGE (INTVAL (op1)))
3594 {
3595 HOST_WIDE_INT even = INTVAL (op1) - 1;
3596 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3597 op0 = gen_rtx_CONST (Pmode, op0);
3598 op1 = const1_rtx;
3599 }
3600
3601 emit_move_insn (temp, op0);
3602 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3603
3604 if (reg != 0)
3605 {
3606 s390_load_address (reg, new_rtx);
3607 new_rtx = reg;
3608 }
3609 }
3610 else
3611 {
3612 /* If the offset is even, we can just use LARL.
3613 This will happen automatically. */
3614 }
3615 }
3616 else
3617 {
3618 /* Access local symbols relative to the GOT. */
3619
3620 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3621
3622 if (reload_in_progress || reload_completed)
3623 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3624
3625 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3626 UNSPEC_GOTOFF);
3627 addr = gen_rtx_PLUS (Pmode, addr, op1);
3628 addr = gen_rtx_CONST (Pmode, addr);
3629 addr = force_const_mem (Pmode, addr);
3630 emit_move_insn (temp, addr);
3631
3632 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3633 if (reg != 0)
3634 {
3635 s390_load_address (reg, new_rtx);
3636 new_rtx = reg;
3637 }
3638 }
3639 }
3640
3641 /* Now, check whether it is a GOT relative symbol plus offset
3642 that was pulled out of the literal pool. Force it back in. */
3643
3644 else if (GET_CODE (op0) == UNSPEC
3645 && GET_CODE (op1) == CONST_INT
3646 && XINT (op0, 1) == UNSPEC_GOTOFF)
3647 {
3648 gcc_assert (XVECLEN (op0, 0) == 1);
3649
3650 new_rtx = force_const_mem (Pmode, orig);
3651 }
3652
3653 /* Otherwise, compute the sum. */
3654 else
3655 {
3656 base = legitimize_pic_address (XEXP (addr, 0), reg);
3657 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3658 base == reg ? NULL_RTX : reg);
3659 if (GET_CODE (new_rtx) == CONST_INT)
3660 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3661 else
3662 {
3663 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3664 {
3665 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3666 new_rtx = XEXP (new_rtx, 1);
3667 }
3668 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3669 }
3670
3671 if (GET_CODE (new_rtx) == CONST)
3672 new_rtx = XEXP (new_rtx, 0);
3673 new_rtx = force_operand (new_rtx, 0);
3674 }
3675 }
3676 }
3677 return new_rtx;
3678 }
3679
3680 /* Load the thread pointer into a register. */
3681
3682 rtx
3683 s390_get_thread_pointer (void)
3684 {
3685 rtx tp = gen_reg_rtx (Pmode);
3686
3687 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3688 mark_reg_pointer (tp, BITS_PER_WORD);
3689
3690 return tp;
3691 }
3692
3693 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3694 in s390_tls_symbol which always refers to __tls_get_offset.
3695 The returned offset is written to RESULT_REG and an USE rtx is
3696 generated for TLS_CALL. */
3697
3698 static GTY(()) rtx s390_tls_symbol;
3699
3700 static void
3701 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3702 {
3703 rtx insn;
3704
3705 if (!flag_pic)
3706 emit_insn (s390_load_got ());
3707
3708 if (!s390_tls_symbol)
3709 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3710
3711 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3712 gen_rtx_REG (Pmode, RETURN_REGNUM));
3713
3714 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3715 RTL_CONST_CALL_P (insn) = 1;
3716 }
3717
3718 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3719 this (thread-local) address. REG may be used as temporary. */
3720
3721 static rtx
3722 legitimize_tls_address (rtx addr, rtx reg)
3723 {
3724 rtx new_rtx, tls_call, temp, base, r2, insn;
3725
3726 if (GET_CODE (addr) == SYMBOL_REF)
3727 switch (tls_symbolic_operand (addr))
3728 {
3729 case TLS_MODEL_GLOBAL_DYNAMIC:
3730 start_sequence ();
3731 r2 = gen_rtx_REG (Pmode, 2);
3732 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3733 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3734 new_rtx = force_const_mem (Pmode, new_rtx);
3735 emit_move_insn (r2, new_rtx);
3736 s390_emit_tls_call_insn (r2, tls_call);
3737 insn = get_insns ();
3738 end_sequence ();
3739
3740 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3741 temp = gen_reg_rtx (Pmode);
3742 emit_libcall_block (insn, temp, r2, new_rtx);
3743
3744 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3745 if (reg != 0)
3746 {
3747 s390_load_address (reg, new_rtx);
3748 new_rtx = reg;
3749 }
3750 break;
3751
3752 case TLS_MODEL_LOCAL_DYNAMIC:
3753 start_sequence ();
3754 r2 = gen_rtx_REG (Pmode, 2);
3755 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3756 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3757 new_rtx = force_const_mem (Pmode, new_rtx);
3758 emit_move_insn (r2, new_rtx);
3759 s390_emit_tls_call_insn (r2, tls_call);
3760 insn = get_insns ();
3761 end_sequence ();
3762
3763 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3764 temp = gen_reg_rtx (Pmode);
3765 emit_libcall_block (insn, temp, r2, new_rtx);
3766
3767 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3768 base = gen_reg_rtx (Pmode);
3769 s390_load_address (base, new_rtx);
3770
3771 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3772 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3773 new_rtx = force_const_mem (Pmode, new_rtx);
3774 temp = gen_reg_rtx (Pmode);
3775 emit_move_insn (temp, new_rtx);
3776
3777 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3778 if (reg != 0)
3779 {
3780 s390_load_address (reg, new_rtx);
3781 new_rtx = reg;
3782 }
3783 break;
3784
3785 case TLS_MODEL_INITIAL_EXEC:
3786 if (flag_pic == 1)
3787 {
3788 /* Assume GOT offset < 4k. This is handled the same way
3789 in both 31- and 64-bit code. */
3790
3791 if (reload_in_progress || reload_completed)
3792 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3793
3794 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3795 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3796 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3797 new_rtx = gen_const_mem (Pmode, new_rtx);
3798 temp = gen_reg_rtx (Pmode);
3799 emit_move_insn (temp, new_rtx);
3800 }
3801 else if (TARGET_CPU_ZARCH)
3802 {
3803 /* If the GOT offset might be >= 4k, we determine the position
3804 of the GOT entry via a PC-relative LARL. */
3805
3806 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3807 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3808 temp = gen_reg_rtx (Pmode);
3809 emit_move_insn (temp, new_rtx);
3810
3811 new_rtx = gen_const_mem (Pmode, temp);
3812 temp = gen_reg_rtx (Pmode);
3813 emit_move_insn (temp, new_rtx);
3814 }
3815 else if (flag_pic)
3816 {
3817 /* If the GOT offset might be >= 4k, we have to load it
3818 from the literal pool. */
3819
3820 if (reload_in_progress || reload_completed)
3821 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3822
3823 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3824 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3825 new_rtx = force_const_mem (Pmode, new_rtx);
3826 temp = gen_reg_rtx (Pmode);
3827 emit_move_insn (temp, new_rtx);
3828
3829 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3830 new_rtx = gen_const_mem (Pmode, new_rtx);
3831
3832 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3833 temp = gen_reg_rtx (Pmode);
3834 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3835 }
3836 else
3837 {
3838 /* In position-dependent code, load the absolute address of
3839 the GOT entry from the literal pool. */
3840
3841 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3842 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3843 new_rtx = force_const_mem (Pmode, new_rtx);
3844 temp = gen_reg_rtx (Pmode);
3845 emit_move_insn (temp, new_rtx);
3846
3847 new_rtx = temp;
3848 new_rtx = gen_const_mem (Pmode, new_rtx);
3849 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3850 temp = gen_reg_rtx (Pmode);
3851 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3852 }
3853
3854 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3855 if (reg != 0)
3856 {
3857 s390_load_address (reg, new_rtx);
3858 new_rtx = reg;
3859 }
3860 break;
3861
3862 case TLS_MODEL_LOCAL_EXEC:
3863 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3864 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3865 new_rtx = force_const_mem (Pmode, new_rtx);
3866 temp = gen_reg_rtx (Pmode);
3867 emit_move_insn (temp, new_rtx);
3868
3869 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3870 if (reg != 0)
3871 {
3872 s390_load_address (reg, new_rtx);
3873 new_rtx = reg;
3874 }
3875 break;
3876
3877 default:
3878 gcc_unreachable ();
3879 }
3880
3881 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3882 {
3883 switch (XINT (XEXP (addr, 0), 1))
3884 {
3885 case UNSPEC_INDNTPOFF:
3886 gcc_assert (TARGET_CPU_ZARCH);
3887 new_rtx = addr;
3888 break;
3889
3890 default:
3891 gcc_unreachable ();
3892 }
3893 }
3894
3895 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3896 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3897 {
3898 new_rtx = XEXP (XEXP (addr, 0), 0);
3899 if (GET_CODE (new_rtx) != SYMBOL_REF)
3900 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3901
3902 new_rtx = legitimize_tls_address (new_rtx, reg);
3903 new_rtx = plus_constant (Pmode, new_rtx,
3904 INTVAL (XEXP (XEXP (addr, 0), 1)));
3905 new_rtx = force_operand (new_rtx, 0);
3906 }
3907
3908 else
3909 gcc_unreachable (); /* for now ... */
3910
3911 return new_rtx;
3912 }
3913
3914 /* Emit insns making the address in operands[1] valid for a standard
3915 move to operands[0]. operands[1] is replaced by an address which
3916 should be used instead of the former RTX to emit the move
3917 pattern. */
3918
3919 void
3920 emit_symbolic_move (rtx *operands)
3921 {
3922 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3923
3924 if (GET_CODE (operands[0]) == MEM)
3925 operands[1] = force_reg (Pmode, operands[1]);
3926 else if (TLS_SYMBOLIC_CONST (operands[1]))
3927 operands[1] = legitimize_tls_address (operands[1], temp);
3928 else if (flag_pic)
3929 operands[1] = legitimize_pic_address (operands[1], temp);
3930 }
3931
3932 /* Try machine-dependent ways of modifying an illegitimate address X
3933 to be legitimate. If we find one, return the new, valid address.
3934
3935 OLDX is the address as it was before break_out_memory_refs was called.
3936 In some cases it is useful to look at this to decide what needs to be done.
3937
3938 MODE is the mode of the operand pointed to by X.
3939
3940 When -fpic is used, special handling is needed for symbolic references.
3941 See comments by legitimize_pic_address for details. */
3942
3943 static rtx
3944 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3945 enum machine_mode mode ATTRIBUTE_UNUSED)
3946 {
3947 rtx constant_term = const0_rtx;
3948
3949 if (TLS_SYMBOLIC_CONST (x))
3950 {
3951 x = legitimize_tls_address (x, 0);
3952
3953 if (s390_legitimate_address_p (mode, x, FALSE))
3954 return x;
3955 }
3956 else if (GET_CODE (x) == PLUS
3957 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3958 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3959 {
3960 return x;
3961 }
3962 else if (flag_pic)
3963 {
3964 if (SYMBOLIC_CONST (x)
3965 || (GET_CODE (x) == PLUS
3966 && (SYMBOLIC_CONST (XEXP (x, 0))
3967 || SYMBOLIC_CONST (XEXP (x, 1)))))
3968 x = legitimize_pic_address (x, 0);
3969
3970 if (s390_legitimate_address_p (mode, x, FALSE))
3971 return x;
3972 }
3973
3974 x = eliminate_constant_term (x, &constant_term);
3975
3976 /* Optimize loading of large displacements by splitting them
3977 into the multiple of 4K and the rest; this allows the
3978 former to be CSE'd if possible.
3979
3980 Don't do this if the displacement is added to a register
3981 pointing into the stack frame, as the offsets will
3982 change later anyway. */
3983
3984 if (GET_CODE (constant_term) == CONST_INT
3985 && !TARGET_LONG_DISPLACEMENT
3986 && !DISP_IN_RANGE (INTVAL (constant_term))
3987 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3988 {
3989 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3990 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3991
3992 rtx temp = gen_reg_rtx (Pmode);
3993 rtx val = force_operand (GEN_INT (upper), temp);
3994 if (val != temp)
3995 emit_move_insn (temp, val);
3996
3997 x = gen_rtx_PLUS (Pmode, x, temp);
3998 constant_term = GEN_INT (lower);
3999 }
4000
4001 if (GET_CODE (x) == PLUS)
4002 {
4003 if (GET_CODE (XEXP (x, 0)) == REG)
4004 {
4005 rtx temp = gen_reg_rtx (Pmode);
4006 rtx val = force_operand (XEXP (x, 1), temp);
4007 if (val != temp)
4008 emit_move_insn (temp, val);
4009
4010 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4011 }
4012
4013 else if (GET_CODE (XEXP (x, 1)) == REG)
4014 {
4015 rtx temp = gen_reg_rtx (Pmode);
4016 rtx val = force_operand (XEXP (x, 0), temp);
4017 if (val != temp)
4018 emit_move_insn (temp, val);
4019
4020 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4021 }
4022 }
4023
4024 if (constant_term != const0_rtx)
4025 x = gen_rtx_PLUS (Pmode, x, constant_term);
4026
4027 return x;
4028 }
4029
4030 /* Try a machine-dependent way of reloading an illegitimate address AD
4031 operand. If we find one, push the reload and return the new address.
4032
4033 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4034 and TYPE is the reload type of the current reload. */
4035
4036 rtx
4037 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
4038 int opnum, int type)
4039 {
4040 if (!optimize || TARGET_LONG_DISPLACEMENT)
4041 return NULL_RTX;
4042
4043 if (GET_CODE (ad) == PLUS)
4044 {
4045 rtx tem = simplify_binary_operation (PLUS, Pmode,
4046 XEXP (ad, 0), XEXP (ad, 1));
4047 if (tem)
4048 ad = tem;
4049 }
4050
4051 if (GET_CODE (ad) == PLUS
4052 && GET_CODE (XEXP (ad, 0)) == REG
4053 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4054 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4055 {
4056 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4057 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4058 rtx cst, tem, new_rtx;
4059
4060 cst = GEN_INT (upper);
4061 if (!legitimate_reload_constant_p (cst))
4062 cst = force_const_mem (Pmode, cst);
4063
4064 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4065 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4066
4067 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4068 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4069 opnum, (enum reload_type) type);
4070 return new_rtx;
4071 }
4072
4073 return NULL_RTX;
4074 }
4075
4076 /* Emit code to move LEN bytes from DST to SRC. */
4077
4078 bool
4079 s390_expand_movmem (rtx dst, rtx src, rtx len)
4080 {
4081 /* When tuning for z10 or higher we rely on the Glibc functions to
4082 do the right thing. Only for constant lengths below 64k we will
4083 generate inline code. */
4084 if (s390_tune >= PROCESSOR_2097_Z10
4085 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4086 return false;
4087
4088 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4089 {
4090 if (INTVAL (len) > 0)
4091 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4092 }
4093
4094 else if (TARGET_MVCLE)
4095 {
4096 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4097 }
4098
4099 else
4100 {
4101 rtx dst_addr, src_addr, count, blocks, temp;
4102 rtx loop_start_label = gen_label_rtx ();
4103 rtx loop_end_label = gen_label_rtx ();
4104 rtx end_label = gen_label_rtx ();
4105 enum machine_mode mode;
4106
4107 mode = GET_MODE (len);
4108 if (mode == VOIDmode)
4109 mode = Pmode;
4110
4111 dst_addr = gen_reg_rtx (Pmode);
4112 src_addr = gen_reg_rtx (Pmode);
4113 count = gen_reg_rtx (mode);
4114 blocks = gen_reg_rtx (mode);
4115
4116 convert_move (count, len, 1);
4117 emit_cmp_and_jump_insns (count, const0_rtx,
4118 EQ, NULL_RTX, mode, 1, end_label);
4119
4120 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4121 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4122 dst = change_address (dst, VOIDmode, dst_addr);
4123 src = change_address (src, VOIDmode, src_addr);
4124
4125 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4126 OPTAB_DIRECT);
4127 if (temp != count)
4128 emit_move_insn (count, temp);
4129
4130 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4131 OPTAB_DIRECT);
4132 if (temp != blocks)
4133 emit_move_insn (blocks, temp);
4134
4135 emit_cmp_and_jump_insns (blocks, const0_rtx,
4136 EQ, NULL_RTX, mode, 1, loop_end_label);
4137
4138 emit_label (loop_start_label);
4139
4140 if (TARGET_Z10
4141 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4142 {
4143 rtx prefetch;
4144
4145 /* Issue a read prefetch for the +3 cache line. */
4146 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4147 const0_rtx, const0_rtx);
4148 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4149 emit_insn (prefetch);
4150
4151 /* Issue a write prefetch for the +3 cache line. */
4152 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4153 const1_rtx, const0_rtx);
4154 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4155 emit_insn (prefetch);
4156 }
4157
4158 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4159 s390_load_address (dst_addr,
4160 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4161 s390_load_address (src_addr,
4162 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4163
4164 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4165 OPTAB_DIRECT);
4166 if (temp != blocks)
4167 emit_move_insn (blocks, temp);
4168
4169 emit_cmp_and_jump_insns (blocks, const0_rtx,
4170 EQ, NULL_RTX, mode, 1, loop_end_label);
4171
4172 emit_jump (loop_start_label);
4173 emit_label (loop_end_label);
4174
4175 emit_insn (gen_movmem_short (dst, src,
4176 convert_to_mode (Pmode, count, 1)));
4177 emit_label (end_label);
4178 }
4179 return true;
4180 }
4181
4182 /* Emit code to set LEN bytes at DST to VAL.
4183 Make use of clrmem if VAL is zero. */
4184
4185 void
4186 s390_expand_setmem (rtx dst, rtx len, rtx val)
4187 {
4188 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4189 return;
4190
4191 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4192
4193 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4194 {
4195 if (val == const0_rtx && INTVAL (len) <= 256)
4196 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4197 else
4198 {
4199 /* Initialize memory by storing the first byte. */
4200 emit_move_insn (adjust_address (dst, QImode, 0), val);
4201
4202 if (INTVAL (len) > 1)
4203 {
4204 /* Initiate 1 byte overlap move.
4205 The first byte of DST is propagated through DSTP1.
4206 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4207 DST is set to size 1 so the rest of the memory location
4208 does not count as source operand. */
4209 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4210 set_mem_size (dst, 1);
4211
4212 emit_insn (gen_movmem_short (dstp1, dst,
4213 GEN_INT (INTVAL (len) - 2)));
4214 }
4215 }
4216 }
4217
4218 else if (TARGET_MVCLE)
4219 {
4220 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4221 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4222 }
4223
4224 else
4225 {
4226 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4227 rtx loop_start_label = gen_label_rtx ();
4228 rtx loop_end_label = gen_label_rtx ();
4229 rtx end_label = gen_label_rtx ();
4230 enum machine_mode mode;
4231
4232 mode = GET_MODE (len);
4233 if (mode == VOIDmode)
4234 mode = Pmode;
4235
4236 dst_addr = gen_reg_rtx (Pmode);
4237 count = gen_reg_rtx (mode);
4238 blocks = gen_reg_rtx (mode);
4239
4240 convert_move (count, len, 1);
4241 emit_cmp_and_jump_insns (count, const0_rtx,
4242 EQ, NULL_RTX, mode, 1, end_label);
4243
4244 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4245 dst = change_address (dst, VOIDmode, dst_addr);
4246
4247 if (val == const0_rtx)
4248 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4249 OPTAB_DIRECT);
4250 else
4251 {
4252 dstp1 = adjust_address (dst, VOIDmode, 1);
4253 set_mem_size (dst, 1);
4254
4255 /* Initialize memory by storing the first byte. */
4256 emit_move_insn (adjust_address (dst, QImode, 0), val);
4257
4258 /* If count is 1 we are done. */
4259 emit_cmp_and_jump_insns (count, const1_rtx,
4260 EQ, NULL_RTX, mode, 1, end_label);
4261
4262 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4263 OPTAB_DIRECT);
4264 }
4265 if (temp != count)
4266 emit_move_insn (count, temp);
4267
4268 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4269 OPTAB_DIRECT);
4270 if (temp != blocks)
4271 emit_move_insn (blocks, temp);
4272
4273 emit_cmp_and_jump_insns (blocks, const0_rtx,
4274 EQ, NULL_RTX, mode, 1, loop_end_label);
4275
4276 emit_label (loop_start_label);
4277
4278 if (TARGET_Z10
4279 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4280 {
4281 /* Issue a write prefetch for the +4 cache line. */
4282 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4283 GEN_INT (1024)),
4284 const1_rtx, const0_rtx);
4285 emit_insn (prefetch);
4286 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4287 }
4288
4289 if (val == const0_rtx)
4290 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4291 else
4292 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4293 s390_load_address (dst_addr,
4294 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4295
4296 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4297 OPTAB_DIRECT);
4298 if (temp != blocks)
4299 emit_move_insn (blocks, temp);
4300
4301 emit_cmp_and_jump_insns (blocks, const0_rtx,
4302 EQ, NULL_RTX, mode, 1, loop_end_label);
4303
4304 emit_jump (loop_start_label);
4305 emit_label (loop_end_label);
4306
4307 if (val == const0_rtx)
4308 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4309 else
4310 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4311 emit_label (end_label);
4312 }
4313 }
4314
4315 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4316 and return the result in TARGET. */
4317
4318 bool
4319 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4320 {
4321 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4322 rtx tmp;
4323
4324 /* When tuning for z10 or higher we rely on the Glibc functions to
4325 do the right thing. Only for constant lengths below 64k we will
4326 generate inline code. */
4327 if (s390_tune >= PROCESSOR_2097_Z10
4328 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4329 return false;
4330
4331 /* As the result of CMPINT is inverted compared to what we need,
4332 we have to swap the operands. */
4333 tmp = op0; op0 = op1; op1 = tmp;
4334
4335 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4336 {
4337 if (INTVAL (len) > 0)
4338 {
4339 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4340 emit_insn (gen_cmpint (target, ccreg));
4341 }
4342 else
4343 emit_move_insn (target, const0_rtx);
4344 }
4345 else if (TARGET_MVCLE)
4346 {
4347 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4348 emit_insn (gen_cmpint (target, ccreg));
4349 }
4350 else
4351 {
4352 rtx addr0, addr1, count, blocks, temp;
4353 rtx loop_start_label = gen_label_rtx ();
4354 rtx loop_end_label = gen_label_rtx ();
4355 rtx end_label = gen_label_rtx ();
4356 enum machine_mode mode;
4357
4358 mode = GET_MODE (len);
4359 if (mode == VOIDmode)
4360 mode = Pmode;
4361
4362 addr0 = gen_reg_rtx (Pmode);
4363 addr1 = gen_reg_rtx (Pmode);
4364 count = gen_reg_rtx (mode);
4365 blocks = gen_reg_rtx (mode);
4366
4367 convert_move (count, len, 1);
4368 emit_cmp_and_jump_insns (count, const0_rtx,
4369 EQ, NULL_RTX, mode, 1, end_label);
4370
4371 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4372 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4373 op0 = change_address (op0, VOIDmode, addr0);
4374 op1 = change_address (op1, VOIDmode, addr1);
4375
4376 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4377 OPTAB_DIRECT);
4378 if (temp != count)
4379 emit_move_insn (count, temp);
4380
4381 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4382 OPTAB_DIRECT);
4383 if (temp != blocks)
4384 emit_move_insn (blocks, temp);
4385
4386 emit_cmp_and_jump_insns (blocks, const0_rtx,
4387 EQ, NULL_RTX, mode, 1, loop_end_label);
4388
4389 emit_label (loop_start_label);
4390
4391 if (TARGET_Z10
4392 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4393 {
4394 rtx prefetch;
4395
4396 /* Issue a read prefetch for the +2 cache line of operand 1. */
4397 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4398 const0_rtx, const0_rtx);
4399 emit_insn (prefetch);
4400 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4401
4402 /* Issue a read prefetch for the +2 cache line of operand 2. */
4403 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4404 const0_rtx, const0_rtx);
4405 emit_insn (prefetch);
4406 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4407 }
4408
4409 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4410 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4411 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4412 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4413 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4414 emit_jump_insn (temp);
4415
4416 s390_load_address (addr0,
4417 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4418 s390_load_address (addr1,
4419 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4420
4421 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4422 OPTAB_DIRECT);
4423 if (temp != blocks)
4424 emit_move_insn (blocks, temp);
4425
4426 emit_cmp_and_jump_insns (blocks, const0_rtx,
4427 EQ, NULL_RTX, mode, 1, loop_end_label);
4428
4429 emit_jump (loop_start_label);
4430 emit_label (loop_end_label);
4431
4432 emit_insn (gen_cmpmem_short (op0, op1,
4433 convert_to_mode (Pmode, count, 1)));
4434 emit_label (end_label);
4435
4436 emit_insn (gen_cmpint (target, ccreg));
4437 }
4438 return true;
4439 }
4440
4441
4442 /* Expand conditional increment or decrement using alc/slb instructions.
4443 Should generate code setting DST to either SRC or SRC + INCREMENT,
4444 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4445 Returns true if successful, false otherwise.
4446
4447 That makes it possible to implement some if-constructs without jumps e.g.:
4448 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4449 unsigned int a, b, c;
4450 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4451 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4452 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4453 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4454
4455 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4456 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4457 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4458 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4459 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4460
4461 bool
4462 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4463 rtx dst, rtx src, rtx increment)
4464 {
4465 enum machine_mode cmp_mode;
4466 enum machine_mode cc_mode;
4467 rtx op_res;
4468 rtx insn;
4469 rtvec p;
4470 int ret;
4471
4472 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4473 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4474 cmp_mode = SImode;
4475 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4476 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4477 cmp_mode = DImode;
4478 else
4479 return false;
4480
4481 /* Try ADD LOGICAL WITH CARRY. */
4482 if (increment == const1_rtx)
4483 {
4484 /* Determine CC mode to use. */
4485 if (cmp_code == EQ || cmp_code == NE)
4486 {
4487 if (cmp_op1 != const0_rtx)
4488 {
4489 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4490 NULL_RTX, 0, OPTAB_WIDEN);
4491 cmp_op1 = const0_rtx;
4492 }
4493
4494 cmp_code = cmp_code == EQ ? LEU : GTU;
4495 }
4496
4497 if (cmp_code == LTU || cmp_code == LEU)
4498 {
4499 rtx tem = cmp_op0;
4500 cmp_op0 = cmp_op1;
4501 cmp_op1 = tem;
4502 cmp_code = swap_condition (cmp_code);
4503 }
4504
4505 switch (cmp_code)
4506 {
4507 case GTU:
4508 cc_mode = CCUmode;
4509 break;
4510
4511 case GEU:
4512 cc_mode = CCL3mode;
4513 break;
4514
4515 default:
4516 return false;
4517 }
4518
4519 /* Emit comparison instruction pattern. */
4520 if (!register_operand (cmp_op0, cmp_mode))
4521 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4522
4523 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4524 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4525 /* We use insn_invalid_p here to add clobbers if required. */
4526 ret = insn_invalid_p (emit_insn (insn), false);
4527 gcc_assert (!ret);
4528
4529 /* Emit ALC instruction pattern. */
4530 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4531 gen_rtx_REG (cc_mode, CC_REGNUM),
4532 const0_rtx);
4533
4534 if (src != const0_rtx)
4535 {
4536 if (!register_operand (src, GET_MODE (dst)))
4537 src = force_reg (GET_MODE (dst), src);
4538
4539 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4540 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4541 }
4542
4543 p = rtvec_alloc (2);
4544 RTVEC_ELT (p, 0) =
4545 gen_rtx_SET (VOIDmode, dst, op_res);
4546 RTVEC_ELT (p, 1) =
4547 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4548 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4549
4550 return true;
4551 }
4552
4553 /* Try SUBTRACT LOGICAL WITH BORROW. */
4554 if (increment == constm1_rtx)
4555 {
4556 /* Determine CC mode to use. */
4557 if (cmp_code == EQ || cmp_code == NE)
4558 {
4559 if (cmp_op1 != const0_rtx)
4560 {
4561 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4562 NULL_RTX, 0, OPTAB_WIDEN);
4563 cmp_op1 = const0_rtx;
4564 }
4565
4566 cmp_code = cmp_code == EQ ? LEU : GTU;
4567 }
4568
4569 if (cmp_code == GTU || cmp_code == GEU)
4570 {
4571 rtx tem = cmp_op0;
4572 cmp_op0 = cmp_op1;
4573 cmp_op1 = tem;
4574 cmp_code = swap_condition (cmp_code);
4575 }
4576
4577 switch (cmp_code)
4578 {
4579 case LEU:
4580 cc_mode = CCUmode;
4581 break;
4582
4583 case LTU:
4584 cc_mode = CCL3mode;
4585 break;
4586
4587 default:
4588 return false;
4589 }
4590
4591 /* Emit comparison instruction pattern. */
4592 if (!register_operand (cmp_op0, cmp_mode))
4593 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4594
4595 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4596 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4597 /* We use insn_invalid_p here to add clobbers if required. */
4598 ret = insn_invalid_p (emit_insn (insn), false);
4599 gcc_assert (!ret);
4600
4601 /* Emit SLB instruction pattern. */
4602 if (!register_operand (src, GET_MODE (dst)))
4603 src = force_reg (GET_MODE (dst), src);
4604
4605 op_res = gen_rtx_MINUS (GET_MODE (dst),
4606 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4607 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4608 gen_rtx_REG (cc_mode, CC_REGNUM),
4609 const0_rtx));
4610 p = rtvec_alloc (2);
4611 RTVEC_ELT (p, 0) =
4612 gen_rtx_SET (VOIDmode, dst, op_res);
4613 RTVEC_ELT (p, 1) =
4614 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4615 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4616
4617 return true;
4618 }
4619
4620 return false;
4621 }
4622
4623 /* Expand code for the insv template. Return true if successful. */
4624
4625 bool
4626 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4627 {
4628 int bitsize = INTVAL (op1);
4629 int bitpos = INTVAL (op2);
4630 enum machine_mode mode = GET_MODE (dest);
4631 enum machine_mode smode;
4632 int smode_bsize, mode_bsize;
4633 rtx op, clobber;
4634
4635 /* Generate INSERT IMMEDIATE (IILL et al). */
4636 /* (set (ze (reg)) (const_int)). */
4637 if (TARGET_ZARCH
4638 && register_operand (dest, word_mode)
4639 && (bitpos % 16) == 0
4640 && (bitsize % 16) == 0
4641 && const_int_operand (src, VOIDmode))
4642 {
4643 HOST_WIDE_INT val = INTVAL (src);
4644 int regpos = bitpos + bitsize;
4645
4646 while (regpos > bitpos)
4647 {
4648 enum machine_mode putmode;
4649 int putsize;
4650
4651 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4652 putmode = SImode;
4653 else
4654 putmode = HImode;
4655
4656 putsize = GET_MODE_BITSIZE (putmode);
4657 regpos -= putsize;
4658 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4659 GEN_INT (putsize),
4660 GEN_INT (regpos)),
4661 gen_int_mode (val, putmode));
4662 val >>= putsize;
4663 }
4664 gcc_assert (regpos == bitpos);
4665 return true;
4666 }
4667
4668 smode = smallest_mode_for_size (bitsize, MODE_INT);
4669 smode_bsize = GET_MODE_BITSIZE (smode);
4670 mode_bsize = GET_MODE_BITSIZE (mode);
4671
4672 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4673 if (bitpos == 0
4674 && (bitsize % BITS_PER_UNIT) == 0
4675 && MEM_P (dest)
4676 && (register_operand (src, word_mode)
4677 || const_int_operand (src, VOIDmode)))
4678 {
4679 /* Emit standard pattern if possible. */
4680 if (smode_bsize == bitsize)
4681 {
4682 emit_move_insn (adjust_address (dest, smode, 0),
4683 gen_lowpart (smode, src));
4684 return true;
4685 }
4686
4687 /* (set (ze (mem)) (const_int)). */
4688 else if (const_int_operand (src, VOIDmode))
4689 {
4690 int size = bitsize / BITS_PER_UNIT;
4691 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4692 BLKmode,
4693 UNITS_PER_WORD - size);
4694
4695 dest = adjust_address (dest, BLKmode, 0);
4696 set_mem_size (dest, size);
4697 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4698 return true;
4699 }
4700
4701 /* (set (ze (mem)) (reg)). */
4702 else if (register_operand (src, word_mode))
4703 {
4704 if (bitsize <= 32)
4705 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4706 const0_rtx), src);
4707 else
4708 {
4709 /* Emit st,stcmh sequence. */
4710 int stcmh_width = bitsize - 32;
4711 int size = stcmh_width / BITS_PER_UNIT;
4712
4713 emit_move_insn (adjust_address (dest, SImode, size),
4714 gen_lowpart (SImode, src));
4715 set_mem_size (dest, size);
4716 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4717 GEN_INT (stcmh_width),
4718 const0_rtx),
4719 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
4720 }
4721 return true;
4722 }
4723 }
4724
4725 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4726 if ((bitpos % BITS_PER_UNIT) == 0
4727 && (bitsize % BITS_PER_UNIT) == 0
4728 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4729 && MEM_P (src)
4730 && (mode == DImode || mode == SImode)
4731 && register_operand (dest, mode))
4732 {
4733 /* Emit a strict_low_part pattern if possible. */
4734 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4735 {
4736 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4737 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4738 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4739 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4740 return true;
4741 }
4742
4743 /* ??? There are more powerful versions of ICM that are not
4744 completely represented in the md file. */
4745 }
4746
4747 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4748 if (TARGET_Z10 && (mode == DImode || mode == SImode))
4749 {
4750 enum machine_mode mode_s = GET_MODE (src);
4751
4752 if (mode_s == VOIDmode)
4753 {
4754 /* Assume const_int etc already in the proper mode. */
4755 src = force_reg (mode, src);
4756 }
4757 else if (mode_s != mode)
4758 {
4759 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4760 src = force_reg (mode_s, src);
4761 src = gen_lowpart (mode, src);
4762 }
4763
4764 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4765 op = gen_rtx_SET (VOIDmode, op, src);
4766
4767 if (!TARGET_ZEC12)
4768 {
4769 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4770 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4771 }
4772 emit_insn (op);
4773
4774 return true;
4775 }
4776
4777 return false;
4778 }
4779
4780 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4781 register that holds VAL of mode MODE shifted by COUNT bits. */
4782
4783 static inline rtx
4784 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4785 {
4786 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4787 NULL_RTX, 1, OPTAB_DIRECT);
4788 return expand_simple_binop (SImode, ASHIFT, val, count,
4789 NULL_RTX, 1, OPTAB_DIRECT);
4790 }
4791
4792 /* Structure to hold the initial parameters for a compare_and_swap operation
4793 in HImode and QImode. */
4794
4795 struct alignment_context
4796 {
4797 rtx memsi; /* SI aligned memory location. */
4798 rtx shift; /* Bit offset with regard to lsb. */
4799 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4800 rtx modemaski; /* ~modemask */
4801 bool aligned; /* True if memory is aligned, false else. */
4802 };
4803
4804 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4805 structure AC for transparent simplifying, if the memory alignment is known
4806 to be at least 32bit. MEM is the memory location for the actual operation
4807 and MODE its mode. */
4808
4809 static void
4810 init_alignment_context (struct alignment_context *ac, rtx mem,
4811 enum machine_mode mode)
4812 {
4813 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4814 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4815
4816 if (ac->aligned)
4817 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4818 else
4819 {
4820 /* Alignment is unknown. */
4821 rtx byteoffset, addr, align;
4822
4823 /* Force the address into a register. */
4824 addr = force_reg (Pmode, XEXP (mem, 0));
4825
4826 /* Align it to SImode. */
4827 align = expand_simple_binop (Pmode, AND, addr,
4828 GEN_INT (-GET_MODE_SIZE (SImode)),
4829 NULL_RTX, 1, OPTAB_DIRECT);
4830 /* Generate MEM. */
4831 ac->memsi = gen_rtx_MEM (SImode, align);
4832 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4833 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4834 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4835
4836 /* Calculate shiftcount. */
4837 byteoffset = expand_simple_binop (Pmode, AND, addr,
4838 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4839 NULL_RTX, 1, OPTAB_DIRECT);
4840 /* As we already have some offset, evaluate the remaining distance. */
4841 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4842 NULL_RTX, 1, OPTAB_DIRECT);
4843 }
4844
4845 /* Shift is the byte count, but we need the bitcount. */
4846 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4847 NULL_RTX, 1, OPTAB_DIRECT);
4848
4849 /* Calculate masks. */
4850 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4851 GEN_INT (GET_MODE_MASK (mode)),
4852 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4853 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4854 NULL_RTX, 1);
4855 }
4856
4857 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4858 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4859 perform the merge in SEQ2. */
4860
4861 static rtx
4862 s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4863 enum machine_mode mode, rtx val, rtx ins)
4864 {
4865 rtx tmp;
4866
4867 if (ac->aligned)
4868 {
4869 start_sequence ();
4870 tmp = copy_to_mode_reg (SImode, val);
4871 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4872 const0_rtx, ins))
4873 {
4874 *seq1 = NULL;
4875 *seq2 = get_insns ();
4876 end_sequence ();
4877 return tmp;
4878 }
4879 end_sequence ();
4880 }
4881
4882 /* Failed to use insv. Generate a two part shift and mask. */
4883 start_sequence ();
4884 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4885 *seq1 = get_insns ();
4886 end_sequence ();
4887
4888 start_sequence ();
4889 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4890 *seq2 = get_insns ();
4891 end_sequence ();
4892
4893 return tmp;
4894 }
4895
4896 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4897 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4898 value to set if CMP == MEM. */
4899
4900 void
4901 s390_expand_cs_hqi (enum machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4902 rtx cmp, rtx new_rtx, bool is_weak)
4903 {
4904 struct alignment_context ac;
4905 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
4906 rtx res = gen_reg_rtx (SImode);
4907 rtx csloop = NULL, csend = NULL;
4908
4909 gcc_assert (MEM_P (mem));
4910
4911 init_alignment_context (&ac, mem, mode);
4912
4913 /* Load full word. Subsequent loads are performed by CS. */
4914 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4915 NULL_RTX, 1, OPTAB_DIRECT);
4916
4917 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4918 possible, we try to use insv to make this happen efficiently. If
4919 that fails we'll generate code both inside and outside the loop. */
4920 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4921 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4922
4923 if (seq0)
4924 emit_insn (seq0);
4925 if (seq1)
4926 emit_insn (seq1);
4927
4928 /* Start CS loop. */
4929 if (!is_weak)
4930 {
4931 /* Begin assuming success. */
4932 emit_move_insn (btarget, const1_rtx);
4933
4934 csloop = gen_label_rtx ();
4935 csend = gen_label_rtx ();
4936 emit_label (csloop);
4937 }
4938
4939 /* val = "<mem>00..0<mem>"
4940 * cmp = "00..0<cmp>00..0"
4941 * new = "00..0<new>00..0"
4942 */
4943
4944 emit_insn (seq2);
4945 emit_insn (seq3);
4946
4947 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4948 if (is_weak)
4949 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
4950 else
4951 {
4952 rtx tmp;
4953
4954 /* Jump to end if we're done (likely?). */
4955 s390_emit_jump (csend, cc);
4956
4957 /* Check for changes outside mode, and loop internal if so.
4958 Arrange the moves so that the compare is adjacent to the
4959 branch so that we can generate CRJ. */
4960 tmp = copy_to_reg (val);
4961 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4962 1, OPTAB_DIRECT);
4963 cc = s390_emit_compare (NE, val, tmp);
4964 s390_emit_jump (csloop, cc);
4965
4966 /* Failed. */
4967 emit_move_insn (btarget, const0_rtx);
4968 emit_label (csend);
4969 }
4970
4971 /* Return the correct part of the bitfield. */
4972 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4973 NULL_RTX, 1, OPTAB_DIRECT), 1);
4974 }
4975
4976 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4977 and VAL the value to play with. If AFTER is true then store the value
4978 MEM holds after the operation, if AFTER is false then store the value MEM
4979 holds before the operation. If TARGET is zero then discard that value, else
4980 store it to TARGET. */
4981
4982 void
4983 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4984 rtx target, rtx mem, rtx val, bool after)
4985 {
4986 struct alignment_context ac;
4987 rtx cmp;
4988 rtx new_rtx = gen_reg_rtx (SImode);
4989 rtx orig = gen_reg_rtx (SImode);
4990 rtx csloop = gen_label_rtx ();
4991
4992 gcc_assert (!target || register_operand (target, VOIDmode));
4993 gcc_assert (MEM_P (mem));
4994
4995 init_alignment_context (&ac, mem, mode);
4996
4997 /* Shift val to the correct bit positions.
4998 Preserve "icm", but prevent "ex icm". */
4999 if (!(ac.aligned && code == SET && MEM_P (val)))
5000 val = s390_expand_mask_and_shift (val, mode, ac.shift);
5001
5002 /* Further preparation insns. */
5003 if (code == PLUS || code == MINUS)
5004 emit_move_insn (orig, val);
5005 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
5006 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
5007 NULL_RTX, 1, OPTAB_DIRECT);
5008
5009 /* Load full word. Subsequent loads are performed by CS. */
5010 cmp = force_reg (SImode, ac.memsi);
5011
5012 /* Start CS loop. */
5013 emit_label (csloop);
5014 emit_move_insn (new_rtx, cmp);
5015
5016 /* Patch new with val at correct position. */
5017 switch (code)
5018 {
5019 case PLUS:
5020 case MINUS:
5021 val = expand_simple_binop (SImode, code, new_rtx, orig,
5022 NULL_RTX, 1, OPTAB_DIRECT);
5023 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5024 NULL_RTX, 1, OPTAB_DIRECT);
5025 /* FALLTHRU */
5026 case SET:
5027 if (ac.aligned && MEM_P (val))
5028 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5029 0, 0, SImode, val);
5030 else
5031 {
5032 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
5033 NULL_RTX, 1, OPTAB_DIRECT);
5034 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
5035 NULL_RTX, 1, OPTAB_DIRECT);
5036 }
5037 break;
5038 case AND:
5039 case IOR:
5040 case XOR:
5041 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
5042 NULL_RTX, 1, OPTAB_DIRECT);
5043 break;
5044 case MULT: /* NAND */
5045 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
5046 NULL_RTX, 1, OPTAB_DIRECT);
5047 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5048 NULL_RTX, 1, OPTAB_DIRECT);
5049 break;
5050 default:
5051 gcc_unreachable ();
5052 }
5053
5054 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
5055 ac.memsi, cmp, new_rtx));
5056
5057 /* Return the correct part of the bitfield. */
5058 if (target)
5059 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
5060 after ? new_rtx : cmp, ac.shift,
5061 NULL_RTX, 1, OPTAB_DIRECT), 1);
5062 }
5063
5064 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5065 We need to emit DTP-relative relocations. */
5066
5067 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5068
5069 static void
5070 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
5071 {
5072 switch (size)
5073 {
5074 case 4:
5075 fputs ("\t.long\t", file);
5076 break;
5077 case 8:
5078 fputs ("\t.quad\t", file);
5079 break;
5080 default:
5081 gcc_unreachable ();
5082 }
5083 output_addr_const (file, x);
5084 fputs ("@DTPOFF", file);
5085 }
5086
5087 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5088 /* Implement TARGET_MANGLE_TYPE. */
5089
5090 static const char *
5091 s390_mangle_type (const_tree type)
5092 {
5093 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5094 && TARGET_LONG_DOUBLE_128)
5095 return "g";
5096
5097 /* For all other types, use normal C++ mangling. */
5098 return NULL;
5099 }
5100 #endif
5101
5102 /* In the name of slightly smaller debug output, and to cater to
5103 general assembler lossage, recognize various UNSPEC sequences
5104 and turn them back into a direct symbol reference. */
5105
5106 static rtx
5107 s390_delegitimize_address (rtx orig_x)
5108 {
5109 rtx x, y;
5110
5111 orig_x = delegitimize_mem_from_attrs (orig_x);
5112 x = orig_x;
5113
5114 /* Extract the symbol ref from:
5115 (plus:SI (reg:SI 12 %r12)
5116 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5117 UNSPEC_GOTOFF/PLTOFF)))
5118 and
5119 (plus:SI (reg:SI 12 %r12)
5120 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5121 UNSPEC_GOTOFF/PLTOFF)
5122 (const_int 4 [0x4])))) */
5123 if (GET_CODE (x) == PLUS
5124 && REG_P (XEXP (x, 0))
5125 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5126 && GET_CODE (XEXP (x, 1)) == CONST)
5127 {
5128 HOST_WIDE_INT offset = 0;
5129
5130 /* The const operand. */
5131 y = XEXP (XEXP (x, 1), 0);
5132
5133 if (GET_CODE (y) == PLUS
5134 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5135 {
5136 offset = INTVAL (XEXP (y, 1));
5137 y = XEXP (y, 0);
5138 }
5139
5140 if (GET_CODE (y) == UNSPEC
5141 && (XINT (y, 1) == UNSPEC_GOTOFF
5142 || XINT (y, 1) == UNSPEC_PLTOFF))
5143 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
5144 }
5145
5146 if (GET_CODE (x) != MEM)
5147 return orig_x;
5148
5149 x = XEXP (x, 0);
5150 if (GET_CODE (x) == PLUS
5151 && GET_CODE (XEXP (x, 1)) == CONST
5152 && GET_CODE (XEXP (x, 0)) == REG
5153 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5154 {
5155 y = XEXP (XEXP (x, 1), 0);
5156 if (GET_CODE (y) == UNSPEC
5157 && XINT (y, 1) == UNSPEC_GOT)
5158 y = XVECEXP (y, 0, 0);
5159 else
5160 return orig_x;
5161 }
5162 else if (GET_CODE (x) == CONST)
5163 {
5164 /* Extract the symbol ref from:
5165 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5166 UNSPEC_PLT/GOTENT))) */
5167
5168 y = XEXP (x, 0);
5169 if (GET_CODE (y) == UNSPEC
5170 && (XINT (y, 1) == UNSPEC_GOTENT
5171 || XINT (y, 1) == UNSPEC_PLT))
5172 y = XVECEXP (y, 0, 0);
5173 else
5174 return orig_x;
5175 }
5176 else
5177 return orig_x;
5178
5179 if (GET_MODE (orig_x) != Pmode)
5180 {
5181 if (GET_MODE (orig_x) == BLKmode)
5182 return orig_x;
5183 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5184 if (y == NULL_RTX)
5185 return orig_x;
5186 }
5187 return y;
5188 }
5189
5190 /* Output operand OP to stdio stream FILE.
5191 OP is an address (register + offset) which is not used to address data;
5192 instead the rightmost bits are interpreted as the value. */
5193
5194 static void
5195 print_shift_count_operand (FILE *file, rtx op)
5196 {
5197 HOST_WIDE_INT offset;
5198 rtx base;
5199
5200 /* Extract base register and offset. */
5201 if (!s390_decompose_shift_count (op, &base, &offset))
5202 gcc_unreachable ();
5203
5204 /* Sanity check. */
5205 if (base)
5206 {
5207 gcc_assert (GET_CODE (base) == REG);
5208 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5209 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5210 }
5211
5212 /* Offsets are constricted to twelve bits. */
5213 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5214 if (base)
5215 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5216 }
5217
5218 /* See 'get_some_local_dynamic_name'. */
5219
5220 static int
5221 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5222 {
5223 rtx x = *px;
5224
5225 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5226 {
5227 x = get_pool_constant (x);
5228 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5229 }
5230
5231 if (GET_CODE (x) == SYMBOL_REF
5232 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5233 {
5234 cfun->machine->some_ld_name = XSTR (x, 0);
5235 return 1;
5236 }
5237
5238 return 0;
5239 }
5240
5241 /* Locate some local-dynamic symbol still in use by this function
5242 so that we can print its name in local-dynamic base patterns. */
5243
5244 static const char *
5245 get_some_local_dynamic_name (void)
5246 {
5247 rtx insn;
5248
5249 if (cfun->machine->some_ld_name)
5250 return cfun->machine->some_ld_name;
5251
5252 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5253 if (INSN_P (insn)
5254 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5255 return cfun->machine->some_ld_name;
5256
5257 gcc_unreachable ();
5258 }
5259
5260 /* Output machine-dependent UNSPECs occurring in address constant X
5261 in assembler syntax to stdio stream FILE. Returns true if the
5262 constant X could be recognized, false otherwise. */
5263
5264 static bool
5265 s390_output_addr_const_extra (FILE *file, rtx x)
5266 {
5267 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5268 switch (XINT (x, 1))
5269 {
5270 case UNSPEC_GOTENT:
5271 output_addr_const (file, XVECEXP (x, 0, 0));
5272 fprintf (file, "@GOTENT");
5273 return true;
5274 case UNSPEC_GOT:
5275 output_addr_const (file, XVECEXP (x, 0, 0));
5276 fprintf (file, "@GOT");
5277 return true;
5278 case UNSPEC_GOTOFF:
5279 output_addr_const (file, XVECEXP (x, 0, 0));
5280 fprintf (file, "@GOTOFF");
5281 return true;
5282 case UNSPEC_PLT:
5283 output_addr_const (file, XVECEXP (x, 0, 0));
5284 fprintf (file, "@PLT");
5285 return true;
5286 case UNSPEC_PLTOFF:
5287 output_addr_const (file, XVECEXP (x, 0, 0));
5288 fprintf (file, "@PLTOFF");
5289 return true;
5290 case UNSPEC_TLSGD:
5291 output_addr_const (file, XVECEXP (x, 0, 0));
5292 fprintf (file, "@TLSGD");
5293 return true;
5294 case UNSPEC_TLSLDM:
5295 assemble_name (file, get_some_local_dynamic_name ());
5296 fprintf (file, "@TLSLDM");
5297 return true;
5298 case UNSPEC_DTPOFF:
5299 output_addr_const (file, XVECEXP (x, 0, 0));
5300 fprintf (file, "@DTPOFF");
5301 return true;
5302 case UNSPEC_NTPOFF:
5303 output_addr_const (file, XVECEXP (x, 0, 0));
5304 fprintf (file, "@NTPOFF");
5305 return true;
5306 case UNSPEC_GOTNTPOFF:
5307 output_addr_const (file, XVECEXP (x, 0, 0));
5308 fprintf (file, "@GOTNTPOFF");
5309 return true;
5310 case UNSPEC_INDNTPOFF:
5311 output_addr_const (file, XVECEXP (x, 0, 0));
5312 fprintf (file, "@INDNTPOFF");
5313 return true;
5314 }
5315
5316 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5317 switch (XINT (x, 1))
5318 {
5319 case UNSPEC_POOL_OFFSET:
5320 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5321 output_addr_const (file, x);
5322 return true;
5323 }
5324 return false;
5325 }
5326
5327 /* Output address operand ADDR in assembler syntax to
5328 stdio stream FILE. */
5329
5330 void
5331 print_operand_address (FILE *file, rtx addr)
5332 {
5333 struct s390_address ad;
5334
5335 if (s390_loadrelative_operand_p (addr))
5336 {
5337 if (!TARGET_Z10)
5338 {
5339 output_operand_lossage ("symbolic memory references are "
5340 "only supported on z10 or later");
5341 return;
5342 }
5343 output_addr_const (file, addr);
5344 return;
5345 }
5346
5347 if (!s390_decompose_address (addr, &ad)
5348 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5349 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5350 output_operand_lossage ("cannot decompose address");
5351
5352 if (ad.disp)
5353 output_addr_const (file, ad.disp);
5354 else
5355 fprintf (file, "0");
5356
5357 if (ad.base && ad.indx)
5358 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5359 reg_names[REGNO (ad.base)]);
5360 else if (ad.base)
5361 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5362 }
5363
5364 /* Output operand X in assembler syntax to stdio stream FILE.
5365 CODE specified the format flag. The following format flags
5366 are recognized:
5367
5368 'C': print opcode suffix for branch condition.
5369 'D': print opcode suffix for inverse branch condition.
5370 'E': print opcode suffix for branch on index instruction.
5371 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5372 'G': print the size of the operand in bytes.
5373 'O': print only the displacement of a memory reference.
5374 'R': print only the base register of a memory reference.
5375 'S': print S-type memory reference (base+displacement).
5376 'N': print the second word of a DImode operand.
5377 'M': print the second word of a TImode operand.
5378 'Y': print shift count operand.
5379
5380 'b': print integer X as if it's an unsigned byte.
5381 'c': print integer X as if it's an signed byte.
5382 'x': print integer X as if it's an unsigned halfword.
5383 'h': print integer X as if it's a signed halfword.
5384 'i': print the first nonzero HImode part of X.
5385 'j': print the first HImode part unequal to -1 of X.
5386 'k': print the first nonzero SImode part of X.
5387 'm': print the first SImode part unequal to -1 of X.
5388 'o': print integer X as if it's an unsigned 32bit word. */
5389
5390 void
5391 print_operand (FILE *file, rtx x, int code)
5392 {
5393 switch (code)
5394 {
5395 case 'C':
5396 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5397 return;
5398
5399 case 'D':
5400 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5401 return;
5402
5403 case 'E':
5404 if (GET_CODE (x) == LE)
5405 fprintf (file, "l");
5406 else if (GET_CODE (x) == GT)
5407 fprintf (file, "h");
5408 else
5409 output_operand_lossage ("invalid comparison operator "
5410 "for 'E' output modifier");
5411 return;
5412
5413 case 'J':
5414 if (GET_CODE (x) == SYMBOL_REF)
5415 {
5416 fprintf (file, "%s", ":tls_load:");
5417 output_addr_const (file, x);
5418 }
5419 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5420 {
5421 fprintf (file, "%s", ":tls_gdcall:");
5422 output_addr_const (file, XVECEXP (x, 0, 0));
5423 }
5424 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5425 {
5426 fprintf (file, "%s", ":tls_ldcall:");
5427 assemble_name (file, get_some_local_dynamic_name ());
5428 }
5429 else
5430 output_operand_lossage ("invalid reference for 'J' output modifier");
5431 return;
5432
5433 case 'G':
5434 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5435 return;
5436
5437 case 'O':
5438 {
5439 struct s390_address ad;
5440 int ret;
5441
5442 if (!MEM_P (x))
5443 {
5444 output_operand_lossage ("memory reference expected for "
5445 "'O' output modifier");
5446 return;
5447 }
5448
5449 ret = s390_decompose_address (XEXP (x, 0), &ad);
5450
5451 if (!ret
5452 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5453 || ad.indx)
5454 {
5455 output_operand_lossage ("invalid address for 'O' output modifier");
5456 return;
5457 }
5458
5459 if (ad.disp)
5460 output_addr_const (file, ad.disp);
5461 else
5462 fprintf (file, "0");
5463 }
5464 return;
5465
5466 case 'R':
5467 {
5468 struct s390_address ad;
5469 int ret;
5470
5471 if (!MEM_P (x))
5472 {
5473 output_operand_lossage ("memory reference expected for "
5474 "'R' output modifier");
5475 return;
5476 }
5477
5478 ret = s390_decompose_address (XEXP (x, 0), &ad);
5479
5480 if (!ret
5481 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5482 || ad.indx)
5483 {
5484 output_operand_lossage ("invalid address for 'R' output modifier");
5485 return;
5486 }
5487
5488 if (ad.base)
5489 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5490 else
5491 fprintf (file, "0");
5492 }
5493 return;
5494
5495 case 'S':
5496 {
5497 struct s390_address ad;
5498 int ret;
5499
5500 if (!MEM_P (x))
5501 {
5502 output_operand_lossage ("memory reference expected for "
5503 "'S' output modifier");
5504 return;
5505 }
5506 ret = s390_decompose_address (XEXP (x, 0), &ad);
5507
5508 if (!ret
5509 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5510 || ad.indx)
5511 {
5512 output_operand_lossage ("invalid address for 'S' output modifier");
5513 return;
5514 }
5515
5516 if (ad.disp)
5517 output_addr_const (file, ad.disp);
5518 else
5519 fprintf (file, "0");
5520
5521 if (ad.base)
5522 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5523 }
5524 return;
5525
5526 case 'N':
5527 if (GET_CODE (x) == REG)
5528 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5529 else if (GET_CODE (x) == MEM)
5530 x = change_address (x, VOIDmode,
5531 plus_constant (Pmode, XEXP (x, 0), 4));
5532 else
5533 output_operand_lossage ("register or memory expression expected "
5534 "for 'N' output modifier");
5535 break;
5536
5537 case 'M':
5538 if (GET_CODE (x) == REG)
5539 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5540 else if (GET_CODE (x) == MEM)
5541 x = change_address (x, VOIDmode,
5542 plus_constant (Pmode, XEXP (x, 0), 8));
5543 else
5544 output_operand_lossage ("register or memory expression expected "
5545 "for 'M' output modifier");
5546 break;
5547
5548 case 'Y':
5549 print_shift_count_operand (file, x);
5550 return;
5551 }
5552
5553 switch (GET_CODE (x))
5554 {
5555 case REG:
5556 fprintf (file, "%s", reg_names[REGNO (x)]);
5557 break;
5558
5559 case MEM:
5560 output_address (XEXP (x, 0));
5561 break;
5562
5563 case CONST:
5564 case CODE_LABEL:
5565 case LABEL_REF:
5566 case SYMBOL_REF:
5567 output_addr_const (file, x);
5568 break;
5569
5570 case CONST_INT:
5571 if (code == 'b')
5572 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5573 else if (code == 'c')
5574 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5575 else if (code == 'x')
5576 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5577 else if (code == 'h')
5578 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5579 else if (code == 'i')
5580 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5581 s390_extract_part (x, HImode, 0));
5582 else if (code == 'j')
5583 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5584 s390_extract_part (x, HImode, -1));
5585 else if (code == 'k')
5586 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5587 s390_extract_part (x, SImode, 0));
5588 else if (code == 'm')
5589 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5590 s390_extract_part (x, SImode, -1));
5591 else if (code == 'o')
5592 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5593 else
5594 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5595 break;
5596
5597 case CONST_DOUBLE:
5598 gcc_assert (GET_MODE (x) == VOIDmode);
5599 if (code == 'b')
5600 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5601 else if (code == 'x')
5602 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5603 else if (code == 'h')
5604 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5605 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5606 else
5607 {
5608 if (code == 0)
5609 output_operand_lossage ("invalid constant - try using "
5610 "an output modifier");
5611 else
5612 output_operand_lossage ("invalid constant for output modifier '%c'",
5613 code);
5614 }
5615 break;
5616
5617 default:
5618 if (code == 0)
5619 output_operand_lossage ("invalid expression - try using "
5620 "an output modifier");
5621 else
5622 output_operand_lossage ("invalid expression for output "
5623 "modifier '%c'", code);
5624 break;
5625 }
5626 }
5627
5628 /* Target hook for assembling integer objects. We need to define it
5629 here to work a round a bug in some versions of GAS, which couldn't
5630 handle values smaller than INT_MIN when printed in decimal. */
5631
5632 static bool
5633 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5634 {
5635 if (size == 8 && aligned_p
5636 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5637 {
5638 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5639 INTVAL (x));
5640 return true;
5641 }
5642 return default_assemble_integer (x, size, aligned_p);
5643 }
5644
5645 /* Returns true if register REGNO is used for forming
5646 a memory address in expression X. */
5647
5648 static bool
5649 reg_used_in_mem_p (int regno, rtx x)
5650 {
5651 enum rtx_code code = GET_CODE (x);
5652 int i, j;
5653 const char *fmt;
5654
5655 if (code == MEM)
5656 {
5657 if (refers_to_regno_p (regno, regno+1,
5658 XEXP (x, 0), 0))
5659 return true;
5660 }
5661 else if (code == SET
5662 && GET_CODE (SET_DEST (x)) == PC)
5663 {
5664 if (refers_to_regno_p (regno, regno+1,
5665 SET_SRC (x), 0))
5666 return true;
5667 }
5668
5669 fmt = GET_RTX_FORMAT (code);
5670 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5671 {
5672 if (fmt[i] == 'e'
5673 && reg_used_in_mem_p (regno, XEXP (x, i)))
5674 return true;
5675
5676 else if (fmt[i] == 'E')
5677 for (j = 0; j < XVECLEN (x, i); j++)
5678 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5679 return true;
5680 }
5681 return false;
5682 }
5683
5684 /* Returns true if expression DEP_RTX sets an address register
5685 used by instruction INSN to address memory. */
5686
5687 static bool
5688 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5689 {
5690 rtx target, pat;
5691
5692 if (GET_CODE (dep_rtx) == INSN)
5693 dep_rtx = PATTERN (dep_rtx);
5694
5695 if (GET_CODE (dep_rtx) == SET)
5696 {
5697 target = SET_DEST (dep_rtx);
5698 if (GET_CODE (target) == STRICT_LOW_PART)
5699 target = XEXP (target, 0);
5700 while (GET_CODE (target) == SUBREG)
5701 target = SUBREG_REG (target);
5702
5703 if (GET_CODE (target) == REG)
5704 {
5705 int regno = REGNO (target);
5706
5707 if (s390_safe_attr_type (insn) == TYPE_LA)
5708 {
5709 pat = PATTERN (insn);
5710 if (GET_CODE (pat) == PARALLEL)
5711 {
5712 gcc_assert (XVECLEN (pat, 0) == 2);
5713 pat = XVECEXP (pat, 0, 0);
5714 }
5715 gcc_assert (GET_CODE (pat) == SET);
5716 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5717 }
5718 else if (get_attr_atype (insn) == ATYPE_AGEN)
5719 return reg_used_in_mem_p (regno, PATTERN (insn));
5720 }
5721 }
5722 return false;
5723 }
5724
5725 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5726
5727 int
5728 s390_agen_dep_p (rtx dep_insn, rtx insn)
5729 {
5730 rtx dep_rtx = PATTERN (dep_insn);
5731 int i;
5732
5733 if (GET_CODE (dep_rtx) == SET
5734 && addr_generation_dependency_p (dep_rtx, insn))
5735 return 1;
5736 else if (GET_CODE (dep_rtx) == PARALLEL)
5737 {
5738 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5739 {
5740 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5741 return 1;
5742 }
5743 }
5744 return 0;
5745 }
5746
5747
5748 /* A C statement (sans semicolon) to update the integer scheduling priority
5749 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5750 reduce the priority to execute INSN later. Do not define this macro if
5751 you do not need to adjust the scheduling priorities of insns.
5752
5753 A STD instruction should be scheduled earlier,
5754 in order to use the bypass. */
5755 static int
5756 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5757 {
5758 if (! INSN_P (insn))
5759 return priority;
5760
5761 if (s390_tune != PROCESSOR_2084_Z990
5762 && s390_tune != PROCESSOR_2094_Z9_109
5763 && s390_tune != PROCESSOR_2097_Z10
5764 && s390_tune != PROCESSOR_2817_Z196
5765 && s390_tune != PROCESSOR_2827_ZEC12)
5766 return priority;
5767
5768 switch (s390_safe_attr_type (insn))
5769 {
5770 case TYPE_FSTOREDF:
5771 case TYPE_FSTORESF:
5772 priority = priority << 3;
5773 break;
5774 case TYPE_STORE:
5775 case TYPE_STM:
5776 priority = priority << 1;
5777 break;
5778 default:
5779 break;
5780 }
5781 return priority;
5782 }
5783
5784
5785 /* The number of instructions that can be issued per cycle. */
5786
5787 static int
5788 s390_issue_rate (void)
5789 {
5790 switch (s390_tune)
5791 {
5792 case PROCESSOR_2084_Z990:
5793 case PROCESSOR_2094_Z9_109:
5794 case PROCESSOR_2817_Z196:
5795 return 3;
5796 case PROCESSOR_2097_Z10:
5797 case PROCESSOR_2827_ZEC12:
5798 return 2;
5799 default:
5800 return 1;
5801 }
5802 }
5803
5804 static int
5805 s390_first_cycle_multipass_dfa_lookahead (void)
5806 {
5807 return 4;
5808 }
5809
5810 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5811 Fix up MEMs as required. */
5812
5813 static void
5814 annotate_constant_pool_refs (rtx *x)
5815 {
5816 int i, j;
5817 const char *fmt;
5818
5819 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5820 || !CONSTANT_POOL_ADDRESS_P (*x));
5821
5822 /* Literal pool references can only occur inside a MEM ... */
5823 if (GET_CODE (*x) == MEM)
5824 {
5825 rtx memref = XEXP (*x, 0);
5826
5827 if (GET_CODE (memref) == SYMBOL_REF
5828 && CONSTANT_POOL_ADDRESS_P (memref))
5829 {
5830 rtx base = cfun->machine->base_reg;
5831 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5832 UNSPEC_LTREF);
5833
5834 *x = replace_equiv_address (*x, addr);
5835 return;
5836 }
5837
5838 if (GET_CODE (memref) == CONST
5839 && GET_CODE (XEXP (memref, 0)) == PLUS
5840 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5841 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5842 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5843 {
5844 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5845 rtx sym = XEXP (XEXP (memref, 0), 0);
5846 rtx base = cfun->machine->base_reg;
5847 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5848 UNSPEC_LTREF);
5849
5850 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5851 return;
5852 }
5853 }
5854
5855 /* ... or a load-address type pattern. */
5856 if (GET_CODE (*x) == SET)
5857 {
5858 rtx addrref = SET_SRC (*x);
5859
5860 if (GET_CODE (addrref) == SYMBOL_REF
5861 && CONSTANT_POOL_ADDRESS_P (addrref))
5862 {
5863 rtx base = cfun->machine->base_reg;
5864 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5865 UNSPEC_LTREF);
5866
5867 SET_SRC (*x) = addr;
5868 return;
5869 }
5870
5871 if (GET_CODE (addrref) == CONST
5872 && GET_CODE (XEXP (addrref, 0)) == PLUS
5873 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5874 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5875 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5876 {
5877 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5878 rtx sym = XEXP (XEXP (addrref, 0), 0);
5879 rtx base = cfun->machine->base_reg;
5880 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5881 UNSPEC_LTREF);
5882
5883 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5884 return;
5885 }
5886 }
5887
5888 /* Annotate LTREL_BASE as well. */
5889 if (GET_CODE (*x) == UNSPEC
5890 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5891 {
5892 rtx base = cfun->machine->base_reg;
5893 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5894 UNSPEC_LTREL_BASE);
5895 return;
5896 }
5897
5898 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5899 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5900 {
5901 if (fmt[i] == 'e')
5902 {
5903 annotate_constant_pool_refs (&XEXP (*x, i));
5904 }
5905 else if (fmt[i] == 'E')
5906 {
5907 for (j = 0; j < XVECLEN (*x, i); j++)
5908 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5909 }
5910 }
5911 }
5912
5913 /* Split all branches that exceed the maximum distance.
5914 Returns true if this created a new literal pool entry. */
5915
5916 static int
5917 s390_split_branches (void)
5918 {
5919 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5920 int new_literal = 0, ret;
5921 rtx insn, pat, tmp, target;
5922 rtx *label;
5923
5924 /* We need correct insn addresses. */
5925
5926 shorten_branches (get_insns ());
5927
5928 /* Find all branches that exceed 64KB, and split them. */
5929
5930 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5931 {
5932 if (GET_CODE (insn) != JUMP_INSN)
5933 continue;
5934
5935 pat = PATTERN (insn);
5936 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5937 pat = XVECEXP (pat, 0, 0);
5938 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5939 continue;
5940
5941 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5942 {
5943 label = &SET_SRC (pat);
5944 }
5945 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5946 {
5947 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5948 label = &XEXP (SET_SRC (pat), 1);
5949 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5950 label = &XEXP (SET_SRC (pat), 2);
5951 else
5952 continue;
5953 }
5954 else
5955 continue;
5956
5957 if (get_attr_length (insn) <= 4)
5958 continue;
5959
5960 /* We are going to use the return register as scratch register,
5961 make sure it will be saved/restored by the prologue/epilogue. */
5962 cfun_frame_layout.save_return_addr_p = 1;
5963
5964 if (!flag_pic)
5965 {
5966 new_literal = 1;
5967 tmp = force_const_mem (Pmode, *label);
5968 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5969 INSN_ADDRESSES_NEW (tmp, -1);
5970 annotate_constant_pool_refs (&PATTERN (tmp));
5971
5972 target = temp_reg;
5973 }
5974 else
5975 {
5976 new_literal = 1;
5977 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5978 UNSPEC_LTREL_OFFSET);
5979 target = gen_rtx_CONST (Pmode, target);
5980 target = force_const_mem (Pmode, target);
5981 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5982 INSN_ADDRESSES_NEW (tmp, -1);
5983 annotate_constant_pool_refs (&PATTERN (tmp));
5984
5985 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5986 cfun->machine->base_reg),
5987 UNSPEC_LTREL_BASE);
5988 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5989 }
5990
5991 ret = validate_change (insn, label, target, 0);
5992 gcc_assert (ret);
5993 }
5994
5995 return new_literal;
5996 }
5997
5998
5999 /* Find an annotated literal pool symbol referenced in RTX X,
6000 and store it at REF. Will abort if X contains references to
6001 more than one such pool symbol; multiple references to the same
6002 symbol are allowed, however.
6003
6004 The rtx pointed to by REF must be initialized to NULL_RTX
6005 by the caller before calling this routine. */
6006
6007 static void
6008 find_constant_pool_ref (rtx x, rtx *ref)
6009 {
6010 int i, j;
6011 const char *fmt;
6012
6013 /* Ignore LTREL_BASE references. */
6014 if (GET_CODE (x) == UNSPEC
6015 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6016 return;
6017 /* Likewise POOL_ENTRY insns. */
6018 if (GET_CODE (x) == UNSPEC_VOLATILE
6019 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6020 return;
6021
6022 gcc_assert (GET_CODE (x) != SYMBOL_REF
6023 || !CONSTANT_POOL_ADDRESS_P (x));
6024
6025 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
6026 {
6027 rtx sym = XVECEXP (x, 0, 0);
6028 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6029 && CONSTANT_POOL_ADDRESS_P (sym));
6030
6031 if (*ref == NULL_RTX)
6032 *ref = sym;
6033 else
6034 gcc_assert (*ref == sym);
6035
6036 return;
6037 }
6038
6039 fmt = GET_RTX_FORMAT (GET_CODE (x));
6040 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6041 {
6042 if (fmt[i] == 'e')
6043 {
6044 find_constant_pool_ref (XEXP (x, i), ref);
6045 }
6046 else if (fmt[i] == 'E')
6047 {
6048 for (j = 0; j < XVECLEN (x, i); j++)
6049 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6050 }
6051 }
6052 }
6053
6054 /* Replace every reference to the annotated literal pool
6055 symbol REF in X by its base plus OFFSET. */
6056
6057 static void
6058 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
6059 {
6060 int i, j;
6061 const char *fmt;
6062
6063 gcc_assert (*x != ref);
6064
6065 if (GET_CODE (*x) == UNSPEC
6066 && XINT (*x, 1) == UNSPEC_LTREF
6067 && XVECEXP (*x, 0, 0) == ref)
6068 {
6069 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6070 return;
6071 }
6072
6073 if (GET_CODE (*x) == PLUS
6074 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6075 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6076 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6077 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
6078 {
6079 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
6080 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
6081 return;
6082 }
6083
6084 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6085 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6086 {
6087 if (fmt[i] == 'e')
6088 {
6089 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
6090 }
6091 else if (fmt[i] == 'E')
6092 {
6093 for (j = 0; j < XVECLEN (*x, i); j++)
6094 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
6095 }
6096 }
6097 }
6098
6099 /* Check whether X contains an UNSPEC_LTREL_BASE.
6100 Return its constant pool symbol if found, NULL_RTX otherwise. */
6101
6102 static rtx
6103 find_ltrel_base (rtx x)
6104 {
6105 int i, j;
6106 const char *fmt;
6107
6108 if (GET_CODE (x) == UNSPEC
6109 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6110 return XVECEXP (x, 0, 0);
6111
6112 fmt = GET_RTX_FORMAT (GET_CODE (x));
6113 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6114 {
6115 if (fmt[i] == 'e')
6116 {
6117 rtx fnd = find_ltrel_base (XEXP (x, i));
6118 if (fnd)
6119 return fnd;
6120 }
6121 else if (fmt[i] == 'E')
6122 {
6123 for (j = 0; j < XVECLEN (x, i); j++)
6124 {
6125 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6126 if (fnd)
6127 return fnd;
6128 }
6129 }
6130 }
6131
6132 return NULL_RTX;
6133 }
6134
6135 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6136
6137 static void
6138 replace_ltrel_base (rtx *x)
6139 {
6140 int i, j;
6141 const char *fmt;
6142
6143 if (GET_CODE (*x) == UNSPEC
6144 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6145 {
6146 *x = XVECEXP (*x, 0, 1);
6147 return;
6148 }
6149
6150 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6151 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6152 {
6153 if (fmt[i] == 'e')
6154 {
6155 replace_ltrel_base (&XEXP (*x, i));
6156 }
6157 else if (fmt[i] == 'E')
6158 {
6159 for (j = 0; j < XVECLEN (*x, i); j++)
6160 replace_ltrel_base (&XVECEXP (*x, i, j));
6161 }
6162 }
6163 }
6164
6165
6166 /* We keep a list of constants which we have to add to internal
6167 constant tables in the middle of large functions. */
6168
6169 #define NR_C_MODES 11
6170 enum machine_mode constant_modes[NR_C_MODES] =
6171 {
6172 TFmode, TImode, TDmode,
6173 DFmode, DImode, DDmode,
6174 SFmode, SImode, SDmode,
6175 HImode,
6176 QImode
6177 };
6178
6179 struct constant
6180 {
6181 struct constant *next;
6182 rtx value;
6183 rtx label;
6184 };
6185
6186 struct constant_pool
6187 {
6188 struct constant_pool *next;
6189 rtx first_insn;
6190 rtx pool_insn;
6191 bitmap insns;
6192 rtx emit_pool_after;
6193
6194 struct constant *constants[NR_C_MODES];
6195 struct constant *execute;
6196 rtx label;
6197 int size;
6198 };
6199
6200 /* Allocate new constant_pool structure. */
6201
6202 static struct constant_pool *
6203 s390_alloc_pool (void)
6204 {
6205 struct constant_pool *pool;
6206 int i;
6207
6208 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6209 pool->next = NULL;
6210 for (i = 0; i < NR_C_MODES; i++)
6211 pool->constants[i] = NULL;
6212
6213 pool->execute = NULL;
6214 pool->label = gen_label_rtx ();
6215 pool->first_insn = NULL_RTX;
6216 pool->pool_insn = NULL_RTX;
6217 pool->insns = BITMAP_ALLOC (NULL);
6218 pool->size = 0;
6219 pool->emit_pool_after = NULL_RTX;
6220
6221 return pool;
6222 }
6223
6224 /* Create new constant pool covering instructions starting at INSN
6225 and chain it to the end of POOL_LIST. */
6226
6227 static struct constant_pool *
6228 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6229 {
6230 struct constant_pool *pool, **prev;
6231
6232 pool = s390_alloc_pool ();
6233 pool->first_insn = insn;
6234
6235 for (prev = pool_list; *prev; prev = &(*prev)->next)
6236 ;
6237 *prev = pool;
6238
6239 return pool;
6240 }
6241
6242 /* End range of instructions covered by POOL at INSN and emit
6243 placeholder insn representing the pool. */
6244
6245 static void
6246 s390_end_pool (struct constant_pool *pool, rtx insn)
6247 {
6248 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6249
6250 if (!insn)
6251 insn = get_last_insn ();
6252
6253 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6254 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6255 }
6256
6257 /* Add INSN to the list of insns covered by POOL. */
6258
6259 static void
6260 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6261 {
6262 bitmap_set_bit (pool->insns, INSN_UID (insn));
6263 }
6264
6265 /* Return pool out of POOL_LIST that covers INSN. */
6266
6267 static struct constant_pool *
6268 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6269 {
6270 struct constant_pool *pool;
6271
6272 for (pool = pool_list; pool; pool = pool->next)
6273 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6274 break;
6275
6276 return pool;
6277 }
6278
6279 /* Add constant VAL of mode MODE to the constant pool POOL. */
6280
6281 static void
6282 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6283 {
6284 struct constant *c;
6285 int i;
6286
6287 for (i = 0; i < NR_C_MODES; i++)
6288 if (constant_modes[i] == mode)
6289 break;
6290 gcc_assert (i != NR_C_MODES);
6291
6292 for (c = pool->constants[i]; c != NULL; c = c->next)
6293 if (rtx_equal_p (val, c->value))
6294 break;
6295
6296 if (c == NULL)
6297 {
6298 c = (struct constant *) xmalloc (sizeof *c);
6299 c->value = val;
6300 c->label = gen_label_rtx ();
6301 c->next = pool->constants[i];
6302 pool->constants[i] = c;
6303 pool->size += GET_MODE_SIZE (mode);
6304 }
6305 }
6306
6307 /* Return an rtx that represents the offset of X from the start of
6308 pool POOL. */
6309
6310 static rtx
6311 s390_pool_offset (struct constant_pool *pool, rtx x)
6312 {
6313 rtx label;
6314
6315 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6316 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6317 UNSPEC_POOL_OFFSET);
6318 return gen_rtx_CONST (GET_MODE (x), x);
6319 }
6320
6321 /* Find constant VAL of mode MODE in the constant pool POOL.
6322 Return an RTX describing the distance from the start of
6323 the pool to the location of the new constant. */
6324
6325 static rtx
6326 s390_find_constant (struct constant_pool *pool, rtx val,
6327 enum machine_mode mode)
6328 {
6329 struct constant *c;
6330 int i;
6331
6332 for (i = 0; i < NR_C_MODES; i++)
6333 if (constant_modes[i] == mode)
6334 break;
6335 gcc_assert (i != NR_C_MODES);
6336
6337 for (c = pool->constants[i]; c != NULL; c = c->next)
6338 if (rtx_equal_p (val, c->value))
6339 break;
6340
6341 gcc_assert (c);
6342
6343 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6344 }
6345
6346 /* Check whether INSN is an execute. Return the label_ref to its
6347 execute target template if so, NULL_RTX otherwise. */
6348
6349 static rtx
6350 s390_execute_label (rtx insn)
6351 {
6352 if (GET_CODE (insn) == INSN
6353 && GET_CODE (PATTERN (insn)) == PARALLEL
6354 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6355 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6356 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6357
6358 return NULL_RTX;
6359 }
6360
6361 /* Add execute target for INSN to the constant pool POOL. */
6362
6363 static void
6364 s390_add_execute (struct constant_pool *pool, rtx insn)
6365 {
6366 struct constant *c;
6367
6368 for (c = pool->execute; c != NULL; c = c->next)
6369 if (INSN_UID (insn) == INSN_UID (c->value))
6370 break;
6371
6372 if (c == NULL)
6373 {
6374 c = (struct constant *) xmalloc (sizeof *c);
6375 c->value = insn;
6376 c->label = gen_label_rtx ();
6377 c->next = pool->execute;
6378 pool->execute = c;
6379 pool->size += 6;
6380 }
6381 }
6382
6383 /* Find execute target for INSN in the constant pool POOL.
6384 Return an RTX describing the distance from the start of
6385 the pool to the location of the execute target. */
6386
6387 static rtx
6388 s390_find_execute (struct constant_pool *pool, rtx insn)
6389 {
6390 struct constant *c;
6391
6392 for (c = pool->execute; c != NULL; c = c->next)
6393 if (INSN_UID (insn) == INSN_UID (c->value))
6394 break;
6395
6396 gcc_assert (c);
6397
6398 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6399 }
6400
6401 /* For an execute INSN, extract the execute target template. */
6402
6403 static rtx
6404 s390_execute_target (rtx insn)
6405 {
6406 rtx pattern = PATTERN (insn);
6407 gcc_assert (s390_execute_label (insn));
6408
6409 if (XVECLEN (pattern, 0) == 2)
6410 {
6411 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6412 }
6413 else
6414 {
6415 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6416 int i;
6417
6418 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6419 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6420
6421 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6422 }
6423
6424 return pattern;
6425 }
6426
6427 /* Indicate that INSN cannot be duplicated. This is the case for
6428 execute insns that carry a unique label. */
6429
6430 static bool
6431 s390_cannot_copy_insn_p (rtx insn)
6432 {
6433 rtx label = s390_execute_label (insn);
6434 return label && label != const0_rtx;
6435 }
6436
6437 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6438 do not emit the pool base label. */
6439
6440 static void
6441 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6442 {
6443 struct constant *c;
6444 rtx insn = pool->pool_insn;
6445 int i;
6446
6447 /* Switch to rodata section. */
6448 if (TARGET_CPU_ZARCH)
6449 {
6450 insn = emit_insn_after (gen_pool_section_start (), insn);
6451 INSN_ADDRESSES_NEW (insn, -1);
6452 }
6453
6454 /* Ensure minimum pool alignment. */
6455 if (TARGET_CPU_ZARCH)
6456 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6457 else
6458 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6459 INSN_ADDRESSES_NEW (insn, -1);
6460
6461 /* Emit pool base label. */
6462 if (!remote_label)
6463 {
6464 insn = emit_label_after (pool->label, insn);
6465 INSN_ADDRESSES_NEW (insn, -1);
6466 }
6467
6468 /* Dump constants in descending alignment requirement order,
6469 ensuring proper alignment for every constant. */
6470 for (i = 0; i < NR_C_MODES; i++)
6471 for (c = pool->constants[i]; c; c = c->next)
6472 {
6473 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6474 rtx value = copy_rtx (c->value);
6475 if (GET_CODE (value) == CONST
6476 && GET_CODE (XEXP (value, 0)) == UNSPEC
6477 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6478 && XVECLEN (XEXP (value, 0), 0) == 1)
6479 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6480
6481 insn = emit_label_after (c->label, insn);
6482 INSN_ADDRESSES_NEW (insn, -1);
6483
6484 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6485 gen_rtvec (1, value),
6486 UNSPECV_POOL_ENTRY);
6487 insn = emit_insn_after (value, insn);
6488 INSN_ADDRESSES_NEW (insn, -1);
6489 }
6490
6491 /* Ensure minimum alignment for instructions. */
6492 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6493 INSN_ADDRESSES_NEW (insn, -1);
6494
6495 /* Output in-pool execute template insns. */
6496 for (c = pool->execute; c; c = c->next)
6497 {
6498 insn = emit_label_after (c->label, insn);
6499 INSN_ADDRESSES_NEW (insn, -1);
6500
6501 insn = emit_insn_after (s390_execute_target (c->value), insn);
6502 INSN_ADDRESSES_NEW (insn, -1);
6503 }
6504
6505 /* Switch back to previous section. */
6506 if (TARGET_CPU_ZARCH)
6507 {
6508 insn = emit_insn_after (gen_pool_section_end (), insn);
6509 INSN_ADDRESSES_NEW (insn, -1);
6510 }
6511
6512 insn = emit_barrier_after (insn);
6513 INSN_ADDRESSES_NEW (insn, -1);
6514
6515 /* Remove placeholder insn. */
6516 remove_insn (pool->pool_insn);
6517 }
6518
6519 /* Free all memory used by POOL. */
6520
6521 static void
6522 s390_free_pool (struct constant_pool *pool)
6523 {
6524 struct constant *c, *next;
6525 int i;
6526
6527 for (i = 0; i < NR_C_MODES; i++)
6528 for (c = pool->constants[i]; c; c = next)
6529 {
6530 next = c->next;
6531 free (c);
6532 }
6533
6534 for (c = pool->execute; c; c = next)
6535 {
6536 next = c->next;
6537 free (c);
6538 }
6539
6540 BITMAP_FREE (pool->insns);
6541 free (pool);
6542 }
6543
6544
6545 /* Collect main literal pool. Return NULL on overflow. */
6546
6547 static struct constant_pool *
6548 s390_mainpool_start (void)
6549 {
6550 struct constant_pool *pool;
6551 rtx insn;
6552
6553 pool = s390_alloc_pool ();
6554
6555 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6556 {
6557 if (GET_CODE (insn) == INSN
6558 && GET_CODE (PATTERN (insn)) == SET
6559 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6560 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6561 {
6562 gcc_assert (!pool->pool_insn);
6563 pool->pool_insn = insn;
6564 }
6565
6566 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6567 {
6568 s390_add_execute (pool, insn);
6569 }
6570 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6571 {
6572 rtx pool_ref = NULL_RTX;
6573 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6574 if (pool_ref)
6575 {
6576 rtx constant = get_pool_constant (pool_ref);
6577 enum machine_mode mode = get_pool_mode (pool_ref);
6578 s390_add_constant (pool, constant, mode);
6579 }
6580 }
6581
6582 /* If hot/cold partitioning is enabled we have to make sure that
6583 the literal pool is emitted in the same section where the
6584 initialization of the literal pool base pointer takes place.
6585 emit_pool_after is only used in the non-overflow case on non
6586 Z cpus where we can emit the literal pool at the end of the
6587 function body within the text section. */
6588 if (NOTE_P (insn)
6589 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6590 && !pool->emit_pool_after)
6591 pool->emit_pool_after = PREV_INSN (insn);
6592 }
6593
6594 gcc_assert (pool->pool_insn || pool->size == 0);
6595
6596 if (pool->size >= 4096)
6597 {
6598 /* We're going to chunkify the pool, so remove the main
6599 pool placeholder insn. */
6600 remove_insn (pool->pool_insn);
6601
6602 s390_free_pool (pool);
6603 pool = NULL;
6604 }
6605
6606 /* If the functions ends with the section where the literal pool
6607 should be emitted set the marker to its end. */
6608 if (pool && !pool->emit_pool_after)
6609 pool->emit_pool_after = get_last_insn ();
6610
6611 return pool;
6612 }
6613
6614 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6615 Modify the current function to output the pool constants as well as
6616 the pool register setup instruction. */
6617
6618 static void
6619 s390_mainpool_finish (struct constant_pool *pool)
6620 {
6621 rtx base_reg = cfun->machine->base_reg;
6622 rtx insn;
6623
6624 /* If the pool is empty, we're done. */
6625 if (pool->size == 0)
6626 {
6627 /* We don't actually need a base register after all. */
6628 cfun->machine->base_reg = NULL_RTX;
6629
6630 if (pool->pool_insn)
6631 remove_insn (pool->pool_insn);
6632 s390_free_pool (pool);
6633 return;
6634 }
6635
6636 /* We need correct insn addresses. */
6637 shorten_branches (get_insns ());
6638
6639 /* On zSeries, we use a LARL to load the pool register. The pool is
6640 located in the .rodata section, so we emit it after the function. */
6641 if (TARGET_CPU_ZARCH)
6642 {
6643 insn = gen_main_base_64 (base_reg, pool->label);
6644 insn = emit_insn_after (insn, pool->pool_insn);
6645 INSN_ADDRESSES_NEW (insn, -1);
6646 remove_insn (pool->pool_insn);
6647
6648 insn = get_last_insn ();
6649 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6650 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6651
6652 s390_dump_pool (pool, 0);
6653 }
6654
6655 /* On S/390, if the total size of the function's code plus literal pool
6656 does not exceed 4096 bytes, we use BASR to set up a function base
6657 pointer, and emit the literal pool at the end of the function. */
6658 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6659 + pool->size + 8 /* alignment slop */ < 4096)
6660 {
6661 insn = gen_main_base_31_small (base_reg, pool->label);
6662 insn = emit_insn_after (insn, pool->pool_insn);
6663 INSN_ADDRESSES_NEW (insn, -1);
6664 remove_insn (pool->pool_insn);
6665
6666 insn = emit_label_after (pool->label, insn);
6667 INSN_ADDRESSES_NEW (insn, -1);
6668
6669 /* emit_pool_after will be set by s390_mainpool_start to the
6670 last insn of the section where the literal pool should be
6671 emitted. */
6672 insn = pool->emit_pool_after;
6673
6674 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6675 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6676
6677 s390_dump_pool (pool, 1);
6678 }
6679
6680 /* Otherwise, we emit an inline literal pool and use BASR to branch
6681 over it, setting up the pool register at the same time. */
6682 else
6683 {
6684 rtx pool_end = gen_label_rtx ();
6685
6686 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6687 insn = emit_jump_insn_after (insn, pool->pool_insn);
6688 JUMP_LABEL (insn) = pool_end;
6689 INSN_ADDRESSES_NEW (insn, -1);
6690 remove_insn (pool->pool_insn);
6691
6692 insn = emit_label_after (pool->label, insn);
6693 INSN_ADDRESSES_NEW (insn, -1);
6694
6695 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6696 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6697
6698 insn = emit_label_after (pool_end, pool->pool_insn);
6699 INSN_ADDRESSES_NEW (insn, -1);
6700
6701 s390_dump_pool (pool, 1);
6702 }
6703
6704
6705 /* Replace all literal pool references. */
6706
6707 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6708 {
6709 if (INSN_P (insn))
6710 replace_ltrel_base (&PATTERN (insn));
6711
6712 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6713 {
6714 rtx addr, pool_ref = NULL_RTX;
6715 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6716 if (pool_ref)
6717 {
6718 if (s390_execute_label (insn))
6719 addr = s390_find_execute (pool, insn);
6720 else
6721 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6722 get_pool_mode (pool_ref));
6723
6724 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6725 INSN_CODE (insn) = -1;
6726 }
6727 }
6728 }
6729
6730
6731 /* Free the pool. */
6732 s390_free_pool (pool);
6733 }
6734
6735 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6736 We have decided we cannot use this pool, so revert all changes
6737 to the current function that were done by s390_mainpool_start. */
6738 static void
6739 s390_mainpool_cancel (struct constant_pool *pool)
6740 {
6741 /* We didn't actually change the instruction stream, so simply
6742 free the pool memory. */
6743 s390_free_pool (pool);
6744 }
6745
6746
6747 /* Chunkify the literal pool. */
6748
6749 #define S390_POOL_CHUNK_MIN 0xc00
6750 #define S390_POOL_CHUNK_MAX 0xe00
6751
6752 static struct constant_pool *
6753 s390_chunkify_start (void)
6754 {
6755 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6756 int extra_size = 0;
6757 bitmap far_labels;
6758 rtx pending_ltrel = NULL_RTX;
6759 rtx insn;
6760
6761 rtx (*gen_reload_base) (rtx, rtx) =
6762 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6763
6764
6765 /* We need correct insn addresses. */
6766
6767 shorten_branches (get_insns ());
6768
6769 /* Scan all insns and move literals to pool chunks. */
6770
6771 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6772 {
6773 bool section_switch_p = false;
6774
6775 /* Check for pending LTREL_BASE. */
6776 if (INSN_P (insn))
6777 {
6778 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6779 if (ltrel_base)
6780 {
6781 gcc_assert (ltrel_base == pending_ltrel);
6782 pending_ltrel = NULL_RTX;
6783 }
6784 }
6785
6786 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6787 {
6788 if (!curr_pool)
6789 curr_pool = s390_start_pool (&pool_list, insn);
6790
6791 s390_add_execute (curr_pool, insn);
6792 s390_add_pool_insn (curr_pool, insn);
6793 }
6794 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6795 {
6796 rtx pool_ref = NULL_RTX;
6797 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6798 if (pool_ref)
6799 {
6800 rtx constant = get_pool_constant (pool_ref);
6801 enum machine_mode mode = get_pool_mode (pool_ref);
6802
6803 if (!curr_pool)
6804 curr_pool = s390_start_pool (&pool_list, insn);
6805
6806 s390_add_constant (curr_pool, constant, mode);
6807 s390_add_pool_insn (curr_pool, insn);
6808
6809 /* Don't split the pool chunk between a LTREL_OFFSET load
6810 and the corresponding LTREL_BASE. */
6811 if (GET_CODE (constant) == CONST
6812 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6813 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6814 {
6815 gcc_assert (!pending_ltrel);
6816 pending_ltrel = pool_ref;
6817 }
6818 }
6819 }
6820
6821 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6822 {
6823 if (curr_pool)
6824 s390_add_pool_insn (curr_pool, insn);
6825 /* An LTREL_BASE must follow within the same basic block. */
6826 gcc_assert (!pending_ltrel);
6827 }
6828
6829 if (NOTE_P (insn))
6830 switch (NOTE_KIND (insn))
6831 {
6832 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6833 section_switch_p = true;
6834 break;
6835 case NOTE_INSN_VAR_LOCATION:
6836 case NOTE_INSN_CALL_ARG_LOCATION:
6837 continue;
6838 default:
6839 break;
6840 }
6841
6842 if (!curr_pool
6843 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6844 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6845 continue;
6846
6847 if (TARGET_CPU_ZARCH)
6848 {
6849 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6850 continue;
6851
6852 s390_end_pool (curr_pool, NULL_RTX);
6853 curr_pool = NULL;
6854 }
6855 else
6856 {
6857 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6858 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6859 + extra_size;
6860
6861 /* We will later have to insert base register reload insns.
6862 Those will have an effect on code size, which we need to
6863 consider here. This calculation makes rather pessimistic
6864 worst-case assumptions. */
6865 if (GET_CODE (insn) == CODE_LABEL)
6866 extra_size += 6;
6867
6868 if (chunk_size < S390_POOL_CHUNK_MIN
6869 && curr_pool->size < S390_POOL_CHUNK_MIN
6870 && !section_switch_p)
6871 continue;
6872
6873 /* Pool chunks can only be inserted after BARRIERs ... */
6874 if (GET_CODE (insn) == BARRIER)
6875 {
6876 s390_end_pool (curr_pool, insn);
6877 curr_pool = NULL;
6878 extra_size = 0;
6879 }
6880
6881 /* ... so if we don't find one in time, create one. */
6882 else if (chunk_size > S390_POOL_CHUNK_MAX
6883 || curr_pool->size > S390_POOL_CHUNK_MAX
6884 || section_switch_p)
6885 {
6886 rtx label, jump, barrier, next, prev;
6887
6888 if (!section_switch_p)
6889 {
6890 /* We can insert the barrier only after a 'real' insn. */
6891 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6892 continue;
6893 if (get_attr_length (insn) == 0)
6894 continue;
6895 /* Don't separate LTREL_BASE from the corresponding
6896 LTREL_OFFSET load. */
6897 if (pending_ltrel)
6898 continue;
6899 next = insn;
6900 do
6901 {
6902 insn = next;
6903 next = NEXT_INSN (insn);
6904 }
6905 while (next
6906 && NOTE_P (next)
6907 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6908 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6909 }
6910 else
6911 {
6912 gcc_assert (!pending_ltrel);
6913
6914 /* The old pool has to end before the section switch
6915 note in order to make it part of the current
6916 section. */
6917 insn = PREV_INSN (insn);
6918 }
6919
6920 label = gen_label_rtx ();
6921 prev = insn;
6922 if (prev && NOTE_P (prev))
6923 prev = prev_nonnote_insn (prev);
6924 if (prev)
6925 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6926 INSN_LOCATION (prev));
6927 else
6928 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6929 barrier = emit_barrier_after (jump);
6930 insn = emit_label_after (label, barrier);
6931 JUMP_LABEL (jump) = label;
6932 LABEL_NUSES (label) = 1;
6933
6934 INSN_ADDRESSES_NEW (jump, -1);
6935 INSN_ADDRESSES_NEW (barrier, -1);
6936 INSN_ADDRESSES_NEW (insn, -1);
6937
6938 s390_end_pool (curr_pool, barrier);
6939 curr_pool = NULL;
6940 extra_size = 0;
6941 }
6942 }
6943 }
6944
6945 if (curr_pool)
6946 s390_end_pool (curr_pool, NULL_RTX);
6947 gcc_assert (!pending_ltrel);
6948
6949 /* Find all labels that are branched into
6950 from an insn belonging to a different chunk. */
6951
6952 far_labels = BITMAP_ALLOC (NULL);
6953
6954 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6955 {
6956 /* Labels marked with LABEL_PRESERVE_P can be target
6957 of non-local jumps, so we have to mark them.
6958 The same holds for named labels.
6959
6960 Don't do that, however, if it is the label before
6961 a jump table. */
6962
6963 if (GET_CODE (insn) == CODE_LABEL
6964 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6965 {
6966 rtx vec_insn = next_real_insn (insn);
6967 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6968 PATTERN (vec_insn) : NULL_RTX;
6969 if (!vec_pat
6970 || !(GET_CODE (vec_pat) == ADDR_VEC
6971 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6972 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6973 }
6974
6975 /* If we have a direct jump (conditional or unconditional)
6976 or a casesi jump, check all potential targets. */
6977 else if (GET_CODE (insn) == JUMP_INSN)
6978 {
6979 rtx pat = PATTERN (insn);
6980 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6981 pat = XVECEXP (pat, 0, 0);
6982
6983 if (GET_CODE (pat) == SET)
6984 {
6985 rtx label = JUMP_LABEL (insn);
6986 if (label)
6987 {
6988 if (s390_find_pool (pool_list, label)
6989 != s390_find_pool (pool_list, insn))
6990 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6991 }
6992 }
6993 else if (GET_CODE (pat) == PARALLEL
6994 && XVECLEN (pat, 0) == 2
6995 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6996 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6997 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6998 {
6999 /* Find the jump table used by this casesi jump. */
7000 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
7001 rtx vec_insn = next_real_insn (vec_label);
7002 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
7003 PATTERN (vec_insn) : NULL_RTX;
7004 if (vec_pat
7005 && (GET_CODE (vec_pat) == ADDR_VEC
7006 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
7007 {
7008 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7009
7010 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7011 {
7012 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
7013
7014 if (s390_find_pool (pool_list, label)
7015 != s390_find_pool (pool_list, insn))
7016 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7017 }
7018 }
7019 }
7020 }
7021 }
7022
7023 /* Insert base register reload insns before every pool. */
7024
7025 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7026 {
7027 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7028 curr_pool->label);
7029 rtx insn = curr_pool->first_insn;
7030 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7031 }
7032
7033 /* Insert base register reload insns at every far label. */
7034
7035 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7036 if (GET_CODE (insn) == CODE_LABEL
7037 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7038 {
7039 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7040 if (pool)
7041 {
7042 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7043 pool->label);
7044 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
7045 }
7046 }
7047
7048
7049 BITMAP_FREE (far_labels);
7050
7051
7052 /* Recompute insn addresses. */
7053
7054 init_insn_lengths ();
7055 shorten_branches (get_insns ());
7056
7057 return pool_list;
7058 }
7059
7060 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7061 After we have decided to use this list, finish implementing
7062 all changes to the current function as required. */
7063
7064 static void
7065 s390_chunkify_finish (struct constant_pool *pool_list)
7066 {
7067 struct constant_pool *curr_pool = NULL;
7068 rtx insn;
7069
7070
7071 /* Replace all literal pool references. */
7072
7073 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7074 {
7075 if (INSN_P (insn))
7076 replace_ltrel_base (&PATTERN (insn));
7077
7078 curr_pool = s390_find_pool (pool_list, insn);
7079 if (!curr_pool)
7080 continue;
7081
7082 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
7083 {
7084 rtx addr, pool_ref = NULL_RTX;
7085 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7086 if (pool_ref)
7087 {
7088 if (s390_execute_label (insn))
7089 addr = s390_find_execute (curr_pool, insn);
7090 else
7091 addr = s390_find_constant (curr_pool,
7092 get_pool_constant (pool_ref),
7093 get_pool_mode (pool_ref));
7094
7095 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7096 INSN_CODE (insn) = -1;
7097 }
7098 }
7099 }
7100
7101 /* Dump out all literal pools. */
7102
7103 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7104 s390_dump_pool (curr_pool, 0);
7105
7106 /* Free pool list. */
7107
7108 while (pool_list)
7109 {
7110 struct constant_pool *next = pool_list->next;
7111 s390_free_pool (pool_list);
7112 pool_list = next;
7113 }
7114 }
7115
7116 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7117 We have decided we cannot use this list, so revert all changes
7118 to the current function that were done by s390_chunkify_start. */
7119
7120 static void
7121 s390_chunkify_cancel (struct constant_pool *pool_list)
7122 {
7123 struct constant_pool *curr_pool = NULL;
7124 rtx insn;
7125
7126 /* Remove all pool placeholder insns. */
7127
7128 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7129 {
7130 /* Did we insert an extra barrier? Remove it. */
7131 rtx barrier = PREV_INSN (curr_pool->pool_insn);
7132 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
7133 rtx label = NEXT_INSN (curr_pool->pool_insn);
7134
7135 if (jump && GET_CODE (jump) == JUMP_INSN
7136 && barrier && GET_CODE (barrier) == BARRIER
7137 && label && GET_CODE (label) == CODE_LABEL
7138 && GET_CODE (PATTERN (jump)) == SET
7139 && SET_DEST (PATTERN (jump)) == pc_rtx
7140 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7141 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7142 {
7143 remove_insn (jump);
7144 remove_insn (barrier);
7145 remove_insn (label);
7146 }
7147
7148 remove_insn (curr_pool->pool_insn);
7149 }
7150
7151 /* Remove all base register reload insns. */
7152
7153 for (insn = get_insns (); insn; )
7154 {
7155 rtx next_insn = NEXT_INSN (insn);
7156
7157 if (GET_CODE (insn) == INSN
7158 && GET_CODE (PATTERN (insn)) == SET
7159 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7160 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7161 remove_insn (insn);
7162
7163 insn = next_insn;
7164 }
7165
7166 /* Free pool list. */
7167
7168 while (pool_list)
7169 {
7170 struct constant_pool *next = pool_list->next;
7171 s390_free_pool (pool_list);
7172 pool_list = next;
7173 }
7174 }
7175
7176 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7177
7178 void
7179 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
7180 {
7181 REAL_VALUE_TYPE r;
7182
7183 switch (GET_MODE_CLASS (mode))
7184 {
7185 case MODE_FLOAT:
7186 case MODE_DECIMAL_FLOAT:
7187 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7188
7189 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7190 assemble_real (r, mode, align);
7191 break;
7192
7193 case MODE_INT:
7194 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7195 mark_symbol_refs_as_used (exp);
7196 break;
7197
7198 default:
7199 gcc_unreachable ();
7200 }
7201 }
7202
7203
7204 /* Return an RTL expression representing the value of the return address
7205 for the frame COUNT steps up from the current frame. FRAME is the
7206 frame pointer of that frame. */
7207
7208 rtx
7209 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7210 {
7211 int offset;
7212 rtx addr;
7213
7214 /* Without backchain, we fail for all but the current frame. */
7215
7216 if (!TARGET_BACKCHAIN && count > 0)
7217 return NULL_RTX;
7218
7219 /* For the current frame, we need to make sure the initial
7220 value of RETURN_REGNUM is actually saved. */
7221
7222 if (count == 0)
7223 {
7224 /* On non-z architectures branch splitting could overwrite r14. */
7225 if (TARGET_CPU_ZARCH)
7226 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7227 else
7228 {
7229 cfun_frame_layout.save_return_addr_p = true;
7230 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7231 }
7232 }
7233
7234 if (TARGET_PACKED_STACK)
7235 offset = -2 * UNITS_PER_LONG;
7236 else
7237 offset = RETURN_REGNUM * UNITS_PER_LONG;
7238
7239 addr = plus_constant (Pmode, frame, offset);
7240 addr = memory_address (Pmode, addr);
7241 return gen_rtx_MEM (Pmode, addr);
7242 }
7243
7244 /* Return an RTL expression representing the back chain stored in
7245 the current stack frame. */
7246
7247 rtx
7248 s390_back_chain_rtx (void)
7249 {
7250 rtx chain;
7251
7252 gcc_assert (TARGET_BACKCHAIN);
7253
7254 if (TARGET_PACKED_STACK)
7255 chain = plus_constant (Pmode, stack_pointer_rtx,
7256 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7257 else
7258 chain = stack_pointer_rtx;
7259
7260 chain = gen_rtx_MEM (Pmode, chain);
7261 return chain;
7262 }
7263
7264 /* Find first call clobbered register unused in a function.
7265 This could be used as base register in a leaf function
7266 or for holding the return address before epilogue. */
7267
7268 static int
7269 find_unused_clobbered_reg (void)
7270 {
7271 int i;
7272 for (i = 0; i < 6; i++)
7273 if (!df_regs_ever_live_p (i))
7274 return i;
7275 return 0;
7276 }
7277
7278
7279 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7280 clobbered hard regs in SETREG. */
7281
7282 static void
7283 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7284 {
7285 int *regs_ever_clobbered = (int *)data;
7286 unsigned int i, regno;
7287 enum machine_mode mode = GET_MODE (setreg);
7288
7289 if (GET_CODE (setreg) == SUBREG)
7290 {
7291 rtx inner = SUBREG_REG (setreg);
7292 if (!GENERAL_REG_P (inner))
7293 return;
7294 regno = subreg_regno (setreg);
7295 }
7296 else if (GENERAL_REG_P (setreg))
7297 regno = REGNO (setreg);
7298 else
7299 return;
7300
7301 for (i = regno;
7302 i < regno + HARD_REGNO_NREGS (regno, mode);
7303 i++)
7304 regs_ever_clobbered[i] = 1;
7305 }
7306
7307 /* Walks through all basic blocks of the current function looking
7308 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7309 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7310 each of those regs. */
7311
7312 static void
7313 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7314 {
7315 basic_block cur_bb;
7316 rtx cur_insn;
7317 unsigned int i;
7318
7319 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7320
7321 /* For non-leaf functions we have to consider all call clobbered regs to be
7322 clobbered. */
7323 if (!crtl->is_leaf)
7324 {
7325 for (i = 0; i < 16; i++)
7326 regs_ever_clobbered[i] = call_really_used_regs[i];
7327 }
7328
7329 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7330 this work is done by liveness analysis (mark_regs_live_at_end).
7331 Special care is needed for functions containing landing pads. Landing pads
7332 may use the eh registers, but the code which sets these registers is not
7333 contained in that function. Hence s390_regs_ever_clobbered is not able to
7334 deal with this automatically. */
7335 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7336 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7337 if (crtl->calls_eh_return
7338 || (cfun->machine->has_landing_pad_p
7339 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7340 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7341
7342 /* For nonlocal gotos all call-saved registers have to be saved.
7343 This flag is also set for the unwinding code in libgcc.
7344 See expand_builtin_unwind_init. For regs_ever_live this is done by
7345 reload. */
7346 if (cfun->has_nonlocal_label)
7347 for (i = 0; i < 16; i++)
7348 if (!call_really_used_regs[i])
7349 regs_ever_clobbered[i] = 1;
7350
7351 FOR_EACH_BB (cur_bb)
7352 {
7353 FOR_BB_INSNS (cur_bb, cur_insn)
7354 {
7355 if (INSN_P (cur_insn))
7356 note_stores (PATTERN (cur_insn),
7357 s390_reg_clobbered_rtx,
7358 regs_ever_clobbered);
7359 }
7360 }
7361 }
7362
7363 /* Determine the frame area which actually has to be accessed
7364 in the function epilogue. The values are stored at the
7365 given pointers AREA_BOTTOM (address of the lowest used stack
7366 address) and AREA_TOP (address of the first item which does
7367 not belong to the stack frame). */
7368
7369 static void
7370 s390_frame_area (int *area_bottom, int *area_top)
7371 {
7372 int b, t;
7373 int i;
7374
7375 b = INT_MAX;
7376 t = INT_MIN;
7377
7378 if (cfun_frame_layout.first_restore_gpr != -1)
7379 {
7380 b = (cfun_frame_layout.gprs_offset
7381 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7382 t = b + (cfun_frame_layout.last_restore_gpr
7383 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7384 }
7385
7386 if (TARGET_64BIT && cfun_save_high_fprs_p)
7387 {
7388 b = MIN (b, cfun_frame_layout.f8_offset);
7389 t = MAX (t, (cfun_frame_layout.f8_offset
7390 + cfun_frame_layout.high_fprs * 8));
7391 }
7392
7393 if (!TARGET_64BIT)
7394 for (i = 2; i < 4; i++)
7395 if (cfun_fpr_bit_p (i))
7396 {
7397 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7398 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7399 }
7400
7401 *area_bottom = b;
7402 *area_top = t;
7403 }
7404
7405 /* Fill cfun->machine with info about register usage of current function.
7406 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7407
7408 static void
7409 s390_register_info (int clobbered_regs[])
7410 {
7411 int i, j;
7412
7413 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7414 cfun_frame_layout.fpr_bitmap = 0;
7415 cfun_frame_layout.high_fprs = 0;
7416 if (TARGET_64BIT)
7417 for (i = 24; i < 32; i++)
7418 if (df_regs_ever_live_p (i) && !global_regs[i])
7419 {
7420 cfun_set_fpr_bit (i - 16);
7421 cfun_frame_layout.high_fprs++;
7422 }
7423
7424 /* Find first and last gpr to be saved. We trust regs_ever_live
7425 data, except that we don't save and restore global registers.
7426
7427 Also, all registers with special meaning to the compiler need
7428 to be handled extra. */
7429
7430 s390_regs_ever_clobbered (clobbered_regs);
7431
7432 for (i = 0; i < 16; i++)
7433 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7434
7435 if (frame_pointer_needed)
7436 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7437
7438 if (flag_pic)
7439 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7440 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7441
7442 clobbered_regs[BASE_REGNUM]
7443 |= (cfun->machine->base_reg
7444 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7445
7446 clobbered_regs[RETURN_REGNUM]
7447 |= (!crtl->is_leaf
7448 || TARGET_TPF_PROFILING
7449 || cfun->machine->split_branches_pending_p
7450 || cfun_frame_layout.save_return_addr_p
7451 || crtl->calls_eh_return
7452 || cfun->stdarg);
7453
7454 clobbered_regs[STACK_POINTER_REGNUM]
7455 |= (!crtl->is_leaf
7456 || TARGET_TPF_PROFILING
7457 || cfun_save_high_fprs_p
7458 || get_frame_size () > 0
7459 || cfun->calls_alloca
7460 || cfun->stdarg);
7461
7462 for (i = 6; i < 16; i++)
7463 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7464 break;
7465 for (j = 15; j > i; j--)
7466 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7467 break;
7468
7469 if (i == 16)
7470 {
7471 /* Nothing to save/restore. */
7472 cfun_frame_layout.first_save_gpr_slot = -1;
7473 cfun_frame_layout.last_save_gpr_slot = -1;
7474 cfun_frame_layout.first_save_gpr = -1;
7475 cfun_frame_layout.first_restore_gpr = -1;
7476 cfun_frame_layout.last_save_gpr = -1;
7477 cfun_frame_layout.last_restore_gpr = -1;
7478 }
7479 else
7480 {
7481 /* Save slots for gprs from i to j. */
7482 cfun_frame_layout.first_save_gpr_slot = i;
7483 cfun_frame_layout.last_save_gpr_slot = j;
7484
7485 for (i = cfun_frame_layout.first_save_gpr_slot;
7486 i < cfun_frame_layout.last_save_gpr_slot + 1;
7487 i++)
7488 if (clobbered_regs[i])
7489 break;
7490
7491 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7492 if (clobbered_regs[j])
7493 break;
7494
7495 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7496 {
7497 /* Nothing to save/restore. */
7498 cfun_frame_layout.first_save_gpr = -1;
7499 cfun_frame_layout.first_restore_gpr = -1;
7500 cfun_frame_layout.last_save_gpr = -1;
7501 cfun_frame_layout.last_restore_gpr = -1;
7502 }
7503 else
7504 {
7505 /* Save / Restore from gpr i to j. */
7506 cfun_frame_layout.first_save_gpr = i;
7507 cfun_frame_layout.first_restore_gpr = i;
7508 cfun_frame_layout.last_save_gpr = j;
7509 cfun_frame_layout.last_restore_gpr = j;
7510 }
7511 }
7512
7513 if (cfun->stdarg)
7514 {
7515 /* Varargs functions need to save gprs 2 to 6. */
7516 if (cfun->va_list_gpr_size
7517 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7518 {
7519 int min_gpr = crtl->args.info.gprs;
7520 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7521 if (max_gpr > GP_ARG_NUM_REG)
7522 max_gpr = GP_ARG_NUM_REG;
7523
7524 if (cfun_frame_layout.first_save_gpr == -1
7525 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7526 {
7527 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7528 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7529 }
7530
7531 if (cfun_frame_layout.last_save_gpr == -1
7532 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7533 {
7534 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7535 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7536 }
7537 }
7538
7539 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7540 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7541 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7542 {
7543 int min_fpr = crtl->args.info.fprs;
7544 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7545 if (max_fpr > FP_ARG_NUM_REG)
7546 max_fpr = FP_ARG_NUM_REG;
7547
7548 /* ??? This is currently required to ensure proper location
7549 of the fpr save slots within the va_list save area. */
7550 if (TARGET_PACKED_STACK)
7551 min_fpr = 0;
7552
7553 for (i = min_fpr; i < max_fpr; i++)
7554 cfun_set_fpr_bit (i);
7555 }
7556 }
7557
7558 if (!TARGET_64BIT)
7559 for (i = 2; i < 4; i++)
7560 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7561 cfun_set_fpr_bit (i);
7562 }
7563
7564 /* Fill cfun->machine with info about frame of current function. */
7565
7566 static void
7567 s390_frame_info (void)
7568 {
7569 int i;
7570
7571 cfun_frame_layout.frame_size = get_frame_size ();
7572 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7573 fatal_error ("total size of local variables exceeds architecture limit");
7574
7575 if (!TARGET_PACKED_STACK)
7576 {
7577 cfun_frame_layout.backchain_offset = 0;
7578 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7579 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7580 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7581 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7582 * UNITS_PER_LONG);
7583 }
7584 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7585 {
7586 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7587 - UNITS_PER_LONG);
7588 cfun_frame_layout.gprs_offset
7589 = (cfun_frame_layout.backchain_offset
7590 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7591 * UNITS_PER_LONG);
7592
7593 if (TARGET_64BIT)
7594 {
7595 cfun_frame_layout.f4_offset
7596 = (cfun_frame_layout.gprs_offset
7597 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7598
7599 cfun_frame_layout.f0_offset
7600 = (cfun_frame_layout.f4_offset
7601 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7602 }
7603 else
7604 {
7605 /* On 31 bit we have to care about alignment of the
7606 floating point regs to provide fastest access. */
7607 cfun_frame_layout.f0_offset
7608 = ((cfun_frame_layout.gprs_offset
7609 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7610 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7611
7612 cfun_frame_layout.f4_offset
7613 = (cfun_frame_layout.f0_offset
7614 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7615 }
7616 }
7617 else /* no backchain */
7618 {
7619 cfun_frame_layout.f4_offset
7620 = (STACK_POINTER_OFFSET
7621 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7622
7623 cfun_frame_layout.f0_offset
7624 = (cfun_frame_layout.f4_offset
7625 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7626
7627 cfun_frame_layout.gprs_offset
7628 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7629 }
7630
7631 if (crtl->is_leaf
7632 && !TARGET_TPF_PROFILING
7633 && cfun_frame_layout.frame_size == 0
7634 && !cfun_save_high_fprs_p
7635 && !cfun->calls_alloca
7636 && !cfun->stdarg)
7637 return;
7638
7639 if (!TARGET_PACKED_STACK)
7640 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7641 + crtl->outgoing_args_size
7642 + cfun_frame_layout.high_fprs * 8);
7643 else
7644 {
7645 if (TARGET_BACKCHAIN)
7646 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7647
7648 /* No alignment trouble here because f8-f15 are only saved under
7649 64 bit. */
7650 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7651 cfun_frame_layout.f4_offset),
7652 cfun_frame_layout.gprs_offset)
7653 - cfun_frame_layout.high_fprs * 8);
7654
7655 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7656
7657 for (i = 0; i < 8; i++)
7658 if (cfun_fpr_bit_p (i))
7659 cfun_frame_layout.frame_size += 8;
7660
7661 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7662
7663 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7664 the frame size to sustain 8 byte alignment of stack frames. */
7665 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7666 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7667 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7668
7669 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7670 }
7671 }
7672
7673 /* Generate frame layout. Fills in register and frame data for the current
7674 function in cfun->machine. This routine can be called multiple times;
7675 it will re-do the complete frame layout every time. */
7676
7677 static void
7678 s390_init_frame_layout (void)
7679 {
7680 HOST_WIDE_INT frame_size;
7681 int base_used;
7682 int clobbered_regs[16];
7683
7684 /* On S/390 machines, we may need to perform branch splitting, which
7685 will require both base and return address register. We have no
7686 choice but to assume we're going to need them until right at the
7687 end of the machine dependent reorg phase. */
7688 if (!TARGET_CPU_ZARCH)
7689 cfun->machine->split_branches_pending_p = true;
7690
7691 do
7692 {
7693 frame_size = cfun_frame_layout.frame_size;
7694
7695 /* Try to predict whether we'll need the base register. */
7696 base_used = cfun->machine->split_branches_pending_p
7697 || crtl->uses_const_pool
7698 || (!DISP_IN_RANGE (frame_size)
7699 && !CONST_OK_FOR_K (frame_size));
7700
7701 /* Decide which register to use as literal pool base. In small
7702 leaf functions, try to use an unused call-clobbered register
7703 as base register to avoid save/restore overhead. */
7704 if (!base_used)
7705 cfun->machine->base_reg = NULL_RTX;
7706 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7707 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7708 else
7709 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7710
7711 s390_register_info (clobbered_regs);
7712 s390_frame_info ();
7713 }
7714 while (frame_size != cfun_frame_layout.frame_size);
7715 }
7716
7717 /* Update frame layout. Recompute actual register save data based on
7718 current info and update regs_ever_live for the special registers.
7719 May be called multiple times, but may never cause *more* registers
7720 to be saved than s390_init_frame_layout allocated room for. */
7721
7722 static void
7723 s390_update_frame_layout (void)
7724 {
7725 int clobbered_regs[16];
7726
7727 s390_register_info (clobbered_regs);
7728
7729 df_set_regs_ever_live (BASE_REGNUM,
7730 clobbered_regs[BASE_REGNUM] ? true : false);
7731 df_set_regs_ever_live (RETURN_REGNUM,
7732 clobbered_regs[RETURN_REGNUM] ? true : false);
7733 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7734 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7735
7736 if (cfun->machine->base_reg)
7737 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7738 }
7739
7740 /* Return true if it is legal to put a value with MODE into REGNO. */
7741
7742 bool
7743 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7744 {
7745 switch (REGNO_REG_CLASS (regno))
7746 {
7747 case FP_REGS:
7748 if (REGNO_PAIR_OK (regno, mode))
7749 {
7750 if (mode == SImode || mode == DImode)
7751 return true;
7752
7753 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7754 return true;
7755 }
7756 break;
7757 case ADDR_REGS:
7758 if (FRAME_REGNO_P (regno) && mode == Pmode)
7759 return true;
7760
7761 /* fallthrough */
7762 case GENERAL_REGS:
7763 if (REGNO_PAIR_OK (regno, mode))
7764 {
7765 if (TARGET_ZARCH
7766 || (mode != TFmode && mode != TCmode && mode != TDmode))
7767 return true;
7768 }
7769 break;
7770 case CC_REGS:
7771 if (GET_MODE_CLASS (mode) == MODE_CC)
7772 return true;
7773 break;
7774 case ACCESS_REGS:
7775 if (REGNO_PAIR_OK (regno, mode))
7776 {
7777 if (mode == SImode || mode == Pmode)
7778 return true;
7779 }
7780 break;
7781 default:
7782 return false;
7783 }
7784
7785 return false;
7786 }
7787
7788 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7789
7790 bool
7791 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7792 {
7793 /* Once we've decided upon a register to use as base register, it must
7794 no longer be used for any other purpose. */
7795 if (cfun->machine->base_reg)
7796 if (REGNO (cfun->machine->base_reg) == old_reg
7797 || REGNO (cfun->machine->base_reg) == new_reg)
7798 return false;
7799
7800 return true;
7801 }
7802
7803 /* Maximum number of registers to represent a value of mode MODE
7804 in a register of class RCLASS. */
7805
7806 int
7807 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7808 {
7809 switch (rclass)
7810 {
7811 case FP_REGS:
7812 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7813 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7814 else
7815 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7816 case ACCESS_REGS:
7817 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7818 default:
7819 break;
7820 }
7821 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7822 }
7823
7824 /* Return true if register FROM can be eliminated via register TO. */
7825
7826 static bool
7827 s390_can_eliminate (const int from, const int to)
7828 {
7829 /* On zSeries machines, we have not marked the base register as fixed.
7830 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7831 If a function requires the base register, we say here that this
7832 elimination cannot be performed. This will cause reload to free
7833 up the base register (as if it were fixed). On the other hand,
7834 if the current function does *not* require the base register, we
7835 say here the elimination succeeds, which in turn allows reload
7836 to allocate the base register for any other purpose. */
7837 if (from == BASE_REGNUM && to == BASE_REGNUM)
7838 {
7839 if (TARGET_CPU_ZARCH)
7840 {
7841 s390_init_frame_layout ();
7842 return cfun->machine->base_reg == NULL_RTX;
7843 }
7844
7845 return false;
7846 }
7847
7848 /* Everything else must point into the stack frame. */
7849 gcc_assert (to == STACK_POINTER_REGNUM
7850 || to == HARD_FRAME_POINTER_REGNUM);
7851
7852 gcc_assert (from == FRAME_POINTER_REGNUM
7853 || from == ARG_POINTER_REGNUM
7854 || from == RETURN_ADDRESS_POINTER_REGNUM);
7855
7856 /* Make sure we actually saved the return address. */
7857 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7858 if (!crtl->calls_eh_return
7859 && !cfun->stdarg
7860 && !cfun_frame_layout.save_return_addr_p)
7861 return false;
7862
7863 return true;
7864 }
7865
7866 /* Return offset between register FROM and TO initially after prolog. */
7867
7868 HOST_WIDE_INT
7869 s390_initial_elimination_offset (int from, int to)
7870 {
7871 HOST_WIDE_INT offset;
7872 int index;
7873
7874 /* ??? Why are we called for non-eliminable pairs? */
7875 if (!s390_can_eliminate (from, to))
7876 return 0;
7877
7878 switch (from)
7879 {
7880 case FRAME_POINTER_REGNUM:
7881 offset = (get_frame_size()
7882 + STACK_POINTER_OFFSET
7883 + crtl->outgoing_args_size);
7884 break;
7885
7886 case ARG_POINTER_REGNUM:
7887 s390_init_frame_layout ();
7888 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7889 break;
7890
7891 case RETURN_ADDRESS_POINTER_REGNUM:
7892 s390_init_frame_layout ();
7893 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7894 gcc_assert (index >= 0);
7895 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7896 offset += index * UNITS_PER_LONG;
7897 break;
7898
7899 case BASE_REGNUM:
7900 offset = 0;
7901 break;
7902
7903 default:
7904 gcc_unreachable ();
7905 }
7906
7907 return offset;
7908 }
7909
7910 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7911 to register BASE. Return generated insn. */
7912
7913 static rtx
7914 save_fpr (rtx base, int offset, int regnum)
7915 {
7916 rtx addr;
7917 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7918
7919 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7920 set_mem_alias_set (addr, get_varargs_alias_set ());
7921 else
7922 set_mem_alias_set (addr, get_frame_alias_set ());
7923
7924 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7925 }
7926
7927 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7928 to register BASE. Return generated insn. */
7929
7930 static rtx
7931 restore_fpr (rtx base, int offset, int regnum)
7932 {
7933 rtx addr;
7934 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7935 set_mem_alias_set (addr, get_frame_alias_set ());
7936
7937 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7938 }
7939
7940 /* Return true if REGNO is a global register, but not one
7941 of the special ones that need to be saved/restored in anyway. */
7942
7943 static inline bool
7944 global_not_special_regno_p (int regno)
7945 {
7946 return (global_regs[regno]
7947 /* These registers are special and need to be
7948 restored in any case. */
7949 && !(regno == STACK_POINTER_REGNUM
7950 || regno == RETURN_REGNUM
7951 || regno == BASE_REGNUM
7952 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7953 }
7954
7955 /* Generate insn to save registers FIRST to LAST into
7956 the register save area located at offset OFFSET
7957 relative to register BASE. */
7958
7959 static rtx
7960 save_gprs (rtx base, int offset, int first, int last)
7961 {
7962 rtx addr, insn, note;
7963 int i;
7964
7965 addr = plus_constant (Pmode, base, offset);
7966 addr = gen_rtx_MEM (Pmode, addr);
7967
7968 set_mem_alias_set (addr, get_frame_alias_set ());
7969
7970 /* Special-case single register. */
7971 if (first == last)
7972 {
7973 if (TARGET_64BIT)
7974 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7975 else
7976 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7977
7978 if (!global_not_special_regno_p (first))
7979 RTX_FRAME_RELATED_P (insn) = 1;
7980 return insn;
7981 }
7982
7983
7984 insn = gen_store_multiple (addr,
7985 gen_rtx_REG (Pmode, first),
7986 GEN_INT (last - first + 1));
7987
7988 if (first <= 6 && cfun->stdarg)
7989 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7990 {
7991 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7992
7993 if (first + i <= 6)
7994 set_mem_alias_set (mem, get_varargs_alias_set ());
7995 }
7996
7997 /* We need to set the FRAME_RELATED flag on all SETs
7998 inside the store-multiple pattern.
7999
8000 However, we must not emit DWARF records for registers 2..5
8001 if they are stored for use by variable arguments ...
8002
8003 ??? Unfortunately, it is not enough to simply not the
8004 FRAME_RELATED flags for those SETs, because the first SET
8005 of the PARALLEL is always treated as if it had the flag
8006 set, even if it does not. Therefore we emit a new pattern
8007 without those registers as REG_FRAME_RELATED_EXPR note. */
8008
8009 if (first >= 6 && !global_not_special_regno_p (first))
8010 {
8011 rtx pat = PATTERN (insn);
8012
8013 for (i = 0; i < XVECLEN (pat, 0); i++)
8014 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8015 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8016 0, i)))))
8017 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8018
8019 RTX_FRAME_RELATED_P (insn) = 1;
8020 }
8021 else if (last >= 6)
8022 {
8023 int start;
8024
8025 for (start = first >= 6 ? first : 6; start <= last; start++)
8026 if (!global_not_special_regno_p (start))
8027 break;
8028
8029 if (start > last)
8030 return insn;
8031
8032 addr = plus_constant (Pmode, base,
8033 offset + (start - first) * UNITS_PER_LONG);
8034 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
8035 gen_rtx_REG (Pmode, start),
8036 GEN_INT (last - start + 1));
8037 note = PATTERN (note);
8038
8039 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8040
8041 for (i = 0; i < XVECLEN (note, 0); i++)
8042 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8043 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8044 0, i)))))
8045 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8046
8047 RTX_FRAME_RELATED_P (insn) = 1;
8048 }
8049
8050 return insn;
8051 }
8052
8053 /* Generate insn to restore registers FIRST to LAST from
8054 the register save area located at offset OFFSET
8055 relative to register BASE. */
8056
8057 static rtx
8058 restore_gprs (rtx base, int offset, int first, int last)
8059 {
8060 rtx addr, insn;
8061
8062 addr = plus_constant (Pmode, base, offset);
8063 addr = gen_rtx_MEM (Pmode, addr);
8064 set_mem_alias_set (addr, get_frame_alias_set ());
8065
8066 /* Special-case single register. */
8067 if (first == last)
8068 {
8069 if (TARGET_64BIT)
8070 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8071 else
8072 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8073
8074 return insn;
8075 }
8076
8077 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8078 addr,
8079 GEN_INT (last - first + 1));
8080 return insn;
8081 }
8082
8083 /* Return insn sequence to load the GOT register. */
8084
8085 static GTY(()) rtx got_symbol;
8086 rtx
8087 s390_load_got (void)
8088 {
8089 rtx insns;
8090
8091 /* We cannot use pic_offset_table_rtx here since we use this
8092 function also for non-pic if __tls_get_offset is called and in
8093 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8094 aren't usable. */
8095 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8096
8097 if (!got_symbol)
8098 {
8099 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8100 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8101 }
8102
8103 start_sequence ();
8104
8105 if (TARGET_CPU_ZARCH)
8106 {
8107 emit_move_insn (got_rtx, got_symbol);
8108 }
8109 else
8110 {
8111 rtx offset;
8112
8113 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
8114 UNSPEC_LTREL_OFFSET);
8115 offset = gen_rtx_CONST (Pmode, offset);
8116 offset = force_const_mem (Pmode, offset);
8117
8118 emit_move_insn (got_rtx, offset);
8119
8120 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
8121 UNSPEC_LTREL_BASE);
8122 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
8123
8124 emit_move_insn (got_rtx, offset);
8125 }
8126
8127 insns = get_insns ();
8128 end_sequence ();
8129 return insns;
8130 }
8131
8132 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8133 and the change to the stack pointer. */
8134
8135 static void
8136 s390_emit_stack_tie (void)
8137 {
8138 rtx mem = gen_frame_mem (BLKmode,
8139 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8140
8141 emit_insn (gen_stack_tie (mem));
8142 }
8143
8144 /* Expand the prologue into a bunch of separate insns. */
8145
8146 void
8147 s390_emit_prologue (void)
8148 {
8149 rtx insn, addr;
8150 rtx temp_reg;
8151 int i;
8152 int offset;
8153 int next_fpr = 0;
8154
8155 /* Complete frame layout. */
8156
8157 s390_update_frame_layout ();
8158
8159 /* Annotate all constant pool references to let the scheduler know
8160 they implicitly use the base register. */
8161
8162 push_topmost_sequence ();
8163
8164 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8165 if (INSN_P (insn))
8166 {
8167 annotate_constant_pool_refs (&PATTERN (insn));
8168 df_insn_rescan (insn);
8169 }
8170
8171 pop_topmost_sequence ();
8172
8173 /* Choose best register to use for temp use within prologue.
8174 See below for why TPF must use the register 1. */
8175
8176 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8177 && !crtl->is_leaf
8178 && !TARGET_TPF_PROFILING)
8179 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8180 else
8181 temp_reg = gen_rtx_REG (Pmode, 1);
8182
8183 /* Save call saved gprs. */
8184 if (cfun_frame_layout.first_save_gpr != -1)
8185 {
8186 insn = save_gprs (stack_pointer_rtx,
8187 cfun_frame_layout.gprs_offset +
8188 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8189 - cfun_frame_layout.first_save_gpr_slot),
8190 cfun_frame_layout.first_save_gpr,
8191 cfun_frame_layout.last_save_gpr);
8192 emit_insn (insn);
8193 }
8194
8195 /* Dummy insn to mark literal pool slot. */
8196
8197 if (cfun->machine->base_reg)
8198 emit_insn (gen_main_pool (cfun->machine->base_reg));
8199
8200 offset = cfun_frame_layout.f0_offset;
8201
8202 /* Save f0 and f2. */
8203 for (i = 0; i < 2; i++)
8204 {
8205 if (cfun_fpr_bit_p (i))
8206 {
8207 save_fpr (stack_pointer_rtx, offset, i + 16);
8208 offset += 8;
8209 }
8210 else if (!TARGET_PACKED_STACK)
8211 offset += 8;
8212 }
8213
8214 /* Save f4 and f6. */
8215 offset = cfun_frame_layout.f4_offset;
8216 for (i = 2; i < 4; i++)
8217 {
8218 if (cfun_fpr_bit_p (i))
8219 {
8220 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8221 offset += 8;
8222
8223 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8224 therefore are not frame related. */
8225 if (!call_really_used_regs[i + 16])
8226 RTX_FRAME_RELATED_P (insn) = 1;
8227 }
8228 else if (!TARGET_PACKED_STACK)
8229 offset += 8;
8230 }
8231
8232 if (TARGET_PACKED_STACK
8233 && cfun_save_high_fprs_p
8234 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8235 {
8236 offset = (cfun_frame_layout.f8_offset
8237 + (cfun_frame_layout.high_fprs - 1) * 8);
8238
8239 for (i = 15; i > 7 && offset >= 0; i--)
8240 if (cfun_fpr_bit_p (i))
8241 {
8242 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8243
8244 RTX_FRAME_RELATED_P (insn) = 1;
8245 offset -= 8;
8246 }
8247 if (offset >= cfun_frame_layout.f8_offset)
8248 next_fpr = i + 16;
8249 }
8250
8251 if (!TARGET_PACKED_STACK)
8252 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8253
8254 if (flag_stack_usage_info)
8255 current_function_static_stack_size = cfun_frame_layout.frame_size;
8256
8257 /* Decrement stack pointer. */
8258
8259 if (cfun_frame_layout.frame_size > 0)
8260 {
8261 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8262 rtx real_frame_off;
8263
8264 if (s390_stack_size)
8265 {
8266 HOST_WIDE_INT stack_guard;
8267
8268 if (s390_stack_guard)
8269 stack_guard = s390_stack_guard;
8270 else
8271 {
8272 /* If no value for stack guard is provided the smallest power of 2
8273 larger than the current frame size is chosen. */
8274 stack_guard = 1;
8275 while (stack_guard < cfun_frame_layout.frame_size)
8276 stack_guard <<= 1;
8277 }
8278
8279 if (cfun_frame_layout.frame_size >= s390_stack_size)
8280 {
8281 warning (0, "frame size of function %qs is %wd"
8282 " bytes exceeding user provided stack limit of "
8283 "%d bytes. "
8284 "An unconditional trap is added.",
8285 current_function_name(), cfun_frame_layout.frame_size,
8286 s390_stack_size);
8287 emit_insn (gen_trap ());
8288 }
8289 else
8290 {
8291 /* stack_guard has to be smaller than s390_stack_size.
8292 Otherwise we would emit an AND with zero which would
8293 not match the test under mask pattern. */
8294 if (stack_guard >= s390_stack_size)
8295 {
8296 warning (0, "frame size of function %qs is %wd"
8297 " bytes which is more than half the stack size. "
8298 "The dynamic check would not be reliable. "
8299 "No check emitted for this function.",
8300 current_function_name(),
8301 cfun_frame_layout.frame_size);
8302 }
8303 else
8304 {
8305 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8306 & ~(stack_guard - 1));
8307
8308 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8309 GEN_INT (stack_check_mask));
8310 if (TARGET_64BIT)
8311 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8312 t, const0_rtx),
8313 t, const0_rtx, const0_rtx));
8314 else
8315 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8316 t, const0_rtx),
8317 t, const0_rtx, const0_rtx));
8318 }
8319 }
8320 }
8321
8322 if (s390_warn_framesize > 0
8323 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8324 warning (0, "frame size of %qs is %wd bytes",
8325 current_function_name (), cfun_frame_layout.frame_size);
8326
8327 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8328 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8329
8330 /* Save incoming stack pointer into temp reg. */
8331 if (TARGET_BACKCHAIN || next_fpr)
8332 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8333
8334 /* Subtract frame size from stack pointer. */
8335
8336 if (DISP_IN_RANGE (INTVAL (frame_off)))
8337 {
8338 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8339 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8340 frame_off));
8341 insn = emit_insn (insn);
8342 }
8343 else
8344 {
8345 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8346 frame_off = force_const_mem (Pmode, frame_off);
8347
8348 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8349 annotate_constant_pool_refs (&PATTERN (insn));
8350 }
8351
8352 RTX_FRAME_RELATED_P (insn) = 1;
8353 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8354 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8355 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8356 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8357 real_frame_off)));
8358
8359 /* Set backchain. */
8360
8361 if (TARGET_BACKCHAIN)
8362 {
8363 if (cfun_frame_layout.backchain_offset)
8364 addr = gen_rtx_MEM (Pmode,
8365 plus_constant (Pmode, stack_pointer_rtx,
8366 cfun_frame_layout.backchain_offset));
8367 else
8368 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8369 set_mem_alias_set (addr, get_frame_alias_set ());
8370 insn = emit_insn (gen_move_insn (addr, temp_reg));
8371 }
8372
8373 /* If we support non-call exceptions (e.g. for Java),
8374 we need to make sure the backchain pointer is set up
8375 before any possibly trapping memory access. */
8376 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8377 {
8378 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8379 emit_clobber (addr);
8380 }
8381 }
8382
8383 /* Save fprs 8 - 15 (64 bit ABI). */
8384
8385 if (cfun_save_high_fprs_p && next_fpr)
8386 {
8387 /* If the stack might be accessed through a different register
8388 we have to make sure that the stack pointer decrement is not
8389 moved below the use of the stack slots. */
8390 s390_emit_stack_tie ();
8391
8392 insn = emit_insn (gen_add2_insn (temp_reg,
8393 GEN_INT (cfun_frame_layout.f8_offset)));
8394
8395 offset = 0;
8396
8397 for (i = 24; i <= next_fpr; i++)
8398 if (cfun_fpr_bit_p (i - 16))
8399 {
8400 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8401 cfun_frame_layout.frame_size
8402 + cfun_frame_layout.f8_offset
8403 + offset);
8404
8405 insn = save_fpr (temp_reg, offset, i);
8406 offset += 8;
8407 RTX_FRAME_RELATED_P (insn) = 1;
8408 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8409 gen_rtx_SET (VOIDmode,
8410 gen_rtx_MEM (DFmode, addr),
8411 gen_rtx_REG (DFmode, i)));
8412 }
8413 }
8414
8415 /* Set frame pointer, if needed. */
8416
8417 if (frame_pointer_needed)
8418 {
8419 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8420 RTX_FRAME_RELATED_P (insn) = 1;
8421 }
8422
8423 /* Set up got pointer, if needed. */
8424
8425 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8426 {
8427 rtx insns = s390_load_got ();
8428
8429 for (insn = insns; insn; insn = NEXT_INSN (insn))
8430 annotate_constant_pool_refs (&PATTERN (insn));
8431
8432 emit_insn (insns);
8433 }
8434
8435 if (TARGET_TPF_PROFILING)
8436 {
8437 /* Generate a BAS instruction to serve as a function
8438 entry intercept to facilitate the use of tracing
8439 algorithms located at the branch target. */
8440 emit_insn (gen_prologue_tpf ());
8441
8442 /* Emit a blockage here so that all code
8443 lies between the profiling mechanisms. */
8444 emit_insn (gen_blockage ());
8445 }
8446 }
8447
8448 /* Expand the epilogue into a bunch of separate insns. */
8449
8450 void
8451 s390_emit_epilogue (bool sibcall)
8452 {
8453 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8454 int area_bottom, area_top, offset = 0;
8455 int next_offset;
8456 rtvec p;
8457 int i;
8458
8459 if (TARGET_TPF_PROFILING)
8460 {
8461
8462 /* Generate a BAS instruction to serve as a function
8463 entry intercept to facilitate the use of tracing
8464 algorithms located at the branch target. */
8465
8466 /* Emit a blockage here so that all code
8467 lies between the profiling mechanisms. */
8468 emit_insn (gen_blockage ());
8469
8470 emit_insn (gen_epilogue_tpf ());
8471 }
8472
8473 /* Check whether to use frame or stack pointer for restore. */
8474
8475 frame_pointer = (frame_pointer_needed
8476 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8477
8478 s390_frame_area (&area_bottom, &area_top);
8479
8480 /* Check whether we can access the register save area.
8481 If not, increment the frame pointer as required. */
8482
8483 if (area_top <= area_bottom)
8484 {
8485 /* Nothing to restore. */
8486 }
8487 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8488 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8489 {
8490 /* Area is in range. */
8491 offset = cfun_frame_layout.frame_size;
8492 }
8493 else
8494 {
8495 rtx insn, frame_off, cfa;
8496
8497 offset = area_bottom < 0 ? -area_bottom : 0;
8498 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8499
8500 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8501 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8502 if (DISP_IN_RANGE (INTVAL (frame_off)))
8503 {
8504 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8505 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8506 insn = emit_insn (insn);
8507 }
8508 else
8509 {
8510 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8511 frame_off = force_const_mem (Pmode, frame_off);
8512
8513 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8514 annotate_constant_pool_refs (&PATTERN (insn));
8515 }
8516 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8517 RTX_FRAME_RELATED_P (insn) = 1;
8518 }
8519
8520 /* Restore call saved fprs. */
8521
8522 if (TARGET_64BIT)
8523 {
8524 if (cfun_save_high_fprs_p)
8525 {
8526 next_offset = cfun_frame_layout.f8_offset;
8527 for (i = 24; i < 32; i++)
8528 {
8529 if (cfun_fpr_bit_p (i - 16))
8530 {
8531 restore_fpr (frame_pointer,
8532 offset + next_offset, i);
8533 cfa_restores
8534 = alloc_reg_note (REG_CFA_RESTORE,
8535 gen_rtx_REG (DFmode, i), cfa_restores);
8536 next_offset += 8;
8537 }
8538 }
8539 }
8540
8541 }
8542 else
8543 {
8544 next_offset = cfun_frame_layout.f4_offset;
8545 for (i = 18; i < 20; i++)
8546 {
8547 if (cfun_fpr_bit_p (i - 16))
8548 {
8549 restore_fpr (frame_pointer,
8550 offset + next_offset, i);
8551 cfa_restores
8552 = alloc_reg_note (REG_CFA_RESTORE,
8553 gen_rtx_REG (DFmode, i), cfa_restores);
8554 next_offset += 8;
8555 }
8556 else if (!TARGET_PACKED_STACK)
8557 next_offset += 8;
8558 }
8559
8560 }
8561
8562 /* Return register. */
8563
8564 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8565
8566 /* Restore call saved gprs. */
8567
8568 if (cfun_frame_layout.first_restore_gpr != -1)
8569 {
8570 rtx insn, addr;
8571 int i;
8572
8573 /* Check for global register and save them
8574 to stack location from where they get restored. */
8575
8576 for (i = cfun_frame_layout.first_restore_gpr;
8577 i <= cfun_frame_layout.last_restore_gpr;
8578 i++)
8579 {
8580 if (global_not_special_regno_p (i))
8581 {
8582 addr = plus_constant (Pmode, frame_pointer,
8583 offset + cfun_frame_layout.gprs_offset
8584 + (i - cfun_frame_layout.first_save_gpr_slot)
8585 * UNITS_PER_LONG);
8586 addr = gen_rtx_MEM (Pmode, addr);
8587 set_mem_alias_set (addr, get_frame_alias_set ());
8588 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8589 }
8590 else
8591 cfa_restores
8592 = alloc_reg_note (REG_CFA_RESTORE,
8593 gen_rtx_REG (Pmode, i), cfa_restores);
8594 }
8595
8596 if (! sibcall)
8597 {
8598 /* Fetch return address from stack before load multiple,
8599 this will do good for scheduling. */
8600
8601 if (cfun_frame_layout.save_return_addr_p
8602 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8603 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8604 {
8605 int return_regnum = find_unused_clobbered_reg();
8606 if (!return_regnum)
8607 return_regnum = 4;
8608 return_reg = gen_rtx_REG (Pmode, return_regnum);
8609
8610 addr = plus_constant (Pmode, frame_pointer,
8611 offset + cfun_frame_layout.gprs_offset
8612 + (RETURN_REGNUM
8613 - cfun_frame_layout.first_save_gpr_slot)
8614 * UNITS_PER_LONG);
8615 addr = gen_rtx_MEM (Pmode, addr);
8616 set_mem_alias_set (addr, get_frame_alias_set ());
8617 emit_move_insn (return_reg, addr);
8618 }
8619 }
8620
8621 insn = restore_gprs (frame_pointer,
8622 offset + cfun_frame_layout.gprs_offset
8623 + (cfun_frame_layout.first_restore_gpr
8624 - cfun_frame_layout.first_save_gpr_slot)
8625 * UNITS_PER_LONG,
8626 cfun_frame_layout.first_restore_gpr,
8627 cfun_frame_layout.last_restore_gpr);
8628 insn = emit_insn (insn);
8629 REG_NOTES (insn) = cfa_restores;
8630 add_reg_note (insn, REG_CFA_DEF_CFA,
8631 plus_constant (Pmode, stack_pointer_rtx,
8632 STACK_POINTER_OFFSET));
8633 RTX_FRAME_RELATED_P (insn) = 1;
8634 }
8635
8636 if (! sibcall)
8637 {
8638
8639 /* Return to caller. */
8640
8641 p = rtvec_alloc (2);
8642
8643 RTVEC_ELT (p, 0) = ret_rtx;
8644 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8645 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8646 }
8647 }
8648
8649
8650 /* Return the size in bytes of a function argument of
8651 type TYPE and/or mode MODE. At least one of TYPE or
8652 MODE must be specified. */
8653
8654 static int
8655 s390_function_arg_size (enum machine_mode mode, const_tree type)
8656 {
8657 if (type)
8658 return int_size_in_bytes (type);
8659
8660 /* No type info available for some library calls ... */
8661 if (mode != BLKmode)
8662 return GET_MODE_SIZE (mode);
8663
8664 /* If we have neither type nor mode, abort */
8665 gcc_unreachable ();
8666 }
8667
8668 /* Return true if a function argument of type TYPE and mode MODE
8669 is to be passed in a floating-point register, if available. */
8670
8671 static bool
8672 s390_function_arg_float (enum machine_mode mode, const_tree type)
8673 {
8674 int size = s390_function_arg_size (mode, type);
8675 if (size > 8)
8676 return false;
8677
8678 /* Soft-float changes the ABI: no floating-point registers are used. */
8679 if (TARGET_SOFT_FLOAT)
8680 return false;
8681
8682 /* No type info available for some library calls ... */
8683 if (!type)
8684 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8685
8686 /* The ABI says that record types with a single member are treated
8687 just like that member would be. */
8688 while (TREE_CODE (type) == RECORD_TYPE)
8689 {
8690 tree field, single = NULL_TREE;
8691
8692 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8693 {
8694 if (TREE_CODE (field) != FIELD_DECL)
8695 continue;
8696
8697 if (single == NULL_TREE)
8698 single = TREE_TYPE (field);
8699 else
8700 return false;
8701 }
8702
8703 if (single == NULL_TREE)
8704 return false;
8705 else
8706 type = single;
8707 }
8708
8709 return TREE_CODE (type) == REAL_TYPE;
8710 }
8711
8712 /* Return true if a function argument of type TYPE and mode MODE
8713 is to be passed in an integer register, or a pair of integer
8714 registers, if available. */
8715
8716 static bool
8717 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8718 {
8719 int size = s390_function_arg_size (mode, type);
8720 if (size > 8)
8721 return false;
8722
8723 /* No type info available for some library calls ... */
8724 if (!type)
8725 return GET_MODE_CLASS (mode) == MODE_INT
8726 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8727
8728 /* We accept small integral (and similar) types. */
8729 if (INTEGRAL_TYPE_P (type)
8730 || POINTER_TYPE_P (type)
8731 || TREE_CODE (type) == NULLPTR_TYPE
8732 || TREE_CODE (type) == OFFSET_TYPE
8733 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8734 return true;
8735
8736 /* We also accept structs of size 1, 2, 4, 8 that are not
8737 passed in floating-point registers. */
8738 if (AGGREGATE_TYPE_P (type)
8739 && exact_log2 (size) >= 0
8740 && !s390_function_arg_float (mode, type))
8741 return true;
8742
8743 return false;
8744 }
8745
8746 /* Return 1 if a function argument of type TYPE and mode MODE
8747 is to be passed by reference. The ABI specifies that only
8748 structures of size 1, 2, 4, or 8 bytes are passed by value,
8749 all other structures (and complex numbers) are passed by
8750 reference. */
8751
8752 static bool
8753 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8754 enum machine_mode mode, const_tree type,
8755 bool named ATTRIBUTE_UNUSED)
8756 {
8757 int size = s390_function_arg_size (mode, type);
8758 if (size > 8)
8759 return true;
8760
8761 if (type)
8762 {
8763 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8764 return 1;
8765
8766 if (TREE_CODE (type) == COMPLEX_TYPE
8767 || TREE_CODE (type) == VECTOR_TYPE)
8768 return 1;
8769 }
8770
8771 return 0;
8772 }
8773
8774 /* Update the data in CUM to advance over an argument of mode MODE and
8775 data type TYPE. (TYPE is null for libcalls where that information
8776 may not be available.). The boolean NAMED specifies whether the
8777 argument is a named argument (as opposed to an unnamed argument
8778 matching an ellipsis). */
8779
8780 static void
8781 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8782 const_tree type, bool named ATTRIBUTE_UNUSED)
8783 {
8784 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8785
8786 if (s390_function_arg_float (mode, type))
8787 {
8788 cum->fprs += 1;
8789 }
8790 else if (s390_function_arg_integer (mode, type))
8791 {
8792 int size = s390_function_arg_size (mode, type);
8793 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8794 }
8795 else
8796 gcc_unreachable ();
8797 }
8798
8799 /* Define where to put the arguments to a function.
8800 Value is zero to push the argument on the stack,
8801 or a hard register in which to store the argument.
8802
8803 MODE is the argument's machine mode.
8804 TYPE is the data type of the argument (as a tree).
8805 This is null for libcalls where that information may
8806 not be available.
8807 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8808 the preceding args and about the function being called.
8809 NAMED is nonzero if this argument is a named parameter
8810 (otherwise it is an extra parameter matching an ellipsis).
8811
8812 On S/390, we use general purpose registers 2 through 6 to
8813 pass integer, pointer, and certain structure arguments, and
8814 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8815 to pass floating point arguments. All remaining arguments
8816 are pushed to the stack. */
8817
8818 static rtx
8819 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8820 const_tree type, bool named ATTRIBUTE_UNUSED)
8821 {
8822 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8823
8824 if (s390_function_arg_float (mode, type))
8825 {
8826 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8827 return 0;
8828 else
8829 return gen_rtx_REG (mode, cum->fprs + 16);
8830 }
8831 else if (s390_function_arg_integer (mode, type))
8832 {
8833 int size = s390_function_arg_size (mode, type);
8834 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8835
8836 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8837 return 0;
8838 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8839 return gen_rtx_REG (mode, cum->gprs + 2);
8840 else if (n_gprs == 2)
8841 {
8842 rtvec p = rtvec_alloc (2);
8843
8844 RTVEC_ELT (p, 0)
8845 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8846 const0_rtx);
8847 RTVEC_ELT (p, 1)
8848 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8849 GEN_INT (4));
8850
8851 return gen_rtx_PARALLEL (mode, p);
8852 }
8853 }
8854
8855 /* After the real arguments, expand_call calls us once again
8856 with a void_type_node type. Whatever we return here is
8857 passed as operand 2 to the call expanders.
8858
8859 We don't need this feature ... */
8860 else if (type == void_type_node)
8861 return const0_rtx;
8862
8863 gcc_unreachable ();
8864 }
8865
8866 /* Return true if return values of type TYPE should be returned
8867 in a memory buffer whose address is passed by the caller as
8868 hidden first argument. */
8869
8870 static bool
8871 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8872 {
8873 /* We accept small integral (and similar) types. */
8874 if (INTEGRAL_TYPE_P (type)
8875 || POINTER_TYPE_P (type)
8876 || TREE_CODE (type) == OFFSET_TYPE
8877 || TREE_CODE (type) == REAL_TYPE)
8878 return int_size_in_bytes (type) > 8;
8879
8880 /* Aggregates and similar constructs are always returned
8881 in memory. */
8882 if (AGGREGATE_TYPE_P (type)
8883 || TREE_CODE (type) == COMPLEX_TYPE
8884 || TREE_CODE (type) == VECTOR_TYPE)
8885 return true;
8886
8887 /* ??? We get called on all sorts of random stuff from
8888 aggregate_value_p. We can't abort, but it's not clear
8889 what's safe to return. Pretend it's a struct I guess. */
8890 return true;
8891 }
8892
8893 /* Function arguments and return values are promoted to word size. */
8894
8895 static enum machine_mode
8896 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8897 int *punsignedp,
8898 const_tree fntype ATTRIBUTE_UNUSED,
8899 int for_return ATTRIBUTE_UNUSED)
8900 {
8901 if (INTEGRAL_MODE_P (mode)
8902 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8903 {
8904 if (type != NULL_TREE && POINTER_TYPE_P (type))
8905 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8906 return Pmode;
8907 }
8908
8909 return mode;
8910 }
8911
8912 /* Define where to return a (scalar) value of type RET_TYPE.
8913 If RET_TYPE is null, define where to return a (scalar)
8914 value of mode MODE from a libcall. */
8915
8916 static rtx
8917 s390_function_and_libcall_value (enum machine_mode mode,
8918 const_tree ret_type,
8919 const_tree fntype_or_decl,
8920 bool outgoing ATTRIBUTE_UNUSED)
8921 {
8922 /* For normal functions perform the promotion as
8923 promote_function_mode would do. */
8924 if (ret_type)
8925 {
8926 int unsignedp = TYPE_UNSIGNED (ret_type);
8927 mode = promote_function_mode (ret_type, mode, &unsignedp,
8928 fntype_or_decl, 1);
8929 }
8930
8931 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8932 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8933
8934 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8935 return gen_rtx_REG (mode, 16);
8936 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8937 || UNITS_PER_LONG == UNITS_PER_WORD)
8938 return gen_rtx_REG (mode, 2);
8939 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8940 {
8941 /* This case is triggered when returning a 64 bit value with
8942 -m31 -mzarch. Although the value would fit into a single
8943 register it has to be forced into a 32 bit register pair in
8944 order to match the ABI. */
8945 rtvec p = rtvec_alloc (2);
8946
8947 RTVEC_ELT (p, 0)
8948 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8949 RTVEC_ELT (p, 1)
8950 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8951
8952 return gen_rtx_PARALLEL (mode, p);
8953 }
8954
8955 gcc_unreachable ();
8956 }
8957
8958 /* Define where to return a scalar return value of type RET_TYPE. */
8959
8960 static rtx
8961 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8962 bool outgoing)
8963 {
8964 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8965 fn_decl_or_type, outgoing);
8966 }
8967
8968 /* Define where to return a scalar libcall return value of mode
8969 MODE. */
8970
8971 static rtx
8972 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8973 {
8974 return s390_function_and_libcall_value (mode, NULL_TREE,
8975 NULL_TREE, true);
8976 }
8977
8978
8979 /* Create and return the va_list datatype.
8980
8981 On S/390, va_list is an array type equivalent to
8982
8983 typedef struct __va_list_tag
8984 {
8985 long __gpr;
8986 long __fpr;
8987 void *__overflow_arg_area;
8988 void *__reg_save_area;
8989 } va_list[1];
8990
8991 where __gpr and __fpr hold the number of general purpose
8992 or floating point arguments used up to now, respectively,
8993 __overflow_arg_area points to the stack location of the
8994 next argument passed on the stack, and __reg_save_area
8995 always points to the start of the register area in the
8996 call frame of the current function. The function prologue
8997 saves all registers used for argument passing into this
8998 area if the function uses variable arguments. */
8999
9000 static tree
9001 s390_build_builtin_va_list (void)
9002 {
9003 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9004
9005 record = lang_hooks.types.make_type (RECORD_TYPE);
9006
9007 type_decl =
9008 build_decl (BUILTINS_LOCATION,
9009 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9010
9011 f_gpr = build_decl (BUILTINS_LOCATION,
9012 FIELD_DECL, get_identifier ("__gpr"),
9013 long_integer_type_node);
9014 f_fpr = build_decl (BUILTINS_LOCATION,
9015 FIELD_DECL, get_identifier ("__fpr"),
9016 long_integer_type_node);
9017 f_ovf = build_decl (BUILTINS_LOCATION,
9018 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9019 ptr_type_node);
9020 f_sav = build_decl (BUILTINS_LOCATION,
9021 FIELD_DECL, get_identifier ("__reg_save_area"),
9022 ptr_type_node);
9023
9024 va_list_gpr_counter_field = f_gpr;
9025 va_list_fpr_counter_field = f_fpr;
9026
9027 DECL_FIELD_CONTEXT (f_gpr) = record;
9028 DECL_FIELD_CONTEXT (f_fpr) = record;
9029 DECL_FIELD_CONTEXT (f_ovf) = record;
9030 DECL_FIELD_CONTEXT (f_sav) = record;
9031
9032 TYPE_STUB_DECL (record) = type_decl;
9033 TYPE_NAME (record) = type_decl;
9034 TYPE_FIELDS (record) = f_gpr;
9035 DECL_CHAIN (f_gpr) = f_fpr;
9036 DECL_CHAIN (f_fpr) = f_ovf;
9037 DECL_CHAIN (f_ovf) = f_sav;
9038
9039 layout_type (record);
9040
9041 /* The correct type is an array type of one element. */
9042 return build_array_type (record, build_index_type (size_zero_node));
9043 }
9044
9045 /* Implement va_start by filling the va_list structure VALIST.
9046 STDARG_P is always true, and ignored.
9047 NEXTARG points to the first anonymous stack argument.
9048
9049 The following global variables are used to initialize
9050 the va_list structure:
9051
9052 crtl->args.info:
9053 holds number of gprs and fprs used for named arguments.
9054 crtl->args.arg_offset_rtx:
9055 holds the offset of the first anonymous stack argument
9056 (relative to the virtual arg pointer). */
9057
9058 static void
9059 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9060 {
9061 HOST_WIDE_INT n_gpr, n_fpr;
9062 int off;
9063 tree f_gpr, f_fpr, f_ovf, f_sav;
9064 tree gpr, fpr, ovf, sav, t;
9065
9066 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9067 f_fpr = DECL_CHAIN (f_gpr);
9068 f_ovf = DECL_CHAIN (f_fpr);
9069 f_sav = DECL_CHAIN (f_ovf);
9070
9071 valist = build_simple_mem_ref (valist);
9072 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9073 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9074 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9075 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9076
9077 /* Count number of gp and fp argument registers used. */
9078
9079 n_gpr = crtl->args.info.gprs;
9080 n_fpr = crtl->args.info.fprs;
9081
9082 if (cfun->va_list_gpr_size)
9083 {
9084 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9085 build_int_cst (NULL_TREE, n_gpr));
9086 TREE_SIDE_EFFECTS (t) = 1;
9087 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9088 }
9089
9090 if (cfun->va_list_fpr_size)
9091 {
9092 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9093 build_int_cst (NULL_TREE, n_fpr));
9094 TREE_SIDE_EFFECTS (t) = 1;
9095 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9096 }
9097
9098 /* Find the overflow area. */
9099 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9100 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9101 {
9102 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9103
9104 off = INTVAL (crtl->args.arg_offset_rtx);
9105 off = off < 0 ? 0 : off;
9106 if (TARGET_DEBUG_ARG)
9107 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9108 (int)n_gpr, (int)n_fpr, off);
9109
9110 t = fold_build_pointer_plus_hwi (t, off);
9111
9112 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9113 TREE_SIDE_EFFECTS (t) = 1;
9114 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9115 }
9116
9117 /* Find the register save area. */
9118 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9119 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9120 {
9121 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
9122 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
9123
9124 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9125 TREE_SIDE_EFFECTS (t) = 1;
9126 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9127 }
9128 }
9129
9130 /* Implement va_arg by updating the va_list structure
9131 VALIST as required to retrieve an argument of type
9132 TYPE, and returning that argument.
9133
9134 Generates code equivalent to:
9135
9136 if (integral value) {
9137 if (size <= 4 && args.gpr < 5 ||
9138 size > 4 && args.gpr < 4 )
9139 ret = args.reg_save_area[args.gpr+8]
9140 else
9141 ret = *args.overflow_arg_area++;
9142 } else if (float value) {
9143 if (args.fgpr < 2)
9144 ret = args.reg_save_area[args.fpr+64]
9145 else
9146 ret = *args.overflow_arg_area++;
9147 } else if (aggregate value) {
9148 if (args.gpr < 5)
9149 ret = *args.reg_save_area[args.gpr]
9150 else
9151 ret = **args.overflow_arg_area++;
9152 } */
9153
9154 static tree
9155 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9156 gimple_seq *post_p ATTRIBUTE_UNUSED)
9157 {
9158 tree f_gpr, f_fpr, f_ovf, f_sav;
9159 tree gpr, fpr, ovf, sav, reg, t, u;
9160 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
9161 tree lab_false, lab_over, addr;
9162
9163 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9164 f_fpr = DECL_CHAIN (f_gpr);
9165 f_ovf = DECL_CHAIN (f_fpr);
9166 f_sav = DECL_CHAIN (f_ovf);
9167
9168 valist = build_va_arg_indirect_ref (valist);
9169 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9170 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9171 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9172
9173 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9174 both appear on a lhs. */
9175 valist = unshare_expr (valist);
9176 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9177
9178 size = int_size_in_bytes (type);
9179
9180 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9181 {
9182 if (TARGET_DEBUG_ARG)
9183 {
9184 fprintf (stderr, "va_arg: aggregate type");
9185 debug_tree (type);
9186 }
9187
9188 /* Aggregates are passed by reference. */
9189 indirect_p = 1;
9190 reg = gpr;
9191 n_reg = 1;
9192
9193 /* kernel stack layout on 31 bit: It is assumed here that no padding
9194 will be added by s390_frame_info because for va_args always an even
9195 number of gprs has to be saved r15-r2 = 14 regs. */
9196 sav_ofs = 2 * UNITS_PER_LONG;
9197 sav_scale = UNITS_PER_LONG;
9198 size = UNITS_PER_LONG;
9199 max_reg = GP_ARG_NUM_REG - n_reg;
9200 }
9201 else if (s390_function_arg_float (TYPE_MODE (type), type))
9202 {
9203 if (TARGET_DEBUG_ARG)
9204 {
9205 fprintf (stderr, "va_arg: float type");
9206 debug_tree (type);
9207 }
9208
9209 /* FP args go in FP registers, if present. */
9210 indirect_p = 0;
9211 reg = fpr;
9212 n_reg = 1;
9213 sav_ofs = 16 * UNITS_PER_LONG;
9214 sav_scale = 8;
9215 max_reg = FP_ARG_NUM_REG - n_reg;
9216 }
9217 else
9218 {
9219 if (TARGET_DEBUG_ARG)
9220 {
9221 fprintf (stderr, "va_arg: other type");
9222 debug_tree (type);
9223 }
9224
9225 /* Otherwise into GP registers. */
9226 indirect_p = 0;
9227 reg = gpr;
9228 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9229
9230 /* kernel stack layout on 31 bit: It is assumed here that no padding
9231 will be added by s390_frame_info because for va_args always an even
9232 number of gprs has to be saved r15-r2 = 14 regs. */
9233 sav_ofs = 2 * UNITS_PER_LONG;
9234
9235 if (size < UNITS_PER_LONG)
9236 sav_ofs += UNITS_PER_LONG - size;
9237
9238 sav_scale = UNITS_PER_LONG;
9239 max_reg = GP_ARG_NUM_REG - n_reg;
9240 }
9241
9242 /* Pull the value out of the saved registers ... */
9243
9244 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9245 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9246 addr = create_tmp_var (ptr_type_node, "addr");
9247
9248 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9249 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9250 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9251 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9252 gimplify_and_add (t, pre_p);
9253
9254 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9255 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9256 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9257 t = fold_build_pointer_plus (t, u);
9258
9259 gimplify_assign (addr, t, pre_p);
9260
9261 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9262
9263 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9264
9265
9266 /* ... Otherwise out of the overflow area. */
9267
9268 t = ovf;
9269 if (size < UNITS_PER_LONG)
9270 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9271
9272 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9273
9274 gimplify_assign (addr, t, pre_p);
9275
9276 t = fold_build_pointer_plus_hwi (t, size);
9277 gimplify_assign (ovf, t, pre_p);
9278
9279 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9280
9281
9282 /* Increment register save count. */
9283
9284 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9285 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9286 gimplify_and_add (u, pre_p);
9287
9288 if (indirect_p)
9289 {
9290 t = build_pointer_type_for_mode (build_pointer_type (type),
9291 ptr_mode, true);
9292 addr = fold_convert (t, addr);
9293 addr = build_va_arg_indirect_ref (addr);
9294 }
9295 else
9296 {
9297 t = build_pointer_type_for_mode (type, ptr_mode, true);
9298 addr = fold_convert (t, addr);
9299 }
9300
9301 return build_va_arg_indirect_ref (addr);
9302 }
9303
9304 /* Output assembly code for the trampoline template to
9305 stdio stream FILE.
9306
9307 On S/390, we use gpr 1 internally in the trampoline code;
9308 gpr 0 is used to hold the static chain. */
9309
9310 static void
9311 s390_asm_trampoline_template (FILE *file)
9312 {
9313 rtx op[2];
9314 op[0] = gen_rtx_REG (Pmode, 0);
9315 op[1] = gen_rtx_REG (Pmode, 1);
9316
9317 if (TARGET_64BIT)
9318 {
9319 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9320 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9321 output_asm_insn ("br\t%1", op); /* 2 byte */
9322 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9323 }
9324 else
9325 {
9326 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9327 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9328 output_asm_insn ("br\t%1", op); /* 2 byte */
9329 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9330 }
9331 }
9332
9333 /* Emit RTL insns to initialize the variable parts of a trampoline.
9334 FNADDR is an RTX for the address of the function's pure code.
9335 CXT is an RTX for the static chain value for the function. */
9336
9337 static void
9338 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9339 {
9340 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9341 rtx mem;
9342
9343 emit_block_move (m_tramp, assemble_trampoline_template (),
9344 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9345
9346 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9347 emit_move_insn (mem, cxt);
9348 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9349 emit_move_insn (mem, fnaddr);
9350 }
9351
9352 /* Output assembler code to FILE to increment profiler label # LABELNO
9353 for profiling a function entry. */
9354
9355 void
9356 s390_function_profiler (FILE *file, int labelno)
9357 {
9358 rtx op[7];
9359
9360 char label[128];
9361 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9362
9363 fprintf (file, "# function profiler \n");
9364
9365 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9366 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9367 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9368
9369 op[2] = gen_rtx_REG (Pmode, 1);
9370 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9371 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9372
9373 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9374 if (flag_pic)
9375 {
9376 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9377 op[4] = gen_rtx_CONST (Pmode, op[4]);
9378 }
9379
9380 if (TARGET_64BIT)
9381 {
9382 output_asm_insn ("stg\t%0,%1", op);
9383 output_asm_insn ("larl\t%2,%3", op);
9384 output_asm_insn ("brasl\t%0,%4", op);
9385 output_asm_insn ("lg\t%0,%1", op);
9386 }
9387 else if (!flag_pic)
9388 {
9389 op[6] = gen_label_rtx ();
9390
9391 output_asm_insn ("st\t%0,%1", op);
9392 output_asm_insn ("bras\t%2,%l6", op);
9393 output_asm_insn (".long\t%4", op);
9394 output_asm_insn (".long\t%3", op);
9395 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9396 output_asm_insn ("l\t%0,0(%2)", op);
9397 output_asm_insn ("l\t%2,4(%2)", op);
9398 output_asm_insn ("basr\t%0,%0", op);
9399 output_asm_insn ("l\t%0,%1", op);
9400 }
9401 else
9402 {
9403 op[5] = gen_label_rtx ();
9404 op[6] = gen_label_rtx ();
9405
9406 output_asm_insn ("st\t%0,%1", op);
9407 output_asm_insn ("bras\t%2,%l6", op);
9408 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9409 output_asm_insn (".long\t%4-%l5", op);
9410 output_asm_insn (".long\t%3-%l5", op);
9411 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9412 output_asm_insn ("lr\t%0,%2", op);
9413 output_asm_insn ("a\t%0,0(%2)", op);
9414 output_asm_insn ("a\t%2,4(%2)", op);
9415 output_asm_insn ("basr\t%0,%0", op);
9416 output_asm_insn ("l\t%0,%1", op);
9417 }
9418 }
9419
9420 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9421 into its SYMBOL_REF_FLAGS. */
9422
9423 static void
9424 s390_encode_section_info (tree decl, rtx rtl, int first)
9425 {
9426 default_encode_section_info (decl, rtl, first);
9427
9428 if (TREE_CODE (decl) == VAR_DECL)
9429 {
9430 /* If a variable has a forced alignment to < 2 bytes, mark it
9431 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9432 operand. */
9433 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9434 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9435 if (!DECL_SIZE (decl)
9436 || !DECL_ALIGN (decl)
9437 || !host_integerp (DECL_SIZE (decl), 0)
9438 || (DECL_ALIGN (decl) <= 64
9439 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9440 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9441 }
9442
9443 /* Literal pool references don't have a decl so they are handled
9444 differently here. We rely on the information in the MEM_ALIGN
9445 entry to decide upon natural alignment. */
9446 if (MEM_P (rtl)
9447 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9448 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9449 && (MEM_ALIGN (rtl) == 0
9450 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9451 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9452 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9453 }
9454
9455 /* Output thunk to FILE that implements a C++ virtual function call (with
9456 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9457 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9458 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9459 relative to the resulting this pointer. */
9460
9461 static void
9462 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9463 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9464 tree function)
9465 {
9466 rtx op[10];
9467 int nonlocal = 0;
9468
9469 /* Make sure unwind info is emitted for the thunk if needed. */
9470 final_start_function (emit_barrier (), file, 1);
9471
9472 /* Operand 0 is the target function. */
9473 op[0] = XEXP (DECL_RTL (function), 0);
9474 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9475 {
9476 nonlocal = 1;
9477 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9478 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9479 op[0] = gen_rtx_CONST (Pmode, op[0]);
9480 }
9481
9482 /* Operand 1 is the 'this' pointer. */
9483 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9484 op[1] = gen_rtx_REG (Pmode, 3);
9485 else
9486 op[1] = gen_rtx_REG (Pmode, 2);
9487
9488 /* Operand 2 is the delta. */
9489 op[2] = GEN_INT (delta);
9490
9491 /* Operand 3 is the vcall_offset. */
9492 op[3] = GEN_INT (vcall_offset);
9493
9494 /* Operand 4 is the temporary register. */
9495 op[4] = gen_rtx_REG (Pmode, 1);
9496
9497 /* Operands 5 to 8 can be used as labels. */
9498 op[5] = NULL_RTX;
9499 op[6] = NULL_RTX;
9500 op[7] = NULL_RTX;
9501 op[8] = NULL_RTX;
9502
9503 /* Operand 9 can be used for temporary register. */
9504 op[9] = NULL_RTX;
9505
9506 /* Generate code. */
9507 if (TARGET_64BIT)
9508 {
9509 /* Setup literal pool pointer if required. */
9510 if ((!DISP_IN_RANGE (delta)
9511 && !CONST_OK_FOR_K (delta)
9512 && !CONST_OK_FOR_Os (delta))
9513 || (!DISP_IN_RANGE (vcall_offset)
9514 && !CONST_OK_FOR_K (vcall_offset)
9515 && !CONST_OK_FOR_Os (vcall_offset)))
9516 {
9517 op[5] = gen_label_rtx ();
9518 output_asm_insn ("larl\t%4,%5", op);
9519 }
9520
9521 /* Add DELTA to this pointer. */
9522 if (delta)
9523 {
9524 if (CONST_OK_FOR_J (delta))
9525 output_asm_insn ("la\t%1,%2(%1)", op);
9526 else if (DISP_IN_RANGE (delta))
9527 output_asm_insn ("lay\t%1,%2(%1)", op);
9528 else if (CONST_OK_FOR_K (delta))
9529 output_asm_insn ("aghi\t%1,%2", op);
9530 else if (CONST_OK_FOR_Os (delta))
9531 output_asm_insn ("agfi\t%1,%2", op);
9532 else
9533 {
9534 op[6] = gen_label_rtx ();
9535 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9536 }
9537 }
9538
9539 /* Perform vcall adjustment. */
9540 if (vcall_offset)
9541 {
9542 if (DISP_IN_RANGE (vcall_offset))
9543 {
9544 output_asm_insn ("lg\t%4,0(%1)", op);
9545 output_asm_insn ("ag\t%1,%3(%4)", op);
9546 }
9547 else if (CONST_OK_FOR_K (vcall_offset))
9548 {
9549 output_asm_insn ("lghi\t%4,%3", op);
9550 output_asm_insn ("ag\t%4,0(%1)", op);
9551 output_asm_insn ("ag\t%1,0(%4)", op);
9552 }
9553 else if (CONST_OK_FOR_Os (vcall_offset))
9554 {
9555 output_asm_insn ("lgfi\t%4,%3", op);
9556 output_asm_insn ("ag\t%4,0(%1)", op);
9557 output_asm_insn ("ag\t%1,0(%4)", op);
9558 }
9559 else
9560 {
9561 op[7] = gen_label_rtx ();
9562 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9563 output_asm_insn ("ag\t%4,0(%1)", op);
9564 output_asm_insn ("ag\t%1,0(%4)", op);
9565 }
9566 }
9567
9568 /* Jump to target. */
9569 output_asm_insn ("jg\t%0", op);
9570
9571 /* Output literal pool if required. */
9572 if (op[5])
9573 {
9574 output_asm_insn (".align\t4", op);
9575 targetm.asm_out.internal_label (file, "L",
9576 CODE_LABEL_NUMBER (op[5]));
9577 }
9578 if (op[6])
9579 {
9580 targetm.asm_out.internal_label (file, "L",
9581 CODE_LABEL_NUMBER (op[6]));
9582 output_asm_insn (".long\t%2", op);
9583 }
9584 if (op[7])
9585 {
9586 targetm.asm_out.internal_label (file, "L",
9587 CODE_LABEL_NUMBER (op[7]));
9588 output_asm_insn (".long\t%3", op);
9589 }
9590 }
9591 else
9592 {
9593 /* Setup base pointer if required. */
9594 if (!vcall_offset
9595 || (!DISP_IN_RANGE (delta)
9596 && !CONST_OK_FOR_K (delta)
9597 && !CONST_OK_FOR_Os (delta))
9598 || (!DISP_IN_RANGE (delta)
9599 && !CONST_OK_FOR_K (vcall_offset)
9600 && !CONST_OK_FOR_Os (vcall_offset)))
9601 {
9602 op[5] = gen_label_rtx ();
9603 output_asm_insn ("basr\t%4,0", op);
9604 targetm.asm_out.internal_label (file, "L",
9605 CODE_LABEL_NUMBER (op[5]));
9606 }
9607
9608 /* Add DELTA to this pointer. */
9609 if (delta)
9610 {
9611 if (CONST_OK_FOR_J (delta))
9612 output_asm_insn ("la\t%1,%2(%1)", op);
9613 else if (DISP_IN_RANGE (delta))
9614 output_asm_insn ("lay\t%1,%2(%1)", op);
9615 else if (CONST_OK_FOR_K (delta))
9616 output_asm_insn ("ahi\t%1,%2", op);
9617 else if (CONST_OK_FOR_Os (delta))
9618 output_asm_insn ("afi\t%1,%2", op);
9619 else
9620 {
9621 op[6] = gen_label_rtx ();
9622 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9623 }
9624 }
9625
9626 /* Perform vcall adjustment. */
9627 if (vcall_offset)
9628 {
9629 if (CONST_OK_FOR_J (vcall_offset))
9630 {
9631 output_asm_insn ("l\t%4,0(%1)", op);
9632 output_asm_insn ("a\t%1,%3(%4)", op);
9633 }
9634 else if (DISP_IN_RANGE (vcall_offset))
9635 {
9636 output_asm_insn ("l\t%4,0(%1)", op);
9637 output_asm_insn ("ay\t%1,%3(%4)", op);
9638 }
9639 else if (CONST_OK_FOR_K (vcall_offset))
9640 {
9641 output_asm_insn ("lhi\t%4,%3", op);
9642 output_asm_insn ("a\t%4,0(%1)", op);
9643 output_asm_insn ("a\t%1,0(%4)", op);
9644 }
9645 else if (CONST_OK_FOR_Os (vcall_offset))
9646 {
9647 output_asm_insn ("iilf\t%4,%3", op);
9648 output_asm_insn ("a\t%4,0(%1)", op);
9649 output_asm_insn ("a\t%1,0(%4)", op);
9650 }
9651 else
9652 {
9653 op[7] = gen_label_rtx ();
9654 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9655 output_asm_insn ("a\t%4,0(%1)", op);
9656 output_asm_insn ("a\t%1,0(%4)", op);
9657 }
9658
9659 /* We had to clobber the base pointer register.
9660 Re-setup the base pointer (with a different base). */
9661 op[5] = gen_label_rtx ();
9662 output_asm_insn ("basr\t%4,0", op);
9663 targetm.asm_out.internal_label (file, "L",
9664 CODE_LABEL_NUMBER (op[5]));
9665 }
9666
9667 /* Jump to target. */
9668 op[8] = gen_label_rtx ();
9669
9670 if (!flag_pic)
9671 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9672 else if (!nonlocal)
9673 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9674 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9675 else if (flag_pic == 1)
9676 {
9677 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9678 output_asm_insn ("l\t%4,%0(%4)", op);
9679 }
9680 else if (flag_pic == 2)
9681 {
9682 op[9] = gen_rtx_REG (Pmode, 0);
9683 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9684 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9685 output_asm_insn ("ar\t%4,%9", op);
9686 output_asm_insn ("l\t%4,0(%4)", op);
9687 }
9688
9689 output_asm_insn ("br\t%4", op);
9690
9691 /* Output literal pool. */
9692 output_asm_insn (".align\t4", op);
9693
9694 if (nonlocal && flag_pic == 2)
9695 output_asm_insn (".long\t%0", op);
9696 if (nonlocal)
9697 {
9698 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9699 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9700 }
9701
9702 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9703 if (!flag_pic)
9704 output_asm_insn (".long\t%0", op);
9705 else
9706 output_asm_insn (".long\t%0-%5", op);
9707
9708 if (op[6])
9709 {
9710 targetm.asm_out.internal_label (file, "L",
9711 CODE_LABEL_NUMBER (op[6]));
9712 output_asm_insn (".long\t%2", op);
9713 }
9714 if (op[7])
9715 {
9716 targetm.asm_out.internal_label (file, "L",
9717 CODE_LABEL_NUMBER (op[7]));
9718 output_asm_insn (".long\t%3", op);
9719 }
9720 }
9721 final_end_function ();
9722 }
9723
9724 static bool
9725 s390_valid_pointer_mode (enum machine_mode mode)
9726 {
9727 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9728 }
9729
9730 /* Checks whether the given CALL_EXPR would use a caller
9731 saved register. This is used to decide whether sibling call
9732 optimization could be performed on the respective function
9733 call. */
9734
9735 static bool
9736 s390_call_saved_register_used (tree call_expr)
9737 {
9738 CUMULATIVE_ARGS cum_v;
9739 cumulative_args_t cum;
9740 tree parameter;
9741 enum machine_mode mode;
9742 tree type;
9743 rtx parm_rtx;
9744 int reg, i;
9745
9746 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9747 cum = pack_cumulative_args (&cum_v);
9748
9749 for (i = 0; i < call_expr_nargs (call_expr); i++)
9750 {
9751 parameter = CALL_EXPR_ARG (call_expr, i);
9752 gcc_assert (parameter);
9753
9754 /* For an undeclared variable passed as parameter we will get
9755 an ERROR_MARK node here. */
9756 if (TREE_CODE (parameter) == ERROR_MARK)
9757 return true;
9758
9759 type = TREE_TYPE (parameter);
9760 gcc_assert (type);
9761
9762 mode = TYPE_MODE (type);
9763 gcc_assert (mode);
9764
9765 if (pass_by_reference (&cum_v, mode, type, true))
9766 {
9767 mode = Pmode;
9768 type = build_pointer_type (type);
9769 }
9770
9771 parm_rtx = s390_function_arg (cum, mode, type, 0);
9772
9773 s390_function_arg_advance (cum, mode, type, 0);
9774
9775 if (!parm_rtx)
9776 continue;
9777
9778 if (REG_P (parm_rtx))
9779 {
9780 for (reg = 0;
9781 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9782 reg++)
9783 if (!call_used_regs[reg + REGNO (parm_rtx)])
9784 return true;
9785 }
9786
9787 if (GET_CODE (parm_rtx) == PARALLEL)
9788 {
9789 int i;
9790
9791 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9792 {
9793 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9794
9795 gcc_assert (REG_P (r));
9796
9797 for (reg = 0;
9798 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9799 reg++)
9800 if (!call_used_regs[reg + REGNO (r)])
9801 return true;
9802 }
9803 }
9804
9805 }
9806 return false;
9807 }
9808
9809 /* Return true if the given call expression can be
9810 turned into a sibling call.
9811 DECL holds the declaration of the function to be called whereas
9812 EXP is the call expression itself. */
9813
9814 static bool
9815 s390_function_ok_for_sibcall (tree decl, tree exp)
9816 {
9817 /* The TPF epilogue uses register 1. */
9818 if (TARGET_TPF_PROFILING)
9819 return false;
9820
9821 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9822 which would have to be restored before the sibcall. */
9823 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9824 return false;
9825
9826 /* Register 6 on s390 is available as an argument register but unfortunately
9827 "caller saved". This makes functions needing this register for arguments
9828 not suitable for sibcalls. */
9829 return !s390_call_saved_register_used (exp);
9830 }
9831
9832 /* Return the fixed registers used for condition codes. */
9833
9834 static bool
9835 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9836 {
9837 *p1 = CC_REGNUM;
9838 *p2 = INVALID_REGNUM;
9839
9840 return true;
9841 }
9842
9843 /* This function is used by the call expanders of the machine description.
9844 It emits the call insn itself together with the necessary operations
9845 to adjust the target address and returns the emitted insn.
9846 ADDR_LOCATION is the target address rtx
9847 TLS_CALL the location of the thread-local symbol
9848 RESULT_REG the register where the result of the call should be stored
9849 RETADDR_REG the register where the return address should be stored
9850 If this parameter is NULL_RTX the call is considered
9851 to be a sibling call. */
9852
9853 rtx
9854 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9855 rtx retaddr_reg)
9856 {
9857 bool plt_call = false;
9858 rtx insn;
9859 rtx call;
9860 rtx clobber;
9861 rtvec vec;
9862
9863 /* Direct function calls need special treatment. */
9864 if (GET_CODE (addr_location) == SYMBOL_REF)
9865 {
9866 /* When calling a global routine in PIC mode, we must
9867 replace the symbol itself with the PLT stub. */
9868 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9869 {
9870 if (retaddr_reg != NULL_RTX)
9871 {
9872 addr_location = gen_rtx_UNSPEC (Pmode,
9873 gen_rtvec (1, addr_location),
9874 UNSPEC_PLT);
9875 addr_location = gen_rtx_CONST (Pmode, addr_location);
9876 plt_call = true;
9877 }
9878 else
9879 /* For -fpic code the PLT entries might use r12 which is
9880 call-saved. Therefore we cannot do a sibcall when
9881 calling directly using a symbol ref. When reaching
9882 this point we decided (in s390_function_ok_for_sibcall)
9883 to do a sibcall for a function pointer but one of the
9884 optimizers was able to get rid of the function pointer
9885 by propagating the symbol ref into the call. This
9886 optimization is illegal for S/390 so we turn the direct
9887 call into a indirect call again. */
9888 addr_location = force_reg (Pmode, addr_location);
9889 }
9890
9891 /* Unless we can use the bras(l) insn, force the
9892 routine address into a register. */
9893 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9894 {
9895 if (flag_pic)
9896 addr_location = legitimize_pic_address (addr_location, 0);
9897 else
9898 addr_location = force_reg (Pmode, addr_location);
9899 }
9900 }
9901
9902 /* If it is already an indirect call or the code above moved the
9903 SYMBOL_REF to somewhere else make sure the address can be found in
9904 register 1. */
9905 if (retaddr_reg == NULL_RTX
9906 && GET_CODE (addr_location) != SYMBOL_REF
9907 && !plt_call)
9908 {
9909 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9910 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9911 }
9912
9913 addr_location = gen_rtx_MEM (QImode, addr_location);
9914 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9915
9916 if (result_reg != NULL_RTX)
9917 call = gen_rtx_SET (VOIDmode, result_reg, call);
9918
9919 if (retaddr_reg != NULL_RTX)
9920 {
9921 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9922
9923 if (tls_call != NULL_RTX)
9924 vec = gen_rtvec (3, call, clobber,
9925 gen_rtx_USE (VOIDmode, tls_call));
9926 else
9927 vec = gen_rtvec (2, call, clobber);
9928
9929 call = gen_rtx_PARALLEL (VOIDmode, vec);
9930 }
9931
9932 insn = emit_call_insn (call);
9933
9934 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9935 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9936 {
9937 /* s390_function_ok_for_sibcall should
9938 have denied sibcalls in this case. */
9939 gcc_assert (retaddr_reg != NULL_RTX);
9940 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
9941 }
9942 return insn;
9943 }
9944
9945 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9946
9947 static void
9948 s390_conditional_register_usage (void)
9949 {
9950 int i;
9951
9952 if (flag_pic)
9953 {
9954 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9955 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9956 }
9957 if (TARGET_CPU_ZARCH)
9958 {
9959 fixed_regs[BASE_REGNUM] = 0;
9960 call_used_regs[BASE_REGNUM] = 0;
9961 fixed_regs[RETURN_REGNUM] = 0;
9962 call_used_regs[RETURN_REGNUM] = 0;
9963 }
9964 if (TARGET_64BIT)
9965 {
9966 for (i = 24; i < 32; i++)
9967 call_used_regs[i] = call_really_used_regs[i] = 0;
9968 }
9969 else
9970 {
9971 for (i = 18; i < 20; i++)
9972 call_used_regs[i] = call_really_used_regs[i] = 0;
9973 }
9974
9975 if (TARGET_SOFT_FLOAT)
9976 {
9977 for (i = 16; i < 32; i++)
9978 call_used_regs[i] = fixed_regs[i] = 1;
9979 }
9980 }
9981
9982 /* Corresponding function to eh_return expander. */
9983
9984 static GTY(()) rtx s390_tpf_eh_return_symbol;
9985 void
9986 s390_emit_tpf_eh_return (rtx target)
9987 {
9988 rtx insn, reg;
9989
9990 if (!s390_tpf_eh_return_symbol)
9991 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9992
9993 reg = gen_rtx_REG (Pmode, 2);
9994
9995 emit_move_insn (reg, target);
9996 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9997 gen_rtx_REG (Pmode, RETURN_REGNUM));
9998 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9999
10000 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
10001 }
10002
10003 /* Rework the prologue/epilogue to avoid saving/restoring
10004 registers unnecessarily. */
10005
10006 static void
10007 s390_optimize_prologue (void)
10008 {
10009 rtx insn, new_insn, next_insn;
10010
10011 /* Do a final recompute of the frame-related data. */
10012
10013 s390_update_frame_layout ();
10014
10015 /* If all special registers are in fact used, there's nothing we
10016 can do, so no point in walking the insn list. */
10017
10018 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
10019 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
10020 && (TARGET_CPU_ZARCH
10021 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
10022 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10023 return;
10024
10025 /* Search for prologue/epilogue insns and replace them. */
10026
10027 for (insn = get_insns (); insn; insn = next_insn)
10028 {
10029 int first, last, off;
10030 rtx set, base, offset;
10031
10032 next_insn = NEXT_INSN (insn);
10033
10034 if (GET_CODE (insn) != INSN)
10035 continue;
10036
10037 if (GET_CODE (PATTERN (insn)) == PARALLEL
10038 && store_multiple_operation (PATTERN (insn), VOIDmode))
10039 {
10040 set = XVECEXP (PATTERN (insn), 0, 0);
10041 first = REGNO (SET_SRC (set));
10042 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10043 offset = const0_rtx;
10044 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10045 off = INTVAL (offset);
10046
10047 if (GET_CODE (base) != REG || off < 0)
10048 continue;
10049 if (cfun_frame_layout.first_save_gpr != -1
10050 && (cfun_frame_layout.first_save_gpr < first
10051 || cfun_frame_layout.last_save_gpr > last))
10052 continue;
10053 if (REGNO (base) != STACK_POINTER_REGNUM
10054 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10055 continue;
10056 if (first > BASE_REGNUM || last < BASE_REGNUM)
10057 continue;
10058
10059 if (cfun_frame_layout.first_save_gpr != -1)
10060 {
10061 new_insn = save_gprs (base,
10062 off + (cfun_frame_layout.first_save_gpr
10063 - first) * UNITS_PER_LONG,
10064 cfun_frame_layout.first_save_gpr,
10065 cfun_frame_layout.last_save_gpr);
10066 new_insn = emit_insn_before (new_insn, insn);
10067 INSN_ADDRESSES_NEW (new_insn, -1);
10068 }
10069
10070 remove_insn (insn);
10071 continue;
10072 }
10073
10074 if (cfun_frame_layout.first_save_gpr == -1
10075 && GET_CODE (PATTERN (insn)) == SET
10076 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10077 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10078 || (!TARGET_CPU_ZARCH
10079 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10080 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10081 {
10082 set = PATTERN (insn);
10083 first = REGNO (SET_SRC (set));
10084 offset = const0_rtx;
10085 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10086 off = INTVAL (offset);
10087
10088 if (GET_CODE (base) != REG || off < 0)
10089 continue;
10090 if (REGNO (base) != STACK_POINTER_REGNUM
10091 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10092 continue;
10093
10094 remove_insn (insn);
10095 continue;
10096 }
10097
10098 if (GET_CODE (PATTERN (insn)) == PARALLEL
10099 && load_multiple_operation (PATTERN (insn), VOIDmode))
10100 {
10101 set = XVECEXP (PATTERN (insn), 0, 0);
10102 first = REGNO (SET_DEST (set));
10103 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10104 offset = const0_rtx;
10105 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10106 off = INTVAL (offset);
10107
10108 if (GET_CODE (base) != REG || off < 0)
10109 continue;
10110 if (cfun_frame_layout.first_restore_gpr != -1
10111 && (cfun_frame_layout.first_restore_gpr < first
10112 || cfun_frame_layout.last_restore_gpr > last))
10113 continue;
10114 if (REGNO (base) != STACK_POINTER_REGNUM
10115 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10116 continue;
10117 if (first > BASE_REGNUM || last < BASE_REGNUM)
10118 continue;
10119
10120 if (cfun_frame_layout.first_restore_gpr != -1)
10121 {
10122 new_insn = restore_gprs (base,
10123 off + (cfun_frame_layout.first_restore_gpr
10124 - first) * UNITS_PER_LONG,
10125 cfun_frame_layout.first_restore_gpr,
10126 cfun_frame_layout.last_restore_gpr);
10127 new_insn = emit_insn_before (new_insn, insn);
10128 INSN_ADDRESSES_NEW (new_insn, -1);
10129 }
10130
10131 remove_insn (insn);
10132 continue;
10133 }
10134
10135 if (cfun_frame_layout.first_restore_gpr == -1
10136 && GET_CODE (PATTERN (insn)) == SET
10137 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10138 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10139 || (!TARGET_CPU_ZARCH
10140 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10141 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10142 {
10143 set = PATTERN (insn);
10144 first = REGNO (SET_DEST (set));
10145 offset = const0_rtx;
10146 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10147 off = INTVAL (offset);
10148
10149 if (GET_CODE (base) != REG || off < 0)
10150 continue;
10151 if (REGNO (base) != STACK_POINTER_REGNUM
10152 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10153 continue;
10154
10155 remove_insn (insn);
10156 continue;
10157 }
10158 }
10159 }
10160
10161 /* On z10 and later the dynamic branch prediction must see the
10162 backward jump within a certain windows. If not it falls back to
10163 the static prediction. This function rearranges the loop backward
10164 branch in a way which makes the static prediction always correct.
10165 The function returns true if it added an instruction. */
10166 static bool
10167 s390_fix_long_loop_prediction (rtx insn)
10168 {
10169 rtx set = single_set (insn);
10170 rtx code_label, label_ref, new_label;
10171 rtx uncond_jump;
10172 rtx cur_insn;
10173 rtx tmp;
10174 int distance;
10175
10176 /* This will exclude branch on count and branch on index patterns
10177 since these are correctly statically predicted. */
10178 if (!set
10179 || SET_DEST (set) != pc_rtx
10180 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10181 return false;
10182
10183 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10184 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10185
10186 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10187
10188 code_label = XEXP (label_ref, 0);
10189
10190 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10191 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10192 || (INSN_ADDRESSES (INSN_UID (insn))
10193 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10194 return false;
10195
10196 for (distance = 0, cur_insn = PREV_INSN (insn);
10197 distance < PREDICT_DISTANCE - 6;
10198 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10199 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10200 return false;
10201
10202 new_label = gen_label_rtx ();
10203 uncond_jump = emit_jump_insn_after (
10204 gen_rtx_SET (VOIDmode, pc_rtx,
10205 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10206 insn);
10207 emit_label_after (new_label, uncond_jump);
10208
10209 tmp = XEXP (SET_SRC (set), 1);
10210 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10211 XEXP (SET_SRC (set), 2) = tmp;
10212 INSN_CODE (insn) = -1;
10213
10214 XEXP (label_ref, 0) = new_label;
10215 JUMP_LABEL (insn) = new_label;
10216 JUMP_LABEL (uncond_jump) = code_label;
10217
10218 return true;
10219 }
10220
10221 /* Returns 1 if INSN reads the value of REG for purposes not related
10222 to addressing of memory, and 0 otherwise. */
10223 static int
10224 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10225 {
10226 return reg_referenced_p (reg, PATTERN (insn))
10227 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10228 }
10229
10230 /* Starting from INSN find_cond_jump looks downwards in the insn
10231 stream for a single jump insn which is the last user of the
10232 condition code set in INSN. */
10233 static rtx
10234 find_cond_jump (rtx insn)
10235 {
10236 for (; insn; insn = NEXT_INSN (insn))
10237 {
10238 rtx ite, cc;
10239
10240 if (LABEL_P (insn))
10241 break;
10242
10243 if (!JUMP_P (insn))
10244 {
10245 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10246 break;
10247 continue;
10248 }
10249
10250 /* This will be triggered by a return. */
10251 if (GET_CODE (PATTERN (insn)) != SET)
10252 break;
10253
10254 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10255 ite = SET_SRC (PATTERN (insn));
10256
10257 if (GET_CODE (ite) != IF_THEN_ELSE)
10258 break;
10259
10260 cc = XEXP (XEXP (ite, 0), 0);
10261 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10262 break;
10263
10264 if (find_reg_note (insn, REG_DEAD, cc))
10265 return insn;
10266 break;
10267 }
10268
10269 return NULL_RTX;
10270 }
10271
10272 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10273 the semantics does not change. If NULL_RTX is passed as COND the
10274 function tries to find the conditional jump starting with INSN. */
10275 static void
10276 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10277 {
10278 rtx tmp = *op0;
10279
10280 if (cond == NULL_RTX)
10281 {
10282 rtx jump = find_cond_jump (NEXT_INSN (insn));
10283 jump = jump ? single_set (jump) : NULL_RTX;
10284
10285 if (jump == NULL_RTX)
10286 return;
10287
10288 cond = XEXP (XEXP (jump, 1), 0);
10289 }
10290
10291 *op0 = *op1;
10292 *op1 = tmp;
10293 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10294 }
10295
10296 /* On z10, instructions of the compare-and-branch family have the
10297 property to access the register occurring as second operand with
10298 its bits complemented. If such a compare is grouped with a second
10299 instruction that accesses the same register non-complemented, and
10300 if that register's value is delivered via a bypass, then the
10301 pipeline recycles, thereby causing significant performance decline.
10302 This function locates such situations and exchanges the two
10303 operands of the compare. The function return true whenever it
10304 added an insn. */
10305 static bool
10306 s390_z10_optimize_cmp (rtx insn)
10307 {
10308 rtx prev_insn, next_insn;
10309 bool insn_added_p = false;
10310 rtx cond, *op0, *op1;
10311
10312 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10313 {
10314 /* Handle compare and branch and branch on count
10315 instructions. */
10316 rtx pattern = single_set (insn);
10317
10318 if (!pattern
10319 || SET_DEST (pattern) != pc_rtx
10320 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10321 return false;
10322
10323 cond = XEXP (SET_SRC (pattern), 0);
10324 op0 = &XEXP (cond, 0);
10325 op1 = &XEXP (cond, 1);
10326 }
10327 else if (GET_CODE (PATTERN (insn)) == SET)
10328 {
10329 rtx src, dest;
10330
10331 /* Handle normal compare instructions. */
10332 src = SET_SRC (PATTERN (insn));
10333 dest = SET_DEST (PATTERN (insn));
10334
10335 if (!REG_P (dest)
10336 || !CC_REGNO_P (REGNO (dest))
10337 || GET_CODE (src) != COMPARE)
10338 return false;
10339
10340 /* s390_swap_cmp will try to find the conditional
10341 jump when passing NULL_RTX as condition. */
10342 cond = NULL_RTX;
10343 op0 = &XEXP (src, 0);
10344 op1 = &XEXP (src, 1);
10345 }
10346 else
10347 return false;
10348
10349 if (!REG_P (*op0) || !REG_P (*op1))
10350 return false;
10351
10352 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10353 return false;
10354
10355 /* Swap the COMPARE arguments and its mask if there is a
10356 conflicting access in the previous insn. */
10357 prev_insn = prev_active_insn (insn);
10358 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10359 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10360 s390_swap_cmp (cond, op0, op1, insn);
10361
10362 /* Check if there is a conflict with the next insn. If there
10363 was no conflict with the previous insn, then swap the
10364 COMPARE arguments and its mask. If we already swapped
10365 the operands, or if swapping them would cause a conflict
10366 with the previous insn, issue a NOP after the COMPARE in
10367 order to separate the two instuctions. */
10368 next_insn = next_active_insn (insn);
10369 if (next_insn != NULL_RTX && INSN_P (next_insn)
10370 && s390_non_addr_reg_read_p (*op1, next_insn))
10371 {
10372 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10373 && s390_non_addr_reg_read_p (*op0, prev_insn))
10374 {
10375 if (REGNO (*op1) == 0)
10376 emit_insn_after (gen_nop1 (), insn);
10377 else
10378 emit_insn_after (gen_nop (), insn);
10379 insn_added_p = true;
10380 }
10381 else
10382 s390_swap_cmp (cond, op0, op1, insn);
10383 }
10384 return insn_added_p;
10385 }
10386
10387 /* Perform machine-dependent processing. */
10388
10389 static void
10390 s390_reorg (void)
10391 {
10392 bool pool_overflow = false;
10393
10394 /* Make sure all splits have been performed; splits after
10395 machine_dependent_reorg might confuse insn length counts. */
10396 split_all_insns_noflow ();
10397
10398 /* Install the main literal pool and the associated base
10399 register load insns.
10400
10401 In addition, there are two problematic situations we need
10402 to correct:
10403
10404 - the literal pool might be > 4096 bytes in size, so that
10405 some of its elements cannot be directly accessed
10406
10407 - a branch target might be > 64K away from the branch, so that
10408 it is not possible to use a PC-relative instruction.
10409
10410 To fix those, we split the single literal pool into multiple
10411 pool chunks, reloading the pool base register at various
10412 points throughout the function to ensure it always points to
10413 the pool chunk the following code expects, and / or replace
10414 PC-relative branches by absolute branches.
10415
10416 However, the two problems are interdependent: splitting the
10417 literal pool can move a branch further away from its target,
10418 causing the 64K limit to overflow, and on the other hand,
10419 replacing a PC-relative branch by an absolute branch means
10420 we need to put the branch target address into the literal
10421 pool, possibly causing it to overflow.
10422
10423 So, we loop trying to fix up both problems until we manage
10424 to satisfy both conditions at the same time. Note that the
10425 loop is guaranteed to terminate as every pass of the loop
10426 strictly decreases the total number of PC-relative branches
10427 in the function. (This is not completely true as there
10428 might be branch-over-pool insns introduced by chunkify_start.
10429 Those never need to be split however.) */
10430
10431 for (;;)
10432 {
10433 struct constant_pool *pool = NULL;
10434
10435 /* Collect the literal pool. */
10436 if (!pool_overflow)
10437 {
10438 pool = s390_mainpool_start ();
10439 if (!pool)
10440 pool_overflow = true;
10441 }
10442
10443 /* If literal pool overflowed, start to chunkify it. */
10444 if (pool_overflow)
10445 pool = s390_chunkify_start ();
10446
10447 /* Split out-of-range branches. If this has created new
10448 literal pool entries, cancel current chunk list and
10449 recompute it. zSeries machines have large branch
10450 instructions, so we never need to split a branch. */
10451 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10452 {
10453 if (pool_overflow)
10454 s390_chunkify_cancel (pool);
10455 else
10456 s390_mainpool_cancel (pool);
10457
10458 continue;
10459 }
10460
10461 /* If we made it up to here, both conditions are satisfied.
10462 Finish up literal pool related changes. */
10463 if (pool_overflow)
10464 s390_chunkify_finish (pool);
10465 else
10466 s390_mainpool_finish (pool);
10467
10468 /* We're done splitting branches. */
10469 cfun->machine->split_branches_pending_p = false;
10470 break;
10471 }
10472
10473 /* Generate out-of-pool execute target insns. */
10474 if (TARGET_CPU_ZARCH)
10475 {
10476 rtx insn, label, target;
10477
10478 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10479 {
10480 label = s390_execute_label (insn);
10481 if (!label)
10482 continue;
10483
10484 gcc_assert (label != const0_rtx);
10485
10486 target = emit_label (XEXP (label, 0));
10487 INSN_ADDRESSES_NEW (target, -1);
10488
10489 target = emit_insn (s390_execute_target (insn));
10490 INSN_ADDRESSES_NEW (target, -1);
10491 }
10492 }
10493
10494 /* Try to optimize prologue and epilogue further. */
10495 s390_optimize_prologue ();
10496
10497 /* Walk over the insns and do some >=z10 specific changes. */
10498 if (s390_tune == PROCESSOR_2097_Z10
10499 || s390_tune == PROCESSOR_2817_Z196
10500 || s390_tune == PROCESSOR_2827_ZEC12)
10501 {
10502 rtx insn;
10503 bool insn_added_p = false;
10504
10505 /* The insn lengths and addresses have to be up to date for the
10506 following manipulations. */
10507 shorten_branches (get_insns ());
10508
10509 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10510 {
10511 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10512 continue;
10513
10514 if (JUMP_P (insn))
10515 insn_added_p |= s390_fix_long_loop_prediction (insn);
10516
10517 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10518 || GET_CODE (PATTERN (insn)) == SET)
10519 && s390_tune == PROCESSOR_2097_Z10)
10520 insn_added_p |= s390_z10_optimize_cmp (insn);
10521 }
10522
10523 /* Adjust branches if we added new instructions. */
10524 if (insn_added_p)
10525 shorten_branches (get_insns ());
10526 }
10527 }
10528
10529 /* Return true if INSN is a fp load insn writing register REGNO. */
10530 static inline bool
10531 s390_fpload_toreg (rtx insn, unsigned int regno)
10532 {
10533 rtx set;
10534 enum attr_type flag = s390_safe_attr_type (insn);
10535
10536 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10537 return false;
10538
10539 set = single_set (insn);
10540
10541 if (set == NULL_RTX)
10542 return false;
10543
10544 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10545 return false;
10546
10547 if (REGNO (SET_DEST (set)) != regno)
10548 return false;
10549
10550 return true;
10551 }
10552
10553 /* This value describes the distance to be avoided between an
10554 aritmetic fp instruction and an fp load writing the same register.
10555 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10556 fine but the exact value has to be avoided. Otherwise the FP
10557 pipeline will throw an exception causing a major penalty. */
10558 #define Z10_EARLYLOAD_DISTANCE 7
10559
10560 /* Rearrange the ready list in order to avoid the situation described
10561 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10562 moved to the very end of the ready list. */
10563 static void
10564 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10565 {
10566 unsigned int regno;
10567 int nready = *nready_p;
10568 rtx tmp;
10569 int i;
10570 rtx insn;
10571 rtx set;
10572 enum attr_type flag;
10573 int distance;
10574
10575 /* Skip DISTANCE - 1 active insns. */
10576 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10577 distance > 0 && insn != NULL_RTX;
10578 distance--, insn = prev_active_insn (insn))
10579 if (CALL_P (insn) || JUMP_P (insn))
10580 return;
10581
10582 if (insn == NULL_RTX)
10583 return;
10584
10585 set = single_set (insn);
10586
10587 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10588 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10589 return;
10590
10591 flag = s390_safe_attr_type (insn);
10592
10593 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10594 return;
10595
10596 regno = REGNO (SET_DEST (set));
10597 i = nready - 1;
10598
10599 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10600 i--;
10601
10602 if (!i)
10603 return;
10604
10605 tmp = ready[i];
10606 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10607 ready[0] = tmp;
10608 }
10609
10610
10611 /* The s390_sched_state variable tracks the state of the current or
10612 the last instruction group.
10613
10614 0,1,2 number of instructions scheduled in the current group
10615 3 the last group is complete - normal insns
10616 4 the last group was a cracked/expanded insn */
10617
10618 static int s390_sched_state;
10619
10620 #define S390_OOO_SCHED_STATE_NORMAL 3
10621 #define S390_OOO_SCHED_STATE_CRACKED 4
10622
10623 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
10624 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
10625 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
10626 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
10627
10628 static unsigned int
10629 s390_get_sched_attrmask (rtx insn)
10630 {
10631 unsigned int mask = 0;
10632
10633 if (get_attr_ooo_cracked (insn))
10634 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
10635 if (get_attr_ooo_expanded (insn))
10636 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
10637 if (get_attr_ooo_endgroup (insn))
10638 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
10639 if (get_attr_ooo_groupalone (insn))
10640 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
10641 return mask;
10642 }
10643
10644 /* Return the scheduling score for INSN. The higher the score the
10645 better. The score is calculated from the OOO scheduling attributes
10646 of INSN and the scheduling state s390_sched_state. */
10647 static int
10648 s390_sched_score (rtx insn)
10649 {
10650 unsigned int mask = s390_get_sched_attrmask (insn);
10651 int score = 0;
10652
10653 switch (s390_sched_state)
10654 {
10655 case 0:
10656 /* Try to put insns into the first slot which would otherwise
10657 break a group. */
10658 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
10659 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
10660 score += 5;
10661 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
10662 score += 10;
10663 case 1:
10664 /* Prefer not cracked insns while trying to put together a
10665 group. */
10666 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
10667 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
10668 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
10669 score += 10;
10670 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
10671 score += 5;
10672 break;
10673 case 2:
10674 /* Prefer not cracked insns while trying to put together a
10675 group. */
10676 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
10677 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
10678 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
10679 score += 10;
10680 /* Prefer endgroup insns in the last slot. */
10681 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
10682 score += 10;
10683 break;
10684 case S390_OOO_SCHED_STATE_NORMAL:
10685 /* Prefer not cracked insns if the last was not cracked. */
10686 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
10687 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
10688 score += 5;
10689 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
10690 score += 10;
10691 break;
10692 case S390_OOO_SCHED_STATE_CRACKED:
10693 /* Try to keep cracked insns together to prevent them from
10694 interrupting groups. */
10695 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
10696 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
10697 score += 5;
10698 break;
10699 }
10700 return score;
10701 }
10702
10703 /* This function is called via hook TARGET_SCHED_REORDER before
10704 issueing one insn from list READY which contains *NREADYP entries.
10705 For target z10 it reorders load instructions to avoid early load
10706 conflicts in the floating point pipeline */
10707 static int
10708 s390_sched_reorder (FILE *file, int verbose,
10709 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10710 {
10711 if (s390_tune == PROCESSOR_2097_Z10)
10712 if (reload_completed && *nreadyp > 1)
10713 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10714
10715 if (s390_tune == PROCESSOR_2827_ZEC12
10716 && reload_completed
10717 && *nreadyp > 1)
10718 {
10719 int i;
10720 int last_index = *nreadyp - 1;
10721 int max_index = -1;
10722 int max_score = -1;
10723 rtx tmp;
10724
10725 /* Just move the insn with the highest score to the top (the
10726 end) of the list. A full sort is not needed since a conflict
10727 in the hazard recognition cannot happen. So the top insn in
10728 the ready list will always be taken. */
10729 for (i = last_index; i >= 0; i--)
10730 {
10731 int score;
10732
10733 if (recog_memoized (ready[i]) < 0)
10734 continue;
10735
10736 score = s390_sched_score (ready[i]);
10737 if (score > max_score)
10738 {
10739 max_score = score;
10740 max_index = i;
10741 }
10742 }
10743
10744 if (max_index != -1)
10745 {
10746 if (max_index != last_index)
10747 {
10748 tmp = ready[max_index];
10749 ready[max_index] = ready[last_index];
10750 ready[last_index] = tmp;
10751
10752 if (verbose > 5)
10753 fprintf (file,
10754 "move insn %d to the top of list\n",
10755 INSN_UID (ready[last_index]));
10756 }
10757 else if (verbose > 5)
10758 fprintf (file,
10759 "best insn %d already on top\n",
10760 INSN_UID (ready[last_index]));
10761 }
10762
10763 if (verbose > 5)
10764 {
10765 fprintf (file, "ready list ooo attributes - sched state: %d\n",
10766 s390_sched_state);
10767
10768 for (i = last_index; i >= 0; i--)
10769 {
10770 if (recog_memoized (ready[i]) < 0)
10771 continue;
10772 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
10773 s390_sched_score (ready[i]));
10774 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
10775 PRINT_OOO_ATTR (ooo_cracked);
10776 PRINT_OOO_ATTR (ooo_expanded);
10777 PRINT_OOO_ATTR (ooo_endgroup);
10778 PRINT_OOO_ATTR (ooo_groupalone);
10779 #undef PRINT_OOO_ATTR
10780 fprintf (file, "\n");
10781 }
10782 }
10783 }
10784
10785 return s390_issue_rate ();
10786 }
10787
10788
10789 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10790 the scheduler has issued INSN. It stores the last issued insn into
10791 last_scheduled_insn in order to make it available for
10792 s390_sched_reorder. */
10793 static int
10794 s390_sched_variable_issue (FILE *file, int verbose, rtx insn, int more)
10795 {
10796 last_scheduled_insn = insn;
10797
10798 if (s390_tune == PROCESSOR_2827_ZEC12
10799 && reload_completed
10800 && recog_memoized (insn) >= 0)
10801 {
10802 unsigned int mask = s390_get_sched_attrmask (insn);
10803
10804 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
10805 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
10806 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
10807 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
10808 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
10809 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
10810 else
10811 {
10812 /* Only normal insns are left (mask == 0). */
10813 switch (s390_sched_state)
10814 {
10815 case 0:
10816 case 1:
10817 case 2:
10818 case S390_OOO_SCHED_STATE_NORMAL:
10819 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
10820 s390_sched_state = 1;
10821 else
10822 s390_sched_state++;
10823
10824 break;
10825 case S390_OOO_SCHED_STATE_CRACKED:
10826 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
10827 break;
10828 }
10829 }
10830 if (verbose > 5)
10831 {
10832 fprintf (file, "insn %d: ", INSN_UID (insn));
10833 #define PRINT_OOO_ATTR(ATTR) \
10834 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
10835 PRINT_OOO_ATTR (ooo_cracked);
10836 PRINT_OOO_ATTR (ooo_expanded);
10837 PRINT_OOO_ATTR (ooo_endgroup);
10838 PRINT_OOO_ATTR (ooo_groupalone);
10839 #undef PRINT_OOO_ATTR
10840 fprintf (file, "\n");
10841 fprintf (file, "sched state: %d\n", s390_sched_state);
10842 }
10843 }
10844
10845 if (GET_CODE (PATTERN (insn)) != USE
10846 && GET_CODE (PATTERN (insn)) != CLOBBER)
10847 return more - 1;
10848 else
10849 return more;
10850 }
10851
10852 static void
10853 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10854 int verbose ATTRIBUTE_UNUSED,
10855 int max_ready ATTRIBUTE_UNUSED)
10856 {
10857 last_scheduled_insn = NULL_RTX;
10858 s390_sched_state = 0;
10859 }
10860
10861 /* This function checks the whole of insn X for memory references. The
10862 function always returns zero because the framework it is called
10863 from would stop recursively analyzing the insn upon a return value
10864 other than zero. The real result of this function is updating
10865 counter variable MEM_COUNT. */
10866 static int
10867 check_dpu (rtx *x, unsigned *mem_count)
10868 {
10869 if (*x != NULL_RTX && MEM_P (*x))
10870 (*mem_count)++;
10871 return 0;
10872 }
10873
10874 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10875 a new number struct loop *loop should be unrolled if tuned for cpus with
10876 a built-in stride prefetcher.
10877 The loop is analyzed for memory accesses by calling check_dpu for
10878 each rtx of the loop. Depending on the loop_depth and the amount of
10879 memory accesses a new number <=nunroll is returned to improve the
10880 behaviour of the hardware prefetch unit. */
10881 static unsigned
10882 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10883 {
10884 basic_block *bbs;
10885 rtx insn;
10886 unsigned i;
10887 unsigned mem_count = 0;
10888
10889 if (s390_tune != PROCESSOR_2097_Z10
10890 && s390_tune != PROCESSOR_2817_Z196
10891 && s390_tune != PROCESSOR_2827_ZEC12)
10892 return nunroll;
10893
10894 /* Count the number of memory references within the loop body. */
10895 bbs = get_loop_body (loop);
10896 for (i = 0; i < loop->num_nodes; i++)
10897 {
10898 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10899 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10900 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10901 }
10902 free (bbs);
10903
10904 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10905 if (mem_count == 0)
10906 return nunroll;
10907
10908 switch (loop_depth(loop))
10909 {
10910 case 1:
10911 return MIN (nunroll, 28 / mem_count);
10912 case 2:
10913 return MIN (nunroll, 22 / mem_count);
10914 default:
10915 return MIN (nunroll, 16 / mem_count);
10916 }
10917 }
10918
10919 /* Initialize GCC target structure. */
10920
10921 #undef TARGET_ASM_ALIGNED_HI_OP
10922 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10923 #undef TARGET_ASM_ALIGNED_DI_OP
10924 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10925 #undef TARGET_ASM_INTEGER
10926 #define TARGET_ASM_INTEGER s390_assemble_integer
10927
10928 #undef TARGET_ASM_OPEN_PAREN
10929 #define TARGET_ASM_OPEN_PAREN ""
10930
10931 #undef TARGET_ASM_CLOSE_PAREN
10932 #define TARGET_ASM_CLOSE_PAREN ""
10933
10934 #undef TARGET_OPTION_OVERRIDE
10935 #define TARGET_OPTION_OVERRIDE s390_option_override
10936
10937 #undef TARGET_ENCODE_SECTION_INFO
10938 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10939
10940 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10941 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10942
10943 #ifdef HAVE_AS_TLS
10944 #undef TARGET_HAVE_TLS
10945 #define TARGET_HAVE_TLS true
10946 #endif
10947 #undef TARGET_CANNOT_FORCE_CONST_MEM
10948 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10949
10950 #undef TARGET_DELEGITIMIZE_ADDRESS
10951 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10952
10953 #undef TARGET_LEGITIMIZE_ADDRESS
10954 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10955
10956 #undef TARGET_RETURN_IN_MEMORY
10957 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10958
10959 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10960 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10961
10962 #undef TARGET_ASM_OUTPUT_MI_THUNK
10963 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10964 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10965 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10966
10967 #undef TARGET_SCHED_ADJUST_PRIORITY
10968 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10969 #undef TARGET_SCHED_ISSUE_RATE
10970 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10971 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10972 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10973
10974 #undef TARGET_SCHED_VARIABLE_ISSUE
10975 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10976 #undef TARGET_SCHED_REORDER
10977 #define TARGET_SCHED_REORDER s390_sched_reorder
10978 #undef TARGET_SCHED_INIT
10979 #define TARGET_SCHED_INIT s390_sched_init
10980
10981 #undef TARGET_CANNOT_COPY_INSN_P
10982 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10983 #undef TARGET_RTX_COSTS
10984 #define TARGET_RTX_COSTS s390_rtx_costs
10985 #undef TARGET_ADDRESS_COST
10986 #define TARGET_ADDRESS_COST s390_address_cost
10987 #undef TARGET_REGISTER_MOVE_COST
10988 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10989 #undef TARGET_MEMORY_MOVE_COST
10990 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10991
10992 #undef TARGET_MACHINE_DEPENDENT_REORG
10993 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10994
10995 #undef TARGET_VALID_POINTER_MODE
10996 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10997
10998 #undef TARGET_BUILD_BUILTIN_VA_LIST
10999 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
11000 #undef TARGET_EXPAND_BUILTIN_VA_START
11001 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
11002 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11003 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
11004
11005 #undef TARGET_PROMOTE_FUNCTION_MODE
11006 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
11007 #undef TARGET_PASS_BY_REFERENCE
11008 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
11009
11010 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11011 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
11012 #undef TARGET_FUNCTION_ARG
11013 #define TARGET_FUNCTION_ARG s390_function_arg
11014 #undef TARGET_FUNCTION_ARG_ADVANCE
11015 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
11016 #undef TARGET_FUNCTION_VALUE
11017 #define TARGET_FUNCTION_VALUE s390_function_value
11018 #undef TARGET_LIBCALL_VALUE
11019 #define TARGET_LIBCALL_VALUE s390_libcall_value
11020
11021 #undef TARGET_FIXED_CONDITION_CODE_REGS
11022 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
11023
11024 #undef TARGET_CC_MODES_COMPATIBLE
11025 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
11026
11027 #undef TARGET_INVALID_WITHIN_DOLOOP
11028 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
11029
11030 #ifdef HAVE_AS_TLS
11031 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
11032 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
11033 #endif
11034
11035 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11036 #undef TARGET_MANGLE_TYPE
11037 #define TARGET_MANGLE_TYPE s390_mangle_type
11038 #endif
11039
11040 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11041 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11042
11043 #undef TARGET_PREFERRED_RELOAD_CLASS
11044 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
11045
11046 #undef TARGET_SECONDARY_RELOAD
11047 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
11048
11049 #undef TARGET_LIBGCC_CMP_RETURN_MODE
11050 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
11051
11052 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
11053 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
11054
11055 #undef TARGET_LEGITIMATE_ADDRESS_P
11056 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
11057
11058 #undef TARGET_LEGITIMATE_CONSTANT_P
11059 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
11060
11061 #undef TARGET_CAN_ELIMINATE
11062 #define TARGET_CAN_ELIMINATE s390_can_eliminate
11063
11064 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11065 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
11066
11067 #undef TARGET_LOOP_UNROLL_ADJUST
11068 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
11069
11070 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11071 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
11072 #undef TARGET_TRAMPOLINE_INIT
11073 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
11074
11075 #undef TARGET_UNWIND_WORD_MODE
11076 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
11077
11078 #undef TARGET_CANONICALIZE_COMPARISON
11079 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
11080
11081 struct gcc_target targetm = TARGET_INITIALIZER;
11082
11083 #include "gt-s390.h"