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[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 02110-1301, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "tree-gimple.h"
54
55
56 /* Define the specific costs for a given cpu. */
57
58 struct processor_costs
59 {
60 /* multiplication */
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
74 /* square root */
75 const int sqdbr; /* cost of square root in DFmode. */
76 const int sqebr; /* cost of square root in SFmode. */
77 /* multiply and add */
78 const int madbr; /* cost of multiply and add in DFmode. */
79 const int maebr; /* cost of multiply and add in SFmode. */
80 /* division */
81 const int ddbr;
82 const int ddr;
83 const int debr;
84 const int der;
85 const int dlgr;
86 const int dlr;
87 const int dr;
88 const int dsgfr;
89 const int dsgr;
90 };
91
92 const struct processor_costs *s390_cost;
93
94 static const
95 struct processor_costs z900_cost =
96 {
97 COSTS_N_INSNS (5), /* M */
98 COSTS_N_INSNS (10), /* MGHI */
99 COSTS_N_INSNS (5), /* MH */
100 COSTS_N_INSNS (4), /* MHI */
101 COSTS_N_INSNS (5), /* ML */
102 COSTS_N_INSNS (5), /* MR */
103 COSTS_N_INSNS (4), /* MS */
104 COSTS_N_INSNS (15), /* MSG */
105 COSTS_N_INSNS (7), /* MSGF */
106 COSTS_N_INSNS (7), /* MSGFR */
107 COSTS_N_INSNS (10), /* MSGR */
108 COSTS_N_INSNS (4), /* MSR */
109 COSTS_N_INSNS (7), /* multiplication in DFmode */
110 COSTS_N_INSNS (44), /* SQDBR */
111 COSTS_N_INSNS (35), /* SQEBR */
112 COSTS_N_INSNS (18), /* MADBR */
113 COSTS_N_INSNS (13), /* MAEBR */
114 COSTS_N_INSNS (30), /* DDBR */
115 COSTS_N_INSNS (30), /* DDR */
116 COSTS_N_INSNS (27), /* DEBR */
117 COSTS_N_INSNS (26), /* DER */
118 COSTS_N_INSNS (220), /* DLGR */
119 COSTS_N_INSNS (34), /* DLR */
120 COSTS_N_INSNS (34), /* DR */
121 COSTS_N_INSNS (32), /* DSGFR */
122 COSTS_N_INSNS (32), /* DSGR */
123 };
124
125 static const
126 struct processor_costs z990_cost =
127 {
128 COSTS_N_INSNS (4), /* M */
129 COSTS_N_INSNS (2), /* MGHI */
130 COSTS_N_INSNS (2), /* MH */
131 COSTS_N_INSNS (2), /* MHI */
132 COSTS_N_INSNS (4), /* ML */
133 COSTS_N_INSNS (4), /* MR */
134 COSTS_N_INSNS (5), /* MS */
135 COSTS_N_INSNS (6), /* MSG */
136 COSTS_N_INSNS (4), /* MSGF */
137 COSTS_N_INSNS (4), /* MSGFR */
138 COSTS_N_INSNS (4), /* MSGR */
139 COSTS_N_INSNS (4), /* MSR */
140 COSTS_N_INSNS (1), /* multiplication in DFmode */
141 COSTS_N_INSNS (66), /* SQDBR */
142 COSTS_N_INSNS (38), /* SQEBR */
143 COSTS_N_INSNS (1), /* MADBR */
144 COSTS_N_INSNS (1), /* MAEBR */
145 COSTS_N_INSNS (40), /* DDBR */
146 COSTS_N_INSNS (44), /* DDR */
147 COSTS_N_INSNS (26), /* DDBR */
148 COSTS_N_INSNS (28), /* DER */
149 COSTS_N_INSNS (176), /* DLGR */
150 COSTS_N_INSNS (31), /* DLR */
151 COSTS_N_INSNS (31), /* DR */
152 COSTS_N_INSNS (31), /* DSGFR */
153 COSTS_N_INSNS (31), /* DSGR */
154 };
155
156 static const
157 struct processor_costs z9_109_cost =
158 {
159 COSTS_N_INSNS (4), /* M */
160 COSTS_N_INSNS (2), /* MGHI */
161 COSTS_N_INSNS (2), /* MH */
162 COSTS_N_INSNS (2), /* MHI */
163 COSTS_N_INSNS (4), /* ML */
164 COSTS_N_INSNS (4), /* MR */
165 COSTS_N_INSNS (5), /* MS */
166 COSTS_N_INSNS (6), /* MSG */
167 COSTS_N_INSNS (4), /* MSGF */
168 COSTS_N_INSNS (4), /* MSGFR */
169 COSTS_N_INSNS (4), /* MSGR */
170 COSTS_N_INSNS (4), /* MSR */
171 COSTS_N_INSNS (1), /* multiplication in DFmode */
172 COSTS_N_INSNS (66), /* SQDBR */
173 COSTS_N_INSNS (38), /* SQEBR */
174 COSTS_N_INSNS (1), /* MADBR */
175 COSTS_N_INSNS (1), /* MAEBR */
176 COSTS_N_INSNS (40), /* DDBR */
177 COSTS_N_INSNS (37), /* DDR */
178 COSTS_N_INSNS (26), /* DDBR */
179 COSTS_N_INSNS (28), /* DER */
180 COSTS_N_INSNS (30), /* DLGR */
181 COSTS_N_INSNS (23), /* DLR */
182 COSTS_N_INSNS (23), /* DR */
183 COSTS_N_INSNS (24), /* DSGFR */
184 COSTS_N_INSNS (24), /* DSGR */
185 };
186
187 extern int reload_completed;
188
189 /* Save information from a "cmpxx" operation until the branch or scc is
190 emitted. */
191 rtx s390_compare_op0, s390_compare_op1;
192
193 /* Save the result of a compare_and_swap until the branch or scc is
194 emitted. */
195 rtx s390_compare_emitted = NULL_RTX;
196
197 /* Structure used to hold the components of a S/390 memory
198 address. A legitimate address on S/390 is of the general
199 form
200 base + index + displacement
201 where any of the components is optional.
202
203 base and index are registers of the class ADDR_REGS,
204 displacement is an unsigned 12-bit immediate constant. */
205
206 struct s390_address
207 {
208 rtx base;
209 rtx indx;
210 rtx disp;
211 bool pointer;
212 bool literal_pool;
213 };
214
215 /* Which cpu are we tuning for. */
216 enum processor_type s390_tune = PROCESSOR_max;
217 enum processor_flags s390_tune_flags;
218 /* Which instruction set architecture to use. */
219 enum processor_type s390_arch;
220 enum processor_flags s390_arch_flags;
221
222 HOST_WIDE_INT s390_warn_framesize = 0;
223 HOST_WIDE_INT s390_stack_size = 0;
224 HOST_WIDE_INT s390_stack_guard = 0;
225
226 /* The following structure is embedded in the machine
227 specific part of struct function. */
228
229 struct s390_frame_layout GTY (())
230 {
231 /* Offset within stack frame. */
232 HOST_WIDE_INT gprs_offset;
233 HOST_WIDE_INT f0_offset;
234 HOST_WIDE_INT f4_offset;
235 HOST_WIDE_INT f8_offset;
236 HOST_WIDE_INT backchain_offset;
237
238 /* Number of first and last gpr where slots in the register
239 save area are reserved for. */
240 int first_save_gpr_slot;
241 int last_save_gpr_slot;
242
243 /* Number of first and last gpr to be saved, restored. */
244 int first_save_gpr;
245 int first_restore_gpr;
246 int last_save_gpr;
247 int last_restore_gpr;
248
249 /* Bits standing for floating point registers. Set, if the
250 respective register has to be saved. Starting with reg 16 (f0)
251 at the rightmost bit.
252 Bit 15 - 8 7 6 5 4 3 2 1 0
253 fpr 15 - 8 7 5 3 1 6 4 2 0
254 reg 31 - 24 23 22 21 20 19 18 17 16 */
255 unsigned int fpr_bitmap;
256
257 /* Number of floating point registers f8-f15 which must be saved. */
258 int high_fprs;
259
260 /* Set if return address needs to be saved.
261 This flag is set by s390_return_addr_rtx if it could not use
262 the initial value of r14 and therefore depends on r14 saved
263 to the stack. */
264 bool save_return_addr_p;
265
266 /* Size of stack frame. */
267 HOST_WIDE_INT frame_size;
268 };
269
270 /* Define the structure for the machine field in struct function. */
271
272 struct machine_function GTY(())
273 {
274 struct s390_frame_layout frame_layout;
275
276 /* Literal pool base register. */
277 rtx base_reg;
278
279 /* True if we may need to perform branch splitting. */
280 bool split_branches_pending_p;
281
282 /* True during final stage of literal pool processing. */
283 bool decomposed_literal_pool_addresses_ok_p;
284
285 /* Some local-dynamic TLS symbol name. */
286 const char *some_ld_name;
287
288 bool has_landing_pad_p;
289 };
290
291 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
292
293 #define cfun_frame_layout (cfun->machine->frame_layout)
294 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
295 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
296 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
297 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
298 (1 << (BITNUM)))
299 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
300 (1 << (BITNUM))))
301
302 /* Number of GPRs and FPRs used for argument passing. */
303 #define GP_ARG_NUM_REG 5
304 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
305
306 /* A couple of shortcuts. */
307 #define CONST_OK_FOR_J(x) \
308 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
309 #define CONST_OK_FOR_K(x) \
310 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
311 #define CONST_OK_FOR_Os(x) \
312 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
313 #define CONST_OK_FOR_Op(x) \
314 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
315 #define CONST_OK_FOR_On(x) \
316 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
317
318 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
319
320 void
321 s390_set_has_landing_pad_p (bool value)
322 {
323 cfun->machine->has_landing_pad_p = value;
324 }
325
326 /* If two condition code modes are compatible, return a condition code
327 mode which is compatible with both. Otherwise, return
328 VOIDmode. */
329
330 static enum machine_mode
331 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
332 {
333 if (m1 == m2)
334 return m1;
335
336 switch (m1)
337 {
338 case CCZmode:
339 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
340 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
341 return m2;
342 return VOIDmode;
343
344 case CCSmode:
345 case CCUmode:
346 case CCTmode:
347 case CCSRmode:
348 case CCURmode:
349 case CCZ1mode:
350 if (m2 == CCZmode)
351 return m1;
352
353 return VOIDmode;
354
355 default:
356 return VOIDmode;
357 }
358 return VOIDmode;
359 }
360
361 /* Return true if SET either doesn't set the CC register, or else
362 the source and destination have matching CC modes and that
363 CC mode is at least as constrained as REQ_MODE. */
364
365 static bool
366 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
367 {
368 enum machine_mode set_mode;
369
370 gcc_assert (GET_CODE (set) == SET);
371
372 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
373 return 1;
374
375 set_mode = GET_MODE (SET_DEST (set));
376 switch (set_mode)
377 {
378 case CCSmode:
379 case CCSRmode:
380 case CCUmode:
381 case CCURmode:
382 case CCLmode:
383 case CCL1mode:
384 case CCL2mode:
385 case CCL3mode:
386 case CCT1mode:
387 case CCT2mode:
388 case CCT3mode:
389 if (req_mode != set_mode)
390 return 0;
391 break;
392
393 case CCZmode:
394 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
395 && req_mode != CCSRmode && req_mode != CCURmode)
396 return 0;
397 break;
398
399 case CCAPmode:
400 case CCANmode:
401 if (req_mode != CCAmode)
402 return 0;
403 break;
404
405 default:
406 gcc_unreachable ();
407 }
408
409 return (GET_MODE (SET_SRC (set)) == set_mode);
410 }
411
412 /* Return true if every SET in INSN that sets the CC register
413 has source and destination with matching CC modes and that
414 CC mode is at least as constrained as REQ_MODE.
415 If REQ_MODE is VOIDmode, always return false. */
416
417 bool
418 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
419 {
420 int i;
421
422 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
423 if (req_mode == VOIDmode)
424 return false;
425
426 if (GET_CODE (PATTERN (insn)) == SET)
427 return s390_match_ccmode_set (PATTERN (insn), req_mode);
428
429 if (GET_CODE (PATTERN (insn)) == PARALLEL)
430 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
431 {
432 rtx set = XVECEXP (PATTERN (insn), 0, i);
433 if (GET_CODE (set) == SET)
434 if (!s390_match_ccmode_set (set, req_mode))
435 return false;
436 }
437
438 return true;
439 }
440
441 /* If a test-under-mask instruction can be used to implement
442 (compare (and ... OP1) OP2), return the CC mode required
443 to do that. Otherwise, return VOIDmode.
444 MIXED is true if the instruction can distinguish between
445 CC1 and CC2 for mixed selected bits (TMxx), it is false
446 if the instruction cannot (TM). */
447
448 enum machine_mode
449 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
450 {
451 int bit0, bit1;
452
453 /* ??? Fixme: should work on CONST_DOUBLE as well. */
454 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
455 return VOIDmode;
456
457 /* Selected bits all zero: CC0.
458 e.g.: int a; if ((a & (16 + 128)) == 0) */
459 if (INTVAL (op2) == 0)
460 return CCTmode;
461
462 /* Selected bits all one: CC3.
463 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
464 if (INTVAL (op2) == INTVAL (op1))
465 return CCT3mode;
466
467 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
468 int a;
469 if ((a & (16 + 128)) == 16) -> CCT1
470 if ((a & (16 + 128)) == 128) -> CCT2 */
471 if (mixed)
472 {
473 bit1 = exact_log2 (INTVAL (op2));
474 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
475 if (bit0 != -1 && bit1 != -1)
476 return bit0 > bit1 ? CCT1mode : CCT2mode;
477 }
478
479 return VOIDmode;
480 }
481
482 /* Given a comparison code OP (EQ, NE, etc.) and the operands
483 OP0 and OP1 of a COMPARE, return the mode to be used for the
484 comparison. */
485
486 enum machine_mode
487 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
488 {
489 switch (code)
490 {
491 case EQ:
492 case NE:
493 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
494 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
495 return CCAPmode;
496 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
497 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
498 return CCAPmode;
499 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
500 || GET_CODE (op1) == NEG)
501 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
502 return CCLmode;
503
504 if (GET_CODE (op0) == AND)
505 {
506 /* Check whether we can potentially do it via TM. */
507 enum machine_mode ccmode;
508 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
509 if (ccmode != VOIDmode)
510 {
511 /* Relax CCTmode to CCZmode to allow fall-back to AND
512 if that turns out to be beneficial. */
513 return ccmode == CCTmode ? CCZmode : ccmode;
514 }
515 }
516
517 if (register_operand (op0, HImode)
518 && GET_CODE (op1) == CONST_INT
519 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
520 return CCT3mode;
521 if (register_operand (op0, QImode)
522 && GET_CODE (op1) == CONST_INT
523 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
524 return CCT3mode;
525
526 return CCZmode;
527
528 case LE:
529 case LT:
530 case GE:
531 case GT:
532 /* The only overflow condition of NEG and ABS happens when
533 -INT_MAX is used as parameter, which stays negative. So
534 we have an overflow from a positive value to a negative.
535 Using CCAP mode the resulting cc can be used for comparisons. */
536 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
537 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
538 return CCAPmode;
539
540 /* If constants are involved in an add instruction it is possible to use
541 the resulting cc for comparisons with zero. Knowing the sign of the
542 constant the overflow behavior gets predictable. e.g.:
543 int a, b; if ((b = a + c) > 0)
544 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
545 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
546 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
547 {
548 if (INTVAL (XEXP((op0), 1)) < 0)
549 return CCANmode;
550 else
551 return CCAPmode;
552 }
553 /* Fall through. */
554 case UNORDERED:
555 case ORDERED:
556 case UNEQ:
557 case UNLE:
558 case UNLT:
559 case UNGE:
560 case UNGT:
561 case LTGT:
562 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
563 && GET_CODE (op1) != CONST_INT)
564 return CCSRmode;
565 return CCSmode;
566
567 case LTU:
568 case GEU:
569 if (GET_CODE (op0) == PLUS
570 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
571 return CCL1mode;
572
573 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
574 && GET_CODE (op1) != CONST_INT)
575 return CCURmode;
576 return CCUmode;
577
578 case LEU:
579 case GTU:
580 if (GET_CODE (op0) == MINUS
581 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
582 return CCL2mode;
583
584 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
585 && GET_CODE (op1) != CONST_INT)
586 return CCURmode;
587 return CCUmode;
588
589 default:
590 gcc_unreachable ();
591 }
592 }
593
594 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
595 that we can implement more efficiently. */
596
597 void
598 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
599 {
600 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
601 if ((*code == EQ || *code == NE)
602 && *op1 == const0_rtx
603 && GET_CODE (*op0) == ZERO_EXTRACT
604 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
605 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
606 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
607 {
608 rtx inner = XEXP (*op0, 0);
609 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
610 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
611 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
612
613 if (len > 0 && len < modesize
614 && pos >= 0 && pos + len <= modesize
615 && modesize <= HOST_BITS_PER_WIDE_INT)
616 {
617 unsigned HOST_WIDE_INT block;
618 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
619 block <<= modesize - pos - len;
620
621 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
622 gen_int_mode (block, GET_MODE (inner)));
623 }
624 }
625
626 /* Narrow AND of memory against immediate to enable TM. */
627 if ((*code == EQ || *code == NE)
628 && *op1 == const0_rtx
629 && GET_CODE (*op0) == AND
630 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
631 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
632 {
633 rtx inner = XEXP (*op0, 0);
634 rtx mask = XEXP (*op0, 1);
635
636 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
637 if (GET_CODE (inner) == SUBREG
638 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
639 && (GET_MODE_SIZE (GET_MODE (inner))
640 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
641 && ((INTVAL (mask)
642 & GET_MODE_MASK (GET_MODE (inner))
643 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
644 == 0))
645 inner = SUBREG_REG (inner);
646
647 /* Do not change volatile MEMs. */
648 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
649 {
650 int part = s390_single_part (XEXP (*op0, 1),
651 GET_MODE (inner), QImode, 0);
652 if (part >= 0)
653 {
654 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
655 inner = adjust_address_nv (inner, QImode, part);
656 *op0 = gen_rtx_AND (QImode, inner, mask);
657 }
658 }
659 }
660
661 /* Narrow comparisons against 0xffff to HImode if possible. */
662 if ((*code == EQ || *code == NE)
663 && GET_CODE (*op1) == CONST_INT
664 && INTVAL (*op1) == 0xffff
665 && SCALAR_INT_MODE_P (GET_MODE (*op0))
666 && (nonzero_bits (*op0, GET_MODE (*op0))
667 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
668 {
669 *op0 = gen_lowpart (HImode, *op0);
670 *op1 = constm1_rtx;
671 }
672
673
674 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
675 if (GET_CODE (*op0) == UNSPEC
676 && XINT (*op0, 1) == UNSPEC_CMPINT
677 && XVECLEN (*op0, 0) == 1
678 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
679 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
680 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
681 && *op1 == const0_rtx)
682 {
683 enum rtx_code new_code = UNKNOWN;
684 switch (*code)
685 {
686 case EQ: new_code = EQ; break;
687 case NE: new_code = NE; break;
688 case LT: new_code = GTU; break;
689 case GT: new_code = LTU; break;
690 case LE: new_code = GEU; break;
691 case GE: new_code = LEU; break;
692 default: break;
693 }
694
695 if (new_code != UNKNOWN)
696 {
697 *op0 = XVECEXP (*op0, 0, 0);
698 *code = new_code;
699 }
700 }
701
702 /* Simplify cascaded EQ, NE with const0_rtx. */
703 if ((*code == NE || *code == EQ)
704 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
705 && GET_MODE (*op0) == SImode
706 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
707 && REG_P (XEXP (*op0, 0))
708 && XEXP (*op0, 1) == const0_rtx
709 && *op1 == const0_rtx)
710 {
711 if ((*code == EQ && GET_CODE (*op0) == NE)
712 || (*code == NE && GET_CODE (*op0) == EQ))
713 *code = EQ;
714 else
715 *code = NE;
716 *op0 = XEXP (*op0, 0);
717 }
718
719 /* Prefer register over memory as first operand. */
720 if (MEM_P (*op0) && REG_P (*op1))
721 {
722 rtx tem = *op0; *op0 = *op1; *op1 = tem;
723 *code = swap_condition (*code);
724 }
725 }
726
727 /* Emit a compare instruction suitable to implement the comparison
728 OP0 CODE OP1. Return the correct condition RTL to be placed in
729 the IF_THEN_ELSE of the conditional branch testing the result. */
730
731 rtx
732 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
733 {
734 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
735 rtx ret = NULL_RTX;
736
737 /* Do not output a redundant compare instruction if a compare_and_swap
738 pattern already computed the result and the machine modes are compatible. */
739 if (s390_compare_emitted
740 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
741 == GET_MODE (s390_compare_emitted)))
742 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
743 else
744 {
745 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
746
747 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
748 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
749 }
750 s390_compare_emitted = NULL_RTX;
751 return ret;
752 }
753
754 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
755 unconditional jump, else a conditional jump under condition COND. */
756
757 void
758 s390_emit_jump (rtx target, rtx cond)
759 {
760 rtx insn;
761
762 target = gen_rtx_LABEL_REF (VOIDmode, target);
763 if (cond)
764 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
765
766 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
767 emit_jump_insn (insn);
768 }
769
770 /* Return branch condition mask to implement a branch
771 specified by CODE. Return -1 for invalid comparisons. */
772
773 int
774 s390_branch_condition_mask (rtx code)
775 {
776 const int CC0 = 1 << 3;
777 const int CC1 = 1 << 2;
778 const int CC2 = 1 << 1;
779 const int CC3 = 1 << 0;
780
781 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
782 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
783 gcc_assert (XEXP (code, 1) == const0_rtx);
784
785 switch (GET_MODE (XEXP (code, 0)))
786 {
787 case CCZmode:
788 case CCZ1mode:
789 switch (GET_CODE (code))
790 {
791 case EQ: return CC0;
792 case NE: return CC1 | CC2 | CC3;
793 default: return -1;
794 }
795 break;
796
797 case CCT1mode:
798 switch (GET_CODE (code))
799 {
800 case EQ: return CC1;
801 case NE: return CC0 | CC2 | CC3;
802 default: return -1;
803 }
804 break;
805
806 case CCT2mode:
807 switch (GET_CODE (code))
808 {
809 case EQ: return CC2;
810 case NE: return CC0 | CC1 | CC3;
811 default: return -1;
812 }
813 break;
814
815 case CCT3mode:
816 switch (GET_CODE (code))
817 {
818 case EQ: return CC3;
819 case NE: return CC0 | CC1 | CC2;
820 default: return -1;
821 }
822 break;
823
824 case CCLmode:
825 switch (GET_CODE (code))
826 {
827 case EQ: return CC0 | CC2;
828 case NE: return CC1 | CC3;
829 default: return -1;
830 }
831 break;
832
833 case CCL1mode:
834 switch (GET_CODE (code))
835 {
836 case LTU: return CC2 | CC3; /* carry */
837 case GEU: return CC0 | CC1; /* no carry */
838 default: return -1;
839 }
840 break;
841
842 case CCL2mode:
843 switch (GET_CODE (code))
844 {
845 case GTU: return CC0 | CC1; /* borrow */
846 case LEU: return CC2 | CC3; /* no borrow */
847 default: return -1;
848 }
849 break;
850
851 case CCL3mode:
852 switch (GET_CODE (code))
853 {
854 case EQ: return CC0 | CC2;
855 case NE: return CC1 | CC3;
856 case LTU: return CC1;
857 case GTU: return CC3;
858 case LEU: return CC1 | CC2;
859 case GEU: return CC2 | CC3;
860 default: return -1;
861 }
862
863 case CCUmode:
864 switch (GET_CODE (code))
865 {
866 case EQ: return CC0;
867 case NE: return CC1 | CC2 | CC3;
868 case LTU: return CC1;
869 case GTU: return CC2;
870 case LEU: return CC0 | CC1;
871 case GEU: return CC0 | CC2;
872 default: return -1;
873 }
874 break;
875
876 case CCURmode:
877 switch (GET_CODE (code))
878 {
879 case EQ: return CC0;
880 case NE: return CC2 | CC1 | CC3;
881 case LTU: return CC2;
882 case GTU: return CC1;
883 case LEU: return CC0 | CC2;
884 case GEU: return CC0 | CC1;
885 default: return -1;
886 }
887 break;
888
889 case CCAPmode:
890 switch (GET_CODE (code))
891 {
892 case EQ: return CC0;
893 case NE: return CC1 | CC2 | CC3;
894 case LT: return CC1 | CC3;
895 case GT: return CC2;
896 case LE: return CC0 | CC1 | CC3;
897 case GE: return CC0 | CC2;
898 default: return -1;
899 }
900 break;
901
902 case CCANmode:
903 switch (GET_CODE (code))
904 {
905 case EQ: return CC0;
906 case NE: return CC1 | CC2 | CC3;
907 case LT: return CC1;
908 case GT: return CC2 | CC3;
909 case LE: return CC0 | CC1;
910 case GE: return CC0 | CC2 | CC3;
911 default: return -1;
912 }
913 break;
914
915 case CCSmode:
916 switch (GET_CODE (code))
917 {
918 case EQ: return CC0;
919 case NE: return CC1 | CC2 | CC3;
920 case LT: return CC1;
921 case GT: return CC2;
922 case LE: return CC0 | CC1;
923 case GE: return CC0 | CC2;
924 case UNORDERED: return CC3;
925 case ORDERED: return CC0 | CC1 | CC2;
926 case UNEQ: return CC0 | CC3;
927 case UNLT: return CC1 | CC3;
928 case UNGT: return CC2 | CC3;
929 case UNLE: return CC0 | CC1 | CC3;
930 case UNGE: return CC0 | CC2 | CC3;
931 case LTGT: return CC1 | CC2;
932 default: return -1;
933 }
934 break;
935
936 case CCSRmode:
937 switch (GET_CODE (code))
938 {
939 case EQ: return CC0;
940 case NE: return CC2 | CC1 | CC3;
941 case LT: return CC2;
942 case GT: return CC1;
943 case LE: return CC0 | CC2;
944 case GE: return CC0 | CC1;
945 case UNORDERED: return CC3;
946 case ORDERED: return CC0 | CC2 | CC1;
947 case UNEQ: return CC0 | CC3;
948 case UNLT: return CC2 | CC3;
949 case UNGT: return CC1 | CC3;
950 case UNLE: return CC0 | CC2 | CC3;
951 case UNGE: return CC0 | CC1 | CC3;
952 case LTGT: return CC2 | CC1;
953 default: return -1;
954 }
955 break;
956
957 default:
958 return -1;
959 }
960 }
961
962 /* If INV is false, return assembler mnemonic string to implement
963 a branch specified by CODE. If INV is true, return mnemonic
964 for the corresponding inverted branch. */
965
966 static const char *
967 s390_branch_condition_mnemonic (rtx code, int inv)
968 {
969 static const char *const mnemonic[16] =
970 {
971 NULL, "o", "h", "nle",
972 "l", "nhe", "lh", "ne",
973 "e", "nlh", "he", "nl",
974 "le", "nh", "no", NULL
975 };
976
977 int mask = s390_branch_condition_mask (code);
978 gcc_assert (mask >= 0);
979
980 if (inv)
981 mask ^= 15;
982
983 gcc_assert (mask >= 1 && mask <= 14);
984
985 return mnemonic[mask];
986 }
987
988 /* Return the part of op which has a value different from def.
989 The size of the part is determined by mode.
990 Use this function only if you already know that op really
991 contains such a part. */
992
993 unsigned HOST_WIDE_INT
994 s390_extract_part (rtx op, enum machine_mode mode, int def)
995 {
996 unsigned HOST_WIDE_INT value = 0;
997 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
998 int part_bits = GET_MODE_BITSIZE (mode);
999 unsigned HOST_WIDE_INT part_mask
1000 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1001 int i;
1002
1003 for (i = 0; i < max_parts; i++)
1004 {
1005 if (i == 0)
1006 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1007 else
1008 value >>= part_bits;
1009
1010 if ((value & part_mask) != (def & part_mask))
1011 return value & part_mask;
1012 }
1013
1014 gcc_unreachable ();
1015 }
1016
1017 /* If OP is an integer constant of mode MODE with exactly one
1018 part of mode PART_MODE unequal to DEF, return the number of that
1019 part. Otherwise, return -1. */
1020
1021 int
1022 s390_single_part (rtx op,
1023 enum machine_mode mode,
1024 enum machine_mode part_mode,
1025 int def)
1026 {
1027 unsigned HOST_WIDE_INT value = 0;
1028 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1029 unsigned HOST_WIDE_INT part_mask
1030 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1031 int i, part = -1;
1032
1033 if (GET_CODE (op) != CONST_INT)
1034 return -1;
1035
1036 for (i = 0; i < n_parts; i++)
1037 {
1038 if (i == 0)
1039 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1040 else
1041 value >>= GET_MODE_BITSIZE (part_mode);
1042
1043 if ((value & part_mask) != (def & part_mask))
1044 {
1045 if (part != -1)
1046 return -1;
1047 else
1048 part = i;
1049 }
1050 }
1051 return part == -1 ? -1 : n_parts - 1 - part;
1052 }
1053
1054 /* Check whether we can (and want to) split a double-word
1055 move in mode MODE from SRC to DST into two single-word
1056 moves, moving the subword FIRST_SUBWORD first. */
1057
1058 bool
1059 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1060 {
1061 /* Floating point registers cannot be split. */
1062 if (FP_REG_P (src) || FP_REG_P (dst))
1063 return false;
1064
1065 /* We don't need to split if operands are directly accessible. */
1066 if (s_operand (src, mode) || s_operand (dst, mode))
1067 return false;
1068
1069 /* Non-offsettable memory references cannot be split. */
1070 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1071 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1072 return false;
1073
1074 /* Moving the first subword must not clobber a register
1075 needed to move the second subword. */
1076 if (register_operand (dst, mode))
1077 {
1078 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1079 if (reg_overlap_mentioned_p (subreg, src))
1080 return false;
1081 }
1082
1083 return true;
1084 }
1085
1086 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1087 and [MEM2, MEM2 + SIZE] do overlap and false
1088 otherwise. */
1089
1090 bool
1091 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1092 {
1093 rtx addr1, addr2, addr_delta;
1094 HOST_WIDE_INT delta;
1095
1096 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1097 return true;
1098
1099 if (size == 0)
1100 return false;
1101
1102 addr1 = XEXP (mem1, 0);
1103 addr2 = XEXP (mem2, 0);
1104
1105 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1106
1107 /* This overlapping check is used by peepholes merging memory block operations.
1108 Overlapping operations would otherwise be recognized by the S/390 hardware
1109 and would fall back to a slower implementation. Allowing overlapping
1110 operations would lead to slow code but not to wrong code. Therefore we are
1111 somewhat optimistic if we cannot prove that the memory blocks are
1112 overlapping.
1113 That's why we return false here although this may accept operations on
1114 overlapping memory areas. */
1115 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1116 return false;
1117
1118 delta = INTVAL (addr_delta);
1119
1120 if (delta == 0
1121 || (delta > 0 && delta < size)
1122 || (delta < 0 && -delta < size))
1123 return true;
1124
1125 return false;
1126 }
1127
1128 /* Check whether the address of memory reference MEM2 equals exactly
1129 the address of memory reference MEM1 plus DELTA. Return true if
1130 we can prove this to be the case, false otherwise. */
1131
1132 bool
1133 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1134 {
1135 rtx addr1, addr2, addr_delta;
1136
1137 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1138 return false;
1139
1140 addr1 = XEXP (mem1, 0);
1141 addr2 = XEXP (mem2, 0);
1142
1143 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1144 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1145 return false;
1146
1147 return true;
1148 }
1149
1150 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1151
1152 void
1153 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1154 rtx *operands)
1155 {
1156 enum machine_mode wmode = mode;
1157 rtx dst = operands[0];
1158 rtx src1 = operands[1];
1159 rtx src2 = operands[2];
1160 rtx op, clob, tem;
1161
1162 /* If we cannot handle the operation directly, use a temp register. */
1163 if (!s390_logical_operator_ok_p (operands))
1164 dst = gen_reg_rtx (mode);
1165
1166 /* QImode and HImode patterns make sense only if we have a destination
1167 in memory. Otherwise perform the operation in SImode. */
1168 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1169 wmode = SImode;
1170
1171 /* Widen operands if required. */
1172 if (mode != wmode)
1173 {
1174 if (GET_CODE (dst) == SUBREG
1175 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1176 dst = tem;
1177 else if (REG_P (dst))
1178 dst = gen_rtx_SUBREG (wmode, dst, 0);
1179 else
1180 dst = gen_reg_rtx (wmode);
1181
1182 if (GET_CODE (src1) == SUBREG
1183 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1184 src1 = tem;
1185 else if (GET_MODE (src1) != VOIDmode)
1186 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1187
1188 if (GET_CODE (src2) == SUBREG
1189 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1190 src2 = tem;
1191 else if (GET_MODE (src2) != VOIDmode)
1192 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1193 }
1194
1195 /* Emit the instruction. */
1196 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1197 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1198 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1199
1200 /* Fix up the destination if needed. */
1201 if (dst != operands[0])
1202 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1203 }
1204
1205 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1206
1207 bool
1208 s390_logical_operator_ok_p (rtx *operands)
1209 {
1210 /* If the destination operand is in memory, it needs to coincide
1211 with one of the source operands. After reload, it has to be
1212 the first source operand. */
1213 if (GET_CODE (operands[0]) == MEM)
1214 return rtx_equal_p (operands[0], operands[1])
1215 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1216
1217 return true;
1218 }
1219
1220 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1221 operand IMMOP to switch from SS to SI type instructions. */
1222
1223 void
1224 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1225 {
1226 int def = code == AND ? -1 : 0;
1227 HOST_WIDE_INT mask;
1228 int part;
1229
1230 gcc_assert (GET_CODE (*memop) == MEM);
1231 gcc_assert (!MEM_VOLATILE_P (*memop));
1232
1233 mask = s390_extract_part (*immop, QImode, def);
1234 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1235 gcc_assert (part >= 0);
1236
1237 *memop = adjust_address (*memop, QImode, part);
1238 *immop = gen_int_mode (mask, QImode);
1239 }
1240
1241
1242 /* How to allocate a 'struct machine_function'. */
1243
1244 static struct machine_function *
1245 s390_init_machine_status (void)
1246 {
1247 return ggc_alloc_cleared (sizeof (struct machine_function));
1248 }
1249
1250 /* Change optimizations to be performed, depending on the
1251 optimization level.
1252
1253 LEVEL is the optimization level specified; 2 if `-O2' is
1254 specified, 1 if `-O' is specified, and 0 if neither is specified.
1255
1256 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1257
1258 void
1259 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1260 {
1261 /* ??? There are apparently still problems with -fcaller-saves. */
1262 flag_caller_saves = 0;
1263
1264 /* By default, always emit DWARF-2 unwind info. This allows debugging
1265 without maintaining a stack frame back-chain. */
1266 flag_asynchronous_unwind_tables = 1;
1267
1268 /* Use MVCLE instructions to decrease code size if requested. */
1269 if (size != 0)
1270 target_flags |= MASK_MVCLE;
1271 }
1272
1273 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1274 to the associated processor_type and processor_flags if so. */
1275
1276 static bool
1277 s390_handle_arch_option (const char *arg,
1278 enum processor_type *type,
1279 enum processor_flags *flags)
1280 {
1281 static struct pta
1282 {
1283 const char *const name; /* processor name or nickname. */
1284 const enum processor_type processor;
1285 const enum processor_flags flags;
1286 }
1287 const processor_alias_table[] =
1288 {
1289 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1290 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1291 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1292 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1293 | PF_LONG_DISPLACEMENT},
1294 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1295 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1296 };
1297 size_t i;
1298
1299 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1300 if (strcmp (arg, processor_alias_table[i].name) == 0)
1301 {
1302 *type = processor_alias_table[i].processor;
1303 *flags = processor_alias_table[i].flags;
1304 return true;
1305 }
1306 return false;
1307 }
1308
1309 /* Implement TARGET_HANDLE_OPTION. */
1310
1311 static bool
1312 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1313 {
1314 switch (code)
1315 {
1316 case OPT_march_:
1317 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1318
1319 case OPT_mstack_guard_:
1320 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1321 return false;
1322 if (exact_log2 (s390_stack_guard) == -1)
1323 error ("stack guard value must be an exact power of 2");
1324 return true;
1325
1326 case OPT_mstack_size_:
1327 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1328 return false;
1329 if (exact_log2 (s390_stack_size) == -1)
1330 error ("stack size must be an exact power of 2");
1331 return true;
1332
1333 case OPT_mtune_:
1334 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1335
1336 case OPT_mwarn_framesize_:
1337 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1338
1339 default:
1340 return true;
1341 }
1342 }
1343
1344 void
1345 override_options (void)
1346 {
1347 /* Set up function hooks. */
1348 init_machine_status = s390_init_machine_status;
1349
1350 /* Architecture mode defaults according to ABI. */
1351 if (!(target_flags_explicit & MASK_ZARCH))
1352 {
1353 if (TARGET_64BIT)
1354 target_flags |= MASK_ZARCH;
1355 else
1356 target_flags &= ~MASK_ZARCH;
1357 }
1358
1359 /* Determine processor architectural level. */
1360 if (!s390_arch_string)
1361 {
1362 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1363 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1364 }
1365
1366 /* Determine processor to tune for. */
1367 if (s390_tune == PROCESSOR_max)
1368 {
1369 s390_tune = s390_arch;
1370 s390_tune_flags = s390_arch_flags;
1371 }
1372
1373 /* Sanity checks. */
1374 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1375 error ("z/Architecture mode not supported on %s", s390_arch_string);
1376 if (TARGET_64BIT && !TARGET_ZARCH)
1377 error ("64-bit ABI not supported in ESA/390 mode");
1378
1379 /* Set processor cost function. */
1380 if (s390_tune == PROCESSOR_2094_Z9_109)
1381 s390_cost = &z9_109_cost;
1382 else if (s390_tune == PROCESSOR_2084_Z990)
1383 s390_cost = &z990_cost;
1384 else
1385 s390_cost = &z900_cost;
1386
1387 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1388 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1389 "in combination");
1390
1391 if (s390_stack_size)
1392 {
1393 if (!s390_stack_guard)
1394 error ("-mstack-size implies use of -mstack-guard");
1395 else if (s390_stack_guard >= s390_stack_size)
1396 error ("stack size must be greater than the stack guard value");
1397 else if (s390_stack_size > 1 << 16)
1398 error ("stack size must not be greater than 64k");
1399 }
1400 else if (s390_stack_guard)
1401 error ("-mstack-guard implies use of -mstack-size");
1402 }
1403
1404 /* Map for smallest class containing reg regno. */
1405
1406 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1407 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1408 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1409 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1410 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1411 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1412 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1413 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1414 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1415 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1416 ACCESS_REGS, ACCESS_REGS
1417 };
1418
1419 /* Return attribute type of insn. */
1420
1421 static enum attr_type
1422 s390_safe_attr_type (rtx insn)
1423 {
1424 if (recog_memoized (insn) >= 0)
1425 return get_attr_type (insn);
1426 else
1427 return TYPE_NONE;
1428 }
1429
1430 /* Return true if DISP is a valid short displacement. */
1431
1432 static bool
1433 s390_short_displacement (rtx disp)
1434 {
1435 /* No displacement is OK. */
1436 if (!disp)
1437 return true;
1438
1439 /* Integer displacement in range. */
1440 if (GET_CODE (disp) == CONST_INT)
1441 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1442
1443 /* GOT offset is not OK, the GOT can be large. */
1444 if (GET_CODE (disp) == CONST
1445 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1446 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1447 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1448 return false;
1449
1450 /* All other symbolic constants are literal pool references,
1451 which are OK as the literal pool must be small. */
1452 if (GET_CODE (disp) == CONST)
1453 return true;
1454
1455 return false;
1456 }
1457
1458 /* Decompose a RTL expression ADDR for a memory address into
1459 its components, returned in OUT.
1460
1461 Returns false if ADDR is not a valid memory address, true
1462 otherwise. If OUT is NULL, don't return the components,
1463 but check for validity only.
1464
1465 Note: Only addresses in canonical form are recognized.
1466 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1467 canonical form so that they will be recognized. */
1468
1469 static int
1470 s390_decompose_address (rtx addr, struct s390_address *out)
1471 {
1472 HOST_WIDE_INT offset = 0;
1473 rtx base = NULL_RTX;
1474 rtx indx = NULL_RTX;
1475 rtx disp = NULL_RTX;
1476 rtx orig_disp;
1477 bool pointer = false;
1478 bool base_ptr = false;
1479 bool indx_ptr = false;
1480 bool literal_pool = false;
1481
1482 /* We may need to substitute the literal pool base register into the address
1483 below. However, at this point we do not know which register is going to
1484 be used as base, so we substitute the arg pointer register. This is going
1485 to be treated as holding a pointer below -- it shouldn't be used for any
1486 other purpose. */
1487 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1488
1489 /* Decompose address into base + index + displacement. */
1490
1491 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1492 base = addr;
1493
1494 else if (GET_CODE (addr) == PLUS)
1495 {
1496 rtx op0 = XEXP (addr, 0);
1497 rtx op1 = XEXP (addr, 1);
1498 enum rtx_code code0 = GET_CODE (op0);
1499 enum rtx_code code1 = GET_CODE (op1);
1500
1501 if (code0 == REG || code0 == UNSPEC)
1502 {
1503 if (code1 == REG || code1 == UNSPEC)
1504 {
1505 indx = op0; /* index + base */
1506 base = op1;
1507 }
1508
1509 else
1510 {
1511 base = op0; /* base + displacement */
1512 disp = op1;
1513 }
1514 }
1515
1516 else if (code0 == PLUS)
1517 {
1518 indx = XEXP (op0, 0); /* index + base + disp */
1519 base = XEXP (op0, 1);
1520 disp = op1;
1521 }
1522
1523 else
1524 {
1525 return false;
1526 }
1527 }
1528
1529 else
1530 disp = addr; /* displacement */
1531
1532 /* Extract integer part of displacement. */
1533 orig_disp = disp;
1534 if (disp)
1535 {
1536 if (GET_CODE (disp) == CONST_INT)
1537 {
1538 offset = INTVAL (disp);
1539 disp = NULL_RTX;
1540 }
1541 else if (GET_CODE (disp) == CONST
1542 && GET_CODE (XEXP (disp, 0)) == PLUS
1543 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1544 {
1545 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1546 disp = XEXP (XEXP (disp, 0), 0);
1547 }
1548 }
1549
1550 /* Strip off CONST here to avoid special case tests later. */
1551 if (disp && GET_CODE (disp) == CONST)
1552 disp = XEXP (disp, 0);
1553
1554 /* We can convert literal pool addresses to
1555 displacements by basing them off the base register. */
1556 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1557 {
1558 /* Either base or index must be free to hold the base register. */
1559 if (!base)
1560 base = fake_pool_base, literal_pool = true;
1561 else if (!indx)
1562 indx = fake_pool_base, literal_pool = true;
1563 else
1564 return false;
1565
1566 /* Mark up the displacement. */
1567 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1568 UNSPEC_LTREL_OFFSET);
1569 }
1570
1571 /* Validate base register. */
1572 if (base)
1573 {
1574 if (GET_CODE (base) == UNSPEC)
1575 switch (XINT (base, 1))
1576 {
1577 case UNSPEC_LTREF:
1578 if (!disp)
1579 disp = gen_rtx_UNSPEC (Pmode,
1580 gen_rtvec (1, XVECEXP (base, 0, 0)),
1581 UNSPEC_LTREL_OFFSET);
1582 else
1583 return false;
1584
1585 base = XVECEXP (base, 0, 1);
1586 break;
1587
1588 case UNSPEC_LTREL_BASE:
1589 if (XVECLEN (base, 0) == 1)
1590 base = fake_pool_base, literal_pool = true;
1591 else
1592 base = XVECEXP (base, 0, 1);
1593 break;
1594
1595 default:
1596 return false;
1597 }
1598
1599 if (GET_CODE (base) != REG || GET_MODE (base) != Pmode)
1600 return false;
1601
1602 if (REGNO (base) == STACK_POINTER_REGNUM
1603 || REGNO (base) == FRAME_POINTER_REGNUM
1604 || ((reload_completed || reload_in_progress)
1605 && frame_pointer_needed
1606 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1607 || REGNO (base) == ARG_POINTER_REGNUM
1608 || (flag_pic
1609 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1610 pointer = base_ptr = true;
1611
1612 if ((reload_completed || reload_in_progress)
1613 && base == cfun->machine->base_reg)
1614 pointer = base_ptr = literal_pool = true;
1615 }
1616
1617 /* Validate index register. */
1618 if (indx)
1619 {
1620 if (GET_CODE (indx) == UNSPEC)
1621 switch (XINT (indx, 1))
1622 {
1623 case UNSPEC_LTREF:
1624 if (!disp)
1625 disp = gen_rtx_UNSPEC (Pmode,
1626 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1627 UNSPEC_LTREL_OFFSET);
1628 else
1629 return false;
1630
1631 indx = XVECEXP (indx, 0, 1);
1632 break;
1633
1634 case UNSPEC_LTREL_BASE:
1635 if (XVECLEN (indx, 0) == 1)
1636 indx = fake_pool_base, literal_pool = true;
1637 else
1638 indx = XVECEXP (indx, 0, 1);
1639 break;
1640
1641 default:
1642 return false;
1643 }
1644
1645 if (GET_CODE (indx) != REG || GET_MODE (indx) != Pmode)
1646 return false;
1647
1648 if (REGNO (indx) == STACK_POINTER_REGNUM
1649 || REGNO (indx) == FRAME_POINTER_REGNUM
1650 || ((reload_completed || reload_in_progress)
1651 && frame_pointer_needed
1652 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1653 || REGNO (indx) == ARG_POINTER_REGNUM
1654 || (flag_pic
1655 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1656 pointer = indx_ptr = true;
1657
1658 if ((reload_completed || reload_in_progress)
1659 && indx == cfun->machine->base_reg)
1660 pointer = indx_ptr = literal_pool = true;
1661 }
1662
1663 /* Prefer to use pointer as base, not index. */
1664 if (base && indx && !base_ptr
1665 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1666 {
1667 rtx tmp = base;
1668 base = indx;
1669 indx = tmp;
1670 }
1671
1672 /* Validate displacement. */
1673 if (!disp)
1674 {
1675 /* If virtual registers are involved, the displacement will change later
1676 anyway as the virtual registers get eliminated. This could make a
1677 valid displacement invalid, but it is more likely to make an invalid
1678 displacement valid, because we sometimes access the register save area
1679 via negative offsets to one of those registers.
1680 Thus we don't check the displacement for validity here. If after
1681 elimination the displacement turns out to be invalid after all,
1682 this is fixed up by reload in any case. */
1683 if (base != arg_pointer_rtx
1684 && indx != arg_pointer_rtx
1685 && base != return_address_pointer_rtx
1686 && indx != return_address_pointer_rtx
1687 && base != frame_pointer_rtx
1688 && indx != frame_pointer_rtx
1689 && base != virtual_stack_vars_rtx
1690 && indx != virtual_stack_vars_rtx)
1691 if (!DISP_IN_RANGE (offset))
1692 return false;
1693 }
1694 else
1695 {
1696 /* All the special cases are pointers. */
1697 pointer = true;
1698
1699 /* In the small-PIC case, the linker converts @GOT
1700 and @GOTNTPOFF offsets to possible displacements. */
1701 if (GET_CODE (disp) == UNSPEC
1702 && (XINT (disp, 1) == UNSPEC_GOT
1703 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1704 && offset == 0
1705 && flag_pic == 1)
1706 {
1707 ;
1708 }
1709
1710 /* Accept chunkified literal pool symbol references. */
1711 else if (cfun && cfun->machine
1712 && cfun->machine->decomposed_literal_pool_addresses_ok_p
1713 && GET_CODE (disp) == MINUS
1714 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1715 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1716 {
1717 ;
1718 }
1719
1720 /* Accept literal pool references. */
1721 else if (GET_CODE (disp) == UNSPEC
1722 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1723 {
1724 orig_disp = gen_rtx_CONST (Pmode, disp);
1725 if (offset)
1726 {
1727 /* If we have an offset, make sure it does not
1728 exceed the size of the constant pool entry. */
1729 rtx sym = XVECEXP (disp, 0, 0);
1730 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1731 return false;
1732
1733 orig_disp = plus_constant (orig_disp, offset);
1734 }
1735 }
1736
1737 else
1738 return false;
1739 }
1740
1741 if (!base && !indx)
1742 pointer = true;
1743
1744 if (out)
1745 {
1746 out->base = base;
1747 out->indx = indx;
1748 out->disp = orig_disp;
1749 out->pointer = pointer;
1750 out->literal_pool = literal_pool;
1751 }
1752
1753 return true;
1754 }
1755
1756 /* Decompose a RTL expression OP for a shift count into its components,
1757 and return the base register in BASE and the offset in OFFSET.
1758
1759 Return true if OP is a valid shift count, false if not. */
1760
1761 bool
1762 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1763 {
1764 HOST_WIDE_INT off = 0;
1765
1766 /* We can have an integer constant, an address register,
1767 or a sum of the two. */
1768 if (GET_CODE (op) == CONST_INT)
1769 {
1770 off = INTVAL (op);
1771 op = NULL_RTX;
1772 }
1773 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1774 {
1775 off = INTVAL (XEXP (op, 1));
1776 op = XEXP (op, 0);
1777 }
1778 while (op && GET_CODE (op) == SUBREG)
1779 op = SUBREG_REG (op);
1780
1781 if (op && GET_CODE (op) != REG)
1782 return false;
1783
1784 if (offset)
1785 *offset = off;
1786 if (base)
1787 *base = op;
1788
1789 return true;
1790 }
1791
1792
1793 /* Return true if CODE is a valid address without index. */
1794
1795 bool
1796 s390_legitimate_address_without_index_p (rtx op)
1797 {
1798 struct s390_address addr;
1799
1800 if (!s390_decompose_address (XEXP (op, 0), &addr))
1801 return false;
1802 if (addr.indx)
1803 return false;
1804
1805 return true;
1806 }
1807
1808 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1809
1810 int
1811 s390_extra_constraint_str (rtx op, int c, const char * str)
1812 {
1813 struct s390_address addr;
1814
1815 gcc_assert (c == str[0]);
1816
1817 /* Check for offsettable variants of memory constraints. */
1818 if (c == 'A')
1819 {
1820 /* Only accept non-volatile MEMs. */
1821 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1822 return 0;
1823
1824 if ((reload_completed || reload_in_progress)
1825 ? !offsettable_memref_p (op)
1826 : !offsettable_nonstrict_memref_p (op))
1827 return 0;
1828
1829 c = str[1];
1830 }
1831
1832 /* Check for non-literal-pool variants of memory constraints. */
1833 else if (c == 'B')
1834 {
1835 if (GET_CODE (op) != MEM)
1836 return 0;
1837 if (!s390_decompose_address (XEXP (op, 0), &addr))
1838 return 0;
1839 if (addr.literal_pool)
1840 return 0;
1841
1842 c = str[1];
1843 }
1844
1845 switch (c)
1846 {
1847 case 'Q':
1848 if (GET_CODE (op) != MEM)
1849 return 0;
1850 if (!s390_decompose_address (XEXP (op, 0), &addr))
1851 return 0;
1852 if (addr.indx)
1853 return 0;
1854
1855 if (TARGET_LONG_DISPLACEMENT)
1856 {
1857 if (!s390_short_displacement (addr.disp))
1858 return 0;
1859 }
1860 break;
1861
1862 case 'R':
1863 if (GET_CODE (op) != MEM)
1864 return 0;
1865
1866 if (TARGET_LONG_DISPLACEMENT)
1867 {
1868 if (!s390_decompose_address (XEXP (op, 0), &addr))
1869 return 0;
1870 if (!s390_short_displacement (addr.disp))
1871 return 0;
1872 }
1873 break;
1874
1875 case 'S':
1876 if (!TARGET_LONG_DISPLACEMENT)
1877 return 0;
1878 if (GET_CODE (op) != MEM)
1879 return 0;
1880 if (!s390_decompose_address (XEXP (op, 0), &addr))
1881 return 0;
1882 if (addr.indx)
1883 return 0;
1884 if (s390_short_displacement (addr.disp))
1885 return 0;
1886 break;
1887
1888 case 'T':
1889 if (!TARGET_LONG_DISPLACEMENT)
1890 return 0;
1891 if (GET_CODE (op) != MEM)
1892 return 0;
1893 /* Any invalid address here will be fixed up by reload,
1894 so accept it for the most generic constraint. */
1895 if (s390_decompose_address (XEXP (op, 0), &addr)
1896 && s390_short_displacement (addr.disp))
1897 return 0;
1898 break;
1899
1900 case 'U':
1901 if (TARGET_LONG_DISPLACEMENT)
1902 {
1903 if (!s390_decompose_address (op, &addr))
1904 return 0;
1905 if (!s390_short_displacement (addr.disp))
1906 return 0;
1907 }
1908 break;
1909
1910 case 'W':
1911 if (!TARGET_LONG_DISPLACEMENT)
1912 return 0;
1913 /* Any invalid address here will be fixed up by reload,
1914 so accept it for the most generic constraint. */
1915 if (s390_decompose_address (op, &addr)
1916 && s390_short_displacement (addr.disp))
1917 return 0;
1918 break;
1919
1920 case 'Y':
1921 /* Simply check for the basic form of a shift count. Reload will
1922 take care of making sure we have a proper base register. */
1923 if (!s390_decompose_shift_count (op, NULL, NULL))
1924 return 0;
1925 break;
1926
1927 default:
1928 return 0;
1929 }
1930
1931 return 1;
1932 }
1933
1934 /* Return true if VALUE matches the constraint STR. */
1935
1936 int
1937 s390_const_double_ok_for_constraint_p (rtx value,
1938 int c,
1939 const char * str)
1940 {
1941 gcc_assert (c == str[0]);
1942
1943 switch (str[0])
1944 {
1945 case 'G':
1946 /* The floating point zero constant. */
1947 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1948 && value == CONST0_RTX (GET_MODE (value)));
1949
1950 default:
1951 return 0;
1952 }
1953 }
1954
1955 /* Return true if VALUE matches the constraint STR. */
1956
1957 int
1958 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1959 int c,
1960 const char * str)
1961 {
1962 enum machine_mode mode, part_mode;
1963 int def;
1964 int part, part_goal;
1965
1966 gcc_assert (c == str[0]);
1967
1968 switch (str[0])
1969 {
1970 case 'I':
1971 return (unsigned int)value < 256;
1972
1973 case 'J':
1974 return (unsigned int)value < 4096;
1975
1976 case 'K':
1977 return value >= -32768 && value < 32768;
1978
1979 case 'L':
1980 return (TARGET_LONG_DISPLACEMENT ?
1981 (value >= -524288 && value <= 524287)
1982 : (value >= 0 && value <= 4095));
1983 case 'M':
1984 return value == 2147483647;
1985
1986 case 'N':
1987 if (str[1] == 'x')
1988 part_goal = -1;
1989 else
1990 part_goal = str[1] - '0';
1991
1992 switch (str[2])
1993 {
1994 case 'Q': part_mode = QImode; break;
1995 case 'H': part_mode = HImode; break;
1996 case 'S': part_mode = SImode; break;
1997 default: return 0;
1998 }
1999
2000 switch (str[3])
2001 {
2002 case 'H': mode = HImode; break;
2003 case 'S': mode = SImode; break;
2004 case 'D': mode = DImode; break;
2005 default: return 0;
2006 }
2007
2008 switch (str[4])
2009 {
2010 case '0': def = 0; break;
2011 case 'F': def = -1; break;
2012 default: return 0;
2013 }
2014
2015 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2016 return 0;
2017
2018 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2019 if (part < 0)
2020 return 0;
2021 if (part_goal != -1 && part_goal != part)
2022 return 0;
2023
2024 break;
2025
2026 case 'O':
2027 if (!TARGET_EXTIMM)
2028 return 0;
2029
2030 switch (str[1])
2031 {
2032 case 's':
2033 return trunc_int_for_mode (value, SImode) == value;
2034
2035 case 'p':
2036 return value == 0
2037 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2038
2039 case 'n':
2040 return value == -1
2041 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
2042
2043 default:
2044 gcc_unreachable ();
2045 }
2046 break;
2047
2048 case 'P':
2049 return legitimate_reload_constant_p (GEN_INT (value));
2050
2051 default:
2052 return 0;
2053 }
2054
2055 return 1;
2056 }
2057
2058 /* Compute a (partial) cost for rtx X. Return true if the complete
2059 cost has been computed, and false if subexpressions should be
2060 scanned. In either case, *TOTAL contains the cost result.
2061 CODE contains GET_CODE (x), OUTER_CODE contains the code
2062 of the superexpression of x. */
2063
2064 static bool
2065 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2066 {
2067 switch (code)
2068 {
2069 case CONST:
2070 case CONST_INT:
2071 case LABEL_REF:
2072 case SYMBOL_REF:
2073 case CONST_DOUBLE:
2074 case MEM:
2075 *total = 0;
2076 return true;
2077
2078 case ASHIFT:
2079 case ASHIFTRT:
2080 case LSHIFTRT:
2081 case ROTATE:
2082 case ROTATERT:
2083 case AND:
2084 case IOR:
2085 case XOR:
2086 case NEG:
2087 case NOT:
2088 *total = COSTS_N_INSNS (1);
2089 return false;
2090
2091 case PLUS:
2092 case MINUS:
2093 /* Check for multiply and add. */
2094 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2095 && GET_CODE (XEXP (x, 0)) == MULT
2096 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2097 {
2098 /* This is the multiply and add case. */
2099 if (GET_MODE (x) == DFmode)
2100 *total = s390_cost->madbr;
2101 else
2102 *total = s390_cost->maebr;
2103 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2104 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2105 + rtx_cost (XEXP (x, 1), code);
2106 return true; /* Do not do an additional recursive descent. */
2107 }
2108 *total = COSTS_N_INSNS (1);
2109 return false;
2110
2111 case MULT:
2112 switch (GET_MODE (x))
2113 {
2114 case SImode:
2115 {
2116 rtx left = XEXP (x, 0);
2117 rtx right = XEXP (x, 1);
2118 if (GET_CODE (right) == CONST_INT
2119 && CONST_OK_FOR_K (INTVAL (right)))
2120 *total = s390_cost->mhi;
2121 else if (GET_CODE (left) == SIGN_EXTEND)
2122 *total = s390_cost->mh;
2123 else
2124 *total = s390_cost->ms; /* msr, ms, msy */
2125 break;
2126 }
2127 case DImode:
2128 {
2129 rtx left = XEXP (x, 0);
2130 rtx right = XEXP (x, 1);
2131 if (TARGET_64BIT)
2132 {
2133 if (GET_CODE (right) == CONST_INT
2134 && CONST_OK_FOR_K (INTVAL (right)))
2135 *total = s390_cost->mghi;
2136 else if (GET_CODE (left) == SIGN_EXTEND)
2137 *total = s390_cost->msgf;
2138 else
2139 *total = s390_cost->msg; /* msgr, msg */
2140 }
2141 else /* TARGET_31BIT */
2142 {
2143 if (GET_CODE (left) == SIGN_EXTEND
2144 && GET_CODE (right) == SIGN_EXTEND)
2145 /* mulsidi case: mr, m */
2146 *total = s390_cost->m;
2147 else if (GET_CODE (left) == ZERO_EXTEND
2148 && GET_CODE (right) == ZERO_EXTEND
2149 && TARGET_CPU_ZARCH)
2150 /* umulsidi case: ml, mlr */
2151 *total = s390_cost->ml;
2152 else
2153 /* Complex calculation is required. */
2154 *total = COSTS_N_INSNS (40);
2155 }
2156 break;
2157 }
2158 case SFmode:
2159 case DFmode:
2160 *total = s390_cost->mult_df;
2161 break;
2162 default:
2163 return false;
2164 }
2165 return false;
2166
2167 case UDIV:
2168 case UMOD:
2169 if (GET_MODE (x) == TImode) /* 128 bit division */
2170 *total = s390_cost->dlgr;
2171 else if (GET_MODE (x) == DImode)
2172 {
2173 rtx right = XEXP (x, 1);
2174 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2175 *total = s390_cost->dlr;
2176 else /* 64 by 64 bit division */
2177 *total = s390_cost->dlgr;
2178 }
2179 else if (GET_MODE (x) == SImode) /* 32 bit division */
2180 *total = s390_cost->dlr;
2181 return false;
2182
2183 case DIV:
2184 case MOD:
2185 if (GET_MODE (x) == DImode)
2186 {
2187 rtx right = XEXP (x, 1);
2188 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2189 if (TARGET_64BIT)
2190 *total = s390_cost->dsgfr;
2191 else
2192 *total = s390_cost->dr;
2193 else /* 64 by 64 bit division */
2194 *total = s390_cost->dsgr;
2195 }
2196 else if (GET_MODE (x) == SImode) /* 32 bit division */
2197 *total = s390_cost->dlr;
2198 else if (GET_MODE (x) == SFmode)
2199 {
2200 if (TARGET_IEEE_FLOAT)
2201 *total = s390_cost->debr;
2202 else /* TARGET_IBM_FLOAT */
2203 *total = s390_cost->der;
2204 }
2205 else if (GET_MODE (x) == DFmode)
2206 {
2207 if (TARGET_IEEE_FLOAT)
2208 *total = s390_cost->ddbr;
2209 else /* TARGET_IBM_FLOAT */
2210 *total = s390_cost->ddr;
2211 }
2212 return false;
2213
2214 case SQRT:
2215 if (GET_MODE (x) == SFmode)
2216 *total = s390_cost->sqebr;
2217 else /* DFmode */
2218 *total = s390_cost->sqdbr;
2219 return false;
2220
2221 case SIGN_EXTEND:
2222 case ZERO_EXTEND:
2223 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2224 || outer_code == PLUS || outer_code == MINUS
2225 || outer_code == COMPARE)
2226 *total = 0;
2227 return false;
2228
2229 case COMPARE:
2230 *total = COSTS_N_INSNS (1);
2231 if (GET_CODE (XEXP (x, 0)) == AND
2232 && GET_CODE (XEXP (x, 1)) == CONST_INT
2233 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2234 {
2235 rtx op0 = XEXP (XEXP (x, 0), 0);
2236 rtx op1 = XEXP (XEXP (x, 0), 1);
2237 rtx op2 = XEXP (x, 1);
2238
2239 if (memory_operand (op0, GET_MODE (op0))
2240 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2241 return true;
2242 if (register_operand (op0, GET_MODE (op0))
2243 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2244 return true;
2245 }
2246 return false;
2247
2248 default:
2249 return false;
2250 }
2251 }
2252
2253 /* Return the cost of an address rtx ADDR. */
2254
2255 static int
2256 s390_address_cost (rtx addr)
2257 {
2258 struct s390_address ad;
2259 if (!s390_decompose_address (addr, &ad))
2260 return 1000;
2261
2262 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2263 }
2264
2265 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2266 otherwise return 0. */
2267
2268 int
2269 tls_symbolic_operand (rtx op)
2270 {
2271 if (GET_CODE (op) != SYMBOL_REF)
2272 return 0;
2273 return SYMBOL_REF_TLS_MODEL (op);
2274 }
2275 \f
2276 /* Split DImode access register reference REG (on 64-bit) into its constituent
2277 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2278 gen_highpart cannot be used as they assume all registers are word-sized,
2279 while our access registers have only half that size. */
2280
2281 void
2282 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2283 {
2284 gcc_assert (TARGET_64BIT);
2285 gcc_assert (ACCESS_REG_P (reg));
2286 gcc_assert (GET_MODE (reg) == DImode);
2287 gcc_assert (!(REGNO (reg) & 1));
2288
2289 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2290 *hi = gen_rtx_REG (SImode, REGNO (reg));
2291 }
2292
2293 /* Return true if OP contains a symbol reference */
2294
2295 bool
2296 symbolic_reference_mentioned_p (rtx op)
2297 {
2298 const char *fmt;
2299 int i;
2300
2301 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2302 return 1;
2303
2304 fmt = GET_RTX_FORMAT (GET_CODE (op));
2305 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2306 {
2307 if (fmt[i] == 'E')
2308 {
2309 int j;
2310
2311 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2312 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2313 return 1;
2314 }
2315
2316 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2317 return 1;
2318 }
2319
2320 return 0;
2321 }
2322
2323 /* Return true if OP contains a reference to a thread-local symbol. */
2324
2325 bool
2326 tls_symbolic_reference_mentioned_p (rtx op)
2327 {
2328 const char *fmt;
2329 int i;
2330
2331 if (GET_CODE (op) == SYMBOL_REF)
2332 return tls_symbolic_operand (op);
2333
2334 fmt = GET_RTX_FORMAT (GET_CODE (op));
2335 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2336 {
2337 if (fmt[i] == 'E')
2338 {
2339 int j;
2340
2341 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2342 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2343 return true;
2344 }
2345
2346 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2347 return true;
2348 }
2349
2350 return false;
2351 }
2352
2353
2354 /* Return true if OP is a legitimate general operand when
2355 generating PIC code. It is given that flag_pic is on
2356 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2357
2358 int
2359 legitimate_pic_operand_p (rtx op)
2360 {
2361 /* Accept all non-symbolic constants. */
2362 if (!SYMBOLIC_CONST (op))
2363 return 1;
2364
2365 /* Reject everything else; must be handled
2366 via emit_symbolic_move. */
2367 return 0;
2368 }
2369
2370 /* Returns true if the constant value OP is a legitimate general operand.
2371 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2372
2373 int
2374 legitimate_constant_p (rtx op)
2375 {
2376 /* Accept all non-symbolic constants. */
2377 if (!SYMBOLIC_CONST (op))
2378 return 1;
2379
2380 /* Accept immediate LARL operands. */
2381 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2382 return 1;
2383
2384 /* Thread-local symbols are never legal constants. This is
2385 so that emit_call knows that computing such addresses
2386 might require a function call. */
2387 if (TLS_SYMBOLIC_CONST (op))
2388 return 0;
2389
2390 /* In the PIC case, symbolic constants must *not* be
2391 forced into the literal pool. We accept them here,
2392 so that they will be handled by emit_symbolic_move. */
2393 if (flag_pic)
2394 return 1;
2395
2396 /* All remaining non-PIC symbolic constants are
2397 forced into the literal pool. */
2398 return 0;
2399 }
2400
2401 /* Determine if it's legal to put X into the constant pool. This
2402 is not possible if X contains the address of a symbol that is
2403 not constant (TLS) or not known at final link time (PIC). */
2404
2405 static bool
2406 s390_cannot_force_const_mem (rtx x)
2407 {
2408 switch (GET_CODE (x))
2409 {
2410 case CONST_INT:
2411 case CONST_DOUBLE:
2412 /* Accept all non-symbolic constants. */
2413 return false;
2414
2415 case LABEL_REF:
2416 /* Labels are OK iff we are non-PIC. */
2417 return flag_pic != 0;
2418
2419 case SYMBOL_REF:
2420 /* 'Naked' TLS symbol references are never OK,
2421 non-TLS symbols are OK iff we are non-PIC. */
2422 if (tls_symbolic_operand (x))
2423 return true;
2424 else
2425 return flag_pic != 0;
2426
2427 case CONST:
2428 return s390_cannot_force_const_mem (XEXP (x, 0));
2429 case PLUS:
2430 case MINUS:
2431 return s390_cannot_force_const_mem (XEXP (x, 0))
2432 || s390_cannot_force_const_mem (XEXP (x, 1));
2433
2434 case UNSPEC:
2435 switch (XINT (x, 1))
2436 {
2437 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2438 case UNSPEC_LTREL_OFFSET:
2439 case UNSPEC_GOT:
2440 case UNSPEC_GOTOFF:
2441 case UNSPEC_PLTOFF:
2442 case UNSPEC_TLSGD:
2443 case UNSPEC_TLSLDM:
2444 case UNSPEC_NTPOFF:
2445 case UNSPEC_DTPOFF:
2446 case UNSPEC_GOTNTPOFF:
2447 case UNSPEC_INDNTPOFF:
2448 return false;
2449
2450 /* If the literal pool shares the code section, be put
2451 execute template placeholders into the pool as well. */
2452 case UNSPEC_INSN:
2453 return TARGET_CPU_ZARCH;
2454
2455 default:
2456 return true;
2457 }
2458 break;
2459
2460 default:
2461 gcc_unreachable ();
2462 }
2463 }
2464
2465 /* Returns true if the constant value OP is a legitimate general
2466 operand during and after reload. The difference to
2467 legitimate_constant_p is that this function will not accept
2468 a constant that would need to be forced to the literal pool
2469 before it can be used as operand. */
2470
2471 bool
2472 legitimate_reload_constant_p (rtx op)
2473 {
2474 /* Accept la(y) operands. */
2475 if (GET_CODE (op) == CONST_INT
2476 && DISP_IN_RANGE (INTVAL (op)))
2477 return true;
2478
2479 /* Accept l(g)hi/l(g)fi operands. */
2480 if (GET_CODE (op) == CONST_INT
2481 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2482 return true;
2483
2484 /* Accept lliXX operands. */
2485 if (TARGET_ZARCH
2486 && GET_CODE (op) == CONST_INT
2487 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2488 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2489 return true;
2490
2491 if (TARGET_EXTIMM
2492 && GET_CODE (op) == CONST_INT
2493 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2494 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2495 return true;
2496
2497 /* Accept larl operands. */
2498 if (TARGET_CPU_ZARCH
2499 && larl_operand (op, VOIDmode))
2500 return true;
2501
2502 /* Accept lzXX operands. */
2503 if (GET_CODE (op) == CONST_DOUBLE
2504 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2505 return true;
2506
2507 /* Accept double-word operands that can be split. */
2508 if (GET_CODE (op) == CONST_INT
2509 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2510 {
2511 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2512 rtx hi = operand_subword (op, 0, 0, dword_mode);
2513 rtx lo = operand_subword (op, 1, 0, dword_mode);
2514 return legitimate_reload_constant_p (hi)
2515 && legitimate_reload_constant_p (lo);
2516 }
2517
2518 /* Everything else cannot be handled without reload. */
2519 return false;
2520 }
2521
2522 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2523 return the class of reg to actually use. */
2524
2525 enum reg_class
2526 s390_preferred_reload_class (rtx op, enum reg_class class)
2527 {
2528 switch (GET_CODE (op))
2529 {
2530 /* Constants we cannot reload must be forced into the
2531 literal pool. */
2532
2533 case CONST_DOUBLE:
2534 case CONST_INT:
2535 if (legitimate_reload_constant_p (op))
2536 return class;
2537 else
2538 return NO_REGS;
2539
2540 /* If a symbolic constant or a PLUS is reloaded,
2541 it is most likely being used as an address, so
2542 prefer ADDR_REGS. If 'class' is not a superset
2543 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2544 case PLUS:
2545 case LABEL_REF:
2546 case SYMBOL_REF:
2547 case CONST:
2548 if (reg_class_subset_p (ADDR_REGS, class))
2549 return ADDR_REGS;
2550 else
2551 return NO_REGS;
2552
2553 default:
2554 break;
2555 }
2556
2557 return class;
2558 }
2559
2560 /* Return the register class of a scratch register needed to
2561 load IN into a register of class CLASS in MODE.
2562
2563 We need a temporary when loading a PLUS expression which
2564 is not a legitimate operand of the LOAD ADDRESS instruction. */
2565
2566 enum reg_class
2567 s390_secondary_input_reload_class (enum reg_class class,
2568 enum machine_mode mode, rtx in)
2569 {
2570 if (s390_plus_operand (in, mode))
2571 return ADDR_REGS;
2572
2573 if (reg_classes_intersect_p (CC_REGS, class))
2574 return GENERAL_REGS;
2575
2576 return NO_REGS;
2577 }
2578
2579 /* Return the register class of a scratch register needed to
2580 store a register of class CLASS in MODE into OUT:
2581
2582 We need a temporary when storing a double-word to a
2583 non-offsettable memory address. */
2584
2585 enum reg_class
2586 s390_secondary_output_reload_class (enum reg_class class,
2587 enum machine_mode mode, rtx out)
2588 {
2589 if ((TARGET_64BIT ? mode == TImode
2590 : (mode == DImode || mode == DFmode))
2591 && reg_classes_intersect_p (GENERAL_REGS, class)
2592 && GET_CODE (out) == MEM
2593 && GET_CODE (XEXP (out, 0)) == PLUS
2594 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2595 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2596 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2597 + GET_MODE_SIZE (mode) - 1))
2598 return ADDR_REGS;
2599
2600 if (reg_classes_intersect_p (CC_REGS, class))
2601 return GENERAL_REGS;
2602
2603 return NO_REGS;
2604 }
2605
2606 /* Generate code to load SRC, which is PLUS that is not a
2607 legitimate operand for the LA instruction, into TARGET.
2608 SCRATCH may be used as scratch register. */
2609
2610 void
2611 s390_expand_plus_operand (rtx target, rtx src,
2612 rtx scratch)
2613 {
2614 rtx sum1, sum2;
2615 struct s390_address ad;
2616
2617 /* src must be a PLUS; get its two operands. */
2618 gcc_assert (GET_CODE (src) == PLUS);
2619 gcc_assert (GET_MODE (src) == Pmode);
2620
2621 /* Check if any of the two operands is already scheduled
2622 for replacement by reload. This can happen e.g. when
2623 float registers occur in an address. */
2624 sum1 = find_replacement (&XEXP (src, 0));
2625 sum2 = find_replacement (&XEXP (src, 1));
2626 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2627
2628 /* If the address is already strictly valid, there's nothing to do. */
2629 if (!s390_decompose_address (src, &ad)
2630 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2631 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
2632 {
2633 /* Otherwise, one of the operands cannot be an address register;
2634 we reload its value into the scratch register. */
2635 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2636 {
2637 emit_move_insn (scratch, sum1);
2638 sum1 = scratch;
2639 }
2640 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2641 {
2642 emit_move_insn (scratch, sum2);
2643 sum2 = scratch;
2644 }
2645
2646 /* According to the way these invalid addresses are generated
2647 in reload.c, it should never happen (at least on s390) that
2648 *neither* of the PLUS components, after find_replacements
2649 was applied, is an address register. */
2650 if (sum1 == scratch && sum2 == scratch)
2651 {
2652 debug_rtx (src);
2653 gcc_unreachable ();
2654 }
2655
2656 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2657 }
2658
2659 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2660 is only ever performed on addresses, so we can mark the
2661 sum as legitimate for LA in any case. */
2662 s390_load_address (target, src);
2663 }
2664
2665
2666 /* Return true if ADDR is a valid memory address.
2667 STRICT specifies whether strict register checking applies. */
2668
2669 bool
2670 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2671 rtx addr, int strict)
2672 {
2673 struct s390_address ad;
2674 if (!s390_decompose_address (addr, &ad))
2675 return false;
2676
2677 if (strict)
2678 {
2679 if (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2680 return false;
2681 if (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))
2682 return false;
2683 }
2684 else
2685 {
2686 if (ad.base && !REG_OK_FOR_BASE_NONSTRICT_P (ad.base))
2687 return false;
2688 if (ad.indx && !REG_OK_FOR_INDEX_NONSTRICT_P (ad.indx))
2689 return false;
2690 }
2691
2692 return true;
2693 }
2694
2695 /* Return true if OP is a valid operand for the LA instruction.
2696 In 31-bit, we need to prove that the result is used as an
2697 address, as LA performs only a 31-bit addition. */
2698
2699 bool
2700 legitimate_la_operand_p (rtx op)
2701 {
2702 struct s390_address addr;
2703 if (!s390_decompose_address (op, &addr))
2704 return false;
2705
2706 return (TARGET_64BIT || addr.pointer);
2707 }
2708
2709 /* Return true if it is valid *and* preferable to use LA to
2710 compute the sum of OP1 and OP2. */
2711
2712 bool
2713 preferred_la_operand_p (rtx op1, rtx op2)
2714 {
2715 struct s390_address addr;
2716
2717 if (op2 != const0_rtx)
2718 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2719
2720 if (!s390_decompose_address (op1, &addr))
2721 return false;
2722 if (addr.base && !REG_OK_FOR_BASE_STRICT_P (addr.base))
2723 return false;
2724 if (addr.indx && !REG_OK_FOR_INDEX_STRICT_P (addr.indx))
2725 return false;
2726
2727 if (!TARGET_64BIT && !addr.pointer)
2728 return false;
2729
2730 if (addr.pointer)
2731 return true;
2732
2733 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2734 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2735 return true;
2736
2737 return false;
2738 }
2739
2740 /* Emit a forced load-address operation to load SRC into DST.
2741 This will use the LOAD ADDRESS instruction even in situations
2742 where legitimate_la_operand_p (SRC) returns false. */
2743
2744 void
2745 s390_load_address (rtx dst, rtx src)
2746 {
2747 if (TARGET_64BIT)
2748 emit_move_insn (dst, src);
2749 else
2750 emit_insn (gen_force_la_31 (dst, src));
2751 }
2752
2753 /* Return a legitimate reference for ORIG (an address) using the
2754 register REG. If REG is 0, a new pseudo is generated.
2755
2756 There are two types of references that must be handled:
2757
2758 1. Global data references must load the address from the GOT, via
2759 the PIC reg. An insn is emitted to do this load, and the reg is
2760 returned.
2761
2762 2. Static data references, constant pool addresses, and code labels
2763 compute the address as an offset from the GOT, whose base is in
2764 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2765 differentiate them from global data objects. The returned
2766 address is the PIC reg + an unspec constant.
2767
2768 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2769 reg also appears in the address. */
2770
2771 rtx
2772 legitimize_pic_address (rtx orig, rtx reg)
2773 {
2774 rtx addr = orig;
2775 rtx new = orig;
2776 rtx base;
2777
2778 if (GET_CODE (addr) == LABEL_REF
2779 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2780 {
2781 /* This is a local symbol. */
2782 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2783 {
2784 /* Access local symbols PC-relative via LARL.
2785 This is the same as in the non-PIC case, so it is
2786 handled automatically ... */
2787 }
2788 else
2789 {
2790 /* Access local symbols relative to the GOT. */
2791
2792 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2793
2794 if (reload_in_progress || reload_completed)
2795 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2796
2797 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2798 addr = gen_rtx_CONST (Pmode, addr);
2799 addr = force_const_mem (Pmode, addr);
2800 emit_move_insn (temp, addr);
2801
2802 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2803 if (reg != 0)
2804 {
2805 s390_load_address (reg, new);
2806 new = reg;
2807 }
2808 }
2809 }
2810 else if (GET_CODE (addr) == SYMBOL_REF)
2811 {
2812 if (reg == 0)
2813 reg = gen_reg_rtx (Pmode);
2814
2815 if (flag_pic == 1)
2816 {
2817 /* Assume GOT offset < 4k. This is handled the same way
2818 in both 31- and 64-bit code (@GOT). */
2819
2820 if (reload_in_progress || reload_completed)
2821 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2822
2823 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2824 new = gen_rtx_CONST (Pmode, new);
2825 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2826 new = gen_const_mem (Pmode, new);
2827 emit_move_insn (reg, new);
2828 new = reg;
2829 }
2830 else if (TARGET_CPU_ZARCH)
2831 {
2832 /* If the GOT offset might be >= 4k, we determine the position
2833 of the GOT entry via a PC-relative LARL (@GOTENT). */
2834
2835 rtx temp = gen_reg_rtx (Pmode);
2836
2837 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2838 new = gen_rtx_CONST (Pmode, new);
2839 emit_move_insn (temp, new);
2840
2841 new = gen_const_mem (Pmode, temp);
2842 emit_move_insn (reg, new);
2843 new = reg;
2844 }
2845 else
2846 {
2847 /* If the GOT offset might be >= 4k, we have to load it
2848 from the literal pool (@GOT). */
2849
2850 rtx temp = gen_reg_rtx (Pmode);
2851
2852 if (reload_in_progress || reload_completed)
2853 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2854
2855 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2856 addr = gen_rtx_CONST (Pmode, addr);
2857 addr = force_const_mem (Pmode, addr);
2858 emit_move_insn (temp, addr);
2859
2860 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2861 new = gen_const_mem (Pmode, new);
2862 emit_move_insn (reg, new);
2863 new = reg;
2864 }
2865 }
2866 else
2867 {
2868 if (GET_CODE (addr) == CONST)
2869 {
2870 addr = XEXP (addr, 0);
2871 if (GET_CODE (addr) == UNSPEC)
2872 {
2873 gcc_assert (XVECLEN (addr, 0) == 1);
2874 switch (XINT (addr, 1))
2875 {
2876 /* If someone moved a GOT-relative UNSPEC
2877 out of the literal pool, force them back in. */
2878 case UNSPEC_GOTOFF:
2879 case UNSPEC_PLTOFF:
2880 new = force_const_mem (Pmode, orig);
2881 break;
2882
2883 /* @GOT is OK as is if small. */
2884 case UNSPEC_GOT:
2885 if (flag_pic == 2)
2886 new = force_const_mem (Pmode, orig);
2887 break;
2888
2889 /* @GOTENT is OK as is. */
2890 case UNSPEC_GOTENT:
2891 break;
2892
2893 /* @PLT is OK as is on 64-bit, must be converted to
2894 GOT-relative @PLTOFF on 31-bit. */
2895 case UNSPEC_PLT:
2896 if (!TARGET_CPU_ZARCH)
2897 {
2898 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2899
2900 if (reload_in_progress || reload_completed)
2901 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2902
2903 addr = XVECEXP (addr, 0, 0);
2904 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2905 UNSPEC_PLTOFF);
2906 addr = gen_rtx_CONST (Pmode, addr);
2907 addr = force_const_mem (Pmode, addr);
2908 emit_move_insn (temp, addr);
2909
2910 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2911 if (reg != 0)
2912 {
2913 s390_load_address (reg, new);
2914 new = reg;
2915 }
2916 }
2917 break;
2918
2919 /* Everything else cannot happen. */
2920 default:
2921 gcc_unreachable ();
2922 }
2923 }
2924 else
2925 gcc_assert (GET_CODE (addr) == PLUS);
2926 }
2927 if (GET_CODE (addr) == PLUS)
2928 {
2929 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2930 /* Check first to see if this is a constant offset
2931 from a local symbol reference. */
2932 if ((GET_CODE (op0) == LABEL_REF
2933 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
2934 && GET_CODE (op1) == CONST_INT)
2935 {
2936 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
2937 {
2938 if (INTVAL (op1) & 1)
2939 {
2940 /* LARL can't handle odd offsets, so emit a
2941 pair of LARL and LA. */
2942 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2943
2944 if (!DISP_IN_RANGE (INTVAL (op1)))
2945 {
2946 int even = INTVAL (op1) - 1;
2947 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
2948 op0 = gen_rtx_CONST (Pmode, op0);
2949 op1 = const1_rtx;
2950 }
2951
2952 emit_move_insn (temp, op0);
2953 new = gen_rtx_PLUS (Pmode, temp, op1);
2954
2955 if (reg != 0)
2956 {
2957 s390_load_address (reg, new);
2958 new = reg;
2959 }
2960 }
2961 else
2962 {
2963 /* If the offset is even, we can just use LARL.
2964 This will happen automatically. */
2965 }
2966 }
2967 else
2968 {
2969 /* Access local symbols relative to the GOT. */
2970
2971 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2972
2973 if (reload_in_progress || reload_completed)
2974 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2975
2976 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
2977 UNSPEC_GOTOFF);
2978 addr = gen_rtx_PLUS (Pmode, addr, op1);
2979 addr = gen_rtx_CONST (Pmode, addr);
2980 addr = force_const_mem (Pmode, addr);
2981 emit_move_insn (temp, addr);
2982
2983 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2984 if (reg != 0)
2985 {
2986 s390_load_address (reg, new);
2987 new = reg;
2988 }
2989 }
2990 }
2991
2992 /* Now, check whether it is a GOT relative symbol plus offset
2993 that was pulled out of the literal pool. Force it back in. */
2994
2995 else if (GET_CODE (op0) == UNSPEC
2996 && GET_CODE (op1) == CONST_INT
2997 && XINT (op0, 1) == UNSPEC_GOTOFF)
2998 {
2999 gcc_assert (XVECLEN (op0, 0) == 1);
3000
3001 new = force_const_mem (Pmode, orig);
3002 }
3003
3004 /* Otherwise, compute the sum. */
3005 else
3006 {
3007 base = legitimize_pic_address (XEXP (addr, 0), reg);
3008 new = legitimize_pic_address (XEXP (addr, 1),
3009 base == reg ? NULL_RTX : reg);
3010 if (GET_CODE (new) == CONST_INT)
3011 new = plus_constant (base, INTVAL (new));
3012 else
3013 {
3014 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3015 {
3016 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3017 new = XEXP (new, 1);
3018 }
3019 new = gen_rtx_PLUS (Pmode, base, new);
3020 }
3021
3022 if (GET_CODE (new) == CONST)
3023 new = XEXP (new, 0);
3024 new = force_operand (new, 0);
3025 }
3026 }
3027 }
3028 return new;
3029 }
3030
3031 /* Load the thread pointer into a register. */
3032
3033 rtx
3034 s390_get_thread_pointer (void)
3035 {
3036 rtx tp = gen_reg_rtx (Pmode);
3037
3038 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3039 mark_reg_pointer (tp, BITS_PER_WORD);
3040
3041 return tp;
3042 }
3043
3044 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3045 in s390_tls_symbol which always refers to __tls_get_offset.
3046 The returned offset is written to RESULT_REG and an USE rtx is
3047 generated for TLS_CALL. */
3048
3049 static GTY(()) rtx s390_tls_symbol;
3050
3051 static void
3052 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3053 {
3054 rtx insn;
3055
3056 gcc_assert (flag_pic);
3057
3058 if (!s390_tls_symbol)
3059 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3060
3061 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3062 gen_rtx_REG (Pmode, RETURN_REGNUM));
3063
3064 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3065 CONST_OR_PURE_CALL_P (insn) = 1;
3066 }
3067
3068 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3069 this (thread-local) address. REG may be used as temporary. */
3070
3071 static rtx
3072 legitimize_tls_address (rtx addr, rtx reg)
3073 {
3074 rtx new, tls_call, temp, base, r2, insn;
3075
3076 if (GET_CODE (addr) == SYMBOL_REF)
3077 switch (tls_symbolic_operand (addr))
3078 {
3079 case TLS_MODEL_GLOBAL_DYNAMIC:
3080 start_sequence ();
3081 r2 = gen_rtx_REG (Pmode, 2);
3082 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3083 new = gen_rtx_CONST (Pmode, tls_call);
3084 new = force_const_mem (Pmode, new);
3085 emit_move_insn (r2, new);
3086 s390_emit_tls_call_insn (r2, tls_call);
3087 insn = get_insns ();
3088 end_sequence ();
3089
3090 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3091 temp = gen_reg_rtx (Pmode);
3092 emit_libcall_block (insn, temp, r2, new);
3093
3094 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3095 if (reg != 0)
3096 {
3097 s390_load_address (reg, new);
3098 new = reg;
3099 }
3100 break;
3101
3102 case TLS_MODEL_LOCAL_DYNAMIC:
3103 start_sequence ();
3104 r2 = gen_rtx_REG (Pmode, 2);
3105 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3106 new = gen_rtx_CONST (Pmode, tls_call);
3107 new = force_const_mem (Pmode, new);
3108 emit_move_insn (r2, new);
3109 s390_emit_tls_call_insn (r2, tls_call);
3110 insn = get_insns ();
3111 end_sequence ();
3112
3113 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3114 temp = gen_reg_rtx (Pmode);
3115 emit_libcall_block (insn, temp, r2, new);
3116
3117 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3118 base = gen_reg_rtx (Pmode);
3119 s390_load_address (base, new);
3120
3121 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3122 new = gen_rtx_CONST (Pmode, new);
3123 new = force_const_mem (Pmode, new);
3124 temp = gen_reg_rtx (Pmode);
3125 emit_move_insn (temp, new);
3126
3127 new = gen_rtx_PLUS (Pmode, base, temp);
3128 if (reg != 0)
3129 {
3130 s390_load_address (reg, new);
3131 new = reg;
3132 }
3133 break;
3134
3135 case TLS_MODEL_INITIAL_EXEC:
3136 if (flag_pic == 1)
3137 {
3138 /* Assume GOT offset < 4k. This is handled the same way
3139 in both 31- and 64-bit code. */
3140
3141 if (reload_in_progress || reload_completed)
3142 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3143
3144 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3145 new = gen_rtx_CONST (Pmode, new);
3146 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3147 new = gen_const_mem (Pmode, new);
3148 temp = gen_reg_rtx (Pmode);
3149 emit_move_insn (temp, new);
3150 }
3151 else if (TARGET_CPU_ZARCH)
3152 {
3153 /* If the GOT offset might be >= 4k, we determine the position
3154 of the GOT entry via a PC-relative LARL. */
3155
3156 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3157 new = gen_rtx_CONST (Pmode, new);
3158 temp = gen_reg_rtx (Pmode);
3159 emit_move_insn (temp, new);
3160
3161 new = gen_const_mem (Pmode, temp);
3162 temp = gen_reg_rtx (Pmode);
3163 emit_move_insn (temp, new);
3164 }
3165 else if (flag_pic)
3166 {
3167 /* If the GOT offset might be >= 4k, we have to load it
3168 from the literal pool. */
3169
3170 if (reload_in_progress || reload_completed)
3171 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3172
3173 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3174 new = gen_rtx_CONST (Pmode, new);
3175 new = force_const_mem (Pmode, new);
3176 temp = gen_reg_rtx (Pmode);
3177 emit_move_insn (temp, new);
3178
3179 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3180 new = gen_const_mem (Pmode, new);
3181
3182 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3183 temp = gen_reg_rtx (Pmode);
3184 emit_insn (gen_rtx_SET (Pmode, temp, new));
3185 }
3186 else
3187 {
3188 /* In position-dependent code, load the absolute address of
3189 the GOT entry from the literal pool. */
3190
3191 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3192 new = gen_rtx_CONST (Pmode, new);
3193 new = force_const_mem (Pmode, new);
3194 temp = gen_reg_rtx (Pmode);
3195 emit_move_insn (temp, new);
3196
3197 new = temp;
3198 new = gen_const_mem (Pmode, new);
3199 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3200 temp = gen_reg_rtx (Pmode);
3201 emit_insn (gen_rtx_SET (Pmode, temp, new));
3202 }
3203
3204 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3205 if (reg != 0)
3206 {
3207 s390_load_address (reg, new);
3208 new = reg;
3209 }
3210 break;
3211
3212 case TLS_MODEL_LOCAL_EXEC:
3213 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3214 new = gen_rtx_CONST (Pmode, new);
3215 new = force_const_mem (Pmode, new);
3216 temp = gen_reg_rtx (Pmode);
3217 emit_move_insn (temp, new);
3218
3219 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3220 if (reg != 0)
3221 {
3222 s390_load_address (reg, new);
3223 new = reg;
3224 }
3225 break;
3226
3227 default:
3228 gcc_unreachable ();
3229 }
3230
3231 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3232 {
3233 switch (XINT (XEXP (addr, 0), 1))
3234 {
3235 case UNSPEC_INDNTPOFF:
3236 gcc_assert (TARGET_CPU_ZARCH);
3237 new = addr;
3238 break;
3239
3240 default:
3241 gcc_unreachable ();
3242 }
3243 }
3244
3245 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3246 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3247 {
3248 new = XEXP (XEXP (addr, 0), 0);
3249 if (GET_CODE (new) != SYMBOL_REF)
3250 new = gen_rtx_CONST (Pmode, new);
3251
3252 new = legitimize_tls_address (new, reg);
3253 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3254 new = force_operand (new, 0);
3255 }
3256
3257 else
3258 gcc_unreachable (); /* for now ... */
3259
3260 return new;
3261 }
3262
3263 /* Emit insns to move operands[1] into operands[0]. */
3264
3265 void
3266 emit_symbolic_move (rtx *operands)
3267 {
3268 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3269
3270 if (GET_CODE (operands[0]) == MEM)
3271 operands[1] = force_reg (Pmode, operands[1]);
3272 else if (TLS_SYMBOLIC_CONST (operands[1]))
3273 operands[1] = legitimize_tls_address (operands[1], temp);
3274 else if (flag_pic)
3275 operands[1] = legitimize_pic_address (operands[1], temp);
3276 }
3277
3278 /* Try machine-dependent ways of modifying an illegitimate address X
3279 to be legitimate. If we find one, return the new, valid address.
3280
3281 OLDX is the address as it was before break_out_memory_refs was called.
3282 In some cases it is useful to look at this to decide what needs to be done.
3283
3284 MODE is the mode of the operand pointed to by X.
3285
3286 When -fpic is used, special handling is needed for symbolic references.
3287 See comments by legitimize_pic_address for details. */
3288
3289 rtx
3290 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3291 enum machine_mode mode ATTRIBUTE_UNUSED)
3292 {
3293 rtx constant_term = const0_rtx;
3294
3295 if (TLS_SYMBOLIC_CONST (x))
3296 {
3297 x = legitimize_tls_address (x, 0);
3298
3299 if (legitimate_address_p (mode, x, FALSE))
3300 return x;
3301 }
3302 else if (flag_pic)
3303 {
3304 if (SYMBOLIC_CONST (x)
3305 || (GET_CODE (x) == PLUS
3306 && (SYMBOLIC_CONST (XEXP (x, 0))
3307 || SYMBOLIC_CONST (XEXP (x, 1)))))
3308 x = legitimize_pic_address (x, 0);
3309
3310 if (legitimate_address_p (mode, x, FALSE))
3311 return x;
3312 }
3313
3314 x = eliminate_constant_term (x, &constant_term);
3315
3316 /* Optimize loading of large displacements by splitting them
3317 into the multiple of 4K and the rest; this allows the
3318 former to be CSE'd if possible.
3319
3320 Don't do this if the displacement is added to a register
3321 pointing into the stack frame, as the offsets will
3322 change later anyway. */
3323
3324 if (GET_CODE (constant_term) == CONST_INT
3325 && !TARGET_LONG_DISPLACEMENT
3326 && !DISP_IN_RANGE (INTVAL (constant_term))
3327 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3328 {
3329 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3330 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3331
3332 rtx temp = gen_reg_rtx (Pmode);
3333 rtx val = force_operand (GEN_INT (upper), temp);
3334 if (val != temp)
3335 emit_move_insn (temp, val);
3336
3337 x = gen_rtx_PLUS (Pmode, x, temp);
3338 constant_term = GEN_INT (lower);
3339 }
3340
3341 if (GET_CODE (x) == PLUS)
3342 {
3343 if (GET_CODE (XEXP (x, 0)) == REG)
3344 {
3345 rtx temp = gen_reg_rtx (Pmode);
3346 rtx val = force_operand (XEXP (x, 1), temp);
3347 if (val != temp)
3348 emit_move_insn (temp, val);
3349
3350 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3351 }
3352
3353 else if (GET_CODE (XEXP (x, 1)) == REG)
3354 {
3355 rtx temp = gen_reg_rtx (Pmode);
3356 rtx val = force_operand (XEXP (x, 0), temp);
3357 if (val != temp)
3358 emit_move_insn (temp, val);
3359
3360 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3361 }
3362 }
3363
3364 if (constant_term != const0_rtx)
3365 x = gen_rtx_PLUS (Pmode, x, constant_term);
3366
3367 return x;
3368 }
3369
3370 /* Try a machine-dependent way of reloading an illegitimate address AD
3371 operand. If we find one, push the reload and and return the new address.
3372
3373 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3374 and TYPE is the reload type of the current reload. */
3375
3376 rtx
3377 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3378 int opnum, int type)
3379 {
3380 if (!optimize || TARGET_LONG_DISPLACEMENT)
3381 return NULL_RTX;
3382
3383 if (GET_CODE (ad) == PLUS)
3384 {
3385 rtx tem = simplify_binary_operation (PLUS, Pmode,
3386 XEXP (ad, 0), XEXP (ad, 1));
3387 if (tem)
3388 ad = tem;
3389 }
3390
3391 if (GET_CODE (ad) == PLUS
3392 && GET_CODE (XEXP (ad, 0)) == REG
3393 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3394 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3395 {
3396 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3397 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3398 rtx cst, tem, new;
3399
3400 cst = GEN_INT (upper);
3401 if (!legitimate_reload_constant_p (cst))
3402 cst = force_const_mem (Pmode, cst);
3403
3404 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3405 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3406
3407 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3408 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3409 opnum, (enum reload_type) type);
3410 return new;
3411 }
3412
3413 return NULL_RTX;
3414 }
3415
3416 /* Emit code to move LEN bytes from DST to SRC. */
3417
3418 void
3419 s390_expand_movmem (rtx dst, rtx src, rtx len)
3420 {
3421 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3422 {
3423 if (INTVAL (len) > 0)
3424 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3425 }
3426
3427 else if (TARGET_MVCLE)
3428 {
3429 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3430 }
3431
3432 else
3433 {
3434 rtx dst_addr, src_addr, count, blocks, temp;
3435 rtx loop_start_label = gen_label_rtx ();
3436 rtx loop_end_label = gen_label_rtx ();
3437 rtx end_label = gen_label_rtx ();
3438 enum machine_mode mode;
3439
3440 mode = GET_MODE (len);
3441 if (mode == VOIDmode)
3442 mode = Pmode;
3443
3444 dst_addr = gen_reg_rtx (Pmode);
3445 src_addr = gen_reg_rtx (Pmode);
3446 count = gen_reg_rtx (mode);
3447 blocks = gen_reg_rtx (mode);
3448
3449 convert_move (count, len, 1);
3450 emit_cmp_and_jump_insns (count, const0_rtx,
3451 EQ, NULL_RTX, mode, 1, end_label);
3452
3453 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3454 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3455 dst = change_address (dst, VOIDmode, dst_addr);
3456 src = change_address (src, VOIDmode, src_addr);
3457
3458 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3459 if (temp != count)
3460 emit_move_insn (count, temp);
3461
3462 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3463 if (temp != blocks)
3464 emit_move_insn (blocks, temp);
3465
3466 emit_cmp_and_jump_insns (blocks, const0_rtx,
3467 EQ, NULL_RTX, mode, 1, loop_end_label);
3468
3469 emit_label (loop_start_label);
3470
3471 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3472 s390_load_address (dst_addr,
3473 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3474 s390_load_address (src_addr,
3475 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3476
3477 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3478 if (temp != blocks)
3479 emit_move_insn (blocks, temp);
3480
3481 emit_cmp_and_jump_insns (blocks, const0_rtx,
3482 EQ, NULL_RTX, mode, 1, loop_end_label);
3483
3484 emit_jump (loop_start_label);
3485 emit_label (loop_end_label);
3486
3487 emit_insn (gen_movmem_short (dst, src,
3488 convert_to_mode (Pmode, count, 1)));
3489 emit_label (end_label);
3490 }
3491 }
3492
3493 /* Emit code to set LEN bytes at DST to VAL.
3494 Make use of clrmem if VAL is zero. */
3495
3496 void
3497 s390_expand_setmem (rtx dst, rtx len, rtx val)
3498 {
3499 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3500 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3501
3502 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3503 {
3504 if (val == const0_rtx && INTVAL (len) <= 256)
3505 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3506 else
3507 {
3508 /* Initialize memory by storing the first byte. */
3509 emit_move_insn (adjust_address (dst, QImode, 0), val);
3510
3511 if (INTVAL (len) > 1)
3512 {
3513 /* Initiate 1 byte overlap move.
3514 The first byte of DST is propagated through DSTP1.
3515 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3516 DST is set to size 1 so the rest of the memory location
3517 does not count as source operand. */
3518 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3519 set_mem_size (dst, const1_rtx);
3520
3521 emit_insn (gen_movmem_short (dstp1, dst,
3522 GEN_INT (INTVAL (len) - 2)));
3523 }
3524 }
3525 }
3526
3527 else if (TARGET_MVCLE)
3528 {
3529 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3530 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3531 }
3532
3533 else
3534 {
3535 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3536 rtx loop_start_label = gen_label_rtx ();
3537 rtx loop_end_label = gen_label_rtx ();
3538 rtx end_label = gen_label_rtx ();
3539 enum machine_mode mode;
3540
3541 mode = GET_MODE (len);
3542 if (mode == VOIDmode)
3543 mode = Pmode;
3544
3545 dst_addr = gen_reg_rtx (Pmode);
3546 src_addr = gen_reg_rtx (Pmode);
3547 count = gen_reg_rtx (mode);
3548 blocks = gen_reg_rtx (mode);
3549
3550 convert_move (count, len, 1);
3551 emit_cmp_and_jump_insns (count, const0_rtx,
3552 EQ, NULL_RTX, mode, 1, end_label);
3553
3554 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3555 dst = change_address (dst, VOIDmode, dst_addr);
3556
3557 if (val == const0_rtx)
3558 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3559 else
3560 {
3561 dstp1 = adjust_address (dst, VOIDmode, 1);
3562 set_mem_size (dst, const1_rtx);
3563
3564 /* Initialize memory by storing the first byte. */
3565 emit_move_insn (adjust_address (dst, QImode, 0), val);
3566
3567 /* If count is 1 we are done. */
3568 emit_cmp_and_jump_insns (count, const1_rtx,
3569 EQ, NULL_RTX, mode, 1, end_label);
3570
3571 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3572 }
3573 if (temp != count)
3574 emit_move_insn (count, temp);
3575
3576 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3577 if (temp != blocks)
3578 emit_move_insn (blocks, temp);
3579
3580 emit_cmp_and_jump_insns (blocks, const0_rtx,
3581 EQ, NULL_RTX, mode, 1, loop_end_label);
3582
3583 emit_label (loop_start_label);
3584
3585 if (val == const0_rtx)
3586 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3587 else
3588 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3589 s390_load_address (dst_addr,
3590 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3591
3592 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3593 if (temp != blocks)
3594 emit_move_insn (blocks, temp);
3595
3596 emit_cmp_and_jump_insns (blocks, const0_rtx,
3597 EQ, NULL_RTX, mode, 1, loop_end_label);
3598
3599 emit_jump (loop_start_label);
3600 emit_label (loop_end_label);
3601
3602 if (val == const0_rtx)
3603 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3604 else
3605 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3606 emit_label (end_label);
3607 }
3608 }
3609
3610 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3611 and return the result in TARGET. */
3612
3613 void
3614 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3615 {
3616 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3617 rtx tmp;
3618
3619 /* As the result of CMPINT is inverted compared to what we need,
3620 we have to swap the operands. */
3621 tmp = op0; op0 = op1; op1 = tmp;
3622
3623 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3624 {
3625 if (INTVAL (len) > 0)
3626 {
3627 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3628 emit_insn (gen_cmpint (target, ccreg));
3629 }
3630 else
3631 emit_move_insn (target, const0_rtx);
3632 }
3633 else if (TARGET_MVCLE)
3634 {
3635 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3636 emit_insn (gen_cmpint (target, ccreg));
3637 }
3638 else
3639 {
3640 rtx addr0, addr1, count, blocks, temp;
3641 rtx loop_start_label = gen_label_rtx ();
3642 rtx loop_end_label = gen_label_rtx ();
3643 rtx end_label = gen_label_rtx ();
3644 enum machine_mode mode;
3645
3646 mode = GET_MODE (len);
3647 if (mode == VOIDmode)
3648 mode = Pmode;
3649
3650 addr0 = gen_reg_rtx (Pmode);
3651 addr1 = gen_reg_rtx (Pmode);
3652 count = gen_reg_rtx (mode);
3653 blocks = gen_reg_rtx (mode);
3654
3655 convert_move (count, len, 1);
3656 emit_cmp_and_jump_insns (count, const0_rtx,
3657 EQ, NULL_RTX, mode, 1, end_label);
3658
3659 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3660 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3661 op0 = change_address (op0, VOIDmode, addr0);
3662 op1 = change_address (op1, VOIDmode, addr1);
3663
3664 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3665 if (temp != count)
3666 emit_move_insn (count, temp);
3667
3668 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3669 if (temp != blocks)
3670 emit_move_insn (blocks, temp);
3671
3672 emit_cmp_and_jump_insns (blocks, const0_rtx,
3673 EQ, NULL_RTX, mode, 1, loop_end_label);
3674
3675 emit_label (loop_start_label);
3676
3677 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3678 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3679 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3680 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3681 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3682 emit_jump_insn (temp);
3683
3684 s390_load_address (addr0,
3685 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3686 s390_load_address (addr1,
3687 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3688
3689 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3690 if (temp != blocks)
3691 emit_move_insn (blocks, temp);
3692
3693 emit_cmp_and_jump_insns (blocks, const0_rtx,
3694 EQ, NULL_RTX, mode, 1, loop_end_label);
3695
3696 emit_jump (loop_start_label);
3697 emit_label (loop_end_label);
3698
3699 emit_insn (gen_cmpmem_short (op0, op1,
3700 convert_to_mode (Pmode, count, 1)));
3701 emit_label (end_label);
3702
3703 emit_insn (gen_cmpint (target, ccreg));
3704 }
3705 }
3706
3707
3708 /* Expand conditional increment or decrement using alc/slb instructions.
3709 Should generate code setting DST to either SRC or SRC + INCREMENT,
3710 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3711 Returns true if successful, false otherwise.
3712
3713 That makes it possible to implement some if-constructs without jumps e.g.:
3714 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3715 unsigned int a, b, c;
3716 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3717 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3718 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3719 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3720
3721 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3722 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3723 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3724 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3725 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3726
3727 bool
3728 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3729 rtx dst, rtx src, rtx increment)
3730 {
3731 enum machine_mode cmp_mode;
3732 enum machine_mode cc_mode;
3733 rtx op_res;
3734 rtx insn;
3735 rtvec p;
3736 int ret;
3737
3738 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3739 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3740 cmp_mode = SImode;
3741 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3742 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3743 cmp_mode = DImode;
3744 else
3745 return false;
3746
3747 /* Try ADD LOGICAL WITH CARRY. */
3748 if (increment == const1_rtx)
3749 {
3750 /* Determine CC mode to use. */
3751 if (cmp_code == EQ || cmp_code == NE)
3752 {
3753 if (cmp_op1 != const0_rtx)
3754 {
3755 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3756 NULL_RTX, 0, OPTAB_WIDEN);
3757 cmp_op1 = const0_rtx;
3758 }
3759
3760 cmp_code = cmp_code == EQ ? LEU : GTU;
3761 }
3762
3763 if (cmp_code == LTU || cmp_code == LEU)
3764 {
3765 rtx tem = cmp_op0;
3766 cmp_op0 = cmp_op1;
3767 cmp_op1 = tem;
3768 cmp_code = swap_condition (cmp_code);
3769 }
3770
3771 switch (cmp_code)
3772 {
3773 case GTU:
3774 cc_mode = CCUmode;
3775 break;
3776
3777 case GEU:
3778 cc_mode = CCL3mode;
3779 break;
3780
3781 default:
3782 return false;
3783 }
3784
3785 /* Emit comparison instruction pattern. */
3786 if (!register_operand (cmp_op0, cmp_mode))
3787 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3788
3789 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3790 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3791 /* We use insn_invalid_p here to add clobbers if required. */
3792 ret = insn_invalid_p (emit_insn (insn));
3793 gcc_assert (!ret);
3794
3795 /* Emit ALC instruction pattern. */
3796 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3797 gen_rtx_REG (cc_mode, CC_REGNUM),
3798 const0_rtx);
3799
3800 if (src != const0_rtx)
3801 {
3802 if (!register_operand (src, GET_MODE (dst)))
3803 src = force_reg (GET_MODE (dst), src);
3804
3805 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3806 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3807 }
3808
3809 p = rtvec_alloc (2);
3810 RTVEC_ELT (p, 0) =
3811 gen_rtx_SET (VOIDmode, dst, op_res);
3812 RTVEC_ELT (p, 1) =
3813 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3814 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3815
3816 return true;
3817 }
3818
3819 /* Try SUBTRACT LOGICAL WITH BORROW. */
3820 if (increment == constm1_rtx)
3821 {
3822 /* Determine CC mode to use. */
3823 if (cmp_code == EQ || cmp_code == NE)
3824 {
3825 if (cmp_op1 != const0_rtx)
3826 {
3827 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3828 NULL_RTX, 0, OPTAB_WIDEN);
3829 cmp_op1 = const0_rtx;
3830 }
3831
3832 cmp_code = cmp_code == EQ ? LEU : GTU;
3833 }
3834
3835 if (cmp_code == GTU || cmp_code == GEU)
3836 {
3837 rtx tem = cmp_op0;
3838 cmp_op0 = cmp_op1;
3839 cmp_op1 = tem;
3840 cmp_code = swap_condition (cmp_code);
3841 }
3842
3843 switch (cmp_code)
3844 {
3845 case LEU:
3846 cc_mode = CCUmode;
3847 break;
3848
3849 case LTU:
3850 cc_mode = CCL3mode;
3851 break;
3852
3853 default:
3854 return false;
3855 }
3856
3857 /* Emit comparison instruction pattern. */
3858 if (!register_operand (cmp_op0, cmp_mode))
3859 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3860
3861 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3862 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3863 /* We use insn_invalid_p here to add clobbers if required. */
3864 ret = insn_invalid_p (emit_insn (insn));
3865 gcc_assert (!ret);
3866
3867 /* Emit SLB instruction pattern. */
3868 if (!register_operand (src, GET_MODE (dst)))
3869 src = force_reg (GET_MODE (dst), src);
3870
3871 op_res = gen_rtx_MINUS (GET_MODE (dst),
3872 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3873 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3874 gen_rtx_REG (cc_mode, CC_REGNUM),
3875 const0_rtx));
3876 p = rtvec_alloc (2);
3877 RTVEC_ELT (p, 0) =
3878 gen_rtx_SET (VOIDmode, dst, op_res);
3879 RTVEC_ELT (p, 1) =
3880 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3881 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3882
3883 return true;
3884 }
3885
3886 return false;
3887 }
3888
3889 /* Expand code for the insv template. Return true if successful, false else. */
3890
3891 bool
3892 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3893 {
3894 int bitsize = INTVAL (op1);
3895 int bitpos = INTVAL (op2);
3896
3897 /* We need byte alignment. */
3898 if (bitsize % BITS_PER_UNIT)
3899 return false;
3900
3901 if (bitpos == 0
3902 && memory_operand (dest, VOIDmode)
3903 && (register_operand (src, word_mode)
3904 || const_int_operand (src, VOIDmode)))
3905 {
3906 /* Emit standard pattern if possible. */
3907 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3908 if (GET_MODE_BITSIZE (mode) == bitsize)
3909 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3910
3911 /* (set (ze (mem)) (const_int)). */
3912 else if (const_int_operand (src, VOIDmode))
3913 {
3914 int size = bitsize / BITS_PER_UNIT;
3915 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
3916 GET_MODE_SIZE (word_mode) - size);
3917
3918 dest = adjust_address (dest, BLKmode, 0);
3919 set_mem_size (dest, GEN_INT (size));
3920 s390_expand_movmem (dest, src_mem, GEN_INT (size));
3921 }
3922
3923 /* (set (ze (mem)) (reg)). */
3924 else if (register_operand (src, word_mode))
3925 {
3926 if (bitsize <= GET_MODE_BITSIZE (SImode))
3927 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
3928 const0_rtx), src);
3929 else
3930 {
3931 /* Emit st,stcmh sequence. */
3932 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
3933 int size = stcmh_width / BITS_PER_UNIT;
3934
3935 emit_move_insn (adjust_address (dest, SImode, size),
3936 gen_lowpart (SImode, src));
3937 set_mem_size (dest, GEN_INT (size));
3938 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
3939 (stcmh_width), const0_rtx),
3940 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
3941 (GET_MODE_BITSIZE (SImode))));
3942 }
3943 }
3944 else
3945 return false;
3946
3947 return true;
3948 }
3949
3950 /* (set (ze (reg)) (const_int)). */
3951 if (TARGET_ZARCH
3952 && register_operand (dest, word_mode)
3953 && (bitpos % 16) == 0
3954 && (bitsize % 16) == 0
3955 && const_int_operand (src, VOIDmode))
3956 {
3957 HOST_WIDE_INT val = INTVAL (src);
3958 int regpos = bitpos + bitsize;
3959
3960 while (regpos > bitpos)
3961 {
3962 enum machine_mode putmode;
3963 int putsize;
3964
3965 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
3966 putmode = SImode;
3967 else
3968 putmode = HImode;
3969
3970 putsize = GET_MODE_BITSIZE (putmode);
3971 regpos -= putsize;
3972 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
3973 GEN_INT (putsize),
3974 GEN_INT (regpos)),
3975 gen_int_mode (val, putmode));
3976 val >>= putsize;
3977 }
3978 gcc_assert (regpos == bitpos);
3979 return true;
3980 }
3981
3982 return false;
3983 }
3984
3985 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
3986 register that holds VAL of mode MODE shifted by COUNT bits. */
3987
3988 static inline rtx
3989 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
3990 {
3991 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
3992 NULL_RTX, 1, OPTAB_DIRECT);
3993 return expand_simple_binop (SImode, ASHIFT, val, count,
3994 NULL_RTX, 1, OPTAB_DIRECT);
3995 }
3996
3997 /* Structure to hold the initial parameters for a compare_and_swap operation
3998 in HImode and QImode. */
3999
4000 struct alignment_context
4001 {
4002 rtx memsi; /* SI aligned memory location. */
4003 rtx shift; /* Bit offset with regard to lsb. */
4004 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4005 rtx modemaski; /* ~modemask */
4006 bool aligned; /* True if memory is aligned, false else. */
4007 };
4008
4009 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4010 structure AC for transparent simplifying, if the memory alignment is known
4011 to be at least 32bit. MEM is the memory location for the actual operation
4012 and MODE its mode. */
4013
4014 static void
4015 init_alignment_context (struct alignment_context *ac, rtx mem,
4016 enum machine_mode mode)
4017 {
4018 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4019 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4020
4021 if (ac->aligned)
4022 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4023 else
4024 {
4025 /* Alignment is unknown. */
4026 rtx byteoffset, addr, align;
4027
4028 /* Force the address into a register. */
4029 addr = force_reg (Pmode, XEXP (mem, 0));
4030
4031 /* Align it to SImode. */
4032 align = expand_simple_binop (Pmode, AND, addr,
4033 GEN_INT (-GET_MODE_SIZE (SImode)),
4034 NULL_RTX, 1, OPTAB_DIRECT);
4035 /* Generate MEM. */
4036 ac->memsi = gen_rtx_MEM (SImode, align);
4037 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4038 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4039 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4040
4041 /* Calculate shiftcount. */
4042 byteoffset = expand_simple_binop (Pmode, AND, addr,
4043 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4044 NULL_RTX, 1, OPTAB_DIRECT);
4045 /* As we already have some offset, evaluate the remaining distance. */
4046 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4047 NULL_RTX, 1, OPTAB_DIRECT);
4048
4049 }
4050 /* Shift is the byte count, but we need the bitcount. */
4051 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4052 NULL_RTX, 1, OPTAB_DIRECT);
4053 /* Calculate masks. */
4054 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4055 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4056 NULL_RTX, 1, OPTAB_DIRECT);
4057 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4058 }
4059
4060 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4061 the memory location, CMP the old value to compare MEM with and NEW the value
4062 to set if CMP == MEM.
4063 CMP is never in memory for compare_and_swap_cc because
4064 expand_bool_compare_and_swap puts it into a register for later compare. */
4065
4066 void
4067 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4068 {
4069 struct alignment_context ac;
4070 rtx cmpv, newv, val, resv, cc;
4071 rtx res = gen_reg_rtx (SImode);
4072 rtx csloop = gen_label_rtx ();
4073 rtx csend = gen_label_rtx ();
4074
4075 gcc_assert (register_operand (target, VOIDmode));
4076 gcc_assert (MEM_P (mem));
4077
4078 init_alignment_context (&ac, mem, mode);
4079
4080 /* Shift the values to the correct bit positions. */
4081 if (!(ac.aligned && MEM_P (cmp)))
4082 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4083 if (!(ac.aligned && MEM_P (new)))
4084 new = s390_expand_mask_and_shift (new, mode, ac.shift);
4085
4086 /* Load full word. Subsequent loads are performed by CS. */
4087 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4088 NULL_RTX, 1, OPTAB_DIRECT);
4089
4090 /* Start CS loop. */
4091 emit_label (csloop);
4092 /* val = "<mem>00..0<mem>"
4093 * cmp = "00..0<cmp>00..0"
4094 * new = "00..0<new>00..0"
4095 */
4096
4097 /* Patch cmp and new with val at correct position. */
4098 if (ac.aligned && MEM_P (cmp))
4099 {
4100 cmpv = force_reg (SImode, val);
4101 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4102 }
4103 else
4104 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4105 NULL_RTX, 1, OPTAB_DIRECT));
4106 if (ac.aligned && MEM_P (new))
4107 {
4108 newv = force_reg (SImode, val);
4109 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4110 }
4111 else
4112 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4113 NULL_RTX, 1, OPTAB_DIRECT));
4114
4115 /* Emit compare_and_swap pattern. */
4116 emit_insn (gen_sync_compare_and_swap_ccsi (res, ac.memsi, cmpv, newv));
4117
4118 /* Jump to end if we're done (likely?). */
4119 s390_emit_jump (csend, s390_emit_compare (EQ, cmpv, ac.memsi));
4120
4121 /* Check for changes outside mode. */
4122 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4123 NULL_RTX, 1, OPTAB_DIRECT);
4124 cc = s390_emit_compare (NE, resv, val);
4125 emit_move_insn (val, resv);
4126 /* Loop internal if so. */
4127 s390_emit_jump (csloop, cc);
4128
4129 emit_label (csend);
4130
4131 /* Return the correct part of the bitfield. */
4132 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4133 NULL_RTX, 1, OPTAB_DIRECT), 1);
4134 }
4135
4136 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4137 and VAL the value to play with. If AFTER is true then store the the value
4138 MEM holds after the operation, if AFTER is false then store the value MEM
4139 holds before the operation. If TARGET is zero then discard that value, else
4140 store it to TARGET. */
4141
4142 void
4143 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4144 rtx target, rtx mem, rtx val, bool after)
4145 {
4146 struct alignment_context ac;
4147 rtx cmp;
4148 rtx new = gen_reg_rtx (SImode);
4149 rtx orig = gen_reg_rtx (SImode);
4150 rtx csloop = gen_label_rtx ();
4151
4152 gcc_assert (!target || register_operand (target, VOIDmode));
4153 gcc_assert (MEM_P (mem));
4154
4155 init_alignment_context (&ac, mem, mode);
4156
4157 /* Shift val to the correct bit positions.
4158 Preserve "icm", but prevent "ex icm". */
4159 if (!(ac.aligned && code == SET && MEM_P (val)))
4160 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4161
4162 /* Further preparation insns. */
4163 if (code == PLUS || code == MINUS)
4164 emit_move_insn (orig, val);
4165 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4166 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4167 NULL_RTX, 1, OPTAB_DIRECT);
4168
4169 /* Load full word. Subsequent loads are performed by CS. */
4170 cmp = force_reg (SImode, ac.memsi);
4171
4172 /* Start CS loop. */
4173 emit_label (csloop);
4174 emit_move_insn (new, cmp);
4175
4176 /* Patch new with val at correct position. */
4177 switch (code)
4178 {
4179 case PLUS:
4180 case MINUS:
4181 val = expand_simple_binop (SImode, code, new, orig,
4182 NULL_RTX, 1, OPTAB_DIRECT);
4183 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4184 NULL_RTX, 1, OPTAB_DIRECT);
4185 /* FALLTHRU */
4186 case SET:
4187 if (ac.aligned && MEM_P (val))
4188 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4189 else
4190 {
4191 new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4192 NULL_RTX, 1, OPTAB_DIRECT);
4193 new = expand_simple_binop (SImode, IOR, new, val,
4194 NULL_RTX, 1, OPTAB_DIRECT);
4195 }
4196 break;
4197 case AND:
4198 case IOR:
4199 case XOR:
4200 new = expand_simple_binop (SImode, code, new, val,
4201 NULL_RTX, 1, OPTAB_DIRECT);
4202 break;
4203 case MULT: /* NAND */
4204 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4205 NULL_RTX, 1, OPTAB_DIRECT);
4206 new = expand_simple_binop (SImode, AND, new, val,
4207 NULL_RTX, 1, OPTAB_DIRECT);
4208 break;
4209 default:
4210 gcc_unreachable ();
4211 }
4212 /* Emit compare_and_swap pattern. */
4213 emit_insn (gen_sync_compare_and_swap_ccsi (cmp, ac.memsi, cmp, new));
4214
4215 /* Loop until swapped (unlikely?). */
4216 s390_emit_jump (csloop, gen_rtx_fmt_ee (NE, CCZ1mode,
4217 gen_rtx_REG (CCZ1mode, CC_REGNUM),
4218 const0_rtx));
4219
4220 /* Return the correct part of the bitfield. */
4221 if (target)
4222 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4223 after ? new : cmp, ac.shift,
4224 NULL_RTX, 1, OPTAB_DIRECT), 1);
4225 }
4226
4227 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4228 We need to emit DTP-relative relocations. */
4229
4230 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4231
4232 static void
4233 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4234 {
4235 switch (size)
4236 {
4237 case 4:
4238 fputs ("\t.long\t", file);
4239 break;
4240 case 8:
4241 fputs ("\t.quad\t", file);
4242 break;
4243 default:
4244 gcc_unreachable ();
4245 }
4246 output_addr_const (file, x);
4247 fputs ("@DTPOFF", file);
4248 }
4249
4250 /* In the name of slightly smaller debug output, and to cater to
4251 general assembler lossage, recognize various UNSPEC sequences
4252 and turn them back into a direct symbol reference. */
4253
4254 static rtx
4255 s390_delegitimize_address (rtx orig_x)
4256 {
4257 rtx x = orig_x, y;
4258
4259 if (GET_CODE (x) != MEM)
4260 return orig_x;
4261
4262 x = XEXP (x, 0);
4263 if (GET_CODE (x) == PLUS
4264 && GET_CODE (XEXP (x, 1)) == CONST
4265 && GET_CODE (XEXP (x, 0)) == REG
4266 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4267 {
4268 y = XEXP (XEXP (x, 1), 0);
4269 if (GET_CODE (y) == UNSPEC
4270 && XINT (y, 1) == UNSPEC_GOT)
4271 return XVECEXP (y, 0, 0);
4272 return orig_x;
4273 }
4274
4275 if (GET_CODE (x) == CONST)
4276 {
4277 y = XEXP (x, 0);
4278 if (GET_CODE (y) == UNSPEC
4279 && XINT (y, 1) == UNSPEC_GOTENT)
4280 return XVECEXP (y, 0, 0);
4281 return orig_x;
4282 }
4283
4284 return orig_x;
4285 }
4286
4287 /* Output operand OP to stdio stream FILE.
4288 OP is an address (register + offset) which is not used to address data;
4289 instead the rightmost bits are interpreted as the value. */
4290
4291 static void
4292 print_shift_count_operand (FILE *file, rtx op)
4293 {
4294 HOST_WIDE_INT offset;
4295 rtx base;
4296
4297 /* Extract base register and offset. */
4298 if (!s390_decompose_shift_count (op, &base, &offset))
4299 gcc_unreachable ();
4300
4301 /* Sanity check. */
4302 if (base)
4303 {
4304 gcc_assert (GET_CODE (base) == REG);
4305 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4306 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4307 }
4308
4309 /* Offsets are constricted to twelve bits. */
4310 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4311 if (base)
4312 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4313 }
4314
4315 /* See 'get_some_local_dynamic_name'. */
4316
4317 static int
4318 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4319 {
4320 rtx x = *px;
4321
4322 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4323 {
4324 x = get_pool_constant (x);
4325 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4326 }
4327
4328 if (GET_CODE (x) == SYMBOL_REF
4329 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4330 {
4331 cfun->machine->some_ld_name = XSTR (x, 0);
4332 return 1;
4333 }
4334
4335 return 0;
4336 }
4337
4338 /* Locate some local-dynamic symbol still in use by this function
4339 so that we can print its name in local-dynamic base patterns. */
4340
4341 static const char *
4342 get_some_local_dynamic_name (void)
4343 {
4344 rtx insn;
4345
4346 if (cfun->machine->some_ld_name)
4347 return cfun->machine->some_ld_name;
4348
4349 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4350 if (INSN_P (insn)
4351 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4352 return cfun->machine->some_ld_name;
4353
4354 gcc_unreachable ();
4355 }
4356
4357 /* Output machine-dependent UNSPECs occurring in address constant X
4358 in assembler syntax to stdio stream FILE. Returns true if the
4359 constant X could be recognized, false otherwise. */
4360
4361 bool
4362 s390_output_addr_const_extra (FILE *file, rtx x)
4363 {
4364 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4365 switch (XINT (x, 1))
4366 {
4367 case UNSPEC_GOTENT:
4368 output_addr_const (file, XVECEXP (x, 0, 0));
4369 fprintf (file, "@GOTENT");
4370 return true;
4371 case UNSPEC_GOT:
4372 output_addr_const (file, XVECEXP (x, 0, 0));
4373 fprintf (file, "@GOT");
4374 return true;
4375 case UNSPEC_GOTOFF:
4376 output_addr_const (file, XVECEXP (x, 0, 0));
4377 fprintf (file, "@GOTOFF");
4378 return true;
4379 case UNSPEC_PLT:
4380 output_addr_const (file, XVECEXP (x, 0, 0));
4381 fprintf (file, "@PLT");
4382 return true;
4383 case UNSPEC_PLTOFF:
4384 output_addr_const (file, XVECEXP (x, 0, 0));
4385 fprintf (file, "@PLTOFF");
4386 return true;
4387 case UNSPEC_TLSGD:
4388 output_addr_const (file, XVECEXP (x, 0, 0));
4389 fprintf (file, "@TLSGD");
4390 return true;
4391 case UNSPEC_TLSLDM:
4392 assemble_name (file, get_some_local_dynamic_name ());
4393 fprintf (file, "@TLSLDM");
4394 return true;
4395 case UNSPEC_DTPOFF:
4396 output_addr_const (file, XVECEXP (x, 0, 0));
4397 fprintf (file, "@DTPOFF");
4398 return true;
4399 case UNSPEC_NTPOFF:
4400 output_addr_const (file, XVECEXP (x, 0, 0));
4401 fprintf (file, "@NTPOFF");
4402 return true;
4403 case UNSPEC_GOTNTPOFF:
4404 output_addr_const (file, XVECEXP (x, 0, 0));
4405 fprintf (file, "@GOTNTPOFF");
4406 return true;
4407 case UNSPEC_INDNTPOFF:
4408 output_addr_const (file, XVECEXP (x, 0, 0));
4409 fprintf (file, "@INDNTPOFF");
4410 return true;
4411 }
4412
4413 return false;
4414 }
4415
4416 /* Output address operand ADDR in assembler syntax to
4417 stdio stream FILE. */
4418
4419 void
4420 print_operand_address (FILE *file, rtx addr)
4421 {
4422 struct s390_address ad;
4423
4424 if (!s390_decompose_address (addr, &ad)
4425 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
4426 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
4427 output_operand_lossage ("cannot decompose address");
4428
4429 if (ad.disp)
4430 output_addr_const (file, ad.disp);
4431 else
4432 fprintf (file, "0");
4433
4434 if (ad.base && ad.indx)
4435 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4436 reg_names[REGNO (ad.base)]);
4437 else if (ad.base)
4438 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4439 }
4440
4441 /* Output operand X in assembler syntax to stdio stream FILE.
4442 CODE specified the format flag. The following format flags
4443 are recognized:
4444
4445 'C': print opcode suffix for branch condition.
4446 'D': print opcode suffix for inverse branch condition.
4447 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4448 'G': print the size of the operand in bytes.
4449 'O': print only the displacement of a memory reference.
4450 'R': print only the base register of a memory reference.
4451 'S': print S-type memory reference (base+displacement).
4452 'N': print the second word of a DImode operand.
4453 'M': print the second word of a TImode operand.
4454 'Y': print shift count operand.
4455
4456 'b': print integer X as if it's an unsigned byte.
4457 'x': print integer X as if it's an unsigned halfword.
4458 'h': print integer X as if it's a signed halfword.
4459 'i': print the first nonzero HImode part of X.
4460 'j': print the first HImode part unequal to -1 of X.
4461 'k': print the first nonzero SImode part of X.
4462 'm': print the first SImode part unequal to -1 of X.
4463 'o': print integer X as if it's an unsigned 32bit word. */
4464
4465 void
4466 print_operand (FILE *file, rtx x, int code)
4467 {
4468 switch (code)
4469 {
4470 case 'C':
4471 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4472 return;
4473
4474 case 'D':
4475 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4476 return;
4477
4478 case 'J':
4479 if (GET_CODE (x) == SYMBOL_REF)
4480 {
4481 fprintf (file, "%s", ":tls_load:");
4482 output_addr_const (file, x);
4483 }
4484 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4485 {
4486 fprintf (file, "%s", ":tls_gdcall:");
4487 output_addr_const (file, XVECEXP (x, 0, 0));
4488 }
4489 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4490 {
4491 fprintf (file, "%s", ":tls_ldcall:");
4492 assemble_name (file, get_some_local_dynamic_name ());
4493 }
4494 else
4495 gcc_unreachable ();
4496 return;
4497
4498 case 'G':
4499 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4500 return;
4501
4502 case 'O':
4503 {
4504 struct s390_address ad;
4505 int ret;
4506
4507 gcc_assert (GET_CODE (x) == MEM);
4508 ret = s390_decompose_address (XEXP (x, 0), &ad);
4509 gcc_assert (ret);
4510 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4511 gcc_assert (!ad.indx);
4512
4513 if (ad.disp)
4514 output_addr_const (file, ad.disp);
4515 else
4516 fprintf (file, "0");
4517 }
4518 return;
4519
4520 case 'R':
4521 {
4522 struct s390_address ad;
4523 int ret;
4524
4525 gcc_assert (GET_CODE (x) == MEM);
4526 ret = s390_decompose_address (XEXP (x, 0), &ad);
4527 gcc_assert (ret);
4528 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4529 gcc_assert (!ad.indx);
4530
4531 if (ad.base)
4532 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4533 else
4534 fprintf (file, "0");
4535 }
4536 return;
4537
4538 case 'S':
4539 {
4540 struct s390_address ad;
4541 int ret;
4542
4543 gcc_assert (GET_CODE (x) == MEM);
4544 ret = s390_decompose_address (XEXP (x, 0), &ad);
4545 gcc_assert (ret);
4546 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4547 gcc_assert (!ad.indx);
4548
4549 if (ad.disp)
4550 output_addr_const (file, ad.disp);
4551 else
4552 fprintf (file, "0");
4553
4554 if (ad.base)
4555 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4556 }
4557 return;
4558
4559 case 'N':
4560 if (GET_CODE (x) == REG)
4561 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4562 else if (GET_CODE (x) == MEM)
4563 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4564 else
4565 gcc_unreachable ();
4566 break;
4567
4568 case 'M':
4569 if (GET_CODE (x) == REG)
4570 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4571 else if (GET_CODE (x) == MEM)
4572 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4573 else
4574 gcc_unreachable ();
4575 break;
4576
4577 case 'Y':
4578 print_shift_count_operand (file, x);
4579 return;
4580 }
4581
4582 switch (GET_CODE (x))
4583 {
4584 case REG:
4585 fprintf (file, "%s", reg_names[REGNO (x)]);
4586 break;
4587
4588 case MEM:
4589 output_address (XEXP (x, 0));
4590 break;
4591
4592 case CONST:
4593 case CODE_LABEL:
4594 case LABEL_REF:
4595 case SYMBOL_REF:
4596 output_addr_const (file, x);
4597 break;
4598
4599 case CONST_INT:
4600 if (code == 'b')
4601 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4602 else if (code == 'x')
4603 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4604 else if (code == 'h')
4605 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4606 else if (code == 'i')
4607 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4608 s390_extract_part (x, HImode, 0));
4609 else if (code == 'j')
4610 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4611 s390_extract_part (x, HImode, -1));
4612 else if (code == 'k')
4613 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4614 s390_extract_part (x, SImode, 0));
4615 else if (code == 'm')
4616 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4617 s390_extract_part (x, SImode, -1));
4618 else if (code == 'o')
4619 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4620 else
4621 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4622 break;
4623
4624 case CONST_DOUBLE:
4625 gcc_assert (GET_MODE (x) == VOIDmode);
4626 if (code == 'b')
4627 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4628 else if (code == 'x')
4629 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4630 else if (code == 'h')
4631 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4632 else
4633 gcc_unreachable ();
4634 break;
4635
4636 default:
4637 fatal_insn ("UNKNOWN in print_operand !?", x);
4638 break;
4639 }
4640 }
4641
4642 /* Target hook for assembling integer objects. We need to define it
4643 here to work a round a bug in some versions of GAS, which couldn't
4644 handle values smaller than INT_MIN when printed in decimal. */
4645
4646 static bool
4647 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4648 {
4649 if (size == 8 && aligned_p
4650 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4651 {
4652 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4653 INTVAL (x));
4654 return true;
4655 }
4656 return default_assemble_integer (x, size, aligned_p);
4657 }
4658
4659 /* Returns true if register REGNO is used for forming
4660 a memory address in expression X. */
4661
4662 static bool
4663 reg_used_in_mem_p (int regno, rtx x)
4664 {
4665 enum rtx_code code = GET_CODE (x);
4666 int i, j;
4667 const char *fmt;
4668
4669 if (code == MEM)
4670 {
4671 if (refers_to_regno_p (regno, regno+1,
4672 XEXP (x, 0), 0))
4673 return true;
4674 }
4675 else if (code == SET
4676 && GET_CODE (SET_DEST (x)) == PC)
4677 {
4678 if (refers_to_regno_p (regno, regno+1,
4679 SET_SRC (x), 0))
4680 return true;
4681 }
4682
4683 fmt = GET_RTX_FORMAT (code);
4684 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4685 {
4686 if (fmt[i] == 'e'
4687 && reg_used_in_mem_p (regno, XEXP (x, i)))
4688 return true;
4689
4690 else if (fmt[i] == 'E')
4691 for (j = 0; j < XVECLEN (x, i); j++)
4692 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4693 return true;
4694 }
4695 return false;
4696 }
4697
4698 /* Returns true if expression DEP_RTX sets an address register
4699 used by instruction INSN to address memory. */
4700
4701 static bool
4702 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4703 {
4704 rtx target, pat;
4705
4706 if (GET_CODE (dep_rtx) == INSN)
4707 dep_rtx = PATTERN (dep_rtx);
4708
4709 if (GET_CODE (dep_rtx) == SET)
4710 {
4711 target = SET_DEST (dep_rtx);
4712 if (GET_CODE (target) == STRICT_LOW_PART)
4713 target = XEXP (target, 0);
4714 while (GET_CODE (target) == SUBREG)
4715 target = SUBREG_REG (target);
4716
4717 if (GET_CODE (target) == REG)
4718 {
4719 int regno = REGNO (target);
4720
4721 if (s390_safe_attr_type (insn) == TYPE_LA)
4722 {
4723 pat = PATTERN (insn);
4724 if (GET_CODE (pat) == PARALLEL)
4725 {
4726 gcc_assert (XVECLEN (pat, 0) == 2);
4727 pat = XVECEXP (pat, 0, 0);
4728 }
4729 gcc_assert (GET_CODE (pat) == SET);
4730 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4731 }
4732 else if (get_attr_atype (insn) == ATYPE_AGEN)
4733 return reg_used_in_mem_p (regno, PATTERN (insn));
4734 }
4735 }
4736 return false;
4737 }
4738
4739 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4740
4741 int
4742 s390_agen_dep_p (rtx dep_insn, rtx insn)
4743 {
4744 rtx dep_rtx = PATTERN (dep_insn);
4745 int i;
4746
4747 if (GET_CODE (dep_rtx) == SET
4748 && addr_generation_dependency_p (dep_rtx, insn))
4749 return 1;
4750 else if (GET_CODE (dep_rtx) == PARALLEL)
4751 {
4752 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4753 {
4754 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4755 return 1;
4756 }
4757 }
4758 return 0;
4759 }
4760
4761 /* A C statement (sans semicolon) to update the integer scheduling priority
4762 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4763 reduce the priority to execute INSN later. Do not define this macro if
4764 you do not need to adjust the scheduling priorities of insns.
4765
4766 A STD instruction should be scheduled earlier,
4767 in order to use the bypass. */
4768
4769 static int
4770 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4771 {
4772 if (! INSN_P (insn))
4773 return priority;
4774
4775 if (s390_tune != PROCESSOR_2084_Z990
4776 && s390_tune != PROCESSOR_2094_Z9_109)
4777 return priority;
4778
4779 switch (s390_safe_attr_type (insn))
4780 {
4781 case TYPE_FSTOREDF:
4782 case TYPE_FSTORESF:
4783 priority = priority << 3;
4784 break;
4785 case TYPE_STORE:
4786 case TYPE_STM:
4787 priority = priority << 1;
4788 break;
4789 default:
4790 break;
4791 }
4792 return priority;
4793 }
4794
4795 /* The number of instructions that can be issued per cycle. */
4796
4797 static int
4798 s390_issue_rate (void)
4799 {
4800 if (s390_tune == PROCESSOR_2084_Z990
4801 || s390_tune == PROCESSOR_2094_Z9_109)
4802 return 3;
4803 return 1;
4804 }
4805
4806 static int
4807 s390_first_cycle_multipass_dfa_lookahead (void)
4808 {
4809 return 4;
4810 }
4811
4812
4813 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4814 Fix up MEMs as required. */
4815
4816 static void
4817 annotate_constant_pool_refs (rtx *x)
4818 {
4819 int i, j;
4820 const char *fmt;
4821
4822 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4823 || !CONSTANT_POOL_ADDRESS_P (*x));
4824
4825 /* Literal pool references can only occur inside a MEM ... */
4826 if (GET_CODE (*x) == MEM)
4827 {
4828 rtx memref = XEXP (*x, 0);
4829
4830 if (GET_CODE (memref) == SYMBOL_REF
4831 && CONSTANT_POOL_ADDRESS_P (memref))
4832 {
4833 rtx base = cfun->machine->base_reg;
4834 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4835 UNSPEC_LTREF);
4836
4837 *x = replace_equiv_address (*x, addr);
4838 return;
4839 }
4840
4841 if (GET_CODE (memref) == CONST
4842 && GET_CODE (XEXP (memref, 0)) == PLUS
4843 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4844 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4845 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4846 {
4847 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4848 rtx sym = XEXP (XEXP (memref, 0), 0);
4849 rtx base = cfun->machine->base_reg;
4850 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4851 UNSPEC_LTREF);
4852
4853 *x = replace_equiv_address (*x, plus_constant (addr, off));
4854 return;
4855 }
4856 }
4857
4858 /* ... or a load-address type pattern. */
4859 if (GET_CODE (*x) == SET)
4860 {
4861 rtx addrref = SET_SRC (*x);
4862
4863 if (GET_CODE (addrref) == SYMBOL_REF
4864 && CONSTANT_POOL_ADDRESS_P (addrref))
4865 {
4866 rtx base = cfun->machine->base_reg;
4867 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4868 UNSPEC_LTREF);
4869
4870 SET_SRC (*x) = addr;
4871 return;
4872 }
4873
4874 if (GET_CODE (addrref) == CONST
4875 && GET_CODE (XEXP (addrref, 0)) == PLUS
4876 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4877 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4878 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4879 {
4880 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4881 rtx sym = XEXP (XEXP (addrref, 0), 0);
4882 rtx base = cfun->machine->base_reg;
4883 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4884 UNSPEC_LTREF);
4885
4886 SET_SRC (*x) = plus_constant (addr, off);
4887 return;
4888 }
4889 }
4890
4891 /* Annotate LTREL_BASE as well. */
4892 if (GET_CODE (*x) == UNSPEC
4893 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4894 {
4895 rtx base = cfun->machine->base_reg;
4896 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4897 UNSPEC_LTREL_BASE);
4898 return;
4899 }
4900
4901 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4902 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4903 {
4904 if (fmt[i] == 'e')
4905 {
4906 annotate_constant_pool_refs (&XEXP (*x, i));
4907 }
4908 else if (fmt[i] == 'E')
4909 {
4910 for (j = 0; j < XVECLEN (*x, i); j++)
4911 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
4912 }
4913 }
4914 }
4915
4916 /* Split all branches that exceed the maximum distance.
4917 Returns true if this created a new literal pool entry. */
4918
4919 static int
4920 s390_split_branches (void)
4921 {
4922 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4923 int new_literal = 0, ret;
4924 rtx insn, pat, tmp, target;
4925 rtx *label;
4926
4927 /* We need correct insn addresses. */
4928
4929 shorten_branches (get_insns ());
4930
4931 /* Find all branches that exceed 64KB, and split them. */
4932
4933 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4934 {
4935 if (GET_CODE (insn) != JUMP_INSN)
4936 continue;
4937
4938 pat = PATTERN (insn);
4939 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
4940 pat = XVECEXP (pat, 0, 0);
4941 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
4942 continue;
4943
4944 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
4945 {
4946 label = &SET_SRC (pat);
4947 }
4948 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
4949 {
4950 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
4951 label = &XEXP (SET_SRC (pat), 1);
4952 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
4953 label = &XEXP (SET_SRC (pat), 2);
4954 else
4955 continue;
4956 }
4957 else
4958 continue;
4959
4960 if (get_attr_length (insn) <= 4)
4961 continue;
4962
4963 /* We are going to use the return register as scratch register,
4964 make sure it will be saved/restored by the prologue/epilogue. */
4965 cfun_frame_layout.save_return_addr_p = 1;
4966
4967 if (!flag_pic)
4968 {
4969 new_literal = 1;
4970 tmp = force_const_mem (Pmode, *label);
4971 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
4972 INSN_ADDRESSES_NEW (tmp, -1);
4973 annotate_constant_pool_refs (&PATTERN (tmp));
4974
4975 target = temp_reg;
4976 }
4977 else
4978 {
4979 new_literal = 1;
4980 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
4981 UNSPEC_LTREL_OFFSET);
4982 target = gen_rtx_CONST (Pmode, target);
4983 target = force_const_mem (Pmode, target);
4984 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
4985 INSN_ADDRESSES_NEW (tmp, -1);
4986 annotate_constant_pool_refs (&PATTERN (tmp));
4987
4988 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
4989 cfun->machine->base_reg),
4990 UNSPEC_LTREL_BASE);
4991 target = gen_rtx_PLUS (Pmode, temp_reg, target);
4992 }
4993
4994 ret = validate_change (insn, label, target, 0);
4995 gcc_assert (ret);
4996 }
4997
4998 return new_literal;
4999 }
5000
5001
5002 /* Find an annotated literal pool symbol referenced in RTX X,
5003 and store it at REF. Will abort if X contains references to
5004 more than one such pool symbol; multiple references to the same
5005 symbol are allowed, however.
5006
5007 The rtx pointed to by REF must be initialized to NULL_RTX
5008 by the caller before calling this routine. */
5009
5010 static void
5011 find_constant_pool_ref (rtx x, rtx *ref)
5012 {
5013 int i, j;
5014 const char *fmt;
5015
5016 /* Ignore LTREL_BASE references. */
5017 if (GET_CODE (x) == UNSPEC
5018 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5019 return;
5020 /* Likewise POOL_ENTRY insns. */
5021 if (GET_CODE (x) == UNSPEC_VOLATILE
5022 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5023 return;
5024
5025 gcc_assert (GET_CODE (x) != SYMBOL_REF
5026 || !CONSTANT_POOL_ADDRESS_P (x));
5027
5028 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5029 {
5030 rtx sym = XVECEXP (x, 0, 0);
5031 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5032 && CONSTANT_POOL_ADDRESS_P (sym));
5033
5034 if (*ref == NULL_RTX)
5035 *ref = sym;
5036 else
5037 gcc_assert (*ref == sym);
5038
5039 return;
5040 }
5041
5042 fmt = GET_RTX_FORMAT (GET_CODE (x));
5043 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5044 {
5045 if (fmt[i] == 'e')
5046 {
5047 find_constant_pool_ref (XEXP (x, i), ref);
5048 }
5049 else if (fmt[i] == 'E')
5050 {
5051 for (j = 0; j < XVECLEN (x, i); j++)
5052 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5053 }
5054 }
5055 }
5056
5057 /* Replace every reference to the annotated literal pool
5058 symbol REF in X by its base plus OFFSET. */
5059
5060 static void
5061 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5062 {
5063 int i, j;
5064 const char *fmt;
5065
5066 gcc_assert (*x != ref);
5067
5068 if (GET_CODE (*x) == UNSPEC
5069 && XINT (*x, 1) == UNSPEC_LTREF
5070 && XVECEXP (*x, 0, 0) == ref)
5071 {
5072 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5073 return;
5074 }
5075
5076 if (GET_CODE (*x) == PLUS
5077 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5078 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5079 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5080 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5081 {
5082 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5083 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5084 return;
5085 }
5086
5087 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5088 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5089 {
5090 if (fmt[i] == 'e')
5091 {
5092 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5093 }
5094 else if (fmt[i] == 'E')
5095 {
5096 for (j = 0; j < XVECLEN (*x, i); j++)
5097 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5098 }
5099 }
5100 }
5101
5102 /* Check whether X contains an UNSPEC_LTREL_BASE.
5103 Return its constant pool symbol if found, NULL_RTX otherwise. */
5104
5105 static rtx
5106 find_ltrel_base (rtx x)
5107 {
5108 int i, j;
5109 const char *fmt;
5110
5111 if (GET_CODE (x) == UNSPEC
5112 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5113 return XVECEXP (x, 0, 0);
5114
5115 fmt = GET_RTX_FORMAT (GET_CODE (x));
5116 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5117 {
5118 if (fmt[i] == 'e')
5119 {
5120 rtx fnd = find_ltrel_base (XEXP (x, i));
5121 if (fnd)
5122 return fnd;
5123 }
5124 else if (fmt[i] == 'E')
5125 {
5126 for (j = 0; j < XVECLEN (x, i); j++)
5127 {
5128 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5129 if (fnd)
5130 return fnd;
5131 }
5132 }
5133 }
5134
5135 return NULL_RTX;
5136 }
5137
5138 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5139
5140 static void
5141 replace_ltrel_base (rtx *x)
5142 {
5143 int i, j;
5144 const char *fmt;
5145
5146 if (GET_CODE (*x) == UNSPEC
5147 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5148 {
5149 *x = XVECEXP (*x, 0, 1);
5150 return;
5151 }
5152
5153 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5154 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5155 {
5156 if (fmt[i] == 'e')
5157 {
5158 replace_ltrel_base (&XEXP (*x, i));
5159 }
5160 else if (fmt[i] == 'E')
5161 {
5162 for (j = 0; j < XVECLEN (*x, i); j++)
5163 replace_ltrel_base (&XVECEXP (*x, i, j));
5164 }
5165 }
5166 }
5167
5168
5169 /* We keep a list of constants which we have to add to internal
5170 constant tables in the middle of large functions. */
5171
5172 #define NR_C_MODES 7
5173 enum machine_mode constant_modes[NR_C_MODES] =
5174 {
5175 TImode,
5176 DFmode, DImode,
5177 SFmode, SImode,
5178 HImode,
5179 QImode
5180 };
5181
5182 struct constant
5183 {
5184 struct constant *next;
5185 rtx value;
5186 rtx label;
5187 };
5188
5189 struct constant_pool
5190 {
5191 struct constant_pool *next;
5192 rtx first_insn;
5193 rtx pool_insn;
5194 bitmap insns;
5195
5196 struct constant *constants[NR_C_MODES];
5197 struct constant *execute;
5198 rtx label;
5199 int size;
5200 };
5201
5202 /* Allocate new constant_pool structure. */
5203
5204 static struct constant_pool *
5205 s390_alloc_pool (void)
5206 {
5207 struct constant_pool *pool;
5208 int i;
5209
5210 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5211 pool->next = NULL;
5212 for (i = 0; i < NR_C_MODES; i++)
5213 pool->constants[i] = NULL;
5214
5215 pool->execute = NULL;
5216 pool->label = gen_label_rtx ();
5217 pool->first_insn = NULL_RTX;
5218 pool->pool_insn = NULL_RTX;
5219 pool->insns = BITMAP_ALLOC (NULL);
5220 pool->size = 0;
5221
5222 return pool;
5223 }
5224
5225 /* Create new constant pool covering instructions starting at INSN
5226 and chain it to the end of POOL_LIST. */
5227
5228 static struct constant_pool *
5229 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5230 {
5231 struct constant_pool *pool, **prev;
5232
5233 pool = s390_alloc_pool ();
5234 pool->first_insn = insn;
5235
5236 for (prev = pool_list; *prev; prev = &(*prev)->next)
5237 ;
5238 *prev = pool;
5239
5240 return pool;
5241 }
5242
5243 /* End range of instructions covered by POOL at INSN and emit
5244 placeholder insn representing the pool. */
5245
5246 static void
5247 s390_end_pool (struct constant_pool *pool, rtx insn)
5248 {
5249 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5250
5251 if (!insn)
5252 insn = get_last_insn ();
5253
5254 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5255 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5256 }
5257
5258 /* Add INSN to the list of insns covered by POOL. */
5259
5260 static void
5261 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5262 {
5263 bitmap_set_bit (pool->insns, INSN_UID (insn));
5264 }
5265
5266 /* Return pool out of POOL_LIST that covers INSN. */
5267
5268 static struct constant_pool *
5269 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5270 {
5271 struct constant_pool *pool;
5272
5273 for (pool = pool_list; pool; pool = pool->next)
5274 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5275 break;
5276
5277 return pool;
5278 }
5279
5280 /* Add constant VAL of mode MODE to the constant pool POOL. */
5281
5282 static void
5283 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5284 {
5285 struct constant *c;
5286 int i;
5287
5288 for (i = 0; i < NR_C_MODES; i++)
5289 if (constant_modes[i] == mode)
5290 break;
5291 gcc_assert (i != NR_C_MODES);
5292
5293 for (c = pool->constants[i]; c != NULL; c = c->next)
5294 if (rtx_equal_p (val, c->value))
5295 break;
5296
5297 if (c == NULL)
5298 {
5299 c = (struct constant *) xmalloc (sizeof *c);
5300 c->value = val;
5301 c->label = gen_label_rtx ();
5302 c->next = pool->constants[i];
5303 pool->constants[i] = c;
5304 pool->size += GET_MODE_SIZE (mode);
5305 }
5306 }
5307
5308 /* Find constant VAL of mode MODE in the constant pool POOL.
5309 Return an RTX describing the distance from the start of
5310 the pool to the location of the new constant. */
5311
5312 static rtx
5313 s390_find_constant (struct constant_pool *pool, rtx val,
5314 enum machine_mode mode)
5315 {
5316 struct constant *c;
5317 rtx offset;
5318 int i;
5319
5320 for (i = 0; i < NR_C_MODES; i++)
5321 if (constant_modes[i] == mode)
5322 break;
5323 gcc_assert (i != NR_C_MODES);
5324
5325 for (c = pool->constants[i]; c != NULL; c = c->next)
5326 if (rtx_equal_p (val, c->value))
5327 break;
5328
5329 gcc_assert (c);
5330
5331 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5332 gen_rtx_LABEL_REF (Pmode, pool->label));
5333 offset = gen_rtx_CONST (Pmode, offset);
5334 return offset;
5335 }
5336
5337 /* Check whether INSN is an execute. Return the label_ref to its
5338 execute target template if so, NULL_RTX otherwise. */
5339
5340 static rtx
5341 s390_execute_label (rtx insn)
5342 {
5343 if (GET_CODE (insn) == INSN
5344 && GET_CODE (PATTERN (insn)) == PARALLEL
5345 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5346 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5347 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5348
5349 return NULL_RTX;
5350 }
5351
5352 /* Add execute target for INSN to the constant pool POOL. */
5353
5354 static void
5355 s390_add_execute (struct constant_pool *pool, rtx insn)
5356 {
5357 struct constant *c;
5358
5359 for (c = pool->execute; c != NULL; c = c->next)
5360 if (INSN_UID (insn) == INSN_UID (c->value))
5361 break;
5362
5363 if (c == NULL)
5364 {
5365 c = (struct constant *) xmalloc (sizeof *c);
5366 c->value = insn;
5367 c->label = gen_label_rtx ();
5368 c->next = pool->execute;
5369 pool->execute = c;
5370 pool->size += 6;
5371 }
5372 }
5373
5374 /* Find execute target for INSN in the constant pool POOL.
5375 Return an RTX describing the distance from the start of
5376 the pool to the location of the execute target. */
5377
5378 static rtx
5379 s390_find_execute (struct constant_pool *pool, rtx insn)
5380 {
5381 struct constant *c;
5382 rtx offset;
5383
5384 for (c = pool->execute; c != NULL; c = c->next)
5385 if (INSN_UID (insn) == INSN_UID (c->value))
5386 break;
5387
5388 gcc_assert (c);
5389
5390 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5391 gen_rtx_LABEL_REF (Pmode, pool->label));
5392 offset = gen_rtx_CONST (Pmode, offset);
5393 return offset;
5394 }
5395
5396 /* For an execute INSN, extract the execute target template. */
5397
5398 static rtx
5399 s390_execute_target (rtx insn)
5400 {
5401 rtx pattern = PATTERN (insn);
5402 gcc_assert (s390_execute_label (insn));
5403
5404 if (XVECLEN (pattern, 0) == 2)
5405 {
5406 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5407 }
5408 else
5409 {
5410 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5411 int i;
5412
5413 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5414 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5415
5416 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5417 }
5418
5419 return pattern;
5420 }
5421
5422 /* Indicate that INSN cannot be duplicated. This is the case for
5423 execute insns that carry a unique label. */
5424
5425 static bool
5426 s390_cannot_copy_insn_p (rtx insn)
5427 {
5428 rtx label = s390_execute_label (insn);
5429 return label && label != const0_rtx;
5430 }
5431
5432 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5433 do not emit the pool base label. */
5434
5435 static void
5436 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5437 {
5438 struct constant *c;
5439 rtx insn = pool->pool_insn;
5440 int i;
5441
5442 /* Switch to rodata section. */
5443 if (TARGET_CPU_ZARCH)
5444 {
5445 insn = emit_insn_after (gen_pool_section_start (), insn);
5446 INSN_ADDRESSES_NEW (insn, -1);
5447 }
5448
5449 /* Ensure minimum pool alignment. */
5450 if (TARGET_CPU_ZARCH)
5451 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5452 else
5453 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5454 INSN_ADDRESSES_NEW (insn, -1);
5455
5456 /* Emit pool base label. */
5457 if (!remote_label)
5458 {
5459 insn = emit_label_after (pool->label, insn);
5460 INSN_ADDRESSES_NEW (insn, -1);
5461 }
5462
5463 /* Dump constants in descending alignment requirement order,
5464 ensuring proper alignment for every constant. */
5465 for (i = 0; i < NR_C_MODES; i++)
5466 for (c = pool->constants[i]; c; c = c->next)
5467 {
5468 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5469 rtx value = c->value;
5470 if (GET_CODE (value) == CONST
5471 && GET_CODE (XEXP (value, 0)) == UNSPEC
5472 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5473 && XVECLEN (XEXP (value, 0), 0) == 1)
5474 {
5475 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5476 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5477 value = gen_rtx_CONST (VOIDmode, value);
5478 }
5479
5480 insn = emit_label_after (c->label, insn);
5481 INSN_ADDRESSES_NEW (insn, -1);
5482
5483 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5484 gen_rtvec (1, value),
5485 UNSPECV_POOL_ENTRY);
5486 insn = emit_insn_after (value, insn);
5487 INSN_ADDRESSES_NEW (insn, -1);
5488 }
5489
5490 /* Ensure minimum alignment for instructions. */
5491 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5492 INSN_ADDRESSES_NEW (insn, -1);
5493
5494 /* Output in-pool execute template insns. */
5495 for (c = pool->execute; c; c = c->next)
5496 {
5497 insn = emit_label_after (c->label, insn);
5498 INSN_ADDRESSES_NEW (insn, -1);
5499
5500 insn = emit_insn_after (s390_execute_target (c->value), insn);
5501 INSN_ADDRESSES_NEW (insn, -1);
5502 }
5503
5504 /* Switch back to previous section. */
5505 if (TARGET_CPU_ZARCH)
5506 {
5507 insn = emit_insn_after (gen_pool_section_end (), insn);
5508 INSN_ADDRESSES_NEW (insn, -1);
5509 }
5510
5511 insn = emit_barrier_after (insn);
5512 INSN_ADDRESSES_NEW (insn, -1);
5513
5514 /* Remove placeholder insn. */
5515 remove_insn (pool->pool_insn);
5516 }
5517
5518 /* Free all memory used by POOL. */
5519
5520 static void
5521 s390_free_pool (struct constant_pool *pool)
5522 {
5523 struct constant *c, *next;
5524 int i;
5525
5526 for (i = 0; i < NR_C_MODES; i++)
5527 for (c = pool->constants[i]; c; c = next)
5528 {
5529 next = c->next;
5530 free (c);
5531 }
5532
5533 for (c = pool->execute; c; c = next)
5534 {
5535 next = c->next;
5536 free (c);
5537 }
5538
5539 BITMAP_FREE (pool->insns);
5540 free (pool);
5541 }
5542
5543
5544 /* Collect main literal pool. Return NULL on overflow. */
5545
5546 static struct constant_pool *
5547 s390_mainpool_start (void)
5548 {
5549 struct constant_pool *pool;
5550 rtx insn;
5551
5552 pool = s390_alloc_pool ();
5553
5554 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5555 {
5556 if (GET_CODE (insn) == INSN
5557 && GET_CODE (PATTERN (insn)) == SET
5558 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5559 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5560 {
5561 gcc_assert (!pool->pool_insn);
5562 pool->pool_insn = insn;
5563 }
5564
5565 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5566 {
5567 s390_add_execute (pool, insn);
5568 }
5569 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5570 {
5571 rtx pool_ref = NULL_RTX;
5572 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5573 if (pool_ref)
5574 {
5575 rtx constant = get_pool_constant (pool_ref);
5576 enum machine_mode mode = get_pool_mode (pool_ref);
5577 s390_add_constant (pool, constant, mode);
5578 }
5579 }
5580 }
5581
5582 gcc_assert (pool->pool_insn || pool->size == 0);
5583
5584 if (pool->size >= 4096)
5585 {
5586 /* We're going to chunkify the pool, so remove the main
5587 pool placeholder insn. */
5588 remove_insn (pool->pool_insn);
5589
5590 s390_free_pool (pool);
5591 pool = NULL;
5592 }
5593
5594 return pool;
5595 }
5596
5597 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5598 Modify the current function to output the pool constants as well as
5599 the pool register setup instruction. */
5600
5601 static void
5602 s390_mainpool_finish (struct constant_pool *pool)
5603 {
5604 rtx base_reg = cfun->machine->base_reg;
5605 rtx insn;
5606
5607 /* If the pool is empty, we're done. */
5608 if (pool->size == 0)
5609 {
5610 /* We don't actually need a base register after all. */
5611 cfun->machine->base_reg = NULL_RTX;
5612
5613 if (pool->pool_insn)
5614 remove_insn (pool->pool_insn);
5615 s390_free_pool (pool);
5616 return;
5617 }
5618
5619 /* We need correct insn addresses. */
5620 shorten_branches (get_insns ());
5621
5622 /* On zSeries, we use a LARL to load the pool register. The pool is
5623 located in the .rodata section, so we emit it after the function. */
5624 if (TARGET_CPU_ZARCH)
5625 {
5626 insn = gen_main_base_64 (base_reg, pool->label);
5627 insn = emit_insn_after (insn, pool->pool_insn);
5628 INSN_ADDRESSES_NEW (insn, -1);
5629 remove_insn (pool->pool_insn);
5630
5631 insn = get_last_insn ();
5632 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5633 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5634
5635 s390_dump_pool (pool, 0);
5636 }
5637
5638 /* On S/390, if the total size of the function's code plus literal pool
5639 does not exceed 4096 bytes, we use BASR to set up a function base
5640 pointer, and emit the literal pool at the end of the function. */
5641 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5642 + pool->size + 8 /* alignment slop */ < 4096)
5643 {
5644 insn = gen_main_base_31_small (base_reg, pool->label);
5645 insn = emit_insn_after (insn, pool->pool_insn);
5646 INSN_ADDRESSES_NEW (insn, -1);
5647 remove_insn (pool->pool_insn);
5648
5649 insn = emit_label_after (pool->label, insn);
5650 INSN_ADDRESSES_NEW (insn, -1);
5651
5652 insn = get_last_insn ();
5653 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5654 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5655
5656 s390_dump_pool (pool, 1);
5657 }
5658
5659 /* Otherwise, we emit an inline literal pool and use BASR to branch
5660 over it, setting up the pool register at the same time. */
5661 else
5662 {
5663 rtx pool_end = gen_label_rtx ();
5664
5665 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5666 insn = emit_insn_after (insn, pool->pool_insn);
5667 INSN_ADDRESSES_NEW (insn, -1);
5668 remove_insn (pool->pool_insn);
5669
5670 insn = emit_label_after (pool->label, insn);
5671 INSN_ADDRESSES_NEW (insn, -1);
5672
5673 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5674 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5675
5676 insn = emit_label_after (pool_end, pool->pool_insn);
5677 INSN_ADDRESSES_NEW (insn, -1);
5678
5679 s390_dump_pool (pool, 1);
5680 }
5681
5682
5683 /* Replace all literal pool references. */
5684
5685 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5686 {
5687 if (INSN_P (insn))
5688 replace_ltrel_base (&PATTERN (insn));
5689
5690 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5691 {
5692 rtx addr, pool_ref = NULL_RTX;
5693 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5694 if (pool_ref)
5695 {
5696 if (s390_execute_label (insn))
5697 addr = s390_find_execute (pool, insn);
5698 else
5699 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5700 get_pool_mode (pool_ref));
5701
5702 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5703 INSN_CODE (insn) = -1;
5704 }
5705 }
5706 }
5707
5708
5709 /* Free the pool. */
5710 s390_free_pool (pool);
5711 }
5712
5713 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5714 We have decided we cannot use this pool, so revert all changes
5715 to the current function that were done by s390_mainpool_start. */
5716 static void
5717 s390_mainpool_cancel (struct constant_pool *pool)
5718 {
5719 /* We didn't actually change the instruction stream, so simply
5720 free the pool memory. */
5721 s390_free_pool (pool);
5722 }
5723
5724
5725 /* Chunkify the literal pool. */
5726
5727 #define S390_POOL_CHUNK_MIN 0xc00
5728 #define S390_POOL_CHUNK_MAX 0xe00
5729
5730 static struct constant_pool *
5731 s390_chunkify_start (void)
5732 {
5733 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5734 int extra_size = 0;
5735 bitmap far_labels;
5736 rtx pending_ltrel = NULL_RTX;
5737 rtx insn;
5738
5739 rtx (*gen_reload_base) (rtx, rtx) =
5740 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5741
5742
5743 /* We need correct insn addresses. */
5744
5745 shorten_branches (get_insns ());
5746
5747 /* Scan all insns and move literals to pool chunks. */
5748
5749 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5750 {
5751 /* Check for pending LTREL_BASE. */
5752 if (INSN_P (insn))
5753 {
5754 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5755 if (ltrel_base)
5756 {
5757 gcc_assert (ltrel_base == pending_ltrel);
5758 pending_ltrel = NULL_RTX;
5759 }
5760 }
5761
5762 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5763 {
5764 if (!curr_pool)
5765 curr_pool = s390_start_pool (&pool_list, insn);
5766
5767 s390_add_execute (curr_pool, insn);
5768 s390_add_pool_insn (curr_pool, insn);
5769 }
5770 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5771 {
5772 rtx pool_ref = NULL_RTX;
5773 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5774 if (pool_ref)
5775 {
5776 rtx constant = get_pool_constant (pool_ref);
5777 enum machine_mode mode = get_pool_mode (pool_ref);
5778
5779 if (!curr_pool)
5780 curr_pool = s390_start_pool (&pool_list, insn);
5781
5782 s390_add_constant (curr_pool, constant, mode);
5783 s390_add_pool_insn (curr_pool, insn);
5784
5785 /* Don't split the pool chunk between a LTREL_OFFSET load
5786 and the corresponding LTREL_BASE. */
5787 if (GET_CODE (constant) == CONST
5788 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5789 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5790 {
5791 gcc_assert (!pending_ltrel);
5792 pending_ltrel = pool_ref;
5793 }
5794 }
5795 }
5796
5797 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5798 {
5799 if (curr_pool)
5800 s390_add_pool_insn (curr_pool, insn);
5801 /* An LTREL_BASE must follow within the same basic block. */
5802 gcc_assert (!pending_ltrel);
5803 }
5804
5805 if (!curr_pool
5806 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5807 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5808 continue;
5809
5810 if (TARGET_CPU_ZARCH)
5811 {
5812 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5813 continue;
5814
5815 s390_end_pool (curr_pool, NULL_RTX);
5816 curr_pool = NULL;
5817 }
5818 else
5819 {
5820 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5821 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5822 + extra_size;
5823
5824 /* We will later have to insert base register reload insns.
5825 Those will have an effect on code size, which we need to
5826 consider here. This calculation makes rather pessimistic
5827 worst-case assumptions. */
5828 if (GET_CODE (insn) == CODE_LABEL)
5829 extra_size += 6;
5830
5831 if (chunk_size < S390_POOL_CHUNK_MIN
5832 && curr_pool->size < S390_POOL_CHUNK_MIN)
5833 continue;
5834
5835 /* Pool chunks can only be inserted after BARRIERs ... */
5836 if (GET_CODE (insn) == BARRIER)
5837 {
5838 s390_end_pool (curr_pool, insn);
5839 curr_pool = NULL;
5840 extra_size = 0;
5841 }
5842
5843 /* ... so if we don't find one in time, create one. */
5844 else if ((chunk_size > S390_POOL_CHUNK_MAX
5845 || curr_pool->size > S390_POOL_CHUNK_MAX))
5846 {
5847 rtx label, jump, barrier;
5848
5849 /* We can insert the barrier only after a 'real' insn. */
5850 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5851 continue;
5852 if (get_attr_length (insn) == 0)
5853 continue;
5854
5855 /* Don't separate LTREL_BASE from the corresponding
5856 LTREL_OFFSET load. */
5857 if (pending_ltrel)
5858 continue;
5859
5860 label = gen_label_rtx ();
5861 jump = emit_jump_insn_after (gen_jump (label), insn);
5862 barrier = emit_barrier_after (jump);
5863 insn = emit_label_after (label, barrier);
5864 JUMP_LABEL (jump) = label;
5865 LABEL_NUSES (label) = 1;
5866
5867 INSN_ADDRESSES_NEW (jump, -1);
5868 INSN_ADDRESSES_NEW (barrier, -1);
5869 INSN_ADDRESSES_NEW (insn, -1);
5870
5871 s390_end_pool (curr_pool, barrier);
5872 curr_pool = NULL;
5873 extra_size = 0;
5874 }
5875 }
5876 }
5877
5878 if (curr_pool)
5879 s390_end_pool (curr_pool, NULL_RTX);
5880 gcc_assert (!pending_ltrel);
5881
5882 /* Find all labels that are branched into
5883 from an insn belonging to a different chunk. */
5884
5885 far_labels = BITMAP_ALLOC (NULL);
5886
5887 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5888 {
5889 /* Labels marked with LABEL_PRESERVE_P can be target
5890 of non-local jumps, so we have to mark them.
5891 The same holds for named labels.
5892
5893 Don't do that, however, if it is the label before
5894 a jump table. */
5895
5896 if (GET_CODE (insn) == CODE_LABEL
5897 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5898 {
5899 rtx vec_insn = next_real_insn (insn);
5900 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5901 PATTERN (vec_insn) : NULL_RTX;
5902 if (!vec_pat
5903 || !(GET_CODE (vec_pat) == ADDR_VEC
5904 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5905 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
5906 }
5907
5908 /* If we have a direct jump (conditional or unconditional)
5909 or a casesi jump, check all potential targets. */
5910 else if (GET_CODE (insn) == JUMP_INSN)
5911 {
5912 rtx pat = PATTERN (insn);
5913 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5914 pat = XVECEXP (pat, 0, 0);
5915
5916 if (GET_CODE (pat) == SET)
5917 {
5918 rtx label = JUMP_LABEL (insn);
5919 if (label)
5920 {
5921 if (s390_find_pool (pool_list, label)
5922 != s390_find_pool (pool_list, insn))
5923 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5924 }
5925 }
5926 else if (GET_CODE (pat) == PARALLEL
5927 && XVECLEN (pat, 0) == 2
5928 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
5929 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
5930 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
5931 {
5932 /* Find the jump table used by this casesi jump. */
5933 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
5934 rtx vec_insn = next_real_insn (vec_label);
5935 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5936 PATTERN (vec_insn) : NULL_RTX;
5937 if (vec_pat
5938 && (GET_CODE (vec_pat) == ADDR_VEC
5939 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5940 {
5941 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
5942
5943 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
5944 {
5945 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
5946
5947 if (s390_find_pool (pool_list, label)
5948 != s390_find_pool (pool_list, insn))
5949 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5950 }
5951 }
5952 }
5953 }
5954 }
5955
5956 /* Insert base register reload insns before every pool. */
5957
5958 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5959 {
5960 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5961 curr_pool->label);
5962 rtx insn = curr_pool->first_insn;
5963 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
5964 }
5965
5966 /* Insert base register reload insns at every far label. */
5967
5968 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5969 if (GET_CODE (insn) == CODE_LABEL
5970 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
5971 {
5972 struct constant_pool *pool = s390_find_pool (pool_list, insn);
5973 if (pool)
5974 {
5975 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5976 pool->label);
5977 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
5978 }
5979 }
5980
5981
5982 BITMAP_FREE (far_labels);
5983
5984
5985 /* Recompute insn addresses. */
5986
5987 init_insn_lengths ();
5988 shorten_branches (get_insns ());
5989
5990 return pool_list;
5991 }
5992
5993 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
5994 After we have decided to use this list, finish implementing
5995 all changes to the current function as required. */
5996
5997 static void
5998 s390_chunkify_finish (struct constant_pool *pool_list)
5999 {
6000 struct constant_pool *curr_pool = NULL;
6001 rtx insn;
6002
6003
6004 /* Replace all literal pool references. */
6005
6006 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6007 {
6008 if (INSN_P (insn))
6009 replace_ltrel_base (&PATTERN (insn));
6010
6011 curr_pool = s390_find_pool (pool_list, insn);
6012 if (!curr_pool)
6013 continue;
6014
6015 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6016 {
6017 rtx addr, pool_ref = NULL_RTX;
6018 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6019 if (pool_ref)
6020 {
6021 if (s390_execute_label (insn))
6022 addr = s390_find_execute (curr_pool, insn);
6023 else
6024 addr = s390_find_constant (curr_pool,
6025 get_pool_constant (pool_ref),
6026 get_pool_mode (pool_ref));
6027
6028 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6029 INSN_CODE (insn) = -1;
6030 }
6031 }
6032 }
6033
6034 /* Dump out all literal pools. */
6035
6036 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6037 s390_dump_pool (curr_pool, 0);
6038
6039 /* Free pool list. */
6040
6041 while (pool_list)
6042 {
6043 struct constant_pool *next = pool_list->next;
6044 s390_free_pool (pool_list);
6045 pool_list = next;
6046 }
6047 }
6048
6049 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6050 We have decided we cannot use this list, so revert all changes
6051 to the current function that were done by s390_chunkify_start. */
6052
6053 static void
6054 s390_chunkify_cancel (struct constant_pool *pool_list)
6055 {
6056 struct constant_pool *curr_pool = NULL;
6057 rtx insn;
6058
6059 /* Remove all pool placeholder insns. */
6060
6061 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6062 {
6063 /* Did we insert an extra barrier? Remove it. */
6064 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6065 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6066 rtx label = NEXT_INSN (curr_pool->pool_insn);
6067
6068 if (jump && GET_CODE (jump) == JUMP_INSN
6069 && barrier && GET_CODE (barrier) == BARRIER
6070 && label && GET_CODE (label) == CODE_LABEL
6071 && GET_CODE (PATTERN (jump)) == SET
6072 && SET_DEST (PATTERN (jump)) == pc_rtx
6073 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6074 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6075 {
6076 remove_insn (jump);
6077 remove_insn (barrier);
6078 remove_insn (label);
6079 }
6080
6081 remove_insn (curr_pool->pool_insn);
6082 }
6083
6084 /* Remove all base register reload insns. */
6085
6086 for (insn = get_insns (); insn; )
6087 {
6088 rtx next_insn = NEXT_INSN (insn);
6089
6090 if (GET_CODE (insn) == INSN
6091 && GET_CODE (PATTERN (insn)) == SET
6092 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6093 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6094 remove_insn (insn);
6095
6096 insn = next_insn;
6097 }
6098
6099 /* Free pool list. */
6100
6101 while (pool_list)
6102 {
6103 struct constant_pool *next = pool_list->next;
6104 s390_free_pool (pool_list);
6105 pool_list = next;
6106 }
6107 }
6108
6109
6110 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6111
6112 void
6113 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6114 {
6115 REAL_VALUE_TYPE r;
6116
6117 switch (GET_MODE_CLASS (mode))
6118 {
6119 case MODE_FLOAT:
6120 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6121
6122 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6123 assemble_real (r, mode, align);
6124 break;
6125
6126 case MODE_INT:
6127 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6128 break;
6129
6130 default:
6131 gcc_unreachable ();
6132 }
6133 }
6134
6135
6136 /* Return an RTL expression representing the value of the return address
6137 for the frame COUNT steps up from the current frame. FRAME is the
6138 frame pointer of that frame. */
6139
6140 rtx
6141 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6142 {
6143 int offset;
6144 rtx addr;
6145
6146 /* Without backchain, we fail for all but the current frame. */
6147
6148 if (!TARGET_BACKCHAIN && count > 0)
6149 return NULL_RTX;
6150
6151 /* For the current frame, we need to make sure the initial
6152 value of RETURN_REGNUM is actually saved. */
6153
6154 if (count == 0)
6155 {
6156 /* On non-z architectures branch splitting could overwrite r14. */
6157 if (TARGET_CPU_ZARCH)
6158 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6159 else
6160 {
6161 cfun_frame_layout.save_return_addr_p = true;
6162 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6163 }
6164 }
6165
6166 if (TARGET_PACKED_STACK)
6167 offset = -2 * UNITS_PER_WORD;
6168 else
6169 offset = RETURN_REGNUM * UNITS_PER_WORD;
6170
6171 addr = plus_constant (frame, offset);
6172 addr = memory_address (Pmode, addr);
6173 return gen_rtx_MEM (Pmode, addr);
6174 }
6175
6176 /* Return an RTL expression representing the back chain stored in
6177 the current stack frame. */
6178
6179 rtx
6180 s390_back_chain_rtx (void)
6181 {
6182 rtx chain;
6183
6184 gcc_assert (TARGET_BACKCHAIN);
6185
6186 if (TARGET_PACKED_STACK)
6187 chain = plus_constant (stack_pointer_rtx,
6188 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6189 else
6190 chain = stack_pointer_rtx;
6191
6192 chain = gen_rtx_MEM (Pmode, chain);
6193 return chain;
6194 }
6195
6196 /* Find first call clobbered register unused in a function.
6197 This could be used as base register in a leaf function
6198 or for holding the return address before epilogue. */
6199
6200 static int
6201 find_unused_clobbered_reg (void)
6202 {
6203 int i;
6204 for (i = 0; i < 6; i++)
6205 if (!regs_ever_live[i])
6206 return i;
6207 return 0;
6208 }
6209
6210
6211 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6212 clobbered hard regs in SETREG. */
6213
6214 static void
6215 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6216 {
6217 int *regs_ever_clobbered = (int *)data;
6218 unsigned int i, regno;
6219 enum machine_mode mode = GET_MODE (setreg);
6220
6221 if (GET_CODE (setreg) == SUBREG)
6222 {
6223 rtx inner = SUBREG_REG (setreg);
6224 if (!GENERAL_REG_P (inner))
6225 return;
6226 regno = subreg_regno (setreg);
6227 }
6228 else if (GENERAL_REG_P (setreg))
6229 regno = REGNO (setreg);
6230 else
6231 return;
6232
6233 for (i = regno;
6234 i < regno + HARD_REGNO_NREGS (regno, mode);
6235 i++)
6236 regs_ever_clobbered[i] = 1;
6237 }
6238
6239 /* Walks through all basic blocks of the current function looking
6240 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6241 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6242 each of those regs. */
6243
6244 static void
6245 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6246 {
6247 basic_block cur_bb;
6248 rtx cur_insn;
6249 unsigned int i;
6250
6251 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6252
6253 /* For non-leaf functions we have to consider all call clobbered regs to be
6254 clobbered. */
6255 if (!current_function_is_leaf)
6256 {
6257 for (i = 0; i < 16; i++)
6258 regs_ever_clobbered[i] = call_really_used_regs[i];
6259 }
6260
6261 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6262 this work is done by liveness analysis (mark_regs_live_at_end).
6263 Special care is needed for functions containing landing pads. Landing pads
6264 may use the eh registers, but the code which sets these registers is not
6265 contained in that function. Hence s390_regs_ever_clobbered is not able to
6266 deal with this automatically. */
6267 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6268 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6269 if (current_function_calls_eh_return
6270 || (cfun->machine->has_landing_pad_p
6271 && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6272 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6273
6274 /* For nonlocal gotos all call-saved registers have to be saved.
6275 This flag is also set for the unwinding code in libgcc.
6276 See expand_builtin_unwind_init. For regs_ever_live this is done by
6277 reload. */
6278 if (current_function_has_nonlocal_label)
6279 for (i = 0; i < 16; i++)
6280 if (!call_really_used_regs[i])
6281 regs_ever_clobbered[i] = 1;
6282
6283 FOR_EACH_BB (cur_bb)
6284 {
6285 FOR_BB_INSNS (cur_bb, cur_insn)
6286 {
6287 if (INSN_P (cur_insn))
6288 note_stores (PATTERN (cur_insn),
6289 s390_reg_clobbered_rtx,
6290 regs_ever_clobbered);
6291 }
6292 }
6293 }
6294
6295 /* Determine the frame area which actually has to be accessed
6296 in the function epilogue. The values are stored at the
6297 given pointers AREA_BOTTOM (address of the lowest used stack
6298 address) and AREA_TOP (address of the first item which does
6299 not belong to the stack frame). */
6300
6301 static void
6302 s390_frame_area (int *area_bottom, int *area_top)
6303 {
6304 int b, t;
6305 int i;
6306
6307 b = INT_MAX;
6308 t = INT_MIN;
6309
6310 if (cfun_frame_layout.first_restore_gpr != -1)
6311 {
6312 b = (cfun_frame_layout.gprs_offset
6313 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6314 t = b + (cfun_frame_layout.last_restore_gpr
6315 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6316 }
6317
6318 if (TARGET_64BIT && cfun_save_high_fprs_p)
6319 {
6320 b = MIN (b, cfun_frame_layout.f8_offset);
6321 t = MAX (t, (cfun_frame_layout.f8_offset
6322 + cfun_frame_layout.high_fprs * 8));
6323 }
6324
6325 if (!TARGET_64BIT)
6326 for (i = 2; i < 4; i++)
6327 if (cfun_fpr_bit_p (i))
6328 {
6329 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6330 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6331 }
6332
6333 *area_bottom = b;
6334 *area_top = t;
6335 }
6336
6337 /* Fill cfun->machine with info about register usage of current function.
6338 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6339
6340 static void
6341 s390_register_info (int clobbered_regs[])
6342 {
6343 int i, j;
6344
6345 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6346 cfun_frame_layout.fpr_bitmap = 0;
6347 cfun_frame_layout.high_fprs = 0;
6348 if (TARGET_64BIT)
6349 for (i = 24; i < 32; i++)
6350 if (regs_ever_live[i] && !global_regs[i])
6351 {
6352 cfun_set_fpr_bit (i - 16);
6353 cfun_frame_layout.high_fprs++;
6354 }
6355
6356 /* Find first and last gpr to be saved. We trust regs_ever_live
6357 data, except that we don't save and restore global registers.
6358
6359 Also, all registers with special meaning to the compiler need
6360 to be handled extra. */
6361
6362 s390_regs_ever_clobbered (clobbered_regs);
6363
6364 for (i = 0; i < 16; i++)
6365 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6366
6367 if (frame_pointer_needed)
6368 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6369
6370 if (flag_pic)
6371 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6372 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6373
6374 clobbered_regs[BASE_REGNUM]
6375 |= (cfun->machine->base_reg
6376 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6377
6378 clobbered_regs[RETURN_REGNUM]
6379 |= (!current_function_is_leaf
6380 || TARGET_TPF_PROFILING
6381 || cfun->machine->split_branches_pending_p
6382 || cfun_frame_layout.save_return_addr_p
6383 || current_function_calls_eh_return
6384 || current_function_stdarg);
6385
6386 clobbered_regs[STACK_POINTER_REGNUM]
6387 |= (!current_function_is_leaf
6388 || TARGET_TPF_PROFILING
6389 || cfun_save_high_fprs_p
6390 || get_frame_size () > 0
6391 || current_function_calls_alloca
6392 || current_function_stdarg);
6393
6394 for (i = 6; i < 16; i++)
6395 if (regs_ever_live[i] || clobbered_regs[i])
6396 break;
6397 for (j = 15; j > i; j--)
6398 if (regs_ever_live[j] || clobbered_regs[j])
6399 break;
6400
6401 if (i == 16)
6402 {
6403 /* Nothing to save/restore. */
6404 cfun_frame_layout.first_save_gpr_slot = -1;
6405 cfun_frame_layout.last_save_gpr_slot = -1;
6406 cfun_frame_layout.first_save_gpr = -1;
6407 cfun_frame_layout.first_restore_gpr = -1;
6408 cfun_frame_layout.last_save_gpr = -1;
6409 cfun_frame_layout.last_restore_gpr = -1;
6410 }
6411 else
6412 {
6413 /* Save slots for gprs from i to j. */
6414 cfun_frame_layout.first_save_gpr_slot = i;
6415 cfun_frame_layout.last_save_gpr_slot = j;
6416
6417 for (i = cfun_frame_layout.first_save_gpr_slot;
6418 i < cfun_frame_layout.last_save_gpr_slot + 1;
6419 i++)
6420 if (clobbered_regs[i])
6421 break;
6422
6423 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6424 if (clobbered_regs[j])
6425 break;
6426
6427 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6428 {
6429 /* Nothing to save/restore. */
6430 cfun_frame_layout.first_save_gpr = -1;
6431 cfun_frame_layout.first_restore_gpr = -1;
6432 cfun_frame_layout.last_save_gpr = -1;
6433 cfun_frame_layout.last_restore_gpr = -1;
6434 }
6435 else
6436 {
6437 /* Save / Restore from gpr i to j. */
6438 cfun_frame_layout.first_save_gpr = i;
6439 cfun_frame_layout.first_restore_gpr = i;
6440 cfun_frame_layout.last_save_gpr = j;
6441 cfun_frame_layout.last_restore_gpr = j;
6442 }
6443 }
6444
6445 if (current_function_stdarg)
6446 {
6447 /* Varargs functions need to save gprs 2 to 6. */
6448 if (cfun->va_list_gpr_size
6449 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6450 {
6451 int min_gpr = current_function_args_info.gprs;
6452 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6453 if (max_gpr > GP_ARG_NUM_REG)
6454 max_gpr = GP_ARG_NUM_REG;
6455
6456 if (cfun_frame_layout.first_save_gpr == -1
6457 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6458 {
6459 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6460 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6461 }
6462
6463 if (cfun_frame_layout.last_save_gpr == -1
6464 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6465 {
6466 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6467 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6468 }
6469 }
6470
6471 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6472 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6473 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6474 {
6475 int min_fpr = current_function_args_info.fprs;
6476 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6477 if (max_fpr > FP_ARG_NUM_REG)
6478 max_fpr = FP_ARG_NUM_REG;
6479
6480 /* ??? This is currently required to ensure proper location
6481 of the fpr save slots within the va_list save area. */
6482 if (TARGET_PACKED_STACK)
6483 min_fpr = 0;
6484
6485 for (i = min_fpr; i < max_fpr; i++)
6486 cfun_set_fpr_bit (i);
6487 }
6488 }
6489
6490 if (!TARGET_64BIT)
6491 for (i = 2; i < 4; i++)
6492 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6493 cfun_set_fpr_bit (i);
6494 }
6495
6496 /* Fill cfun->machine with info about frame of current function. */
6497
6498 static void
6499 s390_frame_info (void)
6500 {
6501 int i;
6502
6503 cfun_frame_layout.frame_size = get_frame_size ();
6504 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6505 fatal_error ("total size of local variables exceeds architecture limit");
6506
6507 if (!TARGET_PACKED_STACK)
6508 {
6509 cfun_frame_layout.backchain_offset = 0;
6510 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6511 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6512 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6513 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6514 * UNITS_PER_WORD);
6515 }
6516 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6517 {
6518 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6519 - UNITS_PER_WORD);
6520 cfun_frame_layout.gprs_offset
6521 = (cfun_frame_layout.backchain_offset
6522 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6523 * UNITS_PER_WORD);
6524
6525 if (TARGET_64BIT)
6526 {
6527 cfun_frame_layout.f4_offset
6528 = (cfun_frame_layout.gprs_offset
6529 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6530
6531 cfun_frame_layout.f0_offset
6532 = (cfun_frame_layout.f4_offset
6533 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6534 }
6535 else
6536 {
6537 /* On 31 bit we have to care about alignment of the
6538 floating point regs to provide fastest access. */
6539 cfun_frame_layout.f0_offset
6540 = ((cfun_frame_layout.gprs_offset
6541 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6542 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6543
6544 cfun_frame_layout.f4_offset
6545 = (cfun_frame_layout.f0_offset
6546 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6547 }
6548 }
6549 else /* no backchain */
6550 {
6551 cfun_frame_layout.f4_offset
6552 = (STACK_POINTER_OFFSET
6553 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6554
6555 cfun_frame_layout.f0_offset
6556 = (cfun_frame_layout.f4_offset
6557 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6558
6559 cfun_frame_layout.gprs_offset
6560 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6561 }
6562
6563 if (current_function_is_leaf
6564 && !TARGET_TPF_PROFILING
6565 && cfun_frame_layout.frame_size == 0
6566 && !cfun_save_high_fprs_p
6567 && !current_function_calls_alloca
6568 && !current_function_stdarg)
6569 return;
6570
6571 if (!TARGET_PACKED_STACK)
6572 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6573 + current_function_outgoing_args_size
6574 + cfun_frame_layout.high_fprs * 8);
6575 else
6576 {
6577 if (TARGET_BACKCHAIN)
6578 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6579
6580 /* No alignment trouble here because f8-f15 are only saved under
6581 64 bit. */
6582 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6583 cfun_frame_layout.f4_offset),
6584 cfun_frame_layout.gprs_offset)
6585 - cfun_frame_layout.high_fprs * 8);
6586
6587 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6588
6589 for (i = 0; i < 8; i++)
6590 if (cfun_fpr_bit_p (i))
6591 cfun_frame_layout.frame_size += 8;
6592
6593 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6594
6595 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6596 the frame size to sustain 8 byte alignment of stack frames. */
6597 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6598 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6599 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6600
6601 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6602 }
6603 }
6604
6605 /* Generate frame layout. Fills in register and frame data for the current
6606 function in cfun->machine. This routine can be called multiple times;
6607 it will re-do the complete frame layout every time. */
6608
6609 static void
6610 s390_init_frame_layout (void)
6611 {
6612 HOST_WIDE_INT frame_size;
6613 int base_used;
6614 int clobbered_regs[16];
6615
6616 /* On S/390 machines, we may need to perform branch splitting, which
6617 will require both base and return address register. We have no
6618 choice but to assume we're going to need them until right at the
6619 end of the machine dependent reorg phase. */
6620 if (!TARGET_CPU_ZARCH)
6621 cfun->machine->split_branches_pending_p = true;
6622
6623 do
6624 {
6625 frame_size = cfun_frame_layout.frame_size;
6626
6627 /* Try to predict whether we'll need the base register. */
6628 base_used = cfun->machine->split_branches_pending_p
6629 || current_function_uses_const_pool
6630 || (!DISP_IN_RANGE (-frame_size)
6631 && !CONST_OK_FOR_K (-frame_size));
6632
6633 /* Decide which register to use as literal pool base. In small
6634 leaf functions, try to use an unused call-clobbered register
6635 as base register to avoid save/restore overhead. */
6636 if (!base_used)
6637 cfun->machine->base_reg = NULL_RTX;
6638 else if (current_function_is_leaf && !regs_ever_live[5])
6639 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6640 else
6641 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6642
6643 s390_register_info (clobbered_regs);
6644 s390_frame_info ();
6645 }
6646 while (frame_size != cfun_frame_layout.frame_size);
6647 }
6648
6649 /* Update frame layout. Recompute actual register save data based on
6650 current info and update regs_ever_live for the special registers.
6651 May be called multiple times, but may never cause *more* registers
6652 to be saved than s390_init_frame_layout allocated room for. */
6653
6654 static void
6655 s390_update_frame_layout (void)
6656 {
6657 int clobbered_regs[16];
6658
6659 s390_register_info (clobbered_regs);
6660
6661 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6662 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6663 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6664
6665 if (cfun->machine->base_reg)
6666 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6667 }
6668
6669 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6670
6671 bool
6672 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6673 {
6674 /* Once we've decided upon a register to use as base register, it must
6675 no longer be used for any other purpose. */
6676 if (cfun->machine->base_reg)
6677 if (REGNO (cfun->machine->base_reg) == old_reg
6678 || REGNO (cfun->machine->base_reg) == new_reg)
6679 return false;
6680
6681 return true;
6682 }
6683
6684 /* Return true if register FROM can be eliminated via register TO. */
6685
6686 bool
6687 s390_can_eliminate (int from, int to)
6688 {
6689 /* On zSeries machines, we have not marked the base register as fixed.
6690 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6691 If a function requires the base register, we say here that this
6692 elimination cannot be performed. This will cause reload to free
6693 up the base register (as if it were fixed). On the other hand,
6694 if the current function does *not* require the base register, we
6695 say here the elimination succeeds, which in turn allows reload
6696 to allocate the base register for any other purpose. */
6697 if (from == BASE_REGNUM && to == BASE_REGNUM)
6698 {
6699 if (TARGET_CPU_ZARCH)
6700 {
6701 s390_init_frame_layout ();
6702 return cfun->machine->base_reg == NULL_RTX;
6703 }
6704
6705 return false;
6706 }
6707
6708 /* Everything else must point into the stack frame. */
6709 gcc_assert (to == STACK_POINTER_REGNUM
6710 || to == HARD_FRAME_POINTER_REGNUM);
6711
6712 gcc_assert (from == FRAME_POINTER_REGNUM
6713 || from == ARG_POINTER_REGNUM
6714 || from == RETURN_ADDRESS_POINTER_REGNUM);
6715
6716 /* Make sure we actually saved the return address. */
6717 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6718 if (!current_function_calls_eh_return
6719 && !current_function_stdarg
6720 && !cfun_frame_layout.save_return_addr_p)
6721 return false;
6722
6723 return true;
6724 }
6725
6726 /* Return offset between register FROM and TO initially after prolog. */
6727
6728 HOST_WIDE_INT
6729 s390_initial_elimination_offset (int from, int to)
6730 {
6731 HOST_WIDE_INT offset;
6732 int index;
6733
6734 /* ??? Why are we called for non-eliminable pairs? */
6735 if (!s390_can_eliminate (from, to))
6736 return 0;
6737
6738 switch (from)
6739 {
6740 case FRAME_POINTER_REGNUM:
6741 offset = (get_frame_size()
6742 + STACK_POINTER_OFFSET
6743 + current_function_outgoing_args_size);
6744 break;
6745
6746 case ARG_POINTER_REGNUM:
6747 s390_init_frame_layout ();
6748 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6749 break;
6750
6751 case RETURN_ADDRESS_POINTER_REGNUM:
6752 s390_init_frame_layout ();
6753 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6754 gcc_assert (index >= 0);
6755 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6756 offset += index * UNITS_PER_WORD;
6757 break;
6758
6759 case BASE_REGNUM:
6760 offset = 0;
6761 break;
6762
6763 default:
6764 gcc_unreachable ();
6765 }
6766
6767 return offset;
6768 }
6769
6770 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6771 to register BASE. Return generated insn. */
6772
6773 static rtx
6774 save_fpr (rtx base, int offset, int regnum)
6775 {
6776 rtx addr;
6777 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6778
6779 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6780 set_mem_alias_set (addr, get_varargs_alias_set ());
6781 else
6782 set_mem_alias_set (addr, get_frame_alias_set ());
6783
6784 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6785 }
6786
6787 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6788 to register BASE. Return generated insn. */
6789
6790 static rtx
6791 restore_fpr (rtx base, int offset, int regnum)
6792 {
6793 rtx addr;
6794 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6795 set_mem_alias_set (addr, get_frame_alias_set ());
6796
6797 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6798 }
6799
6800 /* Generate insn to save registers FIRST to LAST into
6801 the register save area located at offset OFFSET
6802 relative to register BASE. */
6803
6804 static rtx
6805 save_gprs (rtx base, int offset, int first, int last)
6806 {
6807 rtx addr, insn, note;
6808 int i;
6809
6810 addr = plus_constant (base, offset);
6811 addr = gen_rtx_MEM (Pmode, addr);
6812
6813 set_mem_alias_set (addr, get_frame_alias_set ());
6814
6815 /* Special-case single register. */
6816 if (first == last)
6817 {
6818 if (TARGET_64BIT)
6819 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6820 else
6821 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6822
6823 RTX_FRAME_RELATED_P (insn) = 1;
6824 return insn;
6825 }
6826
6827
6828 insn = gen_store_multiple (addr,
6829 gen_rtx_REG (Pmode, first),
6830 GEN_INT (last - first + 1));
6831
6832 if (first <= 6 && current_function_stdarg)
6833 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6834 {
6835 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
6836
6837 if (first + i <= 6)
6838 set_mem_alias_set (mem, get_varargs_alias_set ());
6839 }
6840
6841 /* We need to set the FRAME_RELATED flag on all SETs
6842 inside the store-multiple pattern.
6843
6844 However, we must not emit DWARF records for registers 2..5
6845 if they are stored for use by variable arguments ...
6846
6847 ??? Unfortunately, it is not enough to simply not the
6848 FRAME_RELATED flags for those SETs, because the first SET
6849 of the PARALLEL is always treated as if it had the flag
6850 set, even if it does not. Therefore we emit a new pattern
6851 without those registers as REG_FRAME_RELATED_EXPR note. */
6852
6853 if (first >= 6)
6854 {
6855 rtx pat = PATTERN (insn);
6856
6857 for (i = 0; i < XVECLEN (pat, 0); i++)
6858 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
6859 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
6860
6861 RTX_FRAME_RELATED_P (insn) = 1;
6862 }
6863 else if (last >= 6)
6864 {
6865 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
6866 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
6867 gen_rtx_REG (Pmode, 6),
6868 GEN_INT (last - 6 + 1));
6869 note = PATTERN (note);
6870
6871 REG_NOTES (insn) =
6872 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6873 note, REG_NOTES (insn));
6874
6875 for (i = 0; i < XVECLEN (note, 0); i++)
6876 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
6877 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
6878
6879 RTX_FRAME_RELATED_P (insn) = 1;
6880 }
6881
6882 return insn;
6883 }
6884
6885 /* Generate insn to restore registers FIRST to LAST from
6886 the register save area located at offset OFFSET
6887 relative to register BASE. */
6888
6889 static rtx
6890 restore_gprs (rtx base, int offset, int first, int last)
6891 {
6892 rtx addr, insn;
6893
6894 addr = plus_constant (base, offset);
6895 addr = gen_rtx_MEM (Pmode, addr);
6896 set_mem_alias_set (addr, get_frame_alias_set ());
6897
6898 /* Special-case single register. */
6899 if (first == last)
6900 {
6901 if (TARGET_64BIT)
6902 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
6903 else
6904 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
6905
6906 return insn;
6907 }
6908
6909 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
6910 addr,
6911 GEN_INT (last - first + 1));
6912 return insn;
6913 }
6914
6915 /* Return insn sequence to load the GOT register. */
6916
6917 static GTY(()) rtx got_symbol;
6918 rtx
6919 s390_load_got (void)
6920 {
6921 rtx insns;
6922
6923 if (!got_symbol)
6924 {
6925 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
6926 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
6927 }
6928
6929 start_sequence ();
6930
6931 if (TARGET_CPU_ZARCH)
6932 {
6933 emit_move_insn (pic_offset_table_rtx, got_symbol);
6934 }
6935 else
6936 {
6937 rtx offset;
6938
6939 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
6940 UNSPEC_LTREL_OFFSET);
6941 offset = gen_rtx_CONST (Pmode, offset);
6942 offset = force_const_mem (Pmode, offset);
6943
6944 emit_move_insn (pic_offset_table_rtx, offset);
6945
6946 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
6947 UNSPEC_LTREL_BASE);
6948 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
6949
6950 emit_move_insn (pic_offset_table_rtx, offset);
6951 }
6952
6953 insns = get_insns ();
6954 end_sequence ();
6955 return insns;
6956 }
6957
6958 /* Expand the prologue into a bunch of separate insns. */
6959
6960 void
6961 s390_emit_prologue (void)
6962 {
6963 rtx insn, addr;
6964 rtx temp_reg;
6965 int i;
6966 int offset;
6967 int next_fpr = 0;
6968
6969 /* Complete frame layout. */
6970
6971 s390_update_frame_layout ();
6972
6973 /* Annotate all constant pool references to let the scheduler know
6974 they implicitly use the base register. */
6975
6976 push_topmost_sequence ();
6977
6978 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6979 if (INSN_P (insn))
6980 annotate_constant_pool_refs (&PATTERN (insn));
6981
6982 pop_topmost_sequence ();
6983
6984 /* Choose best register to use for temp use within prologue.
6985 See below for why TPF must use the register 1. */
6986
6987 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
6988 && !current_function_is_leaf
6989 && !TARGET_TPF_PROFILING)
6990 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6991 else
6992 temp_reg = gen_rtx_REG (Pmode, 1);
6993
6994 /* Save call saved gprs. */
6995 if (cfun_frame_layout.first_save_gpr != -1)
6996 {
6997 insn = save_gprs (stack_pointer_rtx,
6998 cfun_frame_layout.gprs_offset +
6999 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7000 - cfun_frame_layout.first_save_gpr_slot),
7001 cfun_frame_layout.first_save_gpr,
7002 cfun_frame_layout.last_save_gpr);
7003 emit_insn (insn);
7004 }
7005
7006 /* Dummy insn to mark literal pool slot. */
7007
7008 if (cfun->machine->base_reg)
7009 emit_insn (gen_main_pool (cfun->machine->base_reg));
7010
7011 offset = cfun_frame_layout.f0_offset;
7012
7013 /* Save f0 and f2. */
7014 for (i = 0; i < 2; i++)
7015 {
7016 if (cfun_fpr_bit_p (i))
7017 {
7018 save_fpr (stack_pointer_rtx, offset, i + 16);
7019 offset += 8;
7020 }
7021 else if (!TARGET_PACKED_STACK)
7022 offset += 8;
7023 }
7024
7025 /* Save f4 and f6. */
7026 offset = cfun_frame_layout.f4_offset;
7027 for (i = 2; i < 4; i++)
7028 {
7029 if (cfun_fpr_bit_p (i))
7030 {
7031 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7032 offset += 8;
7033
7034 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7035 therefore are not frame related. */
7036 if (!call_really_used_regs[i + 16])
7037 RTX_FRAME_RELATED_P (insn) = 1;
7038 }
7039 else if (!TARGET_PACKED_STACK)
7040 offset += 8;
7041 }
7042
7043 if (TARGET_PACKED_STACK
7044 && cfun_save_high_fprs_p
7045 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7046 {
7047 offset = (cfun_frame_layout.f8_offset
7048 + (cfun_frame_layout.high_fprs - 1) * 8);
7049
7050 for (i = 15; i > 7 && offset >= 0; i--)
7051 if (cfun_fpr_bit_p (i))
7052 {
7053 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7054
7055 RTX_FRAME_RELATED_P (insn) = 1;
7056 offset -= 8;
7057 }
7058 if (offset >= cfun_frame_layout.f8_offset)
7059 next_fpr = i + 16;
7060 }
7061
7062 if (!TARGET_PACKED_STACK)
7063 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7064
7065 /* Decrement stack pointer. */
7066
7067 if (cfun_frame_layout.frame_size > 0)
7068 {
7069 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7070
7071 if (s390_stack_size)
7072 {
7073 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7074 & ~(s390_stack_guard - 1));
7075 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7076 GEN_INT (stack_check_mask));
7077
7078 if (TARGET_64BIT)
7079 gen_cmpdi (t, const0_rtx);
7080 else
7081 gen_cmpsi (t, const0_rtx);
7082
7083 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7084 gen_rtx_REG (CCmode,
7085 CC_REGNUM),
7086 const0_rtx),
7087 const0_rtx));
7088 }
7089
7090 if (s390_warn_framesize > 0
7091 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7092 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7093 current_function_name (), cfun_frame_layout.frame_size);
7094
7095 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7096 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7097
7098 /* Save incoming stack pointer into temp reg. */
7099 if (TARGET_BACKCHAIN || next_fpr)
7100 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7101
7102 /* Subtract frame size from stack pointer. */
7103
7104 if (DISP_IN_RANGE (INTVAL (frame_off)))
7105 {
7106 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7107 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7108 frame_off));
7109 insn = emit_insn (insn);
7110 }
7111 else
7112 {
7113 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7114 frame_off = force_const_mem (Pmode, frame_off);
7115
7116 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7117 annotate_constant_pool_refs (&PATTERN (insn));
7118 }
7119
7120 RTX_FRAME_RELATED_P (insn) = 1;
7121 REG_NOTES (insn) =
7122 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7123 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7124 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7125 GEN_INT (-cfun_frame_layout.frame_size))),
7126 REG_NOTES (insn));
7127
7128 /* Set backchain. */
7129
7130 if (TARGET_BACKCHAIN)
7131 {
7132 if (cfun_frame_layout.backchain_offset)
7133 addr = gen_rtx_MEM (Pmode,
7134 plus_constant (stack_pointer_rtx,
7135 cfun_frame_layout.backchain_offset));
7136 else
7137 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7138 set_mem_alias_set (addr, get_frame_alias_set ());
7139 insn = emit_insn (gen_move_insn (addr, temp_reg));
7140 }
7141
7142 /* If we support asynchronous exceptions (e.g. for Java),
7143 we need to make sure the backchain pointer is set up
7144 before any possibly trapping memory access. */
7145
7146 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7147 {
7148 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7149 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7150 }
7151 }
7152
7153 /* Save fprs 8 - 15 (64 bit ABI). */
7154
7155 if (cfun_save_high_fprs_p && next_fpr)
7156 {
7157 insn = emit_insn (gen_add2_insn (temp_reg,
7158 GEN_INT (cfun_frame_layout.f8_offset)));
7159
7160 offset = 0;
7161
7162 for (i = 24; i <= next_fpr; i++)
7163 if (cfun_fpr_bit_p (i - 16))
7164 {
7165 rtx addr = plus_constant (stack_pointer_rtx,
7166 cfun_frame_layout.frame_size
7167 + cfun_frame_layout.f8_offset
7168 + offset);
7169
7170 insn = save_fpr (temp_reg, offset, i);
7171 offset += 8;
7172 RTX_FRAME_RELATED_P (insn) = 1;
7173 REG_NOTES (insn) =
7174 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7175 gen_rtx_SET (VOIDmode,
7176 gen_rtx_MEM (DFmode, addr),
7177 gen_rtx_REG (DFmode, i)),
7178 REG_NOTES (insn));
7179 }
7180 }
7181
7182 /* Set frame pointer, if needed. */
7183
7184 if (frame_pointer_needed)
7185 {
7186 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7187 RTX_FRAME_RELATED_P (insn) = 1;
7188 }
7189
7190 /* Set up got pointer, if needed. */
7191
7192 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7193 {
7194 rtx insns = s390_load_got ();
7195
7196 for (insn = insns; insn; insn = NEXT_INSN (insn))
7197 {
7198 annotate_constant_pool_refs (&PATTERN (insn));
7199
7200 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7201 REG_NOTES (insn));
7202 }
7203
7204 emit_insn (insns);
7205 }
7206
7207 if (TARGET_TPF_PROFILING)
7208 {
7209 /* Generate a BAS instruction to serve as a function
7210 entry intercept to facilitate the use of tracing
7211 algorithms located at the branch target. */
7212 emit_insn (gen_prologue_tpf ());
7213
7214 /* Emit a blockage here so that all code
7215 lies between the profiling mechanisms. */
7216 emit_insn (gen_blockage ());
7217 }
7218 }
7219
7220 /* Expand the epilogue into a bunch of separate insns. */
7221
7222 void
7223 s390_emit_epilogue (bool sibcall)
7224 {
7225 rtx frame_pointer, return_reg;
7226 int area_bottom, area_top, offset = 0;
7227 int next_offset;
7228 rtvec p;
7229 int i;
7230
7231 if (TARGET_TPF_PROFILING)
7232 {
7233
7234 /* Generate a BAS instruction to serve as a function
7235 entry intercept to facilitate the use of tracing
7236 algorithms located at the branch target. */
7237
7238 /* Emit a blockage here so that all code
7239 lies between the profiling mechanisms. */
7240 emit_insn (gen_blockage ());
7241
7242 emit_insn (gen_epilogue_tpf ());
7243 }
7244
7245 /* Check whether to use frame or stack pointer for restore. */
7246
7247 frame_pointer = (frame_pointer_needed
7248 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7249
7250 s390_frame_area (&area_bottom, &area_top);
7251
7252 /* Check whether we can access the register save area.
7253 If not, increment the frame pointer as required. */
7254
7255 if (area_top <= area_bottom)
7256 {
7257 /* Nothing to restore. */
7258 }
7259 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7260 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7261 {
7262 /* Area is in range. */
7263 offset = cfun_frame_layout.frame_size;
7264 }
7265 else
7266 {
7267 rtx insn, frame_off;
7268
7269 offset = area_bottom < 0 ? -area_bottom : 0;
7270 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7271
7272 if (DISP_IN_RANGE (INTVAL (frame_off)))
7273 {
7274 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7275 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7276 insn = emit_insn (insn);
7277 }
7278 else
7279 {
7280 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7281 frame_off = force_const_mem (Pmode, frame_off);
7282
7283 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7284 annotate_constant_pool_refs (&PATTERN (insn));
7285 }
7286 }
7287
7288 /* Restore call saved fprs. */
7289
7290 if (TARGET_64BIT)
7291 {
7292 if (cfun_save_high_fprs_p)
7293 {
7294 next_offset = cfun_frame_layout.f8_offset;
7295 for (i = 24; i < 32; i++)
7296 {
7297 if (cfun_fpr_bit_p (i - 16))
7298 {
7299 restore_fpr (frame_pointer,
7300 offset + next_offset, i);
7301 next_offset += 8;
7302 }
7303 }
7304 }
7305
7306 }
7307 else
7308 {
7309 next_offset = cfun_frame_layout.f4_offset;
7310 for (i = 18; i < 20; i++)
7311 {
7312 if (cfun_fpr_bit_p (i - 16))
7313 {
7314 restore_fpr (frame_pointer,
7315 offset + next_offset, i);
7316 next_offset += 8;
7317 }
7318 else if (!TARGET_PACKED_STACK)
7319 next_offset += 8;
7320 }
7321
7322 }
7323
7324 /* Return register. */
7325
7326 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7327
7328 /* Restore call saved gprs. */
7329
7330 if (cfun_frame_layout.first_restore_gpr != -1)
7331 {
7332 rtx insn, addr;
7333 int i;
7334
7335 /* Check for global register and save them
7336 to stack location from where they get restored. */
7337
7338 for (i = cfun_frame_layout.first_restore_gpr;
7339 i <= cfun_frame_layout.last_restore_gpr;
7340 i++)
7341 {
7342 /* These registers are special and need to be
7343 restored in any case. */
7344 if (i == STACK_POINTER_REGNUM
7345 || i == RETURN_REGNUM
7346 || i == BASE_REGNUM
7347 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7348 continue;
7349
7350 if (global_regs[i])
7351 {
7352 addr = plus_constant (frame_pointer,
7353 offset + cfun_frame_layout.gprs_offset
7354 + (i - cfun_frame_layout.first_save_gpr_slot)
7355 * UNITS_PER_WORD);
7356 addr = gen_rtx_MEM (Pmode, addr);
7357 set_mem_alias_set (addr, get_frame_alias_set ());
7358 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7359 }
7360 }
7361
7362 if (! sibcall)
7363 {
7364 /* Fetch return address from stack before load multiple,
7365 this will do good for scheduling. */
7366
7367 if (cfun_frame_layout.save_return_addr_p
7368 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7369 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7370 {
7371 int return_regnum = find_unused_clobbered_reg();
7372 if (!return_regnum)
7373 return_regnum = 4;
7374 return_reg = gen_rtx_REG (Pmode, return_regnum);
7375
7376 addr = plus_constant (frame_pointer,
7377 offset + cfun_frame_layout.gprs_offset
7378 + (RETURN_REGNUM
7379 - cfun_frame_layout.first_save_gpr_slot)
7380 * UNITS_PER_WORD);
7381 addr = gen_rtx_MEM (Pmode, addr);
7382 set_mem_alias_set (addr, get_frame_alias_set ());
7383 emit_move_insn (return_reg, addr);
7384 }
7385 }
7386
7387 insn = restore_gprs (frame_pointer,
7388 offset + cfun_frame_layout.gprs_offset
7389 + (cfun_frame_layout.first_restore_gpr
7390 - cfun_frame_layout.first_save_gpr_slot)
7391 * UNITS_PER_WORD,
7392 cfun_frame_layout.first_restore_gpr,
7393 cfun_frame_layout.last_restore_gpr);
7394 emit_insn (insn);
7395 }
7396
7397 if (! sibcall)
7398 {
7399
7400 /* Return to caller. */
7401
7402 p = rtvec_alloc (2);
7403
7404 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7405 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7406 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7407 }
7408 }
7409
7410
7411 /* Return the size in bytes of a function argument of
7412 type TYPE and/or mode MODE. At least one of TYPE or
7413 MODE must be specified. */
7414
7415 static int
7416 s390_function_arg_size (enum machine_mode mode, tree type)
7417 {
7418 if (type)
7419 return int_size_in_bytes (type);
7420
7421 /* No type info available for some library calls ... */
7422 if (mode != BLKmode)
7423 return GET_MODE_SIZE (mode);
7424
7425 /* If we have neither type nor mode, abort */
7426 gcc_unreachable ();
7427 }
7428
7429 /* Return true if a function argument of type TYPE and mode MODE
7430 is to be passed in a floating-point register, if available. */
7431
7432 static bool
7433 s390_function_arg_float (enum machine_mode mode, tree type)
7434 {
7435 int size = s390_function_arg_size (mode, type);
7436 if (size > 8)
7437 return false;
7438
7439 /* Soft-float changes the ABI: no floating-point registers are used. */
7440 if (TARGET_SOFT_FLOAT)
7441 return false;
7442
7443 /* No type info available for some library calls ... */
7444 if (!type)
7445 return mode == SFmode || mode == DFmode;
7446
7447 /* The ABI says that record types with a single member are treated
7448 just like that member would be. */
7449 while (TREE_CODE (type) == RECORD_TYPE)
7450 {
7451 tree field, single = NULL_TREE;
7452
7453 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7454 {
7455 if (TREE_CODE (field) != FIELD_DECL)
7456 continue;
7457
7458 if (single == NULL_TREE)
7459 single = TREE_TYPE (field);
7460 else
7461 return false;
7462 }
7463
7464 if (single == NULL_TREE)
7465 return false;
7466 else
7467 type = single;
7468 }
7469
7470 return TREE_CODE (type) == REAL_TYPE;
7471 }
7472
7473 /* Return true if a function argument of type TYPE and mode MODE
7474 is to be passed in an integer register, or a pair of integer
7475 registers, if available. */
7476
7477 static bool
7478 s390_function_arg_integer (enum machine_mode mode, tree type)
7479 {
7480 int size = s390_function_arg_size (mode, type);
7481 if (size > 8)
7482 return false;
7483
7484 /* No type info available for some library calls ... */
7485 if (!type)
7486 return GET_MODE_CLASS (mode) == MODE_INT
7487 || (TARGET_SOFT_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT);
7488
7489 /* We accept small integral (and similar) types. */
7490 if (INTEGRAL_TYPE_P (type)
7491 || POINTER_TYPE_P (type)
7492 || TREE_CODE (type) == OFFSET_TYPE
7493 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7494 return true;
7495
7496 /* We also accept structs of size 1, 2, 4, 8 that are not
7497 passed in floating-point registers. */
7498 if (AGGREGATE_TYPE_P (type)
7499 && exact_log2 (size) >= 0
7500 && !s390_function_arg_float (mode, type))
7501 return true;
7502
7503 return false;
7504 }
7505
7506 /* Return 1 if a function argument of type TYPE and mode MODE
7507 is to be passed by reference. The ABI specifies that only
7508 structures of size 1, 2, 4, or 8 bytes are passed by value,
7509 all other structures (and complex numbers) are passed by
7510 reference. */
7511
7512 static bool
7513 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7514 enum machine_mode mode, tree type,
7515 bool named ATTRIBUTE_UNUSED)
7516 {
7517 int size = s390_function_arg_size (mode, type);
7518 if (size > 8)
7519 return true;
7520
7521 if (type)
7522 {
7523 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7524 return 1;
7525
7526 if (TREE_CODE (type) == COMPLEX_TYPE
7527 || TREE_CODE (type) == VECTOR_TYPE)
7528 return 1;
7529 }
7530
7531 return 0;
7532 }
7533
7534 /* Update the data in CUM to advance over an argument of mode MODE and
7535 data type TYPE. (TYPE is null for libcalls where that information
7536 may not be available.). The boolean NAMED specifies whether the
7537 argument is a named argument (as opposed to an unnamed argument
7538 matching an ellipsis). */
7539
7540 void
7541 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7542 tree type, int named ATTRIBUTE_UNUSED)
7543 {
7544 if (s390_function_arg_float (mode, type))
7545 {
7546 cum->fprs += 1;
7547 }
7548 else if (s390_function_arg_integer (mode, type))
7549 {
7550 int size = s390_function_arg_size (mode, type);
7551 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7552 }
7553 else
7554 gcc_unreachable ();
7555 }
7556
7557 /* Define where to put the arguments to a function.
7558 Value is zero to push the argument on the stack,
7559 or a hard register in which to store the argument.
7560
7561 MODE is the argument's machine mode.
7562 TYPE is the data type of the argument (as a tree).
7563 This is null for libcalls where that information may
7564 not be available.
7565 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7566 the preceding args and about the function being called.
7567 NAMED is nonzero if this argument is a named parameter
7568 (otherwise it is an extra parameter matching an ellipsis).
7569
7570 On S/390, we use general purpose registers 2 through 6 to
7571 pass integer, pointer, and certain structure arguments, and
7572 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7573 to pass floating point arguments. All remaining arguments
7574 are pushed to the stack. */
7575
7576 rtx
7577 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7578 int named ATTRIBUTE_UNUSED)
7579 {
7580 if (s390_function_arg_float (mode, type))
7581 {
7582 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7583 return 0;
7584 else
7585 return gen_rtx_REG (mode, cum->fprs + 16);
7586 }
7587 else if (s390_function_arg_integer (mode, type))
7588 {
7589 int size = s390_function_arg_size (mode, type);
7590 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7591
7592 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7593 return 0;
7594 else
7595 return gen_rtx_REG (mode, cum->gprs + 2);
7596 }
7597
7598 /* After the real arguments, expand_call calls us once again
7599 with a void_type_node type. Whatever we return here is
7600 passed as operand 2 to the call expanders.
7601
7602 We don't need this feature ... */
7603 else if (type == void_type_node)
7604 return const0_rtx;
7605
7606 gcc_unreachable ();
7607 }
7608
7609 /* Return true if return values of type TYPE should be returned
7610 in a memory buffer whose address is passed by the caller as
7611 hidden first argument. */
7612
7613 static bool
7614 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7615 {
7616 /* We accept small integral (and similar) types. */
7617 if (INTEGRAL_TYPE_P (type)
7618 || POINTER_TYPE_P (type)
7619 || TREE_CODE (type) == OFFSET_TYPE
7620 || TREE_CODE (type) == REAL_TYPE)
7621 return int_size_in_bytes (type) > 8;
7622
7623 /* Aggregates and similar constructs are always returned
7624 in memory. */
7625 if (AGGREGATE_TYPE_P (type)
7626 || TREE_CODE (type) == COMPLEX_TYPE
7627 || TREE_CODE (type) == VECTOR_TYPE)
7628 return true;
7629
7630 /* ??? We get called on all sorts of random stuff from
7631 aggregate_value_p. We can't abort, but it's not clear
7632 what's safe to return. Pretend it's a struct I guess. */
7633 return true;
7634 }
7635
7636 /* Define where to return a (scalar) value of type TYPE.
7637 If TYPE is null, define where to return a (scalar)
7638 value of mode MODE from a libcall. */
7639
7640 rtx
7641 s390_function_value (tree type, enum machine_mode mode)
7642 {
7643 if (type)
7644 {
7645 int unsignedp = TYPE_UNSIGNED (type);
7646 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7647 }
7648
7649 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
7650 || GET_MODE_CLASS (mode) == MODE_FLOAT);
7651 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7652
7653 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
7654 return gen_rtx_REG (mode, 16);
7655 else
7656 return gen_rtx_REG (mode, 2);
7657 }
7658
7659
7660 /* Create and return the va_list datatype.
7661
7662 On S/390, va_list is an array type equivalent to
7663
7664 typedef struct __va_list_tag
7665 {
7666 long __gpr;
7667 long __fpr;
7668 void *__overflow_arg_area;
7669 void *__reg_save_area;
7670 } va_list[1];
7671
7672 where __gpr and __fpr hold the number of general purpose
7673 or floating point arguments used up to now, respectively,
7674 __overflow_arg_area points to the stack location of the
7675 next argument passed on the stack, and __reg_save_area
7676 always points to the start of the register area in the
7677 call frame of the current function. The function prologue
7678 saves all registers used for argument passing into this
7679 area if the function uses variable arguments. */
7680
7681 static tree
7682 s390_build_builtin_va_list (void)
7683 {
7684 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7685
7686 record = lang_hooks.types.make_type (RECORD_TYPE);
7687
7688 type_decl =
7689 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7690
7691 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7692 long_integer_type_node);
7693 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7694 long_integer_type_node);
7695 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7696 ptr_type_node);
7697 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7698 ptr_type_node);
7699
7700 va_list_gpr_counter_field = f_gpr;
7701 va_list_fpr_counter_field = f_fpr;
7702
7703 DECL_FIELD_CONTEXT (f_gpr) = record;
7704 DECL_FIELD_CONTEXT (f_fpr) = record;
7705 DECL_FIELD_CONTEXT (f_ovf) = record;
7706 DECL_FIELD_CONTEXT (f_sav) = record;
7707
7708 TREE_CHAIN (record) = type_decl;
7709 TYPE_NAME (record) = type_decl;
7710 TYPE_FIELDS (record) = f_gpr;
7711 TREE_CHAIN (f_gpr) = f_fpr;
7712 TREE_CHAIN (f_fpr) = f_ovf;
7713 TREE_CHAIN (f_ovf) = f_sav;
7714
7715 layout_type (record);
7716
7717 /* The correct type is an array type of one element. */
7718 return build_array_type (record, build_index_type (size_zero_node));
7719 }
7720
7721 /* Implement va_start by filling the va_list structure VALIST.
7722 STDARG_P is always true, and ignored.
7723 NEXTARG points to the first anonymous stack argument.
7724
7725 The following global variables are used to initialize
7726 the va_list structure:
7727
7728 current_function_args_info:
7729 holds number of gprs and fprs used for named arguments.
7730 current_function_arg_offset_rtx:
7731 holds the offset of the first anonymous stack argument
7732 (relative to the virtual arg pointer). */
7733
7734 void
7735 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7736 {
7737 HOST_WIDE_INT n_gpr, n_fpr;
7738 int off;
7739 tree f_gpr, f_fpr, f_ovf, f_sav;
7740 tree gpr, fpr, ovf, sav, t;
7741
7742 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7743 f_fpr = TREE_CHAIN (f_gpr);
7744 f_ovf = TREE_CHAIN (f_fpr);
7745 f_sav = TREE_CHAIN (f_ovf);
7746
7747 valist = build_va_arg_indirect_ref (valist);
7748 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7749 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7750 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7751 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7752
7753 /* Count number of gp and fp argument registers used. */
7754
7755 n_gpr = current_function_args_info.gprs;
7756 n_fpr = current_function_args_info.fprs;
7757
7758 if (cfun->va_list_gpr_size)
7759 {
7760 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7761 build_int_cst (NULL_TREE, n_gpr));
7762 TREE_SIDE_EFFECTS (t) = 1;
7763 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7764 }
7765
7766 if (cfun->va_list_fpr_size)
7767 {
7768 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7769 build_int_cst (NULL_TREE, n_fpr));
7770 TREE_SIDE_EFFECTS (t) = 1;
7771 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7772 }
7773
7774 /* Find the overflow area. */
7775 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7776 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7777 {
7778 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7779
7780 off = INTVAL (current_function_arg_offset_rtx);
7781 off = off < 0 ? 0 : off;
7782 if (TARGET_DEBUG_ARG)
7783 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7784 (int)n_gpr, (int)n_fpr, off);
7785
7786 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7787
7788 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7789 TREE_SIDE_EFFECTS (t) = 1;
7790 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7791 }
7792
7793 /* Find the register save area. */
7794 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7795 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7796 {
7797 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7798 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
7799 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7800
7801 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7802 TREE_SIDE_EFFECTS (t) = 1;
7803 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7804 }
7805 }
7806
7807 /* Implement va_arg by updating the va_list structure
7808 VALIST as required to retrieve an argument of type
7809 TYPE, and returning that argument.
7810
7811 Generates code equivalent to:
7812
7813 if (integral value) {
7814 if (size <= 4 && args.gpr < 5 ||
7815 size > 4 && args.gpr < 4 )
7816 ret = args.reg_save_area[args.gpr+8]
7817 else
7818 ret = *args.overflow_arg_area++;
7819 } else if (float value) {
7820 if (args.fgpr < 2)
7821 ret = args.reg_save_area[args.fpr+64]
7822 else
7823 ret = *args.overflow_arg_area++;
7824 } else if (aggregate value) {
7825 if (args.gpr < 5)
7826 ret = *args.reg_save_area[args.gpr]
7827 else
7828 ret = **args.overflow_arg_area++;
7829 } */
7830
7831 static tree
7832 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
7833 tree *post_p ATTRIBUTE_UNUSED)
7834 {
7835 tree f_gpr, f_fpr, f_ovf, f_sav;
7836 tree gpr, fpr, ovf, sav, reg, t, u;
7837 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
7838 tree lab_false, lab_over, addr;
7839
7840 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7841 f_fpr = TREE_CHAIN (f_gpr);
7842 f_ovf = TREE_CHAIN (f_fpr);
7843 f_sav = TREE_CHAIN (f_ovf);
7844
7845 valist = build_va_arg_indirect_ref (valist);
7846 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7847 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7848 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7849 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7850
7851 size = int_size_in_bytes (type);
7852
7853 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7854 {
7855 if (TARGET_DEBUG_ARG)
7856 {
7857 fprintf (stderr, "va_arg: aggregate type");
7858 debug_tree (type);
7859 }
7860
7861 /* Aggregates are passed by reference. */
7862 indirect_p = 1;
7863 reg = gpr;
7864 n_reg = 1;
7865
7866 /* kernel stack layout on 31 bit: It is assumed here that no padding
7867 will be added by s390_frame_info because for va_args always an even
7868 number of gprs has to be saved r15-r2 = 14 regs. */
7869 sav_ofs = 2 * UNITS_PER_WORD;
7870 sav_scale = UNITS_PER_WORD;
7871 size = UNITS_PER_WORD;
7872 max_reg = GP_ARG_NUM_REG - n_reg;
7873 }
7874 else if (s390_function_arg_float (TYPE_MODE (type), type))
7875 {
7876 if (TARGET_DEBUG_ARG)
7877 {
7878 fprintf (stderr, "va_arg: float type");
7879 debug_tree (type);
7880 }
7881
7882 /* FP args go in FP registers, if present. */
7883 indirect_p = 0;
7884 reg = fpr;
7885 n_reg = 1;
7886 sav_ofs = 16 * UNITS_PER_WORD;
7887 sav_scale = 8;
7888 max_reg = FP_ARG_NUM_REG - n_reg;
7889 }
7890 else
7891 {
7892 if (TARGET_DEBUG_ARG)
7893 {
7894 fprintf (stderr, "va_arg: other type");
7895 debug_tree (type);
7896 }
7897
7898 /* Otherwise into GP registers. */
7899 indirect_p = 0;
7900 reg = gpr;
7901 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7902
7903 /* kernel stack layout on 31 bit: It is assumed here that no padding
7904 will be added by s390_frame_info because for va_args always an even
7905 number of gprs has to be saved r15-r2 = 14 regs. */
7906 sav_ofs = 2 * UNITS_PER_WORD;
7907
7908 if (size < UNITS_PER_WORD)
7909 sav_ofs += UNITS_PER_WORD - size;
7910
7911 sav_scale = UNITS_PER_WORD;
7912 max_reg = GP_ARG_NUM_REG - n_reg;
7913 }
7914
7915 /* Pull the value out of the saved registers ... */
7916
7917 lab_false = create_artificial_label ();
7918 lab_over = create_artificial_label ();
7919 addr = create_tmp_var (ptr_type_node, "addr");
7920 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
7921
7922 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
7923 t = build2 (GT_EXPR, boolean_type_node, reg, t);
7924 u = build1 (GOTO_EXPR, void_type_node, lab_false);
7925 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
7926 gimplify_and_add (t, pre_p);
7927
7928 t = build2 (PLUS_EXPR, ptr_type_node, sav,
7929 fold_convert (ptr_type_node, size_int (sav_ofs)));
7930 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
7931 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
7932 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
7933
7934 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
7935 gimplify_and_add (t, pre_p);
7936
7937 t = build1 (GOTO_EXPR, void_type_node, lab_over);
7938 gimplify_and_add (t, pre_p);
7939
7940 t = build1 (LABEL_EXPR, void_type_node, lab_false);
7941 append_to_statement_list (t, pre_p);
7942
7943
7944 /* ... Otherwise out of the overflow area. */
7945
7946 t = ovf;
7947 if (size < UNITS_PER_WORD)
7948 t = build2 (PLUS_EXPR, ptr_type_node, t,
7949 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
7950
7951 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7952
7953 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
7954 gimplify_and_add (u, pre_p);
7955
7956 t = build2 (PLUS_EXPR, ptr_type_node, t,
7957 fold_convert (ptr_type_node, size_int (size)));
7958 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
7959 gimplify_and_add (t, pre_p);
7960
7961 t = build1 (LABEL_EXPR, void_type_node, lab_over);
7962 append_to_statement_list (t, pre_p);
7963
7964
7965 /* Increment register save count. */
7966
7967 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
7968 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
7969 gimplify_and_add (u, pre_p);
7970
7971 if (indirect_p)
7972 {
7973 t = build_pointer_type (build_pointer_type (type));
7974 addr = fold_convert (t, addr);
7975 addr = build_va_arg_indirect_ref (addr);
7976 }
7977 else
7978 {
7979 t = build_pointer_type (type);
7980 addr = fold_convert (t, addr);
7981 }
7982
7983 return build_va_arg_indirect_ref (addr);
7984 }
7985
7986
7987 /* Builtins. */
7988
7989 enum s390_builtin
7990 {
7991 S390_BUILTIN_THREAD_POINTER,
7992 S390_BUILTIN_SET_THREAD_POINTER,
7993
7994 S390_BUILTIN_max
7995 };
7996
7997 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
7998 CODE_FOR_get_tp_64,
7999 CODE_FOR_set_tp_64
8000 };
8001
8002 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8003 CODE_FOR_get_tp_31,
8004 CODE_FOR_set_tp_31
8005 };
8006
8007 static void
8008 s390_init_builtins (void)
8009 {
8010 tree ftype;
8011
8012 ftype = build_function_type (ptr_type_node, void_list_node);
8013 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
8014 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8015 NULL, NULL_TREE);
8016
8017 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8018 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
8019 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8020 NULL, NULL_TREE);
8021 }
8022
8023 /* Expand an expression EXP that calls a built-in function,
8024 with result going to TARGET if that's convenient
8025 (and in mode MODE if that's convenient).
8026 SUBTARGET may be used as the target for computing one of EXP's operands.
8027 IGNORE is nonzero if the value is to be ignored. */
8028
8029 static rtx
8030 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8031 enum machine_mode mode ATTRIBUTE_UNUSED,
8032 int ignore ATTRIBUTE_UNUSED)
8033 {
8034 #define MAX_ARGS 2
8035
8036 unsigned int const *code_for_builtin =
8037 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8038
8039 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8040 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8041 tree arglist = TREE_OPERAND (exp, 1);
8042 enum insn_code icode;
8043 rtx op[MAX_ARGS], pat;
8044 int arity;
8045 bool nonvoid;
8046
8047 if (fcode >= S390_BUILTIN_max)
8048 internal_error ("bad builtin fcode");
8049 icode = code_for_builtin[fcode];
8050 if (icode == 0)
8051 internal_error ("bad builtin fcode");
8052
8053 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8054
8055 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
8056 arglist;
8057 arglist = TREE_CHAIN (arglist), arity++)
8058 {
8059 const struct insn_operand_data *insn_op;
8060
8061 tree arg = TREE_VALUE (arglist);
8062 if (arg == error_mark_node)
8063 return NULL_RTX;
8064 if (arity > MAX_ARGS)
8065 return NULL_RTX;
8066
8067 insn_op = &insn_data[icode].operand[arity + nonvoid];
8068
8069 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8070
8071 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8072 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8073 }
8074
8075 if (nonvoid)
8076 {
8077 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8078 if (!target
8079 || GET_MODE (target) != tmode
8080 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8081 target = gen_reg_rtx (tmode);
8082 }
8083
8084 switch (arity)
8085 {
8086 case 0:
8087 pat = GEN_FCN (icode) (target);
8088 break;
8089 case 1:
8090 if (nonvoid)
8091 pat = GEN_FCN (icode) (target, op[0]);
8092 else
8093 pat = GEN_FCN (icode) (op[0]);
8094 break;
8095 case 2:
8096 pat = GEN_FCN (icode) (target, op[0], op[1]);
8097 break;
8098 default:
8099 gcc_unreachable ();
8100 }
8101 if (!pat)
8102 return NULL_RTX;
8103 emit_insn (pat);
8104
8105 if (nonvoid)
8106 return target;
8107 else
8108 return const0_rtx;
8109 }
8110
8111
8112 /* Output assembly code for the trampoline template to
8113 stdio stream FILE.
8114
8115 On S/390, we use gpr 1 internally in the trampoline code;
8116 gpr 0 is used to hold the static chain. */
8117
8118 void
8119 s390_trampoline_template (FILE *file)
8120 {
8121 rtx op[2];
8122 op[0] = gen_rtx_REG (Pmode, 0);
8123 op[1] = gen_rtx_REG (Pmode, 1);
8124
8125 if (TARGET_64BIT)
8126 {
8127 output_asm_insn ("basr\t%1,0", op);
8128 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8129 output_asm_insn ("br\t%1", op);
8130 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8131 }
8132 else
8133 {
8134 output_asm_insn ("basr\t%1,0", op);
8135 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8136 output_asm_insn ("br\t%1", op);
8137 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8138 }
8139 }
8140
8141 /* Emit RTL insns to initialize the variable parts of a trampoline.
8142 FNADDR is an RTX for the address of the function's pure code.
8143 CXT is an RTX for the static chain value for the function. */
8144
8145 void
8146 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8147 {
8148 emit_move_insn (gen_rtx_MEM (Pmode,
8149 memory_address (Pmode,
8150 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8151 emit_move_insn (gen_rtx_MEM (Pmode,
8152 memory_address (Pmode,
8153 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8154 }
8155
8156 /* Return rtx for 64-bit constant formed from the 32-bit subwords
8157 LOW and HIGH, independent of the host word size. */
8158
8159 rtx
8160 s390_gen_rtx_const_DI (int high, int low)
8161 {
8162 #if HOST_BITS_PER_WIDE_INT >= 64
8163 HOST_WIDE_INT val;
8164 val = (HOST_WIDE_INT)high;
8165 val <<= 32;
8166 val |= (HOST_WIDE_INT)low;
8167
8168 return GEN_INT (val);
8169 #else
8170 #if HOST_BITS_PER_WIDE_INT >= 32
8171 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8172 #else
8173 gcc_unreachable ();
8174 #endif
8175 #endif
8176 }
8177
8178 /* Output assembler code to FILE to increment profiler label # LABELNO
8179 for profiling a function entry. */
8180
8181 void
8182 s390_function_profiler (FILE *file, int labelno)
8183 {
8184 rtx op[7];
8185
8186 char label[128];
8187 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8188
8189 fprintf (file, "# function profiler \n");
8190
8191 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8192 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8193 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8194
8195 op[2] = gen_rtx_REG (Pmode, 1);
8196 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8197 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8198
8199 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8200 if (flag_pic)
8201 {
8202 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8203 op[4] = gen_rtx_CONST (Pmode, op[4]);
8204 }
8205
8206 if (TARGET_64BIT)
8207 {
8208 output_asm_insn ("stg\t%0,%1", op);
8209 output_asm_insn ("larl\t%2,%3", op);
8210 output_asm_insn ("brasl\t%0,%4", op);
8211 output_asm_insn ("lg\t%0,%1", op);
8212 }
8213 else if (!flag_pic)
8214 {
8215 op[6] = gen_label_rtx ();
8216
8217 output_asm_insn ("st\t%0,%1", op);
8218 output_asm_insn ("bras\t%2,%l6", op);
8219 output_asm_insn (".long\t%4", op);
8220 output_asm_insn (".long\t%3", op);
8221 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8222 output_asm_insn ("l\t%0,0(%2)", op);
8223 output_asm_insn ("l\t%2,4(%2)", op);
8224 output_asm_insn ("basr\t%0,%0", op);
8225 output_asm_insn ("l\t%0,%1", op);
8226 }
8227 else
8228 {
8229 op[5] = gen_label_rtx ();
8230 op[6] = gen_label_rtx ();
8231
8232 output_asm_insn ("st\t%0,%1", op);
8233 output_asm_insn ("bras\t%2,%l6", op);
8234 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8235 output_asm_insn (".long\t%4-%l5", op);
8236 output_asm_insn (".long\t%3-%l5", op);
8237 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8238 output_asm_insn ("lr\t%0,%2", op);
8239 output_asm_insn ("a\t%0,0(%2)", op);
8240 output_asm_insn ("a\t%2,4(%2)", op);
8241 output_asm_insn ("basr\t%0,%0", op);
8242 output_asm_insn ("l\t%0,%1", op);
8243 }
8244 }
8245
8246 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8247 into its SYMBOL_REF_FLAGS. */
8248
8249 static void
8250 s390_encode_section_info (tree decl, rtx rtl, int first)
8251 {
8252 default_encode_section_info (decl, rtl, first);
8253
8254 /* If a variable has a forced alignment to < 2 bytes, mark it with
8255 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8256 if (TREE_CODE (decl) == VAR_DECL
8257 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8258 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8259 }
8260
8261 /* Output thunk to FILE that implements a C++ virtual function call (with
8262 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8263 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8264 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8265 relative to the resulting this pointer. */
8266
8267 static void
8268 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8269 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8270 tree function)
8271 {
8272 rtx op[10];
8273 int nonlocal = 0;
8274
8275 /* Operand 0 is the target function. */
8276 op[0] = XEXP (DECL_RTL (function), 0);
8277 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8278 {
8279 nonlocal = 1;
8280 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8281 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8282 op[0] = gen_rtx_CONST (Pmode, op[0]);
8283 }
8284
8285 /* Operand 1 is the 'this' pointer. */
8286 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8287 op[1] = gen_rtx_REG (Pmode, 3);
8288 else
8289 op[1] = gen_rtx_REG (Pmode, 2);
8290
8291 /* Operand 2 is the delta. */
8292 op[2] = GEN_INT (delta);
8293
8294 /* Operand 3 is the vcall_offset. */
8295 op[3] = GEN_INT (vcall_offset);
8296
8297 /* Operand 4 is the temporary register. */
8298 op[4] = gen_rtx_REG (Pmode, 1);
8299
8300 /* Operands 5 to 8 can be used as labels. */
8301 op[5] = NULL_RTX;
8302 op[6] = NULL_RTX;
8303 op[7] = NULL_RTX;
8304 op[8] = NULL_RTX;
8305
8306 /* Operand 9 can be used for temporary register. */
8307 op[9] = NULL_RTX;
8308
8309 /* Generate code. */
8310 if (TARGET_64BIT)
8311 {
8312 /* Setup literal pool pointer if required. */
8313 if ((!DISP_IN_RANGE (delta)
8314 && !CONST_OK_FOR_K (delta)
8315 && !CONST_OK_FOR_Os (delta))
8316 || (!DISP_IN_RANGE (vcall_offset)
8317 && !CONST_OK_FOR_K (vcall_offset)
8318 && !CONST_OK_FOR_Os (vcall_offset)))
8319 {
8320 op[5] = gen_label_rtx ();
8321 output_asm_insn ("larl\t%4,%5", op);
8322 }
8323
8324 /* Add DELTA to this pointer. */
8325 if (delta)
8326 {
8327 if (CONST_OK_FOR_J (delta))
8328 output_asm_insn ("la\t%1,%2(%1)", op);
8329 else if (DISP_IN_RANGE (delta))
8330 output_asm_insn ("lay\t%1,%2(%1)", op);
8331 else if (CONST_OK_FOR_K (delta))
8332 output_asm_insn ("aghi\t%1,%2", op);
8333 else if (CONST_OK_FOR_Os (delta))
8334 output_asm_insn ("agfi\t%1,%2", op);
8335 else
8336 {
8337 op[6] = gen_label_rtx ();
8338 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8339 }
8340 }
8341
8342 /* Perform vcall adjustment. */
8343 if (vcall_offset)
8344 {
8345 if (DISP_IN_RANGE (vcall_offset))
8346 {
8347 output_asm_insn ("lg\t%4,0(%1)", op);
8348 output_asm_insn ("ag\t%1,%3(%4)", op);
8349 }
8350 else if (CONST_OK_FOR_K (vcall_offset))
8351 {
8352 output_asm_insn ("lghi\t%4,%3", op);
8353 output_asm_insn ("ag\t%4,0(%1)", op);
8354 output_asm_insn ("ag\t%1,0(%4)", op);
8355 }
8356 else if (CONST_OK_FOR_Os (vcall_offset))
8357 {
8358 output_asm_insn ("lgfi\t%4,%3", op);
8359 output_asm_insn ("ag\t%4,0(%1)", op);
8360 output_asm_insn ("ag\t%1,0(%4)", op);
8361 }
8362 else
8363 {
8364 op[7] = gen_label_rtx ();
8365 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8366 output_asm_insn ("ag\t%4,0(%1)", op);
8367 output_asm_insn ("ag\t%1,0(%4)", op);
8368 }
8369 }
8370
8371 /* Jump to target. */
8372 output_asm_insn ("jg\t%0", op);
8373
8374 /* Output literal pool if required. */
8375 if (op[5])
8376 {
8377 output_asm_insn (".align\t4", op);
8378 targetm.asm_out.internal_label (file, "L",
8379 CODE_LABEL_NUMBER (op[5]));
8380 }
8381 if (op[6])
8382 {
8383 targetm.asm_out.internal_label (file, "L",
8384 CODE_LABEL_NUMBER (op[6]));
8385 output_asm_insn (".long\t%2", op);
8386 }
8387 if (op[7])
8388 {
8389 targetm.asm_out.internal_label (file, "L",
8390 CODE_LABEL_NUMBER (op[7]));
8391 output_asm_insn (".long\t%3", op);
8392 }
8393 }
8394 else
8395 {
8396 /* Setup base pointer if required. */
8397 if (!vcall_offset
8398 || (!DISP_IN_RANGE (delta)
8399 && !CONST_OK_FOR_K (delta)
8400 && !CONST_OK_FOR_Os (delta))
8401 || (!DISP_IN_RANGE (delta)
8402 && !CONST_OK_FOR_K (vcall_offset)
8403 && !CONST_OK_FOR_Os (vcall_offset)))
8404 {
8405 op[5] = gen_label_rtx ();
8406 output_asm_insn ("basr\t%4,0", op);
8407 targetm.asm_out.internal_label (file, "L",
8408 CODE_LABEL_NUMBER (op[5]));
8409 }
8410
8411 /* Add DELTA to this pointer. */
8412 if (delta)
8413 {
8414 if (CONST_OK_FOR_J (delta))
8415 output_asm_insn ("la\t%1,%2(%1)", op);
8416 else if (DISP_IN_RANGE (delta))
8417 output_asm_insn ("lay\t%1,%2(%1)", op);
8418 else if (CONST_OK_FOR_K (delta))
8419 output_asm_insn ("ahi\t%1,%2", op);
8420 else if (CONST_OK_FOR_Os (delta))
8421 output_asm_insn ("afi\t%1,%2", op);
8422 else
8423 {
8424 op[6] = gen_label_rtx ();
8425 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8426 }
8427 }
8428
8429 /* Perform vcall adjustment. */
8430 if (vcall_offset)
8431 {
8432 if (CONST_OK_FOR_J (vcall_offset))
8433 {
8434 output_asm_insn ("l\t%4,0(%1)", op);
8435 output_asm_insn ("a\t%1,%3(%4)", op);
8436 }
8437 else if (DISP_IN_RANGE (vcall_offset))
8438 {
8439 output_asm_insn ("l\t%4,0(%1)", op);
8440 output_asm_insn ("ay\t%1,%3(%4)", op);
8441 }
8442 else if (CONST_OK_FOR_K (vcall_offset))
8443 {
8444 output_asm_insn ("lhi\t%4,%3", op);
8445 output_asm_insn ("a\t%4,0(%1)", op);
8446 output_asm_insn ("a\t%1,0(%4)", op);
8447 }
8448 else if (CONST_OK_FOR_Os (vcall_offset))
8449 {
8450 output_asm_insn ("iilf\t%4,%3", op);
8451 output_asm_insn ("a\t%4,0(%1)", op);
8452 output_asm_insn ("a\t%1,0(%4)", op);
8453 }
8454 else
8455 {
8456 op[7] = gen_label_rtx ();
8457 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8458 output_asm_insn ("a\t%4,0(%1)", op);
8459 output_asm_insn ("a\t%1,0(%4)", op);
8460 }
8461
8462 /* We had to clobber the base pointer register.
8463 Re-setup the base pointer (with a different base). */
8464 op[5] = gen_label_rtx ();
8465 output_asm_insn ("basr\t%4,0", op);
8466 targetm.asm_out.internal_label (file, "L",
8467 CODE_LABEL_NUMBER (op[5]));
8468 }
8469
8470 /* Jump to target. */
8471 op[8] = gen_label_rtx ();
8472
8473 if (!flag_pic)
8474 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8475 else if (!nonlocal)
8476 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8477 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8478 else if (flag_pic == 1)
8479 {
8480 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8481 output_asm_insn ("l\t%4,%0(%4)", op);
8482 }
8483 else if (flag_pic == 2)
8484 {
8485 op[9] = gen_rtx_REG (Pmode, 0);
8486 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8487 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8488 output_asm_insn ("ar\t%4,%9", op);
8489 output_asm_insn ("l\t%4,0(%4)", op);
8490 }
8491
8492 output_asm_insn ("br\t%4", op);
8493
8494 /* Output literal pool. */
8495 output_asm_insn (".align\t4", op);
8496
8497 if (nonlocal && flag_pic == 2)
8498 output_asm_insn (".long\t%0", op);
8499 if (nonlocal)
8500 {
8501 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8502 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8503 }
8504
8505 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8506 if (!flag_pic)
8507 output_asm_insn (".long\t%0", op);
8508 else
8509 output_asm_insn (".long\t%0-%5", op);
8510
8511 if (op[6])
8512 {
8513 targetm.asm_out.internal_label (file, "L",
8514 CODE_LABEL_NUMBER (op[6]));
8515 output_asm_insn (".long\t%2", op);
8516 }
8517 if (op[7])
8518 {
8519 targetm.asm_out.internal_label (file, "L",
8520 CODE_LABEL_NUMBER (op[7]));
8521 output_asm_insn (".long\t%3", op);
8522 }
8523 }
8524 }
8525
8526 static bool
8527 s390_valid_pointer_mode (enum machine_mode mode)
8528 {
8529 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8530 }
8531
8532 /* Checks whether the given ARGUMENT_LIST would use a caller
8533 saved register. This is used to decide whether sibling call
8534 optimization could be performed on the respective function
8535 call. */
8536
8537 static bool
8538 s390_call_saved_register_used (tree argument_list)
8539 {
8540 CUMULATIVE_ARGS cum;
8541 tree parameter;
8542 enum machine_mode mode;
8543 tree type;
8544 rtx parm_rtx;
8545 int reg;
8546
8547 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8548
8549 while (argument_list)
8550 {
8551 parameter = TREE_VALUE (argument_list);
8552 argument_list = TREE_CHAIN (argument_list);
8553
8554 gcc_assert (parameter);
8555
8556 /* For an undeclared variable passed as parameter we will get
8557 an ERROR_MARK node here. */
8558 if (TREE_CODE (parameter) == ERROR_MARK)
8559 return true;
8560
8561 type = TREE_TYPE (parameter);
8562 gcc_assert (type);
8563
8564 mode = TYPE_MODE (type);
8565 gcc_assert (mode);
8566
8567 if (pass_by_reference (&cum, mode, type, true))
8568 {
8569 mode = Pmode;
8570 type = build_pointer_type (type);
8571 }
8572
8573 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8574
8575 s390_function_arg_advance (&cum, mode, type, 0);
8576
8577 if (parm_rtx && REG_P (parm_rtx))
8578 {
8579 for (reg = 0;
8580 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8581 reg++)
8582 if (! call_used_regs[reg + REGNO (parm_rtx)])
8583 return true;
8584 }
8585 }
8586 return false;
8587 }
8588
8589 /* Return true if the given call expression can be
8590 turned into a sibling call.
8591 DECL holds the declaration of the function to be called whereas
8592 EXP is the call expression itself. */
8593
8594 static bool
8595 s390_function_ok_for_sibcall (tree decl, tree exp)
8596 {
8597 /* The TPF epilogue uses register 1. */
8598 if (TARGET_TPF_PROFILING)
8599 return false;
8600
8601 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8602 which would have to be restored before the sibcall. */
8603 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
8604 return false;
8605
8606 /* Register 6 on s390 is available as an argument register but unfortunately
8607 "caller saved". This makes functions needing this register for arguments
8608 not suitable for sibcalls. */
8609 if (TREE_OPERAND (exp, 1)
8610 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8611 return false;
8612
8613 return true;
8614 }
8615
8616 /* Return the fixed registers used for condition codes. */
8617
8618 static bool
8619 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8620 {
8621 *p1 = CC_REGNUM;
8622 *p2 = INVALID_REGNUM;
8623
8624 return true;
8625 }
8626
8627 /* This function is used by the call expanders of the machine description.
8628 It emits the call insn itself together with the necessary operations
8629 to adjust the target address and returns the emitted insn.
8630 ADDR_LOCATION is the target address rtx
8631 TLS_CALL the location of the thread-local symbol
8632 RESULT_REG the register where the result of the call should be stored
8633 RETADDR_REG the register where the return address should be stored
8634 If this parameter is NULL_RTX the call is considered
8635 to be a sibling call. */
8636
8637 rtx
8638 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8639 rtx retaddr_reg)
8640 {
8641 bool plt_call = false;
8642 rtx insn;
8643 rtx call;
8644 rtx clobber;
8645 rtvec vec;
8646
8647 /* Direct function calls need special treatment. */
8648 if (GET_CODE (addr_location) == SYMBOL_REF)
8649 {
8650 /* When calling a global routine in PIC mode, we must
8651 replace the symbol itself with the PLT stub. */
8652 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8653 {
8654 addr_location = gen_rtx_UNSPEC (Pmode,
8655 gen_rtvec (1, addr_location),
8656 UNSPEC_PLT);
8657 addr_location = gen_rtx_CONST (Pmode, addr_location);
8658 plt_call = true;
8659 }
8660
8661 /* Unless we can use the bras(l) insn, force the
8662 routine address into a register. */
8663 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8664 {
8665 if (flag_pic)
8666 addr_location = legitimize_pic_address (addr_location, 0);
8667 else
8668 addr_location = force_reg (Pmode, addr_location);
8669 }
8670 }
8671
8672 /* If it is already an indirect call or the code above moved the
8673 SYMBOL_REF to somewhere else make sure the address can be found in
8674 register 1. */
8675 if (retaddr_reg == NULL_RTX
8676 && GET_CODE (addr_location) != SYMBOL_REF
8677 && !plt_call)
8678 {
8679 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8680 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8681 }
8682
8683 addr_location = gen_rtx_MEM (QImode, addr_location);
8684 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8685
8686 if (result_reg != NULL_RTX)
8687 call = gen_rtx_SET (VOIDmode, result_reg, call);
8688
8689 if (retaddr_reg != NULL_RTX)
8690 {
8691 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8692
8693 if (tls_call != NULL_RTX)
8694 vec = gen_rtvec (3, call, clobber,
8695 gen_rtx_USE (VOIDmode, tls_call));
8696 else
8697 vec = gen_rtvec (2, call, clobber);
8698
8699 call = gen_rtx_PARALLEL (VOIDmode, vec);
8700 }
8701
8702 insn = emit_call_insn (call);
8703
8704 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8705 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8706 {
8707 /* s390_function_ok_for_sibcall should
8708 have denied sibcalls in this case. */
8709 gcc_assert (retaddr_reg != NULL_RTX);
8710
8711 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8712 }
8713 return insn;
8714 }
8715
8716 /* Implement CONDITIONAL_REGISTER_USAGE. */
8717
8718 void
8719 s390_conditional_register_usage (void)
8720 {
8721 int i;
8722
8723 if (flag_pic)
8724 {
8725 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8726 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8727 }
8728 if (TARGET_CPU_ZARCH)
8729 {
8730 fixed_regs[BASE_REGNUM] = 0;
8731 call_used_regs[BASE_REGNUM] = 0;
8732 fixed_regs[RETURN_REGNUM] = 0;
8733 call_used_regs[RETURN_REGNUM] = 0;
8734 }
8735 if (TARGET_64BIT)
8736 {
8737 for (i = 24; i < 32; i++)
8738 call_used_regs[i] = call_really_used_regs[i] = 0;
8739 }
8740 else
8741 {
8742 for (i = 18; i < 20; i++)
8743 call_used_regs[i] = call_really_used_regs[i] = 0;
8744 }
8745
8746 if (TARGET_SOFT_FLOAT)
8747 {
8748 for (i = 16; i < 32; i++)
8749 call_used_regs[i] = fixed_regs[i] = 1;
8750 }
8751 }
8752
8753 /* Corresponding function to eh_return expander. */
8754
8755 static GTY(()) rtx s390_tpf_eh_return_symbol;
8756 void
8757 s390_emit_tpf_eh_return (rtx target)
8758 {
8759 rtx insn, reg;
8760
8761 if (!s390_tpf_eh_return_symbol)
8762 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8763
8764 reg = gen_rtx_REG (Pmode, 2);
8765
8766 emit_move_insn (reg, target);
8767 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8768 gen_rtx_REG (Pmode, RETURN_REGNUM));
8769 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8770
8771 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8772 }
8773
8774 /* Rework the prologue/epilogue to avoid saving/restoring
8775 registers unnecessarily. */
8776
8777 static void
8778 s390_optimize_prologue (void)
8779 {
8780 rtx insn, new_insn, next_insn;
8781
8782 /* Do a final recompute of the frame-related data. */
8783
8784 s390_update_frame_layout ();
8785
8786 /* If all special registers are in fact used, there's nothing we
8787 can do, so no point in walking the insn list. */
8788
8789 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8790 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8791 && (TARGET_CPU_ZARCH
8792 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8793 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8794 return;
8795
8796 /* Search for prologue/epilogue insns and replace them. */
8797
8798 for (insn = get_insns (); insn; insn = next_insn)
8799 {
8800 int first, last, off;
8801 rtx set, base, offset;
8802
8803 next_insn = NEXT_INSN (insn);
8804
8805 if (GET_CODE (insn) != INSN)
8806 continue;
8807
8808 if (GET_CODE (PATTERN (insn)) == PARALLEL
8809 && store_multiple_operation (PATTERN (insn), VOIDmode))
8810 {
8811 set = XVECEXP (PATTERN (insn), 0, 0);
8812 first = REGNO (SET_SRC (set));
8813 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8814 offset = const0_rtx;
8815 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8816 off = INTVAL (offset);
8817
8818 if (GET_CODE (base) != REG || off < 0)
8819 continue;
8820 if (cfun_frame_layout.first_save_gpr != -1
8821 && (cfun_frame_layout.first_save_gpr < first
8822 || cfun_frame_layout.last_save_gpr > last))
8823 continue;
8824 if (REGNO (base) != STACK_POINTER_REGNUM
8825 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8826 continue;
8827 if (first > BASE_REGNUM || last < BASE_REGNUM)
8828 continue;
8829
8830 if (cfun_frame_layout.first_save_gpr != -1)
8831 {
8832 new_insn = save_gprs (base,
8833 off + (cfun_frame_layout.first_save_gpr
8834 - first) * UNITS_PER_WORD,
8835 cfun_frame_layout.first_save_gpr,
8836 cfun_frame_layout.last_save_gpr);
8837 new_insn = emit_insn_before (new_insn, insn);
8838 INSN_ADDRESSES_NEW (new_insn, -1);
8839 }
8840
8841 remove_insn (insn);
8842 continue;
8843 }
8844
8845 if (cfun_frame_layout.first_save_gpr == -1
8846 && GET_CODE (PATTERN (insn)) == SET
8847 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
8848 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
8849 || (!TARGET_CPU_ZARCH
8850 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
8851 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
8852 {
8853 set = PATTERN (insn);
8854 first = REGNO (SET_SRC (set));
8855 offset = const0_rtx;
8856 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8857 off = INTVAL (offset);
8858
8859 if (GET_CODE (base) != REG || off < 0)
8860 continue;
8861 if (REGNO (base) != STACK_POINTER_REGNUM
8862 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8863 continue;
8864
8865 remove_insn (insn);
8866 continue;
8867 }
8868
8869 if (GET_CODE (PATTERN (insn)) == PARALLEL
8870 && load_multiple_operation (PATTERN (insn), VOIDmode))
8871 {
8872 set = XVECEXP (PATTERN (insn), 0, 0);
8873 first = REGNO (SET_DEST (set));
8874 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8875 offset = const0_rtx;
8876 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8877 off = INTVAL (offset);
8878
8879 if (GET_CODE (base) != REG || off < 0)
8880 continue;
8881 if (cfun_frame_layout.first_restore_gpr != -1
8882 && (cfun_frame_layout.first_restore_gpr < first
8883 || cfun_frame_layout.last_restore_gpr > last))
8884 continue;
8885 if (REGNO (base) != STACK_POINTER_REGNUM
8886 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8887 continue;
8888 if (first > BASE_REGNUM || last < BASE_REGNUM)
8889 continue;
8890
8891 if (cfun_frame_layout.first_restore_gpr != -1)
8892 {
8893 new_insn = restore_gprs (base,
8894 off + (cfun_frame_layout.first_restore_gpr
8895 - first) * UNITS_PER_WORD,
8896 cfun_frame_layout.first_restore_gpr,
8897 cfun_frame_layout.last_restore_gpr);
8898 new_insn = emit_insn_before (new_insn, insn);
8899 INSN_ADDRESSES_NEW (new_insn, -1);
8900 }
8901
8902 remove_insn (insn);
8903 continue;
8904 }
8905
8906 if (cfun_frame_layout.first_restore_gpr == -1
8907 && GET_CODE (PATTERN (insn)) == SET
8908 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
8909 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
8910 || (!TARGET_CPU_ZARCH
8911 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
8912 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
8913 {
8914 set = PATTERN (insn);
8915 first = REGNO (SET_DEST (set));
8916 offset = const0_rtx;
8917 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8918 off = INTVAL (offset);
8919
8920 if (GET_CODE (base) != REG || off < 0)
8921 continue;
8922 if (REGNO (base) != STACK_POINTER_REGNUM
8923 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8924 continue;
8925
8926 remove_insn (insn);
8927 continue;
8928 }
8929 }
8930 }
8931
8932 /* Perform machine-dependent processing. */
8933
8934 static void
8935 s390_reorg (void)
8936 {
8937 bool pool_overflow = false;
8938
8939 /* Make sure all splits have been performed; splits after
8940 machine_dependent_reorg might confuse insn length counts. */
8941 split_all_insns_noflow ();
8942
8943 /* From here on decomposed literal pool addresses must be accepted. */
8944 cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
8945
8946 /* Install the main literal pool and the associated base
8947 register load insns.
8948
8949 In addition, there are two problematic situations we need
8950 to correct:
8951
8952 - the literal pool might be > 4096 bytes in size, so that
8953 some of its elements cannot be directly accessed
8954
8955 - a branch target might be > 64K away from the branch, so that
8956 it is not possible to use a PC-relative instruction.
8957
8958 To fix those, we split the single literal pool into multiple
8959 pool chunks, reloading the pool base register at various
8960 points throughout the function to ensure it always points to
8961 the pool chunk the following code expects, and / or replace
8962 PC-relative branches by absolute branches.
8963
8964 However, the two problems are interdependent: splitting the
8965 literal pool can move a branch further away from its target,
8966 causing the 64K limit to overflow, and on the other hand,
8967 replacing a PC-relative branch by an absolute branch means
8968 we need to put the branch target address into the literal
8969 pool, possibly causing it to overflow.
8970
8971 So, we loop trying to fix up both problems until we manage
8972 to satisfy both conditions at the same time. Note that the
8973 loop is guaranteed to terminate as every pass of the loop
8974 strictly decreases the total number of PC-relative branches
8975 in the function. (This is not completely true as there
8976 might be branch-over-pool insns introduced by chunkify_start.
8977 Those never need to be split however.) */
8978
8979 for (;;)
8980 {
8981 struct constant_pool *pool = NULL;
8982
8983 /* Collect the literal pool. */
8984 if (!pool_overflow)
8985 {
8986 pool = s390_mainpool_start ();
8987 if (!pool)
8988 pool_overflow = true;
8989 }
8990
8991 /* If literal pool overflowed, start to chunkify it. */
8992 if (pool_overflow)
8993 pool = s390_chunkify_start ();
8994
8995 /* Split out-of-range branches. If this has created new
8996 literal pool entries, cancel current chunk list and
8997 recompute it. zSeries machines have large branch
8998 instructions, so we never need to split a branch. */
8999 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9000 {
9001 if (pool_overflow)
9002 s390_chunkify_cancel (pool);
9003 else
9004 s390_mainpool_cancel (pool);
9005
9006 continue;
9007 }
9008
9009 /* If we made it up to here, both conditions are satisfied.
9010 Finish up literal pool related changes. */
9011 if (pool_overflow)
9012 s390_chunkify_finish (pool);
9013 else
9014 s390_mainpool_finish (pool);
9015
9016 /* We're done splitting branches. */
9017 cfun->machine->split_branches_pending_p = false;
9018 break;
9019 }
9020
9021 /* Generate out-of-pool execute target insns. */
9022 if (TARGET_CPU_ZARCH)
9023 {
9024 rtx insn, label, target;
9025
9026 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9027 {
9028 label = s390_execute_label (insn);
9029 if (!label)
9030 continue;
9031
9032 gcc_assert (label != const0_rtx);
9033
9034 target = emit_label (XEXP (label, 0));
9035 INSN_ADDRESSES_NEW (target, -1);
9036
9037 target = emit_insn (s390_execute_target (insn));
9038 INSN_ADDRESSES_NEW (target, -1);
9039 }
9040 }
9041
9042 /* Try to optimize prologue and epilogue further. */
9043 s390_optimize_prologue ();
9044 }
9045
9046
9047 /* Initialize GCC target structure. */
9048
9049 #undef TARGET_ASM_ALIGNED_HI_OP
9050 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9051 #undef TARGET_ASM_ALIGNED_DI_OP
9052 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9053 #undef TARGET_ASM_INTEGER
9054 #define TARGET_ASM_INTEGER s390_assemble_integer
9055
9056 #undef TARGET_ASM_OPEN_PAREN
9057 #define TARGET_ASM_OPEN_PAREN ""
9058
9059 #undef TARGET_ASM_CLOSE_PAREN
9060 #define TARGET_ASM_CLOSE_PAREN ""
9061
9062 #undef TARGET_DEFAULT_TARGET_FLAGS
9063 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9064 #undef TARGET_HANDLE_OPTION
9065 #define TARGET_HANDLE_OPTION s390_handle_option
9066
9067 #undef TARGET_ENCODE_SECTION_INFO
9068 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9069
9070 #ifdef HAVE_AS_TLS
9071 #undef TARGET_HAVE_TLS
9072 #define TARGET_HAVE_TLS true
9073 #endif
9074 #undef TARGET_CANNOT_FORCE_CONST_MEM
9075 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9076
9077 #undef TARGET_DELEGITIMIZE_ADDRESS
9078 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9079
9080 #undef TARGET_RETURN_IN_MEMORY
9081 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9082
9083 #undef TARGET_INIT_BUILTINS
9084 #define TARGET_INIT_BUILTINS s390_init_builtins
9085 #undef TARGET_EXPAND_BUILTIN
9086 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9087
9088 #undef TARGET_ASM_OUTPUT_MI_THUNK
9089 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9090 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9091 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9092
9093 #undef TARGET_SCHED_ADJUST_PRIORITY
9094 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9095 #undef TARGET_SCHED_ISSUE_RATE
9096 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9097 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9098 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9099
9100 #undef TARGET_CANNOT_COPY_INSN_P
9101 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9102 #undef TARGET_RTX_COSTS
9103 #define TARGET_RTX_COSTS s390_rtx_costs
9104 #undef TARGET_ADDRESS_COST
9105 #define TARGET_ADDRESS_COST s390_address_cost
9106
9107 #undef TARGET_MACHINE_DEPENDENT_REORG
9108 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9109
9110 #undef TARGET_VALID_POINTER_MODE
9111 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9112
9113 #undef TARGET_BUILD_BUILTIN_VA_LIST
9114 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9115 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9116 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9117
9118 #undef TARGET_PROMOTE_FUNCTION_ARGS
9119 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9120 #undef TARGET_PROMOTE_FUNCTION_RETURN
9121 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9122 #undef TARGET_PASS_BY_REFERENCE
9123 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9124
9125 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9126 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9127
9128 #undef TARGET_FIXED_CONDITION_CODE_REGS
9129 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9130
9131 #undef TARGET_CC_MODES_COMPATIBLE
9132 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9133
9134 #undef TARGET_INVALID_WITHIN_DOLOOP
9135 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9136
9137 #ifdef HAVE_AS_TLS
9138 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9139 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9140 #endif
9141
9142 struct gcc_target targetm = TARGET_INITIALIZER;
9143
9144 #include "gt-s390.h"