1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2019 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #define IN_TARGET_CODE 1
27 #include "coretypes.h"
30 #include "target-globals.h"
39 #include "stringpool.h"
47 #include "diagnostic-core.h"
48 #include "diagnostic.h"
50 #include "fold-const.h"
51 #include "print-tree.h"
52 #include "stor-layout.h"
55 #include "conditions.h"
57 #include "insn-attr.h"
69 #include "cfgcleanup.h"
71 #include "langhooks.h"
72 #include "internal-fn.h"
73 #include "gimple-fold.h"
78 #include "tree-pass.h"
83 #include "tm-constrs.h"
85 #include "symbol-summary.h"
87 #include "ipa-fnsummary.h"
88 #include "sched-int.h"
90 /* This file should be included last. */
91 #include "target-def.h"
93 static bool s390_hard_regno_mode_ok (unsigned int, machine_mode
);
95 /* Remember the last target of s390_set_current_function. */
96 static GTY(()) tree s390_previous_fndecl
;
98 /* Define the specific costs for a given cpu. */
100 struct processor_costs
103 const int m
; /* cost of an M instruction. */
104 const int mghi
; /* cost of an MGHI instruction. */
105 const int mh
; /* cost of an MH instruction. */
106 const int mhi
; /* cost of an MHI instruction. */
107 const int ml
; /* cost of an ML instruction. */
108 const int mr
; /* cost of an MR instruction. */
109 const int ms
; /* cost of an MS instruction. */
110 const int msg
; /* cost of an MSG instruction. */
111 const int msgf
; /* cost of an MSGF instruction. */
112 const int msgfr
; /* cost of an MSGFR instruction. */
113 const int msgr
; /* cost of an MSGR instruction. */
114 const int msr
; /* cost of an MSR instruction. */
115 const int mult_df
; /* cost of multiplication in DFmode. */
118 const int sqxbr
; /* cost of square root in TFmode. */
119 const int sqdbr
; /* cost of square root in DFmode. */
120 const int sqebr
; /* cost of square root in SFmode. */
121 /* multiply and add */
122 const int madbr
; /* cost of multiply and add in DFmode. */
123 const int maebr
; /* cost of multiply and add in SFmode. */
135 #define s390_cost ((const struct processor_costs *)(s390_cost_pointer))
138 struct processor_costs z900_cost
=
140 COSTS_N_INSNS (5), /* M */
141 COSTS_N_INSNS (10), /* MGHI */
142 COSTS_N_INSNS (5), /* MH */
143 COSTS_N_INSNS (4), /* MHI */
144 COSTS_N_INSNS (5), /* ML */
145 COSTS_N_INSNS (5), /* MR */
146 COSTS_N_INSNS (4), /* MS */
147 COSTS_N_INSNS (15), /* MSG */
148 COSTS_N_INSNS (7), /* MSGF */
149 COSTS_N_INSNS (7), /* MSGFR */
150 COSTS_N_INSNS (10), /* MSGR */
151 COSTS_N_INSNS (4), /* MSR */
152 COSTS_N_INSNS (7), /* multiplication in DFmode */
153 COSTS_N_INSNS (13), /* MXBR */
154 COSTS_N_INSNS (136), /* SQXBR */
155 COSTS_N_INSNS (44), /* SQDBR */
156 COSTS_N_INSNS (35), /* SQEBR */
157 COSTS_N_INSNS (18), /* MADBR */
158 COSTS_N_INSNS (13), /* MAEBR */
159 COSTS_N_INSNS (134), /* DXBR */
160 COSTS_N_INSNS (30), /* DDBR */
161 COSTS_N_INSNS (27), /* DEBR */
162 COSTS_N_INSNS (220), /* DLGR */
163 COSTS_N_INSNS (34), /* DLR */
164 COSTS_N_INSNS (34), /* DR */
165 COSTS_N_INSNS (32), /* DSGFR */
166 COSTS_N_INSNS (32), /* DSGR */
170 struct processor_costs z990_cost
=
172 COSTS_N_INSNS (4), /* M */
173 COSTS_N_INSNS (2), /* MGHI */
174 COSTS_N_INSNS (2), /* MH */
175 COSTS_N_INSNS (2), /* MHI */
176 COSTS_N_INSNS (4), /* ML */
177 COSTS_N_INSNS (4), /* MR */
178 COSTS_N_INSNS (5), /* MS */
179 COSTS_N_INSNS (6), /* MSG */
180 COSTS_N_INSNS (4), /* MSGF */
181 COSTS_N_INSNS (4), /* MSGFR */
182 COSTS_N_INSNS (4), /* MSGR */
183 COSTS_N_INSNS (4), /* MSR */
184 COSTS_N_INSNS (1), /* multiplication in DFmode */
185 COSTS_N_INSNS (28), /* MXBR */
186 COSTS_N_INSNS (130), /* SQXBR */
187 COSTS_N_INSNS (66), /* SQDBR */
188 COSTS_N_INSNS (38), /* SQEBR */
189 COSTS_N_INSNS (1), /* MADBR */
190 COSTS_N_INSNS (1), /* MAEBR */
191 COSTS_N_INSNS (60), /* DXBR */
192 COSTS_N_INSNS (40), /* DDBR */
193 COSTS_N_INSNS (26), /* DEBR */
194 COSTS_N_INSNS (176), /* DLGR */
195 COSTS_N_INSNS (31), /* DLR */
196 COSTS_N_INSNS (31), /* DR */
197 COSTS_N_INSNS (31), /* DSGFR */
198 COSTS_N_INSNS (31), /* DSGR */
202 struct processor_costs z9_109_cost
=
204 COSTS_N_INSNS (4), /* M */
205 COSTS_N_INSNS (2), /* MGHI */
206 COSTS_N_INSNS (2), /* MH */
207 COSTS_N_INSNS (2), /* MHI */
208 COSTS_N_INSNS (4), /* ML */
209 COSTS_N_INSNS (4), /* MR */
210 COSTS_N_INSNS (5), /* MS */
211 COSTS_N_INSNS (6), /* MSG */
212 COSTS_N_INSNS (4), /* MSGF */
213 COSTS_N_INSNS (4), /* MSGFR */
214 COSTS_N_INSNS (4), /* MSGR */
215 COSTS_N_INSNS (4), /* MSR */
216 COSTS_N_INSNS (1), /* multiplication in DFmode */
217 COSTS_N_INSNS (28), /* MXBR */
218 COSTS_N_INSNS (130), /* SQXBR */
219 COSTS_N_INSNS (66), /* SQDBR */
220 COSTS_N_INSNS (38), /* SQEBR */
221 COSTS_N_INSNS (1), /* MADBR */
222 COSTS_N_INSNS (1), /* MAEBR */
223 COSTS_N_INSNS (60), /* DXBR */
224 COSTS_N_INSNS (40), /* DDBR */
225 COSTS_N_INSNS (26), /* DEBR */
226 COSTS_N_INSNS (30), /* DLGR */
227 COSTS_N_INSNS (23), /* DLR */
228 COSTS_N_INSNS (23), /* DR */
229 COSTS_N_INSNS (24), /* DSGFR */
230 COSTS_N_INSNS (24), /* DSGR */
234 struct processor_costs z10_cost
=
236 COSTS_N_INSNS (10), /* M */
237 COSTS_N_INSNS (10), /* MGHI */
238 COSTS_N_INSNS (10), /* MH */
239 COSTS_N_INSNS (10), /* MHI */
240 COSTS_N_INSNS (10), /* ML */
241 COSTS_N_INSNS (10), /* MR */
242 COSTS_N_INSNS (10), /* MS */
243 COSTS_N_INSNS (10), /* MSG */
244 COSTS_N_INSNS (10), /* MSGF */
245 COSTS_N_INSNS (10), /* MSGFR */
246 COSTS_N_INSNS (10), /* MSGR */
247 COSTS_N_INSNS (10), /* MSR */
248 COSTS_N_INSNS (1) , /* multiplication in DFmode */
249 COSTS_N_INSNS (50), /* MXBR */
250 COSTS_N_INSNS (120), /* SQXBR */
251 COSTS_N_INSNS (52), /* SQDBR */
252 COSTS_N_INSNS (38), /* SQEBR */
253 COSTS_N_INSNS (1), /* MADBR */
254 COSTS_N_INSNS (1), /* MAEBR */
255 COSTS_N_INSNS (111), /* DXBR */
256 COSTS_N_INSNS (39), /* DDBR */
257 COSTS_N_INSNS (32), /* DEBR */
258 COSTS_N_INSNS (160), /* DLGR */
259 COSTS_N_INSNS (71), /* DLR */
260 COSTS_N_INSNS (71), /* DR */
261 COSTS_N_INSNS (71), /* DSGFR */
262 COSTS_N_INSNS (71), /* DSGR */
266 struct processor_costs z196_cost
=
268 COSTS_N_INSNS (7), /* M */
269 COSTS_N_INSNS (5), /* MGHI */
270 COSTS_N_INSNS (5), /* MH */
271 COSTS_N_INSNS (5), /* MHI */
272 COSTS_N_INSNS (7), /* ML */
273 COSTS_N_INSNS (7), /* MR */
274 COSTS_N_INSNS (6), /* MS */
275 COSTS_N_INSNS (8), /* MSG */
276 COSTS_N_INSNS (6), /* MSGF */
277 COSTS_N_INSNS (6), /* MSGFR */
278 COSTS_N_INSNS (8), /* MSGR */
279 COSTS_N_INSNS (6), /* MSR */
280 COSTS_N_INSNS (1) , /* multiplication in DFmode */
281 COSTS_N_INSNS (40), /* MXBR B+40 */
282 COSTS_N_INSNS (100), /* SQXBR B+100 */
283 COSTS_N_INSNS (42), /* SQDBR B+42 */
284 COSTS_N_INSNS (28), /* SQEBR B+28 */
285 COSTS_N_INSNS (1), /* MADBR B */
286 COSTS_N_INSNS (1), /* MAEBR B */
287 COSTS_N_INSNS (101), /* DXBR B+101 */
288 COSTS_N_INSNS (29), /* DDBR */
289 COSTS_N_INSNS (22), /* DEBR */
290 COSTS_N_INSNS (160), /* DLGR cracked */
291 COSTS_N_INSNS (160), /* DLR cracked */
292 COSTS_N_INSNS (160), /* DR expanded */
293 COSTS_N_INSNS (160), /* DSGFR cracked */
294 COSTS_N_INSNS (160), /* DSGR cracked */
298 struct processor_costs zEC12_cost
=
300 COSTS_N_INSNS (7), /* M */
301 COSTS_N_INSNS (5), /* MGHI */
302 COSTS_N_INSNS (5), /* MH */
303 COSTS_N_INSNS (5), /* MHI */
304 COSTS_N_INSNS (7), /* ML */
305 COSTS_N_INSNS (7), /* MR */
306 COSTS_N_INSNS (6), /* MS */
307 COSTS_N_INSNS (8), /* MSG */
308 COSTS_N_INSNS (6), /* MSGF */
309 COSTS_N_INSNS (6), /* MSGFR */
310 COSTS_N_INSNS (8), /* MSGR */
311 COSTS_N_INSNS (6), /* MSR */
312 COSTS_N_INSNS (1) , /* multiplication in DFmode */
313 COSTS_N_INSNS (40), /* MXBR B+40 */
314 COSTS_N_INSNS (100), /* SQXBR B+100 */
315 COSTS_N_INSNS (42), /* SQDBR B+42 */
316 COSTS_N_INSNS (28), /* SQEBR B+28 */
317 COSTS_N_INSNS (1), /* MADBR B */
318 COSTS_N_INSNS (1), /* MAEBR B */
319 COSTS_N_INSNS (131), /* DXBR B+131 */
320 COSTS_N_INSNS (29), /* DDBR */
321 COSTS_N_INSNS (22), /* DEBR */
322 COSTS_N_INSNS (160), /* DLGR cracked */
323 COSTS_N_INSNS (160), /* DLR cracked */
324 COSTS_N_INSNS (160), /* DR expanded */
325 COSTS_N_INSNS (160), /* DSGFR cracked */
326 COSTS_N_INSNS (160), /* DSGR cracked */
329 const struct s390_processor processor_table
[] =
331 { "z900", "z900", PROCESSOR_2064_Z900
, &z900_cost
, 5 },
332 { "z990", "z990", PROCESSOR_2084_Z990
, &z990_cost
, 6 },
333 { "z9-109", "z9-109", PROCESSOR_2094_Z9_109
, &z9_109_cost
, 7 },
334 { "z9-ec", "z9-ec", PROCESSOR_2094_Z9_EC
, &z9_109_cost
, 7 },
335 { "z10", "z10", PROCESSOR_2097_Z10
, &z10_cost
, 8 },
336 { "z196", "z196", PROCESSOR_2817_Z196
, &z196_cost
, 9 },
337 { "zEC12", "zEC12", PROCESSOR_2827_ZEC12
, &zEC12_cost
, 10 },
338 { "z13", "z13", PROCESSOR_2964_Z13
, &zEC12_cost
, 11 },
339 { "z14", "arch12", PROCESSOR_3906_Z14
, &zEC12_cost
, 12 },
340 { "native", "", PROCESSOR_NATIVE
, NULL
, 0 }
343 extern int reload_completed
;
345 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
346 static rtx_insn
*last_scheduled_insn
;
349 #define MAX_SCHED_UNITS 4
350 static int last_scheduled_unit_distance
[MAX_SCHED_UNITS
][NUM_SIDES
];
352 /* Estimate of number of cycles a long-running insn occupies an
354 static int fxd_longrunning
[NUM_SIDES
];
355 static int fpd_longrunning
[NUM_SIDES
];
357 /* The maximum score added for an instruction whose unit hasn't been
358 in use for MAX_SCHED_MIX_DISTANCE steps. Increase this value to
359 give instruction mix scheduling more priority over instruction
361 #define MAX_SCHED_MIX_SCORE 2
363 /* The maximum distance up to which individual scores will be
364 calculated. Everything beyond this gives MAX_SCHED_MIX_SCORE.
365 Increase this with the OOO windows size of the machine. */
366 #define MAX_SCHED_MIX_DISTANCE 70
368 /* Structure used to hold the components of a S/390 memory
369 address. A legitimate address on S/390 is of the general
371 base + index + displacement
372 where any of the components is optional.
374 base and index are registers of the class ADDR_REGS,
375 displacement is an unsigned 12-bit immediate constant. */
377 /* The max number of insns of backend generated memset/memcpy/memcmp
378 loops. This value is used in the unroll adjust hook to detect such
379 loops. Current max is 9 coming from the memcmp loop. */
380 #define BLOCK_MEM_OPS_LOOP_INSNS 9
391 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
393 #define cfun_frame_layout (cfun->machine->frame_layout)
394 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
395 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
396 ? cfun_frame_layout.fpr_bitmap & 0x0f \
397 : cfun_frame_layout.fpr_bitmap & 0x03))
398 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
399 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
400 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
401 (1 << (REGNO - FPR0_REGNUM)))
402 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
403 (1 << (REGNO - FPR0_REGNUM))))
404 #define cfun_gpr_save_slot(REGNO) \
405 cfun->machine->frame_layout.gpr_save_slots[REGNO]
407 /* Number of GPRs and FPRs used for argument passing. */
408 #define GP_ARG_NUM_REG 5
409 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
410 #define VEC_ARG_NUM_REG 8
412 /* A couple of shortcuts. */
413 #define CONST_OK_FOR_J(x) \
414 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
415 #define CONST_OK_FOR_K(x) \
416 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
417 #define CONST_OK_FOR_Os(x) \
418 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
419 #define CONST_OK_FOR_Op(x) \
420 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
421 #define CONST_OK_FOR_On(x) \
422 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
424 #define REGNO_PAIR_OK(REGNO, MODE) \
425 (s390_hard_regno_nregs ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
427 /* That's the read ahead of the dynamic branch prediction unit in
428 bytes on a z10 (or higher) CPU. */
429 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
431 /* Masks per jump target register indicating which thunk need to be
433 static GTY(()) int indirect_branch_prez10thunk_mask
= 0;
434 static GTY(()) int indirect_branch_z10thunk_mask
= 0;
436 #define INDIRECT_BRANCH_NUM_OPTIONS 4
438 enum s390_indirect_branch_option
440 s390_opt_indirect_branch_jump
= 0,
441 s390_opt_indirect_branch_call
,
442 s390_opt_function_return_reg
,
443 s390_opt_function_return_mem
446 static GTY(()) int indirect_branch_table_label_no
[INDIRECT_BRANCH_NUM_OPTIONS
] = { 0 };
447 const char *indirect_branch_table_label
[INDIRECT_BRANCH_NUM_OPTIONS
] = \
448 { "LJUMP", "LCALL", "LRETREG", "LRETMEM" };
449 const char *indirect_branch_table_name
[INDIRECT_BRANCH_NUM_OPTIONS
] = \
450 { ".s390_indirect_jump", ".s390_indirect_call",
451 ".s390_return_reg", ".s390_return_mem" };
454 s390_return_addr_from_memory ()
456 return cfun_gpr_save_slot(RETURN_REGNUM
) == SAVE_SLOT_STACK
;
459 /* Indicate which ABI has been used for passing vector args.
460 0 - no vector type arguments have been passed where the ABI is relevant
461 1 - the old ABI has been used
462 2 - a vector type argument has been passed either in a vector register
463 or on the stack by value */
464 static int s390_vector_abi
= 0;
466 /* Set the vector ABI marker if TYPE is subject to the vector ABI
467 switch. The vector ABI affects only vector data types. There are
468 two aspects of the vector ABI relevant here:
470 1. vectors >= 16 bytes have an alignment of 8 bytes with the new
471 ABI and natural alignment with the old.
473 2. vector <= 16 bytes are passed in VRs or by value on the stack
474 with the new ABI but by reference on the stack with the old.
476 If ARG_P is true TYPE is used for a function argument or return
477 value. The ABI marker then is set for all vector data types. If
478 ARG_P is false only type 1 vectors are being checked. */
481 s390_check_type_for_vector_abi (const_tree type
, bool arg_p
, bool in_struct_p
)
483 static hash_set
<const_tree
> visited_types_hash
;
488 if (type
== NULL_TREE
|| TREE_CODE (type
) == ERROR_MARK
)
491 if (visited_types_hash
.contains (type
))
494 visited_types_hash
.add (type
);
496 if (VECTOR_TYPE_P (type
))
498 int type_size
= int_size_in_bytes (type
);
500 /* Outside arguments only the alignment is changing and this
501 only happens for vector types >= 16 bytes. */
502 if (!arg_p
&& type_size
< 16)
505 /* In arguments vector types > 16 are passed as before (GCC
506 never enforced the bigger alignment for arguments which was
507 required by the old vector ABI). However, it might still be
508 ABI relevant due to the changed alignment if it is a struct
510 if (arg_p
&& type_size
> 16 && !in_struct_p
)
513 s390_vector_abi
= TARGET_VX_ABI
? 2 : 1;
515 else if (POINTER_TYPE_P (type
) || TREE_CODE (type
) == ARRAY_TYPE
)
517 /* ARRAY_TYPE: Since with neither of the ABIs we have more than
518 natural alignment there will never be ABI dependent padding
519 in an array type. That's why we do not set in_struct_p to
521 s390_check_type_for_vector_abi (TREE_TYPE (type
), arg_p
, in_struct_p
);
523 else if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
527 /* Check the return type. */
528 s390_check_type_for_vector_abi (TREE_TYPE (type
), true, false);
530 for (arg_chain
= TYPE_ARG_TYPES (type
);
532 arg_chain
= TREE_CHAIN (arg_chain
))
533 s390_check_type_for_vector_abi (TREE_VALUE (arg_chain
), true, false);
535 else if (RECORD_OR_UNION_TYPE_P (type
))
539 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
541 if (TREE_CODE (field
) != FIELD_DECL
)
544 s390_check_type_for_vector_abi (TREE_TYPE (field
), arg_p
, true);
550 /* System z builtins. */
552 #include "s390-builtins.h"
554 const unsigned int bflags_builtin
[S390_BUILTIN_MAX
+ 1] =
559 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, ...) BFLAGS,
561 #define OB_DEF_VAR(...)
562 #include "s390-builtins.def"
566 const unsigned int opflags_builtin
[S390_BUILTIN_MAX
+ 1] =
571 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, ...) OPFLAGS,
573 #define OB_DEF_VAR(...)
574 #include "s390-builtins.def"
578 const unsigned int bflags_overloaded_builtin
[S390_OVERLOADED_BUILTIN_MAX
+ 1] =
584 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, ...) BFLAGS,
585 #define OB_DEF_VAR(...)
586 #include "s390-builtins.def"
591 bflags_overloaded_builtin_var
[S390_OVERLOADED_BUILTIN_VAR_MAX
+ 1] =
598 #define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) FLAGS,
599 #include "s390-builtins.def"
604 opflags_overloaded_builtin_var
[S390_OVERLOADED_BUILTIN_VAR_MAX
+ 1] =
611 #define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) OPFLAGS,
612 #include "s390-builtins.def"
616 tree s390_builtin_types
[BT_MAX
];
617 tree s390_builtin_fn_types
[BT_FN_MAX
];
618 tree s390_builtin_decls
[S390_BUILTIN_MAX
+
619 S390_OVERLOADED_BUILTIN_MAX
+
620 S390_OVERLOADED_BUILTIN_VAR_MAX
];
622 static enum insn_code
const code_for_builtin
[S390_BUILTIN_MAX
+ 1] = {
626 #define B_DEF(NAME, PATTERN, ...) CODE_FOR_##PATTERN,
628 #define OB_DEF_VAR(...)
630 #include "s390-builtins.def"
635 s390_init_builtins (void)
637 /* These definitions are being used in s390-builtins.def. */
638 tree returns_twice_attr
= tree_cons (get_identifier ("returns_twice"),
640 tree noreturn_attr
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
641 tree c_uint64_type_node
;
643 /* The uint64_type_node from tree.c is not compatible to the C99
644 uint64_t data type. What we want is c_uint64_type_node from
645 c-common.c. But since backend code is not supposed to interface
646 with the frontend we recreate it here. */
648 c_uint64_type_node
= long_unsigned_type_node
;
650 c_uint64_type_node
= long_long_unsigned_type_node
;
653 #define DEF_TYPE(INDEX, NODE, CONST_P) \
654 if (s390_builtin_types[INDEX] == NULL) \
655 s390_builtin_types[INDEX] = (!CONST_P) ? \
656 (NODE) : build_type_variant ((NODE), 1, 0);
658 #undef DEF_POINTER_TYPE
659 #define DEF_POINTER_TYPE(INDEX, INDEX_BASE) \
660 if (s390_builtin_types[INDEX] == NULL) \
661 s390_builtin_types[INDEX] = \
662 build_pointer_type (s390_builtin_types[INDEX_BASE]);
664 #undef DEF_DISTINCT_TYPE
665 #define DEF_DISTINCT_TYPE(INDEX, INDEX_BASE) \
666 if (s390_builtin_types[INDEX] == NULL) \
667 s390_builtin_types[INDEX] = \
668 build_distinct_type_copy (s390_builtin_types[INDEX_BASE]);
670 #undef DEF_VECTOR_TYPE
671 #define DEF_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \
672 if (s390_builtin_types[INDEX] == NULL) \
673 s390_builtin_types[INDEX] = \
674 build_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
676 #undef DEF_OPAQUE_VECTOR_TYPE
677 #define DEF_OPAQUE_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \
678 if (s390_builtin_types[INDEX] == NULL) \
679 s390_builtin_types[INDEX] = \
680 build_opaque_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
683 #define DEF_FN_TYPE(INDEX, args...) \
684 if (s390_builtin_fn_types[INDEX] == NULL) \
685 s390_builtin_fn_types[INDEX] = \
686 build_function_type_list (args, NULL_TREE);
688 #define DEF_OV_TYPE(...)
689 #include "s390-builtin-types.def"
692 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, FNTYPE) \
693 if (s390_builtin_decls[S390_BUILTIN_##NAME] == NULL) \
694 s390_builtin_decls[S390_BUILTIN_##NAME] = \
695 add_builtin_function ("__builtin_" #NAME, \
696 s390_builtin_fn_types[FNTYPE], \
697 S390_BUILTIN_##NAME, \
702 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, FNTYPE) \
703 if (s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] \
705 s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] = \
706 add_builtin_function ("__builtin_" #NAME, \
707 s390_builtin_fn_types[FNTYPE], \
708 S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX, \
713 #define OB_DEF_VAR(...)
714 #include "s390-builtins.def"
718 /* Return true if ARG is appropriate as argument number ARGNUM of
719 builtin DECL. The operand flags from s390-builtins.def have to
720 passed as OP_FLAGS. */
722 s390_const_operand_ok (tree arg
, int argnum
, int op_flags
, tree decl
)
724 if (O_UIMM_P (op_flags
))
726 int bitwidths
[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32 };
727 int bitwidth
= bitwidths
[op_flags
- O_U1
];
729 if (!tree_fits_uhwi_p (arg
)
730 || tree_to_uhwi (arg
) > (HOST_WIDE_INT_1U
<< bitwidth
) - 1)
732 error ("constant argument %d for builtin %qF is out of range "
733 "(0..%wu)", argnum
, decl
,
734 (HOST_WIDE_INT_1U
<< bitwidth
) - 1);
739 if (O_SIMM_P (op_flags
))
741 int bitwidths
[] = { 2, 3, 4, 5, 8, 12, 16, 32 };
742 int bitwidth
= bitwidths
[op_flags
- O_S2
];
744 if (!tree_fits_shwi_p (arg
)
745 || tree_to_shwi (arg
) < -(HOST_WIDE_INT_1
<< (bitwidth
- 1))
746 || tree_to_shwi (arg
) > ((HOST_WIDE_INT_1
<< (bitwidth
- 1)) - 1))
748 error ("constant argument %d for builtin %qF is out of range "
749 "(%wd..%wd)", argnum
, decl
,
750 -(HOST_WIDE_INT_1
<< (bitwidth
- 1)),
751 (HOST_WIDE_INT_1
<< (bitwidth
- 1)) - 1);
758 /* Expand an expression EXP that calls a built-in function,
759 with result going to TARGET if that's convenient
760 (and in mode MODE if that's convenient).
761 SUBTARGET may be used as the target for computing one of EXP's operands.
762 IGNORE is nonzero if the value is to be ignored. */
765 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
766 machine_mode mode ATTRIBUTE_UNUSED
,
767 int ignore ATTRIBUTE_UNUSED
)
771 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
772 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
773 enum insn_code icode
;
774 rtx op
[MAX_ARGS
], pat
;
778 call_expr_arg_iterator iter
;
779 unsigned int all_op_flags
= opflags_for_builtin (fcode
);
780 machine_mode last_vec_mode
= VOIDmode
;
782 if (TARGET_DEBUG_ARG
)
785 "s390_expand_builtin, code = %4d, %s, bflags = 0x%x\n",
786 (int)fcode
, IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
787 bflags_for_builtin (fcode
));
790 if (S390_USE_TARGET_ATTRIBUTE
)
794 bflags
= bflags_for_builtin (fcode
);
795 if ((bflags
& B_HTM
) && !TARGET_HTM
)
797 error ("builtin %qF is not supported without %<-mhtm%> "
798 "(default with %<-march=zEC12%> and higher).", fndecl
);
801 if (((bflags
& B_VX
) || (bflags
& B_VXE
)) && !TARGET_VX
)
803 error ("builtin %qF requires %<-mvx%> "
804 "(default with %<-march=z13%> and higher).", fndecl
);
808 if ((bflags
& B_VXE
) && !TARGET_VXE
)
810 error ("Builtin %qF requires z14 or higher.", fndecl
);
814 if (fcode
>= S390_OVERLOADED_BUILTIN_VAR_OFFSET
815 && fcode
< S390_ALL_BUILTIN_MAX
)
819 else if (fcode
< S390_OVERLOADED_BUILTIN_OFFSET
)
821 icode
= code_for_builtin
[fcode
];
822 /* Set a flag in the machine specific cfun part in order to support
823 saving/restoring of FPRs. */
824 if (fcode
== S390_BUILTIN_tbegin
|| fcode
== S390_BUILTIN_tbegin_retry
)
825 cfun
->machine
->tbegin_p
= true;
827 else if (fcode
< S390_OVERLOADED_BUILTIN_VAR_OFFSET
)
829 error ("unresolved overloaded builtin");
833 internal_error ("bad builtin fcode");
836 internal_error ("bad builtin icode");
838 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
842 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
844 || GET_MODE (target
) != tmode
845 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
846 target
= gen_reg_rtx (tmode
);
848 /* There are builtins (e.g. vec_promote) with no vector
849 arguments but an element selector. So we have to also look
850 at the vector return type when emitting the modulo
852 if (VECTOR_MODE_P (insn_data
[icode
].operand
[0].mode
))
853 last_vec_mode
= insn_data
[icode
].operand
[0].mode
;
857 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
860 const struct insn_operand_data
*insn_op
;
861 unsigned int op_flags
= all_op_flags
& ((1 << O_SHIFT
) - 1);
863 all_op_flags
= all_op_flags
>> O_SHIFT
;
865 if (arg
== error_mark_node
)
867 if (arity
>= MAX_ARGS
)
870 if (O_IMM_P (op_flags
)
871 && TREE_CODE (arg
) != INTEGER_CST
)
873 error ("constant value required for builtin %qF argument %d",
878 if (!s390_const_operand_ok (arg
, arity
+ 1, op_flags
, fndecl
))
881 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
882 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
884 /* expand_expr truncates constants to the target mode only if it
885 is "convenient". However, our checks below rely on this
887 if (CONST_INT_P (op
[arity
])
888 && SCALAR_INT_MODE_P (insn_op
->mode
)
889 && GET_MODE (op
[arity
]) != insn_op
->mode
)
890 op
[arity
] = GEN_INT (trunc_int_for_mode (INTVAL (op
[arity
]),
893 /* Wrap the expanded RTX for pointer types into a MEM expr with
894 the proper mode. This allows us to use e.g. (match_operand
895 "memory_operand"..) in the insn patterns instead of (mem
896 (match_operand "address_operand)). This is helpful for
897 patterns not just accepting MEMs. */
898 if (POINTER_TYPE_P (TREE_TYPE (arg
))
899 && insn_op
->predicate
!= address_operand
)
900 op
[arity
] = gen_rtx_MEM (insn_op
->mode
, op
[arity
]);
902 /* Expand the module operation required on element selectors. */
903 if (op_flags
== O_ELEM
)
905 gcc_assert (last_vec_mode
!= VOIDmode
);
906 op
[arity
] = simplify_expand_binop (SImode
, code_to_optab (AND
),
908 GEN_INT (GET_MODE_NUNITS (last_vec_mode
) - 1),
909 NULL_RTX
, 1, OPTAB_DIRECT
);
912 /* Record the vector mode used for an element selector. This assumes:
913 1. There is no builtin with two different vector modes and an element selector
914 2. The element selector comes after the vector type it is referring to.
915 This currently the true for all the builtins but FIXME we
916 should better check for that. */
917 if (VECTOR_MODE_P (insn_op
->mode
))
918 last_vec_mode
= insn_op
->mode
;
920 if (insn_op
->predicate (op
[arity
], insn_op
->mode
))
926 /* A memory operand is rejected by the memory_operand predicate.
927 Try making the address legal by copying it into a register. */
928 if (MEM_P (op
[arity
])
929 && insn_op
->predicate
== memory_operand
930 && (GET_MODE (XEXP (op
[arity
], 0)) == Pmode
931 || GET_MODE (XEXP (op
[arity
], 0)) == VOIDmode
))
933 op
[arity
] = replace_equiv_address (op
[arity
],
934 copy_to_mode_reg (Pmode
,
935 XEXP (op
[arity
], 0)));
937 /* Some of the builtins require different modes/types than the
938 pattern in order to implement a specific API. Instead of
939 adding many expanders which do the mode change we do it here.
940 E.g. s390_vec_add_u128 required to have vector unsigned char
941 arguments is mapped to addti3. */
942 else if (insn_op
->mode
!= VOIDmode
943 && GET_MODE (op
[arity
]) != VOIDmode
944 && GET_MODE (op
[arity
]) != insn_op
->mode
945 && ((tmp_rtx
= simplify_gen_subreg (insn_op
->mode
, op
[arity
],
946 GET_MODE (op
[arity
]), 0))
952 /* The predicate rejects the operand although the mode is fine.
953 Copy the operand to register. */
954 if (!insn_op
->predicate (op
[arity
], insn_op
->mode
)
955 && (GET_MODE (op
[arity
]) == insn_op
->mode
956 || GET_MODE (op
[arity
]) == VOIDmode
957 || (insn_op
->predicate
== address_operand
958 && GET_MODE (op
[arity
]) == Pmode
)))
960 /* An address_operand usually has VOIDmode in the expander
961 so we cannot use this. */
962 machine_mode target_mode
=
963 (insn_op
->predicate
== address_operand
964 ? (machine_mode
) Pmode
: insn_op
->mode
);
965 op
[arity
] = copy_to_mode_reg (target_mode
, op
[arity
]);
968 if (!insn_op
->predicate (op
[arity
], insn_op
->mode
))
970 error ("invalid argument %d for builtin %qF", arity
+ 1, fndecl
);
979 pat
= GEN_FCN (icode
) (target
);
983 pat
= GEN_FCN (icode
) (target
, op
[0]);
985 pat
= GEN_FCN (icode
) (op
[0]);
989 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
991 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
995 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2]);
997 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
1001 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3]);
1003 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
1007 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4]);
1009 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4]);
1013 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
1015 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
1031 static const int s390_hotpatch_hw_max
= 1000000;
1032 static int s390_hotpatch_hw_before_label
= 0;
1033 static int s390_hotpatch_hw_after_label
= 0;
1035 /* Check whether the hotpatch attribute is applied to a function and, if it has
1036 an argument, the argument is valid. */
1039 s390_handle_hotpatch_attribute (tree
*node
, tree name
, tree args
,
1040 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1046 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1048 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
1050 *no_add_attrs
= true;
1052 if (args
!= NULL
&& TREE_CHAIN (args
) != NULL
)
1054 expr
= TREE_VALUE (args
);
1055 expr2
= TREE_VALUE (TREE_CHAIN (args
));
1057 if (args
== NULL
|| TREE_CHAIN (args
) == NULL
)
1059 else if (TREE_CODE (expr
) != INTEGER_CST
1060 || !INTEGRAL_TYPE_P (TREE_TYPE (expr
))
1061 || wi::gtu_p (wi::to_wide (expr
), s390_hotpatch_hw_max
))
1063 else if (TREE_CODE (expr2
) != INTEGER_CST
1064 || !INTEGRAL_TYPE_P (TREE_TYPE (expr2
))
1065 || wi::gtu_p (wi::to_wide (expr2
), s390_hotpatch_hw_max
))
1071 error ("requested %qE attribute is not a comma separated pair of"
1072 " non-negative integer constants or too large (max. %d)", name
,
1073 s390_hotpatch_hw_max
);
1074 *no_add_attrs
= true;
1080 /* Expand the s390_vector_bool type attribute. */
1083 s390_handle_vectorbool_attribute (tree
*node
, tree name ATTRIBUTE_UNUSED
,
1084 tree args ATTRIBUTE_UNUSED
,
1085 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1087 tree type
= *node
, result
= NULL_TREE
;
1090 while (POINTER_TYPE_P (type
)
1091 || TREE_CODE (type
) == FUNCTION_TYPE
1092 || TREE_CODE (type
) == METHOD_TYPE
1093 || TREE_CODE (type
) == ARRAY_TYPE
)
1094 type
= TREE_TYPE (type
);
1096 mode
= TYPE_MODE (type
);
1099 case E_DImode
: case E_V2DImode
:
1100 result
= s390_builtin_types
[BT_BV2DI
];
1102 case E_SImode
: case E_V4SImode
:
1103 result
= s390_builtin_types
[BT_BV4SI
];
1105 case E_HImode
: case E_V8HImode
:
1106 result
= s390_builtin_types
[BT_BV8HI
];
1108 case E_QImode
: case E_V16QImode
:
1109 result
= s390_builtin_types
[BT_BV16QI
];
1115 *no_add_attrs
= true; /* No need to hang on to the attribute. */
1118 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
1123 /* Check syntax of function decl attributes having a string type value. */
1126 s390_handle_string_attribute (tree
*node
, tree name ATTRIBUTE_UNUSED
,
1127 tree args ATTRIBUTE_UNUSED
,
1128 int flags ATTRIBUTE_UNUSED
,
1133 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1135 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
1137 *no_add_attrs
= true;
1140 cst
= TREE_VALUE (args
);
1142 if (TREE_CODE (cst
) != STRING_CST
)
1144 warning (OPT_Wattributes
,
1145 "%qE attribute requires a string constant argument",
1147 *no_add_attrs
= true;
1150 if (is_attribute_p ("indirect_branch", name
)
1151 || is_attribute_p ("indirect_branch_call", name
)
1152 || is_attribute_p ("function_return", name
)
1153 || is_attribute_p ("function_return_reg", name
)
1154 || is_attribute_p ("function_return_mem", name
))
1156 if (strcmp (TREE_STRING_POINTER (cst
), "keep") != 0
1157 && strcmp (TREE_STRING_POINTER (cst
), "thunk") != 0
1158 && strcmp (TREE_STRING_POINTER (cst
), "thunk-extern") != 0)
1160 warning (OPT_Wattributes
,
1161 "argument to %qE attribute is not "
1162 "(keep|thunk|thunk-extern)", name
);
1163 *no_add_attrs
= true;
1167 if (is_attribute_p ("indirect_branch_jump", name
)
1168 && strcmp (TREE_STRING_POINTER (cst
), "keep") != 0
1169 && strcmp (TREE_STRING_POINTER (cst
), "thunk") != 0
1170 && strcmp (TREE_STRING_POINTER (cst
), "thunk-inline") != 0
1171 && strcmp (TREE_STRING_POINTER (cst
), "thunk-extern") != 0)
1173 warning (OPT_Wattributes
,
1174 "argument to %qE attribute is not "
1175 "(keep|thunk|thunk-inline|thunk-extern)", name
);
1176 *no_add_attrs
= true;
1182 static const struct attribute_spec s390_attribute_table
[] = {
1183 { "hotpatch", 2, 2, true, false, false, false,
1184 s390_handle_hotpatch_attribute
, NULL
},
1185 { "s390_vector_bool", 0, 0, false, true, false, true,
1186 s390_handle_vectorbool_attribute
, NULL
},
1187 { "indirect_branch", 1, 1, true, false, false, false,
1188 s390_handle_string_attribute
, NULL
},
1189 { "indirect_branch_jump", 1, 1, true, false, false, false,
1190 s390_handle_string_attribute
, NULL
},
1191 { "indirect_branch_call", 1, 1, true, false, false, false,
1192 s390_handle_string_attribute
, NULL
},
1193 { "function_return", 1, 1, true, false, false, false,
1194 s390_handle_string_attribute
, NULL
},
1195 { "function_return_reg", 1, 1, true, false, false, false,
1196 s390_handle_string_attribute
, NULL
},
1197 { "function_return_mem", 1, 1, true, false, false, false,
1198 s390_handle_string_attribute
, NULL
},
1201 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
1204 /* Return the alignment for LABEL. We default to the -falign-labels
1205 value except for the literal pool base label. */
1207 s390_label_align (rtx_insn
*label
)
1209 rtx_insn
*prev_insn
= prev_active_insn (label
);
1212 if (prev_insn
== NULL_RTX
)
1215 set
= single_set (prev_insn
);
1217 if (set
== NULL_RTX
)
1220 src
= SET_SRC (set
);
1222 /* Don't align literal pool base labels. */
1223 if (GET_CODE (src
) == UNSPEC
1224 && XINT (src
, 1) == UNSPEC_MAIN_BASE
)
1228 return align_labels
.levels
[0].log
;
1231 static GTY(()) rtx got_symbol
;
1233 /* Return the GOT table symbol. The symbol will be created when the
1234 function is invoked for the first time. */
1237 s390_got_symbol (void)
1241 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1242 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
1248 static scalar_int_mode
1249 s390_libgcc_cmp_return_mode (void)
1251 return TARGET_64BIT
? DImode
: SImode
;
1254 static scalar_int_mode
1255 s390_libgcc_shift_count_mode (void)
1257 return TARGET_64BIT
? DImode
: SImode
;
1260 static scalar_int_mode
1261 s390_unwind_word_mode (void)
1263 return TARGET_64BIT
? DImode
: SImode
;
1266 /* Return true if the back end supports mode MODE. */
1268 s390_scalar_mode_supported_p (scalar_mode mode
)
1270 /* In contrast to the default implementation reject TImode constants on 31bit
1271 TARGET_ZARCH for ABI compliance. */
1272 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
1275 if (DECIMAL_FLOAT_MODE_P (mode
))
1276 return default_decimal_float_supported_p ();
1278 return default_scalar_mode_supported_p (mode
);
1281 /* Return true if the back end supports vector mode MODE. */
1283 s390_vector_mode_supported_p (machine_mode mode
)
1287 if (!VECTOR_MODE_P (mode
)
1289 || GET_MODE_SIZE (mode
) > 16)
1292 inner
= GET_MODE_INNER (mode
);
1310 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
1313 s390_set_has_landing_pad_p (bool value
)
1315 cfun
->machine
->has_landing_pad_p
= value
;
1318 /* If two condition code modes are compatible, return a condition code
1319 mode which is compatible with both. Otherwise, return
1323 s390_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
1331 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
1332 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
1353 /* Return true if SET either doesn't set the CC register, or else
1354 the source and destination have matching CC modes and that
1355 CC mode is at least as constrained as REQ_MODE. */
1358 s390_match_ccmode_set (rtx set
, machine_mode req_mode
)
1360 machine_mode set_mode
;
1362 gcc_assert (GET_CODE (set
) == SET
);
1364 /* These modes are supposed to be used only in CC consumer
1366 gcc_assert (req_mode
!= CCVIALLmode
&& req_mode
!= CCVIANYmode
1367 && req_mode
!= CCVFALLmode
&& req_mode
!= CCVFANYmode
);
1369 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
1372 set_mode
= GET_MODE (SET_DEST (set
));
1392 if (req_mode
!= set_mode
)
1397 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
1398 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
1399 && req_mode
!= CCZ1mode
)
1405 if (req_mode
!= CCAmode
)
1413 return (GET_MODE (SET_SRC (set
)) == set_mode
);
1416 /* Return true if every SET in INSN that sets the CC register
1417 has source and destination with matching CC modes and that
1418 CC mode is at least as constrained as REQ_MODE.
1419 If REQ_MODE is VOIDmode, always return false. */
1422 s390_match_ccmode (rtx_insn
*insn
, machine_mode req_mode
)
1426 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
1427 if (req_mode
== VOIDmode
)
1430 if (GET_CODE (PATTERN (insn
)) == SET
)
1431 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
1433 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1434 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1436 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
1437 if (GET_CODE (set
) == SET
)
1438 if (!s390_match_ccmode_set (set
, req_mode
))
1445 /* If a test-under-mask instruction can be used to implement
1446 (compare (and ... OP1) OP2), return the CC mode required
1447 to do that. Otherwise, return VOIDmode.
1448 MIXED is true if the instruction can distinguish between
1449 CC1 and CC2 for mixed selected bits (TMxx), it is false
1450 if the instruction cannot (TM). */
1453 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
1457 /* ??? Fixme: should work on CONST_WIDE_INT as well. */
1458 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
1461 /* Selected bits all zero: CC0.
1462 e.g.: int a; if ((a & (16 + 128)) == 0) */
1463 if (INTVAL (op2
) == 0)
1466 /* Selected bits all one: CC3.
1467 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
1468 if (INTVAL (op2
) == INTVAL (op1
))
1471 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
1473 if ((a & (16 + 128)) == 16) -> CCT1
1474 if ((a & (16 + 128)) == 128) -> CCT2 */
1477 bit1
= exact_log2 (INTVAL (op2
));
1478 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
1479 if (bit0
!= -1 && bit1
!= -1)
1480 return bit0
> bit1
? CCT1mode
: CCT2mode
;
1486 /* Given a comparison code OP (EQ, NE, etc.) and the operands
1487 OP0 and OP1 of a COMPARE, return the mode to be used for the
1491 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
1497 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1498 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1500 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1501 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
1503 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1504 || GET_CODE (op1
) == NEG
)
1505 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1508 if (GET_CODE (op0
) == AND
)
1510 /* Check whether we can potentially do it via TM. */
1511 machine_mode ccmode
;
1512 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
1513 if (ccmode
!= VOIDmode
)
1515 /* Relax CCTmode to CCZmode to allow fall-back to AND
1516 if that turns out to be beneficial. */
1517 return ccmode
== CCTmode
? CCZmode
: ccmode
;
1521 if (register_operand (op0
, HImode
)
1522 && GET_CODE (op1
) == CONST_INT
1523 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
1525 if (register_operand (op0
, QImode
)
1526 && GET_CODE (op1
) == CONST_INT
1527 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
1536 /* The only overflow condition of NEG and ABS happens when
1537 -INT_MAX is used as parameter, which stays negative. So
1538 we have an overflow from a positive value to a negative.
1539 Using CCAP mode the resulting cc can be used for comparisons. */
1540 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1541 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1544 /* If constants are involved in an add instruction it is possible to use
1545 the resulting cc for comparisons with zero. Knowing the sign of the
1546 constant the overflow behavior gets predictable. e.g.:
1547 int a, b; if ((b = a + c) > 0)
1548 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
1549 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1550 && (CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1)))
1551 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0
, 1)), 'O', "Os")
1552 /* Avoid INT32_MIN on 32 bit. */
1553 && (!TARGET_ZARCH
|| INTVAL (XEXP (op0
, 1)) != -0x7fffffff - 1))))
1555 if (INTVAL (XEXP((op0
), 1)) < 0)
1569 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1570 && GET_CODE (op1
) != CONST_INT
)
1576 if (GET_CODE (op0
) == PLUS
1577 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1580 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1581 && GET_CODE (op1
) != CONST_INT
)
1587 if (GET_CODE (op0
) == MINUS
1588 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1591 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1592 && GET_CODE (op1
) != CONST_INT
)
1601 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
1602 that we can implement more efficiently. */
1605 s390_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
1606 bool op0_preserve_value
)
1608 if (op0_preserve_value
)
1611 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
1612 if ((*code
== EQ
|| *code
== NE
)
1613 && *op1
== const0_rtx
1614 && GET_CODE (*op0
) == ZERO_EXTRACT
1615 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1616 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
1617 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1619 rtx inner
= XEXP (*op0
, 0);
1620 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
1621 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
1622 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
1624 if (len
> 0 && len
< modesize
1625 && pos
>= 0 && pos
+ len
<= modesize
1626 && modesize
<= HOST_BITS_PER_WIDE_INT
)
1628 unsigned HOST_WIDE_INT block
;
1629 block
= (HOST_WIDE_INT_1U
<< len
) - 1;
1630 block
<<= modesize
- pos
- len
;
1632 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
1633 gen_int_mode (block
, GET_MODE (inner
)));
1637 /* Narrow AND of memory against immediate to enable TM. */
1638 if ((*code
== EQ
|| *code
== NE
)
1639 && *op1
== const0_rtx
1640 && GET_CODE (*op0
) == AND
1641 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1642 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1644 rtx inner
= XEXP (*op0
, 0);
1645 rtx mask
= XEXP (*op0
, 1);
1647 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
1648 if (GET_CODE (inner
) == SUBREG
1649 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
1650 && (GET_MODE_SIZE (GET_MODE (inner
))
1651 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1653 & GET_MODE_MASK (GET_MODE (inner
))
1654 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
1656 inner
= SUBREG_REG (inner
);
1658 /* Do not change volatile MEMs. */
1659 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
1661 int part
= s390_single_part (XEXP (*op0
, 1),
1662 GET_MODE (inner
), QImode
, 0);
1665 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
1666 inner
= adjust_address_nv (inner
, QImode
, part
);
1667 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
1672 /* Narrow comparisons against 0xffff to HImode if possible. */
1673 if ((*code
== EQ
|| *code
== NE
)
1674 && GET_CODE (*op1
) == CONST_INT
1675 && INTVAL (*op1
) == 0xffff
1676 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
1677 && (nonzero_bits (*op0
, GET_MODE (*op0
))
1678 & ~HOST_WIDE_INT_UC (0xffff)) == 0)
1680 *op0
= gen_lowpart (HImode
, *op0
);
1684 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
1685 if (GET_CODE (*op0
) == UNSPEC
1686 && XINT (*op0
, 1) == UNSPEC_STRCMPCC_TO_INT
1687 && XVECLEN (*op0
, 0) == 1
1688 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
1689 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1690 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1691 && *op1
== const0_rtx
)
1693 enum rtx_code new_code
= UNKNOWN
;
1696 case EQ
: new_code
= EQ
; break;
1697 case NE
: new_code
= NE
; break;
1698 case LT
: new_code
= GTU
; break;
1699 case GT
: new_code
= LTU
; break;
1700 case LE
: new_code
= GEU
; break;
1701 case GE
: new_code
= LEU
; break;
1705 if (new_code
!= UNKNOWN
)
1707 *op0
= XVECEXP (*op0
, 0, 0);
1712 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
1713 if (GET_CODE (*op0
) == UNSPEC
1714 && XINT (*op0
, 1) == UNSPEC_CC_TO_INT
1715 && XVECLEN (*op0
, 0) == 1
1716 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1717 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1718 && CONST_INT_P (*op1
))
1720 enum rtx_code new_code
= UNKNOWN
;
1721 switch (GET_MODE (XVECEXP (*op0
, 0, 0)))
1727 case EQ
: new_code
= EQ
; break;
1728 case NE
: new_code
= NE
; break;
1735 if (new_code
!= UNKNOWN
)
1737 /* For CCRAWmode put the required cc mask into the second
1739 if (GET_MODE (XVECEXP (*op0
, 0, 0)) == CCRAWmode
1740 && INTVAL (*op1
) >= 0 && INTVAL (*op1
) <= 3)
1741 *op1
= gen_rtx_CONST_INT (VOIDmode
, 1 << (3 - INTVAL (*op1
)));
1742 *op0
= XVECEXP (*op0
, 0, 0);
1747 /* Simplify cascaded EQ, NE with const0_rtx. */
1748 if ((*code
== NE
|| *code
== EQ
)
1749 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
1750 && GET_MODE (*op0
) == SImode
1751 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
1752 && REG_P (XEXP (*op0
, 0))
1753 && XEXP (*op0
, 1) == const0_rtx
1754 && *op1
== const0_rtx
)
1756 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
1757 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
1761 *op0
= XEXP (*op0
, 0);
1764 /* Prefer register over memory as first operand. */
1765 if (MEM_P (*op0
) && REG_P (*op1
))
1767 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
1768 *code
= (int)swap_condition ((enum rtx_code
)*code
);
1771 /* A comparison result is compared against zero. Replace it with
1772 the (perhaps inverted) original comparison.
1773 This probably should be done by simplify_relational_operation. */
1774 if ((*code
== EQ
|| *code
== NE
)
1775 && *op1
== const0_rtx
1776 && COMPARISON_P (*op0
)
1777 && CC_REG_P (XEXP (*op0
, 0)))
1779 enum rtx_code new_code
;
1782 new_code
= reversed_comparison_code_parts (GET_CODE (*op0
),
1784 XEXP (*op1
, 0), NULL
);
1786 new_code
= GET_CODE (*op0
);
1788 if (new_code
!= UNKNOWN
)
1791 *op1
= XEXP (*op0
, 1);
1792 *op0
= XEXP (*op0
, 0);
1798 /* Emit a compare instruction suitable to implement the comparison
1799 OP0 CODE OP1. Return the correct condition RTL to be placed in
1800 the IF_THEN_ELSE of the conditional branch testing the result. */
1803 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
1805 machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
1808 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
1810 /* Do not output a redundant compare instruction if a
1811 compare_and_swap pattern already computed the result and the
1812 machine modes are compatible. */
1813 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
1819 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
1820 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
1823 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
1826 /* If MEM is not a legitimate compare-and-swap memory operand, return a new
1827 MEM, whose address is a pseudo containing the original MEM's address. */
1830 s390_legitimize_cs_operand (rtx mem
)
1834 if (!contains_symbol_ref_p (mem
))
1836 tmp
= gen_reg_rtx (Pmode
);
1837 emit_move_insn (tmp
, copy_rtx (XEXP (mem
, 0)));
1838 return change_address (mem
, VOIDmode
, tmp
);
1841 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1843 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1844 conditional branch testing the result. */
1847 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
,
1848 rtx cmp
, rtx new_rtx
, machine_mode ccmode
)
1852 mem
= s390_legitimize_cs_operand (mem
);
1853 cc
= gen_rtx_REG (ccmode
, CC_REGNUM
);
1854 switch (GET_MODE (mem
))
1857 emit_insn (gen_atomic_compare_and_swapsi_internal (old
, mem
, cmp
,
1861 emit_insn (gen_atomic_compare_and_swapdi_internal (old
, mem
, cmp
,
1865 emit_insn (gen_atomic_compare_and_swapti_internal (old
, mem
, cmp
,
1873 return s390_emit_compare (code
, cc
, const0_rtx
);
1876 /* Emit a jump instruction to TARGET and return it. If COND is
1877 NULL_RTX, emit an unconditional jump, else a conditional jump under
1881 s390_emit_jump (rtx target
, rtx cond
)
1885 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
1887 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
1889 insn
= gen_rtx_SET (pc_rtx
, target
);
1890 return emit_jump_insn (insn
);
1893 /* Return branch condition mask to implement a branch
1894 specified by CODE. Return -1 for invalid comparisons. */
1897 s390_branch_condition_mask (rtx code
)
1899 const int CC0
= 1 << 3;
1900 const int CC1
= 1 << 2;
1901 const int CC2
= 1 << 1;
1902 const int CC3
= 1 << 0;
1904 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
1905 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
1906 gcc_assert (XEXP (code
, 1) == const0_rtx
1907 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1908 && CONST_INT_P (XEXP (code
, 1))));
1911 switch (GET_MODE (XEXP (code
, 0)))
1915 switch (GET_CODE (code
))
1917 case EQ
: return CC0
;
1918 case NE
: return CC1
| CC2
| CC3
;
1924 switch (GET_CODE (code
))
1926 case EQ
: return CC1
;
1927 case NE
: return CC0
| CC2
| CC3
;
1933 switch (GET_CODE (code
))
1935 case EQ
: return CC2
;
1936 case NE
: return CC0
| CC1
| CC3
;
1942 switch (GET_CODE (code
))
1944 case EQ
: return CC3
;
1945 case NE
: return CC0
| CC1
| CC2
;
1951 switch (GET_CODE (code
))
1953 case EQ
: return CC0
| CC2
;
1954 case NE
: return CC1
| CC3
;
1960 switch (GET_CODE (code
))
1962 case LTU
: return CC2
| CC3
; /* carry */
1963 case GEU
: return CC0
| CC1
; /* no carry */
1969 switch (GET_CODE (code
))
1971 case GTU
: return CC0
| CC1
; /* borrow */
1972 case LEU
: return CC2
| CC3
; /* no borrow */
1978 switch (GET_CODE (code
))
1980 case EQ
: return CC0
| CC2
;
1981 case NE
: return CC1
| CC3
;
1982 case LTU
: return CC1
;
1983 case GTU
: return CC3
;
1984 case LEU
: return CC1
| CC2
;
1985 case GEU
: return CC2
| CC3
;
1990 switch (GET_CODE (code
))
1992 case EQ
: return CC0
;
1993 case NE
: return CC1
| CC2
| CC3
;
1994 case LTU
: return CC1
;
1995 case GTU
: return CC2
;
1996 case LEU
: return CC0
| CC1
;
1997 case GEU
: return CC0
| CC2
;
2003 switch (GET_CODE (code
))
2005 case EQ
: return CC0
;
2006 case NE
: return CC2
| CC1
| CC3
;
2007 case LTU
: return CC2
;
2008 case GTU
: return CC1
;
2009 case LEU
: return CC0
| CC2
;
2010 case GEU
: return CC0
| CC1
;
2016 switch (GET_CODE (code
))
2018 case EQ
: return CC0
;
2019 case NE
: return CC1
| CC2
| CC3
;
2020 case LT
: return CC1
| CC3
;
2021 case GT
: return CC2
;
2022 case LE
: return CC0
| CC1
| CC3
;
2023 case GE
: return CC0
| CC2
;
2029 switch (GET_CODE (code
))
2031 case EQ
: return CC0
;
2032 case NE
: return CC1
| CC2
| CC3
;
2033 case LT
: return CC1
;
2034 case GT
: return CC2
| CC3
;
2035 case LE
: return CC0
| CC1
;
2036 case GE
: return CC0
| CC2
| CC3
;
2042 switch (GET_CODE (code
))
2044 case EQ
: return CC0
;
2045 case NE
: return CC1
| CC2
| CC3
;
2046 case LT
: return CC1
;
2047 case GT
: return CC2
;
2048 case LE
: return CC0
| CC1
;
2049 case GE
: return CC0
| CC2
;
2050 case UNORDERED
: return CC3
;
2051 case ORDERED
: return CC0
| CC1
| CC2
;
2052 case UNEQ
: return CC0
| CC3
;
2053 case UNLT
: return CC1
| CC3
;
2054 case UNGT
: return CC2
| CC3
;
2055 case UNLE
: return CC0
| CC1
| CC3
;
2056 case UNGE
: return CC0
| CC2
| CC3
;
2057 case LTGT
: return CC1
| CC2
;
2063 switch (GET_CODE (code
))
2065 case EQ
: return CC0
;
2066 case NE
: return CC2
| CC1
| CC3
;
2067 case LT
: return CC2
;
2068 case GT
: return CC1
;
2069 case LE
: return CC0
| CC2
;
2070 case GE
: return CC0
| CC1
;
2071 case UNORDERED
: return CC3
;
2072 case ORDERED
: return CC0
| CC2
| CC1
;
2073 case UNEQ
: return CC0
| CC3
;
2074 case UNLT
: return CC2
| CC3
;
2075 case UNGT
: return CC1
| CC3
;
2076 case UNLE
: return CC0
| CC2
| CC3
;
2077 case UNGE
: return CC0
| CC1
| CC3
;
2078 case LTGT
: return CC2
| CC1
;
2083 /* Vector comparison modes. */
2084 /* CC2 will never be set. It however is part of the negated
2087 switch (GET_CODE (code
))
2092 case GE
: return CC0
;
2093 /* The inverted modes are in fact *any* modes. */
2097 case LT
: return CC3
| CC1
| CC2
;
2102 switch (GET_CODE (code
))
2107 case GE
: return CC0
| CC1
;
2108 /* The inverted modes are in fact *all* modes. */
2112 case LT
: return CC3
| CC2
;
2116 switch (GET_CODE (code
))
2120 case GE
: return CC0
;
2121 /* The inverted modes are in fact *any* modes. */
2124 case UNLT
: return CC3
| CC1
| CC2
;
2129 switch (GET_CODE (code
))
2133 case GE
: return CC0
| CC1
;
2134 /* The inverted modes are in fact *all* modes. */
2137 case UNLT
: return CC3
| CC2
;
2142 switch (GET_CODE (code
))
2145 return INTVAL (XEXP (code
, 1));
2147 return (INTVAL (XEXP (code
, 1))) ^ 0xf;
2158 /* Return branch condition mask to implement a compare and branch
2159 specified by CODE. Return -1 for invalid comparisons. */
2162 s390_compare_and_branch_condition_mask (rtx code
)
2164 const int CC0
= 1 << 3;
2165 const int CC1
= 1 << 2;
2166 const int CC2
= 1 << 1;
2168 switch (GET_CODE (code
))
2192 /* If INV is false, return assembler mnemonic string to implement
2193 a branch specified by CODE. If INV is true, return mnemonic
2194 for the corresponding inverted branch. */
2197 s390_branch_condition_mnemonic (rtx code
, int inv
)
2201 static const char *const mnemonic
[16] =
2203 NULL
, "o", "h", "nle",
2204 "l", "nhe", "lh", "ne",
2205 "e", "nlh", "he", "nl",
2206 "le", "nh", "no", NULL
2209 if (GET_CODE (XEXP (code
, 0)) == REG
2210 && REGNO (XEXP (code
, 0)) == CC_REGNUM
2211 && (XEXP (code
, 1) == const0_rtx
2212 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
2213 && CONST_INT_P (XEXP (code
, 1)))))
2214 mask
= s390_branch_condition_mask (code
);
2216 mask
= s390_compare_and_branch_condition_mask (code
);
2218 gcc_assert (mask
>= 0);
2223 gcc_assert (mask
>= 1 && mask
<= 14);
2225 return mnemonic
[mask
];
2228 /* Return the part of op which has a value different from def.
2229 The size of the part is determined by mode.
2230 Use this function only if you already know that op really
2231 contains such a part. */
2233 unsigned HOST_WIDE_INT
2234 s390_extract_part (rtx op
, machine_mode mode
, int def
)
2236 unsigned HOST_WIDE_INT value
= 0;
2237 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
2238 int part_bits
= GET_MODE_BITSIZE (mode
);
2239 unsigned HOST_WIDE_INT part_mask
= (HOST_WIDE_INT_1U
<< part_bits
) - 1;
2242 for (i
= 0; i
< max_parts
; i
++)
2245 value
= UINTVAL (op
);
2247 value
>>= part_bits
;
2249 if ((value
& part_mask
) != (def
& part_mask
))
2250 return value
& part_mask
;
2256 /* If OP is an integer constant of mode MODE with exactly one
2257 part of mode PART_MODE unequal to DEF, return the number of that
2258 part. Otherwise, return -1. */
2261 s390_single_part (rtx op
,
2263 machine_mode part_mode
,
2266 unsigned HOST_WIDE_INT value
= 0;
2267 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
2268 unsigned HOST_WIDE_INT part_mask
2269 = (HOST_WIDE_INT_1U
<< GET_MODE_BITSIZE (part_mode
)) - 1;
2272 if (GET_CODE (op
) != CONST_INT
)
2275 for (i
= 0; i
< n_parts
; i
++)
2278 value
= UINTVAL (op
);
2280 value
>>= GET_MODE_BITSIZE (part_mode
);
2282 if ((value
& part_mask
) != (def
& part_mask
))
2290 return part
== -1 ? -1 : n_parts
- 1 - part
;
2293 /* Return true if IN contains a contiguous bitfield in the lower SIZE
2294 bits and no other bits are set in (the lower SIZE bits of) IN.
2296 PSTART and PEND can be used to obtain the start and end
2297 position (inclusive) of the bitfield relative to 64
2298 bits. *PSTART / *PEND gives the position of the first/last bit
2299 of the bitfield counting from the highest order bit starting
2303 s390_contiguous_bitmask_nowrap_p (unsigned HOST_WIDE_INT in
, int size
,
2304 int *pstart
, int *pend
)
2308 int lowbit
= HOST_BITS_PER_WIDE_INT
- 1;
2309 int highbit
= HOST_BITS_PER_WIDE_INT
- size
;
2310 unsigned HOST_WIDE_INT bitmask
= HOST_WIDE_INT_1U
;
2312 gcc_assert (!!pstart
== !!pend
);
2313 for (start
= lowbit
; start
>= highbit
; bitmask
<<= 1, start
--)
2316 /* Look for the rightmost bit of a contiguous range of ones. */
2323 /* Look for the firt zero bit after the range of ones. */
2324 if (! (bitmask
& in
))
2328 /* We're one past the last one-bit. */
2332 /* No one bits found. */
2335 if (start
> highbit
)
2337 unsigned HOST_WIDE_INT mask
;
2339 /* Calculate a mask for all bits beyond the contiguous bits. */
2340 mask
= ((~HOST_WIDE_INT_0U
>> highbit
)
2341 & (~HOST_WIDE_INT_0U
<< (lowbit
- start
+ 1)));
2343 /* There are more bits set beyond the first range of one bits. */
2356 /* Same as s390_contiguous_bitmask_nowrap_p but also returns true
2357 if ~IN contains a contiguous bitfield. In that case, *END is <
2360 If WRAP_P is true, a bitmask that wraps around is also tested.
2361 When a wraparoud occurs *START is greater than *END (in
2362 non-null pointers), and the uppermost (64 - SIZE) bits are thus
2363 part of the range. If WRAP_P is false, no wraparound is
2367 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, bool wrap_p
,
2368 int size
, int *start
, int *end
)
2370 int bs
= HOST_BITS_PER_WIDE_INT
;
2373 gcc_assert (!!start
== !!end
);
2374 if ((in
& ((~HOST_WIDE_INT_0U
) >> (bs
- size
))) == 0)
2375 /* This cannot be expressed as a contiguous bitmask. Exit early because
2376 the second call of s390_contiguous_bitmask_nowrap_p would accept this as
2379 b
= s390_contiguous_bitmask_nowrap_p (in
, size
, start
, end
);
2384 b
= s390_contiguous_bitmask_nowrap_p (~in
, size
, start
, end
);
2390 gcc_assert (s
>= 1);
2391 *start
= ((e
+ 1) & (bs
- 1));
2392 *end
= ((s
- 1 + bs
) & (bs
- 1));
2398 /* Return true if OP contains the same contiguous bitfield in *all*
2399 its elements. START and END can be used to obtain the start and
2400 end position of the bitfield.
2402 START/STOP give the position of the first/last bit of the bitfield
2403 counting from the lowest order bit starting with zero. In order to
2404 use these values for S/390 instructions this has to be converted to
2405 "bits big endian" style. */
2408 s390_contiguous_bitmask_vector_p (rtx op
, int *start
, int *end
)
2410 unsigned HOST_WIDE_INT mask
;
2415 gcc_assert (!!start
== !!end
);
2416 if (!const_vec_duplicate_p (op
, &elt
)
2417 || !CONST_INT_P (elt
))
2420 size
= GET_MODE_UNIT_BITSIZE (GET_MODE (op
));
2422 /* We cannot deal with V1TI/V1TF. This would require a vgmq. */
2426 mask
= UINTVAL (elt
);
2428 b
= s390_contiguous_bitmask_p (mask
, true, size
, start
, end
);
2433 *start
-= (HOST_BITS_PER_WIDE_INT
- size
);
2434 *end
-= (HOST_BITS_PER_WIDE_INT
- size
);
2442 /* Return true if C consists only of byte chunks being either 0 or
2443 0xff. If MASK is !=NULL a byte mask is generated which is
2444 appropriate for the vector generate byte mask instruction. */
2447 s390_bytemask_vector_p (rtx op
, unsigned *mask
)
2450 unsigned tmp_mask
= 0;
2451 int nunit
, unit_size
;
2453 if (!VECTOR_MODE_P (GET_MODE (op
))
2454 || GET_CODE (op
) != CONST_VECTOR
2455 || !CONST_INT_P (XVECEXP (op
, 0, 0)))
2458 nunit
= GET_MODE_NUNITS (GET_MODE (op
));
2459 unit_size
= GET_MODE_UNIT_SIZE (GET_MODE (op
));
2461 for (i
= 0; i
< nunit
; i
++)
2463 unsigned HOST_WIDE_INT c
;
2466 if (!CONST_INT_P (XVECEXP (op
, 0, i
)))
2469 c
= UINTVAL (XVECEXP (op
, 0, i
));
2470 for (j
= 0; j
< unit_size
; j
++)
2472 if ((c
& 0xff) != 0 && (c
& 0xff) != 0xff)
2474 tmp_mask
|= (c
& 1) << ((nunit
- 1 - i
) * unit_size
+ j
);
2475 c
= c
>> BITS_PER_UNIT
;
2485 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
2486 equivalent to a shift followed by the AND. In particular, CONTIG
2487 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
2488 for ROTL indicate a rotate to the right. */
2491 s390_extzv_shift_ok (int bitsize
, int rotl
, unsigned HOST_WIDE_INT contig
)
2496 ok
= s390_contiguous_bitmask_nowrap_p (contig
, bitsize
, &start
, &end
);
2500 return (64 - end
>= rotl
);
2503 /* Translate "- rotate right" in BITSIZE mode to "rotate left" in
2505 rotl
= -rotl
+ (64 - bitsize
);
2506 return (start
>= rotl
);
2510 /* Check whether we can (and want to) split a double-word
2511 move in mode MODE from SRC to DST into two single-word
2512 moves, moving the subword FIRST_SUBWORD first. */
2515 s390_split_ok_p (rtx dst
, rtx src
, machine_mode mode
, int first_subword
)
2517 /* Floating point and vector registers cannot be split. */
2518 if (FP_REG_P (src
) || FP_REG_P (dst
) || VECTOR_REG_P (src
) || VECTOR_REG_P (dst
))
2521 /* Non-offsettable memory references cannot be split. */
2522 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
2523 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
2526 /* Moving the first subword must not clobber a register
2527 needed to move the second subword. */
2528 if (register_operand (dst
, mode
))
2530 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
2531 if (reg_overlap_mentioned_p (subreg
, src
))
2538 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
2539 and [MEM2, MEM2 + SIZE] do overlap and false
2543 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
2545 rtx addr1
, addr2
, addr_delta
;
2546 HOST_WIDE_INT delta
;
2548 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2554 addr1
= XEXP (mem1
, 0);
2555 addr2
= XEXP (mem2
, 0);
2557 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2559 /* This overlapping check is used by peepholes merging memory block operations.
2560 Overlapping operations would otherwise be recognized by the S/390 hardware
2561 and would fall back to a slower implementation. Allowing overlapping
2562 operations would lead to slow code but not to wrong code. Therefore we are
2563 somewhat optimistic if we cannot prove that the memory blocks are
2565 That's why we return false here although this may accept operations on
2566 overlapping memory areas. */
2567 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
2570 delta
= INTVAL (addr_delta
);
2573 || (delta
> 0 && delta
< size
)
2574 || (delta
< 0 && -delta
< size
))
2580 /* Check whether the address of memory reference MEM2 equals exactly
2581 the address of memory reference MEM1 plus DELTA. Return true if
2582 we can prove this to be the case, false otherwise. */
2585 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
2587 rtx addr1
, addr2
, addr_delta
;
2589 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2592 addr1
= XEXP (mem1
, 0);
2593 addr2
= XEXP (mem2
, 0);
2595 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2596 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
2602 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
2605 s390_expand_logical_operator (enum rtx_code code
, machine_mode mode
,
2608 machine_mode wmode
= mode
;
2609 rtx dst
= operands
[0];
2610 rtx src1
= operands
[1];
2611 rtx src2
= operands
[2];
2614 /* If we cannot handle the operation directly, use a temp register. */
2615 if (!s390_logical_operator_ok_p (operands
))
2616 dst
= gen_reg_rtx (mode
);
2618 /* QImode and HImode patterns make sense only if we have a destination
2619 in memory. Otherwise perform the operation in SImode. */
2620 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
2623 /* Widen operands if required. */
2626 if (GET_CODE (dst
) == SUBREG
2627 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
2629 else if (REG_P (dst
))
2630 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
2632 dst
= gen_reg_rtx (wmode
);
2634 if (GET_CODE (src1
) == SUBREG
2635 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
2637 else if (GET_MODE (src1
) != VOIDmode
)
2638 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
2640 if (GET_CODE (src2
) == SUBREG
2641 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
2643 else if (GET_MODE (src2
) != VOIDmode
)
2644 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
2647 /* Emit the instruction. */
2648 op
= gen_rtx_SET (dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
2649 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
2650 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
2652 /* Fix up the destination if needed. */
2653 if (dst
!= operands
[0])
2654 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
2657 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
2660 s390_logical_operator_ok_p (rtx
*operands
)
2662 /* If the destination operand is in memory, it needs to coincide
2663 with one of the source operands. After reload, it has to be
2664 the first source operand. */
2665 if (GET_CODE (operands
[0]) == MEM
)
2666 return rtx_equal_p (operands
[0], operands
[1])
2667 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
2672 /* Narrow logical operation CODE of memory operand MEMOP with immediate
2673 operand IMMOP to switch from SS to SI type instructions. */
2676 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
2678 int def
= code
== AND
? -1 : 0;
2682 gcc_assert (GET_CODE (*memop
) == MEM
);
2683 gcc_assert (!MEM_VOLATILE_P (*memop
));
2685 mask
= s390_extract_part (*immop
, QImode
, def
);
2686 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
2687 gcc_assert (part
>= 0);
2689 *memop
= adjust_address (*memop
, QImode
, part
);
2690 *immop
= gen_int_mode (mask
, QImode
);
2694 /* How to allocate a 'struct machine_function'. */
2696 static struct machine_function
*
2697 s390_init_machine_status (void)
2699 return ggc_cleared_alloc
<machine_function
> ();
2702 /* Map for smallest class containing reg regno. */
2704 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
2705 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 0 */
2706 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 4 */
2707 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 8 */
2708 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 12 */
2709 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 16 */
2710 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 20 */
2711 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 24 */
2712 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 28 */
2713 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
, /* 32 */
2714 ACCESS_REGS
, ACCESS_REGS
, VEC_REGS
, VEC_REGS
, /* 36 */
2715 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 40 */
2716 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 44 */
2717 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 48 */
2718 VEC_REGS
, VEC_REGS
/* 52 */
2721 /* Return attribute type of insn. */
2723 static enum attr_type
2724 s390_safe_attr_type (rtx_insn
*insn
)
2726 if (recog_memoized (insn
) >= 0)
2727 return get_attr_type (insn
);
2732 /* Return attribute relative_long of insn. */
2735 s390_safe_relative_long_p (rtx_insn
*insn
)
2737 if (recog_memoized (insn
) >= 0)
2738 return get_attr_relative_long (insn
) == RELATIVE_LONG_YES
;
2743 /* Return true if DISP is a valid short displacement. */
2746 s390_short_displacement (rtx disp
)
2748 /* No displacement is OK. */
2752 /* Without the long displacement facility we don't need to
2753 distingiush between long and short displacement. */
2754 if (!TARGET_LONG_DISPLACEMENT
)
2757 /* Integer displacement in range. */
2758 if (GET_CODE (disp
) == CONST_INT
)
2759 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
2761 /* GOT offset is not OK, the GOT can be large. */
2762 if (GET_CODE (disp
) == CONST
2763 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
2764 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
2765 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
2768 /* All other symbolic constants are literal pool references,
2769 which are OK as the literal pool must be small. */
2770 if (GET_CODE (disp
) == CONST
)
2776 /* Attempts to split `ref', which should be UNSPEC_LTREF, into (base + `disp').
2777 If successful, also determines the
2778 following characteristics of `ref': `is_ptr' - whether it can be an
2779 LA argument, `is_base_ptr' - whether the resulting base is a well-known
2780 base register (stack/frame pointer, etc), `is_pool_ptr` - whether it is
2781 considered a literal pool pointer for purposes of avoiding two different
2782 literal pool pointers per insn during or after reload (`B' constraint). */
2784 s390_decompose_constant_pool_ref (rtx
*ref
, rtx
*disp
, bool *is_ptr
,
2785 bool *is_base_ptr
, bool *is_pool_ptr
)
2790 if (GET_CODE (*ref
) == UNSPEC
)
2791 switch (XINT (*ref
, 1))
2795 *disp
= gen_rtx_UNSPEC (Pmode
,
2796 gen_rtvec (1, XVECEXP (*ref
, 0, 0)),
2797 UNSPEC_LTREL_OFFSET
);
2801 *ref
= XVECEXP (*ref
, 0, 1);
2808 if (!REG_P (*ref
) || GET_MODE (*ref
) != Pmode
)
2811 if (REGNO (*ref
) == STACK_POINTER_REGNUM
2812 || REGNO (*ref
) == FRAME_POINTER_REGNUM
2813 || ((reload_completed
|| reload_in_progress
)
2814 && frame_pointer_needed
2815 && REGNO (*ref
) == HARD_FRAME_POINTER_REGNUM
)
2816 || REGNO (*ref
) == ARG_POINTER_REGNUM
2818 && REGNO (*ref
) == PIC_OFFSET_TABLE_REGNUM
))
2819 *is_ptr
= *is_base_ptr
= true;
2821 if ((reload_completed
|| reload_in_progress
)
2822 && *ref
== cfun
->machine
->base_reg
)
2823 *is_ptr
= *is_base_ptr
= *is_pool_ptr
= true;
2828 /* Decompose a RTL expression ADDR for a memory address into
2829 its components, returned in OUT.
2831 Returns false if ADDR is not a valid memory address, true
2832 otherwise. If OUT is NULL, don't return the components,
2833 but check for validity only.
2835 Note: Only addresses in canonical form are recognized.
2836 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
2837 canonical form so that they will be recognized. */
2840 s390_decompose_address (rtx addr
, struct s390_address
*out
)
2842 HOST_WIDE_INT offset
= 0;
2843 rtx base
= NULL_RTX
;
2844 rtx indx
= NULL_RTX
;
2845 rtx disp
= NULL_RTX
;
2847 bool pointer
= false;
2848 bool base_ptr
= false;
2849 bool indx_ptr
= false;
2850 bool literal_pool
= false;
2852 /* We may need to substitute the literal pool base register into the address
2853 below. However, at this point we do not know which register is going to
2854 be used as base, so we substitute the arg pointer register. This is going
2855 to be treated as holding a pointer below -- it shouldn't be used for any
2857 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
2859 /* Decompose address into base + index + displacement. */
2861 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
2864 else if (GET_CODE (addr
) == PLUS
)
2866 rtx op0
= XEXP (addr
, 0);
2867 rtx op1
= XEXP (addr
, 1);
2868 enum rtx_code code0
= GET_CODE (op0
);
2869 enum rtx_code code1
= GET_CODE (op1
);
2871 if (code0
== REG
|| code0
== UNSPEC
)
2873 if (code1
== REG
|| code1
== UNSPEC
)
2875 indx
= op0
; /* index + base */
2881 base
= op0
; /* base + displacement */
2886 else if (code0
== PLUS
)
2888 indx
= XEXP (op0
, 0); /* index + base + disp */
2889 base
= XEXP (op0
, 1);
2900 disp
= addr
; /* displacement */
2902 /* Extract integer part of displacement. */
2906 if (GET_CODE (disp
) == CONST_INT
)
2908 offset
= INTVAL (disp
);
2911 else if (GET_CODE (disp
) == CONST
2912 && GET_CODE (XEXP (disp
, 0)) == PLUS
2913 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
2915 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
2916 disp
= XEXP (XEXP (disp
, 0), 0);
2920 /* Strip off CONST here to avoid special case tests later. */
2921 if (disp
&& GET_CODE (disp
) == CONST
)
2922 disp
= XEXP (disp
, 0);
2924 /* We can convert literal pool addresses to
2925 displacements by basing them off the base register. */
2926 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
2931 base
= fake_pool_base
, literal_pool
= true;
2933 /* Mark up the displacement. */
2934 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
2935 UNSPEC_LTREL_OFFSET
);
2938 /* Validate base register. */
2939 if (!s390_decompose_constant_pool_ref (&base
, &disp
, &pointer
, &base_ptr
,
2943 /* Validate index register. */
2944 if (!s390_decompose_constant_pool_ref (&indx
, &disp
, &pointer
, &indx_ptr
,
2948 /* Prefer to use pointer as base, not index. */
2949 if (base
&& indx
&& !base_ptr
2950 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
2957 /* Validate displacement. */
2960 /* If virtual registers are involved, the displacement will change later
2961 anyway as the virtual registers get eliminated. This could make a
2962 valid displacement invalid, but it is more likely to make an invalid
2963 displacement valid, because we sometimes access the register save area
2964 via negative offsets to one of those registers.
2965 Thus we don't check the displacement for validity here. If after
2966 elimination the displacement turns out to be invalid after all,
2967 this is fixed up by reload in any case. */
2968 /* LRA maintains always displacements up to date and we need to
2969 know the displacement is right during all LRA not only at the
2970 final elimination. */
2972 || (base
!= arg_pointer_rtx
2973 && indx
!= arg_pointer_rtx
2974 && base
!= return_address_pointer_rtx
2975 && indx
!= return_address_pointer_rtx
2976 && base
!= frame_pointer_rtx
2977 && indx
!= frame_pointer_rtx
2978 && base
!= virtual_stack_vars_rtx
2979 && indx
!= virtual_stack_vars_rtx
))
2980 if (!DISP_IN_RANGE (offset
))
2985 /* All the special cases are pointers. */
2988 /* In the small-PIC case, the linker converts @GOT
2989 and @GOTNTPOFF offsets to possible displacements. */
2990 if (GET_CODE (disp
) == UNSPEC
2991 && (XINT (disp
, 1) == UNSPEC_GOT
2992 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2998 /* Accept pool label offsets. */
2999 else if (GET_CODE (disp
) == UNSPEC
3000 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
3003 /* Accept literal pool references. */
3004 else if (GET_CODE (disp
) == UNSPEC
3005 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
3007 /* In case CSE pulled a non literal pool reference out of
3008 the pool we have to reject the address. This is
3009 especially important when loading the GOT pointer on non
3010 zarch CPUs. In this case the literal pool contains an lt
3011 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
3012 will most likely exceed the displacement. */
3013 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
3014 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
3017 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
3020 /* If we have an offset, make sure it does not
3021 exceed the size of the constant pool entry.
3022 Otherwise we might generate an out-of-range
3023 displacement for the base register form. */
3024 rtx sym
= XVECEXP (disp
, 0, 0);
3025 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
3028 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
3043 out
->disp
= orig_disp
;
3044 out
->pointer
= pointer
;
3045 out
->literal_pool
= literal_pool
;
3051 /* Decompose a RTL expression OP for an address style operand into its
3052 components, and return the base register in BASE and the offset in
3053 OFFSET. While OP looks like an address it is never supposed to be
3056 Return true if OP is a valid address operand, false if not. */
3059 s390_decompose_addrstyle_without_index (rtx op
, rtx
*base
,
3060 HOST_WIDE_INT
*offset
)
3064 /* We can have an integer constant, an address register,
3065 or a sum of the two. */
3066 if (CONST_SCALAR_INT_P (op
))
3071 if (op
&& GET_CODE (op
) == PLUS
&& CONST_SCALAR_INT_P (XEXP (op
, 1)))
3076 while (op
&& GET_CODE (op
) == SUBREG
)
3077 op
= SUBREG_REG (op
);
3079 if (op
&& GET_CODE (op
) != REG
)
3084 if (off
== NULL_RTX
)
3086 else if (CONST_INT_P (off
))
3087 *offset
= INTVAL (off
);
3088 else if (CONST_WIDE_INT_P (off
))
3089 /* The offset will anyway be cut down to 12 bits so take just
3090 the lowest order chunk of the wide int. */
3091 *offset
= CONST_WIDE_INT_ELT (off
, 0);
3102 /* Return true if CODE is a valid address without index. */
3105 s390_legitimate_address_without_index_p (rtx op
)
3107 struct s390_address addr
;
3109 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
3118 /* Return TRUE if ADDR is an operand valid for a load/store relative
3119 instruction. Be aware that the alignment of the operand needs to
3120 be checked separately.
3121 Valid addresses are single references or a sum of a reference and a
3122 constant integer. Return these parts in SYMREF and ADDEND. You can
3123 pass NULL in REF and/or ADDEND if you are not interested in these
3127 s390_loadrelative_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
3129 HOST_WIDE_INT tmpaddend
= 0;
3131 if (GET_CODE (addr
) == CONST
)
3132 addr
= XEXP (addr
, 0);
3134 if (GET_CODE (addr
) == PLUS
)
3136 if (!CONST_INT_P (XEXP (addr
, 1)))
3139 tmpaddend
= INTVAL (XEXP (addr
, 1));
3140 addr
= XEXP (addr
, 0);
3143 if (GET_CODE (addr
) == SYMBOL_REF
3144 || (GET_CODE (addr
) == UNSPEC
3145 && (XINT (addr
, 1) == UNSPEC_GOTENT
3146 || XINT (addr
, 1) == UNSPEC_PLT
)))
3151 *addend
= tmpaddend
;
3158 /* Return true if the address in OP is valid for constraint letter C
3159 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
3160 pool MEMs should be accepted. Only the Q, R, S, T constraint
3161 letters are allowed for C. */
3164 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
3167 struct s390_address addr
;
3168 bool decomposed
= false;
3170 if (!address_operand (op
, GET_MODE (op
)))
3173 /* This check makes sure that no symbolic address (except literal
3174 pool references) are accepted by the R or T constraints. */
3175 if (s390_loadrelative_operand_p (op
, &symref
, NULL
)
3177 || !SYMBOL_REF_P (symref
)
3178 || !CONSTANT_POOL_ADDRESS_P (symref
)))
3181 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
3184 if (!s390_decompose_address (op
, &addr
))
3186 if (addr
.literal_pool
)
3191 /* With reload, we sometimes get intermediate address forms that are
3192 actually invalid as-is, but we need to accept them in the most
3193 generic cases below ('R' or 'T'), since reload will in fact fix
3194 them up. LRA behaves differently here; we never see such forms,
3195 but on the other hand, we need to strictly reject every invalid
3196 address form. After both reload and LRA invalid address forms
3197 must be rejected, because nothing will fix them up later. Perform
3198 this check right up front. */
3199 if (lra_in_progress
|| reload_completed
)
3201 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3208 case 'Q': /* no index short displacement */
3209 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3213 if (!s390_short_displacement (addr
.disp
))
3217 case 'R': /* with index short displacement */
3218 if (TARGET_LONG_DISPLACEMENT
)
3220 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3222 if (!s390_short_displacement (addr
.disp
))
3225 /* Any invalid address here will be fixed up by reload,
3226 so accept it for the most generic constraint. */
3229 case 'S': /* no index long displacement */
3230 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3236 case 'T': /* with index long displacement */
3237 /* Any invalid address here will be fixed up by reload,
3238 so accept it for the most generic constraint. */
3248 /* Evaluates constraint strings described by the regular expression
3249 ([A|B|Z](Q|R|S|T))|Y and returns 1 if OP is a valid operand for
3250 the constraint given in STR, or 0 else. */
3253 s390_mem_constraint (const char *str
, rtx op
)
3260 /* Check for offsettable variants of memory constraints. */
3261 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
3263 if ((reload_completed
|| reload_in_progress
)
3264 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
3266 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
3268 /* Check for non-literal-pool variants of memory constraints. */
3271 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
3276 if (GET_CODE (op
) != MEM
)
3278 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
3280 /* Simply check for the basic form of a shift count. Reload will
3281 take care of making sure we have a proper base register. */
3282 if (!s390_decompose_addrstyle_without_index (op
, NULL
, NULL
))
3286 return s390_check_qrst_address (str
[1], op
, true);
3294 /* Evaluates constraint strings starting with letter O. Input
3295 parameter C is the second letter following the "O" in the constraint
3296 string. Returns 1 if VALUE meets the respective constraint and 0
3300 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
3308 return trunc_int_for_mode (value
, SImode
) == value
;
3312 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
3315 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
3323 /* Evaluates constraint strings starting with letter N. Parameter STR
3324 contains the letters following letter "N" in the constraint string.
3325 Returns true if VALUE matches the constraint. */
3328 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
3330 machine_mode mode
, part_mode
;
3332 int part
, part_goal
;
3338 part_goal
= str
[0] - '0';
3382 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
3385 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
3388 if (part_goal
!= -1 && part_goal
!= part
)
3395 /* Returns true if the input parameter VALUE is a float zero. */
3398 s390_float_const_zero_p (rtx value
)
3400 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
3401 && value
== CONST0_RTX (GET_MODE (value
)));
3404 /* Implement TARGET_REGISTER_MOVE_COST. */
3407 s390_register_move_cost (machine_mode mode
,
3408 reg_class_t from
, reg_class_t to
)
3410 /* On s390, copy between fprs and gprs is expensive. */
3412 /* It becomes somewhat faster having ldgr/lgdr. */
3413 if (TARGET_Z10
&& GET_MODE_SIZE (mode
) == 8)
3415 /* ldgr is single cycle. */
3416 if (reg_classes_intersect_p (from
, GENERAL_REGS
)
3417 && reg_classes_intersect_p (to
, FP_REGS
))
3419 /* lgdr needs 3 cycles. */
3420 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
3421 && reg_classes_intersect_p (from
, FP_REGS
))
3425 /* Otherwise copying is done via memory. */
3426 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
3427 && reg_classes_intersect_p (to
, FP_REGS
))
3428 || (reg_classes_intersect_p (from
, FP_REGS
)
3429 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
3432 /* We usually do not want to copy via CC. */
3433 if (reg_classes_intersect_p (from
, CC_REGS
)
3434 || reg_classes_intersect_p (to
, CC_REGS
))
3440 /* Implement TARGET_MEMORY_MOVE_COST. */
3443 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3444 reg_class_t rclass ATTRIBUTE_UNUSED
,
3445 bool in ATTRIBUTE_UNUSED
)
3450 /* Compute a (partial) cost for rtx X. Return true if the complete
3451 cost has been computed, and false if subexpressions should be
3452 scanned. In either case, *TOTAL contains the cost result. The
3453 initial value of *TOTAL is the default value computed by
3454 rtx_cost. It may be left unmodified. OUTER_CODE contains the
3455 code of the superexpression of x. */
3458 s390_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
3459 int opno ATTRIBUTE_UNUSED
,
3460 int *total
, bool speed ATTRIBUTE_UNUSED
)
3462 int code
= GET_CODE (x
);
3470 case CONST_WIDE_INT
:
3477 /* Without this a conditional move instruction would be
3478 accounted as 3 * COSTS_N_INSNS (set, if_then_else,
3479 comparison operator). That's a bit pessimistic. */
3481 if (!TARGET_Z196
|| GET_CODE (SET_SRC (x
)) != IF_THEN_ELSE
)
3484 rtx cond
= XEXP (SET_SRC (x
), 0);
3486 if (!CC_REG_P (XEXP (cond
, 0)) || !CONST_INT_P (XEXP (cond
, 1)))
3489 /* It is going to be a load/store on condition. Make it
3490 slightly more expensive than a normal load. */
3491 *total
= COSTS_N_INSNS (1) + 1;
3493 rtx dst
= SET_DEST (x
);
3494 rtx then
= XEXP (SET_SRC (x
), 1);
3495 rtx els
= XEXP (SET_SRC (x
), 2);
3497 /* It is a real IF-THEN-ELSE. An additional move will be
3498 needed to implement that. */
3499 if (reload_completed
3500 && !rtx_equal_p (dst
, then
)
3501 && !rtx_equal_p (dst
, els
))
3502 *total
+= COSTS_N_INSNS (1) / 2;
3504 /* A minor penalty for constants we cannot directly handle. */
3505 if ((CONST_INT_P (then
) || CONST_INT_P (els
))
3506 && (!TARGET_Z13
|| MEM_P (dst
)
3507 || (CONST_INT_P (then
) && !satisfies_constraint_K (then
))
3508 || (CONST_INT_P (els
) && !satisfies_constraint_K (els
))))
3509 *total
+= COSTS_N_INSNS (1) / 2;
3511 /* A store on condition can only handle register src operands. */
3512 if (MEM_P (dst
) && (!REG_P (then
) || !REG_P (els
)))
3513 *total
+= COSTS_N_INSNS (1) / 2;
3519 if (GET_CODE (XEXP (x
, 0)) == AND
3520 && GET_CODE (XEXP (x
, 1)) == ASHIFT
3521 && REG_P (XEXP (XEXP (x
, 0), 0))
3522 && REG_P (XEXP (XEXP (x
, 1), 0))
3523 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3524 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
3525 && (UINTVAL (XEXP (XEXP (x
, 0), 1)) ==
3526 (HOST_WIDE_INT_1U
<< UINTVAL (XEXP (XEXP (x
, 1), 1))) - 1))
3528 *total
= COSTS_N_INSNS (2);
3532 /* ~AND on a 128 bit mode. This can be done using a vector
3535 && GET_CODE (XEXP (x
, 0)) == NOT
3536 && GET_CODE (XEXP (x
, 1)) == NOT
3537 && REG_P (XEXP (XEXP (x
, 0), 0))
3538 && REG_P (XEXP (XEXP (x
, 1), 0))
3539 && GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0), 0))) == 16
3540 && s390_hard_regno_mode_ok (VR0_REGNUM
,
3541 GET_MODE (XEXP (XEXP (x
, 0), 0))))
3543 *total
= COSTS_N_INSNS (1);
3556 *total
= COSTS_N_INSNS (1);
3561 *total
= COSTS_N_INSNS (1);
3569 rtx left
= XEXP (x
, 0);
3570 rtx right
= XEXP (x
, 1);
3571 if (GET_CODE (right
) == CONST_INT
3572 && CONST_OK_FOR_K (INTVAL (right
)))
3573 *total
= s390_cost
->mhi
;
3574 else if (GET_CODE (left
) == SIGN_EXTEND
)
3575 *total
= s390_cost
->mh
;
3577 *total
= s390_cost
->ms
; /* msr, ms, msy */
3582 rtx left
= XEXP (x
, 0);
3583 rtx right
= XEXP (x
, 1);
3586 if (GET_CODE (right
) == CONST_INT
3587 && CONST_OK_FOR_K (INTVAL (right
)))
3588 *total
= s390_cost
->mghi
;
3589 else if (GET_CODE (left
) == SIGN_EXTEND
)
3590 *total
= s390_cost
->msgf
;
3592 *total
= s390_cost
->msg
; /* msgr, msg */
3594 else /* TARGET_31BIT */
3596 if (GET_CODE (left
) == SIGN_EXTEND
3597 && GET_CODE (right
) == SIGN_EXTEND
)
3598 /* mulsidi case: mr, m */
3599 *total
= s390_cost
->m
;
3600 else if (GET_CODE (left
) == ZERO_EXTEND
3601 && GET_CODE (right
) == ZERO_EXTEND
)
3602 /* umulsidi case: ml, mlr */
3603 *total
= s390_cost
->ml
;
3605 /* Complex calculation is required. */
3606 *total
= COSTS_N_INSNS (40);
3612 *total
= s390_cost
->mult_df
;
3615 *total
= s390_cost
->mxbr
;
3626 *total
= s390_cost
->madbr
;
3629 *total
= s390_cost
->maebr
;
3634 /* Negate in the third argument is free: FMSUB. */
3635 if (GET_CODE (XEXP (x
, 2)) == NEG
)
3637 *total
+= (rtx_cost (XEXP (x
, 0), mode
, FMA
, 0, speed
)
3638 + rtx_cost (XEXP (x
, 1), mode
, FMA
, 1, speed
)
3639 + rtx_cost (XEXP (XEXP (x
, 2), 0), mode
, FMA
, 2, speed
));
3646 if (mode
== TImode
) /* 128 bit division */
3647 *total
= s390_cost
->dlgr
;
3648 else if (mode
== DImode
)
3650 rtx right
= XEXP (x
, 1);
3651 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3652 *total
= s390_cost
->dlr
;
3653 else /* 64 by 64 bit division */
3654 *total
= s390_cost
->dlgr
;
3656 else if (mode
== SImode
) /* 32 bit division */
3657 *total
= s390_cost
->dlr
;
3664 rtx right
= XEXP (x
, 1);
3665 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3667 *total
= s390_cost
->dsgfr
;
3669 *total
= s390_cost
->dr
;
3670 else /* 64 by 64 bit division */
3671 *total
= s390_cost
->dsgr
;
3673 else if (mode
== SImode
) /* 32 bit division */
3674 *total
= s390_cost
->dlr
;
3675 else if (mode
== SFmode
)
3677 *total
= s390_cost
->debr
;
3679 else if (mode
== DFmode
)
3681 *total
= s390_cost
->ddbr
;
3683 else if (mode
== TFmode
)
3685 *total
= s390_cost
->dxbr
;
3691 *total
= s390_cost
->sqebr
;
3692 else if (mode
== DFmode
)
3693 *total
= s390_cost
->sqdbr
;
3695 *total
= s390_cost
->sqxbr
;
3700 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
3701 || outer_code
== PLUS
|| outer_code
== MINUS
3702 || outer_code
== COMPARE
)
3707 *total
= COSTS_N_INSNS (1);
3708 if (GET_CODE (XEXP (x
, 0)) == AND
3709 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3710 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
3712 rtx op0
= XEXP (XEXP (x
, 0), 0);
3713 rtx op1
= XEXP (XEXP (x
, 0), 1);
3714 rtx op2
= XEXP (x
, 1);
3716 if (memory_operand (op0
, GET_MODE (op0
))
3717 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
3719 if (register_operand (op0
, GET_MODE (op0
))
3720 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
3730 /* Return the cost of an address rtx ADDR. */
3733 s390_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
3734 addr_space_t as ATTRIBUTE_UNUSED
,
3735 bool speed ATTRIBUTE_UNUSED
)
3737 struct s390_address ad
;
3738 if (!s390_decompose_address (addr
, &ad
))
3741 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
3744 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3746 s390_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
3748 int misalign ATTRIBUTE_UNUSED
)
3750 switch (type_of_cost
)
3758 case vector_gather_load
:
3759 case vector_scatter_store
:
3762 case cond_branch_not_taken
:
3764 case vec_promote_demote
:
3765 case unaligned_load
:
3766 case unaligned_store
:
3769 case cond_branch_taken
:
3773 return TYPE_VECTOR_SUBPARTS (vectype
) - 1;
3780 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
3781 otherwise return 0. */
3784 tls_symbolic_operand (rtx op
)
3786 if (GET_CODE (op
) != SYMBOL_REF
)
3788 return SYMBOL_REF_TLS_MODEL (op
);
3791 /* Split DImode access register reference REG (on 64-bit) into its constituent
3792 low and high parts, and store them into LO and HI. Note that gen_lowpart/
3793 gen_highpart cannot be used as they assume all registers are word-sized,
3794 while our access registers have only half that size. */
3797 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
3799 gcc_assert (TARGET_64BIT
);
3800 gcc_assert (ACCESS_REG_P (reg
));
3801 gcc_assert (GET_MODE (reg
) == DImode
);
3802 gcc_assert (!(REGNO (reg
) & 1));
3804 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
3805 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
3808 /* Return true if OP contains a symbol reference */
3811 symbolic_reference_mentioned_p (rtx op
)
3816 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
3819 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3820 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3826 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3827 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3831 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
3838 /* Return true if OP contains a reference to a thread-local symbol. */
3841 tls_symbolic_reference_mentioned_p (rtx op
)
3846 if (GET_CODE (op
) == SYMBOL_REF
)
3847 return tls_symbolic_operand (op
);
3849 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3850 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3856 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3857 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3861 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
3869 /* Return true if OP is a legitimate general operand when
3870 generating PIC code. It is given that flag_pic is on
3871 and that OP satisfies CONSTANT_P. */
3874 legitimate_pic_operand_p (rtx op
)
3876 /* Accept all non-symbolic constants. */
3877 if (!SYMBOLIC_CONST (op
))
3880 /* Accept addresses that can be expressed relative to (pc). */
3881 if (larl_operand (op
, VOIDmode
))
3884 /* Reject everything else; must be handled
3885 via emit_symbolic_move. */
3889 /* Returns true if the constant value OP is a legitimate general operand.
3890 It is given that OP satisfies CONSTANT_P. */
3893 s390_legitimate_constant_p (machine_mode mode
, rtx op
)
3895 if (TARGET_VX
&& VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
3897 if (GET_MODE_SIZE (mode
) != 16)
3900 if (!satisfies_constraint_j00 (op
)
3901 && !satisfies_constraint_jm1 (op
)
3902 && !satisfies_constraint_jKK (op
)
3903 && !satisfies_constraint_jxx (op
)
3904 && !satisfies_constraint_jyy (op
))
3908 /* Accept all non-symbolic constants. */
3909 if (!SYMBOLIC_CONST (op
))
3912 /* Accept immediate LARL operands. */
3913 if (larl_operand (op
, mode
))
3916 /* Thread-local symbols are never legal constants. This is
3917 so that emit_call knows that computing such addresses
3918 might require a function call. */
3919 if (TLS_SYMBOLIC_CONST (op
))
3922 /* In the PIC case, symbolic constants must *not* be
3923 forced into the literal pool. We accept them here,
3924 so that they will be handled by emit_symbolic_move. */
3928 /* All remaining non-PIC symbolic constants are
3929 forced into the literal pool. */
3933 /* Determine if it's legal to put X into the constant pool. This
3934 is not possible if X contains the address of a symbol that is
3935 not constant (TLS) or not known at final link time (PIC). */
3938 s390_cannot_force_const_mem (machine_mode mode
, rtx x
)
3940 switch (GET_CODE (x
))
3944 case CONST_WIDE_INT
:
3946 /* Accept all non-symbolic constants. */
3950 /* Labels are OK iff we are non-PIC. */
3951 return flag_pic
!= 0;
3954 /* 'Naked' TLS symbol references are never OK,
3955 non-TLS symbols are OK iff we are non-PIC. */
3956 if (tls_symbolic_operand (x
))
3959 return flag_pic
!= 0;
3962 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
3965 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
3966 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
3969 switch (XINT (x
, 1))
3971 /* Only lt-relative or GOT-relative UNSPECs are OK. */
3972 case UNSPEC_LTREL_OFFSET
:
3980 case UNSPEC_GOTNTPOFF
:
3981 case UNSPEC_INDNTPOFF
:
3984 /* If the literal pool shares the code section, be put
3985 execute template placeholders into the pool as well. */
3997 /* Returns true if the constant value OP is a legitimate general
3998 operand during and after reload. The difference to
3999 legitimate_constant_p is that this function will not accept
4000 a constant that would need to be forced to the literal pool
4001 before it can be used as operand.
4002 This function accepts all constants which can be loaded directly
4006 legitimate_reload_constant_p (rtx op
)
4008 /* Accept la(y) operands. */
4009 if (GET_CODE (op
) == CONST_INT
4010 && DISP_IN_RANGE (INTVAL (op
)))
4013 /* Accept l(g)hi/l(g)fi operands. */
4014 if (GET_CODE (op
) == CONST_INT
4015 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
4018 /* Accept lliXX operands. */
4020 && GET_CODE (op
) == CONST_INT
4021 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
4022 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
4026 && GET_CODE (op
) == CONST_INT
4027 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
4028 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
4031 /* Accept larl operands. */
4032 if (larl_operand (op
, VOIDmode
))
4035 /* Accept floating-point zero operands that fit into a single GPR. */
4036 if (GET_CODE (op
) == CONST_DOUBLE
4037 && s390_float_const_zero_p (op
)
4038 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
4041 /* Accept double-word operands that can be split. */
4042 if (GET_CODE (op
) == CONST_WIDE_INT
4043 || (GET_CODE (op
) == CONST_INT
4044 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
)))
4046 machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
4047 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
4048 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
4049 return legitimate_reload_constant_p (hi
)
4050 && legitimate_reload_constant_p (lo
);
4053 /* Everything else cannot be handled without reload. */
4057 /* Returns true if the constant value OP is a legitimate fp operand
4058 during and after reload.
4059 This function accepts all constants which can be loaded directly
4063 legitimate_reload_fp_constant_p (rtx op
)
4065 /* Accept floating-point zero operands if the load zero instruction
4066 can be used. Prior to z196 the load fp zero instruction caused a
4067 performance penalty if the result is used as BFP number. */
4069 && GET_CODE (op
) == CONST_DOUBLE
4070 && s390_float_const_zero_p (op
))
4076 /* Returns true if the constant value OP is a legitimate vector operand
4077 during and after reload.
4078 This function accepts all constants which can be loaded directly
4082 legitimate_reload_vector_constant_p (rtx op
)
4084 if (TARGET_VX
&& GET_MODE_SIZE (GET_MODE (op
)) == 16
4085 && (satisfies_constraint_j00 (op
)
4086 || satisfies_constraint_jm1 (op
)
4087 || satisfies_constraint_jKK (op
)
4088 || satisfies_constraint_jxx (op
)
4089 || satisfies_constraint_jyy (op
)))
4095 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
4096 return the class of reg to actually use. */
4099 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
4101 switch (GET_CODE (op
))
4103 /* Constants we cannot reload into general registers
4104 must be forced into the literal pool. */
4108 case CONST_WIDE_INT
:
4109 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
4110 && legitimate_reload_constant_p (op
))
4111 return GENERAL_REGS
;
4112 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
4113 && legitimate_reload_constant_p (op
))
4115 else if (reg_class_subset_p (FP_REGS
, rclass
)
4116 && legitimate_reload_fp_constant_p (op
))
4118 else if (reg_class_subset_p (VEC_REGS
, rclass
)
4119 && legitimate_reload_vector_constant_p (op
))
4124 /* If a symbolic constant or a PLUS is reloaded,
4125 it is most likely being used as an address, so
4126 prefer ADDR_REGS. If 'class' is not a superset
4127 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
4129 /* Symrefs cannot be pushed into the literal pool with -fPIC
4130 so we *MUST NOT* return NO_REGS for these cases
4131 (s390_cannot_force_const_mem will return true).
4133 On the other hand we MUST return NO_REGS for symrefs with
4134 invalid addend which might have been pushed to the literal
4135 pool (no -fPIC). Usually we would expect them to be
4136 handled via secondary reload but this does not happen if
4137 they are used as literal pool slot replacement in reload
4138 inheritance (see emit_input_reload_insns). */
4139 if (GET_CODE (XEXP (op
, 0)) == PLUS
4140 && GET_CODE (XEXP (XEXP(op
, 0), 0)) == SYMBOL_REF
4141 && GET_CODE (XEXP (XEXP(op
, 0), 1)) == CONST_INT
)
4143 if (flag_pic
&& reg_class_subset_p (ADDR_REGS
, rclass
))
4151 if (!legitimate_reload_constant_p (op
))
4155 /* load address will be used. */
4156 if (reg_class_subset_p (ADDR_REGS
, rclass
))
4168 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
4169 multiple of ALIGNMENT and the SYMBOL_REF being naturally
4173 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
4175 HOST_WIDE_INT addend
;
4178 /* The "required alignment" might be 0 (e.g. for certain structs
4179 accessed via BLKmode). Early abort in this case, as well as when
4180 an alignment > 8 is required. */
4181 if (alignment
< 2 || alignment
> 8)
4184 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
4187 if (addend
& (alignment
- 1))
4190 if (GET_CODE (symref
) == SYMBOL_REF
)
4192 /* s390_encode_section_info is not called for anchors, since they don't
4193 have corresponding VAR_DECLs. Therefore, we cannot rely on
4194 SYMBOL_FLAG_NOTALIGN{2,4,8}_P returning useful information. */
4195 if (SYMBOL_REF_ANCHOR_P (symref
))
4197 HOST_WIDE_INT block_offset
= SYMBOL_REF_BLOCK_OFFSET (symref
);
4198 unsigned int block_alignment
= (SYMBOL_REF_BLOCK (symref
)->alignment
4201 gcc_assert (block_offset
>= 0);
4202 return ((block_offset
& (alignment
- 1)) == 0
4203 && block_alignment
>= alignment
);
4206 /* We have load-relative instructions for 2-byte, 4-byte, and
4207 8-byte alignment so allow only these. */
4210 case 8: return !SYMBOL_FLAG_NOTALIGN8_P (symref
);
4211 case 4: return !SYMBOL_FLAG_NOTALIGN4_P (symref
);
4212 case 2: return !SYMBOL_FLAG_NOTALIGN2_P (symref
);
4213 default: return false;
4217 if (GET_CODE (symref
) == UNSPEC
4218 && alignment
<= UNITS_PER_LONG
)
4224 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
4225 operand SCRATCH is used to reload the even part of the address and
4229 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
4231 HOST_WIDE_INT addend
;
4234 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
4238 /* Easy case. The addend is even so larl will do fine. */
4239 emit_move_insn (reg
, addr
);
4242 /* We can leave the scratch register untouched if the target
4243 register is a valid base register. */
4244 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
4245 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
4248 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
4249 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
4252 emit_move_insn (scratch
,
4253 gen_rtx_CONST (Pmode
,
4254 gen_rtx_PLUS (Pmode
, symref
,
4255 GEN_INT (addend
- 1))));
4257 emit_move_insn (scratch
, symref
);
4259 /* Increment the address using la in order to avoid clobbering cc. */
4260 s390_load_address (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
4264 /* Generate what is necessary to move between REG and MEM using
4265 SCRATCH. The direction is given by TOMEM. */
4268 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
4270 /* Reload might have pulled a constant out of the literal pool.
4271 Force it back in. */
4272 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
4273 || GET_CODE (mem
) == CONST_WIDE_INT
4274 || GET_CODE (mem
) == CONST_VECTOR
4275 || GET_CODE (mem
) == CONST
)
4276 mem
= force_const_mem (GET_MODE (reg
), mem
);
4278 gcc_assert (MEM_P (mem
));
4280 /* For a load from memory we can leave the scratch register
4281 untouched if the target register is a valid base register. */
4283 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
4284 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
4285 && GET_MODE (reg
) == GET_MODE (scratch
))
4288 /* Load address into scratch register. Since we can't have a
4289 secondary reload for a secondary reload we have to cover the case
4290 where larl would need a secondary reload here as well. */
4291 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
4293 /* Now we can use a standard load/store to do the move. */
4295 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
4297 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
4300 /* Inform reload about cases where moving X with a mode MODE to a register in
4301 RCLASS requires an extra scratch or immediate register. Return the class
4302 needed for the immediate register. */
4305 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
4306 machine_mode mode
, secondary_reload_info
*sri
)
4308 enum reg_class rclass
= (enum reg_class
) rclass_i
;
4310 /* Intermediate register needed. */
4311 if (reg_classes_intersect_p (CC_REGS
, rclass
))
4312 return GENERAL_REGS
;
4316 /* The vst/vl vector move instructions allow only for short
4319 && GET_CODE (XEXP (x
, 0)) == PLUS
4320 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4321 && !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x
, 0), 1)))
4322 && reg_class_subset_p (rclass
, VEC_REGS
)
4323 && (!reg_class_subset_p (rclass
, FP_REGS
)
4324 || (GET_MODE_SIZE (mode
) > 8
4325 && s390_class_max_nregs (FP_REGS
, mode
) == 1)))
4328 sri
->icode
= (TARGET_64BIT
?
4329 CODE_FOR_reloaddi_la_in
:
4330 CODE_FOR_reloadsi_la_in
);
4332 sri
->icode
= (TARGET_64BIT
?
4333 CODE_FOR_reloaddi_la_out
:
4334 CODE_FOR_reloadsi_la_out
);
4340 HOST_WIDE_INT offset
;
4343 /* On z10 several optimizer steps may generate larl operands with
4346 && s390_loadrelative_operand_p (x
, &symref
, &offset
)
4348 && !SYMBOL_FLAG_NOTALIGN2_P (symref
)
4349 && (offset
& 1) == 1)
4350 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
4351 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
4353 /* Handle all the (mem (symref)) accesses we cannot use the z10
4354 instructions for. */
4356 && s390_loadrelative_operand_p (XEXP (x
, 0), NULL
, NULL
)
4358 || !reg_class_subset_p (rclass
, GENERAL_REGS
)
4359 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4360 || !s390_check_symref_alignment (XEXP (x
, 0),
4361 GET_MODE_SIZE (mode
))))
4363 #define __SECONDARY_RELOAD_CASE(M,m) \
4366 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
4367 CODE_FOR_reload##m##di_tomem_z10; \
4369 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
4370 CODE_FOR_reload##m##si_tomem_z10; \
4373 switch (GET_MODE (x
))
4375 __SECONDARY_RELOAD_CASE (QI
, qi
);
4376 __SECONDARY_RELOAD_CASE (HI
, hi
);
4377 __SECONDARY_RELOAD_CASE (SI
, si
);
4378 __SECONDARY_RELOAD_CASE (DI
, di
);
4379 __SECONDARY_RELOAD_CASE (TI
, ti
);
4380 __SECONDARY_RELOAD_CASE (SF
, sf
);
4381 __SECONDARY_RELOAD_CASE (DF
, df
);
4382 __SECONDARY_RELOAD_CASE (TF
, tf
);
4383 __SECONDARY_RELOAD_CASE (SD
, sd
);
4384 __SECONDARY_RELOAD_CASE (DD
, dd
);
4385 __SECONDARY_RELOAD_CASE (TD
, td
);
4386 __SECONDARY_RELOAD_CASE (V1QI
, v1qi
);
4387 __SECONDARY_RELOAD_CASE (V2QI
, v2qi
);
4388 __SECONDARY_RELOAD_CASE (V4QI
, v4qi
);
4389 __SECONDARY_RELOAD_CASE (V8QI
, v8qi
);
4390 __SECONDARY_RELOAD_CASE (V16QI
, v16qi
);
4391 __SECONDARY_RELOAD_CASE (V1HI
, v1hi
);
4392 __SECONDARY_RELOAD_CASE (V2HI
, v2hi
);
4393 __SECONDARY_RELOAD_CASE (V4HI
, v4hi
);
4394 __SECONDARY_RELOAD_CASE (V8HI
, v8hi
);
4395 __SECONDARY_RELOAD_CASE (V1SI
, v1si
);
4396 __SECONDARY_RELOAD_CASE (V2SI
, v2si
);
4397 __SECONDARY_RELOAD_CASE (V4SI
, v4si
);
4398 __SECONDARY_RELOAD_CASE (V1DI
, v1di
);
4399 __SECONDARY_RELOAD_CASE (V2DI
, v2di
);
4400 __SECONDARY_RELOAD_CASE (V1TI
, v1ti
);
4401 __SECONDARY_RELOAD_CASE (V1SF
, v1sf
);
4402 __SECONDARY_RELOAD_CASE (V2SF
, v2sf
);
4403 __SECONDARY_RELOAD_CASE (V4SF
, v4sf
);
4404 __SECONDARY_RELOAD_CASE (V1DF
, v1df
);
4405 __SECONDARY_RELOAD_CASE (V2DF
, v2df
);
4406 __SECONDARY_RELOAD_CASE (V1TF
, v1tf
);
4410 #undef __SECONDARY_RELOAD_CASE
4414 /* We need a scratch register when loading a PLUS expression which
4415 is not a legitimate operand of the LOAD ADDRESS instruction. */
4416 /* LRA can deal with transformation of plus op very well -- so we
4417 don't need to prompt LRA in this case. */
4418 if (! lra_in_progress
&& in_p
&& s390_plus_operand (x
, mode
))
4419 sri
->icode
= (TARGET_64BIT
?
4420 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
4422 /* Performing a multiword move from or to memory we have to make sure the
4423 second chunk in memory is addressable without causing a displacement
4424 overflow. If that would be the case we calculate the address in
4425 a scratch register. */
4427 && GET_CODE (XEXP (x
, 0)) == PLUS
4428 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4429 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
4430 + GET_MODE_SIZE (mode
) - 1))
4432 /* For GENERAL_REGS a displacement overflow is no problem if occurring
4433 in a s_operand address since we may fallback to lm/stm. So we only
4434 have to care about overflows in the b+i+d case. */
4435 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
4436 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
4437 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4438 /* For FP_REGS no lm/stm is available so this check is triggered
4439 for displacement overflows in b+i+d and b+d like addresses. */
4440 || (reg_classes_intersect_p (FP_REGS
, rclass
)
4441 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
4444 sri
->icode
= (TARGET_64BIT
?
4445 CODE_FOR_reloaddi_la_in
:
4446 CODE_FOR_reloadsi_la_in
);
4448 sri
->icode
= (TARGET_64BIT
?
4449 CODE_FOR_reloaddi_la_out
:
4450 CODE_FOR_reloadsi_la_out
);
4454 /* A scratch address register is needed when a symbolic constant is
4455 copied to r0 compiling with -fPIC. In other cases the target
4456 register might be used as temporary (see legitimize_pic_address). */
4457 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
4458 sri
->icode
= (TARGET_64BIT
?
4459 CODE_FOR_reloaddi_PIC_addr
:
4460 CODE_FOR_reloadsi_PIC_addr
);
4462 /* Either scratch or no register needed. */
4466 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4468 We need secondary memory to move data between GPRs and FPRs.
4470 - With DFP the ldgr lgdr instructions are available. Due to the
4471 different alignment we cannot use them for SFmode. For 31 bit a
4472 64 bit value in GPR would be a register pair so here we still
4473 need to go via memory.
4475 - With z13 we can do the SF/SImode moves with vlgvf. Due to the
4476 overlapping of FPRs and VRs we still disallow TF/TD modes to be
4477 in full VRs so as before also on z13 we do these moves via
4480 FIXME: Should we try splitting it into two vlgvg's/vlvg's instead? */
4483 s390_secondary_memory_needed (machine_mode mode
,
4484 reg_class_t class1
, reg_class_t class2
)
4486 return (((reg_classes_intersect_p (class1
, VEC_REGS
)
4487 && reg_classes_intersect_p (class2
, GENERAL_REGS
))
4488 || (reg_classes_intersect_p (class1
, GENERAL_REGS
)
4489 && reg_classes_intersect_p (class2
, VEC_REGS
)))
4490 && (!TARGET_DFP
|| !TARGET_64BIT
|| GET_MODE_SIZE (mode
) != 8)
4491 && (!TARGET_VX
|| (SCALAR_FLOAT_MODE_P (mode
)
4492 && GET_MODE_SIZE (mode
) > 8)));
4495 /* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
4497 get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
4498 because the movsi and movsf patterns don't handle r/f moves. */
4501 s390_secondary_memory_needed_mode (machine_mode mode
)
4503 if (GET_MODE_BITSIZE (mode
) < 32)
4504 return mode_for_size (32, GET_MODE_CLASS (mode
), 0).require ();
4508 /* Generate code to load SRC, which is PLUS that is not a
4509 legitimate operand for the LA instruction, into TARGET.
4510 SCRATCH may be used as scratch register. */
4513 s390_expand_plus_operand (rtx target
, rtx src
,
4517 struct s390_address ad
;
4519 /* src must be a PLUS; get its two operands. */
4520 gcc_assert (GET_CODE (src
) == PLUS
);
4521 gcc_assert (GET_MODE (src
) == Pmode
);
4523 /* Check if any of the two operands is already scheduled
4524 for replacement by reload. This can happen e.g. when
4525 float registers occur in an address. */
4526 sum1
= find_replacement (&XEXP (src
, 0));
4527 sum2
= find_replacement (&XEXP (src
, 1));
4528 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4530 /* If the address is already strictly valid, there's nothing to do. */
4531 if (!s390_decompose_address (src
, &ad
)
4532 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4533 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
4535 /* Otherwise, one of the operands cannot be an address register;
4536 we reload its value into the scratch register. */
4537 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
4539 emit_move_insn (scratch
, sum1
);
4542 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
4544 emit_move_insn (scratch
, sum2
);
4548 /* According to the way these invalid addresses are generated
4549 in reload.c, it should never happen (at least on s390) that
4550 *neither* of the PLUS components, after find_replacements
4551 was applied, is an address register. */
4552 if (sum1
== scratch
&& sum2
== scratch
)
4558 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4561 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
4562 is only ever performed on addresses, so we can mark the
4563 sum as legitimate for LA in any case. */
4564 s390_load_address (target
, src
);
4568 /* Return true if ADDR is a valid memory address.
4569 STRICT specifies whether strict register checking applies. */
4572 s390_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4574 struct s390_address ad
;
4577 && larl_operand (addr
, VOIDmode
)
4578 && (mode
== VOIDmode
4579 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
4582 if (!s390_decompose_address (addr
, &ad
))
4587 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4590 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
4596 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
4597 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
4601 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
4602 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
4608 /* Return true if OP is a valid operand for the LA instruction.
4609 In 31-bit, we need to prove that the result is used as an
4610 address, as LA performs only a 31-bit addition. */
4613 legitimate_la_operand_p (rtx op
)
4615 struct s390_address addr
;
4616 if (!s390_decompose_address (op
, &addr
))
4619 return (TARGET_64BIT
|| addr
.pointer
);
4622 /* Return true if it is valid *and* preferable to use LA to
4623 compute the sum of OP1 and OP2. */
4626 preferred_la_operand_p (rtx op1
, rtx op2
)
4628 struct s390_address addr
;
4630 if (op2
!= const0_rtx
)
4631 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
4633 if (!s390_decompose_address (op1
, &addr
))
4635 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
4637 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
4640 /* Avoid LA instructions with index (and base) register on z196 or
4641 later; it is preferable to use regular add instructions when
4642 possible. Starting with zEC12 the la with index register is
4643 "uncracked" again but still slower than a regular add. */
4644 if (addr
.indx
&& s390_tune
>= PROCESSOR_2817_Z196
)
4647 if (!TARGET_64BIT
&& !addr
.pointer
)
4653 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
4654 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
4660 /* Emit a forced load-address operation to load SRC into DST.
4661 This will use the LOAD ADDRESS instruction even in situations
4662 where legitimate_la_operand_p (SRC) returns false. */
4665 s390_load_address (rtx dst
, rtx src
)
4668 emit_move_insn (dst
, src
);
4670 emit_insn (gen_force_la_31 (dst
, src
));
4673 /* Return true if it ok to use SYMBOL_REF in a relative address. */
4676 s390_rel_address_ok_p (rtx symbol_ref
)
4680 if (symbol_ref
== s390_got_symbol () || CONSTANT_POOL_ADDRESS_P (symbol_ref
))
4683 decl
= SYMBOL_REF_DECL (symbol_ref
);
4685 if (!flag_pic
|| SYMBOL_REF_LOCAL_P (symbol_ref
))
4686 return (s390_pic_data_is_text_relative
4688 && TREE_CODE (decl
) == FUNCTION_DECL
));
4693 /* Return a legitimate reference for ORIG (an address) using the
4694 register REG. If REG is 0, a new pseudo is generated.
4696 There are two types of references that must be handled:
4698 1. Global data references must load the address from the GOT, via
4699 the PIC reg. An insn is emitted to do this load, and the reg is
4702 2. Static data references, constant pool addresses, and code labels
4703 compute the address as an offset from the GOT, whose base is in
4704 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
4705 differentiate them from global data objects. The returned
4706 address is the PIC reg + an unspec constant.
4708 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
4709 reg also appears in the address. */
4712 legitimize_pic_address (rtx orig
, rtx reg
)
4715 rtx addend
= const0_rtx
;
4718 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
4720 if (GET_CODE (addr
) == CONST
)
4721 addr
= XEXP (addr
, 0);
4723 if (GET_CODE (addr
) == PLUS
)
4725 addend
= XEXP (addr
, 1);
4726 addr
= XEXP (addr
, 0);
4729 if ((GET_CODE (addr
) == LABEL_REF
4730 || (SYMBOL_REF_P (addr
) && s390_rel_address_ok_p (addr
))
4731 || (GET_CODE (addr
) == UNSPEC
&&
4732 (XINT (addr
, 1) == UNSPEC_GOTENT
4733 || XINT (addr
, 1) == UNSPEC_PLT
)))
4734 && GET_CODE (addend
) == CONST_INT
)
4736 /* This can be locally addressed. */
4738 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
4739 rtx const_addr
= (GET_CODE (addr
) == UNSPEC
?
4740 gen_rtx_CONST (Pmode
, addr
) : addr
);
4742 if (larl_operand (const_addr
, VOIDmode
)
4743 && INTVAL (addend
) < HOST_WIDE_INT_1
<< 31
4744 && INTVAL (addend
) >= -(HOST_WIDE_INT_1
<< 31))
4746 if (INTVAL (addend
) & 1)
4748 /* LARL can't handle odd offsets, so emit a pair of LARL
4750 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4752 if (!DISP_IN_RANGE (INTVAL (addend
)))
4754 HOST_WIDE_INT even
= INTVAL (addend
) - 1;
4755 addr
= gen_rtx_PLUS (Pmode
, addr
, GEN_INT (even
));
4756 addr
= gen_rtx_CONST (Pmode
, addr
);
4757 addend
= const1_rtx
;
4760 emit_move_insn (temp
, addr
);
4761 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, addend
);
4765 s390_load_address (reg
, new_rtx
);
4771 /* If the offset is even, we can just use LARL. This
4772 will happen automatically. */
4777 /* No larl - Access local symbols relative to the GOT. */
4779 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4781 if (reload_in_progress
|| reload_completed
)
4782 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4784 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
4785 if (addend
!= const0_rtx
)
4786 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
4787 addr
= gen_rtx_CONST (Pmode
, addr
);
4788 addr
= force_const_mem (Pmode
, addr
);
4789 emit_move_insn (temp
, addr
);
4791 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4794 s390_load_address (reg
, new_rtx
);
4799 else if (GET_CODE (addr
) == SYMBOL_REF
&& addend
== const0_rtx
)
4801 /* A non-local symbol reference without addend.
4803 The symbol ref is wrapped into an UNSPEC to make sure the
4804 proper operand modifier (@GOT or @GOTENT) will be emitted.
4805 This will tell the linker to put the symbol into the GOT.
4807 Additionally the code dereferencing the GOT slot is emitted here.
4809 An addend to the symref needs to be added afterwards.
4810 legitimize_pic_address calls itself recursively to handle
4811 that case. So no need to do it here. */
4814 reg
= gen_reg_rtx (Pmode
);
4818 /* Use load relative if possible.
4819 lgrl <target>, sym@GOTENT */
4820 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4821 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4822 new_rtx
= gen_const_mem (GET_MODE (reg
), new_rtx
);
4824 emit_move_insn (reg
, new_rtx
);
4827 else if (flag_pic
== 1)
4829 /* Assume GOT offset is a valid displacement operand (< 4k
4830 or < 512k with z990). This is handled the same way in
4831 both 31- and 64-bit code (@GOT).
4832 lg <target>, sym@GOT(r12) */
4834 if (reload_in_progress
|| reload_completed
)
4835 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4837 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
4838 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4839 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
4840 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4841 emit_move_insn (reg
, new_rtx
);
4846 /* If the GOT offset might be >= 4k, we determine the position
4847 of the GOT entry via a PC-relative LARL (@GOTENT).
4848 larl temp, sym@GOTENT
4849 lg <target>, 0(temp) */
4851 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4853 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
4854 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
4856 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4857 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4858 emit_move_insn (temp
, new_rtx
);
4859 new_rtx
= gen_const_mem (Pmode
, temp
);
4860 emit_move_insn (reg
, new_rtx
);
4865 else if (GET_CODE (addr
) == UNSPEC
&& GET_CODE (addend
) == CONST_INT
)
4867 gcc_assert (XVECLEN (addr
, 0) == 1);
4868 switch (XINT (addr
, 1))
4870 /* These address symbols (or PLT slots) relative to the GOT
4871 (not GOT slots!). In general this will exceed the
4872 displacement range so these value belong into the literal
4876 new_rtx
= force_const_mem (Pmode
, orig
);
4879 /* For -fPIC the GOT size might exceed the displacement
4880 range so make sure the value is in the literal pool. */
4883 new_rtx
= force_const_mem (Pmode
, orig
);
4886 /* For @GOTENT larl is used. This is handled like local
4892 /* For @PLT larl is used. This is handled like local
4898 /* Everything else cannot happen. */
4903 else if (addend
!= const0_rtx
)
4905 /* Otherwise, compute the sum. */
4907 rtx base
= legitimize_pic_address (addr
, reg
);
4908 new_rtx
= legitimize_pic_address (addend
,
4909 base
== reg
? NULL_RTX
: reg
);
4910 if (GET_CODE (new_rtx
) == CONST_INT
)
4911 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
4914 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
4916 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
4917 new_rtx
= XEXP (new_rtx
, 1);
4919 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
4922 if (GET_CODE (new_rtx
) == CONST
)
4923 new_rtx
= XEXP (new_rtx
, 0);
4924 new_rtx
= force_operand (new_rtx
, 0);
4930 /* Load the thread pointer into a register. */
4933 s390_get_thread_pointer (void)
4935 rtx tp
= gen_reg_rtx (Pmode
);
4937 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
4938 mark_reg_pointer (tp
, BITS_PER_WORD
);
4943 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
4944 in s390_tls_symbol which always refers to __tls_get_offset.
4945 The returned offset is written to RESULT_REG and an USE rtx is
4946 generated for TLS_CALL. */
4948 static GTY(()) rtx s390_tls_symbol
;
4951 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
4956 emit_insn (s390_load_got ());
4958 if (!s390_tls_symbol
)
4959 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
4961 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
4962 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
4964 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
4965 RTL_CONST_CALL_P (insn
) = 1;
4968 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4969 this (thread-local) address. REG may be used as temporary. */
4972 legitimize_tls_address (rtx addr
, rtx reg
)
4974 rtx new_rtx
, tls_call
, temp
, base
, r2
;
4977 if (GET_CODE (addr
) == SYMBOL_REF
)
4978 switch (tls_symbolic_operand (addr
))
4980 case TLS_MODEL_GLOBAL_DYNAMIC
:
4982 r2
= gen_rtx_REG (Pmode
, 2);
4983 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
4984 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
4985 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4986 emit_move_insn (r2
, new_rtx
);
4987 s390_emit_tls_call_insn (r2
, tls_call
);
4988 insn
= get_insns ();
4991 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
4992 temp
= gen_reg_rtx (Pmode
);
4993 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
4995 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4998 s390_load_address (reg
, new_rtx
);
5003 case TLS_MODEL_LOCAL_DYNAMIC
:
5005 r2
= gen_rtx_REG (Pmode
, 2);
5006 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
5007 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
5008 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5009 emit_move_insn (r2
, new_rtx
);
5010 s390_emit_tls_call_insn (r2
, tls_call
);
5011 insn
= get_insns ();
5014 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
5015 temp
= gen_reg_rtx (Pmode
);
5016 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
5018 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
5019 base
= gen_reg_rtx (Pmode
);
5020 s390_load_address (base
, new_rtx
);
5022 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
5023 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5024 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5025 temp
= gen_reg_rtx (Pmode
);
5026 emit_move_insn (temp
, new_rtx
);
5028 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
5031 s390_load_address (reg
, new_rtx
);
5036 case TLS_MODEL_INITIAL_EXEC
:
5039 /* Assume GOT offset < 4k. This is handled the same way
5040 in both 31- and 64-bit code. */
5042 if (reload_in_progress
|| reload_completed
)
5043 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
5045 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
5046 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5047 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
5048 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
5049 temp
= gen_reg_rtx (Pmode
);
5050 emit_move_insn (temp
, new_rtx
);
5054 /* If the GOT offset might be >= 4k, we determine the position
5055 of the GOT entry via a PC-relative LARL. */
5057 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
5058 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5059 temp
= gen_reg_rtx (Pmode
);
5060 emit_move_insn (temp
, new_rtx
);
5062 new_rtx
= gen_const_mem (Pmode
, temp
);
5063 temp
= gen_reg_rtx (Pmode
);
5064 emit_move_insn (temp
, new_rtx
);
5067 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
5070 s390_load_address (reg
, new_rtx
);
5075 case TLS_MODEL_LOCAL_EXEC
:
5076 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
5077 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5078 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5079 temp
= gen_reg_rtx (Pmode
);
5080 emit_move_insn (temp
, new_rtx
);
5082 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
5085 s390_load_address (reg
, new_rtx
);
5094 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
5096 switch (XINT (XEXP (addr
, 0), 1))
5098 case UNSPEC_INDNTPOFF
:
5107 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
5108 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
5110 new_rtx
= XEXP (XEXP (addr
, 0), 0);
5111 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
5112 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5114 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
5115 new_rtx
= plus_constant (Pmode
, new_rtx
,
5116 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5117 new_rtx
= force_operand (new_rtx
, 0);
5121 gcc_unreachable (); /* for now ... */
5126 /* Emit insns making the address in operands[1] valid for a standard
5127 move to operands[0]. operands[1] is replaced by an address which
5128 should be used instead of the former RTX to emit the move
5132 emit_symbolic_move (rtx
*operands
)
5134 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
5136 if (GET_CODE (operands
[0]) == MEM
)
5137 operands
[1] = force_reg (Pmode
, operands
[1]);
5138 else if (TLS_SYMBOLIC_CONST (operands
[1]))
5139 operands
[1] = legitimize_tls_address (operands
[1], temp
);
5141 operands
[1] = legitimize_pic_address (operands
[1], temp
);
5144 /* Try machine-dependent ways of modifying an illegitimate address X
5145 to be legitimate. If we find one, return the new, valid address.
5147 OLDX is the address as it was before break_out_memory_refs was called.
5148 In some cases it is useful to look at this to decide what needs to be done.
5150 MODE is the mode of the operand pointed to by X.
5152 When -fpic is used, special handling is needed for symbolic references.
5153 See comments by legitimize_pic_address for details. */
5156 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
5157 machine_mode mode ATTRIBUTE_UNUSED
)
5159 rtx constant_term
= const0_rtx
;
5161 if (TLS_SYMBOLIC_CONST (x
))
5163 x
= legitimize_tls_address (x
, 0);
5165 if (s390_legitimate_address_p (mode
, x
, FALSE
))
5168 else if (GET_CODE (x
) == PLUS
5169 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
5170 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
5176 if (SYMBOLIC_CONST (x
)
5177 || (GET_CODE (x
) == PLUS
5178 && (SYMBOLIC_CONST (XEXP (x
, 0))
5179 || SYMBOLIC_CONST (XEXP (x
, 1)))))
5180 x
= legitimize_pic_address (x
, 0);
5182 if (s390_legitimate_address_p (mode
, x
, FALSE
))
5186 x
= eliminate_constant_term (x
, &constant_term
);
5188 /* Optimize loading of large displacements by splitting them
5189 into the multiple of 4K and the rest; this allows the
5190 former to be CSE'd if possible.
5192 Don't do this if the displacement is added to a register
5193 pointing into the stack frame, as the offsets will
5194 change later anyway. */
5196 if (GET_CODE (constant_term
) == CONST_INT
5197 && !TARGET_LONG_DISPLACEMENT
5198 && !DISP_IN_RANGE (INTVAL (constant_term
))
5199 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
5201 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
5202 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
5204 rtx temp
= gen_reg_rtx (Pmode
);
5205 rtx val
= force_operand (GEN_INT (upper
), temp
);
5207 emit_move_insn (temp
, val
);
5209 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
5210 constant_term
= GEN_INT (lower
);
5213 if (GET_CODE (x
) == PLUS
)
5215 if (GET_CODE (XEXP (x
, 0)) == REG
)
5217 rtx temp
= gen_reg_rtx (Pmode
);
5218 rtx val
= force_operand (XEXP (x
, 1), temp
);
5220 emit_move_insn (temp
, val
);
5222 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
5225 else if (GET_CODE (XEXP (x
, 1)) == REG
)
5227 rtx temp
= gen_reg_rtx (Pmode
);
5228 rtx val
= force_operand (XEXP (x
, 0), temp
);
5230 emit_move_insn (temp
, val
);
5232 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
5236 if (constant_term
!= const0_rtx
)
5237 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
5242 /* Try a machine-dependent way of reloading an illegitimate address AD
5243 operand. If we find one, push the reload and return the new address.
5245 MODE is the mode of the enclosing MEM. OPNUM is the operand number
5246 and TYPE is the reload type of the current reload. */
5249 legitimize_reload_address (rtx ad
, machine_mode mode ATTRIBUTE_UNUSED
,
5250 int opnum
, int type
)
5252 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
5255 if (GET_CODE (ad
) == PLUS
)
5257 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
5258 XEXP (ad
, 0), XEXP (ad
, 1));
5263 if (GET_CODE (ad
) == PLUS
5264 && GET_CODE (XEXP (ad
, 0)) == REG
5265 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
5266 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
5268 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
5269 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
5270 rtx cst
, tem
, new_rtx
;
5272 cst
= GEN_INT (upper
);
5273 if (!legitimate_reload_constant_p (cst
))
5274 cst
= force_const_mem (Pmode
, cst
);
5276 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
5277 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
5279 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
5280 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
5281 opnum
, (enum reload_type
) type
);
5288 /* Emit code to move LEN bytes from DST to SRC. */
5291 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
5293 /* When tuning for z10 or higher we rely on the Glibc functions to
5294 do the right thing. Only for constant lengths below 64k we will
5295 generate inline code. */
5296 if (s390_tune
>= PROCESSOR_2097_Z10
5297 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5300 /* Expand memcpy for constant length operands without a loop if it
5301 is shorter that way.
5303 With a constant length argument a
5304 memcpy loop (without pfd) is 36 bytes -> 6 * mvc */
5305 if (GET_CODE (len
) == CONST_INT
5306 && INTVAL (len
) >= 0
5307 && INTVAL (len
) <= 256 * 6
5308 && (!TARGET_MVCLE
|| INTVAL (len
) <= 256))
5312 for (l
= INTVAL (len
), o
= 0; l
> 0; l
-= 256, o
+= 256)
5314 rtx newdst
= adjust_address (dst
, BLKmode
, o
);
5315 rtx newsrc
= adjust_address (src
, BLKmode
, o
);
5316 emit_insn (gen_movmem_short (newdst
, newsrc
,
5317 GEN_INT (l
> 256 ? 255 : l
- 1)));
5321 else if (TARGET_MVCLE
)
5323 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
5328 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
5329 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5330 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5331 rtx_code_label
*end_label
= gen_label_rtx ();
5334 mode
= GET_MODE (len
);
5335 if (mode
== VOIDmode
)
5338 dst_addr
= gen_reg_rtx (Pmode
);
5339 src_addr
= gen_reg_rtx (Pmode
);
5340 count
= gen_reg_rtx (mode
);
5341 blocks
= gen_reg_rtx (mode
);
5343 convert_move (count
, len
, 1);
5344 emit_cmp_and_jump_insns (count
, const0_rtx
,
5345 EQ
, NULL_RTX
, mode
, 1, end_label
);
5347 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5348 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
5349 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5350 src
= change_address (src
, VOIDmode
, src_addr
);
5352 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5355 emit_move_insn (count
, temp
);
5357 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5360 emit_move_insn (blocks
, temp
);
5362 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5363 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5365 emit_label (loop_start_label
);
5368 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
5372 /* Issue a read prefetch for the +3 cache line. */
5373 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
5374 const0_rtx
, const0_rtx
);
5375 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5376 emit_insn (prefetch
);
5378 /* Issue a write prefetch for the +3 cache line. */
5379 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
5380 const1_rtx
, const0_rtx
);
5381 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5382 emit_insn (prefetch
);
5385 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
5386 s390_load_address (dst_addr
,
5387 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5388 s390_load_address (src_addr
,
5389 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
5391 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5394 emit_move_insn (blocks
, temp
);
5396 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5397 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5399 emit_jump (loop_start_label
);
5400 emit_label (loop_end_label
);
5402 emit_insn (gen_movmem_short (dst
, src
,
5403 convert_to_mode (Pmode
, count
, 1)));
5404 emit_label (end_label
);
5409 /* Emit code to set LEN bytes at DST to VAL.
5410 Make use of clrmem if VAL is zero. */
5413 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
5415 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) <= 0)
5418 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
5420 /* Expand setmem/clrmem for a constant length operand without a
5421 loop if it will be shorter that way.
5422 clrmem loop (with PFD) is 30 bytes -> 5 * xc
5423 clrmem loop (without PFD) is 24 bytes -> 4 * xc
5424 setmem loop (with PFD) is 38 bytes -> ~4 * (mvi/stc + mvc)
5425 setmem loop (without PFD) is 32 bytes -> ~4 * (mvi/stc + mvc) */
5426 if (GET_CODE (len
) == CONST_INT
5427 && ((val
== const0_rtx
5428 && (INTVAL (len
) <= 256 * 4
5429 || (INTVAL (len
) <= 256 * 5 && TARGET_SETMEM_PFD(val
,len
))))
5430 || (val
!= const0_rtx
&& INTVAL (len
) <= 257 * 4))
5431 && (!TARGET_MVCLE
|| INTVAL (len
) <= 256))
5435 if (val
== const0_rtx
)
5436 /* clrmem: emit 256 byte blockwise XCs. */
5437 for (l
= INTVAL (len
), o
= 0; l
> 0; l
-= 256, o
+= 256)
5439 rtx newdst
= adjust_address (dst
, BLKmode
, o
);
5440 emit_insn (gen_clrmem_short (newdst
,
5441 GEN_INT (l
> 256 ? 255 : l
- 1)));
5444 /* setmem: emit 1(mvi) + 256(mvc) byte blockwise memsets by
5445 setting first byte to val and using a 256 byte mvc with one
5446 byte overlap to propagate the byte. */
5447 for (l
= INTVAL (len
), o
= 0; l
> 0; l
-= 257, o
+= 257)
5449 rtx newdst
= adjust_address (dst
, BLKmode
, o
);
5450 emit_move_insn (adjust_address (dst
, QImode
, o
), val
);
5453 rtx newdstp1
= adjust_address (dst
, BLKmode
, o
+ 1);
5454 emit_insn (gen_movmem_short (newdstp1
, newdst
,
5455 GEN_INT (l
> 257 ? 255 : l
- 2)));
5460 else if (TARGET_MVCLE
)
5462 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
5464 emit_insn (gen_setmem_long_di (dst
, convert_to_mode (Pmode
, len
, 1),
5467 emit_insn (gen_setmem_long_si (dst
, convert_to_mode (Pmode
, len
, 1),
5473 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
5474 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5475 rtx_code_label
*onebyte_end_label
= gen_label_rtx ();
5476 rtx_code_label
*zerobyte_end_label
= gen_label_rtx ();
5477 rtx_code_label
*restbyte_end_label
= gen_label_rtx ();
5480 mode
= GET_MODE (len
);
5481 if (mode
== VOIDmode
)
5484 dst_addr
= gen_reg_rtx (Pmode
);
5485 count
= gen_reg_rtx (mode
);
5486 blocks
= gen_reg_rtx (mode
);
5488 convert_move (count
, len
, 1);
5489 emit_cmp_and_jump_insns (count
, const0_rtx
,
5490 EQ
, NULL_RTX
, mode
, 1, zerobyte_end_label
,
5491 profile_probability::very_unlikely ());
5493 /* We need to make a copy of the target address since memset is
5494 supposed to return it unmodified. We have to make it here
5495 already since the new reg is used at onebyte_end_label. */
5496 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5497 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5499 if (val
!= const0_rtx
)
5501 /* When using the overlapping mvc the original target
5502 address is only accessed as single byte entity (even by
5503 the mvc reading this value). */
5504 set_mem_size (dst
, 1);
5505 dstp1
= adjust_address (dst
, VOIDmode
, 1);
5506 emit_cmp_and_jump_insns (count
,
5507 const1_rtx
, EQ
, NULL_RTX
, mode
, 1,
5509 profile_probability::very_unlikely ());
5512 /* There is one unconditional (mvi+mvc)/xc after the loop
5513 dealing with the rest of the bytes, subtracting two (mvi+mvc)
5514 or one (xc) here leaves this number of bytes to be handled by
5516 temp
= expand_binop (mode
, add_optab
, count
,
5517 val
== const0_rtx
? constm1_rtx
: GEN_INT (-2),
5518 count
, 1, OPTAB_DIRECT
);
5520 emit_move_insn (count
, temp
);
5522 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5525 emit_move_insn (blocks
, temp
);
5527 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5528 EQ
, NULL_RTX
, mode
, 1, restbyte_end_label
);
5530 emit_jump (loop_start_label
);
5532 if (val
!= const0_rtx
)
5534 /* The 1 byte != 0 special case. Not handled efficiently
5535 since we require two jumps for that. However, this
5536 should be very rare. */
5537 emit_label (onebyte_end_label
);
5538 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5539 emit_jump (zerobyte_end_label
);
5542 emit_label (loop_start_label
);
5544 if (TARGET_SETMEM_PFD (val
, len
))
5546 /* Issue a write prefetch. */
5547 rtx distance
= GEN_INT (TARGET_SETMEM_PREFETCH_DISTANCE
);
5548 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, distance
),
5549 const1_rtx
, const0_rtx
);
5550 emit_insn (prefetch
);
5551 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5554 if (val
== const0_rtx
)
5555 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
5558 /* Set the first byte in the block to the value and use an
5559 overlapping mvc for the block. */
5560 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5561 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (254)));
5563 s390_load_address (dst_addr
,
5564 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5566 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5569 emit_move_insn (blocks
, temp
);
5571 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5572 NE
, NULL_RTX
, mode
, 1, loop_start_label
);
5574 emit_label (restbyte_end_label
);
5576 if (val
== const0_rtx
)
5577 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
5580 /* Set the first byte in the block to the value and use an
5581 overlapping mvc for the block. */
5582 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5583 /* execute only uses the lowest 8 bits of count that's
5584 exactly what we need here. */
5585 emit_insn (gen_movmem_short (dstp1
, dst
,
5586 convert_to_mode (Pmode
, count
, 1)));
5589 emit_label (zerobyte_end_label
);
5593 /* Emit code to compare LEN bytes at OP0 with those at OP1,
5594 and return the result in TARGET. */
5597 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
5599 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
5602 /* When tuning for z10 or higher we rely on the Glibc functions to
5603 do the right thing. Only for constant lengths below 64k we will
5604 generate inline code. */
5605 if (s390_tune
>= PROCESSOR_2097_Z10
5606 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5609 /* As the result of CMPINT is inverted compared to what we need,
5610 we have to swap the operands. */
5611 tmp
= op0
; op0
= op1
; op1
= tmp
;
5613 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
5615 if (INTVAL (len
) > 0)
5617 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
5618 emit_insn (gen_cmpint (target
, ccreg
));
5621 emit_move_insn (target
, const0_rtx
);
5623 else if (TARGET_MVCLE
)
5625 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
5626 emit_insn (gen_cmpint (target
, ccreg
));
5630 rtx addr0
, addr1
, count
, blocks
, temp
;
5631 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5632 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5633 rtx_code_label
*end_label
= gen_label_rtx ();
5636 mode
= GET_MODE (len
);
5637 if (mode
== VOIDmode
)
5640 addr0
= gen_reg_rtx (Pmode
);
5641 addr1
= gen_reg_rtx (Pmode
);
5642 count
= gen_reg_rtx (mode
);
5643 blocks
= gen_reg_rtx (mode
);
5645 convert_move (count
, len
, 1);
5646 emit_cmp_and_jump_insns (count
, const0_rtx
,
5647 EQ
, NULL_RTX
, mode
, 1, end_label
);
5649 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
5650 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
5651 op0
= change_address (op0
, VOIDmode
, addr0
);
5652 op1
= change_address (op1
, VOIDmode
, addr1
);
5654 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5657 emit_move_insn (count
, temp
);
5659 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5662 emit_move_insn (blocks
, temp
);
5664 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5665 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5667 emit_label (loop_start_label
);
5670 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
5674 /* Issue a read prefetch for the +2 cache line of operand 1. */
5675 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
5676 const0_rtx
, const0_rtx
);
5677 emit_insn (prefetch
);
5678 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5680 /* Issue a read prefetch for the +2 cache line of operand 2. */
5681 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
5682 const0_rtx
, const0_rtx
);
5683 emit_insn (prefetch
);
5684 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5687 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
5688 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
5689 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5690 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
5691 temp
= gen_rtx_SET (pc_rtx
, temp
);
5692 emit_jump_insn (temp
);
5694 s390_load_address (addr0
,
5695 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
5696 s390_load_address (addr1
,
5697 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
5699 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5702 emit_move_insn (blocks
, temp
);
5704 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5705 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5707 emit_jump (loop_start_label
);
5708 emit_label (loop_end_label
);
5710 emit_insn (gen_cmpmem_short (op0
, op1
,
5711 convert_to_mode (Pmode
, count
, 1)));
5712 emit_label (end_label
);
5714 emit_insn (gen_cmpint (target
, ccreg
));
5719 /* Emit a conditional jump to LABEL for condition code mask MASK using
5720 comparsion operator COMPARISON. Return the emitted jump insn. */
5723 s390_emit_ccraw_jump (HOST_WIDE_INT mask
, enum rtx_code comparison
, rtx label
)
5727 gcc_assert (comparison
== EQ
|| comparison
== NE
);
5728 gcc_assert (mask
> 0 && mask
< 15);
5730 temp
= gen_rtx_fmt_ee (comparison
, VOIDmode
,
5731 gen_rtx_REG (CCRAWmode
, CC_REGNUM
), GEN_INT (mask
));
5732 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5733 gen_rtx_LABEL_REF (VOIDmode
, label
), pc_rtx
);
5734 temp
= gen_rtx_SET (pc_rtx
, temp
);
5735 return emit_jump_insn (temp
);
5738 /* Emit the instructions to implement strlen of STRING and store the
5739 result in TARGET. The string has the known ALIGNMENT. This
5740 version uses vector instructions and is therefore not appropriate
5741 for targets prior to z13. */
5744 s390_expand_vec_strlen (rtx target
, rtx string
, rtx alignment
)
5746 rtx highest_index_to_load_reg
= gen_reg_rtx (Pmode
);
5747 rtx str_reg
= gen_reg_rtx (V16QImode
);
5748 rtx str_addr_base_reg
= gen_reg_rtx (Pmode
);
5749 rtx str_idx_reg
= gen_reg_rtx (Pmode
);
5750 rtx result_reg
= gen_reg_rtx (V16QImode
);
5751 rtx is_aligned_label
= gen_label_rtx ();
5752 rtx into_loop_label
= NULL_RTX
;
5753 rtx loop_start_label
= gen_label_rtx ();
5755 rtx len
= gen_reg_rtx (QImode
);
5758 s390_load_address (str_addr_base_reg
, XEXP (string
, 0));
5759 emit_move_insn (str_idx_reg
, const0_rtx
);
5761 if (INTVAL (alignment
) < 16)
5763 /* Check whether the address happens to be aligned properly so
5764 jump directly to the aligned loop. */
5765 emit_cmp_and_jump_insns (gen_rtx_AND (Pmode
,
5766 str_addr_base_reg
, GEN_INT (15)),
5767 const0_rtx
, EQ
, NULL_RTX
,
5768 Pmode
, 1, is_aligned_label
);
5770 temp
= gen_reg_rtx (Pmode
);
5771 temp
= expand_binop (Pmode
, and_optab
, str_addr_base_reg
,
5772 GEN_INT (15), temp
, 1, OPTAB_DIRECT
);
5773 gcc_assert (REG_P (temp
));
5774 highest_index_to_load_reg
=
5775 expand_binop (Pmode
, sub_optab
, GEN_INT (15), temp
,
5776 highest_index_to_load_reg
, 1, OPTAB_DIRECT
);
5777 gcc_assert (REG_P (highest_index_to_load_reg
));
5778 emit_insn (gen_vllv16qi (str_reg
,
5779 convert_to_mode (SImode
, highest_index_to_load_reg
, 1),
5780 gen_rtx_MEM (BLKmode
, str_addr_base_reg
)));
5782 into_loop_label
= gen_label_rtx ();
5783 s390_emit_jump (into_loop_label
, NULL_RTX
);
5787 emit_label (is_aligned_label
);
5788 LABEL_NUSES (is_aligned_label
) = INTVAL (alignment
) < 16 ? 2 : 1;
5790 /* Reaching this point we are only performing 16 bytes aligned
5792 emit_move_insn (highest_index_to_load_reg
, GEN_INT (15));
5794 emit_label (loop_start_label
);
5795 LABEL_NUSES (loop_start_label
) = 1;
5797 /* Load 16 bytes of the string into VR. */
5798 emit_move_insn (str_reg
,
5799 gen_rtx_MEM (V16QImode
,
5800 gen_rtx_PLUS (Pmode
, str_idx_reg
,
5801 str_addr_base_reg
)));
5802 if (into_loop_label
!= NULL_RTX
)
5804 emit_label (into_loop_label
);
5805 LABEL_NUSES (into_loop_label
) = 1;
5808 /* Increment string index by 16 bytes. */
5809 expand_binop (Pmode
, add_optab
, str_idx_reg
, GEN_INT (16),
5810 str_idx_reg
, 1, OPTAB_DIRECT
);
5812 emit_insn (gen_vec_vfenesv16qi (result_reg
, str_reg
, str_reg
,
5813 GEN_INT (VSTRING_FLAG_ZS
| VSTRING_FLAG_CS
)));
5815 add_int_reg_note (s390_emit_ccraw_jump (8, NE
, loop_start_label
),
5817 profile_probability::very_likely ().to_reg_br_prob_note ());
5818 emit_insn (gen_vec_extractv16qiqi (len
, result_reg
, GEN_INT (7)));
5820 /* If the string pointer wasn't aligned we have loaded less then 16
5821 bytes and the remaining bytes got filled with zeros (by vll).
5822 Now we have to check whether the resulting index lies within the
5823 bytes actually part of the string. */
5825 cond
= s390_emit_compare (GT
, convert_to_mode (Pmode
, len
, 1),
5826 highest_index_to_load_reg
);
5827 s390_load_address (highest_index_to_load_reg
,
5828 gen_rtx_PLUS (Pmode
, highest_index_to_load_reg
,
5831 emit_insn (gen_movdicc (str_idx_reg
, cond
,
5832 highest_index_to_load_reg
, str_idx_reg
));
5834 emit_insn (gen_movsicc (str_idx_reg
, cond
,
5835 highest_index_to_load_reg
, str_idx_reg
));
5837 add_reg_br_prob_note (s390_emit_jump (is_aligned_label
, cond
),
5838 profile_probability::very_unlikely ());
5840 expand_binop (Pmode
, add_optab
, str_idx_reg
,
5841 GEN_INT (-16), str_idx_reg
, 1, OPTAB_DIRECT
);
5842 /* FIXME: len is already zero extended - so avoid the llgcr emitted
5844 temp
= expand_binop (Pmode
, add_optab
, str_idx_reg
,
5845 convert_to_mode (Pmode
, len
, 1),
5846 target
, 1, OPTAB_DIRECT
);
5848 emit_move_insn (target
, temp
);
5852 s390_expand_vec_movstr (rtx result
, rtx dst
, rtx src
)
5854 rtx temp
= gen_reg_rtx (Pmode
);
5855 rtx src_addr
= XEXP (src
, 0);
5856 rtx dst_addr
= XEXP (dst
, 0);
5857 rtx src_addr_reg
= gen_reg_rtx (Pmode
);
5858 rtx dst_addr_reg
= gen_reg_rtx (Pmode
);
5859 rtx offset
= gen_reg_rtx (Pmode
);
5860 rtx vsrc
= gen_reg_rtx (V16QImode
);
5861 rtx vpos
= gen_reg_rtx (V16QImode
);
5862 rtx loadlen
= gen_reg_rtx (SImode
);
5863 rtx gpos_qi
= gen_reg_rtx(QImode
);
5864 rtx gpos
= gen_reg_rtx (SImode
);
5865 rtx done_label
= gen_label_rtx ();
5866 rtx loop_label
= gen_label_rtx ();
5867 rtx exit_label
= gen_label_rtx ();
5868 rtx full_label
= gen_label_rtx ();
5870 /* Perform a quick check for string ending on the first up to 16
5871 bytes and exit early if successful. */
5873 emit_insn (gen_vlbb (vsrc
, src
, GEN_INT (6)));
5874 emit_insn (gen_lcbb (loadlen
, src_addr
, GEN_INT (6)));
5875 emit_insn (gen_vfenezv16qi (vpos
, vsrc
, vsrc
));
5876 emit_insn (gen_vec_extractv16qiqi (gpos_qi
, vpos
, GEN_INT (7)));
5877 emit_move_insn (gpos
, gen_rtx_SUBREG (SImode
, gpos_qi
, 0));
5878 /* gpos is the byte index if a zero was found and 16 otherwise.
5879 So if it is lower than the loaded bytes we have a hit. */
5880 emit_cmp_and_jump_insns (gpos
, loadlen
, GE
, NULL_RTX
, SImode
, 1,
5882 emit_insn (gen_vstlv16qi (vsrc
, gpos
, dst
));
5884 force_expand_binop (Pmode
, add_optab
, dst_addr
, gpos
, result
,
5886 emit_jump (exit_label
);
5889 emit_label (full_label
);
5890 LABEL_NUSES (full_label
) = 1;
5892 /* Calculate `offset' so that src + offset points to the last byte
5893 before 16 byte alignment. */
5895 /* temp = src_addr & 0xf */
5896 force_expand_binop (Pmode
, and_optab
, src_addr
, GEN_INT (15), temp
,
5899 /* offset = 0xf - temp */
5900 emit_move_insn (offset
, GEN_INT (15));
5901 force_expand_binop (Pmode
, sub_optab
, offset
, temp
, offset
,
5904 /* Store `offset' bytes in the dstination string. The quick check
5905 has loaded at least `offset' bytes into vsrc. */
5907 emit_insn (gen_vstlv16qi (vsrc
, gen_lowpart (SImode
, offset
), dst
));
5909 /* Advance to the next byte to be loaded. */
5910 force_expand_binop (Pmode
, add_optab
, offset
, const1_rtx
, offset
,
5913 /* Make sure the addresses are single regs which can be used as a
5915 emit_move_insn (src_addr_reg
, src_addr
);
5916 emit_move_insn (dst_addr_reg
, dst_addr
);
5920 emit_label (loop_label
);
5921 LABEL_NUSES (loop_label
) = 1;
5923 emit_move_insn (vsrc
,
5924 gen_rtx_MEM (V16QImode
,
5925 gen_rtx_PLUS (Pmode
, src_addr_reg
, offset
)));
5927 emit_insn (gen_vec_vfenesv16qi (vpos
, vsrc
, vsrc
,
5928 GEN_INT (VSTRING_FLAG_ZS
| VSTRING_FLAG_CS
)));
5929 add_int_reg_note (s390_emit_ccraw_jump (8, EQ
, done_label
),
5930 REG_BR_PROB
, profile_probability::very_unlikely ()
5931 .to_reg_br_prob_note ());
5933 emit_move_insn (gen_rtx_MEM (V16QImode
,
5934 gen_rtx_PLUS (Pmode
, dst_addr_reg
, offset
)),
5937 force_expand_binop (Pmode
, add_optab
, offset
, GEN_INT (16),
5938 offset
, 1, OPTAB_DIRECT
);
5940 emit_jump (loop_label
);
5945 /* We are done. Add the offset of the zero character to the dst_addr
5946 pointer to get the result. */
5948 emit_label (done_label
);
5949 LABEL_NUSES (done_label
) = 1;
5951 force_expand_binop (Pmode
, add_optab
, dst_addr_reg
, offset
, dst_addr_reg
,
5954 emit_insn (gen_vec_extractv16qiqi (gpos_qi
, vpos
, GEN_INT (7)));
5955 emit_move_insn (gpos
, gen_rtx_SUBREG (SImode
, gpos_qi
, 0));
5957 emit_insn (gen_vstlv16qi (vsrc
, gpos
, gen_rtx_MEM (BLKmode
, dst_addr_reg
)));
5959 force_expand_binop (Pmode
, add_optab
, dst_addr_reg
, gpos
, result
,
5964 emit_label (exit_label
);
5965 LABEL_NUSES (exit_label
) = 1;
5969 /* Expand conditional increment or decrement using alc/slb instructions.
5970 Should generate code setting DST to either SRC or SRC + INCREMENT,
5971 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
5972 Returns true if successful, false otherwise.
5974 That makes it possible to implement some if-constructs without jumps e.g.:
5975 (borrow = CC0 | CC1 and carry = CC2 | CC3)
5976 unsigned int a, b, c;
5977 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
5978 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
5979 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
5980 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
5982 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
5983 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
5984 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
5985 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
5986 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
5989 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
5990 rtx dst
, rtx src
, rtx increment
)
5992 machine_mode cmp_mode
;
5993 machine_mode cc_mode
;
5999 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
6000 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
6002 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
6003 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
6008 /* Try ADD LOGICAL WITH CARRY. */
6009 if (increment
== const1_rtx
)
6011 /* Determine CC mode to use. */
6012 if (cmp_code
== EQ
|| cmp_code
== NE
)
6014 if (cmp_op1
!= const0_rtx
)
6016 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
6017 NULL_RTX
, 0, OPTAB_WIDEN
);
6018 cmp_op1
= const0_rtx
;
6021 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
6024 if (cmp_code
== LTU
|| cmp_code
== LEU
)
6029 cmp_code
= swap_condition (cmp_code
);
6046 /* Emit comparison instruction pattern. */
6047 if (!register_operand (cmp_op0
, cmp_mode
))
6048 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
6050 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
6051 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
6052 /* We use insn_invalid_p here to add clobbers if required. */
6053 ret
= insn_invalid_p (emit_insn (insn
), false);
6056 /* Emit ALC instruction pattern. */
6057 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
6058 gen_rtx_REG (cc_mode
, CC_REGNUM
),
6061 if (src
!= const0_rtx
)
6063 if (!register_operand (src
, GET_MODE (dst
)))
6064 src
= force_reg (GET_MODE (dst
), src
);
6066 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
6067 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
6070 p
= rtvec_alloc (2);
6072 gen_rtx_SET (dst
, op_res
);
6074 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6075 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
6080 /* Try SUBTRACT LOGICAL WITH BORROW. */
6081 if (increment
== constm1_rtx
)
6083 /* Determine CC mode to use. */
6084 if (cmp_code
== EQ
|| cmp_code
== NE
)
6086 if (cmp_op1
!= const0_rtx
)
6088 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
6089 NULL_RTX
, 0, OPTAB_WIDEN
);
6090 cmp_op1
= const0_rtx
;
6093 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
6096 if (cmp_code
== GTU
|| cmp_code
== GEU
)
6101 cmp_code
= swap_condition (cmp_code
);
6118 /* Emit comparison instruction pattern. */
6119 if (!register_operand (cmp_op0
, cmp_mode
))
6120 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
6122 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
6123 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
6124 /* We use insn_invalid_p here to add clobbers if required. */
6125 ret
= insn_invalid_p (emit_insn (insn
), false);
6128 /* Emit SLB instruction pattern. */
6129 if (!register_operand (src
, GET_MODE (dst
)))
6130 src
= force_reg (GET_MODE (dst
), src
);
6132 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
6133 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
6134 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
6135 gen_rtx_REG (cc_mode
, CC_REGNUM
),
6137 p
= rtvec_alloc (2);
6139 gen_rtx_SET (dst
, op_res
);
6141 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6142 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
6150 /* Expand code for the insv template. Return true if successful. */
6153 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
6155 int bitsize
= INTVAL (op1
);
6156 int bitpos
= INTVAL (op2
);
6157 machine_mode mode
= GET_MODE (dest
);
6159 int smode_bsize
, mode_bsize
;
6162 if (bitsize
+ bitpos
> GET_MODE_BITSIZE (mode
))
6165 /* Generate INSERT IMMEDIATE (IILL et al). */
6166 /* (set (ze (reg)) (const_int)). */
6168 && register_operand (dest
, word_mode
)
6169 && (bitpos
% 16) == 0
6170 && (bitsize
% 16) == 0
6171 && const_int_operand (src
, VOIDmode
))
6173 HOST_WIDE_INT val
= INTVAL (src
);
6174 int regpos
= bitpos
+ bitsize
;
6176 while (regpos
> bitpos
)
6178 machine_mode putmode
;
6181 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
6186 putsize
= GET_MODE_BITSIZE (putmode
);
6188 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
6191 gen_int_mode (val
, putmode
));
6194 gcc_assert (regpos
== bitpos
);
6198 smode
= smallest_int_mode_for_size (bitsize
);
6199 smode_bsize
= GET_MODE_BITSIZE (smode
);
6200 mode_bsize
= GET_MODE_BITSIZE (mode
);
6202 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
6204 && (bitsize
% BITS_PER_UNIT
) == 0
6206 && (register_operand (src
, word_mode
)
6207 || const_int_operand (src
, VOIDmode
)))
6209 /* Emit standard pattern if possible. */
6210 if (smode_bsize
== bitsize
)
6212 emit_move_insn (adjust_address (dest
, smode
, 0),
6213 gen_lowpart (smode
, src
));
6217 /* (set (ze (mem)) (const_int)). */
6218 else if (const_int_operand (src
, VOIDmode
))
6220 int size
= bitsize
/ BITS_PER_UNIT
;
6221 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
),
6223 UNITS_PER_WORD
- size
);
6225 dest
= adjust_address (dest
, BLKmode
, 0);
6226 set_mem_size (dest
, size
);
6227 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
6231 /* (set (ze (mem)) (reg)). */
6232 else if (register_operand (src
, word_mode
))
6235 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
6239 /* Emit st,stcmh sequence. */
6240 int stcmh_width
= bitsize
- 32;
6241 int size
= stcmh_width
/ BITS_PER_UNIT
;
6243 emit_move_insn (adjust_address (dest
, SImode
, size
),
6244 gen_lowpart (SImode
, src
));
6245 set_mem_size (dest
, size
);
6246 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
6247 GEN_INT (stcmh_width
),
6249 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT (32)));
6255 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
6256 if ((bitpos
% BITS_PER_UNIT
) == 0
6257 && (bitsize
% BITS_PER_UNIT
) == 0
6258 && (bitpos
& 32) == ((bitpos
+ bitsize
- 1) & 32)
6260 && (mode
== DImode
|| mode
== SImode
)
6261 && register_operand (dest
, mode
))
6263 /* Emit a strict_low_part pattern if possible. */
6264 if (smode_bsize
== bitsize
&& bitpos
== mode_bsize
- smode_bsize
)
6266 op
= gen_rtx_STRICT_LOW_PART (VOIDmode
, gen_lowpart (smode
, dest
));
6267 op
= gen_rtx_SET (op
, gen_lowpart (smode
, src
));
6268 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6269 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
6273 /* ??? There are more powerful versions of ICM that are not
6274 completely represented in the md file. */
6277 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
6278 if (TARGET_Z10
&& (mode
== DImode
|| mode
== SImode
))
6280 machine_mode mode_s
= GET_MODE (src
);
6282 if (CONSTANT_P (src
))
6284 /* For constant zero values the representation with AND
6285 appears to be folded in more situations than the (set
6286 (zero_extract) ...).
6287 We only do this when the start and end of the bitfield
6288 remain in the same SImode chunk. That way nihf or nilf
6290 The AND patterns might still generate a risbg for this. */
6291 if (src
== const0_rtx
&& bitpos
/ 32 == (bitpos
+ bitsize
- 1) / 32)
6294 src
= force_reg (mode
, src
);
6296 else if (mode_s
!= mode
)
6298 gcc_assert (GET_MODE_BITSIZE (mode_s
) >= bitsize
);
6299 src
= force_reg (mode_s
, src
);
6300 src
= gen_lowpart (mode
, src
);
6303 op
= gen_rtx_ZERO_EXTRACT (mode
, dest
, op1
, op2
),
6304 op
= gen_rtx_SET (op
, src
);
6308 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6309 op
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
));
6319 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
6320 register that holds VAL of mode MODE shifted by COUNT bits. */
6323 s390_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
6325 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
6326 NULL_RTX
, 1, OPTAB_DIRECT
);
6327 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
6328 NULL_RTX
, 1, OPTAB_DIRECT
);
6331 /* Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store
6332 the result in TARGET. */
6335 s390_expand_vec_compare (rtx target
, enum rtx_code cond
,
6336 rtx cmp_op1
, rtx cmp_op2
)
6338 machine_mode mode
= GET_MODE (target
);
6339 bool neg_p
= false, swap_p
= false;
6342 if (GET_MODE_CLASS (GET_MODE (cmp_op1
)) == MODE_VECTOR_FLOAT
)
6346 /* NE a != b -> !(a == b) */
6347 case NE
: cond
= EQ
; neg_p
= true; break;
6348 /* UNGT a u> b -> !(b >= a) */
6349 case UNGT
: cond
= GE
; neg_p
= true; swap_p
= true; break;
6350 /* UNGE a u>= b -> !(b > a) */
6351 case UNGE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
6352 /* LE: a <= b -> b >= a */
6353 case LE
: cond
= GE
; swap_p
= true; break;
6354 /* UNLE: a u<= b -> !(a > b) */
6355 case UNLE
: cond
= GT
; neg_p
= true; break;
6356 /* LT: a < b -> b > a */
6357 case LT
: cond
= GT
; swap_p
= true; break;
6358 /* UNLT: a u< b -> !(a >= b) */
6359 case UNLT
: cond
= GE
; neg_p
= true; break;
6361 emit_insn (gen_vec_cmpuneq (target
, cmp_op1
, cmp_op2
));
6364 emit_insn (gen_vec_cmpltgt (target
, cmp_op1
, cmp_op2
));
6367 emit_insn (gen_vec_ordered (target
, cmp_op1
, cmp_op2
));
6370 emit_insn (gen_vec_unordered (target
, cmp_op1
, cmp_op2
));
6379 /* NE: a != b -> !(a == b) */
6380 case NE
: cond
= EQ
; neg_p
= true; break;
6381 /* GE: a >= b -> !(b > a) */
6382 case GE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
6383 /* GEU: a >= b -> !(b > a) */
6384 case GEU
: cond
= GTU
; neg_p
= true; swap_p
= true; break;
6385 /* LE: a <= b -> !(a > b) */
6386 case LE
: cond
= GT
; neg_p
= true; break;
6387 /* LEU: a <= b -> !(a > b) */
6388 case LEU
: cond
= GTU
; neg_p
= true; break;
6389 /* LT: a < b -> b > a */
6390 case LT
: cond
= GT
; swap_p
= true; break;
6391 /* LTU: a < b -> b > a */
6392 case LTU
: cond
= GTU
; swap_p
= true; break;
6399 tmp
= cmp_op1
; cmp_op1
= cmp_op2
; cmp_op2
= tmp
;
6402 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (cond
,
6404 cmp_op1
, cmp_op2
)));
6406 emit_insn (gen_rtx_SET (target
, gen_rtx_NOT (mode
, target
)));
6409 /* Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into
6410 TARGET if either all (ALL_P is true) or any (ALL_P is false) of the
6411 elements in CMP1 and CMP2 fulfill the comparison.
6412 This function is only used to emit patterns for the vx builtins and
6413 therefore only handles comparison codes required by the
6416 s390_expand_vec_compare_cc (rtx target
, enum rtx_code code
,
6417 rtx cmp1
, rtx cmp2
, bool all_p
)
6419 machine_mode cc_producer_mode
, cc_consumer_mode
, scratch_mode
;
6420 rtx tmp_reg
= gen_reg_rtx (SImode
);
6421 bool swap_p
= false;
6423 if (GET_MODE_CLASS (GET_MODE (cmp1
)) == MODE_VECTOR_INT
)
6429 cc_producer_mode
= CCVEQmode
;
6433 code
= swap_condition (code
);
6438 cc_producer_mode
= CCVIHmode
;
6442 code
= swap_condition (code
);
6447 cc_producer_mode
= CCVIHUmode
;
6453 scratch_mode
= GET_MODE (cmp1
);
6454 /* These codes represent inverted CC interpretations. Inverting
6455 an ALL CC mode results in an ANY CC mode and the other way
6456 around. Invert the all_p flag here to compensate for
6458 if (code
== NE
|| code
== LE
|| code
== LEU
)
6461 cc_consumer_mode
= all_p
? CCVIALLmode
: CCVIANYmode
;
6463 else if (GET_MODE_CLASS (GET_MODE (cmp1
)) == MODE_VECTOR_FLOAT
)
6469 case EQ
: cc_producer_mode
= CCVEQmode
; break;
6470 case NE
: cc_producer_mode
= CCVEQmode
; inv_p
= true; break;
6471 case GT
: cc_producer_mode
= CCVFHmode
; break;
6472 case GE
: cc_producer_mode
= CCVFHEmode
; break;
6473 case UNLE
: cc_producer_mode
= CCVFHmode
; inv_p
= true; break;
6474 case UNLT
: cc_producer_mode
= CCVFHEmode
; inv_p
= true; break;
6475 case LT
: cc_producer_mode
= CCVFHmode
; code
= GT
; swap_p
= true; break;
6476 case LE
: cc_producer_mode
= CCVFHEmode
; code
= GE
; swap_p
= true; break;
6477 default: gcc_unreachable ();
6479 scratch_mode
= mode_for_int_vector (GET_MODE (cmp1
)).require ();
6484 cc_consumer_mode
= all_p
? CCVFALLmode
: CCVFANYmode
;
6496 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6497 gen_rtvec (2, gen_rtx_SET (
6498 gen_rtx_REG (cc_producer_mode
, CC_REGNUM
),
6499 gen_rtx_COMPARE (cc_producer_mode
, cmp1
, cmp2
)),
6500 gen_rtx_CLOBBER (VOIDmode
,
6501 gen_rtx_SCRATCH (scratch_mode
)))));
6502 emit_move_insn (target
, const0_rtx
);
6503 emit_move_insn (tmp_reg
, const1_rtx
);
6505 emit_move_insn (target
,
6506 gen_rtx_IF_THEN_ELSE (SImode
,
6507 gen_rtx_fmt_ee (code
, VOIDmode
,
6508 gen_rtx_REG (cc_consumer_mode
, CC_REGNUM
),
6513 /* Invert the comparison CODE applied to a CC mode. This is only safe
6514 if we know whether there result was created by a floating point
6515 compare or not. For the CCV modes this is encoded as part of the
6518 s390_reverse_condition (machine_mode mode
, enum rtx_code code
)
6520 /* Reversal of FP compares takes care -- an ordered compare
6521 becomes an unordered compare and vice versa. */
6522 if (mode
== CCVFALLmode
|| mode
== CCVFANYmode
)
6523 return reverse_condition_maybe_unordered (code
);
6524 else if (mode
== CCVIALLmode
|| mode
== CCVIANYmode
)
6525 return reverse_condition (code
);
6530 /* Generate a vector comparison expression loading either elements of
6531 THEN or ELS into TARGET depending on the comparison COND of CMP_OP1
6535 s390_expand_vcond (rtx target
, rtx then
, rtx els
,
6536 enum rtx_code cond
, rtx cmp_op1
, rtx cmp_op2
)
6539 machine_mode result_mode
;
6542 machine_mode target_mode
= GET_MODE (target
);
6543 machine_mode cmp_mode
= GET_MODE (cmp_op1
);
6544 rtx op
= (cond
== LT
) ? els
: then
;
6546 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
6547 and x < 0 ? 1 : 0 into (unsigned) x >> 31. Likewise
6548 for short and byte (x >> 15 and x >> 7 respectively). */
6549 if ((cond
== LT
|| cond
== GE
)
6550 && target_mode
== cmp_mode
6551 && cmp_op2
== CONST0_RTX (cmp_mode
)
6552 && op
== CONST0_RTX (target_mode
)
6553 && s390_vector_mode_supported_p (target_mode
)
6554 && GET_MODE_CLASS (target_mode
) == MODE_VECTOR_INT
)
6556 rtx negop
= (cond
== LT
) ? then
: els
;
6558 int shift
= GET_MODE_BITSIZE (GET_MODE_INNER (target_mode
)) - 1;
6560 /* if x < 0 ? 1 : 0 or if x >= 0 ? 0 : 1 */
6561 if (negop
== CONST1_RTX (target_mode
))
6563 rtx res
= expand_simple_binop (cmp_mode
, LSHIFTRT
, cmp_op1
,
6564 GEN_INT (shift
), target
,
6567 emit_move_insn (target
, res
);
6571 /* if x < 0 ? -1 : 0 or if x >= 0 ? 0 : -1 */
6572 else if (all_ones_operand (negop
, target_mode
))
6574 rtx res
= expand_simple_binop (cmp_mode
, ASHIFTRT
, cmp_op1
,
6575 GEN_INT (shift
), target
,
6578 emit_move_insn (target
, res
);
6583 /* We always use an integral type vector to hold the comparison
6585 result_mode
= mode_for_int_vector (cmp_mode
).require ();
6586 result_target
= gen_reg_rtx (result_mode
);
6588 /* We allow vector immediates as comparison operands that
6589 can be handled by the optimization above but not by the
6590 following code. Hence, force them into registers here. */
6591 if (!REG_P (cmp_op1
))
6592 cmp_op1
= force_reg (GET_MODE (cmp_op1
), cmp_op1
);
6594 if (!REG_P (cmp_op2
))
6595 cmp_op2
= force_reg (GET_MODE (cmp_op2
), cmp_op2
);
6597 s390_expand_vec_compare (result_target
, cond
,
6600 /* If the results are supposed to be either -1 or 0 we are done
6601 since this is what our compare instructions generate anyway. */
6602 if (all_ones_operand (then
, GET_MODE (then
))
6603 && const0_operand (els
, GET_MODE (els
)))
6605 emit_move_insn (target
, gen_rtx_SUBREG (target_mode
,
6610 /* Otherwise we will do a vsel afterwards. */
6611 /* This gets triggered e.g.
6612 with gcc.c-torture/compile/pr53410-1.c */
6614 then
= force_reg (target_mode
, then
);
6617 els
= force_reg (target_mode
, els
);
6619 tmp
= gen_rtx_fmt_ee (EQ
, VOIDmode
,
6621 CONST0_RTX (result_mode
));
6623 /* We compared the result against zero above so we have to swap then
6625 tmp
= gen_rtx_IF_THEN_ELSE (target_mode
, tmp
, els
, then
);
6627 gcc_assert (target_mode
== GET_MODE (then
));
6628 emit_insn (gen_rtx_SET (target
, tmp
));
6631 /* Emit the RTX necessary to initialize the vector TARGET with values
6634 s390_expand_vec_init (rtx target
, rtx vals
)
6636 machine_mode mode
= GET_MODE (target
);
6637 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6638 int n_elts
= GET_MODE_NUNITS (mode
);
6639 bool all_same
= true, all_regs
= true, all_const_int
= true;
6643 for (i
= 0; i
< n_elts
; ++i
)
6645 x
= XVECEXP (vals
, 0, i
);
6647 if (!CONST_INT_P (x
))
6648 all_const_int
= false;
6650 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6657 /* Use vector gen mask or vector gen byte mask if possible. */
6658 if (all_same
&& all_const_int
6659 && (XVECEXP (vals
, 0, 0) == const0_rtx
6660 || s390_contiguous_bitmask_vector_p (XVECEXP (vals
, 0, 0),
6662 || s390_bytemask_vector_p (XVECEXP (vals
, 0, 0), NULL
)))
6664 emit_insn (gen_rtx_SET (target
,
6665 gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0))));
6669 /* Use vector replicate instructions. vlrep/vrepi/vrep */
6672 rtx elem
= XVECEXP (vals
, 0, 0);
6674 /* vec_splats accepts general_operand as source. */
6675 if (!general_operand (elem
, GET_MODE (elem
)))
6676 elem
= force_reg (inner_mode
, elem
);
6678 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, elem
)));
6685 && GET_MODE_SIZE (inner_mode
) == 8)
6687 /* Use vector load pair. */
6688 emit_insn (gen_rtx_SET (target
,
6689 gen_rtx_VEC_CONCAT (mode
,
6690 XVECEXP (vals
, 0, 0),
6691 XVECEXP (vals
, 0, 1))));
6695 /* Use vector load logical element and zero. */
6696 if (TARGET_VXE
&& (mode
== V4SImode
|| mode
== V4SFmode
))
6700 x
= XVECEXP (vals
, 0, 0);
6701 if (memory_operand (x
, inner_mode
))
6703 for (i
= 1; i
< n_elts
; ++i
)
6704 found
= found
&& XVECEXP (vals
, 0, i
) == const0_rtx
;
6708 machine_mode half_mode
= (inner_mode
== SFmode
6709 ? V2SFmode
: V2SImode
);
6710 emit_insn (gen_rtx_SET (target
,
6711 gen_rtx_VEC_CONCAT (mode
,
6712 gen_rtx_VEC_CONCAT (half_mode
,
6715 gen_rtx_VEC_CONCAT (half_mode
,
6723 /* We are about to set the vector elements one by one. Zero out the
6724 full register first in order to help the data flow framework to
6725 detect it as full VR set. */
6726 emit_insn (gen_rtx_SET (target
, CONST0_RTX (mode
)));
6728 /* Unfortunately the vec_init expander is not allowed to fail. So
6729 we have to implement the fallback ourselves. */
6730 for (i
= 0; i
< n_elts
; i
++)
6732 rtx elem
= XVECEXP (vals
, 0, i
);
6733 if (!general_operand (elem
, GET_MODE (elem
)))
6734 elem
= force_reg (inner_mode
, elem
);
6736 emit_insn (gen_rtx_SET (target
,
6737 gen_rtx_UNSPEC (mode
,
6739 GEN_INT (i
), target
),
6744 /* Structure to hold the initial parameters for a compare_and_swap operation
6745 in HImode and QImode. */
6747 struct alignment_context
6749 rtx memsi
; /* SI aligned memory location. */
6750 rtx shift
; /* Bit offset with regard to lsb. */
6751 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
6752 rtx modemaski
; /* ~modemask */
6753 bool aligned
; /* True if memory is aligned, false else. */
6756 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
6757 structure AC for transparent simplifying, if the memory alignment is known
6758 to be at least 32bit. MEM is the memory location for the actual operation
6759 and MODE its mode. */
6762 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
6765 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
6766 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
6769 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
6772 /* Alignment is unknown. */
6773 rtx byteoffset
, addr
, align
;
6775 /* Force the address into a register. */
6776 addr
= force_reg (Pmode
, XEXP (mem
, 0));
6778 /* Align it to SImode. */
6779 align
= expand_simple_binop (Pmode
, AND
, addr
,
6780 GEN_INT (-GET_MODE_SIZE (SImode
)),
6781 NULL_RTX
, 1, OPTAB_DIRECT
);
6783 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
6784 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
6785 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
6786 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
6788 /* Calculate shiftcount. */
6789 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
6790 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
6791 NULL_RTX
, 1, OPTAB_DIRECT
);
6792 /* As we already have some offset, evaluate the remaining distance. */
6793 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
6794 NULL_RTX
, 1, OPTAB_DIRECT
);
6797 /* Shift is the byte count, but we need the bitcount. */
6798 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
, GEN_INT (3),
6799 NULL_RTX
, 1, OPTAB_DIRECT
);
6801 /* Calculate masks. */
6802 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
6803 GEN_INT (GET_MODE_MASK (mode
)),
6804 ac
->shift
, NULL_RTX
, 1, OPTAB_DIRECT
);
6805 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
,
6809 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
6810 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
6811 perform the merge in SEQ2. */
6814 s390_two_part_insv (struct alignment_context
*ac
, rtx
*seq1
, rtx
*seq2
,
6815 machine_mode mode
, rtx val
, rtx ins
)
6822 tmp
= copy_to_mode_reg (SImode
, val
);
6823 if (s390_expand_insv (tmp
, GEN_INT (GET_MODE_BITSIZE (mode
)),
6827 *seq2
= get_insns ();
6834 /* Failed to use insv. Generate a two part shift and mask. */
6836 tmp
= s390_expand_mask_and_shift (ins
, mode
, ac
->shift
);
6837 *seq1
= get_insns ();
6841 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
, NULL_RTX
, 1, OPTAB_DIRECT
);
6842 *seq2
= get_insns ();
6848 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
6849 the memory location, CMP the old value to compare MEM with and NEW_RTX the
6850 value to set if CMP == MEM. */
6853 s390_expand_cs_hqi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
6854 rtx cmp
, rtx new_rtx
, bool is_weak
)
6856 struct alignment_context ac
;
6857 rtx cmpv
, newv
, val
, cc
, seq0
, seq1
, seq2
, seq3
;
6858 rtx res
= gen_reg_rtx (SImode
);
6859 rtx_code_label
*csloop
= NULL
, *csend
= NULL
;
6861 gcc_assert (MEM_P (mem
));
6863 init_alignment_context (&ac
, mem
, mode
);
6865 /* Load full word. Subsequent loads are performed by CS. */
6866 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
6867 NULL_RTX
, 1, OPTAB_DIRECT
);
6869 /* Prepare insertions of cmp and new_rtx into the loaded value. When
6870 possible, we try to use insv to make this happen efficiently. If
6871 that fails we'll generate code both inside and outside the loop. */
6872 cmpv
= s390_two_part_insv (&ac
, &seq0
, &seq2
, mode
, val
, cmp
);
6873 newv
= s390_two_part_insv (&ac
, &seq1
, &seq3
, mode
, val
, new_rtx
);
6880 /* Start CS loop. */
6883 /* Begin assuming success. */
6884 emit_move_insn (btarget
, const1_rtx
);
6886 csloop
= gen_label_rtx ();
6887 csend
= gen_label_rtx ();
6888 emit_label (csloop
);
6891 /* val = "<mem>00..0<mem>"
6892 * cmp = "00..0<cmp>00..0"
6893 * new = "00..0<new>00..0"
6899 cc
= s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
, cmpv
, newv
, CCZ1mode
);
6901 emit_insn (gen_cstorecc4 (btarget
, cc
, XEXP (cc
, 0), XEXP (cc
, 1)));
6906 /* Jump to end if we're done (likely?). */
6907 s390_emit_jump (csend
, cc
);
6909 /* Check for changes outside mode, and loop internal if so.
6910 Arrange the moves so that the compare is adjacent to the
6911 branch so that we can generate CRJ. */
6912 tmp
= copy_to_reg (val
);
6913 force_expand_binop (SImode
, and_optab
, res
, ac
.modemaski
, val
,
6915 cc
= s390_emit_compare (NE
, val
, tmp
);
6916 s390_emit_jump (csloop
, cc
);
6919 emit_move_insn (btarget
, const0_rtx
);
6923 /* Return the correct part of the bitfield. */
6924 convert_move (vtarget
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
6925 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
6928 /* Variant of s390_expand_cs for SI, DI and TI modes. */
6930 s390_expand_cs_tdsi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
6931 rtx cmp
, rtx new_rtx
, bool is_weak
)
6933 rtx output
= vtarget
;
6934 rtx_code_label
*skip_cs_label
= NULL
;
6935 bool do_const_opt
= false;
6937 if (!register_operand (output
, mode
))
6938 output
= gen_reg_rtx (mode
);
6940 /* If IS_WEAK is true and the INPUT value is a constant, compare the memory
6941 with the constant first and skip the compare_and_swap because its very
6942 expensive and likely to fail anyway.
6943 Note 1: This is done only for IS_WEAK. C11 allows optimizations that may
6944 cause spurious in that case.
6945 Note 2: It may be useful to do this also for non-constant INPUT.
6946 Note 3: Currently only targets with "load on condition" are supported
6947 (z196 and newer). */
6950 && (mode
== SImode
|| mode
== DImode
))
6951 do_const_opt
= (is_weak
&& CONST_INT_P (cmp
));
6955 rtx cc
= gen_rtx_REG (CCZmode
, CC_REGNUM
);
6957 skip_cs_label
= gen_label_rtx ();
6958 emit_move_insn (btarget
, const0_rtx
);
6959 if (CONST_INT_P (cmp
) && INTVAL (cmp
) == 0)
6961 rtvec lt
= rtvec_alloc (2);
6963 /* Load-and-test + conditional jump. */
6965 = gen_rtx_SET (cc
, gen_rtx_COMPARE (CCZmode
, mem
, cmp
));
6966 RTVEC_ELT (lt
, 1) = gen_rtx_SET (output
, mem
);
6967 emit_insn (gen_rtx_PARALLEL (VOIDmode
, lt
));
6971 emit_move_insn (output
, mem
);
6972 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (CCZmode
, output
, cmp
)));
6974 s390_emit_jump (skip_cs_label
, gen_rtx_NE (VOIDmode
, cc
, const0_rtx
));
6975 add_reg_br_prob_note (get_last_insn (),
6976 profile_probability::very_unlikely ());
6977 /* If the jump is not taken, OUTPUT is the expected value. */
6979 /* Reload newval to a register manually, *after* the compare and jump
6980 above. Otherwise Reload might place it before the jump. */
6983 cmp
= force_reg (mode
, cmp
);
6984 new_rtx
= force_reg (mode
, new_rtx
);
6985 s390_emit_compare_and_swap (EQ
, output
, mem
, cmp
, new_rtx
,
6986 (do_const_opt
) ? CCZmode
: CCZ1mode
);
6987 if (skip_cs_label
!= NULL
)
6988 emit_label (skip_cs_label
);
6990 /* We deliberately accept non-register operands in the predicate
6991 to ensure the write back to the output operand happens *before*
6992 the store-flags code below. This makes it easier for combine
6993 to merge the store-flags code with a potential test-and-branch
6994 pattern following (immediately!) afterwards. */
6995 if (output
!= vtarget
)
6996 emit_move_insn (vtarget
, output
);
7002 /* Do not use gen_cstorecc4 here because it writes either 1 or 0, but
7003 btarget has already been initialized with 0 above. */
7004 cc
= gen_rtx_REG (CCZmode
, CC_REGNUM
);
7005 cond
= gen_rtx_EQ (VOIDmode
, cc
, const0_rtx
);
7006 ite
= gen_rtx_IF_THEN_ELSE (SImode
, cond
, const1_rtx
, btarget
);
7007 emit_insn (gen_rtx_SET (btarget
, ite
));
7013 cc
= gen_rtx_REG (CCZ1mode
, CC_REGNUM
);
7014 cond
= gen_rtx_EQ (SImode
, cc
, const0_rtx
);
7015 emit_insn (gen_cstorecc4 (btarget
, cond
, cc
, const0_rtx
));
7019 /* Expand an atomic compare and swap operation. MEM is the memory location,
7020 CMP the old value to compare MEM with and NEW_RTX the value to set if
7024 s390_expand_cs (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
7025 rtx cmp
, rtx new_rtx
, bool is_weak
)
7032 s390_expand_cs_tdsi (mode
, btarget
, vtarget
, mem
, cmp
, new_rtx
, is_weak
);
7036 s390_expand_cs_hqi (mode
, btarget
, vtarget
, mem
, cmp
, new_rtx
, is_weak
);
7043 /* Expand an atomic_exchange operation simulated with a compare-and-swap loop.
7044 The memory location MEM is set to INPUT. OUTPUT is set to the previous value
7048 s390_expand_atomic_exchange_tdsi (rtx output
, rtx mem
, rtx input
)
7050 machine_mode mode
= GET_MODE (mem
);
7051 rtx_code_label
*csloop
;
7054 && (mode
== DImode
|| mode
== SImode
)
7055 && CONST_INT_P (input
) && INTVAL (input
) == 0)
7057 emit_move_insn (output
, const0_rtx
);
7059 emit_insn (gen_atomic_fetch_anddi (output
, mem
, const0_rtx
, input
));
7061 emit_insn (gen_atomic_fetch_andsi (output
, mem
, const0_rtx
, input
));
7065 input
= force_reg (mode
, input
);
7066 emit_move_insn (output
, mem
);
7067 csloop
= gen_label_rtx ();
7068 emit_label (csloop
);
7069 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, output
, mem
, output
,
7073 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
7074 and VAL the value to play with. If AFTER is true then store the value
7075 MEM holds after the operation, if AFTER is false then store the value MEM
7076 holds before the operation. If TARGET is zero then discard that value, else
7077 store it to TARGET. */
7080 s390_expand_atomic (machine_mode mode
, enum rtx_code code
,
7081 rtx target
, rtx mem
, rtx val
, bool after
)
7083 struct alignment_context ac
;
7085 rtx new_rtx
= gen_reg_rtx (SImode
);
7086 rtx orig
= gen_reg_rtx (SImode
);
7087 rtx_code_label
*csloop
= gen_label_rtx ();
7089 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
7090 gcc_assert (MEM_P (mem
));
7092 init_alignment_context (&ac
, mem
, mode
);
7094 /* Shift val to the correct bit positions.
7095 Preserve "icm", but prevent "ex icm". */
7096 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
7097 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
7099 /* Further preparation insns. */
7100 if (code
== PLUS
|| code
== MINUS
)
7101 emit_move_insn (orig
, val
);
7102 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
7103 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
7104 NULL_RTX
, 1, OPTAB_DIRECT
);
7106 /* Load full word. Subsequent loads are performed by CS. */
7107 cmp
= force_reg (SImode
, ac
.memsi
);
7109 /* Start CS loop. */
7110 emit_label (csloop
);
7111 emit_move_insn (new_rtx
, cmp
);
7113 /* Patch new with val at correct position. */
7118 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
7119 NULL_RTX
, 1, OPTAB_DIRECT
);
7120 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
7121 NULL_RTX
, 1, OPTAB_DIRECT
);
7124 if (ac
.aligned
&& MEM_P (val
))
7125 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
7126 0, 0, SImode
, val
, false);
7129 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
7130 NULL_RTX
, 1, OPTAB_DIRECT
);
7131 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
7132 NULL_RTX
, 1, OPTAB_DIRECT
);
7138 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
7139 NULL_RTX
, 1, OPTAB_DIRECT
);
7141 case MULT
: /* NAND */
7142 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
7143 NULL_RTX
, 1, OPTAB_DIRECT
);
7144 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
7145 NULL_RTX
, 1, OPTAB_DIRECT
);
7151 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
7152 ac
.memsi
, cmp
, new_rtx
,
7155 /* Return the correct part of the bitfield. */
7157 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
7158 after
? new_rtx
: cmp
, ac
.shift
,
7159 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
7162 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7163 We need to emit DTP-relative relocations. */
7165 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
7168 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7173 fputs ("\t.long\t", file
);
7176 fputs ("\t.quad\t", file
);
7181 output_addr_const (file
, x
);
7182 fputs ("@DTPOFF", file
);
7185 /* Return the proper mode for REGNO being represented in the dwarf
7188 s390_dwarf_frame_reg_mode (int regno
)
7190 machine_mode save_mode
= default_dwarf_frame_reg_mode (regno
);
7192 /* Make sure not to return DImode for any GPR with -m31 -mzarch. */
7193 if (GENERAL_REGNO_P (regno
))
7196 /* The rightmost 64 bits of vector registers are call-clobbered. */
7197 if (GET_MODE_SIZE (save_mode
) > 8)
7203 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
7204 /* Implement TARGET_MANGLE_TYPE. */
7207 s390_mangle_type (const_tree type
)
7209 type
= TYPE_MAIN_VARIANT (type
);
7211 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
7212 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
7215 if (type
== s390_builtin_types
[BT_BV16QI
]) return "U6__boolc";
7216 if (type
== s390_builtin_types
[BT_BV8HI
]) return "U6__bools";
7217 if (type
== s390_builtin_types
[BT_BV4SI
]) return "U6__booli";
7218 if (type
== s390_builtin_types
[BT_BV2DI
]) return "U6__booll";
7220 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
7221 && TARGET_LONG_DOUBLE_128
)
7224 /* For all other types, use normal C++ mangling. */
7229 /* In the name of slightly smaller debug output, and to cater to
7230 general assembler lossage, recognize various UNSPEC sequences
7231 and turn them back into a direct symbol reference. */
7234 s390_delegitimize_address (rtx orig_x
)
7238 orig_x
= delegitimize_mem_from_attrs (orig_x
);
7241 /* Extract the symbol ref from:
7242 (plus:SI (reg:SI 12 %r12)
7243 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
7244 UNSPEC_GOTOFF/PLTOFF)))
7246 (plus:SI (reg:SI 12 %r12)
7247 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
7248 UNSPEC_GOTOFF/PLTOFF)
7249 (const_int 4 [0x4])))) */
7250 if (GET_CODE (x
) == PLUS
7251 && REG_P (XEXP (x
, 0))
7252 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
7253 && GET_CODE (XEXP (x
, 1)) == CONST
)
7255 HOST_WIDE_INT offset
= 0;
7257 /* The const operand. */
7258 y
= XEXP (XEXP (x
, 1), 0);
7260 if (GET_CODE (y
) == PLUS
7261 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
7263 offset
= INTVAL (XEXP (y
, 1));
7267 if (GET_CODE (y
) == UNSPEC
7268 && (XINT (y
, 1) == UNSPEC_GOTOFF
7269 || XINT (y
, 1) == UNSPEC_PLTOFF
))
7270 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
7273 if (GET_CODE (x
) != MEM
)
7277 if (GET_CODE (x
) == PLUS
7278 && GET_CODE (XEXP (x
, 1)) == CONST
7279 && GET_CODE (XEXP (x
, 0)) == REG
7280 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
7282 y
= XEXP (XEXP (x
, 1), 0);
7283 if (GET_CODE (y
) == UNSPEC
7284 && XINT (y
, 1) == UNSPEC_GOT
)
7285 y
= XVECEXP (y
, 0, 0);
7289 else if (GET_CODE (x
) == CONST
)
7291 /* Extract the symbol ref from:
7292 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
7293 UNSPEC_PLT/GOTENT))) */
7296 if (GET_CODE (y
) == UNSPEC
7297 && (XINT (y
, 1) == UNSPEC_GOTENT
7298 || XINT (y
, 1) == UNSPEC_PLT
))
7299 y
= XVECEXP (y
, 0, 0);
7306 if (GET_MODE (orig_x
) != Pmode
)
7308 if (GET_MODE (orig_x
) == BLKmode
)
7310 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
7317 /* Output operand OP to stdio stream FILE.
7318 OP is an address (register + offset) which is not used to address data;
7319 instead the rightmost bits are interpreted as the value. */
7322 print_addrstyle_operand (FILE *file
, rtx op
)
7324 HOST_WIDE_INT offset
;
7327 /* Extract base register and offset. */
7328 if (!s390_decompose_addrstyle_without_index (op
, &base
, &offset
))
7334 gcc_assert (GET_CODE (base
) == REG
);
7335 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
7336 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
7339 /* Offsets are constricted to twelve bits. */
7340 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
7342 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
7345 /* Assigns the number of NOP halfwords to be emitted before and after the
7346 function label to *HW_BEFORE and *HW_AFTER. Both pointers must not be NULL.
7347 If hotpatching is disabled for the function, the values are set to zero.
7351 s390_function_num_hotpatch_hw (tree decl
,
7357 attr
= lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl
));
7359 /* Handle the arguments of the hotpatch attribute. The values
7360 specified via attribute might override the cmdline argument
7364 tree args
= TREE_VALUE (attr
);
7366 *hw_before
= TREE_INT_CST_LOW (TREE_VALUE (args
));
7367 *hw_after
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (args
)));
7371 /* Use the values specified by the cmdline arguments. */
7372 *hw_before
= s390_hotpatch_hw_before_label
;
7373 *hw_after
= s390_hotpatch_hw_after_label
;
7377 /* Write the current .machine and .machinemode specification to the assembler
7380 #ifdef HAVE_AS_MACHINE_MACHINEMODE
7382 s390_asm_output_machine_for_arch (FILE *asm_out_file
)
7384 fprintf (asm_out_file
, "\t.machinemode %s\n",
7385 (TARGET_ZARCH
) ? "zarch" : "esa");
7386 fprintf (asm_out_file
, "\t.machine \"%s",
7387 processor_table
[s390_arch
].binutils_name
);
7388 if (S390_USE_ARCHITECTURE_MODIFIERS
)
7392 cpu_flags
= processor_flags_table
[(int) s390_arch
];
7393 if (TARGET_HTM
&& !(cpu_flags
& PF_TX
))
7394 fprintf (asm_out_file
, "+htm");
7395 else if (!TARGET_HTM
&& (cpu_flags
& PF_TX
))
7396 fprintf (asm_out_file
, "+nohtm");
7397 if (TARGET_VX
&& !(cpu_flags
& PF_VX
))
7398 fprintf (asm_out_file
, "+vx");
7399 else if (!TARGET_VX
&& (cpu_flags
& PF_VX
))
7400 fprintf (asm_out_file
, "+novx");
7402 fprintf (asm_out_file
, "\"\n");
7405 /* Write an extra function header before the very start of the function. */
7408 s390_asm_output_function_prefix (FILE *asm_out_file
,
7409 const char *fnname ATTRIBUTE_UNUSED
)
7411 if (DECL_FUNCTION_SPECIFIC_TARGET (current_function_decl
) == NULL
)
7413 /* Since only the function specific options are saved but not the indications
7414 which options are set, it's too much work here to figure out which options
7415 have actually changed. Thus, generate .machine and .machinemode whenever a
7416 function has the target attribute or pragma. */
7417 fprintf (asm_out_file
, "\t.machinemode push\n");
7418 fprintf (asm_out_file
, "\t.machine push\n");
7419 s390_asm_output_machine_for_arch (asm_out_file
);
7422 /* Write an extra function footer after the very end of the function. */
7425 s390_asm_declare_function_size (FILE *asm_out_file
,
7426 const char *fnname
, tree decl
)
7428 if (!flag_inhibit_size_directive
)
7429 ASM_OUTPUT_MEASURED_SIZE (asm_out_file
, fnname
);
7430 if (DECL_FUNCTION_SPECIFIC_TARGET (decl
) == NULL
)
7432 fprintf (asm_out_file
, "\t.machine pop\n");
7433 fprintf (asm_out_file
, "\t.machinemode pop\n");
7437 /* Write the extra assembler code needed to declare a function properly. */
7440 s390_asm_output_function_label (FILE *asm_out_file
, const char *fname
,
7443 int hw_before
, hw_after
;
7445 s390_function_num_hotpatch_hw (decl
, &hw_before
, &hw_after
);
7448 unsigned int function_alignment
;
7451 /* Add a trampoline code area before the function label and initialize it
7452 with two-byte nop instructions. This area can be overwritten with code
7453 that jumps to a patched version of the function. */
7454 asm_fprintf (asm_out_file
, "\tnopr\t%%r0"
7455 "\t# pre-label NOPs for hotpatch (%d halfwords)\n",
7457 for (i
= 1; i
< hw_before
; i
++)
7458 fputs ("\tnopr\t%r0\n", asm_out_file
);
7460 /* Note: The function label must be aligned so that (a) the bytes of the
7461 following nop do not cross a cacheline boundary, and (b) a jump address
7462 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
7463 stored directly before the label without crossing a cacheline
7464 boundary. All this is necessary to make sure the trampoline code can
7465 be changed atomically.
7466 This alignment is done automatically using the FOUNCTION_BOUNDARY, but
7467 if there are NOPs before the function label, the alignment is placed
7468 before them. So it is necessary to duplicate the alignment after the
7470 function_alignment
= MAX (8, DECL_ALIGN (decl
) / BITS_PER_UNIT
);
7471 if (! DECL_USER_ALIGN (decl
))
7473 = MAX (function_alignment
,
7474 (unsigned int) align_functions
.levels
[0].get_value ());
7475 fputs ("\t# alignment for hotpatch\n", asm_out_file
);
7476 ASM_OUTPUT_ALIGN (asm_out_file
, align_functions
.levels
[0].log
);
7479 if (S390_USE_TARGET_ATTRIBUTE
&& TARGET_DEBUG_ARG
)
7481 asm_fprintf (asm_out_file
, "\t# fn:%s ar%d\n", fname
, s390_arch
);
7482 asm_fprintf (asm_out_file
, "\t# fn:%s tu%d\n", fname
, s390_tune
);
7483 asm_fprintf (asm_out_file
, "\t# fn:%s sg%d\n", fname
, s390_stack_guard
);
7484 asm_fprintf (asm_out_file
, "\t# fn:%s ss%d\n", fname
, s390_stack_size
);
7485 asm_fprintf (asm_out_file
, "\t# fn:%s bc%d\n", fname
, s390_branch_cost
);
7486 asm_fprintf (asm_out_file
, "\t# fn:%s wf%d\n", fname
,
7487 s390_warn_framesize
);
7488 asm_fprintf (asm_out_file
, "\t# fn:%s ba%d\n", fname
, TARGET_BACKCHAIN
);
7489 asm_fprintf (asm_out_file
, "\t# fn:%s hd%d\n", fname
, TARGET_HARD_DFP
);
7490 asm_fprintf (asm_out_file
, "\t# fn:%s hf%d\n", fname
, !TARGET_SOFT_FLOAT
);
7491 asm_fprintf (asm_out_file
, "\t# fn:%s ht%d\n", fname
, TARGET_OPT_HTM
);
7492 asm_fprintf (asm_out_file
, "\t# fn:%s vx%d\n", fname
, TARGET_OPT_VX
);
7493 asm_fprintf (asm_out_file
, "\t# fn:%s ps%d\n", fname
,
7494 TARGET_PACKED_STACK
);
7495 asm_fprintf (asm_out_file
, "\t# fn:%s se%d\n", fname
, TARGET_SMALL_EXEC
);
7496 asm_fprintf (asm_out_file
, "\t# fn:%s mv%d\n", fname
, TARGET_MVCLE
);
7497 asm_fprintf (asm_out_file
, "\t# fn:%s zv%d\n", fname
, TARGET_ZVECTOR
);
7498 asm_fprintf (asm_out_file
, "\t# fn:%s wd%d\n", fname
,
7499 s390_warn_dynamicstack_p
);
7501 ASM_OUTPUT_LABEL (asm_out_file
, fname
);
7503 asm_fprintf (asm_out_file
,
7504 "\t# post-label NOPs for hotpatch (%d halfwords)\n",
7508 /* Output machine-dependent UNSPECs occurring in address constant X
7509 in assembler syntax to stdio stream FILE. Returns true if the
7510 constant X could be recognized, false otherwise. */
7513 s390_output_addr_const_extra (FILE *file
, rtx x
)
7515 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
7516 switch (XINT (x
, 1))
7519 output_addr_const (file
, XVECEXP (x
, 0, 0));
7520 fprintf (file
, "@GOTENT");
7523 output_addr_const (file
, XVECEXP (x
, 0, 0));
7524 fprintf (file
, "@GOT");
7527 output_addr_const (file
, XVECEXP (x
, 0, 0));
7528 fprintf (file
, "@GOTOFF");
7531 output_addr_const (file
, XVECEXP (x
, 0, 0));
7532 fprintf (file
, "@PLT");
7535 output_addr_const (file
, XVECEXP (x
, 0, 0));
7536 fprintf (file
, "@PLTOFF");
7539 output_addr_const (file
, XVECEXP (x
, 0, 0));
7540 fprintf (file
, "@TLSGD");
7543 assemble_name (file
, get_some_local_dynamic_name ());
7544 fprintf (file
, "@TLSLDM");
7547 output_addr_const (file
, XVECEXP (x
, 0, 0));
7548 fprintf (file
, "@DTPOFF");
7551 output_addr_const (file
, XVECEXP (x
, 0, 0));
7552 fprintf (file
, "@NTPOFF");
7554 case UNSPEC_GOTNTPOFF
:
7555 output_addr_const (file
, XVECEXP (x
, 0, 0));
7556 fprintf (file
, "@GOTNTPOFF");
7558 case UNSPEC_INDNTPOFF
:
7559 output_addr_const (file
, XVECEXP (x
, 0, 0));
7560 fprintf (file
, "@INDNTPOFF");
7564 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
7565 switch (XINT (x
, 1))
7567 case UNSPEC_POOL_OFFSET
:
7568 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
7569 output_addr_const (file
, x
);
7575 /* Output address operand ADDR in assembler syntax to
7576 stdio stream FILE. */
7579 print_operand_address (FILE *file
, rtx addr
)
7581 struct s390_address ad
;
7582 memset (&ad
, 0, sizeof (s390_address
));
7584 if (s390_loadrelative_operand_p (addr
, NULL
, NULL
))
7588 output_operand_lossage ("symbolic memory references are "
7589 "only supported on z10 or later");
7592 output_addr_const (file
, addr
);
7596 if (!s390_decompose_address (addr
, &ad
)
7597 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7598 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
7599 output_operand_lossage ("cannot decompose address");
7602 output_addr_const (file
, ad
.disp
);
7604 fprintf (file
, "0");
7606 if (ad
.base
&& ad
.indx
)
7607 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
7608 reg_names
[REGNO (ad
.base
)]);
7610 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
7613 /* Output operand X in assembler syntax to stdio stream FILE.
7614 CODE specified the format flag. The following format flags
7617 'A': On z14 or higher: If operand is a mem print the alignment
7618 hint usable with vl/vst prefixed by a comma.
7619 'C': print opcode suffix for branch condition.
7620 'D': print opcode suffix for inverse branch condition.
7621 'E': print opcode suffix for branch on index instruction.
7622 'G': print the size of the operand in bytes.
7623 'J': print tls_load/tls_gdcall/tls_ldcall suffix
7624 'M': print the second word of a TImode operand.
7625 'N': print the second word of a DImode operand.
7626 'O': print only the displacement of a memory reference or address.
7627 'R': print only the base register of a memory reference or address.
7628 'S': print S-type memory reference (base+displacement).
7629 'Y': print address style operand without index (e.g. shift count or setmem
7632 'b': print integer X as if it's an unsigned byte.
7633 'c': print integer X as if it's an signed byte.
7634 'e': "end" contiguous bitmask X in either DImode or vector inner mode.
7635 'f': "end" contiguous bitmask X in SImode.
7636 'h': print integer X as if it's a signed halfword.
7637 'i': print the first nonzero HImode part of X.
7638 'j': print the first HImode part unequal to -1 of X.
7639 'k': print the first nonzero SImode part of X.
7640 'm': print the first SImode part unequal to -1 of X.
7641 'o': print integer X as if it's an unsigned 32bit word.
7642 's': "start" of contiguous bitmask X in either DImode or vector inner mode.
7643 't': CONST_INT: "start" of contiguous bitmask X in SImode.
7644 CONST_VECTOR: Generate a bitmask for vgbm instruction.
7645 'x': print integer X as if it's an unsigned halfword.
7646 'v': print register number as vector register (v1 instead of f1).
7650 print_operand (FILE *file
, rtx x
, int code
)
7657 #ifdef HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS
7658 if (TARGET_Z14
&& MEM_P (x
))
7660 if (MEM_ALIGN (x
) >= 128)
7661 fprintf (file
, ",4");
7662 else if (MEM_ALIGN (x
) == 64)
7663 fprintf (file
, ",3");
7668 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
7672 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
7676 if (GET_CODE (x
) == LE
)
7677 fprintf (file
, "l");
7678 else if (GET_CODE (x
) == GT
)
7679 fprintf (file
, "h");
7681 output_operand_lossage ("invalid comparison operator "
7682 "for 'E' output modifier");
7686 if (GET_CODE (x
) == SYMBOL_REF
)
7688 fprintf (file
, "%s", ":tls_load:");
7689 output_addr_const (file
, x
);
7691 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
7693 fprintf (file
, "%s", ":tls_gdcall:");
7694 output_addr_const (file
, XVECEXP (x
, 0, 0));
7696 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
7698 fprintf (file
, "%s", ":tls_ldcall:");
7699 const char *name
= get_some_local_dynamic_name ();
7701 assemble_name (file
, name
);
7704 output_operand_lossage ("invalid reference for 'J' output modifier");
7708 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
7713 struct s390_address ad
;
7716 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
7719 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7722 output_operand_lossage ("invalid address for 'O' output modifier");
7727 output_addr_const (file
, ad
.disp
);
7729 fprintf (file
, "0");
7735 struct s390_address ad
;
7738 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
7741 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7744 output_operand_lossage ("invalid address for 'R' output modifier");
7749 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
7751 fprintf (file
, "0");
7757 struct s390_address ad
;
7762 output_operand_lossage ("memory reference expected for "
7763 "'S' output modifier");
7766 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
7769 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7772 output_operand_lossage ("invalid address for 'S' output modifier");
7777 output_addr_const (file
, ad
.disp
);
7779 fprintf (file
, "0");
7782 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
7787 if (GET_CODE (x
) == REG
)
7788 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
7789 else if (GET_CODE (x
) == MEM
)
7790 x
= change_address (x
, VOIDmode
,
7791 plus_constant (Pmode
, XEXP (x
, 0), 4));
7793 output_operand_lossage ("register or memory expression expected "
7794 "for 'N' output modifier");
7798 if (GET_CODE (x
) == REG
)
7799 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
7800 else if (GET_CODE (x
) == MEM
)
7801 x
= change_address (x
, VOIDmode
,
7802 plus_constant (Pmode
, XEXP (x
, 0), 8));
7804 output_operand_lossage ("register or memory expression expected "
7805 "for 'M' output modifier");
7809 print_addrstyle_operand (file
, x
);
7813 switch (GET_CODE (x
))
7816 /* Print FP regs as fx instead of vx when they are accessed
7817 through non-vector mode. */
7819 || VECTOR_NOFP_REG_P (x
)
7820 || (FP_REG_P (x
) && VECTOR_MODE_P (GET_MODE (x
)))
7821 || (VECTOR_REG_P (x
)
7822 && (GET_MODE_SIZE (GET_MODE (x
)) /
7823 s390_class_max_nregs (FP_REGS
, GET_MODE (x
))) > 8))
7824 fprintf (file
, "%%v%s", reg_names
[REGNO (x
)] + 2);
7826 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
7830 output_address (GET_MODE (x
), XEXP (x
, 0));
7837 output_addr_const (file
, x
);
7850 ival
= ((ival
& 0xff) ^ 0x80) - 0x80;
7856 ival
= ((ival
& 0xffff) ^ 0x8000) - 0x8000;
7859 ival
= s390_extract_part (x
, HImode
, 0);
7862 ival
= s390_extract_part (x
, HImode
, -1);
7865 ival
= s390_extract_part (x
, SImode
, 0);
7868 ival
= s390_extract_part (x
, SImode
, -1);
7880 len
= (code
== 's' || code
== 'e' ? 64 : 32);
7881 ok
= s390_contiguous_bitmask_p (ival
, true, len
, &start
, &end
);
7883 if (code
== 's' || code
== 't')
7890 output_operand_lossage ("invalid constant for output modifier '%c'", code
);
7892 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7895 case CONST_WIDE_INT
:
7897 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7898 CONST_WIDE_INT_ELT (x
, 0) & 0xff);
7899 else if (code
== 'x')
7900 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7901 CONST_WIDE_INT_ELT (x
, 0) & 0xffff);
7902 else if (code
== 'h')
7903 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7904 ((CONST_WIDE_INT_ELT (x
, 0) & 0xffff) ^ 0x8000) - 0x8000);
7908 output_operand_lossage ("invalid constant - try using "
7909 "an output modifier");
7911 output_operand_lossage ("invalid constant for output modifier '%c'",
7919 gcc_assert (const_vec_duplicate_p (x
));
7920 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7921 ((INTVAL (XVECEXP (x
, 0, 0)) & 0xffff) ^ 0x8000) - 0x8000);
7929 ok
= s390_contiguous_bitmask_vector_p (x
, &start
, &end
);
7931 ival
= (code
== 's') ? start
: end
;
7932 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7938 bool ok
= s390_bytemask_vector_p (x
, &mask
);
7940 fprintf (file
, "%u", mask
);
7945 output_operand_lossage ("invalid constant vector for output "
7946 "modifier '%c'", code
);
7952 output_operand_lossage ("invalid expression - try using "
7953 "an output modifier");
7955 output_operand_lossage ("invalid expression for output "
7956 "modifier '%c'", code
);
7961 /* Target hook for assembling integer objects. We need to define it
7962 here to work a round a bug in some versions of GAS, which couldn't
7963 handle values smaller than INT_MIN when printed in decimal. */
7966 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
7968 if (size
== 8 && aligned_p
7969 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
7971 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
7975 return default_assemble_integer (x
, size
, aligned_p
);
7978 /* Returns true if register REGNO is used for forming
7979 a memory address in expression X. */
7982 reg_used_in_mem_p (int regno
, rtx x
)
7984 enum rtx_code code
= GET_CODE (x
);
7990 if (refers_to_regno_p (regno
, XEXP (x
, 0)))
7993 else if (code
== SET
7994 && GET_CODE (SET_DEST (x
)) == PC
)
7996 if (refers_to_regno_p (regno
, SET_SRC (x
)))
8000 fmt
= GET_RTX_FORMAT (code
);
8001 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8004 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
8007 else if (fmt
[i
] == 'E')
8008 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8009 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
8015 /* Returns true if expression DEP_RTX sets an address register
8016 used by instruction INSN to address memory. */
8019 addr_generation_dependency_p (rtx dep_rtx
, rtx_insn
*insn
)
8023 if (NONJUMP_INSN_P (dep_rtx
))
8024 dep_rtx
= PATTERN (dep_rtx
);
8026 if (GET_CODE (dep_rtx
) == SET
)
8028 target
= SET_DEST (dep_rtx
);
8029 if (GET_CODE (target
) == STRICT_LOW_PART
)
8030 target
= XEXP (target
, 0);
8031 while (GET_CODE (target
) == SUBREG
)
8032 target
= SUBREG_REG (target
);
8034 if (GET_CODE (target
) == REG
)
8036 int regno
= REGNO (target
);
8038 if (s390_safe_attr_type (insn
) == TYPE_LA
)
8040 pat
= PATTERN (insn
);
8041 if (GET_CODE (pat
) == PARALLEL
)
8043 gcc_assert (XVECLEN (pat
, 0) == 2);
8044 pat
= XVECEXP (pat
, 0, 0);
8046 gcc_assert (GET_CODE (pat
) == SET
);
8047 return refers_to_regno_p (regno
, SET_SRC (pat
));
8049 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
8050 return reg_used_in_mem_p (regno
, PATTERN (insn
));
8056 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
8059 s390_agen_dep_p (rtx_insn
*dep_insn
, rtx_insn
*insn
)
8061 rtx dep_rtx
= PATTERN (dep_insn
);
8064 if (GET_CODE (dep_rtx
) == SET
8065 && addr_generation_dependency_p (dep_rtx
, insn
))
8067 else if (GET_CODE (dep_rtx
) == PARALLEL
)
8069 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
8071 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
8079 /* A C statement (sans semicolon) to update the integer scheduling priority
8080 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
8081 reduce the priority to execute INSN later. Do not define this macro if
8082 you do not need to adjust the scheduling priorities of insns.
8084 A STD instruction should be scheduled earlier,
8085 in order to use the bypass. */
8087 s390_adjust_priority (rtx_insn
*insn
, int priority
)
8089 if (! INSN_P (insn
))
8092 if (s390_tune
<= PROCESSOR_2064_Z900
)
8095 switch (s390_safe_attr_type (insn
))
8099 priority
= priority
<< 3;
8103 priority
= priority
<< 1;
8112 /* The number of instructions that can be issued per cycle. */
8115 s390_issue_rate (void)
8119 case PROCESSOR_2084_Z990
:
8120 case PROCESSOR_2094_Z9_109
:
8121 case PROCESSOR_2094_Z9_EC
:
8122 case PROCESSOR_2817_Z196
:
8124 case PROCESSOR_2097_Z10
:
8126 case PROCESSOR_2064_Z900
:
8127 /* Starting with EC12 we use the sched_reorder hook to take care
8128 of instruction dispatch constraints. The algorithm only
8129 picks the best instruction and assumes only a single
8130 instruction gets issued per cycle. */
8131 case PROCESSOR_2827_ZEC12
:
8132 case PROCESSOR_2964_Z13
:
8133 case PROCESSOR_3906_Z14
:
8140 s390_first_cycle_multipass_dfa_lookahead (void)
8146 annotate_constant_pool_refs_1 (rtx
*x
)
8151 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
8152 || !CONSTANT_POOL_ADDRESS_P (*x
));
8154 /* Literal pool references can only occur inside a MEM ... */
8155 if (GET_CODE (*x
) == MEM
)
8157 rtx memref
= XEXP (*x
, 0);
8159 if (GET_CODE (memref
) == SYMBOL_REF
8160 && CONSTANT_POOL_ADDRESS_P (memref
))
8162 rtx base
= cfun
->machine
->base_reg
;
8163 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
8166 *x
= replace_equiv_address (*x
, addr
);
8170 if (GET_CODE (memref
) == CONST
8171 && GET_CODE (XEXP (memref
, 0)) == PLUS
8172 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
8173 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
8174 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
8176 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
8177 rtx sym
= XEXP (XEXP (memref
, 0), 0);
8178 rtx base
= cfun
->machine
->base_reg
;
8179 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
8182 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
8187 /* ... or a load-address type pattern. */
8188 if (GET_CODE (*x
) == SET
)
8190 rtx addrref
= SET_SRC (*x
);
8192 if (GET_CODE (addrref
) == SYMBOL_REF
8193 && CONSTANT_POOL_ADDRESS_P (addrref
))
8195 rtx base
= cfun
->machine
->base_reg
;
8196 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
8199 SET_SRC (*x
) = addr
;
8203 if (GET_CODE (addrref
) == CONST
8204 && GET_CODE (XEXP (addrref
, 0)) == PLUS
8205 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
8206 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
8207 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
8209 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
8210 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
8211 rtx base
= cfun
->machine
->base_reg
;
8212 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
8215 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
8220 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
8221 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
8225 annotate_constant_pool_refs_1 (&XEXP (*x
, i
));
8227 else if (fmt
[i
] == 'E')
8229 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
8230 annotate_constant_pool_refs_1 (&XVECEXP (*x
, i
, j
));
8235 /* Annotate every literal pool reference in INSN by an UNSPEC_LTREF expression.
8236 Fix up MEMs as required.
8237 Skip insns which support relative addressing, because they do not use a base
8241 annotate_constant_pool_refs (rtx_insn
*insn
)
8243 if (s390_safe_relative_long_p (insn
))
8245 annotate_constant_pool_refs_1 (&PATTERN (insn
));
8249 find_constant_pool_ref_1 (rtx x
, rtx
*ref
)
8254 /* Likewise POOL_ENTRY insns. */
8255 if (GET_CODE (x
) == UNSPEC_VOLATILE
8256 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
8259 gcc_assert (GET_CODE (x
) != SYMBOL_REF
8260 || !CONSTANT_POOL_ADDRESS_P (x
));
8262 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
8264 rtx sym
= XVECEXP (x
, 0, 0);
8265 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
8266 && CONSTANT_POOL_ADDRESS_P (sym
));
8268 if (*ref
== NULL_RTX
)
8271 gcc_assert (*ref
== sym
);
8276 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
8277 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8281 find_constant_pool_ref_1 (XEXP (x
, i
), ref
);
8283 else if (fmt
[i
] == 'E')
8285 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8286 find_constant_pool_ref_1 (XVECEXP (x
, i
, j
), ref
);
8291 /* Find an annotated literal pool symbol referenced in INSN,
8292 and store it at REF. Will abort if INSN contains references to
8293 more than one such pool symbol; multiple references to the same
8294 symbol are allowed, however.
8296 The rtx pointed to by REF must be initialized to NULL_RTX
8297 by the caller before calling this routine.
8299 Skip insns which support relative addressing, because they do not use a base
8303 find_constant_pool_ref (rtx_insn
*insn
, rtx
*ref
)
8305 if (s390_safe_relative_long_p (insn
))
8307 find_constant_pool_ref_1 (PATTERN (insn
), ref
);
8311 replace_constant_pool_ref_1 (rtx
*x
, rtx ref
, rtx offset
)
8316 gcc_assert (*x
!= ref
);
8318 if (GET_CODE (*x
) == UNSPEC
8319 && XINT (*x
, 1) == UNSPEC_LTREF
8320 && XVECEXP (*x
, 0, 0) == ref
)
8322 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
8326 if (GET_CODE (*x
) == PLUS
8327 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
8328 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
8329 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
8330 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
8332 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
8333 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
8337 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
8338 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
8342 replace_constant_pool_ref_1 (&XEXP (*x
, i
), ref
, offset
);
8344 else if (fmt
[i
] == 'E')
8346 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
8347 replace_constant_pool_ref_1 (&XVECEXP (*x
, i
, j
), ref
, offset
);
8352 /* Replace every reference to the annotated literal pool
8353 symbol REF in INSN by its base plus OFFSET.
8354 Skip insns which support relative addressing, because they do not use a base
8358 replace_constant_pool_ref (rtx_insn
*insn
, rtx ref
, rtx offset
)
8360 if (s390_safe_relative_long_p (insn
))
8362 replace_constant_pool_ref_1 (&PATTERN (insn
), ref
, offset
);
8365 /* We keep a list of constants which we have to add to internal
8366 constant tables in the middle of large functions. */
8368 #define NR_C_MODES 32
8369 machine_mode constant_modes
[NR_C_MODES
] =
8371 TFmode
, TImode
, TDmode
,
8372 V16QImode
, V8HImode
, V4SImode
, V2DImode
, V1TImode
,
8373 V4SFmode
, V2DFmode
, V1TFmode
,
8374 DFmode
, DImode
, DDmode
,
8375 V8QImode
, V4HImode
, V2SImode
, V1DImode
, V2SFmode
, V1DFmode
,
8376 SFmode
, SImode
, SDmode
,
8377 V4QImode
, V2HImode
, V1SImode
, V1SFmode
,
8386 struct constant
*next
;
8388 rtx_code_label
*label
;
8391 struct constant_pool
8393 struct constant_pool
*next
;
8394 rtx_insn
*first_insn
;
8395 rtx_insn
*pool_insn
;
8397 rtx_insn
*emit_pool_after
;
8399 struct constant
*constants
[NR_C_MODES
];
8400 struct constant
*execute
;
8401 rtx_code_label
*label
;
8405 /* Allocate new constant_pool structure. */
8407 static struct constant_pool
*
8408 s390_alloc_pool (void)
8410 struct constant_pool
*pool
;
8413 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
8415 for (i
= 0; i
< NR_C_MODES
; i
++)
8416 pool
->constants
[i
] = NULL
;
8418 pool
->execute
= NULL
;
8419 pool
->label
= gen_label_rtx ();
8420 pool
->first_insn
= NULL
;
8421 pool
->pool_insn
= NULL
;
8422 pool
->insns
= BITMAP_ALLOC (NULL
);
8424 pool
->emit_pool_after
= NULL
;
8429 /* Create new constant pool covering instructions starting at INSN
8430 and chain it to the end of POOL_LIST. */
8432 static struct constant_pool
*
8433 s390_start_pool (struct constant_pool
**pool_list
, rtx_insn
*insn
)
8435 struct constant_pool
*pool
, **prev
;
8437 pool
= s390_alloc_pool ();
8438 pool
->first_insn
= insn
;
8440 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
8447 /* End range of instructions covered by POOL at INSN and emit
8448 placeholder insn representing the pool. */
8451 s390_end_pool (struct constant_pool
*pool
, rtx_insn
*insn
)
8453 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
8456 insn
= get_last_insn ();
8458 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
8459 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8462 /* Add INSN to the list of insns covered by POOL. */
8465 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
8467 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
8470 /* Return pool out of POOL_LIST that covers INSN. */
8472 static struct constant_pool
*
8473 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
8475 struct constant_pool
*pool
;
8477 for (pool
= pool_list
; pool
; pool
= pool
->next
)
8478 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
8484 /* Add constant VAL of mode MODE to the constant pool POOL. */
8487 s390_add_constant (struct constant_pool
*pool
, rtx val
, machine_mode mode
)
8492 for (i
= 0; i
< NR_C_MODES
; i
++)
8493 if (constant_modes
[i
] == mode
)
8495 gcc_assert (i
!= NR_C_MODES
);
8497 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
8498 if (rtx_equal_p (val
, c
->value
))
8503 c
= (struct constant
*) xmalloc (sizeof *c
);
8505 c
->label
= gen_label_rtx ();
8506 c
->next
= pool
->constants
[i
];
8507 pool
->constants
[i
] = c
;
8508 pool
->size
+= GET_MODE_SIZE (mode
);
8512 /* Return an rtx that represents the offset of X from the start of
8516 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
8520 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
8521 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
8522 UNSPEC_POOL_OFFSET
);
8523 return gen_rtx_CONST (GET_MODE (x
), x
);
8526 /* Find constant VAL of mode MODE in the constant pool POOL.
8527 Return an RTX describing the distance from the start of
8528 the pool to the location of the new constant. */
8531 s390_find_constant (struct constant_pool
*pool
, rtx val
,
8537 for (i
= 0; i
< NR_C_MODES
; i
++)
8538 if (constant_modes
[i
] == mode
)
8540 gcc_assert (i
!= NR_C_MODES
);
8542 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
8543 if (rtx_equal_p (val
, c
->value
))
8548 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
8551 /* Check whether INSN is an execute. Return the label_ref to its
8552 execute target template if so, NULL_RTX otherwise. */
8555 s390_execute_label (rtx insn
)
8558 && GET_CODE (PATTERN (insn
)) == PARALLEL
8559 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
8560 && (XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
8561 || XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE_JUMP
))
8563 if (XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
8564 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
8567 gcc_assert (JUMP_P (insn
));
8568 /* For jump insns as execute target:
8569 - There is one operand less in the parallel (the
8570 modification register of the execute is always 0).
8571 - The execute target label is wrapped into an
8572 if_then_else in order to hide it from jump analysis. */
8573 return XEXP (XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 0), 0);
8580 /* Find execute target for INSN in the constant pool POOL.
8581 Return an RTX describing the distance from the start of
8582 the pool to the location of the execute target. */
8585 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
8589 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
8590 if (INSN_UID (insn
) == INSN_UID (c
->value
))
8595 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
8598 /* For an execute INSN, extract the execute target template. */
8601 s390_execute_target (rtx insn
)
8603 rtx pattern
= PATTERN (insn
);
8604 gcc_assert (s390_execute_label (insn
));
8606 if (XVECLEN (pattern
, 0) == 2)
8608 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
8612 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
8615 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
8616 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
8618 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
8624 /* Indicate that INSN cannot be duplicated. This is the case for
8625 execute insns that carry a unique label. */
8628 s390_cannot_copy_insn_p (rtx_insn
*insn
)
8630 rtx label
= s390_execute_label (insn
);
8631 return label
&& label
!= const0_rtx
;
8634 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
8635 do not emit the pool base label. */
8638 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
8641 rtx_insn
*insn
= pool
->pool_insn
;
8644 /* Switch to rodata section. */
8645 insn
= emit_insn_after (gen_pool_section_start (), insn
);
8646 INSN_ADDRESSES_NEW (insn
, -1);
8648 /* Ensure minimum pool alignment. */
8649 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
8650 INSN_ADDRESSES_NEW (insn
, -1);
8652 /* Emit pool base label. */
8655 insn
= emit_label_after (pool
->label
, insn
);
8656 INSN_ADDRESSES_NEW (insn
, -1);
8659 /* Dump constants in descending alignment requirement order,
8660 ensuring proper alignment for every constant. */
8661 for (i
= 0; i
< NR_C_MODES
; i
++)
8662 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
8664 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
8665 rtx value
= copy_rtx (c
->value
);
8666 if (GET_CODE (value
) == CONST
8667 && GET_CODE (XEXP (value
, 0)) == UNSPEC
8668 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
8669 && XVECLEN (XEXP (value
, 0), 0) == 1)
8670 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
8672 insn
= emit_label_after (c
->label
, insn
);
8673 INSN_ADDRESSES_NEW (insn
, -1);
8675 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
8676 gen_rtvec (1, value
),
8677 UNSPECV_POOL_ENTRY
);
8678 insn
= emit_insn_after (value
, insn
);
8679 INSN_ADDRESSES_NEW (insn
, -1);
8682 /* Ensure minimum alignment for instructions. */
8683 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
8684 INSN_ADDRESSES_NEW (insn
, -1);
8686 /* Output in-pool execute template insns. */
8687 for (c
= pool
->execute
; c
; c
= c
->next
)
8689 insn
= emit_label_after (c
->label
, insn
);
8690 INSN_ADDRESSES_NEW (insn
, -1);
8692 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
8693 INSN_ADDRESSES_NEW (insn
, -1);
8696 /* Switch back to previous section. */
8697 insn
= emit_insn_after (gen_pool_section_end (), insn
);
8698 INSN_ADDRESSES_NEW (insn
, -1);
8700 insn
= emit_barrier_after (insn
);
8701 INSN_ADDRESSES_NEW (insn
, -1);
8703 /* Remove placeholder insn. */
8704 remove_insn (pool
->pool_insn
);
8707 /* Free all memory used by POOL. */
8710 s390_free_pool (struct constant_pool
*pool
)
8712 struct constant
*c
, *next
;
8715 for (i
= 0; i
< NR_C_MODES
; i
++)
8716 for (c
= pool
->constants
[i
]; c
; c
= next
)
8722 for (c
= pool
->execute
; c
; c
= next
)
8728 BITMAP_FREE (pool
->insns
);
8733 /* Collect main literal pool. Return NULL on overflow. */
8735 static struct constant_pool
*
8736 s390_mainpool_start (void)
8738 struct constant_pool
*pool
;
8741 pool
= s390_alloc_pool ();
8743 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8745 if (NONJUMP_INSN_P (insn
)
8746 && GET_CODE (PATTERN (insn
)) == SET
8747 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
8748 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
8750 /* There might be two main_pool instructions if base_reg
8751 is call-clobbered; one for shrink-wrapped code and one
8752 for the rest. We want to keep the first. */
8753 if (pool
->pool_insn
)
8755 insn
= PREV_INSN (insn
);
8756 delete_insn (NEXT_INSN (insn
));
8759 pool
->pool_insn
= insn
;
8762 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8764 rtx pool_ref
= NULL_RTX
;
8765 find_constant_pool_ref (insn
, &pool_ref
);
8768 rtx constant
= get_pool_constant (pool_ref
);
8769 machine_mode mode
= get_pool_mode (pool_ref
);
8770 s390_add_constant (pool
, constant
, mode
);
8774 /* If hot/cold partitioning is enabled we have to make sure that
8775 the literal pool is emitted in the same section where the
8776 initialization of the literal pool base pointer takes place.
8777 emit_pool_after is only used in the non-overflow case on non
8778 Z cpus where we can emit the literal pool at the end of the
8779 function body within the text section. */
8781 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
8782 && !pool
->emit_pool_after
)
8783 pool
->emit_pool_after
= PREV_INSN (insn
);
8786 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
8788 if (pool
->size
>= 4096)
8790 /* We're going to chunkify the pool, so remove the main
8791 pool placeholder insn. */
8792 remove_insn (pool
->pool_insn
);
8794 s390_free_pool (pool
);
8798 /* If the functions ends with the section where the literal pool
8799 should be emitted set the marker to its end. */
8800 if (pool
&& !pool
->emit_pool_after
)
8801 pool
->emit_pool_after
= get_last_insn ();
8806 /* POOL holds the main literal pool as collected by s390_mainpool_start.
8807 Modify the current function to output the pool constants as well as
8808 the pool register setup instruction. */
8811 s390_mainpool_finish (struct constant_pool
*pool
)
8813 rtx base_reg
= cfun
->machine
->base_reg
;
8817 /* If the pool is empty, we're done. */
8818 if (pool
->size
== 0)
8820 /* We don't actually need a base register after all. */
8821 cfun
->machine
->base_reg
= NULL_RTX
;
8823 if (pool
->pool_insn
)
8824 remove_insn (pool
->pool_insn
);
8825 s390_free_pool (pool
);
8829 /* We need correct insn addresses. */
8830 shorten_branches (get_insns ());
8832 /* Use a LARL to load the pool register. The pool is
8833 located in the .rodata section, so we emit it after the function. */
8834 set
= gen_main_base_64 (base_reg
, pool
->label
);
8835 insn
= emit_insn_after (set
, pool
->pool_insn
);
8836 INSN_ADDRESSES_NEW (insn
, -1);
8837 remove_insn (pool
->pool_insn
);
8839 insn
= get_last_insn ();
8840 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
8841 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8843 s390_dump_pool (pool
, 0);
8845 /* Replace all literal pool references. */
8847 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8849 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8851 rtx addr
, pool_ref
= NULL_RTX
;
8852 find_constant_pool_ref (insn
, &pool_ref
);
8855 if (s390_execute_label (insn
))
8856 addr
= s390_find_execute (pool
, insn
);
8858 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
8859 get_pool_mode (pool_ref
));
8861 replace_constant_pool_ref (insn
, pool_ref
, addr
);
8862 INSN_CODE (insn
) = -1;
8868 /* Free the pool. */
8869 s390_free_pool (pool
);
8872 /* Chunkify the literal pool. */
8874 #define S390_POOL_CHUNK_MIN 0xc00
8875 #define S390_POOL_CHUNK_MAX 0xe00
8877 static struct constant_pool
*
8878 s390_chunkify_start (void)
8880 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
8884 /* We need correct insn addresses. */
8886 shorten_branches (get_insns ());
8888 /* Scan all insns and move literals to pool chunks. */
8890 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8892 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8894 rtx pool_ref
= NULL_RTX
;
8895 find_constant_pool_ref (insn
, &pool_ref
);
8898 rtx constant
= get_pool_constant (pool_ref
);
8899 machine_mode mode
= get_pool_mode (pool_ref
);
8902 curr_pool
= s390_start_pool (&pool_list
, insn
);
8904 s390_add_constant (curr_pool
, constant
, mode
);
8905 s390_add_pool_insn (curr_pool
, insn
);
8909 if (JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
) || LABEL_P (insn
))
8912 s390_add_pool_insn (curr_pool
, insn
);
8915 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
8919 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
8920 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
8923 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
8926 s390_end_pool (curr_pool
, NULL
);
8931 s390_end_pool (curr_pool
, NULL
);
8933 /* Find all labels that are branched into
8934 from an insn belonging to a different chunk. */
8936 far_labels
= BITMAP_ALLOC (NULL
);
8938 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8940 rtx_jump_table_data
*table
;
8942 /* Labels marked with LABEL_PRESERVE_P can be target
8943 of non-local jumps, so we have to mark them.
8944 The same holds for named labels.
8946 Don't do that, however, if it is the label before
8950 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
8952 rtx_insn
*vec_insn
= NEXT_INSN (insn
);
8953 if (! vec_insn
|| ! JUMP_TABLE_DATA_P (vec_insn
))
8954 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
8956 /* Check potential targets in a table jump (casesi_jump). */
8957 else if (tablejump_p (insn
, NULL
, &table
))
8959 rtx vec_pat
= PATTERN (table
);
8960 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
8962 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
8964 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
8966 if (s390_find_pool (pool_list
, label
)
8967 != s390_find_pool (pool_list
, insn
))
8968 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
8971 /* If we have a direct jump (conditional or unconditional),
8972 check all potential targets. */
8973 else if (JUMP_P (insn
))
8975 rtx pat
= PATTERN (insn
);
8977 if (GET_CODE (pat
) == PARALLEL
)
8978 pat
= XVECEXP (pat
, 0, 0);
8980 if (GET_CODE (pat
) == SET
)
8982 rtx label
= JUMP_LABEL (insn
);
8983 if (label
&& !ANY_RETURN_P (label
))
8985 if (s390_find_pool (pool_list
, label
)
8986 != s390_find_pool (pool_list
, insn
))
8987 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
8993 /* Insert base register reload insns before every pool. */
8995 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
8997 rtx new_insn
= gen_reload_base_64 (cfun
->machine
->base_reg
,
8999 rtx_insn
*insn
= curr_pool
->first_insn
;
9000 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
9003 /* Insert base register reload insns at every far label. */
9005 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9007 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
9009 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
9012 rtx new_insn
= gen_reload_base_64 (cfun
->machine
->base_reg
,
9014 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
9019 BITMAP_FREE (far_labels
);
9022 /* Recompute insn addresses. */
9024 init_insn_lengths ();
9025 shorten_branches (get_insns ());
9030 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
9031 After we have decided to use this list, finish implementing
9032 all changes to the current function as required. */
9035 s390_chunkify_finish (struct constant_pool
*pool_list
)
9037 struct constant_pool
*curr_pool
= NULL
;
9041 /* Replace all literal pool references. */
9043 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9045 curr_pool
= s390_find_pool (pool_list
, insn
);
9049 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
9051 rtx addr
, pool_ref
= NULL_RTX
;
9052 find_constant_pool_ref (insn
, &pool_ref
);
9055 if (s390_execute_label (insn
))
9056 addr
= s390_find_execute (curr_pool
, insn
);
9058 addr
= s390_find_constant (curr_pool
,
9059 get_pool_constant (pool_ref
),
9060 get_pool_mode (pool_ref
));
9062 replace_constant_pool_ref (insn
, pool_ref
, addr
);
9063 INSN_CODE (insn
) = -1;
9068 /* Dump out all literal pools. */
9070 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
9071 s390_dump_pool (curr_pool
, 0);
9073 /* Free pool list. */
9077 struct constant_pool
*next
= pool_list
->next
;
9078 s390_free_pool (pool_list
);
9083 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
9086 s390_output_pool_entry (rtx exp
, machine_mode mode
, unsigned int align
)
9088 switch (GET_MODE_CLASS (mode
))
9091 case MODE_DECIMAL_FLOAT
:
9092 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
9094 assemble_real (*CONST_DOUBLE_REAL_VALUE (exp
),
9095 as_a
<scalar_float_mode
> (mode
), align
);
9099 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
9100 mark_symbol_refs_as_used (exp
);
9103 case MODE_VECTOR_INT
:
9104 case MODE_VECTOR_FLOAT
:
9107 machine_mode inner_mode
;
9108 gcc_assert (GET_CODE (exp
) == CONST_VECTOR
);
9110 inner_mode
= GET_MODE_INNER (GET_MODE (exp
));
9111 for (i
= 0; i
< XVECLEN (exp
, 0); i
++)
9112 s390_output_pool_entry (XVECEXP (exp
, 0, i
),
9116 : GET_MODE_BITSIZE (inner_mode
));
9126 /* Return an RTL expression representing the value of the return address
9127 for the frame COUNT steps up from the current frame. FRAME is the
9128 frame pointer of that frame. */
9131 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
9136 /* Without backchain, we fail for all but the current frame. */
9138 if (!TARGET_BACKCHAIN
&& count
> 0)
9141 /* For the current frame, we need to make sure the initial
9142 value of RETURN_REGNUM is actually saved. */
9145 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
9147 if (TARGET_PACKED_STACK
)
9148 offset
= -2 * UNITS_PER_LONG
;
9150 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
9152 addr
= plus_constant (Pmode
, frame
, offset
);
9153 addr
= memory_address (Pmode
, addr
);
9154 return gen_rtx_MEM (Pmode
, addr
);
9157 /* Return an RTL expression representing the back chain stored in
9158 the current stack frame. */
9161 s390_back_chain_rtx (void)
9165 gcc_assert (TARGET_BACKCHAIN
);
9167 if (TARGET_PACKED_STACK
)
9168 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
9169 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
9171 chain
= stack_pointer_rtx
;
9173 chain
= gen_rtx_MEM (Pmode
, chain
);
9177 /* Find first call clobbered register unused in a function.
9178 This could be used as base register in a leaf function
9179 or for holding the return address before epilogue. */
9182 find_unused_clobbered_reg (void)
9185 for (i
= 0; i
< 6; i
++)
9186 if (!df_regs_ever_live_p (i
))
9192 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
9193 clobbered hard regs in SETREG. */
9196 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
9198 char *regs_ever_clobbered
= (char *)data
;
9199 unsigned int i
, regno
;
9200 machine_mode mode
= GET_MODE (setreg
);
9202 if (GET_CODE (setreg
) == SUBREG
)
9204 rtx inner
= SUBREG_REG (setreg
);
9205 if (!GENERAL_REG_P (inner
) && !FP_REG_P (inner
))
9207 regno
= subreg_regno (setreg
);
9209 else if (GENERAL_REG_P (setreg
) || FP_REG_P (setreg
))
9210 regno
= REGNO (setreg
);
9215 i
< end_hard_regno (mode
, regno
);
9217 regs_ever_clobbered
[i
] = 1;
9220 /* Walks through all basic blocks of the current function looking
9221 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
9222 of the passed integer array REGS_EVER_CLOBBERED are set to one for
9223 each of those regs. */
9226 s390_regs_ever_clobbered (char regs_ever_clobbered
[])
9232 memset (regs_ever_clobbered
, 0, 32);
9234 /* For non-leaf functions we have to consider all call clobbered regs to be
9238 for (i
= 0; i
< 32; i
++)
9239 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
9242 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
9243 this work is done by liveness analysis (mark_regs_live_at_end).
9244 Special care is needed for functions containing landing pads. Landing pads
9245 may use the eh registers, but the code which sets these registers is not
9246 contained in that function. Hence s390_regs_ever_clobbered is not able to
9247 deal with this automatically. */
9248 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
9249 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9250 if (crtl
->calls_eh_return
9251 || (cfun
->machine
->has_landing_pad_p
9252 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
9253 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
9255 /* For nonlocal gotos all call-saved registers have to be saved.
9256 This flag is also set for the unwinding code in libgcc.
9257 See expand_builtin_unwind_init. For regs_ever_live this is done by
9259 if (crtl
->saves_all_registers
)
9260 for (i
= 0; i
< 32; i
++)
9261 if (!call_really_used_regs
[i
])
9262 regs_ever_clobbered
[i
] = 1;
9264 FOR_EACH_BB_FN (cur_bb
, cfun
)
9266 FOR_BB_INSNS (cur_bb
, cur_insn
)
9270 if (!INSN_P (cur_insn
))
9273 pat
= PATTERN (cur_insn
);
9275 /* Ignore GPR restore insns. */
9276 if (epilogue_completed
&& RTX_FRAME_RELATED_P (cur_insn
))
9278 if (GET_CODE (pat
) == SET
9279 && GENERAL_REG_P (SET_DEST (pat
)))
9282 if (GET_MODE (SET_SRC (pat
)) == DImode
9283 && FP_REG_P (SET_SRC (pat
)))
9287 if (GET_CODE (SET_SRC (pat
)) == MEM
)
9292 if (GET_CODE (pat
) == PARALLEL
9293 && load_multiple_operation (pat
, VOIDmode
))
9298 s390_reg_clobbered_rtx
,
9299 regs_ever_clobbered
);
9304 /* Determine the frame area which actually has to be accessed
9305 in the function epilogue. The values are stored at the
9306 given pointers AREA_BOTTOM (address of the lowest used stack
9307 address) and AREA_TOP (address of the first item which does
9308 not belong to the stack frame). */
9311 s390_frame_area (int *area_bottom
, int *area_top
)
9318 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9320 b
= (cfun_frame_layout
.gprs_offset
9321 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
9322 t
= b
+ (cfun_frame_layout
.last_restore_gpr
9323 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
9326 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
9328 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
9329 t
= MAX (t
, (cfun_frame_layout
.f8_offset
9330 + cfun_frame_layout
.high_fprs
* 8));
9335 if (cfun_fpr_save_p (FPR4_REGNUM
))
9337 b
= MIN (b
, cfun_frame_layout
.f4_offset
);
9338 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 8);
9340 if (cfun_fpr_save_p (FPR6_REGNUM
))
9342 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ 8);
9343 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 16);
9349 /* Update gpr_save_slots in the frame layout trying to make use of
9350 FPRs as GPR save slots.
9351 This is a helper routine of s390_register_info. */
9354 s390_register_info_gprtofpr ()
9356 int save_reg_slot
= FPR0_REGNUM
;
9359 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
9362 /* builtin_eh_return needs to be able to modify the return address
9363 on the stack. It could also adjust the FPR save slot instead but
9364 is it worth the trouble?! */
9365 if (crtl
->calls_eh_return
)
9368 for (i
= 15; i
>= 6; i
--)
9370 if (cfun_gpr_save_slot (i
) == SAVE_SLOT_NONE
)
9373 /* Advance to the next FP register which can be used as a
9375 while ((!call_really_used_regs
[save_reg_slot
]
9376 || df_regs_ever_live_p (save_reg_slot
)
9377 || cfun_fpr_save_p (save_reg_slot
))
9378 && FP_REGNO_P (save_reg_slot
))
9380 if (!FP_REGNO_P (save_reg_slot
))
9382 /* We only want to use ldgr/lgdr if we can get rid of
9383 stm/lm entirely. So undo the gpr slot allocation in
9384 case we ran out of FPR save slots. */
9385 for (j
= 6; j
<= 15; j
++)
9386 if (FP_REGNO_P (cfun_gpr_save_slot (j
)))
9387 cfun_gpr_save_slot (j
) = SAVE_SLOT_STACK
;
9390 cfun_gpr_save_slot (i
) = save_reg_slot
++;
9394 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
9396 This is a helper routine for s390_register_info. */
9399 s390_register_info_stdarg_fpr ()
9405 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
9406 f0-f4 for 64 bit. */
9408 || !TARGET_HARD_FLOAT
9409 || !cfun
->va_list_fpr_size
9410 || crtl
->args
.info
.fprs
>= FP_ARG_NUM_REG
)
9413 min_fpr
= crtl
->args
.info
.fprs
;
9414 max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
- 1;
9415 if (max_fpr
>= FP_ARG_NUM_REG
)
9416 max_fpr
= FP_ARG_NUM_REG
- 1;
9418 /* FPR argument regs start at f0. */
9419 min_fpr
+= FPR0_REGNUM
;
9420 max_fpr
+= FPR0_REGNUM
;
9422 for (i
= min_fpr
; i
<= max_fpr
; i
++)
9423 cfun_set_fpr_save (i
);
9426 /* Reserve the GPR save slots for GPRs which need to be saved due to
9428 This is a helper routine for s390_register_info. */
9431 s390_register_info_stdarg_gpr ()
9438 || !cfun
->va_list_gpr_size
9439 || crtl
->args
.info
.gprs
>= GP_ARG_NUM_REG
)
9442 min_gpr
= crtl
->args
.info
.gprs
;
9443 max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
- 1;
9444 if (max_gpr
>= GP_ARG_NUM_REG
)
9445 max_gpr
= GP_ARG_NUM_REG
- 1;
9447 /* GPR argument regs start at r2. */
9448 min_gpr
+= GPR2_REGNUM
;
9449 max_gpr
+= GPR2_REGNUM
;
9451 /* If r6 was supposed to be saved into an FPR and now needs to go to
9452 the stack for vararg we have to adjust the restore range to make
9453 sure that the restore is done from stack as well. */
9454 if (FP_REGNO_P (cfun_gpr_save_slot (GPR6_REGNUM
))
9455 && min_gpr
<= GPR6_REGNUM
9456 && max_gpr
>= GPR6_REGNUM
)
9458 if (cfun_frame_layout
.first_restore_gpr
== -1
9459 || cfun_frame_layout
.first_restore_gpr
> GPR6_REGNUM
)
9460 cfun_frame_layout
.first_restore_gpr
= GPR6_REGNUM
;
9461 if (cfun_frame_layout
.last_restore_gpr
== -1
9462 || cfun_frame_layout
.last_restore_gpr
< GPR6_REGNUM
)
9463 cfun_frame_layout
.last_restore_gpr
= GPR6_REGNUM
;
9466 if (cfun_frame_layout
.first_save_gpr
== -1
9467 || cfun_frame_layout
.first_save_gpr
> min_gpr
)
9468 cfun_frame_layout
.first_save_gpr
= min_gpr
;
9470 if (cfun_frame_layout
.last_save_gpr
== -1
9471 || cfun_frame_layout
.last_save_gpr
< max_gpr
)
9472 cfun_frame_layout
.last_save_gpr
= max_gpr
;
9474 for (i
= min_gpr
; i
<= max_gpr
; i
++)
9475 cfun_gpr_save_slot (i
) = SAVE_SLOT_STACK
;
9478 /* Calculate the save and restore ranges for stm(g) and lm(g) in the
9479 prologue and epilogue. */
9482 s390_register_info_set_ranges ()
9486 /* Find the first and the last save slot supposed to use the stack
9487 to set the restore range.
9488 Vararg regs might be marked as save to stack but only the
9489 call-saved regs really need restoring (i.e. r6). This code
9490 assumes that the vararg regs have not yet been recorded in
9491 cfun_gpr_save_slot. */
9492 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != SAVE_SLOT_STACK
; i
++);
9493 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != SAVE_SLOT_STACK
; j
--);
9494 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
9495 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
9496 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
9497 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
9500 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
9501 for registers which need to be saved in function prologue.
9502 This function can be used until the insns emitted for save/restore
9503 of the regs are visible in the RTL stream. */
9506 s390_register_info ()
9509 char clobbered_regs
[32];
9511 gcc_assert (!epilogue_completed
);
9513 if (reload_completed
)
9514 /* After reload we rely on our own routine to determine which
9515 registers need saving. */
9516 s390_regs_ever_clobbered (clobbered_regs
);
9518 /* During reload we use regs_ever_live as a base since reload
9519 does changes in there which we otherwise would not be aware
9521 for (i
= 0; i
< 32; i
++)
9522 clobbered_regs
[i
] = df_regs_ever_live_p (i
);
9524 for (i
= 0; i
< 32; i
++)
9525 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
9527 /* Mark the call-saved FPRs which need to be saved.
9528 This needs to be done before checking the special GPRs since the
9529 stack pointer usage depends on whether high FPRs have to be saved
9531 cfun_frame_layout
.fpr_bitmap
= 0;
9532 cfun_frame_layout
.high_fprs
= 0;
9533 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
9534 if (clobbered_regs
[i
] && !call_really_used_regs
[i
])
9536 cfun_set_fpr_save (i
);
9537 if (i
>= FPR8_REGNUM
)
9538 cfun_frame_layout
.high_fprs
++;
9541 /* Register 12 is used for GOT address, but also as temp in prologue
9542 for split-stack stdarg functions (unless r14 is available). */
9544 |= ((flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
9545 || (flag_split_stack
&& cfun
->stdarg
9546 && (crtl
->is_leaf
|| TARGET_TPF_PROFILING
9547 || has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
))));
9549 clobbered_regs
[BASE_REGNUM
]
9550 |= (cfun
->machine
->base_reg
9551 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
9553 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
]
9554 |= !!frame_pointer_needed
;
9556 /* On pre z900 machines this might take until machine dependent
9558 save_return_addr_p will only be set on non-zarch machines so
9559 there is no risk that r14 goes into an FPR instead of a stack
9561 clobbered_regs
[RETURN_REGNUM
]
9563 || TARGET_TPF_PROFILING
9564 || cfun_frame_layout
.save_return_addr_p
9565 || crtl
->calls_eh_return
);
9567 clobbered_regs
[STACK_POINTER_REGNUM
]
9569 || TARGET_TPF_PROFILING
9570 || cfun_save_high_fprs_p
9571 || get_frame_size () > 0
9572 || (reload_completed
&& cfun_frame_layout
.frame_size
> 0)
9573 || cfun
->calls_alloca
);
9575 memset (cfun_frame_layout
.gpr_save_slots
, SAVE_SLOT_NONE
, 16);
9577 for (i
= 6; i
< 16; i
++)
9578 if (clobbered_regs
[i
])
9579 cfun_gpr_save_slot (i
) = SAVE_SLOT_STACK
;
9581 s390_register_info_stdarg_fpr ();
9582 s390_register_info_gprtofpr ();
9583 s390_register_info_set_ranges ();
9584 /* stdarg functions might need to save GPRs 2 to 6. This might
9585 override the GPR->FPR save decision made by
9586 s390_register_info_gprtofpr for r6 since vararg regs must go to
9588 s390_register_info_stdarg_gpr ();
9591 /* Return true if REGNO is a global register, but not one
9592 of the special ones that need to be saved/restored in anyway. */
9595 global_not_special_regno_p (int regno
)
9597 return (global_regs
[regno
]
9598 /* These registers are special and need to be
9599 restored in any case. */
9600 && !(regno
== STACK_POINTER_REGNUM
9601 || regno
== RETURN_REGNUM
9602 || regno
== BASE_REGNUM
9603 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
9606 /* This function is called by s390_optimize_prologue in order to get
9607 rid of unnecessary GPR save/restore instructions. The register info
9608 for the GPRs is re-computed and the ranges are re-calculated. */
9611 s390_optimize_register_info ()
9613 char clobbered_regs
[32];
9616 gcc_assert (epilogue_completed
);
9618 s390_regs_ever_clobbered (clobbered_regs
);
9620 /* Global registers do not need to be saved and restored unless it
9621 is one of our special regs. (r12, r13, r14, or r15). */
9622 for (i
= 0; i
< 32; i
++)
9623 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_not_special_regno_p (i
);
9625 /* There is still special treatment needed for cases invisible to
9626 s390_regs_ever_clobbered. */
9627 clobbered_regs
[RETURN_REGNUM
]
9628 |= (TARGET_TPF_PROFILING
9629 /* When expanding builtin_return_addr in ESA mode we do not
9630 know whether r14 will later be needed as scratch reg when
9631 doing branch splitting. So the builtin always accesses the
9632 r14 save slot and we need to stick to the save/restore
9633 decision for r14 even if it turns out that it didn't get
9635 || cfun_frame_layout
.save_return_addr_p
9636 || crtl
->calls_eh_return
);
9638 memset (cfun_frame_layout
.gpr_save_slots
, SAVE_SLOT_NONE
, 6);
9640 for (i
= 6; i
< 16; i
++)
9641 if (!clobbered_regs
[i
])
9642 cfun_gpr_save_slot (i
) = SAVE_SLOT_NONE
;
9644 s390_register_info_set_ranges ();
9645 s390_register_info_stdarg_gpr ();
9648 /* Fill cfun->machine with info about frame of current function. */
9651 s390_frame_info (void)
9653 HOST_WIDE_INT lowest_offset
;
9655 cfun_frame_layout
.first_save_gpr_slot
= cfun_frame_layout
.first_save_gpr
;
9656 cfun_frame_layout
.last_save_gpr_slot
= cfun_frame_layout
.last_save_gpr
;
9658 /* The va_arg builtin uses a constant distance of 16 *
9659 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
9660 pointer. So even if we are going to save the stack pointer in an
9661 FPR we need the stack space in order to keep the offsets
9663 if (cfun
->stdarg
&& cfun_save_arg_fprs_p
)
9665 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
9667 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
9668 cfun_frame_layout
.first_save_gpr_slot
= STACK_POINTER_REGNUM
;
9671 cfun_frame_layout
.frame_size
= get_frame_size ();
9672 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
9673 fatal_error (input_location
,
9674 "total size of local variables exceeds architecture limit");
9676 if (!TARGET_PACKED_STACK
)
9678 /* Fixed stack layout. */
9679 cfun_frame_layout
.backchain_offset
= 0;
9680 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
9681 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
9682 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
9683 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
9686 else if (TARGET_BACKCHAIN
)
9688 /* Kernel stack layout - packed stack, backchain, no float */
9689 gcc_assert (TARGET_SOFT_FLOAT
);
9690 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
9693 /* The distance between the backchain and the return address
9694 save slot must not change. So we always need a slot for the
9695 stack pointer which resides in between. */
9696 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
9698 cfun_frame_layout
.gprs_offset
9699 = cfun_frame_layout
.backchain_offset
- cfun_gprs_save_area_size
;
9701 /* FPRs will not be saved. Nevertheless pick sane values to
9702 keep area calculations valid. */
9703 cfun_frame_layout
.f0_offset
=
9704 cfun_frame_layout
.f4_offset
=
9705 cfun_frame_layout
.f8_offset
= cfun_frame_layout
.gprs_offset
;
9711 /* Packed stack layout without backchain. */
9713 /* With stdarg FPRs need their dedicated slots. */
9714 num_fprs
= (TARGET_64BIT
&& cfun
->stdarg
? 2
9715 : (cfun_fpr_save_p (FPR4_REGNUM
) +
9716 cfun_fpr_save_p (FPR6_REGNUM
)));
9717 cfun_frame_layout
.f4_offset
= STACK_POINTER_OFFSET
- 8 * num_fprs
;
9719 num_fprs
= (cfun
->stdarg
? 2
9720 : (cfun_fpr_save_p (FPR0_REGNUM
)
9721 + cfun_fpr_save_p (FPR2_REGNUM
)));
9722 cfun_frame_layout
.f0_offset
= cfun_frame_layout
.f4_offset
- 8 * num_fprs
;
9724 cfun_frame_layout
.gprs_offset
9725 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
9727 cfun_frame_layout
.f8_offset
= (cfun_frame_layout
.gprs_offset
9728 - cfun_frame_layout
.high_fprs
* 8);
9731 if (cfun_save_high_fprs_p
)
9732 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
9735 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
9737 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
9738 sized area at the bottom of the stack. This is required also for
9739 leaf functions. When GCC generates a local stack reference it
9740 will always add STACK_POINTER_OFFSET to all these references. */
9742 && !TARGET_TPF_PROFILING
9743 && cfun_frame_layout
.frame_size
== 0
9744 && !cfun
->calls_alloca
)
9747 /* Calculate the number of bytes we have used in our own register
9748 save area. With the packed stack layout we can re-use the
9749 remaining bytes for normal stack elements. */
9751 if (TARGET_PACKED_STACK
)
9752 lowest_offset
= MIN (MIN (cfun_frame_layout
.f0_offset
,
9753 cfun_frame_layout
.f4_offset
),
9754 cfun_frame_layout
.gprs_offset
);
9758 if (TARGET_BACKCHAIN
)
9759 lowest_offset
= MIN (lowest_offset
, cfun_frame_layout
.backchain_offset
);
9761 cfun_frame_layout
.frame_size
+= STACK_POINTER_OFFSET
- lowest_offset
;
9763 /* If under 31 bit an odd number of gprs has to be saved we have to
9764 adjust the frame size to sustain 8 byte alignment of stack
9766 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
9767 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
9768 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
9771 /* Generate frame layout. Fills in register and frame data for the current
9772 function in cfun->machine. This routine can be called multiple times;
9773 it will re-do the complete frame layout every time. */
9776 s390_init_frame_layout (void)
9778 HOST_WIDE_INT frame_size
;
9781 /* After LRA the frame layout is supposed to be read-only and should
9782 not be re-computed. */
9783 if (reload_completed
)
9788 frame_size
= cfun_frame_layout
.frame_size
;
9790 /* Try to predict whether we'll need the base register. */
9791 base_used
= crtl
->uses_const_pool
9792 || (!DISP_IN_RANGE (frame_size
)
9793 && !CONST_OK_FOR_K (frame_size
));
9795 /* Decide which register to use as literal pool base. In small
9796 leaf functions, try to use an unused call-clobbered register
9797 as base register to avoid save/restore overhead. */
9799 cfun
->machine
->base_reg
= NULL_RTX
;
9805 /* Prefer r5 (most likely to be free). */
9806 for (br
= 5; br
>= 2 && df_regs_ever_live_p (br
); br
--)
9808 cfun
->machine
->base_reg
=
9809 gen_rtx_REG (Pmode
, (br
>= 2) ? br
: BASE_REGNUM
);
9812 s390_register_info ();
9815 while (frame_size
!= cfun_frame_layout
.frame_size
);
9818 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
9819 the TX is nonescaping. A transaction is considered escaping if
9820 there is at least one path from tbegin returning CC0 to the
9821 function exit block without an tend.
9823 The check so far has some limitations:
9824 - only single tbegin/tend BBs are supported
9825 - the first cond jump after tbegin must separate the CC0 path from ~CC0
9826 - when CC is copied to a GPR and the CC0 check is done with the GPR
9827 this is not supported
9831 s390_optimize_nonescaping_tx (void)
9833 const unsigned int CC0
= 1 << 3;
9834 basic_block tbegin_bb
= NULL
;
9835 basic_block tend_bb
= NULL
;
9840 rtx_insn
*tbegin_insn
= NULL
;
9842 if (!cfun
->machine
->tbegin_p
)
9845 for (bb_index
= 0; bb_index
< n_basic_blocks_for_fn (cfun
); bb_index
++)
9847 bb
= BASIC_BLOCK_FOR_FN (cfun
, bb_index
);
9852 FOR_BB_INSNS (bb
, insn
)
9854 rtx ite
, cc
, pat
, target
;
9855 unsigned HOST_WIDE_INT mask
;
9857 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
9860 pat
= PATTERN (insn
);
9862 if (GET_CODE (pat
) == PARALLEL
)
9863 pat
= XVECEXP (pat
, 0, 0);
9865 if (GET_CODE (pat
) != SET
9866 || GET_CODE (SET_SRC (pat
)) != UNSPEC_VOLATILE
)
9869 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TBEGIN
)
9875 /* Just return if the tbegin doesn't have clobbers. */
9876 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
9879 if (tbegin_bb
!= NULL
)
9882 /* Find the next conditional jump. */
9883 for (tmp
= NEXT_INSN (insn
);
9885 tmp
= NEXT_INSN (tmp
))
9887 if (reg_set_p (gen_rtx_REG (CCmode
, CC_REGNUM
), tmp
))
9892 ite
= SET_SRC (PATTERN (tmp
));
9893 if (GET_CODE (ite
) != IF_THEN_ELSE
)
9896 cc
= XEXP (XEXP (ite
, 0), 0);
9897 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
))
9898 || GET_MODE (cc
) != CCRAWmode
9899 || GET_CODE (XEXP (XEXP (ite
, 0), 1)) != CONST_INT
)
9902 if (bb
->succs
->length () != 2)
9905 mask
= INTVAL (XEXP (XEXP (ite
, 0), 1));
9906 if (GET_CODE (XEXP (ite
, 0)) == NE
)
9910 target
= XEXP (ite
, 1);
9911 else if (mask
== (CC0
^ 0xf))
9912 target
= XEXP (ite
, 2);
9920 ei
= ei_start (bb
->succs
);
9921 e1
= ei_safe_edge (ei
);
9923 e2
= ei_safe_edge (ei
);
9925 if (e2
->flags
& EDGE_FALLTHRU
)
9928 e1
= ei_safe_edge (ei
);
9931 if (!(e1
->flags
& EDGE_FALLTHRU
))
9934 tbegin_bb
= (target
== pc_rtx
) ? e1
->dest
: e2
->dest
;
9936 if (tmp
== BB_END (bb
))
9941 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TEND
)
9943 if (tend_bb
!= NULL
)
9950 /* Either we successfully remove the FPR clobbers here or we are not
9951 able to do anything for this TX. Both cases don't qualify for
9953 cfun
->machine
->tbegin_p
= false;
9955 if (tbegin_bb
== NULL
|| tend_bb
== NULL
)
9958 calculate_dominance_info (CDI_POST_DOMINATORS
);
9959 result
= dominated_by_p (CDI_POST_DOMINATORS
, tbegin_bb
, tend_bb
);
9960 free_dominance_info (CDI_POST_DOMINATORS
);
9965 PATTERN (tbegin_insn
) = gen_rtx_PARALLEL (VOIDmode
,
9967 XVECEXP (PATTERN (tbegin_insn
), 0, 0),
9968 XVECEXP (PATTERN (tbegin_insn
), 0, 1)));
9969 INSN_CODE (tbegin_insn
) = -1;
9970 df_insn_rescan (tbegin_insn
);
9975 /* Implement TARGET_HARD_REGNO_NREGS. Because all registers in a class
9976 have the same size, this is equivalent to CLASS_MAX_NREGS. */
9979 s390_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
9981 return s390_class_max_nregs (REGNO_REG_CLASS (regno
), mode
);
9984 /* Implement TARGET_HARD_REGNO_MODE_OK.
9986 Integer modes <= word size fit into any GPR.
9987 Integer modes > word size fit into successive GPRs, starting with
9988 an even-numbered register.
9989 SImode and DImode fit into FPRs as well.
9991 Floating point modes <= word size fit into any FPR or GPR.
9992 Floating point modes > word size (i.e. DFmode on 32-bit) fit
9993 into any FPR, or an even-odd GPR pair.
9994 TFmode fits only into an even-odd FPR pair.
9996 Complex floating point modes fit either into two FPRs, or into
9997 successive GPRs (again starting with an even number).
9998 TCmode fits only into two successive even-odd FPR pairs.
10000 Condition code modes fit only into the CC register. */
10003 s390_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
10005 if (!TARGET_VX
&& VECTOR_NOFP_REGNO_P (regno
))
10008 switch (REGNO_REG_CLASS (regno
))
10011 return ((GET_MODE_CLASS (mode
) == MODE_INT
10012 && s390_class_max_nregs (VEC_REGS
, mode
) == 1)
10014 || (TARGET_VXE
&& mode
== SFmode
)
10015 || s390_vector_mode_supported_p (mode
));
10019 && ((GET_MODE_CLASS (mode
) == MODE_INT
10020 && s390_class_max_nregs (FP_REGS
, mode
) == 1)
10022 || s390_vector_mode_supported_p (mode
)))
10025 if (REGNO_PAIR_OK (regno
, mode
))
10027 if (mode
== SImode
|| mode
== DImode
)
10030 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
10035 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
10040 if (REGNO_PAIR_OK (regno
, mode
))
10043 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
10048 if (GET_MODE_CLASS (mode
) == MODE_CC
)
10052 if (REGNO_PAIR_OK (regno
, mode
))
10054 if (mode
== SImode
|| mode
== Pmode
)
10065 /* Implement TARGET_MODES_TIEABLE_P. */
10068 s390_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
10070 return ((mode1
== SFmode
|| mode1
== DFmode
)
10071 == (mode2
== SFmode
|| mode2
== DFmode
));
10074 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
10077 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
10079 /* Once we've decided upon a register to use as base register, it must
10080 no longer be used for any other purpose. */
10081 if (cfun
->machine
->base_reg
)
10082 if (REGNO (cfun
->machine
->base_reg
) == old_reg
10083 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
10086 /* Prevent regrename from using call-saved regs which haven't
10087 actually been saved. This is necessary since regrename assumes
10088 the backend save/restore decisions are based on
10089 df_regs_ever_live. Since we have our own routine we have to tell
10090 regrename manually about it. */
10091 if (GENERAL_REGNO_P (new_reg
)
10092 && !call_really_used_regs
[new_reg
]
10093 && cfun_gpr_save_slot (new_reg
) == SAVE_SLOT_NONE
)
10099 /* Return nonzero if register REGNO can be used as a scratch register
10103 s390_hard_regno_scratch_ok (unsigned int regno
)
10105 /* See s390_hard_regno_rename_ok. */
10106 if (GENERAL_REGNO_P (regno
)
10107 && !call_really_used_regs
[regno
]
10108 && cfun_gpr_save_slot (regno
) == SAVE_SLOT_NONE
)
10114 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. When generating
10115 code that runs in z/Architecture mode, but conforms to the 31-bit
10116 ABI, GPRs can hold 8 bytes; the ABI guarantees only that the lower 4
10117 bytes are saved across calls, however. */
10120 s390_hard_regno_call_part_clobbered (rtx_insn
*insn ATTRIBUTE_UNUSED
,
10121 unsigned int regno
, machine_mode mode
)
10125 && GET_MODE_SIZE (mode
) > 4
10126 && ((regno
>= 6 && regno
<= 15) || regno
== 32))
10130 && GET_MODE_SIZE (mode
) > 8
10131 && (((TARGET_64BIT
&& regno
>= 24 && regno
<= 31))
10132 || (!TARGET_64BIT
&& (regno
== 18 || regno
== 19))))
10138 /* Maximum number of registers to represent a value of mode MODE
10139 in a register of class RCLASS. */
10142 s390_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
10145 bool reg_pair_required_p
= false;
10151 reg_size
= TARGET_VX
? 16 : 8;
10153 /* TF and TD modes would fit into a VR but we put them into a
10154 register pair since we do not have 128bit FP instructions on
10157 && SCALAR_FLOAT_MODE_P (mode
)
10158 && GET_MODE_SIZE (mode
) >= 16)
10159 reg_pair_required_p
= true;
10161 /* Even if complex types would fit into a single FPR/VR we force
10162 them into a register pair to deal with the parts more easily.
10163 (FIXME: What about complex ints?) */
10164 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
10165 reg_pair_required_p
= true;
10171 reg_size
= UNITS_PER_WORD
;
10175 if (reg_pair_required_p
)
10176 return 2 * ((GET_MODE_SIZE (mode
) / 2 + reg_size
- 1) / reg_size
);
10178 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
10181 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
10184 s390_can_change_mode_class (machine_mode from_mode
,
10185 machine_mode to_mode
,
10186 reg_class_t rclass
)
10188 machine_mode small_mode
;
10189 machine_mode big_mode
;
10191 /* V1TF and TF have different representations in vector
10193 if (reg_classes_intersect_p (VEC_REGS
, rclass
)
10194 && ((from_mode
== V1TFmode
&& to_mode
== TFmode
)
10195 || (from_mode
== TFmode
&& to_mode
== V1TFmode
)))
10198 if (GET_MODE_SIZE (from_mode
) == GET_MODE_SIZE (to_mode
))
10201 if (GET_MODE_SIZE (from_mode
) < GET_MODE_SIZE (to_mode
))
10203 small_mode
= from_mode
;
10204 big_mode
= to_mode
;
10208 small_mode
= to_mode
;
10209 big_mode
= from_mode
;
10212 /* Values residing in VRs are little-endian style. All modes are
10213 placed left-aligned in an VR. This means that we cannot allow
10214 switching between modes with differing sizes. Also if the vector
10215 facility is available we still place TFmode values in VR register
10216 pairs, since the only instructions we have operating on TFmodes
10217 only deal with register pairs. Therefore we have to allow DFmode
10218 subregs of TFmodes to enable the TFmode splitters. */
10219 if (reg_classes_intersect_p (VEC_REGS
, rclass
)
10220 && (GET_MODE_SIZE (small_mode
) < 8
10221 || s390_class_max_nregs (VEC_REGS
, big_mode
) == 1))
10224 /* Likewise for access registers, since they have only half the
10225 word size on 64-bit. */
10226 if (reg_classes_intersect_p (ACCESS_REGS
, rclass
))
10232 /* Return true if we use LRA instead of reload pass. */
10236 return s390_lra_flag
;
10239 /* Return true if register FROM can be eliminated via register TO. */
10242 s390_can_eliminate (const int from
, const int to
)
10244 /* We have not marked the base register as fixed.
10245 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
10246 If a function requires the base register, we say here that this
10247 elimination cannot be performed. This will cause reload to free
10248 up the base register (as if it were fixed). On the other hand,
10249 if the current function does *not* require the base register, we
10250 say here the elimination succeeds, which in turn allows reload
10251 to allocate the base register for any other purpose. */
10252 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
10254 s390_init_frame_layout ();
10255 return cfun
->machine
->base_reg
== NULL_RTX
;
10258 /* Everything else must point into the stack frame. */
10259 gcc_assert (to
== STACK_POINTER_REGNUM
10260 || to
== HARD_FRAME_POINTER_REGNUM
);
10262 gcc_assert (from
== FRAME_POINTER_REGNUM
10263 || from
== ARG_POINTER_REGNUM
10264 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
10266 /* Make sure we actually saved the return address. */
10267 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
10268 if (!crtl
->calls_eh_return
10270 && !cfun_frame_layout
.save_return_addr_p
)
10276 /* Return offset between register FROM and TO initially after prolog. */
10279 s390_initial_elimination_offset (int from
, int to
)
10281 HOST_WIDE_INT offset
;
10283 /* ??? Why are we called for non-eliminable pairs? */
10284 if (!s390_can_eliminate (from
, to
))
10289 case FRAME_POINTER_REGNUM
:
10290 offset
= (get_frame_size()
10291 + STACK_POINTER_OFFSET
10292 + crtl
->outgoing_args_size
);
10295 case ARG_POINTER_REGNUM
:
10296 s390_init_frame_layout ();
10297 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
10300 case RETURN_ADDRESS_POINTER_REGNUM
:
10301 s390_init_frame_layout ();
10303 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
10305 /* If it turns out that for stdarg nothing went into the reg
10306 save area we also do not need the return address
10308 if (cfun
->stdarg
&& !cfun_save_arg_fprs_p
)
10311 gcc_unreachable ();
10314 /* In order to make the following work it is not necessary for
10315 r14 to have a save slot. It is sufficient if one other GPR
10316 got one. Since the GPRs are always stored without gaps we
10317 are able to calculate where the r14 save slot would
10319 offset
= (cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
+
10320 (RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
) *
10329 gcc_unreachable ();
10335 /* Emit insn to save fpr REGNUM at offset OFFSET relative
10336 to register BASE. Return generated insn. */
10339 save_fpr (rtx base
, int offset
, int regnum
)
10342 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
10344 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
10345 set_mem_alias_set (addr
, get_varargs_alias_set ());
10347 set_mem_alias_set (addr
, get_frame_alias_set ());
10349 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
10352 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
10353 to register BASE. Return generated insn. */
10356 restore_fpr (rtx base
, int offset
, int regnum
)
10359 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
10360 set_mem_alias_set (addr
, get_frame_alias_set ());
10362 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
10365 /* Generate insn to save registers FIRST to LAST into
10366 the register save area located at offset OFFSET
10367 relative to register BASE. */
10370 save_gprs (rtx base
, int offset
, int first
, int last
)
10372 rtx addr
, insn
, note
;
10375 addr
= plus_constant (Pmode
, base
, offset
);
10376 addr
= gen_rtx_MEM (Pmode
, addr
);
10378 set_mem_alias_set (addr
, get_frame_alias_set ());
10380 /* Special-case single register. */
10384 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
10386 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
10388 if (!global_not_special_regno_p (first
))
10389 RTX_FRAME_RELATED_P (insn
) = 1;
10394 insn
= gen_store_multiple (addr
,
10395 gen_rtx_REG (Pmode
, first
),
10396 GEN_INT (last
- first
+ 1));
10398 if (first
<= 6 && cfun
->stdarg
)
10399 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
10401 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
10403 if (first
+ i
<= 6)
10404 set_mem_alias_set (mem
, get_varargs_alias_set ());
10407 /* We need to set the FRAME_RELATED flag on all SETs
10408 inside the store-multiple pattern.
10410 However, we must not emit DWARF records for registers 2..5
10411 if they are stored for use by variable arguments ...
10413 ??? Unfortunately, it is not enough to simply not the
10414 FRAME_RELATED flags for those SETs, because the first SET
10415 of the PARALLEL is always treated as if it had the flag
10416 set, even if it does not. Therefore we emit a new pattern
10417 without those registers as REG_FRAME_RELATED_EXPR note. */
10419 if (first
>= 6 && !global_not_special_regno_p (first
))
10421 rtx pat
= PATTERN (insn
);
10423 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10424 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
10425 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
10427 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
10429 RTX_FRAME_RELATED_P (insn
) = 1;
10431 else if (last
>= 6)
10435 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
10436 if (!global_not_special_regno_p (start
))
10442 addr
= plus_constant (Pmode
, base
,
10443 offset
+ (start
- first
) * UNITS_PER_LONG
);
10448 note
= gen_movdi (gen_rtx_MEM (Pmode
, addr
),
10449 gen_rtx_REG (Pmode
, start
));
10451 note
= gen_movsi (gen_rtx_MEM (Pmode
, addr
),
10452 gen_rtx_REG (Pmode
, start
));
10453 note
= PATTERN (note
);
10455 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
10456 RTX_FRAME_RELATED_P (insn
) = 1;
10461 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
10462 gen_rtx_REG (Pmode
, start
),
10463 GEN_INT (last
- start
+ 1));
10464 note
= PATTERN (note
);
10466 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
10468 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
10469 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
10470 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
10472 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
10474 RTX_FRAME_RELATED_P (insn
) = 1;
10480 /* Generate insn to restore registers FIRST to LAST from
10481 the register save area located at offset OFFSET
10482 relative to register BASE. */
10485 restore_gprs (rtx base
, int offset
, int first
, int last
)
10489 addr
= plus_constant (Pmode
, base
, offset
);
10490 addr
= gen_rtx_MEM (Pmode
, addr
);
10491 set_mem_alias_set (addr
, get_frame_alias_set ());
10493 /* Special-case single register. */
10497 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
10499 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
10501 RTX_FRAME_RELATED_P (insn
) = 1;
10505 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
10507 GEN_INT (last
- first
+ 1));
10508 RTX_FRAME_RELATED_P (insn
) = 1;
10512 /* Return insn sequence to load the GOT register. */
10515 s390_load_got (void)
10519 /* We cannot use pic_offset_table_rtx here since we use this
10520 function also for non-pic if __tls_get_offset is called and in
10521 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
10523 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
10527 emit_move_insn (got_rtx
, s390_got_symbol ());
10529 insns
= get_insns ();
10534 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
10535 and the change to the stack pointer. */
10538 s390_emit_stack_tie (void)
10540 rtx mem
= gen_frame_mem (BLKmode
,
10541 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
10543 emit_insn (gen_stack_tie (mem
));
10546 /* Copy GPRS into FPR save slots. */
10549 s390_save_gprs_to_fprs (void)
10553 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
10556 for (i
= 6; i
< 16; i
++)
10558 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
10561 emit_move_insn (gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)),
10562 gen_rtx_REG (DImode
, i
));
10563 RTX_FRAME_RELATED_P (insn
) = 1;
10564 /* This prevents dwarf2cfi from interpreting the set. Doing
10565 so it might emit def_cfa_register infos setting an FPR as
10567 add_reg_note (insn
, REG_CFA_REGISTER
, copy_rtx (PATTERN (insn
)));
10572 /* Restore GPRs from FPR save slots. */
10575 s390_restore_gprs_from_fprs (void)
10579 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
10582 for (i
= 6; i
< 16; i
++)
10586 if (!FP_REGNO_P (cfun_gpr_save_slot (i
)))
10589 rtx fpr
= gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
));
10591 if (i
== STACK_POINTER_REGNUM
)
10592 insn
= emit_insn (gen_stack_restore_from_fpr (fpr
));
10594 insn
= emit_move_insn (gen_rtx_REG (DImode
, i
), fpr
);
10596 df_set_regs_ever_live (i
, true);
10597 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (DImode
, i
));
10598 if (i
== STACK_POINTER_REGNUM
)
10599 add_reg_note (insn
, REG_CFA_DEF_CFA
,
10600 plus_constant (Pmode
, stack_pointer_rtx
,
10601 STACK_POINTER_OFFSET
));
10602 RTX_FRAME_RELATED_P (insn
) = 1;
10607 /* A pass run immediately before shrink-wrapping and prologue and epilogue
10612 const pass_data pass_data_s390_early_mach
=
10614 RTL_PASS
, /* type */
10615 "early_mach", /* name */
10616 OPTGROUP_NONE
, /* optinfo_flags */
10617 TV_MACH_DEP
, /* tv_id */
10618 0, /* properties_required */
10619 0, /* properties_provided */
10620 0, /* properties_destroyed */
10621 0, /* todo_flags_start */
10622 ( TODO_df_verify
| TODO_df_finish
), /* todo_flags_finish */
10625 class pass_s390_early_mach
: public rtl_opt_pass
10628 pass_s390_early_mach (gcc::context
*ctxt
)
10629 : rtl_opt_pass (pass_data_s390_early_mach
, ctxt
)
10632 /* opt_pass methods: */
10633 virtual unsigned int execute (function
*);
10635 }; // class pass_s390_early_mach
10638 pass_s390_early_mach::execute (function
*fun
)
10642 /* Try to get rid of the FPR clobbers. */
10643 s390_optimize_nonescaping_tx ();
10645 /* Re-compute register info. */
10646 s390_register_info ();
10648 /* If we're using a base register, ensure that it is always valid for
10649 the first non-prologue instruction. */
10650 if (fun
->machine
->base_reg
)
10651 emit_insn_at_entry (gen_main_pool (fun
->machine
->base_reg
));
10653 /* Annotate all constant pool references to let the scheduler know
10654 they implicitly use the base register. */
10655 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10658 annotate_constant_pool_refs (insn
);
10659 df_insn_rescan (insn
);
10664 } // anon namespace
10667 make_pass_s390_early_mach (gcc::context
*ctxt
)
10669 return new pass_s390_early_mach (ctxt
);
10672 /* Calculate TARGET = REG + OFFSET as s390_emit_prologue would do it.
10673 - push too big immediates to the literal pool and annotate the refs
10674 - emit frame related notes for stack pointer changes. */
10677 s390_prologue_plus_offset (rtx target
, rtx reg
, rtx offset
, bool frame_related_p
)
10680 rtx orig_offset
= offset
;
10682 gcc_assert (REG_P (target
));
10683 gcc_assert (REG_P (reg
));
10684 gcc_assert (CONST_INT_P (offset
));
10686 if (offset
== const0_rtx
) /* lr/lgr */
10688 insn
= emit_move_insn (target
, reg
);
10690 else if (DISP_IN_RANGE (INTVAL (offset
))) /* la */
10692 insn
= emit_move_insn (target
, gen_rtx_PLUS (Pmode
, reg
,
10697 if (!satisfies_constraint_K (offset
) /* ahi/aghi */
10699 || (!satisfies_constraint_Op (offset
) /* alfi/algfi */
10700 && !satisfies_constraint_On (offset
)))) /* slfi/slgfi */
10701 offset
= force_const_mem (Pmode
, offset
);
10705 insn
= emit_move_insn (target
, reg
);
10706 RTX_FRAME_RELATED_P (insn
) = frame_related_p
? 1 : 0;
10709 insn
= emit_insn (gen_add2_insn (target
, offset
));
10711 if (!CONST_INT_P (offset
))
10713 annotate_constant_pool_refs (insn
);
10715 if (frame_related_p
)
10716 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
10717 gen_rtx_SET (target
,
10718 gen_rtx_PLUS (Pmode
, target
,
10723 RTX_FRAME_RELATED_P (insn
) = frame_related_p
? 1 : 0;
10725 /* If this is a stack adjustment and we are generating a stack clash
10726 prologue, then add a REG_STACK_CHECK note to signal that this insn
10727 should be left alone. */
10728 if (flag_stack_clash_protection
&& target
== stack_pointer_rtx
)
10729 add_reg_note (insn
, REG_STACK_CHECK
, const0_rtx
);
10734 /* Emit a compare instruction with a volatile memory access as stack
10735 probe. It does not waste store tags and does not clobber any
10736 registers apart from the condition code. */
10738 s390_emit_stack_probe (rtx addr
)
10740 rtx tmp
= gen_rtx_MEM (Pmode
, addr
);
10741 MEM_VOLATILE_P (tmp
) = 1;
10742 s390_emit_compare (EQ
, gen_rtx_REG (Pmode
, 0), tmp
);
10743 emit_insn (gen_blockage ());
10746 /* Use a runtime loop if we have to emit more probes than this. */
10747 #define MIN_UNROLL_PROBES 3
10749 /* Allocate SIZE bytes of stack space, using TEMP_REG as a temporary
10750 if necessary. LAST_PROBE_OFFSET contains the offset of the closest
10751 probe relative to the stack pointer.
10753 Note that SIZE is negative.
10755 The return value is true if TEMP_REG has been clobbered. */
10757 allocate_stack_space (rtx size
, HOST_WIDE_INT last_probe_offset
,
10760 bool temp_reg_clobbered_p
= false;
10761 HOST_WIDE_INT probe_interval
10762 = 1 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
);
10763 HOST_WIDE_INT guard_size
10764 = 1 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE
);
10766 if (flag_stack_clash_protection
)
10768 if (last_probe_offset
+ -INTVAL (size
) < guard_size
)
10769 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME
, true);
10772 rtx offset
= GEN_INT (probe_interval
- UNITS_PER_LONG
);
10773 HOST_WIDE_INT rounded_size
= -INTVAL (size
) & -probe_interval
;
10774 HOST_WIDE_INT num_probes
= rounded_size
/ probe_interval
;
10775 HOST_WIDE_INT residual
= -INTVAL (size
) - rounded_size
;
10777 if (num_probes
< MIN_UNROLL_PROBES
)
10779 /* Emit unrolled probe statements. */
10781 for (unsigned int i
= 0; i
< num_probes
; i
++)
10783 s390_prologue_plus_offset (stack_pointer_rtx
,
10785 GEN_INT (-probe_interval
), true);
10786 s390_emit_stack_probe (gen_rtx_PLUS (Pmode
,
10790 dump_stack_clash_frame_info (PROBE_INLINE
, residual
!= 0);
10794 /* Emit a loop probing the pages. */
10796 rtx_code_label
*loop_start_label
= gen_label_rtx ();
10798 /* From now on temp_reg will be the CFA register. */
10799 s390_prologue_plus_offset (temp_reg
, stack_pointer_rtx
,
10800 GEN_INT (-rounded_size
), true);
10801 emit_label (loop_start_label
);
10803 s390_prologue_plus_offset (stack_pointer_rtx
,
10805 GEN_INT (-probe_interval
), false);
10806 s390_emit_stack_probe (gen_rtx_PLUS (Pmode
,
10809 emit_cmp_and_jump_insns (stack_pointer_rtx
, temp_reg
,
10811 Pmode
, 1, loop_start_label
);
10813 /* Without this make_edges ICEes. */
10814 JUMP_LABEL (get_last_insn ()) = loop_start_label
;
10815 LABEL_NUSES (loop_start_label
) = 1;
10817 /* That's going to be a NOP since stack pointer and
10818 temp_reg are supposed to be the same here. We just
10819 emit it to set the CFA reg back to r15. */
10820 s390_prologue_plus_offset (stack_pointer_rtx
, temp_reg
,
10822 temp_reg_clobbered_p
= true;
10823 dump_stack_clash_frame_info (PROBE_LOOP
, residual
!= 0);
10826 /* Handle any residual allocation request. */
10827 s390_prologue_plus_offset (stack_pointer_rtx
,
10829 GEN_INT (-residual
), true);
10830 last_probe_offset
+= residual
;
10831 if (last_probe_offset
>= probe_interval
)
10832 s390_emit_stack_probe (gen_rtx_PLUS (Pmode
,
10835 - UNITS_PER_LONG
)));
10837 return temp_reg_clobbered_p
;
10841 /* Subtract frame size from stack pointer. */
10842 s390_prologue_plus_offset (stack_pointer_rtx
,
10846 return temp_reg_clobbered_p
;
10849 /* Expand the prologue into a bunch of separate insns. */
10852 s390_emit_prologue (void)
10860 /* Choose best register to use for temp use within prologue.
10861 TPF with profiling must avoid the register 14 - the tracing function
10862 needs the original contents of r14 to be preserved. */
10864 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
10866 && !TARGET_TPF_PROFILING
)
10867 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
10868 else if (flag_split_stack
&& cfun
->stdarg
)
10869 temp_reg
= gen_rtx_REG (Pmode
, 12);
10871 temp_reg
= gen_rtx_REG (Pmode
, 1);
10873 /* When probing for stack-clash mitigation, we have to track the distance
10874 between the stack pointer and closest known reference.
10876 Most of the time we have to make a worst case assumption. The
10877 only exception is when TARGET_BACKCHAIN is active, in which case
10878 we know *sp (offset 0) was written. */
10879 HOST_WIDE_INT probe_interval
10880 = 1 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
);
10881 HOST_WIDE_INT last_probe_offset
10882 = (TARGET_BACKCHAIN
10883 ? (TARGET_PACKED_STACK
? STACK_POINTER_OFFSET
- UNITS_PER_LONG
: 0)
10884 : probe_interval
- (STACK_BOUNDARY
/ UNITS_PER_WORD
));
10886 s390_save_gprs_to_fprs ();
10888 /* Save call saved gprs. */
10889 if (cfun_frame_layout
.first_save_gpr
!= -1)
10891 insn
= save_gprs (stack_pointer_rtx
,
10892 cfun_frame_layout
.gprs_offset
+
10893 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
10894 - cfun_frame_layout
.first_save_gpr_slot
),
10895 cfun_frame_layout
.first_save_gpr
,
10896 cfun_frame_layout
.last_save_gpr
);
10898 /* This is not 100% correct. If we have more than one register saved,
10899 then LAST_PROBE_OFFSET can move even closer to sp. */
10901 = (cfun_frame_layout
.gprs_offset
+
10902 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
10903 - cfun_frame_layout
.first_save_gpr_slot
));
10908 /* Dummy insn to mark literal pool slot. */
10910 if (cfun
->machine
->base_reg
)
10911 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
10913 offset
= cfun_frame_layout
.f0_offset
;
10915 /* Save f0 and f2. */
10916 for (i
= FPR0_REGNUM
; i
<= FPR0_REGNUM
+ 1; i
++)
10918 if (cfun_fpr_save_p (i
))
10920 save_fpr (stack_pointer_rtx
, offset
, i
);
10921 if (offset
< last_probe_offset
)
10922 last_probe_offset
= offset
;
10925 else if (!TARGET_PACKED_STACK
|| cfun
->stdarg
)
10929 /* Save f4 and f6. */
10930 offset
= cfun_frame_layout
.f4_offset
;
10931 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
10933 if (cfun_fpr_save_p (i
))
10935 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
10936 if (offset
< last_probe_offset
)
10937 last_probe_offset
= offset
;
10940 /* If f4 and f6 are call clobbered they are saved due to
10941 stdargs and therefore are not frame related. */
10942 if (!call_really_used_regs
[i
])
10943 RTX_FRAME_RELATED_P (insn
) = 1;
10945 else if (!TARGET_PACKED_STACK
|| call_really_used_regs
[i
])
10949 if (TARGET_PACKED_STACK
10950 && cfun_save_high_fprs_p
10951 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
10953 offset
= (cfun_frame_layout
.f8_offset
10954 + (cfun_frame_layout
.high_fprs
- 1) * 8);
10956 for (i
= FPR15_REGNUM
; i
>= FPR8_REGNUM
&& offset
>= 0; i
--)
10957 if (cfun_fpr_save_p (i
))
10959 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
10960 if (offset
< last_probe_offset
)
10961 last_probe_offset
= offset
;
10963 RTX_FRAME_RELATED_P (insn
) = 1;
10966 if (offset
>= cfun_frame_layout
.f8_offset
)
10970 if (!TARGET_PACKED_STACK
)
10971 next_fpr
= cfun_save_high_fprs_p
? FPR15_REGNUM
: 0;
10973 if (flag_stack_usage_info
)
10974 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
10976 /* Decrement stack pointer. */
10978 if (cfun_frame_layout
.frame_size
> 0)
10980 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
10981 rtx_insn
*stack_pointer_backup_loc
;
10982 bool temp_reg_clobbered_p
;
10984 if (s390_stack_size
)
10986 HOST_WIDE_INT stack_guard
;
10988 if (s390_stack_guard
)
10989 stack_guard
= s390_stack_guard
;
10992 /* If no value for stack guard is provided the smallest power of 2
10993 larger than the current frame size is chosen. */
10995 while (stack_guard
< cfun_frame_layout
.frame_size
)
10999 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
11001 warning (0, "frame size of function %qs is %wd"
11002 " bytes exceeding user provided stack limit of "
11004 "An unconditional trap is added.",
11005 current_function_name(), cfun_frame_layout
.frame_size
,
11007 emit_insn (gen_trap ());
11012 /* stack_guard has to be smaller than s390_stack_size.
11013 Otherwise we would emit an AND with zero which would
11014 not match the test under mask pattern. */
11015 if (stack_guard
>= s390_stack_size
)
11017 warning (0, "frame size of function %qs is %wd"
11018 " bytes which is more than half the stack size. "
11019 "The dynamic check would not be reliable. "
11020 "No check emitted for this function.",
11021 current_function_name(),
11022 cfun_frame_layout
.frame_size
);
11026 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
11027 & ~(stack_guard
- 1));
11029 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
11030 GEN_INT (stack_check_mask
));
11032 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
11034 t
, const0_rtx
, const0_rtx
));
11036 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
11038 t
, const0_rtx
, const0_rtx
));
11043 if (s390_warn_framesize
> 0
11044 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
11045 warning (0, "frame size of %qs is %wd bytes",
11046 current_function_name (), cfun_frame_layout
.frame_size
);
11048 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
11049 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
11051 /* Save the location where we could backup the incoming stack
11053 stack_pointer_backup_loc
= get_last_insn ();
11055 temp_reg_clobbered_p
= allocate_stack_space (frame_off
, last_probe_offset
,
11058 if (TARGET_BACKCHAIN
|| next_fpr
)
11060 if (temp_reg_clobbered_p
)
11062 /* allocate_stack_space had to make use of temp_reg and
11063 we need it to hold a backup of the incoming stack
11064 pointer. Calculate back that value from the current
11066 s390_prologue_plus_offset (temp_reg
, stack_pointer_rtx
,
11067 GEN_INT (cfun_frame_layout
.frame_size
),
11072 /* allocate_stack_space didn't actually required
11073 temp_reg. Insert the stack pointer backup insn
11074 before the stack pointer decrement code - knowing now
11075 that the value will survive. */
11076 emit_insn_after (gen_move_insn (temp_reg
, stack_pointer_rtx
),
11077 stack_pointer_backup_loc
);
11081 /* Set backchain. */
11083 if (TARGET_BACKCHAIN
)
11085 if (cfun_frame_layout
.backchain_offset
)
11086 addr
= gen_rtx_MEM (Pmode
,
11087 plus_constant (Pmode
, stack_pointer_rtx
,
11088 cfun_frame_layout
.backchain_offset
));
11090 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
11091 set_mem_alias_set (addr
, get_frame_alias_set ());
11092 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
11095 /* If we support non-call exceptions (e.g. for Java),
11096 we need to make sure the backchain pointer is set up
11097 before any possibly trapping memory access. */
11098 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
11100 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
11101 emit_clobber (addr
);
11104 else if (flag_stack_clash_protection
)
11105 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME
, false);
11107 /* Save fprs 8 - 15 (64 bit ABI). */
11109 if (cfun_save_high_fprs_p
&& next_fpr
)
11111 /* If the stack might be accessed through a different register
11112 we have to make sure that the stack pointer decrement is not
11113 moved below the use of the stack slots. */
11114 s390_emit_stack_tie ();
11116 insn
= emit_insn (gen_add2_insn (temp_reg
,
11117 GEN_INT (cfun_frame_layout
.f8_offset
)));
11121 for (i
= FPR8_REGNUM
; i
<= next_fpr
; i
++)
11122 if (cfun_fpr_save_p (i
))
11124 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
11125 cfun_frame_layout
.frame_size
11126 + cfun_frame_layout
.f8_offset
11129 insn
= save_fpr (temp_reg
, offset
, i
);
11131 RTX_FRAME_RELATED_P (insn
) = 1;
11132 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
11133 gen_rtx_SET (gen_rtx_MEM (DFmode
, addr
),
11134 gen_rtx_REG (DFmode
, i
)));
11138 /* Set frame pointer, if needed. */
11140 if (frame_pointer_needed
)
11142 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11143 RTX_FRAME_RELATED_P (insn
) = 1;
11146 /* Set up got pointer, if needed. */
11148 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
11150 rtx_insn
*insns
= s390_load_got ();
11152 for (rtx_insn
*insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
11153 annotate_constant_pool_refs (insn
);
11158 if (TARGET_TPF_PROFILING
)
11160 /* Generate a BAS instruction to serve as a function
11161 entry intercept to facilitate the use of tracing
11162 algorithms located at the branch target. */
11163 emit_insn (gen_prologue_tpf ());
11165 /* Emit a blockage here so that all code
11166 lies between the profiling mechanisms. */
11167 emit_insn (gen_blockage ());
11171 /* Expand the epilogue into a bunch of separate insns. */
11174 s390_emit_epilogue (bool sibcall
)
11176 rtx frame_pointer
, return_reg
= NULL_RTX
, cfa_restores
= NULL_RTX
;
11177 int area_bottom
, area_top
, offset
= 0;
11181 if (TARGET_TPF_PROFILING
)
11184 /* Generate a BAS instruction to serve as a function
11185 entry intercept to facilitate the use of tracing
11186 algorithms located at the branch target. */
11188 /* Emit a blockage here so that all code
11189 lies between the profiling mechanisms. */
11190 emit_insn (gen_blockage ());
11192 emit_insn (gen_epilogue_tpf ());
11195 /* Check whether to use frame or stack pointer for restore. */
11197 frame_pointer
= (frame_pointer_needed
11198 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
11200 s390_frame_area (&area_bottom
, &area_top
);
11202 /* Check whether we can access the register save area.
11203 If not, increment the frame pointer as required. */
11205 if (area_top
<= area_bottom
)
11207 /* Nothing to restore. */
11209 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
11210 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
11212 /* Area is in range. */
11213 offset
= cfun_frame_layout
.frame_size
;
11218 rtx frame_off
, cfa
;
11220 offset
= area_bottom
< 0 ? -area_bottom
: 0;
11221 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
11223 cfa
= gen_rtx_SET (frame_pointer
,
11224 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
11225 if (DISP_IN_RANGE (INTVAL (frame_off
)))
11229 set
= gen_rtx_SET (frame_pointer
,
11230 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
11231 insn
= emit_insn (set
);
11235 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
11236 frame_off
= force_const_mem (Pmode
, frame_off
);
11238 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
11239 annotate_constant_pool_refs (insn
);
11241 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
11242 RTX_FRAME_RELATED_P (insn
) = 1;
11245 /* Restore call saved fprs. */
11249 if (cfun_save_high_fprs_p
)
11251 next_offset
= cfun_frame_layout
.f8_offset
;
11252 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
11254 if (cfun_fpr_save_p (i
))
11256 restore_fpr (frame_pointer
,
11257 offset
+ next_offset
, i
);
11259 = alloc_reg_note (REG_CFA_RESTORE
,
11260 gen_rtx_REG (DFmode
, i
), cfa_restores
);
11269 next_offset
= cfun_frame_layout
.f4_offset
;
11271 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
11273 if (cfun_fpr_save_p (i
))
11275 restore_fpr (frame_pointer
,
11276 offset
+ next_offset
, i
);
11278 = alloc_reg_note (REG_CFA_RESTORE
,
11279 gen_rtx_REG (DFmode
, i
), cfa_restores
);
11282 else if (!TARGET_PACKED_STACK
)
11288 /* Restore call saved gprs. */
11290 if (cfun_frame_layout
.first_restore_gpr
!= -1)
11295 /* Check for global register and save them
11296 to stack location from where they get restored. */
11298 for (i
= cfun_frame_layout
.first_restore_gpr
;
11299 i
<= cfun_frame_layout
.last_restore_gpr
;
11302 if (global_not_special_regno_p (i
))
11304 addr
= plus_constant (Pmode
, frame_pointer
,
11305 offset
+ cfun_frame_layout
.gprs_offset
11306 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
11308 addr
= gen_rtx_MEM (Pmode
, addr
);
11309 set_mem_alias_set (addr
, get_frame_alias_set ());
11310 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
11314 = alloc_reg_note (REG_CFA_RESTORE
,
11315 gen_rtx_REG (Pmode
, i
), cfa_restores
);
11318 /* Fetch return address from stack before load multiple,
11319 this will do good for scheduling.
11321 Only do this if we already decided that r14 needs to be
11322 saved to a stack slot. (And not just because r14 happens to
11323 be in between two GPRs which need saving.) Otherwise it
11324 would be difficult to take that decision back in
11325 s390_optimize_prologue.
11327 This optimization is only helpful on in-order machines. */
11329 && cfun_gpr_save_slot (RETURN_REGNUM
) == SAVE_SLOT_STACK
11330 && s390_tune
<= PROCESSOR_2097_Z10
)
11332 int return_regnum
= find_unused_clobbered_reg();
11334 || (TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION
11336 && return_regnum
== INDIRECT_BRANCH_THUNK_REGNUM
))
11338 gcc_assert (INDIRECT_BRANCH_THUNK_REGNUM
!= 4);
11341 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
11343 addr
= plus_constant (Pmode
, frame_pointer
,
11344 offset
+ cfun_frame_layout
.gprs_offset
11346 - cfun_frame_layout
.first_save_gpr_slot
)
11348 addr
= gen_rtx_MEM (Pmode
, addr
);
11349 set_mem_alias_set (addr
, get_frame_alias_set ());
11350 emit_move_insn (return_reg
, addr
);
11352 /* Once we did that optimization we have to make sure
11353 s390_optimize_prologue does not try to remove the store
11354 of r14 since we will not be able to find the load issued
11356 cfun_frame_layout
.save_return_addr_p
= true;
11359 insn
= restore_gprs (frame_pointer
,
11360 offset
+ cfun_frame_layout
.gprs_offset
11361 + (cfun_frame_layout
.first_restore_gpr
11362 - cfun_frame_layout
.first_save_gpr_slot
)
11364 cfun_frame_layout
.first_restore_gpr
,
11365 cfun_frame_layout
.last_restore_gpr
);
11366 insn
= emit_insn (insn
);
11367 REG_NOTES (insn
) = cfa_restores
;
11368 add_reg_note (insn
, REG_CFA_DEF_CFA
,
11369 plus_constant (Pmode
, stack_pointer_rtx
,
11370 STACK_POINTER_OFFSET
));
11371 RTX_FRAME_RELATED_P (insn
) = 1;
11374 s390_restore_gprs_from_fprs ();
11378 if (!return_reg
&& !s390_can_use_return_insn ())
11379 /* We planned to emit (return), be we are not allowed to. */
11380 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
11383 /* Emit (return) and (use). */
11384 emit_jump_insn (gen_return_use (return_reg
));
11386 /* The fact that RETURN_REGNUM is used is already reflected by
11387 EPILOGUE_USES. Emit plain (return). */
11388 emit_jump_insn (gen_return ());
11392 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
11395 s300_set_up_by_prologue (hard_reg_set_container
*regs
)
11397 if (cfun
->machine
->base_reg
11398 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
11399 SET_HARD_REG_BIT (regs
->set
, REGNO (cfun
->machine
->base_reg
));
11402 /* -fsplit-stack support. */
11404 /* A SYMBOL_REF for __morestack. */
11405 static GTY(()) rtx morestack_ref
;
11407 /* When using -fsplit-stack, the allocation routines set a field in
11408 the TCB to the bottom of the stack plus this much space, measured
11411 #define SPLIT_STACK_AVAILABLE 1024
11413 /* Emit -fsplit-stack prologue, which goes before the regular function
11417 s390_expand_split_stack_prologue (void)
11419 rtx r1
, guard
, cc
= NULL
;
11421 /* Offset from thread pointer to __private_ss. */
11422 int psso
= TARGET_64BIT
? 0x38 : 0x20;
11423 /* Pointer size in bytes. */
11424 /* Frame size and argument size - the two parameters to __morestack. */
11425 HOST_WIDE_INT frame_size
= cfun_frame_layout
.frame_size
;
11426 /* Align argument size to 8 bytes - simplifies __morestack code. */
11427 HOST_WIDE_INT args_size
= crtl
->args
.size
>= 0
11428 ? ((crtl
->args
.size
+ 7) & ~7)
11430 /* Label to be called by __morestack. */
11431 rtx_code_label
*call_done
= NULL
;
11432 rtx_code_label
*parm_base
= NULL
;
11435 gcc_assert (flag_split_stack
&& reload_completed
);
11437 r1
= gen_rtx_REG (Pmode
, 1);
11439 /* If no stack frame will be allocated, don't do anything. */
11442 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
11444 /* If va_start is used, just use r15. */
11445 emit_move_insn (r1
,
11446 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
11447 GEN_INT (STACK_POINTER_OFFSET
)));
11453 if (morestack_ref
== NULL_RTX
)
11455 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
11456 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
11457 | SYMBOL_FLAG_FUNCTION
);
11460 if (CONST_OK_FOR_K (frame_size
) || CONST_OK_FOR_Op (frame_size
))
11462 /* If frame_size will fit in an add instruction, do a stack space
11463 check, and only call __morestack if there's not enough space. */
11465 /* Get thread pointer. r1 is the only register we can always destroy - r0
11466 could contain a static chain (and cannot be used to address memory
11467 anyway), r2-r6 can contain parameters, and r6-r15 are callee-saved. */
11468 emit_move_insn (r1
, gen_rtx_REG (Pmode
, TP_REGNUM
));
11469 /* Aim at __private_ss. */
11470 guard
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
, r1
, psso
));
11472 /* If less that 1kiB used, skip addition and compare directly with
11474 if (frame_size
> SPLIT_STACK_AVAILABLE
)
11476 emit_move_insn (r1
, guard
);
11478 emit_insn (gen_adddi3 (r1
, r1
, GEN_INT (frame_size
)));
11480 emit_insn (gen_addsi3 (r1
, r1
, GEN_INT (frame_size
)));
11484 /* Compare the (maybe adjusted) guard with the stack pointer. */
11485 cc
= s390_emit_compare (LT
, stack_pointer_rtx
, guard
);
11488 call_done
= gen_label_rtx ();
11489 parm_base
= gen_label_rtx ();
11491 /* Emit the parameter block. */
11492 tmp
= gen_split_stack_data (parm_base
, call_done
,
11493 GEN_INT (frame_size
),
11494 GEN_INT (args_size
));
11495 insn
= emit_insn (tmp
);
11496 add_reg_note (insn
, REG_LABEL_OPERAND
, call_done
);
11497 LABEL_NUSES (call_done
)++;
11498 add_reg_note (insn
, REG_LABEL_OPERAND
, parm_base
);
11499 LABEL_NUSES (parm_base
)++;
11501 /* %r1 = litbase. */
11502 insn
= emit_move_insn (r1
, gen_rtx_LABEL_REF (VOIDmode
, parm_base
));
11503 add_reg_note (insn
, REG_LABEL_OPERAND
, parm_base
);
11504 LABEL_NUSES (parm_base
)++;
11506 /* Now, we need to call __morestack. It has very special calling
11507 conventions: it preserves param/return/static chain registers for
11508 calling main function body, and looks for its own parameters at %r1. */
11512 tmp
= gen_split_stack_cond_call (morestack_ref
, cc
, call_done
);
11514 insn
= emit_jump_insn (tmp
);
11515 JUMP_LABEL (insn
) = call_done
;
11516 LABEL_NUSES (call_done
)++;
11518 /* Mark the jump as very unlikely to be taken. */
11519 add_reg_br_prob_note (insn
,
11520 profile_probability::very_unlikely ());
11522 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
11524 /* If va_start is used, and __morestack was not called, just use
11526 emit_move_insn (r1
,
11527 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
11528 GEN_INT (STACK_POINTER_OFFSET
)));
11533 tmp
= gen_split_stack_call (morestack_ref
, call_done
);
11534 insn
= emit_jump_insn (tmp
);
11535 JUMP_LABEL (insn
) = call_done
;
11536 LABEL_NUSES (call_done
)++;
11540 /* __morestack will call us here. */
11542 emit_label (call_done
);
11545 /* We may have to tell the dataflow pass that the split stack prologue
11546 is initializing a register. */
11549 s390_live_on_entry (bitmap regs
)
11551 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
11553 gcc_assert (flag_split_stack
);
11554 bitmap_set_bit (regs
, 1);
11558 /* Return true if the function can use simple_return to return outside
11559 of a shrink-wrapped region. At present shrink-wrapping is supported
11563 s390_can_use_simple_return_insn (void)
11568 /* Return true if the epilogue is guaranteed to contain only a return
11569 instruction and if a direct return can therefore be used instead.
11570 One of the main advantages of using direct return instructions
11571 is that we can then use conditional returns. */
11574 s390_can_use_return_insn (void)
11578 if (!reload_completed
)
11584 if (TARGET_TPF_PROFILING
)
11587 for (i
= 0; i
< 16; i
++)
11588 if (cfun_gpr_save_slot (i
) != SAVE_SLOT_NONE
)
11591 /* For 31 bit this is not covered by the frame_size check below
11592 since f4, f6 are saved in the register save area without needing
11593 additional stack space. */
11595 && (cfun_fpr_save_p (FPR4_REGNUM
) || cfun_fpr_save_p (FPR6_REGNUM
)))
11598 if (cfun
->machine
->base_reg
11599 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
11602 return cfun_frame_layout
.frame_size
== 0;
11605 /* The VX ABI differs for vararg functions. Therefore we need the
11606 prototype of the callee to be available when passing vector type
11608 static const char *
11609 s390_invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
11611 return ((TARGET_VX_ABI
11613 && VECTOR_TYPE_P (TREE_TYPE (val
))
11614 && (funcdecl
== NULL_TREE
11615 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
11616 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
11617 ? N_("vector argument passed to unprototyped function")
11622 /* Return the size in bytes of a function argument of
11623 type TYPE and/or mode MODE. At least one of TYPE or
11624 MODE must be specified. */
11627 s390_function_arg_size (machine_mode mode
, const_tree type
)
11630 return int_size_in_bytes (type
);
11632 /* No type info available for some library calls ... */
11633 if (mode
!= BLKmode
)
11634 return GET_MODE_SIZE (mode
);
11636 /* If we have neither type nor mode, abort */
11637 gcc_unreachable ();
11640 /* Return true if a function argument of type TYPE and mode MODE
11641 is to be passed in a vector register, if available. */
11644 s390_function_arg_vector (machine_mode mode
, const_tree type
)
11646 if (!TARGET_VX_ABI
)
11649 if (s390_function_arg_size (mode
, type
) > 16)
11652 /* No type info available for some library calls ... */
11654 return VECTOR_MODE_P (mode
);
11656 /* The ABI says that record types with a single member are treated
11657 just like that member would be. */
11658 while (TREE_CODE (type
) == RECORD_TYPE
)
11660 tree field
, single
= NULL_TREE
;
11662 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
11664 if (TREE_CODE (field
) != FIELD_DECL
)
11667 if (single
== NULL_TREE
)
11668 single
= TREE_TYPE (field
);
11673 if (single
== NULL_TREE
)
11677 /* If the field declaration adds extra byte due to
11678 e.g. padding this is not accepted as vector type. */
11679 if (int_size_in_bytes (single
) <= 0
11680 || int_size_in_bytes (single
) != int_size_in_bytes (type
))
11686 return VECTOR_TYPE_P (type
);
11689 /* Return true if a function argument of type TYPE and mode MODE
11690 is to be passed in a floating-point register, if available. */
11693 s390_function_arg_float (machine_mode mode
, const_tree type
)
11695 if (s390_function_arg_size (mode
, type
) > 8)
11698 /* Soft-float changes the ABI: no floating-point registers are used. */
11699 if (TARGET_SOFT_FLOAT
)
11702 /* No type info available for some library calls ... */
11704 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
11706 /* The ABI says that record types with a single member are treated
11707 just like that member would be. */
11708 while (TREE_CODE (type
) == RECORD_TYPE
)
11710 tree field
, single
= NULL_TREE
;
11712 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
11714 if (TREE_CODE (field
) != FIELD_DECL
)
11717 if (single
== NULL_TREE
)
11718 single
= TREE_TYPE (field
);
11723 if (single
== NULL_TREE
)
11729 return TREE_CODE (type
) == REAL_TYPE
;
11732 /* Return true if a function argument of type TYPE and mode MODE
11733 is to be passed in an integer register, or a pair of integer
11734 registers, if available. */
11737 s390_function_arg_integer (machine_mode mode
, const_tree type
)
11739 int size
= s390_function_arg_size (mode
, type
);
11743 /* No type info available for some library calls ... */
11745 return GET_MODE_CLASS (mode
) == MODE_INT
11746 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
11748 /* We accept small integral (and similar) types. */
11749 if (INTEGRAL_TYPE_P (type
)
11750 || POINTER_TYPE_P (type
)
11751 || TREE_CODE (type
) == NULLPTR_TYPE
11752 || TREE_CODE (type
) == OFFSET_TYPE
11753 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
11756 /* We also accept structs of size 1, 2, 4, 8 that are not
11757 passed in floating-point registers. */
11758 if (AGGREGATE_TYPE_P (type
)
11759 && exact_log2 (size
) >= 0
11760 && !s390_function_arg_float (mode
, type
))
11766 /* Return 1 if a function argument of type TYPE and mode MODE
11767 is to be passed by reference. The ABI specifies that only
11768 structures of size 1, 2, 4, or 8 bytes are passed by value,
11769 all other structures (and complex numbers) are passed by
11773 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
11774 machine_mode mode
, const_tree type
,
11775 bool named ATTRIBUTE_UNUSED
)
11777 int size
= s390_function_arg_size (mode
, type
);
11779 if (s390_function_arg_vector (mode
, type
))
11787 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
11790 if (TREE_CODE (type
) == COMPLEX_TYPE
11791 || TREE_CODE (type
) == VECTOR_TYPE
)
11798 /* Update the data in CUM to advance over an argument of mode MODE and
11799 data type TYPE. (TYPE is null for libcalls where that information
11800 may not be available.). The boolean NAMED specifies whether the
11801 argument is a named argument (as opposed to an unnamed argument
11802 matching an ellipsis). */
11805 s390_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
11806 const_tree type
, bool named
)
11808 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11810 if (s390_function_arg_vector (mode
, type
))
11812 /* We are called for unnamed vector stdarg arguments which are
11813 passed on the stack. In this case this hook does not have to
11814 do anything since stack arguments are tracked by common
11820 else if (s390_function_arg_float (mode
, type
))
11824 else if (s390_function_arg_integer (mode
, type
))
11826 int size
= s390_function_arg_size (mode
, type
);
11827 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
11830 gcc_unreachable ();
11833 /* Define where to put the arguments to a function.
11834 Value is zero to push the argument on the stack,
11835 or a hard register in which to store the argument.
11837 MODE is the argument's machine mode.
11838 TYPE is the data type of the argument (as a tree).
11839 This is null for libcalls where that information may
11841 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11842 the preceding args and about the function being called.
11843 NAMED is nonzero if this argument is a named parameter
11844 (otherwise it is an extra parameter matching an ellipsis).
11846 On S/390, we use general purpose registers 2 through 6 to
11847 pass integer, pointer, and certain structure arguments, and
11848 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
11849 to pass floating point arguments. All remaining arguments
11850 are pushed to the stack. */
11853 s390_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
11854 const_tree type
, bool named
)
11856 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11859 s390_check_type_for_vector_abi (type
, true, false);
11861 if (s390_function_arg_vector (mode
, type
))
11863 /* Vector arguments being part of the ellipsis are passed on the
11865 if (!named
|| (cum
->vrs
+ 1 > VEC_ARG_NUM_REG
))
11868 return gen_rtx_REG (mode
, cum
->vrs
+ FIRST_VEC_ARG_REGNO
);
11870 else if (s390_function_arg_float (mode
, type
))
11872 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
11875 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
11877 else if (s390_function_arg_integer (mode
, type
))
11879 int size
= s390_function_arg_size (mode
, type
);
11880 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
11882 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
11884 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
11885 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
11886 else if (n_gprs
== 2)
11888 rtvec p
= rtvec_alloc (2);
11891 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
11894 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
11897 return gen_rtx_PARALLEL (mode
, p
);
11901 /* After the real arguments, expand_call calls us once again
11902 with a void_type_node type. Whatever we return here is
11903 passed as operand 2 to the call expanders.
11905 We don't need this feature ... */
11906 else if (type
== void_type_node
)
11909 gcc_unreachable ();
11912 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Vector arguments are
11913 left-justified when placed on the stack during parameter passing. */
11915 static pad_direction
11916 s390_function_arg_padding (machine_mode mode
, const_tree type
)
11918 if (s390_function_arg_vector (mode
, type
))
11921 return default_function_arg_padding (mode
, type
);
11924 /* Return true if return values of type TYPE should be returned
11925 in a memory buffer whose address is passed by the caller as
11926 hidden first argument. */
11929 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
11931 /* We accept small integral (and similar) types. */
11932 if (INTEGRAL_TYPE_P (type
)
11933 || POINTER_TYPE_P (type
)
11934 || TREE_CODE (type
) == OFFSET_TYPE
11935 || TREE_CODE (type
) == REAL_TYPE
)
11936 return int_size_in_bytes (type
) > 8;
11938 /* vector types which fit into a VR. */
11940 && VECTOR_TYPE_P (type
)
11941 && int_size_in_bytes (type
) <= 16)
11944 /* Aggregates and similar constructs are always returned
11946 if (AGGREGATE_TYPE_P (type
)
11947 || TREE_CODE (type
) == COMPLEX_TYPE
11948 || VECTOR_TYPE_P (type
))
11951 /* ??? We get called on all sorts of random stuff from
11952 aggregate_value_p. We can't abort, but it's not clear
11953 what's safe to return. Pretend it's a struct I guess. */
11957 /* Function arguments and return values are promoted to word size. */
11959 static machine_mode
11960 s390_promote_function_mode (const_tree type
, machine_mode mode
,
11962 const_tree fntype ATTRIBUTE_UNUSED
,
11963 int for_return ATTRIBUTE_UNUSED
)
11965 if (INTEGRAL_MODE_P (mode
)
11966 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
11968 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
11969 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
11976 /* Define where to return a (scalar) value of type RET_TYPE.
11977 If RET_TYPE is null, define where to return a (scalar)
11978 value of mode MODE from a libcall. */
11981 s390_function_and_libcall_value (machine_mode mode
,
11982 const_tree ret_type
,
11983 const_tree fntype_or_decl
,
11984 bool outgoing ATTRIBUTE_UNUSED
)
11986 /* For vector return types it is important to use the RET_TYPE
11987 argument whenever available since the middle-end might have
11988 changed the mode to a scalar mode. */
11989 bool vector_ret_type_p
= ((ret_type
&& VECTOR_TYPE_P (ret_type
))
11990 || (!ret_type
&& VECTOR_MODE_P (mode
)));
11992 /* For normal functions perform the promotion as
11993 promote_function_mode would do. */
11996 int unsignedp
= TYPE_UNSIGNED (ret_type
);
11997 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
11998 fntype_or_decl
, 1);
12001 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
12002 || SCALAR_FLOAT_MODE_P (mode
)
12003 || (TARGET_VX_ABI
&& vector_ret_type_p
));
12004 gcc_assert (GET_MODE_SIZE (mode
) <= (TARGET_VX_ABI
? 16 : 8));
12006 if (TARGET_VX_ABI
&& vector_ret_type_p
)
12007 return gen_rtx_REG (mode
, FIRST_VEC_ARG_REGNO
);
12008 else if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
12009 return gen_rtx_REG (mode
, 16);
12010 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
12011 || UNITS_PER_LONG
== UNITS_PER_WORD
)
12012 return gen_rtx_REG (mode
, 2);
12013 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
12015 /* This case is triggered when returning a 64 bit value with
12016 -m31 -mzarch. Although the value would fit into a single
12017 register it has to be forced into a 32 bit register pair in
12018 order to match the ABI. */
12019 rtvec p
= rtvec_alloc (2);
12022 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
12024 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
12026 return gen_rtx_PARALLEL (mode
, p
);
12029 gcc_unreachable ();
12032 /* Define where to return a scalar return value of type RET_TYPE. */
12035 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
12038 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
12039 fn_decl_or_type
, outgoing
);
12042 /* Define where to return a scalar libcall return value of mode
12046 s390_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
12048 return s390_function_and_libcall_value (mode
, NULL_TREE
,
12053 /* Create and return the va_list datatype.
12055 On S/390, va_list is an array type equivalent to
12057 typedef struct __va_list_tag
12061 void *__overflow_arg_area;
12062 void *__reg_save_area;
12065 where __gpr and __fpr hold the number of general purpose
12066 or floating point arguments used up to now, respectively,
12067 __overflow_arg_area points to the stack location of the
12068 next argument passed on the stack, and __reg_save_area
12069 always points to the start of the register area in the
12070 call frame of the current function. The function prologue
12071 saves all registers used for argument passing into this
12072 area if the function uses variable arguments. */
12075 s390_build_builtin_va_list (void)
12077 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
12079 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
12082 build_decl (BUILTINS_LOCATION
,
12083 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
12085 f_gpr
= build_decl (BUILTINS_LOCATION
,
12086 FIELD_DECL
, get_identifier ("__gpr"),
12087 long_integer_type_node
);
12088 f_fpr
= build_decl (BUILTINS_LOCATION
,
12089 FIELD_DECL
, get_identifier ("__fpr"),
12090 long_integer_type_node
);
12091 f_ovf
= build_decl (BUILTINS_LOCATION
,
12092 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
12094 f_sav
= build_decl (BUILTINS_LOCATION
,
12095 FIELD_DECL
, get_identifier ("__reg_save_area"),
12098 va_list_gpr_counter_field
= f_gpr
;
12099 va_list_fpr_counter_field
= f_fpr
;
12101 DECL_FIELD_CONTEXT (f_gpr
) = record
;
12102 DECL_FIELD_CONTEXT (f_fpr
) = record
;
12103 DECL_FIELD_CONTEXT (f_ovf
) = record
;
12104 DECL_FIELD_CONTEXT (f_sav
) = record
;
12106 TYPE_STUB_DECL (record
) = type_decl
;
12107 TYPE_NAME (record
) = type_decl
;
12108 TYPE_FIELDS (record
) = f_gpr
;
12109 DECL_CHAIN (f_gpr
) = f_fpr
;
12110 DECL_CHAIN (f_fpr
) = f_ovf
;
12111 DECL_CHAIN (f_ovf
) = f_sav
;
12113 layout_type (record
);
12115 /* The correct type is an array type of one element. */
12116 return build_array_type (record
, build_index_type (size_zero_node
));
12119 /* Implement va_start by filling the va_list structure VALIST.
12120 STDARG_P is always true, and ignored.
12121 NEXTARG points to the first anonymous stack argument.
12123 The following global variables are used to initialize
12124 the va_list structure:
12127 holds number of gprs and fprs used for named arguments.
12128 crtl->args.arg_offset_rtx:
12129 holds the offset of the first anonymous stack argument
12130 (relative to the virtual arg pointer). */
12133 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
12135 HOST_WIDE_INT n_gpr
, n_fpr
;
12137 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
12138 tree gpr
, fpr
, ovf
, sav
, t
;
12140 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12141 f_fpr
= DECL_CHAIN (f_gpr
);
12142 f_ovf
= DECL_CHAIN (f_fpr
);
12143 f_sav
= DECL_CHAIN (f_ovf
);
12145 valist
= build_simple_mem_ref (valist
);
12146 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12147 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
12148 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
12149 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
12151 /* Count number of gp and fp argument registers used. */
12153 n_gpr
= crtl
->args
.info
.gprs
;
12154 n_fpr
= crtl
->args
.info
.fprs
;
12156 if (cfun
->va_list_gpr_size
)
12158 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
12159 build_int_cst (NULL_TREE
, n_gpr
));
12160 TREE_SIDE_EFFECTS (t
) = 1;
12161 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12164 if (cfun
->va_list_fpr_size
)
12166 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
12167 build_int_cst (NULL_TREE
, n_fpr
));
12168 TREE_SIDE_EFFECTS (t
) = 1;
12169 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12172 if (flag_split_stack
12173 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
12175 && cfun
->machine
->split_stack_varargs_pointer
== NULL_RTX
)
12180 reg
= gen_reg_rtx (Pmode
);
12181 cfun
->machine
->split_stack_varargs_pointer
= reg
;
12184 emit_move_insn (reg
, gen_rtx_REG (Pmode
, 1));
12185 seq
= get_insns ();
12188 push_topmost_sequence ();
12189 emit_insn_after (seq
, entry_of_function ());
12190 pop_topmost_sequence ();
12193 /* Find the overflow area.
12194 FIXME: This currently is too pessimistic when the vector ABI is
12195 enabled. In that case we *always* set up the overflow area
12197 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
12198 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
12201 if (cfun
->machine
->split_stack_varargs_pointer
== NULL_RTX
)
12202 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
12204 t
= make_tree (TREE_TYPE (ovf
), cfun
->machine
->split_stack_varargs_pointer
);
12206 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
12207 off
= off
< 0 ? 0 : off
;
12208 if (TARGET_DEBUG_ARG
)
12209 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
12210 (int)n_gpr
, (int)n_fpr
, off
);
12212 t
= fold_build_pointer_plus_hwi (t
, off
);
12214 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
12215 TREE_SIDE_EFFECTS (t
) = 1;
12216 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12219 /* Find the register save area. */
12220 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
12221 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
12223 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
12224 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
12226 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
12227 TREE_SIDE_EFFECTS (t
) = 1;
12228 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12232 /* Implement va_arg by updating the va_list structure
12233 VALIST as required to retrieve an argument of type
12234 TYPE, and returning that argument.
12236 Generates code equivalent to:
12238 if (integral value) {
12239 if (size <= 4 && args.gpr < 5 ||
12240 size > 4 && args.gpr < 4 )
12241 ret = args.reg_save_area[args.gpr+8]
12243 ret = *args.overflow_arg_area++;
12244 } else if (vector value) {
12245 ret = *args.overflow_arg_area;
12246 args.overflow_arg_area += size / 8;
12247 } else if (float value) {
12249 ret = args.reg_save_area[args.fpr+64]
12251 ret = *args.overflow_arg_area++;
12252 } else if (aggregate value) {
12254 ret = *args.reg_save_area[args.gpr]
12256 ret = **args.overflow_arg_area++;
12260 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
12261 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
12263 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
12264 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
12265 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
12266 tree lab_false
, lab_over
= NULL_TREE
;
12267 tree addr
= create_tmp_var (ptr_type_node
, "addr");
12268 bool left_align_p
; /* How a value < UNITS_PER_LONG is aligned within
12271 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12272 f_fpr
= DECL_CHAIN (f_gpr
);
12273 f_ovf
= DECL_CHAIN (f_fpr
);
12274 f_sav
= DECL_CHAIN (f_ovf
);
12276 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12277 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
12278 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
12280 /* The tree for args* cannot be shared between gpr/fpr and ovf since
12281 both appear on a lhs. */
12282 valist
= unshare_expr (valist
);
12283 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
12285 size
= int_size_in_bytes (type
);
12287 s390_check_type_for_vector_abi (type
, true, false);
12289 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
12291 if (TARGET_DEBUG_ARG
)
12293 fprintf (stderr
, "va_arg: aggregate type");
12297 /* Aggregates are passed by reference. */
12302 /* kernel stack layout on 31 bit: It is assumed here that no padding
12303 will be added by s390_frame_info because for va_args always an even
12304 number of gprs has to be saved r15-r2 = 14 regs. */
12305 sav_ofs
= 2 * UNITS_PER_LONG
;
12306 sav_scale
= UNITS_PER_LONG
;
12307 size
= UNITS_PER_LONG
;
12308 max_reg
= GP_ARG_NUM_REG
- n_reg
;
12309 left_align_p
= false;
12311 else if (s390_function_arg_vector (TYPE_MODE (type
), type
))
12313 if (TARGET_DEBUG_ARG
)
12315 fprintf (stderr
, "va_arg: vector type");
12325 left_align_p
= true;
12327 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
12329 if (TARGET_DEBUG_ARG
)
12331 fprintf (stderr
, "va_arg: float type");
12335 /* FP args go in FP registers, if present. */
12339 sav_ofs
= 16 * UNITS_PER_LONG
;
12341 max_reg
= FP_ARG_NUM_REG
- n_reg
;
12342 left_align_p
= false;
12346 if (TARGET_DEBUG_ARG
)
12348 fprintf (stderr
, "va_arg: other type");
12352 /* Otherwise into GP registers. */
12355 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
12357 /* kernel stack layout on 31 bit: It is assumed here that no padding
12358 will be added by s390_frame_info because for va_args always an even
12359 number of gprs has to be saved r15-r2 = 14 regs. */
12360 sav_ofs
= 2 * UNITS_PER_LONG
;
12362 if (size
< UNITS_PER_LONG
)
12363 sav_ofs
+= UNITS_PER_LONG
- size
;
12365 sav_scale
= UNITS_PER_LONG
;
12366 max_reg
= GP_ARG_NUM_REG
- n_reg
;
12367 left_align_p
= false;
12370 /* Pull the value out of the saved registers ... */
12372 if (reg
!= NULL_TREE
)
12375 if (reg > ((typeof (reg))max_reg))
12378 addr = sav + sav_ofs + reg * save_scale;
12385 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
12386 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
12388 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
12389 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
12390 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
12391 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
12392 gimplify_and_add (t
, pre_p
);
12394 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
12395 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
12396 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
12397 t
= fold_build_pointer_plus (t
, u
);
12399 gimplify_assign (addr
, t
, pre_p
);
12401 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
12403 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
12406 /* ... Otherwise out of the overflow area. */
12409 if (size
< UNITS_PER_LONG
&& !left_align_p
)
12410 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
12412 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
12414 gimplify_assign (addr
, t
, pre_p
);
12416 if (size
< UNITS_PER_LONG
&& left_align_p
)
12417 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
);
12419 t
= fold_build_pointer_plus_hwi (t
, size
);
12421 gimplify_assign (ovf
, t
, pre_p
);
12423 if (reg
!= NULL_TREE
)
12424 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
12427 /* Increment register save count. */
12431 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
12432 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
12433 gimplify_and_add (u
, pre_p
);
12438 t
= build_pointer_type_for_mode (build_pointer_type (type
),
12440 addr
= fold_convert (t
, addr
);
12441 addr
= build_va_arg_indirect_ref (addr
);
12445 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
12446 addr
= fold_convert (t
, addr
);
12449 return build_va_arg_indirect_ref (addr
);
12452 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
12454 DEST - Register location where CC will be stored.
12455 TDB - Pointer to a 256 byte area where to store the transaction.
12456 diagnostic block. NULL if TDB is not needed.
12457 RETRY - Retry count value. If non-NULL a retry loop for CC2
12459 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
12460 of the tbegin instruction pattern. */
12463 s390_expand_tbegin (rtx dest
, rtx tdb
, rtx retry
, bool clobber_fprs_p
)
12465 rtx retry_plus_two
= gen_reg_rtx (SImode
);
12466 rtx retry_reg
= gen_reg_rtx (SImode
);
12467 rtx_code_label
*retry_label
= NULL
;
12469 if (retry
!= NULL_RTX
)
12471 emit_move_insn (retry_reg
, retry
);
12472 emit_insn (gen_addsi3 (retry_plus_two
, retry_reg
, const2_rtx
));
12473 emit_insn (gen_addsi3 (retry_reg
, retry_reg
, const1_rtx
));
12474 retry_label
= gen_label_rtx ();
12475 emit_label (retry_label
);
12478 if (clobber_fprs_p
)
12481 emit_insn (gen_tbegin_1_z13 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12484 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12488 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12491 emit_move_insn (dest
, gen_rtx_UNSPEC (SImode
,
12492 gen_rtvec (1, gen_rtx_REG (CCRAWmode
,
12494 UNSPEC_CC_TO_INT
));
12495 if (retry
!= NULL_RTX
)
12497 const int CC0
= 1 << 3;
12498 const int CC1
= 1 << 2;
12499 const int CC3
= 1 << 0;
12501 rtx count
= gen_reg_rtx (SImode
);
12502 rtx_code_label
*leave_label
= gen_label_rtx ();
12504 /* Exit for success and permanent failures. */
12505 jump
= s390_emit_jump (leave_label
,
12506 gen_rtx_EQ (VOIDmode
,
12507 gen_rtx_REG (CCRAWmode
, CC_REGNUM
),
12508 gen_rtx_CONST_INT (VOIDmode
, CC0
| CC1
| CC3
)));
12509 LABEL_NUSES (leave_label
) = 1;
12511 /* CC2 - transient failure. Perform retry with ppa. */
12512 emit_move_insn (count
, retry_plus_two
);
12513 emit_insn (gen_subsi3 (count
, count
, retry_reg
));
12514 emit_insn (gen_tx_assist (count
));
12515 jump
= emit_jump_insn (gen_doloop_si64 (retry_label
,
12518 JUMP_LABEL (jump
) = retry_label
;
12519 LABEL_NUSES (retry_label
) = 1;
12520 emit_label (leave_label
);
12525 /* Return the decl for the target specific builtin with the function
12529 s390_builtin_decl (unsigned fcode
, bool initialized_p ATTRIBUTE_UNUSED
)
12531 if (fcode
>= S390_BUILTIN_MAX
)
12532 return error_mark_node
;
12534 return s390_builtin_decls
[fcode
];
12537 /* We call mcount before the function prologue. So a profiled leaf
12538 function should stay a leaf function. */
12541 s390_keep_leaf_when_profiled ()
12546 /* Output assembly code for the trampoline template to
12549 On S/390, we use gpr 1 internally in the trampoline code;
12550 gpr 0 is used to hold the static chain. */
12553 s390_asm_trampoline_template (FILE *file
)
12556 op
[0] = gen_rtx_REG (Pmode
, 0);
12557 op
[1] = gen_rtx_REG (Pmode
, 1);
12561 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
12562 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
12563 output_asm_insn ("br\t%1", op
); /* 2 byte */
12564 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
12568 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
12569 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
12570 output_asm_insn ("br\t%1", op
); /* 2 byte */
12571 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
12575 /* Emit RTL insns to initialize the variable parts of a trampoline.
12576 FNADDR is an RTX for the address of the function's pure code.
12577 CXT is an RTX for the static chain value for the function. */
12580 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
12582 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
12585 emit_block_move (m_tramp
, assemble_trampoline_template (),
12586 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
12588 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
12589 emit_move_insn (mem
, cxt
);
12590 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
12591 emit_move_insn (mem
, fnaddr
);
12595 output_asm_nops (const char *user
, int hw
)
12597 asm_fprintf (asm_out_file
, "\t# NOPs for %s (%d halfwords)\n", user
, hw
);
12602 output_asm_insn ("brcl\t0,0", NULL
);
12607 output_asm_insn ("bc\t0,0", NULL
);
12612 output_asm_insn ("bcr\t0,0", NULL
);
12618 /* Output assembler code to FILE to increment profiler label # LABELNO
12619 for profiling a function entry. */
12622 s390_function_profiler (FILE *file
, int labelno
)
12627 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
12629 fprintf (file
, "# function profiler \n");
12631 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
12632 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
12633 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
12634 op
[7] = GEN_INT (UNITS_PER_LONG
);
12636 op
[2] = gen_rtx_REG (Pmode
, 1);
12637 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
12638 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
12640 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, flag_fentry
? "__fentry__" : "_mcount");
12643 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
12644 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
12647 if (flag_record_mcount
)
12648 fprintf (file
, "1:\n");
12652 if (flag_nop_mcount
)
12653 output_asm_nops ("-mnop-mcount", /* brasl */ 3);
12654 else if (cfun
->static_chain_decl
)
12655 warning (OPT_Wcannot_profile
, "nested functions cannot be profiled "
12656 "with %<-mfentry%> on s390");
12658 output_asm_insn ("brasl\t0,%4", op
);
12660 else if (TARGET_64BIT
)
12662 if (flag_nop_mcount
)
12663 output_asm_nops ("-mnop-mcount", /* stg */ 3 + /* larl */ 3 +
12664 /* brasl */ 3 + /* lg */ 3);
12667 output_asm_insn ("stg\t%0,%1", op
);
12668 if (flag_dwarf2_cfi_asm
)
12669 output_asm_insn (".cfi_rel_offset\t%0,%7", op
);
12670 output_asm_insn ("larl\t%2,%3", op
);
12671 output_asm_insn ("brasl\t%0,%4", op
);
12672 output_asm_insn ("lg\t%0,%1", op
);
12673 if (flag_dwarf2_cfi_asm
)
12674 output_asm_insn (".cfi_restore\t%0", op
);
12679 if (flag_nop_mcount
)
12680 output_asm_nops ("-mnop-mcount", /* st */ 2 + /* larl */ 3 +
12681 /* brasl */ 3 + /* l */ 2);
12684 output_asm_insn ("st\t%0,%1", op
);
12685 if (flag_dwarf2_cfi_asm
)
12686 output_asm_insn (".cfi_rel_offset\t%0,%7", op
);
12687 output_asm_insn ("larl\t%2,%3", op
);
12688 output_asm_insn ("brasl\t%0,%4", op
);
12689 output_asm_insn ("l\t%0,%1", op
);
12690 if (flag_dwarf2_cfi_asm
)
12691 output_asm_insn (".cfi_restore\t%0", op
);
12695 if (flag_record_mcount
)
12697 fprintf (file
, "\t.section __mcount_loc, \"a\",@progbits\n");
12698 fprintf (file
, "\t.%s 1b\n", TARGET_64BIT
? "quad" : "long");
12699 fprintf (file
, "\t.previous\n");
12703 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
12704 into its SYMBOL_REF_FLAGS. */
12707 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
12709 default_encode_section_info (decl
, rtl
, first
);
12711 if (TREE_CODE (decl
) == VAR_DECL
)
12713 /* Store the alignment to be able to check if we can use
12714 a larl/load-relative instruction. We only handle the cases
12715 that can go wrong (i.e. no FUNC_DECLs). */
12716 if (DECL_ALIGN (decl
) == 0 || DECL_ALIGN (decl
) % 16)
12717 SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl
, 0));
12718 else if (DECL_ALIGN (decl
) % 32)
12719 SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl
, 0));
12720 else if (DECL_ALIGN (decl
) % 64)
12721 SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl
, 0));
12724 /* Literal pool references don't have a decl so they are handled
12725 differently here. We rely on the information in the MEM_ALIGN
12726 entry to decide upon the alignment. */
12728 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
12729 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0)))
12731 if (MEM_ALIGN (rtl
) == 0 || MEM_ALIGN (rtl
) % 16)
12732 SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl
, 0));
12733 else if (MEM_ALIGN (rtl
) % 32)
12734 SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl
, 0));
12735 else if (MEM_ALIGN (rtl
) % 64)
12736 SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl
, 0));
12740 /* Output thunk to FILE that implements a C++ virtual function call (with
12741 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
12742 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
12743 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
12744 relative to the resulting this pointer. */
12747 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
12748 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12754 /* Make sure unwind info is emitted for the thunk if needed. */
12755 final_start_function (emit_barrier (), file
, 1);
12757 /* Operand 0 is the target function. */
12758 op
[0] = XEXP (DECL_RTL (function
), 0);
12759 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
12762 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
12763 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
12764 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
12767 /* Operand 1 is the 'this' pointer. */
12768 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12769 op
[1] = gen_rtx_REG (Pmode
, 3);
12771 op
[1] = gen_rtx_REG (Pmode
, 2);
12773 /* Operand 2 is the delta. */
12774 op
[2] = GEN_INT (delta
);
12776 /* Operand 3 is the vcall_offset. */
12777 op
[3] = GEN_INT (vcall_offset
);
12779 /* Operand 4 is the temporary register. */
12780 op
[4] = gen_rtx_REG (Pmode
, 1);
12782 /* Operands 5 to 8 can be used as labels. */
12788 /* Operand 9 can be used for temporary register. */
12791 /* Generate code. */
12794 /* Setup literal pool pointer if required. */
12795 if ((!DISP_IN_RANGE (delta
)
12796 && !CONST_OK_FOR_K (delta
)
12797 && !CONST_OK_FOR_Os (delta
))
12798 || (!DISP_IN_RANGE (vcall_offset
)
12799 && !CONST_OK_FOR_K (vcall_offset
)
12800 && !CONST_OK_FOR_Os (vcall_offset
)))
12802 op
[5] = gen_label_rtx ();
12803 output_asm_insn ("larl\t%4,%5", op
);
12806 /* Add DELTA to this pointer. */
12809 if (CONST_OK_FOR_J (delta
))
12810 output_asm_insn ("la\t%1,%2(%1)", op
);
12811 else if (DISP_IN_RANGE (delta
))
12812 output_asm_insn ("lay\t%1,%2(%1)", op
);
12813 else if (CONST_OK_FOR_K (delta
))
12814 output_asm_insn ("aghi\t%1,%2", op
);
12815 else if (CONST_OK_FOR_Os (delta
))
12816 output_asm_insn ("agfi\t%1,%2", op
);
12819 op
[6] = gen_label_rtx ();
12820 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
12824 /* Perform vcall adjustment. */
12827 if (DISP_IN_RANGE (vcall_offset
))
12829 output_asm_insn ("lg\t%4,0(%1)", op
);
12830 output_asm_insn ("ag\t%1,%3(%4)", op
);
12832 else if (CONST_OK_FOR_K (vcall_offset
))
12834 output_asm_insn ("lghi\t%4,%3", op
);
12835 output_asm_insn ("ag\t%4,0(%1)", op
);
12836 output_asm_insn ("ag\t%1,0(%4)", op
);
12838 else if (CONST_OK_FOR_Os (vcall_offset
))
12840 output_asm_insn ("lgfi\t%4,%3", op
);
12841 output_asm_insn ("ag\t%4,0(%1)", op
);
12842 output_asm_insn ("ag\t%1,0(%4)", op
);
12846 op
[7] = gen_label_rtx ();
12847 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
12848 output_asm_insn ("ag\t%4,0(%1)", op
);
12849 output_asm_insn ("ag\t%1,0(%4)", op
);
12853 /* Jump to target. */
12854 output_asm_insn ("jg\t%0", op
);
12856 /* Output literal pool if required. */
12859 output_asm_insn (".align\t4", op
);
12860 targetm
.asm_out
.internal_label (file
, "L",
12861 CODE_LABEL_NUMBER (op
[5]));
12865 targetm
.asm_out
.internal_label (file
, "L",
12866 CODE_LABEL_NUMBER (op
[6]));
12867 output_asm_insn (".long\t%2", op
);
12871 targetm
.asm_out
.internal_label (file
, "L",
12872 CODE_LABEL_NUMBER (op
[7]));
12873 output_asm_insn (".long\t%3", op
);
12878 /* Setup base pointer if required. */
12880 || (!DISP_IN_RANGE (delta
)
12881 && !CONST_OK_FOR_K (delta
)
12882 && !CONST_OK_FOR_Os (delta
))
12883 || (!DISP_IN_RANGE (delta
)
12884 && !CONST_OK_FOR_K (vcall_offset
)
12885 && !CONST_OK_FOR_Os (vcall_offset
)))
12887 op
[5] = gen_label_rtx ();
12888 output_asm_insn ("basr\t%4,0", op
);
12889 targetm
.asm_out
.internal_label (file
, "L",
12890 CODE_LABEL_NUMBER (op
[5]));
12893 /* Add DELTA to this pointer. */
12896 if (CONST_OK_FOR_J (delta
))
12897 output_asm_insn ("la\t%1,%2(%1)", op
);
12898 else if (DISP_IN_RANGE (delta
))
12899 output_asm_insn ("lay\t%1,%2(%1)", op
);
12900 else if (CONST_OK_FOR_K (delta
))
12901 output_asm_insn ("ahi\t%1,%2", op
);
12902 else if (CONST_OK_FOR_Os (delta
))
12903 output_asm_insn ("afi\t%1,%2", op
);
12906 op
[6] = gen_label_rtx ();
12907 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
12911 /* Perform vcall adjustment. */
12914 if (CONST_OK_FOR_J (vcall_offset
))
12916 output_asm_insn ("l\t%4,0(%1)", op
);
12917 output_asm_insn ("a\t%1,%3(%4)", op
);
12919 else if (DISP_IN_RANGE (vcall_offset
))
12921 output_asm_insn ("l\t%4,0(%1)", op
);
12922 output_asm_insn ("ay\t%1,%3(%4)", op
);
12924 else if (CONST_OK_FOR_K (vcall_offset
))
12926 output_asm_insn ("lhi\t%4,%3", op
);
12927 output_asm_insn ("a\t%4,0(%1)", op
);
12928 output_asm_insn ("a\t%1,0(%4)", op
);
12930 else if (CONST_OK_FOR_Os (vcall_offset
))
12932 output_asm_insn ("iilf\t%4,%3", op
);
12933 output_asm_insn ("a\t%4,0(%1)", op
);
12934 output_asm_insn ("a\t%1,0(%4)", op
);
12938 op
[7] = gen_label_rtx ();
12939 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
12940 output_asm_insn ("a\t%4,0(%1)", op
);
12941 output_asm_insn ("a\t%1,0(%4)", op
);
12944 /* We had to clobber the base pointer register.
12945 Re-setup the base pointer (with a different base). */
12946 op
[5] = gen_label_rtx ();
12947 output_asm_insn ("basr\t%4,0", op
);
12948 targetm
.asm_out
.internal_label (file
, "L",
12949 CODE_LABEL_NUMBER (op
[5]));
12952 /* Jump to target. */
12953 op
[8] = gen_label_rtx ();
12956 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
12957 else if (!nonlocal
)
12958 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12959 /* We cannot call through .plt, since .plt requires %r12 loaded. */
12960 else if (flag_pic
== 1)
12962 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12963 output_asm_insn ("l\t%4,%0(%4)", op
);
12965 else if (flag_pic
== 2)
12967 op
[9] = gen_rtx_REG (Pmode
, 0);
12968 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
12969 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12970 output_asm_insn ("ar\t%4,%9", op
);
12971 output_asm_insn ("l\t%4,0(%4)", op
);
12974 output_asm_insn ("br\t%4", op
);
12976 /* Output literal pool. */
12977 output_asm_insn (".align\t4", op
);
12979 if (nonlocal
&& flag_pic
== 2)
12980 output_asm_insn (".long\t%0", op
);
12983 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
12984 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
12987 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
12989 output_asm_insn (".long\t%0", op
);
12991 output_asm_insn (".long\t%0-%5", op
);
12995 targetm
.asm_out
.internal_label (file
, "L",
12996 CODE_LABEL_NUMBER (op
[6]));
12997 output_asm_insn (".long\t%2", op
);
13001 targetm
.asm_out
.internal_label (file
, "L",
13002 CODE_LABEL_NUMBER (op
[7]));
13003 output_asm_insn (".long\t%3", op
);
13006 final_end_function ();
13009 /* Output either an indirect jump or a an indirect call
13010 (RETURN_ADDR_REGNO != INVALID_REGNUM) with target register REGNO
13011 using a branch trampoline disabling branch target prediction. */
13014 s390_indirect_branch_via_thunk (unsigned int regno
,
13015 unsigned int return_addr_regno
,
13016 rtx comparison_operator
,
13017 enum s390_indirect_branch_type type
)
13019 enum s390_indirect_branch_option option
;
13021 if (type
== s390_indirect_branch_type_return
)
13023 if (s390_return_addr_from_memory ())
13024 option
= s390_opt_function_return_mem
;
13026 option
= s390_opt_function_return_reg
;
13028 else if (type
== s390_indirect_branch_type_jump
)
13029 option
= s390_opt_indirect_branch_jump
;
13030 else if (type
== s390_indirect_branch_type_call
)
13031 option
= s390_opt_indirect_branch_call
;
13033 gcc_unreachable ();
13035 if (TARGET_INDIRECT_BRANCH_TABLE
)
13039 ASM_GENERATE_INTERNAL_LABEL (label
,
13040 indirect_branch_table_label
[option
],
13041 indirect_branch_table_label_no
[option
]++);
13042 ASM_OUTPUT_LABEL (asm_out_file
, label
);
13045 if (return_addr_regno
!= INVALID_REGNUM
)
13047 gcc_assert (comparison_operator
== NULL_RTX
);
13048 fprintf (asm_out_file
, " \tbrasl\t%%r%d,", return_addr_regno
);
13052 fputs (" \tjg", asm_out_file
);
13053 if (comparison_operator
!= NULL_RTX
)
13054 print_operand (asm_out_file
, comparison_operator
, 'C');
13056 fputs ("\t", asm_out_file
);
13059 if (TARGET_CPU_Z10
)
13060 fprintf (asm_out_file
,
13061 TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL
"\n",
13064 fprintf (asm_out_file
,
13065 TARGET_INDIRECT_BRANCH_THUNK_NAME_EX
"\n",
13066 INDIRECT_BRANCH_THUNK_REGNUM
, regno
);
13068 if ((option
== s390_opt_indirect_branch_jump
13069 && cfun
->machine
->indirect_branch_jump
== indirect_branch_thunk
)
13070 || (option
== s390_opt_indirect_branch_call
13071 && cfun
->machine
->indirect_branch_call
== indirect_branch_thunk
)
13072 || (option
== s390_opt_function_return_reg
13073 && cfun
->machine
->function_return_reg
== indirect_branch_thunk
)
13074 || (option
== s390_opt_function_return_mem
13075 && cfun
->machine
->function_return_mem
== indirect_branch_thunk
))
13077 if (TARGET_CPU_Z10
)
13078 indirect_branch_z10thunk_mask
|= (1 << regno
);
13080 indirect_branch_prez10thunk_mask
|= (1 << regno
);
13084 /* Output an inline thunk for indirect jumps. EXECUTE_TARGET can
13085 either be an address register or a label pointing to the location
13086 of the jump instruction. */
13089 s390_indirect_branch_via_inline_thunk (rtx execute_target
)
13091 if (TARGET_INDIRECT_BRANCH_TABLE
)
13095 ASM_GENERATE_INTERNAL_LABEL (label
,
13096 indirect_branch_table_label
[s390_opt_indirect_branch_jump
],
13097 indirect_branch_table_label_no
[s390_opt_indirect_branch_jump
]++);
13098 ASM_OUTPUT_LABEL (asm_out_file
, label
);
13102 fputs ("\t.machinemode zarch\n", asm_out_file
);
13104 if (REG_P (execute_target
))
13105 fprintf (asm_out_file
, "\tex\t%%r0,0(%%r%d)\n", REGNO (execute_target
));
13107 output_asm_insn ("\texrl\t%%r0,%0", &execute_target
);
13110 fputs ("\t.machinemode esa\n", asm_out_file
);
13112 fputs ("0:\tj\t0b\n", asm_out_file
);
13116 s390_valid_pointer_mode (scalar_int_mode mode
)
13118 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
13121 /* Checks whether the given CALL_EXPR would use a caller
13122 saved register. This is used to decide whether sibling call
13123 optimization could be performed on the respective function
13127 s390_call_saved_register_used (tree call_expr
)
13129 CUMULATIVE_ARGS cum_v
;
13130 cumulative_args_t cum
;
13137 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
13138 cum
= pack_cumulative_args (&cum_v
);
13140 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
13142 parameter
= CALL_EXPR_ARG (call_expr
, i
);
13143 gcc_assert (parameter
);
13145 /* For an undeclared variable passed as parameter we will get
13146 an ERROR_MARK node here. */
13147 if (TREE_CODE (parameter
) == ERROR_MARK
)
13150 type
= TREE_TYPE (parameter
);
13153 mode
= TYPE_MODE (type
);
13156 /* We assume that in the target function all parameters are
13157 named. This only has an impact on vector argument register
13158 usage none of which is call-saved. */
13159 if (pass_by_reference (&cum_v
, mode
, type
, true))
13162 type
= build_pointer_type (type
);
13165 parm_rtx
= s390_function_arg (cum
, mode
, type
, true);
13167 s390_function_arg_advance (cum
, mode
, type
, true);
13172 if (REG_P (parm_rtx
))
13174 for (reg
= 0; reg
< REG_NREGS (parm_rtx
); reg
++)
13175 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
13179 if (GET_CODE (parm_rtx
) == PARALLEL
)
13183 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
13185 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
13187 gcc_assert (REG_P (r
));
13189 for (reg
= 0; reg
< REG_NREGS (r
); reg
++)
13190 if (!call_used_regs
[reg
+ REGNO (r
)])
13199 /* Return true if the given call expression can be
13200 turned into a sibling call.
13201 DECL holds the declaration of the function to be called whereas
13202 EXP is the call expression itself. */
13205 s390_function_ok_for_sibcall (tree decl
, tree exp
)
13207 /* The TPF epilogue uses register 1. */
13208 if (TARGET_TPF_PROFILING
)
13211 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
13212 which would have to be restored before the sibcall. */
13213 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
13216 /* The thunks for indirect branches require r1 if no exrl is
13217 available. r1 might not be available when doing a sibling
13219 if (TARGET_INDIRECT_BRANCH_NOBP_CALL
13224 /* Register 6 on s390 is available as an argument register but unfortunately
13225 "caller saved". This makes functions needing this register for arguments
13226 not suitable for sibcalls. */
13227 return !s390_call_saved_register_used (exp
);
13230 /* Return the fixed registers used for condition codes. */
13233 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
13236 *p2
= INVALID_REGNUM
;
13241 /* This function is used by the call expanders of the machine description.
13242 It emits the call insn itself together with the necessary operations
13243 to adjust the target address and returns the emitted insn.
13244 ADDR_LOCATION is the target address rtx
13245 TLS_CALL the location of the thread-local symbol
13246 RESULT_REG the register where the result of the call should be stored
13247 RETADDR_REG the register where the return address should be stored
13248 If this parameter is NULL_RTX the call is considered
13249 to be a sibling call. */
13252 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
13255 bool plt_call
= false;
13257 rtx vec
[4] = { NULL_RTX
};
13259 rtx
*call
= &vec
[0];
13260 rtx
*clobber_ret_reg
= &vec
[1];
13261 rtx
*use
= &vec
[2];
13262 rtx
*clobber_thunk_reg
= &vec
[3];
13265 /* Direct function calls need special treatment. */
13266 if (GET_CODE (addr_location
) == SYMBOL_REF
)
13268 /* When calling a global routine in PIC mode, we must
13269 replace the symbol itself with the PLT stub. */
13270 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
13272 if (TARGET_64BIT
|| retaddr_reg
!= NULL_RTX
)
13274 addr_location
= gen_rtx_UNSPEC (Pmode
,
13275 gen_rtvec (1, addr_location
),
13277 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
13281 /* For -fpic code the PLT entries might use r12 which is
13282 call-saved. Therefore we cannot do a sibcall when
13283 calling directly using a symbol ref. When reaching
13284 this point we decided (in s390_function_ok_for_sibcall)
13285 to do a sibcall for a function pointer but one of the
13286 optimizers was able to get rid of the function pointer
13287 by propagating the symbol ref into the call. This
13288 optimization is illegal for S/390 so we turn the direct
13289 call into a indirect call again. */
13290 addr_location
= force_reg (Pmode
, addr_location
);
13294 /* If it is already an indirect call or the code above moved the
13295 SYMBOL_REF to somewhere else make sure the address can be found in
13297 if (retaddr_reg
== NULL_RTX
13298 && GET_CODE (addr_location
) != SYMBOL_REF
13301 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
13302 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
13305 if (TARGET_INDIRECT_BRANCH_NOBP_CALL
13306 && GET_CODE (addr_location
) != SYMBOL_REF
13309 /* Indirect branch thunks require the target to be a single GPR. */
13310 addr_location
= force_reg (Pmode
, addr_location
);
13312 /* Without exrl the indirect branch thunks need an additional
13313 register for larl;ex */
13314 if (!TARGET_CPU_Z10
)
13316 *clobber_thunk_reg
= gen_rtx_REG (Pmode
, INDIRECT_BRANCH_THUNK_REGNUM
);
13317 *clobber_thunk_reg
= gen_rtx_CLOBBER (VOIDmode
, *clobber_thunk_reg
);
13321 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
13322 *call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
13324 if (result_reg
!= NULL_RTX
)
13325 *call
= gen_rtx_SET (result_reg
, *call
);
13327 if (retaddr_reg
!= NULL_RTX
)
13329 *clobber_ret_reg
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
13331 if (tls_call
!= NULL_RTX
)
13332 *use
= gen_rtx_USE (VOIDmode
, tls_call
);
13336 for (i
= 0; i
< 4; i
++)
13337 if (vec
[i
] != NULL_RTX
)
13345 v
= rtvec_alloc (elts
);
13346 for (i
= 0; i
< 4; i
++)
13347 if (vec
[i
] != NULL_RTX
)
13349 RTVEC_ELT (v
, e
) = vec
[i
];
13353 *call
= gen_rtx_PARALLEL (VOIDmode
, v
);
13356 insn
= emit_call_insn (*call
);
13358 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
13359 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
13361 /* s390_function_ok_for_sibcall should
13362 have denied sibcalls in this case. */
13363 gcc_assert (retaddr_reg
!= NULL_RTX
);
13364 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
13369 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
13372 s390_conditional_register_usage (void)
13378 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13379 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13381 fixed_regs
[BASE_REGNUM
] = 0;
13382 call_used_regs
[BASE_REGNUM
] = 0;
13383 fixed_regs
[RETURN_REGNUM
] = 0;
13384 call_used_regs
[RETURN_REGNUM
] = 0;
13387 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
13388 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
13392 call_used_regs
[FPR4_REGNUM
] = call_really_used_regs
[FPR4_REGNUM
] = 0;
13393 call_used_regs
[FPR6_REGNUM
] = call_really_used_regs
[FPR6_REGNUM
] = 0;
13396 if (TARGET_SOFT_FLOAT
)
13398 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
13399 call_used_regs
[i
] = fixed_regs
[i
] = 1;
13402 /* Disable v16 - v31 for non-vector target. */
13405 for (i
= VR16_REGNUM
; i
<= VR31_REGNUM
; i
++)
13406 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
13410 /* Corresponding function to eh_return expander. */
13412 static GTY(()) rtx s390_tpf_eh_return_symbol
;
13414 s390_emit_tpf_eh_return (rtx target
)
13419 if (!s390_tpf_eh_return_symbol
)
13420 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
13422 reg
= gen_rtx_REG (Pmode
, 2);
13423 orig_ra
= gen_rtx_REG (Pmode
, 3);
13425 emit_move_insn (reg
, target
);
13426 emit_move_insn (orig_ra
, get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
));
13427 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
13428 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
13429 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
13430 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), orig_ra
);
13432 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
13435 /* Rework the prologue/epilogue to avoid saving/restoring
13436 registers unnecessarily. */
13439 s390_optimize_prologue (void)
13441 rtx_insn
*insn
, *new_insn
, *next_insn
;
13443 /* Do a final recompute of the frame-related data. */
13444 s390_optimize_register_info ();
13446 /* If all special registers are in fact used, there's nothing we
13447 can do, so no point in walking the insn list. */
13449 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
13450 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
)
13453 /* Search for prologue/epilogue insns and replace them. */
13454 for (insn
= get_insns (); insn
; insn
= next_insn
)
13456 int first
, last
, off
;
13457 rtx set
, base
, offset
;
13460 next_insn
= NEXT_INSN (insn
);
13462 if (! NONJUMP_INSN_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
13465 pat
= PATTERN (insn
);
13467 /* Remove ldgr/lgdr instructions used for saving and restore
13468 GPRs if possible. */
13473 if (INSN_CODE (insn
) == CODE_FOR_stack_restore_from_fpr
)
13474 tmp_pat
= XVECEXP (pat
, 0, 0);
13476 if (GET_CODE (tmp_pat
) == SET
13477 && GET_MODE (SET_SRC (tmp_pat
)) == DImode
13478 && REG_P (SET_SRC (tmp_pat
))
13479 && REG_P (SET_DEST (tmp_pat
)))
13481 int src_regno
= REGNO (SET_SRC (tmp_pat
));
13482 int dest_regno
= REGNO (SET_DEST (tmp_pat
));
13486 if (!((GENERAL_REGNO_P (src_regno
)
13487 && FP_REGNO_P (dest_regno
))
13488 || (FP_REGNO_P (src_regno
)
13489 && GENERAL_REGNO_P (dest_regno
))))
13492 gpr_regno
= GENERAL_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
13493 fpr_regno
= FP_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
13495 /* GPR must be call-saved, FPR must be call-clobbered. */
13496 if (!call_really_used_regs
[fpr_regno
]
13497 || call_really_used_regs
[gpr_regno
])
13500 /* It must not happen that what we once saved in an FPR now
13501 needs a stack slot. */
13502 gcc_assert (cfun_gpr_save_slot (gpr_regno
) != SAVE_SLOT_STACK
);
13504 if (cfun_gpr_save_slot (gpr_regno
) == SAVE_SLOT_NONE
)
13506 remove_insn (insn
);
13512 if (GET_CODE (pat
) == PARALLEL
13513 && store_multiple_operation (pat
, VOIDmode
))
13515 set
= XVECEXP (pat
, 0, 0);
13516 first
= REGNO (SET_SRC (set
));
13517 last
= first
+ XVECLEN (pat
, 0) - 1;
13518 offset
= const0_rtx
;
13519 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
13520 off
= INTVAL (offset
);
13522 if (GET_CODE (base
) != REG
|| off
< 0)
13524 if (cfun_frame_layout
.first_save_gpr
!= -1
13525 && (cfun_frame_layout
.first_save_gpr
< first
13526 || cfun_frame_layout
.last_save_gpr
> last
))
13528 if (REGNO (base
) != STACK_POINTER_REGNUM
13529 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13531 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
13534 if (cfun_frame_layout
.first_save_gpr
!= -1)
13536 rtx s_pat
= save_gprs (base
,
13537 off
+ (cfun_frame_layout
.first_save_gpr
13538 - first
) * UNITS_PER_LONG
,
13539 cfun_frame_layout
.first_save_gpr
,
13540 cfun_frame_layout
.last_save_gpr
);
13541 new_insn
= emit_insn_before (s_pat
, insn
);
13542 INSN_ADDRESSES_NEW (new_insn
, -1);
13545 remove_insn (insn
);
13549 if (cfun_frame_layout
.first_save_gpr
== -1
13550 && GET_CODE (pat
) == SET
13551 && GENERAL_REG_P (SET_SRC (pat
))
13552 && GET_CODE (SET_DEST (pat
)) == MEM
)
13555 first
= REGNO (SET_SRC (set
));
13556 offset
= const0_rtx
;
13557 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
13558 off
= INTVAL (offset
);
13560 if (GET_CODE (base
) != REG
|| off
< 0)
13562 if (REGNO (base
) != STACK_POINTER_REGNUM
13563 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13566 remove_insn (insn
);
13570 if (GET_CODE (pat
) == PARALLEL
13571 && load_multiple_operation (pat
, VOIDmode
))
13573 set
= XVECEXP (pat
, 0, 0);
13574 first
= REGNO (SET_DEST (set
));
13575 last
= first
+ XVECLEN (pat
, 0) - 1;
13576 offset
= const0_rtx
;
13577 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
13578 off
= INTVAL (offset
);
13580 if (GET_CODE (base
) != REG
|| off
< 0)
13583 if (cfun_frame_layout
.first_restore_gpr
!= -1
13584 && (cfun_frame_layout
.first_restore_gpr
< first
13585 || cfun_frame_layout
.last_restore_gpr
> last
))
13587 if (REGNO (base
) != STACK_POINTER_REGNUM
13588 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13590 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
13593 if (cfun_frame_layout
.first_restore_gpr
!= -1)
13595 rtx rpat
= restore_gprs (base
,
13596 off
+ (cfun_frame_layout
.first_restore_gpr
13597 - first
) * UNITS_PER_LONG
,
13598 cfun_frame_layout
.first_restore_gpr
,
13599 cfun_frame_layout
.last_restore_gpr
);
13601 /* Remove REG_CFA_RESTOREs for registers that we no
13602 longer need to save. */
13603 REG_NOTES (rpat
) = REG_NOTES (insn
);
13604 for (rtx
*ptr
= ®_NOTES (rpat
); *ptr
; )
13605 if (REG_NOTE_KIND (*ptr
) == REG_CFA_RESTORE
13606 && ((int) REGNO (XEXP (*ptr
, 0))
13607 < cfun_frame_layout
.first_restore_gpr
))
13608 *ptr
= XEXP (*ptr
, 1);
13610 ptr
= &XEXP (*ptr
, 1);
13611 new_insn
= emit_insn_before (rpat
, insn
);
13612 RTX_FRAME_RELATED_P (new_insn
) = 1;
13613 INSN_ADDRESSES_NEW (new_insn
, -1);
13616 remove_insn (insn
);
13620 if (cfun_frame_layout
.first_restore_gpr
== -1
13621 && GET_CODE (pat
) == SET
13622 && GENERAL_REG_P (SET_DEST (pat
))
13623 && GET_CODE (SET_SRC (pat
)) == MEM
)
13626 first
= REGNO (SET_DEST (set
));
13627 offset
= const0_rtx
;
13628 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
13629 off
= INTVAL (offset
);
13631 if (GET_CODE (base
) != REG
|| off
< 0)
13634 if (REGNO (base
) != STACK_POINTER_REGNUM
13635 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13638 remove_insn (insn
);
13644 /* On z10 and later the dynamic branch prediction must see the
13645 backward jump within a certain windows. If not it falls back to
13646 the static prediction. This function rearranges the loop backward
13647 branch in a way which makes the static prediction always correct.
13648 The function returns true if it added an instruction. */
13650 s390_fix_long_loop_prediction (rtx_insn
*insn
)
13652 rtx set
= single_set (insn
);
13653 rtx code_label
, label_ref
;
13654 rtx_insn
*uncond_jump
;
13655 rtx_insn
*cur_insn
;
13659 /* This will exclude branch on count and branch on index patterns
13660 since these are correctly statically predicted. */
13662 || SET_DEST (set
) != pc_rtx
13663 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
13666 /* Skip conditional returns. */
13667 if (ANY_RETURN_P (XEXP (SET_SRC (set
), 1))
13668 && XEXP (SET_SRC (set
), 2) == pc_rtx
)
13671 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
13672 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
13674 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
13676 code_label
= XEXP (label_ref
, 0);
13678 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
13679 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
13680 || (INSN_ADDRESSES (INSN_UID (insn
))
13681 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
13684 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
13685 distance
< PREDICT_DISTANCE
- 6;
13686 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
13687 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
13690 rtx_code_label
*new_label
= gen_label_rtx ();
13691 uncond_jump
= emit_jump_insn_after (
13692 gen_rtx_SET (pc_rtx
,
13693 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
13695 emit_label_after (new_label
, uncond_jump
);
13697 tmp
= XEXP (SET_SRC (set
), 1);
13698 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
13699 XEXP (SET_SRC (set
), 2) = tmp
;
13700 INSN_CODE (insn
) = -1;
13702 XEXP (label_ref
, 0) = new_label
;
13703 JUMP_LABEL (insn
) = new_label
;
13704 JUMP_LABEL (uncond_jump
) = code_label
;
13709 /* Returns 1 if INSN reads the value of REG for purposes not related
13710 to addressing of memory, and 0 otherwise. */
13712 s390_non_addr_reg_read_p (rtx reg
, rtx_insn
*insn
)
13714 return reg_referenced_p (reg
, PATTERN (insn
))
13715 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
13718 /* Starting from INSN find_cond_jump looks downwards in the insn
13719 stream for a single jump insn which is the last user of the
13720 condition code set in INSN. */
13722 find_cond_jump (rtx_insn
*insn
)
13724 for (; insn
; insn
= NEXT_INSN (insn
))
13728 if (LABEL_P (insn
))
13731 if (!JUMP_P (insn
))
13733 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
13738 /* This will be triggered by a return. */
13739 if (GET_CODE (PATTERN (insn
)) != SET
)
13742 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
13743 ite
= SET_SRC (PATTERN (insn
));
13745 if (GET_CODE (ite
) != IF_THEN_ELSE
)
13748 cc
= XEXP (XEXP (ite
, 0), 0);
13749 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
13752 if (find_reg_note (insn
, REG_DEAD
, cc
))
13760 /* Swap the condition in COND and the operands in OP0 and OP1 so that
13761 the semantics does not change. If NULL_RTX is passed as COND the
13762 function tries to find the conditional jump starting with INSN. */
13764 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx_insn
*insn
)
13768 if (cond
== NULL_RTX
)
13770 rtx_insn
*jump
= find_cond_jump (NEXT_INSN (insn
));
13771 rtx set
= jump
? single_set (jump
) : NULL_RTX
;
13773 if (set
== NULL_RTX
)
13776 cond
= XEXP (SET_SRC (set
), 0);
13781 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
13784 /* On z10, instructions of the compare-and-branch family have the
13785 property to access the register occurring as second operand with
13786 its bits complemented. If such a compare is grouped with a second
13787 instruction that accesses the same register non-complemented, and
13788 if that register's value is delivered via a bypass, then the
13789 pipeline recycles, thereby causing significant performance decline.
13790 This function locates such situations and exchanges the two
13791 operands of the compare. The function return true whenever it
13794 s390_z10_optimize_cmp (rtx_insn
*insn
)
13796 rtx_insn
*prev_insn
, *next_insn
;
13797 bool insn_added_p
= false;
13798 rtx cond
, *op0
, *op1
;
13800 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
13802 /* Handle compare and branch and branch on count
13804 rtx pattern
= single_set (insn
);
13807 || SET_DEST (pattern
) != pc_rtx
13808 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
13811 cond
= XEXP (SET_SRC (pattern
), 0);
13812 op0
= &XEXP (cond
, 0);
13813 op1
= &XEXP (cond
, 1);
13815 else if (GET_CODE (PATTERN (insn
)) == SET
)
13819 /* Handle normal compare instructions. */
13820 src
= SET_SRC (PATTERN (insn
));
13821 dest
= SET_DEST (PATTERN (insn
));
13824 || !CC_REGNO_P (REGNO (dest
))
13825 || GET_CODE (src
) != COMPARE
)
13828 /* s390_swap_cmp will try to find the conditional
13829 jump when passing NULL_RTX as condition. */
13831 op0
= &XEXP (src
, 0);
13832 op1
= &XEXP (src
, 1);
13837 if (!REG_P (*op0
) || !REG_P (*op1
))
13840 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
13843 /* Swap the COMPARE arguments and its mask if there is a
13844 conflicting access in the previous insn. */
13845 prev_insn
= prev_active_insn (insn
);
13846 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
13847 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
13848 s390_swap_cmp (cond
, op0
, op1
, insn
);
13850 /* Check if there is a conflict with the next insn. If there
13851 was no conflict with the previous insn, then swap the
13852 COMPARE arguments and its mask. If we already swapped
13853 the operands, or if swapping them would cause a conflict
13854 with the previous insn, issue a NOP after the COMPARE in
13855 order to separate the two instuctions. */
13856 next_insn
= next_active_insn (insn
);
13857 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
13858 && s390_non_addr_reg_read_p (*op1
, next_insn
))
13860 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
13861 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
13863 if (REGNO (*op1
) == 0)
13864 emit_insn_after (gen_nop_lr1 (), insn
);
13866 emit_insn_after (gen_nop_lr0 (), insn
);
13867 insn_added_p
= true;
13870 s390_swap_cmp (cond
, op0
, op1
, insn
);
13872 return insn_added_p
;
13875 /* Number of INSNs to be scanned backward in the last BB of the loop
13876 and forward in the first BB of the loop. This usually should be a
13877 bit more than the number of INSNs which could go into one
13879 #define S390_OSC_SCAN_INSN_NUM 5
13881 /* Scan LOOP for static OSC collisions and return true if a osc_break
13882 should be issued for this loop. */
13884 s390_adjust_loop_scan_osc (struct loop
* loop
)
13887 HARD_REG_SET modregs
, newregs
;
13888 rtx_insn
*insn
, *store_insn
= NULL
;
13890 struct s390_address addr_store
, addr_load
;
13891 subrtx_iterator::array_type array
;
13894 CLEAR_HARD_REG_SET (modregs
);
13897 FOR_BB_INSNS_REVERSE (loop
->latch
, insn
)
13899 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
13903 if (insn_count
> S390_OSC_SCAN_INSN_NUM
)
13906 find_all_hard_reg_sets (insn
, &newregs
, true);
13907 IOR_HARD_REG_SET (modregs
, newregs
);
13909 set
= single_set (insn
);
13913 if (MEM_P (SET_DEST (set
))
13914 && s390_decompose_address (XEXP (SET_DEST (set
), 0), &addr_store
))
13921 if (store_insn
== NULL_RTX
)
13925 FOR_BB_INSNS (loop
->header
, insn
)
13927 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
13930 if (insn
== store_insn
)
13934 if (insn_count
> S390_OSC_SCAN_INSN_NUM
)
13937 find_all_hard_reg_sets (insn
, &newregs
, true);
13938 IOR_HARD_REG_SET (modregs
, newregs
);
13940 set
= single_set (insn
);
13944 /* An intermediate store disrupts static OSC checking
13946 if (MEM_P (SET_DEST (set
))
13947 && s390_decompose_address (XEXP (SET_DEST (set
), 0), NULL
))
13950 FOR_EACH_SUBRTX (iter
, array
, SET_SRC (set
), NONCONST
)
13952 && s390_decompose_address (XEXP (*iter
, 0), &addr_load
)
13953 && rtx_equal_p (addr_load
.base
, addr_store
.base
)
13954 && rtx_equal_p (addr_load
.indx
, addr_store
.indx
)
13955 && rtx_equal_p (addr_load
.disp
, addr_store
.disp
))
13957 if ((addr_load
.base
!= NULL_RTX
13958 && TEST_HARD_REG_BIT (modregs
, REGNO (addr_load
.base
)))
13959 || (addr_load
.indx
!= NULL_RTX
13960 && TEST_HARD_REG_BIT (modregs
, REGNO (addr_load
.indx
))))
13967 /* Look for adjustments which can be done on simple innermost
13970 s390_adjust_loops ()
13972 struct loop
*loop
= NULL
;
13975 compute_bb_for_insn ();
13977 /* Find the loops. */
13978 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
13980 FOR_EACH_LOOP (loop
, LI_ONLY_INNERMOST
)
13984 flow_loop_dump (loop
, dump_file
, NULL
, 0);
13985 fprintf (dump_file
, ";; OSC loop scan Loop: ");
13987 if (loop
->latch
== NULL
13988 || pc_set (BB_END (loop
->latch
)) == NULL_RTX
13989 || !s390_adjust_loop_scan_osc (loop
))
13993 if (loop
->latch
== NULL
)
13994 fprintf (dump_file
, " muliple backward jumps\n");
13997 fprintf (dump_file
, " header insn: %d latch insn: %d ",
13998 INSN_UID (BB_HEAD (loop
->header
)),
13999 INSN_UID (BB_END (loop
->latch
)));
14000 if (pc_set (BB_END (loop
->latch
)) == NULL_RTX
)
14001 fprintf (dump_file
, " loop does not end with jump\n");
14003 fprintf (dump_file
, " not instrumented\n");
14009 rtx_insn
*new_insn
;
14012 fprintf (dump_file
, " adding OSC break insn: ");
14013 new_insn
= emit_insn_before (gen_osc_break (),
14014 BB_END (loop
->latch
));
14015 INSN_ADDRESSES_NEW (new_insn
, -1);
14019 loop_optimizer_finalize ();
14021 df_finish_pass (false);
14024 /* Perform machine-dependent processing. */
14029 struct constant_pool
*pool
;
14031 int hw_before
, hw_after
;
14033 if (s390_tune
== PROCESSOR_2964_Z13
)
14034 s390_adjust_loops ();
14036 /* Make sure all splits have been performed; splits after
14037 machine_dependent_reorg might confuse insn length counts. */
14038 split_all_insns_noflow ();
14040 /* Install the main literal pool and the associated base
14041 register load insns. The literal pool might be > 4096 bytes in
14042 size, so that some of its elements cannot be directly accessed.
14044 To fix this, we split the single literal pool into multiple
14045 pool chunks, reloading the pool base register at various
14046 points throughout the function to ensure it always points to
14047 the pool chunk the following code expects. */
14049 /* Collect the literal pool. */
14050 pool
= s390_mainpool_start ();
14053 /* Finish up literal pool related changes. */
14054 s390_mainpool_finish (pool
);
14058 /* If literal pool overflowed, chunkify it. */
14059 pool
= s390_chunkify_start ();
14060 s390_chunkify_finish (pool
);
14063 /* Generate out-of-pool execute target insns. */
14064 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14069 label
= s390_execute_label (insn
);
14073 gcc_assert (label
!= const0_rtx
);
14075 target
= emit_label (XEXP (label
, 0));
14076 INSN_ADDRESSES_NEW (target
, -1);
14080 target
= emit_jump_insn (s390_execute_target (insn
));
14081 /* This is important in order to keep a table jump
14082 pointing at the jump table label. Only this makes it
14083 being recognized as table jump. */
14084 JUMP_LABEL (target
) = JUMP_LABEL (insn
);
14087 target
= emit_insn (s390_execute_target (insn
));
14088 INSN_ADDRESSES_NEW (target
, -1);
14091 /* Try to optimize prologue and epilogue further. */
14092 s390_optimize_prologue ();
14094 /* Walk over the insns and do some >=z10 specific changes. */
14095 if (s390_tune
>= PROCESSOR_2097_Z10
)
14098 bool insn_added_p
= false;
14100 /* The insn lengths and addresses have to be up to date for the
14101 following manipulations. */
14102 shorten_branches (get_insns ());
14104 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14106 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
14110 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
14112 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
14113 || GET_CODE (PATTERN (insn
)) == SET
)
14114 && s390_tune
== PROCESSOR_2097_Z10
)
14115 insn_added_p
|= s390_z10_optimize_cmp (insn
);
14118 /* Adjust branches if we added new instructions. */
14120 shorten_branches (get_insns ());
14123 s390_function_num_hotpatch_hw (current_function_decl
, &hw_before
, &hw_after
);
14128 /* Insert NOPs for hotpatching. */
14129 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14131 1. inside the area covered by debug information to allow setting
14132 breakpoints at the NOPs,
14133 2. before any insn which results in an asm instruction,
14134 3. before in-function labels to avoid jumping to the NOPs, for
14135 example as part of a loop,
14136 4. before any barrier in case the function is completely empty
14137 (__builtin_unreachable ()) and has neither internal labels nor
14140 if (active_insn_p (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
14142 /* Output a series of NOPs before the first active insn. */
14143 while (insn
&& hw_after
> 0)
14147 emit_insn_before (gen_nop_6_byte (), insn
);
14150 else if (hw_after
>= 2)
14152 emit_insn_before (gen_nop_4_byte (), insn
);
14157 emit_insn_before (gen_nop_2_byte (), insn
);
14164 /* Return true if INSN is a fp load insn writing register REGNO. */
14166 s390_fpload_toreg (rtx_insn
*insn
, unsigned int regno
)
14169 enum attr_type flag
= s390_safe_attr_type (insn
);
14171 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
14174 set
= single_set (insn
);
14176 if (set
== NULL_RTX
)
14179 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
14182 if (REGNO (SET_DEST (set
)) != regno
)
14188 /* This value describes the distance to be avoided between an
14189 arithmetic fp instruction and an fp load writing the same register.
14190 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
14191 fine but the exact value has to be avoided. Otherwise the FP
14192 pipeline will throw an exception causing a major penalty. */
14193 #define Z10_EARLYLOAD_DISTANCE 7
14195 /* Rearrange the ready list in order to avoid the situation described
14196 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
14197 moved to the very end of the ready list. */
14199 s390_z10_prevent_earlyload_conflicts (rtx_insn
**ready
, int *nready_p
)
14201 unsigned int regno
;
14202 int nready
= *nready_p
;
14207 enum attr_type flag
;
14210 /* Skip DISTANCE - 1 active insns. */
14211 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
14212 distance
> 0 && insn
!= NULL_RTX
;
14213 distance
--, insn
= prev_active_insn (insn
))
14214 if (CALL_P (insn
) || JUMP_P (insn
))
14217 if (insn
== NULL_RTX
)
14220 set
= single_set (insn
);
14222 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
14223 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
14226 flag
= s390_safe_attr_type (insn
);
14228 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
14231 regno
= REGNO (SET_DEST (set
));
14234 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
14241 memmove (&ready
[1], &ready
[0], sizeof (rtx_insn
*) * i
);
14245 /* Returns TRUE if BB is entered via a fallthru edge and all other
14246 incoming edges are less than likely. */
14248 s390_bb_fallthru_entry_likely (basic_block bb
)
14250 edge e
, fallthru_edge
;
14256 fallthru_edge
= find_fallthru_edge (bb
->preds
);
14257 if (!fallthru_edge
)
14260 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14261 if (e
!= fallthru_edge
14262 && e
->probability
>= profile_probability::likely ())
14268 struct s390_sched_state
14270 /* Number of insns in the group. */
14272 /* Execution side of the group. */
14274 /* Group can only hold two insns. */
14276 } s390_sched_state
;
14278 static struct s390_sched_state sched_state
= {0, 1, false};
14280 #define S390_SCHED_ATTR_MASK_CRACKED 0x1
14281 #define S390_SCHED_ATTR_MASK_EXPANDED 0x2
14282 #define S390_SCHED_ATTR_MASK_ENDGROUP 0x4
14283 #define S390_SCHED_ATTR_MASK_GROUPALONE 0x8
14284 #define S390_SCHED_ATTR_MASK_GROUPOFTWO 0x10
14286 static unsigned int
14287 s390_get_sched_attrmask (rtx_insn
*insn
)
14289 unsigned int mask
= 0;
14293 case PROCESSOR_2827_ZEC12
:
14294 if (get_attr_zEC12_cracked (insn
))
14295 mask
|= S390_SCHED_ATTR_MASK_CRACKED
;
14296 if (get_attr_zEC12_expanded (insn
))
14297 mask
|= S390_SCHED_ATTR_MASK_EXPANDED
;
14298 if (get_attr_zEC12_endgroup (insn
))
14299 mask
|= S390_SCHED_ATTR_MASK_ENDGROUP
;
14300 if (get_attr_zEC12_groupalone (insn
))
14301 mask
|= S390_SCHED_ATTR_MASK_GROUPALONE
;
14303 case PROCESSOR_2964_Z13
:
14304 if (get_attr_z13_cracked (insn
))
14305 mask
|= S390_SCHED_ATTR_MASK_CRACKED
;
14306 if (get_attr_z13_expanded (insn
))
14307 mask
|= S390_SCHED_ATTR_MASK_EXPANDED
;
14308 if (get_attr_z13_endgroup (insn
))
14309 mask
|= S390_SCHED_ATTR_MASK_ENDGROUP
;
14310 if (get_attr_z13_groupalone (insn
))
14311 mask
|= S390_SCHED_ATTR_MASK_GROUPALONE
;
14312 if (get_attr_z13_groupoftwo (insn
))
14313 mask
|= S390_SCHED_ATTR_MASK_GROUPOFTWO
;
14315 case PROCESSOR_3906_Z14
:
14316 if (get_attr_z14_cracked (insn
))
14317 mask
|= S390_SCHED_ATTR_MASK_CRACKED
;
14318 if (get_attr_z14_expanded (insn
))
14319 mask
|= S390_SCHED_ATTR_MASK_EXPANDED
;
14320 if (get_attr_z14_endgroup (insn
))
14321 mask
|= S390_SCHED_ATTR_MASK_ENDGROUP
;
14322 if (get_attr_z14_groupalone (insn
))
14323 mask
|= S390_SCHED_ATTR_MASK_GROUPALONE
;
14324 if (get_attr_z14_groupoftwo (insn
))
14325 mask
|= S390_SCHED_ATTR_MASK_GROUPOFTWO
;
14328 gcc_unreachable ();
14333 static unsigned int
14334 s390_get_unit_mask (rtx_insn
*insn
, int *units
)
14336 unsigned int mask
= 0;
14340 case PROCESSOR_2964_Z13
:
14342 if (get_attr_z13_unit_lsu (insn
))
14344 if (get_attr_z13_unit_fxa (insn
))
14346 if (get_attr_z13_unit_fxb (insn
))
14348 if (get_attr_z13_unit_vfu (insn
))
14351 case PROCESSOR_3906_Z14
:
14353 if (get_attr_z14_unit_lsu (insn
))
14355 if (get_attr_z14_unit_fxa (insn
))
14357 if (get_attr_z14_unit_fxb (insn
))
14359 if (get_attr_z14_unit_vfu (insn
))
14363 gcc_unreachable ();
14369 s390_is_fpd (rtx_insn
*insn
)
14371 if (insn
== NULL_RTX
)
14374 return get_attr_z13_unit_fpd (insn
) || get_attr_z14_unit_fpd (insn
);
14378 s390_is_fxd (rtx_insn
*insn
)
14380 if (insn
== NULL_RTX
)
14383 return get_attr_z13_unit_fxd (insn
) || get_attr_z14_unit_fxd (insn
);
14386 /* Returns TRUE if INSN is a long-running instruction. */
14388 s390_is_longrunning (rtx_insn
*insn
)
14390 if (insn
== NULL_RTX
)
14393 return s390_is_fxd (insn
) || s390_is_fpd (insn
);
14397 /* Return the scheduling score for INSN. The higher the score the
14398 better. The score is calculated from the OOO scheduling attributes
14399 of INSN and the scheduling state sched_state. */
14401 s390_sched_score (rtx_insn
*insn
)
14403 unsigned int mask
= s390_get_sched_attrmask (insn
);
14406 switch (sched_state
.group_state
)
14409 /* Try to put insns into the first slot which would otherwise
14411 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) != 0
14412 || (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) != 0)
14414 if ((mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) != 0)
14418 /* Prefer not cracked insns while trying to put together a
14420 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) == 0
14421 && (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) == 0
14422 && (mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) == 0)
14424 if ((mask
& S390_SCHED_ATTR_MASK_ENDGROUP
) == 0)
14426 /* If we are in a group of two already, try to schedule another
14427 group-of-two insn to avoid shortening another group. */
14428 if (sched_state
.group_of_two
14429 && (mask
& S390_SCHED_ATTR_MASK_GROUPOFTWO
) != 0)
14433 /* Prefer not cracked insns while trying to put together a
14435 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) == 0
14436 && (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) == 0
14437 && (mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) == 0)
14439 /* Prefer endgroup insns in the last slot. */
14440 if ((mask
& S390_SCHED_ATTR_MASK_ENDGROUP
) != 0)
14442 /* Try to avoid group-of-two insns in the last slot as they will
14443 shorten this group as well as the next one. */
14444 if ((mask
& S390_SCHED_ATTR_MASK_GROUPOFTWO
) != 0)
14445 score
= MAX (0, score
- 15);
14449 if (s390_tune
>= PROCESSOR_2964_Z13
)
14452 unsigned unit_mask
, m
= 1;
14454 unit_mask
= s390_get_unit_mask (insn
, &units
);
14455 gcc_assert (units
<= MAX_SCHED_UNITS
);
14457 /* Add a score in range 0..MAX_SCHED_MIX_SCORE depending on how long
14458 ago the last insn of this unit type got scheduled. This is
14459 supposed to help providing a proper instruction mix to the
14461 for (i
= 0; i
< units
; i
++, m
<<= 1)
14463 score
+= (last_scheduled_unit_distance
[i
][sched_state
.side
]
14464 * MAX_SCHED_MIX_SCORE
/ MAX_SCHED_MIX_DISTANCE
);
14466 int other_side
= 1 - sched_state
.side
;
14468 /* Try to delay long-running insns when side is busy. */
14469 if (s390_is_longrunning (insn
))
14471 if (s390_is_fxd (insn
))
14473 if (fxd_longrunning
[sched_state
.side
]
14474 && fxd_longrunning
[other_side
]
14475 <= fxd_longrunning
[sched_state
.side
])
14476 score
= MAX (0, score
- 10);
14478 else if (fxd_longrunning
[other_side
]
14479 >= fxd_longrunning
[sched_state
.side
])
14483 if (s390_is_fpd (insn
))
14485 if (fpd_longrunning
[sched_state
.side
]
14486 && fpd_longrunning
[other_side
]
14487 <= fpd_longrunning
[sched_state
.side
])
14488 score
= MAX (0, score
- 10);
14490 else if (fpd_longrunning
[other_side
]
14491 >= fpd_longrunning
[sched_state
.side
])
14500 /* This function is called via hook TARGET_SCHED_REORDER before
14501 issuing one insn from list READY which contains *NREADYP entries.
14502 For target z10 it reorders load instructions to avoid early load
14503 conflicts in the floating point pipeline */
14505 s390_sched_reorder (FILE *file
, int verbose
,
14506 rtx_insn
**ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
14508 if (s390_tune
== PROCESSOR_2097_Z10
14509 && reload_completed
14511 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
14513 if (s390_tune
>= PROCESSOR_2827_ZEC12
14514 && reload_completed
14518 int last_index
= *nreadyp
- 1;
14519 int max_index
= -1;
14520 int max_score
= -1;
14523 /* Just move the insn with the highest score to the top (the
14524 end) of the list. A full sort is not needed since a conflict
14525 in the hazard recognition cannot happen. So the top insn in
14526 the ready list will always be taken. */
14527 for (i
= last_index
; i
>= 0; i
--)
14531 if (recog_memoized (ready
[i
]) < 0)
14534 score
= s390_sched_score (ready
[i
]);
14535 if (score
> max_score
)
14542 if (max_index
!= -1)
14544 if (max_index
!= last_index
)
14546 tmp
= ready
[max_index
];
14547 ready
[max_index
] = ready
[last_index
];
14548 ready
[last_index
] = tmp
;
14552 ";;\t\tBACKEND: move insn %d to the top of list\n",
14553 INSN_UID (ready
[last_index
]));
14555 else if (verbose
> 5)
14557 ";;\t\tBACKEND: best insn %d already on top\n",
14558 INSN_UID (ready
[last_index
]));
14563 fprintf (file
, "ready list ooo attributes - sched state: %d\n",
14564 sched_state
.group_state
);
14566 for (i
= last_index
; i
>= 0; i
--)
14568 unsigned int sched_mask
;
14569 rtx_insn
*insn
= ready
[i
];
14571 if (recog_memoized (insn
) < 0)
14574 sched_mask
= s390_get_sched_attrmask (insn
);
14575 fprintf (file
, ";;\t\tBACKEND: insn %d score: %d: ",
14577 s390_sched_score (insn
));
14578 #define PRINT_SCHED_ATTR(M, ATTR) fprintf (file, "%s ",\
14579 ((M) & sched_mask) ? #ATTR : "");
14580 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_CRACKED
, cracked
);
14581 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_EXPANDED
, expanded
);
14582 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_ENDGROUP
, endgroup
);
14583 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_GROUPALONE
, groupalone
);
14584 #undef PRINT_SCHED_ATTR
14585 if (s390_tune
>= PROCESSOR_2964_Z13
)
14587 unsigned int unit_mask
, m
= 1;
14590 unit_mask
= s390_get_unit_mask (insn
, &units
);
14591 fprintf (file
, "(units:");
14592 for (j
= 0; j
< units
; j
++, m
<<= 1)
14594 fprintf (file
, " u%d", j
);
14595 fprintf (file
, ")");
14597 fprintf (file
, "\n");
14602 return s390_issue_rate ();
14606 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
14607 the scheduler has issued INSN. It stores the last issued insn into
14608 last_scheduled_insn in order to make it available for
14609 s390_sched_reorder. */
14611 s390_sched_variable_issue (FILE *file
, int verbose
, rtx_insn
*insn
, int more
)
14613 last_scheduled_insn
= insn
;
14615 bool ends_group
= false;
14617 if (s390_tune
>= PROCESSOR_2827_ZEC12
14618 && reload_completed
14619 && recog_memoized (insn
) >= 0)
14621 unsigned int mask
= s390_get_sched_attrmask (insn
);
14623 if ((mask
& S390_SCHED_ATTR_MASK_GROUPOFTWO
) != 0)
14624 sched_state
.group_of_two
= true;
14626 /* If this is a group-of-two insn, we actually ended the last group
14627 and this insn is the first one of the new group. */
14628 if (sched_state
.group_state
== 2 && sched_state
.group_of_two
)
14630 sched_state
.side
= sched_state
.side
? 0 : 1;
14631 sched_state
.group_state
= 0;
14634 /* Longrunning and side bookkeeping. */
14635 for (int i
= 0; i
< 2; i
++)
14637 fxd_longrunning
[i
] = MAX (0, fxd_longrunning
[i
] - 1);
14638 fpd_longrunning
[i
] = MAX (0, fpd_longrunning
[i
] - 1);
14641 unsigned latency
= insn_default_latency (insn
);
14642 if (s390_is_longrunning (insn
))
14644 if (s390_is_fxd (insn
))
14645 fxd_longrunning
[sched_state
.side
] = latency
;
14647 fpd_longrunning
[sched_state
.side
] = latency
;
14650 if (s390_tune
>= PROCESSOR_2964_Z13
)
14653 unsigned unit_mask
, m
= 1;
14655 unit_mask
= s390_get_unit_mask (insn
, &units
);
14656 gcc_assert (units
<= MAX_SCHED_UNITS
);
14658 for (i
= 0; i
< units
; i
++, m
<<= 1)
14660 last_scheduled_unit_distance
[i
][sched_state
.side
] = 0;
14661 else if (last_scheduled_unit_distance
[i
][sched_state
.side
]
14662 < MAX_SCHED_MIX_DISTANCE
)
14663 last_scheduled_unit_distance
[i
][sched_state
.side
]++;
14666 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) != 0
14667 || (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) != 0
14668 || (mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) != 0
14669 || (mask
& S390_SCHED_ATTR_MASK_ENDGROUP
) != 0)
14671 sched_state
.group_state
= 0;
14676 switch (sched_state
.group_state
)
14679 sched_state
.group_state
++;
14682 sched_state
.group_state
++;
14683 if (sched_state
.group_of_two
)
14685 sched_state
.group_state
= 0;
14690 sched_state
.group_state
++;
14698 unsigned int sched_mask
;
14700 sched_mask
= s390_get_sched_attrmask (insn
);
14702 fprintf (file
, ";;\t\tBACKEND: insn %d: ", INSN_UID (insn
));
14703 #define PRINT_SCHED_ATTR(M, ATTR) fprintf (file, "%s ", ((M) & sched_mask) ? #ATTR : "");
14704 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_CRACKED
, cracked
);
14705 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_EXPANDED
, expanded
);
14706 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_ENDGROUP
, endgroup
);
14707 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_GROUPALONE
, groupalone
);
14708 #undef PRINT_SCHED_ATTR
14710 if (s390_tune
>= PROCESSOR_2964_Z13
)
14712 unsigned int unit_mask
, m
= 1;
14715 unit_mask
= s390_get_unit_mask (insn
, &units
);
14716 fprintf (file
, "(units:");
14717 for (j
= 0; j
< units
; j
++, m
<<= 1)
14719 fprintf (file
, " %d", j
);
14720 fprintf (file
, ")");
14722 fprintf (file
, " sched state: %d\n", sched_state
.group_state
);
14724 if (s390_tune
>= PROCESSOR_2964_Z13
)
14728 s390_get_unit_mask (insn
, &units
);
14730 fprintf (file
, ";;\t\tBACKEND: units on this side unused for: ");
14731 for (j
= 0; j
< units
; j
++)
14732 fprintf (file
, "%d:%d ", j
,
14733 last_scheduled_unit_distance
[j
][sched_state
.side
]);
14734 fprintf (file
, "\n");
14738 /* If this insn ended a group, the next will be on the other side. */
14741 sched_state
.group_state
= 0;
14742 sched_state
.side
= sched_state
.side
? 0 : 1;
14743 sched_state
.group_of_two
= false;
14747 if (GET_CODE (PATTERN (insn
)) != USE
14748 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
14755 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
14756 int verbose ATTRIBUTE_UNUSED
,
14757 int max_ready ATTRIBUTE_UNUSED
)
14759 /* If the next basic block is most likely entered via a fallthru edge
14760 we keep the last sched state. Otherwise we start a new group.
14761 The scheduler traverses basic blocks in "instruction stream" ordering
14762 so if we see a fallthru edge here, sched_state will be of its
14765 current_sched_info->prev_head is the insn before the first insn of the
14766 block of insns to be scheduled.
14768 rtx_insn
*insn
= current_sched_info
->prev_head
14769 ? NEXT_INSN (current_sched_info
->prev_head
) : NULL
;
14770 basic_block bb
= insn
? BLOCK_FOR_INSN (insn
) : NULL
;
14771 if (s390_tune
< PROCESSOR_2964_Z13
|| !s390_bb_fallthru_entry_likely (bb
))
14773 last_scheduled_insn
= NULL
;
14774 memset (last_scheduled_unit_distance
, 0,
14775 MAX_SCHED_UNITS
* NUM_SIDES
* sizeof (int));
14776 sched_state
.group_state
= 0;
14777 sched_state
.group_of_two
= false;
14781 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
14782 a new number struct loop *loop should be unrolled if tuned for cpus with
14783 a built-in stride prefetcher.
14784 The loop is analyzed for memory accesses by calling check_dpu for
14785 each rtx of the loop. Depending on the loop_depth and the amount of
14786 memory accesses a new number <=nunroll is returned to improve the
14787 behavior of the hardware prefetch unit. */
14789 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
14794 unsigned mem_count
= 0;
14796 if (s390_tune
< PROCESSOR_2097_Z10
)
14799 /* Count the number of memory references within the loop body. */
14800 bbs
= get_loop_body (loop
);
14801 subrtx_iterator::array_type array
;
14802 for (i
= 0; i
< loop
->num_nodes
; i
++)
14803 FOR_BB_INSNS (bbs
[i
], insn
)
14804 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
14808 /* The runtime of small loops with memory block operations
14809 will be determined by the memory operation. Doing
14810 unrolling doesn't help here. Measurements to confirm
14811 this where only done on recent CPU levels. So better do
14812 not change anything for older CPUs. */
14813 if (s390_tune
>= PROCESSOR_2964_Z13
14814 && loop
->ninsns
<= BLOCK_MEM_OPS_LOOP_INSNS
14815 && ((set
= single_set (insn
)) != NULL_RTX
)
14816 && ((GET_MODE (SET_DEST (set
)) == BLKmode
14817 && (GET_MODE (SET_SRC (set
)) == BLKmode
14818 || SET_SRC (set
) == const0_rtx
))
14819 || (GET_CODE (SET_SRC (set
)) == COMPARE
14820 && GET_MODE (XEXP (SET_SRC (set
), 0)) == BLKmode
14821 && GET_MODE (XEXP (SET_SRC (set
), 1)) == BLKmode
)))
14824 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
14830 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
14831 if (mem_count
== 0)
14834 switch (loop_depth(loop
))
14837 return MIN (nunroll
, 28 / mem_count
);
14839 return MIN (nunroll
, 22 / mem_count
);
14841 return MIN (nunroll
, 16 / mem_count
);
14845 /* Restore the current options. This is a hook function and also called
14849 s390_function_specific_restore (struct gcc_options
*opts
,
14850 struct cl_target_option
*ptr ATTRIBUTE_UNUSED
)
14852 opts
->x_s390_cost_pointer
= (long)processor_table
[opts
->x_s390_tune
].cost
;
14856 s390_default_align (struct gcc_options
*opts
)
14858 /* Set the default function alignment to 16 in order to get rid of
14859 some unwanted performance effects. */
14860 if (opts
->x_flag_align_functions
&& !opts
->x_str_align_functions
14861 && opts
->x_s390_tune
>= PROCESSOR_2964_Z13
)
14862 opts
->x_str_align_functions
= "16";
14866 s390_override_options_after_change (void)
14868 s390_default_align (&global_options
);
14872 s390_option_override_internal (struct gcc_options
*opts
,
14873 const struct gcc_options
*opts_set
)
14875 /* Architecture mode defaults according to ABI. */
14876 if (!(opts_set
->x_target_flags
& MASK_ZARCH
))
14879 opts
->x_target_flags
|= MASK_ZARCH
;
14881 opts
->x_target_flags
&= ~MASK_ZARCH
;
14884 /* Set the march default in case it hasn't been specified on cmdline. */
14885 if (!opts_set
->x_s390_arch
)
14886 opts
->x_s390_arch
= PROCESSOR_2064_Z900
;
14888 opts
->x_s390_arch_flags
= processor_flags_table
[(int) opts
->x_s390_arch
];
14890 /* Determine processor to tune for. */
14891 if (!opts_set
->x_s390_tune
)
14892 opts
->x_s390_tune
= opts
->x_s390_arch
;
14894 opts
->x_s390_tune_flags
= processor_flags_table
[opts
->x_s390_tune
];
14896 /* Sanity checks. */
14897 if (opts
->x_s390_arch
== PROCESSOR_NATIVE
14898 || opts
->x_s390_tune
== PROCESSOR_NATIVE
)
14899 gcc_unreachable ();
14900 if (TARGET_64BIT
&& !TARGET_ZARCH_P (opts
->x_target_flags
))
14901 error ("64-bit ABI not supported in ESA/390 mode");
14903 if (opts
->x_s390_indirect_branch
== indirect_branch_thunk_inline
14904 || opts
->x_s390_indirect_branch_call
== indirect_branch_thunk_inline
14905 || opts
->x_s390_function_return
== indirect_branch_thunk_inline
14906 || opts
->x_s390_function_return_reg
== indirect_branch_thunk_inline
14907 || opts
->x_s390_function_return_mem
== indirect_branch_thunk_inline
)
14908 error ("thunk-inline is only supported with %<-mindirect-branch-jump%>");
14910 if (opts
->x_s390_indirect_branch
!= indirect_branch_keep
)
14912 if (!opts_set
->x_s390_indirect_branch_call
)
14913 opts
->x_s390_indirect_branch_call
= opts
->x_s390_indirect_branch
;
14915 if (!opts_set
->x_s390_indirect_branch_jump
)
14916 opts
->x_s390_indirect_branch_jump
= opts
->x_s390_indirect_branch
;
14919 if (opts
->x_s390_function_return
!= indirect_branch_keep
)
14921 if (!opts_set
->x_s390_function_return_reg
)
14922 opts
->x_s390_function_return_reg
= opts
->x_s390_function_return
;
14924 if (!opts_set
->x_s390_function_return_mem
)
14925 opts
->x_s390_function_return_mem
= opts
->x_s390_function_return
;
14928 /* Enable hardware transactions if available and not explicitly
14929 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
14930 if (!TARGET_OPT_HTM_P (opts_set
->x_target_flags
))
14932 if (TARGET_CPU_HTM_P (opts
) && TARGET_ZARCH_P (opts
->x_target_flags
))
14933 opts
->x_target_flags
|= MASK_OPT_HTM
;
14935 opts
->x_target_flags
&= ~MASK_OPT_HTM
;
14938 if (TARGET_OPT_VX_P (opts_set
->x_target_flags
))
14940 if (TARGET_OPT_VX_P (opts
->x_target_flags
))
14942 if (!TARGET_CPU_VX_P (opts
))
14943 error ("hardware vector support not available on %s",
14944 processor_table
[(int)opts
->x_s390_arch
].name
);
14945 if (TARGET_SOFT_FLOAT_P (opts
->x_target_flags
))
14946 error ("hardware vector support not available with "
14947 "%<-msoft-float%>");
14952 if (TARGET_CPU_VX_P (opts
))
14953 /* Enable vector support if available and not explicitly disabled
14954 by user. E.g. with -m31 -march=z13 -mzarch */
14955 opts
->x_target_flags
|= MASK_OPT_VX
;
14957 opts
->x_target_flags
&= ~MASK_OPT_VX
;
14960 /* Use hardware DFP if available and not explicitly disabled by
14961 user. E.g. with -m31 -march=z10 -mzarch */
14962 if (!TARGET_HARD_DFP_P (opts_set
->x_target_flags
))
14964 if (TARGET_DFP_P (opts
))
14965 opts
->x_target_flags
|= MASK_HARD_DFP
;
14967 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
14970 if (TARGET_HARD_DFP_P (opts
->x_target_flags
) && !TARGET_DFP_P (opts
))
14972 if (TARGET_HARD_DFP_P (opts_set
->x_target_flags
))
14974 if (!TARGET_CPU_DFP_P (opts
))
14975 error ("hardware decimal floating point instructions"
14976 " not available on %s",
14977 processor_table
[(int)opts
->x_s390_arch
].name
);
14978 if (!TARGET_ZARCH_P (opts
->x_target_flags
))
14979 error ("hardware decimal floating point instructions"
14980 " not available in ESA/390 mode");
14983 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
14986 if (TARGET_SOFT_FLOAT_P (opts_set
->x_target_flags
)
14987 && TARGET_SOFT_FLOAT_P (opts
->x_target_flags
))
14989 if (TARGET_HARD_DFP_P (opts_set
->x_target_flags
)
14990 && TARGET_HARD_DFP_P (opts
->x_target_flags
))
14991 error ("%<-mhard-dfp%> can%'t be used in conjunction with "
14992 "%<-msoft-float%>");
14994 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
14997 if (TARGET_BACKCHAIN_P (opts
->x_target_flags
)
14998 && TARGET_PACKED_STACK_P (opts
->x_target_flags
)
14999 && TARGET_HARD_FLOAT_P (opts
->x_target_flags
))
15000 error ("%<-mbackchain%> %<-mpacked-stack%> %<-mhard-float%> are not "
15001 "supported in combination");
15003 if (opts
->x_s390_stack_size
)
15005 if (opts
->x_s390_stack_guard
>= opts
->x_s390_stack_size
)
15006 error ("stack size must be greater than the stack guard value");
15007 else if (opts
->x_s390_stack_size
> 1 << 16)
15008 error ("stack size must not be greater than 64k");
15010 else if (opts
->x_s390_stack_guard
)
15011 error ("%<-mstack-guard%> implies use of %<-mstack-size%>");
15013 /* Our implementation of the stack probe requires the probe interval
15014 to be used as displacement in an address operand. The maximum
15015 probe interval currently is 64k. This would exceed short
15016 displacements. Trim that value down to 4k if that happens. This
15017 might result in too many probes being generated only on the
15018 oldest supported machine level z900. */
15019 if (!DISP_IN_RANGE ((1 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
))))
15020 set_param_value ("stack-clash-protection-probe-interval", 12,
15021 opts
->x_param_values
,
15022 opts_set
->x_param_values
);
15024 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
15025 if (!TARGET_LONG_DOUBLE_128_P (opts_set
->x_target_flags
))
15026 opts
->x_target_flags
|= MASK_LONG_DOUBLE_128
;
15029 if (opts
->x_s390_tune
>= PROCESSOR_2097_Z10
)
15031 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
15032 opts
->x_param_values
,
15033 opts_set
->x_param_values
);
15034 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
15035 opts
->x_param_values
,
15036 opts_set
->x_param_values
);
15037 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
15038 opts
->x_param_values
,
15039 opts_set
->x_param_values
);
15040 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
15041 opts
->x_param_values
,
15042 opts_set
->x_param_values
);
15045 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
15046 opts
->x_param_values
,
15047 opts_set
->x_param_values
);
15048 /* values for loop prefetching */
15049 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
15050 opts
->x_param_values
,
15051 opts_set
->x_param_values
);
15052 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
15053 opts
->x_param_values
,
15054 opts_set
->x_param_values
);
15055 /* s390 has more than 2 levels and the size is much larger. Since
15056 we are always running virtualized assume that we only get a small
15057 part of the caches above l1. */
15058 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
15059 opts
->x_param_values
,
15060 opts_set
->x_param_values
);
15061 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
15062 opts
->x_param_values
,
15063 opts_set
->x_param_values
);
15064 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
15065 opts
->x_param_values
,
15066 opts_set
->x_param_values
);
15068 /* Use the alternative scheduling-pressure algorithm by default. */
15069 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
15070 opts
->x_param_values
,
15071 opts_set
->x_param_values
);
15073 maybe_set_param_value (PARAM_MIN_VECT_LOOP_BOUND
, 2,
15074 opts
->x_param_values
,
15075 opts_set
->x_param_values
);
15077 /* Use aggressive inlining parameters. */
15078 if (opts
->x_s390_tune
>= PROCESSOR_2964_Z13
)
15080 maybe_set_param_value (PARAM_INLINE_MIN_SPEEDUP
, 2,
15081 opts
->x_param_values
,
15082 opts_set
->x_param_values
);
15084 maybe_set_param_value (PARAM_MAX_INLINE_INSNS_AUTO
, 80,
15085 opts
->x_param_values
,
15086 opts_set
->x_param_values
);
15089 /* Set the default alignment. */
15090 s390_default_align (opts
);
15092 /* Call target specific restore function to do post-init work. At the moment,
15093 this just sets opts->x_s390_cost_pointer. */
15094 s390_function_specific_restore (opts
, NULL
);
15096 /* Check whether -mfentry is supported. It cannot be used in 31-bit mode,
15097 because 31-bit PLT stubs assume that %r12 contains GOT address, which is
15098 not the case when the code runs before the prolog. */
15099 if (opts
->x_flag_fentry
&& !TARGET_64BIT
)
15100 error ("%<-mfentry%> is supported only for 64-bit CPUs");
15104 s390_option_override (void)
15107 cl_deferred_option
*opt
;
15108 vec
<cl_deferred_option
> *v
=
15109 (vec
<cl_deferred_option
> *) s390_deferred_options
;
15112 FOR_EACH_VEC_ELT (*v
, i
, opt
)
15114 switch (opt
->opt_index
)
15116 case OPT_mhotpatch_
:
15120 char *s
= strtok (ASTRDUP (opt
->arg
), ",");
15121 char *t
= strtok (NULL
, "\0");
15125 val1
= integral_argument (s
);
15126 val2
= integral_argument (t
);
15133 if (val1
== -1 || val2
== -1)
15135 /* argument is not a plain number */
15136 error ("arguments to %qs should be non-negative integers",
15140 else if (val1
> s390_hotpatch_hw_max
15141 || val2
> s390_hotpatch_hw_max
)
15143 error ("argument to %qs is too large (max. %d)",
15144 "-mhotpatch=n,m", s390_hotpatch_hw_max
);
15147 s390_hotpatch_hw_before_label
= val1
;
15148 s390_hotpatch_hw_after_label
= val2
;
15152 gcc_unreachable ();
15156 /* Set up function hooks. */
15157 init_machine_status
= s390_init_machine_status
;
15159 s390_option_override_internal (&global_options
, &global_options_set
);
15161 /* Save the initial options in case the user does function specific
15163 target_option_default_node
= build_target_option_node (&global_options
);
15164 target_option_current_node
= target_option_default_node
;
15166 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
15167 requires the arch flags to be evaluated already. Since prefetching
15168 is beneficial on s390, we enable it if available. */
15169 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
15170 flag_prefetch_loop_arrays
= 1;
15172 if (!s390_pic_data_is_text_relative
&& !flag_pic
)
15173 error ("%<-mno-pic-data-is-text-relative%> cannot be used without "
15174 "%<-fpic%>/%<-fPIC%>");
15178 /* Don't emit DWARF3/4 unless specifically selected. The TPF
15179 debuggers do not yet support DWARF 3/4. */
15180 if (!global_options_set
.x_dwarf_strict
)
15182 if (!global_options_set
.x_dwarf_version
)
15187 #if S390_USE_TARGET_ATTRIBUTE
15188 /* Inner function to process the attribute((target(...))), take an argument and
15189 set the current options from the argument. If we have a list, recursively go
15193 s390_valid_target_attribute_inner_p (tree args
,
15194 struct gcc_options
*opts
,
15195 struct gcc_options
*new_opts_set
,
15201 #define S390_ATTRIB(S,O,A) { S, sizeof (S)-1, O, A, 0 }
15202 #define S390_PRAGMA(S,O,A) { S, sizeof (S)-1, O, A, 1 }
15203 static const struct
15205 const char *string
;
15209 int only_as_pragma
;
15212 S390_ATTRIB ("arch=", OPT_march_
, 1),
15213 S390_ATTRIB ("tune=", OPT_mtune_
, 1),
15214 /* uinteger options */
15215 S390_ATTRIB ("stack-guard=", OPT_mstack_guard_
, 1),
15216 S390_ATTRIB ("stack-size=", OPT_mstack_size_
, 1),
15217 S390_ATTRIB ("branch-cost=", OPT_mbranch_cost_
, 1),
15218 S390_ATTRIB ("warn-framesize=", OPT_mwarn_framesize_
, 1),
15220 S390_ATTRIB ("backchain", OPT_mbackchain
, 0),
15221 S390_ATTRIB ("hard-dfp", OPT_mhard_dfp
, 0),
15222 S390_ATTRIB ("hard-float", OPT_mhard_float
, 0),
15223 S390_ATTRIB ("htm", OPT_mhtm
, 0),
15224 S390_ATTRIB ("vx", OPT_mvx
, 0),
15225 S390_ATTRIB ("packed-stack", OPT_mpacked_stack
, 0),
15226 S390_ATTRIB ("small-exec", OPT_msmall_exec
, 0),
15227 S390_ATTRIB ("soft-float", OPT_msoft_float
, 0),
15228 S390_ATTRIB ("mvcle", OPT_mmvcle
, 0),
15229 S390_PRAGMA ("zvector", OPT_mzvector
, 0),
15230 /* boolean options */
15231 S390_ATTRIB ("warn-dynamicstack", OPT_mwarn_dynamicstack
, 0),
15236 /* If this is a list, recurse to get the options. */
15237 if (TREE_CODE (args
) == TREE_LIST
)
15240 int num_pragma_values
;
15243 /* Note: attribs.c:decl_attributes prepends the values from
15244 current_target_pragma to the list of target attributes. To determine
15245 whether we're looking at a value of the attribute or the pragma we
15246 assume that the first [list_length (current_target_pragma)] values in
15247 the list are the values from the pragma. */
15248 num_pragma_values
= (!force_pragma
&& current_target_pragma
!= NULL
)
15249 ? list_length (current_target_pragma
) : 0;
15250 for (i
= 0; args
; args
= TREE_CHAIN (args
), i
++)
15254 is_pragma
= (force_pragma
|| i
< num_pragma_values
);
15255 if (TREE_VALUE (args
)
15256 && !s390_valid_target_attribute_inner_p (TREE_VALUE (args
),
15257 opts
, new_opts_set
,
15266 else if (TREE_CODE (args
) != STRING_CST
)
15268 error ("attribute %<target%> argument not a string");
15272 /* Handle multiple arguments separated by commas. */
15273 next_optstr
= ASTRDUP (TREE_STRING_POINTER (args
));
15275 while (next_optstr
&& *next_optstr
!= '\0')
15277 char *p
= next_optstr
;
15279 char *comma
= strchr (next_optstr
, ',');
15280 size_t len
, opt_len
;
15286 enum cl_var_type var_type
;
15292 len
= comma
- next_optstr
;
15293 next_optstr
= comma
+ 1;
15298 next_optstr
= NULL
;
15301 /* Recognize no-xxx. */
15302 if (len
> 3 && p
[0] == 'n' && p
[1] == 'o' && p
[2] == '-')
15311 /* Find the option. */
15314 for (i
= 0; i
< ARRAY_SIZE (attrs
); i
++)
15316 opt_len
= attrs
[i
].len
;
15317 if (ch
== attrs
[i
].string
[0]
15318 && ((attrs
[i
].has_arg
) ? len
> opt_len
: len
== opt_len
)
15319 && memcmp (p
, attrs
[i
].string
, opt_len
) == 0)
15321 opt
= attrs
[i
].opt
;
15322 if (!opt_set_p
&& cl_options
[opt
].cl_reject_negative
)
15324 mask
= cl_options
[opt
].var_value
;
15325 var_type
= cl_options
[opt
].var_type
;
15331 /* Process the option. */
15334 error ("attribute(target(\"%s\")) is unknown", orig_p
);
15337 else if (attrs
[i
].only_as_pragma
&& !force_pragma
)
15339 /* Value is not allowed for the target attribute. */
15340 error ("value %qs is not supported by attribute %<target%>",
15345 else if (var_type
== CLVC_BIT_SET
|| var_type
== CLVC_BIT_CLEAR
)
15347 if (var_type
== CLVC_BIT_CLEAR
)
15348 opt_set_p
= !opt_set_p
;
15351 opts
->x_target_flags
|= mask
;
15353 opts
->x_target_flags
&= ~mask
;
15354 new_opts_set
->x_target_flags
|= mask
;
15357 else if (cl_options
[opt
].var_type
== CLVC_BOOLEAN
)
15361 if (cl_options
[opt
].cl_uinteger
)
15363 /* Unsigned integer argument. Code based on the function
15364 decode_cmdline_option () in opts-common.c. */
15365 value
= integral_argument (p
+ opt_len
);
15368 value
= (opt_set_p
) ? 1 : 0;
15372 struct cl_decoded_option decoded
;
15374 /* Value range check; only implemented for numeric and boolean
15375 options at the moment. */
15376 generate_option (opt
, NULL
, value
, CL_TARGET
, &decoded
);
15377 s390_handle_option (opts
, new_opts_set
, &decoded
, input_location
);
15378 set_option (opts
, new_opts_set
, opt
, value
,
15379 p
+ opt_len
, DK_UNSPECIFIED
, input_location
,
15384 error ("attribute(target(\"%s\")) is unknown", orig_p
);
15389 else if (cl_options
[opt
].var_type
== CLVC_ENUM
)
15394 arg_ok
= opt_enum_arg_to_value (opt
, p
+ opt_len
, &value
, CL_TARGET
);
15396 set_option (opts
, new_opts_set
, opt
, value
,
15397 p
+ opt_len
, DK_UNSPECIFIED
, input_location
,
15401 error ("attribute(target(\"%s\")) is unknown", orig_p
);
15407 gcc_unreachable ();
15412 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
15415 s390_valid_target_attribute_tree (tree args
,
15416 struct gcc_options
*opts
,
15417 const struct gcc_options
*opts_set
,
15420 tree t
= NULL_TREE
;
15421 struct gcc_options new_opts_set
;
15423 memset (&new_opts_set
, 0, sizeof (new_opts_set
));
15425 /* Process each of the options on the chain. */
15426 if (! s390_valid_target_attribute_inner_p (args
, opts
, &new_opts_set
,
15428 return error_mark_node
;
15430 /* If some option was set (even if it has not changed), rerun
15431 s390_option_override_internal, and then save the options away. */
15432 if (new_opts_set
.x_target_flags
15433 || new_opts_set
.x_s390_arch
15434 || new_opts_set
.x_s390_tune
15435 || new_opts_set
.x_s390_stack_guard
15436 || new_opts_set
.x_s390_stack_size
15437 || new_opts_set
.x_s390_branch_cost
15438 || new_opts_set
.x_s390_warn_framesize
15439 || new_opts_set
.x_s390_warn_dynamicstack_p
)
15441 const unsigned char *src
= (const unsigned char *)opts_set
;
15442 unsigned char *dest
= (unsigned char *)&new_opts_set
;
15445 /* Merge the original option flags into the new ones. */
15446 for (i
= 0; i
< sizeof(*opts_set
); i
++)
15449 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
15450 s390_option_override_internal (opts
, &new_opts_set
);
15451 /* Save the current options unless we are validating options for
15453 t
= build_target_option_node (opts
);
15458 /* Hook to validate attribute((target("string"))). */
15461 s390_valid_target_attribute_p (tree fndecl
,
15462 tree
ARG_UNUSED (name
),
15464 int ARG_UNUSED (flags
))
15466 struct gcc_options func_options
;
15467 tree new_target
, new_optimize
;
15470 /* attribute((target("default"))) does nothing, beyond
15471 affecting multi-versioning. */
15472 if (TREE_VALUE (args
)
15473 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
15474 && TREE_CHAIN (args
) == NULL_TREE
15475 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args
)), "default") == 0)
15478 tree old_optimize
= build_optimization_node (&global_options
);
15480 /* Get the optimization options of the current function. */
15481 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
15483 if (!func_optimize
)
15484 func_optimize
= old_optimize
;
15486 /* Init func_options. */
15487 memset (&func_options
, 0, sizeof (func_options
));
15488 init_options_struct (&func_options
, NULL
);
15489 lang_hooks
.init_options_struct (&func_options
);
15491 cl_optimization_restore (&func_options
, TREE_OPTIMIZATION (func_optimize
));
15493 /* Initialize func_options to the default before its target options can
15495 cl_target_option_restore (&func_options
,
15496 TREE_TARGET_OPTION (target_option_default_node
));
15498 new_target
= s390_valid_target_attribute_tree (args
, &func_options
,
15499 &global_options_set
,
15501 current_target_pragma
));
15502 new_optimize
= build_optimization_node (&func_options
);
15503 if (new_target
== error_mark_node
)
15505 else if (fndecl
&& new_target
)
15507 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
15508 if (old_optimize
!= new_optimize
)
15509 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
15514 /* Hook to determine if one function can safely inline another. */
15517 s390_can_inline_p (tree caller
, tree callee
)
15519 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
15520 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
15523 callee_tree
= target_option_default_node
;
15525 caller_tree
= target_option_default_node
;
15526 if (callee_tree
== caller_tree
)
15529 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
15530 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
15533 if ((caller_opts
->x_target_flags
& ~(MASK_SOFT_FLOAT
| MASK_HARD_DFP
))
15534 != (callee_opts
->x_target_flags
& ~(MASK_SOFT_FLOAT
| MASK_HARD_DFP
)))
15537 /* Don't inline functions to be compiled for a more recent arch into a
15538 function for an older arch. */
15539 else if (caller_opts
->x_s390_arch
< callee_opts
->x_s390_arch
)
15542 /* Inlining a hard float function into a soft float function is only
15543 allowed if the hard float function doesn't actually make use of
15546 We are called from FEs for multi-versioning call optimization, so
15547 beware of ipa_fn_summaries not available. */
15548 else if (((TARGET_SOFT_FLOAT_P (caller_opts
->x_target_flags
)
15549 && !TARGET_SOFT_FLOAT_P (callee_opts
->x_target_flags
))
15550 || (!TARGET_HARD_DFP_P (caller_opts
->x_target_flags
)
15551 && TARGET_HARD_DFP_P (callee_opts
->x_target_flags
)))
15552 && (! ipa_fn_summaries
15553 || ipa_fn_summaries
->get
15554 (cgraph_node::get (callee
))->fp_expressions
))
15561 /* Set VAL to correct enum value according to the indirect-branch or
15562 function-return attribute in ATTR. */
15565 s390_indirect_branch_attrvalue (tree attr
, enum indirect_branch
*val
)
15567 const char *str
= TREE_STRING_POINTER (TREE_VALUE (TREE_VALUE (attr
)));
15568 if (strcmp (str
, "keep") == 0)
15569 *val
= indirect_branch_keep
;
15570 else if (strcmp (str
, "thunk") == 0)
15571 *val
= indirect_branch_thunk
;
15572 else if (strcmp (str
, "thunk-inline") == 0)
15573 *val
= indirect_branch_thunk_inline
;
15574 else if (strcmp (str
, "thunk-extern") == 0)
15575 *val
= indirect_branch_thunk_extern
;
15578 /* Memorize the setting for -mindirect-branch* and -mfunction-return*
15579 from either the cmdline or the function attributes in
15583 s390_indirect_branch_settings (tree fndecl
)
15590 /* Initialize with the cmdline options and let the attributes
15592 cfun
->machine
->indirect_branch_jump
= s390_indirect_branch_jump
;
15593 cfun
->machine
->indirect_branch_call
= s390_indirect_branch_call
;
15595 cfun
->machine
->function_return_reg
= s390_function_return_reg
;
15596 cfun
->machine
->function_return_mem
= s390_function_return_mem
;
15598 if ((attr
= lookup_attribute ("indirect_branch",
15599 DECL_ATTRIBUTES (fndecl
))))
15601 s390_indirect_branch_attrvalue (attr
,
15602 &cfun
->machine
->indirect_branch_jump
);
15603 s390_indirect_branch_attrvalue (attr
,
15604 &cfun
->machine
->indirect_branch_call
);
15607 if ((attr
= lookup_attribute ("indirect_branch_jump",
15608 DECL_ATTRIBUTES (fndecl
))))
15609 s390_indirect_branch_attrvalue (attr
, &cfun
->machine
->indirect_branch_jump
);
15611 if ((attr
= lookup_attribute ("indirect_branch_call",
15612 DECL_ATTRIBUTES (fndecl
))))
15613 s390_indirect_branch_attrvalue (attr
, &cfun
->machine
->indirect_branch_call
);
15615 if ((attr
= lookup_attribute ("function_return",
15616 DECL_ATTRIBUTES (fndecl
))))
15618 s390_indirect_branch_attrvalue (attr
,
15619 &cfun
->machine
->function_return_reg
);
15620 s390_indirect_branch_attrvalue (attr
,
15621 &cfun
->machine
->function_return_mem
);
15624 if ((attr
= lookup_attribute ("function_return_reg",
15625 DECL_ATTRIBUTES (fndecl
))))
15626 s390_indirect_branch_attrvalue (attr
, &cfun
->machine
->function_return_reg
);
15628 if ((attr
= lookup_attribute ("function_return_mem",
15629 DECL_ATTRIBUTES (fndecl
))))
15630 s390_indirect_branch_attrvalue (attr
, &cfun
->machine
->function_return_mem
);
15633 #if S390_USE_TARGET_ATTRIBUTE
15634 /* Restore targets globals from NEW_TREE and invalidate s390_previous_fndecl
15638 s390_activate_target_options (tree new_tree
)
15640 cl_target_option_restore (&global_options
, TREE_TARGET_OPTION (new_tree
));
15641 if (TREE_TARGET_GLOBALS (new_tree
))
15642 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
15643 else if (new_tree
== target_option_default_node
)
15644 restore_target_globals (&default_target_globals
);
15646 TREE_TARGET_GLOBALS (new_tree
) = save_target_globals_default_opts ();
15647 s390_previous_fndecl
= NULL_TREE
;
15651 /* Establish appropriate back-end context for processing the function
15652 FNDECL. The argument might be NULL to indicate processing at top
15653 level, outside of any function scope. */
15655 s390_set_current_function (tree fndecl
)
15657 #if S390_USE_TARGET_ATTRIBUTE
15658 /* Only change the context if the function changes. This hook is called
15659 several times in the course of compiling a function, and we don't want to
15660 slow things down too much or call target_reinit when it isn't safe. */
15661 if (fndecl
== s390_previous_fndecl
)
15663 s390_indirect_branch_settings (fndecl
);
15668 if (s390_previous_fndecl
== NULL_TREE
)
15669 old_tree
= target_option_current_node
;
15670 else if (DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl
))
15671 old_tree
= DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl
);
15673 old_tree
= target_option_default_node
;
15675 if (fndecl
== NULL_TREE
)
15677 if (old_tree
!= target_option_current_node
)
15678 s390_activate_target_options (target_option_current_node
);
15682 tree new_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
15683 if (new_tree
== NULL_TREE
)
15684 new_tree
= target_option_default_node
;
15686 if (old_tree
!= new_tree
)
15687 s390_activate_target_options (new_tree
);
15688 s390_previous_fndecl
= fndecl
;
15690 s390_indirect_branch_settings (fndecl
);
15693 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
15696 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
15697 unsigned int align ATTRIBUTE_UNUSED
,
15698 enum by_pieces_operation op ATTRIBUTE_UNUSED
,
15699 bool speed_p ATTRIBUTE_UNUSED
)
15701 return (size
== 1 || size
== 2
15702 || size
== 4 || (TARGET_ZARCH
&& size
== 8));
15705 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
15708 s390_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
15710 tree sfpc
= s390_builtin_decls
[S390_BUILTIN_s390_sfpc
];
15711 tree efpc
= s390_builtin_decls
[S390_BUILTIN_s390_efpc
];
15712 tree call_efpc
= build_call_expr (efpc
, 0);
15713 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
15715 #define FPC_EXCEPTION_MASK HOST_WIDE_INT_UC (0xf8000000)
15716 #define FPC_FLAGS_MASK HOST_WIDE_INT_UC (0x00f80000)
15717 #define FPC_DXC_MASK HOST_WIDE_INT_UC (0x0000ff00)
15718 #define FPC_EXCEPTION_MASK_SHIFT HOST_WIDE_INT_UC (24)
15719 #define FPC_FLAGS_SHIFT HOST_WIDE_INT_UC (16)
15720 #define FPC_DXC_SHIFT HOST_WIDE_INT_UC (8)
15722 /* Generates the equivalent of feholdexcept (&fenv_var)
15724 fenv_var = __builtin_s390_efpc ();
15725 __builtin_s390_sfpc (fenv_var & mask) */
15726 tree old_fpc
= build2 (MODIFY_EXPR
, unsigned_type_node
, fenv_var
, call_efpc
);
15728 build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
15729 build_int_cst (unsigned_type_node
,
15730 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
|
15731 FPC_EXCEPTION_MASK
)));
15732 tree set_new_fpc
= build_call_expr (sfpc
, 1, new_fpc
);
15733 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, old_fpc
, set_new_fpc
);
15735 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT)
15737 __builtin_s390_sfpc (__builtin_s390_efpc () & mask) */
15738 new_fpc
= build2 (BIT_AND_EXPR
, unsigned_type_node
, call_efpc
,
15739 build_int_cst (unsigned_type_node
,
15740 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
)));
15741 *clear
= build_call_expr (sfpc
, 1, new_fpc
);
15743 /* Generates the equivalent of feupdateenv (fenv_var)
15745 old_fpc = __builtin_s390_efpc ();
15746 __builtin_s390_sfpc (fenv_var);
15747 __atomic_feraiseexcept ((old_fpc & FPC_FLAGS_MASK) >> FPC_FLAGS_SHIFT); */
15749 old_fpc
= create_tmp_var_raw (unsigned_type_node
);
15750 tree store_old_fpc
= build2 (MODIFY_EXPR
, void_type_node
,
15751 old_fpc
, call_efpc
);
15753 set_new_fpc
= build_call_expr (sfpc
, 1, fenv_var
);
15755 tree raise_old_except
= build2 (BIT_AND_EXPR
, unsigned_type_node
, old_fpc
,
15756 build_int_cst (unsigned_type_node
,
15758 raise_old_except
= build2 (RSHIFT_EXPR
, unsigned_type_node
, raise_old_except
,
15759 build_int_cst (unsigned_type_node
,
15761 tree atomic_feraiseexcept
15762 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
15763 raise_old_except
= build_call_expr (atomic_feraiseexcept
,
15764 1, raise_old_except
);
15766 *update
= build2 (COMPOUND_EXPR
, void_type_node
,
15767 build2 (COMPOUND_EXPR
, void_type_node
,
15768 store_old_fpc
, set_new_fpc
),
15771 #undef FPC_EXCEPTION_MASK
15772 #undef FPC_FLAGS_MASK
15773 #undef FPC_DXC_MASK
15774 #undef FPC_EXCEPTION_MASK_SHIFT
15775 #undef FPC_FLAGS_SHIFT
15776 #undef FPC_DXC_SHIFT
15779 /* Return the vector mode to be used for inner mode MODE when doing
15781 static machine_mode
15782 s390_preferred_simd_mode (scalar_mode mode
)
15810 /* Our hardware does not require vectors to be strictly aligned. */
15812 s390_support_vector_misalignment (machine_mode mode ATTRIBUTE_UNUSED
,
15813 const_tree type ATTRIBUTE_UNUSED
,
15814 int misalignment ATTRIBUTE_UNUSED
,
15815 bool is_packed ATTRIBUTE_UNUSED
)
15820 return default_builtin_support_vector_misalignment (mode
, type
, misalignment
,
15824 /* The vector ABI requires vector types to be aligned on an 8 byte
15825 boundary (our stack alignment). However, we allow this to be
15826 overriden by the user, while this definitely breaks the ABI. */
15827 static HOST_WIDE_INT
15828 s390_vector_alignment (const_tree type
)
15830 if (!TARGET_VX_ABI
)
15831 return default_vector_alignment (type
);
15833 if (TYPE_USER_ALIGN (type
))
15834 return TYPE_ALIGN (type
);
15836 return MIN (64, tree_to_shwi (TYPE_SIZE (type
)));
15839 /* Implement TARGET_CONSTANT_ALIGNMENT. Alignment on even addresses for
15840 LARL instruction. */
15842 static HOST_WIDE_INT
15843 s390_constant_alignment (const_tree
, HOST_WIDE_INT align
)
15845 return MAX (align
, 16);
15848 #ifdef HAVE_AS_MACHINE_MACHINEMODE
15849 /* Implement TARGET_ASM_FILE_START. */
15851 s390_asm_file_start (void)
15853 default_file_start ();
15854 s390_asm_output_machine_for_arch (asm_out_file
);
15858 /* Implement TARGET_ASM_FILE_END. */
15860 s390_asm_file_end (void)
15862 #ifdef HAVE_AS_GNU_ATTRIBUTE
15863 varpool_node
*vnode
;
15864 cgraph_node
*cnode
;
15866 FOR_EACH_VARIABLE (vnode
)
15867 if (TREE_PUBLIC (vnode
->decl
))
15868 s390_check_type_for_vector_abi (TREE_TYPE (vnode
->decl
), false, false);
15870 FOR_EACH_FUNCTION (cnode
)
15871 if (TREE_PUBLIC (cnode
->decl
))
15872 s390_check_type_for_vector_abi (TREE_TYPE (cnode
->decl
), false, false);
15875 if (s390_vector_abi
!= 0)
15876 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
15879 file_end_indicate_exec_stack ();
15881 if (flag_split_stack
)
15882 file_end_indicate_split_stack ();
15885 /* Return true if TYPE is a vector bool type. */
15887 s390_vector_bool_type_p (const_tree type
)
15889 return TYPE_VECTOR_OPAQUE (type
);
15892 /* Return the diagnostic message string if the binary operation OP is
15893 not permitted on TYPE1 and TYPE2, NULL otherwise. */
15895 s390_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
15897 bool bool1_p
, bool2_p
;
15901 machine_mode mode1
, mode2
;
15903 if (!TARGET_ZVECTOR
)
15906 if (!VECTOR_TYPE_P (type1
) || !VECTOR_TYPE_P (type2
))
15909 bool1_p
= s390_vector_bool_type_p (type1
);
15910 bool2_p
= s390_vector_bool_type_p (type2
);
15912 /* Mixing signed and unsigned types is forbidden for all
15914 if (!bool1_p
&& !bool2_p
15915 && TYPE_UNSIGNED (type1
) != TYPE_UNSIGNED (type2
))
15916 return N_("types differ in signedness");
15918 plusminus_p
= (op
== PLUS_EXPR
|| op
== MINUS_EXPR
);
15919 muldiv_p
= (op
== MULT_EXPR
|| op
== RDIV_EXPR
|| op
== TRUNC_DIV_EXPR
15920 || op
== CEIL_DIV_EXPR
|| op
== FLOOR_DIV_EXPR
15921 || op
== ROUND_DIV_EXPR
);
15922 compare_p
= (op
== LT_EXPR
|| op
== LE_EXPR
|| op
== GT_EXPR
|| op
== GE_EXPR
15923 || op
== EQ_EXPR
|| op
== NE_EXPR
);
15925 if (bool1_p
&& bool2_p
&& (plusminus_p
|| muldiv_p
))
15926 return N_("binary operator does not support two vector bool operands");
15928 if (bool1_p
!= bool2_p
&& (muldiv_p
|| compare_p
))
15929 return N_("binary operator does not support vector bool operand");
15931 mode1
= TYPE_MODE (type1
);
15932 mode2
= TYPE_MODE (type2
);
15934 if (bool1_p
!= bool2_p
&& plusminus_p
15935 && (GET_MODE_CLASS (mode1
) == MODE_VECTOR_FLOAT
15936 || GET_MODE_CLASS (mode2
) == MODE_VECTOR_FLOAT
))
15937 return N_("binary operator does not support mixing vector "
15938 "bool with floating point vector operands");
15943 /* Implement TARGET_C_EXCESS_PRECISION.
15945 FIXME: For historical reasons, float_t and double_t are typedef'ed to
15946 double on s390, causing operations on float_t to operate in a higher
15947 precision than is necessary. However, it is not the case that SFmode
15948 operations have implicit excess precision, and we generate more optimal
15949 code if we let the compiler know no implicit extra precision is added.
15951 That means when we are compiling with -fexcess-precision=fast, the value
15952 we set for FLT_EVAL_METHOD will be out of line with the actual precision of
15953 float_t (though they would be correct for -fexcess-precision=standard).
15955 A complete fix would modify glibc to remove the unnecessary typedef
15956 of float_t to double. */
15958 static enum flt_eval_method
15959 s390_excess_precision (enum excess_precision_type type
)
15963 case EXCESS_PRECISION_TYPE_IMPLICIT
:
15964 case EXCESS_PRECISION_TYPE_FAST
:
15965 /* The fastest type to promote to will always be the native type,
15966 whether that occurs with implicit excess precision or
15968 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
15969 case EXCESS_PRECISION_TYPE_STANDARD
:
15970 /* Otherwise, when we are in a standards compliant mode, to
15971 ensure consistency with the implementation in glibc, report that
15972 float is evaluated to the range and precision of double. */
15973 return FLT_EVAL_METHOD_PROMOTE_TO_DOUBLE
;
15975 gcc_unreachable ();
15977 return FLT_EVAL_METHOD_UNPREDICTABLE
;
15980 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
15982 static unsigned HOST_WIDE_INT
15983 s390_asan_shadow_offset (void)
15985 return TARGET_64BIT
? HOST_WIDE_INT_1U
<< 52 : HOST_WIDE_INT_UC (0x20000000);
15988 #ifdef HAVE_GAS_HIDDEN
15989 # define USE_HIDDEN_LINKONCE 1
15991 # define USE_HIDDEN_LINKONCE 0
15994 /* Output an indirect branch trampoline for target register REGNO. */
15997 s390_output_indirect_thunk_function (unsigned int regno
, bool z10_p
)
16000 char thunk_label
[32];
16004 sprintf (thunk_label
, TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL
, regno
);
16006 sprintf (thunk_label
, TARGET_INDIRECT_BRANCH_THUNK_NAME_EX
,
16007 INDIRECT_BRANCH_THUNK_REGNUM
, regno
);
16009 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
16010 get_identifier (thunk_label
),
16011 build_function_type_list (void_type_node
, NULL_TREE
));
16012 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
16013 NULL_TREE
, void_type_node
);
16014 TREE_PUBLIC (decl
) = 1;
16015 TREE_STATIC (decl
) = 1;
16016 DECL_IGNORED_P (decl
) = 1;
16018 if (USE_HIDDEN_LINKONCE
)
16020 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
16022 targetm
.asm_out
.unique_section (decl
, 0);
16023 switch_to_section (get_named_section (decl
, NULL
, 0));
16025 targetm
.asm_out
.globalize_label (asm_out_file
, thunk_label
);
16026 fputs ("\t.hidden\t", asm_out_file
);
16027 assemble_name (asm_out_file
, thunk_label
);
16028 putc ('\n', asm_out_file
);
16029 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, thunk_label
, decl
);
16033 switch_to_section (text_section
);
16034 ASM_OUTPUT_LABEL (asm_out_file
, thunk_label
);
16037 DECL_INITIAL (decl
) = make_node (BLOCK
);
16038 current_function_decl
= decl
;
16039 allocate_struct_function (decl
, false);
16040 init_function_start (decl
);
16041 cfun
->is_thunk
= true;
16042 first_function_block_is_cold
= false;
16043 final_start_function (emit_barrier (), asm_out_file
, 1);
16045 /* This makes CFI at least usable for indirect jumps.
16047 Stopping in the thunk: backtrace will point to the thunk target
16048 is if it was interrupted by a signal. For a call this means that
16049 the call chain will be: caller->callee->thunk */
16050 if (flag_asynchronous_unwind_tables
&& flag_dwarf2_cfi_asm
)
16052 fputs ("\t.cfi_signal_frame\n", asm_out_file
);
16053 fprintf (asm_out_file
, "\t.cfi_return_column %d\n", regno
);
16054 for (i
= 0; i
< FPR15_REGNUM
; i
++)
16055 fprintf (asm_out_file
, "\t.cfi_same_value %s\n", reg_names
[i
]);
16062 /* We generate a thunk for z10 compiled code although z10 is
16063 currently not enabled. Tell the assembler to accept the
16065 if (!TARGET_CPU_Z10
)
16067 fputs ("\t.machine push\n", asm_out_file
);
16068 fputs ("\t.machine z10\n", asm_out_file
);
16070 /* We use exrl even if -mzarch hasn't been specified on the
16071 command line so we have to tell the assembler to accept
16074 fputs ("\t.machinemode zarch\n", asm_out_file
);
16076 fputs ("\texrl\t0,1f\n", asm_out_file
);
16079 fputs ("\t.machinemode esa\n", asm_out_file
);
16081 if (!TARGET_CPU_Z10
)
16082 fputs ("\t.machine pop\n", asm_out_file
);
16087 fprintf (asm_out_file
, "\tlarl\t%%r%d,1f\n",
16088 INDIRECT_BRANCH_THUNK_REGNUM
);
16091 fprintf (asm_out_file
, "\tex\t0,0(%%r%d)\n",
16092 INDIRECT_BRANCH_THUNK_REGNUM
);
16096 fputs ("0:\tj\t0b\n", asm_out_file
);
16098 /* 1: br <regno> */
16099 fprintf (asm_out_file
, "1:\tbr\t%%r%d\n", regno
);
16101 final_end_function ();
16102 init_insn_lengths ();
16103 free_after_compilation (cfun
);
16105 current_function_decl
= NULL
;
16108 /* Implement the asm.code_end target hook. */
16111 s390_code_end (void)
16115 for (i
= 1; i
< 16; i
++)
16117 if (indirect_branch_z10thunk_mask
& (1 << i
))
16118 s390_output_indirect_thunk_function (i
, true);
16120 if (indirect_branch_prez10thunk_mask
& (1 << i
))
16121 s390_output_indirect_thunk_function (i
, false);
16124 if (TARGET_INDIRECT_BRANCH_TABLE
)
16129 for (o
= 0; o
< INDIRECT_BRANCH_NUM_OPTIONS
; o
++)
16131 if (indirect_branch_table_label_no
[o
] == 0)
16134 switch_to_section (get_section (indirect_branch_table_name
[o
],
16137 for (i
= 0; i
< indirect_branch_table_label_no
[o
]; i
++)
16139 char label_start
[32];
16141 ASM_GENERATE_INTERNAL_LABEL (label_start
,
16142 indirect_branch_table_label
[o
], i
);
16144 fputs ("\t.long\t", asm_out_file
);
16145 assemble_name_raw (asm_out_file
, label_start
);
16146 fputs ("-.\n", asm_out_file
);
16148 switch_to_section (current_function_section ());
16153 /* Implement the TARGET_CASE_VALUES_THRESHOLD target hook. */
16156 s390_case_values_threshold (void)
16158 /* Disabling branch prediction for indirect jumps makes jump tables
16159 much more expensive. */
16160 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP
)
16163 return default_case_values_threshold ();
16166 /* Initialize GCC target structure. */
16168 #undef TARGET_ASM_ALIGNED_HI_OP
16169 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
16170 #undef TARGET_ASM_ALIGNED_DI_OP
16171 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
16172 #undef TARGET_ASM_INTEGER
16173 #define TARGET_ASM_INTEGER s390_assemble_integer
16175 #undef TARGET_ASM_OPEN_PAREN
16176 #define TARGET_ASM_OPEN_PAREN ""
16178 #undef TARGET_ASM_CLOSE_PAREN
16179 #define TARGET_ASM_CLOSE_PAREN ""
16181 #undef TARGET_OPTION_OVERRIDE
16182 #define TARGET_OPTION_OVERRIDE s390_option_override
16184 #ifdef TARGET_THREAD_SSP_OFFSET
16185 #undef TARGET_STACK_PROTECT_GUARD
16186 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
16189 #undef TARGET_ENCODE_SECTION_INFO
16190 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
16192 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16193 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
16196 #undef TARGET_HAVE_TLS
16197 #define TARGET_HAVE_TLS true
16199 #undef TARGET_CANNOT_FORCE_CONST_MEM
16200 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
16202 #undef TARGET_DELEGITIMIZE_ADDRESS
16203 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
16205 #undef TARGET_LEGITIMIZE_ADDRESS
16206 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
16208 #undef TARGET_RETURN_IN_MEMORY
16209 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
16211 #undef TARGET_INIT_BUILTINS
16212 #define TARGET_INIT_BUILTINS s390_init_builtins
16213 #undef TARGET_EXPAND_BUILTIN
16214 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
16215 #undef TARGET_BUILTIN_DECL
16216 #define TARGET_BUILTIN_DECL s390_builtin_decl
16218 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
16219 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
16221 #undef TARGET_ASM_OUTPUT_MI_THUNK
16222 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
16223 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16224 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16226 #undef TARGET_C_EXCESS_PRECISION
16227 #define TARGET_C_EXCESS_PRECISION s390_excess_precision
16229 #undef TARGET_SCHED_ADJUST_PRIORITY
16230 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
16231 #undef TARGET_SCHED_ISSUE_RATE
16232 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
16233 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16234 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
16236 #undef TARGET_SCHED_VARIABLE_ISSUE
16237 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
16238 #undef TARGET_SCHED_REORDER
16239 #define TARGET_SCHED_REORDER s390_sched_reorder
16240 #undef TARGET_SCHED_INIT
16241 #define TARGET_SCHED_INIT s390_sched_init
16243 #undef TARGET_CANNOT_COPY_INSN_P
16244 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
16245 #undef TARGET_RTX_COSTS
16246 #define TARGET_RTX_COSTS s390_rtx_costs
16247 #undef TARGET_ADDRESS_COST
16248 #define TARGET_ADDRESS_COST s390_address_cost
16249 #undef TARGET_REGISTER_MOVE_COST
16250 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
16251 #undef TARGET_MEMORY_MOVE_COST
16252 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
16253 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
16254 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
16255 s390_builtin_vectorization_cost
16257 #undef TARGET_MACHINE_DEPENDENT_REORG
16258 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
16260 #undef TARGET_VALID_POINTER_MODE
16261 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
16263 #undef TARGET_BUILD_BUILTIN_VA_LIST
16264 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
16265 #undef TARGET_EXPAND_BUILTIN_VA_START
16266 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
16267 #undef TARGET_ASAN_SHADOW_OFFSET
16268 #define TARGET_ASAN_SHADOW_OFFSET s390_asan_shadow_offset
16269 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16270 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
16272 #undef TARGET_PROMOTE_FUNCTION_MODE
16273 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
16274 #undef TARGET_PASS_BY_REFERENCE
16275 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
16277 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
16278 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE s390_override_options_after_change
16280 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16281 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
16282 #undef TARGET_FUNCTION_ARG
16283 #define TARGET_FUNCTION_ARG s390_function_arg
16284 #undef TARGET_FUNCTION_ARG_ADVANCE
16285 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
16286 #undef TARGET_FUNCTION_ARG_PADDING
16287 #define TARGET_FUNCTION_ARG_PADDING s390_function_arg_padding
16288 #undef TARGET_FUNCTION_VALUE
16289 #define TARGET_FUNCTION_VALUE s390_function_value
16290 #undef TARGET_LIBCALL_VALUE
16291 #define TARGET_LIBCALL_VALUE s390_libcall_value
16292 #undef TARGET_STRICT_ARGUMENT_NAMING
16293 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
16295 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
16296 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
16298 #undef TARGET_FIXED_CONDITION_CODE_REGS
16299 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
16301 #undef TARGET_CC_MODES_COMPATIBLE
16302 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
16304 #undef TARGET_INVALID_WITHIN_DOLOOP
16305 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
16308 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16309 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
16312 #undef TARGET_DWARF_FRAME_REG_MODE
16313 #define TARGET_DWARF_FRAME_REG_MODE s390_dwarf_frame_reg_mode
16315 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
16316 #undef TARGET_MANGLE_TYPE
16317 #define TARGET_MANGLE_TYPE s390_mangle_type
16320 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16321 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
16323 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16324 #define TARGET_VECTOR_MODE_SUPPORTED_P s390_vector_mode_supported_p
16326 #undef TARGET_PREFERRED_RELOAD_CLASS
16327 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
16329 #undef TARGET_SECONDARY_RELOAD
16330 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
16331 #undef TARGET_SECONDARY_MEMORY_NEEDED
16332 #define TARGET_SECONDARY_MEMORY_NEEDED s390_secondary_memory_needed
16333 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
16334 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE s390_secondary_memory_needed_mode
16336 #undef TARGET_LIBGCC_CMP_RETURN_MODE
16337 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
16339 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
16340 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
16342 #undef TARGET_LEGITIMATE_ADDRESS_P
16343 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
16345 #undef TARGET_LEGITIMATE_CONSTANT_P
16346 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
16348 #undef TARGET_LRA_P
16349 #define TARGET_LRA_P s390_lra_p
16351 #undef TARGET_CAN_ELIMINATE
16352 #define TARGET_CAN_ELIMINATE s390_can_eliminate
16354 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16355 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
16357 #undef TARGET_LOOP_UNROLL_ADJUST
16358 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
16360 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
16361 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
16362 #undef TARGET_TRAMPOLINE_INIT
16363 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
16366 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
16367 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
16369 #undef TARGET_UNWIND_WORD_MODE
16370 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
16372 #undef TARGET_CANONICALIZE_COMPARISON
16373 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
16375 #undef TARGET_HARD_REGNO_SCRATCH_OK
16376 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
16378 #undef TARGET_HARD_REGNO_NREGS
16379 #define TARGET_HARD_REGNO_NREGS s390_hard_regno_nregs
16380 #undef TARGET_HARD_REGNO_MODE_OK
16381 #define TARGET_HARD_REGNO_MODE_OK s390_hard_regno_mode_ok
16382 #undef TARGET_MODES_TIEABLE_P
16383 #define TARGET_MODES_TIEABLE_P s390_modes_tieable_p
16385 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
16386 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
16387 s390_hard_regno_call_part_clobbered
16389 #undef TARGET_ATTRIBUTE_TABLE
16390 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
16392 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16393 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16395 #undef TARGET_SET_UP_BY_PROLOGUE
16396 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
16398 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16399 #define TARGET_EXTRA_LIVE_ON_ENTRY s390_live_on_entry
16401 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
16402 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
16403 s390_use_by_pieces_infrastructure_p
16405 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
16406 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV s390_atomic_assign_expand_fenv
16408 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
16409 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN s390_invalid_arg_for_unprototyped_fn
16411 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16412 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE s390_preferred_simd_mode
16414 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
16415 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT s390_support_vector_misalignment
16417 #undef TARGET_VECTOR_ALIGNMENT
16418 #define TARGET_VECTOR_ALIGNMENT s390_vector_alignment
16420 #undef TARGET_INVALID_BINARY_OP
16421 #define TARGET_INVALID_BINARY_OP s390_invalid_binary_op
16423 #ifdef HAVE_AS_MACHINE_MACHINEMODE
16424 #undef TARGET_ASM_FILE_START
16425 #define TARGET_ASM_FILE_START s390_asm_file_start
16428 #undef TARGET_ASM_FILE_END
16429 #define TARGET_ASM_FILE_END s390_asm_file_end
16431 #undef TARGET_SET_CURRENT_FUNCTION
16432 #define TARGET_SET_CURRENT_FUNCTION s390_set_current_function
16434 #if S390_USE_TARGET_ATTRIBUTE
16435 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
16436 #define TARGET_OPTION_VALID_ATTRIBUTE_P s390_valid_target_attribute_p
16438 #undef TARGET_CAN_INLINE_P
16439 #define TARGET_CAN_INLINE_P s390_can_inline_p
16442 #undef TARGET_OPTION_RESTORE
16443 #define TARGET_OPTION_RESTORE s390_function_specific_restore
16445 #undef TARGET_CAN_CHANGE_MODE_CLASS
16446 #define TARGET_CAN_CHANGE_MODE_CLASS s390_can_change_mode_class
16448 #undef TARGET_CONSTANT_ALIGNMENT
16449 #define TARGET_CONSTANT_ALIGNMENT s390_constant_alignment
16451 #undef TARGET_ASM_CODE_END
16452 #define TARGET_ASM_CODE_END s390_code_end
16454 #undef TARGET_CASE_VALUES_THRESHOLD
16455 #define TARGET_CASE_VALUES_THRESHOLD s390_case_values_threshold
16457 /* Use only short displacement, since long displacement is not available for
16458 the floating point instructions. */
16459 #undef TARGET_MAX_ANCHOR_OFFSET
16460 #define TARGET_MAX_ANCHOR_OFFSET 0xfff
16462 struct gcc_target targetm
= TARGET_INITIALIZER
;
16464 #include "gt-s390.h"