1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
47 #include "target-def.h"
49 #include "langhooks.h"
57 /* Define the specific costs for a given cpu. */
59 struct processor_costs
62 const int m
; /* cost of an M instruction. */
63 const int mghi
; /* cost of an MGHI instruction. */
64 const int mh
; /* cost of an MH instruction. */
65 const int mhi
; /* cost of an MHI instruction. */
66 const int ml
; /* cost of an ML instruction. */
67 const int mr
; /* cost of an MR instruction. */
68 const int ms
; /* cost of an MS instruction. */
69 const int msg
; /* cost of an MSG instruction. */
70 const int msgf
; /* cost of an MSGF instruction. */
71 const int msgfr
; /* cost of an MSGFR instruction. */
72 const int msgr
; /* cost of an MSGR instruction. */
73 const int msr
; /* cost of an MSR instruction. */
74 const int mult_df
; /* cost of multiplication in DFmode. */
77 const int sqxbr
; /* cost of square root in TFmode. */
78 const int sqdbr
; /* cost of square root in DFmode. */
79 const int sqebr
; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr
; /* cost of multiply and add in DFmode. */
82 const int maebr
; /* cost of multiply and add in SFmode. */
94 const struct processor_costs
*s390_cost
;
97 struct processor_costs z900_cost
=
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
129 struct processor_costs z990_cost
=
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
161 struct processor_costs z9_109_cost
=
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
193 struct processor_costs z10_cost
=
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
225 struct processor_costs z196_cost
=
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
256 extern int reload_completed
;
258 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
259 static rtx last_scheduled_insn
;
261 /* Structure used to hold the components of a S/390 memory
262 address. A legitimate address on S/390 is of the general
264 base + index + displacement
265 where any of the components is optional.
267 base and index are registers of the class ADDR_REGS,
268 displacement is an unsigned 12-bit immediate constant. */
279 /* The following structure is embedded in the machine
280 specific part of struct function. */
282 struct GTY (()) s390_frame_layout
284 /* Offset within stack frame. */
285 HOST_WIDE_INT gprs_offset
;
286 HOST_WIDE_INT f0_offset
;
287 HOST_WIDE_INT f4_offset
;
288 HOST_WIDE_INT f8_offset
;
289 HOST_WIDE_INT backchain_offset
;
291 /* Number of first and last gpr where slots in the register
292 save area are reserved for. */
293 int first_save_gpr_slot
;
294 int last_save_gpr_slot
;
296 /* Number of first and last gpr to be saved, restored. */
298 int first_restore_gpr
;
300 int last_restore_gpr
;
302 /* Bits standing for floating point registers. Set, if the
303 respective register has to be saved. Starting with reg 16 (f0)
304 at the rightmost bit.
305 Bit 15 - 8 7 6 5 4 3 2 1 0
306 fpr 15 - 8 7 5 3 1 6 4 2 0
307 reg 31 - 24 23 22 21 20 19 18 17 16 */
308 unsigned int fpr_bitmap
;
310 /* Number of floating point registers f8-f15 which must be saved. */
313 /* Set if return address needs to be saved.
314 This flag is set by s390_return_addr_rtx if it could not use
315 the initial value of r14 and therefore depends on r14 saved
317 bool save_return_addr_p
;
319 /* Size of stack frame. */
320 HOST_WIDE_INT frame_size
;
323 /* Define the structure for the machine field in struct function. */
325 struct GTY(()) machine_function
327 struct s390_frame_layout frame_layout
;
329 /* Literal pool base register. */
332 /* True if we may need to perform branch splitting. */
333 bool split_branches_pending_p
;
335 /* Some local-dynamic TLS symbol name. */
336 const char *some_ld_name
;
338 bool has_landing_pad_p
;
341 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
343 #define cfun_frame_layout (cfun->machine->frame_layout)
344 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
345 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
346 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
347 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
349 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
352 /* Number of GPRs and FPRs used for argument passing. */
353 #define GP_ARG_NUM_REG 5
354 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
356 /* A couple of shortcuts. */
357 #define CONST_OK_FOR_J(x) \
358 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
359 #define CONST_OK_FOR_K(x) \
360 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
361 #define CONST_OK_FOR_Os(x) \
362 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
363 #define CONST_OK_FOR_Op(x) \
364 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
365 #define CONST_OK_FOR_On(x) \
366 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
368 #define REGNO_PAIR_OK(REGNO, MODE) \
369 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
371 /* That's the read ahead of the dynamic branch prediction unit in
372 bytes on a z10 (or higher) CPU. */
373 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
375 /* Return the alignment for LABEL. We default to the -falign-labels
376 value except for the literal pool base label. */
378 s390_label_align (rtx label
)
380 rtx prev_insn
= prev_active_insn (label
);
382 if (prev_insn
== NULL_RTX
)
385 prev_insn
= single_set (prev_insn
);
387 if (prev_insn
== NULL_RTX
)
390 prev_insn
= SET_SRC (prev_insn
);
392 /* Don't align literal pool base labels. */
393 if (GET_CODE (prev_insn
) == UNSPEC
394 && XINT (prev_insn
, 1) == UNSPEC_MAIN_BASE
)
398 return align_labels_log
;
401 static enum machine_mode
402 s390_libgcc_cmp_return_mode (void)
404 return TARGET_64BIT
? DImode
: SImode
;
407 static enum machine_mode
408 s390_libgcc_shift_count_mode (void)
410 return TARGET_64BIT
? DImode
: SImode
;
413 static enum machine_mode
414 s390_unwind_word_mode (void)
416 return TARGET_64BIT
? DImode
: SImode
;
419 /* Return true if the back end supports mode MODE. */
421 s390_scalar_mode_supported_p (enum machine_mode mode
)
423 /* In contrast to the default implementation reject TImode constants on 31bit
424 TARGET_ZARCH for ABI compliance. */
425 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
428 if (DECIMAL_FLOAT_MODE_P (mode
))
429 return default_decimal_float_supported_p ();
431 return default_scalar_mode_supported_p (mode
);
434 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
437 s390_set_has_landing_pad_p (bool value
)
439 cfun
->machine
->has_landing_pad_p
= value
;
442 /* If two condition code modes are compatible, return a condition code
443 mode which is compatible with both. Otherwise, return
446 static enum machine_mode
447 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
455 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
456 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
477 /* Return true if SET either doesn't set the CC register, or else
478 the source and destination have matching CC modes and that
479 CC mode is at least as constrained as REQ_MODE. */
482 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
484 enum machine_mode set_mode
;
486 gcc_assert (GET_CODE (set
) == SET
);
488 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
491 set_mode
= GET_MODE (SET_DEST (set
));
505 if (req_mode
!= set_mode
)
510 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
511 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
517 if (req_mode
!= CCAmode
)
525 return (GET_MODE (SET_SRC (set
)) == set_mode
);
528 /* Return true if every SET in INSN that sets the CC register
529 has source and destination with matching CC modes and that
530 CC mode is at least as constrained as REQ_MODE.
531 If REQ_MODE is VOIDmode, always return false. */
534 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
538 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
539 if (req_mode
== VOIDmode
)
542 if (GET_CODE (PATTERN (insn
)) == SET
)
543 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
545 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
546 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
548 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
549 if (GET_CODE (set
) == SET
)
550 if (!s390_match_ccmode_set (set
, req_mode
))
557 /* If a test-under-mask instruction can be used to implement
558 (compare (and ... OP1) OP2), return the CC mode required
559 to do that. Otherwise, return VOIDmode.
560 MIXED is true if the instruction can distinguish between
561 CC1 and CC2 for mixed selected bits (TMxx), it is false
562 if the instruction cannot (TM). */
565 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
569 /* ??? Fixme: should work on CONST_DOUBLE as well. */
570 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
573 /* Selected bits all zero: CC0.
574 e.g.: int a; if ((a & (16 + 128)) == 0) */
575 if (INTVAL (op2
) == 0)
578 /* Selected bits all one: CC3.
579 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
580 if (INTVAL (op2
) == INTVAL (op1
))
583 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
585 if ((a & (16 + 128)) == 16) -> CCT1
586 if ((a & (16 + 128)) == 128) -> CCT2 */
589 bit1
= exact_log2 (INTVAL (op2
));
590 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
591 if (bit0
!= -1 && bit1
!= -1)
592 return bit0
> bit1
? CCT1mode
: CCT2mode
;
598 /* Given a comparison code OP (EQ, NE, etc.) and the operands
599 OP0 and OP1 of a COMPARE, return the mode to be used for the
603 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
609 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
610 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
612 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
613 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
615 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
616 || GET_CODE (op1
) == NEG
)
617 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
620 if (GET_CODE (op0
) == AND
)
622 /* Check whether we can potentially do it via TM. */
623 enum machine_mode ccmode
;
624 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
625 if (ccmode
!= VOIDmode
)
627 /* Relax CCTmode to CCZmode to allow fall-back to AND
628 if that turns out to be beneficial. */
629 return ccmode
== CCTmode
? CCZmode
: ccmode
;
633 if (register_operand (op0
, HImode
)
634 && GET_CODE (op1
) == CONST_INT
635 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
637 if (register_operand (op0
, QImode
)
638 && GET_CODE (op1
) == CONST_INT
639 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
648 /* The only overflow condition of NEG and ABS happens when
649 -INT_MAX is used as parameter, which stays negative. So
650 we have an overflow from a positive value to a negative.
651 Using CCAP mode the resulting cc can be used for comparisons. */
652 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
653 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
656 /* If constants are involved in an add instruction it is possible to use
657 the resulting cc for comparisons with zero. Knowing the sign of the
658 constant the overflow behavior gets predictable. e.g.:
659 int a, b; if ((b = a + c) > 0)
660 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
661 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
662 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
664 if (INTVAL (XEXP((op0
), 1)) < 0)
678 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
679 && GET_CODE (op1
) != CONST_INT
)
685 if (GET_CODE (op0
) == PLUS
686 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
689 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
690 && GET_CODE (op1
) != CONST_INT
)
696 if (GET_CODE (op0
) == MINUS
697 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
700 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
701 && GET_CODE (op1
) != CONST_INT
)
710 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
711 that we can implement more efficiently. */
714 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
716 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
717 if ((*code
== EQ
|| *code
== NE
)
718 && *op1
== const0_rtx
719 && GET_CODE (*op0
) == ZERO_EXTRACT
720 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
721 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
722 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
724 rtx inner
= XEXP (*op0
, 0);
725 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
726 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
727 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
729 if (len
> 0 && len
< modesize
730 && pos
>= 0 && pos
+ len
<= modesize
731 && modesize
<= HOST_BITS_PER_WIDE_INT
)
733 unsigned HOST_WIDE_INT block
;
734 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
735 block
<<= modesize
- pos
- len
;
737 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
738 gen_int_mode (block
, GET_MODE (inner
)));
742 /* Narrow AND of memory against immediate to enable TM. */
743 if ((*code
== EQ
|| *code
== NE
)
744 && *op1
== const0_rtx
745 && GET_CODE (*op0
) == AND
746 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
747 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
749 rtx inner
= XEXP (*op0
, 0);
750 rtx mask
= XEXP (*op0
, 1);
752 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
753 if (GET_CODE (inner
) == SUBREG
754 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
755 && (GET_MODE_SIZE (GET_MODE (inner
))
756 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
758 & GET_MODE_MASK (GET_MODE (inner
))
759 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
761 inner
= SUBREG_REG (inner
);
763 /* Do not change volatile MEMs. */
764 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
766 int part
= s390_single_part (XEXP (*op0
, 1),
767 GET_MODE (inner
), QImode
, 0);
770 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
771 inner
= adjust_address_nv (inner
, QImode
, part
);
772 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
777 /* Narrow comparisons against 0xffff to HImode if possible. */
778 if ((*code
== EQ
|| *code
== NE
)
779 && GET_CODE (*op1
) == CONST_INT
780 && INTVAL (*op1
) == 0xffff
781 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
782 && (nonzero_bits (*op0
, GET_MODE (*op0
))
783 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
785 *op0
= gen_lowpart (HImode
, *op0
);
789 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
790 if (GET_CODE (*op0
) == UNSPEC
791 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
792 && XVECLEN (*op0
, 0) == 1
793 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
794 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
795 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
796 && *op1
== const0_rtx
)
798 enum rtx_code new_code
= UNKNOWN
;
801 case EQ
: new_code
= EQ
; break;
802 case NE
: new_code
= NE
; break;
803 case LT
: new_code
= GTU
; break;
804 case GT
: new_code
= LTU
; break;
805 case LE
: new_code
= GEU
; break;
806 case GE
: new_code
= LEU
; break;
810 if (new_code
!= UNKNOWN
)
812 *op0
= XVECEXP (*op0
, 0, 0);
817 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
818 if (GET_CODE (*op0
) == UNSPEC
819 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
820 && XVECLEN (*op0
, 0) == 1
821 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
822 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
823 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
824 && *op1
== const0_rtx
)
826 enum rtx_code new_code
= UNKNOWN
;
829 case EQ
: new_code
= EQ
; break;
830 case NE
: new_code
= NE
; break;
834 if (new_code
!= UNKNOWN
)
836 *op0
= XVECEXP (*op0
, 0, 0);
841 /* Simplify cascaded EQ, NE with const0_rtx. */
842 if ((*code
== NE
|| *code
== EQ
)
843 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
844 && GET_MODE (*op0
) == SImode
845 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
846 && REG_P (XEXP (*op0
, 0))
847 && XEXP (*op0
, 1) == const0_rtx
848 && *op1
== const0_rtx
)
850 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
851 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
855 *op0
= XEXP (*op0
, 0);
858 /* Prefer register over memory as first operand. */
859 if (MEM_P (*op0
) && REG_P (*op1
))
861 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
862 *code
= swap_condition (*code
);
866 /* Emit a compare instruction suitable to implement the comparison
867 OP0 CODE OP1. Return the correct condition RTL to be placed in
868 the IF_THEN_ELSE of the conditional branch testing the result. */
871 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
873 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
876 /* Do not output a redundant compare instruction if a compare_and_swap
877 pattern already computed the result and the machine modes are compatible. */
878 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
880 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
886 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
887 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
890 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
893 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
895 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
896 conditional branch testing the result. */
899 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
901 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
902 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
905 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
906 unconditional jump, else a conditional jump under condition COND. */
909 s390_emit_jump (rtx target
, rtx cond
)
913 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
915 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
917 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
918 emit_jump_insn (insn
);
921 /* Return branch condition mask to implement a branch
922 specified by CODE. Return -1 for invalid comparisons. */
925 s390_branch_condition_mask (rtx code
)
927 const int CC0
= 1 << 3;
928 const int CC1
= 1 << 2;
929 const int CC2
= 1 << 1;
930 const int CC3
= 1 << 0;
932 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
933 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
934 gcc_assert (XEXP (code
, 1) == const0_rtx
);
936 switch (GET_MODE (XEXP (code
, 0)))
940 switch (GET_CODE (code
))
943 case NE
: return CC1
| CC2
| CC3
;
949 switch (GET_CODE (code
))
952 case NE
: return CC0
| CC2
| CC3
;
958 switch (GET_CODE (code
))
961 case NE
: return CC0
| CC1
| CC3
;
967 switch (GET_CODE (code
))
970 case NE
: return CC0
| CC1
| CC2
;
976 switch (GET_CODE (code
))
978 case EQ
: return CC0
| CC2
;
979 case NE
: return CC1
| CC3
;
985 switch (GET_CODE (code
))
987 case LTU
: return CC2
| CC3
; /* carry */
988 case GEU
: return CC0
| CC1
; /* no carry */
994 switch (GET_CODE (code
))
996 case GTU
: return CC0
| CC1
; /* borrow */
997 case LEU
: return CC2
| CC3
; /* no borrow */
1003 switch (GET_CODE (code
))
1005 case EQ
: return CC0
| CC2
;
1006 case NE
: return CC1
| CC3
;
1007 case LTU
: return CC1
;
1008 case GTU
: return CC3
;
1009 case LEU
: return CC1
| CC2
;
1010 case GEU
: return CC2
| CC3
;
1015 switch (GET_CODE (code
))
1017 case EQ
: return CC0
;
1018 case NE
: return CC1
| CC2
| CC3
;
1019 case LTU
: return CC1
;
1020 case GTU
: return CC2
;
1021 case LEU
: return CC0
| CC1
;
1022 case GEU
: return CC0
| CC2
;
1028 switch (GET_CODE (code
))
1030 case EQ
: return CC0
;
1031 case NE
: return CC2
| CC1
| CC3
;
1032 case LTU
: return CC2
;
1033 case GTU
: return CC1
;
1034 case LEU
: return CC0
| CC2
;
1035 case GEU
: return CC0
| CC1
;
1041 switch (GET_CODE (code
))
1043 case EQ
: return CC0
;
1044 case NE
: return CC1
| CC2
| CC3
;
1045 case LT
: return CC1
| CC3
;
1046 case GT
: return CC2
;
1047 case LE
: return CC0
| CC1
| CC3
;
1048 case GE
: return CC0
| CC2
;
1054 switch (GET_CODE (code
))
1056 case EQ
: return CC0
;
1057 case NE
: return CC1
| CC2
| CC3
;
1058 case LT
: return CC1
;
1059 case GT
: return CC2
| CC3
;
1060 case LE
: return CC0
| CC1
;
1061 case GE
: return CC0
| CC2
| CC3
;
1067 switch (GET_CODE (code
))
1069 case EQ
: return CC0
;
1070 case NE
: return CC1
| CC2
| CC3
;
1071 case LT
: return CC1
;
1072 case GT
: return CC2
;
1073 case LE
: return CC0
| CC1
;
1074 case GE
: return CC0
| CC2
;
1075 case UNORDERED
: return CC3
;
1076 case ORDERED
: return CC0
| CC1
| CC2
;
1077 case UNEQ
: return CC0
| CC3
;
1078 case UNLT
: return CC1
| CC3
;
1079 case UNGT
: return CC2
| CC3
;
1080 case UNLE
: return CC0
| CC1
| CC3
;
1081 case UNGE
: return CC0
| CC2
| CC3
;
1082 case LTGT
: return CC1
| CC2
;
1088 switch (GET_CODE (code
))
1090 case EQ
: return CC0
;
1091 case NE
: return CC2
| CC1
| CC3
;
1092 case LT
: return CC2
;
1093 case GT
: return CC1
;
1094 case LE
: return CC0
| CC2
;
1095 case GE
: return CC0
| CC1
;
1096 case UNORDERED
: return CC3
;
1097 case ORDERED
: return CC0
| CC2
| CC1
;
1098 case UNEQ
: return CC0
| CC3
;
1099 case UNLT
: return CC2
| CC3
;
1100 case UNGT
: return CC1
| CC3
;
1101 case UNLE
: return CC0
| CC2
| CC3
;
1102 case UNGE
: return CC0
| CC1
| CC3
;
1103 case LTGT
: return CC2
| CC1
;
1114 /* Return branch condition mask to implement a compare and branch
1115 specified by CODE. Return -1 for invalid comparisons. */
1118 s390_compare_and_branch_condition_mask (rtx code
)
1120 const int CC0
= 1 << 3;
1121 const int CC1
= 1 << 2;
1122 const int CC2
= 1 << 1;
1124 switch (GET_CODE (code
))
1148 /* If INV is false, return assembler mnemonic string to implement
1149 a branch specified by CODE. If INV is true, return mnemonic
1150 for the corresponding inverted branch. */
1153 s390_branch_condition_mnemonic (rtx code
, int inv
)
1157 static const char *const mnemonic
[16] =
1159 NULL
, "o", "h", "nle",
1160 "l", "nhe", "lh", "ne",
1161 "e", "nlh", "he", "nl",
1162 "le", "nh", "no", NULL
1165 if (GET_CODE (XEXP (code
, 0)) == REG
1166 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1167 && XEXP (code
, 1) == const0_rtx
)
1168 mask
= s390_branch_condition_mask (code
);
1170 mask
= s390_compare_and_branch_condition_mask (code
);
1172 gcc_assert (mask
>= 0);
1177 gcc_assert (mask
>= 1 && mask
<= 14);
1179 return mnemonic
[mask
];
1182 /* Return the part of op which has a value different from def.
1183 The size of the part is determined by mode.
1184 Use this function only if you already know that op really
1185 contains such a part. */
1187 unsigned HOST_WIDE_INT
1188 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1190 unsigned HOST_WIDE_INT value
= 0;
1191 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1192 int part_bits
= GET_MODE_BITSIZE (mode
);
1193 unsigned HOST_WIDE_INT part_mask
1194 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1197 for (i
= 0; i
< max_parts
; i
++)
1200 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1202 value
>>= part_bits
;
1204 if ((value
& part_mask
) != (def
& part_mask
))
1205 return value
& part_mask
;
1211 /* If OP is an integer constant of mode MODE with exactly one
1212 part of mode PART_MODE unequal to DEF, return the number of that
1213 part. Otherwise, return -1. */
1216 s390_single_part (rtx op
,
1217 enum machine_mode mode
,
1218 enum machine_mode part_mode
,
1221 unsigned HOST_WIDE_INT value
= 0;
1222 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1223 unsigned HOST_WIDE_INT part_mask
1224 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1227 if (GET_CODE (op
) != CONST_INT
)
1230 for (i
= 0; i
< n_parts
; i
++)
1233 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1235 value
>>= GET_MODE_BITSIZE (part_mode
);
1237 if ((value
& part_mask
) != (def
& part_mask
))
1245 return part
== -1 ? -1 : n_parts
- 1 - part
;
1248 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1249 bits and no other bits are set in IN. POS and LENGTH can be used
1250 to obtain the start position and the length of the bitfield.
1252 POS gives the position of the first bit of the bitfield counting
1253 from the lowest order bit starting with zero. In order to use this
1254 value for S/390 instructions this has to be converted to "bits big
1258 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1259 int *pos
, int *length
)
1264 unsigned HOST_WIDE_INT mask
= 1ULL;
1265 bool contiguous
= false;
1267 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1291 /* Calculate a mask for all bits beyond the contiguous bits. */
1292 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1297 if (tmp_length
+ tmp_pos
- 1 > size
)
1301 *length
= tmp_length
;
1309 /* Check whether we can (and want to) split a double-word
1310 move in mode MODE from SRC to DST into two single-word
1311 moves, moving the subword FIRST_SUBWORD first. */
1314 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1316 /* Floating point registers cannot be split. */
1317 if (FP_REG_P (src
) || FP_REG_P (dst
))
1320 /* We don't need to split if operands are directly accessible. */
1321 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1324 /* Non-offsettable memory references cannot be split. */
1325 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1326 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1329 /* Moving the first subword must not clobber a register
1330 needed to move the second subword. */
1331 if (register_operand (dst
, mode
))
1333 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1334 if (reg_overlap_mentioned_p (subreg
, src
))
1341 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1342 and [MEM2, MEM2 + SIZE] do overlap and false
1346 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1348 rtx addr1
, addr2
, addr_delta
;
1349 HOST_WIDE_INT delta
;
1351 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1357 addr1
= XEXP (mem1
, 0);
1358 addr2
= XEXP (mem2
, 0);
1360 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1362 /* This overlapping check is used by peepholes merging memory block operations.
1363 Overlapping operations would otherwise be recognized by the S/390 hardware
1364 and would fall back to a slower implementation. Allowing overlapping
1365 operations would lead to slow code but not to wrong code. Therefore we are
1366 somewhat optimistic if we cannot prove that the memory blocks are
1368 That's why we return false here although this may accept operations on
1369 overlapping memory areas. */
1370 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1373 delta
= INTVAL (addr_delta
);
1376 || (delta
> 0 && delta
< size
)
1377 || (delta
< 0 && -delta
< size
))
1383 /* Check whether the address of memory reference MEM2 equals exactly
1384 the address of memory reference MEM1 plus DELTA. Return true if
1385 we can prove this to be the case, false otherwise. */
1388 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1390 rtx addr1
, addr2
, addr_delta
;
1392 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1395 addr1
= XEXP (mem1
, 0);
1396 addr2
= XEXP (mem2
, 0);
1398 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1399 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1405 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1408 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1411 enum machine_mode wmode
= mode
;
1412 rtx dst
= operands
[0];
1413 rtx src1
= operands
[1];
1414 rtx src2
= operands
[2];
1417 /* If we cannot handle the operation directly, use a temp register. */
1418 if (!s390_logical_operator_ok_p (operands
))
1419 dst
= gen_reg_rtx (mode
);
1421 /* QImode and HImode patterns make sense only if we have a destination
1422 in memory. Otherwise perform the operation in SImode. */
1423 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1426 /* Widen operands if required. */
1429 if (GET_CODE (dst
) == SUBREG
1430 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1432 else if (REG_P (dst
))
1433 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1435 dst
= gen_reg_rtx (wmode
);
1437 if (GET_CODE (src1
) == SUBREG
1438 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1440 else if (GET_MODE (src1
) != VOIDmode
)
1441 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1443 if (GET_CODE (src2
) == SUBREG
1444 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1446 else if (GET_MODE (src2
) != VOIDmode
)
1447 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1450 /* Emit the instruction. */
1451 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1452 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1453 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1455 /* Fix up the destination if needed. */
1456 if (dst
!= operands
[0])
1457 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1460 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1463 s390_logical_operator_ok_p (rtx
*operands
)
1465 /* If the destination operand is in memory, it needs to coincide
1466 with one of the source operands. After reload, it has to be
1467 the first source operand. */
1468 if (GET_CODE (operands
[0]) == MEM
)
1469 return rtx_equal_p (operands
[0], operands
[1])
1470 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1475 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1476 operand IMMOP to switch from SS to SI type instructions. */
1479 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1481 int def
= code
== AND
? -1 : 0;
1485 gcc_assert (GET_CODE (*memop
) == MEM
);
1486 gcc_assert (!MEM_VOLATILE_P (*memop
));
1488 mask
= s390_extract_part (*immop
, QImode
, def
);
1489 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1490 gcc_assert (part
>= 0);
1492 *memop
= adjust_address (*memop
, QImode
, part
);
1493 *immop
= gen_int_mode (mask
, QImode
);
1497 /* How to allocate a 'struct machine_function'. */
1499 static struct machine_function
*
1500 s390_init_machine_status (void)
1502 return ggc_alloc_cleared_machine_function ();
1506 s390_option_override (void)
1508 /* Set up function hooks. */
1509 init_machine_status
= s390_init_machine_status
;
1511 /* Architecture mode defaults according to ABI. */
1512 if (!(target_flags_explicit
& MASK_ZARCH
))
1515 target_flags
|= MASK_ZARCH
;
1517 target_flags
&= ~MASK_ZARCH
;
1520 /* Set the march default in case it hasn't been specified on
1522 if (s390_arch
== PROCESSOR_max
)
1524 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1525 s390_arch
= TARGET_ZARCH
? PROCESSOR_2064_Z900
: PROCESSOR_9672_G5
;
1526 s390_arch_flags
= processor_flags_table
[(int)s390_arch
];
1529 /* Determine processor to tune for. */
1530 if (s390_tune
== PROCESSOR_max
)
1532 s390_tune
= s390_arch
;
1533 s390_tune_flags
= s390_arch_flags
;
1536 /* Sanity checks. */
1537 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1538 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1539 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1540 error ("64-bit ABI not supported in ESA/390 mode");
1542 /* Use hardware DFP if available and not explicitly disabled by
1543 user. E.g. with -m31 -march=z10 -mzarch */
1544 if (!(target_flags_explicit
& MASK_HARD_DFP
) && TARGET_DFP
)
1545 target_flags
|= MASK_HARD_DFP
;
1547 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1549 if (target_flags_explicit
& MASK_HARD_DFP
)
1551 if (!TARGET_CPU_DFP
)
1552 error ("hardware decimal floating point instructions"
1553 " not available on %s", s390_arch_string
);
1555 error ("hardware decimal floating point instructions"
1556 " not available in ESA/390 mode");
1559 target_flags
&= ~MASK_HARD_DFP
;
1562 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1564 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1565 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1567 target_flags
&= ~MASK_HARD_DFP
;
1570 /* Set processor cost function. */
1573 case PROCESSOR_2084_Z990
:
1574 s390_cost
= &z990_cost
;
1576 case PROCESSOR_2094_Z9_109
:
1577 s390_cost
= &z9_109_cost
;
1579 case PROCESSOR_2097_Z10
:
1580 s390_cost
= &z10_cost
;
1581 case PROCESSOR_2817_Z196
:
1582 s390_cost
= &z196_cost
;
1585 s390_cost
= &z900_cost
;
1588 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1589 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1592 if (s390_stack_size
)
1594 if (s390_stack_guard
>= s390_stack_size
)
1595 error ("stack size must be greater than the stack guard value");
1596 else if (s390_stack_size
> 1 << 16)
1597 error ("stack size must not be greater than 64k");
1599 else if (s390_stack_guard
)
1600 error ("-mstack-guard implies use of -mstack-size");
1602 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1603 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1604 target_flags
|= MASK_LONG_DOUBLE_128
;
1607 if (s390_tune
== PROCESSOR_2097_Z10
1608 || s390_tune
== PROCESSOR_2817_Z196
)
1610 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
1611 global_options
.x_param_values
,
1612 global_options_set
.x_param_values
);
1613 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
1614 global_options
.x_param_values
,
1615 global_options_set
.x_param_values
);
1616 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
1617 global_options
.x_param_values
,
1618 global_options_set
.x_param_values
);
1619 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
1620 global_options
.x_param_values
,
1621 global_options_set
.x_param_values
);
1624 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
1625 global_options
.x_param_values
,
1626 global_options_set
.x_param_values
);
1627 /* values for loop prefetching */
1628 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
1629 global_options
.x_param_values
,
1630 global_options_set
.x_param_values
);
1631 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
1632 global_options
.x_param_values
,
1633 global_options_set
.x_param_values
);
1634 /* s390 has more than 2 levels and the size is much larger. Since
1635 we are always running virtualized assume that we only get a small
1636 part of the caches above l1. */
1637 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
1638 global_options
.x_param_values
,
1639 global_options_set
.x_param_values
);
1640 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
1641 global_options
.x_param_values
,
1642 global_options_set
.x_param_values
);
1643 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
1644 global_options
.x_param_values
,
1645 global_options_set
.x_param_values
);
1647 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1648 requires the arch flags to be evaluated already. Since prefetching
1649 is beneficial on s390, we enable it if available. */
1650 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1651 flag_prefetch_loop_arrays
= 1;
1653 /* Use the alternative scheduling-pressure algorithm by default. */
1654 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
1655 global_options
.x_param_values
,
1656 global_options_set
.x_param_values
);
1659 /* Map for smallest class containing reg regno. */
1661 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1662 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1663 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1664 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1665 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1666 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1667 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1668 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1669 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1670 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1671 ACCESS_REGS
, ACCESS_REGS
1674 /* Return attribute type of insn. */
1676 static enum attr_type
1677 s390_safe_attr_type (rtx insn
)
1679 if (recog_memoized (insn
) >= 0)
1680 return get_attr_type (insn
);
1685 /* Return true if DISP is a valid short displacement. */
1688 s390_short_displacement (rtx disp
)
1690 /* No displacement is OK. */
1694 /* Without the long displacement facility we don't need to
1695 distingiush between long and short displacement. */
1696 if (!TARGET_LONG_DISPLACEMENT
)
1699 /* Integer displacement in range. */
1700 if (GET_CODE (disp
) == CONST_INT
)
1701 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1703 /* GOT offset is not OK, the GOT can be large. */
1704 if (GET_CODE (disp
) == CONST
1705 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1706 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1707 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1710 /* All other symbolic constants are literal pool references,
1711 which are OK as the literal pool must be small. */
1712 if (GET_CODE (disp
) == CONST
)
1718 /* Decompose a RTL expression ADDR for a memory address into
1719 its components, returned in OUT.
1721 Returns false if ADDR is not a valid memory address, true
1722 otherwise. If OUT is NULL, don't return the components,
1723 but check for validity only.
1725 Note: Only addresses in canonical form are recognized.
1726 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1727 canonical form so that they will be recognized. */
1730 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1732 HOST_WIDE_INT offset
= 0;
1733 rtx base
= NULL_RTX
;
1734 rtx indx
= NULL_RTX
;
1735 rtx disp
= NULL_RTX
;
1737 bool pointer
= false;
1738 bool base_ptr
= false;
1739 bool indx_ptr
= false;
1740 bool literal_pool
= false;
1742 /* We may need to substitute the literal pool base register into the address
1743 below. However, at this point we do not know which register is going to
1744 be used as base, so we substitute the arg pointer register. This is going
1745 to be treated as holding a pointer below -- it shouldn't be used for any
1747 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1749 /* Decompose address into base + index + displacement. */
1751 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1754 else if (GET_CODE (addr
) == PLUS
)
1756 rtx op0
= XEXP (addr
, 0);
1757 rtx op1
= XEXP (addr
, 1);
1758 enum rtx_code code0
= GET_CODE (op0
);
1759 enum rtx_code code1
= GET_CODE (op1
);
1761 if (code0
== REG
|| code0
== UNSPEC
)
1763 if (code1
== REG
|| code1
== UNSPEC
)
1765 indx
= op0
; /* index + base */
1771 base
= op0
; /* base + displacement */
1776 else if (code0
== PLUS
)
1778 indx
= XEXP (op0
, 0); /* index + base + disp */
1779 base
= XEXP (op0
, 1);
1790 disp
= addr
; /* displacement */
1792 /* Extract integer part of displacement. */
1796 if (GET_CODE (disp
) == CONST_INT
)
1798 offset
= INTVAL (disp
);
1801 else if (GET_CODE (disp
) == CONST
1802 && GET_CODE (XEXP (disp
, 0)) == PLUS
1803 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1805 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1806 disp
= XEXP (XEXP (disp
, 0), 0);
1810 /* Strip off CONST here to avoid special case tests later. */
1811 if (disp
&& GET_CODE (disp
) == CONST
)
1812 disp
= XEXP (disp
, 0);
1814 /* We can convert literal pool addresses to
1815 displacements by basing them off the base register. */
1816 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1818 /* Either base or index must be free to hold the base register. */
1820 base
= fake_pool_base
, literal_pool
= true;
1822 indx
= fake_pool_base
, literal_pool
= true;
1826 /* Mark up the displacement. */
1827 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1828 UNSPEC_LTREL_OFFSET
);
1831 /* Validate base register. */
1834 if (GET_CODE (base
) == UNSPEC
)
1835 switch (XINT (base
, 1))
1839 disp
= gen_rtx_UNSPEC (Pmode
,
1840 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1841 UNSPEC_LTREL_OFFSET
);
1845 base
= XVECEXP (base
, 0, 1);
1848 case UNSPEC_LTREL_BASE
:
1849 if (XVECLEN (base
, 0) == 1)
1850 base
= fake_pool_base
, literal_pool
= true;
1852 base
= XVECEXP (base
, 0, 1);
1860 || (GET_MODE (base
) != SImode
1861 && GET_MODE (base
) != Pmode
))
1864 if (REGNO (base
) == STACK_POINTER_REGNUM
1865 || REGNO (base
) == FRAME_POINTER_REGNUM
1866 || ((reload_completed
|| reload_in_progress
)
1867 && frame_pointer_needed
1868 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1869 || REGNO (base
) == ARG_POINTER_REGNUM
1871 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1872 pointer
= base_ptr
= true;
1874 if ((reload_completed
|| reload_in_progress
)
1875 && base
== cfun
->machine
->base_reg
)
1876 pointer
= base_ptr
= literal_pool
= true;
1879 /* Validate index register. */
1882 if (GET_CODE (indx
) == UNSPEC
)
1883 switch (XINT (indx
, 1))
1887 disp
= gen_rtx_UNSPEC (Pmode
,
1888 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1889 UNSPEC_LTREL_OFFSET
);
1893 indx
= XVECEXP (indx
, 0, 1);
1896 case UNSPEC_LTREL_BASE
:
1897 if (XVECLEN (indx
, 0) == 1)
1898 indx
= fake_pool_base
, literal_pool
= true;
1900 indx
= XVECEXP (indx
, 0, 1);
1908 || (GET_MODE (indx
) != SImode
1909 && GET_MODE (indx
) != Pmode
))
1912 if (REGNO (indx
) == STACK_POINTER_REGNUM
1913 || REGNO (indx
) == FRAME_POINTER_REGNUM
1914 || ((reload_completed
|| reload_in_progress
)
1915 && frame_pointer_needed
1916 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1917 || REGNO (indx
) == ARG_POINTER_REGNUM
1919 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1920 pointer
= indx_ptr
= true;
1922 if ((reload_completed
|| reload_in_progress
)
1923 && indx
== cfun
->machine
->base_reg
)
1924 pointer
= indx_ptr
= literal_pool
= true;
1927 /* Prefer to use pointer as base, not index. */
1928 if (base
&& indx
&& !base_ptr
1929 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1936 /* Validate displacement. */
1939 /* If virtual registers are involved, the displacement will change later
1940 anyway as the virtual registers get eliminated. This could make a
1941 valid displacement invalid, but it is more likely to make an invalid
1942 displacement valid, because we sometimes access the register save area
1943 via negative offsets to one of those registers.
1944 Thus we don't check the displacement for validity here. If after
1945 elimination the displacement turns out to be invalid after all,
1946 this is fixed up by reload in any case. */
1947 if (base
!= arg_pointer_rtx
1948 && indx
!= arg_pointer_rtx
1949 && base
!= return_address_pointer_rtx
1950 && indx
!= return_address_pointer_rtx
1951 && base
!= frame_pointer_rtx
1952 && indx
!= frame_pointer_rtx
1953 && base
!= virtual_stack_vars_rtx
1954 && indx
!= virtual_stack_vars_rtx
)
1955 if (!DISP_IN_RANGE (offset
))
1960 /* All the special cases are pointers. */
1963 /* In the small-PIC case, the linker converts @GOT
1964 and @GOTNTPOFF offsets to possible displacements. */
1965 if (GET_CODE (disp
) == UNSPEC
1966 && (XINT (disp
, 1) == UNSPEC_GOT
1967 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
1973 /* Accept pool label offsets. */
1974 else if (GET_CODE (disp
) == UNSPEC
1975 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
1978 /* Accept literal pool references. */
1979 else if (GET_CODE (disp
) == UNSPEC
1980 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
1982 /* In case CSE pulled a non literal pool reference out of
1983 the pool we have to reject the address. This is
1984 especially important when loading the GOT pointer on non
1985 zarch CPUs. In this case the literal pool contains an lt
1986 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1987 will most likely exceed the displacement. */
1988 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
1989 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
1992 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
1995 /* If we have an offset, make sure it does not
1996 exceed the size of the constant pool entry. */
1997 rtx sym
= XVECEXP (disp
, 0, 0);
1998 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2001 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
2016 out
->disp
= orig_disp
;
2017 out
->pointer
= pointer
;
2018 out
->literal_pool
= literal_pool
;
2024 /* Decompose a RTL expression OP for a shift count into its components,
2025 and return the base register in BASE and the offset in OFFSET.
2027 Return true if OP is a valid shift count, false if not. */
2030 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2032 HOST_WIDE_INT off
= 0;
2034 /* We can have an integer constant, an address register,
2035 or a sum of the two. */
2036 if (GET_CODE (op
) == CONST_INT
)
2041 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2043 off
= INTVAL (XEXP (op
, 1));
2046 while (op
&& GET_CODE (op
) == SUBREG
)
2047 op
= SUBREG_REG (op
);
2049 if (op
&& GET_CODE (op
) != REG
)
2061 /* Return true if CODE is a valid address without index. */
2064 s390_legitimate_address_without_index_p (rtx op
)
2066 struct s390_address addr
;
2068 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2077 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2078 and return these parts in SYMREF and ADDEND. You can pass NULL in
2079 SYMREF and/or ADDEND if you are not interested in these values.
2080 Literal pool references are *not* considered symbol references. */
2083 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2085 HOST_WIDE_INT tmpaddend
= 0;
2087 if (GET_CODE (addr
) == CONST
)
2088 addr
= XEXP (addr
, 0);
2090 if (GET_CODE (addr
) == PLUS
)
2092 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2093 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2094 && CONST_INT_P (XEXP (addr
, 1)))
2096 tmpaddend
= INTVAL (XEXP (addr
, 1));
2097 addr
= XEXP (addr
, 0);
2103 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2109 *addend
= tmpaddend
;
2115 /* Return true if the address in OP is valid for constraint letter C
2116 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2117 pool MEMs should be accepted. Only the Q, R, S, T constraint
2118 letters are allowed for C. */
2121 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2123 struct s390_address addr
;
2124 bool decomposed
= false;
2126 /* This check makes sure that no symbolic address (except literal
2127 pool references) are accepted by the R or T constraints. */
2128 if (s390_symref_operand_p (op
, NULL
, NULL
))
2131 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2134 if (!s390_decompose_address (op
, &addr
))
2136 if (addr
.literal_pool
)
2143 case 'Q': /* no index short displacement */
2144 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2148 if (!s390_short_displacement (addr
.disp
))
2152 case 'R': /* with index short displacement */
2153 if (TARGET_LONG_DISPLACEMENT
)
2155 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2157 if (!s390_short_displacement (addr
.disp
))
2160 /* Any invalid address here will be fixed up by reload,
2161 so accept it for the most generic constraint. */
2164 case 'S': /* no index long displacement */
2165 if (!TARGET_LONG_DISPLACEMENT
)
2167 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2171 if (s390_short_displacement (addr
.disp
))
2175 case 'T': /* with index long displacement */
2176 if (!TARGET_LONG_DISPLACEMENT
)
2178 /* Any invalid address here will be fixed up by reload,
2179 so accept it for the most generic constraint. */
2180 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2181 && s390_short_displacement (addr
.disp
))
2191 /* Evaluates constraint strings described by the regular expression
2192 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2193 the constraint given in STR, or 0 else. */
2196 s390_mem_constraint (const char *str
, rtx op
)
2203 /* Check for offsettable variants of memory constraints. */
2204 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2206 if ((reload_completed
|| reload_in_progress
)
2207 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2209 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2211 /* Check for non-literal-pool variants of memory constraints. */
2214 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2219 if (GET_CODE (op
) != MEM
)
2221 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2223 return (s390_check_qrst_address ('Q', op
, true)
2224 || s390_check_qrst_address ('R', op
, true));
2226 return (s390_check_qrst_address ('S', op
, true)
2227 || s390_check_qrst_address ('T', op
, true));
2229 /* Simply check for the basic form of a shift count. Reload will
2230 take care of making sure we have a proper base register. */
2231 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2235 return s390_check_qrst_address (str
[1], op
, true);
2243 /* Evaluates constraint strings starting with letter O. Input
2244 parameter C is the second letter following the "O" in the constraint
2245 string. Returns 1 if VALUE meets the respective constraint and 0
2249 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2257 return trunc_int_for_mode (value
, SImode
) == value
;
2261 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2264 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2272 /* Evaluates constraint strings starting with letter N. Parameter STR
2273 contains the letters following letter "N" in the constraint string.
2274 Returns true if VALUE matches the constraint. */
2277 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2279 enum machine_mode mode
, part_mode
;
2281 int part
, part_goal
;
2287 part_goal
= str
[0] - '0';
2331 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2334 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2337 if (part_goal
!= -1 && part_goal
!= part
)
2344 /* Returns true if the input parameter VALUE is a float zero. */
2347 s390_float_const_zero_p (rtx value
)
2349 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2350 && value
== CONST0_RTX (GET_MODE (value
)));
2353 /* Implement TARGET_REGISTER_MOVE_COST. */
2356 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2357 reg_class_t from
, reg_class_t to
)
2359 /* On s390, copy between fprs and gprs is expensive. */
2360 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
2361 && reg_classes_intersect_p (to
, FP_REGS
))
2362 || (reg_classes_intersect_p (from
, FP_REGS
)
2363 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
2369 /* Implement TARGET_MEMORY_MOVE_COST. */
2372 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2373 reg_class_t rclass ATTRIBUTE_UNUSED
,
2374 bool in ATTRIBUTE_UNUSED
)
2379 /* Compute a (partial) cost for rtx X. Return true if the complete
2380 cost has been computed, and false if subexpressions should be
2381 scanned. In either case, *TOTAL contains the cost result.
2382 CODE contains GET_CODE (x), OUTER_CODE contains the code
2383 of the superexpression of x. */
2386 s390_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2387 int *total
, bool speed ATTRIBUTE_UNUSED
)
2410 *total
= COSTS_N_INSNS (1);
2415 *total
= COSTS_N_INSNS (1);
2419 switch (GET_MODE (x
))
2423 rtx left
= XEXP (x
, 0);
2424 rtx right
= XEXP (x
, 1);
2425 if (GET_CODE (right
) == CONST_INT
2426 && CONST_OK_FOR_K (INTVAL (right
)))
2427 *total
= s390_cost
->mhi
;
2428 else if (GET_CODE (left
) == SIGN_EXTEND
)
2429 *total
= s390_cost
->mh
;
2431 *total
= s390_cost
->ms
; /* msr, ms, msy */
2436 rtx left
= XEXP (x
, 0);
2437 rtx right
= XEXP (x
, 1);
2440 if (GET_CODE (right
) == CONST_INT
2441 && CONST_OK_FOR_K (INTVAL (right
)))
2442 *total
= s390_cost
->mghi
;
2443 else if (GET_CODE (left
) == SIGN_EXTEND
)
2444 *total
= s390_cost
->msgf
;
2446 *total
= s390_cost
->msg
; /* msgr, msg */
2448 else /* TARGET_31BIT */
2450 if (GET_CODE (left
) == SIGN_EXTEND
2451 && GET_CODE (right
) == SIGN_EXTEND
)
2452 /* mulsidi case: mr, m */
2453 *total
= s390_cost
->m
;
2454 else if (GET_CODE (left
) == ZERO_EXTEND
2455 && GET_CODE (right
) == ZERO_EXTEND
2456 && TARGET_CPU_ZARCH
)
2457 /* umulsidi case: ml, mlr */
2458 *total
= s390_cost
->ml
;
2460 /* Complex calculation is required. */
2461 *total
= COSTS_N_INSNS (40);
2467 *total
= s390_cost
->mult_df
;
2470 *total
= s390_cost
->mxbr
;
2478 switch (GET_MODE (x
))
2481 *total
= s390_cost
->madbr
;
2484 *total
= s390_cost
->maebr
;
2489 /* Negate in the third argument is free: FMSUB. */
2490 if (GET_CODE (XEXP (x
, 2)) == NEG
)
2492 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, 0, speed
)
2493 + rtx_cost (XEXP (x
, 1), FMA
, 1, speed
)
2494 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, 2, speed
));
2501 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2502 *total
= s390_cost
->dlgr
;
2503 else if (GET_MODE (x
) == DImode
)
2505 rtx right
= XEXP (x
, 1);
2506 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2507 *total
= s390_cost
->dlr
;
2508 else /* 64 by 64 bit division */
2509 *total
= s390_cost
->dlgr
;
2511 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2512 *total
= s390_cost
->dlr
;
2517 if (GET_MODE (x
) == DImode
)
2519 rtx right
= XEXP (x
, 1);
2520 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2522 *total
= s390_cost
->dsgfr
;
2524 *total
= s390_cost
->dr
;
2525 else /* 64 by 64 bit division */
2526 *total
= s390_cost
->dsgr
;
2528 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2529 *total
= s390_cost
->dlr
;
2530 else if (GET_MODE (x
) == SFmode
)
2532 *total
= s390_cost
->debr
;
2534 else if (GET_MODE (x
) == DFmode
)
2536 *total
= s390_cost
->ddbr
;
2538 else if (GET_MODE (x
) == TFmode
)
2540 *total
= s390_cost
->dxbr
;
2545 if (GET_MODE (x
) == SFmode
)
2546 *total
= s390_cost
->sqebr
;
2547 else if (GET_MODE (x
) == DFmode
)
2548 *total
= s390_cost
->sqdbr
;
2550 *total
= s390_cost
->sqxbr
;
2555 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2556 || outer_code
== PLUS
|| outer_code
== MINUS
2557 || outer_code
== COMPARE
)
2562 *total
= COSTS_N_INSNS (1);
2563 if (GET_CODE (XEXP (x
, 0)) == AND
2564 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2565 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2567 rtx op0
= XEXP (XEXP (x
, 0), 0);
2568 rtx op1
= XEXP (XEXP (x
, 0), 1);
2569 rtx op2
= XEXP (x
, 1);
2571 if (memory_operand (op0
, GET_MODE (op0
))
2572 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2574 if (register_operand (op0
, GET_MODE (op0
))
2575 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2585 /* Return the cost of an address rtx ADDR. */
2588 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2590 struct s390_address ad
;
2591 if (!s390_decompose_address (addr
, &ad
))
2594 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2597 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2598 otherwise return 0. */
2601 tls_symbolic_operand (rtx op
)
2603 if (GET_CODE (op
) != SYMBOL_REF
)
2605 return SYMBOL_REF_TLS_MODEL (op
);
2608 /* Split DImode access register reference REG (on 64-bit) into its constituent
2609 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2610 gen_highpart cannot be used as they assume all registers are word-sized,
2611 while our access registers have only half that size. */
2614 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2616 gcc_assert (TARGET_64BIT
);
2617 gcc_assert (ACCESS_REG_P (reg
));
2618 gcc_assert (GET_MODE (reg
) == DImode
);
2619 gcc_assert (!(REGNO (reg
) & 1));
2621 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2622 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2625 /* Return true if OP contains a symbol reference */
2628 symbolic_reference_mentioned_p (rtx op
)
2633 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2636 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2637 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2643 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2644 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2648 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2655 /* Return true if OP contains a reference to a thread-local symbol. */
2658 tls_symbolic_reference_mentioned_p (rtx op
)
2663 if (GET_CODE (op
) == SYMBOL_REF
)
2664 return tls_symbolic_operand (op
);
2666 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2667 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2673 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2674 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2678 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2686 /* Return true if OP is a legitimate general operand when
2687 generating PIC code. It is given that flag_pic is on
2688 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2691 legitimate_pic_operand_p (rtx op
)
2693 /* Accept all non-symbolic constants. */
2694 if (!SYMBOLIC_CONST (op
))
2697 /* Reject everything else; must be handled
2698 via emit_symbolic_move. */
2702 /* Returns true if the constant value OP is a legitimate general operand.
2703 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2706 s390_legitimate_constant_p (enum machine_mode mode
, rtx op
)
2708 /* Accept all non-symbolic constants. */
2709 if (!SYMBOLIC_CONST (op
))
2712 /* Accept immediate LARL operands. */
2713 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
2716 /* Thread-local symbols are never legal constants. This is
2717 so that emit_call knows that computing such addresses
2718 might require a function call. */
2719 if (TLS_SYMBOLIC_CONST (op
))
2722 /* In the PIC case, symbolic constants must *not* be
2723 forced into the literal pool. We accept them here,
2724 so that they will be handled by emit_symbolic_move. */
2728 /* All remaining non-PIC symbolic constants are
2729 forced into the literal pool. */
2733 /* Determine if it's legal to put X into the constant pool. This
2734 is not possible if X contains the address of a symbol that is
2735 not constant (TLS) or not known at final link time (PIC). */
2738 s390_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2740 switch (GET_CODE (x
))
2744 /* Accept all non-symbolic constants. */
2748 /* Labels are OK iff we are non-PIC. */
2749 return flag_pic
!= 0;
2752 /* 'Naked' TLS symbol references are never OK,
2753 non-TLS symbols are OK iff we are non-PIC. */
2754 if (tls_symbolic_operand (x
))
2757 return flag_pic
!= 0;
2760 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
2763 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
2764 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
2767 switch (XINT (x
, 1))
2769 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2770 case UNSPEC_LTREL_OFFSET
:
2778 case UNSPEC_GOTNTPOFF
:
2779 case UNSPEC_INDNTPOFF
:
2782 /* If the literal pool shares the code section, be put
2783 execute template placeholders into the pool as well. */
2785 return TARGET_CPU_ZARCH
;
2797 /* Returns true if the constant value OP is a legitimate general
2798 operand during and after reload. The difference to
2799 legitimate_constant_p is that this function will not accept
2800 a constant that would need to be forced to the literal pool
2801 before it can be used as operand.
2802 This function accepts all constants which can be loaded directly
2806 legitimate_reload_constant_p (rtx op
)
2808 /* Accept la(y) operands. */
2809 if (GET_CODE (op
) == CONST_INT
2810 && DISP_IN_RANGE (INTVAL (op
)))
2813 /* Accept l(g)hi/l(g)fi operands. */
2814 if (GET_CODE (op
) == CONST_INT
2815 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2818 /* Accept lliXX operands. */
2820 && GET_CODE (op
) == CONST_INT
2821 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2822 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2826 && GET_CODE (op
) == CONST_INT
2827 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2828 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2831 /* Accept larl operands. */
2832 if (TARGET_CPU_ZARCH
2833 && larl_operand (op
, VOIDmode
))
2836 /* Accept floating-point zero operands that fit into a single GPR. */
2837 if (GET_CODE (op
) == CONST_DOUBLE
2838 && s390_float_const_zero_p (op
)
2839 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2842 /* Accept double-word operands that can be split. */
2843 if (GET_CODE (op
) == CONST_INT
2844 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2846 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2847 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2848 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2849 return legitimate_reload_constant_p (hi
)
2850 && legitimate_reload_constant_p (lo
);
2853 /* Everything else cannot be handled without reload. */
2857 /* Returns true if the constant value OP is a legitimate fp operand
2858 during and after reload.
2859 This function accepts all constants which can be loaded directly
2863 legitimate_reload_fp_constant_p (rtx op
)
2865 /* Accept floating-point zero operands if the load zero instruction
2868 && GET_CODE (op
) == CONST_DOUBLE
2869 && s390_float_const_zero_p (op
))
2875 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2876 return the class of reg to actually use. */
2879 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
2881 switch (GET_CODE (op
))
2883 /* Constants we cannot reload into general registers
2884 must be forced into the literal pool. */
2887 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2888 && legitimate_reload_constant_p (op
))
2889 return GENERAL_REGS
;
2890 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2891 && legitimate_reload_constant_p (op
))
2893 else if (reg_class_subset_p (FP_REGS
, rclass
)
2894 && legitimate_reload_fp_constant_p (op
))
2898 /* If a symbolic constant or a PLUS is reloaded,
2899 it is most likely being used as an address, so
2900 prefer ADDR_REGS. If 'class' is not a superset
2901 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2905 if (!legitimate_reload_constant_p (op
))
2909 /* load address will be used. */
2910 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2922 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2923 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2927 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2929 HOST_WIDE_INT addend
;
2932 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2935 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
2936 && !(addend
& (alignment
- 1)));
2939 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2940 operand SCRATCH is used to reload the even part of the address and
2944 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
2946 HOST_WIDE_INT addend
;
2949 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2953 /* Easy case. The addend is even so larl will do fine. */
2954 emit_move_insn (reg
, addr
);
2957 /* We can leave the scratch register untouched if the target
2958 register is a valid base register. */
2959 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
2960 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
2963 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
2964 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
2967 emit_move_insn (scratch
,
2968 gen_rtx_CONST (Pmode
,
2969 gen_rtx_PLUS (Pmode
, symref
,
2970 GEN_INT (addend
- 1))));
2972 emit_move_insn (scratch
, symref
);
2974 /* Increment the address using la in order to avoid clobbering cc. */
2975 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
2979 /* Generate what is necessary to move between REG and MEM using
2980 SCRATCH. The direction is given by TOMEM. */
2983 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
2985 /* Reload might have pulled a constant out of the literal pool.
2986 Force it back in. */
2987 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
2988 || GET_CODE (mem
) == CONST
)
2989 mem
= force_const_mem (GET_MODE (reg
), mem
);
2991 gcc_assert (MEM_P (mem
));
2993 /* For a load from memory we can leave the scratch register
2994 untouched if the target register is a valid base register. */
2996 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
2997 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
2998 && GET_MODE (reg
) == GET_MODE (scratch
))
3001 /* Load address into scratch register. Since we can't have a
3002 secondary reload for a secondary reload we have to cover the case
3003 where larl would need a secondary reload here as well. */
3004 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3006 /* Now we can use a standard load/store to do the move. */
3008 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3010 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3013 /* Inform reload about cases where moving X with a mode MODE to a register in
3014 RCLASS requires an extra scratch or immediate register. Return the class
3015 needed for the immediate register. */
3018 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3019 enum machine_mode mode
, secondary_reload_info
*sri
)
3021 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3023 /* Intermediate register needed. */
3024 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3025 return GENERAL_REGS
;
3029 HOST_WIDE_INT offset
;
3032 /* On z10 several optimizer steps may generate larl operands with
3035 && s390_symref_operand_p (x
, &symref
, &offset
)
3037 && !SYMBOL_REF_ALIGN1_P (symref
)
3038 && (offset
& 1) == 1)
3039 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3040 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3042 /* On z10 we need a scratch register when moving QI, TI or floating
3043 point mode values from or to a memory location with a SYMBOL_REF
3044 or if the symref addend of a SI or DI move is not aligned to the
3045 width of the access. */
3047 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3048 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3049 || (!TARGET_ZARCH
&& mode
== DImode
)
3050 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3051 && (!s390_check_symref_alignment (XEXP (x
, 0),
3052 GET_MODE_SIZE (mode
))))))
3054 #define __SECONDARY_RELOAD_CASE(M,m) \
3057 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3058 CODE_FOR_reload##m##di_tomem_z10; \
3060 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3061 CODE_FOR_reload##m##si_tomem_z10; \
3064 switch (GET_MODE (x
))
3066 __SECONDARY_RELOAD_CASE (QI
, qi
);
3067 __SECONDARY_RELOAD_CASE (HI
, hi
);
3068 __SECONDARY_RELOAD_CASE (SI
, si
);
3069 __SECONDARY_RELOAD_CASE (DI
, di
);
3070 __SECONDARY_RELOAD_CASE (TI
, ti
);
3071 __SECONDARY_RELOAD_CASE (SF
, sf
);
3072 __SECONDARY_RELOAD_CASE (DF
, df
);
3073 __SECONDARY_RELOAD_CASE (TF
, tf
);
3074 __SECONDARY_RELOAD_CASE (SD
, sd
);
3075 __SECONDARY_RELOAD_CASE (DD
, dd
);
3076 __SECONDARY_RELOAD_CASE (TD
, td
);
3081 #undef __SECONDARY_RELOAD_CASE
3085 /* We need a scratch register when loading a PLUS expression which
3086 is not a legitimate operand of the LOAD ADDRESS instruction. */
3087 if (in_p
&& s390_plus_operand (x
, mode
))
3088 sri
->icode
= (TARGET_64BIT
?
3089 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3091 /* Performing a multiword move from or to memory we have to make sure the
3092 second chunk in memory is addressable without causing a displacement
3093 overflow. If that would be the case we calculate the address in
3094 a scratch register. */
3096 && GET_CODE (XEXP (x
, 0)) == PLUS
3097 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3098 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3099 + GET_MODE_SIZE (mode
) - 1))
3101 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3102 in a s_operand address since we may fallback to lm/stm. So we only
3103 have to care about overflows in the b+i+d case. */
3104 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3105 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3106 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3107 /* For FP_REGS no lm/stm is available so this check is triggered
3108 for displacement overflows in b+i+d and b+d like addresses. */
3109 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3110 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3113 sri
->icode
= (TARGET_64BIT
?
3114 CODE_FOR_reloaddi_nonoffmem_in
:
3115 CODE_FOR_reloadsi_nonoffmem_in
);
3117 sri
->icode
= (TARGET_64BIT
?
3118 CODE_FOR_reloaddi_nonoffmem_out
:
3119 CODE_FOR_reloadsi_nonoffmem_out
);
3123 /* A scratch address register is needed when a symbolic constant is
3124 copied to r0 compiling with -fPIC. In other cases the target
3125 register might be used as temporary (see legitimize_pic_address). */
3126 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3127 sri
->icode
= (TARGET_64BIT
?
3128 CODE_FOR_reloaddi_PIC_addr
:
3129 CODE_FOR_reloadsi_PIC_addr
);
3131 /* Either scratch or no register needed. */
3135 /* Generate code to load SRC, which is PLUS that is not a
3136 legitimate operand for the LA instruction, into TARGET.
3137 SCRATCH may be used as scratch register. */
3140 s390_expand_plus_operand (rtx target
, rtx src
,
3144 struct s390_address ad
;
3146 /* src must be a PLUS; get its two operands. */
3147 gcc_assert (GET_CODE (src
) == PLUS
);
3148 gcc_assert (GET_MODE (src
) == Pmode
);
3150 /* Check if any of the two operands is already scheduled
3151 for replacement by reload. This can happen e.g. when
3152 float registers occur in an address. */
3153 sum1
= find_replacement (&XEXP (src
, 0));
3154 sum2
= find_replacement (&XEXP (src
, 1));
3155 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3157 /* If the address is already strictly valid, there's nothing to do. */
3158 if (!s390_decompose_address (src
, &ad
)
3159 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3160 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3162 /* Otherwise, one of the operands cannot be an address register;
3163 we reload its value into the scratch register. */
3164 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3166 emit_move_insn (scratch
, sum1
);
3169 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3171 emit_move_insn (scratch
, sum2
);
3175 /* According to the way these invalid addresses are generated
3176 in reload.c, it should never happen (at least on s390) that
3177 *neither* of the PLUS components, after find_replacements
3178 was applied, is an address register. */
3179 if (sum1
== scratch
&& sum2
== scratch
)
3185 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3188 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3189 is only ever performed on addresses, so we can mark the
3190 sum as legitimate for LA in any case. */
3191 s390_load_address (target
, src
);
3195 /* Return true if ADDR is a valid memory address.
3196 STRICT specifies whether strict register checking applies. */
3199 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3201 struct s390_address ad
;
3204 && larl_operand (addr
, VOIDmode
)
3205 && (mode
== VOIDmode
3206 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3209 if (!s390_decompose_address (addr
, &ad
))
3214 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3217 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3223 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3224 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3228 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3229 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3235 /* Return true if OP is a valid operand for the LA instruction.
3236 In 31-bit, we need to prove that the result is used as an
3237 address, as LA performs only a 31-bit addition. */
3240 legitimate_la_operand_p (rtx op
)
3242 struct s390_address addr
;
3243 if (!s390_decompose_address (op
, &addr
))
3246 return (TARGET_64BIT
|| addr
.pointer
);
3249 /* Return true if it is valid *and* preferable to use LA to
3250 compute the sum of OP1 and OP2. */
3253 preferred_la_operand_p (rtx op1
, rtx op2
)
3255 struct s390_address addr
;
3257 if (op2
!= const0_rtx
)
3258 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3260 if (!s390_decompose_address (op1
, &addr
))
3262 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3264 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3267 /* Avoid LA instructions with index register on z196; it is
3268 preferable to use regular add instructions when possible. */
3269 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3272 if (!TARGET_64BIT
&& !addr
.pointer
)
3278 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3279 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3285 /* Emit a forced load-address operation to load SRC into DST.
3286 This will use the LOAD ADDRESS instruction even in situations
3287 where legitimate_la_operand_p (SRC) returns false. */
3290 s390_load_address (rtx dst
, rtx src
)
3293 emit_move_insn (dst
, src
);
3295 emit_insn (gen_force_la_31 (dst
, src
));
3298 /* Return a legitimate reference for ORIG (an address) using the
3299 register REG. If REG is 0, a new pseudo is generated.
3301 There are two types of references that must be handled:
3303 1. Global data references must load the address from the GOT, via
3304 the PIC reg. An insn is emitted to do this load, and the reg is
3307 2. Static data references, constant pool addresses, and code labels
3308 compute the address as an offset from the GOT, whose base is in
3309 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3310 differentiate them from global data objects. The returned
3311 address is the PIC reg + an unspec constant.
3313 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3314 reg also appears in the address. */
3317 legitimize_pic_address (rtx orig
, rtx reg
)
3323 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3325 if (GET_CODE (addr
) == LABEL_REF
3326 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3328 /* This is a local symbol. */
3329 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3331 /* Access local symbols PC-relative via LARL.
3332 This is the same as in the non-PIC case, so it is
3333 handled automatically ... */
3337 /* Access local symbols relative to the GOT. */
3339 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3341 if (reload_in_progress
|| reload_completed
)
3342 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3344 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3345 addr
= gen_rtx_CONST (Pmode
, addr
);
3346 addr
= force_const_mem (Pmode
, addr
);
3347 emit_move_insn (temp
, addr
);
3349 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3352 s390_load_address (reg
, new_rtx
);
3357 else if (GET_CODE (addr
) == SYMBOL_REF
)
3360 reg
= gen_reg_rtx (Pmode
);
3364 /* Assume GOT offset < 4k. This is handled the same way
3365 in both 31- and 64-bit code (@GOT). */
3367 if (reload_in_progress
|| reload_completed
)
3368 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3370 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3371 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3372 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3373 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3374 emit_move_insn (reg
, new_rtx
);
3377 else if (TARGET_CPU_ZARCH
)
3379 /* If the GOT offset might be >= 4k, we determine the position
3380 of the GOT entry via a PC-relative LARL (@GOTENT). */
3382 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3384 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3385 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3387 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3388 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3389 emit_move_insn (temp
, new_rtx
);
3391 new_rtx
= gen_const_mem (Pmode
, temp
);
3392 emit_move_insn (reg
, new_rtx
);
3397 /* If the GOT offset might be >= 4k, we have to load it
3398 from the literal pool (@GOT). */
3400 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3402 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3403 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3405 if (reload_in_progress
|| reload_completed
)
3406 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3408 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3409 addr
= gen_rtx_CONST (Pmode
, addr
);
3410 addr
= force_const_mem (Pmode
, addr
);
3411 emit_move_insn (temp
, addr
);
3413 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3414 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3415 emit_move_insn (reg
, new_rtx
);
3421 if (GET_CODE (addr
) == CONST
)
3423 addr
= XEXP (addr
, 0);
3424 if (GET_CODE (addr
) == UNSPEC
)
3426 gcc_assert (XVECLEN (addr
, 0) == 1);
3427 switch (XINT (addr
, 1))
3429 /* If someone moved a GOT-relative UNSPEC
3430 out of the literal pool, force them back in. */
3433 new_rtx
= force_const_mem (Pmode
, orig
);
3436 /* @GOT is OK as is if small. */
3439 new_rtx
= force_const_mem (Pmode
, orig
);
3442 /* @GOTENT is OK as is. */
3446 /* @PLT is OK as is on 64-bit, must be converted to
3447 GOT-relative @PLTOFF on 31-bit. */
3449 if (!TARGET_CPU_ZARCH
)
3451 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3453 if (reload_in_progress
|| reload_completed
)
3454 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3456 addr
= XVECEXP (addr
, 0, 0);
3457 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3459 addr
= gen_rtx_CONST (Pmode
, addr
);
3460 addr
= force_const_mem (Pmode
, addr
);
3461 emit_move_insn (temp
, addr
);
3463 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3466 s390_load_address (reg
, new_rtx
);
3472 /* Everything else cannot happen. */
3478 gcc_assert (GET_CODE (addr
) == PLUS
);
3480 if (GET_CODE (addr
) == PLUS
)
3482 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3484 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3485 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3487 /* Check first to see if this is a constant offset
3488 from a local symbol reference. */
3489 if ((GET_CODE (op0
) == LABEL_REF
3490 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3491 && GET_CODE (op1
) == CONST_INT
)
3493 if (TARGET_CPU_ZARCH
3494 && larl_operand (op0
, VOIDmode
)
3495 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3496 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3498 if (INTVAL (op1
) & 1)
3500 /* LARL can't handle odd offsets, so emit a
3501 pair of LARL and LA. */
3502 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3504 if (!DISP_IN_RANGE (INTVAL (op1
)))
3506 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3507 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3508 op0
= gen_rtx_CONST (Pmode
, op0
);
3512 emit_move_insn (temp
, op0
);
3513 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3517 s390_load_address (reg
, new_rtx
);
3523 /* If the offset is even, we can just use LARL.
3524 This will happen automatically. */
3529 /* Access local symbols relative to the GOT. */
3531 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3533 if (reload_in_progress
|| reload_completed
)
3534 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3536 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3538 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3539 addr
= gen_rtx_CONST (Pmode
, addr
);
3540 addr
= force_const_mem (Pmode
, addr
);
3541 emit_move_insn (temp
, addr
);
3543 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3546 s390_load_address (reg
, new_rtx
);
3552 /* Now, check whether it is a GOT relative symbol plus offset
3553 that was pulled out of the literal pool. Force it back in. */
3555 else if (GET_CODE (op0
) == UNSPEC
3556 && GET_CODE (op1
) == CONST_INT
3557 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3559 gcc_assert (XVECLEN (op0
, 0) == 1);
3561 new_rtx
= force_const_mem (Pmode
, orig
);
3564 /* Otherwise, compute the sum. */
3567 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3568 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3569 base
== reg
? NULL_RTX
: reg
);
3570 if (GET_CODE (new_rtx
) == CONST_INT
)
3571 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
3574 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3576 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3577 new_rtx
= XEXP (new_rtx
, 1);
3579 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3582 if (GET_CODE (new_rtx
) == CONST
)
3583 new_rtx
= XEXP (new_rtx
, 0);
3584 new_rtx
= force_operand (new_rtx
, 0);
3591 /* Load the thread pointer into a register. */
3594 s390_get_thread_pointer (void)
3596 rtx tp
= gen_reg_rtx (Pmode
);
3598 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3599 mark_reg_pointer (tp
, BITS_PER_WORD
);
3604 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3605 in s390_tls_symbol which always refers to __tls_get_offset.
3606 The returned offset is written to RESULT_REG and an USE rtx is
3607 generated for TLS_CALL. */
3609 static GTY(()) rtx s390_tls_symbol
;
3612 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3617 emit_insn (s390_load_got ());
3619 if (!s390_tls_symbol
)
3620 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3622 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3623 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3625 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3626 RTL_CONST_CALL_P (insn
) = 1;
3629 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3630 this (thread-local) address. REG may be used as temporary. */
3633 legitimize_tls_address (rtx addr
, rtx reg
)
3635 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3637 if (GET_CODE (addr
) == SYMBOL_REF
)
3638 switch (tls_symbolic_operand (addr
))
3640 case TLS_MODEL_GLOBAL_DYNAMIC
:
3642 r2
= gen_rtx_REG (Pmode
, 2);
3643 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3644 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3645 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3646 emit_move_insn (r2
, new_rtx
);
3647 s390_emit_tls_call_insn (r2
, tls_call
);
3648 insn
= get_insns ();
3651 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3652 temp
= gen_reg_rtx (Pmode
);
3653 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3655 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3658 s390_load_address (reg
, new_rtx
);
3663 case TLS_MODEL_LOCAL_DYNAMIC
:
3665 r2
= gen_rtx_REG (Pmode
, 2);
3666 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3667 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3668 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3669 emit_move_insn (r2
, new_rtx
);
3670 s390_emit_tls_call_insn (r2
, tls_call
);
3671 insn
= get_insns ();
3674 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3675 temp
= gen_reg_rtx (Pmode
);
3676 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3678 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3679 base
= gen_reg_rtx (Pmode
);
3680 s390_load_address (base
, new_rtx
);
3682 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3683 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3684 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3685 temp
= gen_reg_rtx (Pmode
);
3686 emit_move_insn (temp
, new_rtx
);
3688 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3691 s390_load_address (reg
, new_rtx
);
3696 case TLS_MODEL_INITIAL_EXEC
:
3699 /* Assume GOT offset < 4k. This is handled the same way
3700 in both 31- and 64-bit code. */
3702 if (reload_in_progress
|| reload_completed
)
3703 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3705 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3706 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3707 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3708 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3709 temp
= gen_reg_rtx (Pmode
);
3710 emit_move_insn (temp
, new_rtx
);
3712 else if (TARGET_CPU_ZARCH
)
3714 /* If the GOT offset might be >= 4k, we determine the position
3715 of the GOT entry via a PC-relative LARL. */
3717 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3718 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3719 temp
= gen_reg_rtx (Pmode
);
3720 emit_move_insn (temp
, new_rtx
);
3722 new_rtx
= gen_const_mem (Pmode
, temp
);
3723 temp
= gen_reg_rtx (Pmode
);
3724 emit_move_insn (temp
, new_rtx
);
3728 /* If the GOT offset might be >= 4k, we have to load it
3729 from the literal pool. */
3731 if (reload_in_progress
|| reload_completed
)
3732 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3734 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3735 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3736 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3737 temp
= gen_reg_rtx (Pmode
);
3738 emit_move_insn (temp
, new_rtx
);
3740 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3741 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3743 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3744 temp
= gen_reg_rtx (Pmode
);
3745 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3749 /* In position-dependent code, load the absolute address of
3750 the GOT entry from the literal pool. */
3752 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3753 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3754 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3755 temp
= gen_reg_rtx (Pmode
);
3756 emit_move_insn (temp
, new_rtx
);
3759 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3760 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3761 temp
= gen_reg_rtx (Pmode
);
3762 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3765 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3768 s390_load_address (reg
, new_rtx
);
3773 case TLS_MODEL_LOCAL_EXEC
:
3774 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3775 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3776 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3777 temp
= gen_reg_rtx (Pmode
);
3778 emit_move_insn (temp
, new_rtx
);
3780 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3783 s390_load_address (reg
, new_rtx
);
3792 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3794 switch (XINT (XEXP (addr
, 0), 1))
3796 case UNSPEC_INDNTPOFF
:
3797 gcc_assert (TARGET_CPU_ZARCH
);
3806 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3807 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3809 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3810 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3811 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3813 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3814 new_rtx
= plus_constant (Pmode
, new_rtx
,
3815 INTVAL (XEXP (XEXP (addr
, 0), 1)));
3816 new_rtx
= force_operand (new_rtx
, 0);
3820 gcc_unreachable (); /* for now ... */
3825 /* Emit insns making the address in operands[1] valid for a standard
3826 move to operands[0]. operands[1] is replaced by an address which
3827 should be used instead of the former RTX to emit the move
3831 emit_symbolic_move (rtx
*operands
)
3833 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3835 if (GET_CODE (operands
[0]) == MEM
)
3836 operands
[1] = force_reg (Pmode
, operands
[1]);
3837 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3838 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3840 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3843 /* Try machine-dependent ways of modifying an illegitimate address X
3844 to be legitimate. If we find one, return the new, valid address.
3846 OLDX is the address as it was before break_out_memory_refs was called.
3847 In some cases it is useful to look at this to decide what needs to be done.
3849 MODE is the mode of the operand pointed to by X.
3851 When -fpic is used, special handling is needed for symbolic references.
3852 See comments by legitimize_pic_address for details. */
3855 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3856 enum machine_mode mode ATTRIBUTE_UNUSED
)
3858 rtx constant_term
= const0_rtx
;
3860 if (TLS_SYMBOLIC_CONST (x
))
3862 x
= legitimize_tls_address (x
, 0);
3864 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3867 else if (GET_CODE (x
) == PLUS
3868 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3869 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3875 if (SYMBOLIC_CONST (x
)
3876 || (GET_CODE (x
) == PLUS
3877 && (SYMBOLIC_CONST (XEXP (x
, 0))
3878 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3879 x
= legitimize_pic_address (x
, 0);
3881 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3885 x
= eliminate_constant_term (x
, &constant_term
);
3887 /* Optimize loading of large displacements by splitting them
3888 into the multiple of 4K and the rest; this allows the
3889 former to be CSE'd if possible.
3891 Don't do this if the displacement is added to a register
3892 pointing into the stack frame, as the offsets will
3893 change later anyway. */
3895 if (GET_CODE (constant_term
) == CONST_INT
3896 && !TARGET_LONG_DISPLACEMENT
3897 && !DISP_IN_RANGE (INTVAL (constant_term
))
3898 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3900 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3901 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3903 rtx temp
= gen_reg_rtx (Pmode
);
3904 rtx val
= force_operand (GEN_INT (upper
), temp
);
3906 emit_move_insn (temp
, val
);
3908 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3909 constant_term
= GEN_INT (lower
);
3912 if (GET_CODE (x
) == PLUS
)
3914 if (GET_CODE (XEXP (x
, 0)) == REG
)
3916 rtx temp
= gen_reg_rtx (Pmode
);
3917 rtx val
= force_operand (XEXP (x
, 1), temp
);
3919 emit_move_insn (temp
, val
);
3921 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3924 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3926 rtx temp
= gen_reg_rtx (Pmode
);
3927 rtx val
= force_operand (XEXP (x
, 0), temp
);
3929 emit_move_insn (temp
, val
);
3931 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3935 if (constant_term
!= const0_rtx
)
3936 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3941 /* Try a machine-dependent way of reloading an illegitimate address AD
3942 operand. If we find one, push the reload and return the new address.
3944 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3945 and TYPE is the reload type of the current reload. */
3948 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3949 int opnum
, int type
)
3951 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3954 if (GET_CODE (ad
) == PLUS
)
3956 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3957 XEXP (ad
, 0), XEXP (ad
, 1));
3962 if (GET_CODE (ad
) == PLUS
3963 && GET_CODE (XEXP (ad
, 0)) == REG
3964 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3965 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3967 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3968 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3969 rtx cst
, tem
, new_rtx
;
3971 cst
= GEN_INT (upper
);
3972 if (!legitimate_reload_constant_p (cst
))
3973 cst
= force_const_mem (Pmode
, cst
);
3975 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3976 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3978 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3979 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3980 opnum
, (enum reload_type
) type
);
3987 /* Emit code to move LEN bytes from DST to SRC. */
3990 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
3992 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3994 if (INTVAL (len
) > 0)
3995 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
3998 else if (TARGET_MVCLE
)
4000 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4005 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4006 rtx loop_start_label
= gen_label_rtx ();
4007 rtx loop_end_label
= gen_label_rtx ();
4008 rtx end_label
= gen_label_rtx ();
4009 enum machine_mode mode
;
4011 mode
= GET_MODE (len
);
4012 if (mode
== VOIDmode
)
4015 dst_addr
= gen_reg_rtx (Pmode
);
4016 src_addr
= gen_reg_rtx (Pmode
);
4017 count
= gen_reg_rtx (mode
);
4018 blocks
= gen_reg_rtx (mode
);
4020 convert_move (count
, len
, 1);
4021 emit_cmp_and_jump_insns (count
, const0_rtx
,
4022 EQ
, NULL_RTX
, mode
, 1, end_label
);
4024 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4025 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4026 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4027 src
= change_address (src
, VOIDmode
, src_addr
);
4029 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4032 emit_move_insn (count
, temp
);
4034 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4037 emit_move_insn (blocks
, temp
);
4039 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4040 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4042 emit_label (loop_start_label
);
4045 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4049 /* Issue a read prefetch for the +3 cache line. */
4050 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4051 const0_rtx
, const0_rtx
);
4052 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4053 emit_insn (prefetch
);
4055 /* Issue a write prefetch for the +3 cache line. */
4056 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4057 const1_rtx
, const0_rtx
);
4058 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4059 emit_insn (prefetch
);
4062 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4063 s390_load_address (dst_addr
,
4064 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4065 s390_load_address (src_addr
,
4066 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4068 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4071 emit_move_insn (blocks
, temp
);
4073 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4074 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4076 emit_jump (loop_start_label
);
4077 emit_label (loop_end_label
);
4079 emit_insn (gen_movmem_short (dst
, src
,
4080 convert_to_mode (Pmode
, count
, 1)));
4081 emit_label (end_label
);
4085 /* Emit code to set LEN bytes at DST to VAL.
4086 Make use of clrmem if VAL is zero. */
4089 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4091 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4094 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4096 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4098 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4099 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4102 /* Initialize memory by storing the first byte. */
4103 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4105 if (INTVAL (len
) > 1)
4107 /* Initiate 1 byte overlap move.
4108 The first byte of DST is propagated through DSTP1.
4109 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4110 DST is set to size 1 so the rest of the memory location
4111 does not count as source operand. */
4112 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4113 set_mem_size (dst
, 1);
4115 emit_insn (gen_movmem_short (dstp1
, dst
,
4116 GEN_INT (INTVAL (len
) - 2)));
4121 else if (TARGET_MVCLE
)
4123 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4124 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4129 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4130 rtx loop_start_label
= gen_label_rtx ();
4131 rtx loop_end_label
= gen_label_rtx ();
4132 rtx end_label
= gen_label_rtx ();
4133 enum machine_mode mode
;
4135 mode
= GET_MODE (len
);
4136 if (mode
== VOIDmode
)
4139 dst_addr
= gen_reg_rtx (Pmode
);
4140 count
= gen_reg_rtx (mode
);
4141 blocks
= gen_reg_rtx (mode
);
4143 convert_move (count
, len
, 1);
4144 emit_cmp_and_jump_insns (count
, const0_rtx
,
4145 EQ
, NULL_RTX
, mode
, 1, end_label
);
4147 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4148 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4150 if (val
== const0_rtx
)
4151 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4155 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4156 set_mem_size (dst
, 1);
4158 /* Initialize memory by storing the first byte. */
4159 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4161 /* If count is 1 we are done. */
4162 emit_cmp_and_jump_insns (count
, const1_rtx
,
4163 EQ
, NULL_RTX
, mode
, 1, end_label
);
4165 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4169 emit_move_insn (count
, temp
);
4171 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4174 emit_move_insn (blocks
, temp
);
4176 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4177 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4179 emit_label (loop_start_label
);
4182 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4184 /* Issue a write prefetch for the +4 cache line. */
4185 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4187 const1_rtx
, const0_rtx
);
4188 emit_insn (prefetch
);
4189 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4192 if (val
== const0_rtx
)
4193 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4195 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4196 s390_load_address (dst_addr
,
4197 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4199 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4202 emit_move_insn (blocks
, temp
);
4204 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4205 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4207 emit_jump (loop_start_label
);
4208 emit_label (loop_end_label
);
4210 if (val
== const0_rtx
)
4211 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4213 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4214 emit_label (end_label
);
4218 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4219 and return the result in TARGET. */
4222 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4224 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4227 /* As the result of CMPINT is inverted compared to what we need,
4228 we have to swap the operands. */
4229 tmp
= op0
; op0
= op1
; op1
= tmp
;
4231 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4233 if (INTVAL (len
) > 0)
4235 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4236 emit_insn (gen_cmpint (target
, ccreg
));
4239 emit_move_insn (target
, const0_rtx
);
4241 else if (TARGET_MVCLE
)
4243 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4244 emit_insn (gen_cmpint (target
, ccreg
));
4248 rtx addr0
, addr1
, count
, blocks
, temp
;
4249 rtx loop_start_label
= gen_label_rtx ();
4250 rtx loop_end_label
= gen_label_rtx ();
4251 rtx end_label
= gen_label_rtx ();
4252 enum machine_mode mode
;
4254 mode
= GET_MODE (len
);
4255 if (mode
== VOIDmode
)
4258 addr0
= gen_reg_rtx (Pmode
);
4259 addr1
= gen_reg_rtx (Pmode
);
4260 count
= gen_reg_rtx (mode
);
4261 blocks
= gen_reg_rtx (mode
);
4263 convert_move (count
, len
, 1);
4264 emit_cmp_and_jump_insns (count
, const0_rtx
,
4265 EQ
, NULL_RTX
, mode
, 1, end_label
);
4267 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4268 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4269 op0
= change_address (op0
, VOIDmode
, addr0
);
4270 op1
= change_address (op1
, VOIDmode
, addr1
);
4272 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4275 emit_move_insn (count
, temp
);
4277 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4280 emit_move_insn (blocks
, temp
);
4282 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4283 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4285 emit_label (loop_start_label
);
4288 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4292 /* Issue a read prefetch for the +2 cache line of operand 1. */
4293 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4294 const0_rtx
, const0_rtx
);
4295 emit_insn (prefetch
);
4296 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4298 /* Issue a read prefetch for the +2 cache line of operand 2. */
4299 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4300 const0_rtx
, const0_rtx
);
4301 emit_insn (prefetch
);
4302 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4305 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4306 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4307 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4308 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4309 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4310 emit_jump_insn (temp
);
4312 s390_load_address (addr0
,
4313 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4314 s390_load_address (addr1
,
4315 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4317 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4320 emit_move_insn (blocks
, temp
);
4322 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4323 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4325 emit_jump (loop_start_label
);
4326 emit_label (loop_end_label
);
4328 emit_insn (gen_cmpmem_short (op0
, op1
,
4329 convert_to_mode (Pmode
, count
, 1)));
4330 emit_label (end_label
);
4332 emit_insn (gen_cmpint (target
, ccreg
));
4337 /* Expand conditional increment or decrement using alc/slb instructions.
4338 Should generate code setting DST to either SRC or SRC + INCREMENT,
4339 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4340 Returns true if successful, false otherwise.
4342 That makes it possible to implement some if-constructs without jumps e.g.:
4343 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4344 unsigned int a, b, c;
4345 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4346 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4347 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4348 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4350 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4351 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4352 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4353 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4354 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4357 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4358 rtx dst
, rtx src
, rtx increment
)
4360 enum machine_mode cmp_mode
;
4361 enum machine_mode cc_mode
;
4367 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4368 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4370 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4371 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4376 /* Try ADD LOGICAL WITH CARRY. */
4377 if (increment
== const1_rtx
)
4379 /* Determine CC mode to use. */
4380 if (cmp_code
== EQ
|| cmp_code
== NE
)
4382 if (cmp_op1
!= const0_rtx
)
4384 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4385 NULL_RTX
, 0, OPTAB_WIDEN
);
4386 cmp_op1
= const0_rtx
;
4389 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4392 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4397 cmp_code
= swap_condition (cmp_code
);
4414 /* Emit comparison instruction pattern. */
4415 if (!register_operand (cmp_op0
, cmp_mode
))
4416 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4418 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4419 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4420 /* We use insn_invalid_p here to add clobbers if required. */
4421 ret
= insn_invalid_p (emit_insn (insn
), false);
4424 /* Emit ALC instruction pattern. */
4425 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4426 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4429 if (src
!= const0_rtx
)
4431 if (!register_operand (src
, GET_MODE (dst
)))
4432 src
= force_reg (GET_MODE (dst
), src
);
4434 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4435 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4438 p
= rtvec_alloc (2);
4440 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4442 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4443 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4448 /* Try SUBTRACT LOGICAL WITH BORROW. */
4449 if (increment
== constm1_rtx
)
4451 /* Determine CC mode to use. */
4452 if (cmp_code
== EQ
|| cmp_code
== NE
)
4454 if (cmp_op1
!= const0_rtx
)
4456 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4457 NULL_RTX
, 0, OPTAB_WIDEN
);
4458 cmp_op1
= const0_rtx
;
4461 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4464 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4469 cmp_code
= swap_condition (cmp_code
);
4486 /* Emit comparison instruction pattern. */
4487 if (!register_operand (cmp_op0
, cmp_mode
))
4488 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4490 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4491 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4492 /* We use insn_invalid_p here to add clobbers if required. */
4493 ret
= insn_invalid_p (emit_insn (insn
), false);
4496 /* Emit SLB instruction pattern. */
4497 if (!register_operand (src
, GET_MODE (dst
)))
4498 src
= force_reg (GET_MODE (dst
), src
);
4500 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4501 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4502 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4503 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4505 p
= rtvec_alloc (2);
4507 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4509 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4510 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4518 /* Expand code for the insv template. Return true if successful. */
4521 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4523 int bitsize
= INTVAL (op1
);
4524 int bitpos
= INTVAL (op2
);
4526 /* On z10 we can use the risbg instruction to implement insv. */
4528 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4529 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4534 op
= gen_rtx_SET (GET_MODE(src
),
4535 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4537 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4538 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4543 /* We need byte alignment. */
4544 if (bitsize
% BITS_PER_UNIT
)
4548 && memory_operand (dest
, VOIDmode
)
4549 && (register_operand (src
, word_mode
)
4550 || const_int_operand (src
, VOIDmode
)))
4552 /* Emit standard pattern if possible. */
4553 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4554 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4555 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4557 /* (set (ze (mem)) (const_int)). */
4558 else if (const_int_operand (src
, VOIDmode
))
4560 int size
= bitsize
/ BITS_PER_UNIT
;
4561 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4562 GET_MODE_SIZE (word_mode
) - size
);
4564 dest
= adjust_address (dest
, BLKmode
, 0);
4565 set_mem_size (dest
, size
);
4566 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4569 /* (set (ze (mem)) (reg)). */
4570 else if (register_operand (src
, word_mode
))
4572 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4573 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4577 /* Emit st,stcmh sequence. */
4578 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4579 int size
= stcmh_width
/ BITS_PER_UNIT
;
4581 emit_move_insn (adjust_address (dest
, SImode
, size
),
4582 gen_lowpart (SImode
, src
));
4583 set_mem_size (dest
, size
);
4584 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4585 (stcmh_width
), const0_rtx
),
4586 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4587 (GET_MODE_BITSIZE (SImode
))));
4596 /* (set (ze (reg)) (const_int)). */
4598 && register_operand (dest
, word_mode
)
4599 && (bitpos
% 16) == 0
4600 && (bitsize
% 16) == 0
4601 && const_int_operand (src
, VOIDmode
))
4603 HOST_WIDE_INT val
= INTVAL (src
);
4604 int regpos
= bitpos
+ bitsize
;
4606 while (regpos
> bitpos
)
4608 enum machine_mode putmode
;
4611 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4616 putsize
= GET_MODE_BITSIZE (putmode
);
4618 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4621 gen_int_mode (val
, putmode
));
4624 gcc_assert (regpos
== bitpos
);
4631 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4632 register that holds VAL of mode MODE shifted by COUNT bits. */
4635 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4637 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4638 NULL_RTX
, 1, OPTAB_DIRECT
);
4639 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4640 NULL_RTX
, 1, OPTAB_DIRECT
);
4643 /* Structure to hold the initial parameters for a compare_and_swap operation
4644 in HImode and QImode. */
4646 struct alignment_context
4648 rtx memsi
; /* SI aligned memory location. */
4649 rtx shift
; /* Bit offset with regard to lsb. */
4650 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4651 rtx modemaski
; /* ~modemask */
4652 bool aligned
; /* True if memory is aligned, false else. */
4655 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4656 structure AC for transparent simplifying, if the memory alignment is known
4657 to be at least 32bit. MEM is the memory location for the actual operation
4658 and MODE its mode. */
4661 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4662 enum machine_mode mode
)
4664 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4665 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4668 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4671 /* Alignment is unknown. */
4672 rtx byteoffset
, addr
, align
;
4674 /* Force the address into a register. */
4675 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4677 /* Align it to SImode. */
4678 align
= expand_simple_binop (Pmode
, AND
, addr
,
4679 GEN_INT (-GET_MODE_SIZE (SImode
)),
4680 NULL_RTX
, 1, OPTAB_DIRECT
);
4682 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4683 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4684 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4685 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4687 /* Calculate shiftcount. */
4688 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4689 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4690 NULL_RTX
, 1, OPTAB_DIRECT
);
4691 /* As we already have some offset, evaluate the remaining distance. */
4692 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4693 NULL_RTX
, 1, OPTAB_DIRECT
);
4696 /* Shift is the byte count, but we need the bitcount. */
4697 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4698 NULL_RTX
, 1, OPTAB_DIRECT
);
4699 /* Calculate masks. */
4700 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4701 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4702 NULL_RTX
, 1, OPTAB_DIRECT
);
4703 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4706 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4707 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4708 to set if CMP == MEM.
4709 CMP is never in memory for compare_and_swap_cc because
4710 expand_bool_compare_and_swap puts it into a register for later compare. */
4713 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4715 struct alignment_context ac
;
4716 rtx cmpv
, newv
, val
, resv
, cc
;
4717 rtx res
= gen_reg_rtx (SImode
);
4718 rtx csloop
= gen_label_rtx ();
4719 rtx csend
= gen_label_rtx ();
4721 gcc_assert (register_operand (target
, VOIDmode
));
4722 gcc_assert (MEM_P (mem
));
4724 init_alignment_context (&ac
, mem
, mode
);
4726 /* Shift the values to the correct bit positions. */
4727 if (!(ac
.aligned
&& MEM_P (cmp
)))
4728 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4729 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4730 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4732 /* Load full word. Subsequent loads are performed by CS. */
4733 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4734 NULL_RTX
, 1, OPTAB_DIRECT
);
4736 /* Start CS loop. */
4737 emit_label (csloop
);
4738 /* val = "<mem>00..0<mem>"
4739 * cmp = "00..0<cmp>00..0"
4740 * new = "00..0<new>00..0"
4743 /* Patch cmp and new with val at correct position. */
4744 if (ac
.aligned
&& MEM_P (cmp
))
4746 cmpv
= force_reg (SImode
, val
);
4747 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0,
4751 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4752 NULL_RTX
, 1, OPTAB_DIRECT
));
4753 if (ac
.aligned
&& MEM_P (new_rtx
))
4755 newv
= force_reg (SImode
, val
);
4756 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0,
4757 0, 0, SImode
, new_rtx
);
4760 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4761 NULL_RTX
, 1, OPTAB_DIRECT
));
4763 /* Jump to end if we're done (likely?). */
4764 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4767 /* Check for changes outside mode. */
4768 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4769 NULL_RTX
, 1, OPTAB_DIRECT
);
4770 cc
= s390_emit_compare (NE
, resv
, val
);
4771 emit_move_insn (val
, resv
);
4772 /* Loop internal if so. */
4773 s390_emit_jump (csloop
, cc
);
4777 /* Return the correct part of the bitfield. */
4778 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4779 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4782 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4783 and VAL the value to play with. If AFTER is true then store the value
4784 MEM holds after the operation, if AFTER is false then store the value MEM
4785 holds before the operation. If TARGET is zero then discard that value, else
4786 store it to TARGET. */
4789 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4790 rtx target
, rtx mem
, rtx val
, bool after
)
4792 struct alignment_context ac
;
4794 rtx new_rtx
= gen_reg_rtx (SImode
);
4795 rtx orig
= gen_reg_rtx (SImode
);
4796 rtx csloop
= gen_label_rtx ();
4798 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4799 gcc_assert (MEM_P (mem
));
4801 init_alignment_context (&ac
, mem
, mode
);
4803 /* Shift val to the correct bit positions.
4804 Preserve "icm", but prevent "ex icm". */
4805 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4806 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4808 /* Further preparation insns. */
4809 if (code
== PLUS
|| code
== MINUS
)
4810 emit_move_insn (orig
, val
);
4811 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4812 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4813 NULL_RTX
, 1, OPTAB_DIRECT
);
4815 /* Load full word. Subsequent loads are performed by CS. */
4816 cmp
= force_reg (SImode
, ac
.memsi
);
4818 /* Start CS loop. */
4819 emit_label (csloop
);
4820 emit_move_insn (new_rtx
, cmp
);
4822 /* Patch new with val at correct position. */
4827 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4828 NULL_RTX
, 1, OPTAB_DIRECT
);
4829 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4830 NULL_RTX
, 1, OPTAB_DIRECT
);
4833 if (ac
.aligned
&& MEM_P (val
))
4834 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
4838 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4839 NULL_RTX
, 1, OPTAB_DIRECT
);
4840 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4841 NULL_RTX
, 1, OPTAB_DIRECT
);
4847 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4848 NULL_RTX
, 1, OPTAB_DIRECT
);
4850 case MULT
: /* NAND */
4851 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4852 NULL_RTX
, 1, OPTAB_DIRECT
);
4853 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4854 NULL_RTX
, 1, OPTAB_DIRECT
);
4860 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4861 ac
.memsi
, cmp
, new_rtx
));
4863 /* Return the correct part of the bitfield. */
4865 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4866 after
? new_rtx
: cmp
, ac
.shift
,
4867 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4870 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4871 We need to emit DTP-relative relocations. */
4873 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4876 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4881 fputs ("\t.long\t", file
);
4884 fputs ("\t.quad\t", file
);
4889 output_addr_const (file
, x
);
4890 fputs ("@DTPOFF", file
);
4893 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4894 /* Implement TARGET_MANGLE_TYPE. */
4897 s390_mangle_type (const_tree type
)
4899 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4900 && TARGET_LONG_DOUBLE_128
)
4903 /* For all other types, use normal C++ mangling. */
4908 /* In the name of slightly smaller debug output, and to cater to
4909 general assembler lossage, recognize various UNSPEC sequences
4910 and turn them back into a direct symbol reference. */
4913 s390_delegitimize_address (rtx orig_x
)
4917 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4920 /* Extract the symbol ref from:
4921 (plus:SI (reg:SI 12 %r12)
4922 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4923 UNSPEC_GOTOFF/PLTOFF)))
4925 (plus:SI (reg:SI 12 %r12)
4926 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4927 UNSPEC_GOTOFF/PLTOFF)
4928 (const_int 4 [0x4])))) */
4929 if (GET_CODE (x
) == PLUS
4930 && REG_P (XEXP (x
, 0))
4931 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4932 && GET_CODE (XEXP (x
, 1)) == CONST
)
4934 HOST_WIDE_INT offset
= 0;
4936 /* The const operand. */
4937 y
= XEXP (XEXP (x
, 1), 0);
4939 if (GET_CODE (y
) == PLUS
4940 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
4942 offset
= INTVAL (XEXP (y
, 1));
4946 if (GET_CODE (y
) == UNSPEC
4947 && (XINT (y
, 1) == UNSPEC_GOTOFF
4948 || XINT (y
, 1) == UNSPEC_PLTOFF
))
4949 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
4952 if (GET_CODE (x
) != MEM
)
4956 if (GET_CODE (x
) == PLUS
4957 && GET_CODE (XEXP (x
, 1)) == CONST
4958 && GET_CODE (XEXP (x
, 0)) == REG
4959 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4961 y
= XEXP (XEXP (x
, 1), 0);
4962 if (GET_CODE (y
) == UNSPEC
4963 && XINT (y
, 1) == UNSPEC_GOT
)
4964 y
= XVECEXP (y
, 0, 0);
4968 else if (GET_CODE (x
) == CONST
)
4970 /* Extract the symbol ref from:
4971 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
4972 UNSPEC_PLT/GOTENT))) */
4975 if (GET_CODE (y
) == UNSPEC
4976 && (XINT (y
, 1) == UNSPEC_GOTENT
4977 || XINT (y
, 1) == UNSPEC_PLT
))
4978 y
= XVECEXP (y
, 0, 0);
4985 if (GET_MODE (orig_x
) != Pmode
)
4987 if (GET_MODE (orig_x
) == BLKmode
)
4989 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
4996 /* Output operand OP to stdio stream FILE.
4997 OP is an address (register + offset) which is not used to address data;
4998 instead the rightmost bits are interpreted as the value. */
5001 print_shift_count_operand (FILE *file
, rtx op
)
5003 HOST_WIDE_INT offset
;
5006 /* Extract base register and offset. */
5007 if (!s390_decompose_shift_count (op
, &base
, &offset
))
5013 gcc_assert (GET_CODE (base
) == REG
);
5014 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
5015 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5018 /* Offsets are constricted to twelve bits. */
5019 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5021 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5024 /* See 'get_some_local_dynamic_name'. */
5027 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5031 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
5033 x
= get_pool_constant (x
);
5034 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
5037 if (GET_CODE (x
) == SYMBOL_REF
5038 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5040 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5047 /* Locate some local-dynamic symbol still in use by this function
5048 so that we can print its name in local-dynamic base patterns. */
5051 get_some_local_dynamic_name (void)
5055 if (cfun
->machine
->some_ld_name
)
5056 return cfun
->machine
->some_ld_name
;
5058 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5060 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5061 return cfun
->machine
->some_ld_name
;
5066 /* Output machine-dependent UNSPECs occurring in address constant X
5067 in assembler syntax to stdio stream FILE. Returns true if the
5068 constant X could be recognized, false otherwise. */
5071 s390_output_addr_const_extra (FILE *file
, rtx x
)
5073 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5074 switch (XINT (x
, 1))
5077 output_addr_const (file
, XVECEXP (x
, 0, 0));
5078 fprintf (file
, "@GOTENT");
5081 output_addr_const (file
, XVECEXP (x
, 0, 0));
5082 fprintf (file
, "@GOT");
5085 output_addr_const (file
, XVECEXP (x
, 0, 0));
5086 fprintf (file
, "@GOTOFF");
5089 output_addr_const (file
, XVECEXP (x
, 0, 0));
5090 fprintf (file
, "@PLT");
5093 output_addr_const (file
, XVECEXP (x
, 0, 0));
5094 fprintf (file
, "@PLTOFF");
5097 output_addr_const (file
, XVECEXP (x
, 0, 0));
5098 fprintf (file
, "@TLSGD");
5101 assemble_name (file
, get_some_local_dynamic_name ());
5102 fprintf (file
, "@TLSLDM");
5105 output_addr_const (file
, XVECEXP (x
, 0, 0));
5106 fprintf (file
, "@DTPOFF");
5109 output_addr_const (file
, XVECEXP (x
, 0, 0));
5110 fprintf (file
, "@NTPOFF");
5112 case UNSPEC_GOTNTPOFF
:
5113 output_addr_const (file
, XVECEXP (x
, 0, 0));
5114 fprintf (file
, "@GOTNTPOFF");
5116 case UNSPEC_INDNTPOFF
:
5117 output_addr_const (file
, XVECEXP (x
, 0, 0));
5118 fprintf (file
, "@INDNTPOFF");
5122 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5123 switch (XINT (x
, 1))
5125 case UNSPEC_POOL_OFFSET
:
5126 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5127 output_addr_const (file
, x
);
5133 /* Output address operand ADDR in assembler syntax to
5134 stdio stream FILE. */
5137 print_operand_address (FILE *file
, rtx addr
)
5139 struct s390_address ad
;
5141 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5145 output_operand_lossage ("symbolic memory references are "
5146 "only supported on z10 or later");
5149 output_addr_const (file
, addr
);
5153 if (!s390_decompose_address (addr
, &ad
)
5154 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5155 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5156 output_operand_lossage ("cannot decompose address");
5159 output_addr_const (file
, ad
.disp
);
5161 fprintf (file
, "0");
5163 if (ad
.base
&& ad
.indx
)
5164 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5165 reg_names
[REGNO (ad
.base
)]);
5167 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5170 /* Output operand X in assembler syntax to stdio stream FILE.
5171 CODE specified the format flag. The following format flags
5174 'C': print opcode suffix for branch condition.
5175 'D': print opcode suffix for inverse branch condition.
5176 'E': print opcode suffix for branch on index instruction.
5177 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5178 'G': print the size of the operand in bytes.
5179 'O': print only the displacement of a memory reference.
5180 'R': print only the base register of a memory reference.
5181 'S': print S-type memory reference (base+displacement).
5182 'N': print the second word of a DImode operand.
5183 'M': print the second word of a TImode operand.
5184 'Y': print shift count operand.
5186 'b': print integer X as if it's an unsigned byte.
5187 'c': print integer X as if it's an signed byte.
5188 'x': print integer X as if it's an unsigned halfword.
5189 'h': print integer X as if it's a signed halfword.
5190 'i': print the first nonzero HImode part of X.
5191 'j': print the first HImode part unequal to -1 of X.
5192 'k': print the first nonzero SImode part of X.
5193 'm': print the first SImode part unequal to -1 of X.
5194 'o': print integer X as if it's an unsigned 32bit word. */
5197 print_operand (FILE *file
, rtx x
, int code
)
5202 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5206 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5210 if (GET_CODE (x
) == LE
)
5211 fprintf (file
, "l");
5212 else if (GET_CODE (x
) == GT
)
5213 fprintf (file
, "h");
5215 output_operand_lossage ("invalid comparison operator "
5216 "for 'E' output modifier");
5220 if (GET_CODE (x
) == SYMBOL_REF
)
5222 fprintf (file
, "%s", ":tls_load:");
5223 output_addr_const (file
, x
);
5225 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5227 fprintf (file
, "%s", ":tls_gdcall:");
5228 output_addr_const (file
, XVECEXP (x
, 0, 0));
5230 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5232 fprintf (file
, "%s", ":tls_ldcall:");
5233 assemble_name (file
, get_some_local_dynamic_name ());
5236 output_operand_lossage ("invalid reference for 'J' output modifier");
5240 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5245 struct s390_address ad
;
5250 output_operand_lossage ("memory reference expected for "
5251 "'O' output modifier");
5255 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5258 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5261 output_operand_lossage ("invalid address for 'O' output modifier");
5266 output_addr_const (file
, ad
.disp
);
5268 fprintf (file
, "0");
5274 struct s390_address ad
;
5279 output_operand_lossage ("memory reference expected for "
5280 "'R' output modifier");
5284 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5287 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5290 output_operand_lossage ("invalid address for 'R' output modifier");
5295 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5297 fprintf (file
, "0");
5303 struct s390_address ad
;
5308 output_operand_lossage ("memory reference expected for "
5309 "'S' output modifier");
5312 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5315 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5318 output_operand_lossage ("invalid address for 'S' output modifier");
5323 output_addr_const (file
, ad
.disp
);
5325 fprintf (file
, "0");
5328 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5333 if (GET_CODE (x
) == REG
)
5334 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5335 else if (GET_CODE (x
) == MEM
)
5336 x
= change_address (x
, VOIDmode
,
5337 plus_constant (Pmode
, XEXP (x
, 0), 4));
5339 output_operand_lossage ("register or memory expression expected "
5340 "for 'N' output modifier");
5344 if (GET_CODE (x
) == REG
)
5345 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5346 else if (GET_CODE (x
) == MEM
)
5347 x
= change_address (x
, VOIDmode
,
5348 plus_constant (Pmode
, XEXP (x
, 0), 8));
5350 output_operand_lossage ("register or memory expression expected "
5351 "for 'M' output modifier");
5355 print_shift_count_operand (file
, x
);
5359 switch (GET_CODE (x
))
5362 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5366 output_address (XEXP (x
, 0));
5373 output_addr_const (file
, x
);
5378 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5379 else if (code
== 'c')
5380 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5381 else if (code
== 'x')
5382 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5383 else if (code
== 'h')
5384 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5385 else if (code
== 'i')
5386 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5387 s390_extract_part (x
, HImode
, 0));
5388 else if (code
== 'j')
5389 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5390 s390_extract_part (x
, HImode
, -1));
5391 else if (code
== 'k')
5392 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5393 s390_extract_part (x
, SImode
, 0));
5394 else if (code
== 'm')
5395 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5396 s390_extract_part (x
, SImode
, -1));
5397 else if (code
== 'o')
5398 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5400 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5404 gcc_assert (GET_MODE (x
) == VOIDmode
);
5406 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5407 else if (code
== 'x')
5408 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5409 else if (code
== 'h')
5410 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5411 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5415 output_operand_lossage ("invalid constant - try using "
5416 "an output modifier");
5418 output_operand_lossage ("invalid constant for output modifier '%c'",
5425 output_operand_lossage ("invalid expression - try using "
5426 "an output modifier");
5428 output_operand_lossage ("invalid expression for output "
5429 "modifier '%c'", code
);
5434 /* Target hook for assembling integer objects. We need to define it
5435 here to work a round a bug in some versions of GAS, which couldn't
5436 handle values smaller than INT_MIN when printed in decimal. */
5439 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5441 if (size
== 8 && aligned_p
5442 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5444 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5448 return default_assemble_integer (x
, size
, aligned_p
);
5451 /* Returns true if register REGNO is used for forming
5452 a memory address in expression X. */
5455 reg_used_in_mem_p (int regno
, rtx x
)
5457 enum rtx_code code
= GET_CODE (x
);
5463 if (refers_to_regno_p (regno
, regno
+1,
5467 else if (code
== SET
5468 && GET_CODE (SET_DEST (x
)) == PC
)
5470 if (refers_to_regno_p (regno
, regno
+1,
5475 fmt
= GET_RTX_FORMAT (code
);
5476 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5479 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5482 else if (fmt
[i
] == 'E')
5483 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5484 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5490 /* Returns true if expression DEP_RTX sets an address register
5491 used by instruction INSN to address memory. */
5494 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5498 if (GET_CODE (dep_rtx
) == INSN
)
5499 dep_rtx
= PATTERN (dep_rtx
);
5501 if (GET_CODE (dep_rtx
) == SET
)
5503 target
= SET_DEST (dep_rtx
);
5504 if (GET_CODE (target
) == STRICT_LOW_PART
)
5505 target
= XEXP (target
, 0);
5506 while (GET_CODE (target
) == SUBREG
)
5507 target
= SUBREG_REG (target
);
5509 if (GET_CODE (target
) == REG
)
5511 int regno
= REGNO (target
);
5513 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5515 pat
= PATTERN (insn
);
5516 if (GET_CODE (pat
) == PARALLEL
)
5518 gcc_assert (XVECLEN (pat
, 0) == 2);
5519 pat
= XVECEXP (pat
, 0, 0);
5521 gcc_assert (GET_CODE (pat
) == SET
);
5522 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5524 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5525 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5531 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5534 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5536 rtx dep_rtx
= PATTERN (dep_insn
);
5539 if (GET_CODE (dep_rtx
) == SET
5540 && addr_generation_dependency_p (dep_rtx
, insn
))
5542 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5544 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5546 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5554 /* A C statement (sans semicolon) to update the integer scheduling priority
5555 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5556 reduce the priority to execute INSN later. Do not define this macro if
5557 you do not need to adjust the scheduling priorities of insns.
5559 A STD instruction should be scheduled earlier,
5560 in order to use the bypass. */
5562 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5564 if (! INSN_P (insn
))
5567 if (s390_tune
!= PROCESSOR_2084_Z990
5568 && s390_tune
!= PROCESSOR_2094_Z9_109
5569 && s390_tune
!= PROCESSOR_2097_Z10
5570 && s390_tune
!= PROCESSOR_2817_Z196
)
5573 switch (s390_safe_attr_type (insn
))
5577 priority
= priority
<< 3;
5581 priority
= priority
<< 1;
5590 /* The number of instructions that can be issued per cycle. */
5593 s390_issue_rate (void)
5597 case PROCESSOR_2084_Z990
:
5598 case PROCESSOR_2094_Z9_109
:
5599 case PROCESSOR_2817_Z196
:
5601 case PROCESSOR_2097_Z10
:
5609 s390_first_cycle_multipass_dfa_lookahead (void)
5614 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5615 Fix up MEMs as required. */
5618 annotate_constant_pool_refs (rtx
*x
)
5623 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5624 || !CONSTANT_POOL_ADDRESS_P (*x
));
5626 /* Literal pool references can only occur inside a MEM ... */
5627 if (GET_CODE (*x
) == MEM
)
5629 rtx memref
= XEXP (*x
, 0);
5631 if (GET_CODE (memref
) == SYMBOL_REF
5632 && CONSTANT_POOL_ADDRESS_P (memref
))
5634 rtx base
= cfun
->machine
->base_reg
;
5635 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5638 *x
= replace_equiv_address (*x
, addr
);
5642 if (GET_CODE (memref
) == CONST
5643 && GET_CODE (XEXP (memref
, 0)) == PLUS
5644 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5645 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5646 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5648 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5649 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5650 rtx base
= cfun
->machine
->base_reg
;
5651 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5654 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
5659 /* ... or a load-address type pattern. */
5660 if (GET_CODE (*x
) == SET
)
5662 rtx addrref
= SET_SRC (*x
);
5664 if (GET_CODE (addrref
) == SYMBOL_REF
5665 && CONSTANT_POOL_ADDRESS_P (addrref
))
5667 rtx base
= cfun
->machine
->base_reg
;
5668 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5671 SET_SRC (*x
) = addr
;
5675 if (GET_CODE (addrref
) == CONST
5676 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5677 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5678 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5679 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5681 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5682 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5683 rtx base
= cfun
->machine
->base_reg
;
5684 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5687 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
5692 /* Annotate LTREL_BASE as well. */
5693 if (GET_CODE (*x
) == UNSPEC
5694 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5696 rtx base
= cfun
->machine
->base_reg
;
5697 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5702 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5703 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5707 annotate_constant_pool_refs (&XEXP (*x
, i
));
5709 else if (fmt
[i
] == 'E')
5711 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5712 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5717 /* Split all branches that exceed the maximum distance.
5718 Returns true if this created a new literal pool entry. */
5721 s390_split_branches (void)
5723 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5724 int new_literal
= 0, ret
;
5725 rtx insn
, pat
, tmp
, target
;
5728 /* We need correct insn addresses. */
5730 shorten_branches (get_insns ());
5732 /* Find all branches that exceed 64KB, and split them. */
5734 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5736 if (GET_CODE (insn
) != JUMP_INSN
)
5739 pat
= PATTERN (insn
);
5740 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5741 pat
= XVECEXP (pat
, 0, 0);
5742 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5745 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5747 label
= &SET_SRC (pat
);
5749 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5751 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5752 label
= &XEXP (SET_SRC (pat
), 1);
5753 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5754 label
= &XEXP (SET_SRC (pat
), 2);
5761 if (get_attr_length (insn
) <= 4)
5764 /* We are going to use the return register as scratch register,
5765 make sure it will be saved/restored by the prologue/epilogue. */
5766 cfun_frame_layout
.save_return_addr_p
= 1;
5771 tmp
= force_const_mem (Pmode
, *label
);
5772 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5773 INSN_ADDRESSES_NEW (tmp
, -1);
5774 annotate_constant_pool_refs (&PATTERN (tmp
));
5781 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5782 UNSPEC_LTREL_OFFSET
);
5783 target
= gen_rtx_CONST (Pmode
, target
);
5784 target
= force_const_mem (Pmode
, target
);
5785 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5786 INSN_ADDRESSES_NEW (tmp
, -1);
5787 annotate_constant_pool_refs (&PATTERN (tmp
));
5789 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5790 cfun
->machine
->base_reg
),
5792 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5795 ret
= validate_change (insn
, label
, target
, 0);
5803 /* Find an annotated literal pool symbol referenced in RTX X,
5804 and store it at REF. Will abort if X contains references to
5805 more than one such pool symbol; multiple references to the same
5806 symbol are allowed, however.
5808 The rtx pointed to by REF must be initialized to NULL_RTX
5809 by the caller before calling this routine. */
5812 find_constant_pool_ref (rtx x
, rtx
*ref
)
5817 /* Ignore LTREL_BASE references. */
5818 if (GET_CODE (x
) == UNSPEC
5819 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5821 /* Likewise POOL_ENTRY insns. */
5822 if (GET_CODE (x
) == UNSPEC_VOLATILE
5823 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5826 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5827 || !CONSTANT_POOL_ADDRESS_P (x
));
5829 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5831 rtx sym
= XVECEXP (x
, 0, 0);
5832 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5833 && CONSTANT_POOL_ADDRESS_P (sym
));
5835 if (*ref
== NULL_RTX
)
5838 gcc_assert (*ref
== sym
);
5843 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5844 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5848 find_constant_pool_ref (XEXP (x
, i
), ref
);
5850 else if (fmt
[i
] == 'E')
5852 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5853 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5858 /* Replace every reference to the annotated literal pool
5859 symbol REF in X by its base plus OFFSET. */
5862 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5867 gcc_assert (*x
!= ref
);
5869 if (GET_CODE (*x
) == UNSPEC
5870 && XINT (*x
, 1) == UNSPEC_LTREF
5871 && XVECEXP (*x
, 0, 0) == ref
)
5873 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5877 if (GET_CODE (*x
) == PLUS
5878 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5879 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5880 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5881 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5883 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5884 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
5888 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5889 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5893 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5895 else if (fmt
[i
] == 'E')
5897 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5898 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5903 /* Check whether X contains an UNSPEC_LTREL_BASE.
5904 Return its constant pool symbol if found, NULL_RTX otherwise. */
5907 find_ltrel_base (rtx x
)
5912 if (GET_CODE (x
) == UNSPEC
5913 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5914 return XVECEXP (x
, 0, 0);
5916 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5917 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5921 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5925 else if (fmt
[i
] == 'E')
5927 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5929 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5939 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5942 replace_ltrel_base (rtx
*x
)
5947 if (GET_CODE (*x
) == UNSPEC
5948 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5950 *x
= XVECEXP (*x
, 0, 1);
5954 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5955 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5959 replace_ltrel_base (&XEXP (*x
, i
));
5961 else if (fmt
[i
] == 'E')
5963 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5964 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5970 /* We keep a list of constants which we have to add to internal
5971 constant tables in the middle of large functions. */
5973 #define NR_C_MODES 11
5974 enum machine_mode constant_modes
[NR_C_MODES
] =
5976 TFmode
, TImode
, TDmode
,
5977 DFmode
, DImode
, DDmode
,
5978 SFmode
, SImode
, SDmode
,
5985 struct constant
*next
;
5990 struct constant_pool
5992 struct constant_pool
*next
;
5996 rtx emit_pool_after
;
5998 struct constant
*constants
[NR_C_MODES
];
5999 struct constant
*execute
;
6004 /* Allocate new constant_pool structure. */
6006 static struct constant_pool
*
6007 s390_alloc_pool (void)
6009 struct constant_pool
*pool
;
6012 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
6014 for (i
= 0; i
< NR_C_MODES
; i
++)
6015 pool
->constants
[i
] = NULL
;
6017 pool
->execute
= NULL
;
6018 pool
->label
= gen_label_rtx ();
6019 pool
->first_insn
= NULL_RTX
;
6020 pool
->pool_insn
= NULL_RTX
;
6021 pool
->insns
= BITMAP_ALLOC (NULL
);
6023 pool
->emit_pool_after
= NULL_RTX
;
6028 /* Create new constant pool covering instructions starting at INSN
6029 and chain it to the end of POOL_LIST. */
6031 static struct constant_pool
*
6032 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
6034 struct constant_pool
*pool
, **prev
;
6036 pool
= s390_alloc_pool ();
6037 pool
->first_insn
= insn
;
6039 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
6046 /* End range of instructions covered by POOL at INSN and emit
6047 placeholder insn representing the pool. */
6050 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
6052 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
6055 insn
= get_last_insn ();
6057 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
6058 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6061 /* Add INSN to the list of insns covered by POOL. */
6064 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
6066 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
6069 /* Return pool out of POOL_LIST that covers INSN. */
6071 static struct constant_pool
*
6072 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6074 struct constant_pool
*pool
;
6076 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6077 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6083 /* Add constant VAL of mode MODE to the constant pool POOL. */
6086 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
6091 for (i
= 0; i
< NR_C_MODES
; i
++)
6092 if (constant_modes
[i
] == mode
)
6094 gcc_assert (i
!= NR_C_MODES
);
6096 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6097 if (rtx_equal_p (val
, c
->value
))
6102 c
= (struct constant
*) xmalloc (sizeof *c
);
6104 c
->label
= gen_label_rtx ();
6105 c
->next
= pool
->constants
[i
];
6106 pool
->constants
[i
] = c
;
6107 pool
->size
+= GET_MODE_SIZE (mode
);
6111 /* Return an rtx that represents the offset of X from the start of
6115 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6119 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6120 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6121 UNSPEC_POOL_OFFSET
);
6122 return gen_rtx_CONST (GET_MODE (x
), x
);
6125 /* Find constant VAL of mode MODE in the constant pool POOL.
6126 Return an RTX describing the distance from the start of
6127 the pool to the location of the new constant. */
6130 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6131 enum machine_mode mode
)
6136 for (i
= 0; i
< NR_C_MODES
; i
++)
6137 if (constant_modes
[i
] == mode
)
6139 gcc_assert (i
!= NR_C_MODES
);
6141 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6142 if (rtx_equal_p (val
, c
->value
))
6147 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6150 /* Check whether INSN is an execute. Return the label_ref to its
6151 execute target template if so, NULL_RTX otherwise. */
6154 s390_execute_label (rtx insn
)
6156 if (GET_CODE (insn
) == INSN
6157 && GET_CODE (PATTERN (insn
)) == PARALLEL
6158 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6159 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6160 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6165 /* Add execute target for INSN to the constant pool POOL. */
6168 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6172 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6173 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6178 c
= (struct constant
*) xmalloc (sizeof *c
);
6180 c
->label
= gen_label_rtx ();
6181 c
->next
= pool
->execute
;
6187 /* Find execute target for INSN in the constant pool POOL.
6188 Return an RTX describing the distance from the start of
6189 the pool to the location of the execute target. */
6192 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6196 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6197 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6202 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6205 /* For an execute INSN, extract the execute target template. */
6208 s390_execute_target (rtx insn
)
6210 rtx pattern
= PATTERN (insn
);
6211 gcc_assert (s390_execute_label (insn
));
6213 if (XVECLEN (pattern
, 0) == 2)
6215 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6219 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6222 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6223 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6225 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6231 /* Indicate that INSN cannot be duplicated. This is the case for
6232 execute insns that carry a unique label. */
6235 s390_cannot_copy_insn_p (rtx insn
)
6237 rtx label
= s390_execute_label (insn
);
6238 return label
&& label
!= const0_rtx
;
6241 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6242 do not emit the pool base label. */
6245 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6248 rtx insn
= pool
->pool_insn
;
6251 /* Switch to rodata section. */
6252 if (TARGET_CPU_ZARCH
)
6254 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6255 INSN_ADDRESSES_NEW (insn
, -1);
6258 /* Ensure minimum pool alignment. */
6259 if (TARGET_CPU_ZARCH
)
6260 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6262 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6263 INSN_ADDRESSES_NEW (insn
, -1);
6265 /* Emit pool base label. */
6268 insn
= emit_label_after (pool
->label
, insn
);
6269 INSN_ADDRESSES_NEW (insn
, -1);
6272 /* Dump constants in descending alignment requirement order,
6273 ensuring proper alignment for every constant. */
6274 for (i
= 0; i
< NR_C_MODES
; i
++)
6275 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6277 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6278 rtx value
= copy_rtx (c
->value
);
6279 if (GET_CODE (value
) == CONST
6280 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6281 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6282 && XVECLEN (XEXP (value
, 0), 0) == 1)
6283 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6285 insn
= emit_label_after (c
->label
, insn
);
6286 INSN_ADDRESSES_NEW (insn
, -1);
6288 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6289 gen_rtvec (1, value
),
6290 UNSPECV_POOL_ENTRY
);
6291 insn
= emit_insn_after (value
, insn
);
6292 INSN_ADDRESSES_NEW (insn
, -1);
6295 /* Ensure minimum alignment for instructions. */
6296 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6297 INSN_ADDRESSES_NEW (insn
, -1);
6299 /* Output in-pool execute template insns. */
6300 for (c
= pool
->execute
; c
; c
= c
->next
)
6302 insn
= emit_label_after (c
->label
, insn
);
6303 INSN_ADDRESSES_NEW (insn
, -1);
6305 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6306 INSN_ADDRESSES_NEW (insn
, -1);
6309 /* Switch back to previous section. */
6310 if (TARGET_CPU_ZARCH
)
6312 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6313 INSN_ADDRESSES_NEW (insn
, -1);
6316 insn
= emit_barrier_after (insn
);
6317 INSN_ADDRESSES_NEW (insn
, -1);
6319 /* Remove placeholder insn. */
6320 remove_insn (pool
->pool_insn
);
6323 /* Free all memory used by POOL. */
6326 s390_free_pool (struct constant_pool
*pool
)
6328 struct constant
*c
, *next
;
6331 for (i
= 0; i
< NR_C_MODES
; i
++)
6332 for (c
= pool
->constants
[i
]; c
; c
= next
)
6338 for (c
= pool
->execute
; c
; c
= next
)
6344 BITMAP_FREE (pool
->insns
);
6349 /* Collect main literal pool. Return NULL on overflow. */
6351 static struct constant_pool
*
6352 s390_mainpool_start (void)
6354 struct constant_pool
*pool
;
6357 pool
= s390_alloc_pool ();
6359 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6361 if (GET_CODE (insn
) == INSN
6362 && GET_CODE (PATTERN (insn
)) == SET
6363 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6364 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6366 gcc_assert (!pool
->pool_insn
);
6367 pool
->pool_insn
= insn
;
6370 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6372 s390_add_execute (pool
, insn
);
6374 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6376 rtx pool_ref
= NULL_RTX
;
6377 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6380 rtx constant
= get_pool_constant (pool_ref
);
6381 enum machine_mode mode
= get_pool_mode (pool_ref
);
6382 s390_add_constant (pool
, constant
, mode
);
6386 /* If hot/cold partitioning is enabled we have to make sure that
6387 the literal pool is emitted in the same section where the
6388 initialization of the literal pool base pointer takes place.
6389 emit_pool_after is only used in the non-overflow case on non
6390 Z cpus where we can emit the literal pool at the end of the
6391 function body within the text section. */
6393 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6394 && !pool
->emit_pool_after
)
6395 pool
->emit_pool_after
= PREV_INSN (insn
);
6398 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6400 if (pool
->size
>= 4096)
6402 /* We're going to chunkify the pool, so remove the main
6403 pool placeholder insn. */
6404 remove_insn (pool
->pool_insn
);
6406 s390_free_pool (pool
);
6410 /* If the functions ends with the section where the literal pool
6411 should be emitted set the marker to its end. */
6412 if (pool
&& !pool
->emit_pool_after
)
6413 pool
->emit_pool_after
= get_last_insn ();
6418 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6419 Modify the current function to output the pool constants as well as
6420 the pool register setup instruction. */
6423 s390_mainpool_finish (struct constant_pool
*pool
)
6425 rtx base_reg
= cfun
->machine
->base_reg
;
6428 /* If the pool is empty, we're done. */
6429 if (pool
->size
== 0)
6431 /* We don't actually need a base register after all. */
6432 cfun
->machine
->base_reg
= NULL_RTX
;
6434 if (pool
->pool_insn
)
6435 remove_insn (pool
->pool_insn
);
6436 s390_free_pool (pool
);
6440 /* We need correct insn addresses. */
6441 shorten_branches (get_insns ());
6443 /* On zSeries, we use a LARL to load the pool register. The pool is
6444 located in the .rodata section, so we emit it after the function. */
6445 if (TARGET_CPU_ZARCH
)
6447 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6448 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6449 INSN_ADDRESSES_NEW (insn
, -1);
6450 remove_insn (pool
->pool_insn
);
6452 insn
= get_last_insn ();
6453 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6454 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6456 s390_dump_pool (pool
, 0);
6459 /* On S/390, if the total size of the function's code plus literal pool
6460 does not exceed 4096 bytes, we use BASR to set up a function base
6461 pointer, and emit the literal pool at the end of the function. */
6462 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6463 + pool
->size
+ 8 /* alignment slop */ < 4096)
6465 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6466 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6467 INSN_ADDRESSES_NEW (insn
, -1);
6468 remove_insn (pool
->pool_insn
);
6470 insn
= emit_label_after (pool
->label
, insn
);
6471 INSN_ADDRESSES_NEW (insn
, -1);
6473 /* emit_pool_after will be set by s390_mainpool_start to the
6474 last insn of the section where the literal pool should be
6476 insn
= pool
->emit_pool_after
;
6478 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6479 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6481 s390_dump_pool (pool
, 1);
6484 /* Otherwise, we emit an inline literal pool and use BASR to branch
6485 over it, setting up the pool register at the same time. */
6488 rtx pool_end
= gen_label_rtx ();
6490 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6491 insn
= emit_jump_insn_after (insn
, pool
->pool_insn
);
6492 JUMP_LABEL (insn
) = pool_end
;
6493 INSN_ADDRESSES_NEW (insn
, -1);
6494 remove_insn (pool
->pool_insn
);
6496 insn
= emit_label_after (pool
->label
, insn
);
6497 INSN_ADDRESSES_NEW (insn
, -1);
6499 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6500 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6502 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6503 INSN_ADDRESSES_NEW (insn
, -1);
6505 s390_dump_pool (pool
, 1);
6509 /* Replace all literal pool references. */
6511 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6514 replace_ltrel_base (&PATTERN (insn
));
6516 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6518 rtx addr
, pool_ref
= NULL_RTX
;
6519 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6522 if (s390_execute_label (insn
))
6523 addr
= s390_find_execute (pool
, insn
);
6525 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6526 get_pool_mode (pool_ref
));
6528 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6529 INSN_CODE (insn
) = -1;
6535 /* Free the pool. */
6536 s390_free_pool (pool
);
6539 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6540 We have decided we cannot use this pool, so revert all changes
6541 to the current function that were done by s390_mainpool_start. */
6543 s390_mainpool_cancel (struct constant_pool
*pool
)
6545 /* We didn't actually change the instruction stream, so simply
6546 free the pool memory. */
6547 s390_free_pool (pool
);
6551 /* Chunkify the literal pool. */
6553 #define S390_POOL_CHUNK_MIN 0xc00
6554 #define S390_POOL_CHUNK_MAX 0xe00
6556 static struct constant_pool
*
6557 s390_chunkify_start (void)
6559 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6562 rtx pending_ltrel
= NULL_RTX
;
6565 rtx (*gen_reload_base
) (rtx
, rtx
) =
6566 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6569 /* We need correct insn addresses. */
6571 shorten_branches (get_insns ());
6573 /* Scan all insns and move literals to pool chunks. */
6575 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6577 bool section_switch_p
= false;
6579 /* Check for pending LTREL_BASE. */
6582 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6585 gcc_assert (ltrel_base
== pending_ltrel
);
6586 pending_ltrel
= NULL_RTX
;
6590 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6593 curr_pool
= s390_start_pool (&pool_list
, insn
);
6595 s390_add_execute (curr_pool
, insn
);
6596 s390_add_pool_insn (curr_pool
, insn
);
6598 else if (GET_CODE (insn
) == INSN
|| CALL_P (insn
))
6600 rtx pool_ref
= NULL_RTX
;
6601 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6604 rtx constant
= get_pool_constant (pool_ref
);
6605 enum machine_mode mode
= get_pool_mode (pool_ref
);
6608 curr_pool
= s390_start_pool (&pool_list
, insn
);
6610 s390_add_constant (curr_pool
, constant
, mode
);
6611 s390_add_pool_insn (curr_pool
, insn
);
6613 /* Don't split the pool chunk between a LTREL_OFFSET load
6614 and the corresponding LTREL_BASE. */
6615 if (GET_CODE (constant
) == CONST
6616 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6617 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6619 gcc_assert (!pending_ltrel
);
6620 pending_ltrel
= pool_ref
;
6625 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6628 s390_add_pool_insn (curr_pool
, insn
);
6629 /* An LTREL_BASE must follow within the same basic block. */
6630 gcc_assert (!pending_ltrel
);
6634 switch (NOTE_KIND (insn
))
6636 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
6637 section_switch_p
= true;
6639 case NOTE_INSN_VAR_LOCATION
:
6640 case NOTE_INSN_CALL_ARG_LOCATION
:
6647 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6648 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6651 if (TARGET_CPU_ZARCH
)
6653 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6656 s390_end_pool (curr_pool
, NULL_RTX
);
6661 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6662 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6665 /* We will later have to insert base register reload insns.
6666 Those will have an effect on code size, which we need to
6667 consider here. This calculation makes rather pessimistic
6668 worst-case assumptions. */
6669 if (GET_CODE (insn
) == CODE_LABEL
)
6672 if (chunk_size
< S390_POOL_CHUNK_MIN
6673 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6674 && !section_switch_p
)
6677 /* Pool chunks can only be inserted after BARRIERs ... */
6678 if (GET_CODE (insn
) == BARRIER
)
6680 s390_end_pool (curr_pool
, insn
);
6685 /* ... so if we don't find one in time, create one. */
6686 else if (chunk_size
> S390_POOL_CHUNK_MAX
6687 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6688 || section_switch_p
)
6690 rtx label
, jump
, barrier
, next
, prev
;
6692 if (!section_switch_p
)
6694 /* We can insert the barrier only after a 'real' insn. */
6695 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6697 if (get_attr_length (insn
) == 0)
6699 /* Don't separate LTREL_BASE from the corresponding
6700 LTREL_OFFSET load. */
6707 next
= NEXT_INSN (insn
);
6711 && (NOTE_KIND (next
) == NOTE_INSN_VAR_LOCATION
6712 || NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
));
6716 gcc_assert (!pending_ltrel
);
6718 /* The old pool has to end before the section switch
6719 note in order to make it part of the current
6721 insn
= PREV_INSN (insn
);
6724 label
= gen_label_rtx ();
6726 if (prev
&& NOTE_P (prev
))
6727 prev
= prev_nonnote_insn (prev
);
6729 jump
= emit_jump_insn_after_setloc (gen_jump (label
), insn
,
6730 INSN_LOCATOR (prev
));
6732 jump
= emit_jump_insn_after_noloc (gen_jump (label
), insn
);
6733 barrier
= emit_barrier_after (jump
);
6734 insn
= emit_label_after (label
, barrier
);
6735 JUMP_LABEL (jump
) = label
;
6736 LABEL_NUSES (label
) = 1;
6738 INSN_ADDRESSES_NEW (jump
, -1);
6739 INSN_ADDRESSES_NEW (barrier
, -1);
6740 INSN_ADDRESSES_NEW (insn
, -1);
6742 s390_end_pool (curr_pool
, barrier
);
6750 s390_end_pool (curr_pool
, NULL_RTX
);
6751 gcc_assert (!pending_ltrel
);
6753 /* Find all labels that are branched into
6754 from an insn belonging to a different chunk. */
6756 far_labels
= BITMAP_ALLOC (NULL
);
6758 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6760 /* Labels marked with LABEL_PRESERVE_P can be target
6761 of non-local jumps, so we have to mark them.
6762 The same holds for named labels.
6764 Don't do that, however, if it is the label before
6767 if (GET_CODE (insn
) == CODE_LABEL
6768 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6770 rtx vec_insn
= next_real_insn (insn
);
6771 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6772 PATTERN (vec_insn
) : NULL_RTX
;
6774 || !(GET_CODE (vec_pat
) == ADDR_VEC
6775 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6776 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6779 /* If we have a direct jump (conditional or unconditional)
6780 or a casesi jump, check all potential targets. */
6781 else if (GET_CODE (insn
) == JUMP_INSN
)
6783 rtx pat
= PATTERN (insn
);
6784 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6785 pat
= XVECEXP (pat
, 0, 0);
6787 if (GET_CODE (pat
) == SET
)
6789 rtx label
= JUMP_LABEL (insn
);
6792 if (s390_find_pool (pool_list
, label
)
6793 != s390_find_pool (pool_list
, insn
))
6794 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6797 else if (GET_CODE (pat
) == PARALLEL
6798 && XVECLEN (pat
, 0) == 2
6799 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6800 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6801 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6803 /* Find the jump table used by this casesi jump. */
6804 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6805 rtx vec_insn
= next_real_insn (vec_label
);
6806 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6807 PATTERN (vec_insn
) : NULL_RTX
;
6809 && (GET_CODE (vec_pat
) == ADDR_VEC
6810 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6812 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6814 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6816 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6818 if (s390_find_pool (pool_list
, label
)
6819 != s390_find_pool (pool_list
, insn
))
6820 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6827 /* Insert base register reload insns before every pool. */
6829 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6831 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6833 rtx insn
= curr_pool
->first_insn
;
6834 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6837 /* Insert base register reload insns at every far label. */
6839 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6840 if (GET_CODE (insn
) == CODE_LABEL
6841 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6843 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6846 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6848 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6853 BITMAP_FREE (far_labels
);
6856 /* Recompute insn addresses. */
6858 init_insn_lengths ();
6859 shorten_branches (get_insns ());
6864 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6865 After we have decided to use this list, finish implementing
6866 all changes to the current function as required. */
6869 s390_chunkify_finish (struct constant_pool
*pool_list
)
6871 struct constant_pool
*curr_pool
= NULL
;
6875 /* Replace all literal pool references. */
6877 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6880 replace_ltrel_base (&PATTERN (insn
));
6882 curr_pool
= s390_find_pool (pool_list
, insn
);
6886 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6888 rtx addr
, pool_ref
= NULL_RTX
;
6889 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6892 if (s390_execute_label (insn
))
6893 addr
= s390_find_execute (curr_pool
, insn
);
6895 addr
= s390_find_constant (curr_pool
,
6896 get_pool_constant (pool_ref
),
6897 get_pool_mode (pool_ref
));
6899 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6900 INSN_CODE (insn
) = -1;
6905 /* Dump out all literal pools. */
6907 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6908 s390_dump_pool (curr_pool
, 0);
6910 /* Free pool list. */
6914 struct constant_pool
*next
= pool_list
->next
;
6915 s390_free_pool (pool_list
);
6920 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6921 We have decided we cannot use this list, so revert all changes
6922 to the current function that were done by s390_chunkify_start. */
6925 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6927 struct constant_pool
*curr_pool
= NULL
;
6930 /* Remove all pool placeholder insns. */
6932 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6934 /* Did we insert an extra barrier? Remove it. */
6935 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6936 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6937 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6939 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6940 && barrier
&& GET_CODE (barrier
) == BARRIER
6941 && label
&& GET_CODE (label
) == CODE_LABEL
6942 && GET_CODE (PATTERN (jump
)) == SET
6943 && SET_DEST (PATTERN (jump
)) == pc_rtx
6944 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6945 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6948 remove_insn (barrier
);
6949 remove_insn (label
);
6952 remove_insn (curr_pool
->pool_insn
);
6955 /* Remove all base register reload insns. */
6957 for (insn
= get_insns (); insn
; )
6959 rtx next_insn
= NEXT_INSN (insn
);
6961 if (GET_CODE (insn
) == INSN
6962 && GET_CODE (PATTERN (insn
)) == SET
6963 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6964 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6970 /* Free pool list. */
6974 struct constant_pool
*next
= pool_list
->next
;
6975 s390_free_pool (pool_list
);
6980 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6983 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6987 switch (GET_MODE_CLASS (mode
))
6990 case MODE_DECIMAL_FLOAT
:
6991 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6993 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6994 assemble_real (r
, mode
, align
);
6998 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6999 mark_symbol_refs_as_used (exp
);
7008 /* Return an RTL expression representing the value of the return address
7009 for the frame COUNT steps up from the current frame. FRAME is the
7010 frame pointer of that frame. */
7013 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
7018 /* Without backchain, we fail for all but the current frame. */
7020 if (!TARGET_BACKCHAIN
&& count
> 0)
7023 /* For the current frame, we need to make sure the initial
7024 value of RETURN_REGNUM is actually saved. */
7028 /* On non-z architectures branch splitting could overwrite r14. */
7029 if (TARGET_CPU_ZARCH
)
7030 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
7033 cfun_frame_layout
.save_return_addr_p
= true;
7034 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
7038 if (TARGET_PACKED_STACK
)
7039 offset
= -2 * UNITS_PER_LONG
;
7041 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
7043 addr
= plus_constant (Pmode
, frame
, offset
);
7044 addr
= memory_address (Pmode
, addr
);
7045 return gen_rtx_MEM (Pmode
, addr
);
7048 /* Return an RTL expression representing the back chain stored in
7049 the current stack frame. */
7052 s390_back_chain_rtx (void)
7056 gcc_assert (TARGET_BACKCHAIN
);
7058 if (TARGET_PACKED_STACK
)
7059 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
7060 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
7062 chain
= stack_pointer_rtx
;
7064 chain
= gen_rtx_MEM (Pmode
, chain
);
7068 /* Find first call clobbered register unused in a function.
7069 This could be used as base register in a leaf function
7070 or for holding the return address before epilogue. */
7073 find_unused_clobbered_reg (void)
7076 for (i
= 0; i
< 6; i
++)
7077 if (!df_regs_ever_live_p (i
))
7083 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7084 clobbered hard regs in SETREG. */
7087 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
7089 int *regs_ever_clobbered
= (int *)data
;
7090 unsigned int i
, regno
;
7091 enum machine_mode mode
= GET_MODE (setreg
);
7093 if (GET_CODE (setreg
) == SUBREG
)
7095 rtx inner
= SUBREG_REG (setreg
);
7096 if (!GENERAL_REG_P (inner
))
7098 regno
= subreg_regno (setreg
);
7100 else if (GENERAL_REG_P (setreg
))
7101 regno
= REGNO (setreg
);
7106 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7108 regs_ever_clobbered
[i
] = 1;
7111 /* Walks through all basic blocks of the current function looking
7112 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7113 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7114 each of those regs. */
7117 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
7123 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
7125 /* For non-leaf functions we have to consider all call clobbered regs to be
7127 if (!current_function_is_leaf
)
7129 for (i
= 0; i
< 16; i
++)
7130 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7133 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7134 this work is done by liveness analysis (mark_regs_live_at_end).
7135 Special care is needed for functions containing landing pads. Landing pads
7136 may use the eh registers, but the code which sets these registers is not
7137 contained in that function. Hence s390_regs_ever_clobbered is not able to
7138 deal with this automatically. */
7139 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7140 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7141 if (crtl
->calls_eh_return
7142 || (cfun
->machine
->has_landing_pad_p
7143 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7144 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7146 /* For nonlocal gotos all call-saved registers have to be saved.
7147 This flag is also set for the unwinding code in libgcc.
7148 See expand_builtin_unwind_init. For regs_ever_live this is done by
7150 if (cfun
->has_nonlocal_label
)
7151 for (i
= 0; i
< 16; i
++)
7152 if (!call_really_used_regs
[i
])
7153 regs_ever_clobbered
[i
] = 1;
7155 FOR_EACH_BB (cur_bb
)
7157 FOR_BB_INSNS (cur_bb
, cur_insn
)
7159 if (INSN_P (cur_insn
))
7160 note_stores (PATTERN (cur_insn
),
7161 s390_reg_clobbered_rtx
,
7162 regs_ever_clobbered
);
7167 /* Determine the frame area which actually has to be accessed
7168 in the function epilogue. The values are stored at the
7169 given pointers AREA_BOTTOM (address of the lowest used stack
7170 address) and AREA_TOP (address of the first item which does
7171 not belong to the stack frame). */
7174 s390_frame_area (int *area_bottom
, int *area_top
)
7182 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7184 b
= (cfun_frame_layout
.gprs_offset
7185 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7186 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7187 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7190 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7192 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7193 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7194 + cfun_frame_layout
.high_fprs
* 8));
7198 for (i
= 2; i
< 4; i
++)
7199 if (cfun_fpr_bit_p (i
))
7201 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7202 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7209 /* Fill cfun->machine with info about register usage of current function.
7210 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7213 s390_register_info (int clobbered_regs
[])
7217 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7218 cfun_frame_layout
.fpr_bitmap
= 0;
7219 cfun_frame_layout
.high_fprs
= 0;
7221 for (i
= 24; i
< 32; i
++)
7222 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7224 cfun_set_fpr_bit (i
- 16);
7225 cfun_frame_layout
.high_fprs
++;
7228 /* Find first and last gpr to be saved. We trust regs_ever_live
7229 data, except that we don't save and restore global registers.
7231 Also, all registers with special meaning to the compiler need
7232 to be handled extra. */
7234 s390_regs_ever_clobbered (clobbered_regs
);
7236 for (i
= 0; i
< 16; i
++)
7237 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7239 if (frame_pointer_needed
)
7240 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7243 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7244 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7246 clobbered_regs
[BASE_REGNUM
]
7247 |= (cfun
->machine
->base_reg
7248 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7250 clobbered_regs
[RETURN_REGNUM
]
7251 |= (!current_function_is_leaf
7252 || TARGET_TPF_PROFILING
7253 || cfun
->machine
->split_branches_pending_p
7254 || cfun_frame_layout
.save_return_addr_p
7255 || crtl
->calls_eh_return
7258 clobbered_regs
[STACK_POINTER_REGNUM
]
7259 |= (!current_function_is_leaf
7260 || TARGET_TPF_PROFILING
7261 || cfun_save_high_fprs_p
7262 || get_frame_size () > 0
7263 || cfun
->calls_alloca
7266 for (i
= 6; i
< 16; i
++)
7267 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7269 for (j
= 15; j
> i
; j
--)
7270 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7275 /* Nothing to save/restore. */
7276 cfun_frame_layout
.first_save_gpr_slot
= -1;
7277 cfun_frame_layout
.last_save_gpr_slot
= -1;
7278 cfun_frame_layout
.first_save_gpr
= -1;
7279 cfun_frame_layout
.first_restore_gpr
= -1;
7280 cfun_frame_layout
.last_save_gpr
= -1;
7281 cfun_frame_layout
.last_restore_gpr
= -1;
7285 /* Save slots for gprs from i to j. */
7286 cfun_frame_layout
.first_save_gpr_slot
= i
;
7287 cfun_frame_layout
.last_save_gpr_slot
= j
;
7289 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7290 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7292 if (clobbered_regs
[i
])
7295 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7296 if (clobbered_regs
[j
])
7299 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7301 /* Nothing to save/restore. */
7302 cfun_frame_layout
.first_save_gpr
= -1;
7303 cfun_frame_layout
.first_restore_gpr
= -1;
7304 cfun_frame_layout
.last_save_gpr
= -1;
7305 cfun_frame_layout
.last_restore_gpr
= -1;
7309 /* Save / Restore from gpr i to j. */
7310 cfun_frame_layout
.first_save_gpr
= i
;
7311 cfun_frame_layout
.first_restore_gpr
= i
;
7312 cfun_frame_layout
.last_save_gpr
= j
;
7313 cfun_frame_layout
.last_restore_gpr
= j
;
7319 /* Varargs functions need to save gprs 2 to 6. */
7320 if (cfun
->va_list_gpr_size
7321 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7323 int min_gpr
= crtl
->args
.info
.gprs
;
7324 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7325 if (max_gpr
> GP_ARG_NUM_REG
)
7326 max_gpr
= GP_ARG_NUM_REG
;
7328 if (cfun_frame_layout
.first_save_gpr
== -1
7329 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7331 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7332 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7335 if (cfun_frame_layout
.last_save_gpr
== -1
7336 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7338 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7339 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7343 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7344 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7345 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7347 int min_fpr
= crtl
->args
.info
.fprs
;
7348 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7349 if (max_fpr
> FP_ARG_NUM_REG
)
7350 max_fpr
= FP_ARG_NUM_REG
;
7352 /* ??? This is currently required to ensure proper location
7353 of the fpr save slots within the va_list save area. */
7354 if (TARGET_PACKED_STACK
)
7357 for (i
= min_fpr
; i
< max_fpr
; i
++)
7358 cfun_set_fpr_bit (i
);
7363 for (i
= 2; i
< 4; i
++)
7364 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7365 cfun_set_fpr_bit (i
);
7368 /* Fill cfun->machine with info about frame of current function. */
7371 s390_frame_info (void)
7375 cfun_frame_layout
.frame_size
= get_frame_size ();
7376 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7377 fatal_error ("total size of local variables exceeds architecture limit");
7379 if (!TARGET_PACKED_STACK
)
7381 cfun_frame_layout
.backchain_offset
= 0;
7382 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7383 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7384 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7385 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7388 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7390 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7392 cfun_frame_layout
.gprs_offset
7393 = (cfun_frame_layout
.backchain_offset
7394 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7399 cfun_frame_layout
.f4_offset
7400 = (cfun_frame_layout
.gprs_offset
7401 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7403 cfun_frame_layout
.f0_offset
7404 = (cfun_frame_layout
.f4_offset
7405 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7409 /* On 31 bit we have to care about alignment of the
7410 floating point regs to provide fastest access. */
7411 cfun_frame_layout
.f0_offset
7412 = ((cfun_frame_layout
.gprs_offset
7413 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7414 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7416 cfun_frame_layout
.f4_offset
7417 = (cfun_frame_layout
.f0_offset
7418 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7421 else /* no backchain */
7423 cfun_frame_layout
.f4_offset
7424 = (STACK_POINTER_OFFSET
7425 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7427 cfun_frame_layout
.f0_offset
7428 = (cfun_frame_layout
.f4_offset
7429 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7431 cfun_frame_layout
.gprs_offset
7432 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7435 if (current_function_is_leaf
7436 && !TARGET_TPF_PROFILING
7437 && cfun_frame_layout
.frame_size
== 0
7438 && !cfun_save_high_fprs_p
7439 && !cfun
->calls_alloca
7443 if (!TARGET_PACKED_STACK
)
7444 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7445 + crtl
->outgoing_args_size
7446 + cfun_frame_layout
.high_fprs
* 8);
7449 if (TARGET_BACKCHAIN
)
7450 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7452 /* No alignment trouble here because f8-f15 are only saved under
7454 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7455 cfun_frame_layout
.f4_offset
),
7456 cfun_frame_layout
.gprs_offset
)
7457 - cfun_frame_layout
.high_fprs
* 8);
7459 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7461 for (i
= 0; i
< 8; i
++)
7462 if (cfun_fpr_bit_p (i
))
7463 cfun_frame_layout
.frame_size
+= 8;
7465 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7467 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7468 the frame size to sustain 8 byte alignment of stack frames. */
7469 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7470 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7471 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7473 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7477 /* Generate frame layout. Fills in register and frame data for the current
7478 function in cfun->machine. This routine can be called multiple times;
7479 it will re-do the complete frame layout every time. */
7482 s390_init_frame_layout (void)
7484 HOST_WIDE_INT frame_size
;
7486 int clobbered_regs
[16];
7488 /* On S/390 machines, we may need to perform branch splitting, which
7489 will require both base and return address register. We have no
7490 choice but to assume we're going to need them until right at the
7491 end of the machine dependent reorg phase. */
7492 if (!TARGET_CPU_ZARCH
)
7493 cfun
->machine
->split_branches_pending_p
= true;
7497 frame_size
= cfun_frame_layout
.frame_size
;
7499 /* Try to predict whether we'll need the base register. */
7500 base_used
= cfun
->machine
->split_branches_pending_p
7501 || crtl
->uses_const_pool
7502 || (!DISP_IN_RANGE (frame_size
)
7503 && !CONST_OK_FOR_K (frame_size
));
7505 /* Decide which register to use as literal pool base. In small
7506 leaf functions, try to use an unused call-clobbered register
7507 as base register to avoid save/restore overhead. */
7509 cfun
->machine
->base_reg
= NULL_RTX
;
7510 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7511 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7513 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7515 s390_register_info (clobbered_regs
);
7518 while (frame_size
!= cfun_frame_layout
.frame_size
);
7521 /* Update frame layout. Recompute actual register save data based on
7522 current info and update regs_ever_live for the special registers.
7523 May be called multiple times, but may never cause *more* registers
7524 to be saved than s390_init_frame_layout allocated room for. */
7527 s390_update_frame_layout (void)
7529 int clobbered_regs
[16];
7531 s390_register_info (clobbered_regs
);
7533 df_set_regs_ever_live (BASE_REGNUM
,
7534 clobbered_regs
[BASE_REGNUM
] ? true : false);
7535 df_set_regs_ever_live (RETURN_REGNUM
,
7536 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7537 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7538 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7540 if (cfun
->machine
->base_reg
)
7541 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7544 /* Return true if it is legal to put a value with MODE into REGNO. */
7547 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7549 switch (REGNO_REG_CLASS (regno
))
7552 if (REGNO_PAIR_OK (regno
, mode
))
7554 if (mode
== SImode
|| mode
== DImode
)
7557 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7562 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7567 if (REGNO_PAIR_OK (regno
, mode
))
7570 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7575 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7579 if (REGNO_PAIR_OK (regno
, mode
))
7581 if (mode
== SImode
|| mode
== Pmode
)
7592 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7595 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7597 /* Once we've decided upon a register to use as base register, it must
7598 no longer be used for any other purpose. */
7599 if (cfun
->machine
->base_reg
)
7600 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7601 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7607 /* Maximum number of registers to represent a value of mode MODE
7608 in a register of class RCLASS. */
7611 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7616 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7617 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7619 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7621 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7625 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7628 /* Return true if register FROM can be eliminated via register TO. */
7631 s390_can_eliminate (const int from
, const int to
)
7633 /* On zSeries machines, we have not marked the base register as fixed.
7634 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7635 If a function requires the base register, we say here that this
7636 elimination cannot be performed. This will cause reload to free
7637 up the base register (as if it were fixed). On the other hand,
7638 if the current function does *not* require the base register, we
7639 say here the elimination succeeds, which in turn allows reload
7640 to allocate the base register for any other purpose. */
7641 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7643 if (TARGET_CPU_ZARCH
)
7645 s390_init_frame_layout ();
7646 return cfun
->machine
->base_reg
== NULL_RTX
;
7652 /* Everything else must point into the stack frame. */
7653 gcc_assert (to
== STACK_POINTER_REGNUM
7654 || to
== HARD_FRAME_POINTER_REGNUM
);
7656 gcc_assert (from
== FRAME_POINTER_REGNUM
7657 || from
== ARG_POINTER_REGNUM
7658 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7660 /* Make sure we actually saved the return address. */
7661 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7662 if (!crtl
->calls_eh_return
7664 && !cfun_frame_layout
.save_return_addr_p
)
7670 /* Return offset between register FROM and TO initially after prolog. */
7673 s390_initial_elimination_offset (int from
, int to
)
7675 HOST_WIDE_INT offset
;
7678 /* ??? Why are we called for non-eliminable pairs? */
7679 if (!s390_can_eliminate (from
, to
))
7684 case FRAME_POINTER_REGNUM
:
7685 offset
= (get_frame_size()
7686 + STACK_POINTER_OFFSET
7687 + crtl
->outgoing_args_size
);
7690 case ARG_POINTER_REGNUM
:
7691 s390_init_frame_layout ();
7692 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7695 case RETURN_ADDRESS_POINTER_REGNUM
:
7696 s390_init_frame_layout ();
7697 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7698 gcc_assert (index
>= 0);
7699 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7700 offset
+= index
* UNITS_PER_LONG
;
7714 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7715 to register BASE. Return generated insn. */
7718 save_fpr (rtx base
, int offset
, int regnum
)
7721 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
7723 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7724 set_mem_alias_set (addr
, get_varargs_alias_set ());
7726 set_mem_alias_set (addr
, get_frame_alias_set ());
7728 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7731 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7732 to register BASE. Return generated insn. */
7735 restore_fpr (rtx base
, int offset
, int regnum
)
7738 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
7739 set_mem_alias_set (addr
, get_frame_alias_set ());
7741 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7744 /* Return true if REGNO is a global register, but not one
7745 of the special ones that need to be saved/restored in anyway. */
7748 global_not_special_regno_p (int regno
)
7750 return (global_regs
[regno
]
7751 /* These registers are special and need to be
7752 restored in any case. */
7753 && !(regno
== STACK_POINTER_REGNUM
7754 || regno
== RETURN_REGNUM
7755 || regno
== BASE_REGNUM
7756 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7759 /* Generate insn to save registers FIRST to LAST into
7760 the register save area located at offset OFFSET
7761 relative to register BASE. */
7764 save_gprs (rtx base
, int offset
, int first
, int last
)
7766 rtx addr
, insn
, note
;
7769 addr
= plus_constant (Pmode
, base
, offset
);
7770 addr
= gen_rtx_MEM (Pmode
, addr
);
7772 set_mem_alias_set (addr
, get_frame_alias_set ());
7774 /* Special-case single register. */
7778 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7780 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7782 if (!global_not_special_regno_p (first
))
7783 RTX_FRAME_RELATED_P (insn
) = 1;
7788 insn
= gen_store_multiple (addr
,
7789 gen_rtx_REG (Pmode
, first
),
7790 GEN_INT (last
- first
+ 1));
7792 if (first
<= 6 && cfun
->stdarg
)
7793 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7795 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7798 set_mem_alias_set (mem
, get_varargs_alias_set ());
7801 /* We need to set the FRAME_RELATED flag on all SETs
7802 inside the store-multiple pattern.
7804 However, we must not emit DWARF records for registers 2..5
7805 if they are stored for use by variable arguments ...
7807 ??? Unfortunately, it is not enough to simply not the
7808 FRAME_RELATED flags for those SETs, because the first SET
7809 of the PARALLEL is always treated as if it had the flag
7810 set, even if it does not. Therefore we emit a new pattern
7811 without those registers as REG_FRAME_RELATED_EXPR note. */
7813 if (first
>= 6 && !global_not_special_regno_p (first
))
7815 rtx pat
= PATTERN (insn
);
7817 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7818 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7819 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7821 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7823 RTX_FRAME_RELATED_P (insn
) = 1;
7829 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7830 if (!global_not_special_regno_p (start
))
7836 addr
= plus_constant (Pmode
, base
,
7837 offset
+ (start
- first
) * UNITS_PER_LONG
);
7838 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7839 gen_rtx_REG (Pmode
, start
),
7840 GEN_INT (last
- start
+ 1));
7841 note
= PATTERN (note
);
7843 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7845 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7846 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7847 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7849 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7851 RTX_FRAME_RELATED_P (insn
) = 1;
7857 /* Generate insn to restore registers FIRST to LAST from
7858 the register save area located at offset OFFSET
7859 relative to register BASE. */
7862 restore_gprs (rtx base
, int offset
, int first
, int last
)
7866 addr
= plus_constant (Pmode
, base
, offset
);
7867 addr
= gen_rtx_MEM (Pmode
, addr
);
7868 set_mem_alias_set (addr
, get_frame_alias_set ());
7870 /* Special-case single register. */
7874 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7876 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7881 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7883 GEN_INT (last
- first
+ 1));
7887 /* Return insn sequence to load the GOT register. */
7889 static GTY(()) rtx got_symbol
;
7891 s390_load_got (void)
7895 /* We cannot use pic_offset_table_rtx here since we use this
7896 function also for non-pic if __tls_get_offset is called and in
7897 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
7899 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
7903 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7904 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7909 if (TARGET_CPU_ZARCH
)
7911 emit_move_insn (got_rtx
, got_symbol
);
7917 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7918 UNSPEC_LTREL_OFFSET
);
7919 offset
= gen_rtx_CONST (Pmode
, offset
);
7920 offset
= force_const_mem (Pmode
, offset
);
7922 emit_move_insn (got_rtx
, offset
);
7924 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7926 offset
= gen_rtx_PLUS (Pmode
, got_rtx
, offset
);
7928 emit_move_insn (got_rtx
, offset
);
7931 insns
= get_insns ();
7936 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7937 and the change to the stack pointer. */
7940 s390_emit_stack_tie (void)
7942 rtx mem
= gen_frame_mem (BLKmode
,
7943 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7945 emit_insn (gen_stack_tie (mem
));
7948 /* Expand the prologue into a bunch of separate insns. */
7951 s390_emit_prologue (void)
7959 /* Complete frame layout. */
7961 s390_update_frame_layout ();
7963 /* Annotate all constant pool references to let the scheduler know
7964 they implicitly use the base register. */
7966 push_topmost_sequence ();
7968 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7971 annotate_constant_pool_refs (&PATTERN (insn
));
7972 df_insn_rescan (insn
);
7975 pop_topmost_sequence ();
7977 /* Choose best register to use for temp use within prologue.
7978 See below for why TPF must use the register 1. */
7980 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7981 && !current_function_is_leaf
7982 && !TARGET_TPF_PROFILING
)
7983 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7985 temp_reg
= gen_rtx_REG (Pmode
, 1);
7987 /* Save call saved gprs. */
7988 if (cfun_frame_layout
.first_save_gpr
!= -1)
7990 insn
= save_gprs (stack_pointer_rtx
,
7991 cfun_frame_layout
.gprs_offset
+
7992 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
7993 - cfun_frame_layout
.first_save_gpr_slot
),
7994 cfun_frame_layout
.first_save_gpr
,
7995 cfun_frame_layout
.last_save_gpr
);
7999 /* Dummy insn to mark literal pool slot. */
8001 if (cfun
->machine
->base_reg
)
8002 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
8004 offset
= cfun_frame_layout
.f0_offset
;
8006 /* Save f0 and f2. */
8007 for (i
= 0; i
< 2; i
++)
8009 if (cfun_fpr_bit_p (i
))
8011 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8014 else if (!TARGET_PACKED_STACK
)
8018 /* Save f4 and f6. */
8019 offset
= cfun_frame_layout
.f4_offset
;
8020 for (i
= 2; i
< 4; i
++)
8022 if (cfun_fpr_bit_p (i
))
8024 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8027 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8028 therefore are not frame related. */
8029 if (!call_really_used_regs
[i
+ 16])
8030 RTX_FRAME_RELATED_P (insn
) = 1;
8032 else if (!TARGET_PACKED_STACK
)
8036 if (TARGET_PACKED_STACK
8037 && cfun_save_high_fprs_p
8038 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
8040 offset
= (cfun_frame_layout
.f8_offset
8041 + (cfun_frame_layout
.high_fprs
- 1) * 8);
8043 for (i
= 15; i
> 7 && offset
>= 0; i
--)
8044 if (cfun_fpr_bit_p (i
))
8046 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8048 RTX_FRAME_RELATED_P (insn
) = 1;
8051 if (offset
>= cfun_frame_layout
.f8_offset
)
8055 if (!TARGET_PACKED_STACK
)
8056 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
8058 if (flag_stack_usage_info
)
8059 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
8061 /* Decrement stack pointer. */
8063 if (cfun_frame_layout
.frame_size
> 0)
8065 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8068 if (s390_stack_size
)
8070 HOST_WIDE_INT stack_guard
;
8072 if (s390_stack_guard
)
8073 stack_guard
= s390_stack_guard
;
8076 /* If no value for stack guard is provided the smallest power of 2
8077 larger than the current frame size is chosen. */
8079 while (stack_guard
< cfun_frame_layout
.frame_size
)
8083 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
8085 warning (0, "frame size of function %qs is %wd"
8086 " bytes exceeding user provided stack limit of "
8088 "An unconditional trap is added.",
8089 current_function_name(), cfun_frame_layout
.frame_size
,
8091 emit_insn (gen_trap ());
8095 /* stack_guard has to be smaller than s390_stack_size.
8096 Otherwise we would emit an AND with zero which would
8097 not match the test under mask pattern. */
8098 if (stack_guard
>= s390_stack_size
)
8100 warning (0, "frame size of function %qs is %wd"
8101 " bytes which is more than half the stack size. "
8102 "The dynamic check would not be reliable. "
8103 "No check emitted for this function.",
8104 current_function_name(),
8105 cfun_frame_layout
.frame_size
);
8109 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8110 & ~(stack_guard
- 1));
8112 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8113 GEN_INT (stack_check_mask
));
8115 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8117 t
, const0_rtx
, const0_rtx
));
8119 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8121 t
, const0_rtx
, const0_rtx
));
8126 if (s390_warn_framesize
> 0
8127 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8128 warning (0, "frame size of %qs is %wd bytes",
8129 current_function_name (), cfun_frame_layout
.frame_size
);
8131 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8132 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8134 /* Save incoming stack pointer into temp reg. */
8135 if (TARGET_BACKCHAIN
|| next_fpr
)
8136 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8138 /* Subtract frame size from stack pointer. */
8140 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8142 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8143 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8145 insn
= emit_insn (insn
);
8149 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8150 frame_off
= force_const_mem (Pmode
, frame_off
);
8152 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8153 annotate_constant_pool_refs (&PATTERN (insn
));
8156 RTX_FRAME_RELATED_P (insn
) = 1;
8157 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8158 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8159 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8160 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8163 /* Set backchain. */
8165 if (TARGET_BACKCHAIN
)
8167 if (cfun_frame_layout
.backchain_offset
)
8168 addr
= gen_rtx_MEM (Pmode
,
8169 plus_constant (Pmode
, stack_pointer_rtx
,
8170 cfun_frame_layout
.backchain_offset
));
8172 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8173 set_mem_alias_set (addr
, get_frame_alias_set ());
8174 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8177 /* If we support non-call exceptions (e.g. for Java),
8178 we need to make sure the backchain pointer is set up
8179 before any possibly trapping memory access. */
8180 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8182 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8183 emit_clobber (addr
);
8187 /* Save fprs 8 - 15 (64 bit ABI). */
8189 if (cfun_save_high_fprs_p
&& next_fpr
)
8191 /* If the stack might be accessed through a different register
8192 we have to make sure that the stack pointer decrement is not
8193 moved below the use of the stack slots. */
8194 s390_emit_stack_tie ();
8196 insn
= emit_insn (gen_add2_insn (temp_reg
,
8197 GEN_INT (cfun_frame_layout
.f8_offset
)));
8201 for (i
= 24; i
<= next_fpr
; i
++)
8202 if (cfun_fpr_bit_p (i
- 16))
8204 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
8205 cfun_frame_layout
.frame_size
8206 + cfun_frame_layout
.f8_offset
8209 insn
= save_fpr (temp_reg
, offset
, i
);
8211 RTX_FRAME_RELATED_P (insn
) = 1;
8212 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8213 gen_rtx_SET (VOIDmode
,
8214 gen_rtx_MEM (DFmode
, addr
),
8215 gen_rtx_REG (DFmode
, i
)));
8219 /* Set frame pointer, if needed. */
8221 if (frame_pointer_needed
)
8223 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8224 RTX_FRAME_RELATED_P (insn
) = 1;
8227 /* Set up got pointer, if needed. */
8229 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8231 rtx insns
= s390_load_got ();
8233 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8234 annotate_constant_pool_refs (&PATTERN (insn
));
8239 if (TARGET_TPF_PROFILING
)
8241 /* Generate a BAS instruction to serve as a function
8242 entry intercept to facilitate the use of tracing
8243 algorithms located at the branch target. */
8244 emit_insn (gen_prologue_tpf ());
8246 /* Emit a blockage here so that all code
8247 lies between the profiling mechanisms. */
8248 emit_insn (gen_blockage ());
8252 /* Expand the epilogue into a bunch of separate insns. */
8255 s390_emit_epilogue (bool sibcall
)
8257 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8258 int area_bottom
, area_top
, offset
= 0;
8263 if (TARGET_TPF_PROFILING
)
8266 /* Generate a BAS instruction to serve as a function
8267 entry intercept to facilitate the use of tracing
8268 algorithms located at the branch target. */
8270 /* Emit a blockage here so that all code
8271 lies between the profiling mechanisms. */
8272 emit_insn (gen_blockage ());
8274 emit_insn (gen_epilogue_tpf ());
8277 /* Check whether to use frame or stack pointer for restore. */
8279 frame_pointer
= (frame_pointer_needed
8280 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8282 s390_frame_area (&area_bottom
, &area_top
);
8284 /* Check whether we can access the register save area.
8285 If not, increment the frame pointer as required. */
8287 if (area_top
<= area_bottom
)
8289 /* Nothing to restore. */
8291 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8292 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8294 /* Area is in range. */
8295 offset
= cfun_frame_layout
.frame_size
;
8299 rtx insn
, frame_off
, cfa
;
8301 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8302 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8304 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8305 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8306 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8308 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8309 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8310 insn
= emit_insn (insn
);
8314 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8315 frame_off
= force_const_mem (Pmode
, frame_off
);
8317 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8318 annotate_constant_pool_refs (&PATTERN (insn
));
8320 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8321 RTX_FRAME_RELATED_P (insn
) = 1;
8324 /* Restore call saved fprs. */
8328 if (cfun_save_high_fprs_p
)
8330 next_offset
= cfun_frame_layout
.f8_offset
;
8331 for (i
= 24; i
< 32; i
++)
8333 if (cfun_fpr_bit_p (i
- 16))
8335 restore_fpr (frame_pointer
,
8336 offset
+ next_offset
, i
);
8338 = alloc_reg_note (REG_CFA_RESTORE
,
8339 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8348 next_offset
= cfun_frame_layout
.f4_offset
;
8349 for (i
= 18; i
< 20; i
++)
8351 if (cfun_fpr_bit_p (i
- 16))
8353 restore_fpr (frame_pointer
,
8354 offset
+ next_offset
, i
);
8356 = alloc_reg_note (REG_CFA_RESTORE
,
8357 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8360 else if (!TARGET_PACKED_STACK
)
8366 /* Return register. */
8368 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8370 /* Restore call saved gprs. */
8372 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8377 /* Check for global register and save them
8378 to stack location from where they get restored. */
8380 for (i
= cfun_frame_layout
.first_restore_gpr
;
8381 i
<= cfun_frame_layout
.last_restore_gpr
;
8384 if (global_not_special_regno_p (i
))
8386 addr
= plus_constant (Pmode
, frame_pointer
,
8387 offset
+ cfun_frame_layout
.gprs_offset
8388 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8390 addr
= gen_rtx_MEM (Pmode
, addr
);
8391 set_mem_alias_set (addr
, get_frame_alias_set ());
8392 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8396 = alloc_reg_note (REG_CFA_RESTORE
,
8397 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8402 /* Fetch return address from stack before load multiple,
8403 this will do good for scheduling. */
8405 if (cfun_frame_layout
.save_return_addr_p
8406 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8407 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8409 int return_regnum
= find_unused_clobbered_reg();
8412 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8414 addr
= plus_constant (Pmode
, frame_pointer
,
8415 offset
+ cfun_frame_layout
.gprs_offset
8417 - cfun_frame_layout
.first_save_gpr_slot
)
8419 addr
= gen_rtx_MEM (Pmode
, addr
);
8420 set_mem_alias_set (addr
, get_frame_alias_set ());
8421 emit_move_insn (return_reg
, addr
);
8425 insn
= restore_gprs (frame_pointer
,
8426 offset
+ cfun_frame_layout
.gprs_offset
8427 + (cfun_frame_layout
.first_restore_gpr
8428 - cfun_frame_layout
.first_save_gpr_slot
)
8430 cfun_frame_layout
.first_restore_gpr
,
8431 cfun_frame_layout
.last_restore_gpr
);
8432 insn
= emit_insn (insn
);
8433 REG_NOTES (insn
) = cfa_restores
;
8434 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8435 plus_constant (Pmode
, stack_pointer_rtx
,
8436 STACK_POINTER_OFFSET
));
8437 RTX_FRAME_RELATED_P (insn
) = 1;
8443 /* Return to caller. */
8445 p
= rtvec_alloc (2);
8447 RTVEC_ELT (p
, 0) = ret_rtx
;
8448 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8449 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8454 /* Return the size in bytes of a function argument of
8455 type TYPE and/or mode MODE. At least one of TYPE or
8456 MODE must be specified. */
8459 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8462 return int_size_in_bytes (type
);
8464 /* No type info available for some library calls ... */
8465 if (mode
!= BLKmode
)
8466 return GET_MODE_SIZE (mode
);
8468 /* If we have neither type nor mode, abort */
8472 /* Return true if a function argument of type TYPE and mode MODE
8473 is to be passed in a floating-point register, if available. */
8476 s390_function_arg_float (enum machine_mode mode
, const_tree type
)
8478 int size
= s390_function_arg_size (mode
, type
);
8482 /* Soft-float changes the ABI: no floating-point registers are used. */
8483 if (TARGET_SOFT_FLOAT
)
8486 /* No type info available for some library calls ... */
8488 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8490 /* The ABI says that record types with a single member are treated
8491 just like that member would be. */
8492 while (TREE_CODE (type
) == RECORD_TYPE
)
8494 tree field
, single
= NULL_TREE
;
8496 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8498 if (TREE_CODE (field
) != FIELD_DECL
)
8501 if (single
== NULL_TREE
)
8502 single
= TREE_TYPE (field
);
8507 if (single
== NULL_TREE
)
8513 return TREE_CODE (type
) == REAL_TYPE
;
8516 /* Return true if a function argument of type TYPE and mode MODE
8517 is to be passed in an integer register, or a pair of integer
8518 registers, if available. */
8521 s390_function_arg_integer (enum machine_mode mode
, const_tree type
)
8523 int size
= s390_function_arg_size (mode
, type
);
8527 /* No type info available for some library calls ... */
8529 return GET_MODE_CLASS (mode
) == MODE_INT
8530 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8532 /* We accept small integral (and similar) types. */
8533 if (INTEGRAL_TYPE_P (type
)
8534 || POINTER_TYPE_P (type
)
8535 || TREE_CODE (type
) == NULLPTR_TYPE
8536 || TREE_CODE (type
) == OFFSET_TYPE
8537 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8540 /* We also accept structs of size 1, 2, 4, 8 that are not
8541 passed in floating-point registers. */
8542 if (AGGREGATE_TYPE_P (type
)
8543 && exact_log2 (size
) >= 0
8544 && !s390_function_arg_float (mode
, type
))
8550 /* Return 1 if a function argument of type TYPE and mode MODE
8551 is to be passed by reference. The ABI specifies that only
8552 structures of size 1, 2, 4, or 8 bytes are passed by value,
8553 all other structures (and complex numbers) are passed by
8557 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
8558 enum machine_mode mode
, const_tree type
,
8559 bool named ATTRIBUTE_UNUSED
)
8561 int size
= s390_function_arg_size (mode
, type
);
8567 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8570 if (TREE_CODE (type
) == COMPLEX_TYPE
8571 || TREE_CODE (type
) == VECTOR_TYPE
)
8578 /* Update the data in CUM to advance over an argument of mode MODE and
8579 data type TYPE. (TYPE is null for libcalls where that information
8580 may not be available.). The boolean NAMED specifies whether the
8581 argument is a named argument (as opposed to an unnamed argument
8582 matching an ellipsis). */
8585 s390_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
8586 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8588 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8590 if (s390_function_arg_float (mode
, type
))
8594 else if (s390_function_arg_integer (mode
, type
))
8596 int size
= s390_function_arg_size (mode
, type
);
8597 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8603 /* Define where to put the arguments to a function.
8604 Value is zero to push the argument on the stack,
8605 or a hard register in which to store the argument.
8607 MODE is the argument's machine mode.
8608 TYPE is the data type of the argument (as a tree).
8609 This is null for libcalls where that information may
8611 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8612 the preceding args and about the function being called.
8613 NAMED is nonzero if this argument is a named parameter
8614 (otherwise it is an extra parameter matching an ellipsis).
8616 On S/390, we use general purpose registers 2 through 6 to
8617 pass integer, pointer, and certain structure arguments, and
8618 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8619 to pass floating point arguments. All remaining arguments
8620 are pushed to the stack. */
8623 s390_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
8624 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8626 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8628 if (s390_function_arg_float (mode
, type
))
8630 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8633 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8635 else if (s390_function_arg_integer (mode
, type
))
8637 int size
= s390_function_arg_size (mode
, type
);
8638 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8640 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8642 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8643 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8644 else if (n_gprs
== 2)
8646 rtvec p
= rtvec_alloc (2);
8649 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8652 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8655 return gen_rtx_PARALLEL (mode
, p
);
8659 /* After the real arguments, expand_call calls us once again
8660 with a void_type_node type. Whatever we return here is
8661 passed as operand 2 to the call expanders.
8663 We don't need this feature ... */
8664 else if (type
== void_type_node
)
8670 /* Return true if return values of type TYPE should be returned
8671 in a memory buffer whose address is passed by the caller as
8672 hidden first argument. */
8675 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8677 /* We accept small integral (and similar) types. */
8678 if (INTEGRAL_TYPE_P (type
)
8679 || POINTER_TYPE_P (type
)
8680 || TREE_CODE (type
) == OFFSET_TYPE
8681 || TREE_CODE (type
) == REAL_TYPE
)
8682 return int_size_in_bytes (type
) > 8;
8684 /* Aggregates and similar constructs are always returned
8686 if (AGGREGATE_TYPE_P (type
)
8687 || TREE_CODE (type
) == COMPLEX_TYPE
8688 || TREE_CODE (type
) == VECTOR_TYPE
)
8691 /* ??? We get called on all sorts of random stuff from
8692 aggregate_value_p. We can't abort, but it's not clear
8693 what's safe to return. Pretend it's a struct I guess. */
8697 /* Function arguments and return values are promoted to word size. */
8699 static enum machine_mode
8700 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8702 const_tree fntype ATTRIBUTE_UNUSED
,
8703 int for_return ATTRIBUTE_UNUSED
)
8705 if (INTEGRAL_MODE_P (mode
)
8706 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8708 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
8709 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8716 /* Define where to return a (scalar) value of type RET_TYPE.
8717 If RET_TYPE is null, define where to return a (scalar)
8718 value of mode MODE from a libcall. */
8721 s390_function_and_libcall_value (enum machine_mode mode
,
8722 const_tree ret_type
,
8723 const_tree fntype_or_decl
,
8724 bool outgoing ATTRIBUTE_UNUSED
)
8726 /* For normal functions perform the promotion as
8727 promote_function_mode would do. */
8730 int unsignedp
= TYPE_UNSIGNED (ret_type
);
8731 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
8735 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8736 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8738 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8739 return gen_rtx_REG (mode
, 16);
8740 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8741 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8742 return gen_rtx_REG (mode
, 2);
8743 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8745 /* This case is triggered when returning a 64 bit value with
8746 -m31 -mzarch. Although the value would fit into a single
8747 register it has to be forced into a 32 bit register pair in
8748 order to match the ABI. */
8749 rtvec p
= rtvec_alloc (2);
8752 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8754 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8756 return gen_rtx_PARALLEL (mode
, p
);
8762 /* Define where to return a scalar return value of type RET_TYPE. */
8765 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
8768 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
8769 fn_decl_or_type
, outgoing
);
8772 /* Define where to return a scalar libcall return value of mode
8776 s390_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
8778 return s390_function_and_libcall_value (mode
, NULL_TREE
,
8783 /* Create and return the va_list datatype.
8785 On S/390, va_list is an array type equivalent to
8787 typedef struct __va_list_tag
8791 void *__overflow_arg_area;
8792 void *__reg_save_area;
8795 where __gpr and __fpr hold the number of general purpose
8796 or floating point arguments used up to now, respectively,
8797 __overflow_arg_area points to the stack location of the
8798 next argument passed on the stack, and __reg_save_area
8799 always points to the start of the register area in the
8800 call frame of the current function. The function prologue
8801 saves all registers used for argument passing into this
8802 area if the function uses variable arguments. */
8805 s390_build_builtin_va_list (void)
8807 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8809 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8812 build_decl (BUILTINS_LOCATION
,
8813 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8815 f_gpr
= build_decl (BUILTINS_LOCATION
,
8816 FIELD_DECL
, get_identifier ("__gpr"),
8817 long_integer_type_node
);
8818 f_fpr
= build_decl (BUILTINS_LOCATION
,
8819 FIELD_DECL
, get_identifier ("__fpr"),
8820 long_integer_type_node
);
8821 f_ovf
= build_decl (BUILTINS_LOCATION
,
8822 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8824 f_sav
= build_decl (BUILTINS_LOCATION
,
8825 FIELD_DECL
, get_identifier ("__reg_save_area"),
8828 va_list_gpr_counter_field
= f_gpr
;
8829 va_list_fpr_counter_field
= f_fpr
;
8831 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8832 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8833 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8834 DECL_FIELD_CONTEXT (f_sav
) = record
;
8836 TYPE_STUB_DECL (record
) = type_decl
;
8837 TYPE_NAME (record
) = type_decl
;
8838 TYPE_FIELDS (record
) = f_gpr
;
8839 DECL_CHAIN (f_gpr
) = f_fpr
;
8840 DECL_CHAIN (f_fpr
) = f_ovf
;
8841 DECL_CHAIN (f_ovf
) = f_sav
;
8843 layout_type (record
);
8845 /* The correct type is an array type of one element. */
8846 return build_array_type (record
, build_index_type (size_zero_node
));
8849 /* Implement va_start by filling the va_list structure VALIST.
8850 STDARG_P is always true, and ignored.
8851 NEXTARG points to the first anonymous stack argument.
8853 The following global variables are used to initialize
8854 the va_list structure:
8857 holds number of gprs and fprs used for named arguments.
8858 crtl->args.arg_offset_rtx:
8859 holds the offset of the first anonymous stack argument
8860 (relative to the virtual arg pointer). */
8863 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8865 HOST_WIDE_INT n_gpr
, n_fpr
;
8867 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8868 tree gpr
, fpr
, ovf
, sav
, t
;
8870 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8871 f_fpr
= DECL_CHAIN (f_gpr
);
8872 f_ovf
= DECL_CHAIN (f_fpr
);
8873 f_sav
= DECL_CHAIN (f_ovf
);
8875 valist
= build_simple_mem_ref (valist
);
8876 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8877 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8878 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8879 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8881 /* Count number of gp and fp argument registers used. */
8883 n_gpr
= crtl
->args
.info
.gprs
;
8884 n_fpr
= crtl
->args
.info
.fprs
;
8886 if (cfun
->va_list_gpr_size
)
8888 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8889 build_int_cst (NULL_TREE
, n_gpr
));
8890 TREE_SIDE_EFFECTS (t
) = 1;
8891 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8894 if (cfun
->va_list_fpr_size
)
8896 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8897 build_int_cst (NULL_TREE
, n_fpr
));
8898 TREE_SIDE_EFFECTS (t
) = 1;
8899 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8902 /* Find the overflow area. */
8903 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8904 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8906 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8908 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8909 off
= off
< 0 ? 0 : off
;
8910 if (TARGET_DEBUG_ARG
)
8911 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8912 (int)n_gpr
, (int)n_fpr
, off
);
8914 t
= fold_build_pointer_plus_hwi (t
, off
);
8916 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8917 TREE_SIDE_EFFECTS (t
) = 1;
8918 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8921 /* Find the register save area. */
8922 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8923 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8925 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8926 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
8928 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8929 TREE_SIDE_EFFECTS (t
) = 1;
8930 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8934 /* Implement va_arg by updating the va_list structure
8935 VALIST as required to retrieve an argument of type
8936 TYPE, and returning that argument.
8938 Generates code equivalent to:
8940 if (integral value) {
8941 if (size <= 4 && args.gpr < 5 ||
8942 size > 4 && args.gpr < 4 )
8943 ret = args.reg_save_area[args.gpr+8]
8945 ret = *args.overflow_arg_area++;
8946 } else if (float value) {
8948 ret = args.reg_save_area[args.fpr+64]
8950 ret = *args.overflow_arg_area++;
8951 } else if (aggregate value) {
8953 ret = *args.reg_save_area[args.gpr]
8955 ret = **args.overflow_arg_area++;
8959 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8960 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8962 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8963 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8964 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8965 tree lab_false
, lab_over
, addr
;
8967 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8968 f_fpr
= DECL_CHAIN (f_gpr
);
8969 f_ovf
= DECL_CHAIN (f_fpr
);
8970 f_sav
= DECL_CHAIN (f_ovf
);
8972 valist
= build_va_arg_indirect_ref (valist
);
8973 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8974 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8975 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8977 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8978 both appear on a lhs. */
8979 valist
= unshare_expr (valist
);
8980 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8982 size
= int_size_in_bytes (type
);
8984 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8986 if (TARGET_DEBUG_ARG
)
8988 fprintf (stderr
, "va_arg: aggregate type");
8992 /* Aggregates are passed by reference. */
8997 /* kernel stack layout on 31 bit: It is assumed here that no padding
8998 will be added by s390_frame_info because for va_args always an even
8999 number of gprs has to be saved r15-r2 = 14 regs. */
9000 sav_ofs
= 2 * UNITS_PER_LONG
;
9001 sav_scale
= UNITS_PER_LONG
;
9002 size
= UNITS_PER_LONG
;
9003 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9005 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
9007 if (TARGET_DEBUG_ARG
)
9009 fprintf (stderr
, "va_arg: float type");
9013 /* FP args go in FP registers, if present. */
9017 sav_ofs
= 16 * UNITS_PER_LONG
;
9019 max_reg
= FP_ARG_NUM_REG
- n_reg
;
9023 if (TARGET_DEBUG_ARG
)
9025 fprintf (stderr
, "va_arg: other type");
9029 /* Otherwise into GP registers. */
9032 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9034 /* kernel stack layout on 31 bit: It is assumed here that no padding
9035 will be added by s390_frame_info because for va_args always an even
9036 number of gprs has to be saved r15-r2 = 14 regs. */
9037 sav_ofs
= 2 * UNITS_PER_LONG
;
9039 if (size
< UNITS_PER_LONG
)
9040 sav_ofs
+= UNITS_PER_LONG
- size
;
9042 sav_scale
= UNITS_PER_LONG
;
9043 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9046 /* Pull the value out of the saved registers ... */
9048 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
9049 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
9050 addr
= create_tmp_var (ptr_type_node
, "addr");
9052 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
9053 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
9054 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9055 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9056 gimplify_and_add (t
, pre_p
);
9058 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9059 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
9060 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
9061 t
= fold_build_pointer_plus (t
, u
);
9063 gimplify_assign (addr
, t
, pre_p
);
9065 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9067 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
9070 /* ... Otherwise out of the overflow area. */
9073 if (size
< UNITS_PER_LONG
)
9074 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
9076 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9078 gimplify_assign (addr
, t
, pre_p
);
9080 t
= fold_build_pointer_plus_hwi (t
, size
);
9081 gimplify_assign (ovf
, t
, pre_p
);
9083 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
9086 /* Increment register save count. */
9088 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
9089 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
9090 gimplify_and_add (u
, pre_p
);
9094 t
= build_pointer_type_for_mode (build_pointer_type (type
),
9096 addr
= fold_convert (t
, addr
);
9097 addr
= build_va_arg_indirect_ref (addr
);
9101 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9102 addr
= fold_convert (t
, addr
);
9105 return build_va_arg_indirect_ref (addr
);
9113 S390_BUILTIN_THREAD_POINTER
,
9114 S390_BUILTIN_SET_THREAD_POINTER
,
9119 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
9124 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
9130 s390_init_builtins (void)
9134 ftype
= build_function_type_list (ptr_type_node
, NULL_TREE
);
9135 add_builtin_function ("__builtin_thread_pointer", ftype
,
9136 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
9139 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
9140 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
9141 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
9145 /* Expand an expression EXP that calls a built-in function,
9146 with result going to TARGET if that's convenient
9147 (and in mode MODE if that's convenient).
9148 SUBTARGET may be used as the target for computing one of EXP's operands.
9149 IGNORE is nonzero if the value is to be ignored. */
9152 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9153 enum machine_mode mode ATTRIBUTE_UNUSED
,
9154 int ignore ATTRIBUTE_UNUSED
)
9158 enum insn_code
const *code_for_builtin
=
9159 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
9161 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9162 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9163 enum insn_code icode
;
9164 rtx op
[MAX_ARGS
], pat
;
9168 call_expr_arg_iterator iter
;
9170 if (fcode
>= S390_BUILTIN_max
)
9171 internal_error ("bad builtin fcode");
9172 icode
= code_for_builtin
[fcode
];
9174 internal_error ("bad builtin fcode");
9176 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9179 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9181 const struct insn_operand_data
*insn_op
;
9183 if (arg
== error_mark_node
)
9185 if (arity
> MAX_ARGS
)
9188 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
9190 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
9192 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
9193 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
9199 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9201 || GET_MODE (target
) != tmode
9202 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9203 target
= gen_reg_rtx (tmode
);
9209 pat
= GEN_FCN (icode
) (target
);
9213 pat
= GEN_FCN (icode
) (target
, op
[0]);
9215 pat
= GEN_FCN (icode
) (op
[0]);
9218 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9234 /* Output assembly code for the trampoline template to
9237 On S/390, we use gpr 1 internally in the trampoline code;
9238 gpr 0 is used to hold the static chain. */
9241 s390_asm_trampoline_template (FILE *file
)
9244 op
[0] = gen_rtx_REG (Pmode
, 0);
9245 op
[1] = gen_rtx_REG (Pmode
, 1);
9249 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
9250 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
9251 output_asm_insn ("br\t%1", op
); /* 2 byte */
9252 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9256 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
9257 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
9258 output_asm_insn ("br\t%1", op
); /* 2 byte */
9259 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9263 /* Emit RTL insns to initialize the variable parts of a trampoline.
9264 FNADDR is an RTX for the address of the function's pure code.
9265 CXT is an RTX for the static chain value for the function. */
9268 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9270 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9273 emit_block_move (m_tramp
, assemble_trampoline_template (),
9274 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
9276 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
9277 emit_move_insn (mem
, cxt
);
9278 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
9279 emit_move_insn (mem
, fnaddr
);
9282 /* Output assembler code to FILE to increment profiler label # LABELNO
9283 for profiling a function entry. */
9286 s390_function_profiler (FILE *file
, int labelno
)
9291 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9293 fprintf (file
, "# function profiler \n");
9295 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9296 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9297 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
9299 op
[2] = gen_rtx_REG (Pmode
, 1);
9300 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9301 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9303 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9306 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9307 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9312 output_asm_insn ("stg\t%0,%1", op
);
9313 output_asm_insn ("larl\t%2,%3", op
);
9314 output_asm_insn ("brasl\t%0,%4", op
);
9315 output_asm_insn ("lg\t%0,%1", op
);
9319 op
[6] = gen_label_rtx ();
9321 output_asm_insn ("st\t%0,%1", op
);
9322 output_asm_insn ("bras\t%2,%l6", op
);
9323 output_asm_insn (".long\t%4", op
);
9324 output_asm_insn (".long\t%3", op
);
9325 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9326 output_asm_insn ("l\t%0,0(%2)", op
);
9327 output_asm_insn ("l\t%2,4(%2)", op
);
9328 output_asm_insn ("basr\t%0,%0", op
);
9329 output_asm_insn ("l\t%0,%1", op
);
9333 op
[5] = gen_label_rtx ();
9334 op
[6] = gen_label_rtx ();
9336 output_asm_insn ("st\t%0,%1", op
);
9337 output_asm_insn ("bras\t%2,%l6", op
);
9338 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9339 output_asm_insn (".long\t%4-%l5", op
);
9340 output_asm_insn (".long\t%3-%l5", op
);
9341 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9342 output_asm_insn ("lr\t%0,%2", op
);
9343 output_asm_insn ("a\t%0,0(%2)", op
);
9344 output_asm_insn ("a\t%2,4(%2)", op
);
9345 output_asm_insn ("basr\t%0,%0", op
);
9346 output_asm_insn ("l\t%0,%1", op
);
9350 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9351 into its SYMBOL_REF_FLAGS. */
9354 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9356 default_encode_section_info (decl
, rtl
, first
);
9358 if (TREE_CODE (decl
) == VAR_DECL
)
9360 /* If a variable has a forced alignment to < 2 bytes, mark it
9361 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9363 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9364 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9365 if (!DECL_SIZE (decl
)
9366 || !DECL_ALIGN (decl
)
9367 || !host_integerp (DECL_SIZE (decl
), 0)
9368 || (DECL_ALIGN (decl
) <= 64
9369 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9370 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9373 /* Literal pool references don't have a decl so they are handled
9374 differently here. We rely on the information in the MEM_ALIGN
9375 entry to decide upon natural alignment. */
9377 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9378 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9379 && (MEM_ALIGN (rtl
) == 0
9380 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9381 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9382 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9385 /* Output thunk to FILE that implements a C++ virtual function call (with
9386 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9387 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9388 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9389 relative to the resulting this pointer. */
9392 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9393 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9399 /* Make sure unwind info is emitted for the thunk if needed. */
9400 final_start_function (emit_barrier (), file
, 1);
9402 /* Operand 0 is the target function. */
9403 op
[0] = XEXP (DECL_RTL (function
), 0);
9404 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9407 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9408 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9409 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9412 /* Operand 1 is the 'this' pointer. */
9413 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9414 op
[1] = gen_rtx_REG (Pmode
, 3);
9416 op
[1] = gen_rtx_REG (Pmode
, 2);
9418 /* Operand 2 is the delta. */
9419 op
[2] = GEN_INT (delta
);
9421 /* Operand 3 is the vcall_offset. */
9422 op
[3] = GEN_INT (vcall_offset
);
9424 /* Operand 4 is the temporary register. */
9425 op
[4] = gen_rtx_REG (Pmode
, 1);
9427 /* Operands 5 to 8 can be used as labels. */
9433 /* Operand 9 can be used for temporary register. */
9436 /* Generate code. */
9439 /* Setup literal pool pointer if required. */
9440 if ((!DISP_IN_RANGE (delta
)
9441 && !CONST_OK_FOR_K (delta
)
9442 && !CONST_OK_FOR_Os (delta
))
9443 || (!DISP_IN_RANGE (vcall_offset
)
9444 && !CONST_OK_FOR_K (vcall_offset
)
9445 && !CONST_OK_FOR_Os (vcall_offset
)))
9447 op
[5] = gen_label_rtx ();
9448 output_asm_insn ("larl\t%4,%5", op
);
9451 /* Add DELTA to this pointer. */
9454 if (CONST_OK_FOR_J (delta
))
9455 output_asm_insn ("la\t%1,%2(%1)", op
);
9456 else if (DISP_IN_RANGE (delta
))
9457 output_asm_insn ("lay\t%1,%2(%1)", op
);
9458 else if (CONST_OK_FOR_K (delta
))
9459 output_asm_insn ("aghi\t%1,%2", op
);
9460 else if (CONST_OK_FOR_Os (delta
))
9461 output_asm_insn ("agfi\t%1,%2", op
);
9464 op
[6] = gen_label_rtx ();
9465 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9469 /* Perform vcall adjustment. */
9472 if (DISP_IN_RANGE (vcall_offset
))
9474 output_asm_insn ("lg\t%4,0(%1)", op
);
9475 output_asm_insn ("ag\t%1,%3(%4)", op
);
9477 else if (CONST_OK_FOR_K (vcall_offset
))
9479 output_asm_insn ("lghi\t%4,%3", op
);
9480 output_asm_insn ("ag\t%4,0(%1)", op
);
9481 output_asm_insn ("ag\t%1,0(%4)", op
);
9483 else if (CONST_OK_FOR_Os (vcall_offset
))
9485 output_asm_insn ("lgfi\t%4,%3", op
);
9486 output_asm_insn ("ag\t%4,0(%1)", op
);
9487 output_asm_insn ("ag\t%1,0(%4)", op
);
9491 op
[7] = gen_label_rtx ();
9492 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9493 output_asm_insn ("ag\t%4,0(%1)", op
);
9494 output_asm_insn ("ag\t%1,0(%4)", op
);
9498 /* Jump to target. */
9499 output_asm_insn ("jg\t%0", op
);
9501 /* Output literal pool if required. */
9504 output_asm_insn (".align\t4", op
);
9505 targetm
.asm_out
.internal_label (file
, "L",
9506 CODE_LABEL_NUMBER (op
[5]));
9510 targetm
.asm_out
.internal_label (file
, "L",
9511 CODE_LABEL_NUMBER (op
[6]));
9512 output_asm_insn (".long\t%2", op
);
9516 targetm
.asm_out
.internal_label (file
, "L",
9517 CODE_LABEL_NUMBER (op
[7]));
9518 output_asm_insn (".long\t%3", op
);
9523 /* Setup base pointer if required. */
9525 || (!DISP_IN_RANGE (delta
)
9526 && !CONST_OK_FOR_K (delta
)
9527 && !CONST_OK_FOR_Os (delta
))
9528 || (!DISP_IN_RANGE (delta
)
9529 && !CONST_OK_FOR_K (vcall_offset
)
9530 && !CONST_OK_FOR_Os (vcall_offset
)))
9532 op
[5] = gen_label_rtx ();
9533 output_asm_insn ("basr\t%4,0", op
);
9534 targetm
.asm_out
.internal_label (file
, "L",
9535 CODE_LABEL_NUMBER (op
[5]));
9538 /* Add DELTA to this pointer. */
9541 if (CONST_OK_FOR_J (delta
))
9542 output_asm_insn ("la\t%1,%2(%1)", op
);
9543 else if (DISP_IN_RANGE (delta
))
9544 output_asm_insn ("lay\t%1,%2(%1)", op
);
9545 else if (CONST_OK_FOR_K (delta
))
9546 output_asm_insn ("ahi\t%1,%2", op
);
9547 else if (CONST_OK_FOR_Os (delta
))
9548 output_asm_insn ("afi\t%1,%2", op
);
9551 op
[6] = gen_label_rtx ();
9552 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9556 /* Perform vcall adjustment. */
9559 if (CONST_OK_FOR_J (vcall_offset
))
9561 output_asm_insn ("l\t%4,0(%1)", op
);
9562 output_asm_insn ("a\t%1,%3(%4)", op
);
9564 else if (DISP_IN_RANGE (vcall_offset
))
9566 output_asm_insn ("l\t%4,0(%1)", op
);
9567 output_asm_insn ("ay\t%1,%3(%4)", op
);
9569 else if (CONST_OK_FOR_K (vcall_offset
))
9571 output_asm_insn ("lhi\t%4,%3", op
);
9572 output_asm_insn ("a\t%4,0(%1)", op
);
9573 output_asm_insn ("a\t%1,0(%4)", op
);
9575 else if (CONST_OK_FOR_Os (vcall_offset
))
9577 output_asm_insn ("iilf\t%4,%3", op
);
9578 output_asm_insn ("a\t%4,0(%1)", op
);
9579 output_asm_insn ("a\t%1,0(%4)", op
);
9583 op
[7] = gen_label_rtx ();
9584 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9585 output_asm_insn ("a\t%4,0(%1)", op
);
9586 output_asm_insn ("a\t%1,0(%4)", op
);
9589 /* We had to clobber the base pointer register.
9590 Re-setup the base pointer (with a different base). */
9591 op
[5] = gen_label_rtx ();
9592 output_asm_insn ("basr\t%4,0", op
);
9593 targetm
.asm_out
.internal_label (file
, "L",
9594 CODE_LABEL_NUMBER (op
[5]));
9597 /* Jump to target. */
9598 op
[8] = gen_label_rtx ();
9601 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9603 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9604 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9605 else if (flag_pic
== 1)
9607 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9608 output_asm_insn ("l\t%4,%0(%4)", op
);
9610 else if (flag_pic
== 2)
9612 op
[9] = gen_rtx_REG (Pmode
, 0);
9613 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9614 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9615 output_asm_insn ("ar\t%4,%9", op
);
9616 output_asm_insn ("l\t%4,0(%4)", op
);
9619 output_asm_insn ("br\t%4", op
);
9621 /* Output literal pool. */
9622 output_asm_insn (".align\t4", op
);
9624 if (nonlocal
&& flag_pic
== 2)
9625 output_asm_insn (".long\t%0", op
);
9628 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9629 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9632 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9634 output_asm_insn (".long\t%0", op
);
9636 output_asm_insn (".long\t%0-%5", op
);
9640 targetm
.asm_out
.internal_label (file
, "L",
9641 CODE_LABEL_NUMBER (op
[6]));
9642 output_asm_insn (".long\t%2", op
);
9646 targetm
.asm_out
.internal_label (file
, "L",
9647 CODE_LABEL_NUMBER (op
[7]));
9648 output_asm_insn (".long\t%3", op
);
9651 final_end_function ();
9655 s390_valid_pointer_mode (enum machine_mode mode
)
9657 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9660 /* Checks whether the given CALL_EXPR would use a caller
9661 saved register. This is used to decide whether sibling call
9662 optimization could be performed on the respective function
9666 s390_call_saved_register_used (tree call_expr
)
9668 CUMULATIVE_ARGS cum_v
;
9669 cumulative_args_t cum
;
9671 enum machine_mode mode
;
9676 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
9677 cum
= pack_cumulative_args (&cum_v
);
9679 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9681 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9682 gcc_assert (parameter
);
9684 /* For an undeclared variable passed as parameter we will get
9685 an ERROR_MARK node here. */
9686 if (TREE_CODE (parameter
) == ERROR_MARK
)
9689 type
= TREE_TYPE (parameter
);
9692 mode
= TYPE_MODE (type
);
9695 if (pass_by_reference (&cum_v
, mode
, type
, true))
9698 type
= build_pointer_type (type
);
9701 parm_rtx
= s390_function_arg (cum
, mode
, type
, 0);
9703 s390_function_arg_advance (cum
, mode
, type
, 0);
9708 if (REG_P (parm_rtx
))
9711 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9713 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9717 if (GET_CODE (parm_rtx
) == PARALLEL
)
9721 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9723 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9725 gcc_assert (REG_P (r
));
9728 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9730 if (!call_used_regs
[reg
+ REGNO (r
)])
9739 /* Return true if the given call expression can be
9740 turned into a sibling call.
9741 DECL holds the declaration of the function to be called whereas
9742 EXP is the call expression itself. */
9745 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9747 /* The TPF epilogue uses register 1. */
9748 if (TARGET_TPF_PROFILING
)
9751 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9752 which would have to be restored before the sibcall. */
9753 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9756 /* Register 6 on s390 is available as an argument register but unfortunately
9757 "caller saved". This makes functions needing this register for arguments
9758 not suitable for sibcalls. */
9759 return !s390_call_saved_register_used (exp
);
9762 /* Return the fixed registers used for condition codes. */
9765 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9768 *p2
= INVALID_REGNUM
;
9773 /* This function is used by the call expanders of the machine description.
9774 It emits the call insn itself together with the necessary operations
9775 to adjust the target address and returns the emitted insn.
9776 ADDR_LOCATION is the target address rtx
9777 TLS_CALL the location of the thread-local symbol
9778 RESULT_REG the register where the result of the call should be stored
9779 RETADDR_REG the register where the return address should be stored
9780 If this parameter is NULL_RTX the call is considered
9781 to be a sibling call. */
9784 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9787 bool plt_call
= false;
9793 /* Direct function calls need special treatment. */
9794 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9796 /* When calling a global routine in PIC mode, we must
9797 replace the symbol itself with the PLT stub. */
9798 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9800 if (retaddr_reg
!= NULL_RTX
)
9802 addr_location
= gen_rtx_UNSPEC (Pmode
,
9803 gen_rtvec (1, addr_location
),
9805 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9809 /* For -fpic code the PLT entries might use r12 which is
9810 call-saved. Therefore we cannot do a sibcall when
9811 calling directly using a symbol ref. When reaching
9812 this point we decided (in s390_function_ok_for_sibcall)
9813 to do a sibcall for a function pointer but one of the
9814 optimizers was able to get rid of the function pointer
9815 by propagating the symbol ref into the call. This
9816 optimization is illegal for S/390 so we turn the direct
9817 call into a indirect call again. */
9818 addr_location
= force_reg (Pmode
, addr_location
);
9821 /* Unless we can use the bras(l) insn, force the
9822 routine address into a register. */
9823 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9826 addr_location
= legitimize_pic_address (addr_location
, 0);
9828 addr_location
= force_reg (Pmode
, addr_location
);
9832 /* If it is already an indirect call or the code above moved the
9833 SYMBOL_REF to somewhere else make sure the address can be found in
9835 if (retaddr_reg
== NULL_RTX
9836 && GET_CODE (addr_location
) != SYMBOL_REF
9839 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9840 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9843 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9844 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9846 if (result_reg
!= NULL_RTX
)
9847 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9849 if (retaddr_reg
!= NULL_RTX
)
9851 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9853 if (tls_call
!= NULL_RTX
)
9854 vec
= gen_rtvec (3, call
, clobber
,
9855 gen_rtx_USE (VOIDmode
, tls_call
));
9857 vec
= gen_rtvec (2, call
, clobber
);
9859 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9862 insn
= emit_call_insn (call
);
9864 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9865 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9867 /* s390_function_ok_for_sibcall should
9868 have denied sibcalls in this case. */
9869 gcc_assert (retaddr_reg
!= NULL_RTX
);
9870 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
9875 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9878 s390_conditional_register_usage (void)
9884 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9885 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9887 if (TARGET_CPU_ZARCH
)
9889 fixed_regs
[BASE_REGNUM
] = 0;
9890 call_used_regs
[BASE_REGNUM
] = 0;
9891 fixed_regs
[RETURN_REGNUM
] = 0;
9892 call_used_regs
[RETURN_REGNUM
] = 0;
9896 for (i
= 24; i
< 32; i
++)
9897 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9901 for (i
= 18; i
< 20; i
++)
9902 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9905 if (TARGET_SOFT_FLOAT
)
9907 for (i
= 16; i
< 32; i
++)
9908 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9912 /* Corresponding function to eh_return expander. */
9914 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9916 s390_emit_tpf_eh_return (rtx target
)
9920 if (!s390_tpf_eh_return_symbol
)
9921 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9923 reg
= gen_rtx_REG (Pmode
, 2);
9925 emit_move_insn (reg
, target
);
9926 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9927 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9928 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9930 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9933 /* Rework the prologue/epilogue to avoid saving/restoring
9934 registers unnecessarily. */
9937 s390_optimize_prologue (void)
9939 rtx insn
, new_insn
, next_insn
;
9941 /* Do a final recompute of the frame-related data. */
9943 s390_update_frame_layout ();
9945 /* If all special registers are in fact used, there's nothing we
9946 can do, so no point in walking the insn list. */
9948 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9949 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9950 && (TARGET_CPU_ZARCH
9951 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9952 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9955 /* Search for prologue/epilogue insns and replace them. */
9957 for (insn
= get_insns (); insn
; insn
= next_insn
)
9959 int first
, last
, off
;
9960 rtx set
, base
, offset
;
9962 next_insn
= NEXT_INSN (insn
);
9964 if (GET_CODE (insn
) != INSN
)
9967 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9968 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9970 set
= XVECEXP (PATTERN (insn
), 0, 0);
9971 first
= REGNO (SET_SRC (set
));
9972 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9973 offset
= const0_rtx
;
9974 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9975 off
= INTVAL (offset
);
9977 if (GET_CODE (base
) != REG
|| off
< 0)
9979 if (cfun_frame_layout
.first_save_gpr
!= -1
9980 && (cfun_frame_layout
.first_save_gpr
< first
9981 || cfun_frame_layout
.last_save_gpr
> last
))
9983 if (REGNO (base
) != STACK_POINTER_REGNUM
9984 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9986 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9989 if (cfun_frame_layout
.first_save_gpr
!= -1)
9991 new_insn
= save_gprs (base
,
9992 off
+ (cfun_frame_layout
.first_save_gpr
9993 - first
) * UNITS_PER_LONG
,
9994 cfun_frame_layout
.first_save_gpr
,
9995 cfun_frame_layout
.last_save_gpr
);
9996 new_insn
= emit_insn_before (new_insn
, insn
);
9997 INSN_ADDRESSES_NEW (new_insn
, -1);
10000 remove_insn (insn
);
10004 if (cfun_frame_layout
.first_save_gpr
== -1
10005 && GET_CODE (PATTERN (insn
)) == SET
10006 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
10007 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
10008 || (!TARGET_CPU_ZARCH
10009 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
10010 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
10012 set
= PATTERN (insn
);
10013 first
= REGNO (SET_SRC (set
));
10014 offset
= const0_rtx
;
10015 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10016 off
= INTVAL (offset
);
10018 if (GET_CODE (base
) != REG
|| off
< 0)
10020 if (REGNO (base
) != STACK_POINTER_REGNUM
10021 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10024 remove_insn (insn
);
10028 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10029 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
10031 set
= XVECEXP (PATTERN (insn
), 0, 0);
10032 first
= REGNO (SET_DEST (set
));
10033 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
10034 offset
= const0_rtx
;
10035 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10036 off
= INTVAL (offset
);
10038 if (GET_CODE (base
) != REG
|| off
< 0)
10040 if (cfun_frame_layout
.first_restore_gpr
!= -1
10041 && (cfun_frame_layout
.first_restore_gpr
< first
10042 || cfun_frame_layout
.last_restore_gpr
> last
))
10044 if (REGNO (base
) != STACK_POINTER_REGNUM
10045 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10047 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10050 if (cfun_frame_layout
.first_restore_gpr
!= -1)
10052 new_insn
= restore_gprs (base
,
10053 off
+ (cfun_frame_layout
.first_restore_gpr
10054 - first
) * UNITS_PER_LONG
,
10055 cfun_frame_layout
.first_restore_gpr
,
10056 cfun_frame_layout
.last_restore_gpr
);
10057 new_insn
= emit_insn_before (new_insn
, insn
);
10058 INSN_ADDRESSES_NEW (new_insn
, -1);
10061 remove_insn (insn
);
10065 if (cfun_frame_layout
.first_restore_gpr
== -1
10066 && GET_CODE (PATTERN (insn
)) == SET
10067 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
10068 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
10069 || (!TARGET_CPU_ZARCH
10070 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
10071 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
10073 set
= PATTERN (insn
);
10074 first
= REGNO (SET_DEST (set
));
10075 offset
= const0_rtx
;
10076 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10077 off
= INTVAL (offset
);
10079 if (GET_CODE (base
) != REG
|| off
< 0)
10081 if (REGNO (base
) != STACK_POINTER_REGNUM
10082 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10085 remove_insn (insn
);
10091 /* On z10 and later the dynamic branch prediction must see the
10092 backward jump within a certain windows. If not it falls back to
10093 the static prediction. This function rearranges the loop backward
10094 branch in a way which makes the static prediction always correct.
10095 The function returns true if it added an instruction. */
10097 s390_fix_long_loop_prediction (rtx insn
)
10099 rtx set
= single_set (insn
);
10100 rtx code_label
, label_ref
, new_label
;
10106 /* This will exclude branch on count and branch on index patterns
10107 since these are correctly statically predicted. */
10109 || SET_DEST (set
) != pc_rtx
10110 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
10113 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
10114 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
10116 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
10118 code_label
= XEXP (label_ref
, 0);
10120 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
10121 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
10122 || (INSN_ADDRESSES (INSN_UID (insn
))
10123 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
10126 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
10127 distance
< PREDICT_DISTANCE
- 6;
10128 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
10129 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
10132 new_label
= gen_label_rtx ();
10133 uncond_jump
= emit_jump_insn_after (
10134 gen_rtx_SET (VOIDmode
, pc_rtx
,
10135 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
10137 emit_label_after (new_label
, uncond_jump
);
10139 tmp
= XEXP (SET_SRC (set
), 1);
10140 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
10141 XEXP (SET_SRC (set
), 2) = tmp
;
10142 INSN_CODE (insn
) = -1;
10144 XEXP (label_ref
, 0) = new_label
;
10145 JUMP_LABEL (insn
) = new_label
;
10146 JUMP_LABEL (uncond_jump
) = code_label
;
10151 /* Returns 1 if INSN reads the value of REG for purposes not related
10152 to addressing of memory, and 0 otherwise. */
10154 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
10156 return reg_referenced_p (reg
, PATTERN (insn
))
10157 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
10160 /* Starting from INSN find_cond_jump looks downwards in the insn
10161 stream for a single jump insn which is the last user of the
10162 condition code set in INSN. */
10164 find_cond_jump (rtx insn
)
10166 for (; insn
; insn
= NEXT_INSN (insn
))
10170 if (LABEL_P (insn
))
10173 if (!JUMP_P (insn
))
10175 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10180 /* This will be triggered by a return. */
10181 if (GET_CODE (PATTERN (insn
)) != SET
)
10184 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10185 ite
= SET_SRC (PATTERN (insn
));
10187 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10190 cc
= XEXP (XEXP (ite
, 0), 0);
10191 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10194 if (find_reg_note (insn
, REG_DEAD
, cc
))
10202 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10203 the semantics does not change. If NULL_RTX is passed as COND the
10204 function tries to find the conditional jump starting with INSN. */
10206 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10210 if (cond
== NULL_RTX
)
10212 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10213 jump
= jump
? single_set (jump
) : NULL_RTX
;
10215 if (jump
== NULL_RTX
)
10218 cond
= XEXP (XEXP (jump
, 1), 0);
10223 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10226 /* On z10, instructions of the compare-and-branch family have the
10227 property to access the register occurring as second operand with
10228 its bits complemented. If such a compare is grouped with a second
10229 instruction that accesses the same register non-complemented, and
10230 if that register's value is delivered via a bypass, then the
10231 pipeline recycles, thereby causing significant performance decline.
10232 This function locates such situations and exchanges the two
10233 operands of the compare. The function return true whenever it
10236 s390_z10_optimize_cmp (rtx insn
)
10238 rtx prev_insn
, next_insn
;
10239 bool insn_added_p
= false;
10240 rtx cond
, *op0
, *op1
;
10242 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10244 /* Handle compare and branch and branch on count
10246 rtx pattern
= single_set (insn
);
10249 || SET_DEST (pattern
) != pc_rtx
10250 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10253 cond
= XEXP (SET_SRC (pattern
), 0);
10254 op0
= &XEXP (cond
, 0);
10255 op1
= &XEXP (cond
, 1);
10257 else if (GET_CODE (PATTERN (insn
)) == SET
)
10261 /* Handle normal compare instructions. */
10262 src
= SET_SRC (PATTERN (insn
));
10263 dest
= SET_DEST (PATTERN (insn
));
10266 || !CC_REGNO_P (REGNO (dest
))
10267 || GET_CODE (src
) != COMPARE
)
10270 /* s390_swap_cmp will try to find the conditional
10271 jump when passing NULL_RTX as condition. */
10273 op0
= &XEXP (src
, 0);
10274 op1
= &XEXP (src
, 1);
10279 if (!REG_P (*op0
) || !REG_P (*op1
))
10282 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10285 /* Swap the COMPARE arguments and its mask if there is a
10286 conflicting access in the previous insn. */
10287 prev_insn
= prev_active_insn (insn
);
10288 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10289 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10290 s390_swap_cmp (cond
, op0
, op1
, insn
);
10292 /* Check if there is a conflict with the next insn. If there
10293 was no conflict with the previous insn, then swap the
10294 COMPARE arguments and its mask. If we already swapped
10295 the operands, or if swapping them would cause a conflict
10296 with the previous insn, issue a NOP after the COMPARE in
10297 order to separate the two instuctions. */
10298 next_insn
= next_active_insn (insn
);
10299 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10300 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10302 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10303 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10305 if (REGNO (*op1
) == 0)
10306 emit_insn_after (gen_nop1 (), insn
);
10308 emit_insn_after (gen_nop (), insn
);
10309 insn_added_p
= true;
10312 s390_swap_cmp (cond
, op0
, op1
, insn
);
10314 return insn_added_p
;
10317 /* Perform machine-dependent processing. */
10322 bool pool_overflow
= false;
10324 /* Make sure all splits have been performed; splits after
10325 machine_dependent_reorg might confuse insn length counts. */
10326 split_all_insns_noflow ();
10328 /* Install the main literal pool and the associated base
10329 register load insns.
10331 In addition, there are two problematic situations we need
10334 - the literal pool might be > 4096 bytes in size, so that
10335 some of its elements cannot be directly accessed
10337 - a branch target might be > 64K away from the branch, so that
10338 it is not possible to use a PC-relative instruction.
10340 To fix those, we split the single literal pool into multiple
10341 pool chunks, reloading the pool base register at various
10342 points throughout the function to ensure it always points to
10343 the pool chunk the following code expects, and / or replace
10344 PC-relative branches by absolute branches.
10346 However, the two problems are interdependent: splitting the
10347 literal pool can move a branch further away from its target,
10348 causing the 64K limit to overflow, and on the other hand,
10349 replacing a PC-relative branch by an absolute branch means
10350 we need to put the branch target address into the literal
10351 pool, possibly causing it to overflow.
10353 So, we loop trying to fix up both problems until we manage
10354 to satisfy both conditions at the same time. Note that the
10355 loop is guaranteed to terminate as every pass of the loop
10356 strictly decreases the total number of PC-relative branches
10357 in the function. (This is not completely true as there
10358 might be branch-over-pool insns introduced by chunkify_start.
10359 Those never need to be split however.) */
10363 struct constant_pool
*pool
= NULL
;
10365 /* Collect the literal pool. */
10366 if (!pool_overflow
)
10368 pool
= s390_mainpool_start ();
10370 pool_overflow
= true;
10373 /* If literal pool overflowed, start to chunkify it. */
10375 pool
= s390_chunkify_start ();
10377 /* Split out-of-range branches. If this has created new
10378 literal pool entries, cancel current chunk list and
10379 recompute it. zSeries machines have large branch
10380 instructions, so we never need to split a branch. */
10381 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10384 s390_chunkify_cancel (pool
);
10386 s390_mainpool_cancel (pool
);
10391 /* If we made it up to here, both conditions are satisfied.
10392 Finish up literal pool related changes. */
10394 s390_chunkify_finish (pool
);
10396 s390_mainpool_finish (pool
);
10398 /* We're done splitting branches. */
10399 cfun
->machine
->split_branches_pending_p
= false;
10403 /* Generate out-of-pool execute target insns. */
10404 if (TARGET_CPU_ZARCH
)
10406 rtx insn
, label
, target
;
10408 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10410 label
= s390_execute_label (insn
);
10414 gcc_assert (label
!= const0_rtx
);
10416 target
= emit_label (XEXP (label
, 0));
10417 INSN_ADDRESSES_NEW (target
, -1);
10419 target
= emit_insn (s390_execute_target (insn
));
10420 INSN_ADDRESSES_NEW (target
, -1);
10424 /* Try to optimize prologue and epilogue further. */
10425 s390_optimize_prologue ();
10427 /* Walk over the insns and do some >=z10 specific changes. */
10428 if (s390_tune
== PROCESSOR_2097_Z10
10429 || s390_tune
== PROCESSOR_2817_Z196
)
10432 bool insn_added_p
= false;
10434 /* The insn lengths and addresses have to be up to date for the
10435 following manipulations. */
10436 shorten_branches (get_insns ());
10438 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10440 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10444 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10446 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10447 || GET_CODE (PATTERN (insn
)) == SET
)
10448 && s390_tune
== PROCESSOR_2097_Z10
)
10449 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10452 /* Adjust branches if we added new instructions. */
10454 shorten_branches (get_insns ());
10458 /* Return true if INSN is a fp load insn writing register REGNO. */
10460 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10463 enum attr_type flag
= s390_safe_attr_type (insn
);
10465 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10468 set
= single_set (insn
);
10470 if (set
== NULL_RTX
)
10473 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10476 if (REGNO (SET_DEST (set
)) != regno
)
10482 /* This value describes the distance to be avoided between an
10483 aritmetic fp instruction and an fp load writing the same register.
10484 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10485 fine but the exact value has to be avoided. Otherwise the FP
10486 pipeline will throw an exception causing a major penalty. */
10487 #define Z10_EARLYLOAD_DISTANCE 7
10489 /* Rearrange the ready list in order to avoid the situation described
10490 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10491 moved to the very end of the ready list. */
10493 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10495 unsigned int regno
;
10496 int nready
= *nready_p
;
10501 enum attr_type flag
;
10504 /* Skip DISTANCE - 1 active insns. */
10505 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10506 distance
> 0 && insn
!= NULL_RTX
;
10507 distance
--, insn
= prev_active_insn (insn
))
10508 if (CALL_P (insn
) || JUMP_P (insn
))
10511 if (insn
== NULL_RTX
)
10514 set
= single_set (insn
);
10516 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10517 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10520 flag
= s390_safe_attr_type (insn
);
10522 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10525 regno
= REGNO (SET_DEST (set
));
10528 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10535 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10539 /* This function is called via hook TARGET_SCHED_REORDER before
10540 issuing one insn from list READY which contains *NREADYP entries.
10541 For target z10 it reorders load instructions to avoid early load
10542 conflicts in the floating point pipeline */
10544 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10545 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10547 if (s390_tune
== PROCESSOR_2097_Z10
)
10548 if (reload_completed
&& *nreadyp
> 1)
10549 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10551 return s390_issue_rate ();
10554 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10555 the scheduler has issued INSN. It stores the last issued insn into
10556 last_scheduled_insn in order to make it available for
10557 s390_sched_reorder. */
10559 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10560 int verbose ATTRIBUTE_UNUSED
,
10561 rtx insn
, int more
)
10563 last_scheduled_insn
= insn
;
10565 if (GET_CODE (PATTERN (insn
)) != USE
10566 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10573 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10574 int verbose ATTRIBUTE_UNUSED
,
10575 int max_ready ATTRIBUTE_UNUSED
)
10577 last_scheduled_insn
= NULL_RTX
;
10580 /* This function checks the whole of insn X for memory references. The
10581 function always returns zero because the framework it is called
10582 from would stop recursively analyzing the insn upon a return value
10583 other than zero. The real result of this function is updating
10584 counter variable MEM_COUNT. */
10586 check_dpu (rtx
*x
, unsigned *mem_count
)
10588 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10593 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10594 a new number struct loop *loop should be unrolled if tuned for cpus with
10595 a built-in stride prefetcher.
10596 The loop is analyzed for memory accesses by calling check_dpu for
10597 each rtx of the loop. Depending on the loop_depth and the amount of
10598 memory accesses a new number <=nunroll is returned to improve the
10599 behaviour of the hardware prefetch unit. */
10601 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10606 unsigned mem_count
= 0;
10608 if (s390_tune
!= PROCESSOR_2097_Z10
&& s390_tune
!= PROCESSOR_2817_Z196
)
10611 /* Count the number of memory references within the loop body. */
10612 bbs
= get_loop_body (loop
);
10613 for (i
= 0; i
< loop
->num_nodes
; i
++)
10615 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10616 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10617 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10621 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10622 if (mem_count
== 0)
10625 switch (loop_depth(loop
))
10628 return MIN (nunroll
, 28 / mem_count
);
10630 return MIN (nunroll
, 22 / mem_count
);
10632 return MIN (nunroll
, 16 / mem_count
);
10636 /* Initialize GCC target structure. */
10638 #undef TARGET_ASM_ALIGNED_HI_OP
10639 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10640 #undef TARGET_ASM_ALIGNED_DI_OP
10641 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10642 #undef TARGET_ASM_INTEGER
10643 #define TARGET_ASM_INTEGER s390_assemble_integer
10645 #undef TARGET_ASM_OPEN_PAREN
10646 #define TARGET_ASM_OPEN_PAREN ""
10648 #undef TARGET_ASM_CLOSE_PAREN
10649 #define TARGET_ASM_CLOSE_PAREN ""
10651 #undef TARGET_OPTION_OVERRIDE
10652 #define TARGET_OPTION_OVERRIDE s390_option_override
10654 #undef TARGET_ENCODE_SECTION_INFO
10655 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10657 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10658 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10661 #undef TARGET_HAVE_TLS
10662 #define TARGET_HAVE_TLS true
10664 #undef TARGET_CANNOT_FORCE_CONST_MEM
10665 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10667 #undef TARGET_DELEGITIMIZE_ADDRESS
10668 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10670 #undef TARGET_LEGITIMIZE_ADDRESS
10671 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10673 #undef TARGET_RETURN_IN_MEMORY
10674 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10676 #undef TARGET_INIT_BUILTINS
10677 #define TARGET_INIT_BUILTINS s390_init_builtins
10678 #undef TARGET_EXPAND_BUILTIN
10679 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10681 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10682 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10684 #undef TARGET_ASM_OUTPUT_MI_THUNK
10685 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10686 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10687 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10689 #undef TARGET_SCHED_ADJUST_PRIORITY
10690 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10691 #undef TARGET_SCHED_ISSUE_RATE
10692 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10693 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10694 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10696 #undef TARGET_SCHED_VARIABLE_ISSUE
10697 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10698 #undef TARGET_SCHED_REORDER
10699 #define TARGET_SCHED_REORDER s390_sched_reorder
10700 #undef TARGET_SCHED_INIT
10701 #define TARGET_SCHED_INIT s390_sched_init
10703 #undef TARGET_CANNOT_COPY_INSN_P
10704 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10705 #undef TARGET_RTX_COSTS
10706 #define TARGET_RTX_COSTS s390_rtx_costs
10707 #undef TARGET_ADDRESS_COST
10708 #define TARGET_ADDRESS_COST s390_address_cost
10709 #undef TARGET_REGISTER_MOVE_COST
10710 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10711 #undef TARGET_MEMORY_MOVE_COST
10712 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10714 #undef TARGET_MACHINE_DEPENDENT_REORG
10715 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10717 #undef TARGET_VALID_POINTER_MODE
10718 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10720 #undef TARGET_BUILD_BUILTIN_VA_LIST
10721 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10722 #undef TARGET_EXPAND_BUILTIN_VA_START
10723 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10724 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10725 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10727 #undef TARGET_PROMOTE_FUNCTION_MODE
10728 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10729 #undef TARGET_PASS_BY_REFERENCE
10730 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10732 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10733 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10734 #undef TARGET_FUNCTION_ARG
10735 #define TARGET_FUNCTION_ARG s390_function_arg
10736 #undef TARGET_FUNCTION_ARG_ADVANCE
10737 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10738 #undef TARGET_FUNCTION_VALUE
10739 #define TARGET_FUNCTION_VALUE s390_function_value
10740 #undef TARGET_LIBCALL_VALUE
10741 #define TARGET_LIBCALL_VALUE s390_libcall_value
10743 #undef TARGET_FIXED_CONDITION_CODE_REGS
10744 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10746 #undef TARGET_CC_MODES_COMPATIBLE
10747 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10749 #undef TARGET_INVALID_WITHIN_DOLOOP
10750 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10753 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10754 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10757 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10758 #undef TARGET_MANGLE_TYPE
10759 #define TARGET_MANGLE_TYPE s390_mangle_type
10762 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10763 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10765 #undef TARGET_PREFERRED_RELOAD_CLASS
10766 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10768 #undef TARGET_SECONDARY_RELOAD
10769 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10771 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10772 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10774 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10775 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10777 #undef TARGET_LEGITIMATE_ADDRESS_P
10778 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10780 #undef TARGET_LEGITIMATE_CONSTANT_P
10781 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10783 #undef TARGET_CAN_ELIMINATE
10784 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10786 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10787 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10789 #undef TARGET_LOOP_UNROLL_ADJUST
10790 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10792 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10793 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10794 #undef TARGET_TRAMPOLINE_INIT
10795 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10797 #undef TARGET_UNWIND_WORD_MODE
10798 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10800 struct gcc_target targetm
= TARGET_INITIALIZER
;
10802 #include "gt-s390.h"