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s390.c (s390_decompose_address): Allow symbol+offset into the GOT in case we need...
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 02110-1301, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "tree-gimple.h"
54
55
56 /* Define the specific costs for a given cpu. */
57
58 struct processor_costs
59 {
60 /* multiplication */
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
74 const int mxbr;
75 /* square root */
76 const int sqxbr; /* cost of square root in TFmode. */
77 const int sqdbr; /* cost of square root in DFmode. */
78 const int sqebr; /* cost of square root in SFmode. */
79 /* multiply and add */
80 const int madbr; /* cost of multiply and add in DFmode. */
81 const int maebr; /* cost of multiply and add in SFmode. */
82 /* division */
83 const int dxbr;
84 const int dxr;
85 const int ddbr;
86 const int ddr;
87 const int debr;
88 const int der;
89 const int dlgr;
90 const int dlr;
91 const int dr;
92 const int dsgfr;
93 const int dsgr;
94 };
95
96 const struct processor_costs *s390_cost;
97
98 static const
99 struct processor_costs z900_cost =
100 {
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (135), /* DXR */
122 COSTS_N_INSNS (30), /* DDBR */
123 COSTS_N_INSNS (30), /* DDR */
124 COSTS_N_INSNS (27), /* DEBR */
125 COSTS_N_INSNS (26), /* DER */
126 COSTS_N_INSNS (220), /* DLGR */
127 COSTS_N_INSNS (34), /* DLR */
128 COSTS_N_INSNS (34), /* DR */
129 COSTS_N_INSNS (32), /* DSGFR */
130 COSTS_N_INSNS (32), /* DSGR */
131 };
132
133 static const
134 struct processor_costs z990_cost =
135 {
136 COSTS_N_INSNS (4), /* M */
137 COSTS_N_INSNS (2), /* MGHI */
138 COSTS_N_INSNS (2), /* MH */
139 COSTS_N_INSNS (2), /* MHI */
140 COSTS_N_INSNS (4), /* ML */
141 COSTS_N_INSNS (4), /* MR */
142 COSTS_N_INSNS (5), /* MS */
143 COSTS_N_INSNS (6), /* MSG */
144 COSTS_N_INSNS (4), /* MSGF */
145 COSTS_N_INSNS (4), /* MSGFR */
146 COSTS_N_INSNS (4), /* MSGR */
147 COSTS_N_INSNS (4), /* MSR */
148 COSTS_N_INSNS (1), /* multiplication in DFmode */
149 COSTS_N_INSNS (28), /* MXBR */
150 COSTS_N_INSNS (130), /* SQXBR */
151 COSTS_N_INSNS (66), /* SQDBR */
152 COSTS_N_INSNS (38), /* SQEBR */
153 COSTS_N_INSNS (1), /* MADBR */
154 COSTS_N_INSNS (1), /* MAEBR */
155 COSTS_N_INSNS (60), /* DXBR */
156 COSTS_N_INSNS (72), /* DXR */
157 COSTS_N_INSNS (40), /* DDBR */
158 COSTS_N_INSNS (44), /* DDR */
159 COSTS_N_INSNS (26), /* DDBR */
160 COSTS_N_INSNS (28), /* DER */
161 COSTS_N_INSNS (176), /* DLGR */
162 COSTS_N_INSNS (31), /* DLR */
163 COSTS_N_INSNS (31), /* DR */
164 COSTS_N_INSNS (31), /* DSGFR */
165 COSTS_N_INSNS (31), /* DSGR */
166 };
167
168 static const
169 struct processor_costs z9_109_cost =
170 {
171 COSTS_N_INSNS (4), /* M */
172 COSTS_N_INSNS (2), /* MGHI */
173 COSTS_N_INSNS (2), /* MH */
174 COSTS_N_INSNS (2), /* MHI */
175 COSTS_N_INSNS (4), /* ML */
176 COSTS_N_INSNS (4), /* MR */
177 COSTS_N_INSNS (5), /* MS */
178 COSTS_N_INSNS (6), /* MSG */
179 COSTS_N_INSNS (4), /* MSGF */
180 COSTS_N_INSNS (4), /* MSGFR */
181 COSTS_N_INSNS (4), /* MSGR */
182 COSTS_N_INSNS (4), /* MSR */
183 COSTS_N_INSNS (1), /* multiplication in DFmode */
184 COSTS_N_INSNS (28), /* MXBR */
185 COSTS_N_INSNS (130), /* SQXBR */
186 COSTS_N_INSNS (66), /* SQDBR */
187 COSTS_N_INSNS (38), /* SQEBR */
188 COSTS_N_INSNS (1), /* MADBR */
189 COSTS_N_INSNS (1), /* MAEBR */
190 COSTS_N_INSNS (60), /* DXBR */
191 COSTS_N_INSNS (72), /* DXR */
192 COSTS_N_INSNS (40), /* DDBR */
193 COSTS_N_INSNS (37), /* DDR */
194 COSTS_N_INSNS (26), /* DDBR */
195 COSTS_N_INSNS (28), /* DER */
196 COSTS_N_INSNS (30), /* DLGR */
197 COSTS_N_INSNS (23), /* DLR */
198 COSTS_N_INSNS (23), /* DR */
199 COSTS_N_INSNS (24), /* DSGFR */
200 COSTS_N_INSNS (24), /* DSGR */
201 };
202
203 extern int reload_completed;
204
205 /* Save information from a "cmpxx" operation until the branch or scc is
206 emitted. */
207 rtx s390_compare_op0, s390_compare_op1;
208
209 /* Save the result of a compare_and_swap until the branch or scc is
210 emitted. */
211 rtx s390_compare_emitted = NULL_RTX;
212
213 /* Structure used to hold the components of a S/390 memory
214 address. A legitimate address on S/390 is of the general
215 form
216 base + index + displacement
217 where any of the components is optional.
218
219 base and index are registers of the class ADDR_REGS,
220 displacement is an unsigned 12-bit immediate constant. */
221
222 struct s390_address
223 {
224 rtx base;
225 rtx indx;
226 rtx disp;
227 bool pointer;
228 bool literal_pool;
229 };
230
231 /* Which cpu are we tuning for. */
232 enum processor_type s390_tune = PROCESSOR_max;
233 enum processor_flags s390_tune_flags;
234 /* Which instruction set architecture to use. */
235 enum processor_type s390_arch;
236 enum processor_flags s390_arch_flags;
237
238 HOST_WIDE_INT s390_warn_framesize = 0;
239 HOST_WIDE_INT s390_stack_size = 0;
240 HOST_WIDE_INT s390_stack_guard = 0;
241
242 /* The following structure is embedded in the machine
243 specific part of struct function. */
244
245 struct s390_frame_layout GTY (())
246 {
247 /* Offset within stack frame. */
248 HOST_WIDE_INT gprs_offset;
249 HOST_WIDE_INT f0_offset;
250 HOST_WIDE_INT f4_offset;
251 HOST_WIDE_INT f8_offset;
252 HOST_WIDE_INT backchain_offset;
253
254 /* Number of first and last gpr where slots in the register
255 save area are reserved for. */
256 int first_save_gpr_slot;
257 int last_save_gpr_slot;
258
259 /* Number of first and last gpr to be saved, restored. */
260 int first_save_gpr;
261 int first_restore_gpr;
262 int last_save_gpr;
263 int last_restore_gpr;
264
265 /* Bits standing for floating point registers. Set, if the
266 respective register has to be saved. Starting with reg 16 (f0)
267 at the rightmost bit.
268 Bit 15 - 8 7 6 5 4 3 2 1 0
269 fpr 15 - 8 7 5 3 1 6 4 2 0
270 reg 31 - 24 23 22 21 20 19 18 17 16 */
271 unsigned int fpr_bitmap;
272
273 /* Number of floating point registers f8-f15 which must be saved. */
274 int high_fprs;
275
276 /* Set if return address needs to be saved.
277 This flag is set by s390_return_addr_rtx if it could not use
278 the initial value of r14 and therefore depends on r14 saved
279 to the stack. */
280 bool save_return_addr_p;
281
282 /* Size of stack frame. */
283 HOST_WIDE_INT frame_size;
284 };
285
286 /* Define the structure for the machine field in struct function. */
287
288 struct machine_function GTY(())
289 {
290 struct s390_frame_layout frame_layout;
291
292 /* Literal pool base register. */
293 rtx base_reg;
294
295 /* True if we may need to perform branch splitting. */
296 bool split_branches_pending_p;
297
298 /* True during final stage of literal pool processing. */
299 bool decomposed_literal_pool_addresses_ok_p;
300
301 /* Some local-dynamic TLS symbol name. */
302 const char *some_ld_name;
303
304 bool has_landing_pad_p;
305 };
306
307 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
308
309 #define cfun_frame_layout (cfun->machine->frame_layout)
310 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
311 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
312 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
313 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
314 (1 << (BITNUM)))
315 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
316 (1 << (BITNUM))))
317
318 /* Number of GPRs and FPRs used for argument passing. */
319 #define GP_ARG_NUM_REG 5
320 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
321
322 /* A couple of shortcuts. */
323 #define CONST_OK_FOR_J(x) \
324 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
325 #define CONST_OK_FOR_K(x) \
326 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
327 #define CONST_OK_FOR_Os(x) \
328 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
329 #define CONST_OK_FOR_Op(x) \
330 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
331 #define CONST_OK_FOR_On(x) \
332 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
333
334 #define REGNO_PAIR_OK(REGNO, MODE) \
335 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
336
337 /* Return true if the back end supports mode MODE. */
338 static bool
339 s390_scalar_mode_supported_p (enum machine_mode mode)
340 {
341 if (DECIMAL_FLOAT_MODE_P (mode))
342 return true;
343 else
344 return default_scalar_mode_supported_p (mode);
345 }
346
347 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
348
349 void
350 s390_set_has_landing_pad_p (bool value)
351 {
352 cfun->machine->has_landing_pad_p = value;
353 }
354
355 /* If two condition code modes are compatible, return a condition code
356 mode which is compatible with both. Otherwise, return
357 VOIDmode. */
358
359 static enum machine_mode
360 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
361 {
362 if (m1 == m2)
363 return m1;
364
365 switch (m1)
366 {
367 case CCZmode:
368 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
369 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
370 return m2;
371 return VOIDmode;
372
373 case CCSmode:
374 case CCUmode:
375 case CCTmode:
376 case CCSRmode:
377 case CCURmode:
378 case CCZ1mode:
379 if (m2 == CCZmode)
380 return m1;
381
382 return VOIDmode;
383
384 default:
385 return VOIDmode;
386 }
387 return VOIDmode;
388 }
389
390 /* Return true if SET either doesn't set the CC register, or else
391 the source and destination have matching CC modes and that
392 CC mode is at least as constrained as REQ_MODE. */
393
394 static bool
395 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
396 {
397 enum machine_mode set_mode;
398
399 gcc_assert (GET_CODE (set) == SET);
400
401 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
402 return 1;
403
404 set_mode = GET_MODE (SET_DEST (set));
405 switch (set_mode)
406 {
407 case CCSmode:
408 case CCSRmode:
409 case CCUmode:
410 case CCURmode:
411 case CCLmode:
412 case CCL1mode:
413 case CCL2mode:
414 case CCL3mode:
415 case CCT1mode:
416 case CCT2mode:
417 case CCT3mode:
418 if (req_mode != set_mode)
419 return 0;
420 break;
421
422 case CCZmode:
423 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
424 && req_mode != CCSRmode && req_mode != CCURmode)
425 return 0;
426 break;
427
428 case CCAPmode:
429 case CCANmode:
430 if (req_mode != CCAmode)
431 return 0;
432 break;
433
434 default:
435 gcc_unreachable ();
436 }
437
438 return (GET_MODE (SET_SRC (set)) == set_mode);
439 }
440
441 /* Return true if every SET in INSN that sets the CC register
442 has source and destination with matching CC modes and that
443 CC mode is at least as constrained as REQ_MODE.
444 If REQ_MODE is VOIDmode, always return false. */
445
446 bool
447 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
448 {
449 int i;
450
451 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
452 if (req_mode == VOIDmode)
453 return false;
454
455 if (GET_CODE (PATTERN (insn)) == SET)
456 return s390_match_ccmode_set (PATTERN (insn), req_mode);
457
458 if (GET_CODE (PATTERN (insn)) == PARALLEL)
459 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
460 {
461 rtx set = XVECEXP (PATTERN (insn), 0, i);
462 if (GET_CODE (set) == SET)
463 if (!s390_match_ccmode_set (set, req_mode))
464 return false;
465 }
466
467 return true;
468 }
469
470 /* If a test-under-mask instruction can be used to implement
471 (compare (and ... OP1) OP2), return the CC mode required
472 to do that. Otherwise, return VOIDmode.
473 MIXED is true if the instruction can distinguish between
474 CC1 and CC2 for mixed selected bits (TMxx), it is false
475 if the instruction cannot (TM). */
476
477 enum machine_mode
478 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
479 {
480 int bit0, bit1;
481
482 /* ??? Fixme: should work on CONST_DOUBLE as well. */
483 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
484 return VOIDmode;
485
486 /* Selected bits all zero: CC0.
487 e.g.: int a; if ((a & (16 + 128)) == 0) */
488 if (INTVAL (op2) == 0)
489 return CCTmode;
490
491 /* Selected bits all one: CC3.
492 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
493 if (INTVAL (op2) == INTVAL (op1))
494 return CCT3mode;
495
496 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
497 int a;
498 if ((a & (16 + 128)) == 16) -> CCT1
499 if ((a & (16 + 128)) == 128) -> CCT2 */
500 if (mixed)
501 {
502 bit1 = exact_log2 (INTVAL (op2));
503 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
504 if (bit0 != -1 && bit1 != -1)
505 return bit0 > bit1 ? CCT1mode : CCT2mode;
506 }
507
508 return VOIDmode;
509 }
510
511 /* Given a comparison code OP (EQ, NE, etc.) and the operands
512 OP0 and OP1 of a COMPARE, return the mode to be used for the
513 comparison. */
514
515 enum machine_mode
516 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
517 {
518 switch (code)
519 {
520 case EQ:
521 case NE:
522 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
523 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
524 return CCAPmode;
525 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
526 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
527 return CCAPmode;
528 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
529 || GET_CODE (op1) == NEG)
530 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
531 return CCLmode;
532
533 if (GET_CODE (op0) == AND)
534 {
535 /* Check whether we can potentially do it via TM. */
536 enum machine_mode ccmode;
537 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
538 if (ccmode != VOIDmode)
539 {
540 /* Relax CCTmode to CCZmode to allow fall-back to AND
541 if that turns out to be beneficial. */
542 return ccmode == CCTmode ? CCZmode : ccmode;
543 }
544 }
545
546 if (register_operand (op0, HImode)
547 && GET_CODE (op1) == CONST_INT
548 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
549 return CCT3mode;
550 if (register_operand (op0, QImode)
551 && GET_CODE (op1) == CONST_INT
552 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
553 return CCT3mode;
554
555 return CCZmode;
556
557 case LE:
558 case LT:
559 case GE:
560 case GT:
561 /* The only overflow condition of NEG and ABS happens when
562 -INT_MAX is used as parameter, which stays negative. So
563 we have an overflow from a positive value to a negative.
564 Using CCAP mode the resulting cc can be used for comparisons. */
565 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
566 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
567 return CCAPmode;
568
569 /* If constants are involved in an add instruction it is possible to use
570 the resulting cc for comparisons with zero. Knowing the sign of the
571 constant the overflow behavior gets predictable. e.g.:
572 int a, b; if ((b = a + c) > 0)
573 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
574 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
575 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
576 {
577 if (INTVAL (XEXP((op0), 1)) < 0)
578 return CCANmode;
579 else
580 return CCAPmode;
581 }
582 /* Fall through. */
583 case UNORDERED:
584 case ORDERED:
585 case UNEQ:
586 case UNLE:
587 case UNLT:
588 case UNGE:
589 case UNGT:
590 case LTGT:
591 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
592 && GET_CODE (op1) != CONST_INT)
593 return CCSRmode;
594 return CCSmode;
595
596 case LTU:
597 case GEU:
598 if (GET_CODE (op0) == PLUS
599 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
600 return CCL1mode;
601
602 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
603 && GET_CODE (op1) != CONST_INT)
604 return CCURmode;
605 return CCUmode;
606
607 case LEU:
608 case GTU:
609 if (GET_CODE (op0) == MINUS
610 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
611 return CCL2mode;
612
613 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
614 && GET_CODE (op1) != CONST_INT)
615 return CCURmode;
616 return CCUmode;
617
618 default:
619 gcc_unreachable ();
620 }
621 }
622
623 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
624 that we can implement more efficiently. */
625
626 void
627 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
628 {
629 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
630 if ((*code == EQ || *code == NE)
631 && *op1 == const0_rtx
632 && GET_CODE (*op0) == ZERO_EXTRACT
633 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
634 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
635 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
636 {
637 rtx inner = XEXP (*op0, 0);
638 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
639 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
640 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
641
642 if (len > 0 && len < modesize
643 && pos >= 0 && pos + len <= modesize
644 && modesize <= HOST_BITS_PER_WIDE_INT)
645 {
646 unsigned HOST_WIDE_INT block;
647 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
648 block <<= modesize - pos - len;
649
650 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
651 gen_int_mode (block, GET_MODE (inner)));
652 }
653 }
654
655 /* Narrow AND of memory against immediate to enable TM. */
656 if ((*code == EQ || *code == NE)
657 && *op1 == const0_rtx
658 && GET_CODE (*op0) == AND
659 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
660 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
661 {
662 rtx inner = XEXP (*op0, 0);
663 rtx mask = XEXP (*op0, 1);
664
665 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
666 if (GET_CODE (inner) == SUBREG
667 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
668 && (GET_MODE_SIZE (GET_MODE (inner))
669 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
670 && ((INTVAL (mask)
671 & GET_MODE_MASK (GET_MODE (inner))
672 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
673 == 0))
674 inner = SUBREG_REG (inner);
675
676 /* Do not change volatile MEMs. */
677 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
678 {
679 int part = s390_single_part (XEXP (*op0, 1),
680 GET_MODE (inner), QImode, 0);
681 if (part >= 0)
682 {
683 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
684 inner = adjust_address_nv (inner, QImode, part);
685 *op0 = gen_rtx_AND (QImode, inner, mask);
686 }
687 }
688 }
689
690 /* Narrow comparisons against 0xffff to HImode if possible. */
691 if ((*code == EQ || *code == NE)
692 && GET_CODE (*op1) == CONST_INT
693 && INTVAL (*op1) == 0xffff
694 && SCALAR_INT_MODE_P (GET_MODE (*op0))
695 && (nonzero_bits (*op0, GET_MODE (*op0))
696 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
697 {
698 *op0 = gen_lowpart (HImode, *op0);
699 *op1 = constm1_rtx;
700 }
701
702
703 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
704 if (GET_CODE (*op0) == UNSPEC
705 && XINT (*op0, 1) == UNSPEC_CMPINT
706 && XVECLEN (*op0, 0) == 1
707 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
708 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
709 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
710 && *op1 == const0_rtx)
711 {
712 enum rtx_code new_code = UNKNOWN;
713 switch (*code)
714 {
715 case EQ: new_code = EQ; break;
716 case NE: new_code = NE; break;
717 case LT: new_code = GTU; break;
718 case GT: new_code = LTU; break;
719 case LE: new_code = GEU; break;
720 case GE: new_code = LEU; break;
721 default: break;
722 }
723
724 if (new_code != UNKNOWN)
725 {
726 *op0 = XVECEXP (*op0, 0, 0);
727 *code = new_code;
728 }
729 }
730
731 /* Simplify cascaded EQ, NE with const0_rtx. */
732 if ((*code == NE || *code == EQ)
733 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
734 && GET_MODE (*op0) == SImode
735 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
736 && REG_P (XEXP (*op0, 0))
737 && XEXP (*op0, 1) == const0_rtx
738 && *op1 == const0_rtx)
739 {
740 if ((*code == EQ && GET_CODE (*op0) == NE)
741 || (*code == NE && GET_CODE (*op0) == EQ))
742 *code = EQ;
743 else
744 *code = NE;
745 *op0 = XEXP (*op0, 0);
746 }
747
748 /* Prefer register over memory as first operand. */
749 if (MEM_P (*op0) && REG_P (*op1))
750 {
751 rtx tem = *op0; *op0 = *op1; *op1 = tem;
752 *code = swap_condition (*code);
753 }
754 }
755
756 /* Emit a compare instruction suitable to implement the comparison
757 OP0 CODE OP1. Return the correct condition RTL to be placed in
758 the IF_THEN_ELSE of the conditional branch testing the result. */
759
760 rtx
761 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
762 {
763 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
764 rtx ret = NULL_RTX;
765
766 /* Do not output a redundant compare instruction if a compare_and_swap
767 pattern already computed the result and the machine modes are compatible. */
768 if (s390_compare_emitted
769 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
770 == GET_MODE (s390_compare_emitted)))
771 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
772 else
773 {
774 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
775
776 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
777 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
778 }
779 s390_compare_emitted = NULL_RTX;
780 return ret;
781 }
782
783 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
784 unconditional jump, else a conditional jump under condition COND. */
785
786 void
787 s390_emit_jump (rtx target, rtx cond)
788 {
789 rtx insn;
790
791 target = gen_rtx_LABEL_REF (VOIDmode, target);
792 if (cond)
793 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
794
795 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
796 emit_jump_insn (insn);
797 }
798
799 /* Return branch condition mask to implement a branch
800 specified by CODE. Return -1 for invalid comparisons. */
801
802 int
803 s390_branch_condition_mask (rtx code)
804 {
805 const int CC0 = 1 << 3;
806 const int CC1 = 1 << 2;
807 const int CC2 = 1 << 1;
808 const int CC3 = 1 << 0;
809
810 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
811 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
812 gcc_assert (XEXP (code, 1) == const0_rtx);
813
814 switch (GET_MODE (XEXP (code, 0)))
815 {
816 case CCZmode:
817 case CCZ1mode:
818 switch (GET_CODE (code))
819 {
820 case EQ: return CC0;
821 case NE: return CC1 | CC2 | CC3;
822 default: return -1;
823 }
824 break;
825
826 case CCT1mode:
827 switch (GET_CODE (code))
828 {
829 case EQ: return CC1;
830 case NE: return CC0 | CC2 | CC3;
831 default: return -1;
832 }
833 break;
834
835 case CCT2mode:
836 switch (GET_CODE (code))
837 {
838 case EQ: return CC2;
839 case NE: return CC0 | CC1 | CC3;
840 default: return -1;
841 }
842 break;
843
844 case CCT3mode:
845 switch (GET_CODE (code))
846 {
847 case EQ: return CC3;
848 case NE: return CC0 | CC1 | CC2;
849 default: return -1;
850 }
851 break;
852
853 case CCLmode:
854 switch (GET_CODE (code))
855 {
856 case EQ: return CC0 | CC2;
857 case NE: return CC1 | CC3;
858 default: return -1;
859 }
860 break;
861
862 case CCL1mode:
863 switch (GET_CODE (code))
864 {
865 case LTU: return CC2 | CC3; /* carry */
866 case GEU: return CC0 | CC1; /* no carry */
867 default: return -1;
868 }
869 break;
870
871 case CCL2mode:
872 switch (GET_CODE (code))
873 {
874 case GTU: return CC0 | CC1; /* borrow */
875 case LEU: return CC2 | CC3; /* no borrow */
876 default: return -1;
877 }
878 break;
879
880 case CCL3mode:
881 switch (GET_CODE (code))
882 {
883 case EQ: return CC0 | CC2;
884 case NE: return CC1 | CC3;
885 case LTU: return CC1;
886 case GTU: return CC3;
887 case LEU: return CC1 | CC2;
888 case GEU: return CC2 | CC3;
889 default: return -1;
890 }
891
892 case CCUmode:
893 switch (GET_CODE (code))
894 {
895 case EQ: return CC0;
896 case NE: return CC1 | CC2 | CC3;
897 case LTU: return CC1;
898 case GTU: return CC2;
899 case LEU: return CC0 | CC1;
900 case GEU: return CC0 | CC2;
901 default: return -1;
902 }
903 break;
904
905 case CCURmode:
906 switch (GET_CODE (code))
907 {
908 case EQ: return CC0;
909 case NE: return CC2 | CC1 | CC3;
910 case LTU: return CC2;
911 case GTU: return CC1;
912 case LEU: return CC0 | CC2;
913 case GEU: return CC0 | CC1;
914 default: return -1;
915 }
916 break;
917
918 case CCAPmode:
919 switch (GET_CODE (code))
920 {
921 case EQ: return CC0;
922 case NE: return CC1 | CC2 | CC3;
923 case LT: return CC1 | CC3;
924 case GT: return CC2;
925 case LE: return CC0 | CC1 | CC3;
926 case GE: return CC0 | CC2;
927 default: return -1;
928 }
929 break;
930
931 case CCANmode:
932 switch (GET_CODE (code))
933 {
934 case EQ: return CC0;
935 case NE: return CC1 | CC2 | CC3;
936 case LT: return CC1;
937 case GT: return CC2 | CC3;
938 case LE: return CC0 | CC1;
939 case GE: return CC0 | CC2 | CC3;
940 default: return -1;
941 }
942 break;
943
944 case CCSmode:
945 switch (GET_CODE (code))
946 {
947 case EQ: return CC0;
948 case NE: return CC1 | CC2 | CC3;
949 case LT: return CC1;
950 case GT: return CC2;
951 case LE: return CC0 | CC1;
952 case GE: return CC0 | CC2;
953 case UNORDERED: return CC3;
954 case ORDERED: return CC0 | CC1 | CC2;
955 case UNEQ: return CC0 | CC3;
956 case UNLT: return CC1 | CC3;
957 case UNGT: return CC2 | CC3;
958 case UNLE: return CC0 | CC1 | CC3;
959 case UNGE: return CC0 | CC2 | CC3;
960 case LTGT: return CC1 | CC2;
961 default: return -1;
962 }
963 break;
964
965 case CCSRmode:
966 switch (GET_CODE (code))
967 {
968 case EQ: return CC0;
969 case NE: return CC2 | CC1 | CC3;
970 case LT: return CC2;
971 case GT: return CC1;
972 case LE: return CC0 | CC2;
973 case GE: return CC0 | CC1;
974 case UNORDERED: return CC3;
975 case ORDERED: return CC0 | CC2 | CC1;
976 case UNEQ: return CC0 | CC3;
977 case UNLT: return CC2 | CC3;
978 case UNGT: return CC1 | CC3;
979 case UNLE: return CC0 | CC2 | CC3;
980 case UNGE: return CC0 | CC1 | CC3;
981 case LTGT: return CC2 | CC1;
982 default: return -1;
983 }
984 break;
985
986 default:
987 return -1;
988 }
989 }
990
991 /* If INV is false, return assembler mnemonic string to implement
992 a branch specified by CODE. If INV is true, return mnemonic
993 for the corresponding inverted branch. */
994
995 static const char *
996 s390_branch_condition_mnemonic (rtx code, int inv)
997 {
998 static const char *const mnemonic[16] =
999 {
1000 NULL, "o", "h", "nle",
1001 "l", "nhe", "lh", "ne",
1002 "e", "nlh", "he", "nl",
1003 "le", "nh", "no", NULL
1004 };
1005
1006 int mask = s390_branch_condition_mask (code);
1007 gcc_assert (mask >= 0);
1008
1009 if (inv)
1010 mask ^= 15;
1011
1012 gcc_assert (mask >= 1 && mask <= 14);
1013
1014 return mnemonic[mask];
1015 }
1016
1017 /* Return the part of op which has a value different from def.
1018 The size of the part is determined by mode.
1019 Use this function only if you already know that op really
1020 contains such a part. */
1021
1022 unsigned HOST_WIDE_INT
1023 s390_extract_part (rtx op, enum machine_mode mode, int def)
1024 {
1025 unsigned HOST_WIDE_INT value = 0;
1026 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1027 int part_bits = GET_MODE_BITSIZE (mode);
1028 unsigned HOST_WIDE_INT part_mask
1029 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1030 int i;
1031
1032 for (i = 0; i < max_parts; i++)
1033 {
1034 if (i == 0)
1035 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1036 else
1037 value >>= part_bits;
1038
1039 if ((value & part_mask) != (def & part_mask))
1040 return value & part_mask;
1041 }
1042
1043 gcc_unreachable ();
1044 }
1045
1046 /* If OP is an integer constant of mode MODE with exactly one
1047 part of mode PART_MODE unequal to DEF, return the number of that
1048 part. Otherwise, return -1. */
1049
1050 int
1051 s390_single_part (rtx op,
1052 enum machine_mode mode,
1053 enum machine_mode part_mode,
1054 int def)
1055 {
1056 unsigned HOST_WIDE_INT value = 0;
1057 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1058 unsigned HOST_WIDE_INT part_mask
1059 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1060 int i, part = -1;
1061
1062 if (GET_CODE (op) != CONST_INT)
1063 return -1;
1064
1065 for (i = 0; i < n_parts; i++)
1066 {
1067 if (i == 0)
1068 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1069 else
1070 value >>= GET_MODE_BITSIZE (part_mode);
1071
1072 if ((value & part_mask) != (def & part_mask))
1073 {
1074 if (part != -1)
1075 return -1;
1076 else
1077 part = i;
1078 }
1079 }
1080 return part == -1 ? -1 : n_parts - 1 - part;
1081 }
1082
1083 /* Check whether we can (and want to) split a double-word
1084 move in mode MODE from SRC to DST into two single-word
1085 moves, moving the subword FIRST_SUBWORD first. */
1086
1087 bool
1088 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1089 {
1090 /* Floating point registers cannot be split. */
1091 if (FP_REG_P (src) || FP_REG_P (dst))
1092 return false;
1093
1094 /* We don't need to split if operands are directly accessible. */
1095 if (s_operand (src, mode) || s_operand (dst, mode))
1096 return false;
1097
1098 /* Non-offsettable memory references cannot be split. */
1099 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1100 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1101 return false;
1102
1103 /* Moving the first subword must not clobber a register
1104 needed to move the second subword. */
1105 if (register_operand (dst, mode))
1106 {
1107 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1108 if (reg_overlap_mentioned_p (subreg, src))
1109 return false;
1110 }
1111
1112 return true;
1113 }
1114
1115 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1116 and [MEM2, MEM2 + SIZE] do overlap and false
1117 otherwise. */
1118
1119 bool
1120 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1121 {
1122 rtx addr1, addr2, addr_delta;
1123 HOST_WIDE_INT delta;
1124
1125 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1126 return true;
1127
1128 if (size == 0)
1129 return false;
1130
1131 addr1 = XEXP (mem1, 0);
1132 addr2 = XEXP (mem2, 0);
1133
1134 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1135
1136 /* This overlapping check is used by peepholes merging memory block operations.
1137 Overlapping operations would otherwise be recognized by the S/390 hardware
1138 and would fall back to a slower implementation. Allowing overlapping
1139 operations would lead to slow code but not to wrong code. Therefore we are
1140 somewhat optimistic if we cannot prove that the memory blocks are
1141 overlapping.
1142 That's why we return false here although this may accept operations on
1143 overlapping memory areas. */
1144 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1145 return false;
1146
1147 delta = INTVAL (addr_delta);
1148
1149 if (delta == 0
1150 || (delta > 0 && delta < size)
1151 || (delta < 0 && -delta < size))
1152 return true;
1153
1154 return false;
1155 }
1156
1157 /* Check whether the address of memory reference MEM2 equals exactly
1158 the address of memory reference MEM1 plus DELTA. Return true if
1159 we can prove this to be the case, false otherwise. */
1160
1161 bool
1162 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1163 {
1164 rtx addr1, addr2, addr_delta;
1165
1166 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1167 return false;
1168
1169 addr1 = XEXP (mem1, 0);
1170 addr2 = XEXP (mem2, 0);
1171
1172 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1173 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1174 return false;
1175
1176 return true;
1177 }
1178
1179 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1180
1181 void
1182 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1183 rtx *operands)
1184 {
1185 enum machine_mode wmode = mode;
1186 rtx dst = operands[0];
1187 rtx src1 = operands[1];
1188 rtx src2 = operands[2];
1189 rtx op, clob, tem;
1190
1191 /* If we cannot handle the operation directly, use a temp register. */
1192 if (!s390_logical_operator_ok_p (operands))
1193 dst = gen_reg_rtx (mode);
1194
1195 /* QImode and HImode patterns make sense only if we have a destination
1196 in memory. Otherwise perform the operation in SImode. */
1197 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1198 wmode = SImode;
1199
1200 /* Widen operands if required. */
1201 if (mode != wmode)
1202 {
1203 if (GET_CODE (dst) == SUBREG
1204 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1205 dst = tem;
1206 else if (REG_P (dst))
1207 dst = gen_rtx_SUBREG (wmode, dst, 0);
1208 else
1209 dst = gen_reg_rtx (wmode);
1210
1211 if (GET_CODE (src1) == SUBREG
1212 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1213 src1 = tem;
1214 else if (GET_MODE (src1) != VOIDmode)
1215 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1216
1217 if (GET_CODE (src2) == SUBREG
1218 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1219 src2 = tem;
1220 else if (GET_MODE (src2) != VOIDmode)
1221 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1222 }
1223
1224 /* Emit the instruction. */
1225 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1226 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1227 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1228
1229 /* Fix up the destination if needed. */
1230 if (dst != operands[0])
1231 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1232 }
1233
1234 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1235
1236 bool
1237 s390_logical_operator_ok_p (rtx *operands)
1238 {
1239 /* If the destination operand is in memory, it needs to coincide
1240 with one of the source operands. After reload, it has to be
1241 the first source operand. */
1242 if (GET_CODE (operands[0]) == MEM)
1243 return rtx_equal_p (operands[0], operands[1])
1244 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1245
1246 return true;
1247 }
1248
1249 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1250 operand IMMOP to switch from SS to SI type instructions. */
1251
1252 void
1253 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1254 {
1255 int def = code == AND ? -1 : 0;
1256 HOST_WIDE_INT mask;
1257 int part;
1258
1259 gcc_assert (GET_CODE (*memop) == MEM);
1260 gcc_assert (!MEM_VOLATILE_P (*memop));
1261
1262 mask = s390_extract_part (*immop, QImode, def);
1263 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1264 gcc_assert (part >= 0);
1265
1266 *memop = adjust_address (*memop, QImode, part);
1267 *immop = gen_int_mode (mask, QImode);
1268 }
1269
1270
1271 /* How to allocate a 'struct machine_function'. */
1272
1273 static struct machine_function *
1274 s390_init_machine_status (void)
1275 {
1276 return ggc_alloc_cleared (sizeof (struct machine_function));
1277 }
1278
1279 /* Change optimizations to be performed, depending on the
1280 optimization level.
1281
1282 LEVEL is the optimization level specified; 2 if `-O2' is
1283 specified, 1 if `-O' is specified, and 0 if neither is specified.
1284
1285 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1286
1287 void
1288 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1289 {
1290 /* ??? There are apparently still problems with -fcaller-saves. */
1291 flag_caller_saves = 0;
1292
1293 /* By default, always emit DWARF-2 unwind info. This allows debugging
1294 without maintaining a stack frame back-chain. */
1295 flag_asynchronous_unwind_tables = 1;
1296
1297 /* Use MVCLE instructions to decrease code size if requested. */
1298 if (size != 0)
1299 target_flags |= MASK_MVCLE;
1300 }
1301
1302 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1303 to the associated processor_type and processor_flags if so. */
1304
1305 static bool
1306 s390_handle_arch_option (const char *arg,
1307 enum processor_type *type,
1308 enum processor_flags *flags)
1309 {
1310 static struct pta
1311 {
1312 const char *const name; /* processor name or nickname. */
1313 const enum processor_type processor;
1314 const enum processor_flags flags;
1315 }
1316 const processor_alias_table[] =
1317 {
1318 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1319 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1320 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1321 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1322 | PF_LONG_DISPLACEMENT},
1323 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1324 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1325 };
1326 size_t i;
1327
1328 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1329 if (strcmp (arg, processor_alias_table[i].name) == 0)
1330 {
1331 *type = processor_alias_table[i].processor;
1332 *flags = processor_alias_table[i].flags;
1333 return true;
1334 }
1335 return false;
1336 }
1337
1338 /* Implement TARGET_HANDLE_OPTION. */
1339
1340 static bool
1341 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1342 {
1343 switch (code)
1344 {
1345 case OPT_march_:
1346 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1347
1348 case OPT_mstack_guard_:
1349 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1350 return false;
1351 if (exact_log2 (s390_stack_guard) == -1)
1352 error ("stack guard value must be an exact power of 2");
1353 return true;
1354
1355 case OPT_mstack_size_:
1356 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1357 return false;
1358 if (exact_log2 (s390_stack_size) == -1)
1359 error ("stack size must be an exact power of 2");
1360 return true;
1361
1362 case OPT_mtune_:
1363 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1364
1365 case OPT_mwarn_framesize_:
1366 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1367
1368 default:
1369 return true;
1370 }
1371 }
1372
1373 void
1374 override_options (void)
1375 {
1376 /* Set up function hooks. */
1377 init_machine_status = s390_init_machine_status;
1378
1379 /* Architecture mode defaults according to ABI. */
1380 if (!(target_flags_explicit & MASK_ZARCH))
1381 {
1382 if (TARGET_64BIT)
1383 target_flags |= MASK_ZARCH;
1384 else
1385 target_flags &= ~MASK_ZARCH;
1386 }
1387
1388 /* Determine processor architectural level. */
1389 if (!s390_arch_string)
1390 {
1391 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1392 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1393 }
1394
1395 /* Determine processor to tune for. */
1396 if (s390_tune == PROCESSOR_max)
1397 {
1398 s390_tune = s390_arch;
1399 s390_tune_flags = s390_arch_flags;
1400 }
1401
1402 /* Sanity checks. */
1403 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1404 error ("z/Architecture mode not supported on %s", s390_arch_string);
1405 if (TARGET_64BIT && !TARGET_ZARCH)
1406 error ("64-bit ABI not supported in ESA/390 mode");
1407
1408 /* Set processor cost function. */
1409 if (s390_tune == PROCESSOR_2094_Z9_109)
1410 s390_cost = &z9_109_cost;
1411 else if (s390_tune == PROCESSOR_2084_Z990)
1412 s390_cost = &z990_cost;
1413 else
1414 s390_cost = &z900_cost;
1415
1416 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1417 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1418 "in combination");
1419
1420 if (s390_stack_size)
1421 {
1422 if (!s390_stack_guard)
1423 error ("-mstack-size implies use of -mstack-guard");
1424 else if (s390_stack_guard >= s390_stack_size)
1425 error ("stack size must be greater than the stack guard value");
1426 else if (s390_stack_size > 1 << 16)
1427 error ("stack size must not be greater than 64k");
1428 }
1429 else if (s390_stack_guard)
1430 error ("-mstack-guard implies use of -mstack-size");
1431
1432 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1433 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1434 target_flags |= MASK_LONG_DOUBLE_128;
1435 #endif
1436 }
1437
1438 /* Map for smallest class containing reg regno. */
1439
1440 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1441 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1442 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1443 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1444 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1445 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1446 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1447 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1448 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1449 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1450 ACCESS_REGS, ACCESS_REGS
1451 };
1452
1453 /* Return attribute type of insn. */
1454
1455 static enum attr_type
1456 s390_safe_attr_type (rtx insn)
1457 {
1458 if (recog_memoized (insn) >= 0)
1459 return get_attr_type (insn);
1460 else
1461 return TYPE_NONE;
1462 }
1463
1464 /* Return true if DISP is a valid short displacement. */
1465
1466 static bool
1467 s390_short_displacement (rtx disp)
1468 {
1469 /* No displacement is OK. */
1470 if (!disp)
1471 return true;
1472
1473 /* Integer displacement in range. */
1474 if (GET_CODE (disp) == CONST_INT)
1475 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1476
1477 /* GOT offset is not OK, the GOT can be large. */
1478 if (GET_CODE (disp) == CONST
1479 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1480 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1481 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1482 return false;
1483
1484 /* All other symbolic constants are literal pool references,
1485 which are OK as the literal pool must be small. */
1486 if (GET_CODE (disp) == CONST)
1487 return true;
1488
1489 return false;
1490 }
1491
1492 /* Decompose a RTL expression ADDR for a memory address into
1493 its components, returned in OUT.
1494
1495 Returns false if ADDR is not a valid memory address, true
1496 otherwise. If OUT is NULL, don't return the components,
1497 but check for validity only.
1498
1499 Note: Only addresses in canonical form are recognized.
1500 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1501 canonical form so that they will be recognized. */
1502
1503 static int
1504 s390_decompose_address (rtx addr, struct s390_address *out)
1505 {
1506 HOST_WIDE_INT offset = 0;
1507 rtx base = NULL_RTX;
1508 rtx indx = NULL_RTX;
1509 rtx disp = NULL_RTX;
1510 rtx orig_disp;
1511 bool pointer = false;
1512 bool base_ptr = false;
1513 bool indx_ptr = false;
1514 bool literal_pool = false;
1515
1516 /* We may need to substitute the literal pool base register into the address
1517 below. However, at this point we do not know which register is going to
1518 be used as base, so we substitute the arg pointer register. This is going
1519 to be treated as holding a pointer below -- it shouldn't be used for any
1520 other purpose. */
1521 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1522
1523 /* Decompose address into base + index + displacement. */
1524
1525 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1526 base = addr;
1527
1528 else if (GET_CODE (addr) == PLUS)
1529 {
1530 rtx op0 = XEXP (addr, 0);
1531 rtx op1 = XEXP (addr, 1);
1532 enum rtx_code code0 = GET_CODE (op0);
1533 enum rtx_code code1 = GET_CODE (op1);
1534
1535 if (code0 == REG || code0 == UNSPEC)
1536 {
1537 if (code1 == REG || code1 == UNSPEC)
1538 {
1539 indx = op0; /* index + base */
1540 base = op1;
1541 }
1542
1543 else
1544 {
1545 base = op0; /* base + displacement */
1546 disp = op1;
1547 }
1548 }
1549
1550 else if (code0 == PLUS)
1551 {
1552 indx = XEXP (op0, 0); /* index + base + disp */
1553 base = XEXP (op0, 1);
1554 disp = op1;
1555 }
1556
1557 else
1558 {
1559 return false;
1560 }
1561 }
1562
1563 else
1564 disp = addr; /* displacement */
1565
1566 /* Extract integer part of displacement. */
1567 orig_disp = disp;
1568 if (disp)
1569 {
1570 if (GET_CODE (disp) == CONST_INT)
1571 {
1572 offset = INTVAL (disp);
1573 disp = NULL_RTX;
1574 }
1575 else if (GET_CODE (disp) == CONST
1576 && GET_CODE (XEXP (disp, 0)) == PLUS
1577 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1578 {
1579 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1580 disp = XEXP (XEXP (disp, 0), 0);
1581 }
1582 }
1583
1584 /* Strip off CONST here to avoid special case tests later. */
1585 if (disp && GET_CODE (disp) == CONST)
1586 disp = XEXP (disp, 0);
1587
1588 /* We can convert literal pool addresses to
1589 displacements by basing them off the base register. */
1590 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1591 {
1592 /* Either base or index must be free to hold the base register. */
1593 if (!base)
1594 base = fake_pool_base, literal_pool = true;
1595 else if (!indx)
1596 indx = fake_pool_base, literal_pool = true;
1597 else
1598 return false;
1599
1600 /* Mark up the displacement. */
1601 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1602 UNSPEC_LTREL_OFFSET);
1603 }
1604
1605 /* Validate base register. */
1606 if (base)
1607 {
1608 if (GET_CODE (base) == UNSPEC)
1609 switch (XINT (base, 1))
1610 {
1611 case UNSPEC_LTREF:
1612 if (!disp)
1613 disp = gen_rtx_UNSPEC (Pmode,
1614 gen_rtvec (1, XVECEXP (base, 0, 0)),
1615 UNSPEC_LTREL_OFFSET);
1616 else
1617 return false;
1618
1619 base = XVECEXP (base, 0, 1);
1620 break;
1621
1622 case UNSPEC_LTREL_BASE:
1623 if (XVECLEN (base, 0) == 1)
1624 base = fake_pool_base, literal_pool = true;
1625 else
1626 base = XVECEXP (base, 0, 1);
1627 break;
1628
1629 default:
1630 return false;
1631 }
1632
1633 if (!REG_P (base)
1634 || (GET_MODE (base) != SImode
1635 && GET_MODE (base) != Pmode))
1636 return false;
1637
1638 if (REGNO (base) == STACK_POINTER_REGNUM
1639 || REGNO (base) == FRAME_POINTER_REGNUM
1640 || ((reload_completed || reload_in_progress)
1641 && frame_pointer_needed
1642 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1643 || REGNO (base) == ARG_POINTER_REGNUM
1644 || (flag_pic
1645 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1646 pointer = base_ptr = true;
1647
1648 if ((reload_completed || reload_in_progress)
1649 && base == cfun->machine->base_reg)
1650 pointer = base_ptr = literal_pool = true;
1651 }
1652
1653 /* Validate index register. */
1654 if (indx)
1655 {
1656 if (GET_CODE (indx) == UNSPEC)
1657 switch (XINT (indx, 1))
1658 {
1659 case UNSPEC_LTREF:
1660 if (!disp)
1661 disp = gen_rtx_UNSPEC (Pmode,
1662 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1663 UNSPEC_LTREL_OFFSET);
1664 else
1665 return false;
1666
1667 indx = XVECEXP (indx, 0, 1);
1668 break;
1669
1670 case UNSPEC_LTREL_BASE:
1671 if (XVECLEN (indx, 0) == 1)
1672 indx = fake_pool_base, literal_pool = true;
1673 else
1674 indx = XVECEXP (indx, 0, 1);
1675 break;
1676
1677 default:
1678 return false;
1679 }
1680
1681 if (!REG_P (indx)
1682 || (GET_MODE (indx) != SImode
1683 && GET_MODE (indx) != Pmode))
1684 return false;
1685
1686 if (REGNO (indx) == STACK_POINTER_REGNUM
1687 || REGNO (indx) == FRAME_POINTER_REGNUM
1688 || ((reload_completed || reload_in_progress)
1689 && frame_pointer_needed
1690 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1691 || REGNO (indx) == ARG_POINTER_REGNUM
1692 || (flag_pic
1693 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1694 pointer = indx_ptr = true;
1695
1696 if ((reload_completed || reload_in_progress)
1697 && indx == cfun->machine->base_reg)
1698 pointer = indx_ptr = literal_pool = true;
1699 }
1700
1701 /* Prefer to use pointer as base, not index. */
1702 if (base && indx && !base_ptr
1703 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1704 {
1705 rtx tmp = base;
1706 base = indx;
1707 indx = tmp;
1708 }
1709
1710 /* Validate displacement. */
1711 if (!disp)
1712 {
1713 /* If virtual registers are involved, the displacement will change later
1714 anyway as the virtual registers get eliminated. This could make a
1715 valid displacement invalid, but it is more likely to make an invalid
1716 displacement valid, because we sometimes access the register save area
1717 via negative offsets to one of those registers.
1718 Thus we don't check the displacement for validity here. If after
1719 elimination the displacement turns out to be invalid after all,
1720 this is fixed up by reload in any case. */
1721 if (base != arg_pointer_rtx
1722 && indx != arg_pointer_rtx
1723 && base != return_address_pointer_rtx
1724 && indx != return_address_pointer_rtx
1725 && base != frame_pointer_rtx
1726 && indx != frame_pointer_rtx
1727 && base != virtual_stack_vars_rtx
1728 && indx != virtual_stack_vars_rtx)
1729 if (!DISP_IN_RANGE (offset))
1730 return false;
1731 }
1732 else
1733 {
1734 /* All the special cases are pointers. */
1735 pointer = true;
1736
1737 /* In the small-PIC case, the linker converts @GOT
1738 and @GOTNTPOFF offsets to possible displacements. */
1739 if (GET_CODE (disp) == UNSPEC
1740 && (XINT (disp, 1) == UNSPEC_GOT
1741 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1742 && flag_pic == 1)
1743 {
1744 ;
1745 }
1746
1747 /* Accept chunkified literal pool symbol references. */
1748 else if (cfun && cfun->machine
1749 && cfun->machine->decomposed_literal_pool_addresses_ok_p
1750 && GET_CODE (disp) == MINUS
1751 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1752 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1753 {
1754 ;
1755 }
1756
1757 /* Accept literal pool references. */
1758 else if (GET_CODE (disp) == UNSPEC
1759 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1760 {
1761 orig_disp = gen_rtx_CONST (Pmode, disp);
1762 if (offset)
1763 {
1764 /* If we have an offset, make sure it does not
1765 exceed the size of the constant pool entry. */
1766 rtx sym = XVECEXP (disp, 0, 0);
1767 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1768 return false;
1769
1770 orig_disp = plus_constant (orig_disp, offset);
1771 }
1772 }
1773
1774 else
1775 return false;
1776 }
1777
1778 if (!base && !indx)
1779 pointer = true;
1780
1781 if (out)
1782 {
1783 out->base = base;
1784 out->indx = indx;
1785 out->disp = orig_disp;
1786 out->pointer = pointer;
1787 out->literal_pool = literal_pool;
1788 }
1789
1790 return true;
1791 }
1792
1793 /* Decompose a RTL expression OP for a shift count into its components,
1794 and return the base register in BASE and the offset in OFFSET.
1795
1796 Return true if OP is a valid shift count, false if not. */
1797
1798 bool
1799 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1800 {
1801 HOST_WIDE_INT off = 0;
1802
1803 /* We can have an integer constant, an address register,
1804 or a sum of the two. */
1805 if (GET_CODE (op) == CONST_INT)
1806 {
1807 off = INTVAL (op);
1808 op = NULL_RTX;
1809 }
1810 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1811 {
1812 off = INTVAL (XEXP (op, 1));
1813 op = XEXP (op, 0);
1814 }
1815 while (op && GET_CODE (op) == SUBREG)
1816 op = SUBREG_REG (op);
1817
1818 if (op && GET_CODE (op) != REG)
1819 return false;
1820
1821 if (offset)
1822 *offset = off;
1823 if (base)
1824 *base = op;
1825
1826 return true;
1827 }
1828
1829
1830 /* Return true if CODE is a valid address without index. */
1831
1832 bool
1833 s390_legitimate_address_without_index_p (rtx op)
1834 {
1835 struct s390_address addr;
1836
1837 if (!s390_decompose_address (XEXP (op, 0), &addr))
1838 return false;
1839 if (addr.indx)
1840 return false;
1841
1842 return true;
1843 }
1844
1845 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1846
1847 int
1848 s390_extra_constraint_str (rtx op, int c, const char * str)
1849 {
1850 struct s390_address addr;
1851
1852 gcc_assert (c == str[0]);
1853
1854 /* Check for offsettable variants of memory constraints. */
1855 if (c == 'A')
1856 {
1857 /* Only accept non-volatile MEMs. */
1858 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1859 return 0;
1860
1861 if ((reload_completed || reload_in_progress)
1862 ? !offsettable_memref_p (op)
1863 : !offsettable_nonstrict_memref_p (op))
1864 return 0;
1865
1866 c = str[1];
1867 }
1868
1869 /* Check for non-literal-pool variants of memory constraints. */
1870 else if (c == 'B')
1871 {
1872 if (GET_CODE (op) != MEM)
1873 return 0;
1874 if (!s390_decompose_address (XEXP (op, 0), &addr))
1875 return 0;
1876 if (addr.literal_pool)
1877 return 0;
1878
1879 c = str[1];
1880 }
1881
1882 switch (c)
1883 {
1884 case 'Q':
1885 if (GET_CODE (op) != MEM)
1886 return 0;
1887 if (!s390_decompose_address (XEXP (op, 0), &addr))
1888 return 0;
1889 if (addr.indx)
1890 return 0;
1891
1892 if (TARGET_LONG_DISPLACEMENT)
1893 {
1894 if (!s390_short_displacement (addr.disp))
1895 return 0;
1896 }
1897 break;
1898
1899 case 'R':
1900 if (GET_CODE (op) != MEM)
1901 return 0;
1902
1903 if (TARGET_LONG_DISPLACEMENT)
1904 {
1905 if (!s390_decompose_address (XEXP (op, 0), &addr))
1906 return 0;
1907 if (!s390_short_displacement (addr.disp))
1908 return 0;
1909 }
1910 break;
1911
1912 case 'S':
1913 if (!TARGET_LONG_DISPLACEMENT)
1914 return 0;
1915 if (GET_CODE (op) != MEM)
1916 return 0;
1917 if (!s390_decompose_address (XEXP (op, 0), &addr))
1918 return 0;
1919 if (addr.indx)
1920 return 0;
1921 if (s390_short_displacement (addr.disp))
1922 return 0;
1923 break;
1924
1925 case 'T':
1926 if (!TARGET_LONG_DISPLACEMENT)
1927 return 0;
1928 if (GET_CODE (op) != MEM)
1929 return 0;
1930 /* Any invalid address here will be fixed up by reload,
1931 so accept it for the most generic constraint. */
1932 if (s390_decompose_address (XEXP (op, 0), &addr)
1933 && s390_short_displacement (addr.disp))
1934 return 0;
1935 break;
1936
1937 case 'U':
1938 if (TARGET_LONG_DISPLACEMENT)
1939 {
1940 if (!s390_decompose_address (op, &addr))
1941 return 0;
1942 if (!s390_short_displacement (addr.disp))
1943 return 0;
1944 }
1945 break;
1946
1947 case 'W':
1948 if (!TARGET_LONG_DISPLACEMENT)
1949 return 0;
1950 /* Any invalid address here will be fixed up by reload,
1951 so accept it for the most generic constraint. */
1952 if (s390_decompose_address (op, &addr)
1953 && s390_short_displacement (addr.disp))
1954 return 0;
1955 break;
1956
1957 case 'Y':
1958 /* Simply check for the basic form of a shift count. Reload will
1959 take care of making sure we have a proper base register. */
1960 if (!s390_decompose_shift_count (op, NULL, NULL))
1961 return 0;
1962 break;
1963
1964 default:
1965 return 0;
1966 }
1967
1968 return 1;
1969 }
1970
1971 /* Return true if VALUE matches the constraint STR. */
1972
1973 int
1974 s390_const_double_ok_for_constraint_p (rtx value,
1975 int c,
1976 const char * str)
1977 {
1978 gcc_assert (c == str[0]);
1979
1980 switch (str[0])
1981 {
1982 case 'G':
1983 /* The floating point zero constant. */
1984 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1985 && value == CONST0_RTX (GET_MODE (value)));
1986
1987 default:
1988 return 0;
1989 }
1990 }
1991
1992 /* Return true if VALUE matches the constraint STR. */
1993
1994 int
1995 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1996 int c,
1997 const char * str)
1998 {
1999 enum machine_mode mode, part_mode;
2000 int def;
2001 int part, part_goal;
2002
2003 gcc_assert (c == str[0]);
2004
2005 switch (str[0])
2006 {
2007 case 'I':
2008 return (unsigned int)value < 256;
2009
2010 case 'J':
2011 return (unsigned int)value < 4096;
2012
2013 case 'K':
2014 return value >= -32768 && value < 32768;
2015
2016 case 'L':
2017 return (TARGET_LONG_DISPLACEMENT ?
2018 (value >= -524288 && value <= 524287)
2019 : (value >= 0 && value <= 4095));
2020 case 'M':
2021 return value == 2147483647;
2022
2023 case 'N':
2024 if (str[1] == 'x')
2025 part_goal = -1;
2026 else
2027 part_goal = str[1] - '0';
2028
2029 switch (str[2])
2030 {
2031 case 'Q': part_mode = QImode; break;
2032 case 'H': part_mode = HImode; break;
2033 case 'S': part_mode = SImode; break;
2034 default: return 0;
2035 }
2036
2037 switch (str[3])
2038 {
2039 case 'H': mode = HImode; break;
2040 case 'S': mode = SImode; break;
2041 case 'D': mode = DImode; break;
2042 default: return 0;
2043 }
2044
2045 switch (str[4])
2046 {
2047 case '0': def = 0; break;
2048 case 'F': def = -1; break;
2049 default: return 0;
2050 }
2051
2052 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2053 return 0;
2054
2055 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2056 if (part < 0)
2057 return 0;
2058 if (part_goal != -1 && part_goal != part)
2059 return 0;
2060
2061 break;
2062
2063 case 'O':
2064 if (!TARGET_EXTIMM)
2065 return 0;
2066
2067 switch (str[1])
2068 {
2069 case 's':
2070 return trunc_int_for_mode (value, SImode) == value;
2071
2072 case 'p':
2073 return value == 0
2074 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2075
2076 case 'n':
2077 return
2078 (value == -1
2079 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1)
2080 && value != -((HOST_WIDE_INT)1 << 32);
2081
2082 default:
2083 gcc_unreachable ();
2084 }
2085 break;
2086
2087 case 'P':
2088 return legitimate_reload_constant_p (GEN_INT (value));
2089
2090 default:
2091 return 0;
2092 }
2093
2094 return 1;
2095 }
2096
2097 /* Compute a (partial) cost for rtx X. Return true if the complete
2098 cost has been computed, and false if subexpressions should be
2099 scanned. In either case, *TOTAL contains the cost result.
2100 CODE contains GET_CODE (x), OUTER_CODE contains the code
2101 of the superexpression of x. */
2102
2103 static bool
2104 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2105 {
2106 switch (code)
2107 {
2108 case CONST:
2109 case CONST_INT:
2110 case LABEL_REF:
2111 case SYMBOL_REF:
2112 case CONST_DOUBLE:
2113 case MEM:
2114 *total = 0;
2115 return true;
2116
2117 case ASHIFT:
2118 case ASHIFTRT:
2119 case LSHIFTRT:
2120 case ROTATE:
2121 case ROTATERT:
2122 case AND:
2123 case IOR:
2124 case XOR:
2125 case NEG:
2126 case NOT:
2127 *total = COSTS_N_INSNS (1);
2128 return false;
2129
2130 case PLUS:
2131 case MINUS:
2132 /* Check for multiply and add. */
2133 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2134 && GET_CODE (XEXP (x, 0)) == MULT
2135 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2136 {
2137 /* This is the multiply and add case. */
2138 if (GET_MODE (x) == DFmode)
2139 *total = s390_cost->madbr;
2140 else
2141 *total = s390_cost->maebr;
2142 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2143 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2144 + rtx_cost (XEXP (x, 1), code);
2145 return true; /* Do not do an additional recursive descent. */
2146 }
2147 *total = COSTS_N_INSNS (1);
2148 return false;
2149
2150 case MULT:
2151 switch (GET_MODE (x))
2152 {
2153 case SImode:
2154 {
2155 rtx left = XEXP (x, 0);
2156 rtx right = XEXP (x, 1);
2157 if (GET_CODE (right) == CONST_INT
2158 && CONST_OK_FOR_K (INTVAL (right)))
2159 *total = s390_cost->mhi;
2160 else if (GET_CODE (left) == SIGN_EXTEND)
2161 *total = s390_cost->mh;
2162 else
2163 *total = s390_cost->ms; /* msr, ms, msy */
2164 break;
2165 }
2166 case DImode:
2167 {
2168 rtx left = XEXP (x, 0);
2169 rtx right = XEXP (x, 1);
2170 if (TARGET_64BIT)
2171 {
2172 if (GET_CODE (right) == CONST_INT
2173 && CONST_OK_FOR_K (INTVAL (right)))
2174 *total = s390_cost->mghi;
2175 else if (GET_CODE (left) == SIGN_EXTEND)
2176 *total = s390_cost->msgf;
2177 else
2178 *total = s390_cost->msg; /* msgr, msg */
2179 }
2180 else /* TARGET_31BIT */
2181 {
2182 if (GET_CODE (left) == SIGN_EXTEND
2183 && GET_CODE (right) == SIGN_EXTEND)
2184 /* mulsidi case: mr, m */
2185 *total = s390_cost->m;
2186 else if (GET_CODE (left) == ZERO_EXTEND
2187 && GET_CODE (right) == ZERO_EXTEND
2188 && TARGET_CPU_ZARCH)
2189 /* umulsidi case: ml, mlr */
2190 *total = s390_cost->ml;
2191 else
2192 /* Complex calculation is required. */
2193 *total = COSTS_N_INSNS (40);
2194 }
2195 break;
2196 }
2197 case SFmode:
2198 case DFmode:
2199 *total = s390_cost->mult_df;
2200 break;
2201 case TFmode:
2202 *total = s390_cost->mxbr;
2203 break;
2204 default:
2205 return false;
2206 }
2207 return false;
2208
2209 case UDIV:
2210 case UMOD:
2211 if (GET_MODE (x) == TImode) /* 128 bit division */
2212 *total = s390_cost->dlgr;
2213 else if (GET_MODE (x) == DImode)
2214 {
2215 rtx right = XEXP (x, 1);
2216 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2217 *total = s390_cost->dlr;
2218 else /* 64 by 64 bit division */
2219 *total = s390_cost->dlgr;
2220 }
2221 else if (GET_MODE (x) == SImode) /* 32 bit division */
2222 *total = s390_cost->dlr;
2223 return false;
2224
2225 case DIV:
2226 case MOD:
2227 if (GET_MODE (x) == DImode)
2228 {
2229 rtx right = XEXP (x, 1);
2230 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2231 if (TARGET_64BIT)
2232 *total = s390_cost->dsgfr;
2233 else
2234 *total = s390_cost->dr;
2235 else /* 64 by 64 bit division */
2236 *total = s390_cost->dsgr;
2237 }
2238 else if (GET_MODE (x) == SImode) /* 32 bit division */
2239 *total = s390_cost->dlr;
2240 else if (GET_MODE (x) == SFmode)
2241 {
2242 if (TARGET_IEEE_FLOAT)
2243 *total = s390_cost->debr;
2244 else /* TARGET_IBM_FLOAT */
2245 *total = s390_cost->der;
2246 }
2247 else if (GET_MODE (x) == DFmode)
2248 {
2249 if (TARGET_IEEE_FLOAT)
2250 *total = s390_cost->ddbr;
2251 else /* TARGET_IBM_FLOAT */
2252 *total = s390_cost->ddr;
2253 }
2254 else if (GET_MODE (x) == TFmode)
2255 {
2256 if (TARGET_IEEE_FLOAT)
2257 *total = s390_cost->dxbr;
2258 else /* TARGET_IBM_FLOAT */
2259 *total = s390_cost->dxr;
2260 }
2261 return false;
2262
2263 case SQRT:
2264 if (GET_MODE (x) == SFmode)
2265 *total = s390_cost->sqebr;
2266 else if (GET_MODE (x) == DFmode)
2267 *total = s390_cost->sqdbr;
2268 else /* TFmode */
2269 *total = s390_cost->sqxbr;
2270 return false;
2271
2272 case SIGN_EXTEND:
2273 case ZERO_EXTEND:
2274 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2275 || outer_code == PLUS || outer_code == MINUS
2276 || outer_code == COMPARE)
2277 *total = 0;
2278 return false;
2279
2280 case COMPARE:
2281 *total = COSTS_N_INSNS (1);
2282 if (GET_CODE (XEXP (x, 0)) == AND
2283 && GET_CODE (XEXP (x, 1)) == CONST_INT
2284 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2285 {
2286 rtx op0 = XEXP (XEXP (x, 0), 0);
2287 rtx op1 = XEXP (XEXP (x, 0), 1);
2288 rtx op2 = XEXP (x, 1);
2289
2290 if (memory_operand (op0, GET_MODE (op0))
2291 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2292 return true;
2293 if (register_operand (op0, GET_MODE (op0))
2294 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2295 return true;
2296 }
2297 return false;
2298
2299 default:
2300 return false;
2301 }
2302 }
2303
2304 /* Return the cost of an address rtx ADDR. */
2305
2306 static int
2307 s390_address_cost (rtx addr)
2308 {
2309 struct s390_address ad;
2310 if (!s390_decompose_address (addr, &ad))
2311 return 1000;
2312
2313 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2314 }
2315
2316 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2317 otherwise return 0. */
2318
2319 int
2320 tls_symbolic_operand (rtx op)
2321 {
2322 if (GET_CODE (op) != SYMBOL_REF)
2323 return 0;
2324 return SYMBOL_REF_TLS_MODEL (op);
2325 }
2326 \f
2327 /* Split DImode access register reference REG (on 64-bit) into its constituent
2328 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2329 gen_highpart cannot be used as they assume all registers are word-sized,
2330 while our access registers have only half that size. */
2331
2332 void
2333 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2334 {
2335 gcc_assert (TARGET_64BIT);
2336 gcc_assert (ACCESS_REG_P (reg));
2337 gcc_assert (GET_MODE (reg) == DImode);
2338 gcc_assert (!(REGNO (reg) & 1));
2339
2340 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2341 *hi = gen_rtx_REG (SImode, REGNO (reg));
2342 }
2343
2344 /* Return true if OP contains a symbol reference */
2345
2346 bool
2347 symbolic_reference_mentioned_p (rtx op)
2348 {
2349 const char *fmt;
2350 int i;
2351
2352 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2353 return 1;
2354
2355 fmt = GET_RTX_FORMAT (GET_CODE (op));
2356 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2357 {
2358 if (fmt[i] == 'E')
2359 {
2360 int j;
2361
2362 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2363 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2364 return 1;
2365 }
2366
2367 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2368 return 1;
2369 }
2370
2371 return 0;
2372 }
2373
2374 /* Return true if OP contains a reference to a thread-local symbol. */
2375
2376 bool
2377 tls_symbolic_reference_mentioned_p (rtx op)
2378 {
2379 const char *fmt;
2380 int i;
2381
2382 if (GET_CODE (op) == SYMBOL_REF)
2383 return tls_symbolic_operand (op);
2384
2385 fmt = GET_RTX_FORMAT (GET_CODE (op));
2386 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2387 {
2388 if (fmt[i] == 'E')
2389 {
2390 int j;
2391
2392 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2393 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2394 return true;
2395 }
2396
2397 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2398 return true;
2399 }
2400
2401 return false;
2402 }
2403
2404
2405 /* Return true if OP is a legitimate general operand when
2406 generating PIC code. It is given that flag_pic is on
2407 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2408
2409 int
2410 legitimate_pic_operand_p (rtx op)
2411 {
2412 /* Accept all non-symbolic constants. */
2413 if (!SYMBOLIC_CONST (op))
2414 return 1;
2415
2416 /* Reject everything else; must be handled
2417 via emit_symbolic_move. */
2418 return 0;
2419 }
2420
2421 /* Returns true if the constant value OP is a legitimate general operand.
2422 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2423
2424 int
2425 legitimate_constant_p (rtx op)
2426 {
2427 /* Accept all non-symbolic constants. */
2428 if (!SYMBOLIC_CONST (op))
2429 return 1;
2430
2431 /* Accept immediate LARL operands. */
2432 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2433 return 1;
2434
2435 /* Thread-local symbols are never legal constants. This is
2436 so that emit_call knows that computing such addresses
2437 might require a function call. */
2438 if (TLS_SYMBOLIC_CONST (op))
2439 return 0;
2440
2441 /* In the PIC case, symbolic constants must *not* be
2442 forced into the literal pool. We accept them here,
2443 so that they will be handled by emit_symbolic_move. */
2444 if (flag_pic)
2445 return 1;
2446
2447 /* All remaining non-PIC symbolic constants are
2448 forced into the literal pool. */
2449 return 0;
2450 }
2451
2452 /* Determine if it's legal to put X into the constant pool. This
2453 is not possible if X contains the address of a symbol that is
2454 not constant (TLS) or not known at final link time (PIC). */
2455
2456 static bool
2457 s390_cannot_force_const_mem (rtx x)
2458 {
2459 switch (GET_CODE (x))
2460 {
2461 case CONST_INT:
2462 case CONST_DOUBLE:
2463 /* Accept all non-symbolic constants. */
2464 return false;
2465
2466 case LABEL_REF:
2467 /* Labels are OK iff we are non-PIC. */
2468 return flag_pic != 0;
2469
2470 case SYMBOL_REF:
2471 /* 'Naked' TLS symbol references are never OK,
2472 non-TLS symbols are OK iff we are non-PIC. */
2473 if (tls_symbolic_operand (x))
2474 return true;
2475 else
2476 return flag_pic != 0;
2477
2478 case CONST:
2479 return s390_cannot_force_const_mem (XEXP (x, 0));
2480 case PLUS:
2481 case MINUS:
2482 return s390_cannot_force_const_mem (XEXP (x, 0))
2483 || s390_cannot_force_const_mem (XEXP (x, 1));
2484
2485 case UNSPEC:
2486 switch (XINT (x, 1))
2487 {
2488 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2489 case UNSPEC_LTREL_OFFSET:
2490 case UNSPEC_GOT:
2491 case UNSPEC_GOTOFF:
2492 case UNSPEC_PLTOFF:
2493 case UNSPEC_TLSGD:
2494 case UNSPEC_TLSLDM:
2495 case UNSPEC_NTPOFF:
2496 case UNSPEC_DTPOFF:
2497 case UNSPEC_GOTNTPOFF:
2498 case UNSPEC_INDNTPOFF:
2499 return false;
2500
2501 /* If the literal pool shares the code section, be put
2502 execute template placeholders into the pool as well. */
2503 case UNSPEC_INSN:
2504 return TARGET_CPU_ZARCH;
2505
2506 default:
2507 return true;
2508 }
2509 break;
2510
2511 default:
2512 gcc_unreachable ();
2513 }
2514 }
2515
2516 /* Returns true if the constant value OP is a legitimate general
2517 operand during and after reload. The difference to
2518 legitimate_constant_p is that this function will not accept
2519 a constant that would need to be forced to the literal pool
2520 before it can be used as operand. */
2521
2522 bool
2523 legitimate_reload_constant_p (rtx op)
2524 {
2525 /* Accept la(y) operands. */
2526 if (GET_CODE (op) == CONST_INT
2527 && DISP_IN_RANGE (INTVAL (op)))
2528 return true;
2529
2530 /* Accept l(g)hi/l(g)fi operands. */
2531 if (GET_CODE (op) == CONST_INT
2532 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2533 return true;
2534
2535 /* Accept lliXX operands. */
2536 if (TARGET_ZARCH
2537 && GET_CODE (op) == CONST_INT
2538 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2539 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2540 return true;
2541
2542 if (TARGET_EXTIMM
2543 && GET_CODE (op) == CONST_INT
2544 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2545 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2546 return true;
2547
2548 /* Accept larl operands. */
2549 if (TARGET_CPU_ZARCH
2550 && larl_operand (op, VOIDmode))
2551 return true;
2552
2553 /* Accept lzXX operands. */
2554 if (GET_CODE (op) == CONST_DOUBLE
2555 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2556 return true;
2557
2558 /* Accept double-word operands that can be split. */
2559 if (GET_CODE (op) == CONST_INT
2560 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2561 {
2562 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2563 rtx hi = operand_subword (op, 0, 0, dword_mode);
2564 rtx lo = operand_subword (op, 1, 0, dword_mode);
2565 return legitimate_reload_constant_p (hi)
2566 && legitimate_reload_constant_p (lo);
2567 }
2568
2569 /* Everything else cannot be handled without reload. */
2570 return false;
2571 }
2572
2573 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2574 return the class of reg to actually use. */
2575
2576 enum reg_class
2577 s390_preferred_reload_class (rtx op, enum reg_class class)
2578 {
2579 switch (GET_CODE (op))
2580 {
2581 /* Constants we cannot reload must be forced into the
2582 literal pool. */
2583
2584 case CONST_DOUBLE:
2585 case CONST_INT:
2586 if (legitimate_reload_constant_p (op))
2587 return class;
2588 else
2589 return NO_REGS;
2590
2591 /* If a symbolic constant or a PLUS is reloaded,
2592 it is most likely being used as an address, so
2593 prefer ADDR_REGS. If 'class' is not a superset
2594 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2595 case PLUS:
2596 case LABEL_REF:
2597 case SYMBOL_REF:
2598 case CONST:
2599 if (reg_class_subset_p (ADDR_REGS, class))
2600 return ADDR_REGS;
2601 else
2602 return NO_REGS;
2603
2604 default:
2605 break;
2606 }
2607
2608 return class;
2609 }
2610
2611 /* Return the register class of a scratch register needed to
2612 load IN into a register of class CLASS in MODE.
2613
2614 We need a temporary when loading a PLUS expression which
2615 is not a legitimate operand of the LOAD ADDRESS instruction. */
2616
2617 enum reg_class
2618 s390_secondary_input_reload_class (enum reg_class class,
2619 enum machine_mode mode, rtx in)
2620 {
2621 if (s390_plus_operand (in, mode))
2622 return ADDR_REGS;
2623
2624 if (reg_classes_intersect_p (FP_REGS, class)
2625 && mode == TFmode
2626 && GET_CODE (in) == MEM
2627 && GET_CODE (XEXP (in, 0)) == PLUS
2628 && GET_CODE (XEXP (XEXP (in, 0), 1)) == CONST_INT
2629 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (in, 0), 1))
2630 + GET_MODE_SIZE (mode) - 1))
2631 return ADDR_REGS;
2632
2633 if (reg_classes_intersect_p (CC_REGS, class))
2634 return GENERAL_REGS;
2635
2636 return NO_REGS;
2637 }
2638
2639 /* Return the register class of a scratch register needed to
2640 store a register of class CLASS in MODE into OUT:
2641
2642 We need a temporary when storing a double-word to a
2643 non-offsettable memory address. */
2644
2645 enum reg_class
2646 s390_secondary_output_reload_class (enum reg_class class,
2647 enum machine_mode mode, rtx out)
2648 {
2649 if ((TARGET_64BIT ? (mode == TImode || mode == TFmode)
2650 : (mode == DImode || mode == DFmode))
2651 && reg_classes_intersect_p (GENERAL_REGS, class)
2652 && GET_CODE (out) == MEM
2653 && GET_CODE (XEXP (out, 0)) == PLUS
2654 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2655 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2656 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2657 + GET_MODE_SIZE (mode) - 1))
2658 return ADDR_REGS;
2659
2660 if (reg_classes_intersect_p (FP_REGS, class)
2661 && mode == TFmode
2662 && GET_CODE (out) == MEM
2663 && GET_CODE (XEXP (out, 0)) == PLUS
2664 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2665 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2666 + GET_MODE_SIZE (mode) - 1))
2667 return ADDR_REGS;
2668
2669 if (reg_classes_intersect_p (CC_REGS, class))
2670 return GENERAL_REGS;
2671
2672 return NO_REGS;
2673 }
2674
2675 /* Generate code to load SRC, which is PLUS that is not a
2676 legitimate operand for the LA instruction, into TARGET.
2677 SCRATCH may be used as scratch register. */
2678
2679 void
2680 s390_expand_plus_operand (rtx target, rtx src,
2681 rtx scratch)
2682 {
2683 rtx sum1, sum2;
2684 struct s390_address ad;
2685
2686 /* src must be a PLUS; get its two operands. */
2687 gcc_assert (GET_CODE (src) == PLUS);
2688 gcc_assert (GET_MODE (src) == Pmode);
2689
2690 /* Check if any of the two operands is already scheduled
2691 for replacement by reload. This can happen e.g. when
2692 float registers occur in an address. */
2693 sum1 = find_replacement (&XEXP (src, 0));
2694 sum2 = find_replacement (&XEXP (src, 1));
2695 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2696
2697 /* If the address is already strictly valid, there's nothing to do. */
2698 if (!s390_decompose_address (src, &ad)
2699 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2700 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
2701 {
2702 /* Otherwise, one of the operands cannot be an address register;
2703 we reload its value into the scratch register. */
2704 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2705 {
2706 emit_move_insn (scratch, sum1);
2707 sum1 = scratch;
2708 }
2709 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2710 {
2711 emit_move_insn (scratch, sum2);
2712 sum2 = scratch;
2713 }
2714
2715 /* According to the way these invalid addresses are generated
2716 in reload.c, it should never happen (at least on s390) that
2717 *neither* of the PLUS components, after find_replacements
2718 was applied, is an address register. */
2719 if (sum1 == scratch && sum2 == scratch)
2720 {
2721 debug_rtx (src);
2722 gcc_unreachable ();
2723 }
2724
2725 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2726 }
2727
2728 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2729 is only ever performed on addresses, so we can mark the
2730 sum as legitimate for LA in any case. */
2731 s390_load_address (target, src);
2732 }
2733
2734
2735 /* Return true if ADDR is a valid memory address.
2736 STRICT specifies whether strict register checking applies. */
2737
2738 bool
2739 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2740 rtx addr, int strict)
2741 {
2742 struct s390_address ad;
2743 if (!s390_decompose_address (addr, &ad))
2744 return false;
2745
2746 if (strict)
2747 {
2748 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2749 return false;
2750
2751 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
2752 return false;
2753 }
2754 else
2755 {
2756 if (ad.base
2757 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
2758 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
2759 return false;
2760
2761 if (ad.indx
2762 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
2763 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
2764 return false;
2765 }
2766 return true;
2767 }
2768
2769 /* Return true if OP is a valid operand for the LA instruction.
2770 In 31-bit, we need to prove that the result is used as an
2771 address, as LA performs only a 31-bit addition. */
2772
2773 bool
2774 legitimate_la_operand_p (rtx op)
2775 {
2776 struct s390_address addr;
2777 if (!s390_decompose_address (op, &addr))
2778 return false;
2779
2780 return (TARGET_64BIT || addr.pointer);
2781 }
2782
2783 /* Return true if it is valid *and* preferable to use LA to
2784 compute the sum of OP1 and OP2. */
2785
2786 bool
2787 preferred_la_operand_p (rtx op1, rtx op2)
2788 {
2789 struct s390_address addr;
2790
2791 if (op2 != const0_rtx)
2792 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2793
2794 if (!s390_decompose_address (op1, &addr))
2795 return false;
2796 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
2797 return false;
2798 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
2799 return false;
2800
2801 if (!TARGET_64BIT && !addr.pointer)
2802 return false;
2803
2804 if (addr.pointer)
2805 return true;
2806
2807 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2808 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2809 return true;
2810
2811 return false;
2812 }
2813
2814 /* Emit a forced load-address operation to load SRC into DST.
2815 This will use the LOAD ADDRESS instruction even in situations
2816 where legitimate_la_operand_p (SRC) returns false. */
2817
2818 void
2819 s390_load_address (rtx dst, rtx src)
2820 {
2821 if (TARGET_64BIT)
2822 emit_move_insn (dst, src);
2823 else
2824 emit_insn (gen_force_la_31 (dst, src));
2825 }
2826
2827 /* Return a legitimate reference for ORIG (an address) using the
2828 register REG. If REG is 0, a new pseudo is generated.
2829
2830 There are two types of references that must be handled:
2831
2832 1. Global data references must load the address from the GOT, via
2833 the PIC reg. An insn is emitted to do this load, and the reg is
2834 returned.
2835
2836 2. Static data references, constant pool addresses, and code labels
2837 compute the address as an offset from the GOT, whose base is in
2838 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2839 differentiate them from global data objects. The returned
2840 address is the PIC reg + an unspec constant.
2841
2842 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2843 reg also appears in the address. */
2844
2845 rtx
2846 legitimize_pic_address (rtx orig, rtx reg)
2847 {
2848 rtx addr = orig;
2849 rtx new = orig;
2850 rtx base;
2851
2852 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
2853
2854 if (GET_CODE (addr) == LABEL_REF
2855 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2856 {
2857 /* This is a local symbol. */
2858 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2859 {
2860 /* Access local symbols PC-relative via LARL.
2861 This is the same as in the non-PIC case, so it is
2862 handled automatically ... */
2863 }
2864 else
2865 {
2866 /* Access local symbols relative to the GOT. */
2867
2868 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2869
2870 if (reload_in_progress || reload_completed)
2871 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2872
2873 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2874 addr = gen_rtx_CONST (Pmode, addr);
2875 addr = force_const_mem (Pmode, addr);
2876 emit_move_insn (temp, addr);
2877
2878 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2879 if (reg != 0)
2880 {
2881 s390_load_address (reg, new);
2882 new = reg;
2883 }
2884 }
2885 }
2886 else if (GET_CODE (addr) == SYMBOL_REF)
2887 {
2888 if (reg == 0)
2889 reg = gen_reg_rtx (Pmode);
2890
2891 if (flag_pic == 1)
2892 {
2893 /* Assume GOT offset < 4k. This is handled the same way
2894 in both 31- and 64-bit code (@GOT). */
2895
2896 if (reload_in_progress || reload_completed)
2897 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2898
2899 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2900 new = gen_rtx_CONST (Pmode, new);
2901 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2902 new = gen_const_mem (Pmode, new);
2903 emit_move_insn (reg, new);
2904 new = reg;
2905 }
2906 else if (TARGET_CPU_ZARCH)
2907 {
2908 /* If the GOT offset might be >= 4k, we determine the position
2909 of the GOT entry via a PC-relative LARL (@GOTENT). */
2910
2911 rtx temp = gen_reg_rtx (Pmode);
2912
2913 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2914 new = gen_rtx_CONST (Pmode, new);
2915 emit_move_insn (temp, new);
2916
2917 new = gen_const_mem (Pmode, temp);
2918 emit_move_insn (reg, new);
2919 new = reg;
2920 }
2921 else
2922 {
2923 /* If the GOT offset might be >= 4k, we have to load it
2924 from the literal pool (@GOT). */
2925
2926 rtx temp = gen_reg_rtx (Pmode);
2927
2928 if (reload_in_progress || reload_completed)
2929 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2930
2931 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2932 addr = gen_rtx_CONST (Pmode, addr);
2933 addr = force_const_mem (Pmode, addr);
2934 emit_move_insn (temp, addr);
2935
2936 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2937 new = gen_const_mem (Pmode, new);
2938 emit_move_insn (reg, new);
2939 new = reg;
2940 }
2941 }
2942 else
2943 {
2944 if (GET_CODE (addr) == CONST)
2945 {
2946 addr = XEXP (addr, 0);
2947 if (GET_CODE (addr) == UNSPEC)
2948 {
2949 gcc_assert (XVECLEN (addr, 0) == 1);
2950 switch (XINT (addr, 1))
2951 {
2952 /* If someone moved a GOT-relative UNSPEC
2953 out of the literal pool, force them back in. */
2954 case UNSPEC_GOTOFF:
2955 case UNSPEC_PLTOFF:
2956 new = force_const_mem (Pmode, orig);
2957 break;
2958
2959 /* @GOT is OK as is if small. */
2960 case UNSPEC_GOT:
2961 if (flag_pic == 2)
2962 new = force_const_mem (Pmode, orig);
2963 break;
2964
2965 /* @GOTENT is OK as is. */
2966 case UNSPEC_GOTENT:
2967 break;
2968
2969 /* @PLT is OK as is on 64-bit, must be converted to
2970 GOT-relative @PLTOFF on 31-bit. */
2971 case UNSPEC_PLT:
2972 if (!TARGET_CPU_ZARCH)
2973 {
2974 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2975
2976 if (reload_in_progress || reload_completed)
2977 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2978
2979 addr = XVECEXP (addr, 0, 0);
2980 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2981 UNSPEC_PLTOFF);
2982 addr = gen_rtx_CONST (Pmode, addr);
2983 addr = force_const_mem (Pmode, addr);
2984 emit_move_insn (temp, addr);
2985
2986 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2987 if (reg != 0)
2988 {
2989 s390_load_address (reg, new);
2990 new = reg;
2991 }
2992 }
2993 break;
2994
2995 /* Everything else cannot happen. */
2996 default:
2997 gcc_unreachable ();
2998 }
2999 }
3000 else
3001 gcc_assert (GET_CODE (addr) == PLUS);
3002 }
3003 if (GET_CODE (addr) == PLUS)
3004 {
3005 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3006
3007 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3008 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3009
3010 /* Check first to see if this is a constant offset
3011 from a local symbol reference. */
3012 if ((GET_CODE (op0) == LABEL_REF
3013 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3014 && GET_CODE (op1) == CONST_INT)
3015 {
3016 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
3017 {
3018 if (INTVAL (op1) & 1)
3019 {
3020 /* LARL can't handle odd offsets, so emit a
3021 pair of LARL and LA. */
3022 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3023
3024 if (!DISP_IN_RANGE (INTVAL (op1)))
3025 {
3026 int even = INTVAL (op1) - 1;
3027 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3028 op0 = gen_rtx_CONST (Pmode, op0);
3029 op1 = const1_rtx;
3030 }
3031
3032 emit_move_insn (temp, op0);
3033 new = gen_rtx_PLUS (Pmode, temp, op1);
3034
3035 if (reg != 0)
3036 {
3037 s390_load_address (reg, new);
3038 new = reg;
3039 }
3040 }
3041 else
3042 {
3043 /* If the offset is even, we can just use LARL.
3044 This will happen automatically. */
3045 }
3046 }
3047 else
3048 {
3049 /* Access local symbols relative to the GOT. */
3050
3051 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3052
3053 if (reload_in_progress || reload_completed)
3054 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3055
3056 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3057 UNSPEC_GOTOFF);
3058 addr = gen_rtx_PLUS (Pmode, addr, op1);
3059 addr = gen_rtx_CONST (Pmode, addr);
3060 addr = force_const_mem (Pmode, addr);
3061 emit_move_insn (temp, addr);
3062
3063 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3064 if (reg != 0)
3065 {
3066 s390_load_address (reg, new);
3067 new = reg;
3068 }
3069 }
3070 }
3071
3072 /* Now, check whether it is a GOT relative symbol plus offset
3073 that was pulled out of the literal pool. Force it back in. */
3074
3075 else if (GET_CODE (op0) == UNSPEC
3076 && GET_CODE (op1) == CONST_INT
3077 && XINT (op0, 1) == UNSPEC_GOTOFF)
3078 {
3079 gcc_assert (XVECLEN (op0, 0) == 1);
3080
3081 new = force_const_mem (Pmode, orig);
3082 }
3083
3084 /* Otherwise, compute the sum. */
3085 else
3086 {
3087 base = legitimize_pic_address (XEXP (addr, 0), reg);
3088 new = legitimize_pic_address (XEXP (addr, 1),
3089 base == reg ? NULL_RTX : reg);
3090 if (GET_CODE (new) == CONST_INT)
3091 new = plus_constant (base, INTVAL (new));
3092 else
3093 {
3094 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3095 {
3096 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3097 new = XEXP (new, 1);
3098 }
3099 new = gen_rtx_PLUS (Pmode, base, new);
3100 }
3101
3102 if (GET_CODE (new) == CONST)
3103 new = XEXP (new, 0);
3104 new = force_operand (new, 0);
3105 }
3106 }
3107 }
3108 return new;
3109 }
3110
3111 /* Load the thread pointer into a register. */
3112
3113 rtx
3114 s390_get_thread_pointer (void)
3115 {
3116 rtx tp = gen_reg_rtx (Pmode);
3117
3118 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3119 mark_reg_pointer (tp, BITS_PER_WORD);
3120
3121 return tp;
3122 }
3123
3124 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3125 in s390_tls_symbol which always refers to __tls_get_offset.
3126 The returned offset is written to RESULT_REG and an USE rtx is
3127 generated for TLS_CALL. */
3128
3129 static GTY(()) rtx s390_tls_symbol;
3130
3131 static void
3132 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3133 {
3134 rtx insn;
3135
3136 gcc_assert (flag_pic);
3137
3138 if (!s390_tls_symbol)
3139 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3140
3141 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3142 gen_rtx_REG (Pmode, RETURN_REGNUM));
3143
3144 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3145 CONST_OR_PURE_CALL_P (insn) = 1;
3146 }
3147
3148 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3149 this (thread-local) address. REG may be used as temporary. */
3150
3151 static rtx
3152 legitimize_tls_address (rtx addr, rtx reg)
3153 {
3154 rtx new, tls_call, temp, base, r2, insn;
3155
3156 if (GET_CODE (addr) == SYMBOL_REF)
3157 switch (tls_symbolic_operand (addr))
3158 {
3159 case TLS_MODEL_GLOBAL_DYNAMIC:
3160 start_sequence ();
3161 r2 = gen_rtx_REG (Pmode, 2);
3162 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3163 new = gen_rtx_CONST (Pmode, tls_call);
3164 new = force_const_mem (Pmode, new);
3165 emit_move_insn (r2, new);
3166 s390_emit_tls_call_insn (r2, tls_call);
3167 insn = get_insns ();
3168 end_sequence ();
3169
3170 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3171 temp = gen_reg_rtx (Pmode);
3172 emit_libcall_block (insn, temp, r2, new);
3173
3174 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3175 if (reg != 0)
3176 {
3177 s390_load_address (reg, new);
3178 new = reg;
3179 }
3180 break;
3181
3182 case TLS_MODEL_LOCAL_DYNAMIC:
3183 start_sequence ();
3184 r2 = gen_rtx_REG (Pmode, 2);
3185 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3186 new = gen_rtx_CONST (Pmode, tls_call);
3187 new = force_const_mem (Pmode, new);
3188 emit_move_insn (r2, new);
3189 s390_emit_tls_call_insn (r2, tls_call);
3190 insn = get_insns ();
3191 end_sequence ();
3192
3193 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3194 temp = gen_reg_rtx (Pmode);
3195 emit_libcall_block (insn, temp, r2, new);
3196
3197 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3198 base = gen_reg_rtx (Pmode);
3199 s390_load_address (base, new);
3200
3201 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3202 new = gen_rtx_CONST (Pmode, new);
3203 new = force_const_mem (Pmode, new);
3204 temp = gen_reg_rtx (Pmode);
3205 emit_move_insn (temp, new);
3206
3207 new = gen_rtx_PLUS (Pmode, base, temp);
3208 if (reg != 0)
3209 {
3210 s390_load_address (reg, new);
3211 new = reg;
3212 }
3213 break;
3214
3215 case TLS_MODEL_INITIAL_EXEC:
3216 if (flag_pic == 1)
3217 {
3218 /* Assume GOT offset < 4k. This is handled the same way
3219 in both 31- and 64-bit code. */
3220
3221 if (reload_in_progress || reload_completed)
3222 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3223
3224 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3225 new = gen_rtx_CONST (Pmode, new);
3226 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3227 new = gen_const_mem (Pmode, new);
3228 temp = gen_reg_rtx (Pmode);
3229 emit_move_insn (temp, new);
3230 }
3231 else if (TARGET_CPU_ZARCH)
3232 {
3233 /* If the GOT offset might be >= 4k, we determine the position
3234 of the GOT entry via a PC-relative LARL. */
3235
3236 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3237 new = gen_rtx_CONST (Pmode, new);
3238 temp = gen_reg_rtx (Pmode);
3239 emit_move_insn (temp, new);
3240
3241 new = gen_const_mem (Pmode, temp);
3242 temp = gen_reg_rtx (Pmode);
3243 emit_move_insn (temp, new);
3244 }
3245 else if (flag_pic)
3246 {
3247 /* If the GOT offset might be >= 4k, we have to load it
3248 from the literal pool. */
3249
3250 if (reload_in_progress || reload_completed)
3251 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3252
3253 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3254 new = gen_rtx_CONST (Pmode, new);
3255 new = force_const_mem (Pmode, new);
3256 temp = gen_reg_rtx (Pmode);
3257 emit_move_insn (temp, new);
3258
3259 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3260 new = gen_const_mem (Pmode, new);
3261
3262 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3263 temp = gen_reg_rtx (Pmode);
3264 emit_insn (gen_rtx_SET (Pmode, temp, new));
3265 }
3266 else
3267 {
3268 /* In position-dependent code, load the absolute address of
3269 the GOT entry from the literal pool. */
3270
3271 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3272 new = gen_rtx_CONST (Pmode, new);
3273 new = force_const_mem (Pmode, new);
3274 temp = gen_reg_rtx (Pmode);
3275 emit_move_insn (temp, new);
3276
3277 new = temp;
3278 new = gen_const_mem (Pmode, new);
3279 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3280 temp = gen_reg_rtx (Pmode);
3281 emit_insn (gen_rtx_SET (Pmode, temp, new));
3282 }
3283
3284 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3285 if (reg != 0)
3286 {
3287 s390_load_address (reg, new);
3288 new = reg;
3289 }
3290 break;
3291
3292 case TLS_MODEL_LOCAL_EXEC:
3293 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3294 new = gen_rtx_CONST (Pmode, new);
3295 new = force_const_mem (Pmode, new);
3296 temp = gen_reg_rtx (Pmode);
3297 emit_move_insn (temp, new);
3298
3299 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3300 if (reg != 0)
3301 {
3302 s390_load_address (reg, new);
3303 new = reg;
3304 }
3305 break;
3306
3307 default:
3308 gcc_unreachable ();
3309 }
3310
3311 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3312 {
3313 switch (XINT (XEXP (addr, 0), 1))
3314 {
3315 case UNSPEC_INDNTPOFF:
3316 gcc_assert (TARGET_CPU_ZARCH);
3317 new = addr;
3318 break;
3319
3320 default:
3321 gcc_unreachable ();
3322 }
3323 }
3324
3325 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3326 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3327 {
3328 new = XEXP (XEXP (addr, 0), 0);
3329 if (GET_CODE (new) != SYMBOL_REF)
3330 new = gen_rtx_CONST (Pmode, new);
3331
3332 new = legitimize_tls_address (new, reg);
3333 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3334 new = force_operand (new, 0);
3335 }
3336
3337 else
3338 gcc_unreachable (); /* for now ... */
3339
3340 return new;
3341 }
3342
3343 /* Emit insns to move operands[1] into operands[0]. */
3344
3345 void
3346 emit_symbolic_move (rtx *operands)
3347 {
3348 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3349
3350 if (GET_CODE (operands[0]) == MEM)
3351 operands[1] = force_reg (Pmode, operands[1]);
3352 else if (TLS_SYMBOLIC_CONST (operands[1]))
3353 operands[1] = legitimize_tls_address (operands[1], temp);
3354 else if (flag_pic)
3355 operands[1] = legitimize_pic_address (operands[1], temp);
3356 }
3357
3358 /* Try machine-dependent ways of modifying an illegitimate address X
3359 to be legitimate. If we find one, return the new, valid address.
3360
3361 OLDX is the address as it was before break_out_memory_refs was called.
3362 In some cases it is useful to look at this to decide what needs to be done.
3363
3364 MODE is the mode of the operand pointed to by X.
3365
3366 When -fpic is used, special handling is needed for symbolic references.
3367 See comments by legitimize_pic_address for details. */
3368
3369 rtx
3370 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3371 enum machine_mode mode ATTRIBUTE_UNUSED)
3372 {
3373 rtx constant_term = const0_rtx;
3374
3375 if (TLS_SYMBOLIC_CONST (x))
3376 {
3377 x = legitimize_tls_address (x, 0);
3378
3379 if (legitimate_address_p (mode, x, FALSE))
3380 return x;
3381 }
3382 else if (GET_CODE (x) == PLUS
3383 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3384 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3385 {
3386 return x;
3387 }
3388 else if (flag_pic)
3389 {
3390 if (SYMBOLIC_CONST (x)
3391 || (GET_CODE (x) == PLUS
3392 && (SYMBOLIC_CONST (XEXP (x, 0))
3393 || SYMBOLIC_CONST (XEXP (x, 1)))))
3394 x = legitimize_pic_address (x, 0);
3395
3396 if (legitimate_address_p (mode, x, FALSE))
3397 return x;
3398 }
3399
3400 x = eliminate_constant_term (x, &constant_term);
3401
3402 /* Optimize loading of large displacements by splitting them
3403 into the multiple of 4K and the rest; this allows the
3404 former to be CSE'd if possible.
3405
3406 Don't do this if the displacement is added to a register
3407 pointing into the stack frame, as the offsets will
3408 change later anyway. */
3409
3410 if (GET_CODE (constant_term) == CONST_INT
3411 && !TARGET_LONG_DISPLACEMENT
3412 && !DISP_IN_RANGE (INTVAL (constant_term))
3413 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3414 {
3415 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3416 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3417
3418 rtx temp = gen_reg_rtx (Pmode);
3419 rtx val = force_operand (GEN_INT (upper), temp);
3420 if (val != temp)
3421 emit_move_insn (temp, val);
3422
3423 x = gen_rtx_PLUS (Pmode, x, temp);
3424 constant_term = GEN_INT (lower);
3425 }
3426
3427 if (GET_CODE (x) == PLUS)
3428 {
3429 if (GET_CODE (XEXP (x, 0)) == REG)
3430 {
3431 rtx temp = gen_reg_rtx (Pmode);
3432 rtx val = force_operand (XEXP (x, 1), temp);
3433 if (val != temp)
3434 emit_move_insn (temp, val);
3435
3436 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3437 }
3438
3439 else if (GET_CODE (XEXP (x, 1)) == REG)
3440 {
3441 rtx temp = gen_reg_rtx (Pmode);
3442 rtx val = force_operand (XEXP (x, 0), temp);
3443 if (val != temp)
3444 emit_move_insn (temp, val);
3445
3446 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3447 }
3448 }
3449
3450 if (constant_term != const0_rtx)
3451 x = gen_rtx_PLUS (Pmode, x, constant_term);
3452
3453 return x;
3454 }
3455
3456 /* Try a machine-dependent way of reloading an illegitimate address AD
3457 operand. If we find one, push the reload and and return the new address.
3458
3459 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3460 and TYPE is the reload type of the current reload. */
3461
3462 rtx
3463 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3464 int opnum, int type)
3465 {
3466 if (!optimize || TARGET_LONG_DISPLACEMENT)
3467 return NULL_RTX;
3468
3469 if (GET_CODE (ad) == PLUS)
3470 {
3471 rtx tem = simplify_binary_operation (PLUS, Pmode,
3472 XEXP (ad, 0), XEXP (ad, 1));
3473 if (tem)
3474 ad = tem;
3475 }
3476
3477 if (GET_CODE (ad) == PLUS
3478 && GET_CODE (XEXP (ad, 0)) == REG
3479 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3480 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3481 {
3482 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3483 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3484 rtx cst, tem, new;
3485
3486 cst = GEN_INT (upper);
3487 if (!legitimate_reload_constant_p (cst))
3488 cst = force_const_mem (Pmode, cst);
3489
3490 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3491 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3492
3493 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3494 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3495 opnum, (enum reload_type) type);
3496 return new;
3497 }
3498
3499 return NULL_RTX;
3500 }
3501
3502 /* Emit code to move LEN bytes from DST to SRC. */
3503
3504 void
3505 s390_expand_movmem (rtx dst, rtx src, rtx len)
3506 {
3507 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3508 {
3509 if (INTVAL (len) > 0)
3510 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3511 }
3512
3513 else if (TARGET_MVCLE)
3514 {
3515 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3516 }
3517
3518 else
3519 {
3520 rtx dst_addr, src_addr, count, blocks, temp;
3521 rtx loop_start_label = gen_label_rtx ();
3522 rtx loop_end_label = gen_label_rtx ();
3523 rtx end_label = gen_label_rtx ();
3524 enum machine_mode mode;
3525
3526 mode = GET_MODE (len);
3527 if (mode == VOIDmode)
3528 mode = Pmode;
3529
3530 dst_addr = gen_reg_rtx (Pmode);
3531 src_addr = gen_reg_rtx (Pmode);
3532 count = gen_reg_rtx (mode);
3533 blocks = gen_reg_rtx (mode);
3534
3535 convert_move (count, len, 1);
3536 emit_cmp_and_jump_insns (count, const0_rtx,
3537 EQ, NULL_RTX, mode, 1, end_label);
3538
3539 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3540 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3541 dst = change_address (dst, VOIDmode, dst_addr);
3542 src = change_address (src, VOIDmode, src_addr);
3543
3544 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3545 if (temp != count)
3546 emit_move_insn (count, temp);
3547
3548 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3549 if (temp != blocks)
3550 emit_move_insn (blocks, temp);
3551
3552 emit_cmp_and_jump_insns (blocks, const0_rtx,
3553 EQ, NULL_RTX, mode, 1, loop_end_label);
3554
3555 emit_label (loop_start_label);
3556
3557 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3558 s390_load_address (dst_addr,
3559 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3560 s390_load_address (src_addr,
3561 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3562
3563 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3564 if (temp != blocks)
3565 emit_move_insn (blocks, temp);
3566
3567 emit_cmp_and_jump_insns (blocks, const0_rtx,
3568 EQ, NULL_RTX, mode, 1, loop_end_label);
3569
3570 emit_jump (loop_start_label);
3571 emit_label (loop_end_label);
3572
3573 emit_insn (gen_movmem_short (dst, src,
3574 convert_to_mode (Pmode, count, 1)));
3575 emit_label (end_label);
3576 }
3577 }
3578
3579 /* Emit code to set LEN bytes at DST to VAL.
3580 Make use of clrmem if VAL is zero. */
3581
3582 void
3583 s390_expand_setmem (rtx dst, rtx len, rtx val)
3584 {
3585 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3586 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3587
3588 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3589 {
3590 if (val == const0_rtx && INTVAL (len) <= 256)
3591 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3592 else
3593 {
3594 /* Initialize memory by storing the first byte. */
3595 emit_move_insn (adjust_address (dst, QImode, 0), val);
3596
3597 if (INTVAL (len) > 1)
3598 {
3599 /* Initiate 1 byte overlap move.
3600 The first byte of DST is propagated through DSTP1.
3601 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3602 DST is set to size 1 so the rest of the memory location
3603 does not count as source operand. */
3604 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3605 set_mem_size (dst, const1_rtx);
3606
3607 emit_insn (gen_movmem_short (dstp1, dst,
3608 GEN_INT (INTVAL (len) - 2)));
3609 }
3610 }
3611 }
3612
3613 else if (TARGET_MVCLE)
3614 {
3615 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3616 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3617 }
3618
3619 else
3620 {
3621 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3622 rtx loop_start_label = gen_label_rtx ();
3623 rtx loop_end_label = gen_label_rtx ();
3624 rtx end_label = gen_label_rtx ();
3625 enum machine_mode mode;
3626
3627 mode = GET_MODE (len);
3628 if (mode == VOIDmode)
3629 mode = Pmode;
3630
3631 dst_addr = gen_reg_rtx (Pmode);
3632 src_addr = gen_reg_rtx (Pmode);
3633 count = gen_reg_rtx (mode);
3634 blocks = gen_reg_rtx (mode);
3635
3636 convert_move (count, len, 1);
3637 emit_cmp_and_jump_insns (count, const0_rtx,
3638 EQ, NULL_RTX, mode, 1, end_label);
3639
3640 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3641 dst = change_address (dst, VOIDmode, dst_addr);
3642
3643 if (val == const0_rtx)
3644 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3645 else
3646 {
3647 dstp1 = adjust_address (dst, VOIDmode, 1);
3648 set_mem_size (dst, const1_rtx);
3649
3650 /* Initialize memory by storing the first byte. */
3651 emit_move_insn (adjust_address (dst, QImode, 0), val);
3652
3653 /* If count is 1 we are done. */
3654 emit_cmp_and_jump_insns (count, const1_rtx,
3655 EQ, NULL_RTX, mode, 1, end_label);
3656
3657 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3658 }
3659 if (temp != count)
3660 emit_move_insn (count, temp);
3661
3662 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3663 if (temp != blocks)
3664 emit_move_insn (blocks, temp);
3665
3666 emit_cmp_and_jump_insns (blocks, const0_rtx,
3667 EQ, NULL_RTX, mode, 1, loop_end_label);
3668
3669 emit_label (loop_start_label);
3670
3671 if (val == const0_rtx)
3672 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3673 else
3674 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3675 s390_load_address (dst_addr,
3676 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3677
3678 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3679 if (temp != blocks)
3680 emit_move_insn (blocks, temp);
3681
3682 emit_cmp_and_jump_insns (blocks, const0_rtx,
3683 EQ, NULL_RTX, mode, 1, loop_end_label);
3684
3685 emit_jump (loop_start_label);
3686 emit_label (loop_end_label);
3687
3688 if (val == const0_rtx)
3689 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3690 else
3691 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3692 emit_label (end_label);
3693 }
3694 }
3695
3696 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3697 and return the result in TARGET. */
3698
3699 void
3700 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3701 {
3702 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3703 rtx tmp;
3704
3705 /* As the result of CMPINT is inverted compared to what we need,
3706 we have to swap the operands. */
3707 tmp = op0; op0 = op1; op1 = tmp;
3708
3709 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3710 {
3711 if (INTVAL (len) > 0)
3712 {
3713 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3714 emit_insn (gen_cmpint (target, ccreg));
3715 }
3716 else
3717 emit_move_insn (target, const0_rtx);
3718 }
3719 else if (TARGET_MVCLE)
3720 {
3721 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3722 emit_insn (gen_cmpint (target, ccreg));
3723 }
3724 else
3725 {
3726 rtx addr0, addr1, count, blocks, temp;
3727 rtx loop_start_label = gen_label_rtx ();
3728 rtx loop_end_label = gen_label_rtx ();
3729 rtx end_label = gen_label_rtx ();
3730 enum machine_mode mode;
3731
3732 mode = GET_MODE (len);
3733 if (mode == VOIDmode)
3734 mode = Pmode;
3735
3736 addr0 = gen_reg_rtx (Pmode);
3737 addr1 = gen_reg_rtx (Pmode);
3738 count = gen_reg_rtx (mode);
3739 blocks = gen_reg_rtx (mode);
3740
3741 convert_move (count, len, 1);
3742 emit_cmp_and_jump_insns (count, const0_rtx,
3743 EQ, NULL_RTX, mode, 1, end_label);
3744
3745 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3746 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3747 op0 = change_address (op0, VOIDmode, addr0);
3748 op1 = change_address (op1, VOIDmode, addr1);
3749
3750 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3751 if (temp != count)
3752 emit_move_insn (count, temp);
3753
3754 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3755 if (temp != blocks)
3756 emit_move_insn (blocks, temp);
3757
3758 emit_cmp_and_jump_insns (blocks, const0_rtx,
3759 EQ, NULL_RTX, mode, 1, loop_end_label);
3760
3761 emit_label (loop_start_label);
3762
3763 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3764 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3765 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3766 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3767 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3768 emit_jump_insn (temp);
3769
3770 s390_load_address (addr0,
3771 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3772 s390_load_address (addr1,
3773 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3774
3775 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3776 if (temp != blocks)
3777 emit_move_insn (blocks, temp);
3778
3779 emit_cmp_and_jump_insns (blocks, const0_rtx,
3780 EQ, NULL_RTX, mode, 1, loop_end_label);
3781
3782 emit_jump (loop_start_label);
3783 emit_label (loop_end_label);
3784
3785 emit_insn (gen_cmpmem_short (op0, op1,
3786 convert_to_mode (Pmode, count, 1)));
3787 emit_label (end_label);
3788
3789 emit_insn (gen_cmpint (target, ccreg));
3790 }
3791 }
3792
3793
3794 /* Expand conditional increment or decrement using alc/slb instructions.
3795 Should generate code setting DST to either SRC or SRC + INCREMENT,
3796 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3797 Returns true if successful, false otherwise.
3798
3799 That makes it possible to implement some if-constructs without jumps e.g.:
3800 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3801 unsigned int a, b, c;
3802 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3803 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3804 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3805 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3806
3807 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3808 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3809 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3810 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3811 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3812
3813 bool
3814 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3815 rtx dst, rtx src, rtx increment)
3816 {
3817 enum machine_mode cmp_mode;
3818 enum machine_mode cc_mode;
3819 rtx op_res;
3820 rtx insn;
3821 rtvec p;
3822 int ret;
3823
3824 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3825 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3826 cmp_mode = SImode;
3827 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3828 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3829 cmp_mode = DImode;
3830 else
3831 return false;
3832
3833 /* Try ADD LOGICAL WITH CARRY. */
3834 if (increment == const1_rtx)
3835 {
3836 /* Determine CC mode to use. */
3837 if (cmp_code == EQ || cmp_code == NE)
3838 {
3839 if (cmp_op1 != const0_rtx)
3840 {
3841 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3842 NULL_RTX, 0, OPTAB_WIDEN);
3843 cmp_op1 = const0_rtx;
3844 }
3845
3846 cmp_code = cmp_code == EQ ? LEU : GTU;
3847 }
3848
3849 if (cmp_code == LTU || cmp_code == LEU)
3850 {
3851 rtx tem = cmp_op0;
3852 cmp_op0 = cmp_op1;
3853 cmp_op1 = tem;
3854 cmp_code = swap_condition (cmp_code);
3855 }
3856
3857 switch (cmp_code)
3858 {
3859 case GTU:
3860 cc_mode = CCUmode;
3861 break;
3862
3863 case GEU:
3864 cc_mode = CCL3mode;
3865 break;
3866
3867 default:
3868 return false;
3869 }
3870
3871 /* Emit comparison instruction pattern. */
3872 if (!register_operand (cmp_op0, cmp_mode))
3873 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3874
3875 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3876 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3877 /* We use insn_invalid_p here to add clobbers if required. */
3878 ret = insn_invalid_p (emit_insn (insn));
3879 gcc_assert (!ret);
3880
3881 /* Emit ALC instruction pattern. */
3882 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3883 gen_rtx_REG (cc_mode, CC_REGNUM),
3884 const0_rtx);
3885
3886 if (src != const0_rtx)
3887 {
3888 if (!register_operand (src, GET_MODE (dst)))
3889 src = force_reg (GET_MODE (dst), src);
3890
3891 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3892 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3893 }
3894
3895 p = rtvec_alloc (2);
3896 RTVEC_ELT (p, 0) =
3897 gen_rtx_SET (VOIDmode, dst, op_res);
3898 RTVEC_ELT (p, 1) =
3899 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3900 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3901
3902 return true;
3903 }
3904
3905 /* Try SUBTRACT LOGICAL WITH BORROW. */
3906 if (increment == constm1_rtx)
3907 {
3908 /* Determine CC mode to use. */
3909 if (cmp_code == EQ || cmp_code == NE)
3910 {
3911 if (cmp_op1 != const0_rtx)
3912 {
3913 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3914 NULL_RTX, 0, OPTAB_WIDEN);
3915 cmp_op1 = const0_rtx;
3916 }
3917
3918 cmp_code = cmp_code == EQ ? LEU : GTU;
3919 }
3920
3921 if (cmp_code == GTU || cmp_code == GEU)
3922 {
3923 rtx tem = cmp_op0;
3924 cmp_op0 = cmp_op1;
3925 cmp_op1 = tem;
3926 cmp_code = swap_condition (cmp_code);
3927 }
3928
3929 switch (cmp_code)
3930 {
3931 case LEU:
3932 cc_mode = CCUmode;
3933 break;
3934
3935 case LTU:
3936 cc_mode = CCL3mode;
3937 break;
3938
3939 default:
3940 return false;
3941 }
3942
3943 /* Emit comparison instruction pattern. */
3944 if (!register_operand (cmp_op0, cmp_mode))
3945 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3946
3947 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3948 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3949 /* We use insn_invalid_p here to add clobbers if required. */
3950 ret = insn_invalid_p (emit_insn (insn));
3951 gcc_assert (!ret);
3952
3953 /* Emit SLB instruction pattern. */
3954 if (!register_operand (src, GET_MODE (dst)))
3955 src = force_reg (GET_MODE (dst), src);
3956
3957 op_res = gen_rtx_MINUS (GET_MODE (dst),
3958 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3959 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3960 gen_rtx_REG (cc_mode, CC_REGNUM),
3961 const0_rtx));
3962 p = rtvec_alloc (2);
3963 RTVEC_ELT (p, 0) =
3964 gen_rtx_SET (VOIDmode, dst, op_res);
3965 RTVEC_ELT (p, 1) =
3966 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3967 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3968
3969 return true;
3970 }
3971
3972 return false;
3973 }
3974
3975 /* Expand code for the insv template. Return true if successful, false else. */
3976
3977 bool
3978 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3979 {
3980 int bitsize = INTVAL (op1);
3981 int bitpos = INTVAL (op2);
3982
3983 /* We need byte alignment. */
3984 if (bitsize % BITS_PER_UNIT)
3985 return false;
3986
3987 if (bitpos == 0
3988 && memory_operand (dest, VOIDmode)
3989 && (register_operand (src, word_mode)
3990 || const_int_operand (src, VOIDmode)))
3991 {
3992 /* Emit standard pattern if possible. */
3993 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3994 if (GET_MODE_BITSIZE (mode) == bitsize)
3995 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3996
3997 /* (set (ze (mem)) (const_int)). */
3998 else if (const_int_operand (src, VOIDmode))
3999 {
4000 int size = bitsize / BITS_PER_UNIT;
4001 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4002 GET_MODE_SIZE (word_mode) - size);
4003
4004 dest = adjust_address (dest, BLKmode, 0);
4005 set_mem_size (dest, GEN_INT (size));
4006 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4007 }
4008
4009 /* (set (ze (mem)) (reg)). */
4010 else if (register_operand (src, word_mode))
4011 {
4012 if (bitsize <= GET_MODE_BITSIZE (SImode))
4013 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4014 const0_rtx), src);
4015 else
4016 {
4017 /* Emit st,stcmh sequence. */
4018 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4019 int size = stcmh_width / BITS_PER_UNIT;
4020
4021 emit_move_insn (adjust_address (dest, SImode, size),
4022 gen_lowpart (SImode, src));
4023 set_mem_size (dest, GEN_INT (size));
4024 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4025 (stcmh_width), const0_rtx),
4026 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4027 (GET_MODE_BITSIZE (SImode))));
4028 }
4029 }
4030 else
4031 return false;
4032
4033 return true;
4034 }
4035
4036 /* (set (ze (reg)) (const_int)). */
4037 if (TARGET_ZARCH
4038 && register_operand (dest, word_mode)
4039 && (bitpos % 16) == 0
4040 && (bitsize % 16) == 0
4041 && const_int_operand (src, VOIDmode))
4042 {
4043 HOST_WIDE_INT val = INTVAL (src);
4044 int regpos = bitpos + bitsize;
4045
4046 while (regpos > bitpos)
4047 {
4048 enum machine_mode putmode;
4049 int putsize;
4050
4051 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4052 putmode = SImode;
4053 else
4054 putmode = HImode;
4055
4056 putsize = GET_MODE_BITSIZE (putmode);
4057 regpos -= putsize;
4058 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4059 GEN_INT (putsize),
4060 GEN_INT (regpos)),
4061 gen_int_mode (val, putmode));
4062 val >>= putsize;
4063 }
4064 gcc_assert (regpos == bitpos);
4065 return true;
4066 }
4067
4068 return false;
4069 }
4070
4071 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4072 register that holds VAL of mode MODE shifted by COUNT bits. */
4073
4074 static inline rtx
4075 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4076 {
4077 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4078 NULL_RTX, 1, OPTAB_DIRECT);
4079 return expand_simple_binop (SImode, ASHIFT, val, count,
4080 NULL_RTX, 1, OPTAB_DIRECT);
4081 }
4082
4083 /* Structure to hold the initial parameters for a compare_and_swap operation
4084 in HImode and QImode. */
4085
4086 struct alignment_context
4087 {
4088 rtx memsi; /* SI aligned memory location. */
4089 rtx shift; /* Bit offset with regard to lsb. */
4090 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4091 rtx modemaski; /* ~modemask */
4092 bool aligned; /* True if memory is aligned, false else. */
4093 };
4094
4095 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4096 structure AC for transparent simplifying, if the memory alignment is known
4097 to be at least 32bit. MEM is the memory location for the actual operation
4098 and MODE its mode. */
4099
4100 static void
4101 init_alignment_context (struct alignment_context *ac, rtx mem,
4102 enum machine_mode mode)
4103 {
4104 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4105 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4106
4107 if (ac->aligned)
4108 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4109 else
4110 {
4111 /* Alignment is unknown. */
4112 rtx byteoffset, addr, align;
4113
4114 /* Force the address into a register. */
4115 addr = force_reg (Pmode, XEXP (mem, 0));
4116
4117 /* Align it to SImode. */
4118 align = expand_simple_binop (Pmode, AND, addr,
4119 GEN_INT (-GET_MODE_SIZE (SImode)),
4120 NULL_RTX, 1, OPTAB_DIRECT);
4121 /* Generate MEM. */
4122 ac->memsi = gen_rtx_MEM (SImode, align);
4123 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4124 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4125 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4126
4127 /* Calculate shiftcount. */
4128 byteoffset = expand_simple_binop (Pmode, AND, addr,
4129 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4130 NULL_RTX, 1, OPTAB_DIRECT);
4131 /* As we already have some offset, evaluate the remaining distance. */
4132 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4133 NULL_RTX, 1, OPTAB_DIRECT);
4134
4135 }
4136 /* Shift is the byte count, but we need the bitcount. */
4137 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4138 NULL_RTX, 1, OPTAB_DIRECT);
4139 /* Calculate masks. */
4140 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4141 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4142 NULL_RTX, 1, OPTAB_DIRECT);
4143 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4144 }
4145
4146 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4147 the memory location, CMP the old value to compare MEM with and NEW the value
4148 to set if CMP == MEM.
4149 CMP is never in memory for compare_and_swap_cc because
4150 expand_bool_compare_and_swap puts it into a register for later compare. */
4151
4152 void
4153 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4154 {
4155 struct alignment_context ac;
4156 rtx cmpv, newv, val, resv, cc;
4157 rtx res = gen_reg_rtx (SImode);
4158 rtx csloop = gen_label_rtx ();
4159 rtx csend = gen_label_rtx ();
4160
4161 gcc_assert (register_operand (target, VOIDmode));
4162 gcc_assert (MEM_P (mem));
4163
4164 init_alignment_context (&ac, mem, mode);
4165
4166 /* Shift the values to the correct bit positions. */
4167 if (!(ac.aligned && MEM_P (cmp)))
4168 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4169 if (!(ac.aligned && MEM_P (new)))
4170 new = s390_expand_mask_and_shift (new, mode, ac.shift);
4171
4172 /* Load full word. Subsequent loads are performed by CS. */
4173 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4174 NULL_RTX, 1, OPTAB_DIRECT);
4175
4176 /* Start CS loop. */
4177 emit_label (csloop);
4178 /* val = "<mem>00..0<mem>"
4179 * cmp = "00..0<cmp>00..0"
4180 * new = "00..0<new>00..0"
4181 */
4182
4183 /* Patch cmp and new with val at correct position. */
4184 if (ac.aligned && MEM_P (cmp))
4185 {
4186 cmpv = force_reg (SImode, val);
4187 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4188 }
4189 else
4190 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4191 NULL_RTX, 1, OPTAB_DIRECT));
4192 if (ac.aligned && MEM_P (new))
4193 {
4194 newv = force_reg (SImode, val);
4195 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4196 }
4197 else
4198 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4199 NULL_RTX, 1, OPTAB_DIRECT));
4200
4201 /* Emit compare_and_swap pattern. */
4202 emit_insn (gen_sync_compare_and_swap_ccsi (res, ac.memsi, cmpv, newv));
4203
4204 /* Jump to end if we're done (likely?). */
4205 s390_emit_jump (csend, s390_emit_compare (EQ, cmpv, ac.memsi));
4206
4207 /* Check for changes outside mode. */
4208 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4209 NULL_RTX, 1, OPTAB_DIRECT);
4210 cc = s390_emit_compare (NE, resv, val);
4211 emit_move_insn (val, resv);
4212 /* Loop internal if so. */
4213 s390_emit_jump (csloop, cc);
4214
4215 emit_label (csend);
4216
4217 /* Return the correct part of the bitfield. */
4218 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4219 NULL_RTX, 1, OPTAB_DIRECT), 1);
4220 }
4221
4222 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4223 and VAL the value to play with. If AFTER is true then store the the value
4224 MEM holds after the operation, if AFTER is false then store the value MEM
4225 holds before the operation. If TARGET is zero then discard that value, else
4226 store it to TARGET. */
4227
4228 void
4229 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4230 rtx target, rtx mem, rtx val, bool after)
4231 {
4232 struct alignment_context ac;
4233 rtx cmp;
4234 rtx new = gen_reg_rtx (SImode);
4235 rtx orig = gen_reg_rtx (SImode);
4236 rtx csloop = gen_label_rtx ();
4237
4238 gcc_assert (!target || register_operand (target, VOIDmode));
4239 gcc_assert (MEM_P (mem));
4240
4241 init_alignment_context (&ac, mem, mode);
4242
4243 /* Shift val to the correct bit positions.
4244 Preserve "icm", but prevent "ex icm". */
4245 if (!(ac.aligned && code == SET && MEM_P (val)))
4246 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4247
4248 /* Further preparation insns. */
4249 if (code == PLUS || code == MINUS)
4250 emit_move_insn (orig, val);
4251 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4252 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4253 NULL_RTX, 1, OPTAB_DIRECT);
4254
4255 /* Load full word. Subsequent loads are performed by CS. */
4256 cmp = force_reg (SImode, ac.memsi);
4257
4258 /* Start CS loop. */
4259 emit_label (csloop);
4260 emit_move_insn (new, cmp);
4261
4262 /* Patch new with val at correct position. */
4263 switch (code)
4264 {
4265 case PLUS:
4266 case MINUS:
4267 val = expand_simple_binop (SImode, code, new, orig,
4268 NULL_RTX, 1, OPTAB_DIRECT);
4269 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4270 NULL_RTX, 1, OPTAB_DIRECT);
4271 /* FALLTHRU */
4272 case SET:
4273 if (ac.aligned && MEM_P (val))
4274 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4275 else
4276 {
4277 new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4278 NULL_RTX, 1, OPTAB_DIRECT);
4279 new = expand_simple_binop (SImode, IOR, new, val,
4280 NULL_RTX, 1, OPTAB_DIRECT);
4281 }
4282 break;
4283 case AND:
4284 case IOR:
4285 case XOR:
4286 new = expand_simple_binop (SImode, code, new, val,
4287 NULL_RTX, 1, OPTAB_DIRECT);
4288 break;
4289 case MULT: /* NAND */
4290 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4291 NULL_RTX, 1, OPTAB_DIRECT);
4292 new = expand_simple_binop (SImode, AND, new, val,
4293 NULL_RTX, 1, OPTAB_DIRECT);
4294 break;
4295 default:
4296 gcc_unreachable ();
4297 }
4298 /* Emit compare_and_swap pattern. */
4299 emit_insn (gen_sync_compare_and_swap_ccsi (cmp, ac.memsi, cmp, new));
4300
4301 /* Loop until swapped (unlikely?). */
4302 s390_emit_jump (csloop, gen_rtx_fmt_ee (NE, CCZ1mode,
4303 gen_rtx_REG (CCZ1mode, CC_REGNUM),
4304 const0_rtx));
4305
4306 /* Return the correct part of the bitfield. */
4307 if (target)
4308 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4309 after ? new : cmp, ac.shift,
4310 NULL_RTX, 1, OPTAB_DIRECT), 1);
4311 }
4312
4313 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4314 We need to emit DTP-relative relocations. */
4315
4316 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4317
4318 static void
4319 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4320 {
4321 switch (size)
4322 {
4323 case 4:
4324 fputs ("\t.long\t", file);
4325 break;
4326 case 8:
4327 fputs ("\t.quad\t", file);
4328 break;
4329 default:
4330 gcc_unreachable ();
4331 }
4332 output_addr_const (file, x);
4333 fputs ("@DTPOFF", file);
4334 }
4335
4336 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4337 /* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */
4338
4339 static const char *
4340 s390_mangle_fundamental_type (tree type)
4341 {
4342 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4343 && TARGET_LONG_DOUBLE_128)
4344 return "g";
4345
4346 /* For all other types, use normal C++ mangling. */
4347 return NULL;
4348 }
4349 #endif
4350
4351 /* In the name of slightly smaller debug output, and to cater to
4352 general assembler lossage, recognize various UNSPEC sequences
4353 and turn them back into a direct symbol reference. */
4354
4355 static rtx
4356 s390_delegitimize_address (rtx orig_x)
4357 {
4358 rtx x = orig_x, y;
4359
4360 if (GET_CODE (x) != MEM)
4361 return orig_x;
4362
4363 x = XEXP (x, 0);
4364 if (GET_CODE (x) == PLUS
4365 && GET_CODE (XEXP (x, 1)) == CONST
4366 && GET_CODE (XEXP (x, 0)) == REG
4367 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4368 {
4369 y = XEXP (XEXP (x, 1), 0);
4370 if (GET_CODE (y) == UNSPEC
4371 && XINT (y, 1) == UNSPEC_GOT)
4372 return XVECEXP (y, 0, 0);
4373 return orig_x;
4374 }
4375
4376 if (GET_CODE (x) == CONST)
4377 {
4378 y = XEXP (x, 0);
4379 if (GET_CODE (y) == UNSPEC
4380 && XINT (y, 1) == UNSPEC_GOTENT)
4381 return XVECEXP (y, 0, 0);
4382 return orig_x;
4383 }
4384
4385 return orig_x;
4386 }
4387
4388 /* Output operand OP to stdio stream FILE.
4389 OP is an address (register + offset) which is not used to address data;
4390 instead the rightmost bits are interpreted as the value. */
4391
4392 static void
4393 print_shift_count_operand (FILE *file, rtx op)
4394 {
4395 HOST_WIDE_INT offset;
4396 rtx base;
4397
4398 /* Extract base register and offset. */
4399 if (!s390_decompose_shift_count (op, &base, &offset))
4400 gcc_unreachable ();
4401
4402 /* Sanity check. */
4403 if (base)
4404 {
4405 gcc_assert (GET_CODE (base) == REG);
4406 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4407 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4408 }
4409
4410 /* Offsets are constricted to twelve bits. */
4411 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4412 if (base)
4413 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4414 }
4415
4416 /* See 'get_some_local_dynamic_name'. */
4417
4418 static int
4419 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4420 {
4421 rtx x = *px;
4422
4423 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4424 {
4425 x = get_pool_constant (x);
4426 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4427 }
4428
4429 if (GET_CODE (x) == SYMBOL_REF
4430 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4431 {
4432 cfun->machine->some_ld_name = XSTR (x, 0);
4433 return 1;
4434 }
4435
4436 return 0;
4437 }
4438
4439 /* Locate some local-dynamic symbol still in use by this function
4440 so that we can print its name in local-dynamic base patterns. */
4441
4442 static const char *
4443 get_some_local_dynamic_name (void)
4444 {
4445 rtx insn;
4446
4447 if (cfun->machine->some_ld_name)
4448 return cfun->machine->some_ld_name;
4449
4450 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4451 if (INSN_P (insn)
4452 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4453 return cfun->machine->some_ld_name;
4454
4455 gcc_unreachable ();
4456 }
4457
4458 /* Output machine-dependent UNSPECs occurring in address constant X
4459 in assembler syntax to stdio stream FILE. Returns true if the
4460 constant X could be recognized, false otherwise. */
4461
4462 bool
4463 s390_output_addr_const_extra (FILE *file, rtx x)
4464 {
4465 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4466 switch (XINT (x, 1))
4467 {
4468 case UNSPEC_GOTENT:
4469 output_addr_const (file, XVECEXP (x, 0, 0));
4470 fprintf (file, "@GOTENT");
4471 return true;
4472 case UNSPEC_GOT:
4473 output_addr_const (file, XVECEXP (x, 0, 0));
4474 fprintf (file, "@GOT");
4475 return true;
4476 case UNSPEC_GOTOFF:
4477 output_addr_const (file, XVECEXP (x, 0, 0));
4478 fprintf (file, "@GOTOFF");
4479 return true;
4480 case UNSPEC_PLT:
4481 output_addr_const (file, XVECEXP (x, 0, 0));
4482 fprintf (file, "@PLT");
4483 return true;
4484 case UNSPEC_PLTOFF:
4485 output_addr_const (file, XVECEXP (x, 0, 0));
4486 fprintf (file, "@PLTOFF");
4487 return true;
4488 case UNSPEC_TLSGD:
4489 output_addr_const (file, XVECEXP (x, 0, 0));
4490 fprintf (file, "@TLSGD");
4491 return true;
4492 case UNSPEC_TLSLDM:
4493 assemble_name (file, get_some_local_dynamic_name ());
4494 fprintf (file, "@TLSLDM");
4495 return true;
4496 case UNSPEC_DTPOFF:
4497 output_addr_const (file, XVECEXP (x, 0, 0));
4498 fprintf (file, "@DTPOFF");
4499 return true;
4500 case UNSPEC_NTPOFF:
4501 output_addr_const (file, XVECEXP (x, 0, 0));
4502 fprintf (file, "@NTPOFF");
4503 return true;
4504 case UNSPEC_GOTNTPOFF:
4505 output_addr_const (file, XVECEXP (x, 0, 0));
4506 fprintf (file, "@GOTNTPOFF");
4507 return true;
4508 case UNSPEC_INDNTPOFF:
4509 output_addr_const (file, XVECEXP (x, 0, 0));
4510 fprintf (file, "@INDNTPOFF");
4511 return true;
4512 }
4513
4514 return false;
4515 }
4516
4517 /* Output address operand ADDR in assembler syntax to
4518 stdio stream FILE. */
4519
4520 void
4521 print_operand_address (FILE *file, rtx addr)
4522 {
4523 struct s390_address ad;
4524
4525 if (!s390_decompose_address (addr, &ad)
4526 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4527 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4528 output_operand_lossage ("cannot decompose address");
4529
4530 if (ad.disp)
4531 output_addr_const (file, ad.disp);
4532 else
4533 fprintf (file, "0");
4534
4535 if (ad.base && ad.indx)
4536 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4537 reg_names[REGNO (ad.base)]);
4538 else if (ad.base)
4539 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4540 }
4541
4542 /* Output operand X in assembler syntax to stdio stream FILE.
4543 CODE specified the format flag. The following format flags
4544 are recognized:
4545
4546 'C': print opcode suffix for branch condition.
4547 'D': print opcode suffix for inverse branch condition.
4548 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4549 'G': print the size of the operand in bytes.
4550 'O': print only the displacement of a memory reference.
4551 'R': print only the base register of a memory reference.
4552 'S': print S-type memory reference (base+displacement).
4553 'N': print the second word of a DImode operand.
4554 'M': print the second word of a TImode operand.
4555 'Y': print shift count operand.
4556
4557 'b': print integer X as if it's an unsigned byte.
4558 'x': print integer X as if it's an unsigned halfword.
4559 'h': print integer X as if it's a signed halfword.
4560 'i': print the first nonzero HImode part of X.
4561 'j': print the first HImode part unequal to -1 of X.
4562 'k': print the first nonzero SImode part of X.
4563 'm': print the first SImode part unequal to -1 of X.
4564 'o': print integer X as if it's an unsigned 32bit word. */
4565
4566 void
4567 print_operand (FILE *file, rtx x, int code)
4568 {
4569 switch (code)
4570 {
4571 case 'C':
4572 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4573 return;
4574
4575 case 'D':
4576 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4577 return;
4578
4579 case 'J':
4580 if (GET_CODE (x) == SYMBOL_REF)
4581 {
4582 fprintf (file, "%s", ":tls_load:");
4583 output_addr_const (file, x);
4584 }
4585 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4586 {
4587 fprintf (file, "%s", ":tls_gdcall:");
4588 output_addr_const (file, XVECEXP (x, 0, 0));
4589 }
4590 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4591 {
4592 fprintf (file, "%s", ":tls_ldcall:");
4593 assemble_name (file, get_some_local_dynamic_name ());
4594 }
4595 else
4596 gcc_unreachable ();
4597 return;
4598
4599 case 'G':
4600 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4601 return;
4602
4603 case 'O':
4604 {
4605 struct s390_address ad;
4606 int ret;
4607
4608 gcc_assert (GET_CODE (x) == MEM);
4609 ret = s390_decompose_address (XEXP (x, 0), &ad);
4610 gcc_assert (ret);
4611 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4612 gcc_assert (!ad.indx);
4613
4614 if (ad.disp)
4615 output_addr_const (file, ad.disp);
4616 else
4617 fprintf (file, "0");
4618 }
4619 return;
4620
4621 case 'R':
4622 {
4623 struct s390_address ad;
4624 int ret;
4625
4626 gcc_assert (GET_CODE (x) == MEM);
4627 ret = s390_decompose_address (XEXP (x, 0), &ad);
4628 gcc_assert (ret);
4629 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4630 gcc_assert (!ad.indx);
4631
4632 if (ad.base)
4633 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4634 else
4635 fprintf (file, "0");
4636 }
4637 return;
4638
4639 case 'S':
4640 {
4641 struct s390_address ad;
4642 int ret;
4643
4644 gcc_assert (GET_CODE (x) == MEM);
4645 ret = s390_decompose_address (XEXP (x, 0), &ad);
4646 gcc_assert (ret);
4647 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4648 gcc_assert (!ad.indx);
4649
4650 if (ad.disp)
4651 output_addr_const (file, ad.disp);
4652 else
4653 fprintf (file, "0");
4654
4655 if (ad.base)
4656 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4657 }
4658 return;
4659
4660 case 'N':
4661 if (GET_CODE (x) == REG)
4662 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4663 else if (GET_CODE (x) == MEM)
4664 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4665 else
4666 gcc_unreachable ();
4667 break;
4668
4669 case 'M':
4670 if (GET_CODE (x) == REG)
4671 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4672 else if (GET_CODE (x) == MEM)
4673 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4674 else
4675 gcc_unreachable ();
4676 break;
4677
4678 case 'Y':
4679 print_shift_count_operand (file, x);
4680 return;
4681 }
4682
4683 switch (GET_CODE (x))
4684 {
4685 case REG:
4686 fprintf (file, "%s", reg_names[REGNO (x)]);
4687 break;
4688
4689 case MEM:
4690 output_address (XEXP (x, 0));
4691 break;
4692
4693 case CONST:
4694 case CODE_LABEL:
4695 case LABEL_REF:
4696 case SYMBOL_REF:
4697 output_addr_const (file, x);
4698 break;
4699
4700 case CONST_INT:
4701 if (code == 'b')
4702 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4703 else if (code == 'x')
4704 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4705 else if (code == 'h')
4706 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4707 else if (code == 'i')
4708 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4709 s390_extract_part (x, HImode, 0));
4710 else if (code == 'j')
4711 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4712 s390_extract_part (x, HImode, -1));
4713 else if (code == 'k')
4714 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4715 s390_extract_part (x, SImode, 0));
4716 else if (code == 'm')
4717 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4718 s390_extract_part (x, SImode, -1));
4719 else if (code == 'o')
4720 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4721 else
4722 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4723 break;
4724
4725 case CONST_DOUBLE:
4726 gcc_assert (GET_MODE (x) == VOIDmode);
4727 if (code == 'b')
4728 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4729 else if (code == 'x')
4730 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4731 else if (code == 'h')
4732 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4733 else
4734 gcc_unreachable ();
4735 break;
4736
4737 default:
4738 fatal_insn ("UNKNOWN in print_operand !?", x);
4739 break;
4740 }
4741 }
4742
4743 /* Target hook for assembling integer objects. We need to define it
4744 here to work a round a bug in some versions of GAS, which couldn't
4745 handle values smaller than INT_MIN when printed in decimal. */
4746
4747 static bool
4748 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4749 {
4750 if (size == 8 && aligned_p
4751 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4752 {
4753 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4754 INTVAL (x));
4755 return true;
4756 }
4757 return default_assemble_integer (x, size, aligned_p);
4758 }
4759
4760 /* Returns true if register REGNO is used for forming
4761 a memory address in expression X. */
4762
4763 static bool
4764 reg_used_in_mem_p (int regno, rtx x)
4765 {
4766 enum rtx_code code = GET_CODE (x);
4767 int i, j;
4768 const char *fmt;
4769
4770 if (code == MEM)
4771 {
4772 if (refers_to_regno_p (regno, regno+1,
4773 XEXP (x, 0), 0))
4774 return true;
4775 }
4776 else if (code == SET
4777 && GET_CODE (SET_DEST (x)) == PC)
4778 {
4779 if (refers_to_regno_p (regno, regno+1,
4780 SET_SRC (x), 0))
4781 return true;
4782 }
4783
4784 fmt = GET_RTX_FORMAT (code);
4785 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4786 {
4787 if (fmt[i] == 'e'
4788 && reg_used_in_mem_p (regno, XEXP (x, i)))
4789 return true;
4790
4791 else if (fmt[i] == 'E')
4792 for (j = 0; j < XVECLEN (x, i); j++)
4793 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4794 return true;
4795 }
4796 return false;
4797 }
4798
4799 /* Returns true if expression DEP_RTX sets an address register
4800 used by instruction INSN to address memory. */
4801
4802 static bool
4803 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4804 {
4805 rtx target, pat;
4806
4807 if (GET_CODE (dep_rtx) == INSN)
4808 dep_rtx = PATTERN (dep_rtx);
4809
4810 if (GET_CODE (dep_rtx) == SET)
4811 {
4812 target = SET_DEST (dep_rtx);
4813 if (GET_CODE (target) == STRICT_LOW_PART)
4814 target = XEXP (target, 0);
4815 while (GET_CODE (target) == SUBREG)
4816 target = SUBREG_REG (target);
4817
4818 if (GET_CODE (target) == REG)
4819 {
4820 int regno = REGNO (target);
4821
4822 if (s390_safe_attr_type (insn) == TYPE_LA)
4823 {
4824 pat = PATTERN (insn);
4825 if (GET_CODE (pat) == PARALLEL)
4826 {
4827 gcc_assert (XVECLEN (pat, 0) == 2);
4828 pat = XVECEXP (pat, 0, 0);
4829 }
4830 gcc_assert (GET_CODE (pat) == SET);
4831 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4832 }
4833 else if (get_attr_atype (insn) == ATYPE_AGEN)
4834 return reg_used_in_mem_p (regno, PATTERN (insn));
4835 }
4836 }
4837 return false;
4838 }
4839
4840 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4841
4842 int
4843 s390_agen_dep_p (rtx dep_insn, rtx insn)
4844 {
4845 rtx dep_rtx = PATTERN (dep_insn);
4846 int i;
4847
4848 if (GET_CODE (dep_rtx) == SET
4849 && addr_generation_dependency_p (dep_rtx, insn))
4850 return 1;
4851 else if (GET_CODE (dep_rtx) == PARALLEL)
4852 {
4853 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4854 {
4855 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4856 return 1;
4857 }
4858 }
4859 return 0;
4860 }
4861
4862 /* A C statement (sans semicolon) to update the integer scheduling priority
4863 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4864 reduce the priority to execute INSN later. Do not define this macro if
4865 you do not need to adjust the scheduling priorities of insns.
4866
4867 A STD instruction should be scheduled earlier,
4868 in order to use the bypass. */
4869
4870 static int
4871 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4872 {
4873 if (! INSN_P (insn))
4874 return priority;
4875
4876 if (s390_tune != PROCESSOR_2084_Z990
4877 && s390_tune != PROCESSOR_2094_Z9_109)
4878 return priority;
4879
4880 switch (s390_safe_attr_type (insn))
4881 {
4882 case TYPE_FSTOREDF:
4883 case TYPE_FSTORESF:
4884 priority = priority << 3;
4885 break;
4886 case TYPE_STORE:
4887 case TYPE_STM:
4888 priority = priority << 1;
4889 break;
4890 default:
4891 break;
4892 }
4893 return priority;
4894 }
4895
4896 /* The number of instructions that can be issued per cycle. */
4897
4898 static int
4899 s390_issue_rate (void)
4900 {
4901 if (s390_tune == PROCESSOR_2084_Z990
4902 || s390_tune == PROCESSOR_2094_Z9_109)
4903 return 3;
4904 return 1;
4905 }
4906
4907 static int
4908 s390_first_cycle_multipass_dfa_lookahead (void)
4909 {
4910 return 4;
4911 }
4912
4913
4914 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4915 Fix up MEMs as required. */
4916
4917 static void
4918 annotate_constant_pool_refs (rtx *x)
4919 {
4920 int i, j;
4921 const char *fmt;
4922
4923 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4924 || !CONSTANT_POOL_ADDRESS_P (*x));
4925
4926 /* Literal pool references can only occur inside a MEM ... */
4927 if (GET_CODE (*x) == MEM)
4928 {
4929 rtx memref = XEXP (*x, 0);
4930
4931 if (GET_CODE (memref) == SYMBOL_REF
4932 && CONSTANT_POOL_ADDRESS_P (memref))
4933 {
4934 rtx base = cfun->machine->base_reg;
4935 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4936 UNSPEC_LTREF);
4937
4938 *x = replace_equiv_address (*x, addr);
4939 return;
4940 }
4941
4942 if (GET_CODE (memref) == CONST
4943 && GET_CODE (XEXP (memref, 0)) == PLUS
4944 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4945 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4946 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4947 {
4948 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4949 rtx sym = XEXP (XEXP (memref, 0), 0);
4950 rtx base = cfun->machine->base_reg;
4951 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4952 UNSPEC_LTREF);
4953
4954 *x = replace_equiv_address (*x, plus_constant (addr, off));
4955 return;
4956 }
4957 }
4958
4959 /* ... or a load-address type pattern. */
4960 if (GET_CODE (*x) == SET)
4961 {
4962 rtx addrref = SET_SRC (*x);
4963
4964 if (GET_CODE (addrref) == SYMBOL_REF
4965 && CONSTANT_POOL_ADDRESS_P (addrref))
4966 {
4967 rtx base = cfun->machine->base_reg;
4968 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4969 UNSPEC_LTREF);
4970
4971 SET_SRC (*x) = addr;
4972 return;
4973 }
4974
4975 if (GET_CODE (addrref) == CONST
4976 && GET_CODE (XEXP (addrref, 0)) == PLUS
4977 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4978 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4979 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4980 {
4981 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4982 rtx sym = XEXP (XEXP (addrref, 0), 0);
4983 rtx base = cfun->machine->base_reg;
4984 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4985 UNSPEC_LTREF);
4986
4987 SET_SRC (*x) = plus_constant (addr, off);
4988 return;
4989 }
4990 }
4991
4992 /* Annotate LTREL_BASE as well. */
4993 if (GET_CODE (*x) == UNSPEC
4994 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4995 {
4996 rtx base = cfun->machine->base_reg;
4997 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4998 UNSPEC_LTREL_BASE);
4999 return;
5000 }
5001
5002 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5003 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5004 {
5005 if (fmt[i] == 'e')
5006 {
5007 annotate_constant_pool_refs (&XEXP (*x, i));
5008 }
5009 else if (fmt[i] == 'E')
5010 {
5011 for (j = 0; j < XVECLEN (*x, i); j++)
5012 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5013 }
5014 }
5015 }
5016
5017 /* Split all branches that exceed the maximum distance.
5018 Returns true if this created a new literal pool entry. */
5019
5020 static int
5021 s390_split_branches (void)
5022 {
5023 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5024 int new_literal = 0, ret;
5025 rtx insn, pat, tmp, target;
5026 rtx *label;
5027
5028 /* We need correct insn addresses. */
5029
5030 shorten_branches (get_insns ());
5031
5032 /* Find all branches that exceed 64KB, and split them. */
5033
5034 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5035 {
5036 if (GET_CODE (insn) != JUMP_INSN)
5037 continue;
5038
5039 pat = PATTERN (insn);
5040 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5041 pat = XVECEXP (pat, 0, 0);
5042 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5043 continue;
5044
5045 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5046 {
5047 label = &SET_SRC (pat);
5048 }
5049 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5050 {
5051 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5052 label = &XEXP (SET_SRC (pat), 1);
5053 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5054 label = &XEXP (SET_SRC (pat), 2);
5055 else
5056 continue;
5057 }
5058 else
5059 continue;
5060
5061 if (get_attr_length (insn) <= 4)
5062 continue;
5063
5064 /* We are going to use the return register as scratch register,
5065 make sure it will be saved/restored by the prologue/epilogue. */
5066 cfun_frame_layout.save_return_addr_p = 1;
5067
5068 if (!flag_pic)
5069 {
5070 new_literal = 1;
5071 tmp = force_const_mem (Pmode, *label);
5072 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5073 INSN_ADDRESSES_NEW (tmp, -1);
5074 annotate_constant_pool_refs (&PATTERN (tmp));
5075
5076 target = temp_reg;
5077 }
5078 else
5079 {
5080 new_literal = 1;
5081 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5082 UNSPEC_LTREL_OFFSET);
5083 target = gen_rtx_CONST (Pmode, target);
5084 target = force_const_mem (Pmode, target);
5085 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5086 INSN_ADDRESSES_NEW (tmp, -1);
5087 annotate_constant_pool_refs (&PATTERN (tmp));
5088
5089 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5090 cfun->machine->base_reg),
5091 UNSPEC_LTREL_BASE);
5092 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5093 }
5094
5095 ret = validate_change (insn, label, target, 0);
5096 gcc_assert (ret);
5097 }
5098
5099 return new_literal;
5100 }
5101
5102
5103 /* Find an annotated literal pool symbol referenced in RTX X,
5104 and store it at REF. Will abort if X contains references to
5105 more than one such pool symbol; multiple references to the same
5106 symbol are allowed, however.
5107
5108 The rtx pointed to by REF must be initialized to NULL_RTX
5109 by the caller before calling this routine. */
5110
5111 static void
5112 find_constant_pool_ref (rtx x, rtx *ref)
5113 {
5114 int i, j;
5115 const char *fmt;
5116
5117 /* Ignore LTREL_BASE references. */
5118 if (GET_CODE (x) == UNSPEC
5119 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5120 return;
5121 /* Likewise POOL_ENTRY insns. */
5122 if (GET_CODE (x) == UNSPEC_VOLATILE
5123 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5124 return;
5125
5126 gcc_assert (GET_CODE (x) != SYMBOL_REF
5127 || !CONSTANT_POOL_ADDRESS_P (x));
5128
5129 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5130 {
5131 rtx sym = XVECEXP (x, 0, 0);
5132 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5133 && CONSTANT_POOL_ADDRESS_P (sym));
5134
5135 if (*ref == NULL_RTX)
5136 *ref = sym;
5137 else
5138 gcc_assert (*ref == sym);
5139
5140 return;
5141 }
5142
5143 fmt = GET_RTX_FORMAT (GET_CODE (x));
5144 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5145 {
5146 if (fmt[i] == 'e')
5147 {
5148 find_constant_pool_ref (XEXP (x, i), ref);
5149 }
5150 else if (fmt[i] == 'E')
5151 {
5152 for (j = 0; j < XVECLEN (x, i); j++)
5153 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5154 }
5155 }
5156 }
5157
5158 /* Replace every reference to the annotated literal pool
5159 symbol REF in X by its base plus OFFSET. */
5160
5161 static void
5162 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5163 {
5164 int i, j;
5165 const char *fmt;
5166
5167 gcc_assert (*x != ref);
5168
5169 if (GET_CODE (*x) == UNSPEC
5170 && XINT (*x, 1) == UNSPEC_LTREF
5171 && XVECEXP (*x, 0, 0) == ref)
5172 {
5173 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5174 return;
5175 }
5176
5177 if (GET_CODE (*x) == PLUS
5178 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5179 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5180 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5181 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5182 {
5183 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5184 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5185 return;
5186 }
5187
5188 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5189 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5190 {
5191 if (fmt[i] == 'e')
5192 {
5193 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5194 }
5195 else if (fmt[i] == 'E')
5196 {
5197 for (j = 0; j < XVECLEN (*x, i); j++)
5198 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5199 }
5200 }
5201 }
5202
5203 /* Check whether X contains an UNSPEC_LTREL_BASE.
5204 Return its constant pool symbol if found, NULL_RTX otherwise. */
5205
5206 static rtx
5207 find_ltrel_base (rtx x)
5208 {
5209 int i, j;
5210 const char *fmt;
5211
5212 if (GET_CODE (x) == UNSPEC
5213 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5214 return XVECEXP (x, 0, 0);
5215
5216 fmt = GET_RTX_FORMAT (GET_CODE (x));
5217 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5218 {
5219 if (fmt[i] == 'e')
5220 {
5221 rtx fnd = find_ltrel_base (XEXP (x, i));
5222 if (fnd)
5223 return fnd;
5224 }
5225 else if (fmt[i] == 'E')
5226 {
5227 for (j = 0; j < XVECLEN (x, i); j++)
5228 {
5229 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5230 if (fnd)
5231 return fnd;
5232 }
5233 }
5234 }
5235
5236 return NULL_RTX;
5237 }
5238
5239 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5240
5241 static void
5242 replace_ltrel_base (rtx *x)
5243 {
5244 int i, j;
5245 const char *fmt;
5246
5247 if (GET_CODE (*x) == UNSPEC
5248 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5249 {
5250 *x = XVECEXP (*x, 0, 1);
5251 return;
5252 }
5253
5254 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5255 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5256 {
5257 if (fmt[i] == 'e')
5258 {
5259 replace_ltrel_base (&XEXP (*x, i));
5260 }
5261 else if (fmt[i] == 'E')
5262 {
5263 for (j = 0; j < XVECLEN (*x, i); j++)
5264 replace_ltrel_base (&XVECEXP (*x, i, j));
5265 }
5266 }
5267 }
5268
5269
5270 /* We keep a list of constants which we have to add to internal
5271 constant tables in the middle of large functions. */
5272
5273 #define NR_C_MODES 11
5274 enum machine_mode constant_modes[NR_C_MODES] =
5275 {
5276 TFmode, TImode, TDmode,
5277 DFmode, DImode, DDmode,
5278 SFmode, SImode, SDmode,
5279 HImode,
5280 QImode
5281 };
5282
5283 struct constant
5284 {
5285 struct constant *next;
5286 rtx value;
5287 rtx label;
5288 };
5289
5290 struct constant_pool
5291 {
5292 struct constant_pool *next;
5293 rtx first_insn;
5294 rtx pool_insn;
5295 bitmap insns;
5296
5297 struct constant *constants[NR_C_MODES];
5298 struct constant *execute;
5299 rtx label;
5300 int size;
5301 };
5302
5303 /* Allocate new constant_pool structure. */
5304
5305 static struct constant_pool *
5306 s390_alloc_pool (void)
5307 {
5308 struct constant_pool *pool;
5309 int i;
5310
5311 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5312 pool->next = NULL;
5313 for (i = 0; i < NR_C_MODES; i++)
5314 pool->constants[i] = NULL;
5315
5316 pool->execute = NULL;
5317 pool->label = gen_label_rtx ();
5318 pool->first_insn = NULL_RTX;
5319 pool->pool_insn = NULL_RTX;
5320 pool->insns = BITMAP_ALLOC (NULL);
5321 pool->size = 0;
5322
5323 return pool;
5324 }
5325
5326 /* Create new constant pool covering instructions starting at INSN
5327 and chain it to the end of POOL_LIST. */
5328
5329 static struct constant_pool *
5330 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5331 {
5332 struct constant_pool *pool, **prev;
5333
5334 pool = s390_alloc_pool ();
5335 pool->first_insn = insn;
5336
5337 for (prev = pool_list; *prev; prev = &(*prev)->next)
5338 ;
5339 *prev = pool;
5340
5341 return pool;
5342 }
5343
5344 /* End range of instructions covered by POOL at INSN and emit
5345 placeholder insn representing the pool. */
5346
5347 static void
5348 s390_end_pool (struct constant_pool *pool, rtx insn)
5349 {
5350 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5351
5352 if (!insn)
5353 insn = get_last_insn ();
5354
5355 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5356 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5357 }
5358
5359 /* Add INSN to the list of insns covered by POOL. */
5360
5361 static void
5362 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5363 {
5364 bitmap_set_bit (pool->insns, INSN_UID (insn));
5365 }
5366
5367 /* Return pool out of POOL_LIST that covers INSN. */
5368
5369 static struct constant_pool *
5370 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5371 {
5372 struct constant_pool *pool;
5373
5374 for (pool = pool_list; pool; pool = pool->next)
5375 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5376 break;
5377
5378 return pool;
5379 }
5380
5381 /* Add constant VAL of mode MODE to the constant pool POOL. */
5382
5383 static void
5384 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5385 {
5386 struct constant *c;
5387 int i;
5388
5389 for (i = 0; i < NR_C_MODES; i++)
5390 if (constant_modes[i] == mode)
5391 break;
5392 gcc_assert (i != NR_C_MODES);
5393
5394 for (c = pool->constants[i]; c != NULL; c = c->next)
5395 if (rtx_equal_p (val, c->value))
5396 break;
5397
5398 if (c == NULL)
5399 {
5400 c = (struct constant *) xmalloc (sizeof *c);
5401 c->value = val;
5402 c->label = gen_label_rtx ();
5403 c->next = pool->constants[i];
5404 pool->constants[i] = c;
5405 pool->size += GET_MODE_SIZE (mode);
5406 }
5407 }
5408
5409 /* Find constant VAL of mode MODE in the constant pool POOL.
5410 Return an RTX describing the distance from the start of
5411 the pool to the location of the new constant. */
5412
5413 static rtx
5414 s390_find_constant (struct constant_pool *pool, rtx val,
5415 enum machine_mode mode)
5416 {
5417 struct constant *c;
5418 rtx offset;
5419 int i;
5420
5421 for (i = 0; i < NR_C_MODES; i++)
5422 if (constant_modes[i] == mode)
5423 break;
5424 gcc_assert (i != NR_C_MODES);
5425
5426 for (c = pool->constants[i]; c != NULL; c = c->next)
5427 if (rtx_equal_p (val, c->value))
5428 break;
5429
5430 gcc_assert (c);
5431
5432 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5433 gen_rtx_LABEL_REF (Pmode, pool->label));
5434 offset = gen_rtx_CONST (Pmode, offset);
5435 return offset;
5436 }
5437
5438 /* Check whether INSN is an execute. Return the label_ref to its
5439 execute target template if so, NULL_RTX otherwise. */
5440
5441 static rtx
5442 s390_execute_label (rtx insn)
5443 {
5444 if (GET_CODE (insn) == INSN
5445 && GET_CODE (PATTERN (insn)) == PARALLEL
5446 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5447 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5448 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5449
5450 return NULL_RTX;
5451 }
5452
5453 /* Add execute target for INSN to the constant pool POOL. */
5454
5455 static void
5456 s390_add_execute (struct constant_pool *pool, rtx insn)
5457 {
5458 struct constant *c;
5459
5460 for (c = pool->execute; c != NULL; c = c->next)
5461 if (INSN_UID (insn) == INSN_UID (c->value))
5462 break;
5463
5464 if (c == NULL)
5465 {
5466 c = (struct constant *) xmalloc (sizeof *c);
5467 c->value = insn;
5468 c->label = gen_label_rtx ();
5469 c->next = pool->execute;
5470 pool->execute = c;
5471 pool->size += 6;
5472 }
5473 }
5474
5475 /* Find execute target for INSN in the constant pool POOL.
5476 Return an RTX describing the distance from the start of
5477 the pool to the location of the execute target. */
5478
5479 static rtx
5480 s390_find_execute (struct constant_pool *pool, rtx insn)
5481 {
5482 struct constant *c;
5483 rtx offset;
5484
5485 for (c = pool->execute; c != NULL; c = c->next)
5486 if (INSN_UID (insn) == INSN_UID (c->value))
5487 break;
5488
5489 gcc_assert (c);
5490
5491 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5492 gen_rtx_LABEL_REF (Pmode, pool->label));
5493 offset = gen_rtx_CONST (Pmode, offset);
5494 return offset;
5495 }
5496
5497 /* For an execute INSN, extract the execute target template. */
5498
5499 static rtx
5500 s390_execute_target (rtx insn)
5501 {
5502 rtx pattern = PATTERN (insn);
5503 gcc_assert (s390_execute_label (insn));
5504
5505 if (XVECLEN (pattern, 0) == 2)
5506 {
5507 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5508 }
5509 else
5510 {
5511 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5512 int i;
5513
5514 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5515 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5516
5517 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5518 }
5519
5520 return pattern;
5521 }
5522
5523 /* Indicate that INSN cannot be duplicated. This is the case for
5524 execute insns that carry a unique label. */
5525
5526 static bool
5527 s390_cannot_copy_insn_p (rtx insn)
5528 {
5529 rtx label = s390_execute_label (insn);
5530 return label && label != const0_rtx;
5531 }
5532
5533 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5534 do not emit the pool base label. */
5535
5536 static void
5537 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5538 {
5539 struct constant *c;
5540 rtx insn = pool->pool_insn;
5541 int i;
5542
5543 /* Switch to rodata section. */
5544 if (TARGET_CPU_ZARCH)
5545 {
5546 insn = emit_insn_after (gen_pool_section_start (), insn);
5547 INSN_ADDRESSES_NEW (insn, -1);
5548 }
5549
5550 /* Ensure minimum pool alignment. */
5551 if (TARGET_CPU_ZARCH)
5552 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5553 else
5554 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5555 INSN_ADDRESSES_NEW (insn, -1);
5556
5557 /* Emit pool base label. */
5558 if (!remote_label)
5559 {
5560 insn = emit_label_after (pool->label, insn);
5561 INSN_ADDRESSES_NEW (insn, -1);
5562 }
5563
5564 /* Dump constants in descending alignment requirement order,
5565 ensuring proper alignment for every constant. */
5566 for (i = 0; i < NR_C_MODES; i++)
5567 for (c = pool->constants[i]; c; c = c->next)
5568 {
5569 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5570 rtx value = c->value;
5571 if (GET_CODE (value) == CONST
5572 && GET_CODE (XEXP (value, 0)) == UNSPEC
5573 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5574 && XVECLEN (XEXP (value, 0), 0) == 1)
5575 {
5576 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5577 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5578 value = gen_rtx_CONST (VOIDmode, value);
5579 }
5580
5581 insn = emit_label_after (c->label, insn);
5582 INSN_ADDRESSES_NEW (insn, -1);
5583
5584 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5585 gen_rtvec (1, value),
5586 UNSPECV_POOL_ENTRY);
5587 insn = emit_insn_after (value, insn);
5588 INSN_ADDRESSES_NEW (insn, -1);
5589 }
5590
5591 /* Ensure minimum alignment for instructions. */
5592 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5593 INSN_ADDRESSES_NEW (insn, -1);
5594
5595 /* Output in-pool execute template insns. */
5596 for (c = pool->execute; c; c = c->next)
5597 {
5598 insn = emit_label_after (c->label, insn);
5599 INSN_ADDRESSES_NEW (insn, -1);
5600
5601 insn = emit_insn_after (s390_execute_target (c->value), insn);
5602 INSN_ADDRESSES_NEW (insn, -1);
5603 }
5604
5605 /* Switch back to previous section. */
5606 if (TARGET_CPU_ZARCH)
5607 {
5608 insn = emit_insn_after (gen_pool_section_end (), insn);
5609 INSN_ADDRESSES_NEW (insn, -1);
5610 }
5611
5612 insn = emit_barrier_after (insn);
5613 INSN_ADDRESSES_NEW (insn, -1);
5614
5615 /* Remove placeholder insn. */
5616 remove_insn (pool->pool_insn);
5617 }
5618
5619 /* Free all memory used by POOL. */
5620
5621 static void
5622 s390_free_pool (struct constant_pool *pool)
5623 {
5624 struct constant *c, *next;
5625 int i;
5626
5627 for (i = 0; i < NR_C_MODES; i++)
5628 for (c = pool->constants[i]; c; c = next)
5629 {
5630 next = c->next;
5631 free (c);
5632 }
5633
5634 for (c = pool->execute; c; c = next)
5635 {
5636 next = c->next;
5637 free (c);
5638 }
5639
5640 BITMAP_FREE (pool->insns);
5641 free (pool);
5642 }
5643
5644
5645 /* Collect main literal pool. Return NULL on overflow. */
5646
5647 static struct constant_pool *
5648 s390_mainpool_start (void)
5649 {
5650 struct constant_pool *pool;
5651 rtx insn;
5652
5653 pool = s390_alloc_pool ();
5654
5655 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5656 {
5657 if (GET_CODE (insn) == INSN
5658 && GET_CODE (PATTERN (insn)) == SET
5659 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5660 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5661 {
5662 gcc_assert (!pool->pool_insn);
5663 pool->pool_insn = insn;
5664 }
5665
5666 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5667 {
5668 s390_add_execute (pool, insn);
5669 }
5670 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5671 {
5672 rtx pool_ref = NULL_RTX;
5673 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5674 if (pool_ref)
5675 {
5676 rtx constant = get_pool_constant (pool_ref);
5677 enum machine_mode mode = get_pool_mode (pool_ref);
5678 s390_add_constant (pool, constant, mode);
5679 }
5680 }
5681 }
5682
5683 gcc_assert (pool->pool_insn || pool->size == 0);
5684
5685 if (pool->size >= 4096)
5686 {
5687 /* We're going to chunkify the pool, so remove the main
5688 pool placeholder insn. */
5689 remove_insn (pool->pool_insn);
5690
5691 s390_free_pool (pool);
5692 pool = NULL;
5693 }
5694
5695 return pool;
5696 }
5697
5698 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5699 Modify the current function to output the pool constants as well as
5700 the pool register setup instruction. */
5701
5702 static void
5703 s390_mainpool_finish (struct constant_pool *pool)
5704 {
5705 rtx base_reg = cfun->machine->base_reg;
5706 rtx insn;
5707
5708 /* If the pool is empty, we're done. */
5709 if (pool->size == 0)
5710 {
5711 /* We don't actually need a base register after all. */
5712 cfun->machine->base_reg = NULL_RTX;
5713
5714 if (pool->pool_insn)
5715 remove_insn (pool->pool_insn);
5716 s390_free_pool (pool);
5717 return;
5718 }
5719
5720 /* We need correct insn addresses. */
5721 shorten_branches (get_insns ());
5722
5723 /* On zSeries, we use a LARL to load the pool register. The pool is
5724 located in the .rodata section, so we emit it after the function. */
5725 if (TARGET_CPU_ZARCH)
5726 {
5727 insn = gen_main_base_64 (base_reg, pool->label);
5728 insn = emit_insn_after (insn, pool->pool_insn);
5729 INSN_ADDRESSES_NEW (insn, -1);
5730 remove_insn (pool->pool_insn);
5731
5732 insn = get_last_insn ();
5733 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5734 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5735
5736 s390_dump_pool (pool, 0);
5737 }
5738
5739 /* On S/390, if the total size of the function's code plus literal pool
5740 does not exceed 4096 bytes, we use BASR to set up a function base
5741 pointer, and emit the literal pool at the end of the function. */
5742 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5743 + pool->size + 8 /* alignment slop */ < 4096)
5744 {
5745 insn = gen_main_base_31_small (base_reg, pool->label);
5746 insn = emit_insn_after (insn, pool->pool_insn);
5747 INSN_ADDRESSES_NEW (insn, -1);
5748 remove_insn (pool->pool_insn);
5749
5750 insn = emit_label_after (pool->label, insn);
5751 INSN_ADDRESSES_NEW (insn, -1);
5752
5753 insn = get_last_insn ();
5754 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5755 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5756
5757 s390_dump_pool (pool, 1);
5758 }
5759
5760 /* Otherwise, we emit an inline literal pool and use BASR to branch
5761 over it, setting up the pool register at the same time. */
5762 else
5763 {
5764 rtx pool_end = gen_label_rtx ();
5765
5766 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5767 insn = emit_insn_after (insn, pool->pool_insn);
5768 INSN_ADDRESSES_NEW (insn, -1);
5769 remove_insn (pool->pool_insn);
5770
5771 insn = emit_label_after (pool->label, insn);
5772 INSN_ADDRESSES_NEW (insn, -1);
5773
5774 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5775 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5776
5777 insn = emit_label_after (pool_end, pool->pool_insn);
5778 INSN_ADDRESSES_NEW (insn, -1);
5779
5780 s390_dump_pool (pool, 1);
5781 }
5782
5783
5784 /* Replace all literal pool references. */
5785
5786 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5787 {
5788 if (INSN_P (insn))
5789 replace_ltrel_base (&PATTERN (insn));
5790
5791 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5792 {
5793 rtx addr, pool_ref = NULL_RTX;
5794 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5795 if (pool_ref)
5796 {
5797 if (s390_execute_label (insn))
5798 addr = s390_find_execute (pool, insn);
5799 else
5800 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5801 get_pool_mode (pool_ref));
5802
5803 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5804 INSN_CODE (insn) = -1;
5805 }
5806 }
5807 }
5808
5809
5810 /* Free the pool. */
5811 s390_free_pool (pool);
5812 }
5813
5814 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5815 We have decided we cannot use this pool, so revert all changes
5816 to the current function that were done by s390_mainpool_start. */
5817 static void
5818 s390_mainpool_cancel (struct constant_pool *pool)
5819 {
5820 /* We didn't actually change the instruction stream, so simply
5821 free the pool memory. */
5822 s390_free_pool (pool);
5823 }
5824
5825
5826 /* Chunkify the literal pool. */
5827
5828 #define S390_POOL_CHUNK_MIN 0xc00
5829 #define S390_POOL_CHUNK_MAX 0xe00
5830
5831 static struct constant_pool *
5832 s390_chunkify_start (void)
5833 {
5834 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5835 int extra_size = 0;
5836 bitmap far_labels;
5837 rtx pending_ltrel = NULL_RTX;
5838 rtx insn;
5839
5840 rtx (*gen_reload_base) (rtx, rtx) =
5841 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5842
5843
5844 /* We need correct insn addresses. */
5845
5846 shorten_branches (get_insns ());
5847
5848 /* Scan all insns and move literals to pool chunks. */
5849
5850 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5851 {
5852 /* Check for pending LTREL_BASE. */
5853 if (INSN_P (insn))
5854 {
5855 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5856 if (ltrel_base)
5857 {
5858 gcc_assert (ltrel_base == pending_ltrel);
5859 pending_ltrel = NULL_RTX;
5860 }
5861 }
5862
5863 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5864 {
5865 if (!curr_pool)
5866 curr_pool = s390_start_pool (&pool_list, insn);
5867
5868 s390_add_execute (curr_pool, insn);
5869 s390_add_pool_insn (curr_pool, insn);
5870 }
5871 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5872 {
5873 rtx pool_ref = NULL_RTX;
5874 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5875 if (pool_ref)
5876 {
5877 rtx constant = get_pool_constant (pool_ref);
5878 enum machine_mode mode = get_pool_mode (pool_ref);
5879
5880 if (!curr_pool)
5881 curr_pool = s390_start_pool (&pool_list, insn);
5882
5883 s390_add_constant (curr_pool, constant, mode);
5884 s390_add_pool_insn (curr_pool, insn);
5885
5886 /* Don't split the pool chunk between a LTREL_OFFSET load
5887 and the corresponding LTREL_BASE. */
5888 if (GET_CODE (constant) == CONST
5889 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5890 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5891 {
5892 gcc_assert (!pending_ltrel);
5893 pending_ltrel = pool_ref;
5894 }
5895 }
5896 }
5897
5898 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5899 {
5900 if (curr_pool)
5901 s390_add_pool_insn (curr_pool, insn);
5902 /* An LTREL_BASE must follow within the same basic block. */
5903 gcc_assert (!pending_ltrel);
5904 }
5905
5906 if (!curr_pool
5907 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5908 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5909 continue;
5910
5911 if (TARGET_CPU_ZARCH)
5912 {
5913 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5914 continue;
5915
5916 s390_end_pool (curr_pool, NULL_RTX);
5917 curr_pool = NULL;
5918 }
5919 else
5920 {
5921 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5922 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5923 + extra_size;
5924
5925 /* We will later have to insert base register reload insns.
5926 Those will have an effect on code size, which we need to
5927 consider here. This calculation makes rather pessimistic
5928 worst-case assumptions. */
5929 if (GET_CODE (insn) == CODE_LABEL)
5930 extra_size += 6;
5931
5932 if (chunk_size < S390_POOL_CHUNK_MIN
5933 && curr_pool->size < S390_POOL_CHUNK_MIN)
5934 continue;
5935
5936 /* Pool chunks can only be inserted after BARRIERs ... */
5937 if (GET_CODE (insn) == BARRIER)
5938 {
5939 s390_end_pool (curr_pool, insn);
5940 curr_pool = NULL;
5941 extra_size = 0;
5942 }
5943
5944 /* ... so if we don't find one in time, create one. */
5945 else if ((chunk_size > S390_POOL_CHUNK_MAX
5946 || curr_pool->size > S390_POOL_CHUNK_MAX))
5947 {
5948 rtx label, jump, barrier;
5949
5950 /* We can insert the barrier only after a 'real' insn. */
5951 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5952 continue;
5953 if (get_attr_length (insn) == 0)
5954 continue;
5955
5956 /* Don't separate LTREL_BASE from the corresponding
5957 LTREL_OFFSET load. */
5958 if (pending_ltrel)
5959 continue;
5960
5961 label = gen_label_rtx ();
5962 jump = emit_jump_insn_after (gen_jump (label), insn);
5963 barrier = emit_barrier_after (jump);
5964 insn = emit_label_after (label, barrier);
5965 JUMP_LABEL (jump) = label;
5966 LABEL_NUSES (label) = 1;
5967
5968 INSN_ADDRESSES_NEW (jump, -1);
5969 INSN_ADDRESSES_NEW (barrier, -1);
5970 INSN_ADDRESSES_NEW (insn, -1);
5971
5972 s390_end_pool (curr_pool, barrier);
5973 curr_pool = NULL;
5974 extra_size = 0;
5975 }
5976 }
5977 }
5978
5979 if (curr_pool)
5980 s390_end_pool (curr_pool, NULL_RTX);
5981 gcc_assert (!pending_ltrel);
5982
5983 /* Find all labels that are branched into
5984 from an insn belonging to a different chunk. */
5985
5986 far_labels = BITMAP_ALLOC (NULL);
5987
5988 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5989 {
5990 /* Labels marked with LABEL_PRESERVE_P can be target
5991 of non-local jumps, so we have to mark them.
5992 The same holds for named labels.
5993
5994 Don't do that, however, if it is the label before
5995 a jump table. */
5996
5997 if (GET_CODE (insn) == CODE_LABEL
5998 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5999 {
6000 rtx vec_insn = next_real_insn (insn);
6001 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6002 PATTERN (vec_insn) : NULL_RTX;
6003 if (!vec_pat
6004 || !(GET_CODE (vec_pat) == ADDR_VEC
6005 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6006 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6007 }
6008
6009 /* If we have a direct jump (conditional or unconditional)
6010 or a casesi jump, check all potential targets. */
6011 else if (GET_CODE (insn) == JUMP_INSN)
6012 {
6013 rtx pat = PATTERN (insn);
6014 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6015 pat = XVECEXP (pat, 0, 0);
6016
6017 if (GET_CODE (pat) == SET)
6018 {
6019 rtx label = JUMP_LABEL (insn);
6020 if (label)
6021 {
6022 if (s390_find_pool (pool_list, label)
6023 != s390_find_pool (pool_list, insn))
6024 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6025 }
6026 }
6027 else if (GET_CODE (pat) == PARALLEL
6028 && XVECLEN (pat, 0) == 2
6029 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6030 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6031 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6032 {
6033 /* Find the jump table used by this casesi jump. */
6034 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6035 rtx vec_insn = next_real_insn (vec_label);
6036 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6037 PATTERN (vec_insn) : NULL_RTX;
6038 if (vec_pat
6039 && (GET_CODE (vec_pat) == ADDR_VEC
6040 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6041 {
6042 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6043
6044 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6045 {
6046 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6047
6048 if (s390_find_pool (pool_list, label)
6049 != s390_find_pool (pool_list, insn))
6050 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6051 }
6052 }
6053 }
6054 }
6055 }
6056
6057 /* Insert base register reload insns before every pool. */
6058
6059 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6060 {
6061 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6062 curr_pool->label);
6063 rtx insn = curr_pool->first_insn;
6064 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6065 }
6066
6067 /* Insert base register reload insns at every far label. */
6068
6069 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6070 if (GET_CODE (insn) == CODE_LABEL
6071 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6072 {
6073 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6074 if (pool)
6075 {
6076 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6077 pool->label);
6078 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6079 }
6080 }
6081
6082
6083 BITMAP_FREE (far_labels);
6084
6085
6086 /* Recompute insn addresses. */
6087
6088 init_insn_lengths ();
6089 shorten_branches (get_insns ());
6090
6091 return pool_list;
6092 }
6093
6094 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6095 After we have decided to use this list, finish implementing
6096 all changes to the current function as required. */
6097
6098 static void
6099 s390_chunkify_finish (struct constant_pool *pool_list)
6100 {
6101 struct constant_pool *curr_pool = NULL;
6102 rtx insn;
6103
6104
6105 /* Replace all literal pool references. */
6106
6107 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6108 {
6109 if (INSN_P (insn))
6110 replace_ltrel_base (&PATTERN (insn));
6111
6112 curr_pool = s390_find_pool (pool_list, insn);
6113 if (!curr_pool)
6114 continue;
6115
6116 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6117 {
6118 rtx addr, pool_ref = NULL_RTX;
6119 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6120 if (pool_ref)
6121 {
6122 if (s390_execute_label (insn))
6123 addr = s390_find_execute (curr_pool, insn);
6124 else
6125 addr = s390_find_constant (curr_pool,
6126 get_pool_constant (pool_ref),
6127 get_pool_mode (pool_ref));
6128
6129 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6130 INSN_CODE (insn) = -1;
6131 }
6132 }
6133 }
6134
6135 /* Dump out all literal pools. */
6136
6137 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6138 s390_dump_pool (curr_pool, 0);
6139
6140 /* Free pool list. */
6141
6142 while (pool_list)
6143 {
6144 struct constant_pool *next = pool_list->next;
6145 s390_free_pool (pool_list);
6146 pool_list = next;
6147 }
6148 }
6149
6150 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6151 We have decided we cannot use this list, so revert all changes
6152 to the current function that were done by s390_chunkify_start. */
6153
6154 static void
6155 s390_chunkify_cancel (struct constant_pool *pool_list)
6156 {
6157 struct constant_pool *curr_pool = NULL;
6158 rtx insn;
6159
6160 /* Remove all pool placeholder insns. */
6161
6162 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6163 {
6164 /* Did we insert an extra barrier? Remove it. */
6165 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6166 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6167 rtx label = NEXT_INSN (curr_pool->pool_insn);
6168
6169 if (jump && GET_CODE (jump) == JUMP_INSN
6170 && barrier && GET_CODE (barrier) == BARRIER
6171 && label && GET_CODE (label) == CODE_LABEL
6172 && GET_CODE (PATTERN (jump)) == SET
6173 && SET_DEST (PATTERN (jump)) == pc_rtx
6174 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6175 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6176 {
6177 remove_insn (jump);
6178 remove_insn (barrier);
6179 remove_insn (label);
6180 }
6181
6182 remove_insn (curr_pool->pool_insn);
6183 }
6184
6185 /* Remove all base register reload insns. */
6186
6187 for (insn = get_insns (); insn; )
6188 {
6189 rtx next_insn = NEXT_INSN (insn);
6190
6191 if (GET_CODE (insn) == INSN
6192 && GET_CODE (PATTERN (insn)) == SET
6193 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6194 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6195 remove_insn (insn);
6196
6197 insn = next_insn;
6198 }
6199
6200 /* Free pool list. */
6201
6202 while (pool_list)
6203 {
6204 struct constant_pool *next = pool_list->next;
6205 s390_free_pool (pool_list);
6206 pool_list = next;
6207 }
6208 }
6209
6210
6211 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6212
6213 void
6214 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6215 {
6216 REAL_VALUE_TYPE r;
6217
6218 switch (GET_MODE_CLASS (mode))
6219 {
6220 case MODE_FLOAT:
6221 case MODE_DECIMAL_FLOAT:
6222 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6223
6224 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6225 assemble_real (r, mode, align);
6226 break;
6227
6228 case MODE_INT:
6229 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6230 break;
6231
6232 default:
6233 gcc_unreachable ();
6234 }
6235 }
6236
6237
6238 /* Return an RTL expression representing the value of the return address
6239 for the frame COUNT steps up from the current frame. FRAME is the
6240 frame pointer of that frame. */
6241
6242 rtx
6243 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6244 {
6245 int offset;
6246 rtx addr;
6247
6248 /* Without backchain, we fail for all but the current frame. */
6249
6250 if (!TARGET_BACKCHAIN && count > 0)
6251 return NULL_RTX;
6252
6253 /* For the current frame, we need to make sure the initial
6254 value of RETURN_REGNUM is actually saved. */
6255
6256 if (count == 0)
6257 {
6258 /* On non-z architectures branch splitting could overwrite r14. */
6259 if (TARGET_CPU_ZARCH)
6260 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6261 else
6262 {
6263 cfun_frame_layout.save_return_addr_p = true;
6264 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6265 }
6266 }
6267
6268 if (TARGET_PACKED_STACK)
6269 offset = -2 * UNITS_PER_WORD;
6270 else
6271 offset = RETURN_REGNUM * UNITS_PER_WORD;
6272
6273 addr = plus_constant (frame, offset);
6274 addr = memory_address (Pmode, addr);
6275 return gen_rtx_MEM (Pmode, addr);
6276 }
6277
6278 /* Return an RTL expression representing the back chain stored in
6279 the current stack frame. */
6280
6281 rtx
6282 s390_back_chain_rtx (void)
6283 {
6284 rtx chain;
6285
6286 gcc_assert (TARGET_BACKCHAIN);
6287
6288 if (TARGET_PACKED_STACK)
6289 chain = plus_constant (stack_pointer_rtx,
6290 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6291 else
6292 chain = stack_pointer_rtx;
6293
6294 chain = gen_rtx_MEM (Pmode, chain);
6295 return chain;
6296 }
6297
6298 /* Find first call clobbered register unused in a function.
6299 This could be used as base register in a leaf function
6300 or for holding the return address before epilogue. */
6301
6302 static int
6303 find_unused_clobbered_reg (void)
6304 {
6305 int i;
6306 for (i = 0; i < 6; i++)
6307 if (!regs_ever_live[i])
6308 return i;
6309 return 0;
6310 }
6311
6312
6313 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6314 clobbered hard regs in SETREG. */
6315
6316 static void
6317 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6318 {
6319 int *regs_ever_clobbered = (int *)data;
6320 unsigned int i, regno;
6321 enum machine_mode mode = GET_MODE (setreg);
6322
6323 if (GET_CODE (setreg) == SUBREG)
6324 {
6325 rtx inner = SUBREG_REG (setreg);
6326 if (!GENERAL_REG_P (inner))
6327 return;
6328 regno = subreg_regno (setreg);
6329 }
6330 else if (GENERAL_REG_P (setreg))
6331 regno = REGNO (setreg);
6332 else
6333 return;
6334
6335 for (i = regno;
6336 i < regno + HARD_REGNO_NREGS (regno, mode);
6337 i++)
6338 regs_ever_clobbered[i] = 1;
6339 }
6340
6341 /* Walks through all basic blocks of the current function looking
6342 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6343 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6344 each of those regs. */
6345
6346 static void
6347 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6348 {
6349 basic_block cur_bb;
6350 rtx cur_insn;
6351 unsigned int i;
6352
6353 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6354
6355 /* For non-leaf functions we have to consider all call clobbered regs to be
6356 clobbered. */
6357 if (!current_function_is_leaf)
6358 {
6359 for (i = 0; i < 16; i++)
6360 regs_ever_clobbered[i] = call_really_used_regs[i];
6361 }
6362
6363 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6364 this work is done by liveness analysis (mark_regs_live_at_end).
6365 Special care is needed for functions containing landing pads. Landing pads
6366 may use the eh registers, but the code which sets these registers is not
6367 contained in that function. Hence s390_regs_ever_clobbered is not able to
6368 deal with this automatically. */
6369 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6370 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6371 if (current_function_calls_eh_return
6372 || (cfun->machine->has_landing_pad_p
6373 && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6374 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6375
6376 /* For nonlocal gotos all call-saved registers have to be saved.
6377 This flag is also set for the unwinding code in libgcc.
6378 See expand_builtin_unwind_init. For regs_ever_live this is done by
6379 reload. */
6380 if (current_function_has_nonlocal_label)
6381 for (i = 0; i < 16; i++)
6382 if (!call_really_used_regs[i])
6383 regs_ever_clobbered[i] = 1;
6384
6385 FOR_EACH_BB (cur_bb)
6386 {
6387 FOR_BB_INSNS (cur_bb, cur_insn)
6388 {
6389 if (INSN_P (cur_insn))
6390 note_stores (PATTERN (cur_insn),
6391 s390_reg_clobbered_rtx,
6392 regs_ever_clobbered);
6393 }
6394 }
6395 }
6396
6397 /* Determine the frame area which actually has to be accessed
6398 in the function epilogue. The values are stored at the
6399 given pointers AREA_BOTTOM (address of the lowest used stack
6400 address) and AREA_TOP (address of the first item which does
6401 not belong to the stack frame). */
6402
6403 static void
6404 s390_frame_area (int *area_bottom, int *area_top)
6405 {
6406 int b, t;
6407 int i;
6408
6409 b = INT_MAX;
6410 t = INT_MIN;
6411
6412 if (cfun_frame_layout.first_restore_gpr != -1)
6413 {
6414 b = (cfun_frame_layout.gprs_offset
6415 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6416 t = b + (cfun_frame_layout.last_restore_gpr
6417 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6418 }
6419
6420 if (TARGET_64BIT && cfun_save_high_fprs_p)
6421 {
6422 b = MIN (b, cfun_frame_layout.f8_offset);
6423 t = MAX (t, (cfun_frame_layout.f8_offset
6424 + cfun_frame_layout.high_fprs * 8));
6425 }
6426
6427 if (!TARGET_64BIT)
6428 for (i = 2; i < 4; i++)
6429 if (cfun_fpr_bit_p (i))
6430 {
6431 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6432 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6433 }
6434
6435 *area_bottom = b;
6436 *area_top = t;
6437 }
6438
6439 /* Fill cfun->machine with info about register usage of current function.
6440 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6441
6442 static void
6443 s390_register_info (int clobbered_regs[])
6444 {
6445 int i, j;
6446
6447 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6448 cfun_frame_layout.fpr_bitmap = 0;
6449 cfun_frame_layout.high_fprs = 0;
6450 if (TARGET_64BIT)
6451 for (i = 24; i < 32; i++)
6452 if (regs_ever_live[i] && !global_regs[i])
6453 {
6454 cfun_set_fpr_bit (i - 16);
6455 cfun_frame_layout.high_fprs++;
6456 }
6457
6458 /* Find first and last gpr to be saved. We trust regs_ever_live
6459 data, except that we don't save and restore global registers.
6460
6461 Also, all registers with special meaning to the compiler need
6462 to be handled extra. */
6463
6464 s390_regs_ever_clobbered (clobbered_regs);
6465
6466 for (i = 0; i < 16; i++)
6467 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6468
6469 if (frame_pointer_needed)
6470 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6471
6472 if (flag_pic)
6473 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6474 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6475
6476 clobbered_regs[BASE_REGNUM]
6477 |= (cfun->machine->base_reg
6478 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6479
6480 clobbered_regs[RETURN_REGNUM]
6481 |= (!current_function_is_leaf
6482 || TARGET_TPF_PROFILING
6483 || cfun->machine->split_branches_pending_p
6484 || cfun_frame_layout.save_return_addr_p
6485 || current_function_calls_eh_return
6486 || current_function_stdarg);
6487
6488 clobbered_regs[STACK_POINTER_REGNUM]
6489 |= (!current_function_is_leaf
6490 || TARGET_TPF_PROFILING
6491 || cfun_save_high_fprs_p
6492 || get_frame_size () > 0
6493 || current_function_calls_alloca
6494 || current_function_stdarg);
6495
6496 for (i = 6; i < 16; i++)
6497 if (regs_ever_live[i] || clobbered_regs[i])
6498 break;
6499 for (j = 15; j > i; j--)
6500 if (regs_ever_live[j] || clobbered_regs[j])
6501 break;
6502
6503 if (i == 16)
6504 {
6505 /* Nothing to save/restore. */
6506 cfun_frame_layout.first_save_gpr_slot = -1;
6507 cfun_frame_layout.last_save_gpr_slot = -1;
6508 cfun_frame_layout.first_save_gpr = -1;
6509 cfun_frame_layout.first_restore_gpr = -1;
6510 cfun_frame_layout.last_save_gpr = -1;
6511 cfun_frame_layout.last_restore_gpr = -1;
6512 }
6513 else
6514 {
6515 /* Save slots for gprs from i to j. */
6516 cfun_frame_layout.first_save_gpr_slot = i;
6517 cfun_frame_layout.last_save_gpr_slot = j;
6518
6519 for (i = cfun_frame_layout.first_save_gpr_slot;
6520 i < cfun_frame_layout.last_save_gpr_slot + 1;
6521 i++)
6522 if (clobbered_regs[i])
6523 break;
6524
6525 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6526 if (clobbered_regs[j])
6527 break;
6528
6529 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6530 {
6531 /* Nothing to save/restore. */
6532 cfun_frame_layout.first_save_gpr = -1;
6533 cfun_frame_layout.first_restore_gpr = -1;
6534 cfun_frame_layout.last_save_gpr = -1;
6535 cfun_frame_layout.last_restore_gpr = -1;
6536 }
6537 else
6538 {
6539 /* Save / Restore from gpr i to j. */
6540 cfun_frame_layout.first_save_gpr = i;
6541 cfun_frame_layout.first_restore_gpr = i;
6542 cfun_frame_layout.last_save_gpr = j;
6543 cfun_frame_layout.last_restore_gpr = j;
6544 }
6545 }
6546
6547 if (current_function_stdarg)
6548 {
6549 /* Varargs functions need to save gprs 2 to 6. */
6550 if (cfun->va_list_gpr_size
6551 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6552 {
6553 int min_gpr = current_function_args_info.gprs;
6554 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6555 if (max_gpr > GP_ARG_NUM_REG)
6556 max_gpr = GP_ARG_NUM_REG;
6557
6558 if (cfun_frame_layout.first_save_gpr == -1
6559 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6560 {
6561 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6562 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6563 }
6564
6565 if (cfun_frame_layout.last_save_gpr == -1
6566 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6567 {
6568 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6569 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6570 }
6571 }
6572
6573 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6574 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6575 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6576 {
6577 int min_fpr = current_function_args_info.fprs;
6578 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6579 if (max_fpr > FP_ARG_NUM_REG)
6580 max_fpr = FP_ARG_NUM_REG;
6581
6582 /* ??? This is currently required to ensure proper location
6583 of the fpr save slots within the va_list save area. */
6584 if (TARGET_PACKED_STACK)
6585 min_fpr = 0;
6586
6587 for (i = min_fpr; i < max_fpr; i++)
6588 cfun_set_fpr_bit (i);
6589 }
6590 }
6591
6592 if (!TARGET_64BIT)
6593 for (i = 2; i < 4; i++)
6594 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6595 cfun_set_fpr_bit (i);
6596 }
6597
6598 /* Fill cfun->machine with info about frame of current function. */
6599
6600 static void
6601 s390_frame_info (void)
6602 {
6603 int i;
6604
6605 cfun_frame_layout.frame_size = get_frame_size ();
6606 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6607 fatal_error ("total size of local variables exceeds architecture limit");
6608
6609 if (!TARGET_PACKED_STACK)
6610 {
6611 cfun_frame_layout.backchain_offset = 0;
6612 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6613 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6614 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6615 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6616 * UNITS_PER_WORD);
6617 }
6618 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6619 {
6620 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6621 - UNITS_PER_WORD);
6622 cfun_frame_layout.gprs_offset
6623 = (cfun_frame_layout.backchain_offset
6624 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6625 * UNITS_PER_WORD);
6626
6627 if (TARGET_64BIT)
6628 {
6629 cfun_frame_layout.f4_offset
6630 = (cfun_frame_layout.gprs_offset
6631 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6632
6633 cfun_frame_layout.f0_offset
6634 = (cfun_frame_layout.f4_offset
6635 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6636 }
6637 else
6638 {
6639 /* On 31 bit we have to care about alignment of the
6640 floating point regs to provide fastest access. */
6641 cfun_frame_layout.f0_offset
6642 = ((cfun_frame_layout.gprs_offset
6643 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6644 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6645
6646 cfun_frame_layout.f4_offset
6647 = (cfun_frame_layout.f0_offset
6648 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6649 }
6650 }
6651 else /* no backchain */
6652 {
6653 cfun_frame_layout.f4_offset
6654 = (STACK_POINTER_OFFSET
6655 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6656
6657 cfun_frame_layout.f0_offset
6658 = (cfun_frame_layout.f4_offset
6659 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6660
6661 cfun_frame_layout.gprs_offset
6662 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6663 }
6664
6665 if (current_function_is_leaf
6666 && !TARGET_TPF_PROFILING
6667 && cfun_frame_layout.frame_size == 0
6668 && !cfun_save_high_fprs_p
6669 && !current_function_calls_alloca
6670 && !current_function_stdarg)
6671 return;
6672
6673 if (!TARGET_PACKED_STACK)
6674 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6675 + current_function_outgoing_args_size
6676 + cfun_frame_layout.high_fprs * 8);
6677 else
6678 {
6679 if (TARGET_BACKCHAIN)
6680 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6681
6682 /* No alignment trouble here because f8-f15 are only saved under
6683 64 bit. */
6684 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6685 cfun_frame_layout.f4_offset),
6686 cfun_frame_layout.gprs_offset)
6687 - cfun_frame_layout.high_fprs * 8);
6688
6689 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6690
6691 for (i = 0; i < 8; i++)
6692 if (cfun_fpr_bit_p (i))
6693 cfun_frame_layout.frame_size += 8;
6694
6695 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6696
6697 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6698 the frame size to sustain 8 byte alignment of stack frames. */
6699 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6700 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6701 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6702
6703 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6704 }
6705 }
6706
6707 /* Generate frame layout. Fills in register and frame data for the current
6708 function in cfun->machine. This routine can be called multiple times;
6709 it will re-do the complete frame layout every time. */
6710
6711 static void
6712 s390_init_frame_layout (void)
6713 {
6714 HOST_WIDE_INT frame_size;
6715 int base_used;
6716 int clobbered_regs[16];
6717
6718 /* On S/390 machines, we may need to perform branch splitting, which
6719 will require both base and return address register. We have no
6720 choice but to assume we're going to need them until right at the
6721 end of the machine dependent reorg phase. */
6722 if (!TARGET_CPU_ZARCH)
6723 cfun->machine->split_branches_pending_p = true;
6724
6725 do
6726 {
6727 frame_size = cfun_frame_layout.frame_size;
6728
6729 /* Try to predict whether we'll need the base register. */
6730 base_used = cfun->machine->split_branches_pending_p
6731 || current_function_uses_const_pool
6732 || (!DISP_IN_RANGE (-frame_size)
6733 && !CONST_OK_FOR_K (-frame_size));
6734
6735 /* Decide which register to use as literal pool base. In small
6736 leaf functions, try to use an unused call-clobbered register
6737 as base register to avoid save/restore overhead. */
6738 if (!base_used)
6739 cfun->machine->base_reg = NULL_RTX;
6740 else if (current_function_is_leaf && !regs_ever_live[5])
6741 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6742 else
6743 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6744
6745 s390_register_info (clobbered_regs);
6746 s390_frame_info ();
6747 }
6748 while (frame_size != cfun_frame_layout.frame_size);
6749 }
6750
6751 /* Update frame layout. Recompute actual register save data based on
6752 current info and update regs_ever_live for the special registers.
6753 May be called multiple times, but may never cause *more* registers
6754 to be saved than s390_init_frame_layout allocated room for. */
6755
6756 static void
6757 s390_update_frame_layout (void)
6758 {
6759 int clobbered_regs[16];
6760
6761 s390_register_info (clobbered_regs);
6762
6763 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6764 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6765 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6766
6767 if (cfun->machine->base_reg)
6768 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6769 }
6770
6771 /* Return true if it is legal to put a value with MODE into REGNO. */
6772
6773 bool
6774 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
6775 {
6776 switch (REGNO_REG_CLASS (regno))
6777 {
6778 case FP_REGS:
6779 if (REGNO_PAIR_OK (regno, mode))
6780 {
6781 if (mode == SImode || mode == DImode)
6782 return true;
6783
6784 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
6785 return true;
6786 }
6787 break;
6788 case ADDR_REGS:
6789 if (FRAME_REGNO_P (regno) && mode == Pmode)
6790 return true;
6791
6792 /* fallthrough */
6793 case GENERAL_REGS:
6794 if (REGNO_PAIR_OK (regno, mode))
6795 {
6796 if (TARGET_64BIT
6797 || (mode != TFmode && mode != TCmode && mode != TDmode))
6798 return true;
6799 }
6800 break;
6801 case CC_REGS:
6802 if (GET_MODE_CLASS (mode) == MODE_CC)
6803 return true;
6804 break;
6805 case ACCESS_REGS:
6806 if (REGNO_PAIR_OK (regno, mode))
6807 {
6808 if (mode == SImode || mode == Pmode)
6809 return true;
6810 }
6811 break;
6812 default:
6813 return false;
6814 }
6815
6816 return false;
6817 }
6818
6819 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6820
6821 bool
6822 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6823 {
6824 /* Once we've decided upon a register to use as base register, it must
6825 no longer be used for any other purpose. */
6826 if (cfun->machine->base_reg)
6827 if (REGNO (cfun->machine->base_reg) == old_reg
6828 || REGNO (cfun->machine->base_reg) == new_reg)
6829 return false;
6830
6831 return true;
6832 }
6833
6834 /* Maximum number of registers to represent a value of mode MODE
6835 in a register of class CLASS. */
6836
6837 bool
6838 s390_class_max_nregs (enum reg_class class, enum machine_mode mode)
6839 {
6840 switch (class)
6841 {
6842 case FP_REGS:
6843 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6844 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
6845 else
6846 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
6847 case ACCESS_REGS:
6848 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
6849 default:
6850 break;
6851 }
6852 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6853 }
6854
6855 /* Return true if register FROM can be eliminated via register TO. */
6856
6857 bool
6858 s390_can_eliminate (int from, int to)
6859 {
6860 /* On zSeries machines, we have not marked the base register as fixed.
6861 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6862 If a function requires the base register, we say here that this
6863 elimination cannot be performed. This will cause reload to free
6864 up the base register (as if it were fixed). On the other hand,
6865 if the current function does *not* require the base register, we
6866 say here the elimination succeeds, which in turn allows reload
6867 to allocate the base register for any other purpose. */
6868 if (from == BASE_REGNUM && to == BASE_REGNUM)
6869 {
6870 if (TARGET_CPU_ZARCH)
6871 {
6872 s390_init_frame_layout ();
6873 return cfun->machine->base_reg == NULL_RTX;
6874 }
6875
6876 return false;
6877 }
6878
6879 /* Everything else must point into the stack frame. */
6880 gcc_assert (to == STACK_POINTER_REGNUM
6881 || to == HARD_FRAME_POINTER_REGNUM);
6882
6883 gcc_assert (from == FRAME_POINTER_REGNUM
6884 || from == ARG_POINTER_REGNUM
6885 || from == RETURN_ADDRESS_POINTER_REGNUM);
6886
6887 /* Make sure we actually saved the return address. */
6888 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6889 if (!current_function_calls_eh_return
6890 && !current_function_stdarg
6891 && !cfun_frame_layout.save_return_addr_p)
6892 return false;
6893
6894 return true;
6895 }
6896
6897 /* Return offset between register FROM and TO initially after prolog. */
6898
6899 HOST_WIDE_INT
6900 s390_initial_elimination_offset (int from, int to)
6901 {
6902 HOST_WIDE_INT offset;
6903 int index;
6904
6905 /* ??? Why are we called for non-eliminable pairs? */
6906 if (!s390_can_eliminate (from, to))
6907 return 0;
6908
6909 switch (from)
6910 {
6911 case FRAME_POINTER_REGNUM:
6912 offset = (get_frame_size()
6913 + STACK_POINTER_OFFSET
6914 + current_function_outgoing_args_size);
6915 break;
6916
6917 case ARG_POINTER_REGNUM:
6918 s390_init_frame_layout ();
6919 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6920 break;
6921
6922 case RETURN_ADDRESS_POINTER_REGNUM:
6923 s390_init_frame_layout ();
6924 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6925 gcc_assert (index >= 0);
6926 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6927 offset += index * UNITS_PER_WORD;
6928 break;
6929
6930 case BASE_REGNUM:
6931 offset = 0;
6932 break;
6933
6934 default:
6935 gcc_unreachable ();
6936 }
6937
6938 return offset;
6939 }
6940
6941 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6942 to register BASE. Return generated insn. */
6943
6944 static rtx
6945 save_fpr (rtx base, int offset, int regnum)
6946 {
6947 rtx addr;
6948 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6949
6950 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6951 set_mem_alias_set (addr, get_varargs_alias_set ());
6952 else
6953 set_mem_alias_set (addr, get_frame_alias_set ());
6954
6955 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6956 }
6957
6958 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6959 to register BASE. Return generated insn. */
6960
6961 static rtx
6962 restore_fpr (rtx base, int offset, int regnum)
6963 {
6964 rtx addr;
6965 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6966 set_mem_alias_set (addr, get_frame_alias_set ());
6967
6968 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6969 }
6970
6971 /* Generate insn to save registers FIRST to LAST into
6972 the register save area located at offset OFFSET
6973 relative to register BASE. */
6974
6975 static rtx
6976 save_gprs (rtx base, int offset, int first, int last)
6977 {
6978 rtx addr, insn, note;
6979 int i;
6980
6981 addr = plus_constant (base, offset);
6982 addr = gen_rtx_MEM (Pmode, addr);
6983
6984 set_mem_alias_set (addr, get_frame_alias_set ());
6985
6986 /* Special-case single register. */
6987 if (first == last)
6988 {
6989 if (TARGET_64BIT)
6990 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6991 else
6992 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6993
6994 RTX_FRAME_RELATED_P (insn) = 1;
6995 return insn;
6996 }
6997
6998
6999 insn = gen_store_multiple (addr,
7000 gen_rtx_REG (Pmode, first),
7001 GEN_INT (last - first + 1));
7002
7003 if (first <= 6 && current_function_stdarg)
7004 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7005 {
7006 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7007
7008 if (first + i <= 6)
7009 set_mem_alias_set (mem, get_varargs_alias_set ());
7010 }
7011
7012 /* We need to set the FRAME_RELATED flag on all SETs
7013 inside the store-multiple pattern.
7014
7015 However, we must not emit DWARF records for registers 2..5
7016 if they are stored for use by variable arguments ...
7017
7018 ??? Unfortunately, it is not enough to simply not the
7019 FRAME_RELATED flags for those SETs, because the first SET
7020 of the PARALLEL is always treated as if it had the flag
7021 set, even if it does not. Therefore we emit a new pattern
7022 without those registers as REG_FRAME_RELATED_EXPR note. */
7023
7024 if (first >= 6)
7025 {
7026 rtx pat = PATTERN (insn);
7027
7028 for (i = 0; i < XVECLEN (pat, 0); i++)
7029 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
7030 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7031
7032 RTX_FRAME_RELATED_P (insn) = 1;
7033 }
7034 else if (last >= 6)
7035 {
7036 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
7037 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7038 gen_rtx_REG (Pmode, 6),
7039 GEN_INT (last - 6 + 1));
7040 note = PATTERN (note);
7041
7042 REG_NOTES (insn) =
7043 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7044 note, REG_NOTES (insn));
7045
7046 for (i = 0; i < XVECLEN (note, 0); i++)
7047 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
7048 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7049
7050 RTX_FRAME_RELATED_P (insn) = 1;
7051 }
7052
7053 return insn;
7054 }
7055
7056 /* Generate insn to restore registers FIRST to LAST from
7057 the register save area located at offset OFFSET
7058 relative to register BASE. */
7059
7060 static rtx
7061 restore_gprs (rtx base, int offset, int first, int last)
7062 {
7063 rtx addr, insn;
7064
7065 addr = plus_constant (base, offset);
7066 addr = gen_rtx_MEM (Pmode, addr);
7067 set_mem_alias_set (addr, get_frame_alias_set ());
7068
7069 /* Special-case single register. */
7070 if (first == last)
7071 {
7072 if (TARGET_64BIT)
7073 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7074 else
7075 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7076
7077 return insn;
7078 }
7079
7080 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7081 addr,
7082 GEN_INT (last - first + 1));
7083 return insn;
7084 }
7085
7086 /* Return insn sequence to load the GOT register. */
7087
7088 static GTY(()) rtx got_symbol;
7089 rtx
7090 s390_load_got (void)
7091 {
7092 rtx insns;
7093
7094 if (!got_symbol)
7095 {
7096 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7097 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7098 }
7099
7100 start_sequence ();
7101
7102 if (TARGET_CPU_ZARCH)
7103 {
7104 emit_move_insn (pic_offset_table_rtx, got_symbol);
7105 }
7106 else
7107 {
7108 rtx offset;
7109
7110 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7111 UNSPEC_LTREL_OFFSET);
7112 offset = gen_rtx_CONST (Pmode, offset);
7113 offset = force_const_mem (Pmode, offset);
7114
7115 emit_move_insn (pic_offset_table_rtx, offset);
7116
7117 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7118 UNSPEC_LTREL_BASE);
7119 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7120
7121 emit_move_insn (pic_offset_table_rtx, offset);
7122 }
7123
7124 insns = get_insns ();
7125 end_sequence ();
7126 return insns;
7127 }
7128
7129 /* Expand the prologue into a bunch of separate insns. */
7130
7131 void
7132 s390_emit_prologue (void)
7133 {
7134 rtx insn, addr;
7135 rtx temp_reg;
7136 int i;
7137 int offset;
7138 int next_fpr = 0;
7139
7140 /* Complete frame layout. */
7141
7142 s390_update_frame_layout ();
7143
7144 /* Annotate all constant pool references to let the scheduler know
7145 they implicitly use the base register. */
7146
7147 push_topmost_sequence ();
7148
7149 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7150 if (INSN_P (insn))
7151 annotate_constant_pool_refs (&PATTERN (insn));
7152
7153 pop_topmost_sequence ();
7154
7155 /* Choose best register to use for temp use within prologue.
7156 See below for why TPF must use the register 1. */
7157
7158 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7159 && !current_function_is_leaf
7160 && !TARGET_TPF_PROFILING)
7161 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7162 else
7163 temp_reg = gen_rtx_REG (Pmode, 1);
7164
7165 /* Save call saved gprs. */
7166 if (cfun_frame_layout.first_save_gpr != -1)
7167 {
7168 insn = save_gprs (stack_pointer_rtx,
7169 cfun_frame_layout.gprs_offset +
7170 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7171 - cfun_frame_layout.first_save_gpr_slot),
7172 cfun_frame_layout.first_save_gpr,
7173 cfun_frame_layout.last_save_gpr);
7174 emit_insn (insn);
7175 }
7176
7177 /* Dummy insn to mark literal pool slot. */
7178
7179 if (cfun->machine->base_reg)
7180 emit_insn (gen_main_pool (cfun->machine->base_reg));
7181
7182 offset = cfun_frame_layout.f0_offset;
7183
7184 /* Save f0 and f2. */
7185 for (i = 0; i < 2; i++)
7186 {
7187 if (cfun_fpr_bit_p (i))
7188 {
7189 save_fpr (stack_pointer_rtx, offset, i + 16);
7190 offset += 8;
7191 }
7192 else if (!TARGET_PACKED_STACK)
7193 offset += 8;
7194 }
7195
7196 /* Save f4 and f6. */
7197 offset = cfun_frame_layout.f4_offset;
7198 for (i = 2; i < 4; i++)
7199 {
7200 if (cfun_fpr_bit_p (i))
7201 {
7202 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7203 offset += 8;
7204
7205 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7206 therefore are not frame related. */
7207 if (!call_really_used_regs[i + 16])
7208 RTX_FRAME_RELATED_P (insn) = 1;
7209 }
7210 else if (!TARGET_PACKED_STACK)
7211 offset += 8;
7212 }
7213
7214 if (TARGET_PACKED_STACK
7215 && cfun_save_high_fprs_p
7216 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7217 {
7218 offset = (cfun_frame_layout.f8_offset
7219 + (cfun_frame_layout.high_fprs - 1) * 8);
7220
7221 for (i = 15; i > 7 && offset >= 0; i--)
7222 if (cfun_fpr_bit_p (i))
7223 {
7224 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7225
7226 RTX_FRAME_RELATED_P (insn) = 1;
7227 offset -= 8;
7228 }
7229 if (offset >= cfun_frame_layout.f8_offset)
7230 next_fpr = i + 16;
7231 }
7232
7233 if (!TARGET_PACKED_STACK)
7234 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7235
7236 /* Decrement stack pointer. */
7237
7238 if (cfun_frame_layout.frame_size > 0)
7239 {
7240 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7241
7242 if (s390_stack_size)
7243 {
7244 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7245 & ~(s390_stack_guard - 1));
7246 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7247 GEN_INT (stack_check_mask));
7248
7249 if (TARGET_64BIT)
7250 gen_cmpdi (t, const0_rtx);
7251 else
7252 gen_cmpsi (t, const0_rtx);
7253
7254 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7255 gen_rtx_REG (CCmode,
7256 CC_REGNUM),
7257 const0_rtx),
7258 const0_rtx));
7259 }
7260
7261 if (s390_warn_framesize > 0
7262 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7263 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7264 current_function_name (), cfun_frame_layout.frame_size);
7265
7266 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7267 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7268
7269 /* Save incoming stack pointer into temp reg. */
7270 if (TARGET_BACKCHAIN || next_fpr)
7271 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7272
7273 /* Subtract frame size from stack pointer. */
7274
7275 if (DISP_IN_RANGE (INTVAL (frame_off)))
7276 {
7277 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7278 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7279 frame_off));
7280 insn = emit_insn (insn);
7281 }
7282 else
7283 {
7284 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7285 frame_off = force_const_mem (Pmode, frame_off);
7286
7287 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7288 annotate_constant_pool_refs (&PATTERN (insn));
7289 }
7290
7291 RTX_FRAME_RELATED_P (insn) = 1;
7292 REG_NOTES (insn) =
7293 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7294 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7295 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7296 GEN_INT (-cfun_frame_layout.frame_size))),
7297 REG_NOTES (insn));
7298
7299 /* Set backchain. */
7300
7301 if (TARGET_BACKCHAIN)
7302 {
7303 if (cfun_frame_layout.backchain_offset)
7304 addr = gen_rtx_MEM (Pmode,
7305 plus_constant (stack_pointer_rtx,
7306 cfun_frame_layout.backchain_offset));
7307 else
7308 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7309 set_mem_alias_set (addr, get_frame_alias_set ());
7310 insn = emit_insn (gen_move_insn (addr, temp_reg));
7311 }
7312
7313 /* If we support asynchronous exceptions (e.g. for Java),
7314 we need to make sure the backchain pointer is set up
7315 before any possibly trapping memory access. */
7316
7317 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7318 {
7319 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7320 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7321 }
7322 }
7323
7324 /* Save fprs 8 - 15 (64 bit ABI). */
7325
7326 if (cfun_save_high_fprs_p && next_fpr)
7327 {
7328 insn = emit_insn (gen_add2_insn (temp_reg,
7329 GEN_INT (cfun_frame_layout.f8_offset)));
7330
7331 offset = 0;
7332
7333 for (i = 24; i <= next_fpr; i++)
7334 if (cfun_fpr_bit_p (i - 16))
7335 {
7336 rtx addr = plus_constant (stack_pointer_rtx,
7337 cfun_frame_layout.frame_size
7338 + cfun_frame_layout.f8_offset
7339 + offset);
7340
7341 insn = save_fpr (temp_reg, offset, i);
7342 offset += 8;
7343 RTX_FRAME_RELATED_P (insn) = 1;
7344 REG_NOTES (insn) =
7345 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7346 gen_rtx_SET (VOIDmode,
7347 gen_rtx_MEM (DFmode, addr),
7348 gen_rtx_REG (DFmode, i)),
7349 REG_NOTES (insn));
7350 }
7351 }
7352
7353 /* Set frame pointer, if needed. */
7354
7355 if (frame_pointer_needed)
7356 {
7357 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7358 RTX_FRAME_RELATED_P (insn) = 1;
7359 }
7360
7361 /* Set up got pointer, if needed. */
7362
7363 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7364 {
7365 rtx insns = s390_load_got ();
7366
7367 for (insn = insns; insn; insn = NEXT_INSN (insn))
7368 {
7369 annotate_constant_pool_refs (&PATTERN (insn));
7370
7371 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7372 REG_NOTES (insn));
7373 }
7374
7375 emit_insn (insns);
7376 }
7377
7378 if (TARGET_TPF_PROFILING)
7379 {
7380 /* Generate a BAS instruction to serve as a function
7381 entry intercept to facilitate the use of tracing
7382 algorithms located at the branch target. */
7383 emit_insn (gen_prologue_tpf ());
7384
7385 /* Emit a blockage here so that all code
7386 lies between the profiling mechanisms. */
7387 emit_insn (gen_blockage ());
7388 }
7389 }
7390
7391 /* Expand the epilogue into a bunch of separate insns. */
7392
7393 void
7394 s390_emit_epilogue (bool sibcall)
7395 {
7396 rtx frame_pointer, return_reg;
7397 int area_bottom, area_top, offset = 0;
7398 int next_offset;
7399 rtvec p;
7400 int i;
7401
7402 if (TARGET_TPF_PROFILING)
7403 {
7404
7405 /* Generate a BAS instruction to serve as a function
7406 entry intercept to facilitate the use of tracing
7407 algorithms located at the branch target. */
7408
7409 /* Emit a blockage here so that all code
7410 lies between the profiling mechanisms. */
7411 emit_insn (gen_blockage ());
7412
7413 emit_insn (gen_epilogue_tpf ());
7414 }
7415
7416 /* Check whether to use frame or stack pointer for restore. */
7417
7418 frame_pointer = (frame_pointer_needed
7419 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7420
7421 s390_frame_area (&area_bottom, &area_top);
7422
7423 /* Check whether we can access the register save area.
7424 If not, increment the frame pointer as required. */
7425
7426 if (area_top <= area_bottom)
7427 {
7428 /* Nothing to restore. */
7429 }
7430 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7431 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7432 {
7433 /* Area is in range. */
7434 offset = cfun_frame_layout.frame_size;
7435 }
7436 else
7437 {
7438 rtx insn, frame_off;
7439
7440 offset = area_bottom < 0 ? -area_bottom : 0;
7441 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7442
7443 if (DISP_IN_RANGE (INTVAL (frame_off)))
7444 {
7445 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7446 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7447 insn = emit_insn (insn);
7448 }
7449 else
7450 {
7451 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7452 frame_off = force_const_mem (Pmode, frame_off);
7453
7454 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7455 annotate_constant_pool_refs (&PATTERN (insn));
7456 }
7457 }
7458
7459 /* Restore call saved fprs. */
7460
7461 if (TARGET_64BIT)
7462 {
7463 if (cfun_save_high_fprs_p)
7464 {
7465 next_offset = cfun_frame_layout.f8_offset;
7466 for (i = 24; i < 32; i++)
7467 {
7468 if (cfun_fpr_bit_p (i - 16))
7469 {
7470 restore_fpr (frame_pointer,
7471 offset + next_offset, i);
7472 next_offset += 8;
7473 }
7474 }
7475 }
7476
7477 }
7478 else
7479 {
7480 next_offset = cfun_frame_layout.f4_offset;
7481 for (i = 18; i < 20; i++)
7482 {
7483 if (cfun_fpr_bit_p (i - 16))
7484 {
7485 restore_fpr (frame_pointer,
7486 offset + next_offset, i);
7487 next_offset += 8;
7488 }
7489 else if (!TARGET_PACKED_STACK)
7490 next_offset += 8;
7491 }
7492
7493 }
7494
7495 /* Return register. */
7496
7497 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7498
7499 /* Restore call saved gprs. */
7500
7501 if (cfun_frame_layout.first_restore_gpr != -1)
7502 {
7503 rtx insn, addr;
7504 int i;
7505
7506 /* Check for global register and save them
7507 to stack location from where they get restored. */
7508
7509 for (i = cfun_frame_layout.first_restore_gpr;
7510 i <= cfun_frame_layout.last_restore_gpr;
7511 i++)
7512 {
7513 /* These registers are special and need to be
7514 restored in any case. */
7515 if (i == STACK_POINTER_REGNUM
7516 || i == RETURN_REGNUM
7517 || i == BASE_REGNUM
7518 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7519 continue;
7520
7521 if (global_regs[i])
7522 {
7523 addr = plus_constant (frame_pointer,
7524 offset + cfun_frame_layout.gprs_offset
7525 + (i - cfun_frame_layout.first_save_gpr_slot)
7526 * UNITS_PER_WORD);
7527 addr = gen_rtx_MEM (Pmode, addr);
7528 set_mem_alias_set (addr, get_frame_alias_set ());
7529 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7530 }
7531 }
7532
7533 if (! sibcall)
7534 {
7535 /* Fetch return address from stack before load multiple,
7536 this will do good for scheduling. */
7537
7538 if (cfun_frame_layout.save_return_addr_p
7539 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7540 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7541 {
7542 int return_regnum = find_unused_clobbered_reg();
7543 if (!return_regnum)
7544 return_regnum = 4;
7545 return_reg = gen_rtx_REG (Pmode, return_regnum);
7546
7547 addr = plus_constant (frame_pointer,
7548 offset + cfun_frame_layout.gprs_offset
7549 + (RETURN_REGNUM
7550 - cfun_frame_layout.first_save_gpr_slot)
7551 * UNITS_PER_WORD);
7552 addr = gen_rtx_MEM (Pmode, addr);
7553 set_mem_alias_set (addr, get_frame_alias_set ());
7554 emit_move_insn (return_reg, addr);
7555 }
7556 }
7557
7558 insn = restore_gprs (frame_pointer,
7559 offset + cfun_frame_layout.gprs_offset
7560 + (cfun_frame_layout.first_restore_gpr
7561 - cfun_frame_layout.first_save_gpr_slot)
7562 * UNITS_PER_WORD,
7563 cfun_frame_layout.first_restore_gpr,
7564 cfun_frame_layout.last_restore_gpr);
7565 emit_insn (insn);
7566 }
7567
7568 if (! sibcall)
7569 {
7570
7571 /* Return to caller. */
7572
7573 p = rtvec_alloc (2);
7574
7575 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7576 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7577 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7578 }
7579 }
7580
7581
7582 /* Return the size in bytes of a function argument of
7583 type TYPE and/or mode MODE. At least one of TYPE or
7584 MODE must be specified. */
7585
7586 static int
7587 s390_function_arg_size (enum machine_mode mode, tree type)
7588 {
7589 if (type)
7590 return int_size_in_bytes (type);
7591
7592 /* No type info available for some library calls ... */
7593 if (mode != BLKmode)
7594 return GET_MODE_SIZE (mode);
7595
7596 /* If we have neither type nor mode, abort */
7597 gcc_unreachable ();
7598 }
7599
7600 /* Return true if a function argument of type TYPE and mode MODE
7601 is to be passed in a floating-point register, if available. */
7602
7603 static bool
7604 s390_function_arg_float (enum machine_mode mode, tree type)
7605 {
7606 int size = s390_function_arg_size (mode, type);
7607 if (size > 8)
7608 return false;
7609
7610 /* Soft-float changes the ABI: no floating-point registers are used. */
7611 if (TARGET_SOFT_FLOAT)
7612 return false;
7613
7614 /* No type info available for some library calls ... */
7615 if (!type)
7616 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
7617
7618 /* The ABI says that record types with a single member are treated
7619 just like that member would be. */
7620 while (TREE_CODE (type) == RECORD_TYPE)
7621 {
7622 tree field, single = NULL_TREE;
7623
7624 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7625 {
7626 if (TREE_CODE (field) != FIELD_DECL)
7627 continue;
7628
7629 if (single == NULL_TREE)
7630 single = TREE_TYPE (field);
7631 else
7632 return false;
7633 }
7634
7635 if (single == NULL_TREE)
7636 return false;
7637 else
7638 type = single;
7639 }
7640
7641 return TREE_CODE (type) == REAL_TYPE;
7642 }
7643
7644 /* Return true if a function argument of type TYPE and mode MODE
7645 is to be passed in an integer register, or a pair of integer
7646 registers, if available. */
7647
7648 static bool
7649 s390_function_arg_integer (enum machine_mode mode, tree type)
7650 {
7651 int size = s390_function_arg_size (mode, type);
7652 if (size > 8)
7653 return false;
7654
7655 /* No type info available for some library calls ... */
7656 if (!type)
7657 return GET_MODE_CLASS (mode) == MODE_INT
7658 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
7659
7660 /* We accept small integral (and similar) types. */
7661 if (INTEGRAL_TYPE_P (type)
7662 || POINTER_TYPE_P (type)
7663 || TREE_CODE (type) == OFFSET_TYPE
7664 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7665 return true;
7666
7667 /* We also accept structs of size 1, 2, 4, 8 that are not
7668 passed in floating-point registers. */
7669 if (AGGREGATE_TYPE_P (type)
7670 && exact_log2 (size) >= 0
7671 && !s390_function_arg_float (mode, type))
7672 return true;
7673
7674 return false;
7675 }
7676
7677 /* Return 1 if a function argument of type TYPE and mode MODE
7678 is to be passed by reference. The ABI specifies that only
7679 structures of size 1, 2, 4, or 8 bytes are passed by value,
7680 all other structures (and complex numbers) are passed by
7681 reference. */
7682
7683 static bool
7684 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7685 enum machine_mode mode, tree type,
7686 bool named ATTRIBUTE_UNUSED)
7687 {
7688 int size = s390_function_arg_size (mode, type);
7689 if (size > 8)
7690 return true;
7691
7692 if (type)
7693 {
7694 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7695 return 1;
7696
7697 if (TREE_CODE (type) == COMPLEX_TYPE
7698 || TREE_CODE (type) == VECTOR_TYPE)
7699 return 1;
7700 }
7701
7702 return 0;
7703 }
7704
7705 /* Update the data in CUM to advance over an argument of mode MODE and
7706 data type TYPE. (TYPE is null for libcalls where that information
7707 may not be available.). The boolean NAMED specifies whether the
7708 argument is a named argument (as opposed to an unnamed argument
7709 matching an ellipsis). */
7710
7711 void
7712 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7713 tree type, int named ATTRIBUTE_UNUSED)
7714 {
7715 if (s390_function_arg_float (mode, type))
7716 {
7717 cum->fprs += 1;
7718 }
7719 else if (s390_function_arg_integer (mode, type))
7720 {
7721 int size = s390_function_arg_size (mode, type);
7722 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7723 }
7724 else
7725 gcc_unreachable ();
7726 }
7727
7728 /* Define where to put the arguments to a function.
7729 Value is zero to push the argument on the stack,
7730 or a hard register in which to store the argument.
7731
7732 MODE is the argument's machine mode.
7733 TYPE is the data type of the argument (as a tree).
7734 This is null for libcalls where that information may
7735 not be available.
7736 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7737 the preceding args and about the function being called.
7738 NAMED is nonzero if this argument is a named parameter
7739 (otherwise it is an extra parameter matching an ellipsis).
7740
7741 On S/390, we use general purpose registers 2 through 6 to
7742 pass integer, pointer, and certain structure arguments, and
7743 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7744 to pass floating point arguments. All remaining arguments
7745 are pushed to the stack. */
7746
7747 rtx
7748 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7749 int named ATTRIBUTE_UNUSED)
7750 {
7751 if (s390_function_arg_float (mode, type))
7752 {
7753 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7754 return 0;
7755 else
7756 return gen_rtx_REG (mode, cum->fprs + 16);
7757 }
7758 else if (s390_function_arg_integer (mode, type))
7759 {
7760 int size = s390_function_arg_size (mode, type);
7761 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7762
7763 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7764 return 0;
7765 else
7766 return gen_rtx_REG (mode, cum->gprs + 2);
7767 }
7768
7769 /* After the real arguments, expand_call calls us once again
7770 with a void_type_node type. Whatever we return here is
7771 passed as operand 2 to the call expanders.
7772
7773 We don't need this feature ... */
7774 else if (type == void_type_node)
7775 return const0_rtx;
7776
7777 gcc_unreachable ();
7778 }
7779
7780 /* Return true if return values of type TYPE should be returned
7781 in a memory buffer whose address is passed by the caller as
7782 hidden first argument. */
7783
7784 static bool
7785 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7786 {
7787 /* We accept small integral (and similar) types. */
7788 if (INTEGRAL_TYPE_P (type)
7789 || POINTER_TYPE_P (type)
7790 || TREE_CODE (type) == OFFSET_TYPE
7791 || TREE_CODE (type) == REAL_TYPE)
7792 return int_size_in_bytes (type) > 8;
7793
7794 /* Aggregates and similar constructs are always returned
7795 in memory. */
7796 if (AGGREGATE_TYPE_P (type)
7797 || TREE_CODE (type) == COMPLEX_TYPE
7798 || TREE_CODE (type) == VECTOR_TYPE)
7799 return true;
7800
7801 /* ??? We get called on all sorts of random stuff from
7802 aggregate_value_p. We can't abort, but it's not clear
7803 what's safe to return. Pretend it's a struct I guess. */
7804 return true;
7805 }
7806
7807 /* Define where to return a (scalar) value of type TYPE.
7808 If TYPE is null, define where to return a (scalar)
7809 value of mode MODE from a libcall. */
7810
7811 rtx
7812 s390_function_value (tree type, enum machine_mode mode)
7813 {
7814 if (type)
7815 {
7816 int unsignedp = TYPE_UNSIGNED (type);
7817 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7818 }
7819
7820 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
7821 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7822
7823 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
7824 return gen_rtx_REG (mode, 16);
7825 else
7826 return gen_rtx_REG (mode, 2);
7827 }
7828
7829
7830 /* Create and return the va_list datatype.
7831
7832 On S/390, va_list is an array type equivalent to
7833
7834 typedef struct __va_list_tag
7835 {
7836 long __gpr;
7837 long __fpr;
7838 void *__overflow_arg_area;
7839 void *__reg_save_area;
7840 } va_list[1];
7841
7842 where __gpr and __fpr hold the number of general purpose
7843 or floating point arguments used up to now, respectively,
7844 __overflow_arg_area points to the stack location of the
7845 next argument passed on the stack, and __reg_save_area
7846 always points to the start of the register area in the
7847 call frame of the current function. The function prologue
7848 saves all registers used for argument passing into this
7849 area if the function uses variable arguments. */
7850
7851 static tree
7852 s390_build_builtin_va_list (void)
7853 {
7854 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7855
7856 record = lang_hooks.types.make_type (RECORD_TYPE);
7857
7858 type_decl =
7859 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7860
7861 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7862 long_integer_type_node);
7863 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7864 long_integer_type_node);
7865 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7866 ptr_type_node);
7867 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7868 ptr_type_node);
7869
7870 va_list_gpr_counter_field = f_gpr;
7871 va_list_fpr_counter_field = f_fpr;
7872
7873 DECL_FIELD_CONTEXT (f_gpr) = record;
7874 DECL_FIELD_CONTEXT (f_fpr) = record;
7875 DECL_FIELD_CONTEXT (f_ovf) = record;
7876 DECL_FIELD_CONTEXT (f_sav) = record;
7877
7878 TREE_CHAIN (record) = type_decl;
7879 TYPE_NAME (record) = type_decl;
7880 TYPE_FIELDS (record) = f_gpr;
7881 TREE_CHAIN (f_gpr) = f_fpr;
7882 TREE_CHAIN (f_fpr) = f_ovf;
7883 TREE_CHAIN (f_ovf) = f_sav;
7884
7885 layout_type (record);
7886
7887 /* The correct type is an array type of one element. */
7888 return build_array_type (record, build_index_type (size_zero_node));
7889 }
7890
7891 /* Implement va_start by filling the va_list structure VALIST.
7892 STDARG_P is always true, and ignored.
7893 NEXTARG points to the first anonymous stack argument.
7894
7895 The following global variables are used to initialize
7896 the va_list structure:
7897
7898 current_function_args_info:
7899 holds number of gprs and fprs used for named arguments.
7900 current_function_arg_offset_rtx:
7901 holds the offset of the first anonymous stack argument
7902 (relative to the virtual arg pointer). */
7903
7904 void
7905 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7906 {
7907 HOST_WIDE_INT n_gpr, n_fpr;
7908 int off;
7909 tree f_gpr, f_fpr, f_ovf, f_sav;
7910 tree gpr, fpr, ovf, sav, t;
7911
7912 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7913 f_fpr = TREE_CHAIN (f_gpr);
7914 f_ovf = TREE_CHAIN (f_fpr);
7915 f_sav = TREE_CHAIN (f_ovf);
7916
7917 valist = build_va_arg_indirect_ref (valist);
7918 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7919 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7920 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7921 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7922
7923 /* Count number of gp and fp argument registers used. */
7924
7925 n_gpr = current_function_args_info.gprs;
7926 n_fpr = current_function_args_info.fprs;
7927
7928 if (cfun->va_list_gpr_size)
7929 {
7930 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7931 build_int_cst (NULL_TREE, n_gpr));
7932 TREE_SIDE_EFFECTS (t) = 1;
7933 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7934 }
7935
7936 if (cfun->va_list_fpr_size)
7937 {
7938 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7939 build_int_cst (NULL_TREE, n_fpr));
7940 TREE_SIDE_EFFECTS (t) = 1;
7941 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7942 }
7943
7944 /* Find the overflow area. */
7945 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7946 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7947 {
7948 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7949
7950 off = INTVAL (current_function_arg_offset_rtx);
7951 off = off < 0 ? 0 : off;
7952 if (TARGET_DEBUG_ARG)
7953 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7954 (int)n_gpr, (int)n_fpr, off);
7955
7956 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7957
7958 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7959 TREE_SIDE_EFFECTS (t) = 1;
7960 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7961 }
7962
7963 /* Find the register save area. */
7964 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7965 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7966 {
7967 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7968 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
7969 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7970
7971 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7972 TREE_SIDE_EFFECTS (t) = 1;
7973 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7974 }
7975 }
7976
7977 /* Implement va_arg by updating the va_list structure
7978 VALIST as required to retrieve an argument of type
7979 TYPE, and returning that argument.
7980
7981 Generates code equivalent to:
7982
7983 if (integral value) {
7984 if (size <= 4 && args.gpr < 5 ||
7985 size > 4 && args.gpr < 4 )
7986 ret = args.reg_save_area[args.gpr+8]
7987 else
7988 ret = *args.overflow_arg_area++;
7989 } else if (float value) {
7990 if (args.fgpr < 2)
7991 ret = args.reg_save_area[args.fpr+64]
7992 else
7993 ret = *args.overflow_arg_area++;
7994 } else if (aggregate value) {
7995 if (args.gpr < 5)
7996 ret = *args.reg_save_area[args.gpr]
7997 else
7998 ret = **args.overflow_arg_area++;
7999 } */
8000
8001 static tree
8002 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
8003 tree *post_p ATTRIBUTE_UNUSED)
8004 {
8005 tree f_gpr, f_fpr, f_ovf, f_sav;
8006 tree gpr, fpr, ovf, sav, reg, t, u;
8007 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8008 tree lab_false, lab_over, addr;
8009
8010 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8011 f_fpr = TREE_CHAIN (f_gpr);
8012 f_ovf = TREE_CHAIN (f_fpr);
8013 f_sav = TREE_CHAIN (f_ovf);
8014
8015 valist = build_va_arg_indirect_ref (valist);
8016 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8017 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8018 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8019 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8020
8021 size = int_size_in_bytes (type);
8022
8023 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8024 {
8025 if (TARGET_DEBUG_ARG)
8026 {
8027 fprintf (stderr, "va_arg: aggregate type");
8028 debug_tree (type);
8029 }
8030
8031 /* Aggregates are passed by reference. */
8032 indirect_p = 1;
8033 reg = gpr;
8034 n_reg = 1;
8035
8036 /* kernel stack layout on 31 bit: It is assumed here that no padding
8037 will be added by s390_frame_info because for va_args always an even
8038 number of gprs has to be saved r15-r2 = 14 regs. */
8039 sav_ofs = 2 * UNITS_PER_WORD;
8040 sav_scale = UNITS_PER_WORD;
8041 size = UNITS_PER_WORD;
8042 max_reg = GP_ARG_NUM_REG - n_reg;
8043 }
8044 else if (s390_function_arg_float (TYPE_MODE (type), type))
8045 {
8046 if (TARGET_DEBUG_ARG)
8047 {
8048 fprintf (stderr, "va_arg: float type");
8049 debug_tree (type);
8050 }
8051
8052 /* FP args go in FP registers, if present. */
8053 indirect_p = 0;
8054 reg = fpr;
8055 n_reg = 1;
8056 sav_ofs = 16 * UNITS_PER_WORD;
8057 sav_scale = 8;
8058 max_reg = FP_ARG_NUM_REG - n_reg;
8059 }
8060 else
8061 {
8062 if (TARGET_DEBUG_ARG)
8063 {
8064 fprintf (stderr, "va_arg: other type");
8065 debug_tree (type);
8066 }
8067
8068 /* Otherwise into GP registers. */
8069 indirect_p = 0;
8070 reg = gpr;
8071 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8072
8073 /* kernel stack layout on 31 bit: It is assumed here that no padding
8074 will be added by s390_frame_info because for va_args always an even
8075 number of gprs has to be saved r15-r2 = 14 regs. */
8076 sav_ofs = 2 * UNITS_PER_WORD;
8077
8078 if (size < UNITS_PER_WORD)
8079 sav_ofs += UNITS_PER_WORD - size;
8080
8081 sav_scale = UNITS_PER_WORD;
8082 max_reg = GP_ARG_NUM_REG - n_reg;
8083 }
8084
8085 /* Pull the value out of the saved registers ... */
8086
8087 lab_false = create_artificial_label ();
8088 lab_over = create_artificial_label ();
8089 addr = create_tmp_var (ptr_type_node, "addr");
8090 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8091
8092 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8093 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8094 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8095 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8096 gimplify_and_add (t, pre_p);
8097
8098 t = build2 (PLUS_EXPR, ptr_type_node, sav,
8099 fold_convert (ptr_type_node, size_int (sav_ofs)));
8100 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8101 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8102 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
8103
8104 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
8105 gimplify_and_add (t, pre_p);
8106
8107 t = build1 (GOTO_EXPR, void_type_node, lab_over);
8108 gimplify_and_add (t, pre_p);
8109
8110 t = build1 (LABEL_EXPR, void_type_node, lab_false);
8111 append_to_statement_list (t, pre_p);
8112
8113
8114 /* ... Otherwise out of the overflow area. */
8115
8116 t = ovf;
8117 if (size < UNITS_PER_WORD)
8118 t = build2 (PLUS_EXPR, ptr_type_node, t,
8119 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
8120
8121 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8122
8123 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
8124 gimplify_and_add (u, pre_p);
8125
8126 t = build2 (PLUS_EXPR, ptr_type_node, t,
8127 fold_convert (ptr_type_node, size_int (size)));
8128 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
8129 gimplify_and_add (t, pre_p);
8130
8131 t = build1 (LABEL_EXPR, void_type_node, lab_over);
8132 append_to_statement_list (t, pre_p);
8133
8134
8135 /* Increment register save count. */
8136
8137 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8138 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8139 gimplify_and_add (u, pre_p);
8140
8141 if (indirect_p)
8142 {
8143 t = build_pointer_type (build_pointer_type (type));
8144 addr = fold_convert (t, addr);
8145 addr = build_va_arg_indirect_ref (addr);
8146 }
8147 else
8148 {
8149 t = build_pointer_type (type);
8150 addr = fold_convert (t, addr);
8151 }
8152
8153 return build_va_arg_indirect_ref (addr);
8154 }
8155
8156
8157 /* Builtins. */
8158
8159 enum s390_builtin
8160 {
8161 S390_BUILTIN_THREAD_POINTER,
8162 S390_BUILTIN_SET_THREAD_POINTER,
8163
8164 S390_BUILTIN_max
8165 };
8166
8167 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8168 CODE_FOR_get_tp_64,
8169 CODE_FOR_set_tp_64
8170 };
8171
8172 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8173 CODE_FOR_get_tp_31,
8174 CODE_FOR_set_tp_31
8175 };
8176
8177 static void
8178 s390_init_builtins (void)
8179 {
8180 tree ftype;
8181
8182 ftype = build_function_type (ptr_type_node, void_list_node);
8183 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
8184 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8185 NULL, NULL_TREE);
8186
8187 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8188 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
8189 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8190 NULL, NULL_TREE);
8191 }
8192
8193 /* Expand an expression EXP that calls a built-in function,
8194 with result going to TARGET if that's convenient
8195 (and in mode MODE if that's convenient).
8196 SUBTARGET may be used as the target for computing one of EXP's operands.
8197 IGNORE is nonzero if the value is to be ignored. */
8198
8199 static rtx
8200 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8201 enum machine_mode mode ATTRIBUTE_UNUSED,
8202 int ignore ATTRIBUTE_UNUSED)
8203 {
8204 #define MAX_ARGS 2
8205
8206 unsigned int const *code_for_builtin =
8207 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8208
8209 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8210 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8211 tree arglist = TREE_OPERAND (exp, 1);
8212 enum insn_code icode;
8213 rtx op[MAX_ARGS], pat;
8214 int arity;
8215 bool nonvoid;
8216
8217 if (fcode >= S390_BUILTIN_max)
8218 internal_error ("bad builtin fcode");
8219 icode = code_for_builtin[fcode];
8220 if (icode == 0)
8221 internal_error ("bad builtin fcode");
8222
8223 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8224
8225 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
8226 arglist;
8227 arglist = TREE_CHAIN (arglist), arity++)
8228 {
8229 const struct insn_operand_data *insn_op;
8230
8231 tree arg = TREE_VALUE (arglist);
8232 if (arg == error_mark_node)
8233 return NULL_RTX;
8234 if (arity > MAX_ARGS)
8235 return NULL_RTX;
8236
8237 insn_op = &insn_data[icode].operand[arity + nonvoid];
8238
8239 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8240
8241 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8242 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8243 }
8244
8245 if (nonvoid)
8246 {
8247 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8248 if (!target
8249 || GET_MODE (target) != tmode
8250 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8251 target = gen_reg_rtx (tmode);
8252 }
8253
8254 switch (arity)
8255 {
8256 case 0:
8257 pat = GEN_FCN (icode) (target);
8258 break;
8259 case 1:
8260 if (nonvoid)
8261 pat = GEN_FCN (icode) (target, op[0]);
8262 else
8263 pat = GEN_FCN (icode) (op[0]);
8264 break;
8265 case 2:
8266 pat = GEN_FCN (icode) (target, op[0], op[1]);
8267 break;
8268 default:
8269 gcc_unreachable ();
8270 }
8271 if (!pat)
8272 return NULL_RTX;
8273 emit_insn (pat);
8274
8275 if (nonvoid)
8276 return target;
8277 else
8278 return const0_rtx;
8279 }
8280
8281
8282 /* Output assembly code for the trampoline template to
8283 stdio stream FILE.
8284
8285 On S/390, we use gpr 1 internally in the trampoline code;
8286 gpr 0 is used to hold the static chain. */
8287
8288 void
8289 s390_trampoline_template (FILE *file)
8290 {
8291 rtx op[2];
8292 op[0] = gen_rtx_REG (Pmode, 0);
8293 op[1] = gen_rtx_REG (Pmode, 1);
8294
8295 if (TARGET_64BIT)
8296 {
8297 output_asm_insn ("basr\t%1,0", op);
8298 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8299 output_asm_insn ("br\t%1", op);
8300 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8301 }
8302 else
8303 {
8304 output_asm_insn ("basr\t%1,0", op);
8305 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8306 output_asm_insn ("br\t%1", op);
8307 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8308 }
8309 }
8310
8311 /* Emit RTL insns to initialize the variable parts of a trampoline.
8312 FNADDR is an RTX for the address of the function's pure code.
8313 CXT is an RTX for the static chain value for the function. */
8314
8315 void
8316 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8317 {
8318 emit_move_insn (gen_rtx_MEM (Pmode,
8319 memory_address (Pmode,
8320 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8321 emit_move_insn (gen_rtx_MEM (Pmode,
8322 memory_address (Pmode,
8323 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8324 }
8325
8326 /* Return rtx for 64-bit constant formed from the 32-bit subwords
8327 LOW and HIGH, independent of the host word size. */
8328
8329 rtx
8330 s390_gen_rtx_const_DI (int high, int low)
8331 {
8332 #if HOST_BITS_PER_WIDE_INT >= 64
8333 HOST_WIDE_INT val;
8334 val = (HOST_WIDE_INT)high;
8335 val <<= 32;
8336 val |= (HOST_WIDE_INT)low;
8337
8338 return GEN_INT (val);
8339 #else
8340 #if HOST_BITS_PER_WIDE_INT >= 32
8341 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8342 #else
8343 gcc_unreachable ();
8344 #endif
8345 #endif
8346 }
8347
8348 /* Output assembler code to FILE to increment profiler label # LABELNO
8349 for profiling a function entry. */
8350
8351 void
8352 s390_function_profiler (FILE *file, int labelno)
8353 {
8354 rtx op[7];
8355
8356 char label[128];
8357 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8358
8359 fprintf (file, "# function profiler \n");
8360
8361 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8362 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8363 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8364
8365 op[2] = gen_rtx_REG (Pmode, 1);
8366 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8367 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8368
8369 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8370 if (flag_pic)
8371 {
8372 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8373 op[4] = gen_rtx_CONST (Pmode, op[4]);
8374 }
8375
8376 if (TARGET_64BIT)
8377 {
8378 output_asm_insn ("stg\t%0,%1", op);
8379 output_asm_insn ("larl\t%2,%3", op);
8380 output_asm_insn ("brasl\t%0,%4", op);
8381 output_asm_insn ("lg\t%0,%1", op);
8382 }
8383 else if (!flag_pic)
8384 {
8385 op[6] = gen_label_rtx ();
8386
8387 output_asm_insn ("st\t%0,%1", op);
8388 output_asm_insn ("bras\t%2,%l6", op);
8389 output_asm_insn (".long\t%4", op);
8390 output_asm_insn (".long\t%3", op);
8391 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8392 output_asm_insn ("l\t%0,0(%2)", op);
8393 output_asm_insn ("l\t%2,4(%2)", op);
8394 output_asm_insn ("basr\t%0,%0", op);
8395 output_asm_insn ("l\t%0,%1", op);
8396 }
8397 else
8398 {
8399 op[5] = gen_label_rtx ();
8400 op[6] = gen_label_rtx ();
8401
8402 output_asm_insn ("st\t%0,%1", op);
8403 output_asm_insn ("bras\t%2,%l6", op);
8404 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8405 output_asm_insn (".long\t%4-%l5", op);
8406 output_asm_insn (".long\t%3-%l5", op);
8407 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8408 output_asm_insn ("lr\t%0,%2", op);
8409 output_asm_insn ("a\t%0,0(%2)", op);
8410 output_asm_insn ("a\t%2,4(%2)", op);
8411 output_asm_insn ("basr\t%0,%0", op);
8412 output_asm_insn ("l\t%0,%1", op);
8413 }
8414 }
8415
8416 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8417 into its SYMBOL_REF_FLAGS. */
8418
8419 static void
8420 s390_encode_section_info (tree decl, rtx rtl, int first)
8421 {
8422 default_encode_section_info (decl, rtl, first);
8423
8424 /* If a variable has a forced alignment to < 2 bytes, mark it with
8425 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8426 if (TREE_CODE (decl) == VAR_DECL
8427 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8428 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8429 }
8430
8431 /* Output thunk to FILE that implements a C++ virtual function call (with
8432 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8433 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8434 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8435 relative to the resulting this pointer. */
8436
8437 static void
8438 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8439 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8440 tree function)
8441 {
8442 rtx op[10];
8443 int nonlocal = 0;
8444
8445 /* Operand 0 is the target function. */
8446 op[0] = XEXP (DECL_RTL (function), 0);
8447 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8448 {
8449 nonlocal = 1;
8450 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8451 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8452 op[0] = gen_rtx_CONST (Pmode, op[0]);
8453 }
8454
8455 /* Operand 1 is the 'this' pointer. */
8456 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8457 op[1] = gen_rtx_REG (Pmode, 3);
8458 else
8459 op[1] = gen_rtx_REG (Pmode, 2);
8460
8461 /* Operand 2 is the delta. */
8462 op[2] = GEN_INT (delta);
8463
8464 /* Operand 3 is the vcall_offset. */
8465 op[3] = GEN_INT (vcall_offset);
8466
8467 /* Operand 4 is the temporary register. */
8468 op[4] = gen_rtx_REG (Pmode, 1);
8469
8470 /* Operands 5 to 8 can be used as labels. */
8471 op[5] = NULL_RTX;
8472 op[6] = NULL_RTX;
8473 op[7] = NULL_RTX;
8474 op[8] = NULL_RTX;
8475
8476 /* Operand 9 can be used for temporary register. */
8477 op[9] = NULL_RTX;
8478
8479 /* Generate code. */
8480 if (TARGET_64BIT)
8481 {
8482 /* Setup literal pool pointer if required. */
8483 if ((!DISP_IN_RANGE (delta)
8484 && !CONST_OK_FOR_K (delta)
8485 && !CONST_OK_FOR_Os (delta))
8486 || (!DISP_IN_RANGE (vcall_offset)
8487 && !CONST_OK_FOR_K (vcall_offset)
8488 && !CONST_OK_FOR_Os (vcall_offset)))
8489 {
8490 op[5] = gen_label_rtx ();
8491 output_asm_insn ("larl\t%4,%5", op);
8492 }
8493
8494 /* Add DELTA to this pointer. */
8495 if (delta)
8496 {
8497 if (CONST_OK_FOR_J (delta))
8498 output_asm_insn ("la\t%1,%2(%1)", op);
8499 else if (DISP_IN_RANGE (delta))
8500 output_asm_insn ("lay\t%1,%2(%1)", op);
8501 else if (CONST_OK_FOR_K (delta))
8502 output_asm_insn ("aghi\t%1,%2", op);
8503 else if (CONST_OK_FOR_Os (delta))
8504 output_asm_insn ("agfi\t%1,%2", op);
8505 else
8506 {
8507 op[6] = gen_label_rtx ();
8508 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8509 }
8510 }
8511
8512 /* Perform vcall adjustment. */
8513 if (vcall_offset)
8514 {
8515 if (DISP_IN_RANGE (vcall_offset))
8516 {
8517 output_asm_insn ("lg\t%4,0(%1)", op);
8518 output_asm_insn ("ag\t%1,%3(%4)", op);
8519 }
8520 else if (CONST_OK_FOR_K (vcall_offset))
8521 {
8522 output_asm_insn ("lghi\t%4,%3", op);
8523 output_asm_insn ("ag\t%4,0(%1)", op);
8524 output_asm_insn ("ag\t%1,0(%4)", op);
8525 }
8526 else if (CONST_OK_FOR_Os (vcall_offset))
8527 {
8528 output_asm_insn ("lgfi\t%4,%3", op);
8529 output_asm_insn ("ag\t%4,0(%1)", op);
8530 output_asm_insn ("ag\t%1,0(%4)", op);
8531 }
8532 else
8533 {
8534 op[7] = gen_label_rtx ();
8535 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8536 output_asm_insn ("ag\t%4,0(%1)", op);
8537 output_asm_insn ("ag\t%1,0(%4)", op);
8538 }
8539 }
8540
8541 /* Jump to target. */
8542 output_asm_insn ("jg\t%0", op);
8543
8544 /* Output literal pool if required. */
8545 if (op[5])
8546 {
8547 output_asm_insn (".align\t4", op);
8548 targetm.asm_out.internal_label (file, "L",
8549 CODE_LABEL_NUMBER (op[5]));
8550 }
8551 if (op[6])
8552 {
8553 targetm.asm_out.internal_label (file, "L",
8554 CODE_LABEL_NUMBER (op[6]));
8555 output_asm_insn (".long\t%2", op);
8556 }
8557 if (op[7])
8558 {
8559 targetm.asm_out.internal_label (file, "L",
8560 CODE_LABEL_NUMBER (op[7]));
8561 output_asm_insn (".long\t%3", op);
8562 }
8563 }
8564 else
8565 {
8566 /* Setup base pointer if required. */
8567 if (!vcall_offset
8568 || (!DISP_IN_RANGE (delta)
8569 && !CONST_OK_FOR_K (delta)
8570 && !CONST_OK_FOR_Os (delta))
8571 || (!DISP_IN_RANGE (delta)
8572 && !CONST_OK_FOR_K (vcall_offset)
8573 && !CONST_OK_FOR_Os (vcall_offset)))
8574 {
8575 op[5] = gen_label_rtx ();
8576 output_asm_insn ("basr\t%4,0", op);
8577 targetm.asm_out.internal_label (file, "L",
8578 CODE_LABEL_NUMBER (op[5]));
8579 }
8580
8581 /* Add DELTA to this pointer. */
8582 if (delta)
8583 {
8584 if (CONST_OK_FOR_J (delta))
8585 output_asm_insn ("la\t%1,%2(%1)", op);
8586 else if (DISP_IN_RANGE (delta))
8587 output_asm_insn ("lay\t%1,%2(%1)", op);
8588 else if (CONST_OK_FOR_K (delta))
8589 output_asm_insn ("ahi\t%1,%2", op);
8590 else if (CONST_OK_FOR_Os (delta))
8591 output_asm_insn ("afi\t%1,%2", op);
8592 else
8593 {
8594 op[6] = gen_label_rtx ();
8595 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8596 }
8597 }
8598
8599 /* Perform vcall adjustment. */
8600 if (vcall_offset)
8601 {
8602 if (CONST_OK_FOR_J (vcall_offset))
8603 {
8604 output_asm_insn ("l\t%4,0(%1)", op);
8605 output_asm_insn ("a\t%1,%3(%4)", op);
8606 }
8607 else if (DISP_IN_RANGE (vcall_offset))
8608 {
8609 output_asm_insn ("l\t%4,0(%1)", op);
8610 output_asm_insn ("ay\t%1,%3(%4)", op);
8611 }
8612 else if (CONST_OK_FOR_K (vcall_offset))
8613 {
8614 output_asm_insn ("lhi\t%4,%3", op);
8615 output_asm_insn ("a\t%4,0(%1)", op);
8616 output_asm_insn ("a\t%1,0(%4)", op);
8617 }
8618 else if (CONST_OK_FOR_Os (vcall_offset))
8619 {
8620 output_asm_insn ("iilf\t%4,%3", op);
8621 output_asm_insn ("a\t%4,0(%1)", op);
8622 output_asm_insn ("a\t%1,0(%4)", op);
8623 }
8624 else
8625 {
8626 op[7] = gen_label_rtx ();
8627 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8628 output_asm_insn ("a\t%4,0(%1)", op);
8629 output_asm_insn ("a\t%1,0(%4)", op);
8630 }
8631
8632 /* We had to clobber the base pointer register.
8633 Re-setup the base pointer (with a different base). */
8634 op[5] = gen_label_rtx ();
8635 output_asm_insn ("basr\t%4,0", op);
8636 targetm.asm_out.internal_label (file, "L",
8637 CODE_LABEL_NUMBER (op[5]));
8638 }
8639
8640 /* Jump to target. */
8641 op[8] = gen_label_rtx ();
8642
8643 if (!flag_pic)
8644 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8645 else if (!nonlocal)
8646 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8647 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8648 else if (flag_pic == 1)
8649 {
8650 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8651 output_asm_insn ("l\t%4,%0(%4)", op);
8652 }
8653 else if (flag_pic == 2)
8654 {
8655 op[9] = gen_rtx_REG (Pmode, 0);
8656 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8657 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8658 output_asm_insn ("ar\t%4,%9", op);
8659 output_asm_insn ("l\t%4,0(%4)", op);
8660 }
8661
8662 output_asm_insn ("br\t%4", op);
8663
8664 /* Output literal pool. */
8665 output_asm_insn (".align\t4", op);
8666
8667 if (nonlocal && flag_pic == 2)
8668 output_asm_insn (".long\t%0", op);
8669 if (nonlocal)
8670 {
8671 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8672 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8673 }
8674
8675 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8676 if (!flag_pic)
8677 output_asm_insn (".long\t%0", op);
8678 else
8679 output_asm_insn (".long\t%0-%5", op);
8680
8681 if (op[6])
8682 {
8683 targetm.asm_out.internal_label (file, "L",
8684 CODE_LABEL_NUMBER (op[6]));
8685 output_asm_insn (".long\t%2", op);
8686 }
8687 if (op[7])
8688 {
8689 targetm.asm_out.internal_label (file, "L",
8690 CODE_LABEL_NUMBER (op[7]));
8691 output_asm_insn (".long\t%3", op);
8692 }
8693 }
8694 }
8695
8696 static bool
8697 s390_valid_pointer_mode (enum machine_mode mode)
8698 {
8699 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8700 }
8701
8702 /* Checks whether the given ARGUMENT_LIST would use a caller
8703 saved register. This is used to decide whether sibling call
8704 optimization could be performed on the respective function
8705 call. */
8706
8707 static bool
8708 s390_call_saved_register_used (tree argument_list)
8709 {
8710 CUMULATIVE_ARGS cum;
8711 tree parameter;
8712 enum machine_mode mode;
8713 tree type;
8714 rtx parm_rtx;
8715 int reg;
8716
8717 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8718
8719 while (argument_list)
8720 {
8721 parameter = TREE_VALUE (argument_list);
8722 argument_list = TREE_CHAIN (argument_list);
8723
8724 gcc_assert (parameter);
8725
8726 /* For an undeclared variable passed as parameter we will get
8727 an ERROR_MARK node here. */
8728 if (TREE_CODE (parameter) == ERROR_MARK)
8729 return true;
8730
8731 type = TREE_TYPE (parameter);
8732 gcc_assert (type);
8733
8734 mode = TYPE_MODE (type);
8735 gcc_assert (mode);
8736
8737 if (pass_by_reference (&cum, mode, type, true))
8738 {
8739 mode = Pmode;
8740 type = build_pointer_type (type);
8741 }
8742
8743 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8744
8745 s390_function_arg_advance (&cum, mode, type, 0);
8746
8747 if (parm_rtx && REG_P (parm_rtx))
8748 {
8749 for (reg = 0;
8750 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8751 reg++)
8752 if (! call_used_regs[reg + REGNO (parm_rtx)])
8753 return true;
8754 }
8755 }
8756 return false;
8757 }
8758
8759 /* Return true if the given call expression can be
8760 turned into a sibling call.
8761 DECL holds the declaration of the function to be called whereas
8762 EXP is the call expression itself. */
8763
8764 static bool
8765 s390_function_ok_for_sibcall (tree decl, tree exp)
8766 {
8767 /* The TPF epilogue uses register 1. */
8768 if (TARGET_TPF_PROFILING)
8769 return false;
8770
8771 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8772 which would have to be restored before the sibcall. */
8773 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
8774 return false;
8775
8776 /* Register 6 on s390 is available as an argument register but unfortunately
8777 "caller saved". This makes functions needing this register for arguments
8778 not suitable for sibcalls. */
8779 if (TREE_OPERAND (exp, 1)
8780 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8781 return false;
8782
8783 return true;
8784 }
8785
8786 /* Return the fixed registers used for condition codes. */
8787
8788 static bool
8789 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8790 {
8791 *p1 = CC_REGNUM;
8792 *p2 = INVALID_REGNUM;
8793
8794 return true;
8795 }
8796
8797 /* This function is used by the call expanders of the machine description.
8798 It emits the call insn itself together with the necessary operations
8799 to adjust the target address and returns the emitted insn.
8800 ADDR_LOCATION is the target address rtx
8801 TLS_CALL the location of the thread-local symbol
8802 RESULT_REG the register where the result of the call should be stored
8803 RETADDR_REG the register where the return address should be stored
8804 If this parameter is NULL_RTX the call is considered
8805 to be a sibling call. */
8806
8807 rtx
8808 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8809 rtx retaddr_reg)
8810 {
8811 bool plt_call = false;
8812 rtx insn;
8813 rtx call;
8814 rtx clobber;
8815 rtvec vec;
8816
8817 /* Direct function calls need special treatment. */
8818 if (GET_CODE (addr_location) == SYMBOL_REF)
8819 {
8820 /* When calling a global routine in PIC mode, we must
8821 replace the symbol itself with the PLT stub. */
8822 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8823 {
8824 addr_location = gen_rtx_UNSPEC (Pmode,
8825 gen_rtvec (1, addr_location),
8826 UNSPEC_PLT);
8827 addr_location = gen_rtx_CONST (Pmode, addr_location);
8828 plt_call = true;
8829 }
8830
8831 /* Unless we can use the bras(l) insn, force the
8832 routine address into a register. */
8833 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8834 {
8835 if (flag_pic)
8836 addr_location = legitimize_pic_address (addr_location, 0);
8837 else
8838 addr_location = force_reg (Pmode, addr_location);
8839 }
8840 }
8841
8842 /* If it is already an indirect call or the code above moved the
8843 SYMBOL_REF to somewhere else make sure the address can be found in
8844 register 1. */
8845 if (retaddr_reg == NULL_RTX
8846 && GET_CODE (addr_location) != SYMBOL_REF
8847 && !plt_call)
8848 {
8849 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8850 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8851 }
8852
8853 addr_location = gen_rtx_MEM (QImode, addr_location);
8854 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8855
8856 if (result_reg != NULL_RTX)
8857 call = gen_rtx_SET (VOIDmode, result_reg, call);
8858
8859 if (retaddr_reg != NULL_RTX)
8860 {
8861 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8862
8863 if (tls_call != NULL_RTX)
8864 vec = gen_rtvec (3, call, clobber,
8865 gen_rtx_USE (VOIDmode, tls_call));
8866 else
8867 vec = gen_rtvec (2, call, clobber);
8868
8869 call = gen_rtx_PARALLEL (VOIDmode, vec);
8870 }
8871
8872 insn = emit_call_insn (call);
8873
8874 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8875 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8876 {
8877 /* s390_function_ok_for_sibcall should
8878 have denied sibcalls in this case. */
8879 gcc_assert (retaddr_reg != NULL_RTX);
8880
8881 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8882 }
8883 return insn;
8884 }
8885
8886 /* Implement CONDITIONAL_REGISTER_USAGE. */
8887
8888 void
8889 s390_conditional_register_usage (void)
8890 {
8891 int i;
8892
8893 if (flag_pic)
8894 {
8895 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8896 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8897 }
8898 if (TARGET_CPU_ZARCH)
8899 {
8900 fixed_regs[BASE_REGNUM] = 0;
8901 call_used_regs[BASE_REGNUM] = 0;
8902 fixed_regs[RETURN_REGNUM] = 0;
8903 call_used_regs[RETURN_REGNUM] = 0;
8904 }
8905 if (TARGET_64BIT)
8906 {
8907 for (i = 24; i < 32; i++)
8908 call_used_regs[i] = call_really_used_regs[i] = 0;
8909 }
8910 else
8911 {
8912 for (i = 18; i < 20; i++)
8913 call_used_regs[i] = call_really_used_regs[i] = 0;
8914 }
8915
8916 if (TARGET_SOFT_FLOAT)
8917 {
8918 for (i = 16; i < 32; i++)
8919 call_used_regs[i] = fixed_regs[i] = 1;
8920 }
8921 }
8922
8923 /* Corresponding function to eh_return expander. */
8924
8925 static GTY(()) rtx s390_tpf_eh_return_symbol;
8926 void
8927 s390_emit_tpf_eh_return (rtx target)
8928 {
8929 rtx insn, reg;
8930
8931 if (!s390_tpf_eh_return_symbol)
8932 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8933
8934 reg = gen_rtx_REG (Pmode, 2);
8935
8936 emit_move_insn (reg, target);
8937 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8938 gen_rtx_REG (Pmode, RETURN_REGNUM));
8939 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8940
8941 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8942 }
8943
8944 /* Rework the prologue/epilogue to avoid saving/restoring
8945 registers unnecessarily. */
8946
8947 static void
8948 s390_optimize_prologue (void)
8949 {
8950 rtx insn, new_insn, next_insn;
8951
8952 /* Do a final recompute of the frame-related data. */
8953
8954 s390_update_frame_layout ();
8955
8956 /* If all special registers are in fact used, there's nothing we
8957 can do, so no point in walking the insn list. */
8958
8959 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8960 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8961 && (TARGET_CPU_ZARCH
8962 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8963 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8964 return;
8965
8966 /* Search for prologue/epilogue insns and replace them. */
8967
8968 for (insn = get_insns (); insn; insn = next_insn)
8969 {
8970 int first, last, off;
8971 rtx set, base, offset;
8972
8973 next_insn = NEXT_INSN (insn);
8974
8975 if (GET_CODE (insn) != INSN)
8976 continue;
8977
8978 if (GET_CODE (PATTERN (insn)) == PARALLEL
8979 && store_multiple_operation (PATTERN (insn), VOIDmode))
8980 {
8981 set = XVECEXP (PATTERN (insn), 0, 0);
8982 first = REGNO (SET_SRC (set));
8983 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8984 offset = const0_rtx;
8985 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8986 off = INTVAL (offset);
8987
8988 if (GET_CODE (base) != REG || off < 0)
8989 continue;
8990 if (cfun_frame_layout.first_save_gpr != -1
8991 && (cfun_frame_layout.first_save_gpr < first
8992 || cfun_frame_layout.last_save_gpr > last))
8993 continue;
8994 if (REGNO (base) != STACK_POINTER_REGNUM
8995 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8996 continue;
8997 if (first > BASE_REGNUM || last < BASE_REGNUM)
8998 continue;
8999
9000 if (cfun_frame_layout.first_save_gpr != -1)
9001 {
9002 new_insn = save_gprs (base,
9003 off + (cfun_frame_layout.first_save_gpr
9004 - first) * UNITS_PER_WORD,
9005 cfun_frame_layout.first_save_gpr,
9006 cfun_frame_layout.last_save_gpr);
9007 new_insn = emit_insn_before (new_insn, insn);
9008 INSN_ADDRESSES_NEW (new_insn, -1);
9009 }
9010
9011 remove_insn (insn);
9012 continue;
9013 }
9014
9015 if (cfun_frame_layout.first_save_gpr == -1
9016 && GET_CODE (PATTERN (insn)) == SET
9017 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9018 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9019 || (!TARGET_CPU_ZARCH
9020 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9021 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9022 {
9023 set = PATTERN (insn);
9024 first = REGNO (SET_SRC (set));
9025 offset = const0_rtx;
9026 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9027 off = INTVAL (offset);
9028
9029 if (GET_CODE (base) != REG || off < 0)
9030 continue;
9031 if (REGNO (base) != STACK_POINTER_REGNUM
9032 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9033 continue;
9034
9035 remove_insn (insn);
9036 continue;
9037 }
9038
9039 if (GET_CODE (PATTERN (insn)) == PARALLEL
9040 && load_multiple_operation (PATTERN (insn), VOIDmode))
9041 {
9042 set = XVECEXP (PATTERN (insn), 0, 0);
9043 first = REGNO (SET_DEST (set));
9044 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9045 offset = const0_rtx;
9046 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9047 off = INTVAL (offset);
9048
9049 if (GET_CODE (base) != REG || off < 0)
9050 continue;
9051 if (cfun_frame_layout.first_restore_gpr != -1
9052 && (cfun_frame_layout.first_restore_gpr < first
9053 || cfun_frame_layout.last_restore_gpr > last))
9054 continue;
9055 if (REGNO (base) != STACK_POINTER_REGNUM
9056 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9057 continue;
9058 if (first > BASE_REGNUM || last < BASE_REGNUM)
9059 continue;
9060
9061 if (cfun_frame_layout.first_restore_gpr != -1)
9062 {
9063 new_insn = restore_gprs (base,
9064 off + (cfun_frame_layout.first_restore_gpr
9065 - first) * UNITS_PER_WORD,
9066 cfun_frame_layout.first_restore_gpr,
9067 cfun_frame_layout.last_restore_gpr);
9068 new_insn = emit_insn_before (new_insn, insn);
9069 INSN_ADDRESSES_NEW (new_insn, -1);
9070 }
9071
9072 remove_insn (insn);
9073 continue;
9074 }
9075
9076 if (cfun_frame_layout.first_restore_gpr == -1
9077 && GET_CODE (PATTERN (insn)) == SET
9078 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9079 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9080 || (!TARGET_CPU_ZARCH
9081 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9082 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9083 {
9084 set = PATTERN (insn);
9085 first = REGNO (SET_DEST (set));
9086 offset = const0_rtx;
9087 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9088 off = INTVAL (offset);
9089
9090 if (GET_CODE (base) != REG || off < 0)
9091 continue;
9092 if (REGNO (base) != STACK_POINTER_REGNUM
9093 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9094 continue;
9095
9096 remove_insn (insn);
9097 continue;
9098 }
9099 }
9100 }
9101
9102 /* Perform machine-dependent processing. */
9103
9104 static void
9105 s390_reorg (void)
9106 {
9107 bool pool_overflow = false;
9108
9109 /* Make sure all splits have been performed; splits after
9110 machine_dependent_reorg might confuse insn length counts. */
9111 split_all_insns_noflow ();
9112
9113 /* From here on decomposed literal pool addresses must be accepted. */
9114 cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
9115
9116 /* Install the main literal pool and the associated base
9117 register load insns.
9118
9119 In addition, there are two problematic situations we need
9120 to correct:
9121
9122 - the literal pool might be > 4096 bytes in size, so that
9123 some of its elements cannot be directly accessed
9124
9125 - a branch target might be > 64K away from the branch, so that
9126 it is not possible to use a PC-relative instruction.
9127
9128 To fix those, we split the single literal pool into multiple
9129 pool chunks, reloading the pool base register at various
9130 points throughout the function to ensure it always points to
9131 the pool chunk the following code expects, and / or replace
9132 PC-relative branches by absolute branches.
9133
9134 However, the two problems are interdependent: splitting the
9135 literal pool can move a branch further away from its target,
9136 causing the 64K limit to overflow, and on the other hand,
9137 replacing a PC-relative branch by an absolute branch means
9138 we need to put the branch target address into the literal
9139 pool, possibly causing it to overflow.
9140
9141 So, we loop trying to fix up both problems until we manage
9142 to satisfy both conditions at the same time. Note that the
9143 loop is guaranteed to terminate as every pass of the loop
9144 strictly decreases the total number of PC-relative branches
9145 in the function. (This is not completely true as there
9146 might be branch-over-pool insns introduced by chunkify_start.
9147 Those never need to be split however.) */
9148
9149 for (;;)
9150 {
9151 struct constant_pool *pool = NULL;
9152
9153 /* Collect the literal pool. */
9154 if (!pool_overflow)
9155 {
9156 pool = s390_mainpool_start ();
9157 if (!pool)
9158 pool_overflow = true;
9159 }
9160
9161 /* If literal pool overflowed, start to chunkify it. */
9162 if (pool_overflow)
9163 pool = s390_chunkify_start ();
9164
9165 /* Split out-of-range branches. If this has created new
9166 literal pool entries, cancel current chunk list and
9167 recompute it. zSeries machines have large branch
9168 instructions, so we never need to split a branch. */
9169 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9170 {
9171 if (pool_overflow)
9172 s390_chunkify_cancel (pool);
9173 else
9174 s390_mainpool_cancel (pool);
9175
9176 continue;
9177 }
9178
9179 /* If we made it up to here, both conditions are satisfied.
9180 Finish up literal pool related changes. */
9181 if (pool_overflow)
9182 s390_chunkify_finish (pool);
9183 else
9184 s390_mainpool_finish (pool);
9185
9186 /* We're done splitting branches. */
9187 cfun->machine->split_branches_pending_p = false;
9188 break;
9189 }
9190
9191 /* Generate out-of-pool execute target insns. */
9192 if (TARGET_CPU_ZARCH)
9193 {
9194 rtx insn, label, target;
9195
9196 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9197 {
9198 label = s390_execute_label (insn);
9199 if (!label)
9200 continue;
9201
9202 gcc_assert (label != const0_rtx);
9203
9204 target = emit_label (XEXP (label, 0));
9205 INSN_ADDRESSES_NEW (target, -1);
9206
9207 target = emit_insn (s390_execute_target (insn));
9208 INSN_ADDRESSES_NEW (target, -1);
9209 }
9210 }
9211
9212 /* Try to optimize prologue and epilogue further. */
9213 s390_optimize_prologue ();
9214 }
9215
9216
9217 /* Initialize GCC target structure. */
9218
9219 #undef TARGET_ASM_ALIGNED_HI_OP
9220 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9221 #undef TARGET_ASM_ALIGNED_DI_OP
9222 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9223 #undef TARGET_ASM_INTEGER
9224 #define TARGET_ASM_INTEGER s390_assemble_integer
9225
9226 #undef TARGET_ASM_OPEN_PAREN
9227 #define TARGET_ASM_OPEN_PAREN ""
9228
9229 #undef TARGET_ASM_CLOSE_PAREN
9230 #define TARGET_ASM_CLOSE_PAREN ""
9231
9232 #undef TARGET_DEFAULT_TARGET_FLAGS
9233 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9234 #undef TARGET_HANDLE_OPTION
9235 #define TARGET_HANDLE_OPTION s390_handle_option
9236
9237 #undef TARGET_ENCODE_SECTION_INFO
9238 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9239
9240 #ifdef HAVE_AS_TLS
9241 #undef TARGET_HAVE_TLS
9242 #define TARGET_HAVE_TLS true
9243 #endif
9244 #undef TARGET_CANNOT_FORCE_CONST_MEM
9245 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9246
9247 #undef TARGET_DELEGITIMIZE_ADDRESS
9248 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9249
9250 #undef TARGET_RETURN_IN_MEMORY
9251 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9252
9253 #undef TARGET_INIT_BUILTINS
9254 #define TARGET_INIT_BUILTINS s390_init_builtins
9255 #undef TARGET_EXPAND_BUILTIN
9256 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9257
9258 #undef TARGET_ASM_OUTPUT_MI_THUNK
9259 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9260 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9261 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9262
9263 #undef TARGET_SCHED_ADJUST_PRIORITY
9264 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9265 #undef TARGET_SCHED_ISSUE_RATE
9266 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9267 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9268 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9269
9270 #undef TARGET_CANNOT_COPY_INSN_P
9271 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9272 #undef TARGET_RTX_COSTS
9273 #define TARGET_RTX_COSTS s390_rtx_costs
9274 #undef TARGET_ADDRESS_COST
9275 #define TARGET_ADDRESS_COST s390_address_cost
9276
9277 #undef TARGET_MACHINE_DEPENDENT_REORG
9278 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9279
9280 #undef TARGET_VALID_POINTER_MODE
9281 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9282
9283 #undef TARGET_BUILD_BUILTIN_VA_LIST
9284 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9285 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9286 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9287
9288 #undef TARGET_PROMOTE_FUNCTION_ARGS
9289 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9290 #undef TARGET_PROMOTE_FUNCTION_RETURN
9291 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9292 #undef TARGET_PASS_BY_REFERENCE
9293 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9294
9295 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9296 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9297
9298 #undef TARGET_FIXED_CONDITION_CODE_REGS
9299 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9300
9301 #undef TARGET_CC_MODES_COMPATIBLE
9302 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9303
9304 #undef TARGET_INVALID_WITHIN_DOLOOP
9305 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9306
9307 #ifdef HAVE_AS_TLS
9308 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9309 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9310 #endif
9311
9312 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9313 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
9314 #define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type
9315 #endif
9316
9317 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9318 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9319
9320 struct gcc_target targetm = TARGET_INITIALIZER;
9321
9322 #include "gt-s390.h"