1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
59 /* Define the specific costs for a given cpu. */
61 struct processor_costs
64 const int m
; /* cost of an M instruction. */
65 const int mghi
; /* cost of an MGHI instruction. */
66 const int mh
; /* cost of an MH instruction. */
67 const int mhi
; /* cost of an MHI instruction. */
68 const int ml
; /* cost of an ML instruction. */
69 const int mr
; /* cost of an MR instruction. */
70 const int ms
; /* cost of an MS instruction. */
71 const int msg
; /* cost of an MSG instruction. */
72 const int msgf
; /* cost of an MSGF instruction. */
73 const int msgfr
; /* cost of an MSGFR instruction. */
74 const int msgr
; /* cost of an MSGR instruction. */
75 const int msr
; /* cost of an MSR instruction. */
76 const int mult_df
; /* cost of multiplication in DFmode. */
79 const int sqxbr
; /* cost of square root in TFmode. */
80 const int sqdbr
; /* cost of square root in DFmode. */
81 const int sqebr
; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr
; /* cost of multiply and add in DFmode. */
84 const int maebr
; /* cost of multiply and add in SFmode. */
96 const struct processor_costs
*s390_cost
;
99 struct processor_costs z900_cost
=
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
131 struct processor_costs z990_cost
=
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
163 struct processor_costs z9_109_cost
=
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
195 struct processor_costs z10_cost
=
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
227 struct processor_costs z196_cost
=
229 COSTS_N_INSNS (7), /* M */
230 COSTS_N_INSNS (5), /* MGHI */
231 COSTS_N_INSNS (5), /* MH */
232 COSTS_N_INSNS (5), /* MHI */
233 COSTS_N_INSNS (7), /* ML */
234 COSTS_N_INSNS (7), /* MR */
235 COSTS_N_INSNS (6), /* MS */
236 COSTS_N_INSNS (8), /* MSG */
237 COSTS_N_INSNS (6), /* MSGF */
238 COSTS_N_INSNS (6), /* MSGFR */
239 COSTS_N_INSNS (8), /* MSGR */
240 COSTS_N_INSNS (6), /* MSR */
241 COSTS_N_INSNS (1) , /* multiplication in DFmode */
242 COSTS_N_INSNS (40), /* MXBR B+40 */
243 COSTS_N_INSNS (100), /* SQXBR B+100 */
244 COSTS_N_INSNS (42), /* SQDBR B+42 */
245 COSTS_N_INSNS (28), /* SQEBR B+28 */
246 COSTS_N_INSNS (1), /* MADBR B */
247 COSTS_N_INSNS (1), /* MAEBR B */
248 COSTS_N_INSNS (101), /* DXBR B+101 */
249 COSTS_N_INSNS (29), /* DDBR */
250 COSTS_N_INSNS (22), /* DEBR */
251 COSTS_N_INSNS (160), /* DLGR cracked */
252 COSTS_N_INSNS (160), /* DLR cracked */
253 COSTS_N_INSNS (160), /* DR expanded */
254 COSTS_N_INSNS (160), /* DSGFR cracked */
255 COSTS_N_INSNS (160), /* DSGR cracked */
258 extern int reload_completed
;
260 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
261 static rtx last_scheduled_insn
;
263 /* Structure used to hold the components of a S/390 memory
264 address. A legitimate address on S/390 is of the general
266 base + index + displacement
267 where any of the components is optional.
269 base and index are registers of the class ADDR_REGS,
270 displacement is an unsigned 12-bit immediate constant. */
281 /* Which cpu are we tuning for. */
282 enum processor_type s390_tune
= PROCESSOR_max
;
284 /* Which instruction set architecture to use. */
285 enum processor_type s390_arch
;
288 HOST_WIDE_INT s390_warn_framesize
= 0;
289 HOST_WIDE_INT s390_stack_size
= 0;
290 HOST_WIDE_INT s390_stack_guard
= 0;
292 /* The following structure is embedded in the machine
293 specific part of struct function. */
295 struct GTY (()) s390_frame_layout
297 /* Offset within stack frame. */
298 HOST_WIDE_INT gprs_offset
;
299 HOST_WIDE_INT f0_offset
;
300 HOST_WIDE_INT f4_offset
;
301 HOST_WIDE_INT f8_offset
;
302 HOST_WIDE_INT backchain_offset
;
304 /* Number of first and last gpr where slots in the register
305 save area are reserved for. */
306 int first_save_gpr_slot
;
307 int last_save_gpr_slot
;
309 /* Number of first and last gpr to be saved, restored. */
311 int first_restore_gpr
;
313 int last_restore_gpr
;
315 /* Bits standing for floating point registers. Set, if the
316 respective register has to be saved. Starting with reg 16 (f0)
317 at the rightmost bit.
318 Bit 15 - 8 7 6 5 4 3 2 1 0
319 fpr 15 - 8 7 5 3 1 6 4 2 0
320 reg 31 - 24 23 22 21 20 19 18 17 16 */
321 unsigned int fpr_bitmap
;
323 /* Number of floating point registers f8-f15 which must be saved. */
326 /* Set if return address needs to be saved.
327 This flag is set by s390_return_addr_rtx if it could not use
328 the initial value of r14 and therefore depends on r14 saved
330 bool save_return_addr_p
;
332 /* Size of stack frame. */
333 HOST_WIDE_INT frame_size
;
336 /* Define the structure for the machine field in struct function. */
338 struct GTY(()) machine_function
340 struct s390_frame_layout frame_layout
;
342 /* Literal pool base register. */
345 /* True if we may need to perform branch splitting. */
346 bool split_branches_pending_p
;
348 /* Some local-dynamic TLS symbol name. */
349 const char *some_ld_name
;
351 bool has_landing_pad_p
;
354 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
356 #define cfun_frame_layout (cfun->machine->frame_layout)
357 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
358 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
359 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
360 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
362 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
365 /* Number of GPRs and FPRs used for argument passing. */
366 #define GP_ARG_NUM_REG 5
367 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
369 /* A couple of shortcuts. */
370 #define CONST_OK_FOR_J(x) \
371 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
372 #define CONST_OK_FOR_K(x) \
373 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
374 #define CONST_OK_FOR_Os(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
376 #define CONST_OK_FOR_Op(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
378 #define CONST_OK_FOR_On(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
381 #define REGNO_PAIR_OK(REGNO, MODE) \
382 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
384 /* That's the read ahead of the dynamic branch prediction unit in
385 bytes on a z10 (or higher) CPU. */
386 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
388 static enum machine_mode
389 s390_libgcc_cmp_return_mode (void)
391 return TARGET_64BIT
? DImode
: SImode
;
394 static enum machine_mode
395 s390_libgcc_shift_count_mode (void)
397 return TARGET_64BIT
? DImode
: SImode
;
400 static enum machine_mode
401 s390_unwind_word_mode (void)
403 return TARGET_64BIT
? DImode
: SImode
;
406 /* Return true if the back end supports mode MODE. */
408 s390_scalar_mode_supported_p (enum machine_mode mode
)
410 /* In contrast to the default implementation reject TImode constants on 31bit
411 TARGET_ZARCH for ABI compliance. */
412 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
415 if (DECIMAL_FLOAT_MODE_P (mode
))
416 return default_decimal_float_supported_p ();
418 return default_scalar_mode_supported_p (mode
);
421 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
424 s390_set_has_landing_pad_p (bool value
)
426 cfun
->machine
->has_landing_pad_p
= value
;
429 /* If two condition code modes are compatible, return a condition code
430 mode which is compatible with both. Otherwise, return
433 static enum machine_mode
434 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
442 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
443 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
464 /* Return true if SET either doesn't set the CC register, or else
465 the source and destination have matching CC modes and that
466 CC mode is at least as constrained as REQ_MODE. */
469 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
471 enum machine_mode set_mode
;
473 gcc_assert (GET_CODE (set
) == SET
);
475 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
478 set_mode
= GET_MODE (SET_DEST (set
));
492 if (req_mode
!= set_mode
)
497 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
498 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
504 if (req_mode
!= CCAmode
)
512 return (GET_MODE (SET_SRC (set
)) == set_mode
);
515 /* Return true if every SET in INSN that sets the CC register
516 has source and destination with matching CC modes and that
517 CC mode is at least as constrained as REQ_MODE.
518 If REQ_MODE is VOIDmode, always return false. */
521 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
525 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
526 if (req_mode
== VOIDmode
)
529 if (GET_CODE (PATTERN (insn
)) == SET
)
530 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
532 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
533 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
535 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
536 if (GET_CODE (set
) == SET
)
537 if (!s390_match_ccmode_set (set
, req_mode
))
544 /* If a test-under-mask instruction can be used to implement
545 (compare (and ... OP1) OP2), return the CC mode required
546 to do that. Otherwise, return VOIDmode.
547 MIXED is true if the instruction can distinguish between
548 CC1 and CC2 for mixed selected bits (TMxx), it is false
549 if the instruction cannot (TM). */
552 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
556 /* ??? Fixme: should work on CONST_DOUBLE as well. */
557 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
560 /* Selected bits all zero: CC0.
561 e.g.: int a; if ((a & (16 + 128)) == 0) */
562 if (INTVAL (op2
) == 0)
565 /* Selected bits all one: CC3.
566 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
567 if (INTVAL (op2
) == INTVAL (op1
))
570 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
572 if ((a & (16 + 128)) == 16) -> CCT1
573 if ((a & (16 + 128)) == 128) -> CCT2 */
576 bit1
= exact_log2 (INTVAL (op2
));
577 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
578 if (bit0
!= -1 && bit1
!= -1)
579 return bit0
> bit1
? CCT1mode
: CCT2mode
;
585 /* Given a comparison code OP (EQ, NE, etc.) and the operands
586 OP0 and OP1 of a COMPARE, return the mode to be used for the
590 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
596 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
597 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
599 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
600 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
602 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
603 || GET_CODE (op1
) == NEG
)
604 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
607 if (GET_CODE (op0
) == AND
)
609 /* Check whether we can potentially do it via TM. */
610 enum machine_mode ccmode
;
611 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
612 if (ccmode
!= VOIDmode
)
614 /* Relax CCTmode to CCZmode to allow fall-back to AND
615 if that turns out to be beneficial. */
616 return ccmode
== CCTmode
? CCZmode
: ccmode
;
620 if (register_operand (op0
, HImode
)
621 && GET_CODE (op1
) == CONST_INT
622 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
624 if (register_operand (op0
, QImode
)
625 && GET_CODE (op1
) == CONST_INT
626 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
635 /* The only overflow condition of NEG and ABS happens when
636 -INT_MAX is used as parameter, which stays negative. So
637 we have an overflow from a positive value to a negative.
638 Using CCAP mode the resulting cc can be used for comparisons. */
639 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
640 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
643 /* If constants are involved in an add instruction it is possible to use
644 the resulting cc for comparisons with zero. Knowing the sign of the
645 constant the overflow behavior gets predictable. e.g.:
646 int a, b; if ((b = a + c) > 0)
647 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
648 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
649 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
651 if (INTVAL (XEXP((op0
), 1)) < 0)
665 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
666 && GET_CODE (op1
) != CONST_INT
)
672 if (GET_CODE (op0
) == PLUS
673 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
676 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
677 && GET_CODE (op1
) != CONST_INT
)
683 if (GET_CODE (op0
) == MINUS
684 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
687 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
688 && GET_CODE (op1
) != CONST_INT
)
697 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
698 that we can implement more efficiently. */
701 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
703 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
704 if ((*code
== EQ
|| *code
== NE
)
705 && *op1
== const0_rtx
706 && GET_CODE (*op0
) == ZERO_EXTRACT
707 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
708 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
709 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
711 rtx inner
= XEXP (*op0
, 0);
712 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
713 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
714 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
716 if (len
> 0 && len
< modesize
717 && pos
>= 0 && pos
+ len
<= modesize
718 && modesize
<= HOST_BITS_PER_WIDE_INT
)
720 unsigned HOST_WIDE_INT block
;
721 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
722 block
<<= modesize
- pos
- len
;
724 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
725 gen_int_mode (block
, GET_MODE (inner
)));
729 /* Narrow AND of memory against immediate to enable TM. */
730 if ((*code
== EQ
|| *code
== NE
)
731 && *op1
== const0_rtx
732 && GET_CODE (*op0
) == AND
733 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
734 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
736 rtx inner
= XEXP (*op0
, 0);
737 rtx mask
= XEXP (*op0
, 1);
739 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
740 if (GET_CODE (inner
) == SUBREG
741 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
742 && (GET_MODE_SIZE (GET_MODE (inner
))
743 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
745 & GET_MODE_MASK (GET_MODE (inner
))
746 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
748 inner
= SUBREG_REG (inner
);
750 /* Do not change volatile MEMs. */
751 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
753 int part
= s390_single_part (XEXP (*op0
, 1),
754 GET_MODE (inner
), QImode
, 0);
757 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
758 inner
= adjust_address_nv (inner
, QImode
, part
);
759 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
764 /* Narrow comparisons against 0xffff to HImode if possible. */
765 if ((*code
== EQ
|| *code
== NE
)
766 && GET_CODE (*op1
) == CONST_INT
767 && INTVAL (*op1
) == 0xffff
768 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
769 && (nonzero_bits (*op0
, GET_MODE (*op0
))
770 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
772 *op0
= gen_lowpart (HImode
, *op0
);
776 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
777 if (GET_CODE (*op0
) == UNSPEC
778 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
779 && XVECLEN (*op0
, 0) == 1
780 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
781 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
782 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
783 && *op1
== const0_rtx
)
785 enum rtx_code new_code
= UNKNOWN
;
788 case EQ
: new_code
= EQ
; break;
789 case NE
: new_code
= NE
; break;
790 case LT
: new_code
= GTU
; break;
791 case GT
: new_code
= LTU
; break;
792 case LE
: new_code
= GEU
; break;
793 case GE
: new_code
= LEU
; break;
797 if (new_code
!= UNKNOWN
)
799 *op0
= XVECEXP (*op0
, 0, 0);
804 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
805 if (GET_CODE (*op0
) == UNSPEC
806 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
807 && XVECLEN (*op0
, 0) == 1
808 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
809 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
810 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
811 && *op1
== const0_rtx
)
813 enum rtx_code new_code
= UNKNOWN
;
816 case EQ
: new_code
= EQ
; break;
817 case NE
: new_code
= NE
; break;
821 if (new_code
!= UNKNOWN
)
823 *op0
= XVECEXP (*op0
, 0, 0);
828 /* Simplify cascaded EQ, NE with const0_rtx. */
829 if ((*code
== NE
|| *code
== EQ
)
830 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
831 && GET_MODE (*op0
) == SImode
832 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
833 && REG_P (XEXP (*op0
, 0))
834 && XEXP (*op0
, 1) == const0_rtx
835 && *op1
== const0_rtx
)
837 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
838 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
842 *op0
= XEXP (*op0
, 0);
845 /* Prefer register over memory as first operand. */
846 if (MEM_P (*op0
) && REG_P (*op1
))
848 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
849 *code
= swap_condition (*code
);
853 /* Emit a compare instruction suitable to implement the comparison
854 OP0 CODE OP1. Return the correct condition RTL to be placed in
855 the IF_THEN_ELSE of the conditional branch testing the result. */
858 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
860 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
863 /* Do not output a redundant compare instruction if a compare_and_swap
864 pattern already computed the result and the machine modes are compatible. */
865 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
867 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
873 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
874 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
877 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
880 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
882 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
883 conditional branch testing the result. */
886 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
888 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
889 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
892 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
893 unconditional jump, else a conditional jump under condition COND. */
896 s390_emit_jump (rtx target
, rtx cond
)
900 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
902 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
904 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
905 emit_jump_insn (insn
);
908 /* Return branch condition mask to implement a branch
909 specified by CODE. Return -1 for invalid comparisons. */
912 s390_branch_condition_mask (rtx code
)
914 const int CC0
= 1 << 3;
915 const int CC1
= 1 << 2;
916 const int CC2
= 1 << 1;
917 const int CC3
= 1 << 0;
919 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
920 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
921 gcc_assert (XEXP (code
, 1) == const0_rtx
);
923 switch (GET_MODE (XEXP (code
, 0)))
927 switch (GET_CODE (code
))
930 case NE
: return CC1
| CC2
| CC3
;
936 switch (GET_CODE (code
))
939 case NE
: return CC0
| CC2
| CC3
;
945 switch (GET_CODE (code
))
948 case NE
: return CC0
| CC1
| CC3
;
954 switch (GET_CODE (code
))
957 case NE
: return CC0
| CC1
| CC2
;
963 switch (GET_CODE (code
))
965 case EQ
: return CC0
| CC2
;
966 case NE
: return CC1
| CC3
;
972 switch (GET_CODE (code
))
974 case LTU
: return CC2
| CC3
; /* carry */
975 case GEU
: return CC0
| CC1
; /* no carry */
981 switch (GET_CODE (code
))
983 case GTU
: return CC0
| CC1
; /* borrow */
984 case LEU
: return CC2
| CC3
; /* no borrow */
990 switch (GET_CODE (code
))
992 case EQ
: return CC0
| CC2
;
993 case NE
: return CC1
| CC3
;
994 case LTU
: return CC1
;
995 case GTU
: return CC3
;
996 case LEU
: return CC1
| CC2
;
997 case GEU
: return CC2
| CC3
;
1002 switch (GET_CODE (code
))
1004 case EQ
: return CC0
;
1005 case NE
: return CC1
| CC2
| CC3
;
1006 case LTU
: return CC1
;
1007 case GTU
: return CC2
;
1008 case LEU
: return CC0
| CC1
;
1009 case GEU
: return CC0
| CC2
;
1015 switch (GET_CODE (code
))
1017 case EQ
: return CC0
;
1018 case NE
: return CC2
| CC1
| CC3
;
1019 case LTU
: return CC2
;
1020 case GTU
: return CC1
;
1021 case LEU
: return CC0
| CC2
;
1022 case GEU
: return CC0
| CC1
;
1028 switch (GET_CODE (code
))
1030 case EQ
: return CC0
;
1031 case NE
: return CC1
| CC2
| CC3
;
1032 case LT
: return CC1
| CC3
;
1033 case GT
: return CC2
;
1034 case LE
: return CC0
| CC1
| CC3
;
1035 case GE
: return CC0
| CC2
;
1041 switch (GET_CODE (code
))
1043 case EQ
: return CC0
;
1044 case NE
: return CC1
| CC2
| CC3
;
1045 case LT
: return CC1
;
1046 case GT
: return CC2
| CC3
;
1047 case LE
: return CC0
| CC1
;
1048 case GE
: return CC0
| CC2
| CC3
;
1054 switch (GET_CODE (code
))
1056 case EQ
: return CC0
;
1057 case NE
: return CC1
| CC2
| CC3
;
1058 case LT
: return CC1
;
1059 case GT
: return CC2
;
1060 case LE
: return CC0
| CC1
;
1061 case GE
: return CC0
| CC2
;
1062 case UNORDERED
: return CC3
;
1063 case ORDERED
: return CC0
| CC1
| CC2
;
1064 case UNEQ
: return CC0
| CC3
;
1065 case UNLT
: return CC1
| CC3
;
1066 case UNGT
: return CC2
| CC3
;
1067 case UNLE
: return CC0
| CC1
| CC3
;
1068 case UNGE
: return CC0
| CC2
| CC3
;
1069 case LTGT
: return CC1
| CC2
;
1075 switch (GET_CODE (code
))
1077 case EQ
: return CC0
;
1078 case NE
: return CC2
| CC1
| CC3
;
1079 case LT
: return CC2
;
1080 case GT
: return CC1
;
1081 case LE
: return CC0
| CC2
;
1082 case GE
: return CC0
| CC1
;
1083 case UNORDERED
: return CC3
;
1084 case ORDERED
: return CC0
| CC2
| CC1
;
1085 case UNEQ
: return CC0
| CC3
;
1086 case UNLT
: return CC2
| CC3
;
1087 case UNGT
: return CC1
| CC3
;
1088 case UNLE
: return CC0
| CC2
| CC3
;
1089 case UNGE
: return CC0
| CC1
| CC3
;
1090 case LTGT
: return CC2
| CC1
;
1101 /* Return branch condition mask to implement a compare and branch
1102 specified by CODE. Return -1 for invalid comparisons. */
1105 s390_compare_and_branch_condition_mask (rtx code
)
1107 const int CC0
= 1 << 3;
1108 const int CC1
= 1 << 2;
1109 const int CC2
= 1 << 1;
1111 switch (GET_CODE (code
))
1135 /* If INV is false, return assembler mnemonic string to implement
1136 a branch specified by CODE. If INV is true, return mnemonic
1137 for the corresponding inverted branch. */
1140 s390_branch_condition_mnemonic (rtx code
, int inv
)
1144 static const char *const mnemonic
[16] =
1146 NULL
, "o", "h", "nle",
1147 "l", "nhe", "lh", "ne",
1148 "e", "nlh", "he", "nl",
1149 "le", "nh", "no", NULL
1152 if (GET_CODE (XEXP (code
, 0)) == REG
1153 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1154 && XEXP (code
, 1) == const0_rtx
)
1155 mask
= s390_branch_condition_mask (code
);
1157 mask
= s390_compare_and_branch_condition_mask (code
);
1159 gcc_assert (mask
>= 0);
1164 gcc_assert (mask
>= 1 && mask
<= 14);
1166 return mnemonic
[mask
];
1169 /* Return the part of op which has a value different from def.
1170 The size of the part is determined by mode.
1171 Use this function only if you already know that op really
1172 contains such a part. */
1174 unsigned HOST_WIDE_INT
1175 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1177 unsigned HOST_WIDE_INT value
= 0;
1178 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1179 int part_bits
= GET_MODE_BITSIZE (mode
);
1180 unsigned HOST_WIDE_INT part_mask
1181 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1184 for (i
= 0; i
< max_parts
; i
++)
1187 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1189 value
>>= part_bits
;
1191 if ((value
& part_mask
) != (def
& part_mask
))
1192 return value
& part_mask
;
1198 /* If OP is an integer constant of mode MODE with exactly one
1199 part of mode PART_MODE unequal to DEF, return the number of that
1200 part. Otherwise, return -1. */
1203 s390_single_part (rtx op
,
1204 enum machine_mode mode
,
1205 enum machine_mode part_mode
,
1208 unsigned HOST_WIDE_INT value
= 0;
1209 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1210 unsigned HOST_WIDE_INT part_mask
1211 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1214 if (GET_CODE (op
) != CONST_INT
)
1217 for (i
= 0; i
< n_parts
; i
++)
1220 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1222 value
>>= GET_MODE_BITSIZE (part_mode
);
1224 if ((value
& part_mask
) != (def
& part_mask
))
1232 return part
== -1 ? -1 : n_parts
- 1 - part
;
1235 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1236 bits and no other bits are set in IN. POS and LENGTH can be used
1237 to obtain the start position and the length of the bitfield.
1239 POS gives the position of the first bit of the bitfield counting
1240 from the lowest order bit starting with zero. In order to use this
1241 value for S/390 instructions this has to be converted to "bits big
1245 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1246 int *pos
, int *length
)
1251 unsigned HOST_WIDE_INT mask
= 1ULL;
1252 bool contiguous
= false;
1254 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1278 /* Calculate a mask for all bits beyond the contiguous bits. */
1279 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1284 if (tmp_length
+ tmp_pos
- 1 > size
)
1288 *length
= tmp_length
;
1296 /* Check whether we can (and want to) split a double-word
1297 move in mode MODE from SRC to DST into two single-word
1298 moves, moving the subword FIRST_SUBWORD first. */
1301 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1303 /* Floating point registers cannot be split. */
1304 if (FP_REG_P (src
) || FP_REG_P (dst
))
1307 /* We don't need to split if operands are directly accessible. */
1308 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1311 /* Non-offsettable memory references cannot be split. */
1312 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1313 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1316 /* Moving the first subword must not clobber a register
1317 needed to move the second subword. */
1318 if (register_operand (dst
, mode
))
1320 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1321 if (reg_overlap_mentioned_p (subreg
, src
))
1328 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1329 and [MEM2, MEM2 + SIZE] do overlap and false
1333 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1335 rtx addr1
, addr2
, addr_delta
;
1336 HOST_WIDE_INT delta
;
1338 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1344 addr1
= XEXP (mem1
, 0);
1345 addr2
= XEXP (mem2
, 0);
1347 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1349 /* This overlapping check is used by peepholes merging memory block operations.
1350 Overlapping operations would otherwise be recognized by the S/390 hardware
1351 and would fall back to a slower implementation. Allowing overlapping
1352 operations would lead to slow code but not to wrong code. Therefore we are
1353 somewhat optimistic if we cannot prove that the memory blocks are
1355 That's why we return false here although this may accept operations on
1356 overlapping memory areas. */
1357 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1360 delta
= INTVAL (addr_delta
);
1363 || (delta
> 0 && delta
< size
)
1364 || (delta
< 0 && -delta
< size
))
1370 /* Check whether the address of memory reference MEM2 equals exactly
1371 the address of memory reference MEM1 plus DELTA. Return true if
1372 we can prove this to be the case, false otherwise. */
1375 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1377 rtx addr1
, addr2
, addr_delta
;
1379 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1382 addr1
= XEXP (mem1
, 0);
1383 addr2
= XEXP (mem2
, 0);
1385 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1386 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1392 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1395 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1398 enum machine_mode wmode
= mode
;
1399 rtx dst
= operands
[0];
1400 rtx src1
= operands
[1];
1401 rtx src2
= operands
[2];
1404 /* If we cannot handle the operation directly, use a temp register. */
1405 if (!s390_logical_operator_ok_p (operands
))
1406 dst
= gen_reg_rtx (mode
);
1408 /* QImode and HImode patterns make sense only if we have a destination
1409 in memory. Otherwise perform the operation in SImode. */
1410 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1413 /* Widen operands if required. */
1416 if (GET_CODE (dst
) == SUBREG
1417 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1419 else if (REG_P (dst
))
1420 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1422 dst
= gen_reg_rtx (wmode
);
1424 if (GET_CODE (src1
) == SUBREG
1425 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1427 else if (GET_MODE (src1
) != VOIDmode
)
1428 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1430 if (GET_CODE (src2
) == SUBREG
1431 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1433 else if (GET_MODE (src2
) != VOIDmode
)
1434 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1437 /* Emit the instruction. */
1438 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1439 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1440 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1442 /* Fix up the destination if needed. */
1443 if (dst
!= operands
[0])
1444 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1447 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1450 s390_logical_operator_ok_p (rtx
*operands
)
1452 /* If the destination operand is in memory, it needs to coincide
1453 with one of the source operands. After reload, it has to be
1454 the first source operand. */
1455 if (GET_CODE (operands
[0]) == MEM
)
1456 return rtx_equal_p (operands
[0], operands
[1])
1457 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1462 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1463 operand IMMOP to switch from SS to SI type instructions. */
1466 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1468 int def
= code
== AND
? -1 : 0;
1472 gcc_assert (GET_CODE (*memop
) == MEM
);
1473 gcc_assert (!MEM_VOLATILE_P (*memop
));
1475 mask
= s390_extract_part (*immop
, QImode
, def
);
1476 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1477 gcc_assert (part
>= 0);
1479 *memop
= adjust_address (*memop
, QImode
, part
);
1480 *immop
= gen_int_mode (mask
, QImode
);
1484 /* How to allocate a 'struct machine_function'. */
1486 static struct machine_function
*
1487 s390_init_machine_status (void)
1489 return ggc_alloc_cleared_machine_function ();
1492 /* Change optimizations to be performed, depending on the
1495 LEVEL is the optimization level specified; 2 if `-O2' is
1496 specified, 1 if `-O' is specified, and 0 if neither is specified.
1498 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1501 s390_option_optimization (int level ATTRIBUTE_UNUSED
, int size
)
1503 /* ??? There are apparently still problems with -fcaller-saves. */
1504 flag_caller_saves
= 0;
1506 /* By default, always emit DWARF-2 unwind info. This allows debugging
1507 without maintaining a stack frame back-chain. */
1508 flag_asynchronous_unwind_tables
= 1;
1510 /* Use MVCLE instructions to decrease code size if requested. */
1512 target_flags
|= MASK_MVCLE
;
1515 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1516 to the associated processor_type and processor_flags if so. */
1519 s390_handle_arch_option (const char *arg
,
1520 enum processor_type
*type
,
1525 const char *const name
; /* processor name or nickname. */
1526 const enum processor_type processor
;
1527 const int flags
; /* From enum processor_flags. */
1529 const processor_alias_table
[] =
1531 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1532 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1533 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1534 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1535 | PF_LONG_DISPLACEMENT
},
1536 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1537 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1538 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1539 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1540 {"z10", PROCESSOR_2097_Z10
, PF_IEEE_FLOAT
| PF_ZARCH
1541 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
},
1542 {"z196", PROCESSOR_2817_Z196
, PF_IEEE_FLOAT
| PF_ZARCH
1543 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
| PF_Z196
},
1547 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1548 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1550 *type
= processor_alias_table
[i
].processor
;
1551 *flags
= processor_alias_table
[i
].flags
;
1557 /* Implement TARGET_HANDLE_OPTION. */
1560 s390_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1565 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1567 case OPT_mstack_guard_
:
1568 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1570 if (exact_log2 (s390_stack_guard
) == -1)
1571 error ("stack guard value must be an exact power of 2");
1574 case OPT_mstack_size_
:
1575 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1577 if (exact_log2 (s390_stack_size
) == -1)
1578 error ("stack size must be an exact power of 2");
1582 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1584 case OPT_mwarn_framesize_
:
1585 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1593 s390_option_override (void)
1595 /* Set up function hooks. */
1596 init_machine_status
= s390_init_machine_status
;
1598 /* Architecture mode defaults according to ABI. */
1599 if (!(target_flags_explicit
& MASK_ZARCH
))
1602 target_flags
|= MASK_ZARCH
;
1604 target_flags
&= ~MASK_ZARCH
;
1607 /* Determine processor architectural level. */
1608 if (!s390_arch_string
)
1610 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1611 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1614 /* Determine processor to tune for. */
1615 if (s390_tune
== PROCESSOR_max
)
1617 s390_tune
= s390_arch
;
1618 s390_tune_flags
= s390_arch_flags
;
1621 /* Sanity checks. */
1622 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1623 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1624 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1625 error ("64-bit ABI not supported in ESA/390 mode");
1627 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1629 if (target_flags_explicit
& MASK_HARD_DFP
)
1631 if (!TARGET_CPU_DFP
)
1632 error ("Hardware decimal floating point instructions"
1633 " not available on %s", s390_arch_string
);
1635 error ("Hardware decimal floating point instructions"
1636 " not available in ESA/390 mode");
1639 target_flags
&= ~MASK_HARD_DFP
;
1642 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1644 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1645 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1647 target_flags
&= ~MASK_HARD_DFP
;
1650 /* Set processor cost function. */
1653 case PROCESSOR_2084_Z990
:
1654 s390_cost
= &z990_cost
;
1656 case PROCESSOR_2094_Z9_109
:
1657 s390_cost
= &z9_109_cost
;
1659 case PROCESSOR_2097_Z10
:
1660 s390_cost
= &z10_cost
;
1661 case PROCESSOR_2817_Z196
:
1662 s390_cost
= &z196_cost
;
1665 s390_cost
= &z900_cost
;
1668 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1669 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1672 if (s390_stack_size
)
1674 if (s390_stack_guard
>= s390_stack_size
)
1675 error ("stack size must be greater than the stack guard value");
1676 else if (s390_stack_size
> 1 << 16)
1677 error ("stack size must not be greater than 64k");
1679 else if (s390_stack_guard
)
1680 error ("-mstack-guard implies use of -mstack-size");
1682 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1683 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1684 target_flags
|= MASK_LONG_DOUBLE_128
;
1687 if (s390_tune
== PROCESSOR_2097_Z10
1688 || s390_tune
== PROCESSOR_2817_Z196
)
1690 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100);
1691 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32);
1692 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000);
1693 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64);
1696 set_param_value ("max-pending-list-length", 256);
1697 /* values for loop prefetching */
1698 set_param_value ("l1-cache-line-size", 256);
1699 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128);
1700 /* s390 has more than 2 levels and the size is much larger. Since
1701 we are always running virtualized assume that we only get a small
1702 part of the caches above l1. */
1703 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500);
1704 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2);
1705 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6);
1707 /* This cannot reside in s390_option_optimization since HAVE_prefetch
1708 requires the arch flags to be evaluated already. Since prefetching
1709 is beneficial on s390, we enable it if available. */
1710 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1711 flag_prefetch_loop_arrays
= 1;
1714 /* Map for smallest class containing reg regno. */
1716 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1717 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1718 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1719 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1720 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1721 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1722 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1723 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1724 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1725 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1726 ACCESS_REGS
, ACCESS_REGS
1729 /* Return attribute type of insn. */
1731 static enum attr_type
1732 s390_safe_attr_type (rtx insn
)
1734 if (recog_memoized (insn
) >= 0)
1735 return get_attr_type (insn
);
1740 /* Return true if DISP is a valid short displacement. */
1743 s390_short_displacement (rtx disp
)
1745 /* No displacement is OK. */
1749 /* Without the long displacement facility we don't need to
1750 distingiush between long and short displacement. */
1751 if (!TARGET_LONG_DISPLACEMENT
)
1754 /* Integer displacement in range. */
1755 if (GET_CODE (disp
) == CONST_INT
)
1756 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1758 /* GOT offset is not OK, the GOT can be large. */
1759 if (GET_CODE (disp
) == CONST
1760 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1761 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1762 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1765 /* All other symbolic constants are literal pool references,
1766 which are OK as the literal pool must be small. */
1767 if (GET_CODE (disp
) == CONST
)
1773 /* Decompose a RTL expression ADDR for a memory address into
1774 its components, returned in OUT.
1776 Returns false if ADDR is not a valid memory address, true
1777 otherwise. If OUT is NULL, don't return the components,
1778 but check for validity only.
1780 Note: Only addresses in canonical form are recognized.
1781 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1782 canonical form so that they will be recognized. */
1785 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1787 HOST_WIDE_INT offset
= 0;
1788 rtx base
= NULL_RTX
;
1789 rtx indx
= NULL_RTX
;
1790 rtx disp
= NULL_RTX
;
1792 bool pointer
= false;
1793 bool base_ptr
= false;
1794 bool indx_ptr
= false;
1795 bool literal_pool
= false;
1797 /* We may need to substitute the literal pool base register into the address
1798 below. However, at this point we do not know which register is going to
1799 be used as base, so we substitute the arg pointer register. This is going
1800 to be treated as holding a pointer below -- it shouldn't be used for any
1802 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1804 /* Decompose address into base + index + displacement. */
1806 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1809 else if (GET_CODE (addr
) == PLUS
)
1811 rtx op0
= XEXP (addr
, 0);
1812 rtx op1
= XEXP (addr
, 1);
1813 enum rtx_code code0
= GET_CODE (op0
);
1814 enum rtx_code code1
= GET_CODE (op1
);
1816 if (code0
== REG
|| code0
== UNSPEC
)
1818 if (code1
== REG
|| code1
== UNSPEC
)
1820 indx
= op0
; /* index + base */
1826 base
= op0
; /* base + displacement */
1831 else if (code0
== PLUS
)
1833 indx
= XEXP (op0
, 0); /* index + base + disp */
1834 base
= XEXP (op0
, 1);
1845 disp
= addr
; /* displacement */
1847 /* Extract integer part of displacement. */
1851 if (GET_CODE (disp
) == CONST_INT
)
1853 offset
= INTVAL (disp
);
1856 else if (GET_CODE (disp
) == CONST
1857 && GET_CODE (XEXP (disp
, 0)) == PLUS
1858 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1860 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1861 disp
= XEXP (XEXP (disp
, 0), 0);
1865 /* Strip off CONST here to avoid special case tests later. */
1866 if (disp
&& GET_CODE (disp
) == CONST
)
1867 disp
= XEXP (disp
, 0);
1869 /* We can convert literal pool addresses to
1870 displacements by basing them off the base register. */
1871 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1873 /* Either base or index must be free to hold the base register. */
1875 base
= fake_pool_base
, literal_pool
= true;
1877 indx
= fake_pool_base
, literal_pool
= true;
1881 /* Mark up the displacement. */
1882 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1883 UNSPEC_LTREL_OFFSET
);
1886 /* Validate base register. */
1889 if (GET_CODE (base
) == UNSPEC
)
1890 switch (XINT (base
, 1))
1894 disp
= gen_rtx_UNSPEC (Pmode
,
1895 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1896 UNSPEC_LTREL_OFFSET
);
1900 base
= XVECEXP (base
, 0, 1);
1903 case UNSPEC_LTREL_BASE
:
1904 if (XVECLEN (base
, 0) == 1)
1905 base
= fake_pool_base
, literal_pool
= true;
1907 base
= XVECEXP (base
, 0, 1);
1915 || (GET_MODE (base
) != SImode
1916 && GET_MODE (base
) != Pmode
))
1919 if (REGNO (base
) == STACK_POINTER_REGNUM
1920 || REGNO (base
) == FRAME_POINTER_REGNUM
1921 || ((reload_completed
|| reload_in_progress
)
1922 && frame_pointer_needed
1923 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1924 || REGNO (base
) == ARG_POINTER_REGNUM
1926 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1927 pointer
= base_ptr
= true;
1929 if ((reload_completed
|| reload_in_progress
)
1930 && base
== cfun
->machine
->base_reg
)
1931 pointer
= base_ptr
= literal_pool
= true;
1934 /* Validate index register. */
1937 if (GET_CODE (indx
) == UNSPEC
)
1938 switch (XINT (indx
, 1))
1942 disp
= gen_rtx_UNSPEC (Pmode
,
1943 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1944 UNSPEC_LTREL_OFFSET
);
1948 indx
= XVECEXP (indx
, 0, 1);
1951 case UNSPEC_LTREL_BASE
:
1952 if (XVECLEN (indx
, 0) == 1)
1953 indx
= fake_pool_base
, literal_pool
= true;
1955 indx
= XVECEXP (indx
, 0, 1);
1963 || (GET_MODE (indx
) != SImode
1964 && GET_MODE (indx
) != Pmode
))
1967 if (REGNO (indx
) == STACK_POINTER_REGNUM
1968 || REGNO (indx
) == FRAME_POINTER_REGNUM
1969 || ((reload_completed
|| reload_in_progress
)
1970 && frame_pointer_needed
1971 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1972 || REGNO (indx
) == ARG_POINTER_REGNUM
1974 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1975 pointer
= indx_ptr
= true;
1977 if ((reload_completed
|| reload_in_progress
)
1978 && indx
== cfun
->machine
->base_reg
)
1979 pointer
= indx_ptr
= literal_pool
= true;
1982 /* Prefer to use pointer as base, not index. */
1983 if (base
&& indx
&& !base_ptr
1984 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1991 /* Validate displacement. */
1994 /* If virtual registers are involved, the displacement will change later
1995 anyway as the virtual registers get eliminated. This could make a
1996 valid displacement invalid, but it is more likely to make an invalid
1997 displacement valid, because we sometimes access the register save area
1998 via negative offsets to one of those registers.
1999 Thus we don't check the displacement for validity here. If after
2000 elimination the displacement turns out to be invalid after all,
2001 this is fixed up by reload in any case. */
2002 if (base
!= arg_pointer_rtx
2003 && indx
!= arg_pointer_rtx
2004 && base
!= return_address_pointer_rtx
2005 && indx
!= return_address_pointer_rtx
2006 && base
!= frame_pointer_rtx
2007 && indx
!= frame_pointer_rtx
2008 && base
!= virtual_stack_vars_rtx
2009 && indx
!= virtual_stack_vars_rtx
)
2010 if (!DISP_IN_RANGE (offset
))
2015 /* All the special cases are pointers. */
2018 /* In the small-PIC case, the linker converts @GOT
2019 and @GOTNTPOFF offsets to possible displacements. */
2020 if (GET_CODE (disp
) == UNSPEC
2021 && (XINT (disp
, 1) == UNSPEC_GOT
2022 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2028 /* Accept pool label offsets. */
2029 else if (GET_CODE (disp
) == UNSPEC
2030 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2033 /* Accept literal pool references. */
2034 else if (GET_CODE (disp
) == UNSPEC
2035 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2037 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2040 /* If we have an offset, make sure it does not
2041 exceed the size of the constant pool entry. */
2042 rtx sym
= XVECEXP (disp
, 0, 0);
2043 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2046 orig_disp
= plus_constant (orig_disp
, offset
);
2061 out
->disp
= orig_disp
;
2062 out
->pointer
= pointer
;
2063 out
->literal_pool
= literal_pool
;
2069 /* Decompose a RTL expression OP for a shift count into its components,
2070 and return the base register in BASE and the offset in OFFSET.
2072 Return true if OP is a valid shift count, false if not. */
2075 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2077 HOST_WIDE_INT off
= 0;
2079 /* We can have an integer constant, an address register,
2080 or a sum of the two. */
2081 if (GET_CODE (op
) == CONST_INT
)
2086 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2088 off
= INTVAL (XEXP (op
, 1));
2091 while (op
&& GET_CODE (op
) == SUBREG
)
2092 op
= SUBREG_REG (op
);
2094 if (op
&& GET_CODE (op
) != REG
)
2106 /* Return true if CODE is a valid address without index. */
2109 s390_legitimate_address_without_index_p (rtx op
)
2111 struct s390_address addr
;
2113 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2122 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2123 and return these parts in SYMREF and ADDEND. You can pass NULL in
2124 SYMREF and/or ADDEND if you are not interested in these values.
2125 Literal pool references are *not* considered symbol references. */
2128 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2130 HOST_WIDE_INT tmpaddend
= 0;
2132 if (GET_CODE (addr
) == CONST
)
2133 addr
= XEXP (addr
, 0);
2135 if (GET_CODE (addr
) == PLUS
)
2137 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2138 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2139 && CONST_INT_P (XEXP (addr
, 1)))
2141 tmpaddend
= INTVAL (XEXP (addr
, 1));
2142 addr
= XEXP (addr
, 0);
2148 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2154 *addend
= tmpaddend
;
2160 /* Return true if the address in OP is valid for constraint letter C
2161 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2162 pool MEMs should be accepted. Only the Q, R, S, T constraint
2163 letters are allowed for C. */
2166 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2168 struct s390_address addr
;
2169 bool decomposed
= false;
2171 /* This check makes sure that no symbolic address (except literal
2172 pool references) are accepted by the R or T constraints. */
2173 if (s390_symref_operand_p (op
, NULL
, NULL
))
2176 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2179 if (!s390_decompose_address (op
, &addr
))
2181 if (addr
.literal_pool
)
2188 case 'Q': /* no index short displacement */
2189 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2193 if (!s390_short_displacement (addr
.disp
))
2197 case 'R': /* with index short displacement */
2198 if (TARGET_LONG_DISPLACEMENT
)
2200 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2202 if (!s390_short_displacement (addr
.disp
))
2205 /* Any invalid address here will be fixed up by reload,
2206 so accept it for the most generic constraint. */
2209 case 'S': /* no index long displacement */
2210 if (!TARGET_LONG_DISPLACEMENT
)
2212 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2216 if (s390_short_displacement (addr
.disp
))
2220 case 'T': /* with index long displacement */
2221 if (!TARGET_LONG_DISPLACEMENT
)
2223 /* Any invalid address here will be fixed up by reload,
2224 so accept it for the most generic constraint. */
2225 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2226 && s390_short_displacement (addr
.disp
))
2236 /* Evaluates constraint strings described by the regular expression
2237 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2238 the constraint given in STR, or 0 else. */
2241 s390_mem_constraint (const char *str
, rtx op
)
2248 /* Check for offsettable variants of memory constraints. */
2249 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2251 if ((reload_completed
|| reload_in_progress
)
2252 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2254 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2256 /* Check for non-literal-pool variants of memory constraints. */
2259 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2264 if (GET_CODE (op
) != MEM
)
2266 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2268 return (s390_check_qrst_address ('Q', op
, true)
2269 || s390_check_qrst_address ('R', op
, true));
2271 return (s390_check_qrst_address ('S', op
, true)
2272 || s390_check_qrst_address ('T', op
, true));
2274 /* Simply check for the basic form of a shift count. Reload will
2275 take care of making sure we have a proper base register. */
2276 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2280 return s390_check_qrst_address (str
[1], op
, true);
2288 /* Evaluates constraint strings starting with letter O. Input
2289 parameter C is the second letter following the "O" in the constraint
2290 string. Returns 1 if VALUE meets the respective constraint and 0
2294 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2302 return trunc_int_for_mode (value
, SImode
) == value
;
2306 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2309 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2317 /* Evaluates constraint strings starting with letter N. Parameter STR
2318 contains the letters following letter "N" in the constraint string.
2319 Returns true if VALUE matches the constraint. */
2322 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2324 enum machine_mode mode
, part_mode
;
2326 int part
, part_goal
;
2332 part_goal
= str
[0] - '0';
2376 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2379 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2382 if (part_goal
!= -1 && part_goal
!= part
)
2389 /* Returns true if the input parameter VALUE is a float zero. */
2392 s390_float_const_zero_p (rtx value
)
2394 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2395 && value
== CONST0_RTX (GET_MODE (value
)));
2399 /* Compute a (partial) cost for rtx X. Return true if the complete
2400 cost has been computed, and false if subexpressions should be
2401 scanned. In either case, *TOTAL contains the cost result.
2402 CODE contains GET_CODE (x), OUTER_CODE contains the code
2403 of the superexpression of x. */
2406 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2407 bool speed ATTRIBUTE_UNUSED
)
2430 *total
= COSTS_N_INSNS (1);
2435 /* Check for multiply and add. */
2436 if ((GET_MODE (x
) == DFmode
|| GET_MODE (x
) == SFmode
)
2437 && GET_CODE (XEXP (x
, 0)) == MULT
2438 && TARGET_HARD_FLOAT
&& TARGET_FUSED_MADD
)
2440 /* This is the multiply and add case. */
2441 if (GET_MODE (x
) == DFmode
)
2442 *total
= s390_cost
->madbr
;
2444 *total
= s390_cost
->maebr
;
2445 *total
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), MULT
, speed
)
2446 + rtx_cost (XEXP (XEXP (x
, 0), 1), MULT
, speed
)
2447 + rtx_cost (XEXP (x
, 1), (enum rtx_code
) code
, speed
));
2448 return true; /* Do not do an additional recursive descent. */
2450 *total
= COSTS_N_INSNS (1);
2454 switch (GET_MODE (x
))
2458 rtx left
= XEXP (x
, 0);
2459 rtx right
= XEXP (x
, 1);
2460 if (GET_CODE (right
) == CONST_INT
2461 && CONST_OK_FOR_K (INTVAL (right
)))
2462 *total
= s390_cost
->mhi
;
2463 else if (GET_CODE (left
) == SIGN_EXTEND
)
2464 *total
= s390_cost
->mh
;
2466 *total
= s390_cost
->ms
; /* msr, ms, msy */
2471 rtx left
= XEXP (x
, 0);
2472 rtx right
= XEXP (x
, 1);
2475 if (GET_CODE (right
) == CONST_INT
2476 && CONST_OK_FOR_K (INTVAL (right
)))
2477 *total
= s390_cost
->mghi
;
2478 else if (GET_CODE (left
) == SIGN_EXTEND
)
2479 *total
= s390_cost
->msgf
;
2481 *total
= s390_cost
->msg
; /* msgr, msg */
2483 else /* TARGET_31BIT */
2485 if (GET_CODE (left
) == SIGN_EXTEND
2486 && GET_CODE (right
) == SIGN_EXTEND
)
2487 /* mulsidi case: mr, m */
2488 *total
= s390_cost
->m
;
2489 else if (GET_CODE (left
) == ZERO_EXTEND
2490 && GET_CODE (right
) == ZERO_EXTEND
2491 && TARGET_CPU_ZARCH
)
2492 /* umulsidi case: ml, mlr */
2493 *total
= s390_cost
->ml
;
2495 /* Complex calculation is required. */
2496 *total
= COSTS_N_INSNS (40);
2502 *total
= s390_cost
->mult_df
;
2505 *total
= s390_cost
->mxbr
;
2514 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2515 *total
= s390_cost
->dlgr
;
2516 else if (GET_MODE (x
) == DImode
)
2518 rtx right
= XEXP (x
, 1);
2519 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2520 *total
= s390_cost
->dlr
;
2521 else /* 64 by 64 bit division */
2522 *total
= s390_cost
->dlgr
;
2524 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2525 *total
= s390_cost
->dlr
;
2530 if (GET_MODE (x
) == DImode
)
2532 rtx right
= XEXP (x
, 1);
2533 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2535 *total
= s390_cost
->dsgfr
;
2537 *total
= s390_cost
->dr
;
2538 else /* 64 by 64 bit division */
2539 *total
= s390_cost
->dsgr
;
2541 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2542 *total
= s390_cost
->dlr
;
2543 else if (GET_MODE (x
) == SFmode
)
2545 *total
= s390_cost
->debr
;
2547 else if (GET_MODE (x
) == DFmode
)
2549 *total
= s390_cost
->ddbr
;
2551 else if (GET_MODE (x
) == TFmode
)
2553 *total
= s390_cost
->dxbr
;
2558 if (GET_MODE (x
) == SFmode
)
2559 *total
= s390_cost
->sqebr
;
2560 else if (GET_MODE (x
) == DFmode
)
2561 *total
= s390_cost
->sqdbr
;
2563 *total
= s390_cost
->sqxbr
;
2568 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2569 || outer_code
== PLUS
|| outer_code
== MINUS
2570 || outer_code
== COMPARE
)
2575 *total
= COSTS_N_INSNS (1);
2576 if (GET_CODE (XEXP (x
, 0)) == AND
2577 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2578 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2580 rtx op0
= XEXP (XEXP (x
, 0), 0);
2581 rtx op1
= XEXP (XEXP (x
, 0), 1);
2582 rtx op2
= XEXP (x
, 1);
2584 if (memory_operand (op0
, GET_MODE (op0
))
2585 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2587 if (register_operand (op0
, GET_MODE (op0
))
2588 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2598 /* Return the cost of an address rtx ADDR. */
2601 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2603 struct s390_address ad
;
2604 if (!s390_decompose_address (addr
, &ad
))
2607 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2610 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2611 otherwise return 0. */
2614 tls_symbolic_operand (rtx op
)
2616 if (GET_CODE (op
) != SYMBOL_REF
)
2618 return SYMBOL_REF_TLS_MODEL (op
);
2621 /* Split DImode access register reference REG (on 64-bit) into its constituent
2622 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2623 gen_highpart cannot be used as they assume all registers are word-sized,
2624 while our access registers have only half that size. */
2627 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2629 gcc_assert (TARGET_64BIT
);
2630 gcc_assert (ACCESS_REG_P (reg
));
2631 gcc_assert (GET_MODE (reg
) == DImode
);
2632 gcc_assert (!(REGNO (reg
) & 1));
2634 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2635 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2638 /* Return true if OP contains a symbol reference */
2641 symbolic_reference_mentioned_p (rtx op
)
2646 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2649 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2650 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2656 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2657 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2661 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2668 /* Return true if OP contains a reference to a thread-local symbol. */
2671 tls_symbolic_reference_mentioned_p (rtx op
)
2676 if (GET_CODE (op
) == SYMBOL_REF
)
2677 return tls_symbolic_operand (op
);
2679 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2680 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2686 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2687 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2691 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2699 /* Return true if OP is a legitimate general operand when
2700 generating PIC code. It is given that flag_pic is on
2701 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2704 legitimate_pic_operand_p (rtx op
)
2706 /* Accept all non-symbolic constants. */
2707 if (!SYMBOLIC_CONST (op
))
2710 /* Reject everything else; must be handled
2711 via emit_symbolic_move. */
2715 /* Returns true if the constant value OP is a legitimate general operand.
2716 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2719 legitimate_constant_p (rtx op
)
2721 /* Accept all non-symbolic constants. */
2722 if (!SYMBOLIC_CONST (op
))
2725 /* Accept immediate LARL operands. */
2726 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2729 /* Thread-local symbols are never legal constants. This is
2730 so that emit_call knows that computing such addresses
2731 might require a function call. */
2732 if (TLS_SYMBOLIC_CONST (op
))
2735 /* In the PIC case, symbolic constants must *not* be
2736 forced into the literal pool. We accept them here,
2737 so that they will be handled by emit_symbolic_move. */
2741 /* All remaining non-PIC symbolic constants are
2742 forced into the literal pool. */
2746 /* Determine if it's legal to put X into the constant pool. This
2747 is not possible if X contains the address of a symbol that is
2748 not constant (TLS) or not known at final link time (PIC). */
2751 s390_cannot_force_const_mem (rtx x
)
2753 switch (GET_CODE (x
))
2757 /* Accept all non-symbolic constants. */
2761 /* Labels are OK iff we are non-PIC. */
2762 return flag_pic
!= 0;
2765 /* 'Naked' TLS symbol references are never OK,
2766 non-TLS symbols are OK iff we are non-PIC. */
2767 if (tls_symbolic_operand (x
))
2770 return flag_pic
!= 0;
2773 return s390_cannot_force_const_mem (XEXP (x
, 0));
2776 return s390_cannot_force_const_mem (XEXP (x
, 0))
2777 || s390_cannot_force_const_mem (XEXP (x
, 1));
2780 switch (XINT (x
, 1))
2782 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2783 case UNSPEC_LTREL_OFFSET
:
2791 case UNSPEC_GOTNTPOFF
:
2792 case UNSPEC_INDNTPOFF
:
2795 /* If the literal pool shares the code section, be put
2796 execute template placeholders into the pool as well. */
2798 return TARGET_CPU_ZARCH
;
2810 /* Returns true if the constant value OP is a legitimate general
2811 operand during and after reload. The difference to
2812 legitimate_constant_p is that this function will not accept
2813 a constant that would need to be forced to the literal pool
2814 before it can be used as operand.
2815 This function accepts all constants which can be loaded directly
2819 legitimate_reload_constant_p (rtx op
)
2821 /* Accept la(y) operands. */
2822 if (GET_CODE (op
) == CONST_INT
2823 && DISP_IN_RANGE (INTVAL (op
)))
2826 /* Accept l(g)hi/l(g)fi operands. */
2827 if (GET_CODE (op
) == CONST_INT
2828 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2831 /* Accept lliXX operands. */
2833 && GET_CODE (op
) == CONST_INT
2834 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2835 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2839 && GET_CODE (op
) == CONST_INT
2840 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2841 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2844 /* Accept larl operands. */
2845 if (TARGET_CPU_ZARCH
2846 && larl_operand (op
, VOIDmode
))
2849 /* Accept floating-point zero operands that fit into a single GPR. */
2850 if (GET_CODE (op
) == CONST_DOUBLE
2851 && s390_float_const_zero_p (op
)
2852 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2855 /* Accept double-word operands that can be split. */
2856 if (GET_CODE (op
) == CONST_INT
2857 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2859 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2860 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2861 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2862 return legitimate_reload_constant_p (hi
)
2863 && legitimate_reload_constant_p (lo
);
2866 /* Everything else cannot be handled without reload. */
2870 /* Returns true if the constant value OP is a legitimate fp operand
2871 during and after reload.
2872 This function accepts all constants which can be loaded directly
2876 legitimate_reload_fp_constant_p (rtx op
)
2878 /* Accept floating-point zero operands if the load zero instruction
2881 && GET_CODE (op
) == CONST_DOUBLE
2882 && s390_float_const_zero_p (op
))
2888 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2889 return the class of reg to actually use. */
2892 s390_preferred_reload_class (rtx op
, enum reg_class rclass
)
2894 switch (GET_CODE (op
))
2896 /* Constants we cannot reload into general registers
2897 must be forced into the literal pool. */
2900 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2901 && legitimate_reload_constant_p (op
))
2902 return GENERAL_REGS
;
2903 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2904 && legitimate_reload_constant_p (op
))
2906 else if (reg_class_subset_p (FP_REGS
, rclass
)
2907 && legitimate_reload_fp_constant_p (op
))
2911 /* If a symbolic constant or a PLUS is reloaded,
2912 it is most likely being used as an address, so
2913 prefer ADDR_REGS. If 'class' is not a superset
2914 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2919 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2931 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2932 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2936 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2938 HOST_WIDE_INT addend
;
2941 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2944 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
2945 && !(addend
& (alignment
- 1)));
2948 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2949 operand SCRATCH is used to reload the even part of the address and
2953 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
2955 HOST_WIDE_INT addend
;
2958 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2962 /* Easy case. The addend is even so larl will do fine. */
2963 emit_move_insn (reg
, addr
);
2966 /* We can leave the scratch register untouched if the target
2967 register is a valid base register. */
2968 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
2969 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
2972 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
2973 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
2976 emit_move_insn (scratch
,
2977 gen_rtx_CONST (Pmode
,
2978 gen_rtx_PLUS (Pmode
, symref
,
2979 GEN_INT (addend
- 1))));
2981 emit_move_insn (scratch
, symref
);
2983 /* Increment the address using la in order to avoid clobbering cc. */
2984 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
2988 /* Generate what is necessary to move between REG and MEM using
2989 SCRATCH. The direction is given by TOMEM. */
2992 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
2994 /* Reload might have pulled a constant out of the literal pool.
2995 Force it back in. */
2996 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
2997 || GET_CODE (mem
) == CONST
)
2998 mem
= force_const_mem (GET_MODE (reg
), mem
);
3000 gcc_assert (MEM_P (mem
));
3002 /* For a load from memory we can leave the scratch register
3003 untouched if the target register is a valid base register. */
3005 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3006 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3007 && GET_MODE (reg
) == GET_MODE (scratch
))
3010 /* Load address into scratch register. Since we can't have a
3011 secondary reload for a secondary reload we have to cover the case
3012 where larl would need a secondary reload here as well. */
3013 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3015 /* Now we can use a standard load/store to do the move. */
3017 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3019 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3022 /* Inform reload about cases where moving X with a mode MODE to a register in
3023 RCLASS requires an extra scratch or immediate register. Return the class
3024 needed for the immediate register. */
3027 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3028 enum machine_mode mode
, secondary_reload_info
*sri
)
3030 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3032 /* Intermediate register needed. */
3033 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3034 return GENERAL_REGS
;
3038 /* On z10 several optimizer steps may generate larl operands with
3041 && s390_symref_operand_p (x
, NULL
, NULL
)
3043 && !s390_check_symref_alignment (x
, 2))
3044 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3045 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3047 /* On z10 we need a scratch register when moving QI, TI or floating
3048 point mode values from or to a memory location with a SYMBOL_REF
3049 or if the symref addend of a SI or DI move is not aligned to the
3050 width of the access. */
3052 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3053 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3054 || (!TARGET_ZARCH
&& mode
== DImode
)
3055 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3056 && (!s390_check_symref_alignment (XEXP (x
, 0),
3057 GET_MODE_SIZE (mode
))))))
3059 #define __SECONDARY_RELOAD_CASE(M,m) \
3062 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3063 CODE_FOR_reload##m##di_tomem_z10; \
3065 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3066 CODE_FOR_reload##m##si_tomem_z10; \
3069 switch (GET_MODE (x
))
3071 __SECONDARY_RELOAD_CASE (QI
, qi
);
3072 __SECONDARY_RELOAD_CASE (HI
, hi
);
3073 __SECONDARY_RELOAD_CASE (SI
, si
);
3074 __SECONDARY_RELOAD_CASE (DI
, di
);
3075 __SECONDARY_RELOAD_CASE (TI
, ti
);
3076 __SECONDARY_RELOAD_CASE (SF
, sf
);
3077 __SECONDARY_RELOAD_CASE (DF
, df
);
3078 __SECONDARY_RELOAD_CASE (TF
, tf
);
3079 __SECONDARY_RELOAD_CASE (SD
, sd
);
3080 __SECONDARY_RELOAD_CASE (DD
, dd
);
3081 __SECONDARY_RELOAD_CASE (TD
, td
);
3086 #undef __SECONDARY_RELOAD_CASE
3090 /* We need a scratch register when loading a PLUS expression which
3091 is not a legitimate operand of the LOAD ADDRESS instruction. */
3092 if (in_p
&& s390_plus_operand (x
, mode
))
3093 sri
->icode
= (TARGET_64BIT
?
3094 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3096 /* Performing a multiword move from or to memory we have to make sure the
3097 second chunk in memory is addressable without causing a displacement
3098 overflow. If that would be the case we calculate the address in
3099 a scratch register. */
3101 && GET_CODE (XEXP (x
, 0)) == PLUS
3102 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3103 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3104 + GET_MODE_SIZE (mode
) - 1))
3106 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3107 in a s_operand address since we may fallback to lm/stm. So we only
3108 have to care about overflows in the b+i+d case. */
3109 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3110 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3111 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3112 /* For FP_REGS no lm/stm is available so this check is triggered
3113 for displacement overflows in b+i+d and b+d like addresses. */
3114 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3115 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3118 sri
->icode
= (TARGET_64BIT
?
3119 CODE_FOR_reloaddi_nonoffmem_in
:
3120 CODE_FOR_reloadsi_nonoffmem_in
);
3122 sri
->icode
= (TARGET_64BIT
?
3123 CODE_FOR_reloaddi_nonoffmem_out
:
3124 CODE_FOR_reloadsi_nonoffmem_out
);
3128 /* A scratch address register is needed when a symbolic constant is
3129 copied to r0 compiling with -fPIC. In other cases the target
3130 register might be used as temporary (see legitimize_pic_address). */
3131 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3132 sri
->icode
= (TARGET_64BIT
?
3133 CODE_FOR_reloaddi_PIC_addr
:
3134 CODE_FOR_reloadsi_PIC_addr
);
3136 /* Either scratch or no register needed. */
3140 /* Generate code to load SRC, which is PLUS that is not a
3141 legitimate operand for the LA instruction, into TARGET.
3142 SCRATCH may be used as scratch register. */
3145 s390_expand_plus_operand (rtx target
, rtx src
,
3149 struct s390_address ad
;
3151 /* src must be a PLUS; get its two operands. */
3152 gcc_assert (GET_CODE (src
) == PLUS
);
3153 gcc_assert (GET_MODE (src
) == Pmode
);
3155 /* Check if any of the two operands is already scheduled
3156 for replacement by reload. This can happen e.g. when
3157 float registers occur in an address. */
3158 sum1
= find_replacement (&XEXP (src
, 0));
3159 sum2
= find_replacement (&XEXP (src
, 1));
3160 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3162 /* If the address is already strictly valid, there's nothing to do. */
3163 if (!s390_decompose_address (src
, &ad
)
3164 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3165 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3167 /* Otherwise, one of the operands cannot be an address register;
3168 we reload its value into the scratch register. */
3169 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3171 emit_move_insn (scratch
, sum1
);
3174 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3176 emit_move_insn (scratch
, sum2
);
3180 /* According to the way these invalid addresses are generated
3181 in reload.c, it should never happen (at least on s390) that
3182 *neither* of the PLUS components, after find_replacements
3183 was applied, is an address register. */
3184 if (sum1
== scratch
&& sum2
== scratch
)
3190 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3193 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3194 is only ever performed on addresses, so we can mark the
3195 sum as legitimate for LA in any case. */
3196 s390_load_address (target
, src
);
3200 /* Return true if ADDR is a valid memory address.
3201 STRICT specifies whether strict register checking applies. */
3204 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3206 struct s390_address ad
;
3209 && larl_operand (addr
, VOIDmode
)
3210 && (mode
== VOIDmode
3211 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3214 if (!s390_decompose_address (addr
, &ad
))
3219 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3222 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3228 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3229 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3233 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3234 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3240 /* Return true if OP is a valid operand for the LA instruction.
3241 In 31-bit, we need to prove that the result is used as an
3242 address, as LA performs only a 31-bit addition. */
3245 legitimate_la_operand_p (rtx op
)
3247 struct s390_address addr
;
3248 if (!s390_decompose_address (op
, &addr
))
3251 return (TARGET_64BIT
|| addr
.pointer
);
3254 /* Return true if it is valid *and* preferable to use LA to
3255 compute the sum of OP1 and OP2. */
3258 preferred_la_operand_p (rtx op1
, rtx op2
)
3260 struct s390_address addr
;
3262 if (op2
!= const0_rtx
)
3263 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3265 if (!s390_decompose_address (op1
, &addr
))
3267 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3269 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3272 /* Avoid LA instructions with index register on z196; it is
3273 preferable to use regular add instructions when possible. */
3274 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3277 if (!TARGET_64BIT
&& !addr
.pointer
)
3283 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3284 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3290 /* Emit a forced load-address operation to load SRC into DST.
3291 This will use the LOAD ADDRESS instruction even in situations
3292 where legitimate_la_operand_p (SRC) returns false. */
3295 s390_load_address (rtx dst
, rtx src
)
3298 emit_move_insn (dst
, src
);
3300 emit_insn (gen_force_la_31 (dst
, src
));
3303 /* Return a legitimate reference for ORIG (an address) using the
3304 register REG. If REG is 0, a new pseudo is generated.
3306 There are two types of references that must be handled:
3308 1. Global data references must load the address from the GOT, via
3309 the PIC reg. An insn is emitted to do this load, and the reg is
3312 2. Static data references, constant pool addresses, and code labels
3313 compute the address as an offset from the GOT, whose base is in
3314 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3315 differentiate them from global data objects. The returned
3316 address is the PIC reg + an unspec constant.
3318 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3319 reg also appears in the address. */
3322 legitimize_pic_address (rtx orig
, rtx reg
)
3328 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3330 if (GET_CODE (addr
) == LABEL_REF
3331 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3333 /* This is a local symbol. */
3334 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3336 /* Access local symbols PC-relative via LARL.
3337 This is the same as in the non-PIC case, so it is
3338 handled automatically ... */
3342 /* Access local symbols relative to the GOT. */
3344 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3346 if (reload_in_progress
|| reload_completed
)
3347 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3349 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3350 addr
= gen_rtx_CONST (Pmode
, addr
);
3351 addr
= force_const_mem (Pmode
, addr
);
3352 emit_move_insn (temp
, addr
);
3354 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3357 s390_load_address (reg
, new_rtx
);
3362 else if (GET_CODE (addr
) == SYMBOL_REF
)
3365 reg
= gen_reg_rtx (Pmode
);
3369 /* Assume GOT offset < 4k. This is handled the same way
3370 in both 31- and 64-bit code (@GOT). */
3372 if (reload_in_progress
|| reload_completed
)
3373 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3375 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3376 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3377 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3378 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3379 emit_move_insn (reg
, new_rtx
);
3382 else if (TARGET_CPU_ZARCH
)
3384 /* If the GOT offset might be >= 4k, we determine the position
3385 of the GOT entry via a PC-relative LARL (@GOTENT). */
3387 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3389 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3390 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3392 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3393 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3394 emit_move_insn (temp
, new_rtx
);
3396 new_rtx
= gen_const_mem (Pmode
, temp
);
3397 emit_move_insn (reg
, new_rtx
);
3402 /* If the GOT offset might be >= 4k, we have to load it
3403 from the literal pool (@GOT). */
3405 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3407 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3408 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3410 if (reload_in_progress
|| reload_completed
)
3411 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3413 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3414 addr
= gen_rtx_CONST (Pmode
, addr
);
3415 addr
= force_const_mem (Pmode
, addr
);
3416 emit_move_insn (temp
, addr
);
3418 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3419 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3420 emit_move_insn (reg
, new_rtx
);
3426 if (GET_CODE (addr
) == CONST
)
3428 addr
= XEXP (addr
, 0);
3429 if (GET_CODE (addr
) == UNSPEC
)
3431 gcc_assert (XVECLEN (addr
, 0) == 1);
3432 switch (XINT (addr
, 1))
3434 /* If someone moved a GOT-relative UNSPEC
3435 out of the literal pool, force them back in. */
3438 new_rtx
= force_const_mem (Pmode
, orig
);
3441 /* @GOT is OK as is if small. */
3444 new_rtx
= force_const_mem (Pmode
, orig
);
3447 /* @GOTENT is OK as is. */
3451 /* @PLT is OK as is on 64-bit, must be converted to
3452 GOT-relative @PLTOFF on 31-bit. */
3454 if (!TARGET_CPU_ZARCH
)
3456 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3458 if (reload_in_progress
|| reload_completed
)
3459 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3461 addr
= XVECEXP (addr
, 0, 0);
3462 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3464 addr
= gen_rtx_CONST (Pmode
, addr
);
3465 addr
= force_const_mem (Pmode
, addr
);
3466 emit_move_insn (temp
, addr
);
3468 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3471 s390_load_address (reg
, new_rtx
);
3477 /* Everything else cannot happen. */
3483 gcc_assert (GET_CODE (addr
) == PLUS
);
3485 if (GET_CODE (addr
) == PLUS
)
3487 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3489 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3490 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3492 /* Check first to see if this is a constant offset
3493 from a local symbol reference. */
3494 if ((GET_CODE (op0
) == LABEL_REF
3495 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3496 && GET_CODE (op1
) == CONST_INT
)
3498 if (TARGET_CPU_ZARCH
3499 && larl_operand (op0
, VOIDmode
)
3500 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3501 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3503 if (INTVAL (op1
) & 1)
3505 /* LARL can't handle odd offsets, so emit a
3506 pair of LARL and LA. */
3507 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3509 if (!DISP_IN_RANGE (INTVAL (op1
)))
3511 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3512 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3513 op0
= gen_rtx_CONST (Pmode
, op0
);
3517 emit_move_insn (temp
, op0
);
3518 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3522 s390_load_address (reg
, new_rtx
);
3528 /* If the offset is even, we can just use LARL.
3529 This will happen automatically. */
3534 /* Access local symbols relative to the GOT. */
3536 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3538 if (reload_in_progress
|| reload_completed
)
3539 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3541 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3543 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3544 addr
= gen_rtx_CONST (Pmode
, addr
);
3545 addr
= force_const_mem (Pmode
, addr
);
3546 emit_move_insn (temp
, addr
);
3548 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3551 s390_load_address (reg
, new_rtx
);
3557 /* Now, check whether it is a GOT relative symbol plus offset
3558 that was pulled out of the literal pool. Force it back in. */
3560 else if (GET_CODE (op0
) == UNSPEC
3561 && GET_CODE (op1
) == CONST_INT
3562 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3564 gcc_assert (XVECLEN (op0
, 0) == 1);
3566 new_rtx
= force_const_mem (Pmode
, orig
);
3569 /* Otherwise, compute the sum. */
3572 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3573 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3574 base
== reg
? NULL_RTX
: reg
);
3575 if (GET_CODE (new_rtx
) == CONST_INT
)
3576 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3579 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3581 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3582 new_rtx
= XEXP (new_rtx
, 1);
3584 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3587 if (GET_CODE (new_rtx
) == CONST
)
3588 new_rtx
= XEXP (new_rtx
, 0);
3589 new_rtx
= force_operand (new_rtx
, 0);
3596 /* Load the thread pointer into a register. */
3599 s390_get_thread_pointer (void)
3601 rtx tp
= gen_reg_rtx (Pmode
);
3603 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3604 mark_reg_pointer (tp
, BITS_PER_WORD
);
3609 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3610 in s390_tls_symbol which always refers to __tls_get_offset.
3611 The returned offset is written to RESULT_REG and an USE rtx is
3612 generated for TLS_CALL. */
3614 static GTY(()) rtx s390_tls_symbol
;
3617 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3621 gcc_assert (flag_pic
);
3623 if (!s390_tls_symbol
)
3624 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3626 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3627 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3629 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3630 RTL_CONST_CALL_P (insn
) = 1;
3633 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3634 this (thread-local) address. REG may be used as temporary. */
3637 legitimize_tls_address (rtx addr
, rtx reg
)
3639 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3641 if (GET_CODE (addr
) == SYMBOL_REF
)
3642 switch (tls_symbolic_operand (addr
))
3644 case TLS_MODEL_GLOBAL_DYNAMIC
:
3646 r2
= gen_rtx_REG (Pmode
, 2);
3647 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3648 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3649 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3650 emit_move_insn (r2
, new_rtx
);
3651 s390_emit_tls_call_insn (r2
, tls_call
);
3652 insn
= get_insns ();
3655 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3656 temp
= gen_reg_rtx (Pmode
);
3657 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3659 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3662 s390_load_address (reg
, new_rtx
);
3667 case TLS_MODEL_LOCAL_DYNAMIC
:
3669 r2
= gen_rtx_REG (Pmode
, 2);
3670 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3671 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3672 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3673 emit_move_insn (r2
, new_rtx
);
3674 s390_emit_tls_call_insn (r2
, tls_call
);
3675 insn
= get_insns ();
3678 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3679 temp
= gen_reg_rtx (Pmode
);
3680 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3682 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3683 base
= gen_reg_rtx (Pmode
);
3684 s390_load_address (base
, new_rtx
);
3686 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3687 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3688 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3689 temp
= gen_reg_rtx (Pmode
);
3690 emit_move_insn (temp
, new_rtx
);
3692 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3695 s390_load_address (reg
, new_rtx
);
3700 case TLS_MODEL_INITIAL_EXEC
:
3703 /* Assume GOT offset < 4k. This is handled the same way
3704 in both 31- and 64-bit code. */
3706 if (reload_in_progress
|| reload_completed
)
3707 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3709 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3710 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3711 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3712 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3713 temp
= gen_reg_rtx (Pmode
);
3714 emit_move_insn (temp
, new_rtx
);
3716 else if (TARGET_CPU_ZARCH
)
3718 /* If the GOT offset might be >= 4k, we determine the position
3719 of the GOT entry via a PC-relative LARL. */
3721 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3722 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3723 temp
= gen_reg_rtx (Pmode
);
3724 emit_move_insn (temp
, new_rtx
);
3726 new_rtx
= gen_const_mem (Pmode
, temp
);
3727 temp
= gen_reg_rtx (Pmode
);
3728 emit_move_insn (temp
, new_rtx
);
3732 /* If the GOT offset might be >= 4k, we have to load it
3733 from the literal pool. */
3735 if (reload_in_progress
|| reload_completed
)
3736 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3738 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3739 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3740 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3741 temp
= gen_reg_rtx (Pmode
);
3742 emit_move_insn (temp
, new_rtx
);
3744 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3745 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3747 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3748 temp
= gen_reg_rtx (Pmode
);
3749 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3753 /* In position-dependent code, load the absolute address of
3754 the GOT entry from the literal pool. */
3756 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3757 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3758 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3759 temp
= gen_reg_rtx (Pmode
);
3760 emit_move_insn (temp
, new_rtx
);
3763 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3764 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3765 temp
= gen_reg_rtx (Pmode
);
3766 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3769 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3772 s390_load_address (reg
, new_rtx
);
3777 case TLS_MODEL_LOCAL_EXEC
:
3778 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3779 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3780 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3781 temp
= gen_reg_rtx (Pmode
);
3782 emit_move_insn (temp
, new_rtx
);
3784 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3787 s390_load_address (reg
, new_rtx
);
3796 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3798 switch (XINT (XEXP (addr
, 0), 1))
3800 case UNSPEC_INDNTPOFF
:
3801 gcc_assert (TARGET_CPU_ZARCH
);
3810 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3811 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3813 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3814 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3815 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3817 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3818 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3819 new_rtx
= force_operand (new_rtx
, 0);
3823 gcc_unreachable (); /* for now ... */
3828 /* Emit insns making the address in operands[1] valid for a standard
3829 move to operands[0]. operands[1] is replaced by an address which
3830 should be used instead of the former RTX to emit the move
3834 emit_symbolic_move (rtx
*operands
)
3836 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3838 if (GET_CODE (operands
[0]) == MEM
)
3839 operands
[1] = force_reg (Pmode
, operands
[1]);
3840 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3841 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3843 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3846 /* Try machine-dependent ways of modifying an illegitimate address X
3847 to be legitimate. If we find one, return the new, valid address.
3849 OLDX is the address as it was before break_out_memory_refs was called.
3850 In some cases it is useful to look at this to decide what needs to be done.
3852 MODE is the mode of the operand pointed to by X.
3854 When -fpic is used, special handling is needed for symbolic references.
3855 See comments by legitimize_pic_address for details. */
3858 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3859 enum machine_mode mode ATTRIBUTE_UNUSED
)
3861 rtx constant_term
= const0_rtx
;
3863 if (TLS_SYMBOLIC_CONST (x
))
3865 x
= legitimize_tls_address (x
, 0);
3867 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3870 else if (GET_CODE (x
) == PLUS
3871 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3872 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3878 if (SYMBOLIC_CONST (x
)
3879 || (GET_CODE (x
) == PLUS
3880 && (SYMBOLIC_CONST (XEXP (x
, 0))
3881 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3882 x
= legitimize_pic_address (x
, 0);
3884 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3888 x
= eliminate_constant_term (x
, &constant_term
);
3890 /* Optimize loading of large displacements by splitting them
3891 into the multiple of 4K and the rest; this allows the
3892 former to be CSE'd if possible.
3894 Don't do this if the displacement is added to a register
3895 pointing into the stack frame, as the offsets will
3896 change later anyway. */
3898 if (GET_CODE (constant_term
) == CONST_INT
3899 && !TARGET_LONG_DISPLACEMENT
3900 && !DISP_IN_RANGE (INTVAL (constant_term
))
3901 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3903 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3904 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3906 rtx temp
= gen_reg_rtx (Pmode
);
3907 rtx val
= force_operand (GEN_INT (upper
), temp
);
3909 emit_move_insn (temp
, val
);
3911 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3912 constant_term
= GEN_INT (lower
);
3915 if (GET_CODE (x
) == PLUS
)
3917 if (GET_CODE (XEXP (x
, 0)) == REG
)
3919 rtx temp
= gen_reg_rtx (Pmode
);
3920 rtx val
= force_operand (XEXP (x
, 1), temp
);
3922 emit_move_insn (temp
, val
);
3924 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3927 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3929 rtx temp
= gen_reg_rtx (Pmode
);
3930 rtx val
= force_operand (XEXP (x
, 0), temp
);
3932 emit_move_insn (temp
, val
);
3934 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3938 if (constant_term
!= const0_rtx
)
3939 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3944 /* Try a machine-dependent way of reloading an illegitimate address AD
3945 operand. If we find one, push the reload and and return the new address.
3947 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3948 and TYPE is the reload type of the current reload. */
3951 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3952 int opnum
, int type
)
3954 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3957 if (GET_CODE (ad
) == PLUS
)
3959 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3960 XEXP (ad
, 0), XEXP (ad
, 1));
3965 if (GET_CODE (ad
) == PLUS
3966 && GET_CODE (XEXP (ad
, 0)) == REG
3967 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3968 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3970 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3971 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3972 rtx cst
, tem
, new_rtx
;
3974 cst
= GEN_INT (upper
);
3975 if (!legitimate_reload_constant_p (cst
))
3976 cst
= force_const_mem (Pmode
, cst
);
3978 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3979 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3981 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3982 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3983 opnum
, (enum reload_type
) type
);
3990 /* Emit code to move LEN bytes from DST to SRC. */
3993 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
3995 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3997 if (INTVAL (len
) > 0)
3998 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4001 else if (TARGET_MVCLE
)
4003 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4008 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4009 rtx loop_start_label
= gen_label_rtx ();
4010 rtx loop_end_label
= gen_label_rtx ();
4011 rtx end_label
= gen_label_rtx ();
4012 enum machine_mode mode
;
4014 mode
= GET_MODE (len
);
4015 if (mode
== VOIDmode
)
4018 dst_addr
= gen_reg_rtx (Pmode
);
4019 src_addr
= gen_reg_rtx (Pmode
);
4020 count
= gen_reg_rtx (mode
);
4021 blocks
= gen_reg_rtx (mode
);
4023 convert_move (count
, len
, 1);
4024 emit_cmp_and_jump_insns (count
, const0_rtx
,
4025 EQ
, NULL_RTX
, mode
, 1, end_label
);
4027 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4028 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4029 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4030 src
= change_address (src
, VOIDmode
, src_addr
);
4032 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4035 emit_move_insn (count
, temp
);
4037 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4040 emit_move_insn (blocks
, temp
);
4042 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4043 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4045 emit_label (loop_start_label
);
4048 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4052 /* Issue a read prefetch for the +3 cache line. */
4053 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4054 const0_rtx
, const0_rtx
);
4055 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4056 emit_insn (prefetch
);
4058 /* Issue a write prefetch for the +3 cache line. */
4059 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4060 const1_rtx
, const0_rtx
);
4061 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4062 emit_insn (prefetch
);
4065 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4066 s390_load_address (dst_addr
,
4067 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4068 s390_load_address (src_addr
,
4069 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4071 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4074 emit_move_insn (blocks
, temp
);
4076 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4077 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4079 emit_jump (loop_start_label
);
4080 emit_label (loop_end_label
);
4082 emit_insn (gen_movmem_short (dst
, src
,
4083 convert_to_mode (Pmode
, count
, 1)));
4084 emit_label (end_label
);
4088 /* Emit code to set LEN bytes at DST to VAL.
4089 Make use of clrmem if VAL is zero. */
4092 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4094 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4097 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4099 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4101 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4102 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4105 /* Initialize memory by storing the first byte. */
4106 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4108 if (INTVAL (len
) > 1)
4110 /* Initiate 1 byte overlap move.
4111 The first byte of DST is propagated through DSTP1.
4112 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4113 DST is set to size 1 so the rest of the memory location
4114 does not count as source operand. */
4115 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4116 set_mem_size (dst
, const1_rtx
);
4118 emit_insn (gen_movmem_short (dstp1
, dst
,
4119 GEN_INT (INTVAL (len
) - 2)));
4124 else if (TARGET_MVCLE
)
4126 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4127 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4132 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4133 rtx loop_start_label
= gen_label_rtx ();
4134 rtx loop_end_label
= gen_label_rtx ();
4135 rtx end_label
= gen_label_rtx ();
4136 enum machine_mode mode
;
4138 mode
= GET_MODE (len
);
4139 if (mode
== VOIDmode
)
4142 dst_addr
= gen_reg_rtx (Pmode
);
4143 count
= gen_reg_rtx (mode
);
4144 blocks
= gen_reg_rtx (mode
);
4146 convert_move (count
, len
, 1);
4147 emit_cmp_and_jump_insns (count
, const0_rtx
,
4148 EQ
, NULL_RTX
, mode
, 1, end_label
);
4150 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4151 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4153 if (val
== const0_rtx
)
4154 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4158 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4159 set_mem_size (dst
, const1_rtx
);
4161 /* Initialize memory by storing the first byte. */
4162 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4164 /* If count is 1 we are done. */
4165 emit_cmp_and_jump_insns (count
, const1_rtx
,
4166 EQ
, NULL_RTX
, mode
, 1, end_label
);
4168 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4172 emit_move_insn (count
, temp
);
4174 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4177 emit_move_insn (blocks
, temp
);
4179 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4180 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4182 emit_label (loop_start_label
);
4185 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4187 /* Issue a write prefetch for the +4 cache line. */
4188 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4190 const1_rtx
, const0_rtx
);
4191 emit_insn (prefetch
);
4192 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4195 if (val
== const0_rtx
)
4196 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4198 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4199 s390_load_address (dst_addr
,
4200 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4202 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4205 emit_move_insn (blocks
, temp
);
4207 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4208 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4210 emit_jump (loop_start_label
);
4211 emit_label (loop_end_label
);
4213 if (val
== const0_rtx
)
4214 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4216 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4217 emit_label (end_label
);
4221 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4222 and return the result in TARGET. */
4225 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4227 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4230 /* As the result of CMPINT is inverted compared to what we need,
4231 we have to swap the operands. */
4232 tmp
= op0
; op0
= op1
; op1
= tmp
;
4234 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4236 if (INTVAL (len
) > 0)
4238 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4239 emit_insn (gen_cmpint (target
, ccreg
));
4242 emit_move_insn (target
, const0_rtx
);
4244 else if (TARGET_MVCLE
)
4246 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4247 emit_insn (gen_cmpint (target
, ccreg
));
4251 rtx addr0
, addr1
, count
, blocks
, temp
;
4252 rtx loop_start_label
= gen_label_rtx ();
4253 rtx loop_end_label
= gen_label_rtx ();
4254 rtx end_label
= gen_label_rtx ();
4255 enum machine_mode mode
;
4257 mode
= GET_MODE (len
);
4258 if (mode
== VOIDmode
)
4261 addr0
= gen_reg_rtx (Pmode
);
4262 addr1
= gen_reg_rtx (Pmode
);
4263 count
= gen_reg_rtx (mode
);
4264 blocks
= gen_reg_rtx (mode
);
4266 convert_move (count
, len
, 1);
4267 emit_cmp_and_jump_insns (count
, const0_rtx
,
4268 EQ
, NULL_RTX
, mode
, 1, end_label
);
4270 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4271 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4272 op0
= change_address (op0
, VOIDmode
, addr0
);
4273 op1
= change_address (op1
, VOIDmode
, addr1
);
4275 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4278 emit_move_insn (count
, temp
);
4280 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4283 emit_move_insn (blocks
, temp
);
4285 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4286 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4288 emit_label (loop_start_label
);
4291 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4295 /* Issue a read prefetch for the +2 cache line of operand 1. */
4296 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4297 const0_rtx
, const0_rtx
);
4298 emit_insn (prefetch
);
4299 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4301 /* Issue a read prefetch for the +2 cache line of operand 2. */
4302 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4303 const0_rtx
, const0_rtx
);
4304 emit_insn (prefetch
);
4305 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4308 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4309 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4310 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4311 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4312 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4313 emit_jump_insn (temp
);
4315 s390_load_address (addr0
,
4316 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4317 s390_load_address (addr1
,
4318 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4320 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4323 emit_move_insn (blocks
, temp
);
4325 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4326 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4328 emit_jump (loop_start_label
);
4329 emit_label (loop_end_label
);
4331 emit_insn (gen_cmpmem_short (op0
, op1
,
4332 convert_to_mode (Pmode
, count
, 1)));
4333 emit_label (end_label
);
4335 emit_insn (gen_cmpint (target
, ccreg
));
4340 /* Expand conditional increment or decrement using alc/slb instructions.
4341 Should generate code setting DST to either SRC or SRC + INCREMENT,
4342 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4343 Returns true if successful, false otherwise.
4345 That makes it possible to implement some if-constructs without jumps e.g.:
4346 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4347 unsigned int a, b, c;
4348 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4349 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4350 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4351 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4353 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4354 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4355 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4356 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4357 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4360 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4361 rtx dst
, rtx src
, rtx increment
)
4363 enum machine_mode cmp_mode
;
4364 enum machine_mode cc_mode
;
4370 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4371 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4373 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4374 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4379 /* Try ADD LOGICAL WITH CARRY. */
4380 if (increment
== const1_rtx
)
4382 /* Determine CC mode to use. */
4383 if (cmp_code
== EQ
|| cmp_code
== NE
)
4385 if (cmp_op1
!= const0_rtx
)
4387 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4388 NULL_RTX
, 0, OPTAB_WIDEN
);
4389 cmp_op1
= const0_rtx
;
4392 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4395 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4400 cmp_code
= swap_condition (cmp_code
);
4417 /* Emit comparison instruction pattern. */
4418 if (!register_operand (cmp_op0
, cmp_mode
))
4419 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4421 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4422 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4423 /* We use insn_invalid_p here to add clobbers if required. */
4424 ret
= insn_invalid_p (emit_insn (insn
));
4427 /* Emit ALC instruction pattern. */
4428 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4429 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4432 if (src
!= const0_rtx
)
4434 if (!register_operand (src
, GET_MODE (dst
)))
4435 src
= force_reg (GET_MODE (dst
), src
);
4437 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4438 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4441 p
= rtvec_alloc (2);
4443 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4445 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4446 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4451 /* Try SUBTRACT LOGICAL WITH BORROW. */
4452 if (increment
== constm1_rtx
)
4454 /* Determine CC mode to use. */
4455 if (cmp_code
== EQ
|| cmp_code
== NE
)
4457 if (cmp_op1
!= const0_rtx
)
4459 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4460 NULL_RTX
, 0, OPTAB_WIDEN
);
4461 cmp_op1
= const0_rtx
;
4464 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4467 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4472 cmp_code
= swap_condition (cmp_code
);
4489 /* Emit comparison instruction pattern. */
4490 if (!register_operand (cmp_op0
, cmp_mode
))
4491 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4493 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4494 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4495 /* We use insn_invalid_p here to add clobbers if required. */
4496 ret
= insn_invalid_p (emit_insn (insn
));
4499 /* Emit SLB instruction pattern. */
4500 if (!register_operand (src
, GET_MODE (dst
)))
4501 src
= force_reg (GET_MODE (dst
), src
);
4503 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4504 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4505 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4506 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4508 p
= rtvec_alloc (2);
4510 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4512 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4513 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4521 /* Expand code for the insv template. Return true if successful. */
4524 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4526 int bitsize
= INTVAL (op1
);
4527 int bitpos
= INTVAL (op2
);
4529 /* On z10 we can use the risbg instruction to implement insv. */
4531 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4532 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4537 op
= gen_rtx_SET (GET_MODE(src
),
4538 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4540 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4541 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4546 /* We need byte alignment. */
4547 if (bitsize
% BITS_PER_UNIT
)
4551 && memory_operand (dest
, VOIDmode
)
4552 && (register_operand (src
, word_mode
)
4553 || const_int_operand (src
, VOIDmode
)))
4555 /* Emit standard pattern if possible. */
4556 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4557 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4558 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4560 /* (set (ze (mem)) (const_int)). */
4561 else if (const_int_operand (src
, VOIDmode
))
4563 int size
= bitsize
/ BITS_PER_UNIT
;
4564 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4565 GET_MODE_SIZE (word_mode
) - size
);
4567 dest
= adjust_address (dest
, BLKmode
, 0);
4568 set_mem_size (dest
, GEN_INT (size
));
4569 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4572 /* (set (ze (mem)) (reg)). */
4573 else if (register_operand (src
, word_mode
))
4575 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4576 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4580 /* Emit st,stcmh sequence. */
4581 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4582 int size
= stcmh_width
/ BITS_PER_UNIT
;
4584 emit_move_insn (adjust_address (dest
, SImode
, size
),
4585 gen_lowpart (SImode
, src
));
4586 set_mem_size (dest
, GEN_INT (size
));
4587 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4588 (stcmh_width
), const0_rtx
),
4589 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4590 (GET_MODE_BITSIZE (SImode
))));
4599 /* (set (ze (reg)) (const_int)). */
4601 && register_operand (dest
, word_mode
)
4602 && (bitpos
% 16) == 0
4603 && (bitsize
% 16) == 0
4604 && const_int_operand (src
, VOIDmode
))
4606 HOST_WIDE_INT val
= INTVAL (src
);
4607 int regpos
= bitpos
+ bitsize
;
4609 while (regpos
> bitpos
)
4611 enum machine_mode putmode
;
4614 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4619 putsize
= GET_MODE_BITSIZE (putmode
);
4621 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4624 gen_int_mode (val
, putmode
));
4627 gcc_assert (regpos
== bitpos
);
4634 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4635 register that holds VAL of mode MODE shifted by COUNT bits. */
4638 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4640 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4641 NULL_RTX
, 1, OPTAB_DIRECT
);
4642 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4643 NULL_RTX
, 1, OPTAB_DIRECT
);
4646 /* Structure to hold the initial parameters for a compare_and_swap operation
4647 in HImode and QImode. */
4649 struct alignment_context
4651 rtx memsi
; /* SI aligned memory location. */
4652 rtx shift
; /* Bit offset with regard to lsb. */
4653 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4654 rtx modemaski
; /* ~modemask */
4655 bool aligned
; /* True if memory is aligned, false else. */
4658 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4659 structure AC for transparent simplifying, if the memory alignment is known
4660 to be at least 32bit. MEM is the memory location for the actual operation
4661 and MODE its mode. */
4664 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4665 enum machine_mode mode
)
4667 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4668 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4671 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4674 /* Alignment is unknown. */
4675 rtx byteoffset
, addr
, align
;
4677 /* Force the address into a register. */
4678 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4680 /* Align it to SImode. */
4681 align
= expand_simple_binop (Pmode
, AND
, addr
,
4682 GEN_INT (-GET_MODE_SIZE (SImode
)),
4683 NULL_RTX
, 1, OPTAB_DIRECT
);
4685 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4686 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4687 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4688 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4690 /* Calculate shiftcount. */
4691 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4692 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4693 NULL_RTX
, 1, OPTAB_DIRECT
);
4694 /* As we already have some offset, evaluate the remaining distance. */
4695 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4696 NULL_RTX
, 1, OPTAB_DIRECT
);
4699 /* Shift is the byte count, but we need the bitcount. */
4700 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4701 NULL_RTX
, 1, OPTAB_DIRECT
);
4702 /* Calculate masks. */
4703 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4704 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4705 NULL_RTX
, 1, OPTAB_DIRECT
);
4706 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4709 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4710 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4711 to set if CMP == MEM.
4712 CMP is never in memory for compare_and_swap_cc because
4713 expand_bool_compare_and_swap puts it into a register for later compare. */
4716 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4718 struct alignment_context ac
;
4719 rtx cmpv
, newv
, val
, resv
, cc
;
4720 rtx res
= gen_reg_rtx (SImode
);
4721 rtx csloop
= gen_label_rtx ();
4722 rtx csend
= gen_label_rtx ();
4724 gcc_assert (register_operand (target
, VOIDmode
));
4725 gcc_assert (MEM_P (mem
));
4727 init_alignment_context (&ac
, mem
, mode
);
4729 /* Shift the values to the correct bit positions. */
4730 if (!(ac
.aligned
&& MEM_P (cmp
)))
4731 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4732 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4733 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4735 /* Load full word. Subsequent loads are performed by CS. */
4736 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4737 NULL_RTX
, 1, OPTAB_DIRECT
);
4739 /* Start CS loop. */
4740 emit_label (csloop
);
4741 /* val = "<mem>00..0<mem>"
4742 * cmp = "00..0<cmp>00..0"
4743 * new = "00..0<new>00..0"
4746 /* Patch cmp and new with val at correct position. */
4747 if (ac
.aligned
&& MEM_P (cmp
))
4749 cmpv
= force_reg (SImode
, val
);
4750 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4753 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4754 NULL_RTX
, 1, OPTAB_DIRECT
));
4755 if (ac
.aligned
&& MEM_P (new_rtx
))
4757 newv
= force_reg (SImode
, val
);
4758 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new_rtx
);
4761 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4762 NULL_RTX
, 1, OPTAB_DIRECT
));
4764 /* Jump to end if we're done (likely?). */
4765 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4768 /* Check for changes outside mode. */
4769 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4770 NULL_RTX
, 1, OPTAB_DIRECT
);
4771 cc
= s390_emit_compare (NE
, resv
, val
);
4772 emit_move_insn (val
, resv
);
4773 /* Loop internal if so. */
4774 s390_emit_jump (csloop
, cc
);
4778 /* Return the correct part of the bitfield. */
4779 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4780 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4783 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4784 and VAL the value to play with. If AFTER is true then store the value
4785 MEM holds after the operation, if AFTER is false then store the value MEM
4786 holds before the operation. If TARGET is zero then discard that value, else
4787 store it to TARGET. */
4790 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4791 rtx target
, rtx mem
, rtx val
, bool after
)
4793 struct alignment_context ac
;
4795 rtx new_rtx
= gen_reg_rtx (SImode
);
4796 rtx orig
= gen_reg_rtx (SImode
);
4797 rtx csloop
= gen_label_rtx ();
4799 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4800 gcc_assert (MEM_P (mem
));
4802 init_alignment_context (&ac
, mem
, mode
);
4804 /* Shift val to the correct bit positions.
4805 Preserve "icm", but prevent "ex icm". */
4806 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4807 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4809 /* Further preparation insns. */
4810 if (code
== PLUS
|| code
== MINUS
)
4811 emit_move_insn (orig
, val
);
4812 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4813 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4814 NULL_RTX
, 1, OPTAB_DIRECT
);
4816 /* Load full word. Subsequent loads are performed by CS. */
4817 cmp
= force_reg (SImode
, ac
.memsi
);
4819 /* Start CS loop. */
4820 emit_label (csloop
);
4821 emit_move_insn (new_rtx
, cmp
);
4823 /* Patch new with val at correct position. */
4828 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4829 NULL_RTX
, 1, OPTAB_DIRECT
);
4830 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4831 NULL_RTX
, 1, OPTAB_DIRECT
);
4834 if (ac
.aligned
&& MEM_P (val
))
4835 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4838 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4839 NULL_RTX
, 1, OPTAB_DIRECT
);
4840 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4841 NULL_RTX
, 1, OPTAB_DIRECT
);
4847 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4848 NULL_RTX
, 1, OPTAB_DIRECT
);
4850 case MULT
: /* NAND */
4851 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4852 NULL_RTX
, 1, OPTAB_DIRECT
);
4853 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4854 NULL_RTX
, 1, OPTAB_DIRECT
);
4860 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4861 ac
.memsi
, cmp
, new_rtx
));
4863 /* Return the correct part of the bitfield. */
4865 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4866 after
? new_rtx
: cmp
, ac
.shift
,
4867 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4870 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4871 We need to emit DTP-relative relocations. */
4873 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4876 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4881 fputs ("\t.long\t", file
);
4884 fputs ("\t.quad\t", file
);
4889 output_addr_const (file
, x
);
4890 fputs ("@DTPOFF", file
);
4893 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4894 /* Implement TARGET_MANGLE_TYPE. */
4897 s390_mangle_type (const_tree type
)
4899 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4900 && TARGET_LONG_DOUBLE_128
)
4903 /* For all other types, use normal C++ mangling. */
4908 /* In the name of slightly smaller debug output, and to cater to
4909 general assembler lossage, recognize various UNSPEC sequences
4910 and turn them back into a direct symbol reference. */
4913 s390_delegitimize_address (rtx orig_x
)
4917 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4919 if (GET_CODE (x
) != MEM
)
4923 if (GET_CODE (x
) == PLUS
4924 && GET_CODE (XEXP (x
, 1)) == CONST
4925 && GET_CODE (XEXP (x
, 0)) == REG
4926 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4928 y
= XEXP (XEXP (x
, 1), 0);
4929 if (GET_CODE (y
) == UNSPEC
4930 && XINT (y
, 1) == UNSPEC_GOT
)
4931 return XVECEXP (y
, 0, 0);
4935 if (GET_CODE (x
) == CONST
)
4938 if (GET_CODE (y
) == UNSPEC
4939 && XINT (y
, 1) == UNSPEC_GOTENT
)
4940 return XVECEXP (y
, 0, 0);
4947 /* Output operand OP to stdio stream FILE.
4948 OP is an address (register + offset) which is not used to address data;
4949 instead the rightmost bits are interpreted as the value. */
4952 print_shift_count_operand (FILE *file
, rtx op
)
4954 HOST_WIDE_INT offset
;
4957 /* Extract base register and offset. */
4958 if (!s390_decompose_shift_count (op
, &base
, &offset
))
4964 gcc_assert (GET_CODE (base
) == REG
);
4965 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
4966 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
4969 /* Offsets are constricted to twelve bits. */
4970 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
4972 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
4975 /* See 'get_some_local_dynamic_name'. */
4978 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4982 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4984 x
= get_pool_constant (x
);
4985 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
4988 if (GET_CODE (x
) == SYMBOL_REF
4989 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4991 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4998 /* Locate some local-dynamic symbol still in use by this function
4999 so that we can print its name in local-dynamic base patterns. */
5002 get_some_local_dynamic_name (void)
5006 if (cfun
->machine
->some_ld_name
)
5007 return cfun
->machine
->some_ld_name
;
5009 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5011 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5012 return cfun
->machine
->some_ld_name
;
5017 /* Output machine-dependent UNSPECs occurring in address constant X
5018 in assembler syntax to stdio stream FILE. Returns true if the
5019 constant X could be recognized, false otherwise. */
5022 s390_output_addr_const_extra (FILE *file
, rtx x
)
5024 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5025 switch (XINT (x
, 1))
5028 output_addr_const (file
, XVECEXP (x
, 0, 0));
5029 fprintf (file
, "@GOTENT");
5032 output_addr_const (file
, XVECEXP (x
, 0, 0));
5033 fprintf (file
, "@GOT");
5036 output_addr_const (file
, XVECEXP (x
, 0, 0));
5037 fprintf (file
, "@GOTOFF");
5040 output_addr_const (file
, XVECEXP (x
, 0, 0));
5041 fprintf (file
, "@PLT");
5044 output_addr_const (file
, XVECEXP (x
, 0, 0));
5045 fprintf (file
, "@PLTOFF");
5048 output_addr_const (file
, XVECEXP (x
, 0, 0));
5049 fprintf (file
, "@TLSGD");
5052 assemble_name (file
, get_some_local_dynamic_name ());
5053 fprintf (file
, "@TLSLDM");
5056 output_addr_const (file
, XVECEXP (x
, 0, 0));
5057 fprintf (file
, "@DTPOFF");
5060 output_addr_const (file
, XVECEXP (x
, 0, 0));
5061 fprintf (file
, "@NTPOFF");
5063 case UNSPEC_GOTNTPOFF
:
5064 output_addr_const (file
, XVECEXP (x
, 0, 0));
5065 fprintf (file
, "@GOTNTPOFF");
5067 case UNSPEC_INDNTPOFF
:
5068 output_addr_const (file
, XVECEXP (x
, 0, 0));
5069 fprintf (file
, "@INDNTPOFF");
5073 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5074 switch (XINT (x
, 1))
5076 case UNSPEC_POOL_OFFSET
:
5077 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5078 output_addr_const (file
, x
);
5084 /* Output address operand ADDR in assembler syntax to
5085 stdio stream FILE. */
5088 print_operand_address (FILE *file
, rtx addr
)
5090 struct s390_address ad
;
5092 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5094 gcc_assert (TARGET_Z10
);
5095 output_addr_const (file
, addr
);
5099 if (!s390_decompose_address (addr
, &ad
)
5100 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5101 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5102 output_operand_lossage ("cannot decompose address");
5105 output_addr_const (file
, ad
.disp
);
5107 fprintf (file
, "0");
5109 if (ad
.base
&& ad
.indx
)
5110 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5111 reg_names
[REGNO (ad
.base
)]);
5113 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5116 /* Output operand X in assembler syntax to stdio stream FILE.
5117 CODE specified the format flag. The following format flags
5120 'C': print opcode suffix for branch condition.
5121 'D': print opcode suffix for inverse branch condition.
5122 'E': print opcode suffix for branch on index instruction.
5123 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5124 'G': print the size of the operand in bytes.
5125 'O': print only the displacement of a memory reference.
5126 'R': print only the base register of a memory reference.
5127 'S': print S-type memory reference (base+displacement).
5128 'N': print the second word of a DImode operand.
5129 'M': print the second word of a TImode operand.
5130 'Y': print shift count operand.
5132 'b': print integer X as if it's an unsigned byte.
5133 'c': print integer X as if it's an signed byte.
5134 'x': print integer X as if it's an unsigned halfword.
5135 'h': print integer X as if it's a signed halfword.
5136 'i': print the first nonzero HImode part of X.
5137 'j': print the first HImode part unequal to -1 of X.
5138 'k': print the first nonzero SImode part of X.
5139 'm': print the first SImode part unequal to -1 of X.
5140 'o': print integer X as if it's an unsigned 32bit word. */
5143 print_operand (FILE *file
, rtx x
, int code
)
5148 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5152 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5156 if (GET_CODE (x
) == LE
)
5157 fprintf (file
, "l");
5158 else if (GET_CODE (x
) == GT
)
5159 fprintf (file
, "h");
5165 if (GET_CODE (x
) == SYMBOL_REF
)
5167 fprintf (file
, "%s", ":tls_load:");
5168 output_addr_const (file
, x
);
5170 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5172 fprintf (file
, "%s", ":tls_gdcall:");
5173 output_addr_const (file
, XVECEXP (x
, 0, 0));
5175 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5177 fprintf (file
, "%s", ":tls_ldcall:");
5178 assemble_name (file
, get_some_local_dynamic_name ());
5185 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5190 struct s390_address ad
;
5193 gcc_assert (GET_CODE (x
) == MEM
);
5194 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5196 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5197 gcc_assert (!ad
.indx
);
5200 output_addr_const (file
, ad
.disp
);
5202 fprintf (file
, "0");
5208 struct s390_address ad
;
5211 gcc_assert (GET_CODE (x
) == MEM
);
5212 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5214 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5215 gcc_assert (!ad
.indx
);
5218 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5220 fprintf (file
, "0");
5226 struct s390_address ad
;
5229 gcc_assert (GET_CODE (x
) == MEM
);
5230 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5232 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5233 gcc_assert (!ad
.indx
);
5236 output_addr_const (file
, ad
.disp
);
5238 fprintf (file
, "0");
5241 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5246 if (GET_CODE (x
) == REG
)
5247 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5248 else if (GET_CODE (x
) == MEM
)
5249 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5255 if (GET_CODE (x
) == REG
)
5256 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5257 else if (GET_CODE (x
) == MEM
)
5258 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5264 print_shift_count_operand (file
, x
);
5268 switch (GET_CODE (x
))
5271 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5275 output_address (XEXP (x
, 0));
5282 output_addr_const (file
, x
);
5287 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5288 else if (code
== 'c')
5289 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5290 else if (code
== 'x')
5291 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5292 else if (code
== 'h')
5293 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5294 else if (code
== 'i')
5295 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5296 s390_extract_part (x
, HImode
, 0));
5297 else if (code
== 'j')
5298 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5299 s390_extract_part (x
, HImode
, -1));
5300 else if (code
== 'k')
5301 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5302 s390_extract_part (x
, SImode
, 0));
5303 else if (code
== 'm')
5304 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5305 s390_extract_part (x
, SImode
, -1));
5306 else if (code
== 'o')
5307 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5309 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5313 gcc_assert (GET_MODE (x
) == VOIDmode
);
5315 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5316 else if (code
== 'x')
5317 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5318 else if (code
== 'h')
5319 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5325 fatal_insn ("UNKNOWN in print_operand !?", x
);
5330 /* Target hook for assembling integer objects. We need to define it
5331 here to work a round a bug in some versions of GAS, which couldn't
5332 handle values smaller than INT_MIN when printed in decimal. */
5335 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5337 if (size
== 8 && aligned_p
5338 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5340 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5344 return default_assemble_integer (x
, size
, aligned_p
);
5347 /* Returns true if register REGNO is used for forming
5348 a memory address in expression X. */
5351 reg_used_in_mem_p (int regno
, rtx x
)
5353 enum rtx_code code
= GET_CODE (x
);
5359 if (refers_to_regno_p (regno
, regno
+1,
5363 else if (code
== SET
5364 && GET_CODE (SET_DEST (x
)) == PC
)
5366 if (refers_to_regno_p (regno
, regno
+1,
5371 fmt
= GET_RTX_FORMAT (code
);
5372 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5375 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5378 else if (fmt
[i
] == 'E')
5379 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5380 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5386 /* Returns true if expression DEP_RTX sets an address register
5387 used by instruction INSN to address memory. */
5390 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5394 if (GET_CODE (dep_rtx
) == INSN
)
5395 dep_rtx
= PATTERN (dep_rtx
);
5397 if (GET_CODE (dep_rtx
) == SET
)
5399 target
= SET_DEST (dep_rtx
);
5400 if (GET_CODE (target
) == STRICT_LOW_PART
)
5401 target
= XEXP (target
, 0);
5402 while (GET_CODE (target
) == SUBREG
)
5403 target
= SUBREG_REG (target
);
5405 if (GET_CODE (target
) == REG
)
5407 int regno
= REGNO (target
);
5409 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5411 pat
= PATTERN (insn
);
5412 if (GET_CODE (pat
) == PARALLEL
)
5414 gcc_assert (XVECLEN (pat
, 0) == 2);
5415 pat
= XVECEXP (pat
, 0, 0);
5417 gcc_assert (GET_CODE (pat
) == SET
);
5418 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5420 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5421 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5427 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5430 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5432 rtx dep_rtx
= PATTERN (dep_insn
);
5435 if (GET_CODE (dep_rtx
) == SET
5436 && addr_generation_dependency_p (dep_rtx
, insn
))
5438 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5440 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5442 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5450 /* A C statement (sans semicolon) to update the integer scheduling priority
5451 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5452 reduce the priority to execute INSN later. Do not define this macro if
5453 you do not need to adjust the scheduling priorities of insns.
5455 A STD instruction should be scheduled earlier,
5456 in order to use the bypass. */
5458 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5460 if (! INSN_P (insn
))
5463 if (s390_tune
!= PROCESSOR_2084_Z990
5464 && s390_tune
!= PROCESSOR_2094_Z9_109
5465 && s390_tune
!= PROCESSOR_2097_Z10
5466 && s390_tune
!= PROCESSOR_2817_Z196
)
5469 switch (s390_safe_attr_type (insn
))
5473 priority
= priority
<< 3;
5477 priority
= priority
<< 1;
5486 /* The number of instructions that can be issued per cycle. */
5489 s390_issue_rate (void)
5493 case PROCESSOR_2084_Z990
:
5494 case PROCESSOR_2094_Z9_109
:
5495 case PROCESSOR_2817_Z196
:
5497 case PROCESSOR_2097_Z10
:
5505 s390_first_cycle_multipass_dfa_lookahead (void)
5510 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5511 Fix up MEMs as required. */
5514 annotate_constant_pool_refs (rtx
*x
)
5519 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5520 || !CONSTANT_POOL_ADDRESS_P (*x
));
5522 /* Literal pool references can only occur inside a MEM ... */
5523 if (GET_CODE (*x
) == MEM
)
5525 rtx memref
= XEXP (*x
, 0);
5527 if (GET_CODE (memref
) == SYMBOL_REF
5528 && CONSTANT_POOL_ADDRESS_P (memref
))
5530 rtx base
= cfun
->machine
->base_reg
;
5531 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5534 *x
= replace_equiv_address (*x
, addr
);
5538 if (GET_CODE (memref
) == CONST
5539 && GET_CODE (XEXP (memref
, 0)) == PLUS
5540 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5541 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5542 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5544 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5545 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5546 rtx base
= cfun
->machine
->base_reg
;
5547 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5550 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5555 /* ... or a load-address type pattern. */
5556 if (GET_CODE (*x
) == SET
)
5558 rtx addrref
= SET_SRC (*x
);
5560 if (GET_CODE (addrref
) == SYMBOL_REF
5561 && CONSTANT_POOL_ADDRESS_P (addrref
))
5563 rtx base
= cfun
->machine
->base_reg
;
5564 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5567 SET_SRC (*x
) = addr
;
5571 if (GET_CODE (addrref
) == CONST
5572 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5573 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5574 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5575 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5577 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5578 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5579 rtx base
= cfun
->machine
->base_reg
;
5580 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5583 SET_SRC (*x
) = plus_constant (addr
, off
);
5588 /* Annotate LTREL_BASE as well. */
5589 if (GET_CODE (*x
) == UNSPEC
5590 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5592 rtx base
= cfun
->machine
->base_reg
;
5593 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5598 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5599 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5603 annotate_constant_pool_refs (&XEXP (*x
, i
));
5605 else if (fmt
[i
] == 'E')
5607 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5608 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5613 /* Split all branches that exceed the maximum distance.
5614 Returns true if this created a new literal pool entry. */
5617 s390_split_branches (void)
5619 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5620 int new_literal
= 0, ret
;
5621 rtx insn
, pat
, tmp
, target
;
5624 /* We need correct insn addresses. */
5626 shorten_branches (get_insns ());
5628 /* Find all branches that exceed 64KB, and split them. */
5630 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5632 if (GET_CODE (insn
) != JUMP_INSN
)
5635 pat
= PATTERN (insn
);
5636 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5637 pat
= XVECEXP (pat
, 0, 0);
5638 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5641 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5643 label
= &SET_SRC (pat
);
5645 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5647 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5648 label
= &XEXP (SET_SRC (pat
), 1);
5649 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5650 label
= &XEXP (SET_SRC (pat
), 2);
5657 if (get_attr_length (insn
) <= 4)
5660 /* We are going to use the return register as scratch register,
5661 make sure it will be saved/restored by the prologue/epilogue. */
5662 cfun_frame_layout
.save_return_addr_p
= 1;
5667 tmp
= force_const_mem (Pmode
, *label
);
5668 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5669 INSN_ADDRESSES_NEW (tmp
, -1);
5670 annotate_constant_pool_refs (&PATTERN (tmp
));
5677 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5678 UNSPEC_LTREL_OFFSET
);
5679 target
= gen_rtx_CONST (Pmode
, target
);
5680 target
= force_const_mem (Pmode
, target
);
5681 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5682 INSN_ADDRESSES_NEW (tmp
, -1);
5683 annotate_constant_pool_refs (&PATTERN (tmp
));
5685 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5686 cfun
->machine
->base_reg
),
5688 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5691 ret
= validate_change (insn
, label
, target
, 0);
5699 /* Find an annotated literal pool symbol referenced in RTX X,
5700 and store it at REF. Will abort if X contains references to
5701 more than one such pool symbol; multiple references to the same
5702 symbol are allowed, however.
5704 The rtx pointed to by REF must be initialized to NULL_RTX
5705 by the caller before calling this routine. */
5708 find_constant_pool_ref (rtx x
, rtx
*ref
)
5713 /* Ignore LTREL_BASE references. */
5714 if (GET_CODE (x
) == UNSPEC
5715 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5717 /* Likewise POOL_ENTRY insns. */
5718 if (GET_CODE (x
) == UNSPEC_VOLATILE
5719 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5722 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5723 || !CONSTANT_POOL_ADDRESS_P (x
));
5725 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5727 rtx sym
= XVECEXP (x
, 0, 0);
5728 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5729 && CONSTANT_POOL_ADDRESS_P (sym
));
5731 if (*ref
== NULL_RTX
)
5734 gcc_assert (*ref
== sym
);
5739 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5740 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5744 find_constant_pool_ref (XEXP (x
, i
), ref
);
5746 else if (fmt
[i
] == 'E')
5748 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5749 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5754 /* Replace every reference to the annotated literal pool
5755 symbol REF in X by its base plus OFFSET. */
5758 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5763 gcc_assert (*x
!= ref
);
5765 if (GET_CODE (*x
) == UNSPEC
5766 && XINT (*x
, 1) == UNSPEC_LTREF
5767 && XVECEXP (*x
, 0, 0) == ref
)
5769 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5773 if (GET_CODE (*x
) == PLUS
5774 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5775 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5776 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5777 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5779 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5780 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5784 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5785 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5789 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5791 else if (fmt
[i
] == 'E')
5793 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5794 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5799 /* Check whether X contains an UNSPEC_LTREL_BASE.
5800 Return its constant pool symbol if found, NULL_RTX otherwise. */
5803 find_ltrel_base (rtx x
)
5808 if (GET_CODE (x
) == UNSPEC
5809 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5810 return XVECEXP (x
, 0, 0);
5812 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5813 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5817 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5821 else if (fmt
[i
] == 'E')
5823 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5825 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5835 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5838 replace_ltrel_base (rtx
*x
)
5843 if (GET_CODE (*x
) == UNSPEC
5844 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5846 *x
= XVECEXP (*x
, 0, 1);
5850 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5851 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5855 replace_ltrel_base (&XEXP (*x
, i
));
5857 else if (fmt
[i
] == 'E')
5859 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5860 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5866 /* We keep a list of constants which we have to add to internal
5867 constant tables in the middle of large functions. */
5869 #define NR_C_MODES 11
5870 enum machine_mode constant_modes
[NR_C_MODES
] =
5872 TFmode
, TImode
, TDmode
,
5873 DFmode
, DImode
, DDmode
,
5874 SFmode
, SImode
, SDmode
,
5881 struct constant
*next
;
5886 struct constant_pool
5888 struct constant_pool
*next
;
5892 rtx emit_pool_after
;
5894 struct constant
*constants
[NR_C_MODES
];
5895 struct constant
*execute
;
5900 /* Allocate new constant_pool structure. */
5902 static struct constant_pool
*
5903 s390_alloc_pool (void)
5905 struct constant_pool
*pool
;
5908 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
5910 for (i
= 0; i
< NR_C_MODES
; i
++)
5911 pool
->constants
[i
] = NULL
;
5913 pool
->execute
= NULL
;
5914 pool
->label
= gen_label_rtx ();
5915 pool
->first_insn
= NULL_RTX
;
5916 pool
->pool_insn
= NULL_RTX
;
5917 pool
->insns
= BITMAP_ALLOC (NULL
);
5919 pool
->emit_pool_after
= NULL_RTX
;
5924 /* Create new constant pool covering instructions starting at INSN
5925 and chain it to the end of POOL_LIST. */
5927 static struct constant_pool
*
5928 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
5930 struct constant_pool
*pool
, **prev
;
5932 pool
= s390_alloc_pool ();
5933 pool
->first_insn
= insn
;
5935 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
5942 /* End range of instructions covered by POOL at INSN and emit
5943 placeholder insn representing the pool. */
5946 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
5948 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
5951 insn
= get_last_insn ();
5953 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
5954 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5957 /* Add INSN to the list of insns covered by POOL. */
5960 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
5962 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
5965 /* Return pool out of POOL_LIST that covers INSN. */
5967 static struct constant_pool
*
5968 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
5970 struct constant_pool
*pool
;
5972 for (pool
= pool_list
; pool
; pool
= pool
->next
)
5973 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
5979 /* Add constant VAL of mode MODE to the constant pool POOL. */
5982 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
5987 for (i
= 0; i
< NR_C_MODES
; i
++)
5988 if (constant_modes
[i
] == mode
)
5990 gcc_assert (i
!= NR_C_MODES
);
5992 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5993 if (rtx_equal_p (val
, c
->value
))
5998 c
= (struct constant
*) xmalloc (sizeof *c
);
6000 c
->label
= gen_label_rtx ();
6001 c
->next
= pool
->constants
[i
];
6002 pool
->constants
[i
] = c
;
6003 pool
->size
+= GET_MODE_SIZE (mode
);
6007 /* Return an rtx that represents the offset of X from the start of
6011 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6015 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6016 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6017 UNSPEC_POOL_OFFSET
);
6018 return gen_rtx_CONST (GET_MODE (x
), x
);
6021 /* Find constant VAL of mode MODE in the constant pool POOL.
6022 Return an RTX describing the distance from the start of
6023 the pool to the location of the new constant. */
6026 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6027 enum machine_mode mode
)
6032 for (i
= 0; i
< NR_C_MODES
; i
++)
6033 if (constant_modes
[i
] == mode
)
6035 gcc_assert (i
!= NR_C_MODES
);
6037 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6038 if (rtx_equal_p (val
, c
->value
))
6043 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6046 /* Check whether INSN is an execute. Return the label_ref to its
6047 execute target template if so, NULL_RTX otherwise. */
6050 s390_execute_label (rtx insn
)
6052 if (GET_CODE (insn
) == INSN
6053 && GET_CODE (PATTERN (insn
)) == PARALLEL
6054 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6055 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6056 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6061 /* Add execute target for INSN to the constant pool POOL. */
6064 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6068 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6069 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6074 c
= (struct constant
*) xmalloc (sizeof *c
);
6076 c
->label
= gen_label_rtx ();
6077 c
->next
= pool
->execute
;
6083 /* Find execute target for INSN in the constant pool POOL.
6084 Return an RTX describing the distance from the start of
6085 the pool to the location of the execute target. */
6088 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6092 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6093 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6098 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6101 /* For an execute INSN, extract the execute target template. */
6104 s390_execute_target (rtx insn
)
6106 rtx pattern
= PATTERN (insn
);
6107 gcc_assert (s390_execute_label (insn
));
6109 if (XVECLEN (pattern
, 0) == 2)
6111 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6115 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6118 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6119 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6121 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6127 /* Indicate that INSN cannot be duplicated. This is the case for
6128 execute insns that carry a unique label. */
6131 s390_cannot_copy_insn_p (rtx insn
)
6133 rtx label
= s390_execute_label (insn
);
6134 return label
&& label
!= const0_rtx
;
6137 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6138 do not emit the pool base label. */
6141 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6144 rtx insn
= pool
->pool_insn
;
6147 /* Switch to rodata section. */
6148 if (TARGET_CPU_ZARCH
)
6150 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6151 INSN_ADDRESSES_NEW (insn
, -1);
6154 /* Ensure minimum pool alignment. */
6155 if (TARGET_CPU_ZARCH
)
6156 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6158 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6159 INSN_ADDRESSES_NEW (insn
, -1);
6161 /* Emit pool base label. */
6164 insn
= emit_label_after (pool
->label
, insn
);
6165 INSN_ADDRESSES_NEW (insn
, -1);
6168 /* Dump constants in descending alignment requirement order,
6169 ensuring proper alignment for every constant. */
6170 for (i
= 0; i
< NR_C_MODES
; i
++)
6171 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6173 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6174 rtx value
= copy_rtx (c
->value
);
6175 if (GET_CODE (value
) == CONST
6176 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6177 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6178 && XVECLEN (XEXP (value
, 0), 0) == 1)
6179 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6181 insn
= emit_label_after (c
->label
, insn
);
6182 INSN_ADDRESSES_NEW (insn
, -1);
6184 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6185 gen_rtvec (1, value
),
6186 UNSPECV_POOL_ENTRY
);
6187 insn
= emit_insn_after (value
, insn
);
6188 INSN_ADDRESSES_NEW (insn
, -1);
6191 /* Ensure minimum alignment for instructions. */
6192 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6193 INSN_ADDRESSES_NEW (insn
, -1);
6195 /* Output in-pool execute template insns. */
6196 for (c
= pool
->execute
; c
; c
= c
->next
)
6198 insn
= emit_label_after (c
->label
, insn
);
6199 INSN_ADDRESSES_NEW (insn
, -1);
6201 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6202 INSN_ADDRESSES_NEW (insn
, -1);
6205 /* Switch back to previous section. */
6206 if (TARGET_CPU_ZARCH
)
6208 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6209 INSN_ADDRESSES_NEW (insn
, -1);
6212 insn
= emit_barrier_after (insn
);
6213 INSN_ADDRESSES_NEW (insn
, -1);
6215 /* Remove placeholder insn. */
6216 remove_insn (pool
->pool_insn
);
6219 /* Free all memory used by POOL. */
6222 s390_free_pool (struct constant_pool
*pool
)
6224 struct constant
*c
, *next
;
6227 for (i
= 0; i
< NR_C_MODES
; i
++)
6228 for (c
= pool
->constants
[i
]; c
; c
= next
)
6234 for (c
= pool
->execute
; c
; c
= next
)
6240 BITMAP_FREE (pool
->insns
);
6245 /* Collect main literal pool. Return NULL on overflow. */
6247 static struct constant_pool
*
6248 s390_mainpool_start (void)
6250 struct constant_pool
*pool
;
6253 pool
= s390_alloc_pool ();
6255 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6257 if (GET_CODE (insn
) == INSN
6258 && GET_CODE (PATTERN (insn
)) == SET
6259 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6260 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6262 gcc_assert (!pool
->pool_insn
);
6263 pool
->pool_insn
= insn
;
6266 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6268 s390_add_execute (pool
, insn
);
6270 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6272 rtx pool_ref
= NULL_RTX
;
6273 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6276 rtx constant
= get_pool_constant (pool_ref
);
6277 enum machine_mode mode
= get_pool_mode (pool_ref
);
6278 s390_add_constant (pool
, constant
, mode
);
6282 /* If hot/cold partitioning is enabled we have to make sure that
6283 the literal pool is emitted in the same section where the
6284 initialization of the literal pool base pointer takes place.
6285 emit_pool_after is only used in the non-overflow case on non
6286 Z cpus where we can emit the literal pool at the end of the
6287 function body within the text section. */
6289 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6290 && !pool
->emit_pool_after
)
6291 pool
->emit_pool_after
= PREV_INSN (insn
);
6294 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6296 if (pool
->size
>= 4096)
6298 /* We're going to chunkify the pool, so remove the main
6299 pool placeholder insn. */
6300 remove_insn (pool
->pool_insn
);
6302 s390_free_pool (pool
);
6306 /* If the functions ends with the section where the literal pool
6307 should be emitted set the marker to its end. */
6308 if (pool
&& !pool
->emit_pool_after
)
6309 pool
->emit_pool_after
= get_last_insn ();
6314 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6315 Modify the current function to output the pool constants as well as
6316 the pool register setup instruction. */
6319 s390_mainpool_finish (struct constant_pool
*pool
)
6321 rtx base_reg
= cfun
->machine
->base_reg
;
6324 /* If the pool is empty, we're done. */
6325 if (pool
->size
== 0)
6327 /* We don't actually need a base register after all. */
6328 cfun
->machine
->base_reg
= NULL_RTX
;
6330 if (pool
->pool_insn
)
6331 remove_insn (pool
->pool_insn
);
6332 s390_free_pool (pool
);
6336 /* We need correct insn addresses. */
6337 shorten_branches (get_insns ());
6339 /* On zSeries, we use a LARL to load the pool register. The pool is
6340 located in the .rodata section, so we emit it after the function. */
6341 if (TARGET_CPU_ZARCH
)
6343 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6344 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6345 INSN_ADDRESSES_NEW (insn
, -1);
6346 remove_insn (pool
->pool_insn
);
6348 insn
= get_last_insn ();
6349 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6350 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6352 s390_dump_pool (pool
, 0);
6355 /* On S/390, if the total size of the function's code plus literal pool
6356 does not exceed 4096 bytes, we use BASR to set up a function base
6357 pointer, and emit the literal pool at the end of the function. */
6358 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6359 + pool
->size
+ 8 /* alignment slop */ < 4096)
6361 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6362 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6363 INSN_ADDRESSES_NEW (insn
, -1);
6364 remove_insn (pool
->pool_insn
);
6366 insn
= emit_label_after (pool
->label
, insn
);
6367 INSN_ADDRESSES_NEW (insn
, -1);
6369 /* emit_pool_after will be set by s390_mainpool_start to the
6370 last insn of the section where the literal pool should be
6372 insn
= pool
->emit_pool_after
;
6374 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6375 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6377 s390_dump_pool (pool
, 1);
6380 /* Otherwise, we emit an inline literal pool and use BASR to branch
6381 over it, setting up the pool register at the same time. */
6384 rtx pool_end
= gen_label_rtx ();
6386 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6387 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6388 INSN_ADDRESSES_NEW (insn
, -1);
6389 remove_insn (pool
->pool_insn
);
6391 insn
= emit_label_after (pool
->label
, insn
);
6392 INSN_ADDRESSES_NEW (insn
, -1);
6394 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6395 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6397 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6398 INSN_ADDRESSES_NEW (insn
, -1);
6400 s390_dump_pool (pool
, 1);
6404 /* Replace all literal pool references. */
6406 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6409 replace_ltrel_base (&PATTERN (insn
));
6411 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6413 rtx addr
, pool_ref
= NULL_RTX
;
6414 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6417 if (s390_execute_label (insn
))
6418 addr
= s390_find_execute (pool
, insn
);
6420 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6421 get_pool_mode (pool_ref
));
6423 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6424 INSN_CODE (insn
) = -1;
6430 /* Free the pool. */
6431 s390_free_pool (pool
);
6434 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6435 We have decided we cannot use this pool, so revert all changes
6436 to the current function that were done by s390_mainpool_start. */
6438 s390_mainpool_cancel (struct constant_pool
*pool
)
6440 /* We didn't actually change the instruction stream, so simply
6441 free the pool memory. */
6442 s390_free_pool (pool
);
6446 /* Chunkify the literal pool. */
6448 #define S390_POOL_CHUNK_MIN 0xc00
6449 #define S390_POOL_CHUNK_MAX 0xe00
6451 static struct constant_pool
*
6452 s390_chunkify_start (void)
6454 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6457 rtx pending_ltrel
= NULL_RTX
;
6460 rtx (*gen_reload_base
) (rtx
, rtx
) =
6461 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6464 /* We need correct insn addresses. */
6466 shorten_branches (get_insns ());
6468 /* Scan all insns and move literals to pool chunks. */
6470 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6472 bool section_switch_p
= false;
6474 /* Check for pending LTREL_BASE. */
6477 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6480 gcc_assert (ltrel_base
== pending_ltrel
);
6481 pending_ltrel
= NULL_RTX
;
6485 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6488 curr_pool
= s390_start_pool (&pool_list
, insn
);
6490 s390_add_execute (curr_pool
, insn
);
6491 s390_add_pool_insn (curr_pool
, insn
);
6493 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6495 rtx pool_ref
= NULL_RTX
;
6496 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6499 rtx constant
= get_pool_constant (pool_ref
);
6500 enum machine_mode mode
= get_pool_mode (pool_ref
);
6503 curr_pool
= s390_start_pool (&pool_list
, insn
);
6505 s390_add_constant (curr_pool
, constant
, mode
);
6506 s390_add_pool_insn (curr_pool
, insn
);
6508 /* Don't split the pool chunk between a LTREL_OFFSET load
6509 and the corresponding LTREL_BASE. */
6510 if (GET_CODE (constant
) == CONST
6511 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6512 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6514 gcc_assert (!pending_ltrel
);
6515 pending_ltrel
= pool_ref
;
6520 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6523 s390_add_pool_insn (curr_pool
, insn
);
6524 /* An LTREL_BASE must follow within the same basic block. */
6525 gcc_assert (!pending_ltrel
);
6528 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6529 section_switch_p
= true;
6532 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6533 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6536 if (TARGET_CPU_ZARCH
)
6538 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6541 s390_end_pool (curr_pool
, NULL_RTX
);
6546 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6547 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6550 /* We will later have to insert base register reload insns.
6551 Those will have an effect on code size, which we need to
6552 consider here. This calculation makes rather pessimistic
6553 worst-case assumptions. */
6554 if (GET_CODE (insn
) == CODE_LABEL
)
6557 if (chunk_size
< S390_POOL_CHUNK_MIN
6558 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6559 && !section_switch_p
)
6562 /* Pool chunks can only be inserted after BARRIERs ... */
6563 if (GET_CODE (insn
) == BARRIER
)
6565 s390_end_pool (curr_pool
, insn
);
6570 /* ... so if we don't find one in time, create one. */
6571 else if (chunk_size
> S390_POOL_CHUNK_MAX
6572 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6573 || section_switch_p
)
6575 rtx label
, jump
, barrier
;
6577 if (!section_switch_p
)
6579 /* We can insert the barrier only after a 'real' insn. */
6580 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6582 if (get_attr_length (insn
) == 0)
6584 /* Don't separate LTREL_BASE from the corresponding
6585 LTREL_OFFSET load. */
6591 gcc_assert (!pending_ltrel
);
6593 /* The old pool has to end before the section switch
6594 note in order to make it part of the current
6596 insn
= PREV_INSN (insn
);
6599 label
= gen_label_rtx ();
6600 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6601 barrier
= emit_barrier_after (jump
);
6602 insn
= emit_label_after (label
, barrier
);
6603 JUMP_LABEL (jump
) = label
;
6604 LABEL_NUSES (label
) = 1;
6606 INSN_ADDRESSES_NEW (jump
, -1);
6607 INSN_ADDRESSES_NEW (barrier
, -1);
6608 INSN_ADDRESSES_NEW (insn
, -1);
6610 s390_end_pool (curr_pool
, barrier
);
6618 s390_end_pool (curr_pool
, NULL_RTX
);
6619 gcc_assert (!pending_ltrel
);
6621 /* Find all labels that are branched into
6622 from an insn belonging to a different chunk. */
6624 far_labels
= BITMAP_ALLOC (NULL
);
6626 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6628 /* Labels marked with LABEL_PRESERVE_P can be target
6629 of non-local jumps, so we have to mark them.
6630 The same holds for named labels.
6632 Don't do that, however, if it is the label before
6635 if (GET_CODE (insn
) == CODE_LABEL
6636 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6638 rtx vec_insn
= next_real_insn (insn
);
6639 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6640 PATTERN (vec_insn
) : NULL_RTX
;
6642 || !(GET_CODE (vec_pat
) == ADDR_VEC
6643 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6644 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6647 /* If we have a direct jump (conditional or unconditional)
6648 or a casesi jump, check all potential targets. */
6649 else if (GET_CODE (insn
) == JUMP_INSN
)
6651 rtx pat
= PATTERN (insn
);
6652 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6653 pat
= XVECEXP (pat
, 0, 0);
6655 if (GET_CODE (pat
) == SET
)
6657 rtx label
= JUMP_LABEL (insn
);
6660 if (s390_find_pool (pool_list
, label
)
6661 != s390_find_pool (pool_list
, insn
))
6662 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6665 else if (GET_CODE (pat
) == PARALLEL
6666 && XVECLEN (pat
, 0) == 2
6667 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6668 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6669 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6671 /* Find the jump table used by this casesi jump. */
6672 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6673 rtx vec_insn
= next_real_insn (vec_label
);
6674 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6675 PATTERN (vec_insn
) : NULL_RTX
;
6677 && (GET_CODE (vec_pat
) == ADDR_VEC
6678 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6680 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6682 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6684 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6686 if (s390_find_pool (pool_list
, label
)
6687 != s390_find_pool (pool_list
, insn
))
6688 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6695 /* Insert base register reload insns before every pool. */
6697 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6699 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6701 rtx insn
= curr_pool
->first_insn
;
6702 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6705 /* Insert base register reload insns at every far label. */
6707 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6708 if (GET_CODE (insn
) == CODE_LABEL
6709 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6711 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6714 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6716 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6721 BITMAP_FREE (far_labels
);
6724 /* Recompute insn addresses. */
6726 init_insn_lengths ();
6727 shorten_branches (get_insns ());
6732 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6733 After we have decided to use this list, finish implementing
6734 all changes to the current function as required. */
6737 s390_chunkify_finish (struct constant_pool
*pool_list
)
6739 struct constant_pool
*curr_pool
= NULL
;
6743 /* Replace all literal pool references. */
6745 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6748 replace_ltrel_base (&PATTERN (insn
));
6750 curr_pool
= s390_find_pool (pool_list
, insn
);
6754 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6756 rtx addr
, pool_ref
= NULL_RTX
;
6757 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6760 if (s390_execute_label (insn
))
6761 addr
= s390_find_execute (curr_pool
, insn
);
6763 addr
= s390_find_constant (curr_pool
,
6764 get_pool_constant (pool_ref
),
6765 get_pool_mode (pool_ref
));
6767 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6768 INSN_CODE (insn
) = -1;
6773 /* Dump out all literal pools. */
6775 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6776 s390_dump_pool (curr_pool
, 0);
6778 /* Free pool list. */
6782 struct constant_pool
*next
= pool_list
->next
;
6783 s390_free_pool (pool_list
);
6788 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6789 We have decided we cannot use this list, so revert all changes
6790 to the current function that were done by s390_chunkify_start. */
6793 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6795 struct constant_pool
*curr_pool
= NULL
;
6798 /* Remove all pool placeholder insns. */
6800 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6802 /* Did we insert an extra barrier? Remove it. */
6803 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6804 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6805 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6807 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6808 && barrier
&& GET_CODE (barrier
) == BARRIER
6809 && label
&& GET_CODE (label
) == CODE_LABEL
6810 && GET_CODE (PATTERN (jump
)) == SET
6811 && SET_DEST (PATTERN (jump
)) == pc_rtx
6812 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6813 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6816 remove_insn (barrier
);
6817 remove_insn (label
);
6820 remove_insn (curr_pool
->pool_insn
);
6823 /* Remove all base register reload insns. */
6825 for (insn
= get_insns (); insn
; )
6827 rtx next_insn
= NEXT_INSN (insn
);
6829 if (GET_CODE (insn
) == INSN
6830 && GET_CODE (PATTERN (insn
)) == SET
6831 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6832 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6838 /* Free pool list. */
6842 struct constant_pool
*next
= pool_list
->next
;
6843 s390_free_pool (pool_list
);
6848 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6851 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6855 switch (GET_MODE_CLASS (mode
))
6858 case MODE_DECIMAL_FLOAT
:
6859 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6861 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6862 assemble_real (r
, mode
, align
);
6866 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6867 mark_symbol_refs_as_used (exp
);
6876 /* Return an RTL expression representing the value of the return address
6877 for the frame COUNT steps up from the current frame. FRAME is the
6878 frame pointer of that frame. */
6881 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6886 /* Without backchain, we fail for all but the current frame. */
6888 if (!TARGET_BACKCHAIN
&& count
> 0)
6891 /* For the current frame, we need to make sure the initial
6892 value of RETURN_REGNUM is actually saved. */
6896 /* On non-z architectures branch splitting could overwrite r14. */
6897 if (TARGET_CPU_ZARCH
)
6898 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
6901 cfun_frame_layout
.save_return_addr_p
= true;
6902 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
6906 if (TARGET_PACKED_STACK
)
6907 offset
= -2 * UNITS_PER_LONG
;
6909 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
6911 addr
= plus_constant (frame
, offset
);
6912 addr
= memory_address (Pmode
, addr
);
6913 return gen_rtx_MEM (Pmode
, addr
);
6916 /* Return an RTL expression representing the back chain stored in
6917 the current stack frame. */
6920 s390_back_chain_rtx (void)
6924 gcc_assert (TARGET_BACKCHAIN
);
6926 if (TARGET_PACKED_STACK
)
6927 chain
= plus_constant (stack_pointer_rtx
,
6928 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
6930 chain
= stack_pointer_rtx
;
6932 chain
= gen_rtx_MEM (Pmode
, chain
);
6936 /* Find first call clobbered register unused in a function.
6937 This could be used as base register in a leaf function
6938 or for holding the return address before epilogue. */
6941 find_unused_clobbered_reg (void)
6944 for (i
= 0; i
< 6; i
++)
6945 if (!df_regs_ever_live_p (i
))
6951 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6952 clobbered hard regs in SETREG. */
6955 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
6957 int *regs_ever_clobbered
= (int *)data
;
6958 unsigned int i
, regno
;
6959 enum machine_mode mode
= GET_MODE (setreg
);
6961 if (GET_CODE (setreg
) == SUBREG
)
6963 rtx inner
= SUBREG_REG (setreg
);
6964 if (!GENERAL_REG_P (inner
))
6966 regno
= subreg_regno (setreg
);
6968 else if (GENERAL_REG_P (setreg
))
6969 regno
= REGNO (setreg
);
6974 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
6976 regs_ever_clobbered
[i
] = 1;
6979 /* Walks through all basic blocks of the current function looking
6980 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6981 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6982 each of those regs. */
6985 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
6991 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
6993 /* For non-leaf functions we have to consider all call clobbered regs to be
6995 if (!current_function_is_leaf
)
6997 for (i
= 0; i
< 16; i
++)
6998 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7001 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7002 this work is done by liveness analysis (mark_regs_live_at_end).
7003 Special care is needed for functions containing landing pads. Landing pads
7004 may use the eh registers, but the code which sets these registers is not
7005 contained in that function. Hence s390_regs_ever_clobbered is not able to
7006 deal with this automatically. */
7007 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7008 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7009 if (crtl
->calls_eh_return
7010 || (cfun
->machine
->has_landing_pad_p
7011 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7012 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7014 /* For nonlocal gotos all call-saved registers have to be saved.
7015 This flag is also set for the unwinding code in libgcc.
7016 See expand_builtin_unwind_init. For regs_ever_live this is done by
7018 if (cfun
->has_nonlocal_label
)
7019 for (i
= 0; i
< 16; i
++)
7020 if (!call_really_used_regs
[i
])
7021 regs_ever_clobbered
[i
] = 1;
7023 FOR_EACH_BB (cur_bb
)
7025 FOR_BB_INSNS (cur_bb
, cur_insn
)
7027 if (INSN_P (cur_insn
))
7028 note_stores (PATTERN (cur_insn
),
7029 s390_reg_clobbered_rtx
,
7030 regs_ever_clobbered
);
7035 /* Determine the frame area which actually has to be accessed
7036 in the function epilogue. The values are stored at the
7037 given pointers AREA_BOTTOM (address of the lowest used stack
7038 address) and AREA_TOP (address of the first item which does
7039 not belong to the stack frame). */
7042 s390_frame_area (int *area_bottom
, int *area_top
)
7050 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7052 b
= (cfun_frame_layout
.gprs_offset
7053 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7054 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7055 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7058 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7060 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7061 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7062 + cfun_frame_layout
.high_fprs
* 8));
7066 for (i
= 2; i
< 4; i
++)
7067 if (cfun_fpr_bit_p (i
))
7069 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7070 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7077 /* Fill cfun->machine with info about register usage of current function.
7078 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7081 s390_register_info (int clobbered_regs
[])
7085 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7086 cfun_frame_layout
.fpr_bitmap
= 0;
7087 cfun_frame_layout
.high_fprs
= 0;
7089 for (i
= 24; i
< 32; i
++)
7090 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7092 cfun_set_fpr_bit (i
- 16);
7093 cfun_frame_layout
.high_fprs
++;
7096 /* Find first and last gpr to be saved. We trust regs_ever_live
7097 data, except that we don't save and restore global registers.
7099 Also, all registers with special meaning to the compiler need
7100 to be handled extra. */
7102 s390_regs_ever_clobbered (clobbered_regs
);
7104 for (i
= 0; i
< 16; i
++)
7105 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7107 if (frame_pointer_needed
)
7108 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7111 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7112 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7114 clobbered_regs
[BASE_REGNUM
]
7115 |= (cfun
->machine
->base_reg
7116 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7118 clobbered_regs
[RETURN_REGNUM
]
7119 |= (!current_function_is_leaf
7120 || TARGET_TPF_PROFILING
7121 || cfun
->machine
->split_branches_pending_p
7122 || cfun_frame_layout
.save_return_addr_p
7123 || crtl
->calls_eh_return
7126 clobbered_regs
[STACK_POINTER_REGNUM
]
7127 |= (!current_function_is_leaf
7128 || TARGET_TPF_PROFILING
7129 || cfun_save_high_fprs_p
7130 || get_frame_size () > 0
7131 || cfun
->calls_alloca
7134 for (i
= 6; i
< 16; i
++)
7135 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7137 for (j
= 15; j
> i
; j
--)
7138 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7143 /* Nothing to save/restore. */
7144 cfun_frame_layout
.first_save_gpr_slot
= -1;
7145 cfun_frame_layout
.last_save_gpr_slot
= -1;
7146 cfun_frame_layout
.first_save_gpr
= -1;
7147 cfun_frame_layout
.first_restore_gpr
= -1;
7148 cfun_frame_layout
.last_save_gpr
= -1;
7149 cfun_frame_layout
.last_restore_gpr
= -1;
7153 /* Save slots for gprs from i to j. */
7154 cfun_frame_layout
.first_save_gpr_slot
= i
;
7155 cfun_frame_layout
.last_save_gpr_slot
= j
;
7157 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7158 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7160 if (clobbered_regs
[i
])
7163 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7164 if (clobbered_regs
[j
])
7167 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7169 /* Nothing to save/restore. */
7170 cfun_frame_layout
.first_save_gpr
= -1;
7171 cfun_frame_layout
.first_restore_gpr
= -1;
7172 cfun_frame_layout
.last_save_gpr
= -1;
7173 cfun_frame_layout
.last_restore_gpr
= -1;
7177 /* Save / Restore from gpr i to j. */
7178 cfun_frame_layout
.first_save_gpr
= i
;
7179 cfun_frame_layout
.first_restore_gpr
= i
;
7180 cfun_frame_layout
.last_save_gpr
= j
;
7181 cfun_frame_layout
.last_restore_gpr
= j
;
7187 /* Varargs functions need to save gprs 2 to 6. */
7188 if (cfun
->va_list_gpr_size
7189 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7191 int min_gpr
= crtl
->args
.info
.gprs
;
7192 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7193 if (max_gpr
> GP_ARG_NUM_REG
)
7194 max_gpr
= GP_ARG_NUM_REG
;
7196 if (cfun_frame_layout
.first_save_gpr
== -1
7197 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7199 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7200 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7203 if (cfun_frame_layout
.last_save_gpr
== -1
7204 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7206 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7207 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7211 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7212 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7213 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7215 int min_fpr
= crtl
->args
.info
.fprs
;
7216 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7217 if (max_fpr
> FP_ARG_NUM_REG
)
7218 max_fpr
= FP_ARG_NUM_REG
;
7220 /* ??? This is currently required to ensure proper location
7221 of the fpr save slots within the va_list save area. */
7222 if (TARGET_PACKED_STACK
)
7225 for (i
= min_fpr
; i
< max_fpr
; i
++)
7226 cfun_set_fpr_bit (i
);
7231 for (i
= 2; i
< 4; i
++)
7232 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7233 cfun_set_fpr_bit (i
);
7236 /* Fill cfun->machine with info about frame of current function. */
7239 s390_frame_info (void)
7243 cfun_frame_layout
.frame_size
= get_frame_size ();
7244 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7245 fatal_error ("total size of local variables exceeds architecture limit");
7247 if (!TARGET_PACKED_STACK
)
7249 cfun_frame_layout
.backchain_offset
= 0;
7250 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7251 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7252 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7253 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7256 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7258 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7260 cfun_frame_layout
.gprs_offset
7261 = (cfun_frame_layout
.backchain_offset
7262 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7267 cfun_frame_layout
.f4_offset
7268 = (cfun_frame_layout
.gprs_offset
7269 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7271 cfun_frame_layout
.f0_offset
7272 = (cfun_frame_layout
.f4_offset
7273 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7277 /* On 31 bit we have to care about alignment of the
7278 floating point regs to provide fastest access. */
7279 cfun_frame_layout
.f0_offset
7280 = ((cfun_frame_layout
.gprs_offset
7281 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7282 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7284 cfun_frame_layout
.f4_offset
7285 = (cfun_frame_layout
.f0_offset
7286 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7289 else /* no backchain */
7291 cfun_frame_layout
.f4_offset
7292 = (STACK_POINTER_OFFSET
7293 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7295 cfun_frame_layout
.f0_offset
7296 = (cfun_frame_layout
.f4_offset
7297 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7299 cfun_frame_layout
.gprs_offset
7300 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7303 if (current_function_is_leaf
7304 && !TARGET_TPF_PROFILING
7305 && cfun_frame_layout
.frame_size
== 0
7306 && !cfun_save_high_fprs_p
7307 && !cfun
->calls_alloca
7311 if (!TARGET_PACKED_STACK
)
7312 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7313 + crtl
->outgoing_args_size
7314 + cfun_frame_layout
.high_fprs
* 8);
7317 if (TARGET_BACKCHAIN
)
7318 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7320 /* No alignment trouble here because f8-f15 are only saved under
7322 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7323 cfun_frame_layout
.f4_offset
),
7324 cfun_frame_layout
.gprs_offset
)
7325 - cfun_frame_layout
.high_fprs
* 8);
7327 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7329 for (i
= 0; i
< 8; i
++)
7330 if (cfun_fpr_bit_p (i
))
7331 cfun_frame_layout
.frame_size
+= 8;
7333 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7335 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7336 the frame size to sustain 8 byte alignment of stack frames. */
7337 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7338 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7339 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7341 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7345 /* Generate frame layout. Fills in register and frame data for the current
7346 function in cfun->machine. This routine can be called multiple times;
7347 it will re-do the complete frame layout every time. */
7350 s390_init_frame_layout (void)
7352 HOST_WIDE_INT frame_size
;
7354 int clobbered_regs
[16];
7356 /* On S/390 machines, we may need to perform branch splitting, which
7357 will require both base and return address register. We have no
7358 choice but to assume we're going to need them until right at the
7359 end of the machine dependent reorg phase. */
7360 if (!TARGET_CPU_ZARCH
)
7361 cfun
->machine
->split_branches_pending_p
= true;
7365 frame_size
= cfun_frame_layout
.frame_size
;
7367 /* Try to predict whether we'll need the base register. */
7368 base_used
= cfun
->machine
->split_branches_pending_p
7369 || crtl
->uses_const_pool
7370 || (!DISP_IN_RANGE (frame_size
)
7371 && !CONST_OK_FOR_K (frame_size
));
7373 /* Decide which register to use as literal pool base. In small
7374 leaf functions, try to use an unused call-clobbered register
7375 as base register to avoid save/restore overhead. */
7377 cfun
->machine
->base_reg
= NULL_RTX
;
7378 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7379 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7381 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7383 s390_register_info (clobbered_regs
);
7386 while (frame_size
!= cfun_frame_layout
.frame_size
);
7389 /* Update frame layout. Recompute actual register save data based on
7390 current info and update regs_ever_live for the special registers.
7391 May be called multiple times, but may never cause *more* registers
7392 to be saved than s390_init_frame_layout allocated room for. */
7395 s390_update_frame_layout (void)
7397 int clobbered_regs
[16];
7399 s390_register_info (clobbered_regs
);
7401 df_set_regs_ever_live (BASE_REGNUM
,
7402 clobbered_regs
[BASE_REGNUM
] ? true : false);
7403 df_set_regs_ever_live (RETURN_REGNUM
,
7404 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7405 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7406 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7408 if (cfun
->machine
->base_reg
)
7409 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7412 /* Return true if it is legal to put a value with MODE into REGNO. */
7415 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7417 switch (REGNO_REG_CLASS (regno
))
7420 if (REGNO_PAIR_OK (regno
, mode
))
7422 if (mode
== SImode
|| mode
== DImode
)
7425 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7430 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7435 if (REGNO_PAIR_OK (regno
, mode
))
7438 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7443 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7447 if (REGNO_PAIR_OK (regno
, mode
))
7449 if (mode
== SImode
|| mode
== Pmode
)
7460 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7463 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7465 /* Once we've decided upon a register to use as base register, it must
7466 no longer be used for any other purpose. */
7467 if (cfun
->machine
->base_reg
)
7468 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7469 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7475 /* Maximum number of registers to represent a value of mode MODE
7476 in a register of class RCLASS. */
7479 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7484 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7485 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7487 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7489 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7493 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7496 /* Return true if register FROM can be eliminated via register TO. */
7499 s390_can_eliminate (const int from
, const int to
)
7501 /* On zSeries machines, we have not marked the base register as fixed.
7502 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7503 If a function requires the base register, we say here that this
7504 elimination cannot be performed. This will cause reload to free
7505 up the base register (as if it were fixed). On the other hand,
7506 if the current function does *not* require the base register, we
7507 say here the elimination succeeds, which in turn allows reload
7508 to allocate the base register for any other purpose. */
7509 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7511 if (TARGET_CPU_ZARCH
)
7513 s390_init_frame_layout ();
7514 return cfun
->machine
->base_reg
== NULL_RTX
;
7520 /* Everything else must point into the stack frame. */
7521 gcc_assert (to
== STACK_POINTER_REGNUM
7522 || to
== HARD_FRAME_POINTER_REGNUM
);
7524 gcc_assert (from
== FRAME_POINTER_REGNUM
7525 || from
== ARG_POINTER_REGNUM
7526 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7528 /* Make sure we actually saved the return address. */
7529 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7530 if (!crtl
->calls_eh_return
7532 && !cfun_frame_layout
.save_return_addr_p
)
7538 /* Return offset between register FROM and TO initially after prolog. */
7541 s390_initial_elimination_offset (int from
, int to
)
7543 HOST_WIDE_INT offset
;
7546 /* ??? Why are we called for non-eliminable pairs? */
7547 if (!s390_can_eliminate (from
, to
))
7552 case FRAME_POINTER_REGNUM
:
7553 offset
= (get_frame_size()
7554 + STACK_POINTER_OFFSET
7555 + crtl
->outgoing_args_size
);
7558 case ARG_POINTER_REGNUM
:
7559 s390_init_frame_layout ();
7560 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7563 case RETURN_ADDRESS_POINTER_REGNUM
:
7564 s390_init_frame_layout ();
7565 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7566 gcc_assert (index
>= 0);
7567 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7568 offset
+= index
* UNITS_PER_LONG
;
7582 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7583 to register BASE. Return generated insn. */
7586 save_fpr (rtx base
, int offset
, int regnum
)
7589 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7591 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7592 set_mem_alias_set (addr
, get_varargs_alias_set ());
7594 set_mem_alias_set (addr
, get_frame_alias_set ());
7596 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7599 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7600 to register BASE. Return generated insn. */
7603 restore_fpr (rtx base
, int offset
, int regnum
)
7606 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7607 set_mem_alias_set (addr
, get_frame_alias_set ());
7609 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7612 /* Return true if REGNO is a global register, but not one
7613 of the special ones that need to be saved/restored in anyway. */
7616 global_not_special_regno_p (int regno
)
7618 return (global_regs
[regno
]
7619 /* These registers are special and need to be
7620 restored in any case. */
7621 && !(regno
== STACK_POINTER_REGNUM
7622 || regno
== RETURN_REGNUM
7623 || regno
== BASE_REGNUM
7624 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7627 /* Generate insn to save registers FIRST to LAST into
7628 the register save area located at offset OFFSET
7629 relative to register BASE. */
7632 save_gprs (rtx base
, int offset
, int first
, int last
)
7634 rtx addr
, insn
, note
;
7637 addr
= plus_constant (base
, offset
);
7638 addr
= gen_rtx_MEM (Pmode
, addr
);
7640 set_mem_alias_set (addr
, get_frame_alias_set ());
7642 /* Special-case single register. */
7646 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7648 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7650 if (!global_not_special_regno_p (first
))
7651 RTX_FRAME_RELATED_P (insn
) = 1;
7656 insn
= gen_store_multiple (addr
,
7657 gen_rtx_REG (Pmode
, first
),
7658 GEN_INT (last
- first
+ 1));
7660 if (first
<= 6 && cfun
->stdarg
)
7661 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7663 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7666 set_mem_alias_set (mem
, get_varargs_alias_set ());
7669 /* We need to set the FRAME_RELATED flag on all SETs
7670 inside the store-multiple pattern.
7672 However, we must not emit DWARF records for registers 2..5
7673 if they are stored for use by variable arguments ...
7675 ??? Unfortunately, it is not enough to simply not the
7676 FRAME_RELATED flags for those SETs, because the first SET
7677 of the PARALLEL is always treated as if it had the flag
7678 set, even if it does not. Therefore we emit a new pattern
7679 without those registers as REG_FRAME_RELATED_EXPR note. */
7681 if (first
>= 6 && !global_not_special_regno_p (first
))
7683 rtx pat
= PATTERN (insn
);
7685 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7686 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7687 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7689 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7691 RTX_FRAME_RELATED_P (insn
) = 1;
7697 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7698 if (!global_not_special_regno_p (start
))
7704 addr
= plus_constant (base
, offset
+ (start
- first
) * UNITS_PER_LONG
);
7705 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7706 gen_rtx_REG (Pmode
, start
),
7707 GEN_INT (last
- start
+ 1));
7708 note
= PATTERN (note
);
7710 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7712 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7713 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7714 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7716 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7718 RTX_FRAME_RELATED_P (insn
) = 1;
7724 /* Generate insn to restore registers FIRST to LAST from
7725 the register save area located at offset OFFSET
7726 relative to register BASE. */
7729 restore_gprs (rtx base
, int offset
, int first
, int last
)
7733 addr
= plus_constant (base
, offset
);
7734 addr
= gen_rtx_MEM (Pmode
, addr
);
7735 set_mem_alias_set (addr
, get_frame_alias_set ());
7737 /* Special-case single register. */
7741 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7743 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7748 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7750 GEN_INT (last
- first
+ 1));
7754 /* Return insn sequence to load the GOT register. */
7756 static GTY(()) rtx got_symbol
;
7758 s390_load_got (void)
7764 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7765 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7770 if (TARGET_CPU_ZARCH
)
7772 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7778 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7779 UNSPEC_LTREL_OFFSET
);
7780 offset
= gen_rtx_CONST (Pmode
, offset
);
7781 offset
= force_const_mem (Pmode
, offset
);
7783 emit_move_insn (pic_offset_table_rtx
, offset
);
7785 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7787 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7789 emit_move_insn (pic_offset_table_rtx
, offset
);
7792 insns
= get_insns ();
7797 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7798 and the change to the stack pointer. */
7801 s390_emit_stack_tie (void)
7803 rtx mem
= gen_frame_mem (BLKmode
,
7804 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7806 emit_insn (gen_stack_tie (mem
));
7809 /* Expand the prologue into a bunch of separate insns. */
7812 s390_emit_prologue (void)
7820 /* Complete frame layout. */
7822 s390_update_frame_layout ();
7824 /* Annotate all constant pool references to let the scheduler know
7825 they implicitly use the base register. */
7827 push_topmost_sequence ();
7829 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7832 annotate_constant_pool_refs (&PATTERN (insn
));
7833 df_insn_rescan (insn
);
7836 pop_topmost_sequence ();
7838 /* Choose best register to use for temp use within prologue.
7839 See below for why TPF must use the register 1. */
7841 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7842 && !current_function_is_leaf
7843 && !TARGET_TPF_PROFILING
)
7844 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7846 temp_reg
= gen_rtx_REG (Pmode
, 1);
7848 /* Save call saved gprs. */
7849 if (cfun_frame_layout
.first_save_gpr
!= -1)
7851 insn
= save_gprs (stack_pointer_rtx
,
7852 cfun_frame_layout
.gprs_offset
+
7853 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
7854 - cfun_frame_layout
.first_save_gpr_slot
),
7855 cfun_frame_layout
.first_save_gpr
,
7856 cfun_frame_layout
.last_save_gpr
);
7860 /* Dummy insn to mark literal pool slot. */
7862 if (cfun
->machine
->base_reg
)
7863 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7865 offset
= cfun_frame_layout
.f0_offset
;
7867 /* Save f0 and f2. */
7868 for (i
= 0; i
< 2; i
++)
7870 if (cfun_fpr_bit_p (i
))
7872 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7875 else if (!TARGET_PACKED_STACK
)
7879 /* Save f4 and f6. */
7880 offset
= cfun_frame_layout
.f4_offset
;
7881 for (i
= 2; i
< 4; i
++)
7883 if (cfun_fpr_bit_p (i
))
7885 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7888 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7889 therefore are not frame related. */
7890 if (!call_really_used_regs
[i
+ 16])
7891 RTX_FRAME_RELATED_P (insn
) = 1;
7893 else if (!TARGET_PACKED_STACK
)
7897 if (TARGET_PACKED_STACK
7898 && cfun_save_high_fprs_p
7899 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
7901 offset
= (cfun_frame_layout
.f8_offset
7902 + (cfun_frame_layout
.high_fprs
- 1) * 8);
7904 for (i
= 15; i
> 7 && offset
>= 0; i
--)
7905 if (cfun_fpr_bit_p (i
))
7907 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7909 RTX_FRAME_RELATED_P (insn
) = 1;
7912 if (offset
>= cfun_frame_layout
.f8_offset
)
7916 if (!TARGET_PACKED_STACK
)
7917 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
7919 /* Decrement stack pointer. */
7921 if (cfun_frame_layout
.frame_size
> 0)
7923 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7926 if (s390_stack_size
)
7928 HOST_WIDE_INT stack_guard
;
7930 if (s390_stack_guard
)
7931 stack_guard
= s390_stack_guard
;
7934 /* If no value for stack guard is provided the smallest power of 2
7935 larger than the current frame size is chosen. */
7937 while (stack_guard
< cfun_frame_layout
.frame_size
)
7941 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
7943 warning (0, "frame size of function %qs is "
7944 HOST_WIDE_INT_PRINT_DEC
7945 " bytes exceeding user provided stack limit of "
7946 HOST_WIDE_INT_PRINT_DEC
" bytes. "
7947 "An unconditional trap is added.",
7948 current_function_name(), cfun_frame_layout
.frame_size
,
7950 emit_insn (gen_trap ());
7954 /* stack_guard has to be smaller than s390_stack_size.
7955 Otherwise we would emit an AND with zero which would
7956 not match the test under mask pattern. */
7957 if (stack_guard
>= s390_stack_size
)
7959 warning (0, "frame size of function %qs is "
7960 HOST_WIDE_INT_PRINT_DEC
7961 " bytes which is more than half the stack size. "
7962 "The dynamic check would not be reliable. "
7963 "No check emitted for this function.",
7964 current_function_name(),
7965 cfun_frame_layout
.frame_size
);
7969 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
7970 & ~(stack_guard
- 1));
7972 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
7973 GEN_INT (stack_check_mask
));
7975 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
7977 t
, const0_rtx
, const0_rtx
));
7979 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
7981 t
, const0_rtx
, const0_rtx
));
7986 if (s390_warn_framesize
> 0
7987 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
7988 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
7989 current_function_name (), cfun_frame_layout
.frame_size
);
7991 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
7992 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7994 /* Save incoming stack pointer into temp reg. */
7995 if (TARGET_BACKCHAIN
|| next_fpr
)
7996 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
7998 /* Subtract frame size from stack pointer. */
8000 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8002 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8003 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8005 insn
= emit_insn (insn
);
8009 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8010 frame_off
= force_const_mem (Pmode
, frame_off
);
8012 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8013 annotate_constant_pool_refs (&PATTERN (insn
));
8016 RTX_FRAME_RELATED_P (insn
) = 1;
8017 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8018 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8019 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8020 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8023 /* Set backchain. */
8025 if (TARGET_BACKCHAIN
)
8027 if (cfun_frame_layout
.backchain_offset
)
8028 addr
= gen_rtx_MEM (Pmode
,
8029 plus_constant (stack_pointer_rtx
,
8030 cfun_frame_layout
.backchain_offset
));
8032 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8033 set_mem_alias_set (addr
, get_frame_alias_set ());
8034 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8037 /* If we support non-call exceptions (e.g. for Java),
8038 we need to make sure the backchain pointer is set up
8039 before any possibly trapping memory access. */
8040 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8042 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8043 emit_clobber (addr
);
8047 /* Save fprs 8 - 15 (64 bit ABI). */
8049 if (cfun_save_high_fprs_p
&& next_fpr
)
8051 /* If the stack might be accessed through a different register
8052 we have to make sure that the stack pointer decrement is not
8053 moved below the use of the stack slots. */
8054 s390_emit_stack_tie ();
8056 insn
= emit_insn (gen_add2_insn (temp_reg
,
8057 GEN_INT (cfun_frame_layout
.f8_offset
)));
8061 for (i
= 24; i
<= next_fpr
; i
++)
8062 if (cfun_fpr_bit_p (i
- 16))
8064 rtx addr
= plus_constant (stack_pointer_rtx
,
8065 cfun_frame_layout
.frame_size
8066 + cfun_frame_layout
.f8_offset
8069 insn
= save_fpr (temp_reg
, offset
, i
);
8071 RTX_FRAME_RELATED_P (insn
) = 1;
8072 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8073 gen_rtx_SET (VOIDmode
,
8074 gen_rtx_MEM (DFmode
, addr
),
8075 gen_rtx_REG (DFmode
, i
)));
8079 /* Set frame pointer, if needed. */
8081 if (frame_pointer_needed
)
8083 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8084 RTX_FRAME_RELATED_P (insn
) = 1;
8087 /* Set up got pointer, if needed. */
8089 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8091 rtx insns
= s390_load_got ();
8093 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8094 annotate_constant_pool_refs (&PATTERN (insn
));
8099 if (TARGET_TPF_PROFILING
)
8101 /* Generate a BAS instruction to serve as a function
8102 entry intercept to facilitate the use of tracing
8103 algorithms located at the branch target. */
8104 emit_insn (gen_prologue_tpf ());
8106 /* Emit a blockage here so that all code
8107 lies between the profiling mechanisms. */
8108 emit_insn (gen_blockage ());
8112 /* Expand the epilogue into a bunch of separate insns. */
8115 s390_emit_epilogue (bool sibcall
)
8117 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8118 int area_bottom
, area_top
, offset
= 0;
8123 if (TARGET_TPF_PROFILING
)
8126 /* Generate a BAS instruction to serve as a function
8127 entry intercept to facilitate the use of tracing
8128 algorithms located at the branch target. */
8130 /* Emit a blockage here so that all code
8131 lies between the profiling mechanisms. */
8132 emit_insn (gen_blockage ());
8134 emit_insn (gen_epilogue_tpf ());
8137 /* Check whether to use frame or stack pointer for restore. */
8139 frame_pointer
= (frame_pointer_needed
8140 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8142 s390_frame_area (&area_bottom
, &area_top
);
8144 /* Check whether we can access the register save area.
8145 If not, increment the frame pointer as required. */
8147 if (area_top
<= area_bottom
)
8149 /* Nothing to restore. */
8151 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8152 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8154 /* Area is in range. */
8155 offset
= cfun_frame_layout
.frame_size
;
8159 rtx insn
, frame_off
, cfa
;
8161 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8162 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8164 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8165 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8166 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8168 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8169 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8170 insn
= emit_insn (insn
);
8174 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8175 frame_off
= force_const_mem (Pmode
, frame_off
);
8177 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8178 annotate_constant_pool_refs (&PATTERN (insn
));
8180 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8181 RTX_FRAME_RELATED_P (insn
) = 1;
8184 /* Restore call saved fprs. */
8188 if (cfun_save_high_fprs_p
)
8190 next_offset
= cfun_frame_layout
.f8_offset
;
8191 for (i
= 24; i
< 32; i
++)
8193 if (cfun_fpr_bit_p (i
- 16))
8195 restore_fpr (frame_pointer
,
8196 offset
+ next_offset
, i
);
8198 = alloc_reg_note (REG_CFA_RESTORE
,
8199 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8208 next_offset
= cfun_frame_layout
.f4_offset
;
8209 for (i
= 18; i
< 20; i
++)
8211 if (cfun_fpr_bit_p (i
- 16))
8213 restore_fpr (frame_pointer
,
8214 offset
+ next_offset
, i
);
8216 = alloc_reg_note (REG_CFA_RESTORE
,
8217 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8220 else if (!TARGET_PACKED_STACK
)
8226 /* Return register. */
8228 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8230 /* Restore call saved gprs. */
8232 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8237 /* Check for global register and save them
8238 to stack location from where they get restored. */
8240 for (i
= cfun_frame_layout
.first_restore_gpr
;
8241 i
<= cfun_frame_layout
.last_restore_gpr
;
8244 if (global_not_special_regno_p (i
))
8246 addr
= plus_constant (frame_pointer
,
8247 offset
+ cfun_frame_layout
.gprs_offset
8248 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8250 addr
= gen_rtx_MEM (Pmode
, addr
);
8251 set_mem_alias_set (addr
, get_frame_alias_set ());
8252 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8256 = alloc_reg_note (REG_CFA_RESTORE
,
8257 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8262 /* Fetch return address from stack before load multiple,
8263 this will do good for scheduling. */
8265 if (cfun_frame_layout
.save_return_addr_p
8266 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8267 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8269 int return_regnum
= find_unused_clobbered_reg();
8272 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8274 addr
= plus_constant (frame_pointer
,
8275 offset
+ cfun_frame_layout
.gprs_offset
8277 - cfun_frame_layout
.first_save_gpr_slot
)
8279 addr
= gen_rtx_MEM (Pmode
, addr
);
8280 set_mem_alias_set (addr
, get_frame_alias_set ());
8281 emit_move_insn (return_reg
, addr
);
8285 insn
= restore_gprs (frame_pointer
,
8286 offset
+ cfun_frame_layout
.gprs_offset
8287 + (cfun_frame_layout
.first_restore_gpr
8288 - cfun_frame_layout
.first_save_gpr_slot
)
8290 cfun_frame_layout
.first_restore_gpr
,
8291 cfun_frame_layout
.last_restore_gpr
);
8292 insn
= emit_insn (insn
);
8293 REG_NOTES (insn
) = cfa_restores
;
8294 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8295 plus_constant (stack_pointer_rtx
, STACK_POINTER_OFFSET
));
8296 RTX_FRAME_RELATED_P (insn
) = 1;
8302 /* Return to caller. */
8304 p
= rtvec_alloc (2);
8306 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
8307 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8308 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8313 /* Return the size in bytes of a function argument of
8314 type TYPE and/or mode MODE. At least one of TYPE or
8315 MODE must be specified. */
8318 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8321 return int_size_in_bytes (type
);
8323 /* No type info available for some library calls ... */
8324 if (mode
!= BLKmode
)
8325 return GET_MODE_SIZE (mode
);
8327 /* If we have neither type nor mode, abort */
8331 /* Return true if a function argument of type TYPE and mode MODE
8332 is to be passed in a floating-point register, if available. */
8335 s390_function_arg_float (enum machine_mode mode
, const_tree type
)
8337 int size
= s390_function_arg_size (mode
, type
);
8341 /* Soft-float changes the ABI: no floating-point registers are used. */
8342 if (TARGET_SOFT_FLOAT
)
8345 /* No type info available for some library calls ... */
8347 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8349 /* The ABI says that record types with a single member are treated
8350 just like that member would be. */
8351 while (TREE_CODE (type
) == RECORD_TYPE
)
8353 tree field
, single
= NULL_TREE
;
8355 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8357 if (TREE_CODE (field
) != FIELD_DECL
)
8360 if (single
== NULL_TREE
)
8361 single
= TREE_TYPE (field
);
8366 if (single
== NULL_TREE
)
8372 return TREE_CODE (type
) == REAL_TYPE
;
8375 /* Return true if a function argument of type TYPE and mode MODE
8376 is to be passed in an integer register, or a pair of integer
8377 registers, if available. */
8380 s390_function_arg_integer (enum machine_mode mode
, const_tree type
)
8382 int size
= s390_function_arg_size (mode
, type
);
8386 /* No type info available for some library calls ... */
8388 return GET_MODE_CLASS (mode
) == MODE_INT
8389 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8391 /* We accept small integral (and similar) types. */
8392 if (INTEGRAL_TYPE_P (type
)
8393 || POINTER_TYPE_P (type
)
8394 || TREE_CODE (type
) == OFFSET_TYPE
8395 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8398 /* We also accept structs of size 1, 2, 4, 8 that are not
8399 passed in floating-point registers. */
8400 if (AGGREGATE_TYPE_P (type
)
8401 && exact_log2 (size
) >= 0
8402 && !s390_function_arg_float (mode
, type
))
8408 /* Return 1 if a function argument of type TYPE and mode MODE
8409 is to be passed by reference. The ABI specifies that only
8410 structures of size 1, 2, 4, or 8 bytes are passed by value,
8411 all other structures (and complex numbers) are passed by
8415 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
8416 enum machine_mode mode
, const_tree type
,
8417 bool named ATTRIBUTE_UNUSED
)
8419 int size
= s390_function_arg_size (mode
, type
);
8425 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8428 if (TREE_CODE (type
) == COMPLEX_TYPE
8429 || TREE_CODE (type
) == VECTOR_TYPE
)
8436 /* Update the data in CUM to advance over an argument of mode MODE and
8437 data type TYPE. (TYPE is null for libcalls where that information
8438 may not be available.). The boolean NAMED specifies whether the
8439 argument is a named argument (as opposed to an unnamed argument
8440 matching an ellipsis). */
8443 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8444 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8446 if (s390_function_arg_float (mode
, type
))
8450 else if (s390_function_arg_integer (mode
, type
))
8452 int size
= s390_function_arg_size (mode
, type
);
8453 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8459 /* Define where to put the arguments to a function.
8460 Value is zero to push the argument on the stack,
8461 or a hard register in which to store the argument.
8463 MODE is the argument's machine mode.
8464 TYPE is the data type of the argument (as a tree).
8465 This is null for libcalls where that information may
8467 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8468 the preceding args and about the function being called.
8469 NAMED is nonzero if this argument is a named parameter
8470 (otherwise it is an extra parameter matching an ellipsis).
8472 On S/390, we use general purpose registers 2 through 6 to
8473 pass integer, pointer, and certain structure arguments, and
8474 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8475 to pass floating point arguments. All remaining arguments
8476 are pushed to the stack. */
8479 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8480 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8482 if (s390_function_arg_float (mode
, type
))
8484 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8487 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8489 else if (s390_function_arg_integer (mode
, type
))
8491 int size
= s390_function_arg_size (mode
, type
);
8492 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8494 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8496 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8497 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8498 else if (n_gprs
== 2)
8500 rtvec p
= rtvec_alloc (2);
8503 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8506 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8509 return gen_rtx_PARALLEL (mode
, p
);
8513 /* After the real arguments, expand_call calls us once again
8514 with a void_type_node type. Whatever we return here is
8515 passed as operand 2 to the call expanders.
8517 We don't need this feature ... */
8518 else if (type
== void_type_node
)
8524 /* Return true if return values of type TYPE should be returned
8525 in a memory buffer whose address is passed by the caller as
8526 hidden first argument. */
8529 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8531 /* We accept small integral (and similar) types. */
8532 if (INTEGRAL_TYPE_P (type
)
8533 || POINTER_TYPE_P (type
)
8534 || TREE_CODE (type
) == OFFSET_TYPE
8535 || TREE_CODE (type
) == REAL_TYPE
)
8536 return int_size_in_bytes (type
) > 8;
8538 /* Aggregates and similar constructs are always returned
8540 if (AGGREGATE_TYPE_P (type
)
8541 || TREE_CODE (type
) == COMPLEX_TYPE
8542 || TREE_CODE (type
) == VECTOR_TYPE
)
8545 /* ??? We get called on all sorts of random stuff from
8546 aggregate_value_p. We can't abort, but it's not clear
8547 what's safe to return. Pretend it's a struct I guess. */
8551 /* Function arguments and return values are promoted to word size. */
8553 static enum machine_mode
8554 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8556 const_tree fntype ATTRIBUTE_UNUSED
,
8557 int for_return ATTRIBUTE_UNUSED
)
8559 if (INTEGRAL_MODE_P (mode
)
8560 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8562 if (POINTER_TYPE_P (type
))
8563 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8570 /* Define where to return a (scalar) value of type TYPE.
8571 If TYPE is null, define where to return a (scalar)
8572 value of mode MODE from a libcall. */
8575 s390_function_value (const_tree type
, const_tree fn
, enum machine_mode mode
)
8579 int unsignedp
= TYPE_UNSIGNED (type
);
8580 mode
= promote_function_mode (type
, TYPE_MODE (type
), &unsignedp
, fn
, 1);
8583 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8584 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8586 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8587 return gen_rtx_REG (mode
, 16);
8588 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8589 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8590 return gen_rtx_REG (mode
, 2);
8591 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8593 rtvec p
= rtvec_alloc (2);
8596 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8598 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8600 return gen_rtx_PARALLEL (mode
, p
);
8607 /* Create and return the va_list datatype.
8609 On S/390, va_list is an array type equivalent to
8611 typedef struct __va_list_tag
8615 void *__overflow_arg_area;
8616 void *__reg_save_area;
8619 where __gpr and __fpr hold the number of general purpose
8620 or floating point arguments used up to now, respectively,
8621 __overflow_arg_area points to the stack location of the
8622 next argument passed on the stack, and __reg_save_area
8623 always points to the start of the register area in the
8624 call frame of the current function. The function prologue
8625 saves all registers used for argument passing into this
8626 area if the function uses variable arguments. */
8629 s390_build_builtin_va_list (void)
8631 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8633 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8636 build_decl (BUILTINS_LOCATION
,
8637 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8639 f_gpr
= build_decl (BUILTINS_LOCATION
,
8640 FIELD_DECL
, get_identifier ("__gpr"),
8641 long_integer_type_node
);
8642 f_fpr
= build_decl (BUILTINS_LOCATION
,
8643 FIELD_DECL
, get_identifier ("__fpr"),
8644 long_integer_type_node
);
8645 f_ovf
= build_decl (BUILTINS_LOCATION
,
8646 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8648 f_sav
= build_decl (BUILTINS_LOCATION
,
8649 FIELD_DECL
, get_identifier ("__reg_save_area"),
8652 va_list_gpr_counter_field
= f_gpr
;
8653 va_list_fpr_counter_field
= f_fpr
;
8655 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8656 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8657 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8658 DECL_FIELD_CONTEXT (f_sav
) = record
;
8660 TREE_CHAIN (record
) = type_decl
;
8661 TYPE_NAME (record
) = type_decl
;
8662 TYPE_FIELDS (record
) = f_gpr
;
8663 DECL_CHAIN (f_gpr
) = f_fpr
;
8664 DECL_CHAIN (f_fpr
) = f_ovf
;
8665 DECL_CHAIN (f_ovf
) = f_sav
;
8667 layout_type (record
);
8669 /* The correct type is an array type of one element. */
8670 return build_array_type (record
, build_index_type (size_zero_node
));
8673 /* Implement va_start by filling the va_list structure VALIST.
8674 STDARG_P is always true, and ignored.
8675 NEXTARG points to the first anonymous stack argument.
8677 The following global variables are used to initialize
8678 the va_list structure:
8681 holds number of gprs and fprs used for named arguments.
8682 crtl->args.arg_offset_rtx:
8683 holds the offset of the first anonymous stack argument
8684 (relative to the virtual arg pointer). */
8687 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8689 HOST_WIDE_INT n_gpr
, n_fpr
;
8691 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8692 tree gpr
, fpr
, ovf
, sav
, t
;
8694 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8695 f_fpr
= DECL_CHAIN (f_gpr
);
8696 f_ovf
= DECL_CHAIN (f_fpr
);
8697 f_sav
= DECL_CHAIN (f_ovf
);
8699 valist
= build_va_arg_indirect_ref (valist
);
8700 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8701 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8702 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8703 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8705 /* Count number of gp and fp argument registers used. */
8707 n_gpr
= crtl
->args
.info
.gprs
;
8708 n_fpr
= crtl
->args
.info
.fprs
;
8710 if (cfun
->va_list_gpr_size
)
8712 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8713 build_int_cst (NULL_TREE
, n_gpr
));
8714 TREE_SIDE_EFFECTS (t
) = 1;
8715 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8718 if (cfun
->va_list_fpr_size
)
8720 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8721 build_int_cst (NULL_TREE
, n_fpr
));
8722 TREE_SIDE_EFFECTS (t
) = 1;
8723 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8726 /* Find the overflow area. */
8727 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8728 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8730 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8732 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8733 off
= off
< 0 ? 0 : off
;
8734 if (TARGET_DEBUG_ARG
)
8735 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8736 (int)n_gpr
, (int)n_fpr
, off
);
8738 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8740 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8741 TREE_SIDE_EFFECTS (t
) = 1;
8742 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8745 /* Find the register save area. */
8746 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8747 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8749 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8750 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
8751 size_int (-RETURN_REGNUM
* UNITS_PER_LONG
));
8753 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8754 TREE_SIDE_EFFECTS (t
) = 1;
8755 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8759 /* Implement va_arg by updating the va_list structure
8760 VALIST as required to retrieve an argument of type
8761 TYPE, and returning that argument.
8763 Generates code equivalent to:
8765 if (integral value) {
8766 if (size <= 4 && args.gpr < 5 ||
8767 size > 4 && args.gpr < 4 )
8768 ret = args.reg_save_area[args.gpr+8]
8770 ret = *args.overflow_arg_area++;
8771 } else if (float value) {
8773 ret = args.reg_save_area[args.fpr+64]
8775 ret = *args.overflow_arg_area++;
8776 } else if (aggregate value) {
8778 ret = *args.reg_save_area[args.gpr]
8780 ret = **args.overflow_arg_area++;
8784 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8785 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8787 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8788 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8789 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8790 tree lab_false
, lab_over
, addr
;
8792 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8793 f_fpr
= DECL_CHAIN (f_gpr
);
8794 f_ovf
= DECL_CHAIN (f_fpr
);
8795 f_sav
= DECL_CHAIN (f_ovf
);
8797 valist
= build_va_arg_indirect_ref (valist
);
8798 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8799 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8800 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8802 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8803 both appear on a lhs. */
8804 valist
= unshare_expr (valist
);
8805 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8807 size
= int_size_in_bytes (type
);
8809 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8811 if (TARGET_DEBUG_ARG
)
8813 fprintf (stderr
, "va_arg: aggregate type");
8817 /* Aggregates are passed by reference. */
8822 /* kernel stack layout on 31 bit: It is assumed here that no padding
8823 will be added by s390_frame_info because for va_args always an even
8824 number of gprs has to be saved r15-r2 = 14 regs. */
8825 sav_ofs
= 2 * UNITS_PER_LONG
;
8826 sav_scale
= UNITS_PER_LONG
;
8827 size
= UNITS_PER_LONG
;
8828 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8830 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8832 if (TARGET_DEBUG_ARG
)
8834 fprintf (stderr
, "va_arg: float type");
8838 /* FP args go in FP registers, if present. */
8842 sav_ofs
= 16 * UNITS_PER_LONG
;
8844 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8848 if (TARGET_DEBUG_ARG
)
8850 fprintf (stderr
, "va_arg: other type");
8854 /* Otherwise into GP registers. */
8857 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8859 /* kernel stack layout on 31 bit: It is assumed here that no padding
8860 will be added by s390_frame_info because for va_args always an even
8861 number of gprs has to be saved r15-r2 = 14 regs. */
8862 sav_ofs
= 2 * UNITS_PER_LONG
;
8864 if (size
< UNITS_PER_LONG
)
8865 sav_ofs
+= UNITS_PER_LONG
- size
;
8867 sav_scale
= UNITS_PER_LONG
;
8868 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8871 /* Pull the value out of the saved registers ... */
8873 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
8874 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
8875 addr
= create_tmp_var (ptr_type_node
, "addr");
8877 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
8878 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
8879 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
8880 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
8881 gimplify_and_add (t
, pre_p
);
8883 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
8884 size_int (sav_ofs
));
8885 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
8886 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
8887 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
8889 gimplify_assign (addr
, t
, pre_p
);
8891 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
8893 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
8896 /* ... Otherwise out of the overflow area. */
8899 if (size
< UNITS_PER_LONG
)
8900 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8901 size_int (UNITS_PER_LONG
- size
));
8903 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
8905 gimplify_assign (addr
, t
, pre_p
);
8907 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8909 gimplify_assign (ovf
, t
, pre_p
);
8911 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
8914 /* Increment register save count. */
8916 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
8917 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
8918 gimplify_and_add (u
, pre_p
);
8922 t
= build_pointer_type_for_mode (build_pointer_type (type
),
8924 addr
= fold_convert (t
, addr
);
8925 addr
= build_va_arg_indirect_ref (addr
);
8929 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
8930 addr
= fold_convert (t
, addr
);
8933 return build_va_arg_indirect_ref (addr
);
8941 S390_BUILTIN_THREAD_POINTER
,
8942 S390_BUILTIN_SET_THREAD_POINTER
,
8947 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
8952 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
8958 s390_init_builtins (void)
8962 ftype
= build_function_type (ptr_type_node
, void_list_node
);
8963 add_builtin_function ("__builtin_thread_pointer", ftype
,
8964 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
8967 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
8968 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
8969 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
8973 /* Expand an expression EXP that calls a built-in function,
8974 with result going to TARGET if that's convenient
8975 (and in mode MODE if that's convenient).
8976 SUBTARGET may be used as the target for computing one of EXP's operands.
8977 IGNORE is nonzero if the value is to be ignored. */
8980 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8981 enum machine_mode mode ATTRIBUTE_UNUSED
,
8982 int ignore ATTRIBUTE_UNUSED
)
8986 enum insn_code
const *code_for_builtin
=
8987 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
8989 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8990 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8991 enum insn_code icode
;
8992 rtx op
[MAX_ARGS
], pat
;
8996 call_expr_arg_iterator iter
;
8998 if (fcode
>= S390_BUILTIN_max
)
8999 internal_error ("bad builtin fcode");
9000 icode
= code_for_builtin
[fcode
];
9002 internal_error ("bad builtin fcode");
9004 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9007 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9009 const struct insn_operand_data
*insn_op
;
9011 if (arg
== error_mark_node
)
9013 if (arity
> MAX_ARGS
)
9016 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
9018 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
9020 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
9021 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
9027 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9029 || GET_MODE (target
) != tmode
9030 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9031 target
= gen_reg_rtx (tmode
);
9037 pat
= GEN_FCN (icode
) (target
);
9041 pat
= GEN_FCN (icode
) (target
, op
[0]);
9043 pat
= GEN_FCN (icode
) (op
[0]);
9046 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9062 /* Output assembly code for the trampoline template to
9065 On S/390, we use gpr 1 internally in the trampoline code;
9066 gpr 0 is used to hold the static chain. */
9069 s390_asm_trampoline_template (FILE *file
)
9072 op
[0] = gen_rtx_REG (Pmode
, 0);
9073 op
[1] = gen_rtx_REG (Pmode
, 1);
9077 output_asm_insn ("basr\t%1,0", op
);
9078 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
9079 output_asm_insn ("br\t%1", op
);
9080 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9084 output_asm_insn ("basr\t%1,0", op
);
9085 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
9086 output_asm_insn ("br\t%1", op
);
9087 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9091 /* Emit RTL insns to initialize the variable parts of a trampoline.
9092 FNADDR is an RTX for the address of the function's pure code.
9093 CXT is an RTX for the static chain value for the function. */
9096 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9098 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9101 emit_block_move (m_tramp
, assemble_trampoline_template (),
9102 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
9104 mem
= adjust_address (m_tramp
, Pmode
, 2*UNITS_PER_WORD
);
9105 emit_move_insn (mem
, cxt
);
9106 mem
= adjust_address (m_tramp
, Pmode
, 3*UNITS_PER_WORD
);
9107 emit_move_insn (mem
, fnaddr
);
9110 /* Output assembler code to FILE to increment profiler label # LABELNO
9111 for profiling a function entry. */
9114 s390_function_profiler (FILE *file
, int labelno
)
9119 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9121 fprintf (file
, "# function profiler \n");
9123 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9124 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9125 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_LONG
));
9127 op
[2] = gen_rtx_REG (Pmode
, 1);
9128 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9129 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9131 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9134 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9135 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9140 output_asm_insn ("stg\t%0,%1", op
);
9141 output_asm_insn ("larl\t%2,%3", op
);
9142 output_asm_insn ("brasl\t%0,%4", op
);
9143 output_asm_insn ("lg\t%0,%1", op
);
9147 op
[6] = gen_label_rtx ();
9149 output_asm_insn ("st\t%0,%1", op
);
9150 output_asm_insn ("bras\t%2,%l6", op
);
9151 output_asm_insn (".long\t%4", op
);
9152 output_asm_insn (".long\t%3", op
);
9153 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9154 output_asm_insn ("l\t%0,0(%2)", op
);
9155 output_asm_insn ("l\t%2,4(%2)", op
);
9156 output_asm_insn ("basr\t%0,%0", op
);
9157 output_asm_insn ("l\t%0,%1", op
);
9161 op
[5] = gen_label_rtx ();
9162 op
[6] = gen_label_rtx ();
9164 output_asm_insn ("st\t%0,%1", op
);
9165 output_asm_insn ("bras\t%2,%l6", op
);
9166 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9167 output_asm_insn (".long\t%4-%l5", op
);
9168 output_asm_insn (".long\t%3-%l5", op
);
9169 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9170 output_asm_insn ("lr\t%0,%2", op
);
9171 output_asm_insn ("a\t%0,0(%2)", op
);
9172 output_asm_insn ("a\t%2,4(%2)", op
);
9173 output_asm_insn ("basr\t%0,%0", op
);
9174 output_asm_insn ("l\t%0,%1", op
);
9178 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9179 into its SYMBOL_REF_FLAGS. */
9182 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9184 default_encode_section_info (decl
, rtl
, first
);
9186 if (TREE_CODE (decl
) == VAR_DECL
)
9188 /* If a variable has a forced alignment to < 2 bytes, mark it
9189 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9191 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9192 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9193 if (!DECL_SIZE (decl
)
9194 || !DECL_ALIGN (decl
)
9195 || !host_integerp (DECL_SIZE (decl
), 0)
9196 || (DECL_ALIGN (decl
) <= 64
9197 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9198 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9201 /* Literal pool references don't have a decl so they are handled
9202 differently here. We rely on the information in the MEM_ALIGN
9203 entry to decide upon natural alignment. */
9205 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9206 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9207 && (MEM_ALIGN (rtl
) == 0
9208 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9209 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9210 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9213 /* Output thunk to FILE that implements a C++ virtual function call (with
9214 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9215 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9216 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9217 relative to the resulting this pointer. */
9220 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9221 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9227 /* Make sure unwind info is emitted for the thunk if needed. */
9228 final_start_function (emit_barrier (), file
, 1);
9230 /* Operand 0 is the target function. */
9231 op
[0] = XEXP (DECL_RTL (function
), 0);
9232 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9235 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9236 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9237 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9240 /* Operand 1 is the 'this' pointer. */
9241 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9242 op
[1] = gen_rtx_REG (Pmode
, 3);
9244 op
[1] = gen_rtx_REG (Pmode
, 2);
9246 /* Operand 2 is the delta. */
9247 op
[2] = GEN_INT (delta
);
9249 /* Operand 3 is the vcall_offset. */
9250 op
[3] = GEN_INT (vcall_offset
);
9252 /* Operand 4 is the temporary register. */
9253 op
[4] = gen_rtx_REG (Pmode
, 1);
9255 /* Operands 5 to 8 can be used as labels. */
9261 /* Operand 9 can be used for temporary register. */
9264 /* Generate code. */
9267 /* Setup literal pool pointer if required. */
9268 if ((!DISP_IN_RANGE (delta
)
9269 && !CONST_OK_FOR_K (delta
)
9270 && !CONST_OK_FOR_Os (delta
))
9271 || (!DISP_IN_RANGE (vcall_offset
)
9272 && !CONST_OK_FOR_K (vcall_offset
)
9273 && !CONST_OK_FOR_Os (vcall_offset
)))
9275 op
[5] = gen_label_rtx ();
9276 output_asm_insn ("larl\t%4,%5", op
);
9279 /* Add DELTA to this pointer. */
9282 if (CONST_OK_FOR_J (delta
))
9283 output_asm_insn ("la\t%1,%2(%1)", op
);
9284 else if (DISP_IN_RANGE (delta
))
9285 output_asm_insn ("lay\t%1,%2(%1)", op
);
9286 else if (CONST_OK_FOR_K (delta
))
9287 output_asm_insn ("aghi\t%1,%2", op
);
9288 else if (CONST_OK_FOR_Os (delta
))
9289 output_asm_insn ("agfi\t%1,%2", op
);
9292 op
[6] = gen_label_rtx ();
9293 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9297 /* Perform vcall adjustment. */
9300 if (DISP_IN_RANGE (vcall_offset
))
9302 output_asm_insn ("lg\t%4,0(%1)", op
);
9303 output_asm_insn ("ag\t%1,%3(%4)", op
);
9305 else if (CONST_OK_FOR_K (vcall_offset
))
9307 output_asm_insn ("lghi\t%4,%3", op
);
9308 output_asm_insn ("ag\t%4,0(%1)", op
);
9309 output_asm_insn ("ag\t%1,0(%4)", op
);
9311 else if (CONST_OK_FOR_Os (vcall_offset
))
9313 output_asm_insn ("lgfi\t%4,%3", op
);
9314 output_asm_insn ("ag\t%4,0(%1)", op
);
9315 output_asm_insn ("ag\t%1,0(%4)", op
);
9319 op
[7] = gen_label_rtx ();
9320 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9321 output_asm_insn ("ag\t%4,0(%1)", op
);
9322 output_asm_insn ("ag\t%1,0(%4)", op
);
9326 /* Jump to target. */
9327 output_asm_insn ("jg\t%0", op
);
9329 /* Output literal pool if required. */
9332 output_asm_insn (".align\t4", op
);
9333 targetm
.asm_out
.internal_label (file
, "L",
9334 CODE_LABEL_NUMBER (op
[5]));
9338 targetm
.asm_out
.internal_label (file
, "L",
9339 CODE_LABEL_NUMBER (op
[6]));
9340 output_asm_insn (".long\t%2", op
);
9344 targetm
.asm_out
.internal_label (file
, "L",
9345 CODE_LABEL_NUMBER (op
[7]));
9346 output_asm_insn (".long\t%3", op
);
9351 /* Setup base pointer if required. */
9353 || (!DISP_IN_RANGE (delta
)
9354 && !CONST_OK_FOR_K (delta
)
9355 && !CONST_OK_FOR_Os (delta
))
9356 || (!DISP_IN_RANGE (delta
)
9357 && !CONST_OK_FOR_K (vcall_offset
)
9358 && !CONST_OK_FOR_Os (vcall_offset
)))
9360 op
[5] = gen_label_rtx ();
9361 output_asm_insn ("basr\t%4,0", op
);
9362 targetm
.asm_out
.internal_label (file
, "L",
9363 CODE_LABEL_NUMBER (op
[5]));
9366 /* Add DELTA to this pointer. */
9369 if (CONST_OK_FOR_J (delta
))
9370 output_asm_insn ("la\t%1,%2(%1)", op
);
9371 else if (DISP_IN_RANGE (delta
))
9372 output_asm_insn ("lay\t%1,%2(%1)", op
);
9373 else if (CONST_OK_FOR_K (delta
))
9374 output_asm_insn ("ahi\t%1,%2", op
);
9375 else if (CONST_OK_FOR_Os (delta
))
9376 output_asm_insn ("afi\t%1,%2", op
);
9379 op
[6] = gen_label_rtx ();
9380 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9384 /* Perform vcall adjustment. */
9387 if (CONST_OK_FOR_J (vcall_offset
))
9389 output_asm_insn ("l\t%4,0(%1)", op
);
9390 output_asm_insn ("a\t%1,%3(%4)", op
);
9392 else if (DISP_IN_RANGE (vcall_offset
))
9394 output_asm_insn ("l\t%4,0(%1)", op
);
9395 output_asm_insn ("ay\t%1,%3(%4)", op
);
9397 else if (CONST_OK_FOR_K (vcall_offset
))
9399 output_asm_insn ("lhi\t%4,%3", op
);
9400 output_asm_insn ("a\t%4,0(%1)", op
);
9401 output_asm_insn ("a\t%1,0(%4)", op
);
9403 else if (CONST_OK_FOR_Os (vcall_offset
))
9405 output_asm_insn ("iilf\t%4,%3", op
);
9406 output_asm_insn ("a\t%4,0(%1)", op
);
9407 output_asm_insn ("a\t%1,0(%4)", op
);
9411 op
[7] = gen_label_rtx ();
9412 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9413 output_asm_insn ("a\t%4,0(%1)", op
);
9414 output_asm_insn ("a\t%1,0(%4)", op
);
9417 /* We had to clobber the base pointer register.
9418 Re-setup the base pointer (with a different base). */
9419 op
[5] = gen_label_rtx ();
9420 output_asm_insn ("basr\t%4,0", op
);
9421 targetm
.asm_out
.internal_label (file
, "L",
9422 CODE_LABEL_NUMBER (op
[5]));
9425 /* Jump to target. */
9426 op
[8] = gen_label_rtx ();
9429 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9431 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9432 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9433 else if (flag_pic
== 1)
9435 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9436 output_asm_insn ("l\t%4,%0(%4)", op
);
9438 else if (flag_pic
== 2)
9440 op
[9] = gen_rtx_REG (Pmode
, 0);
9441 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9442 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9443 output_asm_insn ("ar\t%4,%9", op
);
9444 output_asm_insn ("l\t%4,0(%4)", op
);
9447 output_asm_insn ("br\t%4", op
);
9449 /* Output literal pool. */
9450 output_asm_insn (".align\t4", op
);
9452 if (nonlocal
&& flag_pic
== 2)
9453 output_asm_insn (".long\t%0", op
);
9456 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9457 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9460 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9462 output_asm_insn (".long\t%0", op
);
9464 output_asm_insn (".long\t%0-%5", op
);
9468 targetm
.asm_out
.internal_label (file
, "L",
9469 CODE_LABEL_NUMBER (op
[6]));
9470 output_asm_insn (".long\t%2", op
);
9474 targetm
.asm_out
.internal_label (file
, "L",
9475 CODE_LABEL_NUMBER (op
[7]));
9476 output_asm_insn (".long\t%3", op
);
9479 final_end_function ();
9483 s390_valid_pointer_mode (enum machine_mode mode
)
9485 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9488 /* Checks whether the given CALL_EXPR would use a caller
9489 saved register. This is used to decide whether sibling call
9490 optimization could be performed on the respective function
9494 s390_call_saved_register_used (tree call_expr
)
9496 CUMULATIVE_ARGS cum
;
9498 enum machine_mode mode
;
9503 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
9505 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9507 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9508 gcc_assert (parameter
);
9510 /* For an undeclared variable passed as parameter we will get
9511 an ERROR_MARK node here. */
9512 if (TREE_CODE (parameter
) == ERROR_MARK
)
9515 type
= TREE_TYPE (parameter
);
9518 mode
= TYPE_MODE (type
);
9521 if (pass_by_reference (&cum
, mode
, type
, true))
9524 type
= build_pointer_type (type
);
9527 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
9529 s390_function_arg_advance (&cum
, mode
, type
, 0);
9534 if (REG_P (parm_rtx
))
9537 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9539 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9543 if (GET_CODE (parm_rtx
) == PARALLEL
)
9547 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9549 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9551 gcc_assert (REG_P (r
));
9554 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9556 if (!call_used_regs
[reg
+ REGNO (r
)])
9565 /* Return true if the given call expression can be
9566 turned into a sibling call.
9567 DECL holds the declaration of the function to be called whereas
9568 EXP is the call expression itself. */
9571 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9573 /* The TPF epilogue uses register 1. */
9574 if (TARGET_TPF_PROFILING
)
9577 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9578 which would have to be restored before the sibcall. */
9579 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9582 /* Register 6 on s390 is available as an argument register but unfortunately
9583 "caller saved". This makes functions needing this register for arguments
9584 not suitable for sibcalls. */
9585 return !s390_call_saved_register_used (exp
);
9588 /* Return the fixed registers used for condition codes. */
9591 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9594 *p2
= INVALID_REGNUM
;
9599 /* This function is used by the call expanders of the machine description.
9600 It emits the call insn itself together with the necessary operations
9601 to adjust the target address and returns the emitted insn.
9602 ADDR_LOCATION is the target address rtx
9603 TLS_CALL the location of the thread-local symbol
9604 RESULT_REG the register where the result of the call should be stored
9605 RETADDR_REG the register where the return address should be stored
9606 If this parameter is NULL_RTX the call is considered
9607 to be a sibling call. */
9610 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9613 bool plt_call
= false;
9619 /* Direct function calls need special treatment. */
9620 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9622 /* When calling a global routine in PIC mode, we must
9623 replace the symbol itself with the PLT stub. */
9624 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9626 if (retaddr_reg
!= NULL_RTX
)
9628 addr_location
= gen_rtx_UNSPEC (Pmode
,
9629 gen_rtvec (1, addr_location
),
9631 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9635 /* For -fpic code the PLT entries might use r12 which is
9636 call-saved. Therefore we cannot do a sibcall when
9637 calling directly using a symbol ref. When reaching
9638 this point we decided (in s390_function_ok_for_sibcall)
9639 to do a sibcall for a function pointer but one of the
9640 optimizers was able to get rid of the function pointer
9641 by propagating the symbol ref into the call. This
9642 optimization is illegal for S/390 so we turn the direct
9643 call into a indirect call again. */
9644 addr_location
= force_reg (Pmode
, addr_location
);
9647 /* Unless we can use the bras(l) insn, force the
9648 routine address into a register. */
9649 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9652 addr_location
= legitimize_pic_address (addr_location
, 0);
9654 addr_location
= force_reg (Pmode
, addr_location
);
9658 /* If it is already an indirect call or the code above moved the
9659 SYMBOL_REF to somewhere else make sure the address can be found in
9661 if (retaddr_reg
== NULL_RTX
9662 && GET_CODE (addr_location
) != SYMBOL_REF
9665 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9666 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9669 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9670 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9672 if (result_reg
!= NULL_RTX
)
9673 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9675 if (retaddr_reg
!= NULL_RTX
)
9677 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9679 if (tls_call
!= NULL_RTX
)
9680 vec
= gen_rtvec (3, call
, clobber
,
9681 gen_rtx_USE (VOIDmode
, tls_call
));
9683 vec
= gen_rtvec (2, call
, clobber
);
9685 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9688 insn
= emit_call_insn (call
);
9690 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9691 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9693 /* s390_function_ok_for_sibcall should
9694 have denied sibcalls in this case. */
9695 gcc_assert (retaddr_reg
!= NULL_RTX
);
9697 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9702 /* Implement CONDITIONAL_REGISTER_USAGE. */
9705 s390_conditional_register_usage (void)
9711 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9712 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9714 if (TARGET_CPU_ZARCH
)
9716 fixed_regs
[BASE_REGNUM
] = 0;
9717 call_used_regs
[BASE_REGNUM
] = 0;
9718 fixed_regs
[RETURN_REGNUM
] = 0;
9719 call_used_regs
[RETURN_REGNUM
] = 0;
9723 for (i
= 24; i
< 32; i
++)
9724 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9728 for (i
= 18; i
< 20; i
++)
9729 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9732 if (TARGET_SOFT_FLOAT
)
9734 for (i
= 16; i
< 32; i
++)
9735 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9739 /* Corresponding function to eh_return expander. */
9741 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9743 s390_emit_tpf_eh_return (rtx target
)
9747 if (!s390_tpf_eh_return_symbol
)
9748 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9750 reg
= gen_rtx_REG (Pmode
, 2);
9752 emit_move_insn (reg
, target
);
9753 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9754 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9755 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9757 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9760 /* Rework the prologue/epilogue to avoid saving/restoring
9761 registers unnecessarily. */
9764 s390_optimize_prologue (void)
9766 rtx insn
, new_insn
, next_insn
;
9768 /* Do a final recompute of the frame-related data. */
9770 s390_update_frame_layout ();
9772 /* If all special registers are in fact used, there's nothing we
9773 can do, so no point in walking the insn list. */
9775 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9776 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9777 && (TARGET_CPU_ZARCH
9778 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9779 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9782 /* Search for prologue/epilogue insns and replace them. */
9784 for (insn
= get_insns (); insn
; insn
= next_insn
)
9786 int first
, last
, off
;
9787 rtx set
, base
, offset
;
9789 next_insn
= NEXT_INSN (insn
);
9791 if (GET_CODE (insn
) != INSN
)
9794 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9795 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9797 set
= XVECEXP (PATTERN (insn
), 0, 0);
9798 first
= REGNO (SET_SRC (set
));
9799 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9800 offset
= const0_rtx
;
9801 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9802 off
= INTVAL (offset
);
9804 if (GET_CODE (base
) != REG
|| off
< 0)
9806 if (cfun_frame_layout
.first_save_gpr
!= -1
9807 && (cfun_frame_layout
.first_save_gpr
< first
9808 || cfun_frame_layout
.last_save_gpr
> last
))
9810 if (REGNO (base
) != STACK_POINTER_REGNUM
9811 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9813 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9816 if (cfun_frame_layout
.first_save_gpr
!= -1)
9818 new_insn
= save_gprs (base
,
9819 off
+ (cfun_frame_layout
.first_save_gpr
9820 - first
) * UNITS_PER_LONG
,
9821 cfun_frame_layout
.first_save_gpr
,
9822 cfun_frame_layout
.last_save_gpr
);
9823 new_insn
= emit_insn_before (new_insn
, insn
);
9824 INSN_ADDRESSES_NEW (new_insn
, -1);
9831 if (cfun_frame_layout
.first_save_gpr
== -1
9832 && GET_CODE (PATTERN (insn
)) == SET
9833 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9834 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9835 || (!TARGET_CPU_ZARCH
9836 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9837 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9839 set
= PATTERN (insn
);
9840 first
= REGNO (SET_SRC (set
));
9841 offset
= const0_rtx
;
9842 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9843 off
= INTVAL (offset
);
9845 if (GET_CODE (base
) != REG
|| off
< 0)
9847 if (REGNO (base
) != STACK_POINTER_REGNUM
9848 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9855 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9856 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9858 set
= XVECEXP (PATTERN (insn
), 0, 0);
9859 first
= REGNO (SET_DEST (set
));
9860 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9861 offset
= const0_rtx
;
9862 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9863 off
= INTVAL (offset
);
9865 if (GET_CODE (base
) != REG
|| off
< 0)
9867 if (cfun_frame_layout
.first_restore_gpr
!= -1
9868 && (cfun_frame_layout
.first_restore_gpr
< first
9869 || cfun_frame_layout
.last_restore_gpr
> last
))
9871 if (REGNO (base
) != STACK_POINTER_REGNUM
9872 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9874 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9877 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9879 new_insn
= restore_gprs (base
,
9880 off
+ (cfun_frame_layout
.first_restore_gpr
9881 - first
) * UNITS_PER_LONG
,
9882 cfun_frame_layout
.first_restore_gpr
,
9883 cfun_frame_layout
.last_restore_gpr
);
9884 new_insn
= emit_insn_before (new_insn
, insn
);
9885 INSN_ADDRESSES_NEW (new_insn
, -1);
9892 if (cfun_frame_layout
.first_restore_gpr
== -1
9893 && GET_CODE (PATTERN (insn
)) == SET
9894 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
9895 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
9896 || (!TARGET_CPU_ZARCH
9897 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
9898 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
9900 set
= PATTERN (insn
);
9901 first
= REGNO (SET_DEST (set
));
9902 offset
= const0_rtx
;
9903 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9904 off
= INTVAL (offset
);
9906 if (GET_CODE (base
) != REG
|| off
< 0)
9908 if (REGNO (base
) != STACK_POINTER_REGNUM
9909 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9918 /* On z10 and later the dynamic branch prediction must see the
9919 backward jump within a certain windows. If not it falls back to
9920 the static prediction. This function rearranges the loop backward
9921 branch in a way which makes the static prediction always correct.
9922 The function returns true if it added an instruction. */
9924 s390_fix_long_loop_prediction (rtx insn
)
9926 rtx set
= single_set (insn
);
9927 rtx code_label
, label_ref
, new_label
;
9933 /* This will exclude branch on count and branch on index patterns
9934 since these are correctly statically predicted. */
9936 || SET_DEST (set
) != pc_rtx
9937 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
9940 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
9941 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
9943 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
9945 code_label
= XEXP (label_ref
, 0);
9947 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
9948 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
9949 || (INSN_ADDRESSES (INSN_UID (insn
))
9950 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
9953 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
9954 distance
< PREDICT_DISTANCE
- 6;
9955 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
9956 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
9959 new_label
= gen_label_rtx ();
9960 uncond_jump
= emit_jump_insn_after (
9961 gen_rtx_SET (VOIDmode
, pc_rtx
,
9962 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
9964 emit_label_after (new_label
, uncond_jump
);
9966 tmp
= XEXP (SET_SRC (set
), 1);
9967 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
9968 XEXP (SET_SRC (set
), 2) = tmp
;
9969 INSN_CODE (insn
) = -1;
9971 XEXP (label_ref
, 0) = new_label
;
9972 JUMP_LABEL (insn
) = new_label
;
9973 JUMP_LABEL (uncond_jump
) = code_label
;
9978 /* Returns 1 if INSN reads the value of REG for purposes not related
9979 to addressing of memory, and 0 otherwise. */
9981 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
9983 return reg_referenced_p (reg
, PATTERN (insn
))
9984 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
9987 /* Starting from INSN find_cond_jump looks downwards in the insn
9988 stream for a single jump insn which is the last user of the
9989 condition code set in INSN. */
9991 find_cond_jump (rtx insn
)
9993 for (; insn
; insn
= NEXT_INSN (insn
))
10000 if (!JUMP_P (insn
))
10002 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10007 /* This will be triggered by a return. */
10008 if (GET_CODE (PATTERN (insn
)) != SET
)
10011 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10012 ite
= SET_SRC (PATTERN (insn
));
10014 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10017 cc
= XEXP (XEXP (ite
, 0), 0);
10018 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10021 if (find_reg_note (insn
, REG_DEAD
, cc
))
10029 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10030 the semantics does not change. If NULL_RTX is passed as COND the
10031 function tries to find the conditional jump starting with INSN. */
10033 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10037 if (cond
== NULL_RTX
)
10039 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10040 jump
= jump
? single_set (jump
) : NULL_RTX
;
10042 if (jump
== NULL_RTX
)
10045 cond
= XEXP (XEXP (jump
, 1), 0);
10050 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10053 /* On z10, instructions of the compare-and-branch family have the
10054 property to access the register occurring as second operand with
10055 its bits complemented. If such a compare is grouped with a second
10056 instruction that accesses the same register non-complemented, and
10057 if that register's value is delivered via a bypass, then the
10058 pipeline recycles, thereby causing significant performance decline.
10059 This function locates such situations and exchanges the two
10060 operands of the compare. The function return true whenever it
10063 s390_z10_optimize_cmp (rtx insn
)
10065 rtx prev_insn
, next_insn
;
10066 bool insn_added_p
= false;
10067 rtx cond
, *op0
, *op1
;
10069 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10071 /* Handle compare and branch and branch on count
10073 rtx pattern
= single_set (insn
);
10076 || SET_DEST (pattern
) != pc_rtx
10077 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10080 cond
= XEXP (SET_SRC (pattern
), 0);
10081 op0
= &XEXP (cond
, 0);
10082 op1
= &XEXP (cond
, 1);
10084 else if (GET_CODE (PATTERN (insn
)) == SET
)
10088 /* Handle normal compare instructions. */
10089 src
= SET_SRC (PATTERN (insn
));
10090 dest
= SET_DEST (PATTERN (insn
));
10093 || !CC_REGNO_P (REGNO (dest
))
10094 || GET_CODE (src
) != COMPARE
)
10097 /* s390_swap_cmp will try to find the conditional
10098 jump when passing NULL_RTX as condition. */
10100 op0
= &XEXP (src
, 0);
10101 op1
= &XEXP (src
, 1);
10106 if (!REG_P (*op0
) || !REG_P (*op1
))
10109 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10112 /* Swap the COMPARE arguments and its mask if there is a
10113 conflicting access in the previous insn. */
10114 prev_insn
= prev_active_insn (insn
);
10115 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10116 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10117 s390_swap_cmp (cond
, op0
, op1
, insn
);
10119 /* Check if there is a conflict with the next insn. If there
10120 was no conflict with the previous insn, then swap the
10121 COMPARE arguments and its mask. If we already swapped
10122 the operands, or if swapping them would cause a conflict
10123 with the previous insn, issue a NOP after the COMPARE in
10124 order to separate the two instuctions. */
10125 next_insn
= next_active_insn (insn
);
10126 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10127 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10129 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10130 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10132 if (REGNO (*op1
) == 0)
10133 emit_insn_after (gen_nop1 (), insn
);
10135 emit_insn_after (gen_nop (), insn
);
10136 insn_added_p
= true;
10139 s390_swap_cmp (cond
, op0
, op1
, insn
);
10141 return insn_added_p
;
10144 /* Perform machine-dependent processing. */
10149 bool pool_overflow
= false;
10151 /* Make sure all splits have been performed; splits after
10152 machine_dependent_reorg might confuse insn length counts. */
10153 split_all_insns_noflow ();
10155 /* Install the main literal pool and the associated base
10156 register load insns.
10158 In addition, there are two problematic situations we need
10161 - the literal pool might be > 4096 bytes in size, so that
10162 some of its elements cannot be directly accessed
10164 - a branch target might be > 64K away from the branch, so that
10165 it is not possible to use a PC-relative instruction.
10167 To fix those, we split the single literal pool into multiple
10168 pool chunks, reloading the pool base register at various
10169 points throughout the function to ensure it always points to
10170 the pool chunk the following code expects, and / or replace
10171 PC-relative branches by absolute branches.
10173 However, the two problems are interdependent: splitting the
10174 literal pool can move a branch further away from its target,
10175 causing the 64K limit to overflow, and on the other hand,
10176 replacing a PC-relative branch by an absolute branch means
10177 we need to put the branch target address into the literal
10178 pool, possibly causing it to overflow.
10180 So, we loop trying to fix up both problems until we manage
10181 to satisfy both conditions at the same time. Note that the
10182 loop is guaranteed to terminate as every pass of the loop
10183 strictly decreases the total number of PC-relative branches
10184 in the function. (This is not completely true as there
10185 might be branch-over-pool insns introduced by chunkify_start.
10186 Those never need to be split however.) */
10190 struct constant_pool
*pool
= NULL
;
10192 /* Collect the literal pool. */
10193 if (!pool_overflow
)
10195 pool
= s390_mainpool_start ();
10197 pool_overflow
= true;
10200 /* If literal pool overflowed, start to chunkify it. */
10202 pool
= s390_chunkify_start ();
10204 /* Split out-of-range branches. If this has created new
10205 literal pool entries, cancel current chunk list and
10206 recompute it. zSeries machines have large branch
10207 instructions, so we never need to split a branch. */
10208 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10211 s390_chunkify_cancel (pool
);
10213 s390_mainpool_cancel (pool
);
10218 /* If we made it up to here, both conditions are satisfied.
10219 Finish up literal pool related changes. */
10221 s390_chunkify_finish (pool
);
10223 s390_mainpool_finish (pool
);
10225 /* We're done splitting branches. */
10226 cfun
->machine
->split_branches_pending_p
= false;
10230 /* Generate out-of-pool execute target insns. */
10231 if (TARGET_CPU_ZARCH
)
10233 rtx insn
, label
, target
;
10235 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10237 label
= s390_execute_label (insn
);
10241 gcc_assert (label
!= const0_rtx
);
10243 target
= emit_label (XEXP (label
, 0));
10244 INSN_ADDRESSES_NEW (target
, -1);
10246 target
= emit_insn (s390_execute_target (insn
));
10247 INSN_ADDRESSES_NEW (target
, -1);
10251 /* Try to optimize prologue and epilogue further. */
10252 s390_optimize_prologue ();
10254 /* Walk over the insns and do some >=z10 specific changes. */
10255 if (s390_tune
== PROCESSOR_2097_Z10
10256 || s390_tune
== PROCESSOR_2817_Z196
)
10259 bool insn_added_p
= false;
10261 /* The insn lengths and addresses have to be up to date for the
10262 following manipulations. */
10263 shorten_branches (get_insns ());
10265 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10267 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10271 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10273 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10274 || GET_CODE (PATTERN (insn
)) == SET
)
10275 && s390_tune
== PROCESSOR_2097_Z10
)
10276 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10279 /* Adjust branches if we added new instructions. */
10281 shorten_branches (get_insns ());
10285 /* Return true if INSN is a fp load insn writing register REGNO. */
10287 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10290 enum attr_type flag
= s390_safe_attr_type (insn
);
10292 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10295 set
= single_set (insn
);
10297 if (set
== NULL_RTX
)
10300 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10303 if (REGNO (SET_DEST (set
)) != regno
)
10309 /* This value describes the distance to be avoided between an
10310 aritmetic fp instruction and an fp load writing the same register.
10311 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10312 fine but the exact value has to be avoided. Otherwise the FP
10313 pipeline will throw an exception causing a major penalty. */
10314 #define Z10_EARLYLOAD_DISTANCE 7
10316 /* Rearrange the ready list in order to avoid the situation described
10317 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10318 moved to the very end of the ready list. */
10320 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10322 unsigned int regno
;
10323 int nready
= *nready_p
;
10328 enum attr_type flag
;
10331 /* Skip DISTANCE - 1 active insns. */
10332 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10333 distance
> 0 && insn
!= NULL_RTX
;
10334 distance
--, insn
= prev_active_insn (insn
))
10335 if (CALL_P (insn
) || JUMP_P (insn
))
10338 if (insn
== NULL_RTX
)
10341 set
= single_set (insn
);
10343 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10344 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10347 flag
= s390_safe_attr_type (insn
);
10349 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10352 regno
= REGNO (SET_DEST (set
));
10355 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10362 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10366 /* This function is called via hook TARGET_SCHED_REORDER before
10367 issueing one insn from list READY which contains *NREADYP entries.
10368 For target z10 it reorders load instructions to avoid early load
10369 conflicts in the floating point pipeline */
10371 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10372 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10374 if (s390_tune
== PROCESSOR_2097_Z10
)
10375 if (reload_completed
&& *nreadyp
> 1)
10376 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10378 return s390_issue_rate ();
10381 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10382 the scheduler has issued INSN. It stores the last issued insn into
10383 last_scheduled_insn in order to make it available for
10384 s390_sched_reorder. */
10386 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10387 int verbose ATTRIBUTE_UNUSED
,
10388 rtx insn
, int more
)
10390 last_scheduled_insn
= insn
;
10392 if (GET_CODE (PATTERN (insn
)) != USE
10393 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10400 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10401 int verbose ATTRIBUTE_UNUSED
,
10402 int max_ready ATTRIBUTE_UNUSED
)
10404 last_scheduled_insn
= NULL_RTX
;
10407 /* This function checks the whole of insn X for memory references. The
10408 function always returns zero because the framework it is called
10409 from would stop recursively analyzing the insn upon a return value
10410 other than zero. The real result of this function is updating
10411 counter variable MEM_COUNT. */
10413 check_dpu (rtx
*x
, unsigned *mem_count
)
10415 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10420 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10421 a new number struct loop *loop should be unrolled if tuned for cpus with
10422 a built-in stride prefetcher.
10423 The loop is analyzed for memory accesses by calling check_dpu for
10424 each rtx of the loop. Depending on the loop_depth and the amount of
10425 memory accesses a new number <=nunroll is returned to improve the
10426 behaviour of the hardware prefetch unit. */
10428 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10433 unsigned mem_count
= 0;
10435 if (s390_tune
!= PROCESSOR_2097_Z10
&& s390_tune
!= PROCESSOR_2817_Z196
)
10438 /* Count the number of memory references within the loop body. */
10439 bbs
= get_loop_body (loop
);
10440 for (i
= 0; i
< loop
->num_nodes
; i
++)
10442 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10443 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10444 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10448 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10449 if (mem_count
== 0)
10452 switch (loop_depth(loop
))
10455 return MIN (nunroll
, 28 / mem_count
);
10457 return MIN (nunroll
, 22 / mem_count
);
10459 return MIN (nunroll
, 16 / mem_count
);
10463 /* Initialize GCC target structure. */
10465 #undef TARGET_ASM_ALIGNED_HI_OP
10466 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10467 #undef TARGET_ASM_ALIGNED_DI_OP
10468 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10469 #undef TARGET_ASM_INTEGER
10470 #define TARGET_ASM_INTEGER s390_assemble_integer
10472 #undef TARGET_ASM_OPEN_PAREN
10473 #define TARGET_ASM_OPEN_PAREN ""
10475 #undef TARGET_ASM_CLOSE_PAREN
10476 #define TARGET_ASM_CLOSE_PAREN ""
10478 #undef TARGET_DEFAULT_TARGET_FLAGS
10479 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10481 #undef TARGET_HANDLE_OPTION
10482 #define TARGET_HANDLE_OPTION s390_handle_option
10484 #undef TARGET_OPTION_OVERRIDE
10485 #define TARGET_OPTION_OVERRIDE s390_option_override
10487 #undef TARGET_OPTION_OPTIMIZATION
10488 #define TARGET_OPTION_OPTIMIZATION s390_option_optimization
10490 #undef TARGET_ENCODE_SECTION_INFO
10491 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10493 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10494 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10497 #undef TARGET_HAVE_TLS
10498 #define TARGET_HAVE_TLS true
10500 #undef TARGET_CANNOT_FORCE_CONST_MEM
10501 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10503 #undef TARGET_DELEGITIMIZE_ADDRESS
10504 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10506 #undef TARGET_LEGITIMIZE_ADDRESS
10507 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10509 #undef TARGET_RETURN_IN_MEMORY
10510 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10512 #undef TARGET_INIT_BUILTINS
10513 #define TARGET_INIT_BUILTINS s390_init_builtins
10514 #undef TARGET_EXPAND_BUILTIN
10515 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10517 #undef TARGET_ASM_OUTPUT_MI_THUNK
10518 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10519 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10520 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10522 #undef TARGET_SCHED_ADJUST_PRIORITY
10523 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10524 #undef TARGET_SCHED_ISSUE_RATE
10525 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10526 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10527 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10529 #undef TARGET_SCHED_VARIABLE_ISSUE
10530 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10531 #undef TARGET_SCHED_REORDER
10532 #define TARGET_SCHED_REORDER s390_sched_reorder
10533 #undef TARGET_SCHED_INIT
10534 #define TARGET_SCHED_INIT s390_sched_init
10536 #undef TARGET_CANNOT_COPY_INSN_P
10537 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10538 #undef TARGET_RTX_COSTS
10539 #define TARGET_RTX_COSTS s390_rtx_costs
10540 #undef TARGET_ADDRESS_COST
10541 #define TARGET_ADDRESS_COST s390_address_cost
10543 #undef TARGET_MACHINE_DEPENDENT_REORG
10544 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10546 #undef TARGET_VALID_POINTER_MODE
10547 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10549 #undef TARGET_BUILD_BUILTIN_VA_LIST
10550 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10551 #undef TARGET_EXPAND_BUILTIN_VA_START
10552 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10553 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10554 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10556 #undef TARGET_PROMOTE_FUNCTION_MODE
10557 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10558 #undef TARGET_PASS_BY_REFERENCE
10559 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10561 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10562 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10563 #undef TARGET_FUNCTION_ARG
10564 #define TARGET_FUNCTION_ARG s390_function_arg
10565 #undef TARGET_FUNCTION_ARG_ADVANCE
10566 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10568 #undef TARGET_FIXED_CONDITION_CODE_REGS
10569 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10571 #undef TARGET_CC_MODES_COMPATIBLE
10572 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10574 #undef TARGET_INVALID_WITHIN_DOLOOP
10575 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10578 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10579 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10582 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10583 #undef TARGET_MANGLE_TYPE
10584 #define TARGET_MANGLE_TYPE s390_mangle_type
10587 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10588 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10590 #undef TARGET_SECONDARY_RELOAD
10591 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10593 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10594 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10596 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10597 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10599 #undef TARGET_LEGITIMATE_ADDRESS_P
10600 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10602 #undef TARGET_CAN_ELIMINATE
10603 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10605 #undef TARGET_LOOP_UNROLL_ADJUST
10606 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10608 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10609 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10610 #undef TARGET_TRAMPOLINE_INIT
10611 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10613 #undef TARGET_UNWIND_WORD_MODE
10614 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10616 struct gcc_target targetm
= TARGET_INITIALIZER
;
10618 #include "gt-s390.h"