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config.gcc: Enable zEC12 for with-arch and with-tune configure switches.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48 #include "debug.h"
49 #include "langhooks.h"
50 #include "optabs.h"
51 #include "gimple.h"
52 #include "df.h"
53 #include "params.h"
54 #include "cfgloop.h"
55 #include "opts.h"
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 static const
225 struct processor_costs z196_cost =
226 {
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
254 };
255
256 static const
257 struct processor_costs zEC12_cost =
258 {
259 COSTS_N_INSNS (7), /* M */
260 COSTS_N_INSNS (5), /* MGHI */
261 COSTS_N_INSNS (5), /* MH */
262 COSTS_N_INSNS (5), /* MHI */
263 COSTS_N_INSNS (7), /* ML */
264 COSTS_N_INSNS (7), /* MR */
265 COSTS_N_INSNS (6), /* MS */
266 COSTS_N_INSNS (8), /* MSG */
267 COSTS_N_INSNS (6), /* MSGF */
268 COSTS_N_INSNS (6), /* MSGFR */
269 COSTS_N_INSNS (8), /* MSGR */
270 COSTS_N_INSNS (6), /* MSR */
271 COSTS_N_INSNS (1) , /* multiplication in DFmode */
272 COSTS_N_INSNS (40), /* MXBR B+40 */
273 COSTS_N_INSNS (100), /* SQXBR B+100 */
274 COSTS_N_INSNS (42), /* SQDBR B+42 */
275 COSTS_N_INSNS (28), /* SQEBR B+28 */
276 COSTS_N_INSNS (1), /* MADBR B */
277 COSTS_N_INSNS (1), /* MAEBR B */
278 COSTS_N_INSNS (131), /* DXBR B+131 */
279 COSTS_N_INSNS (29), /* DDBR */
280 COSTS_N_INSNS (22), /* DEBR */
281 COSTS_N_INSNS (160), /* DLGR cracked */
282 COSTS_N_INSNS (160), /* DLR cracked */
283 COSTS_N_INSNS (160), /* DR expanded */
284 COSTS_N_INSNS (160), /* DSGFR cracked */
285 COSTS_N_INSNS (160), /* DSGR cracked */
286 };
287
288 extern int reload_completed;
289
290 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
291 static rtx last_scheduled_insn;
292
293 /* Structure used to hold the components of a S/390 memory
294 address. A legitimate address on S/390 is of the general
295 form
296 base + index + displacement
297 where any of the components is optional.
298
299 base and index are registers of the class ADDR_REGS,
300 displacement is an unsigned 12-bit immediate constant. */
301
302 struct s390_address
303 {
304 rtx base;
305 rtx indx;
306 rtx disp;
307 bool pointer;
308 bool literal_pool;
309 };
310
311 /* The following structure is embedded in the machine
312 specific part of struct function. */
313
314 struct GTY (()) s390_frame_layout
315 {
316 /* Offset within stack frame. */
317 HOST_WIDE_INT gprs_offset;
318 HOST_WIDE_INT f0_offset;
319 HOST_WIDE_INT f4_offset;
320 HOST_WIDE_INT f8_offset;
321 HOST_WIDE_INT backchain_offset;
322
323 /* Number of first and last gpr where slots in the register
324 save area are reserved for. */
325 int first_save_gpr_slot;
326 int last_save_gpr_slot;
327
328 /* Number of first and last gpr to be saved, restored. */
329 int first_save_gpr;
330 int first_restore_gpr;
331 int last_save_gpr;
332 int last_restore_gpr;
333
334 /* Bits standing for floating point registers. Set, if the
335 respective register has to be saved. Starting with reg 16 (f0)
336 at the rightmost bit.
337 Bit 15 - 8 7 6 5 4 3 2 1 0
338 fpr 15 - 8 7 5 3 1 6 4 2 0
339 reg 31 - 24 23 22 21 20 19 18 17 16 */
340 unsigned int fpr_bitmap;
341
342 /* Number of floating point registers f8-f15 which must be saved. */
343 int high_fprs;
344
345 /* Set if return address needs to be saved.
346 This flag is set by s390_return_addr_rtx if it could not use
347 the initial value of r14 and therefore depends on r14 saved
348 to the stack. */
349 bool save_return_addr_p;
350
351 /* Size of stack frame. */
352 HOST_WIDE_INT frame_size;
353 };
354
355 /* Define the structure for the machine field in struct function. */
356
357 struct GTY(()) machine_function
358 {
359 struct s390_frame_layout frame_layout;
360
361 /* Literal pool base register. */
362 rtx base_reg;
363
364 /* True if we may need to perform branch splitting. */
365 bool split_branches_pending_p;
366
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name;
369
370 bool has_landing_pad_p;
371 };
372
373 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
374
375 #define cfun_frame_layout (cfun->machine->frame_layout)
376 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
377 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
378 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
379 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
380 (1 << (BITNUM)))
381 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
382 (1 << (BITNUM))))
383
384 /* Number of GPRs and FPRs used for argument passing. */
385 #define GP_ARG_NUM_REG 5
386 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
387
388 /* A couple of shortcuts. */
389 #define CONST_OK_FOR_J(x) \
390 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
391 #define CONST_OK_FOR_K(x) \
392 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
393 #define CONST_OK_FOR_Os(x) \
394 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
395 #define CONST_OK_FOR_Op(x) \
396 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
397 #define CONST_OK_FOR_On(x) \
398 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
399
400 #define REGNO_PAIR_OK(REGNO, MODE) \
401 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
402
403 /* That's the read ahead of the dynamic branch prediction unit in
404 bytes on a z10 (or higher) CPU. */
405 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
406
407 /* Return the alignment for LABEL. We default to the -falign-labels
408 value except for the literal pool base label. */
409 int
410 s390_label_align (rtx label)
411 {
412 rtx prev_insn = prev_active_insn (label);
413
414 if (prev_insn == NULL_RTX)
415 goto old;
416
417 prev_insn = single_set (prev_insn);
418
419 if (prev_insn == NULL_RTX)
420 goto old;
421
422 prev_insn = SET_SRC (prev_insn);
423
424 /* Don't align literal pool base labels. */
425 if (GET_CODE (prev_insn) == UNSPEC
426 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
427 return 0;
428
429 old:
430 return align_labels_log;
431 }
432
433 static enum machine_mode
434 s390_libgcc_cmp_return_mode (void)
435 {
436 return TARGET_64BIT ? DImode : SImode;
437 }
438
439 static enum machine_mode
440 s390_libgcc_shift_count_mode (void)
441 {
442 return TARGET_64BIT ? DImode : SImode;
443 }
444
445 static enum machine_mode
446 s390_unwind_word_mode (void)
447 {
448 return TARGET_64BIT ? DImode : SImode;
449 }
450
451 /* Return true if the back end supports mode MODE. */
452 static bool
453 s390_scalar_mode_supported_p (enum machine_mode mode)
454 {
455 /* In contrast to the default implementation reject TImode constants on 31bit
456 TARGET_ZARCH for ABI compliance. */
457 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
458 return false;
459
460 if (DECIMAL_FLOAT_MODE_P (mode))
461 return default_decimal_float_supported_p ();
462
463 return default_scalar_mode_supported_p (mode);
464 }
465
466 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
467
468 void
469 s390_set_has_landing_pad_p (bool value)
470 {
471 cfun->machine->has_landing_pad_p = value;
472 }
473
474 /* If two condition code modes are compatible, return a condition code
475 mode which is compatible with both. Otherwise, return
476 VOIDmode. */
477
478 static enum machine_mode
479 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
480 {
481 if (m1 == m2)
482 return m1;
483
484 switch (m1)
485 {
486 case CCZmode:
487 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
488 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
489 return m2;
490 return VOIDmode;
491
492 case CCSmode:
493 case CCUmode:
494 case CCTmode:
495 case CCSRmode:
496 case CCURmode:
497 case CCZ1mode:
498 if (m2 == CCZmode)
499 return m1;
500
501 return VOIDmode;
502
503 default:
504 return VOIDmode;
505 }
506 return VOIDmode;
507 }
508
509 /* Return true if SET either doesn't set the CC register, or else
510 the source and destination have matching CC modes and that
511 CC mode is at least as constrained as REQ_MODE. */
512
513 static bool
514 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
515 {
516 enum machine_mode set_mode;
517
518 gcc_assert (GET_CODE (set) == SET);
519
520 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
521 return 1;
522
523 set_mode = GET_MODE (SET_DEST (set));
524 switch (set_mode)
525 {
526 case CCSmode:
527 case CCSRmode:
528 case CCUmode:
529 case CCURmode:
530 case CCLmode:
531 case CCL1mode:
532 case CCL2mode:
533 case CCL3mode:
534 case CCT1mode:
535 case CCT2mode:
536 case CCT3mode:
537 if (req_mode != set_mode)
538 return 0;
539 break;
540
541 case CCZmode:
542 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
543 && req_mode != CCSRmode && req_mode != CCURmode)
544 return 0;
545 break;
546
547 case CCAPmode:
548 case CCANmode:
549 if (req_mode != CCAmode)
550 return 0;
551 break;
552
553 default:
554 gcc_unreachable ();
555 }
556
557 return (GET_MODE (SET_SRC (set)) == set_mode);
558 }
559
560 /* Return true if every SET in INSN that sets the CC register
561 has source and destination with matching CC modes and that
562 CC mode is at least as constrained as REQ_MODE.
563 If REQ_MODE is VOIDmode, always return false. */
564
565 bool
566 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
567 {
568 int i;
569
570 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
571 if (req_mode == VOIDmode)
572 return false;
573
574 if (GET_CODE (PATTERN (insn)) == SET)
575 return s390_match_ccmode_set (PATTERN (insn), req_mode);
576
577 if (GET_CODE (PATTERN (insn)) == PARALLEL)
578 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
579 {
580 rtx set = XVECEXP (PATTERN (insn), 0, i);
581 if (GET_CODE (set) == SET)
582 if (!s390_match_ccmode_set (set, req_mode))
583 return false;
584 }
585
586 return true;
587 }
588
589 /* If a test-under-mask instruction can be used to implement
590 (compare (and ... OP1) OP2), return the CC mode required
591 to do that. Otherwise, return VOIDmode.
592 MIXED is true if the instruction can distinguish between
593 CC1 and CC2 for mixed selected bits (TMxx), it is false
594 if the instruction cannot (TM). */
595
596 enum machine_mode
597 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
598 {
599 int bit0, bit1;
600
601 /* ??? Fixme: should work on CONST_DOUBLE as well. */
602 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
603 return VOIDmode;
604
605 /* Selected bits all zero: CC0.
606 e.g.: int a; if ((a & (16 + 128)) == 0) */
607 if (INTVAL (op2) == 0)
608 return CCTmode;
609
610 /* Selected bits all one: CC3.
611 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
612 if (INTVAL (op2) == INTVAL (op1))
613 return CCT3mode;
614
615 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
616 int a;
617 if ((a & (16 + 128)) == 16) -> CCT1
618 if ((a & (16 + 128)) == 128) -> CCT2 */
619 if (mixed)
620 {
621 bit1 = exact_log2 (INTVAL (op2));
622 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
623 if (bit0 != -1 && bit1 != -1)
624 return bit0 > bit1 ? CCT1mode : CCT2mode;
625 }
626
627 return VOIDmode;
628 }
629
630 /* Given a comparison code OP (EQ, NE, etc.) and the operands
631 OP0 and OP1 of a COMPARE, return the mode to be used for the
632 comparison. */
633
634 enum machine_mode
635 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
636 {
637 switch (code)
638 {
639 case EQ:
640 case NE:
641 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
642 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
643 return CCAPmode;
644 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
645 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
646 return CCAPmode;
647 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
648 || GET_CODE (op1) == NEG)
649 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
650 return CCLmode;
651
652 if (GET_CODE (op0) == AND)
653 {
654 /* Check whether we can potentially do it via TM. */
655 enum machine_mode ccmode;
656 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
657 if (ccmode != VOIDmode)
658 {
659 /* Relax CCTmode to CCZmode to allow fall-back to AND
660 if that turns out to be beneficial. */
661 return ccmode == CCTmode ? CCZmode : ccmode;
662 }
663 }
664
665 if (register_operand (op0, HImode)
666 && GET_CODE (op1) == CONST_INT
667 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
668 return CCT3mode;
669 if (register_operand (op0, QImode)
670 && GET_CODE (op1) == CONST_INT
671 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
672 return CCT3mode;
673
674 return CCZmode;
675
676 case LE:
677 case LT:
678 case GE:
679 case GT:
680 /* The only overflow condition of NEG and ABS happens when
681 -INT_MAX is used as parameter, which stays negative. So
682 we have an overflow from a positive value to a negative.
683 Using CCAP mode the resulting cc can be used for comparisons. */
684 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
685 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
686 return CCAPmode;
687
688 /* If constants are involved in an add instruction it is possible to use
689 the resulting cc for comparisons with zero. Knowing the sign of the
690 constant the overflow behavior gets predictable. e.g.:
691 int a, b; if ((b = a + c) > 0)
692 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
693 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
694 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
695 {
696 if (INTVAL (XEXP((op0), 1)) < 0)
697 return CCANmode;
698 else
699 return CCAPmode;
700 }
701 /* Fall through. */
702 case UNORDERED:
703 case ORDERED:
704 case UNEQ:
705 case UNLE:
706 case UNLT:
707 case UNGE:
708 case UNGT:
709 case LTGT:
710 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
711 && GET_CODE (op1) != CONST_INT)
712 return CCSRmode;
713 return CCSmode;
714
715 case LTU:
716 case GEU:
717 if (GET_CODE (op0) == PLUS
718 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
719 return CCL1mode;
720
721 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
722 && GET_CODE (op1) != CONST_INT)
723 return CCURmode;
724 return CCUmode;
725
726 case LEU:
727 case GTU:
728 if (GET_CODE (op0) == MINUS
729 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
730 return CCL2mode;
731
732 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
733 && GET_CODE (op1) != CONST_INT)
734 return CCURmode;
735 return CCUmode;
736
737 default:
738 gcc_unreachable ();
739 }
740 }
741
742 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
743 that we can implement more efficiently. */
744
745 void
746 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
747 {
748 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
749 if ((*code == EQ || *code == NE)
750 && *op1 == const0_rtx
751 && GET_CODE (*op0) == ZERO_EXTRACT
752 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
753 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
754 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
755 {
756 rtx inner = XEXP (*op0, 0);
757 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
758 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
759 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
760
761 if (len > 0 && len < modesize
762 && pos >= 0 && pos + len <= modesize
763 && modesize <= HOST_BITS_PER_WIDE_INT)
764 {
765 unsigned HOST_WIDE_INT block;
766 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
767 block <<= modesize - pos - len;
768
769 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
770 gen_int_mode (block, GET_MODE (inner)));
771 }
772 }
773
774 /* Narrow AND of memory against immediate to enable TM. */
775 if ((*code == EQ || *code == NE)
776 && *op1 == const0_rtx
777 && GET_CODE (*op0) == AND
778 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
779 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
780 {
781 rtx inner = XEXP (*op0, 0);
782 rtx mask = XEXP (*op0, 1);
783
784 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
785 if (GET_CODE (inner) == SUBREG
786 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
787 && (GET_MODE_SIZE (GET_MODE (inner))
788 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
789 && ((INTVAL (mask)
790 & GET_MODE_MASK (GET_MODE (inner))
791 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
792 == 0))
793 inner = SUBREG_REG (inner);
794
795 /* Do not change volatile MEMs. */
796 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
797 {
798 int part = s390_single_part (XEXP (*op0, 1),
799 GET_MODE (inner), QImode, 0);
800 if (part >= 0)
801 {
802 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
803 inner = adjust_address_nv (inner, QImode, part);
804 *op0 = gen_rtx_AND (QImode, inner, mask);
805 }
806 }
807 }
808
809 /* Narrow comparisons against 0xffff to HImode if possible. */
810 if ((*code == EQ || *code == NE)
811 && GET_CODE (*op1) == CONST_INT
812 && INTVAL (*op1) == 0xffff
813 && SCALAR_INT_MODE_P (GET_MODE (*op0))
814 && (nonzero_bits (*op0, GET_MODE (*op0))
815 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
816 {
817 *op0 = gen_lowpart (HImode, *op0);
818 *op1 = constm1_rtx;
819 }
820
821 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
822 if (GET_CODE (*op0) == UNSPEC
823 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
824 && XVECLEN (*op0, 0) == 1
825 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
826 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
827 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
828 && *op1 == const0_rtx)
829 {
830 enum rtx_code new_code = UNKNOWN;
831 switch (*code)
832 {
833 case EQ: new_code = EQ; break;
834 case NE: new_code = NE; break;
835 case LT: new_code = GTU; break;
836 case GT: new_code = LTU; break;
837 case LE: new_code = GEU; break;
838 case GE: new_code = LEU; break;
839 default: break;
840 }
841
842 if (new_code != UNKNOWN)
843 {
844 *op0 = XVECEXP (*op0, 0, 0);
845 *code = new_code;
846 }
847 }
848
849 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
850 if (GET_CODE (*op0) == UNSPEC
851 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
852 && XVECLEN (*op0, 0) == 1
853 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
854 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
855 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
856 && *op1 == const0_rtx)
857 {
858 enum rtx_code new_code = UNKNOWN;
859 switch (*code)
860 {
861 case EQ: new_code = EQ; break;
862 case NE: new_code = NE; break;
863 default: break;
864 }
865
866 if (new_code != UNKNOWN)
867 {
868 *op0 = XVECEXP (*op0, 0, 0);
869 *code = new_code;
870 }
871 }
872
873 /* Simplify cascaded EQ, NE with const0_rtx. */
874 if ((*code == NE || *code == EQ)
875 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
876 && GET_MODE (*op0) == SImode
877 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
878 && REG_P (XEXP (*op0, 0))
879 && XEXP (*op0, 1) == const0_rtx
880 && *op1 == const0_rtx)
881 {
882 if ((*code == EQ && GET_CODE (*op0) == NE)
883 || (*code == NE && GET_CODE (*op0) == EQ))
884 *code = EQ;
885 else
886 *code = NE;
887 *op0 = XEXP (*op0, 0);
888 }
889
890 /* Prefer register over memory as first operand. */
891 if (MEM_P (*op0) && REG_P (*op1))
892 {
893 rtx tem = *op0; *op0 = *op1; *op1 = tem;
894 *code = swap_condition (*code);
895 }
896 }
897
898 /* Emit a compare instruction suitable to implement the comparison
899 OP0 CODE OP1. Return the correct condition RTL to be placed in
900 the IF_THEN_ELSE of the conditional branch testing the result. */
901
902 rtx
903 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
904 {
905 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
906 rtx cc;
907
908 /* Do not output a redundant compare instruction if a compare_and_swap
909 pattern already computed the result and the machine modes are compatible. */
910 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
911 {
912 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
913 == GET_MODE (op0));
914 cc = op0;
915 }
916 else
917 {
918 cc = gen_rtx_REG (mode, CC_REGNUM);
919 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
920 }
921
922 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
923 }
924
925 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
926 matches CMP.
927 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
928 conditional branch testing the result. */
929
930 static rtx
931 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
932 rtx cmp, rtx new_rtx)
933 {
934 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
935 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
936 const0_rtx);
937 }
938
939 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
940 unconditional jump, else a conditional jump under condition COND. */
941
942 void
943 s390_emit_jump (rtx target, rtx cond)
944 {
945 rtx insn;
946
947 target = gen_rtx_LABEL_REF (VOIDmode, target);
948 if (cond)
949 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
950
951 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
952 emit_jump_insn (insn);
953 }
954
955 /* Return branch condition mask to implement a branch
956 specified by CODE. Return -1 for invalid comparisons. */
957
958 int
959 s390_branch_condition_mask (rtx code)
960 {
961 const int CC0 = 1 << 3;
962 const int CC1 = 1 << 2;
963 const int CC2 = 1 << 1;
964 const int CC3 = 1 << 0;
965
966 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
967 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
968 gcc_assert (XEXP (code, 1) == const0_rtx);
969
970 switch (GET_MODE (XEXP (code, 0)))
971 {
972 case CCZmode:
973 case CCZ1mode:
974 switch (GET_CODE (code))
975 {
976 case EQ: return CC0;
977 case NE: return CC1 | CC2 | CC3;
978 default: return -1;
979 }
980 break;
981
982 case CCT1mode:
983 switch (GET_CODE (code))
984 {
985 case EQ: return CC1;
986 case NE: return CC0 | CC2 | CC3;
987 default: return -1;
988 }
989 break;
990
991 case CCT2mode:
992 switch (GET_CODE (code))
993 {
994 case EQ: return CC2;
995 case NE: return CC0 | CC1 | CC3;
996 default: return -1;
997 }
998 break;
999
1000 case CCT3mode:
1001 switch (GET_CODE (code))
1002 {
1003 case EQ: return CC3;
1004 case NE: return CC0 | CC1 | CC2;
1005 default: return -1;
1006 }
1007 break;
1008
1009 case CCLmode:
1010 switch (GET_CODE (code))
1011 {
1012 case EQ: return CC0 | CC2;
1013 case NE: return CC1 | CC3;
1014 default: return -1;
1015 }
1016 break;
1017
1018 case CCL1mode:
1019 switch (GET_CODE (code))
1020 {
1021 case LTU: return CC2 | CC3; /* carry */
1022 case GEU: return CC0 | CC1; /* no carry */
1023 default: return -1;
1024 }
1025 break;
1026
1027 case CCL2mode:
1028 switch (GET_CODE (code))
1029 {
1030 case GTU: return CC0 | CC1; /* borrow */
1031 case LEU: return CC2 | CC3; /* no borrow */
1032 default: return -1;
1033 }
1034 break;
1035
1036 case CCL3mode:
1037 switch (GET_CODE (code))
1038 {
1039 case EQ: return CC0 | CC2;
1040 case NE: return CC1 | CC3;
1041 case LTU: return CC1;
1042 case GTU: return CC3;
1043 case LEU: return CC1 | CC2;
1044 case GEU: return CC2 | CC3;
1045 default: return -1;
1046 }
1047
1048 case CCUmode:
1049 switch (GET_CODE (code))
1050 {
1051 case EQ: return CC0;
1052 case NE: return CC1 | CC2 | CC3;
1053 case LTU: return CC1;
1054 case GTU: return CC2;
1055 case LEU: return CC0 | CC1;
1056 case GEU: return CC0 | CC2;
1057 default: return -1;
1058 }
1059 break;
1060
1061 case CCURmode:
1062 switch (GET_CODE (code))
1063 {
1064 case EQ: return CC0;
1065 case NE: return CC2 | CC1 | CC3;
1066 case LTU: return CC2;
1067 case GTU: return CC1;
1068 case LEU: return CC0 | CC2;
1069 case GEU: return CC0 | CC1;
1070 default: return -1;
1071 }
1072 break;
1073
1074 case CCAPmode:
1075 switch (GET_CODE (code))
1076 {
1077 case EQ: return CC0;
1078 case NE: return CC1 | CC2 | CC3;
1079 case LT: return CC1 | CC3;
1080 case GT: return CC2;
1081 case LE: return CC0 | CC1 | CC3;
1082 case GE: return CC0 | CC2;
1083 default: return -1;
1084 }
1085 break;
1086
1087 case CCANmode:
1088 switch (GET_CODE (code))
1089 {
1090 case EQ: return CC0;
1091 case NE: return CC1 | CC2 | CC3;
1092 case LT: return CC1;
1093 case GT: return CC2 | CC3;
1094 case LE: return CC0 | CC1;
1095 case GE: return CC0 | CC2 | CC3;
1096 default: return -1;
1097 }
1098 break;
1099
1100 case CCSmode:
1101 switch (GET_CODE (code))
1102 {
1103 case EQ: return CC0;
1104 case NE: return CC1 | CC2 | CC3;
1105 case LT: return CC1;
1106 case GT: return CC2;
1107 case LE: return CC0 | CC1;
1108 case GE: return CC0 | CC2;
1109 case UNORDERED: return CC3;
1110 case ORDERED: return CC0 | CC1 | CC2;
1111 case UNEQ: return CC0 | CC3;
1112 case UNLT: return CC1 | CC3;
1113 case UNGT: return CC2 | CC3;
1114 case UNLE: return CC0 | CC1 | CC3;
1115 case UNGE: return CC0 | CC2 | CC3;
1116 case LTGT: return CC1 | CC2;
1117 default: return -1;
1118 }
1119 break;
1120
1121 case CCSRmode:
1122 switch (GET_CODE (code))
1123 {
1124 case EQ: return CC0;
1125 case NE: return CC2 | CC1 | CC3;
1126 case LT: return CC2;
1127 case GT: return CC1;
1128 case LE: return CC0 | CC2;
1129 case GE: return CC0 | CC1;
1130 case UNORDERED: return CC3;
1131 case ORDERED: return CC0 | CC2 | CC1;
1132 case UNEQ: return CC0 | CC3;
1133 case UNLT: return CC2 | CC3;
1134 case UNGT: return CC1 | CC3;
1135 case UNLE: return CC0 | CC2 | CC3;
1136 case UNGE: return CC0 | CC1 | CC3;
1137 case LTGT: return CC2 | CC1;
1138 default: return -1;
1139 }
1140 break;
1141
1142 default:
1143 return -1;
1144 }
1145 }
1146
1147
1148 /* Return branch condition mask to implement a compare and branch
1149 specified by CODE. Return -1 for invalid comparisons. */
1150
1151 int
1152 s390_compare_and_branch_condition_mask (rtx code)
1153 {
1154 const int CC0 = 1 << 3;
1155 const int CC1 = 1 << 2;
1156 const int CC2 = 1 << 1;
1157
1158 switch (GET_CODE (code))
1159 {
1160 case EQ:
1161 return CC0;
1162 case NE:
1163 return CC1 | CC2;
1164 case LT:
1165 case LTU:
1166 return CC1;
1167 case GT:
1168 case GTU:
1169 return CC2;
1170 case LE:
1171 case LEU:
1172 return CC0 | CC1;
1173 case GE:
1174 case GEU:
1175 return CC0 | CC2;
1176 default:
1177 gcc_unreachable ();
1178 }
1179 return -1;
1180 }
1181
1182 /* If INV is false, return assembler mnemonic string to implement
1183 a branch specified by CODE. If INV is true, return mnemonic
1184 for the corresponding inverted branch. */
1185
1186 static const char *
1187 s390_branch_condition_mnemonic (rtx code, int inv)
1188 {
1189 int mask;
1190
1191 static const char *const mnemonic[16] =
1192 {
1193 NULL, "o", "h", "nle",
1194 "l", "nhe", "lh", "ne",
1195 "e", "nlh", "he", "nl",
1196 "le", "nh", "no", NULL
1197 };
1198
1199 if (GET_CODE (XEXP (code, 0)) == REG
1200 && REGNO (XEXP (code, 0)) == CC_REGNUM
1201 && XEXP (code, 1) == const0_rtx)
1202 mask = s390_branch_condition_mask (code);
1203 else
1204 mask = s390_compare_and_branch_condition_mask (code);
1205
1206 gcc_assert (mask >= 0);
1207
1208 if (inv)
1209 mask ^= 15;
1210
1211 gcc_assert (mask >= 1 && mask <= 14);
1212
1213 return mnemonic[mask];
1214 }
1215
1216 /* Return the part of op which has a value different from def.
1217 The size of the part is determined by mode.
1218 Use this function only if you already know that op really
1219 contains such a part. */
1220
1221 unsigned HOST_WIDE_INT
1222 s390_extract_part (rtx op, enum machine_mode mode, int def)
1223 {
1224 unsigned HOST_WIDE_INT value = 0;
1225 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1226 int part_bits = GET_MODE_BITSIZE (mode);
1227 unsigned HOST_WIDE_INT part_mask
1228 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1229 int i;
1230
1231 for (i = 0; i < max_parts; i++)
1232 {
1233 if (i == 0)
1234 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1235 else
1236 value >>= part_bits;
1237
1238 if ((value & part_mask) != (def & part_mask))
1239 return value & part_mask;
1240 }
1241
1242 gcc_unreachable ();
1243 }
1244
1245 /* If OP is an integer constant of mode MODE with exactly one
1246 part of mode PART_MODE unequal to DEF, return the number of that
1247 part. Otherwise, return -1. */
1248
1249 int
1250 s390_single_part (rtx op,
1251 enum machine_mode mode,
1252 enum machine_mode part_mode,
1253 int def)
1254 {
1255 unsigned HOST_WIDE_INT value = 0;
1256 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1257 unsigned HOST_WIDE_INT part_mask
1258 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1259 int i, part = -1;
1260
1261 if (GET_CODE (op) != CONST_INT)
1262 return -1;
1263
1264 for (i = 0; i < n_parts; i++)
1265 {
1266 if (i == 0)
1267 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1268 else
1269 value >>= GET_MODE_BITSIZE (part_mode);
1270
1271 if ((value & part_mask) != (def & part_mask))
1272 {
1273 if (part != -1)
1274 return -1;
1275 else
1276 part = i;
1277 }
1278 }
1279 return part == -1 ? -1 : n_parts - 1 - part;
1280 }
1281
1282 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1283 bits and no other bits are set in IN. POS and LENGTH can be used
1284 to obtain the start position and the length of the bitfield.
1285
1286 POS gives the position of the first bit of the bitfield counting
1287 from the lowest order bit starting with zero. In order to use this
1288 value for S/390 instructions this has to be converted to "bits big
1289 endian" style. */
1290
1291 bool
1292 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1293 int *pos, int *length)
1294 {
1295 int tmp_pos = 0;
1296 int tmp_length = 0;
1297 int i;
1298 unsigned HOST_WIDE_INT mask = 1ULL;
1299 bool contiguous = false;
1300
1301 for (i = 0; i < size; mask <<= 1, i++)
1302 {
1303 if (contiguous)
1304 {
1305 if (mask & in)
1306 tmp_length++;
1307 else
1308 break;
1309 }
1310 else
1311 {
1312 if (mask & in)
1313 {
1314 contiguous = true;
1315 tmp_length++;
1316 }
1317 else
1318 tmp_pos++;
1319 }
1320 }
1321
1322 if (!tmp_length)
1323 return false;
1324
1325 /* Calculate a mask for all bits beyond the contiguous bits. */
1326 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1327
1328 if (mask & in)
1329 return false;
1330
1331 if (tmp_length + tmp_pos - 1 > size)
1332 return false;
1333
1334 if (length)
1335 *length = tmp_length;
1336
1337 if (pos)
1338 *pos = tmp_pos;
1339
1340 return true;
1341 }
1342
1343 /* Check whether we can (and want to) split a double-word
1344 move in mode MODE from SRC to DST into two single-word
1345 moves, moving the subword FIRST_SUBWORD first. */
1346
1347 bool
1348 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1349 {
1350 /* Floating point registers cannot be split. */
1351 if (FP_REG_P (src) || FP_REG_P (dst))
1352 return false;
1353
1354 /* We don't need to split if operands are directly accessible. */
1355 if (s_operand (src, mode) || s_operand (dst, mode))
1356 return false;
1357
1358 /* Non-offsettable memory references cannot be split. */
1359 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1360 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1361 return false;
1362
1363 /* Moving the first subword must not clobber a register
1364 needed to move the second subword. */
1365 if (register_operand (dst, mode))
1366 {
1367 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1368 if (reg_overlap_mentioned_p (subreg, src))
1369 return false;
1370 }
1371
1372 return true;
1373 }
1374
1375 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1376 and [MEM2, MEM2 + SIZE] do overlap and false
1377 otherwise. */
1378
1379 bool
1380 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1381 {
1382 rtx addr1, addr2, addr_delta;
1383 HOST_WIDE_INT delta;
1384
1385 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1386 return true;
1387
1388 if (size == 0)
1389 return false;
1390
1391 addr1 = XEXP (mem1, 0);
1392 addr2 = XEXP (mem2, 0);
1393
1394 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1395
1396 /* This overlapping check is used by peepholes merging memory block operations.
1397 Overlapping operations would otherwise be recognized by the S/390 hardware
1398 and would fall back to a slower implementation. Allowing overlapping
1399 operations would lead to slow code but not to wrong code. Therefore we are
1400 somewhat optimistic if we cannot prove that the memory blocks are
1401 overlapping.
1402 That's why we return false here although this may accept operations on
1403 overlapping memory areas. */
1404 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1405 return false;
1406
1407 delta = INTVAL (addr_delta);
1408
1409 if (delta == 0
1410 || (delta > 0 && delta < size)
1411 || (delta < 0 && -delta < size))
1412 return true;
1413
1414 return false;
1415 }
1416
1417 /* Check whether the address of memory reference MEM2 equals exactly
1418 the address of memory reference MEM1 plus DELTA. Return true if
1419 we can prove this to be the case, false otherwise. */
1420
1421 bool
1422 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1423 {
1424 rtx addr1, addr2, addr_delta;
1425
1426 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1427 return false;
1428
1429 addr1 = XEXP (mem1, 0);
1430 addr2 = XEXP (mem2, 0);
1431
1432 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1433 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1434 return false;
1435
1436 return true;
1437 }
1438
1439 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1440
1441 void
1442 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1443 rtx *operands)
1444 {
1445 enum machine_mode wmode = mode;
1446 rtx dst = operands[0];
1447 rtx src1 = operands[1];
1448 rtx src2 = operands[2];
1449 rtx op, clob, tem;
1450
1451 /* If we cannot handle the operation directly, use a temp register. */
1452 if (!s390_logical_operator_ok_p (operands))
1453 dst = gen_reg_rtx (mode);
1454
1455 /* QImode and HImode patterns make sense only if we have a destination
1456 in memory. Otherwise perform the operation in SImode. */
1457 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1458 wmode = SImode;
1459
1460 /* Widen operands if required. */
1461 if (mode != wmode)
1462 {
1463 if (GET_CODE (dst) == SUBREG
1464 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1465 dst = tem;
1466 else if (REG_P (dst))
1467 dst = gen_rtx_SUBREG (wmode, dst, 0);
1468 else
1469 dst = gen_reg_rtx (wmode);
1470
1471 if (GET_CODE (src1) == SUBREG
1472 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1473 src1 = tem;
1474 else if (GET_MODE (src1) != VOIDmode)
1475 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1476
1477 if (GET_CODE (src2) == SUBREG
1478 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1479 src2 = tem;
1480 else if (GET_MODE (src2) != VOIDmode)
1481 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1482 }
1483
1484 /* Emit the instruction. */
1485 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1486 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1487 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1488
1489 /* Fix up the destination if needed. */
1490 if (dst != operands[0])
1491 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1492 }
1493
1494 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1495
1496 bool
1497 s390_logical_operator_ok_p (rtx *operands)
1498 {
1499 /* If the destination operand is in memory, it needs to coincide
1500 with one of the source operands. After reload, it has to be
1501 the first source operand. */
1502 if (GET_CODE (operands[0]) == MEM)
1503 return rtx_equal_p (operands[0], operands[1])
1504 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1505
1506 return true;
1507 }
1508
1509 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1510 operand IMMOP to switch from SS to SI type instructions. */
1511
1512 void
1513 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1514 {
1515 int def = code == AND ? -1 : 0;
1516 HOST_WIDE_INT mask;
1517 int part;
1518
1519 gcc_assert (GET_CODE (*memop) == MEM);
1520 gcc_assert (!MEM_VOLATILE_P (*memop));
1521
1522 mask = s390_extract_part (*immop, QImode, def);
1523 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1524 gcc_assert (part >= 0);
1525
1526 *memop = adjust_address (*memop, QImode, part);
1527 *immop = gen_int_mode (mask, QImode);
1528 }
1529
1530
1531 /* How to allocate a 'struct machine_function'. */
1532
1533 static struct machine_function *
1534 s390_init_machine_status (void)
1535 {
1536 return ggc_alloc_cleared_machine_function ();
1537 }
1538
1539 static void
1540 s390_option_override (void)
1541 {
1542 /* Set up function hooks. */
1543 init_machine_status = s390_init_machine_status;
1544
1545 /* Architecture mode defaults according to ABI. */
1546 if (!(target_flags_explicit & MASK_ZARCH))
1547 {
1548 if (TARGET_64BIT)
1549 target_flags |= MASK_ZARCH;
1550 else
1551 target_flags &= ~MASK_ZARCH;
1552 }
1553
1554 /* Set the march default in case it hasn't been specified on
1555 cmdline. */
1556 if (s390_arch == PROCESSOR_max)
1557 {
1558 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1559 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1560 s390_arch_flags = processor_flags_table[(int)s390_arch];
1561 }
1562
1563 /* Determine processor to tune for. */
1564 if (s390_tune == PROCESSOR_max)
1565 {
1566 s390_tune = s390_arch;
1567 s390_tune_flags = s390_arch_flags;
1568 }
1569
1570 /* Sanity checks. */
1571 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1572 error ("z/Architecture mode not supported on %s", s390_arch_string);
1573 if (TARGET_64BIT && !TARGET_ZARCH)
1574 error ("64-bit ABI not supported in ESA/390 mode");
1575
1576 /* Use hardware DFP if available and not explicitly disabled by
1577 user. E.g. with -m31 -march=z10 -mzarch */
1578 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1579 target_flags |= MASK_HARD_DFP;
1580
1581 if (TARGET_HARD_DFP && !TARGET_DFP)
1582 {
1583 if (target_flags_explicit & MASK_HARD_DFP)
1584 {
1585 if (!TARGET_CPU_DFP)
1586 error ("hardware decimal floating point instructions"
1587 " not available on %s", s390_arch_string);
1588 if (!TARGET_ZARCH)
1589 error ("hardware decimal floating point instructions"
1590 " not available in ESA/390 mode");
1591 }
1592 else
1593 target_flags &= ~MASK_HARD_DFP;
1594 }
1595
1596 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1597 {
1598 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1599 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1600
1601 target_flags &= ~MASK_HARD_DFP;
1602 }
1603
1604 /* Set processor cost function. */
1605 switch (s390_tune)
1606 {
1607 case PROCESSOR_2084_Z990:
1608 s390_cost = &z990_cost;
1609 break;
1610 case PROCESSOR_2094_Z9_109:
1611 s390_cost = &z9_109_cost;
1612 break;
1613 case PROCESSOR_2097_Z10:
1614 s390_cost = &z10_cost;
1615 break;
1616 case PROCESSOR_2817_Z196:
1617 s390_cost = &z196_cost;
1618 break;
1619 case PROCESSOR_2827_ZEC12:
1620 s390_cost = &zEC12_cost;
1621 break;
1622 default:
1623 s390_cost = &z900_cost;
1624 }
1625
1626 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1627 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1628 "in combination");
1629
1630 if (s390_stack_size)
1631 {
1632 if (s390_stack_guard >= s390_stack_size)
1633 error ("stack size must be greater than the stack guard value");
1634 else if (s390_stack_size > 1 << 16)
1635 error ("stack size must not be greater than 64k");
1636 }
1637 else if (s390_stack_guard)
1638 error ("-mstack-guard implies use of -mstack-size");
1639
1640 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1641 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1642 target_flags |= MASK_LONG_DOUBLE_128;
1643 #endif
1644
1645 if (s390_tune == PROCESSOR_2097_Z10
1646 || s390_tune == PROCESSOR_2817_Z196
1647 || s390_tune == PROCESSOR_2827_ZEC12)
1648 {
1649 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1650 global_options.x_param_values,
1651 global_options_set.x_param_values);
1652 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1653 global_options.x_param_values,
1654 global_options_set.x_param_values);
1655 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1656 global_options.x_param_values,
1657 global_options_set.x_param_values);
1658 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1659 global_options.x_param_values,
1660 global_options_set.x_param_values);
1661 }
1662
1663 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1664 global_options.x_param_values,
1665 global_options_set.x_param_values);
1666 /* values for loop prefetching */
1667 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1668 global_options.x_param_values,
1669 global_options_set.x_param_values);
1670 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1671 global_options.x_param_values,
1672 global_options_set.x_param_values);
1673 /* s390 has more than 2 levels and the size is much larger. Since
1674 we are always running virtualized assume that we only get a small
1675 part of the caches above l1. */
1676 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1677 global_options.x_param_values,
1678 global_options_set.x_param_values);
1679 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1680 global_options.x_param_values,
1681 global_options_set.x_param_values);
1682 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1683 global_options.x_param_values,
1684 global_options_set.x_param_values);
1685
1686 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1687 requires the arch flags to be evaluated already. Since prefetching
1688 is beneficial on s390, we enable it if available. */
1689 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1690 flag_prefetch_loop_arrays = 1;
1691
1692 /* Use the alternative scheduling-pressure algorithm by default. */
1693 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
1694 global_options.x_param_values,
1695 global_options_set.x_param_values);
1696
1697 if (TARGET_TPF)
1698 {
1699 /* Don't emit DWARF3/4 unless specifically selected. The TPF
1700 debuggers do not yet support DWARF 3/4. */
1701 if (!global_options_set.x_dwarf_strict)
1702 dwarf_strict = 1;
1703 if (!global_options_set.x_dwarf_version)
1704 dwarf_version = 2;
1705 }
1706 }
1707
1708 /* Map for smallest class containing reg regno. */
1709
1710 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1711 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1712 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1713 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1714 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1715 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1716 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1717 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1718 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1719 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1720 ACCESS_REGS, ACCESS_REGS
1721 };
1722
1723 /* Return attribute type of insn. */
1724
1725 static enum attr_type
1726 s390_safe_attr_type (rtx insn)
1727 {
1728 if (recog_memoized (insn) >= 0)
1729 return get_attr_type (insn);
1730 else
1731 return TYPE_NONE;
1732 }
1733
1734 /* Return true if DISP is a valid short displacement. */
1735
1736 static bool
1737 s390_short_displacement (rtx disp)
1738 {
1739 /* No displacement is OK. */
1740 if (!disp)
1741 return true;
1742
1743 /* Without the long displacement facility we don't need to
1744 distingiush between long and short displacement. */
1745 if (!TARGET_LONG_DISPLACEMENT)
1746 return true;
1747
1748 /* Integer displacement in range. */
1749 if (GET_CODE (disp) == CONST_INT)
1750 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1751
1752 /* GOT offset is not OK, the GOT can be large. */
1753 if (GET_CODE (disp) == CONST
1754 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1755 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1756 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1757 return false;
1758
1759 /* All other symbolic constants are literal pool references,
1760 which are OK as the literal pool must be small. */
1761 if (GET_CODE (disp) == CONST)
1762 return true;
1763
1764 return false;
1765 }
1766
1767 /* Decompose a RTL expression ADDR for a memory address into
1768 its components, returned in OUT.
1769
1770 Returns false if ADDR is not a valid memory address, true
1771 otherwise. If OUT is NULL, don't return the components,
1772 but check for validity only.
1773
1774 Note: Only addresses in canonical form are recognized.
1775 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1776 canonical form so that they will be recognized. */
1777
1778 static int
1779 s390_decompose_address (rtx addr, struct s390_address *out)
1780 {
1781 HOST_WIDE_INT offset = 0;
1782 rtx base = NULL_RTX;
1783 rtx indx = NULL_RTX;
1784 rtx disp = NULL_RTX;
1785 rtx orig_disp;
1786 bool pointer = false;
1787 bool base_ptr = false;
1788 bool indx_ptr = false;
1789 bool literal_pool = false;
1790
1791 /* We may need to substitute the literal pool base register into the address
1792 below. However, at this point we do not know which register is going to
1793 be used as base, so we substitute the arg pointer register. This is going
1794 to be treated as holding a pointer below -- it shouldn't be used for any
1795 other purpose. */
1796 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1797
1798 /* Decompose address into base + index + displacement. */
1799
1800 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1801 base = addr;
1802
1803 else if (GET_CODE (addr) == PLUS)
1804 {
1805 rtx op0 = XEXP (addr, 0);
1806 rtx op1 = XEXP (addr, 1);
1807 enum rtx_code code0 = GET_CODE (op0);
1808 enum rtx_code code1 = GET_CODE (op1);
1809
1810 if (code0 == REG || code0 == UNSPEC)
1811 {
1812 if (code1 == REG || code1 == UNSPEC)
1813 {
1814 indx = op0; /* index + base */
1815 base = op1;
1816 }
1817
1818 else
1819 {
1820 base = op0; /* base + displacement */
1821 disp = op1;
1822 }
1823 }
1824
1825 else if (code0 == PLUS)
1826 {
1827 indx = XEXP (op0, 0); /* index + base + disp */
1828 base = XEXP (op0, 1);
1829 disp = op1;
1830 }
1831
1832 else
1833 {
1834 return false;
1835 }
1836 }
1837
1838 else
1839 disp = addr; /* displacement */
1840
1841 /* Extract integer part of displacement. */
1842 orig_disp = disp;
1843 if (disp)
1844 {
1845 if (GET_CODE (disp) == CONST_INT)
1846 {
1847 offset = INTVAL (disp);
1848 disp = NULL_RTX;
1849 }
1850 else if (GET_CODE (disp) == CONST
1851 && GET_CODE (XEXP (disp, 0)) == PLUS
1852 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1853 {
1854 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1855 disp = XEXP (XEXP (disp, 0), 0);
1856 }
1857 }
1858
1859 /* Strip off CONST here to avoid special case tests later. */
1860 if (disp && GET_CODE (disp) == CONST)
1861 disp = XEXP (disp, 0);
1862
1863 /* We can convert literal pool addresses to
1864 displacements by basing them off the base register. */
1865 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1866 {
1867 /* Either base or index must be free to hold the base register. */
1868 if (!base)
1869 base = fake_pool_base, literal_pool = true;
1870 else if (!indx)
1871 indx = fake_pool_base, literal_pool = true;
1872 else
1873 return false;
1874
1875 /* Mark up the displacement. */
1876 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1877 UNSPEC_LTREL_OFFSET);
1878 }
1879
1880 /* Validate base register. */
1881 if (base)
1882 {
1883 if (GET_CODE (base) == UNSPEC)
1884 switch (XINT (base, 1))
1885 {
1886 case UNSPEC_LTREF:
1887 if (!disp)
1888 disp = gen_rtx_UNSPEC (Pmode,
1889 gen_rtvec (1, XVECEXP (base, 0, 0)),
1890 UNSPEC_LTREL_OFFSET);
1891 else
1892 return false;
1893
1894 base = XVECEXP (base, 0, 1);
1895 break;
1896
1897 case UNSPEC_LTREL_BASE:
1898 if (XVECLEN (base, 0) == 1)
1899 base = fake_pool_base, literal_pool = true;
1900 else
1901 base = XVECEXP (base, 0, 1);
1902 break;
1903
1904 default:
1905 return false;
1906 }
1907
1908 if (!REG_P (base)
1909 || (GET_MODE (base) != SImode
1910 && GET_MODE (base) != Pmode))
1911 return false;
1912
1913 if (REGNO (base) == STACK_POINTER_REGNUM
1914 || REGNO (base) == FRAME_POINTER_REGNUM
1915 || ((reload_completed || reload_in_progress)
1916 && frame_pointer_needed
1917 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1918 || REGNO (base) == ARG_POINTER_REGNUM
1919 || (flag_pic
1920 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1921 pointer = base_ptr = true;
1922
1923 if ((reload_completed || reload_in_progress)
1924 && base == cfun->machine->base_reg)
1925 pointer = base_ptr = literal_pool = true;
1926 }
1927
1928 /* Validate index register. */
1929 if (indx)
1930 {
1931 if (GET_CODE (indx) == UNSPEC)
1932 switch (XINT (indx, 1))
1933 {
1934 case UNSPEC_LTREF:
1935 if (!disp)
1936 disp = gen_rtx_UNSPEC (Pmode,
1937 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1938 UNSPEC_LTREL_OFFSET);
1939 else
1940 return false;
1941
1942 indx = XVECEXP (indx, 0, 1);
1943 break;
1944
1945 case UNSPEC_LTREL_BASE:
1946 if (XVECLEN (indx, 0) == 1)
1947 indx = fake_pool_base, literal_pool = true;
1948 else
1949 indx = XVECEXP (indx, 0, 1);
1950 break;
1951
1952 default:
1953 return false;
1954 }
1955
1956 if (!REG_P (indx)
1957 || (GET_MODE (indx) != SImode
1958 && GET_MODE (indx) != Pmode))
1959 return false;
1960
1961 if (REGNO (indx) == STACK_POINTER_REGNUM
1962 || REGNO (indx) == FRAME_POINTER_REGNUM
1963 || ((reload_completed || reload_in_progress)
1964 && frame_pointer_needed
1965 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1966 || REGNO (indx) == ARG_POINTER_REGNUM
1967 || (flag_pic
1968 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1969 pointer = indx_ptr = true;
1970
1971 if ((reload_completed || reload_in_progress)
1972 && indx == cfun->machine->base_reg)
1973 pointer = indx_ptr = literal_pool = true;
1974 }
1975
1976 /* Prefer to use pointer as base, not index. */
1977 if (base && indx && !base_ptr
1978 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1979 {
1980 rtx tmp = base;
1981 base = indx;
1982 indx = tmp;
1983 }
1984
1985 /* Validate displacement. */
1986 if (!disp)
1987 {
1988 /* If virtual registers are involved, the displacement will change later
1989 anyway as the virtual registers get eliminated. This could make a
1990 valid displacement invalid, but it is more likely to make an invalid
1991 displacement valid, because we sometimes access the register save area
1992 via negative offsets to one of those registers.
1993 Thus we don't check the displacement for validity here. If after
1994 elimination the displacement turns out to be invalid after all,
1995 this is fixed up by reload in any case. */
1996 if (base != arg_pointer_rtx
1997 && indx != arg_pointer_rtx
1998 && base != return_address_pointer_rtx
1999 && indx != return_address_pointer_rtx
2000 && base != frame_pointer_rtx
2001 && indx != frame_pointer_rtx
2002 && base != virtual_stack_vars_rtx
2003 && indx != virtual_stack_vars_rtx)
2004 if (!DISP_IN_RANGE (offset))
2005 return false;
2006 }
2007 else
2008 {
2009 /* All the special cases are pointers. */
2010 pointer = true;
2011
2012 /* In the small-PIC case, the linker converts @GOT
2013 and @GOTNTPOFF offsets to possible displacements. */
2014 if (GET_CODE (disp) == UNSPEC
2015 && (XINT (disp, 1) == UNSPEC_GOT
2016 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2017 && flag_pic == 1)
2018 {
2019 ;
2020 }
2021
2022 /* Accept pool label offsets. */
2023 else if (GET_CODE (disp) == UNSPEC
2024 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2025 ;
2026
2027 /* Accept literal pool references. */
2028 else if (GET_CODE (disp) == UNSPEC
2029 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2030 {
2031 /* In case CSE pulled a non literal pool reference out of
2032 the pool we have to reject the address. This is
2033 especially important when loading the GOT pointer on non
2034 zarch CPUs. In this case the literal pool contains an lt
2035 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2036 will most likely exceed the displacement. */
2037 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2038 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2039 return false;
2040
2041 orig_disp = gen_rtx_CONST (Pmode, disp);
2042 if (offset)
2043 {
2044 /* If we have an offset, make sure it does not
2045 exceed the size of the constant pool entry. */
2046 rtx sym = XVECEXP (disp, 0, 0);
2047 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2048 return false;
2049
2050 orig_disp = plus_constant (Pmode, orig_disp, offset);
2051 }
2052 }
2053
2054 else
2055 return false;
2056 }
2057
2058 if (!base && !indx)
2059 pointer = true;
2060
2061 if (out)
2062 {
2063 out->base = base;
2064 out->indx = indx;
2065 out->disp = orig_disp;
2066 out->pointer = pointer;
2067 out->literal_pool = literal_pool;
2068 }
2069
2070 return true;
2071 }
2072
2073 /* Decompose a RTL expression OP for a shift count into its components,
2074 and return the base register in BASE and the offset in OFFSET.
2075
2076 Return true if OP is a valid shift count, false if not. */
2077
2078 bool
2079 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2080 {
2081 HOST_WIDE_INT off = 0;
2082
2083 /* We can have an integer constant, an address register,
2084 or a sum of the two. */
2085 if (GET_CODE (op) == CONST_INT)
2086 {
2087 off = INTVAL (op);
2088 op = NULL_RTX;
2089 }
2090 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2091 {
2092 off = INTVAL (XEXP (op, 1));
2093 op = XEXP (op, 0);
2094 }
2095 while (op && GET_CODE (op) == SUBREG)
2096 op = SUBREG_REG (op);
2097
2098 if (op && GET_CODE (op) != REG)
2099 return false;
2100
2101 if (offset)
2102 *offset = off;
2103 if (base)
2104 *base = op;
2105
2106 return true;
2107 }
2108
2109
2110 /* Return true if CODE is a valid address without index. */
2111
2112 bool
2113 s390_legitimate_address_without_index_p (rtx op)
2114 {
2115 struct s390_address addr;
2116
2117 if (!s390_decompose_address (XEXP (op, 0), &addr))
2118 return false;
2119 if (addr.indx)
2120 return false;
2121
2122 return true;
2123 }
2124
2125
2126 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2127 and return these parts in SYMREF and ADDEND. You can pass NULL in
2128 SYMREF and/or ADDEND if you are not interested in these values.
2129 Literal pool references are *not* considered symbol references. */
2130
2131 static bool
2132 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2133 {
2134 HOST_WIDE_INT tmpaddend = 0;
2135
2136 if (GET_CODE (addr) == CONST)
2137 addr = XEXP (addr, 0);
2138
2139 if (GET_CODE (addr) == PLUS)
2140 {
2141 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2142 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2143 && CONST_INT_P (XEXP (addr, 1)))
2144 {
2145 tmpaddend = INTVAL (XEXP (addr, 1));
2146 addr = XEXP (addr, 0);
2147 }
2148 else
2149 return false;
2150 }
2151 else
2152 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2153 return false;
2154
2155 if (symref)
2156 *symref = addr;
2157 if (addend)
2158 *addend = tmpaddend;
2159
2160 return true;
2161 }
2162
2163 /* Return TRUE if ADDR is an operand valid for a load/store relative
2164 instructions. Be aware that the alignment of the operand needs to
2165 be checked separately. */
2166 static bool
2167 s390_loadrelative_operand_p (rtx addr)
2168 {
2169 if (GET_CODE (addr) == CONST)
2170 addr = XEXP (addr, 0);
2171
2172 /* Enable load relative for symbol@GOTENT. */
2173 if (GET_CODE (addr) == UNSPEC
2174 && XINT (addr, 1) == UNSPEC_GOTENT)
2175 return true;
2176
2177 return s390_symref_operand_p (addr, NULL, NULL);
2178 }
2179
2180 /* Return true if the address in OP is valid for constraint letter C
2181 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2182 pool MEMs should be accepted. Only the Q, R, S, T constraint
2183 letters are allowed for C. */
2184
2185 static int
2186 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2187 {
2188 struct s390_address addr;
2189 bool decomposed = false;
2190
2191 /* This check makes sure that no symbolic address (except literal
2192 pool references) are accepted by the R or T constraints. */
2193 if (s390_loadrelative_operand_p (op))
2194 return 0;
2195
2196 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2197 if (!lit_pool_ok)
2198 {
2199 if (!s390_decompose_address (op, &addr))
2200 return 0;
2201 if (addr.literal_pool)
2202 return 0;
2203 decomposed = true;
2204 }
2205
2206 switch (c)
2207 {
2208 case 'Q': /* no index short displacement */
2209 if (!decomposed && !s390_decompose_address (op, &addr))
2210 return 0;
2211 if (addr.indx)
2212 return 0;
2213 if (!s390_short_displacement (addr.disp))
2214 return 0;
2215 break;
2216
2217 case 'R': /* with index short displacement */
2218 if (TARGET_LONG_DISPLACEMENT)
2219 {
2220 if (!decomposed && !s390_decompose_address (op, &addr))
2221 return 0;
2222 if (!s390_short_displacement (addr.disp))
2223 return 0;
2224 }
2225 /* Any invalid address here will be fixed up by reload,
2226 so accept it for the most generic constraint. */
2227 break;
2228
2229 case 'S': /* no index long displacement */
2230 if (!TARGET_LONG_DISPLACEMENT)
2231 return 0;
2232 if (!decomposed && !s390_decompose_address (op, &addr))
2233 return 0;
2234 if (addr.indx)
2235 return 0;
2236 if (s390_short_displacement (addr.disp))
2237 return 0;
2238 break;
2239
2240 case 'T': /* with index long displacement */
2241 if (!TARGET_LONG_DISPLACEMENT)
2242 return 0;
2243 /* Any invalid address here will be fixed up by reload,
2244 so accept it for the most generic constraint. */
2245 if ((decomposed || s390_decompose_address (op, &addr))
2246 && s390_short_displacement (addr.disp))
2247 return 0;
2248 break;
2249 default:
2250 return 0;
2251 }
2252 return 1;
2253 }
2254
2255
2256 /* Evaluates constraint strings described by the regular expression
2257 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2258 the constraint given in STR, or 0 else. */
2259
2260 int
2261 s390_mem_constraint (const char *str, rtx op)
2262 {
2263 char c = str[0];
2264
2265 switch (c)
2266 {
2267 case 'A':
2268 /* Check for offsettable variants of memory constraints. */
2269 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2270 return 0;
2271 if ((reload_completed || reload_in_progress)
2272 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2273 return 0;
2274 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2275 case 'B':
2276 /* Check for non-literal-pool variants of memory constraints. */
2277 if (!MEM_P (op))
2278 return 0;
2279 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2280 case 'Q':
2281 case 'R':
2282 case 'S':
2283 case 'T':
2284 if (GET_CODE (op) != MEM)
2285 return 0;
2286 return s390_check_qrst_address (c, XEXP (op, 0), true);
2287 case 'U':
2288 return (s390_check_qrst_address ('Q', op, true)
2289 || s390_check_qrst_address ('R', op, true));
2290 case 'W':
2291 return (s390_check_qrst_address ('S', op, true)
2292 || s390_check_qrst_address ('T', op, true));
2293 case 'Y':
2294 /* Simply check for the basic form of a shift count. Reload will
2295 take care of making sure we have a proper base register. */
2296 if (!s390_decompose_shift_count (op, NULL, NULL))
2297 return 0;
2298 break;
2299 case 'Z':
2300 return s390_check_qrst_address (str[1], op, true);
2301 default:
2302 return 0;
2303 }
2304 return 1;
2305 }
2306
2307
2308 /* Evaluates constraint strings starting with letter O. Input
2309 parameter C is the second letter following the "O" in the constraint
2310 string. Returns 1 if VALUE meets the respective constraint and 0
2311 otherwise. */
2312
2313 int
2314 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2315 {
2316 if (!TARGET_EXTIMM)
2317 return 0;
2318
2319 switch (c)
2320 {
2321 case 's':
2322 return trunc_int_for_mode (value, SImode) == value;
2323
2324 case 'p':
2325 return value == 0
2326 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2327
2328 case 'n':
2329 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2330
2331 default:
2332 gcc_unreachable ();
2333 }
2334 }
2335
2336
2337 /* Evaluates constraint strings starting with letter N. Parameter STR
2338 contains the letters following letter "N" in the constraint string.
2339 Returns true if VALUE matches the constraint. */
2340
2341 int
2342 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2343 {
2344 enum machine_mode mode, part_mode;
2345 int def;
2346 int part, part_goal;
2347
2348
2349 if (str[0] == 'x')
2350 part_goal = -1;
2351 else
2352 part_goal = str[0] - '0';
2353
2354 switch (str[1])
2355 {
2356 case 'Q':
2357 part_mode = QImode;
2358 break;
2359 case 'H':
2360 part_mode = HImode;
2361 break;
2362 case 'S':
2363 part_mode = SImode;
2364 break;
2365 default:
2366 return 0;
2367 }
2368
2369 switch (str[2])
2370 {
2371 case 'H':
2372 mode = HImode;
2373 break;
2374 case 'S':
2375 mode = SImode;
2376 break;
2377 case 'D':
2378 mode = DImode;
2379 break;
2380 default:
2381 return 0;
2382 }
2383
2384 switch (str[3])
2385 {
2386 case '0':
2387 def = 0;
2388 break;
2389 case 'F':
2390 def = -1;
2391 break;
2392 default:
2393 return 0;
2394 }
2395
2396 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2397 return 0;
2398
2399 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2400 if (part < 0)
2401 return 0;
2402 if (part_goal != -1 && part_goal != part)
2403 return 0;
2404
2405 return 1;
2406 }
2407
2408
2409 /* Returns true if the input parameter VALUE is a float zero. */
2410
2411 int
2412 s390_float_const_zero_p (rtx value)
2413 {
2414 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2415 && value == CONST0_RTX (GET_MODE (value)));
2416 }
2417
2418 /* Implement TARGET_REGISTER_MOVE_COST. */
2419
2420 static int
2421 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2422 reg_class_t from, reg_class_t to)
2423 {
2424 /* On s390, copy between fprs and gprs is expensive. */
2425 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2426 && reg_classes_intersect_p (to, FP_REGS))
2427 || (reg_classes_intersect_p (from, FP_REGS)
2428 && reg_classes_intersect_p (to, GENERAL_REGS)))
2429 return 10;
2430
2431 return 1;
2432 }
2433
2434 /* Implement TARGET_MEMORY_MOVE_COST. */
2435
2436 static int
2437 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2438 reg_class_t rclass ATTRIBUTE_UNUSED,
2439 bool in ATTRIBUTE_UNUSED)
2440 {
2441 return 1;
2442 }
2443
2444 /* Compute a (partial) cost for rtx X. Return true if the complete
2445 cost has been computed, and false if subexpressions should be
2446 scanned. In either case, *TOTAL contains the cost result.
2447 CODE contains GET_CODE (x), OUTER_CODE contains the code
2448 of the superexpression of x. */
2449
2450 static bool
2451 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2452 int *total, bool speed ATTRIBUTE_UNUSED)
2453 {
2454 switch (code)
2455 {
2456 case CONST:
2457 case CONST_INT:
2458 case LABEL_REF:
2459 case SYMBOL_REF:
2460 case CONST_DOUBLE:
2461 case MEM:
2462 *total = 0;
2463 return true;
2464
2465 case ASHIFT:
2466 case ASHIFTRT:
2467 case LSHIFTRT:
2468 case ROTATE:
2469 case ROTATERT:
2470 case AND:
2471 case IOR:
2472 case XOR:
2473 case NEG:
2474 case NOT:
2475 *total = COSTS_N_INSNS (1);
2476 return false;
2477
2478 case PLUS:
2479 case MINUS:
2480 *total = COSTS_N_INSNS (1);
2481 return false;
2482
2483 case MULT:
2484 switch (GET_MODE (x))
2485 {
2486 case SImode:
2487 {
2488 rtx left = XEXP (x, 0);
2489 rtx right = XEXP (x, 1);
2490 if (GET_CODE (right) == CONST_INT
2491 && CONST_OK_FOR_K (INTVAL (right)))
2492 *total = s390_cost->mhi;
2493 else if (GET_CODE (left) == SIGN_EXTEND)
2494 *total = s390_cost->mh;
2495 else
2496 *total = s390_cost->ms; /* msr, ms, msy */
2497 break;
2498 }
2499 case DImode:
2500 {
2501 rtx left = XEXP (x, 0);
2502 rtx right = XEXP (x, 1);
2503 if (TARGET_ZARCH)
2504 {
2505 if (GET_CODE (right) == CONST_INT
2506 && CONST_OK_FOR_K (INTVAL (right)))
2507 *total = s390_cost->mghi;
2508 else if (GET_CODE (left) == SIGN_EXTEND)
2509 *total = s390_cost->msgf;
2510 else
2511 *total = s390_cost->msg; /* msgr, msg */
2512 }
2513 else /* TARGET_31BIT */
2514 {
2515 if (GET_CODE (left) == SIGN_EXTEND
2516 && GET_CODE (right) == SIGN_EXTEND)
2517 /* mulsidi case: mr, m */
2518 *total = s390_cost->m;
2519 else if (GET_CODE (left) == ZERO_EXTEND
2520 && GET_CODE (right) == ZERO_EXTEND
2521 && TARGET_CPU_ZARCH)
2522 /* umulsidi case: ml, mlr */
2523 *total = s390_cost->ml;
2524 else
2525 /* Complex calculation is required. */
2526 *total = COSTS_N_INSNS (40);
2527 }
2528 break;
2529 }
2530 case SFmode:
2531 case DFmode:
2532 *total = s390_cost->mult_df;
2533 break;
2534 case TFmode:
2535 *total = s390_cost->mxbr;
2536 break;
2537 default:
2538 return false;
2539 }
2540 return false;
2541
2542 case FMA:
2543 switch (GET_MODE (x))
2544 {
2545 case DFmode:
2546 *total = s390_cost->madbr;
2547 break;
2548 case SFmode:
2549 *total = s390_cost->maebr;
2550 break;
2551 default:
2552 return false;
2553 }
2554 /* Negate in the third argument is free: FMSUB. */
2555 if (GET_CODE (XEXP (x, 2)) == NEG)
2556 {
2557 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2558 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2559 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2560 return true;
2561 }
2562 return false;
2563
2564 case UDIV:
2565 case UMOD:
2566 if (GET_MODE (x) == TImode) /* 128 bit division */
2567 *total = s390_cost->dlgr;
2568 else if (GET_MODE (x) == DImode)
2569 {
2570 rtx right = XEXP (x, 1);
2571 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2572 *total = s390_cost->dlr;
2573 else /* 64 by 64 bit division */
2574 *total = s390_cost->dlgr;
2575 }
2576 else if (GET_MODE (x) == SImode) /* 32 bit division */
2577 *total = s390_cost->dlr;
2578 return false;
2579
2580 case DIV:
2581 case MOD:
2582 if (GET_MODE (x) == DImode)
2583 {
2584 rtx right = XEXP (x, 1);
2585 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2586 if (TARGET_ZARCH)
2587 *total = s390_cost->dsgfr;
2588 else
2589 *total = s390_cost->dr;
2590 else /* 64 by 64 bit division */
2591 *total = s390_cost->dsgr;
2592 }
2593 else if (GET_MODE (x) == SImode) /* 32 bit division */
2594 *total = s390_cost->dlr;
2595 else if (GET_MODE (x) == SFmode)
2596 {
2597 *total = s390_cost->debr;
2598 }
2599 else if (GET_MODE (x) == DFmode)
2600 {
2601 *total = s390_cost->ddbr;
2602 }
2603 else if (GET_MODE (x) == TFmode)
2604 {
2605 *total = s390_cost->dxbr;
2606 }
2607 return false;
2608
2609 case SQRT:
2610 if (GET_MODE (x) == SFmode)
2611 *total = s390_cost->sqebr;
2612 else if (GET_MODE (x) == DFmode)
2613 *total = s390_cost->sqdbr;
2614 else /* TFmode */
2615 *total = s390_cost->sqxbr;
2616 return false;
2617
2618 case SIGN_EXTEND:
2619 case ZERO_EXTEND:
2620 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2621 || outer_code == PLUS || outer_code == MINUS
2622 || outer_code == COMPARE)
2623 *total = 0;
2624 return false;
2625
2626 case COMPARE:
2627 *total = COSTS_N_INSNS (1);
2628 if (GET_CODE (XEXP (x, 0)) == AND
2629 && GET_CODE (XEXP (x, 1)) == CONST_INT
2630 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2631 {
2632 rtx op0 = XEXP (XEXP (x, 0), 0);
2633 rtx op1 = XEXP (XEXP (x, 0), 1);
2634 rtx op2 = XEXP (x, 1);
2635
2636 if (memory_operand (op0, GET_MODE (op0))
2637 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2638 return true;
2639 if (register_operand (op0, GET_MODE (op0))
2640 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2641 return true;
2642 }
2643 return false;
2644
2645 default:
2646 return false;
2647 }
2648 }
2649
2650 /* Return the cost of an address rtx ADDR. */
2651
2652 static int
2653 s390_address_cost (rtx addr, enum machine_mode mode ATTRIBUTE_UNUSED,
2654 addr_space_t as ATTRIBUTE_UNUSED,
2655 bool speed ATTRIBUTE_UNUSED)
2656 {
2657 struct s390_address ad;
2658 if (!s390_decompose_address (addr, &ad))
2659 return 1000;
2660
2661 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2662 }
2663
2664 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2665 otherwise return 0. */
2666
2667 int
2668 tls_symbolic_operand (rtx op)
2669 {
2670 if (GET_CODE (op) != SYMBOL_REF)
2671 return 0;
2672 return SYMBOL_REF_TLS_MODEL (op);
2673 }
2674 \f
2675 /* Split DImode access register reference REG (on 64-bit) into its constituent
2676 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2677 gen_highpart cannot be used as they assume all registers are word-sized,
2678 while our access registers have only half that size. */
2679
2680 void
2681 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2682 {
2683 gcc_assert (TARGET_64BIT);
2684 gcc_assert (ACCESS_REG_P (reg));
2685 gcc_assert (GET_MODE (reg) == DImode);
2686 gcc_assert (!(REGNO (reg) & 1));
2687
2688 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2689 *hi = gen_rtx_REG (SImode, REGNO (reg));
2690 }
2691
2692 /* Return true if OP contains a symbol reference */
2693
2694 bool
2695 symbolic_reference_mentioned_p (rtx op)
2696 {
2697 const char *fmt;
2698 int i;
2699
2700 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2701 return 1;
2702
2703 fmt = GET_RTX_FORMAT (GET_CODE (op));
2704 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2705 {
2706 if (fmt[i] == 'E')
2707 {
2708 int j;
2709
2710 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2711 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2712 return 1;
2713 }
2714
2715 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2716 return 1;
2717 }
2718
2719 return 0;
2720 }
2721
2722 /* Return true if OP contains a reference to a thread-local symbol. */
2723
2724 bool
2725 tls_symbolic_reference_mentioned_p (rtx op)
2726 {
2727 const char *fmt;
2728 int i;
2729
2730 if (GET_CODE (op) == SYMBOL_REF)
2731 return tls_symbolic_operand (op);
2732
2733 fmt = GET_RTX_FORMAT (GET_CODE (op));
2734 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2735 {
2736 if (fmt[i] == 'E')
2737 {
2738 int j;
2739
2740 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2741 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2742 return true;
2743 }
2744
2745 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2746 return true;
2747 }
2748
2749 return false;
2750 }
2751
2752
2753 /* Return true if OP is a legitimate general operand when
2754 generating PIC code. It is given that flag_pic is on
2755 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2756
2757 int
2758 legitimate_pic_operand_p (rtx op)
2759 {
2760 /* Accept all non-symbolic constants. */
2761 if (!SYMBOLIC_CONST (op))
2762 return 1;
2763
2764 /* Reject everything else; must be handled
2765 via emit_symbolic_move. */
2766 return 0;
2767 }
2768
2769 /* Returns true if the constant value OP is a legitimate general operand.
2770 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2771
2772 static bool
2773 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2774 {
2775 /* Accept all non-symbolic constants. */
2776 if (!SYMBOLIC_CONST (op))
2777 return 1;
2778
2779 /* Accept immediate LARL operands. */
2780 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2781 return 1;
2782
2783 /* Thread-local symbols are never legal constants. This is
2784 so that emit_call knows that computing such addresses
2785 might require a function call. */
2786 if (TLS_SYMBOLIC_CONST (op))
2787 return 0;
2788
2789 /* In the PIC case, symbolic constants must *not* be
2790 forced into the literal pool. We accept them here,
2791 so that they will be handled by emit_symbolic_move. */
2792 if (flag_pic)
2793 return 1;
2794
2795 /* All remaining non-PIC symbolic constants are
2796 forced into the literal pool. */
2797 return 0;
2798 }
2799
2800 /* Determine if it's legal to put X into the constant pool. This
2801 is not possible if X contains the address of a symbol that is
2802 not constant (TLS) or not known at final link time (PIC). */
2803
2804 static bool
2805 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2806 {
2807 switch (GET_CODE (x))
2808 {
2809 case CONST_INT:
2810 case CONST_DOUBLE:
2811 /* Accept all non-symbolic constants. */
2812 return false;
2813
2814 case LABEL_REF:
2815 /* Labels are OK iff we are non-PIC. */
2816 return flag_pic != 0;
2817
2818 case SYMBOL_REF:
2819 /* 'Naked' TLS symbol references are never OK,
2820 non-TLS symbols are OK iff we are non-PIC. */
2821 if (tls_symbolic_operand (x))
2822 return true;
2823 else
2824 return flag_pic != 0;
2825
2826 case CONST:
2827 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2828 case PLUS:
2829 case MINUS:
2830 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2831 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2832
2833 case UNSPEC:
2834 switch (XINT (x, 1))
2835 {
2836 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2837 case UNSPEC_LTREL_OFFSET:
2838 case UNSPEC_GOT:
2839 case UNSPEC_GOTOFF:
2840 case UNSPEC_PLTOFF:
2841 case UNSPEC_TLSGD:
2842 case UNSPEC_TLSLDM:
2843 case UNSPEC_NTPOFF:
2844 case UNSPEC_DTPOFF:
2845 case UNSPEC_GOTNTPOFF:
2846 case UNSPEC_INDNTPOFF:
2847 return false;
2848
2849 /* If the literal pool shares the code section, be put
2850 execute template placeholders into the pool as well. */
2851 case UNSPEC_INSN:
2852 return TARGET_CPU_ZARCH;
2853
2854 default:
2855 return true;
2856 }
2857 break;
2858
2859 default:
2860 gcc_unreachable ();
2861 }
2862 }
2863
2864 /* Returns true if the constant value OP is a legitimate general
2865 operand during and after reload. The difference to
2866 legitimate_constant_p is that this function will not accept
2867 a constant that would need to be forced to the literal pool
2868 before it can be used as operand.
2869 This function accepts all constants which can be loaded directly
2870 into a GPR. */
2871
2872 bool
2873 legitimate_reload_constant_p (rtx op)
2874 {
2875 /* Accept la(y) operands. */
2876 if (GET_CODE (op) == CONST_INT
2877 && DISP_IN_RANGE (INTVAL (op)))
2878 return true;
2879
2880 /* Accept l(g)hi/l(g)fi operands. */
2881 if (GET_CODE (op) == CONST_INT
2882 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2883 return true;
2884
2885 /* Accept lliXX operands. */
2886 if (TARGET_ZARCH
2887 && GET_CODE (op) == CONST_INT
2888 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2889 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2890 return true;
2891
2892 if (TARGET_EXTIMM
2893 && GET_CODE (op) == CONST_INT
2894 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2895 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2896 return true;
2897
2898 /* Accept larl operands. */
2899 if (TARGET_CPU_ZARCH
2900 && larl_operand (op, VOIDmode))
2901 return true;
2902
2903 /* Accept floating-point zero operands that fit into a single GPR. */
2904 if (GET_CODE (op) == CONST_DOUBLE
2905 && s390_float_const_zero_p (op)
2906 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2907 return true;
2908
2909 /* Accept double-word operands that can be split. */
2910 if (GET_CODE (op) == CONST_INT
2911 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2912 {
2913 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2914 rtx hi = operand_subword (op, 0, 0, dword_mode);
2915 rtx lo = operand_subword (op, 1, 0, dword_mode);
2916 return legitimate_reload_constant_p (hi)
2917 && legitimate_reload_constant_p (lo);
2918 }
2919
2920 /* Everything else cannot be handled without reload. */
2921 return false;
2922 }
2923
2924 /* Returns true if the constant value OP is a legitimate fp operand
2925 during and after reload.
2926 This function accepts all constants which can be loaded directly
2927 into an FPR. */
2928
2929 static bool
2930 legitimate_reload_fp_constant_p (rtx op)
2931 {
2932 /* Accept floating-point zero operands if the load zero instruction
2933 can be used. Prior to z196 the load fp zero instruction caused a
2934 performance penalty if the result is used as BFP number. */
2935 if (TARGET_Z196
2936 && GET_CODE (op) == CONST_DOUBLE
2937 && s390_float_const_zero_p (op))
2938 return true;
2939
2940 return false;
2941 }
2942
2943 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2944 return the class of reg to actually use. */
2945
2946 static reg_class_t
2947 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2948 {
2949 switch (GET_CODE (op))
2950 {
2951 /* Constants we cannot reload into general registers
2952 must be forced into the literal pool. */
2953 case CONST_DOUBLE:
2954 case CONST_INT:
2955 if (reg_class_subset_p (GENERAL_REGS, rclass)
2956 && legitimate_reload_constant_p (op))
2957 return GENERAL_REGS;
2958 else if (reg_class_subset_p (ADDR_REGS, rclass)
2959 && legitimate_reload_constant_p (op))
2960 return ADDR_REGS;
2961 else if (reg_class_subset_p (FP_REGS, rclass)
2962 && legitimate_reload_fp_constant_p (op))
2963 return FP_REGS;
2964 return NO_REGS;
2965
2966 /* If a symbolic constant or a PLUS is reloaded,
2967 it is most likely being used as an address, so
2968 prefer ADDR_REGS. If 'class' is not a superset
2969 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2970 case LABEL_REF:
2971 case SYMBOL_REF:
2972 case CONST:
2973 if (!legitimate_reload_constant_p (op))
2974 return NO_REGS;
2975 /* fallthrough */
2976 case PLUS:
2977 /* load address will be used. */
2978 if (reg_class_subset_p (ADDR_REGS, rclass))
2979 return ADDR_REGS;
2980 else
2981 return NO_REGS;
2982
2983 default:
2984 break;
2985 }
2986
2987 return rclass;
2988 }
2989
2990 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2991 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2992 aligned. */
2993
2994 bool
2995 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2996 {
2997 HOST_WIDE_INT addend;
2998 rtx symref;
2999
3000 /* Accept symbol@GOTENT with pointer size alignment. */
3001 if (GET_CODE (addr) == CONST
3002 && GET_CODE (XEXP (addr, 0)) == UNSPEC
3003 && XINT (XEXP (addr, 0), 1) == UNSPEC_GOTENT
3004 && alignment <= UNITS_PER_LONG)
3005 return true;
3006
3007 if (!s390_symref_operand_p (addr, &symref, &addend))
3008 return false;
3009
3010 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
3011 && !(addend & (alignment - 1)));
3012 }
3013
3014 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3015 operand SCRATCH is used to reload the even part of the address and
3016 adding one. */
3017
3018 void
3019 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3020 {
3021 HOST_WIDE_INT addend;
3022 rtx symref;
3023
3024 if (!s390_symref_operand_p (addr, &symref, &addend))
3025 gcc_unreachable ();
3026
3027 if (!(addend & 1))
3028 /* Easy case. The addend is even so larl will do fine. */
3029 emit_move_insn (reg, addr);
3030 else
3031 {
3032 /* We can leave the scratch register untouched if the target
3033 register is a valid base register. */
3034 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3035 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3036 scratch = reg;
3037
3038 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3039 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3040
3041 if (addend != 1)
3042 emit_move_insn (scratch,
3043 gen_rtx_CONST (Pmode,
3044 gen_rtx_PLUS (Pmode, symref,
3045 GEN_INT (addend - 1))));
3046 else
3047 emit_move_insn (scratch, symref);
3048
3049 /* Increment the address using la in order to avoid clobbering cc. */
3050 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3051 }
3052 }
3053
3054 /* Generate what is necessary to move between REG and MEM using
3055 SCRATCH. The direction is given by TOMEM. */
3056
3057 void
3058 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3059 {
3060 /* Reload might have pulled a constant out of the literal pool.
3061 Force it back in. */
3062 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3063 || GET_CODE (mem) == CONST)
3064 mem = force_const_mem (GET_MODE (reg), mem);
3065
3066 gcc_assert (MEM_P (mem));
3067
3068 /* For a load from memory we can leave the scratch register
3069 untouched if the target register is a valid base register. */
3070 if (!tomem
3071 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3072 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3073 && GET_MODE (reg) == GET_MODE (scratch))
3074 scratch = reg;
3075
3076 /* Load address into scratch register. Since we can't have a
3077 secondary reload for a secondary reload we have to cover the case
3078 where larl would need a secondary reload here as well. */
3079 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3080
3081 /* Now we can use a standard load/store to do the move. */
3082 if (tomem)
3083 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3084 else
3085 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3086 }
3087
3088 /* Inform reload about cases where moving X with a mode MODE to a register in
3089 RCLASS requires an extra scratch or immediate register. Return the class
3090 needed for the immediate register. */
3091
3092 static reg_class_t
3093 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3094 enum machine_mode mode, secondary_reload_info *sri)
3095 {
3096 enum reg_class rclass = (enum reg_class) rclass_i;
3097
3098 /* Intermediate register needed. */
3099 if (reg_classes_intersect_p (CC_REGS, rclass))
3100 return GENERAL_REGS;
3101
3102 if (TARGET_Z10)
3103 {
3104 HOST_WIDE_INT offset;
3105 rtx symref;
3106
3107 /* On z10 several optimizer steps may generate larl operands with
3108 an odd addend. */
3109 if (in_p
3110 && s390_symref_operand_p (x, &symref, &offset)
3111 && mode == Pmode
3112 && !SYMBOL_REF_ALIGN1_P (symref)
3113 && (offset & 1) == 1)
3114 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3115 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3116
3117 /* On z10 we need a scratch register when moving QI, TI or floating
3118 point mode values from or to a memory location with a SYMBOL_REF
3119 or if the symref addend of a SI or DI move is not aligned to the
3120 width of the access. */
3121 if (MEM_P (x)
3122 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3123 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3124 || (!TARGET_ZARCH && mode == DImode)
3125 || ((mode == HImode || mode == SImode || mode == DImode)
3126 && (!s390_check_symref_alignment (XEXP (x, 0),
3127 GET_MODE_SIZE (mode))))))
3128 {
3129 #define __SECONDARY_RELOAD_CASE(M,m) \
3130 case M##mode: \
3131 if (TARGET_64BIT) \
3132 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3133 CODE_FOR_reload##m##di_tomem_z10; \
3134 else \
3135 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3136 CODE_FOR_reload##m##si_tomem_z10; \
3137 break;
3138
3139 switch (GET_MODE (x))
3140 {
3141 __SECONDARY_RELOAD_CASE (QI, qi);
3142 __SECONDARY_RELOAD_CASE (HI, hi);
3143 __SECONDARY_RELOAD_CASE (SI, si);
3144 __SECONDARY_RELOAD_CASE (DI, di);
3145 __SECONDARY_RELOAD_CASE (TI, ti);
3146 __SECONDARY_RELOAD_CASE (SF, sf);
3147 __SECONDARY_RELOAD_CASE (DF, df);
3148 __SECONDARY_RELOAD_CASE (TF, tf);
3149 __SECONDARY_RELOAD_CASE (SD, sd);
3150 __SECONDARY_RELOAD_CASE (DD, dd);
3151 __SECONDARY_RELOAD_CASE (TD, td);
3152
3153 default:
3154 gcc_unreachable ();
3155 }
3156 #undef __SECONDARY_RELOAD_CASE
3157 }
3158 }
3159
3160 /* We need a scratch register when loading a PLUS expression which
3161 is not a legitimate operand of the LOAD ADDRESS instruction. */
3162 if (in_p && s390_plus_operand (x, mode))
3163 sri->icode = (TARGET_64BIT ?
3164 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3165
3166 /* Performing a multiword move from or to memory we have to make sure the
3167 second chunk in memory is addressable without causing a displacement
3168 overflow. If that would be the case we calculate the address in
3169 a scratch register. */
3170 if (MEM_P (x)
3171 && GET_CODE (XEXP (x, 0)) == PLUS
3172 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3173 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3174 + GET_MODE_SIZE (mode) - 1))
3175 {
3176 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3177 in a s_operand address since we may fallback to lm/stm. So we only
3178 have to care about overflows in the b+i+d case. */
3179 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3180 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3181 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3182 /* For FP_REGS no lm/stm is available so this check is triggered
3183 for displacement overflows in b+i+d and b+d like addresses. */
3184 || (reg_classes_intersect_p (FP_REGS, rclass)
3185 && s390_class_max_nregs (FP_REGS, mode) > 1))
3186 {
3187 if (in_p)
3188 sri->icode = (TARGET_64BIT ?
3189 CODE_FOR_reloaddi_nonoffmem_in :
3190 CODE_FOR_reloadsi_nonoffmem_in);
3191 else
3192 sri->icode = (TARGET_64BIT ?
3193 CODE_FOR_reloaddi_nonoffmem_out :
3194 CODE_FOR_reloadsi_nonoffmem_out);
3195 }
3196 }
3197
3198 /* A scratch address register is needed when a symbolic constant is
3199 copied to r0 compiling with -fPIC. In other cases the target
3200 register might be used as temporary (see legitimize_pic_address). */
3201 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3202 sri->icode = (TARGET_64BIT ?
3203 CODE_FOR_reloaddi_PIC_addr :
3204 CODE_FOR_reloadsi_PIC_addr);
3205
3206 /* Either scratch or no register needed. */
3207 return NO_REGS;
3208 }
3209
3210 /* Generate code to load SRC, which is PLUS that is not a
3211 legitimate operand for the LA instruction, into TARGET.
3212 SCRATCH may be used as scratch register. */
3213
3214 void
3215 s390_expand_plus_operand (rtx target, rtx src,
3216 rtx scratch)
3217 {
3218 rtx sum1, sum2;
3219 struct s390_address ad;
3220
3221 /* src must be a PLUS; get its two operands. */
3222 gcc_assert (GET_CODE (src) == PLUS);
3223 gcc_assert (GET_MODE (src) == Pmode);
3224
3225 /* Check if any of the two operands is already scheduled
3226 for replacement by reload. This can happen e.g. when
3227 float registers occur in an address. */
3228 sum1 = find_replacement (&XEXP (src, 0));
3229 sum2 = find_replacement (&XEXP (src, 1));
3230 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3231
3232 /* If the address is already strictly valid, there's nothing to do. */
3233 if (!s390_decompose_address (src, &ad)
3234 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3235 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3236 {
3237 /* Otherwise, one of the operands cannot be an address register;
3238 we reload its value into the scratch register. */
3239 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3240 {
3241 emit_move_insn (scratch, sum1);
3242 sum1 = scratch;
3243 }
3244 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3245 {
3246 emit_move_insn (scratch, sum2);
3247 sum2 = scratch;
3248 }
3249
3250 /* According to the way these invalid addresses are generated
3251 in reload.c, it should never happen (at least on s390) that
3252 *neither* of the PLUS components, after find_replacements
3253 was applied, is an address register. */
3254 if (sum1 == scratch && sum2 == scratch)
3255 {
3256 debug_rtx (src);
3257 gcc_unreachable ();
3258 }
3259
3260 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3261 }
3262
3263 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3264 is only ever performed on addresses, so we can mark the
3265 sum as legitimate for LA in any case. */
3266 s390_load_address (target, src);
3267 }
3268
3269
3270 /* Return true if ADDR is a valid memory address.
3271 STRICT specifies whether strict register checking applies. */
3272
3273 static bool
3274 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3275 {
3276 struct s390_address ad;
3277
3278 if (TARGET_Z10
3279 && larl_operand (addr, VOIDmode)
3280 && (mode == VOIDmode
3281 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3282 return true;
3283
3284 if (!s390_decompose_address (addr, &ad))
3285 return false;
3286
3287 if (strict)
3288 {
3289 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3290 return false;
3291
3292 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3293 return false;
3294 }
3295 else
3296 {
3297 if (ad.base
3298 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3299 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3300 return false;
3301
3302 if (ad.indx
3303 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3304 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3305 return false;
3306 }
3307 return true;
3308 }
3309
3310 /* Return true if OP is a valid operand for the LA instruction.
3311 In 31-bit, we need to prove that the result is used as an
3312 address, as LA performs only a 31-bit addition. */
3313
3314 bool
3315 legitimate_la_operand_p (rtx op)
3316 {
3317 struct s390_address addr;
3318 if (!s390_decompose_address (op, &addr))
3319 return false;
3320
3321 return (TARGET_64BIT || addr.pointer);
3322 }
3323
3324 /* Return true if it is valid *and* preferable to use LA to
3325 compute the sum of OP1 and OP2. */
3326
3327 bool
3328 preferred_la_operand_p (rtx op1, rtx op2)
3329 {
3330 struct s390_address addr;
3331
3332 if (op2 != const0_rtx)
3333 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3334
3335 if (!s390_decompose_address (op1, &addr))
3336 return false;
3337 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3338 return false;
3339 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3340 return false;
3341
3342 /* Avoid LA instructions with index register on z196; it is
3343 preferable to use regular add instructions when possible.
3344 Starting with zEC12 the la with index register is "uncracked"
3345 again. */
3346 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3347 return false;
3348
3349 if (!TARGET_64BIT && !addr.pointer)
3350 return false;
3351
3352 if (addr.pointer)
3353 return true;
3354
3355 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3356 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3357 return true;
3358
3359 return false;
3360 }
3361
3362 /* Emit a forced load-address operation to load SRC into DST.
3363 This will use the LOAD ADDRESS instruction even in situations
3364 where legitimate_la_operand_p (SRC) returns false. */
3365
3366 void
3367 s390_load_address (rtx dst, rtx src)
3368 {
3369 if (TARGET_64BIT)
3370 emit_move_insn (dst, src);
3371 else
3372 emit_insn (gen_force_la_31 (dst, src));
3373 }
3374
3375 /* Return a legitimate reference for ORIG (an address) using the
3376 register REG. If REG is 0, a new pseudo is generated.
3377
3378 There are two types of references that must be handled:
3379
3380 1. Global data references must load the address from the GOT, via
3381 the PIC reg. An insn is emitted to do this load, and the reg is
3382 returned.
3383
3384 2. Static data references, constant pool addresses, and code labels
3385 compute the address as an offset from the GOT, whose base is in
3386 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3387 differentiate them from global data objects. The returned
3388 address is the PIC reg + an unspec constant.
3389
3390 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3391 reg also appears in the address. */
3392
3393 rtx
3394 legitimize_pic_address (rtx orig, rtx reg)
3395 {
3396 rtx addr = orig;
3397 rtx new_rtx = orig;
3398 rtx base;
3399
3400 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3401
3402 if (GET_CODE (addr) == LABEL_REF
3403 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3404 {
3405 /* This is a local symbol. */
3406 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3407 {
3408 /* Access local symbols PC-relative via LARL.
3409 This is the same as in the non-PIC case, so it is
3410 handled automatically ... */
3411 }
3412 else
3413 {
3414 /* Access local symbols relative to the GOT. */
3415
3416 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3417
3418 if (reload_in_progress || reload_completed)
3419 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3420
3421 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3422 addr = gen_rtx_CONST (Pmode, addr);
3423 addr = force_const_mem (Pmode, addr);
3424 emit_move_insn (temp, addr);
3425
3426 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3427 if (reg != 0)
3428 {
3429 s390_load_address (reg, new_rtx);
3430 new_rtx = reg;
3431 }
3432 }
3433 }
3434 else if (GET_CODE (addr) == SYMBOL_REF)
3435 {
3436 if (reg == 0)
3437 reg = gen_reg_rtx (Pmode);
3438
3439 if (flag_pic == 1)
3440 {
3441 /* Assume GOT offset < 4k. This is handled the same way
3442 in both 31- and 64-bit code (@GOT). */
3443
3444 if (reload_in_progress || reload_completed)
3445 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3446
3447 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3448 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3449 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3450 new_rtx = gen_const_mem (Pmode, new_rtx);
3451 emit_move_insn (reg, new_rtx);
3452 new_rtx = reg;
3453 }
3454 else if (TARGET_CPU_ZARCH)
3455 {
3456 /* If the GOT offset might be >= 4k, we determine the position
3457 of the GOT entry via a PC-relative LARL (@GOTENT). */
3458
3459 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3460
3461 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3462 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3463
3464 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3465 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3466
3467 if (!TARGET_Z10)
3468 {
3469 emit_move_insn (temp, new_rtx);
3470 new_rtx = gen_const_mem (Pmode, temp);
3471 }
3472 else
3473 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3474 emit_move_insn (reg, new_rtx);
3475 new_rtx = reg;
3476 }
3477 else
3478 {
3479 /* If the GOT offset might be >= 4k, we have to load it
3480 from the literal pool (@GOT). */
3481
3482 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3483
3484 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3485 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3486
3487 if (reload_in_progress || reload_completed)
3488 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3489
3490 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3491 addr = gen_rtx_CONST (Pmode, addr);
3492 addr = force_const_mem (Pmode, addr);
3493 emit_move_insn (temp, addr);
3494
3495 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3496 new_rtx = gen_const_mem (Pmode, new_rtx);
3497 emit_move_insn (reg, new_rtx);
3498 new_rtx = reg;
3499 }
3500 }
3501 else
3502 {
3503 if (GET_CODE (addr) == CONST)
3504 {
3505 addr = XEXP (addr, 0);
3506 if (GET_CODE (addr) == UNSPEC)
3507 {
3508 gcc_assert (XVECLEN (addr, 0) == 1);
3509 switch (XINT (addr, 1))
3510 {
3511 /* If someone moved a GOT-relative UNSPEC
3512 out of the literal pool, force them back in. */
3513 case UNSPEC_GOTOFF:
3514 case UNSPEC_PLTOFF:
3515 new_rtx = force_const_mem (Pmode, orig);
3516 break;
3517
3518 /* @GOT is OK as is if small. */
3519 case UNSPEC_GOT:
3520 if (flag_pic == 2)
3521 new_rtx = force_const_mem (Pmode, orig);
3522 break;
3523
3524 /* @GOTENT is OK as is. */
3525 case UNSPEC_GOTENT:
3526 break;
3527
3528 /* @PLT is OK as is on 64-bit, must be converted to
3529 GOT-relative @PLTOFF on 31-bit. */
3530 case UNSPEC_PLT:
3531 if (!TARGET_CPU_ZARCH)
3532 {
3533 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3534
3535 if (reload_in_progress || reload_completed)
3536 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3537
3538 addr = XVECEXP (addr, 0, 0);
3539 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3540 UNSPEC_PLTOFF);
3541 addr = gen_rtx_CONST (Pmode, addr);
3542 addr = force_const_mem (Pmode, addr);
3543 emit_move_insn (temp, addr);
3544
3545 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3546 if (reg != 0)
3547 {
3548 s390_load_address (reg, new_rtx);
3549 new_rtx = reg;
3550 }
3551 }
3552 break;
3553
3554 /* Everything else cannot happen. */
3555 default:
3556 gcc_unreachable ();
3557 }
3558 }
3559 else
3560 gcc_assert (GET_CODE (addr) == PLUS);
3561 }
3562 if (GET_CODE (addr) == PLUS)
3563 {
3564 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3565
3566 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3567 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3568
3569 /* Check first to see if this is a constant offset
3570 from a local symbol reference. */
3571 if ((GET_CODE (op0) == LABEL_REF
3572 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3573 && GET_CODE (op1) == CONST_INT)
3574 {
3575 if (TARGET_CPU_ZARCH
3576 && larl_operand (op0, VOIDmode)
3577 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3578 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3579 {
3580 if (INTVAL (op1) & 1)
3581 {
3582 /* LARL can't handle odd offsets, so emit a
3583 pair of LARL and LA. */
3584 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3585
3586 if (!DISP_IN_RANGE (INTVAL (op1)))
3587 {
3588 HOST_WIDE_INT even = INTVAL (op1) - 1;
3589 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3590 op0 = gen_rtx_CONST (Pmode, op0);
3591 op1 = const1_rtx;
3592 }
3593
3594 emit_move_insn (temp, op0);
3595 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3596
3597 if (reg != 0)
3598 {
3599 s390_load_address (reg, new_rtx);
3600 new_rtx = reg;
3601 }
3602 }
3603 else
3604 {
3605 /* If the offset is even, we can just use LARL.
3606 This will happen automatically. */
3607 }
3608 }
3609 else
3610 {
3611 /* Access local symbols relative to the GOT. */
3612
3613 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3614
3615 if (reload_in_progress || reload_completed)
3616 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3617
3618 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3619 UNSPEC_GOTOFF);
3620 addr = gen_rtx_PLUS (Pmode, addr, op1);
3621 addr = gen_rtx_CONST (Pmode, addr);
3622 addr = force_const_mem (Pmode, addr);
3623 emit_move_insn (temp, addr);
3624
3625 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3626 if (reg != 0)
3627 {
3628 s390_load_address (reg, new_rtx);
3629 new_rtx = reg;
3630 }
3631 }
3632 }
3633
3634 /* Now, check whether it is a GOT relative symbol plus offset
3635 that was pulled out of the literal pool. Force it back in. */
3636
3637 else if (GET_CODE (op0) == UNSPEC
3638 && GET_CODE (op1) == CONST_INT
3639 && XINT (op0, 1) == UNSPEC_GOTOFF)
3640 {
3641 gcc_assert (XVECLEN (op0, 0) == 1);
3642
3643 new_rtx = force_const_mem (Pmode, orig);
3644 }
3645
3646 /* Otherwise, compute the sum. */
3647 else
3648 {
3649 base = legitimize_pic_address (XEXP (addr, 0), reg);
3650 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3651 base == reg ? NULL_RTX : reg);
3652 if (GET_CODE (new_rtx) == CONST_INT)
3653 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3654 else
3655 {
3656 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3657 {
3658 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3659 new_rtx = XEXP (new_rtx, 1);
3660 }
3661 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3662 }
3663
3664 if (GET_CODE (new_rtx) == CONST)
3665 new_rtx = XEXP (new_rtx, 0);
3666 new_rtx = force_operand (new_rtx, 0);
3667 }
3668 }
3669 }
3670 return new_rtx;
3671 }
3672
3673 /* Load the thread pointer into a register. */
3674
3675 rtx
3676 s390_get_thread_pointer (void)
3677 {
3678 rtx tp = gen_reg_rtx (Pmode);
3679
3680 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3681 mark_reg_pointer (tp, BITS_PER_WORD);
3682
3683 return tp;
3684 }
3685
3686 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3687 in s390_tls_symbol which always refers to __tls_get_offset.
3688 The returned offset is written to RESULT_REG and an USE rtx is
3689 generated for TLS_CALL. */
3690
3691 static GTY(()) rtx s390_tls_symbol;
3692
3693 static void
3694 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3695 {
3696 rtx insn;
3697
3698 if (!flag_pic)
3699 emit_insn (s390_load_got ());
3700
3701 if (!s390_tls_symbol)
3702 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3703
3704 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3705 gen_rtx_REG (Pmode, RETURN_REGNUM));
3706
3707 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3708 RTL_CONST_CALL_P (insn) = 1;
3709 }
3710
3711 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3712 this (thread-local) address. REG may be used as temporary. */
3713
3714 static rtx
3715 legitimize_tls_address (rtx addr, rtx reg)
3716 {
3717 rtx new_rtx, tls_call, temp, base, r2, insn;
3718
3719 if (GET_CODE (addr) == SYMBOL_REF)
3720 switch (tls_symbolic_operand (addr))
3721 {
3722 case TLS_MODEL_GLOBAL_DYNAMIC:
3723 start_sequence ();
3724 r2 = gen_rtx_REG (Pmode, 2);
3725 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3726 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3727 new_rtx = force_const_mem (Pmode, new_rtx);
3728 emit_move_insn (r2, new_rtx);
3729 s390_emit_tls_call_insn (r2, tls_call);
3730 insn = get_insns ();
3731 end_sequence ();
3732
3733 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3734 temp = gen_reg_rtx (Pmode);
3735 emit_libcall_block (insn, temp, r2, new_rtx);
3736
3737 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3738 if (reg != 0)
3739 {
3740 s390_load_address (reg, new_rtx);
3741 new_rtx = reg;
3742 }
3743 break;
3744
3745 case TLS_MODEL_LOCAL_DYNAMIC:
3746 start_sequence ();
3747 r2 = gen_rtx_REG (Pmode, 2);
3748 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3749 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3750 new_rtx = force_const_mem (Pmode, new_rtx);
3751 emit_move_insn (r2, new_rtx);
3752 s390_emit_tls_call_insn (r2, tls_call);
3753 insn = get_insns ();
3754 end_sequence ();
3755
3756 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3757 temp = gen_reg_rtx (Pmode);
3758 emit_libcall_block (insn, temp, r2, new_rtx);
3759
3760 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3761 base = gen_reg_rtx (Pmode);
3762 s390_load_address (base, new_rtx);
3763
3764 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3765 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3766 new_rtx = force_const_mem (Pmode, new_rtx);
3767 temp = gen_reg_rtx (Pmode);
3768 emit_move_insn (temp, new_rtx);
3769
3770 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3771 if (reg != 0)
3772 {
3773 s390_load_address (reg, new_rtx);
3774 new_rtx = reg;
3775 }
3776 break;
3777
3778 case TLS_MODEL_INITIAL_EXEC:
3779 if (flag_pic == 1)
3780 {
3781 /* Assume GOT offset < 4k. This is handled the same way
3782 in both 31- and 64-bit code. */
3783
3784 if (reload_in_progress || reload_completed)
3785 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3786
3787 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3788 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3789 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3790 new_rtx = gen_const_mem (Pmode, new_rtx);
3791 temp = gen_reg_rtx (Pmode);
3792 emit_move_insn (temp, new_rtx);
3793 }
3794 else if (TARGET_CPU_ZARCH)
3795 {
3796 /* If the GOT offset might be >= 4k, we determine the position
3797 of the GOT entry via a PC-relative LARL. */
3798
3799 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3800 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3801 temp = gen_reg_rtx (Pmode);
3802 emit_move_insn (temp, new_rtx);
3803
3804 new_rtx = gen_const_mem (Pmode, temp);
3805 temp = gen_reg_rtx (Pmode);
3806 emit_move_insn (temp, new_rtx);
3807 }
3808 else if (flag_pic)
3809 {
3810 /* If the GOT offset might be >= 4k, we have to load it
3811 from the literal pool. */
3812
3813 if (reload_in_progress || reload_completed)
3814 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3815
3816 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3817 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3818 new_rtx = force_const_mem (Pmode, new_rtx);
3819 temp = gen_reg_rtx (Pmode);
3820 emit_move_insn (temp, new_rtx);
3821
3822 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3823 new_rtx = gen_const_mem (Pmode, new_rtx);
3824
3825 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3826 temp = gen_reg_rtx (Pmode);
3827 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3828 }
3829 else
3830 {
3831 /* In position-dependent code, load the absolute address of
3832 the GOT entry from the literal pool. */
3833
3834 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3835 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3836 new_rtx = force_const_mem (Pmode, new_rtx);
3837 temp = gen_reg_rtx (Pmode);
3838 emit_move_insn (temp, new_rtx);
3839
3840 new_rtx = temp;
3841 new_rtx = gen_const_mem (Pmode, new_rtx);
3842 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3843 temp = gen_reg_rtx (Pmode);
3844 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3845 }
3846
3847 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3848 if (reg != 0)
3849 {
3850 s390_load_address (reg, new_rtx);
3851 new_rtx = reg;
3852 }
3853 break;
3854
3855 case TLS_MODEL_LOCAL_EXEC:
3856 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3857 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3858 new_rtx = force_const_mem (Pmode, new_rtx);
3859 temp = gen_reg_rtx (Pmode);
3860 emit_move_insn (temp, new_rtx);
3861
3862 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3863 if (reg != 0)
3864 {
3865 s390_load_address (reg, new_rtx);
3866 new_rtx = reg;
3867 }
3868 break;
3869
3870 default:
3871 gcc_unreachable ();
3872 }
3873
3874 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3875 {
3876 switch (XINT (XEXP (addr, 0), 1))
3877 {
3878 case UNSPEC_INDNTPOFF:
3879 gcc_assert (TARGET_CPU_ZARCH);
3880 new_rtx = addr;
3881 break;
3882
3883 default:
3884 gcc_unreachable ();
3885 }
3886 }
3887
3888 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3889 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3890 {
3891 new_rtx = XEXP (XEXP (addr, 0), 0);
3892 if (GET_CODE (new_rtx) != SYMBOL_REF)
3893 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3894
3895 new_rtx = legitimize_tls_address (new_rtx, reg);
3896 new_rtx = plus_constant (Pmode, new_rtx,
3897 INTVAL (XEXP (XEXP (addr, 0), 1)));
3898 new_rtx = force_operand (new_rtx, 0);
3899 }
3900
3901 else
3902 gcc_unreachable (); /* for now ... */
3903
3904 return new_rtx;
3905 }
3906
3907 /* Emit insns making the address in operands[1] valid for a standard
3908 move to operands[0]. operands[1] is replaced by an address which
3909 should be used instead of the former RTX to emit the move
3910 pattern. */
3911
3912 void
3913 emit_symbolic_move (rtx *operands)
3914 {
3915 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3916
3917 if (GET_CODE (operands[0]) == MEM)
3918 operands[1] = force_reg (Pmode, operands[1]);
3919 else if (TLS_SYMBOLIC_CONST (operands[1]))
3920 operands[1] = legitimize_tls_address (operands[1], temp);
3921 else if (flag_pic)
3922 operands[1] = legitimize_pic_address (operands[1], temp);
3923 }
3924
3925 /* Try machine-dependent ways of modifying an illegitimate address X
3926 to be legitimate. If we find one, return the new, valid address.
3927
3928 OLDX is the address as it was before break_out_memory_refs was called.
3929 In some cases it is useful to look at this to decide what needs to be done.
3930
3931 MODE is the mode of the operand pointed to by X.
3932
3933 When -fpic is used, special handling is needed for symbolic references.
3934 See comments by legitimize_pic_address for details. */
3935
3936 static rtx
3937 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3938 enum machine_mode mode ATTRIBUTE_UNUSED)
3939 {
3940 rtx constant_term = const0_rtx;
3941
3942 if (TLS_SYMBOLIC_CONST (x))
3943 {
3944 x = legitimize_tls_address (x, 0);
3945
3946 if (s390_legitimate_address_p (mode, x, FALSE))
3947 return x;
3948 }
3949 else if (GET_CODE (x) == PLUS
3950 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3951 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3952 {
3953 return x;
3954 }
3955 else if (flag_pic)
3956 {
3957 if (SYMBOLIC_CONST (x)
3958 || (GET_CODE (x) == PLUS
3959 && (SYMBOLIC_CONST (XEXP (x, 0))
3960 || SYMBOLIC_CONST (XEXP (x, 1)))))
3961 x = legitimize_pic_address (x, 0);
3962
3963 if (s390_legitimate_address_p (mode, x, FALSE))
3964 return x;
3965 }
3966
3967 x = eliminate_constant_term (x, &constant_term);
3968
3969 /* Optimize loading of large displacements by splitting them
3970 into the multiple of 4K and the rest; this allows the
3971 former to be CSE'd if possible.
3972
3973 Don't do this if the displacement is added to a register
3974 pointing into the stack frame, as the offsets will
3975 change later anyway. */
3976
3977 if (GET_CODE (constant_term) == CONST_INT
3978 && !TARGET_LONG_DISPLACEMENT
3979 && !DISP_IN_RANGE (INTVAL (constant_term))
3980 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3981 {
3982 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3983 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3984
3985 rtx temp = gen_reg_rtx (Pmode);
3986 rtx val = force_operand (GEN_INT (upper), temp);
3987 if (val != temp)
3988 emit_move_insn (temp, val);
3989
3990 x = gen_rtx_PLUS (Pmode, x, temp);
3991 constant_term = GEN_INT (lower);
3992 }
3993
3994 if (GET_CODE (x) == PLUS)
3995 {
3996 if (GET_CODE (XEXP (x, 0)) == REG)
3997 {
3998 rtx temp = gen_reg_rtx (Pmode);
3999 rtx val = force_operand (XEXP (x, 1), temp);
4000 if (val != temp)
4001 emit_move_insn (temp, val);
4002
4003 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4004 }
4005
4006 else if (GET_CODE (XEXP (x, 1)) == REG)
4007 {
4008 rtx temp = gen_reg_rtx (Pmode);
4009 rtx val = force_operand (XEXP (x, 0), temp);
4010 if (val != temp)
4011 emit_move_insn (temp, val);
4012
4013 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4014 }
4015 }
4016
4017 if (constant_term != const0_rtx)
4018 x = gen_rtx_PLUS (Pmode, x, constant_term);
4019
4020 return x;
4021 }
4022
4023 /* Try a machine-dependent way of reloading an illegitimate address AD
4024 operand. If we find one, push the reload and return the new address.
4025
4026 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4027 and TYPE is the reload type of the current reload. */
4028
4029 rtx
4030 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
4031 int opnum, int type)
4032 {
4033 if (!optimize || TARGET_LONG_DISPLACEMENT)
4034 return NULL_RTX;
4035
4036 if (GET_CODE (ad) == PLUS)
4037 {
4038 rtx tem = simplify_binary_operation (PLUS, Pmode,
4039 XEXP (ad, 0), XEXP (ad, 1));
4040 if (tem)
4041 ad = tem;
4042 }
4043
4044 if (GET_CODE (ad) == PLUS
4045 && GET_CODE (XEXP (ad, 0)) == REG
4046 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4047 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4048 {
4049 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4050 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4051 rtx cst, tem, new_rtx;
4052
4053 cst = GEN_INT (upper);
4054 if (!legitimate_reload_constant_p (cst))
4055 cst = force_const_mem (Pmode, cst);
4056
4057 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4058 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4059
4060 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4061 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4062 opnum, (enum reload_type) type);
4063 return new_rtx;
4064 }
4065
4066 return NULL_RTX;
4067 }
4068
4069 /* Emit code to move LEN bytes from DST to SRC. */
4070
4071 bool
4072 s390_expand_movmem (rtx dst, rtx src, rtx len)
4073 {
4074 /* When tuning for z10 or higher we rely on the Glibc functions to
4075 do the right thing. Only for constant lengths below 64k we will
4076 generate inline code. */
4077 if (s390_tune >= PROCESSOR_2097_Z10
4078 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4079 return false;
4080
4081 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4082 {
4083 if (INTVAL (len) > 0)
4084 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4085 }
4086
4087 else if (TARGET_MVCLE)
4088 {
4089 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4090 }
4091
4092 else
4093 {
4094 rtx dst_addr, src_addr, count, blocks, temp;
4095 rtx loop_start_label = gen_label_rtx ();
4096 rtx loop_end_label = gen_label_rtx ();
4097 rtx end_label = gen_label_rtx ();
4098 enum machine_mode mode;
4099
4100 mode = GET_MODE (len);
4101 if (mode == VOIDmode)
4102 mode = Pmode;
4103
4104 dst_addr = gen_reg_rtx (Pmode);
4105 src_addr = gen_reg_rtx (Pmode);
4106 count = gen_reg_rtx (mode);
4107 blocks = gen_reg_rtx (mode);
4108
4109 convert_move (count, len, 1);
4110 emit_cmp_and_jump_insns (count, const0_rtx,
4111 EQ, NULL_RTX, mode, 1, end_label);
4112
4113 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4114 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4115 dst = change_address (dst, VOIDmode, dst_addr);
4116 src = change_address (src, VOIDmode, src_addr);
4117
4118 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4119 OPTAB_DIRECT);
4120 if (temp != count)
4121 emit_move_insn (count, temp);
4122
4123 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4124 OPTAB_DIRECT);
4125 if (temp != blocks)
4126 emit_move_insn (blocks, temp);
4127
4128 emit_cmp_and_jump_insns (blocks, const0_rtx,
4129 EQ, NULL_RTX, mode, 1, loop_end_label);
4130
4131 emit_label (loop_start_label);
4132
4133 if (TARGET_Z10
4134 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4135 {
4136 rtx prefetch;
4137
4138 /* Issue a read prefetch for the +3 cache line. */
4139 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4140 const0_rtx, const0_rtx);
4141 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4142 emit_insn (prefetch);
4143
4144 /* Issue a write prefetch for the +3 cache line. */
4145 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4146 const1_rtx, const0_rtx);
4147 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4148 emit_insn (prefetch);
4149 }
4150
4151 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4152 s390_load_address (dst_addr,
4153 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4154 s390_load_address (src_addr,
4155 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4156
4157 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4158 OPTAB_DIRECT);
4159 if (temp != blocks)
4160 emit_move_insn (blocks, temp);
4161
4162 emit_cmp_and_jump_insns (blocks, const0_rtx,
4163 EQ, NULL_RTX, mode, 1, loop_end_label);
4164
4165 emit_jump (loop_start_label);
4166 emit_label (loop_end_label);
4167
4168 emit_insn (gen_movmem_short (dst, src,
4169 convert_to_mode (Pmode, count, 1)));
4170 emit_label (end_label);
4171 }
4172 return true;
4173 }
4174
4175 /* Emit code to set LEN bytes at DST to VAL.
4176 Make use of clrmem if VAL is zero. */
4177
4178 void
4179 s390_expand_setmem (rtx dst, rtx len, rtx val)
4180 {
4181 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4182 return;
4183
4184 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4185
4186 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4187 {
4188 if (val == const0_rtx && INTVAL (len) <= 256)
4189 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4190 else
4191 {
4192 /* Initialize memory by storing the first byte. */
4193 emit_move_insn (adjust_address (dst, QImode, 0), val);
4194
4195 if (INTVAL (len) > 1)
4196 {
4197 /* Initiate 1 byte overlap move.
4198 The first byte of DST is propagated through DSTP1.
4199 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4200 DST is set to size 1 so the rest of the memory location
4201 does not count as source operand. */
4202 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4203 set_mem_size (dst, 1);
4204
4205 emit_insn (gen_movmem_short (dstp1, dst,
4206 GEN_INT (INTVAL (len) - 2)));
4207 }
4208 }
4209 }
4210
4211 else if (TARGET_MVCLE)
4212 {
4213 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4214 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4215 }
4216
4217 else
4218 {
4219 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4220 rtx loop_start_label = gen_label_rtx ();
4221 rtx loop_end_label = gen_label_rtx ();
4222 rtx end_label = gen_label_rtx ();
4223 enum machine_mode mode;
4224
4225 mode = GET_MODE (len);
4226 if (mode == VOIDmode)
4227 mode = Pmode;
4228
4229 dst_addr = gen_reg_rtx (Pmode);
4230 count = gen_reg_rtx (mode);
4231 blocks = gen_reg_rtx (mode);
4232
4233 convert_move (count, len, 1);
4234 emit_cmp_and_jump_insns (count, const0_rtx,
4235 EQ, NULL_RTX, mode, 1, end_label);
4236
4237 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4238 dst = change_address (dst, VOIDmode, dst_addr);
4239
4240 if (val == const0_rtx)
4241 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4242 OPTAB_DIRECT);
4243 else
4244 {
4245 dstp1 = adjust_address (dst, VOIDmode, 1);
4246 set_mem_size (dst, 1);
4247
4248 /* Initialize memory by storing the first byte. */
4249 emit_move_insn (adjust_address (dst, QImode, 0), val);
4250
4251 /* If count is 1 we are done. */
4252 emit_cmp_and_jump_insns (count, const1_rtx,
4253 EQ, NULL_RTX, mode, 1, end_label);
4254
4255 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4256 OPTAB_DIRECT);
4257 }
4258 if (temp != count)
4259 emit_move_insn (count, temp);
4260
4261 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4262 OPTAB_DIRECT);
4263 if (temp != blocks)
4264 emit_move_insn (blocks, temp);
4265
4266 emit_cmp_and_jump_insns (blocks, const0_rtx,
4267 EQ, NULL_RTX, mode, 1, loop_end_label);
4268
4269 emit_label (loop_start_label);
4270
4271 if (TARGET_Z10
4272 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4273 {
4274 /* Issue a write prefetch for the +4 cache line. */
4275 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4276 GEN_INT (1024)),
4277 const1_rtx, const0_rtx);
4278 emit_insn (prefetch);
4279 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4280 }
4281
4282 if (val == const0_rtx)
4283 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4284 else
4285 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4286 s390_load_address (dst_addr,
4287 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4288
4289 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4290 OPTAB_DIRECT);
4291 if (temp != blocks)
4292 emit_move_insn (blocks, temp);
4293
4294 emit_cmp_and_jump_insns (blocks, const0_rtx,
4295 EQ, NULL_RTX, mode, 1, loop_end_label);
4296
4297 emit_jump (loop_start_label);
4298 emit_label (loop_end_label);
4299
4300 if (val == const0_rtx)
4301 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4302 else
4303 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4304 emit_label (end_label);
4305 }
4306 }
4307
4308 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4309 and return the result in TARGET. */
4310
4311 bool
4312 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4313 {
4314 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4315 rtx tmp;
4316
4317 /* When tuning for z10 or higher we rely on the Glibc functions to
4318 do the right thing. Only for constant lengths below 64k we will
4319 generate inline code. */
4320 if (s390_tune >= PROCESSOR_2097_Z10
4321 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4322 return false;
4323
4324 /* As the result of CMPINT is inverted compared to what we need,
4325 we have to swap the operands. */
4326 tmp = op0; op0 = op1; op1 = tmp;
4327
4328 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4329 {
4330 if (INTVAL (len) > 0)
4331 {
4332 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4333 emit_insn (gen_cmpint (target, ccreg));
4334 }
4335 else
4336 emit_move_insn (target, const0_rtx);
4337 }
4338 else if (TARGET_MVCLE)
4339 {
4340 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4341 emit_insn (gen_cmpint (target, ccreg));
4342 }
4343 else
4344 {
4345 rtx addr0, addr1, count, blocks, temp;
4346 rtx loop_start_label = gen_label_rtx ();
4347 rtx loop_end_label = gen_label_rtx ();
4348 rtx end_label = gen_label_rtx ();
4349 enum machine_mode mode;
4350
4351 mode = GET_MODE (len);
4352 if (mode == VOIDmode)
4353 mode = Pmode;
4354
4355 addr0 = gen_reg_rtx (Pmode);
4356 addr1 = gen_reg_rtx (Pmode);
4357 count = gen_reg_rtx (mode);
4358 blocks = gen_reg_rtx (mode);
4359
4360 convert_move (count, len, 1);
4361 emit_cmp_and_jump_insns (count, const0_rtx,
4362 EQ, NULL_RTX, mode, 1, end_label);
4363
4364 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4365 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4366 op0 = change_address (op0, VOIDmode, addr0);
4367 op1 = change_address (op1, VOIDmode, addr1);
4368
4369 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4370 OPTAB_DIRECT);
4371 if (temp != count)
4372 emit_move_insn (count, temp);
4373
4374 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4375 OPTAB_DIRECT);
4376 if (temp != blocks)
4377 emit_move_insn (blocks, temp);
4378
4379 emit_cmp_and_jump_insns (blocks, const0_rtx,
4380 EQ, NULL_RTX, mode, 1, loop_end_label);
4381
4382 emit_label (loop_start_label);
4383
4384 if (TARGET_Z10
4385 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4386 {
4387 rtx prefetch;
4388
4389 /* Issue a read prefetch for the +2 cache line of operand 1. */
4390 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4391 const0_rtx, const0_rtx);
4392 emit_insn (prefetch);
4393 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4394
4395 /* Issue a read prefetch for the +2 cache line of operand 2. */
4396 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4397 const0_rtx, const0_rtx);
4398 emit_insn (prefetch);
4399 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4400 }
4401
4402 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4403 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4404 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4405 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4406 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4407 emit_jump_insn (temp);
4408
4409 s390_load_address (addr0,
4410 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4411 s390_load_address (addr1,
4412 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4413
4414 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4415 OPTAB_DIRECT);
4416 if (temp != blocks)
4417 emit_move_insn (blocks, temp);
4418
4419 emit_cmp_and_jump_insns (blocks, const0_rtx,
4420 EQ, NULL_RTX, mode, 1, loop_end_label);
4421
4422 emit_jump (loop_start_label);
4423 emit_label (loop_end_label);
4424
4425 emit_insn (gen_cmpmem_short (op0, op1,
4426 convert_to_mode (Pmode, count, 1)));
4427 emit_label (end_label);
4428
4429 emit_insn (gen_cmpint (target, ccreg));
4430 }
4431 return true;
4432 }
4433
4434
4435 /* Expand conditional increment or decrement using alc/slb instructions.
4436 Should generate code setting DST to either SRC or SRC + INCREMENT,
4437 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4438 Returns true if successful, false otherwise.
4439
4440 That makes it possible to implement some if-constructs without jumps e.g.:
4441 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4442 unsigned int a, b, c;
4443 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4444 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4445 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4446 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4447
4448 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4449 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4450 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4451 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4452 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4453
4454 bool
4455 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4456 rtx dst, rtx src, rtx increment)
4457 {
4458 enum machine_mode cmp_mode;
4459 enum machine_mode cc_mode;
4460 rtx op_res;
4461 rtx insn;
4462 rtvec p;
4463 int ret;
4464
4465 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4466 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4467 cmp_mode = SImode;
4468 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4469 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4470 cmp_mode = DImode;
4471 else
4472 return false;
4473
4474 /* Try ADD LOGICAL WITH CARRY. */
4475 if (increment == const1_rtx)
4476 {
4477 /* Determine CC mode to use. */
4478 if (cmp_code == EQ || cmp_code == NE)
4479 {
4480 if (cmp_op1 != const0_rtx)
4481 {
4482 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4483 NULL_RTX, 0, OPTAB_WIDEN);
4484 cmp_op1 = const0_rtx;
4485 }
4486
4487 cmp_code = cmp_code == EQ ? LEU : GTU;
4488 }
4489
4490 if (cmp_code == LTU || cmp_code == LEU)
4491 {
4492 rtx tem = cmp_op0;
4493 cmp_op0 = cmp_op1;
4494 cmp_op1 = tem;
4495 cmp_code = swap_condition (cmp_code);
4496 }
4497
4498 switch (cmp_code)
4499 {
4500 case GTU:
4501 cc_mode = CCUmode;
4502 break;
4503
4504 case GEU:
4505 cc_mode = CCL3mode;
4506 break;
4507
4508 default:
4509 return false;
4510 }
4511
4512 /* Emit comparison instruction pattern. */
4513 if (!register_operand (cmp_op0, cmp_mode))
4514 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4515
4516 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4517 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4518 /* We use insn_invalid_p here to add clobbers if required. */
4519 ret = insn_invalid_p (emit_insn (insn), false);
4520 gcc_assert (!ret);
4521
4522 /* Emit ALC instruction pattern. */
4523 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4524 gen_rtx_REG (cc_mode, CC_REGNUM),
4525 const0_rtx);
4526
4527 if (src != const0_rtx)
4528 {
4529 if (!register_operand (src, GET_MODE (dst)))
4530 src = force_reg (GET_MODE (dst), src);
4531
4532 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4533 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4534 }
4535
4536 p = rtvec_alloc (2);
4537 RTVEC_ELT (p, 0) =
4538 gen_rtx_SET (VOIDmode, dst, op_res);
4539 RTVEC_ELT (p, 1) =
4540 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4541 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4542
4543 return true;
4544 }
4545
4546 /* Try SUBTRACT LOGICAL WITH BORROW. */
4547 if (increment == constm1_rtx)
4548 {
4549 /* Determine CC mode to use. */
4550 if (cmp_code == EQ || cmp_code == NE)
4551 {
4552 if (cmp_op1 != const0_rtx)
4553 {
4554 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4555 NULL_RTX, 0, OPTAB_WIDEN);
4556 cmp_op1 = const0_rtx;
4557 }
4558
4559 cmp_code = cmp_code == EQ ? LEU : GTU;
4560 }
4561
4562 if (cmp_code == GTU || cmp_code == GEU)
4563 {
4564 rtx tem = cmp_op0;
4565 cmp_op0 = cmp_op1;
4566 cmp_op1 = tem;
4567 cmp_code = swap_condition (cmp_code);
4568 }
4569
4570 switch (cmp_code)
4571 {
4572 case LEU:
4573 cc_mode = CCUmode;
4574 break;
4575
4576 case LTU:
4577 cc_mode = CCL3mode;
4578 break;
4579
4580 default:
4581 return false;
4582 }
4583
4584 /* Emit comparison instruction pattern. */
4585 if (!register_operand (cmp_op0, cmp_mode))
4586 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4587
4588 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4589 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4590 /* We use insn_invalid_p here to add clobbers if required. */
4591 ret = insn_invalid_p (emit_insn (insn), false);
4592 gcc_assert (!ret);
4593
4594 /* Emit SLB instruction pattern. */
4595 if (!register_operand (src, GET_MODE (dst)))
4596 src = force_reg (GET_MODE (dst), src);
4597
4598 op_res = gen_rtx_MINUS (GET_MODE (dst),
4599 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4600 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4601 gen_rtx_REG (cc_mode, CC_REGNUM),
4602 const0_rtx));
4603 p = rtvec_alloc (2);
4604 RTVEC_ELT (p, 0) =
4605 gen_rtx_SET (VOIDmode, dst, op_res);
4606 RTVEC_ELT (p, 1) =
4607 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4608 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4609
4610 return true;
4611 }
4612
4613 return false;
4614 }
4615
4616 /* Expand code for the insv template. Return true if successful. */
4617
4618 bool
4619 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4620 {
4621 int bitsize = INTVAL (op1);
4622 int bitpos = INTVAL (op2);
4623 enum machine_mode mode = GET_MODE (dest);
4624 enum machine_mode smode;
4625 int smode_bsize, mode_bsize;
4626 rtx op, clobber;
4627
4628 /* Generate INSERT IMMEDIATE (IILL et al). */
4629 /* (set (ze (reg)) (const_int)). */
4630 if (TARGET_ZARCH
4631 && register_operand (dest, word_mode)
4632 && (bitpos % 16) == 0
4633 && (bitsize % 16) == 0
4634 && const_int_operand (src, VOIDmode))
4635 {
4636 HOST_WIDE_INT val = INTVAL (src);
4637 int regpos = bitpos + bitsize;
4638
4639 while (regpos > bitpos)
4640 {
4641 enum machine_mode putmode;
4642 int putsize;
4643
4644 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4645 putmode = SImode;
4646 else
4647 putmode = HImode;
4648
4649 putsize = GET_MODE_BITSIZE (putmode);
4650 regpos -= putsize;
4651 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4652 GEN_INT (putsize),
4653 GEN_INT (regpos)),
4654 gen_int_mode (val, putmode));
4655 val >>= putsize;
4656 }
4657 gcc_assert (regpos == bitpos);
4658 return true;
4659 }
4660
4661 smode = smallest_mode_for_size (bitsize, MODE_INT);
4662 smode_bsize = GET_MODE_BITSIZE (smode);
4663 mode_bsize = GET_MODE_BITSIZE (mode);
4664
4665 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4666 if (bitpos == 0
4667 && (bitsize % BITS_PER_UNIT) == 0
4668 && MEM_P (dest)
4669 && (register_operand (src, word_mode)
4670 || const_int_operand (src, VOIDmode)))
4671 {
4672 /* Emit standard pattern if possible. */
4673 if (smode_bsize == bitsize)
4674 {
4675 emit_move_insn (adjust_address (dest, smode, 0),
4676 gen_lowpart (smode, src));
4677 return true;
4678 }
4679
4680 /* (set (ze (mem)) (const_int)). */
4681 else if (const_int_operand (src, VOIDmode))
4682 {
4683 int size = bitsize / BITS_PER_UNIT;
4684 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4685 BLKmode,
4686 UNITS_PER_WORD - size);
4687
4688 dest = adjust_address (dest, BLKmode, 0);
4689 set_mem_size (dest, size);
4690 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4691 return true;
4692 }
4693
4694 /* (set (ze (mem)) (reg)). */
4695 else if (register_operand (src, word_mode))
4696 {
4697 if (bitsize <= 32)
4698 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4699 const0_rtx), src);
4700 else
4701 {
4702 /* Emit st,stcmh sequence. */
4703 int stcmh_width = bitsize - 32;
4704 int size = stcmh_width / BITS_PER_UNIT;
4705
4706 emit_move_insn (adjust_address (dest, SImode, size),
4707 gen_lowpart (SImode, src));
4708 set_mem_size (dest, size);
4709 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4710 GEN_INT (stcmh_width),
4711 const0_rtx),
4712 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
4713 }
4714 return true;
4715 }
4716 }
4717
4718 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4719 if ((bitpos % BITS_PER_UNIT) == 0
4720 && (bitsize % BITS_PER_UNIT) == 0
4721 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4722 && MEM_P (src)
4723 && (mode == DImode || mode == SImode)
4724 && register_operand (dest, mode))
4725 {
4726 /* Emit a strict_low_part pattern if possible. */
4727 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4728 {
4729 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4730 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4731 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4732 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4733 return true;
4734 }
4735
4736 /* ??? There are more powerful versions of ICM that are not
4737 completely represented in the md file. */
4738 }
4739
4740 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4741 if (TARGET_Z10 && (mode == DImode || mode == SImode))
4742 {
4743 enum machine_mode mode_s = GET_MODE (src);
4744
4745 if (mode_s == VOIDmode)
4746 {
4747 /* Assume const_int etc already in the proper mode. */
4748 src = force_reg (mode, src);
4749 }
4750 else if (mode_s != mode)
4751 {
4752 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4753 src = force_reg (mode_s, src);
4754 src = gen_lowpart (mode, src);
4755 }
4756
4757 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4758 op = gen_rtx_SET (VOIDmode, op, src);
4759
4760 if (!TARGET_ZEC12)
4761 {
4762 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4763 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4764 }
4765 emit_insn (op);
4766
4767 return true;
4768 }
4769
4770 return false;
4771 }
4772
4773 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4774 register that holds VAL of mode MODE shifted by COUNT bits. */
4775
4776 static inline rtx
4777 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4778 {
4779 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4780 NULL_RTX, 1, OPTAB_DIRECT);
4781 return expand_simple_binop (SImode, ASHIFT, val, count,
4782 NULL_RTX, 1, OPTAB_DIRECT);
4783 }
4784
4785 /* Structure to hold the initial parameters for a compare_and_swap operation
4786 in HImode and QImode. */
4787
4788 struct alignment_context
4789 {
4790 rtx memsi; /* SI aligned memory location. */
4791 rtx shift; /* Bit offset with regard to lsb. */
4792 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4793 rtx modemaski; /* ~modemask */
4794 bool aligned; /* True if memory is aligned, false else. */
4795 };
4796
4797 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4798 structure AC for transparent simplifying, if the memory alignment is known
4799 to be at least 32bit. MEM is the memory location for the actual operation
4800 and MODE its mode. */
4801
4802 static void
4803 init_alignment_context (struct alignment_context *ac, rtx mem,
4804 enum machine_mode mode)
4805 {
4806 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4807 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4808
4809 if (ac->aligned)
4810 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4811 else
4812 {
4813 /* Alignment is unknown. */
4814 rtx byteoffset, addr, align;
4815
4816 /* Force the address into a register. */
4817 addr = force_reg (Pmode, XEXP (mem, 0));
4818
4819 /* Align it to SImode. */
4820 align = expand_simple_binop (Pmode, AND, addr,
4821 GEN_INT (-GET_MODE_SIZE (SImode)),
4822 NULL_RTX, 1, OPTAB_DIRECT);
4823 /* Generate MEM. */
4824 ac->memsi = gen_rtx_MEM (SImode, align);
4825 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4826 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4827 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4828
4829 /* Calculate shiftcount. */
4830 byteoffset = expand_simple_binop (Pmode, AND, addr,
4831 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4832 NULL_RTX, 1, OPTAB_DIRECT);
4833 /* As we already have some offset, evaluate the remaining distance. */
4834 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4835 NULL_RTX, 1, OPTAB_DIRECT);
4836 }
4837
4838 /* Shift is the byte count, but we need the bitcount. */
4839 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4840 NULL_RTX, 1, OPTAB_DIRECT);
4841
4842 /* Calculate masks. */
4843 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4844 GEN_INT (GET_MODE_MASK (mode)),
4845 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4846 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4847 NULL_RTX, 1);
4848 }
4849
4850 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4851 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4852 perform the merge in SEQ2. */
4853
4854 static rtx
4855 s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4856 enum machine_mode mode, rtx val, rtx ins)
4857 {
4858 rtx tmp;
4859
4860 if (ac->aligned)
4861 {
4862 start_sequence ();
4863 tmp = copy_to_mode_reg (SImode, val);
4864 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4865 const0_rtx, ins))
4866 {
4867 *seq1 = NULL;
4868 *seq2 = get_insns ();
4869 end_sequence ();
4870 return tmp;
4871 }
4872 end_sequence ();
4873 }
4874
4875 /* Failed to use insv. Generate a two part shift and mask. */
4876 start_sequence ();
4877 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4878 *seq1 = get_insns ();
4879 end_sequence ();
4880
4881 start_sequence ();
4882 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4883 *seq2 = get_insns ();
4884 end_sequence ();
4885
4886 return tmp;
4887 }
4888
4889 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4890 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4891 value to set if CMP == MEM. */
4892
4893 void
4894 s390_expand_cs_hqi (enum machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4895 rtx cmp, rtx new_rtx, bool is_weak)
4896 {
4897 struct alignment_context ac;
4898 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
4899 rtx res = gen_reg_rtx (SImode);
4900 rtx csloop = NULL, csend = NULL;
4901
4902 gcc_assert (MEM_P (mem));
4903
4904 init_alignment_context (&ac, mem, mode);
4905
4906 /* Load full word. Subsequent loads are performed by CS. */
4907 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4908 NULL_RTX, 1, OPTAB_DIRECT);
4909
4910 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4911 possible, we try to use insv to make this happen efficiently. If
4912 that fails we'll generate code both inside and outside the loop. */
4913 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4914 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4915
4916 if (seq0)
4917 emit_insn (seq0);
4918 if (seq1)
4919 emit_insn (seq1);
4920
4921 /* Start CS loop. */
4922 if (!is_weak)
4923 {
4924 /* Begin assuming success. */
4925 emit_move_insn (btarget, const1_rtx);
4926
4927 csloop = gen_label_rtx ();
4928 csend = gen_label_rtx ();
4929 emit_label (csloop);
4930 }
4931
4932 /* val = "<mem>00..0<mem>"
4933 * cmp = "00..0<cmp>00..0"
4934 * new = "00..0<new>00..0"
4935 */
4936
4937 emit_insn (seq2);
4938 emit_insn (seq3);
4939
4940 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4941 if (is_weak)
4942 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
4943 else
4944 {
4945 rtx tmp;
4946
4947 /* Jump to end if we're done (likely?). */
4948 s390_emit_jump (csend, cc);
4949
4950 /* Check for changes outside mode, and loop internal if so.
4951 Arrange the moves so that the compare is adjacent to the
4952 branch so that we can generate CRJ. */
4953 tmp = copy_to_reg (val);
4954 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4955 1, OPTAB_DIRECT);
4956 cc = s390_emit_compare (NE, val, tmp);
4957 s390_emit_jump (csloop, cc);
4958
4959 /* Failed. */
4960 emit_move_insn (btarget, const0_rtx);
4961 emit_label (csend);
4962 }
4963
4964 /* Return the correct part of the bitfield. */
4965 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4966 NULL_RTX, 1, OPTAB_DIRECT), 1);
4967 }
4968
4969 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4970 and VAL the value to play with. If AFTER is true then store the value
4971 MEM holds after the operation, if AFTER is false then store the value MEM
4972 holds before the operation. If TARGET is zero then discard that value, else
4973 store it to TARGET. */
4974
4975 void
4976 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4977 rtx target, rtx mem, rtx val, bool after)
4978 {
4979 struct alignment_context ac;
4980 rtx cmp;
4981 rtx new_rtx = gen_reg_rtx (SImode);
4982 rtx orig = gen_reg_rtx (SImode);
4983 rtx csloop = gen_label_rtx ();
4984
4985 gcc_assert (!target || register_operand (target, VOIDmode));
4986 gcc_assert (MEM_P (mem));
4987
4988 init_alignment_context (&ac, mem, mode);
4989
4990 /* Shift val to the correct bit positions.
4991 Preserve "icm", but prevent "ex icm". */
4992 if (!(ac.aligned && code == SET && MEM_P (val)))
4993 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4994
4995 /* Further preparation insns. */
4996 if (code == PLUS || code == MINUS)
4997 emit_move_insn (orig, val);
4998 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4999 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
5000 NULL_RTX, 1, OPTAB_DIRECT);
5001
5002 /* Load full word. Subsequent loads are performed by CS. */
5003 cmp = force_reg (SImode, ac.memsi);
5004
5005 /* Start CS loop. */
5006 emit_label (csloop);
5007 emit_move_insn (new_rtx, cmp);
5008
5009 /* Patch new with val at correct position. */
5010 switch (code)
5011 {
5012 case PLUS:
5013 case MINUS:
5014 val = expand_simple_binop (SImode, code, new_rtx, orig,
5015 NULL_RTX, 1, OPTAB_DIRECT);
5016 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5017 NULL_RTX, 1, OPTAB_DIRECT);
5018 /* FALLTHRU */
5019 case SET:
5020 if (ac.aligned && MEM_P (val))
5021 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5022 0, 0, SImode, val);
5023 else
5024 {
5025 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
5026 NULL_RTX, 1, OPTAB_DIRECT);
5027 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
5028 NULL_RTX, 1, OPTAB_DIRECT);
5029 }
5030 break;
5031 case AND:
5032 case IOR:
5033 case XOR:
5034 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
5035 NULL_RTX, 1, OPTAB_DIRECT);
5036 break;
5037 case MULT: /* NAND */
5038 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
5039 NULL_RTX, 1, OPTAB_DIRECT);
5040 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5041 NULL_RTX, 1, OPTAB_DIRECT);
5042 break;
5043 default:
5044 gcc_unreachable ();
5045 }
5046
5047 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
5048 ac.memsi, cmp, new_rtx));
5049
5050 /* Return the correct part of the bitfield. */
5051 if (target)
5052 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
5053 after ? new_rtx : cmp, ac.shift,
5054 NULL_RTX, 1, OPTAB_DIRECT), 1);
5055 }
5056
5057 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5058 We need to emit DTP-relative relocations. */
5059
5060 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5061
5062 static void
5063 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
5064 {
5065 switch (size)
5066 {
5067 case 4:
5068 fputs ("\t.long\t", file);
5069 break;
5070 case 8:
5071 fputs ("\t.quad\t", file);
5072 break;
5073 default:
5074 gcc_unreachable ();
5075 }
5076 output_addr_const (file, x);
5077 fputs ("@DTPOFF", file);
5078 }
5079
5080 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5081 /* Implement TARGET_MANGLE_TYPE. */
5082
5083 static const char *
5084 s390_mangle_type (const_tree type)
5085 {
5086 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5087 && TARGET_LONG_DOUBLE_128)
5088 return "g";
5089
5090 /* For all other types, use normal C++ mangling. */
5091 return NULL;
5092 }
5093 #endif
5094
5095 /* In the name of slightly smaller debug output, and to cater to
5096 general assembler lossage, recognize various UNSPEC sequences
5097 and turn them back into a direct symbol reference. */
5098
5099 static rtx
5100 s390_delegitimize_address (rtx orig_x)
5101 {
5102 rtx x, y;
5103
5104 orig_x = delegitimize_mem_from_attrs (orig_x);
5105 x = orig_x;
5106
5107 /* Extract the symbol ref from:
5108 (plus:SI (reg:SI 12 %r12)
5109 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5110 UNSPEC_GOTOFF/PLTOFF)))
5111 and
5112 (plus:SI (reg:SI 12 %r12)
5113 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5114 UNSPEC_GOTOFF/PLTOFF)
5115 (const_int 4 [0x4])))) */
5116 if (GET_CODE (x) == PLUS
5117 && REG_P (XEXP (x, 0))
5118 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5119 && GET_CODE (XEXP (x, 1)) == CONST)
5120 {
5121 HOST_WIDE_INT offset = 0;
5122
5123 /* The const operand. */
5124 y = XEXP (XEXP (x, 1), 0);
5125
5126 if (GET_CODE (y) == PLUS
5127 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5128 {
5129 offset = INTVAL (XEXP (y, 1));
5130 y = XEXP (y, 0);
5131 }
5132
5133 if (GET_CODE (y) == UNSPEC
5134 && (XINT (y, 1) == UNSPEC_GOTOFF
5135 || XINT (y, 1) == UNSPEC_PLTOFF))
5136 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
5137 }
5138
5139 if (GET_CODE (x) != MEM)
5140 return orig_x;
5141
5142 x = XEXP (x, 0);
5143 if (GET_CODE (x) == PLUS
5144 && GET_CODE (XEXP (x, 1)) == CONST
5145 && GET_CODE (XEXP (x, 0)) == REG
5146 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5147 {
5148 y = XEXP (XEXP (x, 1), 0);
5149 if (GET_CODE (y) == UNSPEC
5150 && XINT (y, 1) == UNSPEC_GOT)
5151 y = XVECEXP (y, 0, 0);
5152 else
5153 return orig_x;
5154 }
5155 else if (GET_CODE (x) == CONST)
5156 {
5157 /* Extract the symbol ref from:
5158 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5159 UNSPEC_PLT/GOTENT))) */
5160
5161 y = XEXP (x, 0);
5162 if (GET_CODE (y) == UNSPEC
5163 && (XINT (y, 1) == UNSPEC_GOTENT
5164 || XINT (y, 1) == UNSPEC_PLT))
5165 y = XVECEXP (y, 0, 0);
5166 else
5167 return orig_x;
5168 }
5169 else
5170 return orig_x;
5171
5172 if (GET_MODE (orig_x) != Pmode)
5173 {
5174 if (GET_MODE (orig_x) == BLKmode)
5175 return orig_x;
5176 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5177 if (y == NULL_RTX)
5178 return orig_x;
5179 }
5180 return y;
5181 }
5182
5183 /* Output operand OP to stdio stream FILE.
5184 OP is an address (register + offset) which is not used to address data;
5185 instead the rightmost bits are interpreted as the value. */
5186
5187 static void
5188 print_shift_count_operand (FILE *file, rtx op)
5189 {
5190 HOST_WIDE_INT offset;
5191 rtx base;
5192
5193 /* Extract base register and offset. */
5194 if (!s390_decompose_shift_count (op, &base, &offset))
5195 gcc_unreachable ();
5196
5197 /* Sanity check. */
5198 if (base)
5199 {
5200 gcc_assert (GET_CODE (base) == REG);
5201 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5202 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5203 }
5204
5205 /* Offsets are constricted to twelve bits. */
5206 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5207 if (base)
5208 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5209 }
5210
5211 /* See 'get_some_local_dynamic_name'. */
5212
5213 static int
5214 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5215 {
5216 rtx x = *px;
5217
5218 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5219 {
5220 x = get_pool_constant (x);
5221 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5222 }
5223
5224 if (GET_CODE (x) == SYMBOL_REF
5225 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5226 {
5227 cfun->machine->some_ld_name = XSTR (x, 0);
5228 return 1;
5229 }
5230
5231 return 0;
5232 }
5233
5234 /* Locate some local-dynamic symbol still in use by this function
5235 so that we can print its name in local-dynamic base patterns. */
5236
5237 static const char *
5238 get_some_local_dynamic_name (void)
5239 {
5240 rtx insn;
5241
5242 if (cfun->machine->some_ld_name)
5243 return cfun->machine->some_ld_name;
5244
5245 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5246 if (INSN_P (insn)
5247 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5248 return cfun->machine->some_ld_name;
5249
5250 gcc_unreachable ();
5251 }
5252
5253 /* Output machine-dependent UNSPECs occurring in address constant X
5254 in assembler syntax to stdio stream FILE. Returns true if the
5255 constant X could be recognized, false otherwise. */
5256
5257 static bool
5258 s390_output_addr_const_extra (FILE *file, rtx x)
5259 {
5260 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5261 switch (XINT (x, 1))
5262 {
5263 case UNSPEC_GOTENT:
5264 output_addr_const (file, XVECEXP (x, 0, 0));
5265 fprintf (file, "@GOTENT");
5266 return true;
5267 case UNSPEC_GOT:
5268 output_addr_const (file, XVECEXP (x, 0, 0));
5269 fprintf (file, "@GOT");
5270 return true;
5271 case UNSPEC_GOTOFF:
5272 output_addr_const (file, XVECEXP (x, 0, 0));
5273 fprintf (file, "@GOTOFF");
5274 return true;
5275 case UNSPEC_PLT:
5276 output_addr_const (file, XVECEXP (x, 0, 0));
5277 fprintf (file, "@PLT");
5278 return true;
5279 case UNSPEC_PLTOFF:
5280 output_addr_const (file, XVECEXP (x, 0, 0));
5281 fprintf (file, "@PLTOFF");
5282 return true;
5283 case UNSPEC_TLSGD:
5284 output_addr_const (file, XVECEXP (x, 0, 0));
5285 fprintf (file, "@TLSGD");
5286 return true;
5287 case UNSPEC_TLSLDM:
5288 assemble_name (file, get_some_local_dynamic_name ());
5289 fprintf (file, "@TLSLDM");
5290 return true;
5291 case UNSPEC_DTPOFF:
5292 output_addr_const (file, XVECEXP (x, 0, 0));
5293 fprintf (file, "@DTPOFF");
5294 return true;
5295 case UNSPEC_NTPOFF:
5296 output_addr_const (file, XVECEXP (x, 0, 0));
5297 fprintf (file, "@NTPOFF");
5298 return true;
5299 case UNSPEC_GOTNTPOFF:
5300 output_addr_const (file, XVECEXP (x, 0, 0));
5301 fprintf (file, "@GOTNTPOFF");
5302 return true;
5303 case UNSPEC_INDNTPOFF:
5304 output_addr_const (file, XVECEXP (x, 0, 0));
5305 fprintf (file, "@INDNTPOFF");
5306 return true;
5307 }
5308
5309 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5310 switch (XINT (x, 1))
5311 {
5312 case UNSPEC_POOL_OFFSET:
5313 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5314 output_addr_const (file, x);
5315 return true;
5316 }
5317 return false;
5318 }
5319
5320 /* Output address operand ADDR in assembler syntax to
5321 stdio stream FILE. */
5322
5323 void
5324 print_operand_address (FILE *file, rtx addr)
5325 {
5326 struct s390_address ad;
5327
5328 if (s390_loadrelative_operand_p (addr))
5329 {
5330 if (!TARGET_Z10)
5331 {
5332 output_operand_lossage ("symbolic memory references are "
5333 "only supported on z10 or later");
5334 return;
5335 }
5336 output_addr_const (file, addr);
5337 return;
5338 }
5339
5340 if (!s390_decompose_address (addr, &ad)
5341 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5342 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5343 output_operand_lossage ("cannot decompose address");
5344
5345 if (ad.disp)
5346 output_addr_const (file, ad.disp);
5347 else
5348 fprintf (file, "0");
5349
5350 if (ad.base && ad.indx)
5351 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5352 reg_names[REGNO (ad.base)]);
5353 else if (ad.base)
5354 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5355 }
5356
5357 /* Output operand X in assembler syntax to stdio stream FILE.
5358 CODE specified the format flag. The following format flags
5359 are recognized:
5360
5361 'C': print opcode suffix for branch condition.
5362 'D': print opcode suffix for inverse branch condition.
5363 'E': print opcode suffix for branch on index instruction.
5364 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5365 'G': print the size of the operand in bytes.
5366 'O': print only the displacement of a memory reference.
5367 'R': print only the base register of a memory reference.
5368 'S': print S-type memory reference (base+displacement).
5369 'N': print the second word of a DImode operand.
5370 'M': print the second word of a TImode operand.
5371 'Y': print shift count operand.
5372
5373 'b': print integer X as if it's an unsigned byte.
5374 'c': print integer X as if it's an signed byte.
5375 'x': print integer X as if it's an unsigned halfword.
5376 'h': print integer X as if it's a signed halfword.
5377 'i': print the first nonzero HImode part of X.
5378 'j': print the first HImode part unequal to -1 of X.
5379 'k': print the first nonzero SImode part of X.
5380 'm': print the first SImode part unequal to -1 of X.
5381 'o': print integer X as if it's an unsigned 32bit word. */
5382
5383 void
5384 print_operand (FILE *file, rtx x, int code)
5385 {
5386 switch (code)
5387 {
5388 case 'C':
5389 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5390 return;
5391
5392 case 'D':
5393 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5394 return;
5395
5396 case 'E':
5397 if (GET_CODE (x) == LE)
5398 fprintf (file, "l");
5399 else if (GET_CODE (x) == GT)
5400 fprintf (file, "h");
5401 else
5402 output_operand_lossage ("invalid comparison operator "
5403 "for 'E' output modifier");
5404 return;
5405
5406 case 'J':
5407 if (GET_CODE (x) == SYMBOL_REF)
5408 {
5409 fprintf (file, "%s", ":tls_load:");
5410 output_addr_const (file, x);
5411 }
5412 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5413 {
5414 fprintf (file, "%s", ":tls_gdcall:");
5415 output_addr_const (file, XVECEXP (x, 0, 0));
5416 }
5417 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5418 {
5419 fprintf (file, "%s", ":tls_ldcall:");
5420 assemble_name (file, get_some_local_dynamic_name ());
5421 }
5422 else
5423 output_operand_lossage ("invalid reference for 'J' output modifier");
5424 return;
5425
5426 case 'G':
5427 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5428 return;
5429
5430 case 'O':
5431 {
5432 struct s390_address ad;
5433 int ret;
5434
5435 if (!MEM_P (x))
5436 {
5437 output_operand_lossage ("memory reference expected for "
5438 "'O' output modifier");
5439 return;
5440 }
5441
5442 ret = s390_decompose_address (XEXP (x, 0), &ad);
5443
5444 if (!ret
5445 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5446 || ad.indx)
5447 {
5448 output_operand_lossage ("invalid address for 'O' output modifier");
5449 return;
5450 }
5451
5452 if (ad.disp)
5453 output_addr_const (file, ad.disp);
5454 else
5455 fprintf (file, "0");
5456 }
5457 return;
5458
5459 case 'R':
5460 {
5461 struct s390_address ad;
5462 int ret;
5463
5464 if (!MEM_P (x))
5465 {
5466 output_operand_lossage ("memory reference expected for "
5467 "'R' output modifier");
5468 return;
5469 }
5470
5471 ret = s390_decompose_address (XEXP (x, 0), &ad);
5472
5473 if (!ret
5474 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5475 || ad.indx)
5476 {
5477 output_operand_lossage ("invalid address for 'R' output modifier");
5478 return;
5479 }
5480
5481 if (ad.base)
5482 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5483 else
5484 fprintf (file, "0");
5485 }
5486 return;
5487
5488 case 'S':
5489 {
5490 struct s390_address ad;
5491 int ret;
5492
5493 if (!MEM_P (x))
5494 {
5495 output_operand_lossage ("memory reference expected for "
5496 "'S' output modifier");
5497 return;
5498 }
5499 ret = s390_decompose_address (XEXP (x, 0), &ad);
5500
5501 if (!ret
5502 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5503 || ad.indx)
5504 {
5505 output_operand_lossage ("invalid address for 'S' output modifier");
5506 return;
5507 }
5508
5509 if (ad.disp)
5510 output_addr_const (file, ad.disp);
5511 else
5512 fprintf (file, "0");
5513
5514 if (ad.base)
5515 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5516 }
5517 return;
5518
5519 case 'N':
5520 if (GET_CODE (x) == REG)
5521 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5522 else if (GET_CODE (x) == MEM)
5523 x = change_address (x, VOIDmode,
5524 plus_constant (Pmode, XEXP (x, 0), 4));
5525 else
5526 output_operand_lossage ("register or memory expression expected "
5527 "for 'N' output modifier");
5528 break;
5529
5530 case 'M':
5531 if (GET_CODE (x) == REG)
5532 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5533 else if (GET_CODE (x) == MEM)
5534 x = change_address (x, VOIDmode,
5535 plus_constant (Pmode, XEXP (x, 0), 8));
5536 else
5537 output_operand_lossage ("register or memory expression expected "
5538 "for 'M' output modifier");
5539 break;
5540
5541 case 'Y':
5542 print_shift_count_operand (file, x);
5543 return;
5544 }
5545
5546 switch (GET_CODE (x))
5547 {
5548 case REG:
5549 fprintf (file, "%s", reg_names[REGNO (x)]);
5550 break;
5551
5552 case MEM:
5553 output_address (XEXP (x, 0));
5554 break;
5555
5556 case CONST:
5557 case CODE_LABEL:
5558 case LABEL_REF:
5559 case SYMBOL_REF:
5560 output_addr_const (file, x);
5561 break;
5562
5563 case CONST_INT:
5564 if (code == 'b')
5565 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5566 else if (code == 'c')
5567 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5568 else if (code == 'x')
5569 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5570 else if (code == 'h')
5571 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5572 else if (code == 'i')
5573 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5574 s390_extract_part (x, HImode, 0));
5575 else if (code == 'j')
5576 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5577 s390_extract_part (x, HImode, -1));
5578 else if (code == 'k')
5579 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5580 s390_extract_part (x, SImode, 0));
5581 else if (code == 'm')
5582 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5583 s390_extract_part (x, SImode, -1));
5584 else if (code == 'o')
5585 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5586 else
5587 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5588 break;
5589
5590 case CONST_DOUBLE:
5591 gcc_assert (GET_MODE (x) == VOIDmode);
5592 if (code == 'b')
5593 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5594 else if (code == 'x')
5595 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5596 else if (code == 'h')
5597 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5598 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5599 else
5600 {
5601 if (code == 0)
5602 output_operand_lossage ("invalid constant - try using "
5603 "an output modifier");
5604 else
5605 output_operand_lossage ("invalid constant for output modifier '%c'",
5606 code);
5607 }
5608 break;
5609
5610 default:
5611 if (code == 0)
5612 output_operand_lossage ("invalid expression - try using "
5613 "an output modifier");
5614 else
5615 output_operand_lossage ("invalid expression for output "
5616 "modifier '%c'", code);
5617 break;
5618 }
5619 }
5620
5621 /* Target hook for assembling integer objects. We need to define it
5622 here to work a round a bug in some versions of GAS, which couldn't
5623 handle values smaller than INT_MIN when printed in decimal. */
5624
5625 static bool
5626 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5627 {
5628 if (size == 8 && aligned_p
5629 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5630 {
5631 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5632 INTVAL (x));
5633 return true;
5634 }
5635 return default_assemble_integer (x, size, aligned_p);
5636 }
5637
5638 /* Returns true if register REGNO is used for forming
5639 a memory address in expression X. */
5640
5641 static bool
5642 reg_used_in_mem_p (int regno, rtx x)
5643 {
5644 enum rtx_code code = GET_CODE (x);
5645 int i, j;
5646 const char *fmt;
5647
5648 if (code == MEM)
5649 {
5650 if (refers_to_regno_p (regno, regno+1,
5651 XEXP (x, 0), 0))
5652 return true;
5653 }
5654 else if (code == SET
5655 && GET_CODE (SET_DEST (x)) == PC)
5656 {
5657 if (refers_to_regno_p (regno, regno+1,
5658 SET_SRC (x), 0))
5659 return true;
5660 }
5661
5662 fmt = GET_RTX_FORMAT (code);
5663 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5664 {
5665 if (fmt[i] == 'e'
5666 && reg_used_in_mem_p (regno, XEXP (x, i)))
5667 return true;
5668
5669 else if (fmt[i] == 'E')
5670 for (j = 0; j < XVECLEN (x, i); j++)
5671 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5672 return true;
5673 }
5674 return false;
5675 }
5676
5677 /* Returns true if expression DEP_RTX sets an address register
5678 used by instruction INSN to address memory. */
5679
5680 static bool
5681 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5682 {
5683 rtx target, pat;
5684
5685 if (GET_CODE (dep_rtx) == INSN)
5686 dep_rtx = PATTERN (dep_rtx);
5687
5688 if (GET_CODE (dep_rtx) == SET)
5689 {
5690 target = SET_DEST (dep_rtx);
5691 if (GET_CODE (target) == STRICT_LOW_PART)
5692 target = XEXP (target, 0);
5693 while (GET_CODE (target) == SUBREG)
5694 target = SUBREG_REG (target);
5695
5696 if (GET_CODE (target) == REG)
5697 {
5698 int regno = REGNO (target);
5699
5700 if (s390_safe_attr_type (insn) == TYPE_LA)
5701 {
5702 pat = PATTERN (insn);
5703 if (GET_CODE (pat) == PARALLEL)
5704 {
5705 gcc_assert (XVECLEN (pat, 0) == 2);
5706 pat = XVECEXP (pat, 0, 0);
5707 }
5708 gcc_assert (GET_CODE (pat) == SET);
5709 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5710 }
5711 else if (get_attr_atype (insn) == ATYPE_AGEN)
5712 return reg_used_in_mem_p (regno, PATTERN (insn));
5713 }
5714 }
5715 return false;
5716 }
5717
5718 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5719
5720 int
5721 s390_agen_dep_p (rtx dep_insn, rtx insn)
5722 {
5723 rtx dep_rtx = PATTERN (dep_insn);
5724 int i;
5725
5726 if (GET_CODE (dep_rtx) == SET
5727 && addr_generation_dependency_p (dep_rtx, insn))
5728 return 1;
5729 else if (GET_CODE (dep_rtx) == PARALLEL)
5730 {
5731 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5732 {
5733 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5734 return 1;
5735 }
5736 }
5737 return 0;
5738 }
5739
5740
5741 /* A C statement (sans semicolon) to update the integer scheduling priority
5742 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5743 reduce the priority to execute INSN later. Do not define this macro if
5744 you do not need to adjust the scheduling priorities of insns.
5745
5746 A STD instruction should be scheduled earlier,
5747 in order to use the bypass. */
5748 static int
5749 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5750 {
5751 if (! INSN_P (insn))
5752 return priority;
5753
5754 if (s390_tune != PROCESSOR_2084_Z990
5755 && s390_tune != PROCESSOR_2094_Z9_109
5756 && s390_tune != PROCESSOR_2097_Z10
5757 && s390_tune != PROCESSOR_2817_Z196
5758 && s390_tune != PROCESSOR_2827_ZEC12)
5759 return priority;
5760
5761 switch (s390_safe_attr_type (insn))
5762 {
5763 case TYPE_FSTOREDF:
5764 case TYPE_FSTORESF:
5765 priority = priority << 3;
5766 break;
5767 case TYPE_STORE:
5768 case TYPE_STM:
5769 priority = priority << 1;
5770 break;
5771 default:
5772 break;
5773 }
5774 return priority;
5775 }
5776
5777
5778 /* The number of instructions that can be issued per cycle. */
5779
5780 static int
5781 s390_issue_rate (void)
5782 {
5783 switch (s390_tune)
5784 {
5785 case PROCESSOR_2084_Z990:
5786 case PROCESSOR_2094_Z9_109:
5787 case PROCESSOR_2817_Z196:
5788 return 3;
5789 case PROCESSOR_2097_Z10:
5790 case PROCESSOR_2827_ZEC12:
5791 return 2;
5792 default:
5793 return 1;
5794 }
5795 }
5796
5797 static int
5798 s390_first_cycle_multipass_dfa_lookahead (void)
5799 {
5800 return 4;
5801 }
5802
5803 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5804 Fix up MEMs as required. */
5805
5806 static void
5807 annotate_constant_pool_refs (rtx *x)
5808 {
5809 int i, j;
5810 const char *fmt;
5811
5812 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5813 || !CONSTANT_POOL_ADDRESS_P (*x));
5814
5815 /* Literal pool references can only occur inside a MEM ... */
5816 if (GET_CODE (*x) == MEM)
5817 {
5818 rtx memref = XEXP (*x, 0);
5819
5820 if (GET_CODE (memref) == SYMBOL_REF
5821 && CONSTANT_POOL_ADDRESS_P (memref))
5822 {
5823 rtx base = cfun->machine->base_reg;
5824 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5825 UNSPEC_LTREF);
5826
5827 *x = replace_equiv_address (*x, addr);
5828 return;
5829 }
5830
5831 if (GET_CODE (memref) == CONST
5832 && GET_CODE (XEXP (memref, 0)) == PLUS
5833 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5834 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5835 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5836 {
5837 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5838 rtx sym = XEXP (XEXP (memref, 0), 0);
5839 rtx base = cfun->machine->base_reg;
5840 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5841 UNSPEC_LTREF);
5842
5843 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5844 return;
5845 }
5846 }
5847
5848 /* ... or a load-address type pattern. */
5849 if (GET_CODE (*x) == SET)
5850 {
5851 rtx addrref = SET_SRC (*x);
5852
5853 if (GET_CODE (addrref) == SYMBOL_REF
5854 && CONSTANT_POOL_ADDRESS_P (addrref))
5855 {
5856 rtx base = cfun->machine->base_reg;
5857 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5858 UNSPEC_LTREF);
5859
5860 SET_SRC (*x) = addr;
5861 return;
5862 }
5863
5864 if (GET_CODE (addrref) == CONST
5865 && GET_CODE (XEXP (addrref, 0)) == PLUS
5866 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5867 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5868 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5869 {
5870 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5871 rtx sym = XEXP (XEXP (addrref, 0), 0);
5872 rtx base = cfun->machine->base_reg;
5873 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5874 UNSPEC_LTREF);
5875
5876 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5877 return;
5878 }
5879 }
5880
5881 /* Annotate LTREL_BASE as well. */
5882 if (GET_CODE (*x) == UNSPEC
5883 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5884 {
5885 rtx base = cfun->machine->base_reg;
5886 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5887 UNSPEC_LTREL_BASE);
5888 return;
5889 }
5890
5891 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5892 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5893 {
5894 if (fmt[i] == 'e')
5895 {
5896 annotate_constant_pool_refs (&XEXP (*x, i));
5897 }
5898 else if (fmt[i] == 'E')
5899 {
5900 for (j = 0; j < XVECLEN (*x, i); j++)
5901 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5902 }
5903 }
5904 }
5905
5906 /* Split all branches that exceed the maximum distance.
5907 Returns true if this created a new literal pool entry. */
5908
5909 static int
5910 s390_split_branches (void)
5911 {
5912 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5913 int new_literal = 0, ret;
5914 rtx insn, pat, tmp, target;
5915 rtx *label;
5916
5917 /* We need correct insn addresses. */
5918
5919 shorten_branches (get_insns ());
5920
5921 /* Find all branches that exceed 64KB, and split them. */
5922
5923 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5924 {
5925 if (GET_CODE (insn) != JUMP_INSN)
5926 continue;
5927
5928 pat = PATTERN (insn);
5929 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5930 pat = XVECEXP (pat, 0, 0);
5931 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5932 continue;
5933
5934 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5935 {
5936 label = &SET_SRC (pat);
5937 }
5938 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5939 {
5940 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5941 label = &XEXP (SET_SRC (pat), 1);
5942 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5943 label = &XEXP (SET_SRC (pat), 2);
5944 else
5945 continue;
5946 }
5947 else
5948 continue;
5949
5950 if (get_attr_length (insn) <= 4)
5951 continue;
5952
5953 /* We are going to use the return register as scratch register,
5954 make sure it will be saved/restored by the prologue/epilogue. */
5955 cfun_frame_layout.save_return_addr_p = 1;
5956
5957 if (!flag_pic)
5958 {
5959 new_literal = 1;
5960 tmp = force_const_mem (Pmode, *label);
5961 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5962 INSN_ADDRESSES_NEW (tmp, -1);
5963 annotate_constant_pool_refs (&PATTERN (tmp));
5964
5965 target = temp_reg;
5966 }
5967 else
5968 {
5969 new_literal = 1;
5970 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5971 UNSPEC_LTREL_OFFSET);
5972 target = gen_rtx_CONST (Pmode, target);
5973 target = force_const_mem (Pmode, target);
5974 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5975 INSN_ADDRESSES_NEW (tmp, -1);
5976 annotate_constant_pool_refs (&PATTERN (tmp));
5977
5978 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5979 cfun->machine->base_reg),
5980 UNSPEC_LTREL_BASE);
5981 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5982 }
5983
5984 ret = validate_change (insn, label, target, 0);
5985 gcc_assert (ret);
5986 }
5987
5988 return new_literal;
5989 }
5990
5991
5992 /* Find an annotated literal pool symbol referenced in RTX X,
5993 and store it at REF. Will abort if X contains references to
5994 more than one such pool symbol; multiple references to the same
5995 symbol are allowed, however.
5996
5997 The rtx pointed to by REF must be initialized to NULL_RTX
5998 by the caller before calling this routine. */
5999
6000 static void
6001 find_constant_pool_ref (rtx x, rtx *ref)
6002 {
6003 int i, j;
6004 const char *fmt;
6005
6006 /* Ignore LTREL_BASE references. */
6007 if (GET_CODE (x) == UNSPEC
6008 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6009 return;
6010 /* Likewise POOL_ENTRY insns. */
6011 if (GET_CODE (x) == UNSPEC_VOLATILE
6012 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6013 return;
6014
6015 gcc_assert (GET_CODE (x) != SYMBOL_REF
6016 || !CONSTANT_POOL_ADDRESS_P (x));
6017
6018 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
6019 {
6020 rtx sym = XVECEXP (x, 0, 0);
6021 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6022 && CONSTANT_POOL_ADDRESS_P (sym));
6023
6024 if (*ref == NULL_RTX)
6025 *ref = sym;
6026 else
6027 gcc_assert (*ref == sym);
6028
6029 return;
6030 }
6031
6032 fmt = GET_RTX_FORMAT (GET_CODE (x));
6033 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6034 {
6035 if (fmt[i] == 'e')
6036 {
6037 find_constant_pool_ref (XEXP (x, i), ref);
6038 }
6039 else if (fmt[i] == 'E')
6040 {
6041 for (j = 0; j < XVECLEN (x, i); j++)
6042 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6043 }
6044 }
6045 }
6046
6047 /* Replace every reference to the annotated literal pool
6048 symbol REF in X by its base plus OFFSET. */
6049
6050 static void
6051 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
6052 {
6053 int i, j;
6054 const char *fmt;
6055
6056 gcc_assert (*x != ref);
6057
6058 if (GET_CODE (*x) == UNSPEC
6059 && XINT (*x, 1) == UNSPEC_LTREF
6060 && XVECEXP (*x, 0, 0) == ref)
6061 {
6062 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6063 return;
6064 }
6065
6066 if (GET_CODE (*x) == PLUS
6067 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6068 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6069 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6070 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
6071 {
6072 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
6073 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
6074 return;
6075 }
6076
6077 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6078 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6079 {
6080 if (fmt[i] == 'e')
6081 {
6082 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
6083 }
6084 else if (fmt[i] == 'E')
6085 {
6086 for (j = 0; j < XVECLEN (*x, i); j++)
6087 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
6088 }
6089 }
6090 }
6091
6092 /* Check whether X contains an UNSPEC_LTREL_BASE.
6093 Return its constant pool symbol if found, NULL_RTX otherwise. */
6094
6095 static rtx
6096 find_ltrel_base (rtx x)
6097 {
6098 int i, j;
6099 const char *fmt;
6100
6101 if (GET_CODE (x) == UNSPEC
6102 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6103 return XVECEXP (x, 0, 0);
6104
6105 fmt = GET_RTX_FORMAT (GET_CODE (x));
6106 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6107 {
6108 if (fmt[i] == 'e')
6109 {
6110 rtx fnd = find_ltrel_base (XEXP (x, i));
6111 if (fnd)
6112 return fnd;
6113 }
6114 else if (fmt[i] == 'E')
6115 {
6116 for (j = 0; j < XVECLEN (x, i); j++)
6117 {
6118 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6119 if (fnd)
6120 return fnd;
6121 }
6122 }
6123 }
6124
6125 return NULL_RTX;
6126 }
6127
6128 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6129
6130 static void
6131 replace_ltrel_base (rtx *x)
6132 {
6133 int i, j;
6134 const char *fmt;
6135
6136 if (GET_CODE (*x) == UNSPEC
6137 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6138 {
6139 *x = XVECEXP (*x, 0, 1);
6140 return;
6141 }
6142
6143 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6144 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6145 {
6146 if (fmt[i] == 'e')
6147 {
6148 replace_ltrel_base (&XEXP (*x, i));
6149 }
6150 else if (fmt[i] == 'E')
6151 {
6152 for (j = 0; j < XVECLEN (*x, i); j++)
6153 replace_ltrel_base (&XVECEXP (*x, i, j));
6154 }
6155 }
6156 }
6157
6158
6159 /* We keep a list of constants which we have to add to internal
6160 constant tables in the middle of large functions. */
6161
6162 #define NR_C_MODES 11
6163 enum machine_mode constant_modes[NR_C_MODES] =
6164 {
6165 TFmode, TImode, TDmode,
6166 DFmode, DImode, DDmode,
6167 SFmode, SImode, SDmode,
6168 HImode,
6169 QImode
6170 };
6171
6172 struct constant
6173 {
6174 struct constant *next;
6175 rtx value;
6176 rtx label;
6177 };
6178
6179 struct constant_pool
6180 {
6181 struct constant_pool *next;
6182 rtx first_insn;
6183 rtx pool_insn;
6184 bitmap insns;
6185 rtx emit_pool_after;
6186
6187 struct constant *constants[NR_C_MODES];
6188 struct constant *execute;
6189 rtx label;
6190 int size;
6191 };
6192
6193 /* Allocate new constant_pool structure. */
6194
6195 static struct constant_pool *
6196 s390_alloc_pool (void)
6197 {
6198 struct constant_pool *pool;
6199 int i;
6200
6201 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6202 pool->next = NULL;
6203 for (i = 0; i < NR_C_MODES; i++)
6204 pool->constants[i] = NULL;
6205
6206 pool->execute = NULL;
6207 pool->label = gen_label_rtx ();
6208 pool->first_insn = NULL_RTX;
6209 pool->pool_insn = NULL_RTX;
6210 pool->insns = BITMAP_ALLOC (NULL);
6211 pool->size = 0;
6212 pool->emit_pool_after = NULL_RTX;
6213
6214 return pool;
6215 }
6216
6217 /* Create new constant pool covering instructions starting at INSN
6218 and chain it to the end of POOL_LIST. */
6219
6220 static struct constant_pool *
6221 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6222 {
6223 struct constant_pool *pool, **prev;
6224
6225 pool = s390_alloc_pool ();
6226 pool->first_insn = insn;
6227
6228 for (prev = pool_list; *prev; prev = &(*prev)->next)
6229 ;
6230 *prev = pool;
6231
6232 return pool;
6233 }
6234
6235 /* End range of instructions covered by POOL at INSN and emit
6236 placeholder insn representing the pool. */
6237
6238 static void
6239 s390_end_pool (struct constant_pool *pool, rtx insn)
6240 {
6241 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6242
6243 if (!insn)
6244 insn = get_last_insn ();
6245
6246 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6247 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6248 }
6249
6250 /* Add INSN to the list of insns covered by POOL. */
6251
6252 static void
6253 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6254 {
6255 bitmap_set_bit (pool->insns, INSN_UID (insn));
6256 }
6257
6258 /* Return pool out of POOL_LIST that covers INSN. */
6259
6260 static struct constant_pool *
6261 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6262 {
6263 struct constant_pool *pool;
6264
6265 for (pool = pool_list; pool; pool = pool->next)
6266 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6267 break;
6268
6269 return pool;
6270 }
6271
6272 /* Add constant VAL of mode MODE to the constant pool POOL. */
6273
6274 static void
6275 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6276 {
6277 struct constant *c;
6278 int i;
6279
6280 for (i = 0; i < NR_C_MODES; i++)
6281 if (constant_modes[i] == mode)
6282 break;
6283 gcc_assert (i != NR_C_MODES);
6284
6285 for (c = pool->constants[i]; c != NULL; c = c->next)
6286 if (rtx_equal_p (val, c->value))
6287 break;
6288
6289 if (c == NULL)
6290 {
6291 c = (struct constant *) xmalloc (sizeof *c);
6292 c->value = val;
6293 c->label = gen_label_rtx ();
6294 c->next = pool->constants[i];
6295 pool->constants[i] = c;
6296 pool->size += GET_MODE_SIZE (mode);
6297 }
6298 }
6299
6300 /* Return an rtx that represents the offset of X from the start of
6301 pool POOL. */
6302
6303 static rtx
6304 s390_pool_offset (struct constant_pool *pool, rtx x)
6305 {
6306 rtx label;
6307
6308 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6309 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6310 UNSPEC_POOL_OFFSET);
6311 return gen_rtx_CONST (GET_MODE (x), x);
6312 }
6313
6314 /* Find constant VAL of mode MODE in the constant pool POOL.
6315 Return an RTX describing the distance from the start of
6316 the pool to the location of the new constant. */
6317
6318 static rtx
6319 s390_find_constant (struct constant_pool *pool, rtx val,
6320 enum machine_mode mode)
6321 {
6322 struct constant *c;
6323 int i;
6324
6325 for (i = 0; i < NR_C_MODES; i++)
6326 if (constant_modes[i] == mode)
6327 break;
6328 gcc_assert (i != NR_C_MODES);
6329
6330 for (c = pool->constants[i]; c != NULL; c = c->next)
6331 if (rtx_equal_p (val, c->value))
6332 break;
6333
6334 gcc_assert (c);
6335
6336 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6337 }
6338
6339 /* Check whether INSN is an execute. Return the label_ref to its
6340 execute target template if so, NULL_RTX otherwise. */
6341
6342 static rtx
6343 s390_execute_label (rtx insn)
6344 {
6345 if (GET_CODE (insn) == INSN
6346 && GET_CODE (PATTERN (insn)) == PARALLEL
6347 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6348 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6349 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6350
6351 return NULL_RTX;
6352 }
6353
6354 /* Add execute target for INSN to the constant pool POOL. */
6355
6356 static void
6357 s390_add_execute (struct constant_pool *pool, rtx insn)
6358 {
6359 struct constant *c;
6360
6361 for (c = pool->execute; c != NULL; c = c->next)
6362 if (INSN_UID (insn) == INSN_UID (c->value))
6363 break;
6364
6365 if (c == NULL)
6366 {
6367 c = (struct constant *) xmalloc (sizeof *c);
6368 c->value = insn;
6369 c->label = gen_label_rtx ();
6370 c->next = pool->execute;
6371 pool->execute = c;
6372 pool->size += 6;
6373 }
6374 }
6375
6376 /* Find execute target for INSN in the constant pool POOL.
6377 Return an RTX describing the distance from the start of
6378 the pool to the location of the execute target. */
6379
6380 static rtx
6381 s390_find_execute (struct constant_pool *pool, rtx insn)
6382 {
6383 struct constant *c;
6384
6385 for (c = pool->execute; c != NULL; c = c->next)
6386 if (INSN_UID (insn) == INSN_UID (c->value))
6387 break;
6388
6389 gcc_assert (c);
6390
6391 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6392 }
6393
6394 /* For an execute INSN, extract the execute target template. */
6395
6396 static rtx
6397 s390_execute_target (rtx insn)
6398 {
6399 rtx pattern = PATTERN (insn);
6400 gcc_assert (s390_execute_label (insn));
6401
6402 if (XVECLEN (pattern, 0) == 2)
6403 {
6404 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6405 }
6406 else
6407 {
6408 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6409 int i;
6410
6411 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6412 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6413
6414 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6415 }
6416
6417 return pattern;
6418 }
6419
6420 /* Indicate that INSN cannot be duplicated. This is the case for
6421 execute insns that carry a unique label. */
6422
6423 static bool
6424 s390_cannot_copy_insn_p (rtx insn)
6425 {
6426 rtx label = s390_execute_label (insn);
6427 return label && label != const0_rtx;
6428 }
6429
6430 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6431 do not emit the pool base label. */
6432
6433 static void
6434 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6435 {
6436 struct constant *c;
6437 rtx insn = pool->pool_insn;
6438 int i;
6439
6440 /* Switch to rodata section. */
6441 if (TARGET_CPU_ZARCH)
6442 {
6443 insn = emit_insn_after (gen_pool_section_start (), insn);
6444 INSN_ADDRESSES_NEW (insn, -1);
6445 }
6446
6447 /* Ensure minimum pool alignment. */
6448 if (TARGET_CPU_ZARCH)
6449 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6450 else
6451 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6452 INSN_ADDRESSES_NEW (insn, -1);
6453
6454 /* Emit pool base label. */
6455 if (!remote_label)
6456 {
6457 insn = emit_label_after (pool->label, insn);
6458 INSN_ADDRESSES_NEW (insn, -1);
6459 }
6460
6461 /* Dump constants in descending alignment requirement order,
6462 ensuring proper alignment for every constant. */
6463 for (i = 0; i < NR_C_MODES; i++)
6464 for (c = pool->constants[i]; c; c = c->next)
6465 {
6466 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6467 rtx value = copy_rtx (c->value);
6468 if (GET_CODE (value) == CONST
6469 && GET_CODE (XEXP (value, 0)) == UNSPEC
6470 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6471 && XVECLEN (XEXP (value, 0), 0) == 1)
6472 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6473
6474 insn = emit_label_after (c->label, insn);
6475 INSN_ADDRESSES_NEW (insn, -1);
6476
6477 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6478 gen_rtvec (1, value),
6479 UNSPECV_POOL_ENTRY);
6480 insn = emit_insn_after (value, insn);
6481 INSN_ADDRESSES_NEW (insn, -1);
6482 }
6483
6484 /* Ensure minimum alignment for instructions. */
6485 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6486 INSN_ADDRESSES_NEW (insn, -1);
6487
6488 /* Output in-pool execute template insns. */
6489 for (c = pool->execute; c; c = c->next)
6490 {
6491 insn = emit_label_after (c->label, insn);
6492 INSN_ADDRESSES_NEW (insn, -1);
6493
6494 insn = emit_insn_after (s390_execute_target (c->value), insn);
6495 INSN_ADDRESSES_NEW (insn, -1);
6496 }
6497
6498 /* Switch back to previous section. */
6499 if (TARGET_CPU_ZARCH)
6500 {
6501 insn = emit_insn_after (gen_pool_section_end (), insn);
6502 INSN_ADDRESSES_NEW (insn, -1);
6503 }
6504
6505 insn = emit_barrier_after (insn);
6506 INSN_ADDRESSES_NEW (insn, -1);
6507
6508 /* Remove placeholder insn. */
6509 remove_insn (pool->pool_insn);
6510 }
6511
6512 /* Free all memory used by POOL. */
6513
6514 static void
6515 s390_free_pool (struct constant_pool *pool)
6516 {
6517 struct constant *c, *next;
6518 int i;
6519
6520 for (i = 0; i < NR_C_MODES; i++)
6521 for (c = pool->constants[i]; c; c = next)
6522 {
6523 next = c->next;
6524 free (c);
6525 }
6526
6527 for (c = pool->execute; c; c = next)
6528 {
6529 next = c->next;
6530 free (c);
6531 }
6532
6533 BITMAP_FREE (pool->insns);
6534 free (pool);
6535 }
6536
6537
6538 /* Collect main literal pool. Return NULL on overflow. */
6539
6540 static struct constant_pool *
6541 s390_mainpool_start (void)
6542 {
6543 struct constant_pool *pool;
6544 rtx insn;
6545
6546 pool = s390_alloc_pool ();
6547
6548 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6549 {
6550 if (GET_CODE (insn) == INSN
6551 && GET_CODE (PATTERN (insn)) == SET
6552 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6553 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6554 {
6555 gcc_assert (!pool->pool_insn);
6556 pool->pool_insn = insn;
6557 }
6558
6559 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6560 {
6561 s390_add_execute (pool, insn);
6562 }
6563 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6564 {
6565 rtx pool_ref = NULL_RTX;
6566 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6567 if (pool_ref)
6568 {
6569 rtx constant = get_pool_constant (pool_ref);
6570 enum machine_mode mode = get_pool_mode (pool_ref);
6571 s390_add_constant (pool, constant, mode);
6572 }
6573 }
6574
6575 /* If hot/cold partitioning is enabled we have to make sure that
6576 the literal pool is emitted in the same section where the
6577 initialization of the literal pool base pointer takes place.
6578 emit_pool_after is only used in the non-overflow case on non
6579 Z cpus where we can emit the literal pool at the end of the
6580 function body within the text section. */
6581 if (NOTE_P (insn)
6582 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6583 && !pool->emit_pool_after)
6584 pool->emit_pool_after = PREV_INSN (insn);
6585 }
6586
6587 gcc_assert (pool->pool_insn || pool->size == 0);
6588
6589 if (pool->size >= 4096)
6590 {
6591 /* We're going to chunkify the pool, so remove the main
6592 pool placeholder insn. */
6593 remove_insn (pool->pool_insn);
6594
6595 s390_free_pool (pool);
6596 pool = NULL;
6597 }
6598
6599 /* If the functions ends with the section where the literal pool
6600 should be emitted set the marker to its end. */
6601 if (pool && !pool->emit_pool_after)
6602 pool->emit_pool_after = get_last_insn ();
6603
6604 return pool;
6605 }
6606
6607 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6608 Modify the current function to output the pool constants as well as
6609 the pool register setup instruction. */
6610
6611 static void
6612 s390_mainpool_finish (struct constant_pool *pool)
6613 {
6614 rtx base_reg = cfun->machine->base_reg;
6615 rtx insn;
6616
6617 /* If the pool is empty, we're done. */
6618 if (pool->size == 0)
6619 {
6620 /* We don't actually need a base register after all. */
6621 cfun->machine->base_reg = NULL_RTX;
6622
6623 if (pool->pool_insn)
6624 remove_insn (pool->pool_insn);
6625 s390_free_pool (pool);
6626 return;
6627 }
6628
6629 /* We need correct insn addresses. */
6630 shorten_branches (get_insns ());
6631
6632 /* On zSeries, we use a LARL to load the pool register. The pool is
6633 located in the .rodata section, so we emit it after the function. */
6634 if (TARGET_CPU_ZARCH)
6635 {
6636 insn = gen_main_base_64 (base_reg, pool->label);
6637 insn = emit_insn_after (insn, pool->pool_insn);
6638 INSN_ADDRESSES_NEW (insn, -1);
6639 remove_insn (pool->pool_insn);
6640
6641 insn = get_last_insn ();
6642 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6643 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6644
6645 s390_dump_pool (pool, 0);
6646 }
6647
6648 /* On S/390, if the total size of the function's code plus literal pool
6649 does not exceed 4096 bytes, we use BASR to set up a function base
6650 pointer, and emit the literal pool at the end of the function. */
6651 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6652 + pool->size + 8 /* alignment slop */ < 4096)
6653 {
6654 insn = gen_main_base_31_small (base_reg, pool->label);
6655 insn = emit_insn_after (insn, pool->pool_insn);
6656 INSN_ADDRESSES_NEW (insn, -1);
6657 remove_insn (pool->pool_insn);
6658
6659 insn = emit_label_after (pool->label, insn);
6660 INSN_ADDRESSES_NEW (insn, -1);
6661
6662 /* emit_pool_after will be set by s390_mainpool_start to the
6663 last insn of the section where the literal pool should be
6664 emitted. */
6665 insn = pool->emit_pool_after;
6666
6667 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6668 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6669
6670 s390_dump_pool (pool, 1);
6671 }
6672
6673 /* Otherwise, we emit an inline literal pool and use BASR to branch
6674 over it, setting up the pool register at the same time. */
6675 else
6676 {
6677 rtx pool_end = gen_label_rtx ();
6678
6679 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6680 insn = emit_jump_insn_after (insn, pool->pool_insn);
6681 JUMP_LABEL (insn) = pool_end;
6682 INSN_ADDRESSES_NEW (insn, -1);
6683 remove_insn (pool->pool_insn);
6684
6685 insn = emit_label_after (pool->label, insn);
6686 INSN_ADDRESSES_NEW (insn, -1);
6687
6688 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6689 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6690
6691 insn = emit_label_after (pool_end, pool->pool_insn);
6692 INSN_ADDRESSES_NEW (insn, -1);
6693
6694 s390_dump_pool (pool, 1);
6695 }
6696
6697
6698 /* Replace all literal pool references. */
6699
6700 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6701 {
6702 if (INSN_P (insn))
6703 replace_ltrel_base (&PATTERN (insn));
6704
6705 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6706 {
6707 rtx addr, pool_ref = NULL_RTX;
6708 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6709 if (pool_ref)
6710 {
6711 if (s390_execute_label (insn))
6712 addr = s390_find_execute (pool, insn);
6713 else
6714 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6715 get_pool_mode (pool_ref));
6716
6717 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6718 INSN_CODE (insn) = -1;
6719 }
6720 }
6721 }
6722
6723
6724 /* Free the pool. */
6725 s390_free_pool (pool);
6726 }
6727
6728 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6729 We have decided we cannot use this pool, so revert all changes
6730 to the current function that were done by s390_mainpool_start. */
6731 static void
6732 s390_mainpool_cancel (struct constant_pool *pool)
6733 {
6734 /* We didn't actually change the instruction stream, so simply
6735 free the pool memory. */
6736 s390_free_pool (pool);
6737 }
6738
6739
6740 /* Chunkify the literal pool. */
6741
6742 #define S390_POOL_CHUNK_MIN 0xc00
6743 #define S390_POOL_CHUNK_MAX 0xe00
6744
6745 static struct constant_pool *
6746 s390_chunkify_start (void)
6747 {
6748 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6749 int extra_size = 0;
6750 bitmap far_labels;
6751 rtx pending_ltrel = NULL_RTX;
6752 rtx insn;
6753
6754 rtx (*gen_reload_base) (rtx, rtx) =
6755 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6756
6757
6758 /* We need correct insn addresses. */
6759
6760 shorten_branches (get_insns ());
6761
6762 /* Scan all insns and move literals to pool chunks. */
6763
6764 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6765 {
6766 bool section_switch_p = false;
6767
6768 /* Check for pending LTREL_BASE. */
6769 if (INSN_P (insn))
6770 {
6771 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6772 if (ltrel_base)
6773 {
6774 gcc_assert (ltrel_base == pending_ltrel);
6775 pending_ltrel = NULL_RTX;
6776 }
6777 }
6778
6779 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6780 {
6781 if (!curr_pool)
6782 curr_pool = s390_start_pool (&pool_list, insn);
6783
6784 s390_add_execute (curr_pool, insn);
6785 s390_add_pool_insn (curr_pool, insn);
6786 }
6787 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6788 {
6789 rtx pool_ref = NULL_RTX;
6790 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6791 if (pool_ref)
6792 {
6793 rtx constant = get_pool_constant (pool_ref);
6794 enum machine_mode mode = get_pool_mode (pool_ref);
6795
6796 if (!curr_pool)
6797 curr_pool = s390_start_pool (&pool_list, insn);
6798
6799 s390_add_constant (curr_pool, constant, mode);
6800 s390_add_pool_insn (curr_pool, insn);
6801
6802 /* Don't split the pool chunk between a LTREL_OFFSET load
6803 and the corresponding LTREL_BASE. */
6804 if (GET_CODE (constant) == CONST
6805 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6806 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6807 {
6808 gcc_assert (!pending_ltrel);
6809 pending_ltrel = pool_ref;
6810 }
6811 }
6812 }
6813
6814 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6815 {
6816 if (curr_pool)
6817 s390_add_pool_insn (curr_pool, insn);
6818 /* An LTREL_BASE must follow within the same basic block. */
6819 gcc_assert (!pending_ltrel);
6820 }
6821
6822 if (NOTE_P (insn))
6823 switch (NOTE_KIND (insn))
6824 {
6825 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6826 section_switch_p = true;
6827 break;
6828 case NOTE_INSN_VAR_LOCATION:
6829 case NOTE_INSN_CALL_ARG_LOCATION:
6830 continue;
6831 default:
6832 break;
6833 }
6834
6835 if (!curr_pool
6836 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6837 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6838 continue;
6839
6840 if (TARGET_CPU_ZARCH)
6841 {
6842 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6843 continue;
6844
6845 s390_end_pool (curr_pool, NULL_RTX);
6846 curr_pool = NULL;
6847 }
6848 else
6849 {
6850 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6851 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6852 + extra_size;
6853
6854 /* We will later have to insert base register reload insns.
6855 Those will have an effect on code size, which we need to
6856 consider here. This calculation makes rather pessimistic
6857 worst-case assumptions. */
6858 if (GET_CODE (insn) == CODE_LABEL)
6859 extra_size += 6;
6860
6861 if (chunk_size < S390_POOL_CHUNK_MIN
6862 && curr_pool->size < S390_POOL_CHUNK_MIN
6863 && !section_switch_p)
6864 continue;
6865
6866 /* Pool chunks can only be inserted after BARRIERs ... */
6867 if (GET_CODE (insn) == BARRIER)
6868 {
6869 s390_end_pool (curr_pool, insn);
6870 curr_pool = NULL;
6871 extra_size = 0;
6872 }
6873
6874 /* ... so if we don't find one in time, create one. */
6875 else if (chunk_size > S390_POOL_CHUNK_MAX
6876 || curr_pool->size > S390_POOL_CHUNK_MAX
6877 || section_switch_p)
6878 {
6879 rtx label, jump, barrier, next, prev;
6880
6881 if (!section_switch_p)
6882 {
6883 /* We can insert the barrier only after a 'real' insn. */
6884 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6885 continue;
6886 if (get_attr_length (insn) == 0)
6887 continue;
6888 /* Don't separate LTREL_BASE from the corresponding
6889 LTREL_OFFSET load. */
6890 if (pending_ltrel)
6891 continue;
6892 next = insn;
6893 do
6894 {
6895 insn = next;
6896 next = NEXT_INSN (insn);
6897 }
6898 while (next
6899 && NOTE_P (next)
6900 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6901 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6902 }
6903 else
6904 {
6905 gcc_assert (!pending_ltrel);
6906
6907 /* The old pool has to end before the section switch
6908 note in order to make it part of the current
6909 section. */
6910 insn = PREV_INSN (insn);
6911 }
6912
6913 label = gen_label_rtx ();
6914 prev = insn;
6915 if (prev && NOTE_P (prev))
6916 prev = prev_nonnote_insn (prev);
6917 if (prev)
6918 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6919 INSN_LOCATION (prev));
6920 else
6921 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6922 barrier = emit_barrier_after (jump);
6923 insn = emit_label_after (label, barrier);
6924 JUMP_LABEL (jump) = label;
6925 LABEL_NUSES (label) = 1;
6926
6927 INSN_ADDRESSES_NEW (jump, -1);
6928 INSN_ADDRESSES_NEW (barrier, -1);
6929 INSN_ADDRESSES_NEW (insn, -1);
6930
6931 s390_end_pool (curr_pool, barrier);
6932 curr_pool = NULL;
6933 extra_size = 0;
6934 }
6935 }
6936 }
6937
6938 if (curr_pool)
6939 s390_end_pool (curr_pool, NULL_RTX);
6940 gcc_assert (!pending_ltrel);
6941
6942 /* Find all labels that are branched into
6943 from an insn belonging to a different chunk. */
6944
6945 far_labels = BITMAP_ALLOC (NULL);
6946
6947 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6948 {
6949 /* Labels marked with LABEL_PRESERVE_P can be target
6950 of non-local jumps, so we have to mark them.
6951 The same holds for named labels.
6952
6953 Don't do that, however, if it is the label before
6954 a jump table. */
6955
6956 if (GET_CODE (insn) == CODE_LABEL
6957 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6958 {
6959 rtx vec_insn = next_real_insn (insn);
6960 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6961 PATTERN (vec_insn) : NULL_RTX;
6962 if (!vec_pat
6963 || !(GET_CODE (vec_pat) == ADDR_VEC
6964 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6965 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6966 }
6967
6968 /* If we have a direct jump (conditional or unconditional)
6969 or a casesi jump, check all potential targets. */
6970 else if (GET_CODE (insn) == JUMP_INSN)
6971 {
6972 rtx pat = PATTERN (insn);
6973 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6974 pat = XVECEXP (pat, 0, 0);
6975
6976 if (GET_CODE (pat) == SET)
6977 {
6978 rtx label = JUMP_LABEL (insn);
6979 if (label)
6980 {
6981 if (s390_find_pool (pool_list, label)
6982 != s390_find_pool (pool_list, insn))
6983 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6984 }
6985 }
6986 else if (GET_CODE (pat) == PARALLEL
6987 && XVECLEN (pat, 0) == 2
6988 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6989 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6990 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6991 {
6992 /* Find the jump table used by this casesi jump. */
6993 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6994 rtx vec_insn = next_real_insn (vec_label);
6995 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6996 PATTERN (vec_insn) : NULL_RTX;
6997 if (vec_pat
6998 && (GET_CODE (vec_pat) == ADDR_VEC
6999 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
7000 {
7001 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7002
7003 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7004 {
7005 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
7006
7007 if (s390_find_pool (pool_list, label)
7008 != s390_find_pool (pool_list, insn))
7009 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7010 }
7011 }
7012 }
7013 }
7014 }
7015
7016 /* Insert base register reload insns before every pool. */
7017
7018 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7019 {
7020 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7021 curr_pool->label);
7022 rtx insn = curr_pool->first_insn;
7023 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7024 }
7025
7026 /* Insert base register reload insns at every far label. */
7027
7028 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7029 if (GET_CODE (insn) == CODE_LABEL
7030 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7031 {
7032 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7033 if (pool)
7034 {
7035 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7036 pool->label);
7037 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
7038 }
7039 }
7040
7041
7042 BITMAP_FREE (far_labels);
7043
7044
7045 /* Recompute insn addresses. */
7046
7047 init_insn_lengths ();
7048 shorten_branches (get_insns ());
7049
7050 return pool_list;
7051 }
7052
7053 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7054 After we have decided to use this list, finish implementing
7055 all changes to the current function as required. */
7056
7057 static void
7058 s390_chunkify_finish (struct constant_pool *pool_list)
7059 {
7060 struct constant_pool *curr_pool = NULL;
7061 rtx insn;
7062
7063
7064 /* Replace all literal pool references. */
7065
7066 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7067 {
7068 if (INSN_P (insn))
7069 replace_ltrel_base (&PATTERN (insn));
7070
7071 curr_pool = s390_find_pool (pool_list, insn);
7072 if (!curr_pool)
7073 continue;
7074
7075 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
7076 {
7077 rtx addr, pool_ref = NULL_RTX;
7078 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7079 if (pool_ref)
7080 {
7081 if (s390_execute_label (insn))
7082 addr = s390_find_execute (curr_pool, insn);
7083 else
7084 addr = s390_find_constant (curr_pool,
7085 get_pool_constant (pool_ref),
7086 get_pool_mode (pool_ref));
7087
7088 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7089 INSN_CODE (insn) = -1;
7090 }
7091 }
7092 }
7093
7094 /* Dump out all literal pools. */
7095
7096 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7097 s390_dump_pool (curr_pool, 0);
7098
7099 /* Free pool list. */
7100
7101 while (pool_list)
7102 {
7103 struct constant_pool *next = pool_list->next;
7104 s390_free_pool (pool_list);
7105 pool_list = next;
7106 }
7107 }
7108
7109 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7110 We have decided we cannot use this list, so revert all changes
7111 to the current function that were done by s390_chunkify_start. */
7112
7113 static void
7114 s390_chunkify_cancel (struct constant_pool *pool_list)
7115 {
7116 struct constant_pool *curr_pool = NULL;
7117 rtx insn;
7118
7119 /* Remove all pool placeholder insns. */
7120
7121 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7122 {
7123 /* Did we insert an extra barrier? Remove it. */
7124 rtx barrier = PREV_INSN (curr_pool->pool_insn);
7125 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
7126 rtx label = NEXT_INSN (curr_pool->pool_insn);
7127
7128 if (jump && GET_CODE (jump) == JUMP_INSN
7129 && barrier && GET_CODE (barrier) == BARRIER
7130 && label && GET_CODE (label) == CODE_LABEL
7131 && GET_CODE (PATTERN (jump)) == SET
7132 && SET_DEST (PATTERN (jump)) == pc_rtx
7133 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7134 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7135 {
7136 remove_insn (jump);
7137 remove_insn (barrier);
7138 remove_insn (label);
7139 }
7140
7141 remove_insn (curr_pool->pool_insn);
7142 }
7143
7144 /* Remove all base register reload insns. */
7145
7146 for (insn = get_insns (); insn; )
7147 {
7148 rtx next_insn = NEXT_INSN (insn);
7149
7150 if (GET_CODE (insn) == INSN
7151 && GET_CODE (PATTERN (insn)) == SET
7152 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7153 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7154 remove_insn (insn);
7155
7156 insn = next_insn;
7157 }
7158
7159 /* Free pool list. */
7160
7161 while (pool_list)
7162 {
7163 struct constant_pool *next = pool_list->next;
7164 s390_free_pool (pool_list);
7165 pool_list = next;
7166 }
7167 }
7168
7169 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7170
7171 void
7172 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
7173 {
7174 REAL_VALUE_TYPE r;
7175
7176 switch (GET_MODE_CLASS (mode))
7177 {
7178 case MODE_FLOAT:
7179 case MODE_DECIMAL_FLOAT:
7180 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7181
7182 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7183 assemble_real (r, mode, align);
7184 break;
7185
7186 case MODE_INT:
7187 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7188 mark_symbol_refs_as_used (exp);
7189 break;
7190
7191 default:
7192 gcc_unreachable ();
7193 }
7194 }
7195
7196
7197 /* Return an RTL expression representing the value of the return address
7198 for the frame COUNT steps up from the current frame. FRAME is the
7199 frame pointer of that frame. */
7200
7201 rtx
7202 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7203 {
7204 int offset;
7205 rtx addr;
7206
7207 /* Without backchain, we fail for all but the current frame. */
7208
7209 if (!TARGET_BACKCHAIN && count > 0)
7210 return NULL_RTX;
7211
7212 /* For the current frame, we need to make sure the initial
7213 value of RETURN_REGNUM is actually saved. */
7214
7215 if (count == 0)
7216 {
7217 /* On non-z architectures branch splitting could overwrite r14. */
7218 if (TARGET_CPU_ZARCH)
7219 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7220 else
7221 {
7222 cfun_frame_layout.save_return_addr_p = true;
7223 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7224 }
7225 }
7226
7227 if (TARGET_PACKED_STACK)
7228 offset = -2 * UNITS_PER_LONG;
7229 else
7230 offset = RETURN_REGNUM * UNITS_PER_LONG;
7231
7232 addr = plus_constant (Pmode, frame, offset);
7233 addr = memory_address (Pmode, addr);
7234 return gen_rtx_MEM (Pmode, addr);
7235 }
7236
7237 /* Return an RTL expression representing the back chain stored in
7238 the current stack frame. */
7239
7240 rtx
7241 s390_back_chain_rtx (void)
7242 {
7243 rtx chain;
7244
7245 gcc_assert (TARGET_BACKCHAIN);
7246
7247 if (TARGET_PACKED_STACK)
7248 chain = plus_constant (Pmode, stack_pointer_rtx,
7249 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7250 else
7251 chain = stack_pointer_rtx;
7252
7253 chain = gen_rtx_MEM (Pmode, chain);
7254 return chain;
7255 }
7256
7257 /* Find first call clobbered register unused in a function.
7258 This could be used as base register in a leaf function
7259 or for holding the return address before epilogue. */
7260
7261 static int
7262 find_unused_clobbered_reg (void)
7263 {
7264 int i;
7265 for (i = 0; i < 6; i++)
7266 if (!df_regs_ever_live_p (i))
7267 return i;
7268 return 0;
7269 }
7270
7271
7272 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7273 clobbered hard regs in SETREG. */
7274
7275 static void
7276 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7277 {
7278 int *regs_ever_clobbered = (int *)data;
7279 unsigned int i, regno;
7280 enum machine_mode mode = GET_MODE (setreg);
7281
7282 if (GET_CODE (setreg) == SUBREG)
7283 {
7284 rtx inner = SUBREG_REG (setreg);
7285 if (!GENERAL_REG_P (inner))
7286 return;
7287 regno = subreg_regno (setreg);
7288 }
7289 else if (GENERAL_REG_P (setreg))
7290 regno = REGNO (setreg);
7291 else
7292 return;
7293
7294 for (i = regno;
7295 i < regno + HARD_REGNO_NREGS (regno, mode);
7296 i++)
7297 regs_ever_clobbered[i] = 1;
7298 }
7299
7300 /* Walks through all basic blocks of the current function looking
7301 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7302 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7303 each of those regs. */
7304
7305 static void
7306 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7307 {
7308 basic_block cur_bb;
7309 rtx cur_insn;
7310 unsigned int i;
7311
7312 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7313
7314 /* For non-leaf functions we have to consider all call clobbered regs to be
7315 clobbered. */
7316 if (!crtl->is_leaf)
7317 {
7318 for (i = 0; i < 16; i++)
7319 regs_ever_clobbered[i] = call_really_used_regs[i];
7320 }
7321
7322 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7323 this work is done by liveness analysis (mark_regs_live_at_end).
7324 Special care is needed for functions containing landing pads. Landing pads
7325 may use the eh registers, but the code which sets these registers is not
7326 contained in that function. Hence s390_regs_ever_clobbered is not able to
7327 deal with this automatically. */
7328 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7329 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7330 if (crtl->calls_eh_return
7331 || (cfun->machine->has_landing_pad_p
7332 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7333 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7334
7335 /* For nonlocal gotos all call-saved registers have to be saved.
7336 This flag is also set for the unwinding code in libgcc.
7337 See expand_builtin_unwind_init. For regs_ever_live this is done by
7338 reload. */
7339 if (cfun->has_nonlocal_label)
7340 for (i = 0; i < 16; i++)
7341 if (!call_really_used_regs[i])
7342 regs_ever_clobbered[i] = 1;
7343
7344 FOR_EACH_BB (cur_bb)
7345 {
7346 FOR_BB_INSNS (cur_bb, cur_insn)
7347 {
7348 if (INSN_P (cur_insn))
7349 note_stores (PATTERN (cur_insn),
7350 s390_reg_clobbered_rtx,
7351 regs_ever_clobbered);
7352 }
7353 }
7354 }
7355
7356 /* Determine the frame area which actually has to be accessed
7357 in the function epilogue. The values are stored at the
7358 given pointers AREA_BOTTOM (address of the lowest used stack
7359 address) and AREA_TOP (address of the first item which does
7360 not belong to the stack frame). */
7361
7362 static void
7363 s390_frame_area (int *area_bottom, int *area_top)
7364 {
7365 int b, t;
7366 int i;
7367
7368 b = INT_MAX;
7369 t = INT_MIN;
7370
7371 if (cfun_frame_layout.first_restore_gpr != -1)
7372 {
7373 b = (cfun_frame_layout.gprs_offset
7374 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7375 t = b + (cfun_frame_layout.last_restore_gpr
7376 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7377 }
7378
7379 if (TARGET_64BIT && cfun_save_high_fprs_p)
7380 {
7381 b = MIN (b, cfun_frame_layout.f8_offset);
7382 t = MAX (t, (cfun_frame_layout.f8_offset
7383 + cfun_frame_layout.high_fprs * 8));
7384 }
7385
7386 if (!TARGET_64BIT)
7387 for (i = 2; i < 4; i++)
7388 if (cfun_fpr_bit_p (i))
7389 {
7390 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7391 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7392 }
7393
7394 *area_bottom = b;
7395 *area_top = t;
7396 }
7397
7398 /* Fill cfun->machine with info about register usage of current function.
7399 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7400
7401 static void
7402 s390_register_info (int clobbered_regs[])
7403 {
7404 int i, j;
7405
7406 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7407 cfun_frame_layout.fpr_bitmap = 0;
7408 cfun_frame_layout.high_fprs = 0;
7409 if (TARGET_64BIT)
7410 for (i = 24; i < 32; i++)
7411 if (df_regs_ever_live_p (i) && !global_regs[i])
7412 {
7413 cfun_set_fpr_bit (i - 16);
7414 cfun_frame_layout.high_fprs++;
7415 }
7416
7417 /* Find first and last gpr to be saved. We trust regs_ever_live
7418 data, except that we don't save and restore global registers.
7419
7420 Also, all registers with special meaning to the compiler need
7421 to be handled extra. */
7422
7423 s390_regs_ever_clobbered (clobbered_regs);
7424
7425 for (i = 0; i < 16; i++)
7426 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7427
7428 if (frame_pointer_needed)
7429 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7430
7431 if (flag_pic)
7432 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7433 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7434
7435 clobbered_regs[BASE_REGNUM]
7436 |= (cfun->machine->base_reg
7437 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7438
7439 clobbered_regs[RETURN_REGNUM]
7440 |= (!crtl->is_leaf
7441 || TARGET_TPF_PROFILING
7442 || cfun->machine->split_branches_pending_p
7443 || cfun_frame_layout.save_return_addr_p
7444 || crtl->calls_eh_return
7445 || cfun->stdarg);
7446
7447 clobbered_regs[STACK_POINTER_REGNUM]
7448 |= (!crtl->is_leaf
7449 || TARGET_TPF_PROFILING
7450 || cfun_save_high_fprs_p
7451 || get_frame_size () > 0
7452 || cfun->calls_alloca
7453 || cfun->stdarg);
7454
7455 for (i = 6; i < 16; i++)
7456 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7457 break;
7458 for (j = 15; j > i; j--)
7459 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7460 break;
7461
7462 if (i == 16)
7463 {
7464 /* Nothing to save/restore. */
7465 cfun_frame_layout.first_save_gpr_slot = -1;
7466 cfun_frame_layout.last_save_gpr_slot = -1;
7467 cfun_frame_layout.first_save_gpr = -1;
7468 cfun_frame_layout.first_restore_gpr = -1;
7469 cfun_frame_layout.last_save_gpr = -1;
7470 cfun_frame_layout.last_restore_gpr = -1;
7471 }
7472 else
7473 {
7474 /* Save slots for gprs from i to j. */
7475 cfun_frame_layout.first_save_gpr_slot = i;
7476 cfun_frame_layout.last_save_gpr_slot = j;
7477
7478 for (i = cfun_frame_layout.first_save_gpr_slot;
7479 i < cfun_frame_layout.last_save_gpr_slot + 1;
7480 i++)
7481 if (clobbered_regs[i])
7482 break;
7483
7484 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7485 if (clobbered_regs[j])
7486 break;
7487
7488 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7489 {
7490 /* Nothing to save/restore. */
7491 cfun_frame_layout.first_save_gpr = -1;
7492 cfun_frame_layout.first_restore_gpr = -1;
7493 cfun_frame_layout.last_save_gpr = -1;
7494 cfun_frame_layout.last_restore_gpr = -1;
7495 }
7496 else
7497 {
7498 /* Save / Restore from gpr i to j. */
7499 cfun_frame_layout.first_save_gpr = i;
7500 cfun_frame_layout.first_restore_gpr = i;
7501 cfun_frame_layout.last_save_gpr = j;
7502 cfun_frame_layout.last_restore_gpr = j;
7503 }
7504 }
7505
7506 if (cfun->stdarg)
7507 {
7508 /* Varargs functions need to save gprs 2 to 6. */
7509 if (cfun->va_list_gpr_size
7510 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7511 {
7512 int min_gpr = crtl->args.info.gprs;
7513 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7514 if (max_gpr > GP_ARG_NUM_REG)
7515 max_gpr = GP_ARG_NUM_REG;
7516
7517 if (cfun_frame_layout.first_save_gpr == -1
7518 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7519 {
7520 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7521 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7522 }
7523
7524 if (cfun_frame_layout.last_save_gpr == -1
7525 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7526 {
7527 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7528 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7529 }
7530 }
7531
7532 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7533 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7534 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7535 {
7536 int min_fpr = crtl->args.info.fprs;
7537 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7538 if (max_fpr > FP_ARG_NUM_REG)
7539 max_fpr = FP_ARG_NUM_REG;
7540
7541 /* ??? This is currently required to ensure proper location
7542 of the fpr save slots within the va_list save area. */
7543 if (TARGET_PACKED_STACK)
7544 min_fpr = 0;
7545
7546 for (i = min_fpr; i < max_fpr; i++)
7547 cfun_set_fpr_bit (i);
7548 }
7549 }
7550
7551 if (!TARGET_64BIT)
7552 for (i = 2; i < 4; i++)
7553 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7554 cfun_set_fpr_bit (i);
7555 }
7556
7557 /* Fill cfun->machine with info about frame of current function. */
7558
7559 static void
7560 s390_frame_info (void)
7561 {
7562 int i;
7563
7564 cfun_frame_layout.frame_size = get_frame_size ();
7565 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7566 fatal_error ("total size of local variables exceeds architecture limit");
7567
7568 if (!TARGET_PACKED_STACK)
7569 {
7570 cfun_frame_layout.backchain_offset = 0;
7571 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7572 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7573 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7574 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7575 * UNITS_PER_LONG);
7576 }
7577 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7578 {
7579 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7580 - UNITS_PER_LONG);
7581 cfun_frame_layout.gprs_offset
7582 = (cfun_frame_layout.backchain_offset
7583 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7584 * UNITS_PER_LONG);
7585
7586 if (TARGET_64BIT)
7587 {
7588 cfun_frame_layout.f4_offset
7589 = (cfun_frame_layout.gprs_offset
7590 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7591
7592 cfun_frame_layout.f0_offset
7593 = (cfun_frame_layout.f4_offset
7594 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7595 }
7596 else
7597 {
7598 /* On 31 bit we have to care about alignment of the
7599 floating point regs to provide fastest access. */
7600 cfun_frame_layout.f0_offset
7601 = ((cfun_frame_layout.gprs_offset
7602 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7603 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7604
7605 cfun_frame_layout.f4_offset
7606 = (cfun_frame_layout.f0_offset
7607 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7608 }
7609 }
7610 else /* no backchain */
7611 {
7612 cfun_frame_layout.f4_offset
7613 = (STACK_POINTER_OFFSET
7614 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7615
7616 cfun_frame_layout.f0_offset
7617 = (cfun_frame_layout.f4_offset
7618 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7619
7620 cfun_frame_layout.gprs_offset
7621 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7622 }
7623
7624 if (crtl->is_leaf
7625 && !TARGET_TPF_PROFILING
7626 && cfun_frame_layout.frame_size == 0
7627 && !cfun_save_high_fprs_p
7628 && !cfun->calls_alloca
7629 && !cfun->stdarg)
7630 return;
7631
7632 if (!TARGET_PACKED_STACK)
7633 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7634 + crtl->outgoing_args_size
7635 + cfun_frame_layout.high_fprs * 8);
7636 else
7637 {
7638 if (TARGET_BACKCHAIN)
7639 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7640
7641 /* No alignment trouble here because f8-f15 are only saved under
7642 64 bit. */
7643 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7644 cfun_frame_layout.f4_offset),
7645 cfun_frame_layout.gprs_offset)
7646 - cfun_frame_layout.high_fprs * 8);
7647
7648 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7649
7650 for (i = 0; i < 8; i++)
7651 if (cfun_fpr_bit_p (i))
7652 cfun_frame_layout.frame_size += 8;
7653
7654 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7655
7656 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7657 the frame size to sustain 8 byte alignment of stack frames. */
7658 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7659 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7660 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7661
7662 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7663 }
7664 }
7665
7666 /* Generate frame layout. Fills in register and frame data for the current
7667 function in cfun->machine. This routine can be called multiple times;
7668 it will re-do the complete frame layout every time. */
7669
7670 static void
7671 s390_init_frame_layout (void)
7672 {
7673 HOST_WIDE_INT frame_size;
7674 int base_used;
7675 int clobbered_regs[16];
7676
7677 /* On S/390 machines, we may need to perform branch splitting, which
7678 will require both base and return address register. We have no
7679 choice but to assume we're going to need them until right at the
7680 end of the machine dependent reorg phase. */
7681 if (!TARGET_CPU_ZARCH)
7682 cfun->machine->split_branches_pending_p = true;
7683
7684 do
7685 {
7686 frame_size = cfun_frame_layout.frame_size;
7687
7688 /* Try to predict whether we'll need the base register. */
7689 base_used = cfun->machine->split_branches_pending_p
7690 || crtl->uses_const_pool
7691 || (!DISP_IN_RANGE (frame_size)
7692 && !CONST_OK_FOR_K (frame_size));
7693
7694 /* Decide which register to use as literal pool base. In small
7695 leaf functions, try to use an unused call-clobbered register
7696 as base register to avoid save/restore overhead. */
7697 if (!base_used)
7698 cfun->machine->base_reg = NULL_RTX;
7699 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7700 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7701 else
7702 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7703
7704 s390_register_info (clobbered_regs);
7705 s390_frame_info ();
7706 }
7707 while (frame_size != cfun_frame_layout.frame_size);
7708 }
7709
7710 /* Update frame layout. Recompute actual register save data based on
7711 current info and update regs_ever_live for the special registers.
7712 May be called multiple times, but may never cause *more* registers
7713 to be saved than s390_init_frame_layout allocated room for. */
7714
7715 static void
7716 s390_update_frame_layout (void)
7717 {
7718 int clobbered_regs[16];
7719
7720 s390_register_info (clobbered_regs);
7721
7722 df_set_regs_ever_live (BASE_REGNUM,
7723 clobbered_regs[BASE_REGNUM] ? true : false);
7724 df_set_regs_ever_live (RETURN_REGNUM,
7725 clobbered_regs[RETURN_REGNUM] ? true : false);
7726 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7727 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7728
7729 if (cfun->machine->base_reg)
7730 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7731 }
7732
7733 /* Return true if it is legal to put a value with MODE into REGNO. */
7734
7735 bool
7736 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7737 {
7738 switch (REGNO_REG_CLASS (regno))
7739 {
7740 case FP_REGS:
7741 if (REGNO_PAIR_OK (regno, mode))
7742 {
7743 if (mode == SImode || mode == DImode)
7744 return true;
7745
7746 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7747 return true;
7748 }
7749 break;
7750 case ADDR_REGS:
7751 if (FRAME_REGNO_P (regno) && mode == Pmode)
7752 return true;
7753
7754 /* fallthrough */
7755 case GENERAL_REGS:
7756 if (REGNO_PAIR_OK (regno, mode))
7757 {
7758 if (TARGET_ZARCH
7759 || (mode != TFmode && mode != TCmode && mode != TDmode))
7760 return true;
7761 }
7762 break;
7763 case CC_REGS:
7764 if (GET_MODE_CLASS (mode) == MODE_CC)
7765 return true;
7766 break;
7767 case ACCESS_REGS:
7768 if (REGNO_PAIR_OK (regno, mode))
7769 {
7770 if (mode == SImode || mode == Pmode)
7771 return true;
7772 }
7773 break;
7774 default:
7775 return false;
7776 }
7777
7778 return false;
7779 }
7780
7781 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7782
7783 bool
7784 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7785 {
7786 /* Once we've decided upon a register to use as base register, it must
7787 no longer be used for any other purpose. */
7788 if (cfun->machine->base_reg)
7789 if (REGNO (cfun->machine->base_reg) == old_reg
7790 || REGNO (cfun->machine->base_reg) == new_reg)
7791 return false;
7792
7793 return true;
7794 }
7795
7796 /* Maximum number of registers to represent a value of mode MODE
7797 in a register of class RCLASS. */
7798
7799 int
7800 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7801 {
7802 switch (rclass)
7803 {
7804 case FP_REGS:
7805 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7806 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7807 else
7808 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7809 case ACCESS_REGS:
7810 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7811 default:
7812 break;
7813 }
7814 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7815 }
7816
7817 /* Return true if register FROM can be eliminated via register TO. */
7818
7819 static bool
7820 s390_can_eliminate (const int from, const int to)
7821 {
7822 /* On zSeries machines, we have not marked the base register as fixed.
7823 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7824 If a function requires the base register, we say here that this
7825 elimination cannot be performed. This will cause reload to free
7826 up the base register (as if it were fixed). On the other hand,
7827 if the current function does *not* require the base register, we
7828 say here the elimination succeeds, which in turn allows reload
7829 to allocate the base register for any other purpose. */
7830 if (from == BASE_REGNUM && to == BASE_REGNUM)
7831 {
7832 if (TARGET_CPU_ZARCH)
7833 {
7834 s390_init_frame_layout ();
7835 return cfun->machine->base_reg == NULL_RTX;
7836 }
7837
7838 return false;
7839 }
7840
7841 /* Everything else must point into the stack frame. */
7842 gcc_assert (to == STACK_POINTER_REGNUM
7843 || to == HARD_FRAME_POINTER_REGNUM);
7844
7845 gcc_assert (from == FRAME_POINTER_REGNUM
7846 || from == ARG_POINTER_REGNUM
7847 || from == RETURN_ADDRESS_POINTER_REGNUM);
7848
7849 /* Make sure we actually saved the return address. */
7850 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7851 if (!crtl->calls_eh_return
7852 && !cfun->stdarg
7853 && !cfun_frame_layout.save_return_addr_p)
7854 return false;
7855
7856 return true;
7857 }
7858
7859 /* Return offset between register FROM and TO initially after prolog. */
7860
7861 HOST_WIDE_INT
7862 s390_initial_elimination_offset (int from, int to)
7863 {
7864 HOST_WIDE_INT offset;
7865 int index;
7866
7867 /* ??? Why are we called for non-eliminable pairs? */
7868 if (!s390_can_eliminate (from, to))
7869 return 0;
7870
7871 switch (from)
7872 {
7873 case FRAME_POINTER_REGNUM:
7874 offset = (get_frame_size()
7875 + STACK_POINTER_OFFSET
7876 + crtl->outgoing_args_size);
7877 break;
7878
7879 case ARG_POINTER_REGNUM:
7880 s390_init_frame_layout ();
7881 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7882 break;
7883
7884 case RETURN_ADDRESS_POINTER_REGNUM:
7885 s390_init_frame_layout ();
7886 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7887 gcc_assert (index >= 0);
7888 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7889 offset += index * UNITS_PER_LONG;
7890 break;
7891
7892 case BASE_REGNUM:
7893 offset = 0;
7894 break;
7895
7896 default:
7897 gcc_unreachable ();
7898 }
7899
7900 return offset;
7901 }
7902
7903 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7904 to register BASE. Return generated insn. */
7905
7906 static rtx
7907 save_fpr (rtx base, int offset, int regnum)
7908 {
7909 rtx addr;
7910 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7911
7912 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7913 set_mem_alias_set (addr, get_varargs_alias_set ());
7914 else
7915 set_mem_alias_set (addr, get_frame_alias_set ());
7916
7917 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7918 }
7919
7920 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7921 to register BASE. Return generated insn. */
7922
7923 static rtx
7924 restore_fpr (rtx base, int offset, int regnum)
7925 {
7926 rtx addr;
7927 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7928 set_mem_alias_set (addr, get_frame_alias_set ());
7929
7930 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7931 }
7932
7933 /* Return true if REGNO is a global register, but not one
7934 of the special ones that need to be saved/restored in anyway. */
7935
7936 static inline bool
7937 global_not_special_regno_p (int regno)
7938 {
7939 return (global_regs[regno]
7940 /* These registers are special and need to be
7941 restored in any case. */
7942 && !(regno == STACK_POINTER_REGNUM
7943 || regno == RETURN_REGNUM
7944 || regno == BASE_REGNUM
7945 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7946 }
7947
7948 /* Generate insn to save registers FIRST to LAST into
7949 the register save area located at offset OFFSET
7950 relative to register BASE. */
7951
7952 static rtx
7953 save_gprs (rtx base, int offset, int first, int last)
7954 {
7955 rtx addr, insn, note;
7956 int i;
7957
7958 addr = plus_constant (Pmode, base, offset);
7959 addr = gen_rtx_MEM (Pmode, addr);
7960
7961 set_mem_alias_set (addr, get_frame_alias_set ());
7962
7963 /* Special-case single register. */
7964 if (first == last)
7965 {
7966 if (TARGET_64BIT)
7967 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7968 else
7969 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7970
7971 if (!global_not_special_regno_p (first))
7972 RTX_FRAME_RELATED_P (insn) = 1;
7973 return insn;
7974 }
7975
7976
7977 insn = gen_store_multiple (addr,
7978 gen_rtx_REG (Pmode, first),
7979 GEN_INT (last - first + 1));
7980
7981 if (first <= 6 && cfun->stdarg)
7982 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7983 {
7984 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7985
7986 if (first + i <= 6)
7987 set_mem_alias_set (mem, get_varargs_alias_set ());
7988 }
7989
7990 /* We need to set the FRAME_RELATED flag on all SETs
7991 inside the store-multiple pattern.
7992
7993 However, we must not emit DWARF records for registers 2..5
7994 if they are stored for use by variable arguments ...
7995
7996 ??? Unfortunately, it is not enough to simply not the
7997 FRAME_RELATED flags for those SETs, because the first SET
7998 of the PARALLEL is always treated as if it had the flag
7999 set, even if it does not. Therefore we emit a new pattern
8000 without those registers as REG_FRAME_RELATED_EXPR note. */
8001
8002 if (first >= 6 && !global_not_special_regno_p (first))
8003 {
8004 rtx pat = PATTERN (insn);
8005
8006 for (i = 0; i < XVECLEN (pat, 0); i++)
8007 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8008 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8009 0, i)))))
8010 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8011
8012 RTX_FRAME_RELATED_P (insn) = 1;
8013 }
8014 else if (last >= 6)
8015 {
8016 int start;
8017
8018 for (start = first >= 6 ? first : 6; start <= last; start++)
8019 if (!global_not_special_regno_p (start))
8020 break;
8021
8022 if (start > last)
8023 return insn;
8024
8025 addr = plus_constant (Pmode, base,
8026 offset + (start - first) * UNITS_PER_LONG);
8027 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
8028 gen_rtx_REG (Pmode, start),
8029 GEN_INT (last - start + 1));
8030 note = PATTERN (note);
8031
8032 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8033
8034 for (i = 0; i < XVECLEN (note, 0); i++)
8035 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8036 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8037 0, i)))))
8038 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8039
8040 RTX_FRAME_RELATED_P (insn) = 1;
8041 }
8042
8043 return insn;
8044 }
8045
8046 /* Generate insn to restore registers FIRST to LAST from
8047 the register save area located at offset OFFSET
8048 relative to register BASE. */
8049
8050 static rtx
8051 restore_gprs (rtx base, int offset, int first, int last)
8052 {
8053 rtx addr, insn;
8054
8055 addr = plus_constant (Pmode, base, offset);
8056 addr = gen_rtx_MEM (Pmode, addr);
8057 set_mem_alias_set (addr, get_frame_alias_set ());
8058
8059 /* Special-case single register. */
8060 if (first == last)
8061 {
8062 if (TARGET_64BIT)
8063 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8064 else
8065 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8066
8067 return insn;
8068 }
8069
8070 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8071 addr,
8072 GEN_INT (last - first + 1));
8073 return insn;
8074 }
8075
8076 /* Return insn sequence to load the GOT register. */
8077
8078 static GTY(()) rtx got_symbol;
8079 rtx
8080 s390_load_got (void)
8081 {
8082 rtx insns;
8083
8084 /* We cannot use pic_offset_table_rtx here since we use this
8085 function also for non-pic if __tls_get_offset is called and in
8086 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8087 aren't usable. */
8088 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8089
8090 if (!got_symbol)
8091 {
8092 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8093 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8094 }
8095
8096 start_sequence ();
8097
8098 if (TARGET_CPU_ZARCH)
8099 {
8100 emit_move_insn (got_rtx, got_symbol);
8101 }
8102 else
8103 {
8104 rtx offset;
8105
8106 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
8107 UNSPEC_LTREL_OFFSET);
8108 offset = gen_rtx_CONST (Pmode, offset);
8109 offset = force_const_mem (Pmode, offset);
8110
8111 emit_move_insn (got_rtx, offset);
8112
8113 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
8114 UNSPEC_LTREL_BASE);
8115 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
8116
8117 emit_move_insn (got_rtx, offset);
8118 }
8119
8120 insns = get_insns ();
8121 end_sequence ();
8122 return insns;
8123 }
8124
8125 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8126 and the change to the stack pointer. */
8127
8128 static void
8129 s390_emit_stack_tie (void)
8130 {
8131 rtx mem = gen_frame_mem (BLKmode,
8132 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8133
8134 emit_insn (gen_stack_tie (mem));
8135 }
8136
8137 /* Expand the prologue into a bunch of separate insns. */
8138
8139 void
8140 s390_emit_prologue (void)
8141 {
8142 rtx insn, addr;
8143 rtx temp_reg;
8144 int i;
8145 int offset;
8146 int next_fpr = 0;
8147
8148 /* Complete frame layout. */
8149
8150 s390_update_frame_layout ();
8151
8152 /* Annotate all constant pool references to let the scheduler know
8153 they implicitly use the base register. */
8154
8155 push_topmost_sequence ();
8156
8157 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8158 if (INSN_P (insn))
8159 {
8160 annotate_constant_pool_refs (&PATTERN (insn));
8161 df_insn_rescan (insn);
8162 }
8163
8164 pop_topmost_sequence ();
8165
8166 /* Choose best register to use for temp use within prologue.
8167 See below for why TPF must use the register 1. */
8168
8169 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8170 && !crtl->is_leaf
8171 && !TARGET_TPF_PROFILING)
8172 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8173 else
8174 temp_reg = gen_rtx_REG (Pmode, 1);
8175
8176 /* Save call saved gprs. */
8177 if (cfun_frame_layout.first_save_gpr != -1)
8178 {
8179 insn = save_gprs (stack_pointer_rtx,
8180 cfun_frame_layout.gprs_offset +
8181 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8182 - cfun_frame_layout.first_save_gpr_slot),
8183 cfun_frame_layout.first_save_gpr,
8184 cfun_frame_layout.last_save_gpr);
8185 emit_insn (insn);
8186 }
8187
8188 /* Dummy insn to mark literal pool slot. */
8189
8190 if (cfun->machine->base_reg)
8191 emit_insn (gen_main_pool (cfun->machine->base_reg));
8192
8193 offset = cfun_frame_layout.f0_offset;
8194
8195 /* Save f0 and f2. */
8196 for (i = 0; i < 2; i++)
8197 {
8198 if (cfun_fpr_bit_p (i))
8199 {
8200 save_fpr (stack_pointer_rtx, offset, i + 16);
8201 offset += 8;
8202 }
8203 else if (!TARGET_PACKED_STACK)
8204 offset += 8;
8205 }
8206
8207 /* Save f4 and f6. */
8208 offset = cfun_frame_layout.f4_offset;
8209 for (i = 2; i < 4; i++)
8210 {
8211 if (cfun_fpr_bit_p (i))
8212 {
8213 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8214 offset += 8;
8215
8216 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8217 therefore are not frame related. */
8218 if (!call_really_used_regs[i + 16])
8219 RTX_FRAME_RELATED_P (insn) = 1;
8220 }
8221 else if (!TARGET_PACKED_STACK)
8222 offset += 8;
8223 }
8224
8225 if (TARGET_PACKED_STACK
8226 && cfun_save_high_fprs_p
8227 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8228 {
8229 offset = (cfun_frame_layout.f8_offset
8230 + (cfun_frame_layout.high_fprs - 1) * 8);
8231
8232 for (i = 15; i > 7 && offset >= 0; i--)
8233 if (cfun_fpr_bit_p (i))
8234 {
8235 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8236
8237 RTX_FRAME_RELATED_P (insn) = 1;
8238 offset -= 8;
8239 }
8240 if (offset >= cfun_frame_layout.f8_offset)
8241 next_fpr = i + 16;
8242 }
8243
8244 if (!TARGET_PACKED_STACK)
8245 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8246
8247 if (flag_stack_usage_info)
8248 current_function_static_stack_size = cfun_frame_layout.frame_size;
8249
8250 /* Decrement stack pointer. */
8251
8252 if (cfun_frame_layout.frame_size > 0)
8253 {
8254 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8255 rtx real_frame_off;
8256
8257 if (s390_stack_size)
8258 {
8259 HOST_WIDE_INT stack_guard;
8260
8261 if (s390_stack_guard)
8262 stack_guard = s390_stack_guard;
8263 else
8264 {
8265 /* If no value for stack guard is provided the smallest power of 2
8266 larger than the current frame size is chosen. */
8267 stack_guard = 1;
8268 while (stack_guard < cfun_frame_layout.frame_size)
8269 stack_guard <<= 1;
8270 }
8271
8272 if (cfun_frame_layout.frame_size >= s390_stack_size)
8273 {
8274 warning (0, "frame size of function %qs is %wd"
8275 " bytes exceeding user provided stack limit of "
8276 "%d bytes. "
8277 "An unconditional trap is added.",
8278 current_function_name(), cfun_frame_layout.frame_size,
8279 s390_stack_size);
8280 emit_insn (gen_trap ());
8281 }
8282 else
8283 {
8284 /* stack_guard has to be smaller than s390_stack_size.
8285 Otherwise we would emit an AND with zero which would
8286 not match the test under mask pattern. */
8287 if (stack_guard >= s390_stack_size)
8288 {
8289 warning (0, "frame size of function %qs is %wd"
8290 " bytes which is more than half the stack size. "
8291 "The dynamic check would not be reliable. "
8292 "No check emitted for this function.",
8293 current_function_name(),
8294 cfun_frame_layout.frame_size);
8295 }
8296 else
8297 {
8298 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8299 & ~(stack_guard - 1));
8300
8301 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8302 GEN_INT (stack_check_mask));
8303 if (TARGET_64BIT)
8304 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8305 t, const0_rtx),
8306 t, const0_rtx, const0_rtx));
8307 else
8308 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8309 t, const0_rtx),
8310 t, const0_rtx, const0_rtx));
8311 }
8312 }
8313 }
8314
8315 if (s390_warn_framesize > 0
8316 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8317 warning (0, "frame size of %qs is %wd bytes",
8318 current_function_name (), cfun_frame_layout.frame_size);
8319
8320 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8321 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8322
8323 /* Save incoming stack pointer into temp reg. */
8324 if (TARGET_BACKCHAIN || next_fpr)
8325 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8326
8327 /* Subtract frame size from stack pointer. */
8328
8329 if (DISP_IN_RANGE (INTVAL (frame_off)))
8330 {
8331 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8332 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8333 frame_off));
8334 insn = emit_insn (insn);
8335 }
8336 else
8337 {
8338 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8339 frame_off = force_const_mem (Pmode, frame_off);
8340
8341 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8342 annotate_constant_pool_refs (&PATTERN (insn));
8343 }
8344
8345 RTX_FRAME_RELATED_P (insn) = 1;
8346 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8347 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8348 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8349 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8350 real_frame_off)));
8351
8352 /* Set backchain. */
8353
8354 if (TARGET_BACKCHAIN)
8355 {
8356 if (cfun_frame_layout.backchain_offset)
8357 addr = gen_rtx_MEM (Pmode,
8358 plus_constant (Pmode, stack_pointer_rtx,
8359 cfun_frame_layout.backchain_offset));
8360 else
8361 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8362 set_mem_alias_set (addr, get_frame_alias_set ());
8363 insn = emit_insn (gen_move_insn (addr, temp_reg));
8364 }
8365
8366 /* If we support non-call exceptions (e.g. for Java),
8367 we need to make sure the backchain pointer is set up
8368 before any possibly trapping memory access. */
8369 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8370 {
8371 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8372 emit_clobber (addr);
8373 }
8374 }
8375
8376 /* Save fprs 8 - 15 (64 bit ABI). */
8377
8378 if (cfun_save_high_fprs_p && next_fpr)
8379 {
8380 /* If the stack might be accessed through a different register
8381 we have to make sure that the stack pointer decrement is not
8382 moved below the use of the stack slots. */
8383 s390_emit_stack_tie ();
8384
8385 insn = emit_insn (gen_add2_insn (temp_reg,
8386 GEN_INT (cfun_frame_layout.f8_offset)));
8387
8388 offset = 0;
8389
8390 for (i = 24; i <= next_fpr; i++)
8391 if (cfun_fpr_bit_p (i - 16))
8392 {
8393 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8394 cfun_frame_layout.frame_size
8395 + cfun_frame_layout.f8_offset
8396 + offset);
8397
8398 insn = save_fpr (temp_reg, offset, i);
8399 offset += 8;
8400 RTX_FRAME_RELATED_P (insn) = 1;
8401 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8402 gen_rtx_SET (VOIDmode,
8403 gen_rtx_MEM (DFmode, addr),
8404 gen_rtx_REG (DFmode, i)));
8405 }
8406 }
8407
8408 /* Set frame pointer, if needed. */
8409
8410 if (frame_pointer_needed)
8411 {
8412 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8413 RTX_FRAME_RELATED_P (insn) = 1;
8414 }
8415
8416 /* Set up got pointer, if needed. */
8417
8418 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8419 {
8420 rtx insns = s390_load_got ();
8421
8422 for (insn = insns; insn; insn = NEXT_INSN (insn))
8423 annotate_constant_pool_refs (&PATTERN (insn));
8424
8425 emit_insn (insns);
8426 }
8427
8428 if (TARGET_TPF_PROFILING)
8429 {
8430 /* Generate a BAS instruction to serve as a function
8431 entry intercept to facilitate the use of tracing
8432 algorithms located at the branch target. */
8433 emit_insn (gen_prologue_tpf ());
8434
8435 /* Emit a blockage here so that all code
8436 lies between the profiling mechanisms. */
8437 emit_insn (gen_blockage ());
8438 }
8439 }
8440
8441 /* Expand the epilogue into a bunch of separate insns. */
8442
8443 void
8444 s390_emit_epilogue (bool sibcall)
8445 {
8446 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8447 int area_bottom, area_top, offset = 0;
8448 int next_offset;
8449 rtvec p;
8450 int i;
8451
8452 if (TARGET_TPF_PROFILING)
8453 {
8454
8455 /* Generate a BAS instruction to serve as a function
8456 entry intercept to facilitate the use of tracing
8457 algorithms located at the branch target. */
8458
8459 /* Emit a blockage here so that all code
8460 lies between the profiling mechanisms. */
8461 emit_insn (gen_blockage ());
8462
8463 emit_insn (gen_epilogue_tpf ());
8464 }
8465
8466 /* Check whether to use frame or stack pointer for restore. */
8467
8468 frame_pointer = (frame_pointer_needed
8469 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8470
8471 s390_frame_area (&area_bottom, &area_top);
8472
8473 /* Check whether we can access the register save area.
8474 If not, increment the frame pointer as required. */
8475
8476 if (area_top <= area_bottom)
8477 {
8478 /* Nothing to restore. */
8479 }
8480 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8481 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8482 {
8483 /* Area is in range. */
8484 offset = cfun_frame_layout.frame_size;
8485 }
8486 else
8487 {
8488 rtx insn, frame_off, cfa;
8489
8490 offset = area_bottom < 0 ? -area_bottom : 0;
8491 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8492
8493 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8494 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8495 if (DISP_IN_RANGE (INTVAL (frame_off)))
8496 {
8497 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8498 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8499 insn = emit_insn (insn);
8500 }
8501 else
8502 {
8503 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8504 frame_off = force_const_mem (Pmode, frame_off);
8505
8506 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8507 annotate_constant_pool_refs (&PATTERN (insn));
8508 }
8509 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8510 RTX_FRAME_RELATED_P (insn) = 1;
8511 }
8512
8513 /* Restore call saved fprs. */
8514
8515 if (TARGET_64BIT)
8516 {
8517 if (cfun_save_high_fprs_p)
8518 {
8519 next_offset = cfun_frame_layout.f8_offset;
8520 for (i = 24; i < 32; i++)
8521 {
8522 if (cfun_fpr_bit_p (i - 16))
8523 {
8524 restore_fpr (frame_pointer,
8525 offset + next_offset, i);
8526 cfa_restores
8527 = alloc_reg_note (REG_CFA_RESTORE,
8528 gen_rtx_REG (DFmode, i), cfa_restores);
8529 next_offset += 8;
8530 }
8531 }
8532 }
8533
8534 }
8535 else
8536 {
8537 next_offset = cfun_frame_layout.f4_offset;
8538 for (i = 18; i < 20; i++)
8539 {
8540 if (cfun_fpr_bit_p (i - 16))
8541 {
8542 restore_fpr (frame_pointer,
8543 offset + next_offset, i);
8544 cfa_restores
8545 = alloc_reg_note (REG_CFA_RESTORE,
8546 gen_rtx_REG (DFmode, i), cfa_restores);
8547 next_offset += 8;
8548 }
8549 else if (!TARGET_PACKED_STACK)
8550 next_offset += 8;
8551 }
8552
8553 }
8554
8555 /* Return register. */
8556
8557 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8558
8559 /* Restore call saved gprs. */
8560
8561 if (cfun_frame_layout.first_restore_gpr != -1)
8562 {
8563 rtx insn, addr;
8564 int i;
8565
8566 /* Check for global register and save them
8567 to stack location from where they get restored. */
8568
8569 for (i = cfun_frame_layout.first_restore_gpr;
8570 i <= cfun_frame_layout.last_restore_gpr;
8571 i++)
8572 {
8573 if (global_not_special_regno_p (i))
8574 {
8575 addr = plus_constant (Pmode, frame_pointer,
8576 offset + cfun_frame_layout.gprs_offset
8577 + (i - cfun_frame_layout.first_save_gpr_slot)
8578 * UNITS_PER_LONG);
8579 addr = gen_rtx_MEM (Pmode, addr);
8580 set_mem_alias_set (addr, get_frame_alias_set ());
8581 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8582 }
8583 else
8584 cfa_restores
8585 = alloc_reg_note (REG_CFA_RESTORE,
8586 gen_rtx_REG (Pmode, i), cfa_restores);
8587 }
8588
8589 if (! sibcall)
8590 {
8591 /* Fetch return address from stack before load multiple,
8592 this will do good for scheduling. */
8593
8594 if (cfun_frame_layout.save_return_addr_p
8595 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8596 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8597 {
8598 int return_regnum = find_unused_clobbered_reg();
8599 if (!return_regnum)
8600 return_regnum = 4;
8601 return_reg = gen_rtx_REG (Pmode, return_regnum);
8602
8603 addr = plus_constant (Pmode, frame_pointer,
8604 offset + cfun_frame_layout.gprs_offset
8605 + (RETURN_REGNUM
8606 - cfun_frame_layout.first_save_gpr_slot)
8607 * UNITS_PER_LONG);
8608 addr = gen_rtx_MEM (Pmode, addr);
8609 set_mem_alias_set (addr, get_frame_alias_set ());
8610 emit_move_insn (return_reg, addr);
8611 }
8612 }
8613
8614 insn = restore_gprs (frame_pointer,
8615 offset + cfun_frame_layout.gprs_offset
8616 + (cfun_frame_layout.first_restore_gpr
8617 - cfun_frame_layout.first_save_gpr_slot)
8618 * UNITS_PER_LONG,
8619 cfun_frame_layout.first_restore_gpr,
8620 cfun_frame_layout.last_restore_gpr);
8621 insn = emit_insn (insn);
8622 REG_NOTES (insn) = cfa_restores;
8623 add_reg_note (insn, REG_CFA_DEF_CFA,
8624 plus_constant (Pmode, stack_pointer_rtx,
8625 STACK_POINTER_OFFSET));
8626 RTX_FRAME_RELATED_P (insn) = 1;
8627 }
8628
8629 if (! sibcall)
8630 {
8631
8632 /* Return to caller. */
8633
8634 p = rtvec_alloc (2);
8635
8636 RTVEC_ELT (p, 0) = ret_rtx;
8637 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8638 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8639 }
8640 }
8641
8642
8643 /* Return the size in bytes of a function argument of
8644 type TYPE and/or mode MODE. At least one of TYPE or
8645 MODE must be specified. */
8646
8647 static int
8648 s390_function_arg_size (enum machine_mode mode, const_tree type)
8649 {
8650 if (type)
8651 return int_size_in_bytes (type);
8652
8653 /* No type info available for some library calls ... */
8654 if (mode != BLKmode)
8655 return GET_MODE_SIZE (mode);
8656
8657 /* If we have neither type nor mode, abort */
8658 gcc_unreachable ();
8659 }
8660
8661 /* Return true if a function argument of type TYPE and mode MODE
8662 is to be passed in a floating-point register, if available. */
8663
8664 static bool
8665 s390_function_arg_float (enum machine_mode mode, const_tree type)
8666 {
8667 int size = s390_function_arg_size (mode, type);
8668 if (size > 8)
8669 return false;
8670
8671 /* Soft-float changes the ABI: no floating-point registers are used. */
8672 if (TARGET_SOFT_FLOAT)
8673 return false;
8674
8675 /* No type info available for some library calls ... */
8676 if (!type)
8677 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8678
8679 /* The ABI says that record types with a single member are treated
8680 just like that member would be. */
8681 while (TREE_CODE (type) == RECORD_TYPE)
8682 {
8683 tree field, single = NULL_TREE;
8684
8685 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8686 {
8687 if (TREE_CODE (field) != FIELD_DECL)
8688 continue;
8689
8690 if (single == NULL_TREE)
8691 single = TREE_TYPE (field);
8692 else
8693 return false;
8694 }
8695
8696 if (single == NULL_TREE)
8697 return false;
8698 else
8699 type = single;
8700 }
8701
8702 return TREE_CODE (type) == REAL_TYPE;
8703 }
8704
8705 /* Return true if a function argument of type TYPE and mode MODE
8706 is to be passed in an integer register, or a pair of integer
8707 registers, if available. */
8708
8709 static bool
8710 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8711 {
8712 int size = s390_function_arg_size (mode, type);
8713 if (size > 8)
8714 return false;
8715
8716 /* No type info available for some library calls ... */
8717 if (!type)
8718 return GET_MODE_CLASS (mode) == MODE_INT
8719 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8720
8721 /* We accept small integral (and similar) types. */
8722 if (INTEGRAL_TYPE_P (type)
8723 || POINTER_TYPE_P (type)
8724 || TREE_CODE (type) == NULLPTR_TYPE
8725 || TREE_CODE (type) == OFFSET_TYPE
8726 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8727 return true;
8728
8729 /* We also accept structs of size 1, 2, 4, 8 that are not
8730 passed in floating-point registers. */
8731 if (AGGREGATE_TYPE_P (type)
8732 && exact_log2 (size) >= 0
8733 && !s390_function_arg_float (mode, type))
8734 return true;
8735
8736 return false;
8737 }
8738
8739 /* Return 1 if a function argument of type TYPE and mode MODE
8740 is to be passed by reference. The ABI specifies that only
8741 structures of size 1, 2, 4, or 8 bytes are passed by value,
8742 all other structures (and complex numbers) are passed by
8743 reference. */
8744
8745 static bool
8746 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8747 enum machine_mode mode, const_tree type,
8748 bool named ATTRIBUTE_UNUSED)
8749 {
8750 int size = s390_function_arg_size (mode, type);
8751 if (size > 8)
8752 return true;
8753
8754 if (type)
8755 {
8756 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8757 return 1;
8758
8759 if (TREE_CODE (type) == COMPLEX_TYPE
8760 || TREE_CODE (type) == VECTOR_TYPE)
8761 return 1;
8762 }
8763
8764 return 0;
8765 }
8766
8767 /* Update the data in CUM to advance over an argument of mode MODE and
8768 data type TYPE. (TYPE is null for libcalls where that information
8769 may not be available.). The boolean NAMED specifies whether the
8770 argument is a named argument (as opposed to an unnamed argument
8771 matching an ellipsis). */
8772
8773 static void
8774 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8775 const_tree type, bool named ATTRIBUTE_UNUSED)
8776 {
8777 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8778
8779 if (s390_function_arg_float (mode, type))
8780 {
8781 cum->fprs += 1;
8782 }
8783 else if (s390_function_arg_integer (mode, type))
8784 {
8785 int size = s390_function_arg_size (mode, type);
8786 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8787 }
8788 else
8789 gcc_unreachable ();
8790 }
8791
8792 /* Define where to put the arguments to a function.
8793 Value is zero to push the argument on the stack,
8794 or a hard register in which to store the argument.
8795
8796 MODE is the argument's machine mode.
8797 TYPE is the data type of the argument (as a tree).
8798 This is null for libcalls where that information may
8799 not be available.
8800 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8801 the preceding args and about the function being called.
8802 NAMED is nonzero if this argument is a named parameter
8803 (otherwise it is an extra parameter matching an ellipsis).
8804
8805 On S/390, we use general purpose registers 2 through 6 to
8806 pass integer, pointer, and certain structure arguments, and
8807 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8808 to pass floating point arguments. All remaining arguments
8809 are pushed to the stack. */
8810
8811 static rtx
8812 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8813 const_tree type, bool named ATTRIBUTE_UNUSED)
8814 {
8815 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8816
8817 if (s390_function_arg_float (mode, type))
8818 {
8819 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8820 return 0;
8821 else
8822 return gen_rtx_REG (mode, cum->fprs + 16);
8823 }
8824 else if (s390_function_arg_integer (mode, type))
8825 {
8826 int size = s390_function_arg_size (mode, type);
8827 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8828
8829 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8830 return 0;
8831 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8832 return gen_rtx_REG (mode, cum->gprs + 2);
8833 else if (n_gprs == 2)
8834 {
8835 rtvec p = rtvec_alloc (2);
8836
8837 RTVEC_ELT (p, 0)
8838 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8839 const0_rtx);
8840 RTVEC_ELT (p, 1)
8841 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8842 GEN_INT (4));
8843
8844 return gen_rtx_PARALLEL (mode, p);
8845 }
8846 }
8847
8848 /* After the real arguments, expand_call calls us once again
8849 with a void_type_node type. Whatever we return here is
8850 passed as operand 2 to the call expanders.
8851
8852 We don't need this feature ... */
8853 else if (type == void_type_node)
8854 return const0_rtx;
8855
8856 gcc_unreachable ();
8857 }
8858
8859 /* Return true if return values of type TYPE should be returned
8860 in a memory buffer whose address is passed by the caller as
8861 hidden first argument. */
8862
8863 static bool
8864 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8865 {
8866 /* We accept small integral (and similar) types. */
8867 if (INTEGRAL_TYPE_P (type)
8868 || POINTER_TYPE_P (type)
8869 || TREE_CODE (type) == OFFSET_TYPE
8870 || TREE_CODE (type) == REAL_TYPE)
8871 return int_size_in_bytes (type) > 8;
8872
8873 /* Aggregates and similar constructs are always returned
8874 in memory. */
8875 if (AGGREGATE_TYPE_P (type)
8876 || TREE_CODE (type) == COMPLEX_TYPE
8877 || TREE_CODE (type) == VECTOR_TYPE)
8878 return true;
8879
8880 /* ??? We get called on all sorts of random stuff from
8881 aggregate_value_p. We can't abort, but it's not clear
8882 what's safe to return. Pretend it's a struct I guess. */
8883 return true;
8884 }
8885
8886 /* Function arguments and return values are promoted to word size. */
8887
8888 static enum machine_mode
8889 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8890 int *punsignedp,
8891 const_tree fntype ATTRIBUTE_UNUSED,
8892 int for_return ATTRIBUTE_UNUSED)
8893 {
8894 if (INTEGRAL_MODE_P (mode)
8895 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8896 {
8897 if (type != NULL_TREE && POINTER_TYPE_P (type))
8898 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8899 return Pmode;
8900 }
8901
8902 return mode;
8903 }
8904
8905 /* Define where to return a (scalar) value of type RET_TYPE.
8906 If RET_TYPE is null, define where to return a (scalar)
8907 value of mode MODE from a libcall. */
8908
8909 static rtx
8910 s390_function_and_libcall_value (enum machine_mode mode,
8911 const_tree ret_type,
8912 const_tree fntype_or_decl,
8913 bool outgoing ATTRIBUTE_UNUSED)
8914 {
8915 /* For normal functions perform the promotion as
8916 promote_function_mode would do. */
8917 if (ret_type)
8918 {
8919 int unsignedp = TYPE_UNSIGNED (ret_type);
8920 mode = promote_function_mode (ret_type, mode, &unsignedp,
8921 fntype_or_decl, 1);
8922 }
8923
8924 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8925 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8926
8927 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8928 return gen_rtx_REG (mode, 16);
8929 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8930 || UNITS_PER_LONG == UNITS_PER_WORD)
8931 return gen_rtx_REG (mode, 2);
8932 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8933 {
8934 /* This case is triggered when returning a 64 bit value with
8935 -m31 -mzarch. Although the value would fit into a single
8936 register it has to be forced into a 32 bit register pair in
8937 order to match the ABI. */
8938 rtvec p = rtvec_alloc (2);
8939
8940 RTVEC_ELT (p, 0)
8941 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8942 RTVEC_ELT (p, 1)
8943 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8944
8945 return gen_rtx_PARALLEL (mode, p);
8946 }
8947
8948 gcc_unreachable ();
8949 }
8950
8951 /* Define where to return a scalar return value of type RET_TYPE. */
8952
8953 static rtx
8954 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8955 bool outgoing)
8956 {
8957 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8958 fn_decl_or_type, outgoing);
8959 }
8960
8961 /* Define where to return a scalar libcall return value of mode
8962 MODE. */
8963
8964 static rtx
8965 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8966 {
8967 return s390_function_and_libcall_value (mode, NULL_TREE,
8968 NULL_TREE, true);
8969 }
8970
8971
8972 /* Create and return the va_list datatype.
8973
8974 On S/390, va_list is an array type equivalent to
8975
8976 typedef struct __va_list_tag
8977 {
8978 long __gpr;
8979 long __fpr;
8980 void *__overflow_arg_area;
8981 void *__reg_save_area;
8982 } va_list[1];
8983
8984 where __gpr and __fpr hold the number of general purpose
8985 or floating point arguments used up to now, respectively,
8986 __overflow_arg_area points to the stack location of the
8987 next argument passed on the stack, and __reg_save_area
8988 always points to the start of the register area in the
8989 call frame of the current function. The function prologue
8990 saves all registers used for argument passing into this
8991 area if the function uses variable arguments. */
8992
8993 static tree
8994 s390_build_builtin_va_list (void)
8995 {
8996 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8997
8998 record = lang_hooks.types.make_type (RECORD_TYPE);
8999
9000 type_decl =
9001 build_decl (BUILTINS_LOCATION,
9002 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9003
9004 f_gpr = build_decl (BUILTINS_LOCATION,
9005 FIELD_DECL, get_identifier ("__gpr"),
9006 long_integer_type_node);
9007 f_fpr = build_decl (BUILTINS_LOCATION,
9008 FIELD_DECL, get_identifier ("__fpr"),
9009 long_integer_type_node);
9010 f_ovf = build_decl (BUILTINS_LOCATION,
9011 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9012 ptr_type_node);
9013 f_sav = build_decl (BUILTINS_LOCATION,
9014 FIELD_DECL, get_identifier ("__reg_save_area"),
9015 ptr_type_node);
9016
9017 va_list_gpr_counter_field = f_gpr;
9018 va_list_fpr_counter_field = f_fpr;
9019
9020 DECL_FIELD_CONTEXT (f_gpr) = record;
9021 DECL_FIELD_CONTEXT (f_fpr) = record;
9022 DECL_FIELD_CONTEXT (f_ovf) = record;
9023 DECL_FIELD_CONTEXT (f_sav) = record;
9024
9025 TYPE_STUB_DECL (record) = type_decl;
9026 TYPE_NAME (record) = type_decl;
9027 TYPE_FIELDS (record) = f_gpr;
9028 DECL_CHAIN (f_gpr) = f_fpr;
9029 DECL_CHAIN (f_fpr) = f_ovf;
9030 DECL_CHAIN (f_ovf) = f_sav;
9031
9032 layout_type (record);
9033
9034 /* The correct type is an array type of one element. */
9035 return build_array_type (record, build_index_type (size_zero_node));
9036 }
9037
9038 /* Implement va_start by filling the va_list structure VALIST.
9039 STDARG_P is always true, and ignored.
9040 NEXTARG points to the first anonymous stack argument.
9041
9042 The following global variables are used to initialize
9043 the va_list structure:
9044
9045 crtl->args.info:
9046 holds number of gprs and fprs used for named arguments.
9047 crtl->args.arg_offset_rtx:
9048 holds the offset of the first anonymous stack argument
9049 (relative to the virtual arg pointer). */
9050
9051 static void
9052 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9053 {
9054 HOST_WIDE_INT n_gpr, n_fpr;
9055 int off;
9056 tree f_gpr, f_fpr, f_ovf, f_sav;
9057 tree gpr, fpr, ovf, sav, t;
9058
9059 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9060 f_fpr = DECL_CHAIN (f_gpr);
9061 f_ovf = DECL_CHAIN (f_fpr);
9062 f_sav = DECL_CHAIN (f_ovf);
9063
9064 valist = build_simple_mem_ref (valist);
9065 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9066 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9067 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9068 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9069
9070 /* Count number of gp and fp argument registers used. */
9071
9072 n_gpr = crtl->args.info.gprs;
9073 n_fpr = crtl->args.info.fprs;
9074
9075 if (cfun->va_list_gpr_size)
9076 {
9077 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9078 build_int_cst (NULL_TREE, n_gpr));
9079 TREE_SIDE_EFFECTS (t) = 1;
9080 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9081 }
9082
9083 if (cfun->va_list_fpr_size)
9084 {
9085 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9086 build_int_cst (NULL_TREE, n_fpr));
9087 TREE_SIDE_EFFECTS (t) = 1;
9088 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9089 }
9090
9091 /* Find the overflow area. */
9092 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9093 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9094 {
9095 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9096
9097 off = INTVAL (crtl->args.arg_offset_rtx);
9098 off = off < 0 ? 0 : off;
9099 if (TARGET_DEBUG_ARG)
9100 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9101 (int)n_gpr, (int)n_fpr, off);
9102
9103 t = fold_build_pointer_plus_hwi (t, off);
9104
9105 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9106 TREE_SIDE_EFFECTS (t) = 1;
9107 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9108 }
9109
9110 /* Find the register save area. */
9111 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9112 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9113 {
9114 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
9115 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
9116
9117 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9118 TREE_SIDE_EFFECTS (t) = 1;
9119 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9120 }
9121 }
9122
9123 /* Implement va_arg by updating the va_list structure
9124 VALIST as required to retrieve an argument of type
9125 TYPE, and returning that argument.
9126
9127 Generates code equivalent to:
9128
9129 if (integral value) {
9130 if (size <= 4 && args.gpr < 5 ||
9131 size > 4 && args.gpr < 4 )
9132 ret = args.reg_save_area[args.gpr+8]
9133 else
9134 ret = *args.overflow_arg_area++;
9135 } else if (float value) {
9136 if (args.fgpr < 2)
9137 ret = args.reg_save_area[args.fpr+64]
9138 else
9139 ret = *args.overflow_arg_area++;
9140 } else if (aggregate value) {
9141 if (args.gpr < 5)
9142 ret = *args.reg_save_area[args.gpr]
9143 else
9144 ret = **args.overflow_arg_area++;
9145 } */
9146
9147 static tree
9148 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9149 gimple_seq *post_p ATTRIBUTE_UNUSED)
9150 {
9151 tree f_gpr, f_fpr, f_ovf, f_sav;
9152 tree gpr, fpr, ovf, sav, reg, t, u;
9153 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
9154 tree lab_false, lab_over, addr;
9155
9156 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9157 f_fpr = DECL_CHAIN (f_gpr);
9158 f_ovf = DECL_CHAIN (f_fpr);
9159 f_sav = DECL_CHAIN (f_ovf);
9160
9161 valist = build_va_arg_indirect_ref (valist);
9162 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9163 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9164 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9165
9166 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9167 both appear on a lhs. */
9168 valist = unshare_expr (valist);
9169 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9170
9171 size = int_size_in_bytes (type);
9172
9173 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9174 {
9175 if (TARGET_DEBUG_ARG)
9176 {
9177 fprintf (stderr, "va_arg: aggregate type");
9178 debug_tree (type);
9179 }
9180
9181 /* Aggregates are passed by reference. */
9182 indirect_p = 1;
9183 reg = gpr;
9184 n_reg = 1;
9185
9186 /* kernel stack layout on 31 bit: It is assumed here that no padding
9187 will be added by s390_frame_info because for va_args always an even
9188 number of gprs has to be saved r15-r2 = 14 regs. */
9189 sav_ofs = 2 * UNITS_PER_LONG;
9190 sav_scale = UNITS_PER_LONG;
9191 size = UNITS_PER_LONG;
9192 max_reg = GP_ARG_NUM_REG - n_reg;
9193 }
9194 else if (s390_function_arg_float (TYPE_MODE (type), type))
9195 {
9196 if (TARGET_DEBUG_ARG)
9197 {
9198 fprintf (stderr, "va_arg: float type");
9199 debug_tree (type);
9200 }
9201
9202 /* FP args go in FP registers, if present. */
9203 indirect_p = 0;
9204 reg = fpr;
9205 n_reg = 1;
9206 sav_ofs = 16 * UNITS_PER_LONG;
9207 sav_scale = 8;
9208 max_reg = FP_ARG_NUM_REG - n_reg;
9209 }
9210 else
9211 {
9212 if (TARGET_DEBUG_ARG)
9213 {
9214 fprintf (stderr, "va_arg: other type");
9215 debug_tree (type);
9216 }
9217
9218 /* Otherwise into GP registers. */
9219 indirect_p = 0;
9220 reg = gpr;
9221 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9222
9223 /* kernel stack layout on 31 bit: It is assumed here that no padding
9224 will be added by s390_frame_info because for va_args always an even
9225 number of gprs has to be saved r15-r2 = 14 regs. */
9226 sav_ofs = 2 * UNITS_PER_LONG;
9227
9228 if (size < UNITS_PER_LONG)
9229 sav_ofs += UNITS_PER_LONG - size;
9230
9231 sav_scale = UNITS_PER_LONG;
9232 max_reg = GP_ARG_NUM_REG - n_reg;
9233 }
9234
9235 /* Pull the value out of the saved registers ... */
9236
9237 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9238 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9239 addr = create_tmp_var (ptr_type_node, "addr");
9240
9241 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9242 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9243 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9244 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9245 gimplify_and_add (t, pre_p);
9246
9247 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9248 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9249 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9250 t = fold_build_pointer_plus (t, u);
9251
9252 gimplify_assign (addr, t, pre_p);
9253
9254 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9255
9256 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9257
9258
9259 /* ... Otherwise out of the overflow area. */
9260
9261 t = ovf;
9262 if (size < UNITS_PER_LONG)
9263 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9264
9265 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9266
9267 gimplify_assign (addr, t, pre_p);
9268
9269 t = fold_build_pointer_plus_hwi (t, size);
9270 gimplify_assign (ovf, t, pre_p);
9271
9272 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9273
9274
9275 /* Increment register save count. */
9276
9277 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9278 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9279 gimplify_and_add (u, pre_p);
9280
9281 if (indirect_p)
9282 {
9283 t = build_pointer_type_for_mode (build_pointer_type (type),
9284 ptr_mode, true);
9285 addr = fold_convert (t, addr);
9286 addr = build_va_arg_indirect_ref (addr);
9287 }
9288 else
9289 {
9290 t = build_pointer_type_for_mode (type, ptr_mode, true);
9291 addr = fold_convert (t, addr);
9292 }
9293
9294 return build_va_arg_indirect_ref (addr);
9295 }
9296
9297
9298 /* Builtins. */
9299
9300 enum s390_builtin
9301 {
9302 S390_BUILTIN_THREAD_POINTER,
9303 S390_BUILTIN_SET_THREAD_POINTER,
9304
9305 S390_BUILTIN_max
9306 };
9307
9308 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9309 CODE_FOR_get_tp_64,
9310 CODE_FOR_set_tp_64
9311 };
9312
9313 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9314 CODE_FOR_get_tp_31,
9315 CODE_FOR_set_tp_31
9316 };
9317
9318 static void
9319 s390_init_builtins (void)
9320 {
9321 tree ftype;
9322
9323 ftype = build_function_type_list (ptr_type_node, NULL_TREE);
9324 add_builtin_function ("__builtin_thread_pointer", ftype,
9325 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9326 NULL, NULL_TREE);
9327
9328 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9329 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9330 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9331 NULL, NULL_TREE);
9332 }
9333
9334 /* Expand an expression EXP that calls a built-in function,
9335 with result going to TARGET if that's convenient
9336 (and in mode MODE if that's convenient).
9337 SUBTARGET may be used as the target for computing one of EXP's operands.
9338 IGNORE is nonzero if the value is to be ignored. */
9339
9340 static rtx
9341 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9342 enum machine_mode mode ATTRIBUTE_UNUSED,
9343 int ignore ATTRIBUTE_UNUSED)
9344 {
9345 #define MAX_ARGS 2
9346
9347 enum insn_code const *code_for_builtin =
9348 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9349
9350 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9351 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9352 enum insn_code icode;
9353 rtx op[MAX_ARGS], pat;
9354 int arity;
9355 bool nonvoid;
9356 tree arg;
9357 call_expr_arg_iterator iter;
9358
9359 if (fcode >= S390_BUILTIN_max)
9360 internal_error ("bad builtin fcode");
9361 icode = code_for_builtin[fcode];
9362 if (icode == 0)
9363 internal_error ("bad builtin fcode");
9364
9365 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9366
9367 arity = 0;
9368 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9369 {
9370 const struct insn_operand_data *insn_op;
9371
9372 if (arg == error_mark_node)
9373 return NULL_RTX;
9374 if (arity > MAX_ARGS)
9375 return NULL_RTX;
9376
9377 insn_op = &insn_data[icode].operand[arity + nonvoid];
9378
9379 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9380
9381 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9382 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9383 arity++;
9384 }
9385
9386 if (nonvoid)
9387 {
9388 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9389 if (!target
9390 || GET_MODE (target) != tmode
9391 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9392 target = gen_reg_rtx (tmode);
9393 }
9394
9395 switch (arity)
9396 {
9397 case 0:
9398 pat = GEN_FCN (icode) (target);
9399 break;
9400 case 1:
9401 if (nonvoid)
9402 pat = GEN_FCN (icode) (target, op[0]);
9403 else
9404 pat = GEN_FCN (icode) (op[0]);
9405 break;
9406 case 2:
9407 pat = GEN_FCN (icode) (target, op[0], op[1]);
9408 break;
9409 default:
9410 gcc_unreachable ();
9411 }
9412 if (!pat)
9413 return NULL_RTX;
9414 emit_insn (pat);
9415
9416 if (nonvoid)
9417 return target;
9418 else
9419 return const0_rtx;
9420 }
9421
9422
9423 /* Output assembly code for the trampoline template to
9424 stdio stream FILE.
9425
9426 On S/390, we use gpr 1 internally in the trampoline code;
9427 gpr 0 is used to hold the static chain. */
9428
9429 static void
9430 s390_asm_trampoline_template (FILE *file)
9431 {
9432 rtx op[2];
9433 op[0] = gen_rtx_REG (Pmode, 0);
9434 op[1] = gen_rtx_REG (Pmode, 1);
9435
9436 if (TARGET_64BIT)
9437 {
9438 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9439 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9440 output_asm_insn ("br\t%1", op); /* 2 byte */
9441 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9442 }
9443 else
9444 {
9445 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9446 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9447 output_asm_insn ("br\t%1", op); /* 2 byte */
9448 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9449 }
9450 }
9451
9452 /* Emit RTL insns to initialize the variable parts of a trampoline.
9453 FNADDR is an RTX for the address of the function's pure code.
9454 CXT is an RTX for the static chain value for the function. */
9455
9456 static void
9457 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9458 {
9459 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9460 rtx mem;
9461
9462 emit_block_move (m_tramp, assemble_trampoline_template (),
9463 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9464
9465 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9466 emit_move_insn (mem, cxt);
9467 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9468 emit_move_insn (mem, fnaddr);
9469 }
9470
9471 /* Output assembler code to FILE to increment profiler label # LABELNO
9472 for profiling a function entry. */
9473
9474 void
9475 s390_function_profiler (FILE *file, int labelno)
9476 {
9477 rtx op[7];
9478
9479 char label[128];
9480 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9481
9482 fprintf (file, "# function profiler \n");
9483
9484 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9485 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9486 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9487
9488 op[2] = gen_rtx_REG (Pmode, 1);
9489 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9490 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9491
9492 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9493 if (flag_pic)
9494 {
9495 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9496 op[4] = gen_rtx_CONST (Pmode, op[4]);
9497 }
9498
9499 if (TARGET_64BIT)
9500 {
9501 output_asm_insn ("stg\t%0,%1", op);
9502 output_asm_insn ("larl\t%2,%3", op);
9503 output_asm_insn ("brasl\t%0,%4", op);
9504 output_asm_insn ("lg\t%0,%1", op);
9505 }
9506 else if (!flag_pic)
9507 {
9508 op[6] = gen_label_rtx ();
9509
9510 output_asm_insn ("st\t%0,%1", op);
9511 output_asm_insn ("bras\t%2,%l6", op);
9512 output_asm_insn (".long\t%4", op);
9513 output_asm_insn (".long\t%3", op);
9514 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9515 output_asm_insn ("l\t%0,0(%2)", op);
9516 output_asm_insn ("l\t%2,4(%2)", op);
9517 output_asm_insn ("basr\t%0,%0", op);
9518 output_asm_insn ("l\t%0,%1", op);
9519 }
9520 else
9521 {
9522 op[5] = gen_label_rtx ();
9523 op[6] = gen_label_rtx ();
9524
9525 output_asm_insn ("st\t%0,%1", op);
9526 output_asm_insn ("bras\t%2,%l6", op);
9527 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9528 output_asm_insn (".long\t%4-%l5", op);
9529 output_asm_insn (".long\t%3-%l5", op);
9530 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9531 output_asm_insn ("lr\t%0,%2", op);
9532 output_asm_insn ("a\t%0,0(%2)", op);
9533 output_asm_insn ("a\t%2,4(%2)", op);
9534 output_asm_insn ("basr\t%0,%0", op);
9535 output_asm_insn ("l\t%0,%1", op);
9536 }
9537 }
9538
9539 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9540 into its SYMBOL_REF_FLAGS. */
9541
9542 static void
9543 s390_encode_section_info (tree decl, rtx rtl, int first)
9544 {
9545 default_encode_section_info (decl, rtl, first);
9546
9547 if (TREE_CODE (decl) == VAR_DECL)
9548 {
9549 /* If a variable has a forced alignment to < 2 bytes, mark it
9550 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9551 operand. */
9552 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9553 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9554 if (!DECL_SIZE (decl)
9555 || !DECL_ALIGN (decl)
9556 || !host_integerp (DECL_SIZE (decl), 0)
9557 || (DECL_ALIGN (decl) <= 64
9558 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9559 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9560 }
9561
9562 /* Literal pool references don't have a decl so they are handled
9563 differently here. We rely on the information in the MEM_ALIGN
9564 entry to decide upon natural alignment. */
9565 if (MEM_P (rtl)
9566 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9567 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9568 && (MEM_ALIGN (rtl) == 0
9569 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9570 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9571 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9572 }
9573
9574 /* Output thunk to FILE that implements a C++ virtual function call (with
9575 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9576 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9577 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9578 relative to the resulting this pointer. */
9579
9580 static void
9581 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9582 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9583 tree function)
9584 {
9585 rtx op[10];
9586 int nonlocal = 0;
9587
9588 /* Make sure unwind info is emitted for the thunk if needed. */
9589 final_start_function (emit_barrier (), file, 1);
9590
9591 /* Operand 0 is the target function. */
9592 op[0] = XEXP (DECL_RTL (function), 0);
9593 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9594 {
9595 nonlocal = 1;
9596 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9597 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9598 op[0] = gen_rtx_CONST (Pmode, op[0]);
9599 }
9600
9601 /* Operand 1 is the 'this' pointer. */
9602 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9603 op[1] = gen_rtx_REG (Pmode, 3);
9604 else
9605 op[1] = gen_rtx_REG (Pmode, 2);
9606
9607 /* Operand 2 is the delta. */
9608 op[2] = GEN_INT (delta);
9609
9610 /* Operand 3 is the vcall_offset. */
9611 op[3] = GEN_INT (vcall_offset);
9612
9613 /* Operand 4 is the temporary register. */
9614 op[4] = gen_rtx_REG (Pmode, 1);
9615
9616 /* Operands 5 to 8 can be used as labels. */
9617 op[5] = NULL_RTX;
9618 op[6] = NULL_RTX;
9619 op[7] = NULL_RTX;
9620 op[8] = NULL_RTX;
9621
9622 /* Operand 9 can be used for temporary register. */
9623 op[9] = NULL_RTX;
9624
9625 /* Generate code. */
9626 if (TARGET_64BIT)
9627 {
9628 /* Setup literal pool pointer if required. */
9629 if ((!DISP_IN_RANGE (delta)
9630 && !CONST_OK_FOR_K (delta)
9631 && !CONST_OK_FOR_Os (delta))
9632 || (!DISP_IN_RANGE (vcall_offset)
9633 && !CONST_OK_FOR_K (vcall_offset)
9634 && !CONST_OK_FOR_Os (vcall_offset)))
9635 {
9636 op[5] = gen_label_rtx ();
9637 output_asm_insn ("larl\t%4,%5", op);
9638 }
9639
9640 /* Add DELTA to this pointer. */
9641 if (delta)
9642 {
9643 if (CONST_OK_FOR_J (delta))
9644 output_asm_insn ("la\t%1,%2(%1)", op);
9645 else if (DISP_IN_RANGE (delta))
9646 output_asm_insn ("lay\t%1,%2(%1)", op);
9647 else if (CONST_OK_FOR_K (delta))
9648 output_asm_insn ("aghi\t%1,%2", op);
9649 else if (CONST_OK_FOR_Os (delta))
9650 output_asm_insn ("agfi\t%1,%2", op);
9651 else
9652 {
9653 op[6] = gen_label_rtx ();
9654 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9655 }
9656 }
9657
9658 /* Perform vcall adjustment. */
9659 if (vcall_offset)
9660 {
9661 if (DISP_IN_RANGE (vcall_offset))
9662 {
9663 output_asm_insn ("lg\t%4,0(%1)", op);
9664 output_asm_insn ("ag\t%1,%3(%4)", op);
9665 }
9666 else if (CONST_OK_FOR_K (vcall_offset))
9667 {
9668 output_asm_insn ("lghi\t%4,%3", op);
9669 output_asm_insn ("ag\t%4,0(%1)", op);
9670 output_asm_insn ("ag\t%1,0(%4)", op);
9671 }
9672 else if (CONST_OK_FOR_Os (vcall_offset))
9673 {
9674 output_asm_insn ("lgfi\t%4,%3", op);
9675 output_asm_insn ("ag\t%4,0(%1)", op);
9676 output_asm_insn ("ag\t%1,0(%4)", op);
9677 }
9678 else
9679 {
9680 op[7] = gen_label_rtx ();
9681 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9682 output_asm_insn ("ag\t%4,0(%1)", op);
9683 output_asm_insn ("ag\t%1,0(%4)", op);
9684 }
9685 }
9686
9687 /* Jump to target. */
9688 output_asm_insn ("jg\t%0", op);
9689
9690 /* Output literal pool if required. */
9691 if (op[5])
9692 {
9693 output_asm_insn (".align\t4", op);
9694 targetm.asm_out.internal_label (file, "L",
9695 CODE_LABEL_NUMBER (op[5]));
9696 }
9697 if (op[6])
9698 {
9699 targetm.asm_out.internal_label (file, "L",
9700 CODE_LABEL_NUMBER (op[6]));
9701 output_asm_insn (".long\t%2", op);
9702 }
9703 if (op[7])
9704 {
9705 targetm.asm_out.internal_label (file, "L",
9706 CODE_LABEL_NUMBER (op[7]));
9707 output_asm_insn (".long\t%3", op);
9708 }
9709 }
9710 else
9711 {
9712 /* Setup base pointer if required. */
9713 if (!vcall_offset
9714 || (!DISP_IN_RANGE (delta)
9715 && !CONST_OK_FOR_K (delta)
9716 && !CONST_OK_FOR_Os (delta))
9717 || (!DISP_IN_RANGE (delta)
9718 && !CONST_OK_FOR_K (vcall_offset)
9719 && !CONST_OK_FOR_Os (vcall_offset)))
9720 {
9721 op[5] = gen_label_rtx ();
9722 output_asm_insn ("basr\t%4,0", op);
9723 targetm.asm_out.internal_label (file, "L",
9724 CODE_LABEL_NUMBER (op[5]));
9725 }
9726
9727 /* Add DELTA to this pointer. */
9728 if (delta)
9729 {
9730 if (CONST_OK_FOR_J (delta))
9731 output_asm_insn ("la\t%1,%2(%1)", op);
9732 else if (DISP_IN_RANGE (delta))
9733 output_asm_insn ("lay\t%1,%2(%1)", op);
9734 else if (CONST_OK_FOR_K (delta))
9735 output_asm_insn ("ahi\t%1,%2", op);
9736 else if (CONST_OK_FOR_Os (delta))
9737 output_asm_insn ("afi\t%1,%2", op);
9738 else
9739 {
9740 op[6] = gen_label_rtx ();
9741 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9742 }
9743 }
9744
9745 /* Perform vcall adjustment. */
9746 if (vcall_offset)
9747 {
9748 if (CONST_OK_FOR_J (vcall_offset))
9749 {
9750 output_asm_insn ("l\t%4,0(%1)", op);
9751 output_asm_insn ("a\t%1,%3(%4)", op);
9752 }
9753 else if (DISP_IN_RANGE (vcall_offset))
9754 {
9755 output_asm_insn ("l\t%4,0(%1)", op);
9756 output_asm_insn ("ay\t%1,%3(%4)", op);
9757 }
9758 else if (CONST_OK_FOR_K (vcall_offset))
9759 {
9760 output_asm_insn ("lhi\t%4,%3", op);
9761 output_asm_insn ("a\t%4,0(%1)", op);
9762 output_asm_insn ("a\t%1,0(%4)", op);
9763 }
9764 else if (CONST_OK_FOR_Os (vcall_offset))
9765 {
9766 output_asm_insn ("iilf\t%4,%3", op);
9767 output_asm_insn ("a\t%4,0(%1)", op);
9768 output_asm_insn ("a\t%1,0(%4)", op);
9769 }
9770 else
9771 {
9772 op[7] = gen_label_rtx ();
9773 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9774 output_asm_insn ("a\t%4,0(%1)", op);
9775 output_asm_insn ("a\t%1,0(%4)", op);
9776 }
9777
9778 /* We had to clobber the base pointer register.
9779 Re-setup the base pointer (with a different base). */
9780 op[5] = gen_label_rtx ();
9781 output_asm_insn ("basr\t%4,0", op);
9782 targetm.asm_out.internal_label (file, "L",
9783 CODE_LABEL_NUMBER (op[5]));
9784 }
9785
9786 /* Jump to target. */
9787 op[8] = gen_label_rtx ();
9788
9789 if (!flag_pic)
9790 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9791 else if (!nonlocal)
9792 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9793 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9794 else if (flag_pic == 1)
9795 {
9796 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9797 output_asm_insn ("l\t%4,%0(%4)", op);
9798 }
9799 else if (flag_pic == 2)
9800 {
9801 op[9] = gen_rtx_REG (Pmode, 0);
9802 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9803 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9804 output_asm_insn ("ar\t%4,%9", op);
9805 output_asm_insn ("l\t%4,0(%4)", op);
9806 }
9807
9808 output_asm_insn ("br\t%4", op);
9809
9810 /* Output literal pool. */
9811 output_asm_insn (".align\t4", op);
9812
9813 if (nonlocal && flag_pic == 2)
9814 output_asm_insn (".long\t%0", op);
9815 if (nonlocal)
9816 {
9817 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9818 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9819 }
9820
9821 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9822 if (!flag_pic)
9823 output_asm_insn (".long\t%0", op);
9824 else
9825 output_asm_insn (".long\t%0-%5", op);
9826
9827 if (op[6])
9828 {
9829 targetm.asm_out.internal_label (file, "L",
9830 CODE_LABEL_NUMBER (op[6]));
9831 output_asm_insn (".long\t%2", op);
9832 }
9833 if (op[7])
9834 {
9835 targetm.asm_out.internal_label (file, "L",
9836 CODE_LABEL_NUMBER (op[7]));
9837 output_asm_insn (".long\t%3", op);
9838 }
9839 }
9840 final_end_function ();
9841 }
9842
9843 static bool
9844 s390_valid_pointer_mode (enum machine_mode mode)
9845 {
9846 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9847 }
9848
9849 /* Checks whether the given CALL_EXPR would use a caller
9850 saved register. This is used to decide whether sibling call
9851 optimization could be performed on the respective function
9852 call. */
9853
9854 static bool
9855 s390_call_saved_register_used (tree call_expr)
9856 {
9857 CUMULATIVE_ARGS cum_v;
9858 cumulative_args_t cum;
9859 tree parameter;
9860 enum machine_mode mode;
9861 tree type;
9862 rtx parm_rtx;
9863 int reg, i;
9864
9865 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9866 cum = pack_cumulative_args (&cum_v);
9867
9868 for (i = 0; i < call_expr_nargs (call_expr); i++)
9869 {
9870 parameter = CALL_EXPR_ARG (call_expr, i);
9871 gcc_assert (parameter);
9872
9873 /* For an undeclared variable passed as parameter we will get
9874 an ERROR_MARK node here. */
9875 if (TREE_CODE (parameter) == ERROR_MARK)
9876 return true;
9877
9878 type = TREE_TYPE (parameter);
9879 gcc_assert (type);
9880
9881 mode = TYPE_MODE (type);
9882 gcc_assert (mode);
9883
9884 if (pass_by_reference (&cum_v, mode, type, true))
9885 {
9886 mode = Pmode;
9887 type = build_pointer_type (type);
9888 }
9889
9890 parm_rtx = s390_function_arg (cum, mode, type, 0);
9891
9892 s390_function_arg_advance (cum, mode, type, 0);
9893
9894 if (!parm_rtx)
9895 continue;
9896
9897 if (REG_P (parm_rtx))
9898 {
9899 for (reg = 0;
9900 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9901 reg++)
9902 if (!call_used_regs[reg + REGNO (parm_rtx)])
9903 return true;
9904 }
9905
9906 if (GET_CODE (parm_rtx) == PARALLEL)
9907 {
9908 int i;
9909
9910 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9911 {
9912 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9913
9914 gcc_assert (REG_P (r));
9915
9916 for (reg = 0;
9917 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9918 reg++)
9919 if (!call_used_regs[reg + REGNO (r)])
9920 return true;
9921 }
9922 }
9923
9924 }
9925 return false;
9926 }
9927
9928 /* Return true if the given call expression can be
9929 turned into a sibling call.
9930 DECL holds the declaration of the function to be called whereas
9931 EXP is the call expression itself. */
9932
9933 static bool
9934 s390_function_ok_for_sibcall (tree decl, tree exp)
9935 {
9936 /* The TPF epilogue uses register 1. */
9937 if (TARGET_TPF_PROFILING)
9938 return false;
9939
9940 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9941 which would have to be restored before the sibcall. */
9942 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9943 return false;
9944
9945 /* Register 6 on s390 is available as an argument register but unfortunately
9946 "caller saved". This makes functions needing this register for arguments
9947 not suitable for sibcalls. */
9948 return !s390_call_saved_register_used (exp);
9949 }
9950
9951 /* Return the fixed registers used for condition codes. */
9952
9953 static bool
9954 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9955 {
9956 *p1 = CC_REGNUM;
9957 *p2 = INVALID_REGNUM;
9958
9959 return true;
9960 }
9961
9962 /* This function is used by the call expanders of the machine description.
9963 It emits the call insn itself together with the necessary operations
9964 to adjust the target address and returns the emitted insn.
9965 ADDR_LOCATION is the target address rtx
9966 TLS_CALL the location of the thread-local symbol
9967 RESULT_REG the register where the result of the call should be stored
9968 RETADDR_REG the register where the return address should be stored
9969 If this parameter is NULL_RTX the call is considered
9970 to be a sibling call. */
9971
9972 rtx
9973 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9974 rtx retaddr_reg)
9975 {
9976 bool plt_call = false;
9977 rtx insn;
9978 rtx call;
9979 rtx clobber;
9980 rtvec vec;
9981
9982 /* Direct function calls need special treatment. */
9983 if (GET_CODE (addr_location) == SYMBOL_REF)
9984 {
9985 /* When calling a global routine in PIC mode, we must
9986 replace the symbol itself with the PLT stub. */
9987 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9988 {
9989 if (retaddr_reg != NULL_RTX)
9990 {
9991 addr_location = gen_rtx_UNSPEC (Pmode,
9992 gen_rtvec (1, addr_location),
9993 UNSPEC_PLT);
9994 addr_location = gen_rtx_CONST (Pmode, addr_location);
9995 plt_call = true;
9996 }
9997 else
9998 /* For -fpic code the PLT entries might use r12 which is
9999 call-saved. Therefore we cannot do a sibcall when
10000 calling directly using a symbol ref. When reaching
10001 this point we decided (in s390_function_ok_for_sibcall)
10002 to do a sibcall for a function pointer but one of the
10003 optimizers was able to get rid of the function pointer
10004 by propagating the symbol ref into the call. This
10005 optimization is illegal for S/390 so we turn the direct
10006 call into a indirect call again. */
10007 addr_location = force_reg (Pmode, addr_location);
10008 }
10009
10010 /* Unless we can use the bras(l) insn, force the
10011 routine address into a register. */
10012 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10013 {
10014 if (flag_pic)
10015 addr_location = legitimize_pic_address (addr_location, 0);
10016 else
10017 addr_location = force_reg (Pmode, addr_location);
10018 }
10019 }
10020
10021 /* If it is already an indirect call or the code above moved the
10022 SYMBOL_REF to somewhere else make sure the address can be found in
10023 register 1. */
10024 if (retaddr_reg == NULL_RTX
10025 && GET_CODE (addr_location) != SYMBOL_REF
10026 && !plt_call)
10027 {
10028 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10029 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
10030 }
10031
10032 addr_location = gen_rtx_MEM (QImode, addr_location);
10033 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
10034
10035 if (result_reg != NULL_RTX)
10036 call = gen_rtx_SET (VOIDmode, result_reg, call);
10037
10038 if (retaddr_reg != NULL_RTX)
10039 {
10040 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
10041
10042 if (tls_call != NULL_RTX)
10043 vec = gen_rtvec (3, call, clobber,
10044 gen_rtx_USE (VOIDmode, tls_call));
10045 else
10046 vec = gen_rtvec (2, call, clobber);
10047
10048 call = gen_rtx_PARALLEL (VOIDmode, vec);
10049 }
10050
10051 insn = emit_call_insn (call);
10052
10053 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10054 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10055 {
10056 /* s390_function_ok_for_sibcall should
10057 have denied sibcalls in this case. */
10058 gcc_assert (retaddr_reg != NULL_RTX);
10059 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
10060 }
10061 return insn;
10062 }
10063
10064 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10065
10066 static void
10067 s390_conditional_register_usage (void)
10068 {
10069 int i;
10070
10071 if (flag_pic)
10072 {
10073 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10074 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10075 }
10076 if (TARGET_CPU_ZARCH)
10077 {
10078 fixed_regs[BASE_REGNUM] = 0;
10079 call_used_regs[BASE_REGNUM] = 0;
10080 fixed_regs[RETURN_REGNUM] = 0;
10081 call_used_regs[RETURN_REGNUM] = 0;
10082 }
10083 if (TARGET_64BIT)
10084 {
10085 for (i = 24; i < 32; i++)
10086 call_used_regs[i] = call_really_used_regs[i] = 0;
10087 }
10088 else
10089 {
10090 for (i = 18; i < 20; i++)
10091 call_used_regs[i] = call_really_used_regs[i] = 0;
10092 }
10093
10094 if (TARGET_SOFT_FLOAT)
10095 {
10096 for (i = 16; i < 32; i++)
10097 call_used_regs[i] = fixed_regs[i] = 1;
10098 }
10099 }
10100
10101 /* Corresponding function to eh_return expander. */
10102
10103 static GTY(()) rtx s390_tpf_eh_return_symbol;
10104 void
10105 s390_emit_tpf_eh_return (rtx target)
10106 {
10107 rtx insn, reg;
10108
10109 if (!s390_tpf_eh_return_symbol)
10110 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10111
10112 reg = gen_rtx_REG (Pmode, 2);
10113
10114 emit_move_insn (reg, target);
10115 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10116 gen_rtx_REG (Pmode, RETURN_REGNUM));
10117 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
10118
10119 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
10120 }
10121
10122 /* Rework the prologue/epilogue to avoid saving/restoring
10123 registers unnecessarily. */
10124
10125 static void
10126 s390_optimize_prologue (void)
10127 {
10128 rtx insn, new_insn, next_insn;
10129
10130 /* Do a final recompute of the frame-related data. */
10131
10132 s390_update_frame_layout ();
10133
10134 /* If all special registers are in fact used, there's nothing we
10135 can do, so no point in walking the insn list. */
10136
10137 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
10138 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
10139 && (TARGET_CPU_ZARCH
10140 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
10141 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10142 return;
10143
10144 /* Search for prologue/epilogue insns and replace them. */
10145
10146 for (insn = get_insns (); insn; insn = next_insn)
10147 {
10148 int first, last, off;
10149 rtx set, base, offset;
10150
10151 next_insn = NEXT_INSN (insn);
10152
10153 if (GET_CODE (insn) != INSN)
10154 continue;
10155
10156 if (GET_CODE (PATTERN (insn)) == PARALLEL
10157 && store_multiple_operation (PATTERN (insn), VOIDmode))
10158 {
10159 set = XVECEXP (PATTERN (insn), 0, 0);
10160 first = REGNO (SET_SRC (set));
10161 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10162 offset = const0_rtx;
10163 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10164 off = INTVAL (offset);
10165
10166 if (GET_CODE (base) != REG || off < 0)
10167 continue;
10168 if (cfun_frame_layout.first_save_gpr != -1
10169 && (cfun_frame_layout.first_save_gpr < first
10170 || cfun_frame_layout.last_save_gpr > last))
10171 continue;
10172 if (REGNO (base) != STACK_POINTER_REGNUM
10173 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10174 continue;
10175 if (first > BASE_REGNUM || last < BASE_REGNUM)
10176 continue;
10177
10178 if (cfun_frame_layout.first_save_gpr != -1)
10179 {
10180 new_insn = save_gprs (base,
10181 off + (cfun_frame_layout.first_save_gpr
10182 - first) * UNITS_PER_LONG,
10183 cfun_frame_layout.first_save_gpr,
10184 cfun_frame_layout.last_save_gpr);
10185 new_insn = emit_insn_before (new_insn, insn);
10186 INSN_ADDRESSES_NEW (new_insn, -1);
10187 }
10188
10189 remove_insn (insn);
10190 continue;
10191 }
10192
10193 if (cfun_frame_layout.first_save_gpr == -1
10194 && GET_CODE (PATTERN (insn)) == SET
10195 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10196 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10197 || (!TARGET_CPU_ZARCH
10198 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10199 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10200 {
10201 set = PATTERN (insn);
10202 first = REGNO (SET_SRC (set));
10203 offset = const0_rtx;
10204 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10205 off = INTVAL (offset);
10206
10207 if (GET_CODE (base) != REG || off < 0)
10208 continue;
10209 if (REGNO (base) != STACK_POINTER_REGNUM
10210 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10211 continue;
10212
10213 remove_insn (insn);
10214 continue;
10215 }
10216
10217 if (GET_CODE (PATTERN (insn)) == PARALLEL
10218 && load_multiple_operation (PATTERN (insn), VOIDmode))
10219 {
10220 set = XVECEXP (PATTERN (insn), 0, 0);
10221 first = REGNO (SET_DEST (set));
10222 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10223 offset = const0_rtx;
10224 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10225 off = INTVAL (offset);
10226
10227 if (GET_CODE (base) != REG || off < 0)
10228 continue;
10229 if (cfun_frame_layout.first_restore_gpr != -1
10230 && (cfun_frame_layout.first_restore_gpr < first
10231 || cfun_frame_layout.last_restore_gpr > last))
10232 continue;
10233 if (REGNO (base) != STACK_POINTER_REGNUM
10234 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10235 continue;
10236 if (first > BASE_REGNUM || last < BASE_REGNUM)
10237 continue;
10238
10239 if (cfun_frame_layout.first_restore_gpr != -1)
10240 {
10241 new_insn = restore_gprs (base,
10242 off + (cfun_frame_layout.first_restore_gpr
10243 - first) * UNITS_PER_LONG,
10244 cfun_frame_layout.first_restore_gpr,
10245 cfun_frame_layout.last_restore_gpr);
10246 new_insn = emit_insn_before (new_insn, insn);
10247 INSN_ADDRESSES_NEW (new_insn, -1);
10248 }
10249
10250 remove_insn (insn);
10251 continue;
10252 }
10253
10254 if (cfun_frame_layout.first_restore_gpr == -1
10255 && GET_CODE (PATTERN (insn)) == SET
10256 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10257 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10258 || (!TARGET_CPU_ZARCH
10259 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10260 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10261 {
10262 set = PATTERN (insn);
10263 first = REGNO (SET_DEST (set));
10264 offset = const0_rtx;
10265 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10266 off = INTVAL (offset);
10267
10268 if (GET_CODE (base) != REG || off < 0)
10269 continue;
10270 if (REGNO (base) != STACK_POINTER_REGNUM
10271 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10272 continue;
10273
10274 remove_insn (insn);
10275 continue;
10276 }
10277 }
10278 }
10279
10280 /* On z10 and later the dynamic branch prediction must see the
10281 backward jump within a certain windows. If not it falls back to
10282 the static prediction. This function rearranges the loop backward
10283 branch in a way which makes the static prediction always correct.
10284 The function returns true if it added an instruction. */
10285 static bool
10286 s390_fix_long_loop_prediction (rtx insn)
10287 {
10288 rtx set = single_set (insn);
10289 rtx code_label, label_ref, new_label;
10290 rtx uncond_jump;
10291 rtx cur_insn;
10292 rtx tmp;
10293 int distance;
10294
10295 /* This will exclude branch on count and branch on index patterns
10296 since these are correctly statically predicted. */
10297 if (!set
10298 || SET_DEST (set) != pc_rtx
10299 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10300 return false;
10301
10302 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10303 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10304
10305 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10306
10307 code_label = XEXP (label_ref, 0);
10308
10309 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10310 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10311 || (INSN_ADDRESSES (INSN_UID (insn))
10312 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10313 return false;
10314
10315 for (distance = 0, cur_insn = PREV_INSN (insn);
10316 distance < PREDICT_DISTANCE - 6;
10317 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10318 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10319 return false;
10320
10321 new_label = gen_label_rtx ();
10322 uncond_jump = emit_jump_insn_after (
10323 gen_rtx_SET (VOIDmode, pc_rtx,
10324 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10325 insn);
10326 emit_label_after (new_label, uncond_jump);
10327
10328 tmp = XEXP (SET_SRC (set), 1);
10329 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10330 XEXP (SET_SRC (set), 2) = tmp;
10331 INSN_CODE (insn) = -1;
10332
10333 XEXP (label_ref, 0) = new_label;
10334 JUMP_LABEL (insn) = new_label;
10335 JUMP_LABEL (uncond_jump) = code_label;
10336
10337 return true;
10338 }
10339
10340 /* Returns 1 if INSN reads the value of REG for purposes not related
10341 to addressing of memory, and 0 otherwise. */
10342 static int
10343 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10344 {
10345 return reg_referenced_p (reg, PATTERN (insn))
10346 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10347 }
10348
10349 /* Starting from INSN find_cond_jump looks downwards in the insn
10350 stream for a single jump insn which is the last user of the
10351 condition code set in INSN. */
10352 static rtx
10353 find_cond_jump (rtx insn)
10354 {
10355 for (; insn; insn = NEXT_INSN (insn))
10356 {
10357 rtx ite, cc;
10358
10359 if (LABEL_P (insn))
10360 break;
10361
10362 if (!JUMP_P (insn))
10363 {
10364 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10365 break;
10366 continue;
10367 }
10368
10369 /* This will be triggered by a return. */
10370 if (GET_CODE (PATTERN (insn)) != SET)
10371 break;
10372
10373 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10374 ite = SET_SRC (PATTERN (insn));
10375
10376 if (GET_CODE (ite) != IF_THEN_ELSE)
10377 break;
10378
10379 cc = XEXP (XEXP (ite, 0), 0);
10380 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10381 break;
10382
10383 if (find_reg_note (insn, REG_DEAD, cc))
10384 return insn;
10385 break;
10386 }
10387
10388 return NULL_RTX;
10389 }
10390
10391 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10392 the semantics does not change. If NULL_RTX is passed as COND the
10393 function tries to find the conditional jump starting with INSN. */
10394 static void
10395 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10396 {
10397 rtx tmp = *op0;
10398
10399 if (cond == NULL_RTX)
10400 {
10401 rtx jump = find_cond_jump (NEXT_INSN (insn));
10402 jump = jump ? single_set (jump) : NULL_RTX;
10403
10404 if (jump == NULL_RTX)
10405 return;
10406
10407 cond = XEXP (XEXP (jump, 1), 0);
10408 }
10409
10410 *op0 = *op1;
10411 *op1 = tmp;
10412 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10413 }
10414
10415 /* On z10, instructions of the compare-and-branch family have the
10416 property to access the register occurring as second operand with
10417 its bits complemented. If such a compare is grouped with a second
10418 instruction that accesses the same register non-complemented, and
10419 if that register's value is delivered via a bypass, then the
10420 pipeline recycles, thereby causing significant performance decline.
10421 This function locates such situations and exchanges the two
10422 operands of the compare. The function return true whenever it
10423 added an insn. */
10424 static bool
10425 s390_z10_optimize_cmp (rtx insn)
10426 {
10427 rtx prev_insn, next_insn;
10428 bool insn_added_p = false;
10429 rtx cond, *op0, *op1;
10430
10431 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10432 {
10433 /* Handle compare and branch and branch on count
10434 instructions. */
10435 rtx pattern = single_set (insn);
10436
10437 if (!pattern
10438 || SET_DEST (pattern) != pc_rtx
10439 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10440 return false;
10441
10442 cond = XEXP (SET_SRC (pattern), 0);
10443 op0 = &XEXP (cond, 0);
10444 op1 = &XEXP (cond, 1);
10445 }
10446 else if (GET_CODE (PATTERN (insn)) == SET)
10447 {
10448 rtx src, dest;
10449
10450 /* Handle normal compare instructions. */
10451 src = SET_SRC (PATTERN (insn));
10452 dest = SET_DEST (PATTERN (insn));
10453
10454 if (!REG_P (dest)
10455 || !CC_REGNO_P (REGNO (dest))
10456 || GET_CODE (src) != COMPARE)
10457 return false;
10458
10459 /* s390_swap_cmp will try to find the conditional
10460 jump when passing NULL_RTX as condition. */
10461 cond = NULL_RTX;
10462 op0 = &XEXP (src, 0);
10463 op1 = &XEXP (src, 1);
10464 }
10465 else
10466 return false;
10467
10468 if (!REG_P (*op0) || !REG_P (*op1))
10469 return false;
10470
10471 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10472 return false;
10473
10474 /* Swap the COMPARE arguments and its mask if there is a
10475 conflicting access in the previous insn. */
10476 prev_insn = prev_active_insn (insn);
10477 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10478 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10479 s390_swap_cmp (cond, op0, op1, insn);
10480
10481 /* Check if there is a conflict with the next insn. If there
10482 was no conflict with the previous insn, then swap the
10483 COMPARE arguments and its mask. If we already swapped
10484 the operands, or if swapping them would cause a conflict
10485 with the previous insn, issue a NOP after the COMPARE in
10486 order to separate the two instuctions. */
10487 next_insn = next_active_insn (insn);
10488 if (next_insn != NULL_RTX && INSN_P (next_insn)
10489 && s390_non_addr_reg_read_p (*op1, next_insn))
10490 {
10491 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10492 && s390_non_addr_reg_read_p (*op0, prev_insn))
10493 {
10494 if (REGNO (*op1) == 0)
10495 emit_insn_after (gen_nop1 (), insn);
10496 else
10497 emit_insn_after (gen_nop (), insn);
10498 insn_added_p = true;
10499 }
10500 else
10501 s390_swap_cmp (cond, op0, op1, insn);
10502 }
10503 return insn_added_p;
10504 }
10505
10506 /* Perform machine-dependent processing. */
10507
10508 static void
10509 s390_reorg (void)
10510 {
10511 bool pool_overflow = false;
10512
10513 /* Make sure all splits have been performed; splits after
10514 machine_dependent_reorg might confuse insn length counts. */
10515 split_all_insns_noflow ();
10516
10517 /* Install the main literal pool and the associated base
10518 register load insns.
10519
10520 In addition, there are two problematic situations we need
10521 to correct:
10522
10523 - the literal pool might be > 4096 bytes in size, so that
10524 some of its elements cannot be directly accessed
10525
10526 - a branch target might be > 64K away from the branch, so that
10527 it is not possible to use a PC-relative instruction.
10528
10529 To fix those, we split the single literal pool into multiple
10530 pool chunks, reloading the pool base register at various
10531 points throughout the function to ensure it always points to
10532 the pool chunk the following code expects, and / or replace
10533 PC-relative branches by absolute branches.
10534
10535 However, the two problems are interdependent: splitting the
10536 literal pool can move a branch further away from its target,
10537 causing the 64K limit to overflow, and on the other hand,
10538 replacing a PC-relative branch by an absolute branch means
10539 we need to put the branch target address into the literal
10540 pool, possibly causing it to overflow.
10541
10542 So, we loop trying to fix up both problems until we manage
10543 to satisfy both conditions at the same time. Note that the
10544 loop is guaranteed to terminate as every pass of the loop
10545 strictly decreases the total number of PC-relative branches
10546 in the function. (This is not completely true as there
10547 might be branch-over-pool insns introduced by chunkify_start.
10548 Those never need to be split however.) */
10549
10550 for (;;)
10551 {
10552 struct constant_pool *pool = NULL;
10553
10554 /* Collect the literal pool. */
10555 if (!pool_overflow)
10556 {
10557 pool = s390_mainpool_start ();
10558 if (!pool)
10559 pool_overflow = true;
10560 }
10561
10562 /* If literal pool overflowed, start to chunkify it. */
10563 if (pool_overflow)
10564 pool = s390_chunkify_start ();
10565
10566 /* Split out-of-range branches. If this has created new
10567 literal pool entries, cancel current chunk list and
10568 recompute it. zSeries machines have large branch
10569 instructions, so we never need to split a branch. */
10570 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10571 {
10572 if (pool_overflow)
10573 s390_chunkify_cancel (pool);
10574 else
10575 s390_mainpool_cancel (pool);
10576
10577 continue;
10578 }
10579
10580 /* If we made it up to here, both conditions are satisfied.
10581 Finish up literal pool related changes. */
10582 if (pool_overflow)
10583 s390_chunkify_finish (pool);
10584 else
10585 s390_mainpool_finish (pool);
10586
10587 /* We're done splitting branches. */
10588 cfun->machine->split_branches_pending_p = false;
10589 break;
10590 }
10591
10592 /* Generate out-of-pool execute target insns. */
10593 if (TARGET_CPU_ZARCH)
10594 {
10595 rtx insn, label, target;
10596
10597 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10598 {
10599 label = s390_execute_label (insn);
10600 if (!label)
10601 continue;
10602
10603 gcc_assert (label != const0_rtx);
10604
10605 target = emit_label (XEXP (label, 0));
10606 INSN_ADDRESSES_NEW (target, -1);
10607
10608 target = emit_insn (s390_execute_target (insn));
10609 INSN_ADDRESSES_NEW (target, -1);
10610 }
10611 }
10612
10613 /* Try to optimize prologue and epilogue further. */
10614 s390_optimize_prologue ();
10615
10616 /* Walk over the insns and do some >=z10 specific changes. */
10617 if (s390_tune == PROCESSOR_2097_Z10
10618 || s390_tune == PROCESSOR_2817_Z196
10619 || s390_tune == PROCESSOR_2827_ZEC12)
10620 {
10621 rtx insn;
10622 bool insn_added_p = false;
10623
10624 /* The insn lengths and addresses have to be up to date for the
10625 following manipulations. */
10626 shorten_branches (get_insns ());
10627
10628 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10629 {
10630 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10631 continue;
10632
10633 if (JUMP_P (insn))
10634 insn_added_p |= s390_fix_long_loop_prediction (insn);
10635
10636 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10637 || GET_CODE (PATTERN (insn)) == SET)
10638 && s390_tune == PROCESSOR_2097_Z10)
10639 insn_added_p |= s390_z10_optimize_cmp (insn);
10640 }
10641
10642 /* Adjust branches if we added new instructions. */
10643 if (insn_added_p)
10644 shorten_branches (get_insns ());
10645 }
10646 }
10647
10648 /* Return true if INSN is a fp load insn writing register REGNO. */
10649 static inline bool
10650 s390_fpload_toreg (rtx insn, unsigned int regno)
10651 {
10652 rtx set;
10653 enum attr_type flag = s390_safe_attr_type (insn);
10654
10655 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10656 return false;
10657
10658 set = single_set (insn);
10659
10660 if (set == NULL_RTX)
10661 return false;
10662
10663 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10664 return false;
10665
10666 if (REGNO (SET_DEST (set)) != regno)
10667 return false;
10668
10669 return true;
10670 }
10671
10672 /* This value describes the distance to be avoided between an
10673 aritmetic fp instruction and an fp load writing the same register.
10674 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10675 fine but the exact value has to be avoided. Otherwise the FP
10676 pipeline will throw an exception causing a major penalty. */
10677 #define Z10_EARLYLOAD_DISTANCE 7
10678
10679 /* Rearrange the ready list in order to avoid the situation described
10680 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10681 moved to the very end of the ready list. */
10682 static void
10683 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10684 {
10685 unsigned int regno;
10686 int nready = *nready_p;
10687 rtx tmp;
10688 int i;
10689 rtx insn;
10690 rtx set;
10691 enum attr_type flag;
10692 int distance;
10693
10694 /* Skip DISTANCE - 1 active insns. */
10695 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10696 distance > 0 && insn != NULL_RTX;
10697 distance--, insn = prev_active_insn (insn))
10698 if (CALL_P (insn) || JUMP_P (insn))
10699 return;
10700
10701 if (insn == NULL_RTX)
10702 return;
10703
10704 set = single_set (insn);
10705
10706 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10707 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10708 return;
10709
10710 flag = s390_safe_attr_type (insn);
10711
10712 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10713 return;
10714
10715 regno = REGNO (SET_DEST (set));
10716 i = nready - 1;
10717
10718 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10719 i--;
10720
10721 if (!i)
10722 return;
10723
10724 tmp = ready[i];
10725 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10726 ready[0] = tmp;
10727 }
10728
10729
10730 /* The s390_sched_state variable tracks the state of the current or
10731 the last instruction group.
10732
10733 0,1,2 number of instructions scheduled in the current group
10734 3 the last group is complete - normal insns
10735 4 the last group was a cracked/expanded insn */
10736
10737 static int s390_sched_state;
10738
10739 #define S390_OOO_SCHED_STATE_NORMAL 3
10740 #define S390_OOO_SCHED_STATE_CRACKED 4
10741
10742 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
10743 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
10744 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
10745 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
10746
10747 static unsigned int
10748 s390_get_sched_attrmask (rtx insn)
10749 {
10750 unsigned int mask = 0;
10751
10752 if (get_attr_ooo_cracked (insn))
10753 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
10754 if (get_attr_ooo_expanded (insn))
10755 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
10756 if (get_attr_ooo_endgroup (insn))
10757 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
10758 if (get_attr_ooo_groupalone (insn))
10759 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
10760 return mask;
10761 }
10762
10763 /* Return the scheduling score for INSN. The higher the score the
10764 better. The score is calculated from the OOO scheduling attributes
10765 of INSN and the scheduling state s390_sched_state. */
10766 static int
10767 s390_sched_score (rtx insn)
10768 {
10769 unsigned int mask = s390_get_sched_attrmask (insn);
10770 int score = 0;
10771
10772 switch (s390_sched_state)
10773 {
10774 case 0:
10775 /* Try to put insns into the first slot which would otherwise
10776 break a group. */
10777 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
10778 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
10779 score += 5;
10780 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
10781 score += 10;
10782 case 1:
10783 /* Prefer not cracked insns while trying to put together a
10784 group. */
10785 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
10786 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
10787 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
10788 score += 10;
10789 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
10790 score += 5;
10791 break;
10792 case 2:
10793 /* Prefer not cracked insns while trying to put together a
10794 group. */
10795 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
10796 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
10797 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
10798 score += 10;
10799 /* Prefer endgroup insns in the last slot. */
10800 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
10801 score += 10;
10802 break;
10803 case S390_OOO_SCHED_STATE_NORMAL:
10804 /* Prefer not cracked insns if the last was not cracked. */
10805 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
10806 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
10807 score += 5;
10808 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
10809 score += 10;
10810 break;
10811 case S390_OOO_SCHED_STATE_CRACKED:
10812 /* Try to keep cracked insns together to prevent them from
10813 interrupting groups. */
10814 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
10815 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
10816 score += 5;
10817 break;
10818 }
10819 return score;
10820 }
10821
10822 /* This function is called via hook TARGET_SCHED_REORDER before
10823 issueing one insn from list READY which contains *NREADYP entries.
10824 For target z10 it reorders load instructions to avoid early load
10825 conflicts in the floating point pipeline */
10826 static int
10827 s390_sched_reorder (FILE *file, int verbose,
10828 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10829 {
10830 if (s390_tune == PROCESSOR_2097_Z10)
10831 if (reload_completed && *nreadyp > 1)
10832 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10833
10834 if (s390_tune == PROCESSOR_2827_ZEC12
10835 && reload_completed
10836 && *nreadyp > 1)
10837 {
10838 int i;
10839 int last_index = *nreadyp - 1;
10840 int max_index = -1;
10841 int max_score = -1;
10842 rtx tmp;
10843
10844 /* Just move the insn with the highest score to the top (the
10845 end) of the list. A full sort is not needed since a conflict
10846 in the hazard recognition cannot happen. So the top insn in
10847 the ready list will always be taken. */
10848 for (i = last_index; i >= 0; i--)
10849 {
10850 int score;
10851
10852 if (recog_memoized (ready[i]) < 0)
10853 continue;
10854
10855 score = s390_sched_score (ready[i]);
10856 if (score > max_score)
10857 {
10858 max_score = score;
10859 max_index = i;
10860 }
10861 }
10862
10863 if (max_index != -1)
10864 {
10865 if (max_index != last_index)
10866 {
10867 tmp = ready[max_index];
10868 ready[max_index] = ready[last_index];
10869 ready[last_index] = tmp;
10870
10871 if (verbose > 5)
10872 fprintf (file,
10873 "move insn %d to the top of list\n",
10874 INSN_UID (ready[last_index]));
10875 }
10876 else if (verbose > 5)
10877 fprintf (file,
10878 "best insn %d already on top\n",
10879 INSN_UID (ready[last_index]));
10880 }
10881
10882 if (verbose > 5)
10883 {
10884 fprintf (file, "ready list ooo attributes - sched state: %d\n",
10885 s390_sched_state);
10886
10887 for (i = last_index; i >= 0; i--)
10888 {
10889 if (recog_memoized (ready[i]) < 0)
10890 continue;
10891 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
10892 s390_sched_score (ready[i]));
10893 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
10894 PRINT_OOO_ATTR (ooo_cracked);
10895 PRINT_OOO_ATTR (ooo_expanded);
10896 PRINT_OOO_ATTR (ooo_endgroup);
10897 PRINT_OOO_ATTR (ooo_groupalone);
10898 #undef PRINT_OOO_ATTR
10899 fprintf (file, "\n");
10900 }
10901 }
10902 }
10903
10904 return s390_issue_rate ();
10905 }
10906
10907
10908 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10909 the scheduler has issued INSN. It stores the last issued insn into
10910 last_scheduled_insn in order to make it available for
10911 s390_sched_reorder. */
10912 static int
10913 s390_sched_variable_issue (FILE *file, int verbose, rtx insn, int more)
10914 {
10915 last_scheduled_insn = insn;
10916
10917 if (s390_tune == PROCESSOR_2827_ZEC12
10918 && reload_completed
10919 && recog_memoized (insn) >= 0)
10920 {
10921 unsigned int mask = s390_get_sched_attrmask (insn);
10922
10923 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
10924 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
10925 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
10926 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
10927 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
10928 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
10929 else
10930 {
10931 /* Only normal insns are left (mask == 0). */
10932 switch (s390_sched_state)
10933 {
10934 case 0:
10935 case 1:
10936 case 2:
10937 case S390_OOO_SCHED_STATE_NORMAL:
10938 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
10939 s390_sched_state = 1;
10940 else
10941 s390_sched_state++;
10942
10943 break;
10944 case S390_OOO_SCHED_STATE_CRACKED:
10945 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
10946 break;
10947 }
10948 }
10949 if (verbose > 5)
10950 {
10951 fprintf (file, "insn %d: ", INSN_UID (insn));
10952 #define PRINT_OOO_ATTR(ATTR) \
10953 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
10954 PRINT_OOO_ATTR (ooo_cracked);
10955 PRINT_OOO_ATTR (ooo_expanded);
10956 PRINT_OOO_ATTR (ooo_endgroup);
10957 PRINT_OOO_ATTR (ooo_groupalone);
10958 #undef PRINT_OOO_ATTR
10959 fprintf (file, "\n");
10960 fprintf (file, "sched state: %d\n", s390_sched_state);
10961 }
10962 }
10963
10964 if (GET_CODE (PATTERN (insn)) != USE
10965 && GET_CODE (PATTERN (insn)) != CLOBBER)
10966 return more - 1;
10967 else
10968 return more;
10969 }
10970
10971 static void
10972 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10973 int verbose ATTRIBUTE_UNUSED,
10974 int max_ready ATTRIBUTE_UNUSED)
10975 {
10976 last_scheduled_insn = NULL_RTX;
10977 s390_sched_state = 0;
10978 }
10979
10980 /* This function checks the whole of insn X for memory references. The
10981 function always returns zero because the framework it is called
10982 from would stop recursively analyzing the insn upon a return value
10983 other than zero. The real result of this function is updating
10984 counter variable MEM_COUNT. */
10985 static int
10986 check_dpu (rtx *x, unsigned *mem_count)
10987 {
10988 if (*x != NULL_RTX && MEM_P (*x))
10989 (*mem_count)++;
10990 return 0;
10991 }
10992
10993 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10994 a new number struct loop *loop should be unrolled if tuned for cpus with
10995 a built-in stride prefetcher.
10996 The loop is analyzed for memory accesses by calling check_dpu for
10997 each rtx of the loop. Depending on the loop_depth and the amount of
10998 memory accesses a new number <=nunroll is returned to improve the
10999 behaviour of the hardware prefetch unit. */
11000 static unsigned
11001 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11002 {
11003 basic_block *bbs;
11004 rtx insn;
11005 unsigned i;
11006 unsigned mem_count = 0;
11007
11008 if (s390_tune != PROCESSOR_2097_Z10
11009 && s390_tune != PROCESSOR_2817_Z196
11010 && s390_tune != PROCESSOR_2827_ZEC12)
11011 return nunroll;
11012
11013 /* Count the number of memory references within the loop body. */
11014 bbs = get_loop_body (loop);
11015 for (i = 0; i < loop->num_nodes; i++)
11016 {
11017 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
11018 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11019 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
11020 }
11021 free (bbs);
11022
11023 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11024 if (mem_count == 0)
11025 return nunroll;
11026
11027 switch (loop_depth(loop))
11028 {
11029 case 1:
11030 return MIN (nunroll, 28 / mem_count);
11031 case 2:
11032 return MIN (nunroll, 22 / mem_count);
11033 default:
11034 return MIN (nunroll, 16 / mem_count);
11035 }
11036 }
11037
11038 /* Initialize GCC target structure. */
11039
11040 #undef TARGET_ASM_ALIGNED_HI_OP
11041 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
11042 #undef TARGET_ASM_ALIGNED_DI_OP
11043 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
11044 #undef TARGET_ASM_INTEGER
11045 #define TARGET_ASM_INTEGER s390_assemble_integer
11046
11047 #undef TARGET_ASM_OPEN_PAREN
11048 #define TARGET_ASM_OPEN_PAREN ""
11049
11050 #undef TARGET_ASM_CLOSE_PAREN
11051 #define TARGET_ASM_CLOSE_PAREN ""
11052
11053 #undef TARGET_OPTION_OVERRIDE
11054 #define TARGET_OPTION_OVERRIDE s390_option_override
11055
11056 #undef TARGET_ENCODE_SECTION_INFO
11057 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
11058
11059 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11060 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11061
11062 #ifdef HAVE_AS_TLS
11063 #undef TARGET_HAVE_TLS
11064 #define TARGET_HAVE_TLS true
11065 #endif
11066 #undef TARGET_CANNOT_FORCE_CONST_MEM
11067 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
11068
11069 #undef TARGET_DELEGITIMIZE_ADDRESS
11070 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
11071
11072 #undef TARGET_LEGITIMIZE_ADDRESS
11073 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
11074
11075 #undef TARGET_RETURN_IN_MEMORY
11076 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
11077
11078 #undef TARGET_INIT_BUILTINS
11079 #define TARGET_INIT_BUILTINS s390_init_builtins
11080 #undef TARGET_EXPAND_BUILTIN
11081 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
11082
11083 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
11084 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
11085
11086 #undef TARGET_ASM_OUTPUT_MI_THUNK
11087 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
11088 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11089 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
11090
11091 #undef TARGET_SCHED_ADJUST_PRIORITY
11092 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
11093 #undef TARGET_SCHED_ISSUE_RATE
11094 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
11095 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
11096 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
11097
11098 #undef TARGET_SCHED_VARIABLE_ISSUE
11099 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
11100 #undef TARGET_SCHED_REORDER
11101 #define TARGET_SCHED_REORDER s390_sched_reorder
11102 #undef TARGET_SCHED_INIT
11103 #define TARGET_SCHED_INIT s390_sched_init
11104
11105 #undef TARGET_CANNOT_COPY_INSN_P
11106 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
11107 #undef TARGET_RTX_COSTS
11108 #define TARGET_RTX_COSTS s390_rtx_costs
11109 #undef TARGET_ADDRESS_COST
11110 #define TARGET_ADDRESS_COST s390_address_cost
11111 #undef TARGET_REGISTER_MOVE_COST
11112 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
11113 #undef TARGET_MEMORY_MOVE_COST
11114 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
11115
11116 #undef TARGET_MACHINE_DEPENDENT_REORG
11117 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
11118
11119 #undef TARGET_VALID_POINTER_MODE
11120 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
11121
11122 #undef TARGET_BUILD_BUILTIN_VA_LIST
11123 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
11124 #undef TARGET_EXPAND_BUILTIN_VA_START
11125 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
11126 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11127 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
11128
11129 #undef TARGET_PROMOTE_FUNCTION_MODE
11130 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
11131 #undef TARGET_PASS_BY_REFERENCE
11132 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
11133
11134 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11135 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
11136 #undef TARGET_FUNCTION_ARG
11137 #define TARGET_FUNCTION_ARG s390_function_arg
11138 #undef TARGET_FUNCTION_ARG_ADVANCE
11139 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
11140 #undef TARGET_FUNCTION_VALUE
11141 #define TARGET_FUNCTION_VALUE s390_function_value
11142 #undef TARGET_LIBCALL_VALUE
11143 #define TARGET_LIBCALL_VALUE s390_libcall_value
11144
11145 #undef TARGET_FIXED_CONDITION_CODE_REGS
11146 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
11147
11148 #undef TARGET_CC_MODES_COMPATIBLE
11149 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
11150
11151 #undef TARGET_INVALID_WITHIN_DOLOOP
11152 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
11153
11154 #ifdef HAVE_AS_TLS
11155 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
11156 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
11157 #endif
11158
11159 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11160 #undef TARGET_MANGLE_TYPE
11161 #define TARGET_MANGLE_TYPE s390_mangle_type
11162 #endif
11163
11164 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11165 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11166
11167 #undef TARGET_PREFERRED_RELOAD_CLASS
11168 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
11169
11170 #undef TARGET_SECONDARY_RELOAD
11171 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
11172
11173 #undef TARGET_LIBGCC_CMP_RETURN_MODE
11174 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
11175
11176 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
11177 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
11178
11179 #undef TARGET_LEGITIMATE_ADDRESS_P
11180 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
11181
11182 #undef TARGET_LEGITIMATE_CONSTANT_P
11183 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
11184
11185 #undef TARGET_CAN_ELIMINATE
11186 #define TARGET_CAN_ELIMINATE s390_can_eliminate
11187
11188 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11189 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
11190
11191 #undef TARGET_LOOP_UNROLL_ADJUST
11192 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
11193
11194 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11195 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
11196 #undef TARGET_TRAMPOLINE_INIT
11197 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
11198
11199 #undef TARGET_UNWIND_WORD_MODE
11200 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
11201
11202 struct gcc_target targetm = TARGET_INITIALIZER;
11203
11204 #include "gt-s390.h"