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s390.c (s390_sched_init): New function.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55 #include "params.h"
56
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 extern int reload_completed;
226
227 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
228 static rtx last_scheduled_insn;
229
230 /* Structure used to hold the components of a S/390 memory
231 address. A legitimate address on S/390 is of the general
232 form
233 base + index + displacement
234 where any of the components is optional.
235
236 base and index are registers of the class ADDR_REGS,
237 displacement is an unsigned 12-bit immediate constant. */
238
239 struct s390_address
240 {
241 rtx base;
242 rtx indx;
243 rtx disp;
244 bool pointer;
245 bool literal_pool;
246 };
247
248 /* Which cpu are we tuning for. */
249 enum processor_type s390_tune = PROCESSOR_max;
250 int s390_tune_flags;
251 /* Which instruction set architecture to use. */
252 enum processor_type s390_arch;
253 int s390_arch_flags;
254
255 HOST_WIDE_INT s390_warn_framesize = 0;
256 HOST_WIDE_INT s390_stack_size = 0;
257 HOST_WIDE_INT s390_stack_guard = 0;
258
259 /* The following structure is embedded in the machine
260 specific part of struct function. */
261
262 struct GTY (()) s390_frame_layout
263 {
264 /* Offset within stack frame. */
265 HOST_WIDE_INT gprs_offset;
266 HOST_WIDE_INT f0_offset;
267 HOST_WIDE_INT f4_offset;
268 HOST_WIDE_INT f8_offset;
269 HOST_WIDE_INT backchain_offset;
270
271 /* Number of first and last gpr where slots in the register
272 save area are reserved for. */
273 int first_save_gpr_slot;
274 int last_save_gpr_slot;
275
276 /* Number of first and last gpr to be saved, restored. */
277 int first_save_gpr;
278 int first_restore_gpr;
279 int last_save_gpr;
280 int last_restore_gpr;
281
282 /* Bits standing for floating point registers. Set, if the
283 respective register has to be saved. Starting with reg 16 (f0)
284 at the rightmost bit.
285 Bit 15 - 8 7 6 5 4 3 2 1 0
286 fpr 15 - 8 7 5 3 1 6 4 2 0
287 reg 31 - 24 23 22 21 20 19 18 17 16 */
288 unsigned int fpr_bitmap;
289
290 /* Number of floating point registers f8-f15 which must be saved. */
291 int high_fprs;
292
293 /* Set if return address needs to be saved.
294 This flag is set by s390_return_addr_rtx if it could not use
295 the initial value of r14 and therefore depends on r14 saved
296 to the stack. */
297 bool save_return_addr_p;
298
299 /* Size of stack frame. */
300 HOST_WIDE_INT frame_size;
301 };
302
303 /* Define the structure for the machine field in struct function. */
304
305 struct GTY(()) machine_function
306 {
307 struct s390_frame_layout frame_layout;
308
309 /* Literal pool base register. */
310 rtx base_reg;
311
312 /* True if we may need to perform branch splitting. */
313 bool split_branches_pending_p;
314
315 /* Some local-dynamic TLS symbol name. */
316 const char *some_ld_name;
317
318 bool has_landing_pad_p;
319 };
320
321 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
322
323 #define cfun_frame_layout (cfun->machine->frame_layout)
324 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
325 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
326 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
327 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
328 (1 << (BITNUM)))
329 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
330 (1 << (BITNUM))))
331
332 /* Number of GPRs and FPRs used for argument passing. */
333 #define GP_ARG_NUM_REG 5
334 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
335
336 /* A couple of shortcuts. */
337 #define CONST_OK_FOR_J(x) \
338 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
339 #define CONST_OK_FOR_K(x) \
340 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
341 #define CONST_OK_FOR_Os(x) \
342 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
343 #define CONST_OK_FOR_Op(x) \
344 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
345 #define CONST_OK_FOR_On(x) \
346 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
347
348 #define REGNO_PAIR_OK(REGNO, MODE) \
349 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
350
351 /* That's the read ahead of the dynamic branch prediction unit in
352 bytes on a z10 CPU. */
353 #define Z10_PREDICT_DISTANCE 384
354
355 static enum machine_mode
356 s390_libgcc_cmp_return_mode (void)
357 {
358 return TARGET_64BIT ? DImode : SImode;
359 }
360
361 static enum machine_mode
362 s390_libgcc_shift_count_mode (void)
363 {
364 return TARGET_64BIT ? DImode : SImode;
365 }
366
367 /* Return true if the back end supports mode MODE. */
368 static bool
369 s390_scalar_mode_supported_p (enum machine_mode mode)
370 {
371 if (DECIMAL_FLOAT_MODE_P (mode))
372 return default_decimal_float_supported_p ();
373 else
374 return default_scalar_mode_supported_p (mode);
375 }
376
377 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
378
379 void
380 s390_set_has_landing_pad_p (bool value)
381 {
382 cfun->machine->has_landing_pad_p = value;
383 }
384
385 /* If two condition code modes are compatible, return a condition code
386 mode which is compatible with both. Otherwise, return
387 VOIDmode. */
388
389 static enum machine_mode
390 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
391 {
392 if (m1 == m2)
393 return m1;
394
395 switch (m1)
396 {
397 case CCZmode:
398 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
399 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
400 return m2;
401 return VOIDmode;
402
403 case CCSmode:
404 case CCUmode:
405 case CCTmode:
406 case CCSRmode:
407 case CCURmode:
408 case CCZ1mode:
409 if (m2 == CCZmode)
410 return m1;
411
412 return VOIDmode;
413
414 default:
415 return VOIDmode;
416 }
417 return VOIDmode;
418 }
419
420 /* Return true if SET either doesn't set the CC register, or else
421 the source and destination have matching CC modes and that
422 CC mode is at least as constrained as REQ_MODE. */
423
424 static bool
425 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
426 {
427 enum machine_mode set_mode;
428
429 gcc_assert (GET_CODE (set) == SET);
430
431 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
432 return 1;
433
434 set_mode = GET_MODE (SET_DEST (set));
435 switch (set_mode)
436 {
437 case CCSmode:
438 case CCSRmode:
439 case CCUmode:
440 case CCURmode:
441 case CCLmode:
442 case CCL1mode:
443 case CCL2mode:
444 case CCL3mode:
445 case CCT1mode:
446 case CCT2mode:
447 case CCT3mode:
448 if (req_mode != set_mode)
449 return 0;
450 break;
451
452 case CCZmode:
453 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
454 && req_mode != CCSRmode && req_mode != CCURmode)
455 return 0;
456 break;
457
458 case CCAPmode:
459 case CCANmode:
460 if (req_mode != CCAmode)
461 return 0;
462 break;
463
464 default:
465 gcc_unreachable ();
466 }
467
468 return (GET_MODE (SET_SRC (set)) == set_mode);
469 }
470
471 /* Return true if every SET in INSN that sets the CC register
472 has source and destination with matching CC modes and that
473 CC mode is at least as constrained as REQ_MODE.
474 If REQ_MODE is VOIDmode, always return false. */
475
476 bool
477 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
478 {
479 int i;
480
481 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
482 if (req_mode == VOIDmode)
483 return false;
484
485 if (GET_CODE (PATTERN (insn)) == SET)
486 return s390_match_ccmode_set (PATTERN (insn), req_mode);
487
488 if (GET_CODE (PATTERN (insn)) == PARALLEL)
489 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
490 {
491 rtx set = XVECEXP (PATTERN (insn), 0, i);
492 if (GET_CODE (set) == SET)
493 if (!s390_match_ccmode_set (set, req_mode))
494 return false;
495 }
496
497 return true;
498 }
499
500 /* If a test-under-mask instruction can be used to implement
501 (compare (and ... OP1) OP2), return the CC mode required
502 to do that. Otherwise, return VOIDmode.
503 MIXED is true if the instruction can distinguish between
504 CC1 and CC2 for mixed selected bits (TMxx), it is false
505 if the instruction cannot (TM). */
506
507 enum machine_mode
508 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
509 {
510 int bit0, bit1;
511
512 /* ??? Fixme: should work on CONST_DOUBLE as well. */
513 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
514 return VOIDmode;
515
516 /* Selected bits all zero: CC0.
517 e.g.: int a; if ((a & (16 + 128)) == 0) */
518 if (INTVAL (op2) == 0)
519 return CCTmode;
520
521 /* Selected bits all one: CC3.
522 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
523 if (INTVAL (op2) == INTVAL (op1))
524 return CCT3mode;
525
526 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
527 int a;
528 if ((a & (16 + 128)) == 16) -> CCT1
529 if ((a & (16 + 128)) == 128) -> CCT2 */
530 if (mixed)
531 {
532 bit1 = exact_log2 (INTVAL (op2));
533 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
534 if (bit0 != -1 && bit1 != -1)
535 return bit0 > bit1 ? CCT1mode : CCT2mode;
536 }
537
538 return VOIDmode;
539 }
540
541 /* Given a comparison code OP (EQ, NE, etc.) and the operands
542 OP0 and OP1 of a COMPARE, return the mode to be used for the
543 comparison. */
544
545 enum machine_mode
546 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
547 {
548 switch (code)
549 {
550 case EQ:
551 case NE:
552 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
553 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
554 return CCAPmode;
555 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
556 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
557 return CCAPmode;
558 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
559 || GET_CODE (op1) == NEG)
560 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
561 return CCLmode;
562
563 if (GET_CODE (op0) == AND)
564 {
565 /* Check whether we can potentially do it via TM. */
566 enum machine_mode ccmode;
567 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
568 if (ccmode != VOIDmode)
569 {
570 /* Relax CCTmode to CCZmode to allow fall-back to AND
571 if that turns out to be beneficial. */
572 return ccmode == CCTmode ? CCZmode : ccmode;
573 }
574 }
575
576 if (register_operand (op0, HImode)
577 && GET_CODE (op1) == CONST_INT
578 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
579 return CCT3mode;
580 if (register_operand (op0, QImode)
581 && GET_CODE (op1) == CONST_INT
582 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
583 return CCT3mode;
584
585 return CCZmode;
586
587 case LE:
588 case LT:
589 case GE:
590 case GT:
591 /* The only overflow condition of NEG and ABS happens when
592 -INT_MAX is used as parameter, which stays negative. So
593 we have an overflow from a positive value to a negative.
594 Using CCAP mode the resulting cc can be used for comparisons. */
595 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
596 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
597 return CCAPmode;
598
599 /* If constants are involved in an add instruction it is possible to use
600 the resulting cc for comparisons with zero. Knowing the sign of the
601 constant the overflow behavior gets predictable. e.g.:
602 int a, b; if ((b = a + c) > 0)
603 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
604 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
605 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
606 {
607 if (INTVAL (XEXP((op0), 1)) < 0)
608 return CCANmode;
609 else
610 return CCAPmode;
611 }
612 /* Fall through. */
613 case UNORDERED:
614 case ORDERED:
615 case UNEQ:
616 case UNLE:
617 case UNLT:
618 case UNGE:
619 case UNGT:
620 case LTGT:
621 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
622 && GET_CODE (op1) != CONST_INT)
623 return CCSRmode;
624 return CCSmode;
625
626 case LTU:
627 case GEU:
628 if (GET_CODE (op0) == PLUS
629 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
630 return CCL1mode;
631
632 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
633 && GET_CODE (op1) != CONST_INT)
634 return CCURmode;
635 return CCUmode;
636
637 case LEU:
638 case GTU:
639 if (GET_CODE (op0) == MINUS
640 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
641 return CCL2mode;
642
643 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
644 && GET_CODE (op1) != CONST_INT)
645 return CCURmode;
646 return CCUmode;
647
648 default:
649 gcc_unreachable ();
650 }
651 }
652
653 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
654 that we can implement more efficiently. */
655
656 void
657 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
658 {
659 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
660 if ((*code == EQ || *code == NE)
661 && *op1 == const0_rtx
662 && GET_CODE (*op0) == ZERO_EXTRACT
663 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
664 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
665 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
666 {
667 rtx inner = XEXP (*op0, 0);
668 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
669 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
670 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
671
672 if (len > 0 && len < modesize
673 && pos >= 0 && pos + len <= modesize
674 && modesize <= HOST_BITS_PER_WIDE_INT)
675 {
676 unsigned HOST_WIDE_INT block;
677 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
678 block <<= modesize - pos - len;
679
680 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
681 gen_int_mode (block, GET_MODE (inner)));
682 }
683 }
684
685 /* Narrow AND of memory against immediate to enable TM. */
686 if ((*code == EQ || *code == NE)
687 && *op1 == const0_rtx
688 && GET_CODE (*op0) == AND
689 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
690 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
691 {
692 rtx inner = XEXP (*op0, 0);
693 rtx mask = XEXP (*op0, 1);
694
695 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
696 if (GET_CODE (inner) == SUBREG
697 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
698 && (GET_MODE_SIZE (GET_MODE (inner))
699 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
700 && ((INTVAL (mask)
701 & GET_MODE_MASK (GET_MODE (inner))
702 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
703 == 0))
704 inner = SUBREG_REG (inner);
705
706 /* Do not change volatile MEMs. */
707 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
708 {
709 int part = s390_single_part (XEXP (*op0, 1),
710 GET_MODE (inner), QImode, 0);
711 if (part >= 0)
712 {
713 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
714 inner = adjust_address_nv (inner, QImode, part);
715 *op0 = gen_rtx_AND (QImode, inner, mask);
716 }
717 }
718 }
719
720 /* Narrow comparisons against 0xffff to HImode if possible. */
721 if ((*code == EQ || *code == NE)
722 && GET_CODE (*op1) == CONST_INT
723 && INTVAL (*op1) == 0xffff
724 && SCALAR_INT_MODE_P (GET_MODE (*op0))
725 && (nonzero_bits (*op0, GET_MODE (*op0))
726 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
727 {
728 *op0 = gen_lowpart (HImode, *op0);
729 *op1 = constm1_rtx;
730 }
731
732 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
733 if (GET_CODE (*op0) == UNSPEC
734 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
735 && XVECLEN (*op0, 0) == 1
736 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
737 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
738 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
739 && *op1 == const0_rtx)
740 {
741 enum rtx_code new_code = UNKNOWN;
742 switch (*code)
743 {
744 case EQ: new_code = EQ; break;
745 case NE: new_code = NE; break;
746 case LT: new_code = GTU; break;
747 case GT: new_code = LTU; break;
748 case LE: new_code = GEU; break;
749 case GE: new_code = LEU; break;
750 default: break;
751 }
752
753 if (new_code != UNKNOWN)
754 {
755 *op0 = XVECEXP (*op0, 0, 0);
756 *code = new_code;
757 }
758 }
759
760 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
761 if (GET_CODE (*op0) == UNSPEC
762 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
763 && XVECLEN (*op0, 0) == 1
764 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
765 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
766 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
767 && *op1 == const0_rtx)
768 {
769 enum rtx_code new_code = UNKNOWN;
770 switch (*code)
771 {
772 case EQ: new_code = EQ; break;
773 case NE: new_code = NE; break;
774 default: break;
775 }
776
777 if (new_code != UNKNOWN)
778 {
779 *op0 = XVECEXP (*op0, 0, 0);
780 *code = new_code;
781 }
782 }
783
784 /* Simplify cascaded EQ, NE with const0_rtx. */
785 if ((*code == NE || *code == EQ)
786 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
787 && GET_MODE (*op0) == SImode
788 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
789 && REG_P (XEXP (*op0, 0))
790 && XEXP (*op0, 1) == const0_rtx
791 && *op1 == const0_rtx)
792 {
793 if ((*code == EQ && GET_CODE (*op0) == NE)
794 || (*code == NE && GET_CODE (*op0) == EQ))
795 *code = EQ;
796 else
797 *code = NE;
798 *op0 = XEXP (*op0, 0);
799 }
800
801 /* Prefer register over memory as first operand. */
802 if (MEM_P (*op0) && REG_P (*op1))
803 {
804 rtx tem = *op0; *op0 = *op1; *op1 = tem;
805 *code = swap_condition (*code);
806 }
807 }
808
809 /* Emit a compare instruction suitable to implement the comparison
810 OP0 CODE OP1. Return the correct condition RTL to be placed in
811 the IF_THEN_ELSE of the conditional branch testing the result. */
812
813 rtx
814 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
815 {
816 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
817 rtx cc;
818
819 /* Do not output a redundant compare instruction if a compare_and_swap
820 pattern already computed the result and the machine modes are compatible. */
821 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
822 {
823 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
824 == GET_MODE (op0));
825 cc = op0;
826 }
827 else
828 {
829 cc = gen_rtx_REG (mode, CC_REGNUM);
830 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
831 }
832
833 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
834 }
835
836 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
837 matches CMP.
838 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
839 conditional branch testing the result. */
840
841 static rtx
842 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
843 {
844 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
845 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
846 }
847
848 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
849 unconditional jump, else a conditional jump under condition COND. */
850
851 void
852 s390_emit_jump (rtx target, rtx cond)
853 {
854 rtx insn;
855
856 target = gen_rtx_LABEL_REF (VOIDmode, target);
857 if (cond)
858 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
859
860 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
861 emit_jump_insn (insn);
862 }
863
864 /* Return branch condition mask to implement a branch
865 specified by CODE. Return -1 for invalid comparisons. */
866
867 int
868 s390_branch_condition_mask (rtx code)
869 {
870 const int CC0 = 1 << 3;
871 const int CC1 = 1 << 2;
872 const int CC2 = 1 << 1;
873 const int CC3 = 1 << 0;
874
875 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
876 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
877 gcc_assert (XEXP (code, 1) == const0_rtx);
878
879 switch (GET_MODE (XEXP (code, 0)))
880 {
881 case CCZmode:
882 case CCZ1mode:
883 switch (GET_CODE (code))
884 {
885 case EQ: return CC0;
886 case NE: return CC1 | CC2 | CC3;
887 default: return -1;
888 }
889 break;
890
891 case CCT1mode:
892 switch (GET_CODE (code))
893 {
894 case EQ: return CC1;
895 case NE: return CC0 | CC2 | CC3;
896 default: return -1;
897 }
898 break;
899
900 case CCT2mode:
901 switch (GET_CODE (code))
902 {
903 case EQ: return CC2;
904 case NE: return CC0 | CC1 | CC3;
905 default: return -1;
906 }
907 break;
908
909 case CCT3mode:
910 switch (GET_CODE (code))
911 {
912 case EQ: return CC3;
913 case NE: return CC0 | CC1 | CC2;
914 default: return -1;
915 }
916 break;
917
918 case CCLmode:
919 switch (GET_CODE (code))
920 {
921 case EQ: return CC0 | CC2;
922 case NE: return CC1 | CC3;
923 default: return -1;
924 }
925 break;
926
927 case CCL1mode:
928 switch (GET_CODE (code))
929 {
930 case LTU: return CC2 | CC3; /* carry */
931 case GEU: return CC0 | CC1; /* no carry */
932 default: return -1;
933 }
934 break;
935
936 case CCL2mode:
937 switch (GET_CODE (code))
938 {
939 case GTU: return CC0 | CC1; /* borrow */
940 case LEU: return CC2 | CC3; /* no borrow */
941 default: return -1;
942 }
943 break;
944
945 case CCL3mode:
946 switch (GET_CODE (code))
947 {
948 case EQ: return CC0 | CC2;
949 case NE: return CC1 | CC3;
950 case LTU: return CC1;
951 case GTU: return CC3;
952 case LEU: return CC1 | CC2;
953 case GEU: return CC2 | CC3;
954 default: return -1;
955 }
956
957 case CCUmode:
958 switch (GET_CODE (code))
959 {
960 case EQ: return CC0;
961 case NE: return CC1 | CC2 | CC3;
962 case LTU: return CC1;
963 case GTU: return CC2;
964 case LEU: return CC0 | CC1;
965 case GEU: return CC0 | CC2;
966 default: return -1;
967 }
968 break;
969
970 case CCURmode:
971 switch (GET_CODE (code))
972 {
973 case EQ: return CC0;
974 case NE: return CC2 | CC1 | CC3;
975 case LTU: return CC2;
976 case GTU: return CC1;
977 case LEU: return CC0 | CC2;
978 case GEU: return CC0 | CC1;
979 default: return -1;
980 }
981 break;
982
983 case CCAPmode:
984 switch (GET_CODE (code))
985 {
986 case EQ: return CC0;
987 case NE: return CC1 | CC2 | CC3;
988 case LT: return CC1 | CC3;
989 case GT: return CC2;
990 case LE: return CC0 | CC1 | CC3;
991 case GE: return CC0 | CC2;
992 default: return -1;
993 }
994 break;
995
996 case CCANmode:
997 switch (GET_CODE (code))
998 {
999 case EQ: return CC0;
1000 case NE: return CC1 | CC2 | CC3;
1001 case LT: return CC1;
1002 case GT: return CC2 | CC3;
1003 case LE: return CC0 | CC1;
1004 case GE: return CC0 | CC2 | CC3;
1005 default: return -1;
1006 }
1007 break;
1008
1009 case CCSmode:
1010 switch (GET_CODE (code))
1011 {
1012 case EQ: return CC0;
1013 case NE: return CC1 | CC2 | CC3;
1014 case LT: return CC1;
1015 case GT: return CC2;
1016 case LE: return CC0 | CC1;
1017 case GE: return CC0 | CC2;
1018 case UNORDERED: return CC3;
1019 case ORDERED: return CC0 | CC1 | CC2;
1020 case UNEQ: return CC0 | CC3;
1021 case UNLT: return CC1 | CC3;
1022 case UNGT: return CC2 | CC3;
1023 case UNLE: return CC0 | CC1 | CC3;
1024 case UNGE: return CC0 | CC2 | CC3;
1025 case LTGT: return CC1 | CC2;
1026 default: return -1;
1027 }
1028 break;
1029
1030 case CCSRmode:
1031 switch (GET_CODE (code))
1032 {
1033 case EQ: return CC0;
1034 case NE: return CC2 | CC1 | CC3;
1035 case LT: return CC2;
1036 case GT: return CC1;
1037 case LE: return CC0 | CC2;
1038 case GE: return CC0 | CC1;
1039 case UNORDERED: return CC3;
1040 case ORDERED: return CC0 | CC2 | CC1;
1041 case UNEQ: return CC0 | CC3;
1042 case UNLT: return CC2 | CC3;
1043 case UNGT: return CC1 | CC3;
1044 case UNLE: return CC0 | CC2 | CC3;
1045 case UNGE: return CC0 | CC1 | CC3;
1046 case LTGT: return CC2 | CC1;
1047 default: return -1;
1048 }
1049 break;
1050
1051 default:
1052 return -1;
1053 }
1054 }
1055
1056
1057 /* Return branch condition mask to implement a compare and branch
1058 specified by CODE. Return -1 for invalid comparisons. */
1059
1060 int
1061 s390_compare_and_branch_condition_mask (rtx code)
1062 {
1063 const int CC0 = 1 << 3;
1064 const int CC1 = 1 << 2;
1065 const int CC2 = 1 << 1;
1066
1067 switch (GET_CODE (code))
1068 {
1069 case EQ:
1070 return CC0;
1071 case NE:
1072 return CC1 | CC2;
1073 case LT:
1074 case LTU:
1075 return CC1;
1076 case GT:
1077 case GTU:
1078 return CC2;
1079 case LE:
1080 case LEU:
1081 return CC0 | CC1;
1082 case GE:
1083 case GEU:
1084 return CC0 | CC2;
1085 default:
1086 gcc_unreachable ();
1087 }
1088 return -1;
1089 }
1090
1091 /* If INV is false, return assembler mnemonic string to implement
1092 a branch specified by CODE. If INV is true, return mnemonic
1093 for the corresponding inverted branch. */
1094
1095 static const char *
1096 s390_branch_condition_mnemonic (rtx code, int inv)
1097 {
1098 int mask;
1099
1100 static const char *const mnemonic[16] =
1101 {
1102 NULL, "o", "h", "nle",
1103 "l", "nhe", "lh", "ne",
1104 "e", "nlh", "he", "nl",
1105 "le", "nh", "no", NULL
1106 };
1107
1108 if (GET_CODE (XEXP (code, 0)) == REG
1109 && REGNO (XEXP (code, 0)) == CC_REGNUM
1110 && XEXP (code, 1) == const0_rtx)
1111 mask = s390_branch_condition_mask (code);
1112 else
1113 mask = s390_compare_and_branch_condition_mask (code);
1114
1115 gcc_assert (mask >= 0);
1116
1117 if (inv)
1118 mask ^= 15;
1119
1120 gcc_assert (mask >= 1 && mask <= 14);
1121
1122 return mnemonic[mask];
1123 }
1124
1125 /* Return the part of op which has a value different from def.
1126 The size of the part is determined by mode.
1127 Use this function only if you already know that op really
1128 contains such a part. */
1129
1130 unsigned HOST_WIDE_INT
1131 s390_extract_part (rtx op, enum machine_mode mode, int def)
1132 {
1133 unsigned HOST_WIDE_INT value = 0;
1134 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1135 int part_bits = GET_MODE_BITSIZE (mode);
1136 unsigned HOST_WIDE_INT part_mask
1137 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1138 int i;
1139
1140 for (i = 0; i < max_parts; i++)
1141 {
1142 if (i == 0)
1143 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1144 else
1145 value >>= part_bits;
1146
1147 if ((value & part_mask) != (def & part_mask))
1148 return value & part_mask;
1149 }
1150
1151 gcc_unreachable ();
1152 }
1153
1154 /* If OP is an integer constant of mode MODE with exactly one
1155 part of mode PART_MODE unequal to DEF, return the number of that
1156 part. Otherwise, return -1. */
1157
1158 int
1159 s390_single_part (rtx op,
1160 enum machine_mode mode,
1161 enum machine_mode part_mode,
1162 int def)
1163 {
1164 unsigned HOST_WIDE_INT value = 0;
1165 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1166 unsigned HOST_WIDE_INT part_mask
1167 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1168 int i, part = -1;
1169
1170 if (GET_CODE (op) != CONST_INT)
1171 return -1;
1172
1173 for (i = 0; i < n_parts; i++)
1174 {
1175 if (i == 0)
1176 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1177 else
1178 value >>= GET_MODE_BITSIZE (part_mode);
1179
1180 if ((value & part_mask) != (def & part_mask))
1181 {
1182 if (part != -1)
1183 return -1;
1184 else
1185 part = i;
1186 }
1187 }
1188 return part == -1 ? -1 : n_parts - 1 - part;
1189 }
1190
1191 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1192 bits and no other bits are set in IN. POS and LENGTH can be used
1193 to obtain the start position and the length of the bitfield.
1194
1195 POS gives the position of the first bit of the bitfield counting
1196 from the lowest order bit starting with zero. In order to use this
1197 value for S/390 instructions this has to be converted to "bits big
1198 endian" style. */
1199
1200 bool
1201 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1202 int *pos, int *length)
1203 {
1204 int tmp_pos = 0;
1205 int tmp_length = 0;
1206 int i;
1207 unsigned HOST_WIDE_INT mask = 1ULL;
1208 bool contiguous = false;
1209
1210 for (i = 0; i < size; mask <<= 1, i++)
1211 {
1212 if (contiguous)
1213 {
1214 if (mask & in)
1215 tmp_length++;
1216 else
1217 break;
1218 }
1219 else
1220 {
1221 if (mask & in)
1222 {
1223 contiguous = true;
1224 tmp_length++;
1225 }
1226 else
1227 tmp_pos++;
1228 }
1229 }
1230
1231 if (!tmp_length)
1232 return false;
1233
1234 /* Calculate a mask for all bits beyond the contiguous bits. */
1235 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1236
1237 if (mask & in)
1238 return false;
1239
1240 if (tmp_length + tmp_pos - 1 > size)
1241 return false;
1242
1243 if (length)
1244 *length = tmp_length;
1245
1246 if (pos)
1247 *pos = tmp_pos;
1248
1249 return true;
1250 }
1251
1252 /* Check whether we can (and want to) split a double-word
1253 move in mode MODE from SRC to DST into two single-word
1254 moves, moving the subword FIRST_SUBWORD first. */
1255
1256 bool
1257 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1258 {
1259 /* Floating point registers cannot be split. */
1260 if (FP_REG_P (src) || FP_REG_P (dst))
1261 return false;
1262
1263 /* We don't need to split if operands are directly accessible. */
1264 if (s_operand (src, mode) || s_operand (dst, mode))
1265 return false;
1266
1267 /* Non-offsettable memory references cannot be split. */
1268 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1269 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1270 return false;
1271
1272 /* Moving the first subword must not clobber a register
1273 needed to move the second subword. */
1274 if (register_operand (dst, mode))
1275 {
1276 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1277 if (reg_overlap_mentioned_p (subreg, src))
1278 return false;
1279 }
1280
1281 return true;
1282 }
1283
1284 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1285 and [MEM2, MEM2 + SIZE] do overlap and false
1286 otherwise. */
1287
1288 bool
1289 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1290 {
1291 rtx addr1, addr2, addr_delta;
1292 HOST_WIDE_INT delta;
1293
1294 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1295 return true;
1296
1297 if (size == 0)
1298 return false;
1299
1300 addr1 = XEXP (mem1, 0);
1301 addr2 = XEXP (mem2, 0);
1302
1303 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1304
1305 /* This overlapping check is used by peepholes merging memory block operations.
1306 Overlapping operations would otherwise be recognized by the S/390 hardware
1307 and would fall back to a slower implementation. Allowing overlapping
1308 operations would lead to slow code but not to wrong code. Therefore we are
1309 somewhat optimistic if we cannot prove that the memory blocks are
1310 overlapping.
1311 That's why we return false here although this may accept operations on
1312 overlapping memory areas. */
1313 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1314 return false;
1315
1316 delta = INTVAL (addr_delta);
1317
1318 if (delta == 0
1319 || (delta > 0 && delta < size)
1320 || (delta < 0 && -delta < size))
1321 return true;
1322
1323 return false;
1324 }
1325
1326 /* Check whether the address of memory reference MEM2 equals exactly
1327 the address of memory reference MEM1 plus DELTA. Return true if
1328 we can prove this to be the case, false otherwise. */
1329
1330 bool
1331 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1332 {
1333 rtx addr1, addr2, addr_delta;
1334
1335 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1336 return false;
1337
1338 addr1 = XEXP (mem1, 0);
1339 addr2 = XEXP (mem2, 0);
1340
1341 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1342 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1343 return false;
1344
1345 return true;
1346 }
1347
1348 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1349
1350 void
1351 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1352 rtx *operands)
1353 {
1354 enum machine_mode wmode = mode;
1355 rtx dst = operands[0];
1356 rtx src1 = operands[1];
1357 rtx src2 = operands[2];
1358 rtx op, clob, tem;
1359
1360 /* If we cannot handle the operation directly, use a temp register. */
1361 if (!s390_logical_operator_ok_p (operands))
1362 dst = gen_reg_rtx (mode);
1363
1364 /* QImode and HImode patterns make sense only if we have a destination
1365 in memory. Otherwise perform the operation in SImode. */
1366 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1367 wmode = SImode;
1368
1369 /* Widen operands if required. */
1370 if (mode != wmode)
1371 {
1372 if (GET_CODE (dst) == SUBREG
1373 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1374 dst = tem;
1375 else if (REG_P (dst))
1376 dst = gen_rtx_SUBREG (wmode, dst, 0);
1377 else
1378 dst = gen_reg_rtx (wmode);
1379
1380 if (GET_CODE (src1) == SUBREG
1381 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1382 src1 = tem;
1383 else if (GET_MODE (src1) != VOIDmode)
1384 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1385
1386 if (GET_CODE (src2) == SUBREG
1387 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1388 src2 = tem;
1389 else if (GET_MODE (src2) != VOIDmode)
1390 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1391 }
1392
1393 /* Emit the instruction. */
1394 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1395 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1396 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1397
1398 /* Fix up the destination if needed. */
1399 if (dst != operands[0])
1400 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1401 }
1402
1403 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1404
1405 bool
1406 s390_logical_operator_ok_p (rtx *operands)
1407 {
1408 /* If the destination operand is in memory, it needs to coincide
1409 with one of the source operands. After reload, it has to be
1410 the first source operand. */
1411 if (GET_CODE (operands[0]) == MEM)
1412 return rtx_equal_p (operands[0], operands[1])
1413 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1414
1415 return true;
1416 }
1417
1418 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1419 operand IMMOP to switch from SS to SI type instructions. */
1420
1421 void
1422 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1423 {
1424 int def = code == AND ? -1 : 0;
1425 HOST_WIDE_INT mask;
1426 int part;
1427
1428 gcc_assert (GET_CODE (*memop) == MEM);
1429 gcc_assert (!MEM_VOLATILE_P (*memop));
1430
1431 mask = s390_extract_part (*immop, QImode, def);
1432 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1433 gcc_assert (part >= 0);
1434
1435 *memop = adjust_address (*memop, QImode, part);
1436 *immop = gen_int_mode (mask, QImode);
1437 }
1438
1439
1440 /* How to allocate a 'struct machine_function'. */
1441
1442 static struct machine_function *
1443 s390_init_machine_status (void)
1444 {
1445 return GGC_CNEW (struct machine_function);
1446 }
1447
1448 /* Change optimizations to be performed, depending on the
1449 optimization level.
1450
1451 LEVEL is the optimization level specified; 2 if `-O2' is
1452 specified, 1 if `-O' is specified, and 0 if neither is specified.
1453
1454 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1455
1456 void
1457 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1458 {
1459 /* ??? There are apparently still problems with -fcaller-saves. */
1460 flag_caller_saves = 0;
1461
1462 /* By default, always emit DWARF-2 unwind info. This allows debugging
1463 without maintaining a stack frame back-chain. */
1464 flag_asynchronous_unwind_tables = 1;
1465
1466 /* Use MVCLE instructions to decrease code size if requested. */
1467 if (size != 0)
1468 target_flags |= MASK_MVCLE;
1469 }
1470
1471 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1472 to the associated processor_type and processor_flags if so. */
1473
1474 static bool
1475 s390_handle_arch_option (const char *arg,
1476 enum processor_type *type,
1477 int *flags)
1478 {
1479 static struct pta
1480 {
1481 const char *const name; /* processor name or nickname. */
1482 const enum processor_type processor;
1483 const int flags; /* From enum processor_flags. */
1484 }
1485 const processor_alias_table[] =
1486 {
1487 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1488 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1489 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1490 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1491 | PF_LONG_DISPLACEMENT},
1492 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1493 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1494 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1495 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1496 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1497 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1498 };
1499 size_t i;
1500
1501 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1502 if (strcmp (arg, processor_alias_table[i].name) == 0)
1503 {
1504 *type = processor_alias_table[i].processor;
1505 *flags = processor_alias_table[i].flags;
1506 return true;
1507 }
1508 return false;
1509 }
1510
1511 /* Implement TARGET_HANDLE_OPTION. */
1512
1513 static bool
1514 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1515 {
1516 switch (code)
1517 {
1518 case OPT_march_:
1519 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1520
1521 case OPT_mstack_guard_:
1522 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1523 return false;
1524 if (exact_log2 (s390_stack_guard) == -1)
1525 error ("stack guard value must be an exact power of 2");
1526 return true;
1527
1528 case OPT_mstack_size_:
1529 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1530 return false;
1531 if (exact_log2 (s390_stack_size) == -1)
1532 error ("stack size must be an exact power of 2");
1533 return true;
1534
1535 case OPT_mtune_:
1536 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1537
1538 case OPT_mwarn_framesize_:
1539 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1540
1541 default:
1542 return true;
1543 }
1544 }
1545
1546 void
1547 override_options (void)
1548 {
1549 /* Set up function hooks. */
1550 init_machine_status = s390_init_machine_status;
1551
1552 /* Architecture mode defaults according to ABI. */
1553 if (!(target_flags_explicit & MASK_ZARCH))
1554 {
1555 if (TARGET_64BIT)
1556 target_flags |= MASK_ZARCH;
1557 else
1558 target_flags &= ~MASK_ZARCH;
1559 }
1560
1561 /* Determine processor architectural level. */
1562 if (!s390_arch_string)
1563 {
1564 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1565 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1566 }
1567
1568 /* Determine processor to tune for. */
1569 if (s390_tune == PROCESSOR_max)
1570 {
1571 s390_tune = s390_arch;
1572 s390_tune_flags = s390_arch_flags;
1573 }
1574
1575 /* Sanity checks. */
1576 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1577 error ("z/Architecture mode not supported on %s", s390_arch_string);
1578 if (TARGET_64BIT && !TARGET_ZARCH)
1579 error ("64-bit ABI not supported in ESA/390 mode");
1580
1581 if (TARGET_HARD_DFP && !TARGET_DFP)
1582 {
1583 if (target_flags_explicit & MASK_HARD_DFP)
1584 {
1585 if (!TARGET_CPU_DFP)
1586 error ("Hardware decimal floating point instructions"
1587 " not available on %s", s390_arch_string);
1588 if (!TARGET_ZARCH)
1589 error ("Hardware decimal floating point instructions"
1590 " not available in ESA/390 mode");
1591 }
1592 else
1593 target_flags &= ~MASK_HARD_DFP;
1594 }
1595
1596 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1597 {
1598 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1599 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1600
1601 target_flags &= ~MASK_HARD_DFP;
1602 }
1603
1604 /* Set processor cost function. */
1605 switch (s390_tune)
1606 {
1607 case PROCESSOR_2084_Z990:
1608 s390_cost = &z990_cost;
1609 break;
1610 case PROCESSOR_2094_Z9_109:
1611 s390_cost = &z9_109_cost;
1612 break;
1613 case PROCESSOR_2097_Z10:
1614 s390_cost = &z10_cost;
1615 break;
1616 default:
1617 s390_cost = &z900_cost;
1618 }
1619
1620 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1621 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1622 "in combination");
1623
1624 if (s390_stack_size)
1625 {
1626 if (s390_stack_guard >= s390_stack_size)
1627 error ("stack size must be greater than the stack guard value");
1628 else if (s390_stack_size > 1 << 16)
1629 error ("stack size must not be greater than 64k");
1630 }
1631 else if (s390_stack_guard)
1632 error ("-mstack-guard implies use of -mstack-size");
1633
1634 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1635 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1636 target_flags |= MASK_LONG_DOUBLE_128;
1637 #endif
1638
1639 if (s390_tune == PROCESSOR_2097_Z10
1640 && !PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1641 set_param_value ("max-unrolled-insns", 100);
1642
1643 set_param_value ("max-pending-list-length", 256);
1644
1645 }
1646
1647 /* Map for smallest class containing reg regno. */
1648
1649 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1650 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1651 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1652 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1653 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1658 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1659 ACCESS_REGS, ACCESS_REGS
1660 };
1661
1662 /* Return attribute type of insn. */
1663
1664 static enum attr_type
1665 s390_safe_attr_type (rtx insn)
1666 {
1667 if (recog_memoized (insn) >= 0)
1668 return get_attr_type (insn);
1669 else
1670 return TYPE_NONE;
1671 }
1672
1673 /* Return true if DISP is a valid short displacement. */
1674
1675 static bool
1676 s390_short_displacement (rtx disp)
1677 {
1678 /* No displacement is OK. */
1679 if (!disp)
1680 return true;
1681
1682 /* Without the long displacement facility we don't need to
1683 distingiush between long and short displacement. */
1684 if (!TARGET_LONG_DISPLACEMENT)
1685 return true;
1686
1687 /* Integer displacement in range. */
1688 if (GET_CODE (disp) == CONST_INT)
1689 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1690
1691 /* GOT offset is not OK, the GOT can be large. */
1692 if (GET_CODE (disp) == CONST
1693 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1694 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1695 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1696 return false;
1697
1698 /* All other symbolic constants are literal pool references,
1699 which are OK as the literal pool must be small. */
1700 if (GET_CODE (disp) == CONST)
1701 return true;
1702
1703 return false;
1704 }
1705
1706 /* Decompose a RTL expression ADDR for a memory address into
1707 its components, returned in OUT.
1708
1709 Returns false if ADDR is not a valid memory address, true
1710 otherwise. If OUT is NULL, don't return the components,
1711 but check for validity only.
1712
1713 Note: Only addresses in canonical form are recognized.
1714 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1715 canonical form so that they will be recognized. */
1716
1717 static int
1718 s390_decompose_address (rtx addr, struct s390_address *out)
1719 {
1720 HOST_WIDE_INT offset = 0;
1721 rtx base = NULL_RTX;
1722 rtx indx = NULL_RTX;
1723 rtx disp = NULL_RTX;
1724 rtx orig_disp;
1725 bool pointer = false;
1726 bool base_ptr = false;
1727 bool indx_ptr = false;
1728 bool literal_pool = false;
1729
1730 /* We may need to substitute the literal pool base register into the address
1731 below. However, at this point we do not know which register is going to
1732 be used as base, so we substitute the arg pointer register. This is going
1733 to be treated as holding a pointer below -- it shouldn't be used for any
1734 other purpose. */
1735 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1736
1737 /* Decompose address into base + index + displacement. */
1738
1739 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1740 base = addr;
1741
1742 else if (GET_CODE (addr) == PLUS)
1743 {
1744 rtx op0 = XEXP (addr, 0);
1745 rtx op1 = XEXP (addr, 1);
1746 enum rtx_code code0 = GET_CODE (op0);
1747 enum rtx_code code1 = GET_CODE (op1);
1748
1749 if (code0 == REG || code0 == UNSPEC)
1750 {
1751 if (code1 == REG || code1 == UNSPEC)
1752 {
1753 indx = op0; /* index + base */
1754 base = op1;
1755 }
1756
1757 else
1758 {
1759 base = op0; /* base + displacement */
1760 disp = op1;
1761 }
1762 }
1763
1764 else if (code0 == PLUS)
1765 {
1766 indx = XEXP (op0, 0); /* index + base + disp */
1767 base = XEXP (op0, 1);
1768 disp = op1;
1769 }
1770
1771 else
1772 {
1773 return false;
1774 }
1775 }
1776
1777 else
1778 disp = addr; /* displacement */
1779
1780 /* Extract integer part of displacement. */
1781 orig_disp = disp;
1782 if (disp)
1783 {
1784 if (GET_CODE (disp) == CONST_INT)
1785 {
1786 offset = INTVAL (disp);
1787 disp = NULL_RTX;
1788 }
1789 else if (GET_CODE (disp) == CONST
1790 && GET_CODE (XEXP (disp, 0)) == PLUS
1791 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1792 {
1793 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1794 disp = XEXP (XEXP (disp, 0), 0);
1795 }
1796 }
1797
1798 /* Strip off CONST here to avoid special case tests later. */
1799 if (disp && GET_CODE (disp) == CONST)
1800 disp = XEXP (disp, 0);
1801
1802 /* We can convert literal pool addresses to
1803 displacements by basing them off the base register. */
1804 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1805 {
1806 /* Either base or index must be free to hold the base register. */
1807 if (!base)
1808 base = fake_pool_base, literal_pool = true;
1809 else if (!indx)
1810 indx = fake_pool_base, literal_pool = true;
1811 else
1812 return false;
1813
1814 /* Mark up the displacement. */
1815 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1816 UNSPEC_LTREL_OFFSET);
1817 }
1818
1819 /* Validate base register. */
1820 if (base)
1821 {
1822 if (GET_CODE (base) == UNSPEC)
1823 switch (XINT (base, 1))
1824 {
1825 case UNSPEC_LTREF:
1826 if (!disp)
1827 disp = gen_rtx_UNSPEC (Pmode,
1828 gen_rtvec (1, XVECEXP (base, 0, 0)),
1829 UNSPEC_LTREL_OFFSET);
1830 else
1831 return false;
1832
1833 base = XVECEXP (base, 0, 1);
1834 break;
1835
1836 case UNSPEC_LTREL_BASE:
1837 if (XVECLEN (base, 0) == 1)
1838 base = fake_pool_base, literal_pool = true;
1839 else
1840 base = XVECEXP (base, 0, 1);
1841 break;
1842
1843 default:
1844 return false;
1845 }
1846
1847 if (!REG_P (base)
1848 || (GET_MODE (base) != SImode
1849 && GET_MODE (base) != Pmode))
1850 return false;
1851
1852 if (REGNO (base) == STACK_POINTER_REGNUM
1853 || REGNO (base) == FRAME_POINTER_REGNUM
1854 || ((reload_completed || reload_in_progress)
1855 && frame_pointer_needed
1856 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1857 || REGNO (base) == ARG_POINTER_REGNUM
1858 || (flag_pic
1859 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1860 pointer = base_ptr = true;
1861
1862 if ((reload_completed || reload_in_progress)
1863 && base == cfun->machine->base_reg)
1864 pointer = base_ptr = literal_pool = true;
1865 }
1866
1867 /* Validate index register. */
1868 if (indx)
1869 {
1870 if (GET_CODE (indx) == UNSPEC)
1871 switch (XINT (indx, 1))
1872 {
1873 case UNSPEC_LTREF:
1874 if (!disp)
1875 disp = gen_rtx_UNSPEC (Pmode,
1876 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1877 UNSPEC_LTREL_OFFSET);
1878 else
1879 return false;
1880
1881 indx = XVECEXP (indx, 0, 1);
1882 break;
1883
1884 case UNSPEC_LTREL_BASE:
1885 if (XVECLEN (indx, 0) == 1)
1886 indx = fake_pool_base, literal_pool = true;
1887 else
1888 indx = XVECEXP (indx, 0, 1);
1889 break;
1890
1891 default:
1892 return false;
1893 }
1894
1895 if (!REG_P (indx)
1896 || (GET_MODE (indx) != SImode
1897 && GET_MODE (indx) != Pmode))
1898 return false;
1899
1900 if (REGNO (indx) == STACK_POINTER_REGNUM
1901 || REGNO (indx) == FRAME_POINTER_REGNUM
1902 || ((reload_completed || reload_in_progress)
1903 && frame_pointer_needed
1904 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1905 || REGNO (indx) == ARG_POINTER_REGNUM
1906 || (flag_pic
1907 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1908 pointer = indx_ptr = true;
1909
1910 if ((reload_completed || reload_in_progress)
1911 && indx == cfun->machine->base_reg)
1912 pointer = indx_ptr = literal_pool = true;
1913 }
1914
1915 /* Prefer to use pointer as base, not index. */
1916 if (base && indx && !base_ptr
1917 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1918 {
1919 rtx tmp = base;
1920 base = indx;
1921 indx = tmp;
1922 }
1923
1924 /* Validate displacement. */
1925 if (!disp)
1926 {
1927 /* If virtual registers are involved, the displacement will change later
1928 anyway as the virtual registers get eliminated. This could make a
1929 valid displacement invalid, but it is more likely to make an invalid
1930 displacement valid, because we sometimes access the register save area
1931 via negative offsets to one of those registers.
1932 Thus we don't check the displacement for validity here. If after
1933 elimination the displacement turns out to be invalid after all,
1934 this is fixed up by reload in any case. */
1935 if (base != arg_pointer_rtx
1936 && indx != arg_pointer_rtx
1937 && base != return_address_pointer_rtx
1938 && indx != return_address_pointer_rtx
1939 && base != frame_pointer_rtx
1940 && indx != frame_pointer_rtx
1941 && base != virtual_stack_vars_rtx
1942 && indx != virtual_stack_vars_rtx)
1943 if (!DISP_IN_RANGE (offset))
1944 return false;
1945 }
1946 else
1947 {
1948 /* All the special cases are pointers. */
1949 pointer = true;
1950
1951 /* In the small-PIC case, the linker converts @GOT
1952 and @GOTNTPOFF offsets to possible displacements. */
1953 if (GET_CODE (disp) == UNSPEC
1954 && (XINT (disp, 1) == UNSPEC_GOT
1955 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1956 && flag_pic == 1)
1957 {
1958 ;
1959 }
1960
1961 /* Accept pool label offsets. */
1962 else if (GET_CODE (disp) == UNSPEC
1963 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1964 ;
1965
1966 /* Accept literal pool references. */
1967 else if (GET_CODE (disp) == UNSPEC
1968 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1969 {
1970 orig_disp = gen_rtx_CONST (Pmode, disp);
1971 if (offset)
1972 {
1973 /* If we have an offset, make sure it does not
1974 exceed the size of the constant pool entry. */
1975 rtx sym = XVECEXP (disp, 0, 0);
1976 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1977 return false;
1978
1979 orig_disp = plus_constant (orig_disp, offset);
1980 }
1981 }
1982
1983 else
1984 return false;
1985 }
1986
1987 if (!base && !indx)
1988 pointer = true;
1989
1990 if (out)
1991 {
1992 out->base = base;
1993 out->indx = indx;
1994 out->disp = orig_disp;
1995 out->pointer = pointer;
1996 out->literal_pool = literal_pool;
1997 }
1998
1999 return true;
2000 }
2001
2002 /* Decompose a RTL expression OP for a shift count into its components,
2003 and return the base register in BASE and the offset in OFFSET.
2004
2005 Return true if OP is a valid shift count, false if not. */
2006
2007 bool
2008 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2009 {
2010 HOST_WIDE_INT off = 0;
2011
2012 /* We can have an integer constant, an address register,
2013 or a sum of the two. */
2014 if (GET_CODE (op) == CONST_INT)
2015 {
2016 off = INTVAL (op);
2017 op = NULL_RTX;
2018 }
2019 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2020 {
2021 off = INTVAL (XEXP (op, 1));
2022 op = XEXP (op, 0);
2023 }
2024 while (op && GET_CODE (op) == SUBREG)
2025 op = SUBREG_REG (op);
2026
2027 if (op && GET_CODE (op) != REG)
2028 return false;
2029
2030 if (offset)
2031 *offset = off;
2032 if (base)
2033 *base = op;
2034
2035 return true;
2036 }
2037
2038
2039 /* Return true if CODE is a valid address without index. */
2040
2041 bool
2042 s390_legitimate_address_without_index_p (rtx op)
2043 {
2044 struct s390_address addr;
2045
2046 if (!s390_decompose_address (XEXP (op, 0), &addr))
2047 return false;
2048 if (addr.indx)
2049 return false;
2050
2051 return true;
2052 }
2053
2054
2055 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2056 and return these parts in SYMREF and ADDEND. You can pass NULL in
2057 SYMREF and/or ADDEND if you are not interested in these values. */
2058
2059 static bool
2060 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2061 {
2062 HOST_WIDE_INT tmpaddend = 0;
2063
2064 if (GET_CODE (addr) == CONST)
2065 addr = XEXP (addr, 0);
2066
2067 if (GET_CODE (addr) == PLUS)
2068 {
2069 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2070 && CONST_INT_P (XEXP (addr, 1)))
2071 {
2072 tmpaddend = INTVAL (XEXP (addr, 1));
2073 addr = XEXP (addr, 0);
2074 }
2075 else
2076 return false;
2077 }
2078 else
2079 if (GET_CODE (addr) != SYMBOL_REF)
2080 return false;
2081
2082 if (symref)
2083 *symref = addr;
2084 if (addend)
2085 *addend = tmpaddend;
2086
2087 return true;
2088 }
2089
2090
2091 /* Return true if the address in OP is valid for constraint letter C
2092 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2093 pool MEMs should be accepted. Only the Q, R, S, T constraint
2094 letters are allowed for C. */
2095
2096 static int
2097 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2098 {
2099 struct s390_address addr;
2100 bool decomposed = false;
2101
2102 /* This check makes sure that no symbolic address (except literal
2103 pool references) are accepted by the R or T constraints. */
2104 if (s390_symref_operand_p (op, NULL, NULL))
2105 {
2106 if (!lit_pool_ok)
2107 return 0;
2108 if (!s390_decompose_address (op, &addr))
2109 return 0;
2110 if (!addr.literal_pool)
2111 return 0;
2112 decomposed = true;
2113 }
2114
2115 switch (c)
2116 {
2117 case 'Q': /* no index short displacement */
2118 if (!decomposed && !s390_decompose_address (op, &addr))
2119 return 0;
2120 if (addr.indx)
2121 return 0;
2122 if (!s390_short_displacement (addr.disp))
2123 return 0;
2124 break;
2125
2126 case 'R': /* with index short displacement */
2127 if (TARGET_LONG_DISPLACEMENT)
2128 {
2129 if (!decomposed && !s390_decompose_address (op, &addr))
2130 return 0;
2131 if (!s390_short_displacement (addr.disp))
2132 return 0;
2133 }
2134 /* Any invalid address here will be fixed up by reload,
2135 so accept it for the most generic constraint. */
2136 break;
2137
2138 case 'S': /* no index long displacement */
2139 if (!TARGET_LONG_DISPLACEMENT)
2140 return 0;
2141 if (!decomposed && !s390_decompose_address (op, &addr))
2142 return 0;
2143 if (addr.indx)
2144 return 0;
2145 if (s390_short_displacement (addr.disp))
2146 return 0;
2147 break;
2148
2149 case 'T': /* with index long displacement */
2150 if (!TARGET_LONG_DISPLACEMENT)
2151 return 0;
2152 /* Any invalid address here will be fixed up by reload,
2153 so accept it for the most generic constraint. */
2154 if ((decomposed || s390_decompose_address (op, &addr))
2155 && s390_short_displacement (addr.disp))
2156 return 0;
2157 break;
2158 default:
2159 return 0;
2160 }
2161 return 1;
2162 }
2163
2164
2165 /* Evaluates constraint strings described by the regular expression
2166 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2167 the constraint given in STR, or 0 else. */
2168
2169 int
2170 s390_mem_constraint (const char *str, rtx op)
2171 {
2172 char c = str[0];
2173
2174 switch (c)
2175 {
2176 case 'A':
2177 /* Check for offsettable variants of memory constraints. */
2178 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2179 return 0;
2180 if ((reload_completed || reload_in_progress)
2181 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2182 return 0;
2183 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2184 case 'B':
2185 /* Check for non-literal-pool variants of memory constraints. */
2186 if (!MEM_P (op))
2187 return 0;
2188 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2189 case 'Q':
2190 case 'R':
2191 case 'S':
2192 case 'T':
2193 if (GET_CODE (op) != MEM)
2194 return 0;
2195 return s390_check_qrst_address (c, XEXP (op, 0), true);
2196 case 'U':
2197 return (s390_check_qrst_address ('Q', op, true)
2198 || s390_check_qrst_address ('R', op, true));
2199 case 'W':
2200 return (s390_check_qrst_address ('S', op, true)
2201 || s390_check_qrst_address ('T', op, true));
2202 case 'Y':
2203 /* Simply check for the basic form of a shift count. Reload will
2204 take care of making sure we have a proper base register. */
2205 if (!s390_decompose_shift_count (op, NULL, NULL))
2206 return 0;
2207 break;
2208 case 'Z':
2209 return s390_check_qrst_address (str[1], op, true);
2210 default:
2211 return 0;
2212 }
2213 return 1;
2214 }
2215
2216
2217 /* Evaluates constraint strings starting with letter O. Input
2218 parameter C is the second letter following the "O" in the constraint
2219 string. Returns 1 if VALUE meets the respective constraint and 0
2220 otherwise. */
2221
2222 int
2223 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2224 {
2225 if (!TARGET_EXTIMM)
2226 return 0;
2227
2228 switch (c)
2229 {
2230 case 's':
2231 return trunc_int_for_mode (value, SImode) == value;
2232
2233 case 'p':
2234 return value == 0
2235 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2236
2237 case 'n':
2238 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2239
2240 default:
2241 gcc_unreachable ();
2242 }
2243 }
2244
2245
2246 /* Evaluates constraint strings starting with letter N. Parameter STR
2247 contains the letters following letter "N" in the constraint string.
2248 Returns true if VALUE matches the constraint. */
2249
2250 int
2251 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2252 {
2253 enum machine_mode mode, part_mode;
2254 int def;
2255 int part, part_goal;
2256
2257
2258 if (str[0] == 'x')
2259 part_goal = -1;
2260 else
2261 part_goal = str[0] - '0';
2262
2263 switch (str[1])
2264 {
2265 case 'Q':
2266 part_mode = QImode;
2267 break;
2268 case 'H':
2269 part_mode = HImode;
2270 break;
2271 case 'S':
2272 part_mode = SImode;
2273 break;
2274 default:
2275 return 0;
2276 }
2277
2278 switch (str[2])
2279 {
2280 case 'H':
2281 mode = HImode;
2282 break;
2283 case 'S':
2284 mode = SImode;
2285 break;
2286 case 'D':
2287 mode = DImode;
2288 break;
2289 default:
2290 return 0;
2291 }
2292
2293 switch (str[3])
2294 {
2295 case '0':
2296 def = 0;
2297 break;
2298 case 'F':
2299 def = -1;
2300 break;
2301 default:
2302 return 0;
2303 }
2304
2305 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2306 return 0;
2307
2308 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2309 if (part < 0)
2310 return 0;
2311 if (part_goal != -1 && part_goal != part)
2312 return 0;
2313
2314 return 1;
2315 }
2316
2317
2318 /* Returns true if the input parameter VALUE is a float zero. */
2319
2320 int
2321 s390_float_const_zero_p (rtx value)
2322 {
2323 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2324 && value == CONST0_RTX (GET_MODE (value)));
2325 }
2326
2327
2328 /* Compute a (partial) cost for rtx X. Return true if the complete
2329 cost has been computed, and false if subexpressions should be
2330 scanned. In either case, *TOTAL contains the cost result.
2331 CODE contains GET_CODE (x), OUTER_CODE contains the code
2332 of the superexpression of x. */
2333
2334 static bool
2335 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2336 bool speed ATTRIBUTE_UNUSED)
2337 {
2338 switch (code)
2339 {
2340 case CONST:
2341 case CONST_INT:
2342 case LABEL_REF:
2343 case SYMBOL_REF:
2344 case CONST_DOUBLE:
2345 case MEM:
2346 *total = 0;
2347 return true;
2348
2349 case ASHIFT:
2350 case ASHIFTRT:
2351 case LSHIFTRT:
2352 case ROTATE:
2353 case ROTATERT:
2354 case AND:
2355 case IOR:
2356 case XOR:
2357 case NEG:
2358 case NOT:
2359 *total = COSTS_N_INSNS (1);
2360 return false;
2361
2362 case PLUS:
2363 case MINUS:
2364 /* Check for multiply and add. */
2365 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2366 && GET_CODE (XEXP (x, 0)) == MULT
2367 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2368 {
2369 /* This is the multiply and add case. */
2370 if (GET_MODE (x) == DFmode)
2371 *total = s390_cost->madbr;
2372 else
2373 *total = s390_cost->maebr;
2374 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2375 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2376 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2377 return true; /* Do not do an additional recursive descent. */
2378 }
2379 *total = COSTS_N_INSNS (1);
2380 return false;
2381
2382 case MULT:
2383 switch (GET_MODE (x))
2384 {
2385 case SImode:
2386 {
2387 rtx left = XEXP (x, 0);
2388 rtx right = XEXP (x, 1);
2389 if (GET_CODE (right) == CONST_INT
2390 && CONST_OK_FOR_K (INTVAL (right)))
2391 *total = s390_cost->mhi;
2392 else if (GET_CODE (left) == SIGN_EXTEND)
2393 *total = s390_cost->mh;
2394 else
2395 *total = s390_cost->ms; /* msr, ms, msy */
2396 break;
2397 }
2398 case DImode:
2399 {
2400 rtx left = XEXP (x, 0);
2401 rtx right = XEXP (x, 1);
2402 if (TARGET_64BIT)
2403 {
2404 if (GET_CODE (right) == CONST_INT
2405 && CONST_OK_FOR_K (INTVAL (right)))
2406 *total = s390_cost->mghi;
2407 else if (GET_CODE (left) == SIGN_EXTEND)
2408 *total = s390_cost->msgf;
2409 else
2410 *total = s390_cost->msg; /* msgr, msg */
2411 }
2412 else /* TARGET_31BIT */
2413 {
2414 if (GET_CODE (left) == SIGN_EXTEND
2415 && GET_CODE (right) == SIGN_EXTEND)
2416 /* mulsidi case: mr, m */
2417 *total = s390_cost->m;
2418 else if (GET_CODE (left) == ZERO_EXTEND
2419 && GET_CODE (right) == ZERO_EXTEND
2420 && TARGET_CPU_ZARCH)
2421 /* umulsidi case: ml, mlr */
2422 *total = s390_cost->ml;
2423 else
2424 /* Complex calculation is required. */
2425 *total = COSTS_N_INSNS (40);
2426 }
2427 break;
2428 }
2429 case SFmode:
2430 case DFmode:
2431 *total = s390_cost->mult_df;
2432 break;
2433 case TFmode:
2434 *total = s390_cost->mxbr;
2435 break;
2436 default:
2437 return false;
2438 }
2439 return false;
2440
2441 case UDIV:
2442 case UMOD:
2443 if (GET_MODE (x) == TImode) /* 128 bit division */
2444 *total = s390_cost->dlgr;
2445 else if (GET_MODE (x) == DImode)
2446 {
2447 rtx right = XEXP (x, 1);
2448 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2449 *total = s390_cost->dlr;
2450 else /* 64 by 64 bit division */
2451 *total = s390_cost->dlgr;
2452 }
2453 else if (GET_MODE (x) == SImode) /* 32 bit division */
2454 *total = s390_cost->dlr;
2455 return false;
2456
2457 case DIV:
2458 case MOD:
2459 if (GET_MODE (x) == DImode)
2460 {
2461 rtx right = XEXP (x, 1);
2462 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2463 if (TARGET_64BIT)
2464 *total = s390_cost->dsgfr;
2465 else
2466 *total = s390_cost->dr;
2467 else /* 64 by 64 bit division */
2468 *total = s390_cost->dsgr;
2469 }
2470 else if (GET_MODE (x) == SImode) /* 32 bit division */
2471 *total = s390_cost->dlr;
2472 else if (GET_MODE (x) == SFmode)
2473 {
2474 *total = s390_cost->debr;
2475 }
2476 else if (GET_MODE (x) == DFmode)
2477 {
2478 *total = s390_cost->ddbr;
2479 }
2480 else if (GET_MODE (x) == TFmode)
2481 {
2482 *total = s390_cost->dxbr;
2483 }
2484 return false;
2485
2486 case SQRT:
2487 if (GET_MODE (x) == SFmode)
2488 *total = s390_cost->sqebr;
2489 else if (GET_MODE (x) == DFmode)
2490 *total = s390_cost->sqdbr;
2491 else /* TFmode */
2492 *total = s390_cost->sqxbr;
2493 return false;
2494
2495 case SIGN_EXTEND:
2496 case ZERO_EXTEND:
2497 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2498 || outer_code == PLUS || outer_code == MINUS
2499 || outer_code == COMPARE)
2500 *total = 0;
2501 return false;
2502
2503 case COMPARE:
2504 *total = COSTS_N_INSNS (1);
2505 if (GET_CODE (XEXP (x, 0)) == AND
2506 && GET_CODE (XEXP (x, 1)) == CONST_INT
2507 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2508 {
2509 rtx op0 = XEXP (XEXP (x, 0), 0);
2510 rtx op1 = XEXP (XEXP (x, 0), 1);
2511 rtx op2 = XEXP (x, 1);
2512
2513 if (memory_operand (op0, GET_MODE (op0))
2514 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2515 return true;
2516 if (register_operand (op0, GET_MODE (op0))
2517 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2518 return true;
2519 }
2520 return false;
2521
2522 default:
2523 return false;
2524 }
2525 }
2526
2527 /* Return the cost of an address rtx ADDR. */
2528
2529 static int
2530 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2531 {
2532 struct s390_address ad;
2533 if (!s390_decompose_address (addr, &ad))
2534 return 1000;
2535
2536 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2537 }
2538
2539 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2540 otherwise return 0. */
2541
2542 int
2543 tls_symbolic_operand (rtx op)
2544 {
2545 if (GET_CODE (op) != SYMBOL_REF)
2546 return 0;
2547 return SYMBOL_REF_TLS_MODEL (op);
2548 }
2549 \f
2550 /* Split DImode access register reference REG (on 64-bit) into its constituent
2551 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2552 gen_highpart cannot be used as they assume all registers are word-sized,
2553 while our access registers have only half that size. */
2554
2555 void
2556 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2557 {
2558 gcc_assert (TARGET_64BIT);
2559 gcc_assert (ACCESS_REG_P (reg));
2560 gcc_assert (GET_MODE (reg) == DImode);
2561 gcc_assert (!(REGNO (reg) & 1));
2562
2563 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2564 *hi = gen_rtx_REG (SImode, REGNO (reg));
2565 }
2566
2567 /* Return true if OP contains a symbol reference */
2568
2569 bool
2570 symbolic_reference_mentioned_p (rtx op)
2571 {
2572 const char *fmt;
2573 int i;
2574
2575 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2576 return 1;
2577
2578 fmt = GET_RTX_FORMAT (GET_CODE (op));
2579 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2580 {
2581 if (fmt[i] == 'E')
2582 {
2583 int j;
2584
2585 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2586 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2587 return 1;
2588 }
2589
2590 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2591 return 1;
2592 }
2593
2594 return 0;
2595 }
2596
2597 /* Return true if OP contains a reference to a thread-local symbol. */
2598
2599 bool
2600 tls_symbolic_reference_mentioned_p (rtx op)
2601 {
2602 const char *fmt;
2603 int i;
2604
2605 if (GET_CODE (op) == SYMBOL_REF)
2606 return tls_symbolic_operand (op);
2607
2608 fmt = GET_RTX_FORMAT (GET_CODE (op));
2609 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2610 {
2611 if (fmt[i] == 'E')
2612 {
2613 int j;
2614
2615 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2616 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2617 return true;
2618 }
2619
2620 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2621 return true;
2622 }
2623
2624 return false;
2625 }
2626
2627
2628 /* Return true if OP is a legitimate general operand when
2629 generating PIC code. It is given that flag_pic is on
2630 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2631
2632 int
2633 legitimate_pic_operand_p (rtx op)
2634 {
2635 /* Accept all non-symbolic constants. */
2636 if (!SYMBOLIC_CONST (op))
2637 return 1;
2638
2639 /* Reject everything else; must be handled
2640 via emit_symbolic_move. */
2641 return 0;
2642 }
2643
2644 /* Returns true if the constant value OP is a legitimate general operand.
2645 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2646
2647 int
2648 legitimate_constant_p (rtx op)
2649 {
2650 /* Accept all non-symbolic constants. */
2651 if (!SYMBOLIC_CONST (op))
2652 return 1;
2653
2654 /* Accept immediate LARL operands. */
2655 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2656 return 1;
2657
2658 /* Thread-local symbols are never legal constants. This is
2659 so that emit_call knows that computing such addresses
2660 might require a function call. */
2661 if (TLS_SYMBOLIC_CONST (op))
2662 return 0;
2663
2664 /* In the PIC case, symbolic constants must *not* be
2665 forced into the literal pool. We accept them here,
2666 so that they will be handled by emit_symbolic_move. */
2667 if (flag_pic)
2668 return 1;
2669
2670 /* All remaining non-PIC symbolic constants are
2671 forced into the literal pool. */
2672 return 0;
2673 }
2674
2675 /* Determine if it's legal to put X into the constant pool. This
2676 is not possible if X contains the address of a symbol that is
2677 not constant (TLS) or not known at final link time (PIC). */
2678
2679 static bool
2680 s390_cannot_force_const_mem (rtx x)
2681 {
2682 switch (GET_CODE (x))
2683 {
2684 case CONST_INT:
2685 case CONST_DOUBLE:
2686 /* Accept all non-symbolic constants. */
2687 return false;
2688
2689 case LABEL_REF:
2690 /* Labels are OK iff we are non-PIC. */
2691 return flag_pic != 0;
2692
2693 case SYMBOL_REF:
2694 /* 'Naked' TLS symbol references are never OK,
2695 non-TLS symbols are OK iff we are non-PIC. */
2696 if (tls_symbolic_operand (x))
2697 return true;
2698 else
2699 return flag_pic != 0;
2700
2701 case CONST:
2702 return s390_cannot_force_const_mem (XEXP (x, 0));
2703 case PLUS:
2704 case MINUS:
2705 return s390_cannot_force_const_mem (XEXP (x, 0))
2706 || s390_cannot_force_const_mem (XEXP (x, 1));
2707
2708 case UNSPEC:
2709 switch (XINT (x, 1))
2710 {
2711 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2712 case UNSPEC_LTREL_OFFSET:
2713 case UNSPEC_GOT:
2714 case UNSPEC_GOTOFF:
2715 case UNSPEC_PLTOFF:
2716 case UNSPEC_TLSGD:
2717 case UNSPEC_TLSLDM:
2718 case UNSPEC_NTPOFF:
2719 case UNSPEC_DTPOFF:
2720 case UNSPEC_GOTNTPOFF:
2721 case UNSPEC_INDNTPOFF:
2722 return false;
2723
2724 /* If the literal pool shares the code section, be put
2725 execute template placeholders into the pool as well. */
2726 case UNSPEC_INSN:
2727 return TARGET_CPU_ZARCH;
2728
2729 default:
2730 return true;
2731 }
2732 break;
2733
2734 default:
2735 gcc_unreachable ();
2736 }
2737 }
2738
2739 /* Returns true if the constant value OP is a legitimate general
2740 operand during and after reload. The difference to
2741 legitimate_constant_p is that this function will not accept
2742 a constant that would need to be forced to the literal pool
2743 before it can be used as operand. */
2744
2745 bool
2746 legitimate_reload_constant_p (rtx op)
2747 {
2748 /* Accept la(y) operands. */
2749 if (GET_CODE (op) == CONST_INT
2750 && DISP_IN_RANGE (INTVAL (op)))
2751 return true;
2752
2753 /* Accept l(g)hi/l(g)fi operands. */
2754 if (GET_CODE (op) == CONST_INT
2755 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2756 return true;
2757
2758 /* Accept lliXX operands. */
2759 if (TARGET_ZARCH
2760 && GET_CODE (op) == CONST_INT
2761 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2762 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2763 return true;
2764
2765 if (TARGET_EXTIMM
2766 && GET_CODE (op) == CONST_INT
2767 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2768 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2769 return true;
2770
2771 /* Accept larl operands. */
2772 if (TARGET_CPU_ZARCH
2773 && larl_operand (op, VOIDmode))
2774 return true;
2775
2776 /* Accept lzXX operands. */
2777 if (GET_CODE (op) == CONST_DOUBLE
2778 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2779 return true;
2780
2781 /* Accept double-word operands that can be split. */
2782 if (GET_CODE (op) == CONST_INT
2783 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2784 {
2785 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2786 rtx hi = operand_subword (op, 0, 0, dword_mode);
2787 rtx lo = operand_subword (op, 1, 0, dword_mode);
2788 return legitimate_reload_constant_p (hi)
2789 && legitimate_reload_constant_p (lo);
2790 }
2791
2792 /* Everything else cannot be handled without reload. */
2793 return false;
2794 }
2795
2796 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2797 return the class of reg to actually use. */
2798
2799 enum reg_class
2800 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2801 {
2802 switch (GET_CODE (op))
2803 {
2804 /* Constants we cannot reload must be forced into the
2805 literal pool. */
2806
2807 case CONST_DOUBLE:
2808 case CONST_INT:
2809 if (legitimate_reload_constant_p (op))
2810 return rclass;
2811 else
2812 return NO_REGS;
2813
2814 /* If a symbolic constant or a PLUS is reloaded,
2815 it is most likely being used as an address, so
2816 prefer ADDR_REGS. If 'class' is not a superset
2817 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2818 case PLUS:
2819 case LABEL_REF:
2820 case SYMBOL_REF:
2821 case CONST:
2822 if (reg_class_subset_p (ADDR_REGS, rclass))
2823 return ADDR_REGS;
2824 else
2825 return NO_REGS;
2826
2827 default:
2828 break;
2829 }
2830
2831 return rclass;
2832 }
2833
2834 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2835 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2836 aligned. */
2837
2838 bool
2839 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2840 {
2841 HOST_WIDE_INT addend;
2842 rtx symref;
2843
2844 if (!s390_symref_operand_p (addr, &symref, &addend))
2845 return false;
2846
2847 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2848 && !(addend & (alignment - 1)));
2849 }
2850
2851 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2852 operand SCRATCH is used to reload the even part of the address and
2853 adding one. */
2854
2855 void
2856 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2857 {
2858 HOST_WIDE_INT addend;
2859 rtx symref;
2860
2861 if (!s390_symref_operand_p (addr, &symref, &addend))
2862 gcc_unreachable ();
2863
2864 if (!(addend & 1))
2865 /* Easy case. The addend is even so larl will do fine. */
2866 emit_move_insn (reg, addr);
2867 else
2868 {
2869 /* We can leave the scratch register untouched if the target
2870 register is a valid base register. */
2871 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2872 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2873 scratch = reg;
2874
2875 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2876 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2877
2878 if (addend != 1)
2879 emit_move_insn (scratch,
2880 gen_rtx_CONST (Pmode,
2881 gen_rtx_PLUS (Pmode, symref,
2882 GEN_INT (addend - 1))));
2883 else
2884 emit_move_insn (scratch, symref);
2885
2886 /* Increment the address using la in order to avoid clobbering cc. */
2887 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2888 }
2889 }
2890
2891 /* Generate what is necessary to move between REG and MEM using
2892 SCRATCH. The direction is given by TOMEM. */
2893
2894 void
2895 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2896 {
2897 /* Reload might have pulled a constant out of the literal pool.
2898 Force it back in. */
2899 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2900 || GET_CODE (mem) == CONST)
2901 mem = force_const_mem (GET_MODE (reg), mem);
2902
2903 gcc_assert (MEM_P (mem));
2904
2905 /* For a load from memory we can leave the scratch register
2906 untouched if the target register is a valid base register. */
2907 if (!tomem
2908 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2909 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2910 && GET_MODE (reg) == GET_MODE (scratch))
2911 scratch = reg;
2912
2913 /* Load address into scratch register. Since we can't have a
2914 secondary reload for a secondary reload we have to cover the case
2915 where larl would need a secondary reload here as well. */
2916 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2917
2918 /* Now we can use a standard load/store to do the move. */
2919 if (tomem)
2920 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2921 else
2922 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2923 }
2924
2925 /* Inform reload about cases where moving X with a mode MODE to a register in
2926 RCLASS requires an extra scratch or immediate register. Return the class
2927 needed for the immediate register. */
2928
2929 static enum reg_class
2930 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2931 enum machine_mode mode, secondary_reload_info *sri)
2932 {
2933 /* Intermediate register needed. */
2934 if (reg_classes_intersect_p (CC_REGS, rclass))
2935 return GENERAL_REGS;
2936
2937 if (TARGET_Z10)
2938 {
2939 /* On z10 several optimizer steps may generate larl operands with
2940 an odd addend. */
2941 if (in_p
2942 && s390_symref_operand_p (x, NULL, NULL)
2943 && mode == Pmode
2944 && !s390_check_symref_alignment (x, 2))
2945 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2946 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2947
2948 /* On z10 we need a scratch register when moving QI, TI or floating
2949 point mode values from or to a memory location with a SYMBOL_REF
2950 or if the symref addend of a SI or DI move is not aligned to the
2951 width of the access. */
2952 if (MEM_P (x)
2953 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2954 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2955 || (!TARGET_64BIT && mode == DImode)
2956 || ((mode == HImode || mode == SImode || mode == DImode)
2957 && (!s390_check_symref_alignment (XEXP (x, 0),
2958 GET_MODE_SIZE (mode))))))
2959 {
2960 #define __SECONDARY_RELOAD_CASE(M,m) \
2961 case M##mode: \
2962 if (TARGET_64BIT) \
2963 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2964 CODE_FOR_reload##m##di_tomem_z10; \
2965 else \
2966 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2967 CODE_FOR_reload##m##si_tomem_z10; \
2968 break;
2969
2970 switch (GET_MODE (x))
2971 {
2972 __SECONDARY_RELOAD_CASE (QI, qi);
2973 __SECONDARY_RELOAD_CASE (HI, hi);
2974 __SECONDARY_RELOAD_CASE (SI, si);
2975 __SECONDARY_RELOAD_CASE (DI, di);
2976 __SECONDARY_RELOAD_CASE (TI, ti);
2977 __SECONDARY_RELOAD_CASE (SF, sf);
2978 __SECONDARY_RELOAD_CASE (DF, df);
2979 __SECONDARY_RELOAD_CASE (TF, tf);
2980 __SECONDARY_RELOAD_CASE (SD, sd);
2981 __SECONDARY_RELOAD_CASE (DD, dd);
2982 __SECONDARY_RELOAD_CASE (TD, td);
2983
2984 default:
2985 gcc_unreachable ();
2986 }
2987 #undef __SECONDARY_RELOAD_CASE
2988 }
2989 }
2990
2991 /* We need a scratch register when loading a PLUS expression which
2992 is not a legitimate operand of the LOAD ADDRESS instruction. */
2993 if (in_p && s390_plus_operand (x, mode))
2994 sri->icode = (TARGET_64BIT ?
2995 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
2996
2997 /* Performing a multiword move from or to memory we have to make sure the
2998 second chunk in memory is addressable without causing a displacement
2999 overflow. If that would be the case we calculate the address in
3000 a scratch register. */
3001 if (MEM_P (x)
3002 && GET_CODE (XEXP (x, 0)) == PLUS
3003 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3004 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3005 + GET_MODE_SIZE (mode) - 1))
3006 {
3007 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3008 in a s_operand address since we may fallback to lm/stm. So we only
3009 have to care about overflows in the b+i+d case. */
3010 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3011 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3012 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3013 /* For FP_REGS no lm/stm is available so this check is triggered
3014 for displacement overflows in b+i+d and b+d like addresses. */
3015 || (reg_classes_intersect_p (FP_REGS, rclass)
3016 && s390_class_max_nregs (FP_REGS, mode) > 1))
3017 {
3018 if (in_p)
3019 sri->icode = (TARGET_64BIT ?
3020 CODE_FOR_reloaddi_nonoffmem_in :
3021 CODE_FOR_reloadsi_nonoffmem_in);
3022 else
3023 sri->icode = (TARGET_64BIT ?
3024 CODE_FOR_reloaddi_nonoffmem_out :
3025 CODE_FOR_reloadsi_nonoffmem_out);
3026 }
3027 }
3028
3029 /* A scratch address register is needed when a symbolic constant is
3030 copied to r0 compiling with -fPIC. In other cases the target
3031 register might be used as temporary (see legitimize_pic_address). */
3032 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3033 sri->icode = (TARGET_64BIT ?
3034 CODE_FOR_reloaddi_PIC_addr :
3035 CODE_FOR_reloadsi_PIC_addr);
3036
3037 /* Either scratch or no register needed. */
3038 return NO_REGS;
3039 }
3040
3041 /* Generate code to load SRC, which is PLUS that is not a
3042 legitimate operand for the LA instruction, into TARGET.
3043 SCRATCH may be used as scratch register. */
3044
3045 void
3046 s390_expand_plus_operand (rtx target, rtx src,
3047 rtx scratch)
3048 {
3049 rtx sum1, sum2;
3050 struct s390_address ad;
3051
3052 /* src must be a PLUS; get its two operands. */
3053 gcc_assert (GET_CODE (src) == PLUS);
3054 gcc_assert (GET_MODE (src) == Pmode);
3055
3056 /* Check if any of the two operands is already scheduled
3057 for replacement by reload. This can happen e.g. when
3058 float registers occur in an address. */
3059 sum1 = find_replacement (&XEXP (src, 0));
3060 sum2 = find_replacement (&XEXP (src, 1));
3061 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3062
3063 /* If the address is already strictly valid, there's nothing to do. */
3064 if (!s390_decompose_address (src, &ad)
3065 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3066 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3067 {
3068 /* Otherwise, one of the operands cannot be an address register;
3069 we reload its value into the scratch register. */
3070 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3071 {
3072 emit_move_insn (scratch, sum1);
3073 sum1 = scratch;
3074 }
3075 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3076 {
3077 emit_move_insn (scratch, sum2);
3078 sum2 = scratch;
3079 }
3080
3081 /* According to the way these invalid addresses are generated
3082 in reload.c, it should never happen (at least on s390) that
3083 *neither* of the PLUS components, after find_replacements
3084 was applied, is an address register. */
3085 if (sum1 == scratch && sum2 == scratch)
3086 {
3087 debug_rtx (src);
3088 gcc_unreachable ();
3089 }
3090
3091 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3092 }
3093
3094 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3095 is only ever performed on addresses, so we can mark the
3096 sum as legitimate for LA in any case. */
3097 s390_load_address (target, src);
3098 }
3099
3100
3101 /* Return true if ADDR is a valid memory address.
3102 STRICT specifies whether strict register checking applies. */
3103
3104 static bool
3105 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3106 {
3107 struct s390_address ad;
3108
3109 if (TARGET_Z10
3110 && larl_operand (addr, VOIDmode)
3111 && (mode == VOIDmode
3112 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3113 return true;
3114
3115 if (!s390_decompose_address (addr, &ad))
3116 return false;
3117
3118 if (strict)
3119 {
3120 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3121 return false;
3122
3123 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3124 return false;
3125 }
3126 else
3127 {
3128 if (ad.base
3129 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3130 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3131 return false;
3132
3133 if (ad.indx
3134 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3135 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3136 return false;
3137 }
3138 return true;
3139 }
3140
3141 /* Return true if OP is a valid operand for the LA instruction.
3142 In 31-bit, we need to prove that the result is used as an
3143 address, as LA performs only a 31-bit addition. */
3144
3145 bool
3146 legitimate_la_operand_p (rtx op)
3147 {
3148 struct s390_address addr;
3149 if (!s390_decompose_address (op, &addr))
3150 return false;
3151
3152 return (TARGET_64BIT || addr.pointer);
3153 }
3154
3155 /* Return true if it is valid *and* preferable to use LA to
3156 compute the sum of OP1 and OP2. */
3157
3158 bool
3159 preferred_la_operand_p (rtx op1, rtx op2)
3160 {
3161 struct s390_address addr;
3162
3163 if (op2 != const0_rtx)
3164 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3165
3166 if (!s390_decompose_address (op1, &addr))
3167 return false;
3168 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3169 return false;
3170 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3171 return false;
3172
3173 if (!TARGET_64BIT && !addr.pointer)
3174 return false;
3175
3176 if (addr.pointer)
3177 return true;
3178
3179 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3180 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3181 return true;
3182
3183 return false;
3184 }
3185
3186 /* Emit a forced load-address operation to load SRC into DST.
3187 This will use the LOAD ADDRESS instruction even in situations
3188 where legitimate_la_operand_p (SRC) returns false. */
3189
3190 void
3191 s390_load_address (rtx dst, rtx src)
3192 {
3193 if (TARGET_64BIT)
3194 emit_move_insn (dst, src);
3195 else
3196 emit_insn (gen_force_la_31 (dst, src));
3197 }
3198
3199 /* Return a legitimate reference for ORIG (an address) using the
3200 register REG. If REG is 0, a new pseudo is generated.
3201
3202 There are two types of references that must be handled:
3203
3204 1. Global data references must load the address from the GOT, via
3205 the PIC reg. An insn is emitted to do this load, and the reg is
3206 returned.
3207
3208 2. Static data references, constant pool addresses, and code labels
3209 compute the address as an offset from the GOT, whose base is in
3210 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3211 differentiate them from global data objects. The returned
3212 address is the PIC reg + an unspec constant.
3213
3214 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3215 reg also appears in the address. */
3216
3217 rtx
3218 legitimize_pic_address (rtx orig, rtx reg)
3219 {
3220 rtx addr = orig;
3221 rtx new_rtx = orig;
3222 rtx base;
3223
3224 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3225
3226 if (GET_CODE (addr) == LABEL_REF
3227 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3228 {
3229 /* This is a local symbol. */
3230 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3231 {
3232 /* Access local symbols PC-relative via LARL.
3233 This is the same as in the non-PIC case, so it is
3234 handled automatically ... */
3235 }
3236 else
3237 {
3238 /* Access local symbols relative to the GOT. */
3239
3240 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3241
3242 if (reload_in_progress || reload_completed)
3243 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3244
3245 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3246 addr = gen_rtx_CONST (Pmode, addr);
3247 addr = force_const_mem (Pmode, addr);
3248 emit_move_insn (temp, addr);
3249
3250 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3251 if (reg != 0)
3252 {
3253 s390_load_address (reg, new_rtx);
3254 new_rtx = reg;
3255 }
3256 }
3257 }
3258 else if (GET_CODE (addr) == SYMBOL_REF)
3259 {
3260 if (reg == 0)
3261 reg = gen_reg_rtx (Pmode);
3262
3263 if (flag_pic == 1)
3264 {
3265 /* Assume GOT offset < 4k. This is handled the same way
3266 in both 31- and 64-bit code (@GOT). */
3267
3268 if (reload_in_progress || reload_completed)
3269 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3270
3271 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3272 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3273 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3274 new_rtx = gen_const_mem (Pmode, new_rtx);
3275 emit_move_insn (reg, new_rtx);
3276 new_rtx = reg;
3277 }
3278 else if (TARGET_CPU_ZARCH)
3279 {
3280 /* If the GOT offset might be >= 4k, we determine the position
3281 of the GOT entry via a PC-relative LARL (@GOTENT). */
3282
3283 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3284
3285 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3286 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3287
3288 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3289 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3290 emit_move_insn (temp, new_rtx);
3291
3292 new_rtx = gen_const_mem (Pmode, temp);
3293 emit_move_insn (reg, new_rtx);
3294 new_rtx = reg;
3295 }
3296 else
3297 {
3298 /* If the GOT offset might be >= 4k, we have to load it
3299 from the literal pool (@GOT). */
3300
3301 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3302
3303 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3304 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3305
3306 if (reload_in_progress || reload_completed)
3307 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3308
3309 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3310 addr = gen_rtx_CONST (Pmode, addr);
3311 addr = force_const_mem (Pmode, addr);
3312 emit_move_insn (temp, addr);
3313
3314 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3315 new_rtx = gen_const_mem (Pmode, new_rtx);
3316 emit_move_insn (reg, new_rtx);
3317 new_rtx = reg;
3318 }
3319 }
3320 else
3321 {
3322 if (GET_CODE (addr) == CONST)
3323 {
3324 addr = XEXP (addr, 0);
3325 if (GET_CODE (addr) == UNSPEC)
3326 {
3327 gcc_assert (XVECLEN (addr, 0) == 1);
3328 switch (XINT (addr, 1))
3329 {
3330 /* If someone moved a GOT-relative UNSPEC
3331 out of the literal pool, force them back in. */
3332 case UNSPEC_GOTOFF:
3333 case UNSPEC_PLTOFF:
3334 new_rtx = force_const_mem (Pmode, orig);
3335 break;
3336
3337 /* @GOT is OK as is if small. */
3338 case UNSPEC_GOT:
3339 if (flag_pic == 2)
3340 new_rtx = force_const_mem (Pmode, orig);
3341 break;
3342
3343 /* @GOTENT is OK as is. */
3344 case UNSPEC_GOTENT:
3345 break;
3346
3347 /* @PLT is OK as is on 64-bit, must be converted to
3348 GOT-relative @PLTOFF on 31-bit. */
3349 case UNSPEC_PLT:
3350 if (!TARGET_CPU_ZARCH)
3351 {
3352 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3353
3354 if (reload_in_progress || reload_completed)
3355 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3356
3357 addr = XVECEXP (addr, 0, 0);
3358 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3359 UNSPEC_PLTOFF);
3360 addr = gen_rtx_CONST (Pmode, addr);
3361 addr = force_const_mem (Pmode, addr);
3362 emit_move_insn (temp, addr);
3363
3364 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3365 if (reg != 0)
3366 {
3367 s390_load_address (reg, new_rtx);
3368 new_rtx = reg;
3369 }
3370 }
3371 break;
3372
3373 /* Everything else cannot happen. */
3374 default:
3375 gcc_unreachable ();
3376 }
3377 }
3378 else
3379 gcc_assert (GET_CODE (addr) == PLUS);
3380 }
3381 if (GET_CODE (addr) == PLUS)
3382 {
3383 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3384
3385 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3386 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3387
3388 /* Check first to see if this is a constant offset
3389 from a local symbol reference. */
3390 if ((GET_CODE (op0) == LABEL_REF
3391 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3392 && GET_CODE (op1) == CONST_INT)
3393 {
3394 if (TARGET_CPU_ZARCH
3395 && larl_operand (op0, VOIDmode)
3396 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3397 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3398 {
3399 if (INTVAL (op1) & 1)
3400 {
3401 /* LARL can't handle odd offsets, so emit a
3402 pair of LARL and LA. */
3403 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3404
3405 if (!DISP_IN_RANGE (INTVAL (op1)))
3406 {
3407 HOST_WIDE_INT even = INTVAL (op1) - 1;
3408 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3409 op0 = gen_rtx_CONST (Pmode, op0);
3410 op1 = const1_rtx;
3411 }
3412
3413 emit_move_insn (temp, op0);
3414 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3415
3416 if (reg != 0)
3417 {
3418 s390_load_address (reg, new_rtx);
3419 new_rtx = reg;
3420 }
3421 }
3422 else
3423 {
3424 /* If the offset is even, we can just use LARL.
3425 This will happen automatically. */
3426 }
3427 }
3428 else
3429 {
3430 /* Access local symbols relative to the GOT. */
3431
3432 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3433
3434 if (reload_in_progress || reload_completed)
3435 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3436
3437 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3438 UNSPEC_GOTOFF);
3439 addr = gen_rtx_PLUS (Pmode, addr, op1);
3440 addr = gen_rtx_CONST (Pmode, addr);
3441 addr = force_const_mem (Pmode, addr);
3442 emit_move_insn (temp, addr);
3443
3444 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3445 if (reg != 0)
3446 {
3447 s390_load_address (reg, new_rtx);
3448 new_rtx = reg;
3449 }
3450 }
3451 }
3452
3453 /* Now, check whether it is a GOT relative symbol plus offset
3454 that was pulled out of the literal pool. Force it back in. */
3455
3456 else if (GET_CODE (op0) == UNSPEC
3457 && GET_CODE (op1) == CONST_INT
3458 && XINT (op0, 1) == UNSPEC_GOTOFF)
3459 {
3460 gcc_assert (XVECLEN (op0, 0) == 1);
3461
3462 new_rtx = force_const_mem (Pmode, orig);
3463 }
3464
3465 /* Otherwise, compute the sum. */
3466 else
3467 {
3468 base = legitimize_pic_address (XEXP (addr, 0), reg);
3469 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3470 base == reg ? NULL_RTX : reg);
3471 if (GET_CODE (new_rtx) == CONST_INT)
3472 new_rtx = plus_constant (base, INTVAL (new_rtx));
3473 else
3474 {
3475 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3476 {
3477 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3478 new_rtx = XEXP (new_rtx, 1);
3479 }
3480 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3481 }
3482
3483 if (GET_CODE (new_rtx) == CONST)
3484 new_rtx = XEXP (new_rtx, 0);
3485 new_rtx = force_operand (new_rtx, 0);
3486 }
3487 }
3488 }
3489 return new_rtx;
3490 }
3491
3492 /* Load the thread pointer into a register. */
3493
3494 rtx
3495 s390_get_thread_pointer (void)
3496 {
3497 rtx tp = gen_reg_rtx (Pmode);
3498
3499 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3500 mark_reg_pointer (tp, BITS_PER_WORD);
3501
3502 return tp;
3503 }
3504
3505 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3506 in s390_tls_symbol which always refers to __tls_get_offset.
3507 The returned offset is written to RESULT_REG and an USE rtx is
3508 generated for TLS_CALL. */
3509
3510 static GTY(()) rtx s390_tls_symbol;
3511
3512 static void
3513 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3514 {
3515 rtx insn;
3516
3517 gcc_assert (flag_pic);
3518
3519 if (!s390_tls_symbol)
3520 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3521
3522 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3523 gen_rtx_REG (Pmode, RETURN_REGNUM));
3524
3525 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3526 RTL_CONST_CALL_P (insn) = 1;
3527 }
3528
3529 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3530 this (thread-local) address. REG may be used as temporary. */
3531
3532 static rtx
3533 legitimize_tls_address (rtx addr, rtx reg)
3534 {
3535 rtx new_rtx, tls_call, temp, base, r2, insn;
3536
3537 if (GET_CODE (addr) == SYMBOL_REF)
3538 switch (tls_symbolic_operand (addr))
3539 {
3540 case TLS_MODEL_GLOBAL_DYNAMIC:
3541 start_sequence ();
3542 r2 = gen_rtx_REG (Pmode, 2);
3543 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3544 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3545 new_rtx = force_const_mem (Pmode, new_rtx);
3546 emit_move_insn (r2, new_rtx);
3547 s390_emit_tls_call_insn (r2, tls_call);
3548 insn = get_insns ();
3549 end_sequence ();
3550
3551 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3552 temp = gen_reg_rtx (Pmode);
3553 emit_libcall_block (insn, temp, r2, new_rtx);
3554
3555 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3556 if (reg != 0)
3557 {
3558 s390_load_address (reg, new_rtx);
3559 new_rtx = reg;
3560 }
3561 break;
3562
3563 case TLS_MODEL_LOCAL_DYNAMIC:
3564 start_sequence ();
3565 r2 = gen_rtx_REG (Pmode, 2);
3566 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3567 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3568 new_rtx = force_const_mem (Pmode, new_rtx);
3569 emit_move_insn (r2, new_rtx);
3570 s390_emit_tls_call_insn (r2, tls_call);
3571 insn = get_insns ();
3572 end_sequence ();
3573
3574 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3575 temp = gen_reg_rtx (Pmode);
3576 emit_libcall_block (insn, temp, r2, new_rtx);
3577
3578 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3579 base = gen_reg_rtx (Pmode);
3580 s390_load_address (base, new_rtx);
3581
3582 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3583 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3584 new_rtx = force_const_mem (Pmode, new_rtx);
3585 temp = gen_reg_rtx (Pmode);
3586 emit_move_insn (temp, new_rtx);
3587
3588 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3589 if (reg != 0)
3590 {
3591 s390_load_address (reg, new_rtx);
3592 new_rtx = reg;
3593 }
3594 break;
3595
3596 case TLS_MODEL_INITIAL_EXEC:
3597 if (flag_pic == 1)
3598 {
3599 /* Assume GOT offset < 4k. This is handled the same way
3600 in both 31- and 64-bit code. */
3601
3602 if (reload_in_progress || reload_completed)
3603 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3604
3605 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3606 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3607 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3608 new_rtx = gen_const_mem (Pmode, new_rtx);
3609 temp = gen_reg_rtx (Pmode);
3610 emit_move_insn (temp, new_rtx);
3611 }
3612 else if (TARGET_CPU_ZARCH)
3613 {
3614 /* If the GOT offset might be >= 4k, we determine the position
3615 of the GOT entry via a PC-relative LARL. */
3616
3617 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3618 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3619 temp = gen_reg_rtx (Pmode);
3620 emit_move_insn (temp, new_rtx);
3621
3622 new_rtx = gen_const_mem (Pmode, temp);
3623 temp = gen_reg_rtx (Pmode);
3624 emit_move_insn (temp, new_rtx);
3625 }
3626 else if (flag_pic)
3627 {
3628 /* If the GOT offset might be >= 4k, we have to load it
3629 from the literal pool. */
3630
3631 if (reload_in_progress || reload_completed)
3632 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3633
3634 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3635 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3636 new_rtx = force_const_mem (Pmode, new_rtx);
3637 temp = gen_reg_rtx (Pmode);
3638 emit_move_insn (temp, new_rtx);
3639
3640 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3641 new_rtx = gen_const_mem (Pmode, new_rtx);
3642
3643 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3644 temp = gen_reg_rtx (Pmode);
3645 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3646 }
3647 else
3648 {
3649 /* In position-dependent code, load the absolute address of
3650 the GOT entry from the literal pool. */
3651
3652 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3653 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3654 new_rtx = force_const_mem (Pmode, new_rtx);
3655 temp = gen_reg_rtx (Pmode);
3656 emit_move_insn (temp, new_rtx);
3657
3658 new_rtx = temp;
3659 new_rtx = gen_const_mem (Pmode, new_rtx);
3660 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3661 temp = gen_reg_rtx (Pmode);
3662 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3663 }
3664
3665 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3666 if (reg != 0)
3667 {
3668 s390_load_address (reg, new_rtx);
3669 new_rtx = reg;
3670 }
3671 break;
3672
3673 case TLS_MODEL_LOCAL_EXEC:
3674 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3675 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3676 new_rtx = force_const_mem (Pmode, new_rtx);
3677 temp = gen_reg_rtx (Pmode);
3678 emit_move_insn (temp, new_rtx);
3679
3680 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3681 if (reg != 0)
3682 {
3683 s390_load_address (reg, new_rtx);
3684 new_rtx = reg;
3685 }
3686 break;
3687
3688 default:
3689 gcc_unreachable ();
3690 }
3691
3692 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3693 {
3694 switch (XINT (XEXP (addr, 0), 1))
3695 {
3696 case UNSPEC_INDNTPOFF:
3697 gcc_assert (TARGET_CPU_ZARCH);
3698 new_rtx = addr;
3699 break;
3700
3701 default:
3702 gcc_unreachable ();
3703 }
3704 }
3705
3706 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3707 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3708 {
3709 new_rtx = XEXP (XEXP (addr, 0), 0);
3710 if (GET_CODE (new_rtx) != SYMBOL_REF)
3711 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3712
3713 new_rtx = legitimize_tls_address (new_rtx, reg);
3714 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3715 new_rtx = force_operand (new_rtx, 0);
3716 }
3717
3718 else
3719 gcc_unreachable (); /* for now ... */
3720
3721 return new_rtx;
3722 }
3723
3724 /* Emit insns making the address in operands[1] valid for a standard
3725 move to operands[0]. operands[1] is replaced by an address which
3726 should be used instead of the former RTX to emit the move
3727 pattern. */
3728
3729 void
3730 emit_symbolic_move (rtx *operands)
3731 {
3732 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3733
3734 if (GET_CODE (operands[0]) == MEM)
3735 operands[1] = force_reg (Pmode, operands[1]);
3736 else if (TLS_SYMBOLIC_CONST (operands[1]))
3737 operands[1] = legitimize_tls_address (operands[1], temp);
3738 else if (flag_pic)
3739 operands[1] = legitimize_pic_address (operands[1], temp);
3740 }
3741
3742 /* Try machine-dependent ways of modifying an illegitimate address X
3743 to be legitimate. If we find one, return the new, valid address.
3744
3745 OLDX is the address as it was before break_out_memory_refs was called.
3746 In some cases it is useful to look at this to decide what needs to be done.
3747
3748 MODE is the mode of the operand pointed to by X.
3749
3750 When -fpic is used, special handling is needed for symbolic references.
3751 See comments by legitimize_pic_address for details. */
3752
3753 static rtx
3754 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3755 enum machine_mode mode ATTRIBUTE_UNUSED)
3756 {
3757 rtx constant_term = const0_rtx;
3758
3759 if (TLS_SYMBOLIC_CONST (x))
3760 {
3761 x = legitimize_tls_address (x, 0);
3762
3763 if (s390_legitimate_address_p (mode, x, FALSE))
3764 return x;
3765 }
3766 else if (GET_CODE (x) == PLUS
3767 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3768 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3769 {
3770 return x;
3771 }
3772 else if (flag_pic)
3773 {
3774 if (SYMBOLIC_CONST (x)
3775 || (GET_CODE (x) == PLUS
3776 && (SYMBOLIC_CONST (XEXP (x, 0))
3777 || SYMBOLIC_CONST (XEXP (x, 1)))))
3778 x = legitimize_pic_address (x, 0);
3779
3780 if (s390_legitimate_address_p (mode, x, FALSE))
3781 return x;
3782 }
3783
3784 x = eliminate_constant_term (x, &constant_term);
3785
3786 /* Optimize loading of large displacements by splitting them
3787 into the multiple of 4K and the rest; this allows the
3788 former to be CSE'd if possible.
3789
3790 Don't do this if the displacement is added to a register
3791 pointing into the stack frame, as the offsets will
3792 change later anyway. */
3793
3794 if (GET_CODE (constant_term) == CONST_INT
3795 && !TARGET_LONG_DISPLACEMENT
3796 && !DISP_IN_RANGE (INTVAL (constant_term))
3797 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3798 {
3799 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3800 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3801
3802 rtx temp = gen_reg_rtx (Pmode);
3803 rtx val = force_operand (GEN_INT (upper), temp);
3804 if (val != temp)
3805 emit_move_insn (temp, val);
3806
3807 x = gen_rtx_PLUS (Pmode, x, temp);
3808 constant_term = GEN_INT (lower);
3809 }
3810
3811 if (GET_CODE (x) == PLUS)
3812 {
3813 if (GET_CODE (XEXP (x, 0)) == REG)
3814 {
3815 rtx temp = gen_reg_rtx (Pmode);
3816 rtx val = force_operand (XEXP (x, 1), temp);
3817 if (val != temp)
3818 emit_move_insn (temp, val);
3819
3820 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3821 }
3822
3823 else if (GET_CODE (XEXP (x, 1)) == REG)
3824 {
3825 rtx temp = gen_reg_rtx (Pmode);
3826 rtx val = force_operand (XEXP (x, 0), temp);
3827 if (val != temp)
3828 emit_move_insn (temp, val);
3829
3830 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3831 }
3832 }
3833
3834 if (constant_term != const0_rtx)
3835 x = gen_rtx_PLUS (Pmode, x, constant_term);
3836
3837 return x;
3838 }
3839
3840 /* Try a machine-dependent way of reloading an illegitimate address AD
3841 operand. If we find one, push the reload and and return the new address.
3842
3843 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3844 and TYPE is the reload type of the current reload. */
3845
3846 rtx
3847 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3848 int opnum, int type)
3849 {
3850 if (!optimize || TARGET_LONG_DISPLACEMENT)
3851 return NULL_RTX;
3852
3853 if (GET_CODE (ad) == PLUS)
3854 {
3855 rtx tem = simplify_binary_operation (PLUS, Pmode,
3856 XEXP (ad, 0), XEXP (ad, 1));
3857 if (tem)
3858 ad = tem;
3859 }
3860
3861 if (GET_CODE (ad) == PLUS
3862 && GET_CODE (XEXP (ad, 0)) == REG
3863 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3864 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3865 {
3866 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3867 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3868 rtx cst, tem, new_rtx;
3869
3870 cst = GEN_INT (upper);
3871 if (!legitimate_reload_constant_p (cst))
3872 cst = force_const_mem (Pmode, cst);
3873
3874 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3875 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3876
3877 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3878 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3879 opnum, (enum reload_type) type);
3880 return new_rtx;
3881 }
3882
3883 return NULL_RTX;
3884 }
3885
3886 /* Emit code to move LEN bytes from DST to SRC. */
3887
3888 void
3889 s390_expand_movmem (rtx dst, rtx src, rtx len)
3890 {
3891 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3892 {
3893 if (INTVAL (len) > 0)
3894 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3895 }
3896
3897 else if (TARGET_MVCLE)
3898 {
3899 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3900 }
3901
3902 else
3903 {
3904 rtx dst_addr, src_addr, count, blocks, temp;
3905 rtx loop_start_label = gen_label_rtx ();
3906 rtx loop_end_label = gen_label_rtx ();
3907 rtx end_label = gen_label_rtx ();
3908 enum machine_mode mode;
3909
3910 mode = GET_MODE (len);
3911 if (mode == VOIDmode)
3912 mode = Pmode;
3913
3914 dst_addr = gen_reg_rtx (Pmode);
3915 src_addr = gen_reg_rtx (Pmode);
3916 count = gen_reg_rtx (mode);
3917 blocks = gen_reg_rtx (mode);
3918
3919 convert_move (count, len, 1);
3920 emit_cmp_and_jump_insns (count, const0_rtx,
3921 EQ, NULL_RTX, mode, 1, end_label);
3922
3923 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3924 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3925 dst = change_address (dst, VOIDmode, dst_addr);
3926 src = change_address (src, VOIDmode, src_addr);
3927
3928 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3929 OPTAB_DIRECT);
3930 if (temp != count)
3931 emit_move_insn (count, temp);
3932
3933 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3934 OPTAB_DIRECT);
3935 if (temp != blocks)
3936 emit_move_insn (blocks, temp);
3937
3938 emit_cmp_and_jump_insns (blocks, const0_rtx,
3939 EQ, NULL_RTX, mode, 1, loop_end_label);
3940
3941 emit_label (loop_start_label);
3942
3943 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3944 s390_load_address (dst_addr,
3945 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3946 s390_load_address (src_addr,
3947 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3948
3949 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
3950 OPTAB_DIRECT);
3951 if (temp != blocks)
3952 emit_move_insn (blocks, temp);
3953
3954 emit_cmp_and_jump_insns (blocks, const0_rtx,
3955 EQ, NULL_RTX, mode, 1, loop_end_label);
3956
3957 emit_jump (loop_start_label);
3958 emit_label (loop_end_label);
3959
3960 emit_insn (gen_movmem_short (dst, src,
3961 convert_to_mode (Pmode, count, 1)));
3962 emit_label (end_label);
3963 }
3964 }
3965
3966 /* Emit code to set LEN bytes at DST to VAL.
3967 Make use of clrmem if VAL is zero. */
3968
3969 void
3970 s390_expand_setmem (rtx dst, rtx len, rtx val)
3971 {
3972 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
3973 return;
3974
3975 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3976
3977 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
3978 {
3979 if (val == const0_rtx && INTVAL (len) <= 256)
3980 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3981 else
3982 {
3983 /* Initialize memory by storing the first byte. */
3984 emit_move_insn (adjust_address (dst, QImode, 0), val);
3985
3986 if (INTVAL (len) > 1)
3987 {
3988 /* Initiate 1 byte overlap move.
3989 The first byte of DST is propagated through DSTP1.
3990 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3991 DST is set to size 1 so the rest of the memory location
3992 does not count as source operand. */
3993 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3994 set_mem_size (dst, const1_rtx);
3995
3996 emit_insn (gen_movmem_short (dstp1, dst,
3997 GEN_INT (INTVAL (len) - 2)));
3998 }
3999 }
4000 }
4001
4002 else if (TARGET_MVCLE)
4003 {
4004 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4005 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4006 }
4007
4008 else
4009 {
4010 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
4011 rtx loop_start_label = gen_label_rtx ();
4012 rtx loop_end_label = gen_label_rtx ();
4013 rtx end_label = gen_label_rtx ();
4014 enum machine_mode mode;
4015
4016 mode = GET_MODE (len);
4017 if (mode == VOIDmode)
4018 mode = Pmode;
4019
4020 dst_addr = gen_reg_rtx (Pmode);
4021 src_addr = gen_reg_rtx (Pmode);
4022 count = gen_reg_rtx (mode);
4023 blocks = gen_reg_rtx (mode);
4024
4025 convert_move (count, len, 1);
4026 emit_cmp_and_jump_insns (count, const0_rtx,
4027 EQ, NULL_RTX, mode, 1, end_label);
4028
4029 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4030 dst = change_address (dst, VOIDmode, dst_addr);
4031
4032 if (val == const0_rtx)
4033 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4034 OPTAB_DIRECT);
4035 else
4036 {
4037 dstp1 = adjust_address (dst, VOIDmode, 1);
4038 set_mem_size (dst, const1_rtx);
4039
4040 /* Initialize memory by storing the first byte. */
4041 emit_move_insn (adjust_address (dst, QImode, 0), val);
4042
4043 /* If count is 1 we are done. */
4044 emit_cmp_and_jump_insns (count, const1_rtx,
4045 EQ, NULL_RTX, mode, 1, end_label);
4046
4047 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4048 OPTAB_DIRECT);
4049 }
4050 if (temp != count)
4051 emit_move_insn (count, temp);
4052
4053 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4054 OPTAB_DIRECT);
4055 if (temp != blocks)
4056 emit_move_insn (blocks, temp);
4057
4058 emit_cmp_and_jump_insns (blocks, const0_rtx,
4059 EQ, NULL_RTX, mode, 1, loop_end_label);
4060
4061 emit_label (loop_start_label);
4062
4063 if (val == const0_rtx)
4064 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4065 else
4066 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4067 s390_load_address (dst_addr,
4068 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4069
4070 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4071 OPTAB_DIRECT);
4072 if (temp != blocks)
4073 emit_move_insn (blocks, temp);
4074
4075 emit_cmp_and_jump_insns (blocks, const0_rtx,
4076 EQ, NULL_RTX, mode, 1, loop_end_label);
4077
4078 emit_jump (loop_start_label);
4079 emit_label (loop_end_label);
4080
4081 if (val == const0_rtx)
4082 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4083 else
4084 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4085 emit_label (end_label);
4086 }
4087 }
4088
4089 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4090 and return the result in TARGET. */
4091
4092 void
4093 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4094 {
4095 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4096 rtx tmp;
4097
4098 /* As the result of CMPINT is inverted compared to what we need,
4099 we have to swap the operands. */
4100 tmp = op0; op0 = op1; op1 = tmp;
4101
4102 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4103 {
4104 if (INTVAL (len) > 0)
4105 {
4106 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4107 emit_insn (gen_cmpint (target, ccreg));
4108 }
4109 else
4110 emit_move_insn (target, const0_rtx);
4111 }
4112 else if (TARGET_MVCLE)
4113 {
4114 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4115 emit_insn (gen_cmpint (target, ccreg));
4116 }
4117 else
4118 {
4119 rtx addr0, addr1, count, blocks, temp;
4120 rtx loop_start_label = gen_label_rtx ();
4121 rtx loop_end_label = gen_label_rtx ();
4122 rtx end_label = gen_label_rtx ();
4123 enum machine_mode mode;
4124
4125 mode = GET_MODE (len);
4126 if (mode == VOIDmode)
4127 mode = Pmode;
4128
4129 addr0 = gen_reg_rtx (Pmode);
4130 addr1 = gen_reg_rtx (Pmode);
4131 count = gen_reg_rtx (mode);
4132 blocks = gen_reg_rtx (mode);
4133
4134 convert_move (count, len, 1);
4135 emit_cmp_and_jump_insns (count, const0_rtx,
4136 EQ, NULL_RTX, mode, 1, end_label);
4137
4138 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4139 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4140 op0 = change_address (op0, VOIDmode, addr0);
4141 op1 = change_address (op1, VOIDmode, addr1);
4142
4143 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4144 OPTAB_DIRECT);
4145 if (temp != count)
4146 emit_move_insn (count, temp);
4147
4148 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4149 OPTAB_DIRECT);
4150 if (temp != blocks)
4151 emit_move_insn (blocks, temp);
4152
4153 emit_cmp_and_jump_insns (blocks, const0_rtx,
4154 EQ, NULL_RTX, mode, 1, loop_end_label);
4155
4156 emit_label (loop_start_label);
4157
4158 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4159 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4160 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4161 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4162 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4163 emit_jump_insn (temp);
4164
4165 s390_load_address (addr0,
4166 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4167 s390_load_address (addr1,
4168 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4169
4170 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4171 OPTAB_DIRECT);
4172 if (temp != blocks)
4173 emit_move_insn (blocks, temp);
4174
4175 emit_cmp_and_jump_insns (blocks, const0_rtx,
4176 EQ, NULL_RTX, mode, 1, loop_end_label);
4177
4178 emit_jump (loop_start_label);
4179 emit_label (loop_end_label);
4180
4181 emit_insn (gen_cmpmem_short (op0, op1,
4182 convert_to_mode (Pmode, count, 1)));
4183 emit_label (end_label);
4184
4185 emit_insn (gen_cmpint (target, ccreg));
4186 }
4187 }
4188
4189
4190 /* Expand conditional increment or decrement using alc/slb instructions.
4191 Should generate code setting DST to either SRC or SRC + INCREMENT,
4192 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4193 Returns true if successful, false otherwise.
4194
4195 That makes it possible to implement some if-constructs without jumps e.g.:
4196 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4197 unsigned int a, b, c;
4198 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4199 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4200 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4201 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4202
4203 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4204 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4205 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4206 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4207 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4208
4209 bool
4210 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4211 rtx dst, rtx src, rtx increment)
4212 {
4213 enum machine_mode cmp_mode;
4214 enum machine_mode cc_mode;
4215 rtx op_res;
4216 rtx insn;
4217 rtvec p;
4218 int ret;
4219
4220 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4221 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4222 cmp_mode = SImode;
4223 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4224 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4225 cmp_mode = DImode;
4226 else
4227 return false;
4228
4229 /* Try ADD LOGICAL WITH CARRY. */
4230 if (increment == const1_rtx)
4231 {
4232 /* Determine CC mode to use. */
4233 if (cmp_code == EQ || cmp_code == NE)
4234 {
4235 if (cmp_op1 != const0_rtx)
4236 {
4237 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4238 NULL_RTX, 0, OPTAB_WIDEN);
4239 cmp_op1 = const0_rtx;
4240 }
4241
4242 cmp_code = cmp_code == EQ ? LEU : GTU;
4243 }
4244
4245 if (cmp_code == LTU || cmp_code == LEU)
4246 {
4247 rtx tem = cmp_op0;
4248 cmp_op0 = cmp_op1;
4249 cmp_op1 = tem;
4250 cmp_code = swap_condition (cmp_code);
4251 }
4252
4253 switch (cmp_code)
4254 {
4255 case GTU:
4256 cc_mode = CCUmode;
4257 break;
4258
4259 case GEU:
4260 cc_mode = CCL3mode;
4261 break;
4262
4263 default:
4264 return false;
4265 }
4266
4267 /* Emit comparison instruction pattern. */
4268 if (!register_operand (cmp_op0, cmp_mode))
4269 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4270
4271 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4272 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4273 /* We use insn_invalid_p here to add clobbers if required. */
4274 ret = insn_invalid_p (emit_insn (insn));
4275 gcc_assert (!ret);
4276
4277 /* Emit ALC instruction pattern. */
4278 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4279 gen_rtx_REG (cc_mode, CC_REGNUM),
4280 const0_rtx);
4281
4282 if (src != const0_rtx)
4283 {
4284 if (!register_operand (src, GET_MODE (dst)))
4285 src = force_reg (GET_MODE (dst), src);
4286
4287 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4288 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4289 }
4290
4291 p = rtvec_alloc (2);
4292 RTVEC_ELT (p, 0) =
4293 gen_rtx_SET (VOIDmode, dst, op_res);
4294 RTVEC_ELT (p, 1) =
4295 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4296 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4297
4298 return true;
4299 }
4300
4301 /* Try SUBTRACT LOGICAL WITH BORROW. */
4302 if (increment == constm1_rtx)
4303 {
4304 /* Determine CC mode to use. */
4305 if (cmp_code == EQ || cmp_code == NE)
4306 {
4307 if (cmp_op1 != const0_rtx)
4308 {
4309 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4310 NULL_RTX, 0, OPTAB_WIDEN);
4311 cmp_op1 = const0_rtx;
4312 }
4313
4314 cmp_code = cmp_code == EQ ? LEU : GTU;
4315 }
4316
4317 if (cmp_code == GTU || cmp_code == GEU)
4318 {
4319 rtx tem = cmp_op0;
4320 cmp_op0 = cmp_op1;
4321 cmp_op1 = tem;
4322 cmp_code = swap_condition (cmp_code);
4323 }
4324
4325 switch (cmp_code)
4326 {
4327 case LEU:
4328 cc_mode = CCUmode;
4329 break;
4330
4331 case LTU:
4332 cc_mode = CCL3mode;
4333 break;
4334
4335 default:
4336 return false;
4337 }
4338
4339 /* Emit comparison instruction pattern. */
4340 if (!register_operand (cmp_op0, cmp_mode))
4341 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4342
4343 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4344 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4345 /* We use insn_invalid_p here to add clobbers if required. */
4346 ret = insn_invalid_p (emit_insn (insn));
4347 gcc_assert (!ret);
4348
4349 /* Emit SLB instruction pattern. */
4350 if (!register_operand (src, GET_MODE (dst)))
4351 src = force_reg (GET_MODE (dst), src);
4352
4353 op_res = gen_rtx_MINUS (GET_MODE (dst),
4354 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4355 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4356 gen_rtx_REG (cc_mode, CC_REGNUM),
4357 const0_rtx));
4358 p = rtvec_alloc (2);
4359 RTVEC_ELT (p, 0) =
4360 gen_rtx_SET (VOIDmode, dst, op_res);
4361 RTVEC_ELT (p, 1) =
4362 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4363 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4364
4365 return true;
4366 }
4367
4368 return false;
4369 }
4370
4371 /* Expand code for the insv template. Return true if successful. */
4372
4373 bool
4374 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4375 {
4376 int bitsize = INTVAL (op1);
4377 int bitpos = INTVAL (op2);
4378
4379 /* On z10 we can use the risbg instruction to implement insv. */
4380 if (TARGET_Z10
4381 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4382 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4383 {
4384 rtx op;
4385 rtx clobber;
4386
4387 op = gen_rtx_SET (GET_MODE(src),
4388 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4389 src);
4390 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4391 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4392
4393 return true;
4394 }
4395
4396 /* We need byte alignment. */
4397 if (bitsize % BITS_PER_UNIT)
4398 return false;
4399
4400 if (bitpos == 0
4401 && memory_operand (dest, VOIDmode)
4402 && (register_operand (src, word_mode)
4403 || const_int_operand (src, VOIDmode)))
4404 {
4405 /* Emit standard pattern if possible. */
4406 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4407 if (GET_MODE_BITSIZE (mode) == bitsize)
4408 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4409
4410 /* (set (ze (mem)) (const_int)). */
4411 else if (const_int_operand (src, VOIDmode))
4412 {
4413 int size = bitsize / BITS_PER_UNIT;
4414 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4415 GET_MODE_SIZE (word_mode) - size);
4416
4417 dest = adjust_address (dest, BLKmode, 0);
4418 set_mem_size (dest, GEN_INT (size));
4419 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4420 }
4421
4422 /* (set (ze (mem)) (reg)). */
4423 else if (register_operand (src, word_mode))
4424 {
4425 if (bitsize <= GET_MODE_BITSIZE (SImode))
4426 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4427 const0_rtx), src);
4428 else
4429 {
4430 /* Emit st,stcmh sequence. */
4431 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4432 int size = stcmh_width / BITS_PER_UNIT;
4433
4434 emit_move_insn (adjust_address (dest, SImode, size),
4435 gen_lowpart (SImode, src));
4436 set_mem_size (dest, GEN_INT (size));
4437 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4438 (stcmh_width), const0_rtx),
4439 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4440 (GET_MODE_BITSIZE (SImode))));
4441 }
4442 }
4443 else
4444 return false;
4445
4446 return true;
4447 }
4448
4449 /* (set (ze (reg)) (const_int)). */
4450 if (TARGET_ZARCH
4451 && register_operand (dest, word_mode)
4452 && (bitpos % 16) == 0
4453 && (bitsize % 16) == 0
4454 && const_int_operand (src, VOIDmode))
4455 {
4456 HOST_WIDE_INT val = INTVAL (src);
4457 int regpos = bitpos + bitsize;
4458
4459 while (regpos > bitpos)
4460 {
4461 enum machine_mode putmode;
4462 int putsize;
4463
4464 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4465 putmode = SImode;
4466 else
4467 putmode = HImode;
4468
4469 putsize = GET_MODE_BITSIZE (putmode);
4470 regpos -= putsize;
4471 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4472 GEN_INT (putsize),
4473 GEN_INT (regpos)),
4474 gen_int_mode (val, putmode));
4475 val >>= putsize;
4476 }
4477 gcc_assert (regpos == bitpos);
4478 return true;
4479 }
4480
4481 return false;
4482 }
4483
4484 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4485 register that holds VAL of mode MODE shifted by COUNT bits. */
4486
4487 static inline rtx
4488 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4489 {
4490 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4491 NULL_RTX, 1, OPTAB_DIRECT);
4492 return expand_simple_binop (SImode, ASHIFT, val, count,
4493 NULL_RTX, 1, OPTAB_DIRECT);
4494 }
4495
4496 /* Structure to hold the initial parameters for a compare_and_swap operation
4497 in HImode and QImode. */
4498
4499 struct alignment_context
4500 {
4501 rtx memsi; /* SI aligned memory location. */
4502 rtx shift; /* Bit offset with regard to lsb. */
4503 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4504 rtx modemaski; /* ~modemask */
4505 bool aligned; /* True if memory is aligned, false else. */
4506 };
4507
4508 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4509 structure AC for transparent simplifying, if the memory alignment is known
4510 to be at least 32bit. MEM is the memory location for the actual operation
4511 and MODE its mode. */
4512
4513 static void
4514 init_alignment_context (struct alignment_context *ac, rtx mem,
4515 enum machine_mode mode)
4516 {
4517 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4518 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4519
4520 if (ac->aligned)
4521 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4522 else
4523 {
4524 /* Alignment is unknown. */
4525 rtx byteoffset, addr, align;
4526
4527 /* Force the address into a register. */
4528 addr = force_reg (Pmode, XEXP (mem, 0));
4529
4530 /* Align it to SImode. */
4531 align = expand_simple_binop (Pmode, AND, addr,
4532 GEN_INT (-GET_MODE_SIZE (SImode)),
4533 NULL_RTX, 1, OPTAB_DIRECT);
4534 /* Generate MEM. */
4535 ac->memsi = gen_rtx_MEM (SImode, align);
4536 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4537 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4538 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4539
4540 /* Calculate shiftcount. */
4541 byteoffset = expand_simple_binop (Pmode, AND, addr,
4542 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4543 NULL_RTX, 1, OPTAB_DIRECT);
4544 /* As we already have some offset, evaluate the remaining distance. */
4545 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4546 NULL_RTX, 1, OPTAB_DIRECT);
4547
4548 }
4549 /* Shift is the byte count, but we need the bitcount. */
4550 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4551 NULL_RTX, 1, OPTAB_DIRECT);
4552 /* Calculate masks. */
4553 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4554 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4555 NULL_RTX, 1, OPTAB_DIRECT);
4556 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4557 }
4558
4559 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4560 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4561 to set if CMP == MEM.
4562 CMP is never in memory for compare_and_swap_cc because
4563 expand_bool_compare_and_swap puts it into a register for later compare. */
4564
4565 void
4566 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4567 {
4568 struct alignment_context ac;
4569 rtx cmpv, newv, val, resv, cc;
4570 rtx res = gen_reg_rtx (SImode);
4571 rtx csloop = gen_label_rtx ();
4572 rtx csend = gen_label_rtx ();
4573
4574 gcc_assert (register_operand (target, VOIDmode));
4575 gcc_assert (MEM_P (mem));
4576
4577 init_alignment_context (&ac, mem, mode);
4578
4579 /* Shift the values to the correct bit positions. */
4580 if (!(ac.aligned && MEM_P (cmp)))
4581 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4582 if (!(ac.aligned && MEM_P (new_rtx)))
4583 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4584
4585 /* Load full word. Subsequent loads are performed by CS. */
4586 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4587 NULL_RTX, 1, OPTAB_DIRECT);
4588
4589 /* Start CS loop. */
4590 emit_label (csloop);
4591 /* val = "<mem>00..0<mem>"
4592 * cmp = "00..0<cmp>00..0"
4593 * new = "00..0<new>00..0"
4594 */
4595
4596 /* Patch cmp and new with val at correct position. */
4597 if (ac.aligned && MEM_P (cmp))
4598 {
4599 cmpv = force_reg (SImode, val);
4600 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4601 }
4602 else
4603 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4604 NULL_RTX, 1, OPTAB_DIRECT));
4605 if (ac.aligned && MEM_P (new_rtx))
4606 {
4607 newv = force_reg (SImode, val);
4608 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4609 }
4610 else
4611 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4612 NULL_RTX, 1, OPTAB_DIRECT));
4613
4614 /* Jump to end if we're done (likely?). */
4615 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4616 cmpv, newv));
4617
4618 /* Check for changes outside mode. */
4619 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4620 NULL_RTX, 1, OPTAB_DIRECT);
4621 cc = s390_emit_compare (NE, resv, val);
4622 emit_move_insn (val, resv);
4623 /* Loop internal if so. */
4624 s390_emit_jump (csloop, cc);
4625
4626 emit_label (csend);
4627
4628 /* Return the correct part of the bitfield. */
4629 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4630 NULL_RTX, 1, OPTAB_DIRECT), 1);
4631 }
4632
4633 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4634 and VAL the value to play with. If AFTER is true then store the value
4635 MEM holds after the operation, if AFTER is false then store the value MEM
4636 holds before the operation. If TARGET is zero then discard that value, else
4637 store it to TARGET. */
4638
4639 void
4640 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4641 rtx target, rtx mem, rtx val, bool after)
4642 {
4643 struct alignment_context ac;
4644 rtx cmp;
4645 rtx new_rtx = gen_reg_rtx (SImode);
4646 rtx orig = gen_reg_rtx (SImode);
4647 rtx csloop = gen_label_rtx ();
4648
4649 gcc_assert (!target || register_operand (target, VOIDmode));
4650 gcc_assert (MEM_P (mem));
4651
4652 init_alignment_context (&ac, mem, mode);
4653
4654 /* Shift val to the correct bit positions.
4655 Preserve "icm", but prevent "ex icm". */
4656 if (!(ac.aligned && code == SET && MEM_P (val)))
4657 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4658
4659 /* Further preparation insns. */
4660 if (code == PLUS || code == MINUS)
4661 emit_move_insn (orig, val);
4662 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4663 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4664 NULL_RTX, 1, OPTAB_DIRECT);
4665
4666 /* Load full word. Subsequent loads are performed by CS. */
4667 cmp = force_reg (SImode, ac.memsi);
4668
4669 /* Start CS loop. */
4670 emit_label (csloop);
4671 emit_move_insn (new_rtx, cmp);
4672
4673 /* Patch new with val at correct position. */
4674 switch (code)
4675 {
4676 case PLUS:
4677 case MINUS:
4678 val = expand_simple_binop (SImode, code, new_rtx, orig,
4679 NULL_RTX, 1, OPTAB_DIRECT);
4680 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4681 NULL_RTX, 1, OPTAB_DIRECT);
4682 /* FALLTHRU */
4683 case SET:
4684 if (ac.aligned && MEM_P (val))
4685 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4686 else
4687 {
4688 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4689 NULL_RTX, 1, OPTAB_DIRECT);
4690 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4691 NULL_RTX, 1, OPTAB_DIRECT);
4692 }
4693 break;
4694 case AND:
4695 case IOR:
4696 case XOR:
4697 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4698 NULL_RTX, 1, OPTAB_DIRECT);
4699 break;
4700 case MULT: /* NAND */
4701 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4702 NULL_RTX, 1, OPTAB_DIRECT);
4703 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4704 NULL_RTX, 1, OPTAB_DIRECT);
4705 break;
4706 default:
4707 gcc_unreachable ();
4708 }
4709
4710 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4711 ac.memsi, cmp, new_rtx));
4712
4713 /* Return the correct part of the bitfield. */
4714 if (target)
4715 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4716 after ? new_rtx : cmp, ac.shift,
4717 NULL_RTX, 1, OPTAB_DIRECT), 1);
4718 }
4719
4720 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4721 We need to emit DTP-relative relocations. */
4722
4723 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4724
4725 static void
4726 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4727 {
4728 switch (size)
4729 {
4730 case 4:
4731 fputs ("\t.long\t", file);
4732 break;
4733 case 8:
4734 fputs ("\t.quad\t", file);
4735 break;
4736 default:
4737 gcc_unreachable ();
4738 }
4739 output_addr_const (file, x);
4740 fputs ("@DTPOFF", file);
4741 }
4742
4743 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4744 /* Implement TARGET_MANGLE_TYPE. */
4745
4746 static const char *
4747 s390_mangle_type (const_tree type)
4748 {
4749 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4750 && TARGET_LONG_DOUBLE_128)
4751 return "g";
4752
4753 /* For all other types, use normal C++ mangling. */
4754 return NULL;
4755 }
4756 #endif
4757
4758 /* In the name of slightly smaller debug output, and to cater to
4759 general assembler lossage, recognize various UNSPEC sequences
4760 and turn them back into a direct symbol reference. */
4761
4762 static rtx
4763 s390_delegitimize_address (rtx orig_x)
4764 {
4765 rtx x, y;
4766
4767 orig_x = delegitimize_mem_from_attrs (orig_x);
4768 x = orig_x;
4769 if (GET_CODE (x) != MEM)
4770 return orig_x;
4771
4772 x = XEXP (x, 0);
4773 if (GET_CODE (x) == PLUS
4774 && GET_CODE (XEXP (x, 1)) == CONST
4775 && GET_CODE (XEXP (x, 0)) == REG
4776 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4777 {
4778 y = XEXP (XEXP (x, 1), 0);
4779 if (GET_CODE (y) == UNSPEC
4780 && XINT (y, 1) == UNSPEC_GOT)
4781 return XVECEXP (y, 0, 0);
4782 return orig_x;
4783 }
4784
4785 if (GET_CODE (x) == CONST)
4786 {
4787 y = XEXP (x, 0);
4788 if (GET_CODE (y) == UNSPEC
4789 && XINT (y, 1) == UNSPEC_GOTENT)
4790 return XVECEXP (y, 0, 0);
4791 return orig_x;
4792 }
4793
4794 return orig_x;
4795 }
4796
4797 /* Output operand OP to stdio stream FILE.
4798 OP is an address (register + offset) which is not used to address data;
4799 instead the rightmost bits are interpreted as the value. */
4800
4801 static void
4802 print_shift_count_operand (FILE *file, rtx op)
4803 {
4804 HOST_WIDE_INT offset;
4805 rtx base;
4806
4807 /* Extract base register and offset. */
4808 if (!s390_decompose_shift_count (op, &base, &offset))
4809 gcc_unreachable ();
4810
4811 /* Sanity check. */
4812 if (base)
4813 {
4814 gcc_assert (GET_CODE (base) == REG);
4815 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4816 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4817 }
4818
4819 /* Offsets are constricted to twelve bits. */
4820 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4821 if (base)
4822 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4823 }
4824
4825 /* See 'get_some_local_dynamic_name'. */
4826
4827 static int
4828 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4829 {
4830 rtx x = *px;
4831
4832 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4833 {
4834 x = get_pool_constant (x);
4835 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4836 }
4837
4838 if (GET_CODE (x) == SYMBOL_REF
4839 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4840 {
4841 cfun->machine->some_ld_name = XSTR (x, 0);
4842 return 1;
4843 }
4844
4845 return 0;
4846 }
4847
4848 /* Locate some local-dynamic symbol still in use by this function
4849 so that we can print its name in local-dynamic base patterns. */
4850
4851 static const char *
4852 get_some_local_dynamic_name (void)
4853 {
4854 rtx insn;
4855
4856 if (cfun->machine->some_ld_name)
4857 return cfun->machine->some_ld_name;
4858
4859 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4860 if (INSN_P (insn)
4861 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4862 return cfun->machine->some_ld_name;
4863
4864 gcc_unreachable ();
4865 }
4866
4867 /* Output machine-dependent UNSPECs occurring in address constant X
4868 in assembler syntax to stdio stream FILE. Returns true if the
4869 constant X could be recognized, false otherwise. */
4870
4871 bool
4872 s390_output_addr_const_extra (FILE *file, rtx x)
4873 {
4874 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4875 switch (XINT (x, 1))
4876 {
4877 case UNSPEC_GOTENT:
4878 output_addr_const (file, XVECEXP (x, 0, 0));
4879 fprintf (file, "@GOTENT");
4880 return true;
4881 case UNSPEC_GOT:
4882 output_addr_const (file, XVECEXP (x, 0, 0));
4883 fprintf (file, "@GOT");
4884 return true;
4885 case UNSPEC_GOTOFF:
4886 output_addr_const (file, XVECEXP (x, 0, 0));
4887 fprintf (file, "@GOTOFF");
4888 return true;
4889 case UNSPEC_PLT:
4890 output_addr_const (file, XVECEXP (x, 0, 0));
4891 fprintf (file, "@PLT");
4892 return true;
4893 case UNSPEC_PLTOFF:
4894 output_addr_const (file, XVECEXP (x, 0, 0));
4895 fprintf (file, "@PLTOFF");
4896 return true;
4897 case UNSPEC_TLSGD:
4898 output_addr_const (file, XVECEXP (x, 0, 0));
4899 fprintf (file, "@TLSGD");
4900 return true;
4901 case UNSPEC_TLSLDM:
4902 assemble_name (file, get_some_local_dynamic_name ());
4903 fprintf (file, "@TLSLDM");
4904 return true;
4905 case UNSPEC_DTPOFF:
4906 output_addr_const (file, XVECEXP (x, 0, 0));
4907 fprintf (file, "@DTPOFF");
4908 return true;
4909 case UNSPEC_NTPOFF:
4910 output_addr_const (file, XVECEXP (x, 0, 0));
4911 fprintf (file, "@NTPOFF");
4912 return true;
4913 case UNSPEC_GOTNTPOFF:
4914 output_addr_const (file, XVECEXP (x, 0, 0));
4915 fprintf (file, "@GOTNTPOFF");
4916 return true;
4917 case UNSPEC_INDNTPOFF:
4918 output_addr_const (file, XVECEXP (x, 0, 0));
4919 fprintf (file, "@INDNTPOFF");
4920 return true;
4921 }
4922
4923 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
4924 switch (XINT (x, 1))
4925 {
4926 case UNSPEC_POOL_OFFSET:
4927 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
4928 output_addr_const (file, x);
4929 return true;
4930 }
4931 return false;
4932 }
4933
4934 /* Output address operand ADDR in assembler syntax to
4935 stdio stream FILE. */
4936
4937 void
4938 print_operand_address (FILE *file, rtx addr)
4939 {
4940 struct s390_address ad;
4941
4942 if (s390_symref_operand_p (addr, NULL, NULL))
4943 {
4944 gcc_assert (TARGET_Z10);
4945 output_addr_const (file, addr);
4946 return;
4947 }
4948
4949 if (!s390_decompose_address (addr, &ad)
4950 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4951 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4952 output_operand_lossage ("cannot decompose address");
4953
4954 if (ad.disp)
4955 output_addr_const (file, ad.disp);
4956 else
4957 fprintf (file, "0");
4958
4959 if (ad.base && ad.indx)
4960 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4961 reg_names[REGNO (ad.base)]);
4962 else if (ad.base)
4963 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4964 }
4965
4966 /* Output operand X in assembler syntax to stdio stream FILE.
4967 CODE specified the format flag. The following format flags
4968 are recognized:
4969
4970 'C': print opcode suffix for branch condition.
4971 'D': print opcode suffix for inverse branch condition.
4972 'E': print opcode suffix for branch on index instruction.
4973 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4974 'G': print the size of the operand in bytes.
4975 'O': print only the displacement of a memory reference.
4976 'R': print only the base register of a memory reference.
4977 'S': print S-type memory reference (base+displacement).
4978 'N': print the second word of a DImode operand.
4979 'M': print the second word of a TImode operand.
4980 'Y': print shift count operand.
4981
4982 'b': print integer X as if it's an unsigned byte.
4983 'c': print integer X as if it's an signed byte.
4984 'x': print integer X as if it's an unsigned halfword.
4985 'h': print integer X as if it's a signed halfword.
4986 'i': print the first nonzero HImode part of X.
4987 'j': print the first HImode part unequal to -1 of X.
4988 'k': print the first nonzero SImode part of X.
4989 'm': print the first SImode part unequal to -1 of X.
4990 'o': print integer X as if it's an unsigned 32bit word. */
4991
4992 void
4993 print_operand (FILE *file, rtx x, int code)
4994 {
4995 switch (code)
4996 {
4997 case 'C':
4998 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4999 return;
5000
5001 case 'D':
5002 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5003 return;
5004
5005 case 'E':
5006 if (GET_CODE (x) == LE)
5007 fprintf (file, "l");
5008 else if (GET_CODE (x) == GT)
5009 fprintf (file, "h");
5010 else
5011 gcc_unreachable ();
5012 return;
5013
5014 case 'J':
5015 if (GET_CODE (x) == SYMBOL_REF)
5016 {
5017 fprintf (file, "%s", ":tls_load:");
5018 output_addr_const (file, x);
5019 }
5020 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5021 {
5022 fprintf (file, "%s", ":tls_gdcall:");
5023 output_addr_const (file, XVECEXP (x, 0, 0));
5024 }
5025 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5026 {
5027 fprintf (file, "%s", ":tls_ldcall:");
5028 assemble_name (file, get_some_local_dynamic_name ());
5029 }
5030 else
5031 gcc_unreachable ();
5032 return;
5033
5034 case 'G':
5035 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5036 return;
5037
5038 case 'O':
5039 {
5040 struct s390_address ad;
5041 int ret;
5042
5043 gcc_assert (GET_CODE (x) == MEM);
5044 ret = s390_decompose_address (XEXP (x, 0), &ad);
5045 gcc_assert (ret);
5046 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5047 gcc_assert (!ad.indx);
5048
5049 if (ad.disp)
5050 output_addr_const (file, ad.disp);
5051 else
5052 fprintf (file, "0");
5053 }
5054 return;
5055
5056 case 'R':
5057 {
5058 struct s390_address ad;
5059 int ret;
5060
5061 gcc_assert (GET_CODE (x) == MEM);
5062 ret = s390_decompose_address (XEXP (x, 0), &ad);
5063 gcc_assert (ret);
5064 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5065 gcc_assert (!ad.indx);
5066
5067 if (ad.base)
5068 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5069 else
5070 fprintf (file, "0");
5071 }
5072 return;
5073
5074 case 'S':
5075 {
5076 struct s390_address ad;
5077 int ret;
5078
5079 gcc_assert (GET_CODE (x) == MEM);
5080 ret = s390_decompose_address (XEXP (x, 0), &ad);
5081 gcc_assert (ret);
5082 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5083 gcc_assert (!ad.indx);
5084
5085 if (ad.disp)
5086 output_addr_const (file, ad.disp);
5087 else
5088 fprintf (file, "0");
5089
5090 if (ad.base)
5091 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5092 }
5093 return;
5094
5095 case 'N':
5096 if (GET_CODE (x) == REG)
5097 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5098 else if (GET_CODE (x) == MEM)
5099 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5100 else
5101 gcc_unreachable ();
5102 break;
5103
5104 case 'M':
5105 if (GET_CODE (x) == REG)
5106 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5107 else if (GET_CODE (x) == MEM)
5108 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5109 else
5110 gcc_unreachable ();
5111 break;
5112
5113 case 'Y':
5114 print_shift_count_operand (file, x);
5115 return;
5116 }
5117
5118 switch (GET_CODE (x))
5119 {
5120 case REG:
5121 fprintf (file, "%s", reg_names[REGNO (x)]);
5122 break;
5123
5124 case MEM:
5125 output_address (XEXP (x, 0));
5126 break;
5127
5128 case CONST:
5129 case CODE_LABEL:
5130 case LABEL_REF:
5131 case SYMBOL_REF:
5132 output_addr_const (file, x);
5133 break;
5134
5135 case CONST_INT:
5136 if (code == 'b')
5137 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5138 else if (code == 'c')
5139 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5140 else if (code == 'x')
5141 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5142 else if (code == 'h')
5143 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5144 else if (code == 'i')
5145 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5146 s390_extract_part (x, HImode, 0));
5147 else if (code == 'j')
5148 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5149 s390_extract_part (x, HImode, -1));
5150 else if (code == 'k')
5151 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5152 s390_extract_part (x, SImode, 0));
5153 else if (code == 'm')
5154 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5155 s390_extract_part (x, SImode, -1));
5156 else if (code == 'o')
5157 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5158 else
5159 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5160 break;
5161
5162 case CONST_DOUBLE:
5163 gcc_assert (GET_MODE (x) == VOIDmode);
5164 if (code == 'b')
5165 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5166 else if (code == 'x')
5167 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5168 else if (code == 'h')
5169 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5170 else
5171 gcc_unreachable ();
5172 break;
5173
5174 default:
5175 fatal_insn ("UNKNOWN in print_operand !?", x);
5176 break;
5177 }
5178 }
5179
5180 /* Target hook for assembling integer objects. We need to define it
5181 here to work a round a bug in some versions of GAS, which couldn't
5182 handle values smaller than INT_MIN when printed in decimal. */
5183
5184 static bool
5185 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5186 {
5187 if (size == 8 && aligned_p
5188 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5189 {
5190 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5191 INTVAL (x));
5192 return true;
5193 }
5194 return default_assemble_integer (x, size, aligned_p);
5195 }
5196
5197 /* Returns true if register REGNO is used for forming
5198 a memory address in expression X. */
5199
5200 static bool
5201 reg_used_in_mem_p (int regno, rtx x)
5202 {
5203 enum rtx_code code = GET_CODE (x);
5204 int i, j;
5205 const char *fmt;
5206
5207 if (code == MEM)
5208 {
5209 if (refers_to_regno_p (regno, regno+1,
5210 XEXP (x, 0), 0))
5211 return true;
5212 }
5213 else if (code == SET
5214 && GET_CODE (SET_DEST (x)) == PC)
5215 {
5216 if (refers_to_regno_p (regno, regno+1,
5217 SET_SRC (x), 0))
5218 return true;
5219 }
5220
5221 fmt = GET_RTX_FORMAT (code);
5222 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5223 {
5224 if (fmt[i] == 'e'
5225 && reg_used_in_mem_p (regno, XEXP (x, i)))
5226 return true;
5227
5228 else if (fmt[i] == 'E')
5229 for (j = 0; j < XVECLEN (x, i); j++)
5230 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5231 return true;
5232 }
5233 return false;
5234 }
5235
5236 /* Returns true if expression DEP_RTX sets an address register
5237 used by instruction INSN to address memory. */
5238
5239 static bool
5240 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5241 {
5242 rtx target, pat;
5243
5244 if (GET_CODE (dep_rtx) == INSN)
5245 dep_rtx = PATTERN (dep_rtx);
5246
5247 if (GET_CODE (dep_rtx) == SET)
5248 {
5249 target = SET_DEST (dep_rtx);
5250 if (GET_CODE (target) == STRICT_LOW_PART)
5251 target = XEXP (target, 0);
5252 while (GET_CODE (target) == SUBREG)
5253 target = SUBREG_REG (target);
5254
5255 if (GET_CODE (target) == REG)
5256 {
5257 int regno = REGNO (target);
5258
5259 if (s390_safe_attr_type (insn) == TYPE_LA)
5260 {
5261 pat = PATTERN (insn);
5262 if (GET_CODE (pat) == PARALLEL)
5263 {
5264 gcc_assert (XVECLEN (pat, 0) == 2);
5265 pat = XVECEXP (pat, 0, 0);
5266 }
5267 gcc_assert (GET_CODE (pat) == SET);
5268 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5269 }
5270 else if (get_attr_atype (insn) == ATYPE_AGEN)
5271 return reg_used_in_mem_p (regno, PATTERN (insn));
5272 }
5273 }
5274 return false;
5275 }
5276
5277 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5278
5279 int
5280 s390_agen_dep_p (rtx dep_insn, rtx insn)
5281 {
5282 rtx dep_rtx = PATTERN (dep_insn);
5283 int i;
5284
5285 if (GET_CODE (dep_rtx) == SET
5286 && addr_generation_dependency_p (dep_rtx, insn))
5287 return 1;
5288 else if (GET_CODE (dep_rtx) == PARALLEL)
5289 {
5290 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5291 {
5292 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5293 return 1;
5294 }
5295 }
5296 return 0;
5297 }
5298
5299
5300 /* A C statement (sans semicolon) to update the integer scheduling priority
5301 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5302 reduce the priority to execute INSN later. Do not define this macro if
5303 you do not need to adjust the scheduling priorities of insns.
5304
5305 A STD instruction should be scheduled earlier,
5306 in order to use the bypass. */
5307
5308
5309 static int
5310 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5311 {
5312 if (! INSN_P (insn))
5313 return priority;
5314
5315 if (s390_tune != PROCESSOR_2084_Z990
5316 && s390_tune != PROCESSOR_2094_Z9_109
5317 && s390_tune != PROCESSOR_2097_Z10)
5318 return priority;
5319
5320 switch (s390_safe_attr_type (insn))
5321 {
5322 case TYPE_FSTOREDF:
5323 case TYPE_FSTORESF:
5324 priority = priority << 3;
5325 break;
5326 case TYPE_STORE:
5327 case TYPE_STM:
5328 priority = priority << 1;
5329 break;
5330 default:
5331 break;
5332 }
5333 return priority;
5334 }
5335
5336
5337 /* The number of instructions that can be issued per cycle. */
5338
5339 static int
5340 s390_issue_rate (void)
5341 {
5342 switch (s390_tune)
5343 {
5344 case PROCESSOR_2084_Z990:
5345 case PROCESSOR_2094_Z9_109:
5346 return 3;
5347 case PROCESSOR_2097_Z10:
5348 return 2;
5349 default:
5350 return 1;
5351 }
5352 }
5353
5354 static int
5355 s390_first_cycle_multipass_dfa_lookahead (void)
5356 {
5357 return 4;
5358 }
5359
5360
5361 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5362 Fix up MEMs as required. */
5363
5364 static void
5365 annotate_constant_pool_refs (rtx *x)
5366 {
5367 int i, j;
5368 const char *fmt;
5369
5370 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5371 || !CONSTANT_POOL_ADDRESS_P (*x));
5372
5373 /* Literal pool references can only occur inside a MEM ... */
5374 if (GET_CODE (*x) == MEM)
5375 {
5376 rtx memref = XEXP (*x, 0);
5377
5378 if (GET_CODE (memref) == SYMBOL_REF
5379 && CONSTANT_POOL_ADDRESS_P (memref))
5380 {
5381 rtx base = cfun->machine->base_reg;
5382 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5383 UNSPEC_LTREF);
5384
5385 *x = replace_equiv_address (*x, addr);
5386 return;
5387 }
5388
5389 if (GET_CODE (memref) == CONST
5390 && GET_CODE (XEXP (memref, 0)) == PLUS
5391 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5392 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5393 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5394 {
5395 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5396 rtx sym = XEXP (XEXP (memref, 0), 0);
5397 rtx base = cfun->machine->base_reg;
5398 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5399 UNSPEC_LTREF);
5400
5401 *x = replace_equiv_address (*x, plus_constant (addr, off));
5402 return;
5403 }
5404 }
5405
5406 /* ... or a load-address type pattern. */
5407 if (GET_CODE (*x) == SET)
5408 {
5409 rtx addrref = SET_SRC (*x);
5410
5411 if (GET_CODE (addrref) == SYMBOL_REF
5412 && CONSTANT_POOL_ADDRESS_P (addrref))
5413 {
5414 rtx base = cfun->machine->base_reg;
5415 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5416 UNSPEC_LTREF);
5417
5418 SET_SRC (*x) = addr;
5419 return;
5420 }
5421
5422 if (GET_CODE (addrref) == CONST
5423 && GET_CODE (XEXP (addrref, 0)) == PLUS
5424 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5425 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5426 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5427 {
5428 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5429 rtx sym = XEXP (XEXP (addrref, 0), 0);
5430 rtx base = cfun->machine->base_reg;
5431 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5432 UNSPEC_LTREF);
5433
5434 SET_SRC (*x) = plus_constant (addr, off);
5435 return;
5436 }
5437 }
5438
5439 /* Annotate LTREL_BASE as well. */
5440 if (GET_CODE (*x) == UNSPEC
5441 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5442 {
5443 rtx base = cfun->machine->base_reg;
5444 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5445 UNSPEC_LTREL_BASE);
5446 return;
5447 }
5448
5449 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5450 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5451 {
5452 if (fmt[i] == 'e')
5453 {
5454 annotate_constant_pool_refs (&XEXP (*x, i));
5455 }
5456 else if (fmt[i] == 'E')
5457 {
5458 for (j = 0; j < XVECLEN (*x, i); j++)
5459 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5460 }
5461 }
5462 }
5463
5464 /* Split all branches that exceed the maximum distance.
5465 Returns true if this created a new literal pool entry. */
5466
5467 static int
5468 s390_split_branches (void)
5469 {
5470 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5471 int new_literal = 0, ret;
5472 rtx insn, pat, tmp, target;
5473 rtx *label;
5474
5475 /* We need correct insn addresses. */
5476
5477 shorten_branches (get_insns ());
5478
5479 /* Find all branches that exceed 64KB, and split them. */
5480
5481 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5482 {
5483 if (GET_CODE (insn) != JUMP_INSN)
5484 continue;
5485
5486 pat = PATTERN (insn);
5487 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5488 pat = XVECEXP (pat, 0, 0);
5489 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5490 continue;
5491
5492 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5493 {
5494 label = &SET_SRC (pat);
5495 }
5496 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5497 {
5498 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5499 label = &XEXP (SET_SRC (pat), 1);
5500 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5501 label = &XEXP (SET_SRC (pat), 2);
5502 else
5503 continue;
5504 }
5505 else
5506 continue;
5507
5508 if (get_attr_length (insn) <= 4)
5509 continue;
5510
5511 /* We are going to use the return register as scratch register,
5512 make sure it will be saved/restored by the prologue/epilogue. */
5513 cfun_frame_layout.save_return_addr_p = 1;
5514
5515 if (!flag_pic)
5516 {
5517 new_literal = 1;
5518 tmp = force_const_mem (Pmode, *label);
5519 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5520 INSN_ADDRESSES_NEW (tmp, -1);
5521 annotate_constant_pool_refs (&PATTERN (tmp));
5522
5523 target = temp_reg;
5524 }
5525 else
5526 {
5527 new_literal = 1;
5528 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5529 UNSPEC_LTREL_OFFSET);
5530 target = gen_rtx_CONST (Pmode, target);
5531 target = force_const_mem (Pmode, target);
5532 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5533 INSN_ADDRESSES_NEW (tmp, -1);
5534 annotate_constant_pool_refs (&PATTERN (tmp));
5535
5536 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5537 cfun->machine->base_reg),
5538 UNSPEC_LTREL_BASE);
5539 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5540 }
5541
5542 ret = validate_change (insn, label, target, 0);
5543 gcc_assert (ret);
5544 }
5545
5546 return new_literal;
5547 }
5548
5549
5550 /* Find an annotated literal pool symbol referenced in RTX X,
5551 and store it at REF. Will abort if X contains references to
5552 more than one such pool symbol; multiple references to the same
5553 symbol are allowed, however.
5554
5555 The rtx pointed to by REF must be initialized to NULL_RTX
5556 by the caller before calling this routine. */
5557
5558 static void
5559 find_constant_pool_ref (rtx x, rtx *ref)
5560 {
5561 int i, j;
5562 const char *fmt;
5563
5564 /* Ignore LTREL_BASE references. */
5565 if (GET_CODE (x) == UNSPEC
5566 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5567 return;
5568 /* Likewise POOL_ENTRY insns. */
5569 if (GET_CODE (x) == UNSPEC_VOLATILE
5570 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5571 return;
5572
5573 gcc_assert (GET_CODE (x) != SYMBOL_REF
5574 || !CONSTANT_POOL_ADDRESS_P (x));
5575
5576 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5577 {
5578 rtx sym = XVECEXP (x, 0, 0);
5579 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5580 && CONSTANT_POOL_ADDRESS_P (sym));
5581
5582 if (*ref == NULL_RTX)
5583 *ref = sym;
5584 else
5585 gcc_assert (*ref == sym);
5586
5587 return;
5588 }
5589
5590 fmt = GET_RTX_FORMAT (GET_CODE (x));
5591 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5592 {
5593 if (fmt[i] == 'e')
5594 {
5595 find_constant_pool_ref (XEXP (x, i), ref);
5596 }
5597 else if (fmt[i] == 'E')
5598 {
5599 for (j = 0; j < XVECLEN (x, i); j++)
5600 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5601 }
5602 }
5603 }
5604
5605 /* Replace every reference to the annotated literal pool
5606 symbol REF in X by its base plus OFFSET. */
5607
5608 static void
5609 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5610 {
5611 int i, j;
5612 const char *fmt;
5613
5614 gcc_assert (*x != ref);
5615
5616 if (GET_CODE (*x) == UNSPEC
5617 && XINT (*x, 1) == UNSPEC_LTREF
5618 && XVECEXP (*x, 0, 0) == ref)
5619 {
5620 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5621 return;
5622 }
5623
5624 if (GET_CODE (*x) == PLUS
5625 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5626 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5627 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5628 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5629 {
5630 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5631 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5632 return;
5633 }
5634
5635 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5636 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5637 {
5638 if (fmt[i] == 'e')
5639 {
5640 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5641 }
5642 else if (fmt[i] == 'E')
5643 {
5644 for (j = 0; j < XVECLEN (*x, i); j++)
5645 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5646 }
5647 }
5648 }
5649
5650 /* Check whether X contains an UNSPEC_LTREL_BASE.
5651 Return its constant pool symbol if found, NULL_RTX otherwise. */
5652
5653 static rtx
5654 find_ltrel_base (rtx x)
5655 {
5656 int i, j;
5657 const char *fmt;
5658
5659 if (GET_CODE (x) == UNSPEC
5660 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5661 return XVECEXP (x, 0, 0);
5662
5663 fmt = GET_RTX_FORMAT (GET_CODE (x));
5664 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5665 {
5666 if (fmt[i] == 'e')
5667 {
5668 rtx fnd = find_ltrel_base (XEXP (x, i));
5669 if (fnd)
5670 return fnd;
5671 }
5672 else if (fmt[i] == 'E')
5673 {
5674 for (j = 0; j < XVECLEN (x, i); j++)
5675 {
5676 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5677 if (fnd)
5678 return fnd;
5679 }
5680 }
5681 }
5682
5683 return NULL_RTX;
5684 }
5685
5686 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5687
5688 static void
5689 replace_ltrel_base (rtx *x)
5690 {
5691 int i, j;
5692 const char *fmt;
5693
5694 if (GET_CODE (*x) == UNSPEC
5695 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5696 {
5697 *x = XVECEXP (*x, 0, 1);
5698 return;
5699 }
5700
5701 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5702 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5703 {
5704 if (fmt[i] == 'e')
5705 {
5706 replace_ltrel_base (&XEXP (*x, i));
5707 }
5708 else if (fmt[i] == 'E')
5709 {
5710 for (j = 0; j < XVECLEN (*x, i); j++)
5711 replace_ltrel_base (&XVECEXP (*x, i, j));
5712 }
5713 }
5714 }
5715
5716
5717 /* We keep a list of constants which we have to add to internal
5718 constant tables in the middle of large functions. */
5719
5720 #define NR_C_MODES 11
5721 enum machine_mode constant_modes[NR_C_MODES] =
5722 {
5723 TFmode, TImode, TDmode,
5724 DFmode, DImode, DDmode,
5725 SFmode, SImode, SDmode,
5726 HImode,
5727 QImode
5728 };
5729
5730 struct constant
5731 {
5732 struct constant *next;
5733 rtx value;
5734 rtx label;
5735 };
5736
5737 struct constant_pool
5738 {
5739 struct constant_pool *next;
5740 rtx first_insn;
5741 rtx pool_insn;
5742 bitmap insns;
5743 rtx emit_pool_after;
5744
5745 struct constant *constants[NR_C_MODES];
5746 struct constant *execute;
5747 rtx label;
5748 int size;
5749 };
5750
5751 /* Allocate new constant_pool structure. */
5752
5753 static struct constant_pool *
5754 s390_alloc_pool (void)
5755 {
5756 struct constant_pool *pool;
5757 int i;
5758
5759 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5760 pool->next = NULL;
5761 for (i = 0; i < NR_C_MODES; i++)
5762 pool->constants[i] = NULL;
5763
5764 pool->execute = NULL;
5765 pool->label = gen_label_rtx ();
5766 pool->first_insn = NULL_RTX;
5767 pool->pool_insn = NULL_RTX;
5768 pool->insns = BITMAP_ALLOC (NULL);
5769 pool->size = 0;
5770 pool->emit_pool_after = NULL_RTX;
5771
5772 return pool;
5773 }
5774
5775 /* Create new constant pool covering instructions starting at INSN
5776 and chain it to the end of POOL_LIST. */
5777
5778 static struct constant_pool *
5779 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5780 {
5781 struct constant_pool *pool, **prev;
5782
5783 pool = s390_alloc_pool ();
5784 pool->first_insn = insn;
5785
5786 for (prev = pool_list; *prev; prev = &(*prev)->next)
5787 ;
5788 *prev = pool;
5789
5790 return pool;
5791 }
5792
5793 /* End range of instructions covered by POOL at INSN and emit
5794 placeholder insn representing the pool. */
5795
5796 static void
5797 s390_end_pool (struct constant_pool *pool, rtx insn)
5798 {
5799 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5800
5801 if (!insn)
5802 insn = get_last_insn ();
5803
5804 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5805 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5806 }
5807
5808 /* Add INSN to the list of insns covered by POOL. */
5809
5810 static void
5811 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5812 {
5813 bitmap_set_bit (pool->insns, INSN_UID (insn));
5814 }
5815
5816 /* Return pool out of POOL_LIST that covers INSN. */
5817
5818 static struct constant_pool *
5819 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5820 {
5821 struct constant_pool *pool;
5822
5823 for (pool = pool_list; pool; pool = pool->next)
5824 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5825 break;
5826
5827 return pool;
5828 }
5829
5830 /* Add constant VAL of mode MODE to the constant pool POOL. */
5831
5832 static void
5833 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5834 {
5835 struct constant *c;
5836 int i;
5837
5838 for (i = 0; i < NR_C_MODES; i++)
5839 if (constant_modes[i] == mode)
5840 break;
5841 gcc_assert (i != NR_C_MODES);
5842
5843 for (c = pool->constants[i]; c != NULL; c = c->next)
5844 if (rtx_equal_p (val, c->value))
5845 break;
5846
5847 if (c == NULL)
5848 {
5849 c = (struct constant *) xmalloc (sizeof *c);
5850 c->value = val;
5851 c->label = gen_label_rtx ();
5852 c->next = pool->constants[i];
5853 pool->constants[i] = c;
5854 pool->size += GET_MODE_SIZE (mode);
5855 }
5856 }
5857
5858 /* Return an rtx that represents the offset of X from the start of
5859 pool POOL. */
5860
5861 static rtx
5862 s390_pool_offset (struct constant_pool *pool, rtx x)
5863 {
5864 rtx label;
5865
5866 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5867 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5868 UNSPEC_POOL_OFFSET);
5869 return gen_rtx_CONST (GET_MODE (x), x);
5870 }
5871
5872 /* Find constant VAL of mode MODE in the constant pool POOL.
5873 Return an RTX describing the distance from the start of
5874 the pool to the location of the new constant. */
5875
5876 static rtx
5877 s390_find_constant (struct constant_pool *pool, rtx val,
5878 enum machine_mode mode)
5879 {
5880 struct constant *c;
5881 int i;
5882
5883 for (i = 0; i < NR_C_MODES; i++)
5884 if (constant_modes[i] == mode)
5885 break;
5886 gcc_assert (i != NR_C_MODES);
5887
5888 for (c = pool->constants[i]; c != NULL; c = c->next)
5889 if (rtx_equal_p (val, c->value))
5890 break;
5891
5892 gcc_assert (c);
5893
5894 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5895 }
5896
5897 /* Check whether INSN is an execute. Return the label_ref to its
5898 execute target template if so, NULL_RTX otherwise. */
5899
5900 static rtx
5901 s390_execute_label (rtx insn)
5902 {
5903 if (GET_CODE (insn) == INSN
5904 && GET_CODE (PATTERN (insn)) == PARALLEL
5905 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5906 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5907 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5908
5909 return NULL_RTX;
5910 }
5911
5912 /* Add execute target for INSN to the constant pool POOL. */
5913
5914 static void
5915 s390_add_execute (struct constant_pool *pool, rtx insn)
5916 {
5917 struct constant *c;
5918
5919 for (c = pool->execute; c != NULL; c = c->next)
5920 if (INSN_UID (insn) == INSN_UID (c->value))
5921 break;
5922
5923 if (c == NULL)
5924 {
5925 c = (struct constant *) xmalloc (sizeof *c);
5926 c->value = insn;
5927 c->label = gen_label_rtx ();
5928 c->next = pool->execute;
5929 pool->execute = c;
5930 pool->size += 6;
5931 }
5932 }
5933
5934 /* Find execute target for INSN in the constant pool POOL.
5935 Return an RTX describing the distance from the start of
5936 the pool to the location of the execute target. */
5937
5938 static rtx
5939 s390_find_execute (struct constant_pool *pool, rtx insn)
5940 {
5941 struct constant *c;
5942
5943 for (c = pool->execute; c != NULL; c = c->next)
5944 if (INSN_UID (insn) == INSN_UID (c->value))
5945 break;
5946
5947 gcc_assert (c);
5948
5949 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5950 }
5951
5952 /* For an execute INSN, extract the execute target template. */
5953
5954 static rtx
5955 s390_execute_target (rtx insn)
5956 {
5957 rtx pattern = PATTERN (insn);
5958 gcc_assert (s390_execute_label (insn));
5959
5960 if (XVECLEN (pattern, 0) == 2)
5961 {
5962 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5963 }
5964 else
5965 {
5966 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5967 int i;
5968
5969 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5970 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5971
5972 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5973 }
5974
5975 return pattern;
5976 }
5977
5978 /* Indicate that INSN cannot be duplicated. This is the case for
5979 execute insns that carry a unique label. */
5980
5981 static bool
5982 s390_cannot_copy_insn_p (rtx insn)
5983 {
5984 rtx label = s390_execute_label (insn);
5985 return label && label != const0_rtx;
5986 }
5987
5988 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5989 do not emit the pool base label. */
5990
5991 static void
5992 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5993 {
5994 struct constant *c;
5995 rtx insn = pool->pool_insn;
5996 int i;
5997
5998 /* Switch to rodata section. */
5999 if (TARGET_CPU_ZARCH)
6000 {
6001 insn = emit_insn_after (gen_pool_section_start (), insn);
6002 INSN_ADDRESSES_NEW (insn, -1);
6003 }
6004
6005 /* Ensure minimum pool alignment. */
6006 if (TARGET_CPU_ZARCH)
6007 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6008 else
6009 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6010 INSN_ADDRESSES_NEW (insn, -1);
6011
6012 /* Emit pool base label. */
6013 if (!remote_label)
6014 {
6015 insn = emit_label_after (pool->label, insn);
6016 INSN_ADDRESSES_NEW (insn, -1);
6017 }
6018
6019 /* Dump constants in descending alignment requirement order,
6020 ensuring proper alignment for every constant. */
6021 for (i = 0; i < NR_C_MODES; i++)
6022 for (c = pool->constants[i]; c; c = c->next)
6023 {
6024 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6025 rtx value = copy_rtx (c->value);
6026 if (GET_CODE (value) == CONST
6027 && GET_CODE (XEXP (value, 0)) == UNSPEC
6028 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6029 && XVECLEN (XEXP (value, 0), 0) == 1)
6030 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6031
6032 insn = emit_label_after (c->label, insn);
6033 INSN_ADDRESSES_NEW (insn, -1);
6034
6035 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6036 gen_rtvec (1, value),
6037 UNSPECV_POOL_ENTRY);
6038 insn = emit_insn_after (value, insn);
6039 INSN_ADDRESSES_NEW (insn, -1);
6040 }
6041
6042 /* Ensure minimum alignment for instructions. */
6043 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6044 INSN_ADDRESSES_NEW (insn, -1);
6045
6046 /* Output in-pool execute template insns. */
6047 for (c = pool->execute; c; c = c->next)
6048 {
6049 insn = emit_label_after (c->label, insn);
6050 INSN_ADDRESSES_NEW (insn, -1);
6051
6052 insn = emit_insn_after (s390_execute_target (c->value), insn);
6053 INSN_ADDRESSES_NEW (insn, -1);
6054 }
6055
6056 /* Switch back to previous section. */
6057 if (TARGET_CPU_ZARCH)
6058 {
6059 insn = emit_insn_after (gen_pool_section_end (), insn);
6060 INSN_ADDRESSES_NEW (insn, -1);
6061 }
6062
6063 insn = emit_barrier_after (insn);
6064 INSN_ADDRESSES_NEW (insn, -1);
6065
6066 /* Remove placeholder insn. */
6067 remove_insn (pool->pool_insn);
6068 }
6069
6070 /* Free all memory used by POOL. */
6071
6072 static void
6073 s390_free_pool (struct constant_pool *pool)
6074 {
6075 struct constant *c, *next;
6076 int i;
6077
6078 for (i = 0; i < NR_C_MODES; i++)
6079 for (c = pool->constants[i]; c; c = next)
6080 {
6081 next = c->next;
6082 free (c);
6083 }
6084
6085 for (c = pool->execute; c; c = next)
6086 {
6087 next = c->next;
6088 free (c);
6089 }
6090
6091 BITMAP_FREE (pool->insns);
6092 free (pool);
6093 }
6094
6095
6096 /* Collect main literal pool. Return NULL on overflow. */
6097
6098 static struct constant_pool *
6099 s390_mainpool_start (void)
6100 {
6101 struct constant_pool *pool;
6102 rtx insn;
6103
6104 pool = s390_alloc_pool ();
6105
6106 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6107 {
6108 if (GET_CODE (insn) == INSN
6109 && GET_CODE (PATTERN (insn)) == SET
6110 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6111 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6112 {
6113 gcc_assert (!pool->pool_insn);
6114 pool->pool_insn = insn;
6115 }
6116
6117 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6118 {
6119 s390_add_execute (pool, insn);
6120 }
6121 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6122 {
6123 rtx pool_ref = NULL_RTX;
6124 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6125 if (pool_ref)
6126 {
6127 rtx constant = get_pool_constant (pool_ref);
6128 enum machine_mode mode = get_pool_mode (pool_ref);
6129 s390_add_constant (pool, constant, mode);
6130 }
6131 }
6132
6133 /* If hot/cold partitioning is enabled we have to make sure that
6134 the literal pool is emitted in the same section where the
6135 initialization of the literal pool base pointer takes place.
6136 emit_pool_after is only used in the non-overflow case on non
6137 Z cpus where we can emit the literal pool at the end of the
6138 function body within the text section. */
6139 if (NOTE_P (insn)
6140 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6141 && !pool->emit_pool_after)
6142 pool->emit_pool_after = PREV_INSN (insn);
6143 }
6144
6145 gcc_assert (pool->pool_insn || pool->size == 0);
6146
6147 if (pool->size >= 4096)
6148 {
6149 /* We're going to chunkify the pool, so remove the main
6150 pool placeholder insn. */
6151 remove_insn (pool->pool_insn);
6152
6153 s390_free_pool (pool);
6154 pool = NULL;
6155 }
6156
6157 /* If the functions ends with the section where the literal pool
6158 should be emitted set the marker to its end. */
6159 if (pool && !pool->emit_pool_after)
6160 pool->emit_pool_after = get_last_insn ();
6161
6162 return pool;
6163 }
6164
6165 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6166 Modify the current function to output the pool constants as well as
6167 the pool register setup instruction. */
6168
6169 static void
6170 s390_mainpool_finish (struct constant_pool *pool)
6171 {
6172 rtx base_reg = cfun->machine->base_reg;
6173 rtx insn;
6174
6175 /* If the pool is empty, we're done. */
6176 if (pool->size == 0)
6177 {
6178 /* We don't actually need a base register after all. */
6179 cfun->machine->base_reg = NULL_RTX;
6180
6181 if (pool->pool_insn)
6182 remove_insn (pool->pool_insn);
6183 s390_free_pool (pool);
6184 return;
6185 }
6186
6187 /* We need correct insn addresses. */
6188 shorten_branches (get_insns ());
6189
6190 /* On zSeries, we use a LARL to load the pool register. The pool is
6191 located in the .rodata section, so we emit it after the function. */
6192 if (TARGET_CPU_ZARCH)
6193 {
6194 insn = gen_main_base_64 (base_reg, pool->label);
6195 insn = emit_insn_after (insn, pool->pool_insn);
6196 INSN_ADDRESSES_NEW (insn, -1);
6197 remove_insn (pool->pool_insn);
6198
6199 insn = get_last_insn ();
6200 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6201 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6202
6203 s390_dump_pool (pool, 0);
6204 }
6205
6206 /* On S/390, if the total size of the function's code plus literal pool
6207 does not exceed 4096 bytes, we use BASR to set up a function base
6208 pointer, and emit the literal pool at the end of the function. */
6209 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6210 + pool->size + 8 /* alignment slop */ < 4096)
6211 {
6212 insn = gen_main_base_31_small (base_reg, pool->label);
6213 insn = emit_insn_after (insn, pool->pool_insn);
6214 INSN_ADDRESSES_NEW (insn, -1);
6215 remove_insn (pool->pool_insn);
6216
6217 insn = emit_label_after (pool->label, insn);
6218 INSN_ADDRESSES_NEW (insn, -1);
6219
6220 /* emit_pool_after will be set by s390_mainpool_start to the
6221 last insn of the section where the literal pool should be
6222 emitted. */
6223 insn = pool->emit_pool_after;
6224
6225 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6226 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6227
6228 s390_dump_pool (pool, 1);
6229 }
6230
6231 /* Otherwise, we emit an inline literal pool and use BASR to branch
6232 over it, setting up the pool register at the same time. */
6233 else
6234 {
6235 rtx pool_end = gen_label_rtx ();
6236
6237 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6238 insn = emit_insn_after (insn, pool->pool_insn);
6239 INSN_ADDRESSES_NEW (insn, -1);
6240 remove_insn (pool->pool_insn);
6241
6242 insn = emit_label_after (pool->label, insn);
6243 INSN_ADDRESSES_NEW (insn, -1);
6244
6245 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6246 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6247
6248 insn = emit_label_after (pool_end, pool->pool_insn);
6249 INSN_ADDRESSES_NEW (insn, -1);
6250
6251 s390_dump_pool (pool, 1);
6252 }
6253
6254
6255 /* Replace all literal pool references. */
6256
6257 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6258 {
6259 if (INSN_P (insn))
6260 replace_ltrel_base (&PATTERN (insn));
6261
6262 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6263 {
6264 rtx addr, pool_ref = NULL_RTX;
6265 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6266 if (pool_ref)
6267 {
6268 if (s390_execute_label (insn))
6269 addr = s390_find_execute (pool, insn);
6270 else
6271 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6272 get_pool_mode (pool_ref));
6273
6274 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6275 INSN_CODE (insn) = -1;
6276 }
6277 }
6278 }
6279
6280
6281 /* Free the pool. */
6282 s390_free_pool (pool);
6283 }
6284
6285 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6286 We have decided we cannot use this pool, so revert all changes
6287 to the current function that were done by s390_mainpool_start. */
6288 static void
6289 s390_mainpool_cancel (struct constant_pool *pool)
6290 {
6291 /* We didn't actually change the instruction stream, so simply
6292 free the pool memory. */
6293 s390_free_pool (pool);
6294 }
6295
6296
6297 /* Chunkify the literal pool. */
6298
6299 #define S390_POOL_CHUNK_MIN 0xc00
6300 #define S390_POOL_CHUNK_MAX 0xe00
6301
6302 static struct constant_pool *
6303 s390_chunkify_start (void)
6304 {
6305 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6306 int extra_size = 0;
6307 bitmap far_labels;
6308 rtx pending_ltrel = NULL_RTX;
6309 rtx insn;
6310
6311 rtx (*gen_reload_base) (rtx, rtx) =
6312 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6313
6314
6315 /* We need correct insn addresses. */
6316
6317 shorten_branches (get_insns ());
6318
6319 /* Scan all insns and move literals to pool chunks. */
6320
6321 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6322 {
6323 bool section_switch_p = false;
6324
6325 /* Check for pending LTREL_BASE. */
6326 if (INSN_P (insn))
6327 {
6328 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6329 if (ltrel_base)
6330 {
6331 gcc_assert (ltrel_base == pending_ltrel);
6332 pending_ltrel = NULL_RTX;
6333 }
6334 }
6335
6336 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6337 {
6338 if (!curr_pool)
6339 curr_pool = s390_start_pool (&pool_list, insn);
6340
6341 s390_add_execute (curr_pool, insn);
6342 s390_add_pool_insn (curr_pool, insn);
6343 }
6344 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6345 {
6346 rtx pool_ref = NULL_RTX;
6347 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6348 if (pool_ref)
6349 {
6350 rtx constant = get_pool_constant (pool_ref);
6351 enum machine_mode mode = get_pool_mode (pool_ref);
6352
6353 if (!curr_pool)
6354 curr_pool = s390_start_pool (&pool_list, insn);
6355
6356 s390_add_constant (curr_pool, constant, mode);
6357 s390_add_pool_insn (curr_pool, insn);
6358
6359 /* Don't split the pool chunk between a LTREL_OFFSET load
6360 and the corresponding LTREL_BASE. */
6361 if (GET_CODE (constant) == CONST
6362 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6363 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6364 {
6365 gcc_assert (!pending_ltrel);
6366 pending_ltrel = pool_ref;
6367 }
6368 }
6369 }
6370
6371 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6372 {
6373 if (curr_pool)
6374 s390_add_pool_insn (curr_pool, insn);
6375 /* An LTREL_BASE must follow within the same basic block. */
6376 gcc_assert (!pending_ltrel);
6377 }
6378
6379 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6380 section_switch_p = true;
6381
6382 if (!curr_pool
6383 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6384 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6385 continue;
6386
6387 if (TARGET_CPU_ZARCH)
6388 {
6389 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6390 continue;
6391
6392 s390_end_pool (curr_pool, NULL_RTX);
6393 curr_pool = NULL;
6394 }
6395 else
6396 {
6397 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6398 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6399 + extra_size;
6400
6401 /* We will later have to insert base register reload insns.
6402 Those will have an effect on code size, which we need to
6403 consider here. This calculation makes rather pessimistic
6404 worst-case assumptions. */
6405 if (GET_CODE (insn) == CODE_LABEL)
6406 extra_size += 6;
6407
6408 if (chunk_size < S390_POOL_CHUNK_MIN
6409 && curr_pool->size < S390_POOL_CHUNK_MIN
6410 && !section_switch_p)
6411 continue;
6412
6413 /* Pool chunks can only be inserted after BARRIERs ... */
6414 if (GET_CODE (insn) == BARRIER)
6415 {
6416 s390_end_pool (curr_pool, insn);
6417 curr_pool = NULL;
6418 extra_size = 0;
6419 }
6420
6421 /* ... so if we don't find one in time, create one. */
6422 else if (chunk_size > S390_POOL_CHUNK_MAX
6423 || curr_pool->size > S390_POOL_CHUNK_MAX
6424 || section_switch_p)
6425 {
6426 rtx label, jump, barrier;
6427
6428 if (!section_switch_p)
6429 {
6430 /* We can insert the barrier only after a 'real' insn. */
6431 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6432 continue;
6433 if (get_attr_length (insn) == 0)
6434 continue;
6435 /* Don't separate LTREL_BASE from the corresponding
6436 LTREL_OFFSET load. */
6437 if (pending_ltrel)
6438 continue;
6439 }
6440 else
6441 {
6442 gcc_assert (!pending_ltrel);
6443
6444 /* The old pool has to end before the section switch
6445 note in order to make it part of the current
6446 section. */
6447 insn = PREV_INSN (insn);
6448 }
6449
6450 label = gen_label_rtx ();
6451 jump = emit_jump_insn_after (gen_jump (label), insn);
6452 barrier = emit_barrier_after (jump);
6453 insn = emit_label_after (label, barrier);
6454 JUMP_LABEL (jump) = label;
6455 LABEL_NUSES (label) = 1;
6456
6457 INSN_ADDRESSES_NEW (jump, -1);
6458 INSN_ADDRESSES_NEW (barrier, -1);
6459 INSN_ADDRESSES_NEW (insn, -1);
6460
6461 s390_end_pool (curr_pool, barrier);
6462 curr_pool = NULL;
6463 extra_size = 0;
6464 }
6465 }
6466 }
6467
6468 if (curr_pool)
6469 s390_end_pool (curr_pool, NULL_RTX);
6470 gcc_assert (!pending_ltrel);
6471
6472 /* Find all labels that are branched into
6473 from an insn belonging to a different chunk. */
6474
6475 far_labels = BITMAP_ALLOC (NULL);
6476
6477 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6478 {
6479 /* Labels marked with LABEL_PRESERVE_P can be target
6480 of non-local jumps, so we have to mark them.
6481 The same holds for named labels.
6482
6483 Don't do that, however, if it is the label before
6484 a jump table. */
6485
6486 if (GET_CODE (insn) == CODE_LABEL
6487 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6488 {
6489 rtx vec_insn = next_real_insn (insn);
6490 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6491 PATTERN (vec_insn) : NULL_RTX;
6492 if (!vec_pat
6493 || !(GET_CODE (vec_pat) == ADDR_VEC
6494 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6495 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6496 }
6497
6498 /* If we have a direct jump (conditional or unconditional)
6499 or a casesi jump, check all potential targets. */
6500 else if (GET_CODE (insn) == JUMP_INSN)
6501 {
6502 rtx pat = PATTERN (insn);
6503 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6504 pat = XVECEXP (pat, 0, 0);
6505
6506 if (GET_CODE (pat) == SET)
6507 {
6508 rtx label = JUMP_LABEL (insn);
6509 if (label)
6510 {
6511 if (s390_find_pool (pool_list, label)
6512 != s390_find_pool (pool_list, insn))
6513 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6514 }
6515 }
6516 else if (GET_CODE (pat) == PARALLEL
6517 && XVECLEN (pat, 0) == 2
6518 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6519 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6520 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6521 {
6522 /* Find the jump table used by this casesi jump. */
6523 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6524 rtx vec_insn = next_real_insn (vec_label);
6525 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6526 PATTERN (vec_insn) : NULL_RTX;
6527 if (vec_pat
6528 && (GET_CODE (vec_pat) == ADDR_VEC
6529 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6530 {
6531 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6532
6533 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6534 {
6535 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6536
6537 if (s390_find_pool (pool_list, label)
6538 != s390_find_pool (pool_list, insn))
6539 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6540 }
6541 }
6542 }
6543 }
6544 }
6545
6546 /* Insert base register reload insns before every pool. */
6547
6548 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6549 {
6550 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6551 curr_pool->label);
6552 rtx insn = curr_pool->first_insn;
6553 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6554 }
6555
6556 /* Insert base register reload insns at every far label. */
6557
6558 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6559 if (GET_CODE (insn) == CODE_LABEL
6560 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6561 {
6562 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6563 if (pool)
6564 {
6565 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6566 pool->label);
6567 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6568 }
6569 }
6570
6571
6572 BITMAP_FREE (far_labels);
6573
6574
6575 /* Recompute insn addresses. */
6576
6577 init_insn_lengths ();
6578 shorten_branches (get_insns ());
6579
6580 return pool_list;
6581 }
6582
6583 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6584 After we have decided to use this list, finish implementing
6585 all changes to the current function as required. */
6586
6587 static void
6588 s390_chunkify_finish (struct constant_pool *pool_list)
6589 {
6590 struct constant_pool *curr_pool = NULL;
6591 rtx insn;
6592
6593
6594 /* Replace all literal pool references. */
6595
6596 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6597 {
6598 if (INSN_P (insn))
6599 replace_ltrel_base (&PATTERN (insn));
6600
6601 curr_pool = s390_find_pool (pool_list, insn);
6602 if (!curr_pool)
6603 continue;
6604
6605 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6606 {
6607 rtx addr, pool_ref = NULL_RTX;
6608 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6609 if (pool_ref)
6610 {
6611 if (s390_execute_label (insn))
6612 addr = s390_find_execute (curr_pool, insn);
6613 else
6614 addr = s390_find_constant (curr_pool,
6615 get_pool_constant (pool_ref),
6616 get_pool_mode (pool_ref));
6617
6618 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6619 INSN_CODE (insn) = -1;
6620 }
6621 }
6622 }
6623
6624 /* Dump out all literal pools. */
6625
6626 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6627 s390_dump_pool (curr_pool, 0);
6628
6629 /* Free pool list. */
6630
6631 while (pool_list)
6632 {
6633 struct constant_pool *next = pool_list->next;
6634 s390_free_pool (pool_list);
6635 pool_list = next;
6636 }
6637 }
6638
6639 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6640 We have decided we cannot use this list, so revert all changes
6641 to the current function that were done by s390_chunkify_start. */
6642
6643 static void
6644 s390_chunkify_cancel (struct constant_pool *pool_list)
6645 {
6646 struct constant_pool *curr_pool = NULL;
6647 rtx insn;
6648
6649 /* Remove all pool placeholder insns. */
6650
6651 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6652 {
6653 /* Did we insert an extra barrier? Remove it. */
6654 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6655 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6656 rtx label = NEXT_INSN (curr_pool->pool_insn);
6657
6658 if (jump && GET_CODE (jump) == JUMP_INSN
6659 && barrier && GET_CODE (barrier) == BARRIER
6660 && label && GET_CODE (label) == CODE_LABEL
6661 && GET_CODE (PATTERN (jump)) == SET
6662 && SET_DEST (PATTERN (jump)) == pc_rtx
6663 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6664 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6665 {
6666 remove_insn (jump);
6667 remove_insn (barrier);
6668 remove_insn (label);
6669 }
6670
6671 remove_insn (curr_pool->pool_insn);
6672 }
6673
6674 /* Remove all base register reload insns. */
6675
6676 for (insn = get_insns (); insn; )
6677 {
6678 rtx next_insn = NEXT_INSN (insn);
6679
6680 if (GET_CODE (insn) == INSN
6681 && GET_CODE (PATTERN (insn)) == SET
6682 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6683 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6684 remove_insn (insn);
6685
6686 insn = next_insn;
6687 }
6688
6689 /* Free pool list. */
6690
6691 while (pool_list)
6692 {
6693 struct constant_pool *next = pool_list->next;
6694 s390_free_pool (pool_list);
6695 pool_list = next;
6696 }
6697 }
6698
6699 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6700
6701 void
6702 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6703 {
6704 REAL_VALUE_TYPE r;
6705
6706 switch (GET_MODE_CLASS (mode))
6707 {
6708 case MODE_FLOAT:
6709 case MODE_DECIMAL_FLOAT:
6710 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6711
6712 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6713 assemble_real (r, mode, align);
6714 break;
6715
6716 case MODE_INT:
6717 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6718 mark_symbol_refs_as_used (exp);
6719 break;
6720
6721 default:
6722 gcc_unreachable ();
6723 }
6724 }
6725
6726
6727 /* Return an RTL expression representing the value of the return address
6728 for the frame COUNT steps up from the current frame. FRAME is the
6729 frame pointer of that frame. */
6730
6731 rtx
6732 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6733 {
6734 int offset;
6735 rtx addr;
6736
6737 /* Without backchain, we fail for all but the current frame. */
6738
6739 if (!TARGET_BACKCHAIN && count > 0)
6740 return NULL_RTX;
6741
6742 /* For the current frame, we need to make sure the initial
6743 value of RETURN_REGNUM is actually saved. */
6744
6745 if (count == 0)
6746 {
6747 /* On non-z architectures branch splitting could overwrite r14. */
6748 if (TARGET_CPU_ZARCH)
6749 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6750 else
6751 {
6752 cfun_frame_layout.save_return_addr_p = true;
6753 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6754 }
6755 }
6756
6757 if (TARGET_PACKED_STACK)
6758 offset = -2 * UNITS_PER_WORD;
6759 else
6760 offset = RETURN_REGNUM * UNITS_PER_WORD;
6761
6762 addr = plus_constant (frame, offset);
6763 addr = memory_address (Pmode, addr);
6764 return gen_rtx_MEM (Pmode, addr);
6765 }
6766
6767 /* Return an RTL expression representing the back chain stored in
6768 the current stack frame. */
6769
6770 rtx
6771 s390_back_chain_rtx (void)
6772 {
6773 rtx chain;
6774
6775 gcc_assert (TARGET_BACKCHAIN);
6776
6777 if (TARGET_PACKED_STACK)
6778 chain = plus_constant (stack_pointer_rtx,
6779 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6780 else
6781 chain = stack_pointer_rtx;
6782
6783 chain = gen_rtx_MEM (Pmode, chain);
6784 return chain;
6785 }
6786
6787 /* Find first call clobbered register unused in a function.
6788 This could be used as base register in a leaf function
6789 or for holding the return address before epilogue. */
6790
6791 static int
6792 find_unused_clobbered_reg (void)
6793 {
6794 int i;
6795 for (i = 0; i < 6; i++)
6796 if (!df_regs_ever_live_p (i))
6797 return i;
6798 return 0;
6799 }
6800
6801
6802 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6803 clobbered hard regs in SETREG. */
6804
6805 static void
6806 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6807 {
6808 int *regs_ever_clobbered = (int *)data;
6809 unsigned int i, regno;
6810 enum machine_mode mode = GET_MODE (setreg);
6811
6812 if (GET_CODE (setreg) == SUBREG)
6813 {
6814 rtx inner = SUBREG_REG (setreg);
6815 if (!GENERAL_REG_P (inner))
6816 return;
6817 regno = subreg_regno (setreg);
6818 }
6819 else if (GENERAL_REG_P (setreg))
6820 regno = REGNO (setreg);
6821 else
6822 return;
6823
6824 for (i = regno;
6825 i < regno + HARD_REGNO_NREGS (regno, mode);
6826 i++)
6827 regs_ever_clobbered[i] = 1;
6828 }
6829
6830 /* Walks through all basic blocks of the current function looking
6831 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6832 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6833 each of those regs. */
6834
6835 static void
6836 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6837 {
6838 basic_block cur_bb;
6839 rtx cur_insn;
6840 unsigned int i;
6841
6842 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6843
6844 /* For non-leaf functions we have to consider all call clobbered regs to be
6845 clobbered. */
6846 if (!current_function_is_leaf)
6847 {
6848 for (i = 0; i < 16; i++)
6849 regs_ever_clobbered[i] = call_really_used_regs[i];
6850 }
6851
6852 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6853 this work is done by liveness analysis (mark_regs_live_at_end).
6854 Special care is needed for functions containing landing pads. Landing pads
6855 may use the eh registers, but the code which sets these registers is not
6856 contained in that function. Hence s390_regs_ever_clobbered is not able to
6857 deal with this automatically. */
6858 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6859 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6860 if (crtl->calls_eh_return
6861 || (cfun->machine->has_landing_pad_p
6862 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6863 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6864
6865 /* For nonlocal gotos all call-saved registers have to be saved.
6866 This flag is also set for the unwinding code in libgcc.
6867 See expand_builtin_unwind_init. For regs_ever_live this is done by
6868 reload. */
6869 if (cfun->has_nonlocal_label)
6870 for (i = 0; i < 16; i++)
6871 if (!call_really_used_regs[i])
6872 regs_ever_clobbered[i] = 1;
6873
6874 FOR_EACH_BB (cur_bb)
6875 {
6876 FOR_BB_INSNS (cur_bb, cur_insn)
6877 {
6878 if (INSN_P (cur_insn))
6879 note_stores (PATTERN (cur_insn),
6880 s390_reg_clobbered_rtx,
6881 regs_ever_clobbered);
6882 }
6883 }
6884 }
6885
6886 /* Determine the frame area which actually has to be accessed
6887 in the function epilogue. The values are stored at the
6888 given pointers AREA_BOTTOM (address of the lowest used stack
6889 address) and AREA_TOP (address of the first item which does
6890 not belong to the stack frame). */
6891
6892 static void
6893 s390_frame_area (int *area_bottom, int *area_top)
6894 {
6895 int b, t;
6896 int i;
6897
6898 b = INT_MAX;
6899 t = INT_MIN;
6900
6901 if (cfun_frame_layout.first_restore_gpr != -1)
6902 {
6903 b = (cfun_frame_layout.gprs_offset
6904 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6905 t = b + (cfun_frame_layout.last_restore_gpr
6906 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6907 }
6908
6909 if (TARGET_64BIT && cfun_save_high_fprs_p)
6910 {
6911 b = MIN (b, cfun_frame_layout.f8_offset);
6912 t = MAX (t, (cfun_frame_layout.f8_offset
6913 + cfun_frame_layout.high_fprs * 8));
6914 }
6915
6916 if (!TARGET_64BIT)
6917 for (i = 2; i < 4; i++)
6918 if (cfun_fpr_bit_p (i))
6919 {
6920 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6921 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6922 }
6923
6924 *area_bottom = b;
6925 *area_top = t;
6926 }
6927
6928 /* Fill cfun->machine with info about register usage of current function.
6929 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6930
6931 static void
6932 s390_register_info (int clobbered_regs[])
6933 {
6934 int i, j;
6935
6936 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6937 cfun_frame_layout.fpr_bitmap = 0;
6938 cfun_frame_layout.high_fprs = 0;
6939 if (TARGET_64BIT)
6940 for (i = 24; i < 32; i++)
6941 if (df_regs_ever_live_p (i) && !global_regs[i])
6942 {
6943 cfun_set_fpr_bit (i - 16);
6944 cfun_frame_layout.high_fprs++;
6945 }
6946
6947 /* Find first and last gpr to be saved. We trust regs_ever_live
6948 data, except that we don't save and restore global registers.
6949
6950 Also, all registers with special meaning to the compiler need
6951 to be handled extra. */
6952
6953 s390_regs_ever_clobbered (clobbered_regs);
6954
6955 for (i = 0; i < 16; i++)
6956 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6957
6958 if (frame_pointer_needed)
6959 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6960
6961 if (flag_pic)
6962 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6963 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6964
6965 clobbered_regs[BASE_REGNUM]
6966 |= (cfun->machine->base_reg
6967 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6968
6969 clobbered_regs[RETURN_REGNUM]
6970 |= (!current_function_is_leaf
6971 || TARGET_TPF_PROFILING
6972 || cfun->machine->split_branches_pending_p
6973 || cfun_frame_layout.save_return_addr_p
6974 || crtl->calls_eh_return
6975 || cfun->stdarg);
6976
6977 clobbered_regs[STACK_POINTER_REGNUM]
6978 |= (!current_function_is_leaf
6979 || TARGET_TPF_PROFILING
6980 || cfun_save_high_fprs_p
6981 || get_frame_size () > 0
6982 || cfun->calls_alloca
6983 || cfun->stdarg);
6984
6985 for (i = 6; i < 16; i++)
6986 if (df_regs_ever_live_p (i) || clobbered_regs[i])
6987 break;
6988 for (j = 15; j > i; j--)
6989 if (df_regs_ever_live_p (j) || clobbered_regs[j])
6990 break;
6991
6992 if (i == 16)
6993 {
6994 /* Nothing to save/restore. */
6995 cfun_frame_layout.first_save_gpr_slot = -1;
6996 cfun_frame_layout.last_save_gpr_slot = -1;
6997 cfun_frame_layout.first_save_gpr = -1;
6998 cfun_frame_layout.first_restore_gpr = -1;
6999 cfun_frame_layout.last_save_gpr = -1;
7000 cfun_frame_layout.last_restore_gpr = -1;
7001 }
7002 else
7003 {
7004 /* Save slots for gprs from i to j. */
7005 cfun_frame_layout.first_save_gpr_slot = i;
7006 cfun_frame_layout.last_save_gpr_slot = j;
7007
7008 for (i = cfun_frame_layout.first_save_gpr_slot;
7009 i < cfun_frame_layout.last_save_gpr_slot + 1;
7010 i++)
7011 if (clobbered_regs[i])
7012 break;
7013
7014 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7015 if (clobbered_regs[j])
7016 break;
7017
7018 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7019 {
7020 /* Nothing to save/restore. */
7021 cfun_frame_layout.first_save_gpr = -1;
7022 cfun_frame_layout.first_restore_gpr = -1;
7023 cfun_frame_layout.last_save_gpr = -1;
7024 cfun_frame_layout.last_restore_gpr = -1;
7025 }
7026 else
7027 {
7028 /* Save / Restore from gpr i to j. */
7029 cfun_frame_layout.first_save_gpr = i;
7030 cfun_frame_layout.first_restore_gpr = i;
7031 cfun_frame_layout.last_save_gpr = j;
7032 cfun_frame_layout.last_restore_gpr = j;
7033 }
7034 }
7035
7036 if (cfun->stdarg)
7037 {
7038 /* Varargs functions need to save gprs 2 to 6. */
7039 if (cfun->va_list_gpr_size
7040 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7041 {
7042 int min_gpr = crtl->args.info.gprs;
7043 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7044 if (max_gpr > GP_ARG_NUM_REG)
7045 max_gpr = GP_ARG_NUM_REG;
7046
7047 if (cfun_frame_layout.first_save_gpr == -1
7048 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7049 {
7050 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7051 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7052 }
7053
7054 if (cfun_frame_layout.last_save_gpr == -1
7055 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7056 {
7057 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7058 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7059 }
7060 }
7061
7062 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7063 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7064 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7065 {
7066 int min_fpr = crtl->args.info.fprs;
7067 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7068 if (max_fpr > FP_ARG_NUM_REG)
7069 max_fpr = FP_ARG_NUM_REG;
7070
7071 /* ??? This is currently required to ensure proper location
7072 of the fpr save slots within the va_list save area. */
7073 if (TARGET_PACKED_STACK)
7074 min_fpr = 0;
7075
7076 for (i = min_fpr; i < max_fpr; i++)
7077 cfun_set_fpr_bit (i);
7078 }
7079 }
7080
7081 if (!TARGET_64BIT)
7082 for (i = 2; i < 4; i++)
7083 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7084 cfun_set_fpr_bit (i);
7085 }
7086
7087 /* Fill cfun->machine with info about frame of current function. */
7088
7089 static void
7090 s390_frame_info (void)
7091 {
7092 int i;
7093
7094 cfun_frame_layout.frame_size = get_frame_size ();
7095 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7096 fatal_error ("total size of local variables exceeds architecture limit");
7097
7098 if (!TARGET_PACKED_STACK)
7099 {
7100 cfun_frame_layout.backchain_offset = 0;
7101 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
7102 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7103 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7104 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7105 * UNITS_PER_WORD);
7106 }
7107 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7108 {
7109 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7110 - UNITS_PER_WORD);
7111 cfun_frame_layout.gprs_offset
7112 = (cfun_frame_layout.backchain_offset
7113 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7114 * UNITS_PER_WORD);
7115
7116 if (TARGET_64BIT)
7117 {
7118 cfun_frame_layout.f4_offset
7119 = (cfun_frame_layout.gprs_offset
7120 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7121
7122 cfun_frame_layout.f0_offset
7123 = (cfun_frame_layout.f4_offset
7124 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7125 }
7126 else
7127 {
7128 /* On 31 bit we have to care about alignment of the
7129 floating point regs to provide fastest access. */
7130 cfun_frame_layout.f0_offset
7131 = ((cfun_frame_layout.gprs_offset
7132 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7133 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7134
7135 cfun_frame_layout.f4_offset
7136 = (cfun_frame_layout.f0_offset
7137 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7138 }
7139 }
7140 else /* no backchain */
7141 {
7142 cfun_frame_layout.f4_offset
7143 = (STACK_POINTER_OFFSET
7144 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7145
7146 cfun_frame_layout.f0_offset
7147 = (cfun_frame_layout.f4_offset
7148 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7149
7150 cfun_frame_layout.gprs_offset
7151 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7152 }
7153
7154 if (current_function_is_leaf
7155 && !TARGET_TPF_PROFILING
7156 && cfun_frame_layout.frame_size == 0
7157 && !cfun_save_high_fprs_p
7158 && !cfun->calls_alloca
7159 && !cfun->stdarg)
7160 return;
7161
7162 if (!TARGET_PACKED_STACK)
7163 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7164 + crtl->outgoing_args_size
7165 + cfun_frame_layout.high_fprs * 8);
7166 else
7167 {
7168 if (TARGET_BACKCHAIN)
7169 cfun_frame_layout.frame_size += UNITS_PER_WORD;
7170
7171 /* No alignment trouble here because f8-f15 are only saved under
7172 64 bit. */
7173 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7174 cfun_frame_layout.f4_offset),
7175 cfun_frame_layout.gprs_offset)
7176 - cfun_frame_layout.high_fprs * 8);
7177
7178 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7179
7180 for (i = 0; i < 8; i++)
7181 if (cfun_fpr_bit_p (i))
7182 cfun_frame_layout.frame_size += 8;
7183
7184 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7185
7186 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7187 the frame size to sustain 8 byte alignment of stack frames. */
7188 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7189 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7190 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7191
7192 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7193 }
7194 }
7195
7196 /* Generate frame layout. Fills in register and frame data for the current
7197 function in cfun->machine. This routine can be called multiple times;
7198 it will re-do the complete frame layout every time. */
7199
7200 static void
7201 s390_init_frame_layout (void)
7202 {
7203 HOST_WIDE_INT frame_size;
7204 int base_used;
7205 int clobbered_regs[16];
7206
7207 /* On S/390 machines, we may need to perform branch splitting, which
7208 will require both base and return address register. We have no
7209 choice but to assume we're going to need them until right at the
7210 end of the machine dependent reorg phase. */
7211 if (!TARGET_CPU_ZARCH)
7212 cfun->machine->split_branches_pending_p = true;
7213
7214 do
7215 {
7216 frame_size = cfun_frame_layout.frame_size;
7217
7218 /* Try to predict whether we'll need the base register. */
7219 base_used = cfun->machine->split_branches_pending_p
7220 || crtl->uses_const_pool
7221 || (!DISP_IN_RANGE (frame_size)
7222 && !CONST_OK_FOR_K (frame_size));
7223
7224 /* Decide which register to use as literal pool base. In small
7225 leaf functions, try to use an unused call-clobbered register
7226 as base register to avoid save/restore overhead. */
7227 if (!base_used)
7228 cfun->machine->base_reg = NULL_RTX;
7229 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7230 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7231 else
7232 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7233
7234 s390_register_info (clobbered_regs);
7235 s390_frame_info ();
7236 }
7237 while (frame_size != cfun_frame_layout.frame_size);
7238 }
7239
7240 /* Update frame layout. Recompute actual register save data based on
7241 current info and update regs_ever_live for the special registers.
7242 May be called multiple times, but may never cause *more* registers
7243 to be saved than s390_init_frame_layout allocated room for. */
7244
7245 static void
7246 s390_update_frame_layout (void)
7247 {
7248 int clobbered_regs[16];
7249
7250 s390_register_info (clobbered_regs);
7251
7252 df_set_regs_ever_live (BASE_REGNUM,
7253 clobbered_regs[BASE_REGNUM] ? true : false);
7254 df_set_regs_ever_live (RETURN_REGNUM,
7255 clobbered_regs[RETURN_REGNUM] ? true : false);
7256 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7257 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7258
7259 if (cfun->machine->base_reg)
7260 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7261 }
7262
7263 /* Return true if it is legal to put a value with MODE into REGNO. */
7264
7265 bool
7266 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7267 {
7268 switch (REGNO_REG_CLASS (regno))
7269 {
7270 case FP_REGS:
7271 if (REGNO_PAIR_OK (regno, mode))
7272 {
7273 if (mode == SImode || mode == DImode)
7274 return true;
7275
7276 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7277 return true;
7278 }
7279 break;
7280 case ADDR_REGS:
7281 if (FRAME_REGNO_P (regno) && mode == Pmode)
7282 return true;
7283
7284 /* fallthrough */
7285 case GENERAL_REGS:
7286 if (REGNO_PAIR_OK (regno, mode))
7287 {
7288 if (TARGET_64BIT
7289 || (mode != TFmode && mode != TCmode && mode != TDmode))
7290 return true;
7291 }
7292 break;
7293 case CC_REGS:
7294 if (GET_MODE_CLASS (mode) == MODE_CC)
7295 return true;
7296 break;
7297 case ACCESS_REGS:
7298 if (REGNO_PAIR_OK (regno, mode))
7299 {
7300 if (mode == SImode || mode == Pmode)
7301 return true;
7302 }
7303 break;
7304 default:
7305 return false;
7306 }
7307
7308 return false;
7309 }
7310
7311 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7312
7313 bool
7314 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7315 {
7316 /* Once we've decided upon a register to use as base register, it must
7317 no longer be used for any other purpose. */
7318 if (cfun->machine->base_reg)
7319 if (REGNO (cfun->machine->base_reg) == old_reg
7320 || REGNO (cfun->machine->base_reg) == new_reg)
7321 return false;
7322
7323 return true;
7324 }
7325
7326 /* Maximum number of registers to represent a value of mode MODE
7327 in a register of class RCLASS. */
7328
7329 bool
7330 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7331 {
7332 switch (rclass)
7333 {
7334 case FP_REGS:
7335 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7336 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7337 else
7338 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7339 case ACCESS_REGS:
7340 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7341 default:
7342 break;
7343 }
7344 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7345 }
7346
7347 /* Return true if register FROM can be eliminated via register TO. */
7348
7349 static bool
7350 s390_can_eliminate (const int from, const int to)
7351 {
7352 /* On zSeries machines, we have not marked the base register as fixed.
7353 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7354 If a function requires the base register, we say here that this
7355 elimination cannot be performed. This will cause reload to free
7356 up the base register (as if it were fixed). On the other hand,
7357 if the current function does *not* require the base register, we
7358 say here the elimination succeeds, which in turn allows reload
7359 to allocate the base register for any other purpose. */
7360 if (from == BASE_REGNUM && to == BASE_REGNUM)
7361 {
7362 if (TARGET_CPU_ZARCH)
7363 {
7364 s390_init_frame_layout ();
7365 return cfun->machine->base_reg == NULL_RTX;
7366 }
7367
7368 return false;
7369 }
7370
7371 /* Everything else must point into the stack frame. */
7372 gcc_assert (to == STACK_POINTER_REGNUM
7373 || to == HARD_FRAME_POINTER_REGNUM);
7374
7375 gcc_assert (from == FRAME_POINTER_REGNUM
7376 || from == ARG_POINTER_REGNUM
7377 || from == RETURN_ADDRESS_POINTER_REGNUM);
7378
7379 /* Make sure we actually saved the return address. */
7380 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7381 if (!crtl->calls_eh_return
7382 && !cfun->stdarg
7383 && !cfun_frame_layout.save_return_addr_p)
7384 return false;
7385
7386 return true;
7387 }
7388
7389 /* Return offset between register FROM and TO initially after prolog. */
7390
7391 HOST_WIDE_INT
7392 s390_initial_elimination_offset (int from, int to)
7393 {
7394 HOST_WIDE_INT offset;
7395 int index;
7396
7397 /* ??? Why are we called for non-eliminable pairs? */
7398 if (!s390_can_eliminate (from, to))
7399 return 0;
7400
7401 switch (from)
7402 {
7403 case FRAME_POINTER_REGNUM:
7404 offset = (get_frame_size()
7405 + STACK_POINTER_OFFSET
7406 + crtl->outgoing_args_size);
7407 break;
7408
7409 case ARG_POINTER_REGNUM:
7410 s390_init_frame_layout ();
7411 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7412 break;
7413
7414 case RETURN_ADDRESS_POINTER_REGNUM:
7415 s390_init_frame_layout ();
7416 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7417 gcc_assert (index >= 0);
7418 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7419 offset += index * UNITS_PER_WORD;
7420 break;
7421
7422 case BASE_REGNUM:
7423 offset = 0;
7424 break;
7425
7426 default:
7427 gcc_unreachable ();
7428 }
7429
7430 return offset;
7431 }
7432
7433 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7434 to register BASE. Return generated insn. */
7435
7436 static rtx
7437 save_fpr (rtx base, int offset, int regnum)
7438 {
7439 rtx addr;
7440 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7441
7442 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7443 set_mem_alias_set (addr, get_varargs_alias_set ());
7444 else
7445 set_mem_alias_set (addr, get_frame_alias_set ());
7446
7447 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7448 }
7449
7450 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7451 to register BASE. Return generated insn. */
7452
7453 static rtx
7454 restore_fpr (rtx base, int offset, int regnum)
7455 {
7456 rtx addr;
7457 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7458 set_mem_alias_set (addr, get_frame_alias_set ());
7459
7460 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7461 }
7462
7463 /* Return true if REGNO is a global register, but not one
7464 of the special ones that need to be saved/restored in anyway. */
7465
7466 static inline bool
7467 global_not_special_regno_p (int regno)
7468 {
7469 return (global_regs[regno]
7470 /* These registers are special and need to be
7471 restored in any case. */
7472 && !(regno == STACK_POINTER_REGNUM
7473 || regno == RETURN_REGNUM
7474 || regno == BASE_REGNUM
7475 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7476 }
7477
7478 /* Generate insn to save registers FIRST to LAST into
7479 the register save area located at offset OFFSET
7480 relative to register BASE. */
7481
7482 static rtx
7483 save_gprs (rtx base, int offset, int first, int last)
7484 {
7485 rtx addr, insn, note;
7486 int i;
7487
7488 addr = plus_constant (base, offset);
7489 addr = gen_rtx_MEM (Pmode, addr);
7490
7491 set_mem_alias_set (addr, get_frame_alias_set ());
7492
7493 /* Special-case single register. */
7494 if (first == last)
7495 {
7496 if (TARGET_64BIT)
7497 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7498 else
7499 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7500
7501 if (!global_not_special_regno_p (first))
7502 RTX_FRAME_RELATED_P (insn) = 1;
7503 return insn;
7504 }
7505
7506
7507 insn = gen_store_multiple (addr,
7508 gen_rtx_REG (Pmode, first),
7509 GEN_INT (last - first + 1));
7510
7511 if (first <= 6 && cfun->stdarg)
7512 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7513 {
7514 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7515
7516 if (first + i <= 6)
7517 set_mem_alias_set (mem, get_varargs_alias_set ());
7518 }
7519
7520 /* We need to set the FRAME_RELATED flag on all SETs
7521 inside the store-multiple pattern.
7522
7523 However, we must not emit DWARF records for registers 2..5
7524 if they are stored for use by variable arguments ...
7525
7526 ??? Unfortunately, it is not enough to simply not the
7527 FRAME_RELATED flags for those SETs, because the first SET
7528 of the PARALLEL is always treated as if it had the flag
7529 set, even if it does not. Therefore we emit a new pattern
7530 without those registers as REG_FRAME_RELATED_EXPR note. */
7531
7532 if (first >= 6 && !global_not_special_regno_p (first))
7533 {
7534 rtx pat = PATTERN (insn);
7535
7536 for (i = 0; i < XVECLEN (pat, 0); i++)
7537 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7538 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7539 0, i)))))
7540 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7541
7542 RTX_FRAME_RELATED_P (insn) = 1;
7543 }
7544 else if (last >= 6)
7545 {
7546 int start;
7547
7548 for (start = first >= 6 ? first : 6; start <= last; start++)
7549 if (!global_not_special_regno_p (start))
7550 break;
7551
7552 if (start > last)
7553 return insn;
7554
7555 addr = plus_constant (base, offset + (start - first) * UNITS_PER_WORD);
7556 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7557 gen_rtx_REG (Pmode, start),
7558 GEN_INT (last - start + 1));
7559 note = PATTERN (note);
7560
7561 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7562
7563 for (i = 0; i < XVECLEN (note, 0); i++)
7564 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7565 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7566 0, i)))))
7567 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7568
7569 RTX_FRAME_RELATED_P (insn) = 1;
7570 }
7571
7572 return insn;
7573 }
7574
7575 /* Generate insn to restore registers FIRST to LAST from
7576 the register save area located at offset OFFSET
7577 relative to register BASE. */
7578
7579 static rtx
7580 restore_gprs (rtx base, int offset, int first, int last)
7581 {
7582 rtx addr, insn;
7583
7584 addr = plus_constant (base, offset);
7585 addr = gen_rtx_MEM (Pmode, addr);
7586 set_mem_alias_set (addr, get_frame_alias_set ());
7587
7588 /* Special-case single register. */
7589 if (first == last)
7590 {
7591 if (TARGET_64BIT)
7592 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7593 else
7594 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7595
7596 return insn;
7597 }
7598
7599 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7600 addr,
7601 GEN_INT (last - first + 1));
7602 return insn;
7603 }
7604
7605 /* Return insn sequence to load the GOT register. */
7606
7607 static GTY(()) rtx got_symbol;
7608 rtx
7609 s390_load_got (void)
7610 {
7611 rtx insns;
7612
7613 if (!got_symbol)
7614 {
7615 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7616 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7617 }
7618
7619 start_sequence ();
7620
7621 if (TARGET_CPU_ZARCH)
7622 {
7623 emit_move_insn (pic_offset_table_rtx, got_symbol);
7624 }
7625 else
7626 {
7627 rtx offset;
7628
7629 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7630 UNSPEC_LTREL_OFFSET);
7631 offset = gen_rtx_CONST (Pmode, offset);
7632 offset = force_const_mem (Pmode, offset);
7633
7634 emit_move_insn (pic_offset_table_rtx, offset);
7635
7636 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7637 UNSPEC_LTREL_BASE);
7638 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7639
7640 emit_move_insn (pic_offset_table_rtx, offset);
7641 }
7642
7643 insns = get_insns ();
7644 end_sequence ();
7645 return insns;
7646 }
7647
7648 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7649 and the change to the stack pointer. */
7650
7651 static void
7652 s390_emit_stack_tie (void)
7653 {
7654 rtx mem = gen_frame_mem (BLKmode,
7655 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7656
7657 emit_insn (gen_stack_tie (mem));
7658 }
7659
7660 /* Expand the prologue into a bunch of separate insns. */
7661
7662 void
7663 s390_emit_prologue (void)
7664 {
7665 rtx insn, addr;
7666 rtx temp_reg;
7667 int i;
7668 int offset;
7669 int next_fpr = 0;
7670
7671 /* Complete frame layout. */
7672
7673 s390_update_frame_layout ();
7674
7675 /* Annotate all constant pool references to let the scheduler know
7676 they implicitly use the base register. */
7677
7678 push_topmost_sequence ();
7679
7680 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7681 if (INSN_P (insn))
7682 {
7683 annotate_constant_pool_refs (&PATTERN (insn));
7684 df_insn_rescan (insn);
7685 }
7686
7687 pop_topmost_sequence ();
7688
7689 /* Choose best register to use for temp use within prologue.
7690 See below for why TPF must use the register 1. */
7691
7692 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7693 && !current_function_is_leaf
7694 && !TARGET_TPF_PROFILING)
7695 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7696 else
7697 temp_reg = gen_rtx_REG (Pmode, 1);
7698
7699 /* Save call saved gprs. */
7700 if (cfun_frame_layout.first_save_gpr != -1)
7701 {
7702 insn = save_gprs (stack_pointer_rtx,
7703 cfun_frame_layout.gprs_offset +
7704 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7705 - cfun_frame_layout.first_save_gpr_slot),
7706 cfun_frame_layout.first_save_gpr,
7707 cfun_frame_layout.last_save_gpr);
7708 emit_insn (insn);
7709 }
7710
7711 /* Dummy insn to mark literal pool slot. */
7712
7713 if (cfun->machine->base_reg)
7714 emit_insn (gen_main_pool (cfun->machine->base_reg));
7715
7716 offset = cfun_frame_layout.f0_offset;
7717
7718 /* Save f0 and f2. */
7719 for (i = 0; i < 2; i++)
7720 {
7721 if (cfun_fpr_bit_p (i))
7722 {
7723 save_fpr (stack_pointer_rtx, offset, i + 16);
7724 offset += 8;
7725 }
7726 else if (!TARGET_PACKED_STACK)
7727 offset += 8;
7728 }
7729
7730 /* Save f4 and f6. */
7731 offset = cfun_frame_layout.f4_offset;
7732 for (i = 2; i < 4; i++)
7733 {
7734 if (cfun_fpr_bit_p (i))
7735 {
7736 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7737 offset += 8;
7738
7739 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7740 therefore are not frame related. */
7741 if (!call_really_used_regs[i + 16])
7742 RTX_FRAME_RELATED_P (insn) = 1;
7743 }
7744 else if (!TARGET_PACKED_STACK)
7745 offset += 8;
7746 }
7747
7748 if (TARGET_PACKED_STACK
7749 && cfun_save_high_fprs_p
7750 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7751 {
7752 offset = (cfun_frame_layout.f8_offset
7753 + (cfun_frame_layout.high_fprs - 1) * 8);
7754
7755 for (i = 15; i > 7 && offset >= 0; i--)
7756 if (cfun_fpr_bit_p (i))
7757 {
7758 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7759
7760 RTX_FRAME_RELATED_P (insn) = 1;
7761 offset -= 8;
7762 }
7763 if (offset >= cfun_frame_layout.f8_offset)
7764 next_fpr = i + 16;
7765 }
7766
7767 if (!TARGET_PACKED_STACK)
7768 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7769
7770 /* Decrement stack pointer. */
7771
7772 if (cfun_frame_layout.frame_size > 0)
7773 {
7774 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7775 rtx real_frame_off;
7776
7777 if (s390_stack_size)
7778 {
7779 HOST_WIDE_INT stack_guard;
7780
7781 if (s390_stack_guard)
7782 stack_guard = s390_stack_guard;
7783 else
7784 {
7785 /* If no value for stack guard is provided the smallest power of 2
7786 larger than the current frame size is chosen. */
7787 stack_guard = 1;
7788 while (stack_guard < cfun_frame_layout.frame_size)
7789 stack_guard <<= 1;
7790 }
7791
7792 if (cfun_frame_layout.frame_size >= s390_stack_size)
7793 {
7794 warning (0, "frame size of function %qs is "
7795 HOST_WIDE_INT_PRINT_DEC
7796 " bytes exceeding user provided stack limit of "
7797 HOST_WIDE_INT_PRINT_DEC " bytes. "
7798 "An unconditional trap is added.",
7799 current_function_name(), cfun_frame_layout.frame_size,
7800 s390_stack_size);
7801 emit_insn (gen_trap ());
7802 }
7803 else
7804 {
7805 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7806 & ~(stack_guard - 1));
7807 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7808 GEN_INT (stack_check_mask));
7809 if (TARGET_64BIT)
7810 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7811 t, const0_rtx, const0_rtx));
7812 else
7813 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7814 t, const0_rtx, const0_rtx));
7815 }
7816 }
7817
7818 if (s390_warn_framesize > 0
7819 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7820 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7821 current_function_name (), cfun_frame_layout.frame_size);
7822
7823 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7824 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7825
7826 /* Save incoming stack pointer into temp reg. */
7827 if (TARGET_BACKCHAIN || next_fpr)
7828 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7829
7830 /* Subtract frame size from stack pointer. */
7831
7832 if (DISP_IN_RANGE (INTVAL (frame_off)))
7833 {
7834 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7835 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7836 frame_off));
7837 insn = emit_insn (insn);
7838 }
7839 else
7840 {
7841 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7842 frame_off = force_const_mem (Pmode, frame_off);
7843
7844 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7845 annotate_constant_pool_refs (&PATTERN (insn));
7846 }
7847
7848 RTX_FRAME_RELATED_P (insn) = 1;
7849 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7850 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7851 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7852 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7853 real_frame_off)));
7854
7855 /* Set backchain. */
7856
7857 if (TARGET_BACKCHAIN)
7858 {
7859 if (cfun_frame_layout.backchain_offset)
7860 addr = gen_rtx_MEM (Pmode,
7861 plus_constant (stack_pointer_rtx,
7862 cfun_frame_layout.backchain_offset));
7863 else
7864 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7865 set_mem_alias_set (addr, get_frame_alias_set ());
7866 insn = emit_insn (gen_move_insn (addr, temp_reg));
7867 }
7868
7869 /* If we support asynchronous exceptions (e.g. for Java),
7870 we need to make sure the backchain pointer is set up
7871 before any possibly trapping memory access. */
7872
7873 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7874 {
7875 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7876 emit_clobber (addr);
7877 }
7878 }
7879
7880 /* Save fprs 8 - 15 (64 bit ABI). */
7881
7882 if (cfun_save_high_fprs_p && next_fpr)
7883 {
7884 /* If the stack might be accessed through a different register
7885 we have to make sure that the stack pointer decrement is not
7886 moved below the use of the stack slots. */
7887 s390_emit_stack_tie ();
7888
7889 insn = emit_insn (gen_add2_insn (temp_reg,
7890 GEN_INT (cfun_frame_layout.f8_offset)));
7891
7892 offset = 0;
7893
7894 for (i = 24; i <= next_fpr; i++)
7895 if (cfun_fpr_bit_p (i - 16))
7896 {
7897 rtx addr = plus_constant (stack_pointer_rtx,
7898 cfun_frame_layout.frame_size
7899 + cfun_frame_layout.f8_offset
7900 + offset);
7901
7902 insn = save_fpr (temp_reg, offset, i);
7903 offset += 8;
7904 RTX_FRAME_RELATED_P (insn) = 1;
7905 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7906 gen_rtx_SET (VOIDmode,
7907 gen_rtx_MEM (DFmode, addr),
7908 gen_rtx_REG (DFmode, i)));
7909 }
7910 }
7911
7912 /* Set frame pointer, if needed. */
7913
7914 if (frame_pointer_needed)
7915 {
7916 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7917 RTX_FRAME_RELATED_P (insn) = 1;
7918 }
7919
7920 /* Set up got pointer, if needed. */
7921
7922 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7923 {
7924 rtx insns = s390_load_got ();
7925
7926 for (insn = insns; insn; insn = NEXT_INSN (insn))
7927 annotate_constant_pool_refs (&PATTERN (insn));
7928
7929 emit_insn (insns);
7930 }
7931
7932 if (TARGET_TPF_PROFILING)
7933 {
7934 /* Generate a BAS instruction to serve as a function
7935 entry intercept to facilitate the use of tracing
7936 algorithms located at the branch target. */
7937 emit_insn (gen_prologue_tpf ());
7938
7939 /* Emit a blockage here so that all code
7940 lies between the profiling mechanisms. */
7941 emit_insn (gen_blockage ());
7942 }
7943 }
7944
7945 /* Expand the epilogue into a bunch of separate insns. */
7946
7947 void
7948 s390_emit_epilogue (bool sibcall)
7949 {
7950 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
7951 int area_bottom, area_top, offset = 0;
7952 int next_offset;
7953 rtvec p;
7954 int i;
7955
7956 if (TARGET_TPF_PROFILING)
7957 {
7958
7959 /* Generate a BAS instruction to serve as a function
7960 entry intercept to facilitate the use of tracing
7961 algorithms located at the branch target. */
7962
7963 /* Emit a blockage here so that all code
7964 lies between the profiling mechanisms. */
7965 emit_insn (gen_blockage ());
7966
7967 emit_insn (gen_epilogue_tpf ());
7968 }
7969
7970 /* Check whether to use frame or stack pointer for restore. */
7971
7972 frame_pointer = (frame_pointer_needed
7973 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7974
7975 s390_frame_area (&area_bottom, &area_top);
7976
7977 /* Check whether we can access the register save area.
7978 If not, increment the frame pointer as required. */
7979
7980 if (area_top <= area_bottom)
7981 {
7982 /* Nothing to restore. */
7983 }
7984 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7985 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7986 {
7987 /* Area is in range. */
7988 offset = cfun_frame_layout.frame_size;
7989 }
7990 else
7991 {
7992 rtx insn, frame_off, cfa;
7993
7994 offset = area_bottom < 0 ? -area_bottom : 0;
7995 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7996
7997 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
7998 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7999 if (DISP_IN_RANGE (INTVAL (frame_off)))
8000 {
8001 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8002 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8003 insn = emit_insn (insn);
8004 }
8005 else
8006 {
8007 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8008 frame_off = force_const_mem (Pmode, frame_off);
8009
8010 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8011 annotate_constant_pool_refs (&PATTERN (insn));
8012 }
8013 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8014 RTX_FRAME_RELATED_P (insn) = 1;
8015 }
8016
8017 /* Restore call saved fprs. */
8018
8019 if (TARGET_64BIT)
8020 {
8021 if (cfun_save_high_fprs_p)
8022 {
8023 next_offset = cfun_frame_layout.f8_offset;
8024 for (i = 24; i < 32; i++)
8025 {
8026 if (cfun_fpr_bit_p (i - 16))
8027 {
8028 restore_fpr (frame_pointer,
8029 offset + next_offset, i);
8030 cfa_restores
8031 = alloc_reg_note (REG_CFA_RESTORE,
8032 gen_rtx_REG (DFmode, i), cfa_restores);
8033 next_offset += 8;
8034 }
8035 }
8036 }
8037
8038 }
8039 else
8040 {
8041 next_offset = cfun_frame_layout.f4_offset;
8042 for (i = 18; i < 20; i++)
8043 {
8044 if (cfun_fpr_bit_p (i - 16))
8045 {
8046 restore_fpr (frame_pointer,
8047 offset + next_offset, i);
8048 cfa_restores
8049 = alloc_reg_note (REG_CFA_RESTORE,
8050 gen_rtx_REG (DFmode, i), cfa_restores);
8051 next_offset += 8;
8052 }
8053 else if (!TARGET_PACKED_STACK)
8054 next_offset += 8;
8055 }
8056
8057 }
8058
8059 /* Return register. */
8060
8061 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8062
8063 /* Restore call saved gprs. */
8064
8065 if (cfun_frame_layout.first_restore_gpr != -1)
8066 {
8067 rtx insn, addr;
8068 int i;
8069
8070 /* Check for global register and save them
8071 to stack location from where they get restored. */
8072
8073 for (i = cfun_frame_layout.first_restore_gpr;
8074 i <= cfun_frame_layout.last_restore_gpr;
8075 i++)
8076 {
8077 if (global_not_special_regno_p (i))
8078 {
8079 addr = plus_constant (frame_pointer,
8080 offset + cfun_frame_layout.gprs_offset
8081 + (i - cfun_frame_layout.first_save_gpr_slot)
8082 * UNITS_PER_WORD);
8083 addr = gen_rtx_MEM (Pmode, addr);
8084 set_mem_alias_set (addr, get_frame_alias_set ());
8085 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8086 }
8087 else
8088 cfa_restores
8089 = alloc_reg_note (REG_CFA_RESTORE,
8090 gen_rtx_REG (Pmode, i), cfa_restores);
8091 }
8092
8093 if (! sibcall)
8094 {
8095 /* Fetch return address from stack before load multiple,
8096 this will do good for scheduling. */
8097
8098 if (cfun_frame_layout.save_return_addr_p
8099 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8100 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8101 {
8102 int return_regnum = find_unused_clobbered_reg();
8103 if (!return_regnum)
8104 return_regnum = 4;
8105 return_reg = gen_rtx_REG (Pmode, return_regnum);
8106
8107 addr = plus_constant (frame_pointer,
8108 offset + cfun_frame_layout.gprs_offset
8109 + (RETURN_REGNUM
8110 - cfun_frame_layout.first_save_gpr_slot)
8111 * UNITS_PER_WORD);
8112 addr = gen_rtx_MEM (Pmode, addr);
8113 set_mem_alias_set (addr, get_frame_alias_set ());
8114 emit_move_insn (return_reg, addr);
8115 }
8116 }
8117
8118 insn = restore_gprs (frame_pointer,
8119 offset + cfun_frame_layout.gprs_offset
8120 + (cfun_frame_layout.first_restore_gpr
8121 - cfun_frame_layout.first_save_gpr_slot)
8122 * UNITS_PER_WORD,
8123 cfun_frame_layout.first_restore_gpr,
8124 cfun_frame_layout.last_restore_gpr);
8125 insn = emit_insn (insn);
8126 REG_NOTES (insn) = cfa_restores;
8127 add_reg_note (insn, REG_CFA_DEF_CFA,
8128 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8129 RTX_FRAME_RELATED_P (insn) = 1;
8130 }
8131
8132 if (! sibcall)
8133 {
8134
8135 /* Return to caller. */
8136
8137 p = rtvec_alloc (2);
8138
8139 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8140 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8141 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8142 }
8143 }
8144
8145
8146 /* Return the size in bytes of a function argument of
8147 type TYPE and/or mode MODE. At least one of TYPE or
8148 MODE must be specified. */
8149
8150 static int
8151 s390_function_arg_size (enum machine_mode mode, const_tree type)
8152 {
8153 if (type)
8154 return int_size_in_bytes (type);
8155
8156 /* No type info available for some library calls ... */
8157 if (mode != BLKmode)
8158 return GET_MODE_SIZE (mode);
8159
8160 /* If we have neither type nor mode, abort */
8161 gcc_unreachable ();
8162 }
8163
8164 /* Return true if a function argument of type TYPE and mode MODE
8165 is to be passed in a floating-point register, if available. */
8166
8167 static bool
8168 s390_function_arg_float (enum machine_mode mode, tree type)
8169 {
8170 int size = s390_function_arg_size (mode, type);
8171 if (size > 8)
8172 return false;
8173
8174 /* Soft-float changes the ABI: no floating-point registers are used. */
8175 if (TARGET_SOFT_FLOAT)
8176 return false;
8177
8178 /* No type info available for some library calls ... */
8179 if (!type)
8180 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8181
8182 /* The ABI says that record types with a single member are treated
8183 just like that member would be. */
8184 while (TREE_CODE (type) == RECORD_TYPE)
8185 {
8186 tree field, single = NULL_TREE;
8187
8188 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8189 {
8190 if (TREE_CODE (field) != FIELD_DECL)
8191 continue;
8192
8193 if (single == NULL_TREE)
8194 single = TREE_TYPE (field);
8195 else
8196 return false;
8197 }
8198
8199 if (single == NULL_TREE)
8200 return false;
8201 else
8202 type = single;
8203 }
8204
8205 return TREE_CODE (type) == REAL_TYPE;
8206 }
8207
8208 /* Return true if a function argument of type TYPE and mode MODE
8209 is to be passed in an integer register, or a pair of integer
8210 registers, if available. */
8211
8212 static bool
8213 s390_function_arg_integer (enum machine_mode mode, tree type)
8214 {
8215 int size = s390_function_arg_size (mode, type);
8216 if (size > 8)
8217 return false;
8218
8219 /* No type info available for some library calls ... */
8220 if (!type)
8221 return GET_MODE_CLASS (mode) == MODE_INT
8222 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8223
8224 /* We accept small integral (and similar) types. */
8225 if (INTEGRAL_TYPE_P (type)
8226 || POINTER_TYPE_P (type)
8227 || TREE_CODE (type) == OFFSET_TYPE
8228 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8229 return true;
8230
8231 /* We also accept structs of size 1, 2, 4, 8 that are not
8232 passed in floating-point registers. */
8233 if (AGGREGATE_TYPE_P (type)
8234 && exact_log2 (size) >= 0
8235 && !s390_function_arg_float (mode, type))
8236 return true;
8237
8238 return false;
8239 }
8240
8241 /* Return 1 if a function argument of type TYPE and mode MODE
8242 is to be passed by reference. The ABI specifies that only
8243 structures of size 1, 2, 4, or 8 bytes are passed by value,
8244 all other structures (and complex numbers) are passed by
8245 reference. */
8246
8247 static bool
8248 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8249 enum machine_mode mode, const_tree type,
8250 bool named ATTRIBUTE_UNUSED)
8251 {
8252 int size = s390_function_arg_size (mode, type);
8253 if (size > 8)
8254 return true;
8255
8256 if (type)
8257 {
8258 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8259 return 1;
8260
8261 if (TREE_CODE (type) == COMPLEX_TYPE
8262 || TREE_CODE (type) == VECTOR_TYPE)
8263 return 1;
8264 }
8265
8266 return 0;
8267 }
8268
8269 /* Update the data in CUM to advance over an argument of mode MODE and
8270 data type TYPE. (TYPE is null for libcalls where that information
8271 may not be available.). The boolean NAMED specifies whether the
8272 argument is a named argument (as opposed to an unnamed argument
8273 matching an ellipsis). */
8274
8275 void
8276 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8277 tree type, int named ATTRIBUTE_UNUSED)
8278 {
8279 if (s390_function_arg_float (mode, type))
8280 {
8281 cum->fprs += 1;
8282 }
8283 else if (s390_function_arg_integer (mode, type))
8284 {
8285 int size = s390_function_arg_size (mode, type);
8286 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
8287 }
8288 else
8289 gcc_unreachable ();
8290 }
8291
8292 /* Define where to put the arguments to a function.
8293 Value is zero to push the argument on the stack,
8294 or a hard register in which to store the argument.
8295
8296 MODE is the argument's machine mode.
8297 TYPE is the data type of the argument (as a tree).
8298 This is null for libcalls where that information may
8299 not be available.
8300 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8301 the preceding args and about the function being called.
8302 NAMED is nonzero if this argument is a named parameter
8303 (otherwise it is an extra parameter matching an ellipsis).
8304
8305 On S/390, we use general purpose registers 2 through 6 to
8306 pass integer, pointer, and certain structure arguments, and
8307 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8308 to pass floating point arguments. All remaining arguments
8309 are pushed to the stack. */
8310
8311 rtx
8312 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8313 int named ATTRIBUTE_UNUSED)
8314 {
8315 if (s390_function_arg_float (mode, type))
8316 {
8317 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8318 return 0;
8319 else
8320 return gen_rtx_REG (mode, cum->fprs + 16);
8321 }
8322 else if (s390_function_arg_integer (mode, type))
8323 {
8324 int size = s390_function_arg_size (mode, type);
8325 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
8326
8327 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8328 return 0;
8329 else
8330 return gen_rtx_REG (mode, cum->gprs + 2);
8331 }
8332
8333 /* After the real arguments, expand_call calls us once again
8334 with a void_type_node type. Whatever we return here is
8335 passed as operand 2 to the call expanders.
8336
8337 We don't need this feature ... */
8338 else if (type == void_type_node)
8339 return const0_rtx;
8340
8341 gcc_unreachable ();
8342 }
8343
8344 /* Return true if return values of type TYPE should be returned
8345 in a memory buffer whose address is passed by the caller as
8346 hidden first argument. */
8347
8348 static bool
8349 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8350 {
8351 /* We accept small integral (and similar) types. */
8352 if (INTEGRAL_TYPE_P (type)
8353 || POINTER_TYPE_P (type)
8354 || TREE_CODE (type) == OFFSET_TYPE
8355 || TREE_CODE (type) == REAL_TYPE)
8356 return int_size_in_bytes (type) > 8;
8357
8358 /* Aggregates and similar constructs are always returned
8359 in memory. */
8360 if (AGGREGATE_TYPE_P (type)
8361 || TREE_CODE (type) == COMPLEX_TYPE
8362 || TREE_CODE (type) == VECTOR_TYPE)
8363 return true;
8364
8365 /* ??? We get called on all sorts of random stuff from
8366 aggregate_value_p. We can't abort, but it's not clear
8367 what's safe to return. Pretend it's a struct I guess. */
8368 return true;
8369 }
8370
8371 /* Function arguments and return values are promoted to word size. */
8372
8373 static enum machine_mode
8374 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8375 int *punsignedp,
8376 const_tree fntype ATTRIBUTE_UNUSED,
8377 int for_return ATTRIBUTE_UNUSED)
8378 {
8379 if (INTEGRAL_MODE_P (mode)
8380 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
8381 {
8382 if (POINTER_TYPE_P (type))
8383 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8384 return Pmode;
8385 }
8386
8387 return mode;
8388 }
8389
8390 /* Define where to return a (scalar) value of type TYPE.
8391 If TYPE is null, define where to return a (scalar)
8392 value of mode MODE from a libcall. */
8393
8394 rtx
8395 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8396 {
8397 if (type)
8398 {
8399 int unsignedp = TYPE_UNSIGNED (type);
8400 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8401 }
8402
8403 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8404 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8405
8406 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8407 return gen_rtx_REG (mode, 16);
8408 else
8409 return gen_rtx_REG (mode, 2);
8410 }
8411
8412
8413 /* Create and return the va_list datatype.
8414
8415 On S/390, va_list is an array type equivalent to
8416
8417 typedef struct __va_list_tag
8418 {
8419 long __gpr;
8420 long __fpr;
8421 void *__overflow_arg_area;
8422 void *__reg_save_area;
8423 } va_list[1];
8424
8425 where __gpr and __fpr hold the number of general purpose
8426 or floating point arguments used up to now, respectively,
8427 __overflow_arg_area points to the stack location of the
8428 next argument passed on the stack, and __reg_save_area
8429 always points to the start of the register area in the
8430 call frame of the current function. The function prologue
8431 saves all registers used for argument passing into this
8432 area if the function uses variable arguments. */
8433
8434 static tree
8435 s390_build_builtin_va_list (void)
8436 {
8437 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8438
8439 record = lang_hooks.types.make_type (RECORD_TYPE);
8440
8441 type_decl =
8442 build_decl (BUILTINS_LOCATION,
8443 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8444
8445 f_gpr = build_decl (BUILTINS_LOCATION,
8446 FIELD_DECL, get_identifier ("__gpr"),
8447 long_integer_type_node);
8448 f_fpr = build_decl (BUILTINS_LOCATION,
8449 FIELD_DECL, get_identifier ("__fpr"),
8450 long_integer_type_node);
8451 f_ovf = build_decl (BUILTINS_LOCATION,
8452 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8453 ptr_type_node);
8454 f_sav = build_decl (BUILTINS_LOCATION,
8455 FIELD_DECL, get_identifier ("__reg_save_area"),
8456 ptr_type_node);
8457
8458 va_list_gpr_counter_field = f_gpr;
8459 va_list_fpr_counter_field = f_fpr;
8460
8461 DECL_FIELD_CONTEXT (f_gpr) = record;
8462 DECL_FIELD_CONTEXT (f_fpr) = record;
8463 DECL_FIELD_CONTEXT (f_ovf) = record;
8464 DECL_FIELD_CONTEXT (f_sav) = record;
8465
8466 TREE_CHAIN (record) = type_decl;
8467 TYPE_NAME (record) = type_decl;
8468 TYPE_FIELDS (record) = f_gpr;
8469 TREE_CHAIN (f_gpr) = f_fpr;
8470 TREE_CHAIN (f_fpr) = f_ovf;
8471 TREE_CHAIN (f_ovf) = f_sav;
8472
8473 layout_type (record);
8474
8475 /* The correct type is an array type of one element. */
8476 return build_array_type (record, build_index_type (size_zero_node));
8477 }
8478
8479 /* Implement va_start by filling the va_list structure VALIST.
8480 STDARG_P is always true, and ignored.
8481 NEXTARG points to the first anonymous stack argument.
8482
8483 The following global variables are used to initialize
8484 the va_list structure:
8485
8486 crtl->args.info:
8487 holds number of gprs and fprs used for named arguments.
8488 crtl->args.arg_offset_rtx:
8489 holds the offset of the first anonymous stack argument
8490 (relative to the virtual arg pointer). */
8491
8492 static void
8493 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8494 {
8495 HOST_WIDE_INT n_gpr, n_fpr;
8496 int off;
8497 tree f_gpr, f_fpr, f_ovf, f_sav;
8498 tree gpr, fpr, ovf, sav, t;
8499
8500 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8501 f_fpr = TREE_CHAIN (f_gpr);
8502 f_ovf = TREE_CHAIN (f_fpr);
8503 f_sav = TREE_CHAIN (f_ovf);
8504
8505 valist = build_va_arg_indirect_ref (valist);
8506 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8507 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8508 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8509 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8510
8511 /* Count number of gp and fp argument registers used. */
8512
8513 n_gpr = crtl->args.info.gprs;
8514 n_fpr = crtl->args.info.fprs;
8515
8516 if (cfun->va_list_gpr_size)
8517 {
8518 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8519 build_int_cst (NULL_TREE, n_gpr));
8520 TREE_SIDE_EFFECTS (t) = 1;
8521 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8522 }
8523
8524 if (cfun->va_list_fpr_size)
8525 {
8526 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8527 build_int_cst (NULL_TREE, n_fpr));
8528 TREE_SIDE_EFFECTS (t) = 1;
8529 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8530 }
8531
8532 /* Find the overflow area. */
8533 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8534 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8535 {
8536 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8537
8538 off = INTVAL (crtl->args.arg_offset_rtx);
8539 off = off < 0 ? 0 : off;
8540 if (TARGET_DEBUG_ARG)
8541 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8542 (int)n_gpr, (int)n_fpr, off);
8543
8544 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8545
8546 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8547 TREE_SIDE_EFFECTS (t) = 1;
8548 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8549 }
8550
8551 /* Find the register save area. */
8552 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8553 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8554 {
8555 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8556 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8557 size_int (-RETURN_REGNUM * UNITS_PER_WORD));
8558
8559 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8560 TREE_SIDE_EFFECTS (t) = 1;
8561 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8562 }
8563 }
8564
8565 /* Implement va_arg by updating the va_list structure
8566 VALIST as required to retrieve an argument of type
8567 TYPE, and returning that argument.
8568
8569 Generates code equivalent to:
8570
8571 if (integral value) {
8572 if (size <= 4 && args.gpr < 5 ||
8573 size > 4 && args.gpr < 4 )
8574 ret = args.reg_save_area[args.gpr+8]
8575 else
8576 ret = *args.overflow_arg_area++;
8577 } else if (float value) {
8578 if (args.fgpr < 2)
8579 ret = args.reg_save_area[args.fpr+64]
8580 else
8581 ret = *args.overflow_arg_area++;
8582 } else if (aggregate value) {
8583 if (args.gpr < 5)
8584 ret = *args.reg_save_area[args.gpr]
8585 else
8586 ret = **args.overflow_arg_area++;
8587 } */
8588
8589 static tree
8590 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8591 gimple_seq *post_p ATTRIBUTE_UNUSED)
8592 {
8593 tree f_gpr, f_fpr, f_ovf, f_sav;
8594 tree gpr, fpr, ovf, sav, reg, t, u;
8595 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8596 tree lab_false, lab_over, addr;
8597
8598 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8599 f_fpr = TREE_CHAIN (f_gpr);
8600 f_ovf = TREE_CHAIN (f_fpr);
8601 f_sav = TREE_CHAIN (f_ovf);
8602
8603 valist = build_va_arg_indirect_ref (valist);
8604 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8605 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8606 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8607
8608 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8609 both appear on a lhs. */
8610 valist = unshare_expr (valist);
8611 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8612
8613 size = int_size_in_bytes (type);
8614
8615 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8616 {
8617 if (TARGET_DEBUG_ARG)
8618 {
8619 fprintf (stderr, "va_arg: aggregate type");
8620 debug_tree (type);
8621 }
8622
8623 /* Aggregates are passed by reference. */
8624 indirect_p = 1;
8625 reg = gpr;
8626 n_reg = 1;
8627
8628 /* kernel stack layout on 31 bit: It is assumed here that no padding
8629 will be added by s390_frame_info because for va_args always an even
8630 number of gprs has to be saved r15-r2 = 14 regs. */
8631 sav_ofs = 2 * UNITS_PER_WORD;
8632 sav_scale = UNITS_PER_WORD;
8633 size = UNITS_PER_WORD;
8634 max_reg = GP_ARG_NUM_REG - n_reg;
8635 }
8636 else if (s390_function_arg_float (TYPE_MODE (type), type))
8637 {
8638 if (TARGET_DEBUG_ARG)
8639 {
8640 fprintf (stderr, "va_arg: float type");
8641 debug_tree (type);
8642 }
8643
8644 /* FP args go in FP registers, if present. */
8645 indirect_p = 0;
8646 reg = fpr;
8647 n_reg = 1;
8648 sav_ofs = 16 * UNITS_PER_WORD;
8649 sav_scale = 8;
8650 max_reg = FP_ARG_NUM_REG - n_reg;
8651 }
8652 else
8653 {
8654 if (TARGET_DEBUG_ARG)
8655 {
8656 fprintf (stderr, "va_arg: other type");
8657 debug_tree (type);
8658 }
8659
8660 /* Otherwise into GP registers. */
8661 indirect_p = 0;
8662 reg = gpr;
8663 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8664
8665 /* kernel stack layout on 31 bit: It is assumed here that no padding
8666 will be added by s390_frame_info because for va_args always an even
8667 number of gprs has to be saved r15-r2 = 14 regs. */
8668 sav_ofs = 2 * UNITS_PER_WORD;
8669
8670 if (size < UNITS_PER_WORD)
8671 sav_ofs += UNITS_PER_WORD - size;
8672
8673 sav_scale = UNITS_PER_WORD;
8674 max_reg = GP_ARG_NUM_REG - n_reg;
8675 }
8676
8677 /* Pull the value out of the saved registers ... */
8678
8679 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8680 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8681 addr = create_tmp_var (ptr_type_node, "addr");
8682
8683 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8684 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8685 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8686 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8687 gimplify_and_add (t, pre_p);
8688
8689 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8690 size_int (sav_ofs));
8691 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8692 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8693 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8694
8695 gimplify_assign (addr, t, pre_p);
8696
8697 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8698
8699 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8700
8701
8702 /* ... Otherwise out of the overflow area. */
8703
8704 t = ovf;
8705 if (size < UNITS_PER_WORD)
8706 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8707 size_int (UNITS_PER_WORD - size));
8708
8709 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8710
8711 gimplify_assign (addr, t, pre_p);
8712
8713 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8714 size_int (size));
8715 gimplify_assign (ovf, t, pre_p);
8716
8717 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8718
8719
8720 /* Increment register save count. */
8721
8722 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8723 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8724 gimplify_and_add (u, pre_p);
8725
8726 if (indirect_p)
8727 {
8728 t = build_pointer_type_for_mode (build_pointer_type (type),
8729 ptr_mode, true);
8730 addr = fold_convert (t, addr);
8731 addr = build_va_arg_indirect_ref (addr);
8732 }
8733 else
8734 {
8735 t = build_pointer_type_for_mode (type, ptr_mode, true);
8736 addr = fold_convert (t, addr);
8737 }
8738
8739 return build_va_arg_indirect_ref (addr);
8740 }
8741
8742
8743 /* Builtins. */
8744
8745 enum s390_builtin
8746 {
8747 S390_BUILTIN_THREAD_POINTER,
8748 S390_BUILTIN_SET_THREAD_POINTER,
8749
8750 S390_BUILTIN_max
8751 };
8752
8753 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8754 CODE_FOR_get_tp_64,
8755 CODE_FOR_set_tp_64
8756 };
8757
8758 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8759 CODE_FOR_get_tp_31,
8760 CODE_FOR_set_tp_31
8761 };
8762
8763 static void
8764 s390_init_builtins (void)
8765 {
8766 tree ftype;
8767
8768 ftype = build_function_type (ptr_type_node, void_list_node);
8769 add_builtin_function ("__builtin_thread_pointer", ftype,
8770 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8771 NULL, NULL_TREE);
8772
8773 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8774 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8775 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8776 NULL, NULL_TREE);
8777 }
8778
8779 /* Expand an expression EXP that calls a built-in function,
8780 with result going to TARGET if that's convenient
8781 (and in mode MODE if that's convenient).
8782 SUBTARGET may be used as the target for computing one of EXP's operands.
8783 IGNORE is nonzero if the value is to be ignored. */
8784
8785 static rtx
8786 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8787 enum machine_mode mode ATTRIBUTE_UNUSED,
8788 int ignore ATTRIBUTE_UNUSED)
8789 {
8790 #define MAX_ARGS 2
8791
8792 enum insn_code const *code_for_builtin =
8793 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8794
8795 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8796 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8797 enum insn_code icode;
8798 rtx op[MAX_ARGS], pat;
8799 int arity;
8800 bool nonvoid;
8801 tree arg;
8802 call_expr_arg_iterator iter;
8803
8804 if (fcode >= S390_BUILTIN_max)
8805 internal_error ("bad builtin fcode");
8806 icode = code_for_builtin[fcode];
8807 if (icode == 0)
8808 internal_error ("bad builtin fcode");
8809
8810 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8811
8812 arity = 0;
8813 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8814 {
8815 const struct insn_operand_data *insn_op;
8816
8817 if (arg == error_mark_node)
8818 return NULL_RTX;
8819 if (arity > MAX_ARGS)
8820 return NULL_RTX;
8821
8822 insn_op = &insn_data[icode].operand[arity + nonvoid];
8823
8824 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8825
8826 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8827 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8828 arity++;
8829 }
8830
8831 if (nonvoid)
8832 {
8833 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8834 if (!target
8835 || GET_MODE (target) != tmode
8836 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8837 target = gen_reg_rtx (tmode);
8838 }
8839
8840 switch (arity)
8841 {
8842 case 0:
8843 pat = GEN_FCN (icode) (target);
8844 break;
8845 case 1:
8846 if (nonvoid)
8847 pat = GEN_FCN (icode) (target, op[0]);
8848 else
8849 pat = GEN_FCN (icode) (op[0]);
8850 break;
8851 case 2:
8852 pat = GEN_FCN (icode) (target, op[0], op[1]);
8853 break;
8854 default:
8855 gcc_unreachable ();
8856 }
8857 if (!pat)
8858 return NULL_RTX;
8859 emit_insn (pat);
8860
8861 if (nonvoid)
8862 return target;
8863 else
8864 return const0_rtx;
8865 }
8866
8867
8868 /* Output assembly code for the trampoline template to
8869 stdio stream FILE.
8870
8871 On S/390, we use gpr 1 internally in the trampoline code;
8872 gpr 0 is used to hold the static chain. */
8873
8874 static void
8875 s390_asm_trampoline_template (FILE *file)
8876 {
8877 rtx op[2];
8878 op[0] = gen_rtx_REG (Pmode, 0);
8879 op[1] = gen_rtx_REG (Pmode, 1);
8880
8881 if (TARGET_64BIT)
8882 {
8883 output_asm_insn ("basr\t%1,0", op);
8884 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8885 output_asm_insn ("br\t%1", op);
8886 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8887 }
8888 else
8889 {
8890 output_asm_insn ("basr\t%1,0", op);
8891 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8892 output_asm_insn ("br\t%1", op);
8893 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8894 }
8895 }
8896
8897 /* Emit RTL insns to initialize the variable parts of a trampoline.
8898 FNADDR is an RTX for the address of the function's pure code.
8899 CXT is an RTX for the static chain value for the function. */
8900
8901 static void
8902 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
8903 {
8904 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
8905 rtx mem;
8906
8907 emit_block_move (m_tramp, assemble_trampoline_template (),
8908 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
8909
8910 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
8911 emit_move_insn (mem, cxt);
8912 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
8913 emit_move_insn (mem, fnaddr);
8914 }
8915
8916 /* Output assembler code to FILE to increment profiler label # LABELNO
8917 for profiling a function entry. */
8918
8919 void
8920 s390_function_profiler (FILE *file, int labelno)
8921 {
8922 rtx op[7];
8923
8924 char label[128];
8925 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8926
8927 fprintf (file, "# function profiler \n");
8928
8929 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8930 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8931 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8932
8933 op[2] = gen_rtx_REG (Pmode, 1);
8934 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8935 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8936
8937 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8938 if (flag_pic)
8939 {
8940 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8941 op[4] = gen_rtx_CONST (Pmode, op[4]);
8942 }
8943
8944 if (TARGET_64BIT)
8945 {
8946 output_asm_insn ("stg\t%0,%1", op);
8947 output_asm_insn ("larl\t%2,%3", op);
8948 output_asm_insn ("brasl\t%0,%4", op);
8949 output_asm_insn ("lg\t%0,%1", op);
8950 }
8951 else if (!flag_pic)
8952 {
8953 op[6] = gen_label_rtx ();
8954
8955 output_asm_insn ("st\t%0,%1", op);
8956 output_asm_insn ("bras\t%2,%l6", op);
8957 output_asm_insn (".long\t%4", op);
8958 output_asm_insn (".long\t%3", op);
8959 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8960 output_asm_insn ("l\t%0,0(%2)", op);
8961 output_asm_insn ("l\t%2,4(%2)", op);
8962 output_asm_insn ("basr\t%0,%0", op);
8963 output_asm_insn ("l\t%0,%1", op);
8964 }
8965 else
8966 {
8967 op[5] = gen_label_rtx ();
8968 op[6] = gen_label_rtx ();
8969
8970 output_asm_insn ("st\t%0,%1", op);
8971 output_asm_insn ("bras\t%2,%l6", op);
8972 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8973 output_asm_insn (".long\t%4-%l5", op);
8974 output_asm_insn (".long\t%3-%l5", op);
8975 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8976 output_asm_insn ("lr\t%0,%2", op);
8977 output_asm_insn ("a\t%0,0(%2)", op);
8978 output_asm_insn ("a\t%2,4(%2)", op);
8979 output_asm_insn ("basr\t%0,%0", op);
8980 output_asm_insn ("l\t%0,%1", op);
8981 }
8982 }
8983
8984 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8985 into its SYMBOL_REF_FLAGS. */
8986
8987 static void
8988 s390_encode_section_info (tree decl, rtx rtl, int first)
8989 {
8990 default_encode_section_info (decl, rtl, first);
8991
8992 if (TREE_CODE (decl) == VAR_DECL)
8993 {
8994 /* If a variable has a forced alignment to < 2 bytes, mark it
8995 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8996 operand. */
8997 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8998 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8999 if (!DECL_SIZE (decl)
9000 || !DECL_ALIGN (decl)
9001 || !host_integerp (DECL_SIZE (decl), 0)
9002 || (DECL_ALIGN (decl) <= 64
9003 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9004 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9005 }
9006
9007 /* Literal pool references don't have a decl so they are handled
9008 differently here. We rely on the information in the MEM_ALIGN
9009 entry to decide upon natural alignment. */
9010 if (MEM_P (rtl)
9011 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9012 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9013 && (MEM_ALIGN (rtl) == 0
9014 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9015 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9016 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9017 }
9018
9019 /* Output thunk to FILE that implements a C++ virtual function call (with
9020 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9021 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9022 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9023 relative to the resulting this pointer. */
9024
9025 static void
9026 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9027 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9028 tree function)
9029 {
9030 rtx op[10];
9031 int nonlocal = 0;
9032
9033 /* Operand 0 is the target function. */
9034 op[0] = XEXP (DECL_RTL (function), 0);
9035 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9036 {
9037 nonlocal = 1;
9038 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9039 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9040 op[0] = gen_rtx_CONST (Pmode, op[0]);
9041 }
9042
9043 /* Operand 1 is the 'this' pointer. */
9044 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9045 op[1] = gen_rtx_REG (Pmode, 3);
9046 else
9047 op[1] = gen_rtx_REG (Pmode, 2);
9048
9049 /* Operand 2 is the delta. */
9050 op[2] = GEN_INT (delta);
9051
9052 /* Operand 3 is the vcall_offset. */
9053 op[3] = GEN_INT (vcall_offset);
9054
9055 /* Operand 4 is the temporary register. */
9056 op[4] = gen_rtx_REG (Pmode, 1);
9057
9058 /* Operands 5 to 8 can be used as labels. */
9059 op[5] = NULL_RTX;
9060 op[6] = NULL_RTX;
9061 op[7] = NULL_RTX;
9062 op[8] = NULL_RTX;
9063
9064 /* Operand 9 can be used for temporary register. */
9065 op[9] = NULL_RTX;
9066
9067 /* Generate code. */
9068 if (TARGET_64BIT)
9069 {
9070 /* Setup literal pool pointer if required. */
9071 if ((!DISP_IN_RANGE (delta)
9072 && !CONST_OK_FOR_K (delta)
9073 && !CONST_OK_FOR_Os (delta))
9074 || (!DISP_IN_RANGE (vcall_offset)
9075 && !CONST_OK_FOR_K (vcall_offset)
9076 && !CONST_OK_FOR_Os (vcall_offset)))
9077 {
9078 op[5] = gen_label_rtx ();
9079 output_asm_insn ("larl\t%4,%5", op);
9080 }
9081
9082 /* Add DELTA to this pointer. */
9083 if (delta)
9084 {
9085 if (CONST_OK_FOR_J (delta))
9086 output_asm_insn ("la\t%1,%2(%1)", op);
9087 else if (DISP_IN_RANGE (delta))
9088 output_asm_insn ("lay\t%1,%2(%1)", op);
9089 else if (CONST_OK_FOR_K (delta))
9090 output_asm_insn ("aghi\t%1,%2", op);
9091 else if (CONST_OK_FOR_Os (delta))
9092 output_asm_insn ("agfi\t%1,%2", op);
9093 else
9094 {
9095 op[6] = gen_label_rtx ();
9096 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9097 }
9098 }
9099
9100 /* Perform vcall adjustment. */
9101 if (vcall_offset)
9102 {
9103 if (DISP_IN_RANGE (vcall_offset))
9104 {
9105 output_asm_insn ("lg\t%4,0(%1)", op);
9106 output_asm_insn ("ag\t%1,%3(%4)", op);
9107 }
9108 else if (CONST_OK_FOR_K (vcall_offset))
9109 {
9110 output_asm_insn ("lghi\t%4,%3", op);
9111 output_asm_insn ("ag\t%4,0(%1)", op);
9112 output_asm_insn ("ag\t%1,0(%4)", op);
9113 }
9114 else if (CONST_OK_FOR_Os (vcall_offset))
9115 {
9116 output_asm_insn ("lgfi\t%4,%3", op);
9117 output_asm_insn ("ag\t%4,0(%1)", op);
9118 output_asm_insn ("ag\t%1,0(%4)", op);
9119 }
9120 else
9121 {
9122 op[7] = gen_label_rtx ();
9123 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9124 output_asm_insn ("ag\t%4,0(%1)", op);
9125 output_asm_insn ("ag\t%1,0(%4)", op);
9126 }
9127 }
9128
9129 /* Jump to target. */
9130 output_asm_insn ("jg\t%0", op);
9131
9132 /* Output literal pool if required. */
9133 if (op[5])
9134 {
9135 output_asm_insn (".align\t4", op);
9136 targetm.asm_out.internal_label (file, "L",
9137 CODE_LABEL_NUMBER (op[5]));
9138 }
9139 if (op[6])
9140 {
9141 targetm.asm_out.internal_label (file, "L",
9142 CODE_LABEL_NUMBER (op[6]));
9143 output_asm_insn (".long\t%2", op);
9144 }
9145 if (op[7])
9146 {
9147 targetm.asm_out.internal_label (file, "L",
9148 CODE_LABEL_NUMBER (op[7]));
9149 output_asm_insn (".long\t%3", op);
9150 }
9151 }
9152 else
9153 {
9154 /* Setup base pointer if required. */
9155 if (!vcall_offset
9156 || (!DISP_IN_RANGE (delta)
9157 && !CONST_OK_FOR_K (delta)
9158 && !CONST_OK_FOR_Os (delta))
9159 || (!DISP_IN_RANGE (delta)
9160 && !CONST_OK_FOR_K (vcall_offset)
9161 && !CONST_OK_FOR_Os (vcall_offset)))
9162 {
9163 op[5] = gen_label_rtx ();
9164 output_asm_insn ("basr\t%4,0", op);
9165 targetm.asm_out.internal_label (file, "L",
9166 CODE_LABEL_NUMBER (op[5]));
9167 }
9168
9169 /* Add DELTA to this pointer. */
9170 if (delta)
9171 {
9172 if (CONST_OK_FOR_J (delta))
9173 output_asm_insn ("la\t%1,%2(%1)", op);
9174 else if (DISP_IN_RANGE (delta))
9175 output_asm_insn ("lay\t%1,%2(%1)", op);
9176 else if (CONST_OK_FOR_K (delta))
9177 output_asm_insn ("ahi\t%1,%2", op);
9178 else if (CONST_OK_FOR_Os (delta))
9179 output_asm_insn ("afi\t%1,%2", op);
9180 else
9181 {
9182 op[6] = gen_label_rtx ();
9183 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9184 }
9185 }
9186
9187 /* Perform vcall adjustment. */
9188 if (vcall_offset)
9189 {
9190 if (CONST_OK_FOR_J (vcall_offset))
9191 {
9192 output_asm_insn ("l\t%4,0(%1)", op);
9193 output_asm_insn ("a\t%1,%3(%4)", op);
9194 }
9195 else if (DISP_IN_RANGE (vcall_offset))
9196 {
9197 output_asm_insn ("l\t%4,0(%1)", op);
9198 output_asm_insn ("ay\t%1,%3(%4)", op);
9199 }
9200 else if (CONST_OK_FOR_K (vcall_offset))
9201 {
9202 output_asm_insn ("lhi\t%4,%3", op);
9203 output_asm_insn ("a\t%4,0(%1)", op);
9204 output_asm_insn ("a\t%1,0(%4)", op);
9205 }
9206 else if (CONST_OK_FOR_Os (vcall_offset))
9207 {
9208 output_asm_insn ("iilf\t%4,%3", op);
9209 output_asm_insn ("a\t%4,0(%1)", op);
9210 output_asm_insn ("a\t%1,0(%4)", op);
9211 }
9212 else
9213 {
9214 op[7] = gen_label_rtx ();
9215 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9216 output_asm_insn ("a\t%4,0(%1)", op);
9217 output_asm_insn ("a\t%1,0(%4)", op);
9218 }
9219
9220 /* We had to clobber the base pointer register.
9221 Re-setup the base pointer (with a different base). */
9222 op[5] = gen_label_rtx ();
9223 output_asm_insn ("basr\t%4,0", op);
9224 targetm.asm_out.internal_label (file, "L",
9225 CODE_LABEL_NUMBER (op[5]));
9226 }
9227
9228 /* Jump to target. */
9229 op[8] = gen_label_rtx ();
9230
9231 if (!flag_pic)
9232 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9233 else if (!nonlocal)
9234 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9235 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9236 else if (flag_pic == 1)
9237 {
9238 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9239 output_asm_insn ("l\t%4,%0(%4)", op);
9240 }
9241 else if (flag_pic == 2)
9242 {
9243 op[9] = gen_rtx_REG (Pmode, 0);
9244 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9245 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9246 output_asm_insn ("ar\t%4,%9", op);
9247 output_asm_insn ("l\t%4,0(%4)", op);
9248 }
9249
9250 output_asm_insn ("br\t%4", op);
9251
9252 /* Output literal pool. */
9253 output_asm_insn (".align\t4", op);
9254
9255 if (nonlocal && flag_pic == 2)
9256 output_asm_insn (".long\t%0", op);
9257 if (nonlocal)
9258 {
9259 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9260 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9261 }
9262
9263 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9264 if (!flag_pic)
9265 output_asm_insn (".long\t%0", op);
9266 else
9267 output_asm_insn (".long\t%0-%5", op);
9268
9269 if (op[6])
9270 {
9271 targetm.asm_out.internal_label (file, "L",
9272 CODE_LABEL_NUMBER (op[6]));
9273 output_asm_insn (".long\t%2", op);
9274 }
9275 if (op[7])
9276 {
9277 targetm.asm_out.internal_label (file, "L",
9278 CODE_LABEL_NUMBER (op[7]));
9279 output_asm_insn (".long\t%3", op);
9280 }
9281 }
9282 }
9283
9284 static bool
9285 s390_valid_pointer_mode (enum machine_mode mode)
9286 {
9287 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9288 }
9289
9290 /* Checks whether the given CALL_EXPR would use a caller
9291 saved register. This is used to decide whether sibling call
9292 optimization could be performed on the respective function
9293 call. */
9294
9295 static bool
9296 s390_call_saved_register_used (tree call_expr)
9297 {
9298 CUMULATIVE_ARGS cum;
9299 tree parameter;
9300 enum machine_mode mode;
9301 tree type;
9302 rtx parm_rtx;
9303 int reg, i;
9304
9305 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9306
9307 for (i = 0; i < call_expr_nargs (call_expr); i++)
9308 {
9309 parameter = CALL_EXPR_ARG (call_expr, i);
9310 gcc_assert (parameter);
9311
9312 /* For an undeclared variable passed as parameter we will get
9313 an ERROR_MARK node here. */
9314 if (TREE_CODE (parameter) == ERROR_MARK)
9315 return true;
9316
9317 type = TREE_TYPE (parameter);
9318 gcc_assert (type);
9319
9320 mode = TYPE_MODE (type);
9321 gcc_assert (mode);
9322
9323 if (pass_by_reference (&cum, mode, type, true))
9324 {
9325 mode = Pmode;
9326 type = build_pointer_type (type);
9327 }
9328
9329 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9330
9331 s390_function_arg_advance (&cum, mode, type, 0);
9332
9333 if (parm_rtx && REG_P (parm_rtx))
9334 {
9335 for (reg = 0;
9336 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9337 reg++)
9338 if (! call_used_regs[reg + REGNO (parm_rtx)])
9339 return true;
9340 }
9341 }
9342 return false;
9343 }
9344
9345 /* Return true if the given call expression can be
9346 turned into a sibling call.
9347 DECL holds the declaration of the function to be called whereas
9348 EXP is the call expression itself. */
9349
9350 static bool
9351 s390_function_ok_for_sibcall (tree decl, tree exp)
9352 {
9353 /* The TPF epilogue uses register 1. */
9354 if (TARGET_TPF_PROFILING)
9355 return false;
9356
9357 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9358 which would have to be restored before the sibcall. */
9359 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9360 return false;
9361
9362 /* Register 6 on s390 is available as an argument register but unfortunately
9363 "caller saved". This makes functions needing this register for arguments
9364 not suitable for sibcalls. */
9365 return !s390_call_saved_register_used (exp);
9366 }
9367
9368 /* Return the fixed registers used for condition codes. */
9369
9370 static bool
9371 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9372 {
9373 *p1 = CC_REGNUM;
9374 *p2 = INVALID_REGNUM;
9375
9376 return true;
9377 }
9378
9379 /* This function is used by the call expanders of the machine description.
9380 It emits the call insn itself together with the necessary operations
9381 to adjust the target address and returns the emitted insn.
9382 ADDR_LOCATION is the target address rtx
9383 TLS_CALL the location of the thread-local symbol
9384 RESULT_REG the register where the result of the call should be stored
9385 RETADDR_REG the register where the return address should be stored
9386 If this parameter is NULL_RTX the call is considered
9387 to be a sibling call. */
9388
9389 rtx
9390 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9391 rtx retaddr_reg)
9392 {
9393 bool plt_call = false;
9394 rtx insn;
9395 rtx call;
9396 rtx clobber;
9397 rtvec vec;
9398
9399 /* Direct function calls need special treatment. */
9400 if (GET_CODE (addr_location) == SYMBOL_REF)
9401 {
9402 /* When calling a global routine in PIC mode, we must
9403 replace the symbol itself with the PLT stub. */
9404 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9405 {
9406 addr_location = gen_rtx_UNSPEC (Pmode,
9407 gen_rtvec (1, addr_location),
9408 UNSPEC_PLT);
9409 addr_location = gen_rtx_CONST (Pmode, addr_location);
9410 plt_call = true;
9411 }
9412
9413 /* Unless we can use the bras(l) insn, force the
9414 routine address into a register. */
9415 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9416 {
9417 if (flag_pic)
9418 addr_location = legitimize_pic_address (addr_location, 0);
9419 else
9420 addr_location = force_reg (Pmode, addr_location);
9421 }
9422 }
9423
9424 /* If it is already an indirect call or the code above moved the
9425 SYMBOL_REF to somewhere else make sure the address can be found in
9426 register 1. */
9427 if (retaddr_reg == NULL_RTX
9428 && GET_CODE (addr_location) != SYMBOL_REF
9429 && !plt_call)
9430 {
9431 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9432 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9433 }
9434
9435 addr_location = gen_rtx_MEM (QImode, addr_location);
9436 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9437
9438 if (result_reg != NULL_RTX)
9439 call = gen_rtx_SET (VOIDmode, result_reg, call);
9440
9441 if (retaddr_reg != NULL_RTX)
9442 {
9443 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9444
9445 if (tls_call != NULL_RTX)
9446 vec = gen_rtvec (3, call, clobber,
9447 gen_rtx_USE (VOIDmode, tls_call));
9448 else
9449 vec = gen_rtvec (2, call, clobber);
9450
9451 call = gen_rtx_PARALLEL (VOIDmode, vec);
9452 }
9453
9454 insn = emit_call_insn (call);
9455
9456 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9457 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9458 {
9459 /* s390_function_ok_for_sibcall should
9460 have denied sibcalls in this case. */
9461 gcc_assert (retaddr_reg != NULL_RTX);
9462
9463 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9464 }
9465 return insn;
9466 }
9467
9468 /* Implement CONDITIONAL_REGISTER_USAGE. */
9469
9470 void
9471 s390_conditional_register_usage (void)
9472 {
9473 int i;
9474
9475 if (flag_pic)
9476 {
9477 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9478 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9479 }
9480 if (TARGET_CPU_ZARCH)
9481 {
9482 fixed_regs[BASE_REGNUM] = 0;
9483 call_used_regs[BASE_REGNUM] = 0;
9484 fixed_regs[RETURN_REGNUM] = 0;
9485 call_used_regs[RETURN_REGNUM] = 0;
9486 }
9487 if (TARGET_64BIT)
9488 {
9489 for (i = 24; i < 32; i++)
9490 call_used_regs[i] = call_really_used_regs[i] = 0;
9491 }
9492 else
9493 {
9494 for (i = 18; i < 20; i++)
9495 call_used_regs[i] = call_really_used_regs[i] = 0;
9496 }
9497
9498 if (TARGET_SOFT_FLOAT)
9499 {
9500 for (i = 16; i < 32; i++)
9501 call_used_regs[i] = fixed_regs[i] = 1;
9502 }
9503 }
9504
9505 /* Corresponding function to eh_return expander. */
9506
9507 static GTY(()) rtx s390_tpf_eh_return_symbol;
9508 void
9509 s390_emit_tpf_eh_return (rtx target)
9510 {
9511 rtx insn, reg;
9512
9513 if (!s390_tpf_eh_return_symbol)
9514 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9515
9516 reg = gen_rtx_REG (Pmode, 2);
9517
9518 emit_move_insn (reg, target);
9519 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9520 gen_rtx_REG (Pmode, RETURN_REGNUM));
9521 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9522
9523 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9524 }
9525
9526 /* Rework the prologue/epilogue to avoid saving/restoring
9527 registers unnecessarily. */
9528
9529 static void
9530 s390_optimize_prologue (void)
9531 {
9532 rtx insn, new_insn, next_insn;
9533
9534 /* Do a final recompute of the frame-related data. */
9535
9536 s390_update_frame_layout ();
9537
9538 /* If all special registers are in fact used, there's nothing we
9539 can do, so no point in walking the insn list. */
9540
9541 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9542 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9543 && (TARGET_CPU_ZARCH
9544 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9545 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9546 return;
9547
9548 /* Search for prologue/epilogue insns and replace them. */
9549
9550 for (insn = get_insns (); insn; insn = next_insn)
9551 {
9552 int first, last, off;
9553 rtx set, base, offset;
9554
9555 next_insn = NEXT_INSN (insn);
9556
9557 if (GET_CODE (insn) != INSN)
9558 continue;
9559
9560 if (GET_CODE (PATTERN (insn)) == PARALLEL
9561 && store_multiple_operation (PATTERN (insn), VOIDmode))
9562 {
9563 set = XVECEXP (PATTERN (insn), 0, 0);
9564 first = REGNO (SET_SRC (set));
9565 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9566 offset = const0_rtx;
9567 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9568 off = INTVAL (offset);
9569
9570 if (GET_CODE (base) != REG || off < 0)
9571 continue;
9572 if (cfun_frame_layout.first_save_gpr != -1
9573 && (cfun_frame_layout.first_save_gpr < first
9574 || cfun_frame_layout.last_save_gpr > last))
9575 continue;
9576 if (REGNO (base) != STACK_POINTER_REGNUM
9577 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9578 continue;
9579 if (first > BASE_REGNUM || last < BASE_REGNUM)
9580 continue;
9581
9582 if (cfun_frame_layout.first_save_gpr != -1)
9583 {
9584 new_insn = save_gprs (base,
9585 off + (cfun_frame_layout.first_save_gpr
9586 - first) * UNITS_PER_WORD,
9587 cfun_frame_layout.first_save_gpr,
9588 cfun_frame_layout.last_save_gpr);
9589 new_insn = emit_insn_before (new_insn, insn);
9590 INSN_ADDRESSES_NEW (new_insn, -1);
9591 }
9592
9593 remove_insn (insn);
9594 continue;
9595 }
9596
9597 if (cfun_frame_layout.first_save_gpr == -1
9598 && GET_CODE (PATTERN (insn)) == SET
9599 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9600 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9601 || (!TARGET_CPU_ZARCH
9602 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9603 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9604 {
9605 set = PATTERN (insn);
9606 first = REGNO (SET_SRC (set));
9607 offset = const0_rtx;
9608 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9609 off = INTVAL (offset);
9610
9611 if (GET_CODE (base) != REG || off < 0)
9612 continue;
9613 if (REGNO (base) != STACK_POINTER_REGNUM
9614 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9615 continue;
9616
9617 remove_insn (insn);
9618 continue;
9619 }
9620
9621 if (GET_CODE (PATTERN (insn)) == PARALLEL
9622 && load_multiple_operation (PATTERN (insn), VOIDmode))
9623 {
9624 set = XVECEXP (PATTERN (insn), 0, 0);
9625 first = REGNO (SET_DEST (set));
9626 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9627 offset = const0_rtx;
9628 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9629 off = INTVAL (offset);
9630
9631 if (GET_CODE (base) != REG || off < 0)
9632 continue;
9633 if (cfun_frame_layout.first_restore_gpr != -1
9634 && (cfun_frame_layout.first_restore_gpr < first
9635 || cfun_frame_layout.last_restore_gpr > last))
9636 continue;
9637 if (REGNO (base) != STACK_POINTER_REGNUM
9638 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9639 continue;
9640 if (first > BASE_REGNUM || last < BASE_REGNUM)
9641 continue;
9642
9643 if (cfun_frame_layout.first_restore_gpr != -1)
9644 {
9645 new_insn = restore_gprs (base,
9646 off + (cfun_frame_layout.first_restore_gpr
9647 - first) * UNITS_PER_WORD,
9648 cfun_frame_layout.first_restore_gpr,
9649 cfun_frame_layout.last_restore_gpr);
9650 new_insn = emit_insn_before (new_insn, insn);
9651 INSN_ADDRESSES_NEW (new_insn, -1);
9652 }
9653
9654 remove_insn (insn);
9655 continue;
9656 }
9657
9658 if (cfun_frame_layout.first_restore_gpr == -1
9659 && GET_CODE (PATTERN (insn)) == SET
9660 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9661 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9662 || (!TARGET_CPU_ZARCH
9663 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9664 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9665 {
9666 set = PATTERN (insn);
9667 first = REGNO (SET_DEST (set));
9668 offset = const0_rtx;
9669 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9670 off = INTVAL (offset);
9671
9672 if (GET_CODE (base) != REG || off < 0)
9673 continue;
9674 if (REGNO (base) != STACK_POINTER_REGNUM
9675 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9676 continue;
9677
9678 remove_insn (insn);
9679 continue;
9680 }
9681 }
9682 }
9683
9684 /* On z10 the dynamic branch prediction must see the backward jump in
9685 a window of 384 bytes. If not it falls back to the static
9686 prediction. This function rearranges the loop backward branch in a
9687 way which makes the static prediction always correct. The function
9688 returns true if it added an instruction. */
9689 static bool
9690 s390_z10_fix_long_loop_prediction (rtx insn)
9691 {
9692 rtx set = single_set (insn);
9693 rtx code_label, label_ref, new_label;
9694 rtx uncond_jump;
9695 rtx cur_insn;
9696 rtx tmp;
9697 int distance;
9698
9699 /* This will exclude branch on count and branch on index patterns
9700 since these are correctly statically predicted. */
9701 if (!set
9702 || SET_DEST (set) != pc_rtx
9703 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9704 return false;
9705
9706 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9707 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9708
9709 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9710
9711 code_label = XEXP (label_ref, 0);
9712
9713 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9714 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9715 || (INSN_ADDRESSES (INSN_UID (insn))
9716 - INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE))
9717 return false;
9718
9719 for (distance = 0, cur_insn = PREV_INSN (insn);
9720 distance < Z10_PREDICT_DISTANCE - 6;
9721 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9722 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
9723 return false;
9724
9725 new_label = gen_label_rtx ();
9726 uncond_jump = emit_jump_insn_after (
9727 gen_rtx_SET (VOIDmode, pc_rtx,
9728 gen_rtx_LABEL_REF (VOIDmode, code_label)),
9729 insn);
9730 emit_label_after (new_label, uncond_jump);
9731
9732 tmp = XEXP (SET_SRC (set), 1);
9733 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
9734 XEXP (SET_SRC (set), 2) = tmp;
9735 INSN_CODE (insn) = -1;
9736
9737 XEXP (label_ref, 0) = new_label;
9738 JUMP_LABEL (insn) = new_label;
9739 JUMP_LABEL (uncond_jump) = code_label;
9740
9741 return true;
9742 }
9743
9744 /* Returns 1 if INSN reads the value of REG for purposes not related
9745 to addressing of memory, and 0 otherwise. */
9746 static int
9747 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9748 {
9749 return reg_referenced_p (reg, PATTERN (insn))
9750 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9751 }
9752
9753 /* Starting from INSN find_cond_jump looks downwards in the insn
9754 stream for a single jump insn which is the last user of the
9755 condition code set in INSN. */
9756 static rtx
9757 find_cond_jump (rtx insn)
9758 {
9759 for (; insn; insn = NEXT_INSN (insn))
9760 {
9761 rtx ite, cc;
9762
9763 if (LABEL_P (insn))
9764 break;
9765
9766 if (!JUMP_P (insn))
9767 {
9768 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9769 break;
9770 continue;
9771 }
9772
9773 /* This will be triggered by a return. */
9774 if (GET_CODE (PATTERN (insn)) != SET)
9775 break;
9776
9777 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9778 ite = SET_SRC (PATTERN (insn));
9779
9780 if (GET_CODE (ite) != IF_THEN_ELSE)
9781 break;
9782
9783 cc = XEXP (XEXP (ite, 0), 0);
9784 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9785 break;
9786
9787 if (find_reg_note (insn, REG_DEAD, cc))
9788 return insn;
9789 break;
9790 }
9791
9792 return NULL_RTX;
9793 }
9794
9795 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9796 the semantics does not change. If NULL_RTX is passed as COND the
9797 function tries to find the conditional jump starting with INSN. */
9798 static void
9799 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9800 {
9801 rtx tmp = *op0;
9802
9803 if (cond == NULL_RTX)
9804 {
9805 rtx jump = find_cond_jump (NEXT_INSN (insn));
9806 jump = jump ? single_set (jump) : NULL_RTX;
9807
9808 if (jump == NULL_RTX)
9809 return;
9810
9811 cond = XEXP (XEXP (jump, 1), 0);
9812 }
9813
9814 *op0 = *op1;
9815 *op1 = tmp;
9816 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9817 }
9818
9819 /* On z10, instructions of the compare-and-branch family have the
9820 property to access the register occurring as second operand with
9821 its bits complemented. If such a compare is grouped with a second
9822 instruction that accesses the same register non-complemented, and
9823 if that register's value is delivered via a bypass, then the
9824 pipeline recycles, thereby causing significant performance decline.
9825 This function locates such situations and exchanges the two
9826 operands of the compare. The function return true whenever it
9827 added an insn. */
9828 static bool
9829 s390_z10_optimize_cmp (rtx insn)
9830 {
9831 rtx prev_insn, next_insn;
9832 bool insn_added_p = false;
9833 rtx cond, *op0, *op1;
9834
9835 if (GET_CODE (PATTERN (insn)) == PARALLEL)
9836 {
9837 /* Handle compare and branch and branch on count
9838 instructions. */
9839 rtx pattern = single_set (insn);
9840
9841 if (!pattern
9842 || SET_DEST (pattern) != pc_rtx
9843 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
9844 return false;
9845
9846 cond = XEXP (SET_SRC (pattern), 0);
9847 op0 = &XEXP (cond, 0);
9848 op1 = &XEXP (cond, 1);
9849 }
9850 else if (GET_CODE (PATTERN (insn)) == SET)
9851 {
9852 rtx src, dest;
9853
9854 /* Handle normal compare instructions. */
9855 src = SET_SRC (PATTERN (insn));
9856 dest = SET_DEST (PATTERN (insn));
9857
9858 if (!REG_P (dest)
9859 || !CC_REGNO_P (REGNO (dest))
9860 || GET_CODE (src) != COMPARE)
9861 return false;
9862
9863 /* s390_swap_cmp will try to find the conditional
9864 jump when passing NULL_RTX as condition. */
9865 cond = NULL_RTX;
9866 op0 = &XEXP (src, 0);
9867 op1 = &XEXP (src, 1);
9868 }
9869 else
9870 return false;
9871
9872 if (!REG_P (*op0) || !REG_P (*op1))
9873 return false;
9874
9875 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
9876 return false;
9877
9878 /* Swap the COMPARE arguments and its mask if there is a
9879 conflicting access in the previous insn. */
9880 prev_insn = prev_active_insn (insn);
9881 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9882 && reg_referenced_p (*op1, PATTERN (prev_insn)))
9883 s390_swap_cmp (cond, op0, op1, insn);
9884
9885 /* Check if there is a conflict with the next insn. If there
9886 was no conflict with the previous insn, then swap the
9887 COMPARE arguments and its mask. If we already swapped
9888 the operands, or if swapping them would cause a conflict
9889 with the previous insn, issue a NOP after the COMPARE in
9890 order to separate the two instuctions. */
9891 next_insn = next_active_insn (insn);
9892 if (next_insn != NULL_RTX && INSN_P (next_insn)
9893 && s390_non_addr_reg_read_p (*op1, next_insn))
9894 {
9895 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9896 && s390_non_addr_reg_read_p (*op0, prev_insn))
9897 {
9898 if (REGNO (*op1) == 0)
9899 emit_insn_after (gen_nop1 (), insn);
9900 else
9901 emit_insn_after (gen_nop (), insn);
9902 insn_added_p = true;
9903 }
9904 else
9905 s390_swap_cmp (cond, op0, op1, insn);
9906 }
9907 return insn_added_p;
9908 }
9909
9910 /* Perform machine-dependent processing. */
9911
9912 static void
9913 s390_reorg (void)
9914 {
9915 bool pool_overflow = false;
9916
9917 /* Make sure all splits have been performed; splits after
9918 machine_dependent_reorg might confuse insn length counts. */
9919 split_all_insns_noflow ();
9920
9921 /* Install the main literal pool and the associated base
9922 register load insns.
9923
9924 In addition, there are two problematic situations we need
9925 to correct:
9926
9927 - the literal pool might be > 4096 bytes in size, so that
9928 some of its elements cannot be directly accessed
9929
9930 - a branch target might be > 64K away from the branch, so that
9931 it is not possible to use a PC-relative instruction.
9932
9933 To fix those, we split the single literal pool into multiple
9934 pool chunks, reloading the pool base register at various
9935 points throughout the function to ensure it always points to
9936 the pool chunk the following code expects, and / or replace
9937 PC-relative branches by absolute branches.
9938
9939 However, the two problems are interdependent: splitting the
9940 literal pool can move a branch further away from its target,
9941 causing the 64K limit to overflow, and on the other hand,
9942 replacing a PC-relative branch by an absolute branch means
9943 we need to put the branch target address into the literal
9944 pool, possibly causing it to overflow.
9945
9946 So, we loop trying to fix up both problems until we manage
9947 to satisfy both conditions at the same time. Note that the
9948 loop is guaranteed to terminate as every pass of the loop
9949 strictly decreases the total number of PC-relative branches
9950 in the function. (This is not completely true as there
9951 might be branch-over-pool insns introduced by chunkify_start.
9952 Those never need to be split however.) */
9953
9954 for (;;)
9955 {
9956 struct constant_pool *pool = NULL;
9957
9958 /* Collect the literal pool. */
9959 if (!pool_overflow)
9960 {
9961 pool = s390_mainpool_start ();
9962 if (!pool)
9963 pool_overflow = true;
9964 }
9965
9966 /* If literal pool overflowed, start to chunkify it. */
9967 if (pool_overflow)
9968 pool = s390_chunkify_start ();
9969
9970 /* Split out-of-range branches. If this has created new
9971 literal pool entries, cancel current chunk list and
9972 recompute it. zSeries machines have large branch
9973 instructions, so we never need to split a branch. */
9974 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9975 {
9976 if (pool_overflow)
9977 s390_chunkify_cancel (pool);
9978 else
9979 s390_mainpool_cancel (pool);
9980
9981 continue;
9982 }
9983
9984 /* If we made it up to here, both conditions are satisfied.
9985 Finish up literal pool related changes. */
9986 if (pool_overflow)
9987 s390_chunkify_finish (pool);
9988 else
9989 s390_mainpool_finish (pool);
9990
9991 /* We're done splitting branches. */
9992 cfun->machine->split_branches_pending_p = false;
9993 break;
9994 }
9995
9996 /* Generate out-of-pool execute target insns. */
9997 if (TARGET_CPU_ZARCH)
9998 {
9999 rtx insn, label, target;
10000
10001 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10002 {
10003 label = s390_execute_label (insn);
10004 if (!label)
10005 continue;
10006
10007 gcc_assert (label != const0_rtx);
10008
10009 target = emit_label (XEXP (label, 0));
10010 INSN_ADDRESSES_NEW (target, -1);
10011
10012 target = emit_insn (s390_execute_target (insn));
10013 INSN_ADDRESSES_NEW (target, -1);
10014 }
10015 }
10016
10017 /* Try to optimize prologue and epilogue further. */
10018 s390_optimize_prologue ();
10019
10020 /* Walk over the insns and do some z10 specific changes. */
10021 if (s390_tune == PROCESSOR_2097_Z10)
10022 {
10023 rtx insn;
10024 bool insn_added_p = false;
10025
10026 /* The insn lengths and addresses have to be up to date for the
10027 following manipulations. */
10028 shorten_branches (get_insns ());
10029
10030 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10031 {
10032 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10033 continue;
10034
10035 if (JUMP_P (insn))
10036 insn_added_p |= s390_z10_fix_long_loop_prediction (insn);
10037
10038 if (GET_CODE (PATTERN (insn)) == PARALLEL
10039 || GET_CODE (PATTERN (insn)) == SET)
10040 insn_added_p |= s390_z10_optimize_cmp (insn);
10041 }
10042
10043 /* Adjust branches if we added new instructions. */
10044 if (insn_added_p)
10045 shorten_branches (get_insns ());
10046 }
10047 }
10048
10049 /* Return true if INSN is a fp load insn writing register REGNO. */
10050 static inline bool
10051 s390_fpload_toreg (rtx insn, unsigned int regno)
10052 {
10053 rtx set;
10054 enum attr_type flag = s390_safe_attr_type (insn);
10055
10056 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10057 return false;
10058
10059 set = single_set (insn);
10060
10061 if (set == NULL_RTX)
10062 return false;
10063
10064 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10065 return false;
10066
10067 if (REGNO (SET_DEST (set)) != regno)
10068 return false;
10069
10070 return true;
10071 }
10072
10073 /* This value describes the distance to be avoided between an
10074 aritmetic fp instruction and an fp load writing the same register.
10075 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10076 fine but the exact value has to be avoided. Otherwise the FP
10077 pipeline will throw an exception causing a major penalty. */
10078 #define Z10_EARLYLOAD_DISTANCE 7
10079
10080 /* Rearrange the ready list in order to avoid the situation described
10081 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10082 moved to the very end of the ready list. */
10083 static void
10084 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10085 {
10086 unsigned int regno;
10087 int nready = *nready_p;
10088 rtx tmp;
10089 int i;
10090 rtx insn;
10091 rtx set;
10092 enum attr_type flag;
10093 int distance;
10094
10095 /* Skip DISTANCE - 1 active insns. */
10096 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10097 distance > 0 && insn != NULL_RTX;
10098 distance--, insn = prev_active_insn (insn))
10099 if (CALL_P (insn) || JUMP_P (insn))
10100 return;
10101
10102 if (insn == NULL_RTX)
10103 return;
10104
10105 set = single_set (insn);
10106
10107 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10108 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10109 return;
10110
10111 flag = s390_safe_attr_type (insn);
10112
10113 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10114 return;
10115
10116 regno = REGNO (SET_DEST (set));
10117 i = nready - 1;
10118
10119 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10120 i--;
10121
10122 if (!i)
10123 return;
10124
10125 tmp = ready[i];
10126 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10127 ready[0] = tmp;
10128 }
10129
10130 /* This function is called via hook TARGET_SCHED_REORDER before
10131 issueing one insn from list READY which contains *NREADYP entries.
10132 For target z10 it reorders load instructions to avoid early load
10133 conflicts in the floating point pipeline */
10134 static int
10135 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10136 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10137 {
10138 if (s390_tune == PROCESSOR_2097_Z10)
10139 if (reload_completed && *nreadyp > 1)
10140 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10141
10142 return s390_issue_rate ();
10143 }
10144
10145 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10146 the scheduler has issued INSN. It stores the last issued insn into
10147 last_scheduled_insn in order to make it available for
10148 s390_sched_reorder. */
10149 static int
10150 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10151 int verbose ATTRIBUTE_UNUSED,
10152 rtx insn, int more)
10153 {
10154 last_scheduled_insn = insn;
10155
10156 if (GET_CODE (PATTERN (insn)) != USE
10157 && GET_CODE (PATTERN (insn)) != CLOBBER)
10158 return more - 1;
10159 else
10160 return more;
10161 }
10162
10163 static void
10164 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10165 int verbose ATTRIBUTE_UNUSED,
10166 int max_ready ATTRIBUTE_UNUSED)
10167 {
10168 last_scheduled_insn = NULL_RTX;
10169 }
10170
10171 /* Initialize GCC target structure. */
10172
10173 #undef TARGET_ASM_ALIGNED_HI_OP
10174 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10175 #undef TARGET_ASM_ALIGNED_DI_OP
10176 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10177 #undef TARGET_ASM_INTEGER
10178 #define TARGET_ASM_INTEGER s390_assemble_integer
10179
10180 #undef TARGET_ASM_OPEN_PAREN
10181 #define TARGET_ASM_OPEN_PAREN ""
10182
10183 #undef TARGET_ASM_CLOSE_PAREN
10184 #define TARGET_ASM_CLOSE_PAREN ""
10185
10186 #undef TARGET_DEFAULT_TARGET_FLAGS
10187 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10188 #undef TARGET_HANDLE_OPTION
10189 #define TARGET_HANDLE_OPTION s390_handle_option
10190
10191 #undef TARGET_ENCODE_SECTION_INFO
10192 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10193
10194 #ifdef HAVE_AS_TLS
10195 #undef TARGET_HAVE_TLS
10196 #define TARGET_HAVE_TLS true
10197 #endif
10198 #undef TARGET_CANNOT_FORCE_CONST_MEM
10199 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10200
10201 #undef TARGET_DELEGITIMIZE_ADDRESS
10202 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10203
10204 #undef TARGET_LEGITIMIZE_ADDRESS
10205 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10206
10207 #undef TARGET_RETURN_IN_MEMORY
10208 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10209
10210 #undef TARGET_INIT_BUILTINS
10211 #define TARGET_INIT_BUILTINS s390_init_builtins
10212 #undef TARGET_EXPAND_BUILTIN
10213 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10214
10215 #undef TARGET_ASM_OUTPUT_MI_THUNK
10216 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10217 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10218 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10219
10220 #undef TARGET_SCHED_ADJUST_PRIORITY
10221 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10222 #undef TARGET_SCHED_ISSUE_RATE
10223 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10224 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10225 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10226
10227 #undef TARGET_SCHED_VARIABLE_ISSUE
10228 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10229 #undef TARGET_SCHED_REORDER
10230 #define TARGET_SCHED_REORDER s390_sched_reorder
10231 #undef TARGET_SCHED_INIT
10232 #define TARGET_SCHED_INIT s390_sched_init
10233
10234 #undef TARGET_CANNOT_COPY_INSN_P
10235 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10236 #undef TARGET_RTX_COSTS
10237 #define TARGET_RTX_COSTS s390_rtx_costs
10238 #undef TARGET_ADDRESS_COST
10239 #define TARGET_ADDRESS_COST s390_address_cost
10240
10241 #undef TARGET_MACHINE_DEPENDENT_REORG
10242 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10243
10244 #undef TARGET_VALID_POINTER_MODE
10245 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10246
10247 #undef TARGET_BUILD_BUILTIN_VA_LIST
10248 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10249 #undef TARGET_EXPAND_BUILTIN_VA_START
10250 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10251 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10252 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10253
10254 #undef TARGET_PROMOTE_FUNCTION_MODE
10255 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10256 #undef TARGET_PASS_BY_REFERENCE
10257 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10258
10259 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10260 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10261
10262 #undef TARGET_FIXED_CONDITION_CODE_REGS
10263 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10264
10265 #undef TARGET_CC_MODES_COMPATIBLE
10266 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10267
10268 #undef TARGET_INVALID_WITHIN_DOLOOP
10269 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10270
10271 #ifdef HAVE_AS_TLS
10272 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10273 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10274 #endif
10275
10276 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10277 #undef TARGET_MANGLE_TYPE
10278 #define TARGET_MANGLE_TYPE s390_mangle_type
10279 #endif
10280
10281 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10282 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10283
10284 #undef TARGET_SECONDARY_RELOAD
10285 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10286
10287 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10288 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10289
10290 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10291 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10292
10293 #undef TARGET_LEGITIMATE_ADDRESS_P
10294 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10295
10296 #undef TARGET_CAN_ELIMINATE
10297 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10298
10299 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10300 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10301 #undef TARGET_TRAMPOLINE_INIT
10302 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10303
10304 struct gcc_target targetm = TARGET_INITIALIZER;
10305
10306 #include "gt-s390.h"