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s390.opt ("mhard-float", [...]): Bit value inverted and documentation adjusted.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 02110-1301, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "tree-gimple.h"
54
55
56 /* Define the specific costs for a given cpu. */
57
58 struct processor_costs
59 {
60 /* multiplication */
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
74 const int mxbr;
75 /* square root */
76 const int sqxbr; /* cost of square root in TFmode. */
77 const int sqdbr; /* cost of square root in DFmode. */
78 const int sqebr; /* cost of square root in SFmode. */
79 /* multiply and add */
80 const int madbr; /* cost of multiply and add in DFmode. */
81 const int maebr; /* cost of multiply and add in SFmode. */
82 /* division */
83 const int dxbr;
84 const int dxr;
85 const int ddbr;
86 const int ddr;
87 const int debr;
88 const int der;
89 const int dlgr;
90 const int dlr;
91 const int dr;
92 const int dsgfr;
93 const int dsgr;
94 };
95
96 const struct processor_costs *s390_cost;
97
98 static const
99 struct processor_costs z900_cost =
100 {
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (135), /* DXR */
122 COSTS_N_INSNS (30), /* DDBR */
123 COSTS_N_INSNS (30), /* DDR */
124 COSTS_N_INSNS (27), /* DEBR */
125 COSTS_N_INSNS (26), /* DER */
126 COSTS_N_INSNS (220), /* DLGR */
127 COSTS_N_INSNS (34), /* DLR */
128 COSTS_N_INSNS (34), /* DR */
129 COSTS_N_INSNS (32), /* DSGFR */
130 COSTS_N_INSNS (32), /* DSGR */
131 };
132
133 static const
134 struct processor_costs z990_cost =
135 {
136 COSTS_N_INSNS (4), /* M */
137 COSTS_N_INSNS (2), /* MGHI */
138 COSTS_N_INSNS (2), /* MH */
139 COSTS_N_INSNS (2), /* MHI */
140 COSTS_N_INSNS (4), /* ML */
141 COSTS_N_INSNS (4), /* MR */
142 COSTS_N_INSNS (5), /* MS */
143 COSTS_N_INSNS (6), /* MSG */
144 COSTS_N_INSNS (4), /* MSGF */
145 COSTS_N_INSNS (4), /* MSGFR */
146 COSTS_N_INSNS (4), /* MSGR */
147 COSTS_N_INSNS (4), /* MSR */
148 COSTS_N_INSNS (1), /* multiplication in DFmode */
149 COSTS_N_INSNS (28), /* MXBR */
150 COSTS_N_INSNS (130), /* SQXBR */
151 COSTS_N_INSNS (66), /* SQDBR */
152 COSTS_N_INSNS (38), /* SQEBR */
153 COSTS_N_INSNS (1), /* MADBR */
154 COSTS_N_INSNS (1), /* MAEBR */
155 COSTS_N_INSNS (60), /* DXBR */
156 COSTS_N_INSNS (72), /* DXR */
157 COSTS_N_INSNS (40), /* DDBR */
158 COSTS_N_INSNS (44), /* DDR */
159 COSTS_N_INSNS (26), /* DDBR */
160 COSTS_N_INSNS (28), /* DER */
161 COSTS_N_INSNS (176), /* DLGR */
162 COSTS_N_INSNS (31), /* DLR */
163 COSTS_N_INSNS (31), /* DR */
164 COSTS_N_INSNS (31), /* DSGFR */
165 COSTS_N_INSNS (31), /* DSGR */
166 };
167
168 static const
169 struct processor_costs z9_109_cost =
170 {
171 COSTS_N_INSNS (4), /* M */
172 COSTS_N_INSNS (2), /* MGHI */
173 COSTS_N_INSNS (2), /* MH */
174 COSTS_N_INSNS (2), /* MHI */
175 COSTS_N_INSNS (4), /* ML */
176 COSTS_N_INSNS (4), /* MR */
177 COSTS_N_INSNS (5), /* MS */
178 COSTS_N_INSNS (6), /* MSG */
179 COSTS_N_INSNS (4), /* MSGF */
180 COSTS_N_INSNS (4), /* MSGFR */
181 COSTS_N_INSNS (4), /* MSGR */
182 COSTS_N_INSNS (4), /* MSR */
183 COSTS_N_INSNS (1), /* multiplication in DFmode */
184 COSTS_N_INSNS (28), /* MXBR */
185 COSTS_N_INSNS (130), /* SQXBR */
186 COSTS_N_INSNS (66), /* SQDBR */
187 COSTS_N_INSNS (38), /* SQEBR */
188 COSTS_N_INSNS (1), /* MADBR */
189 COSTS_N_INSNS (1), /* MAEBR */
190 COSTS_N_INSNS (60), /* DXBR */
191 COSTS_N_INSNS (72), /* DXR */
192 COSTS_N_INSNS (40), /* DDBR */
193 COSTS_N_INSNS (37), /* DDR */
194 COSTS_N_INSNS (26), /* DDBR */
195 COSTS_N_INSNS (28), /* DER */
196 COSTS_N_INSNS (30), /* DLGR */
197 COSTS_N_INSNS (23), /* DLR */
198 COSTS_N_INSNS (23), /* DR */
199 COSTS_N_INSNS (24), /* DSGFR */
200 COSTS_N_INSNS (24), /* DSGR */
201 };
202
203 extern int reload_completed;
204
205 /* Save information from a "cmpxx" operation until the branch or scc is
206 emitted. */
207 rtx s390_compare_op0, s390_compare_op1;
208
209 /* Save the result of a compare_and_swap until the branch or scc is
210 emitted. */
211 rtx s390_compare_emitted = NULL_RTX;
212
213 /* Structure used to hold the components of a S/390 memory
214 address. A legitimate address on S/390 is of the general
215 form
216 base + index + displacement
217 where any of the components is optional.
218
219 base and index are registers of the class ADDR_REGS,
220 displacement is an unsigned 12-bit immediate constant. */
221
222 struct s390_address
223 {
224 rtx base;
225 rtx indx;
226 rtx disp;
227 bool pointer;
228 bool literal_pool;
229 };
230
231 /* Which cpu are we tuning for. */
232 enum processor_type s390_tune = PROCESSOR_max;
233 enum processor_flags s390_tune_flags;
234 /* Which instruction set architecture to use. */
235 enum processor_type s390_arch;
236 enum processor_flags s390_arch_flags;
237
238 HOST_WIDE_INT s390_warn_framesize = 0;
239 HOST_WIDE_INT s390_stack_size = 0;
240 HOST_WIDE_INT s390_stack_guard = 0;
241
242 /* The following structure is embedded in the machine
243 specific part of struct function. */
244
245 struct s390_frame_layout GTY (())
246 {
247 /* Offset within stack frame. */
248 HOST_WIDE_INT gprs_offset;
249 HOST_WIDE_INT f0_offset;
250 HOST_WIDE_INT f4_offset;
251 HOST_WIDE_INT f8_offset;
252 HOST_WIDE_INT backchain_offset;
253
254 /* Number of first and last gpr where slots in the register
255 save area are reserved for. */
256 int first_save_gpr_slot;
257 int last_save_gpr_slot;
258
259 /* Number of first and last gpr to be saved, restored. */
260 int first_save_gpr;
261 int first_restore_gpr;
262 int last_save_gpr;
263 int last_restore_gpr;
264
265 /* Bits standing for floating point registers. Set, if the
266 respective register has to be saved. Starting with reg 16 (f0)
267 at the rightmost bit.
268 Bit 15 - 8 7 6 5 4 3 2 1 0
269 fpr 15 - 8 7 5 3 1 6 4 2 0
270 reg 31 - 24 23 22 21 20 19 18 17 16 */
271 unsigned int fpr_bitmap;
272
273 /* Number of floating point registers f8-f15 which must be saved. */
274 int high_fprs;
275
276 /* Set if return address needs to be saved.
277 This flag is set by s390_return_addr_rtx if it could not use
278 the initial value of r14 and therefore depends on r14 saved
279 to the stack. */
280 bool save_return_addr_p;
281
282 /* Size of stack frame. */
283 HOST_WIDE_INT frame_size;
284 };
285
286 /* Define the structure for the machine field in struct function. */
287
288 struct machine_function GTY(())
289 {
290 struct s390_frame_layout frame_layout;
291
292 /* Literal pool base register. */
293 rtx base_reg;
294
295 /* True if we may need to perform branch splitting. */
296 bool split_branches_pending_p;
297
298 /* True during final stage of literal pool processing. */
299 bool decomposed_literal_pool_addresses_ok_p;
300
301 /* Some local-dynamic TLS symbol name. */
302 const char *some_ld_name;
303
304 bool has_landing_pad_p;
305 };
306
307 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
308
309 #define cfun_frame_layout (cfun->machine->frame_layout)
310 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
311 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
312 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
313 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
314 (1 << (BITNUM)))
315 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
316 (1 << (BITNUM))))
317
318 /* Number of GPRs and FPRs used for argument passing. */
319 #define GP_ARG_NUM_REG 5
320 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
321
322 /* A couple of shortcuts. */
323 #define CONST_OK_FOR_J(x) \
324 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
325 #define CONST_OK_FOR_K(x) \
326 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
327 #define CONST_OK_FOR_Os(x) \
328 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
329 #define CONST_OK_FOR_Op(x) \
330 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
331 #define CONST_OK_FOR_On(x) \
332 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
333
334 #define REGNO_PAIR_OK(REGNO, MODE) \
335 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
336
337 /* Return true if the back end supports mode MODE. */
338 static bool
339 s390_scalar_mode_supported_p (enum machine_mode mode)
340 {
341 if (DECIMAL_FLOAT_MODE_P (mode))
342 return true;
343 else
344 return default_scalar_mode_supported_p (mode);
345 }
346
347 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
348
349 void
350 s390_set_has_landing_pad_p (bool value)
351 {
352 cfun->machine->has_landing_pad_p = value;
353 }
354
355 /* If two condition code modes are compatible, return a condition code
356 mode which is compatible with both. Otherwise, return
357 VOIDmode. */
358
359 static enum machine_mode
360 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
361 {
362 if (m1 == m2)
363 return m1;
364
365 switch (m1)
366 {
367 case CCZmode:
368 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
369 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
370 return m2;
371 return VOIDmode;
372
373 case CCSmode:
374 case CCUmode:
375 case CCTmode:
376 case CCSRmode:
377 case CCURmode:
378 case CCZ1mode:
379 if (m2 == CCZmode)
380 return m1;
381
382 return VOIDmode;
383
384 default:
385 return VOIDmode;
386 }
387 return VOIDmode;
388 }
389
390 /* Return true if SET either doesn't set the CC register, or else
391 the source and destination have matching CC modes and that
392 CC mode is at least as constrained as REQ_MODE. */
393
394 static bool
395 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
396 {
397 enum machine_mode set_mode;
398
399 gcc_assert (GET_CODE (set) == SET);
400
401 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
402 return 1;
403
404 set_mode = GET_MODE (SET_DEST (set));
405 switch (set_mode)
406 {
407 case CCSmode:
408 case CCSRmode:
409 case CCUmode:
410 case CCURmode:
411 case CCLmode:
412 case CCL1mode:
413 case CCL2mode:
414 case CCL3mode:
415 case CCT1mode:
416 case CCT2mode:
417 case CCT3mode:
418 if (req_mode != set_mode)
419 return 0;
420 break;
421
422 case CCZmode:
423 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
424 && req_mode != CCSRmode && req_mode != CCURmode)
425 return 0;
426 break;
427
428 case CCAPmode:
429 case CCANmode:
430 if (req_mode != CCAmode)
431 return 0;
432 break;
433
434 default:
435 gcc_unreachable ();
436 }
437
438 return (GET_MODE (SET_SRC (set)) == set_mode);
439 }
440
441 /* Return true if every SET in INSN that sets the CC register
442 has source and destination with matching CC modes and that
443 CC mode is at least as constrained as REQ_MODE.
444 If REQ_MODE is VOIDmode, always return false. */
445
446 bool
447 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
448 {
449 int i;
450
451 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
452 if (req_mode == VOIDmode)
453 return false;
454
455 if (GET_CODE (PATTERN (insn)) == SET)
456 return s390_match_ccmode_set (PATTERN (insn), req_mode);
457
458 if (GET_CODE (PATTERN (insn)) == PARALLEL)
459 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
460 {
461 rtx set = XVECEXP (PATTERN (insn), 0, i);
462 if (GET_CODE (set) == SET)
463 if (!s390_match_ccmode_set (set, req_mode))
464 return false;
465 }
466
467 return true;
468 }
469
470 /* If a test-under-mask instruction can be used to implement
471 (compare (and ... OP1) OP2), return the CC mode required
472 to do that. Otherwise, return VOIDmode.
473 MIXED is true if the instruction can distinguish between
474 CC1 and CC2 for mixed selected bits (TMxx), it is false
475 if the instruction cannot (TM). */
476
477 enum machine_mode
478 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
479 {
480 int bit0, bit1;
481
482 /* ??? Fixme: should work on CONST_DOUBLE as well. */
483 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
484 return VOIDmode;
485
486 /* Selected bits all zero: CC0.
487 e.g.: int a; if ((a & (16 + 128)) == 0) */
488 if (INTVAL (op2) == 0)
489 return CCTmode;
490
491 /* Selected bits all one: CC3.
492 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
493 if (INTVAL (op2) == INTVAL (op1))
494 return CCT3mode;
495
496 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
497 int a;
498 if ((a & (16 + 128)) == 16) -> CCT1
499 if ((a & (16 + 128)) == 128) -> CCT2 */
500 if (mixed)
501 {
502 bit1 = exact_log2 (INTVAL (op2));
503 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
504 if (bit0 != -1 && bit1 != -1)
505 return bit0 > bit1 ? CCT1mode : CCT2mode;
506 }
507
508 return VOIDmode;
509 }
510
511 /* Given a comparison code OP (EQ, NE, etc.) and the operands
512 OP0 and OP1 of a COMPARE, return the mode to be used for the
513 comparison. */
514
515 enum machine_mode
516 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
517 {
518 switch (code)
519 {
520 case EQ:
521 case NE:
522 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
523 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
524 return CCAPmode;
525 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
526 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
527 return CCAPmode;
528 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
529 || GET_CODE (op1) == NEG)
530 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
531 return CCLmode;
532
533 if (GET_CODE (op0) == AND)
534 {
535 /* Check whether we can potentially do it via TM. */
536 enum machine_mode ccmode;
537 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
538 if (ccmode != VOIDmode)
539 {
540 /* Relax CCTmode to CCZmode to allow fall-back to AND
541 if that turns out to be beneficial. */
542 return ccmode == CCTmode ? CCZmode : ccmode;
543 }
544 }
545
546 if (register_operand (op0, HImode)
547 && GET_CODE (op1) == CONST_INT
548 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
549 return CCT3mode;
550 if (register_operand (op0, QImode)
551 && GET_CODE (op1) == CONST_INT
552 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
553 return CCT3mode;
554
555 return CCZmode;
556
557 case LE:
558 case LT:
559 case GE:
560 case GT:
561 /* The only overflow condition of NEG and ABS happens when
562 -INT_MAX is used as parameter, which stays negative. So
563 we have an overflow from a positive value to a negative.
564 Using CCAP mode the resulting cc can be used for comparisons. */
565 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
566 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
567 return CCAPmode;
568
569 /* If constants are involved in an add instruction it is possible to use
570 the resulting cc for comparisons with zero. Knowing the sign of the
571 constant the overflow behavior gets predictable. e.g.:
572 int a, b; if ((b = a + c) > 0)
573 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
574 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
575 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
576 {
577 if (INTVAL (XEXP((op0), 1)) < 0)
578 return CCANmode;
579 else
580 return CCAPmode;
581 }
582 /* Fall through. */
583 case UNORDERED:
584 case ORDERED:
585 case UNEQ:
586 case UNLE:
587 case UNLT:
588 case UNGE:
589 case UNGT:
590 case LTGT:
591 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
592 && GET_CODE (op1) != CONST_INT)
593 return CCSRmode;
594 return CCSmode;
595
596 case LTU:
597 case GEU:
598 if (GET_CODE (op0) == PLUS
599 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
600 return CCL1mode;
601
602 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
603 && GET_CODE (op1) != CONST_INT)
604 return CCURmode;
605 return CCUmode;
606
607 case LEU:
608 case GTU:
609 if (GET_CODE (op0) == MINUS
610 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
611 return CCL2mode;
612
613 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
614 && GET_CODE (op1) != CONST_INT)
615 return CCURmode;
616 return CCUmode;
617
618 default:
619 gcc_unreachable ();
620 }
621 }
622
623 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
624 that we can implement more efficiently. */
625
626 void
627 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
628 {
629 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
630 if ((*code == EQ || *code == NE)
631 && *op1 == const0_rtx
632 && GET_CODE (*op0) == ZERO_EXTRACT
633 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
634 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
635 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
636 {
637 rtx inner = XEXP (*op0, 0);
638 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
639 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
640 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
641
642 if (len > 0 && len < modesize
643 && pos >= 0 && pos + len <= modesize
644 && modesize <= HOST_BITS_PER_WIDE_INT)
645 {
646 unsigned HOST_WIDE_INT block;
647 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
648 block <<= modesize - pos - len;
649
650 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
651 gen_int_mode (block, GET_MODE (inner)));
652 }
653 }
654
655 /* Narrow AND of memory against immediate to enable TM. */
656 if ((*code == EQ || *code == NE)
657 && *op1 == const0_rtx
658 && GET_CODE (*op0) == AND
659 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
660 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
661 {
662 rtx inner = XEXP (*op0, 0);
663 rtx mask = XEXP (*op0, 1);
664
665 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
666 if (GET_CODE (inner) == SUBREG
667 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
668 && (GET_MODE_SIZE (GET_MODE (inner))
669 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
670 && ((INTVAL (mask)
671 & GET_MODE_MASK (GET_MODE (inner))
672 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
673 == 0))
674 inner = SUBREG_REG (inner);
675
676 /* Do not change volatile MEMs. */
677 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
678 {
679 int part = s390_single_part (XEXP (*op0, 1),
680 GET_MODE (inner), QImode, 0);
681 if (part >= 0)
682 {
683 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
684 inner = adjust_address_nv (inner, QImode, part);
685 *op0 = gen_rtx_AND (QImode, inner, mask);
686 }
687 }
688 }
689
690 /* Narrow comparisons against 0xffff to HImode if possible. */
691 if ((*code == EQ || *code == NE)
692 && GET_CODE (*op1) == CONST_INT
693 && INTVAL (*op1) == 0xffff
694 && SCALAR_INT_MODE_P (GET_MODE (*op0))
695 && (nonzero_bits (*op0, GET_MODE (*op0))
696 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
697 {
698 *op0 = gen_lowpart (HImode, *op0);
699 *op1 = constm1_rtx;
700 }
701
702
703 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
704 if (GET_CODE (*op0) == UNSPEC
705 && XINT (*op0, 1) == UNSPEC_CMPINT
706 && XVECLEN (*op0, 0) == 1
707 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
708 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
709 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
710 && *op1 == const0_rtx)
711 {
712 enum rtx_code new_code = UNKNOWN;
713 switch (*code)
714 {
715 case EQ: new_code = EQ; break;
716 case NE: new_code = NE; break;
717 case LT: new_code = GTU; break;
718 case GT: new_code = LTU; break;
719 case LE: new_code = GEU; break;
720 case GE: new_code = LEU; break;
721 default: break;
722 }
723
724 if (new_code != UNKNOWN)
725 {
726 *op0 = XVECEXP (*op0, 0, 0);
727 *code = new_code;
728 }
729 }
730
731 /* Simplify cascaded EQ, NE with const0_rtx. */
732 if ((*code == NE || *code == EQ)
733 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
734 && GET_MODE (*op0) == SImode
735 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
736 && REG_P (XEXP (*op0, 0))
737 && XEXP (*op0, 1) == const0_rtx
738 && *op1 == const0_rtx)
739 {
740 if ((*code == EQ && GET_CODE (*op0) == NE)
741 || (*code == NE && GET_CODE (*op0) == EQ))
742 *code = EQ;
743 else
744 *code = NE;
745 *op0 = XEXP (*op0, 0);
746 }
747
748 /* Prefer register over memory as first operand. */
749 if (MEM_P (*op0) && REG_P (*op1))
750 {
751 rtx tem = *op0; *op0 = *op1; *op1 = tem;
752 *code = swap_condition (*code);
753 }
754 }
755
756 /* Emit a compare instruction suitable to implement the comparison
757 OP0 CODE OP1. Return the correct condition RTL to be placed in
758 the IF_THEN_ELSE of the conditional branch testing the result. */
759
760 rtx
761 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
762 {
763 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
764 rtx ret = NULL_RTX;
765
766 /* Do not output a redundant compare instruction if a compare_and_swap
767 pattern already computed the result and the machine modes are compatible. */
768 if (s390_compare_emitted
769 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
770 == GET_MODE (s390_compare_emitted)))
771 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
772 else
773 {
774 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
775
776 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
777 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
778 }
779 s390_compare_emitted = NULL_RTX;
780 return ret;
781 }
782
783 /* Emit a SImode compare and swap instruction setting MEM to NEW if OLD
784 matches CMP.
785 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
786 conditional branch testing the result. */
787
788 static rtx
789 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new)
790 {
791 rtx ret;
792
793 emit_insn (gen_sync_compare_and_swap_ccsi (old, mem, cmp, new));
794 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
795
796 s390_compare_emitted = NULL_RTX;
797
798 return ret;
799 }
800
801 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
802 unconditional jump, else a conditional jump under condition COND. */
803
804 void
805 s390_emit_jump (rtx target, rtx cond)
806 {
807 rtx insn;
808
809 target = gen_rtx_LABEL_REF (VOIDmode, target);
810 if (cond)
811 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
812
813 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
814 emit_jump_insn (insn);
815 }
816
817 /* Return branch condition mask to implement a branch
818 specified by CODE. Return -1 for invalid comparisons. */
819
820 int
821 s390_branch_condition_mask (rtx code)
822 {
823 const int CC0 = 1 << 3;
824 const int CC1 = 1 << 2;
825 const int CC2 = 1 << 1;
826 const int CC3 = 1 << 0;
827
828 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
829 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
830 gcc_assert (XEXP (code, 1) == const0_rtx);
831
832 switch (GET_MODE (XEXP (code, 0)))
833 {
834 case CCZmode:
835 case CCZ1mode:
836 switch (GET_CODE (code))
837 {
838 case EQ: return CC0;
839 case NE: return CC1 | CC2 | CC3;
840 default: return -1;
841 }
842 break;
843
844 case CCT1mode:
845 switch (GET_CODE (code))
846 {
847 case EQ: return CC1;
848 case NE: return CC0 | CC2 | CC3;
849 default: return -1;
850 }
851 break;
852
853 case CCT2mode:
854 switch (GET_CODE (code))
855 {
856 case EQ: return CC2;
857 case NE: return CC0 | CC1 | CC3;
858 default: return -1;
859 }
860 break;
861
862 case CCT3mode:
863 switch (GET_CODE (code))
864 {
865 case EQ: return CC3;
866 case NE: return CC0 | CC1 | CC2;
867 default: return -1;
868 }
869 break;
870
871 case CCLmode:
872 switch (GET_CODE (code))
873 {
874 case EQ: return CC0 | CC2;
875 case NE: return CC1 | CC3;
876 default: return -1;
877 }
878 break;
879
880 case CCL1mode:
881 switch (GET_CODE (code))
882 {
883 case LTU: return CC2 | CC3; /* carry */
884 case GEU: return CC0 | CC1; /* no carry */
885 default: return -1;
886 }
887 break;
888
889 case CCL2mode:
890 switch (GET_CODE (code))
891 {
892 case GTU: return CC0 | CC1; /* borrow */
893 case LEU: return CC2 | CC3; /* no borrow */
894 default: return -1;
895 }
896 break;
897
898 case CCL3mode:
899 switch (GET_CODE (code))
900 {
901 case EQ: return CC0 | CC2;
902 case NE: return CC1 | CC3;
903 case LTU: return CC1;
904 case GTU: return CC3;
905 case LEU: return CC1 | CC2;
906 case GEU: return CC2 | CC3;
907 default: return -1;
908 }
909
910 case CCUmode:
911 switch (GET_CODE (code))
912 {
913 case EQ: return CC0;
914 case NE: return CC1 | CC2 | CC3;
915 case LTU: return CC1;
916 case GTU: return CC2;
917 case LEU: return CC0 | CC1;
918 case GEU: return CC0 | CC2;
919 default: return -1;
920 }
921 break;
922
923 case CCURmode:
924 switch (GET_CODE (code))
925 {
926 case EQ: return CC0;
927 case NE: return CC2 | CC1 | CC3;
928 case LTU: return CC2;
929 case GTU: return CC1;
930 case LEU: return CC0 | CC2;
931 case GEU: return CC0 | CC1;
932 default: return -1;
933 }
934 break;
935
936 case CCAPmode:
937 switch (GET_CODE (code))
938 {
939 case EQ: return CC0;
940 case NE: return CC1 | CC2 | CC3;
941 case LT: return CC1 | CC3;
942 case GT: return CC2;
943 case LE: return CC0 | CC1 | CC3;
944 case GE: return CC0 | CC2;
945 default: return -1;
946 }
947 break;
948
949 case CCANmode:
950 switch (GET_CODE (code))
951 {
952 case EQ: return CC0;
953 case NE: return CC1 | CC2 | CC3;
954 case LT: return CC1;
955 case GT: return CC2 | CC3;
956 case LE: return CC0 | CC1;
957 case GE: return CC0 | CC2 | CC3;
958 default: return -1;
959 }
960 break;
961
962 case CCSmode:
963 switch (GET_CODE (code))
964 {
965 case EQ: return CC0;
966 case NE: return CC1 | CC2 | CC3;
967 case LT: return CC1;
968 case GT: return CC2;
969 case LE: return CC0 | CC1;
970 case GE: return CC0 | CC2;
971 case UNORDERED: return CC3;
972 case ORDERED: return CC0 | CC1 | CC2;
973 case UNEQ: return CC0 | CC3;
974 case UNLT: return CC1 | CC3;
975 case UNGT: return CC2 | CC3;
976 case UNLE: return CC0 | CC1 | CC3;
977 case UNGE: return CC0 | CC2 | CC3;
978 case LTGT: return CC1 | CC2;
979 default: return -1;
980 }
981 break;
982
983 case CCSRmode:
984 switch (GET_CODE (code))
985 {
986 case EQ: return CC0;
987 case NE: return CC2 | CC1 | CC3;
988 case LT: return CC2;
989 case GT: return CC1;
990 case LE: return CC0 | CC2;
991 case GE: return CC0 | CC1;
992 case UNORDERED: return CC3;
993 case ORDERED: return CC0 | CC2 | CC1;
994 case UNEQ: return CC0 | CC3;
995 case UNLT: return CC2 | CC3;
996 case UNGT: return CC1 | CC3;
997 case UNLE: return CC0 | CC2 | CC3;
998 case UNGE: return CC0 | CC1 | CC3;
999 case LTGT: return CC2 | CC1;
1000 default: return -1;
1001 }
1002 break;
1003
1004 default:
1005 return -1;
1006 }
1007 }
1008
1009 /* If INV is false, return assembler mnemonic string to implement
1010 a branch specified by CODE. If INV is true, return mnemonic
1011 for the corresponding inverted branch. */
1012
1013 static const char *
1014 s390_branch_condition_mnemonic (rtx code, int inv)
1015 {
1016 static const char *const mnemonic[16] =
1017 {
1018 NULL, "o", "h", "nle",
1019 "l", "nhe", "lh", "ne",
1020 "e", "nlh", "he", "nl",
1021 "le", "nh", "no", NULL
1022 };
1023
1024 int mask = s390_branch_condition_mask (code);
1025 gcc_assert (mask >= 0);
1026
1027 if (inv)
1028 mask ^= 15;
1029
1030 gcc_assert (mask >= 1 && mask <= 14);
1031
1032 return mnemonic[mask];
1033 }
1034
1035 /* Return the part of op which has a value different from def.
1036 The size of the part is determined by mode.
1037 Use this function only if you already know that op really
1038 contains such a part. */
1039
1040 unsigned HOST_WIDE_INT
1041 s390_extract_part (rtx op, enum machine_mode mode, int def)
1042 {
1043 unsigned HOST_WIDE_INT value = 0;
1044 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1045 int part_bits = GET_MODE_BITSIZE (mode);
1046 unsigned HOST_WIDE_INT part_mask
1047 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1048 int i;
1049
1050 for (i = 0; i < max_parts; i++)
1051 {
1052 if (i == 0)
1053 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1054 else
1055 value >>= part_bits;
1056
1057 if ((value & part_mask) != (def & part_mask))
1058 return value & part_mask;
1059 }
1060
1061 gcc_unreachable ();
1062 }
1063
1064 /* If OP is an integer constant of mode MODE with exactly one
1065 part of mode PART_MODE unequal to DEF, return the number of that
1066 part. Otherwise, return -1. */
1067
1068 int
1069 s390_single_part (rtx op,
1070 enum machine_mode mode,
1071 enum machine_mode part_mode,
1072 int def)
1073 {
1074 unsigned HOST_WIDE_INT value = 0;
1075 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1076 unsigned HOST_WIDE_INT part_mask
1077 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1078 int i, part = -1;
1079
1080 if (GET_CODE (op) != CONST_INT)
1081 return -1;
1082
1083 for (i = 0; i < n_parts; i++)
1084 {
1085 if (i == 0)
1086 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1087 else
1088 value >>= GET_MODE_BITSIZE (part_mode);
1089
1090 if ((value & part_mask) != (def & part_mask))
1091 {
1092 if (part != -1)
1093 return -1;
1094 else
1095 part = i;
1096 }
1097 }
1098 return part == -1 ? -1 : n_parts - 1 - part;
1099 }
1100
1101 /* Check whether we can (and want to) split a double-word
1102 move in mode MODE from SRC to DST into two single-word
1103 moves, moving the subword FIRST_SUBWORD first. */
1104
1105 bool
1106 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1107 {
1108 /* Floating point registers cannot be split. */
1109 if (FP_REG_P (src) || FP_REG_P (dst))
1110 return false;
1111
1112 /* We don't need to split if operands are directly accessible. */
1113 if (s_operand (src, mode) || s_operand (dst, mode))
1114 return false;
1115
1116 /* Non-offsettable memory references cannot be split. */
1117 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1118 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1119 return false;
1120
1121 /* Moving the first subword must not clobber a register
1122 needed to move the second subword. */
1123 if (register_operand (dst, mode))
1124 {
1125 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1126 if (reg_overlap_mentioned_p (subreg, src))
1127 return false;
1128 }
1129
1130 return true;
1131 }
1132
1133 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1134 and [MEM2, MEM2 + SIZE] do overlap and false
1135 otherwise. */
1136
1137 bool
1138 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1139 {
1140 rtx addr1, addr2, addr_delta;
1141 HOST_WIDE_INT delta;
1142
1143 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1144 return true;
1145
1146 if (size == 0)
1147 return false;
1148
1149 addr1 = XEXP (mem1, 0);
1150 addr2 = XEXP (mem2, 0);
1151
1152 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1153
1154 /* This overlapping check is used by peepholes merging memory block operations.
1155 Overlapping operations would otherwise be recognized by the S/390 hardware
1156 and would fall back to a slower implementation. Allowing overlapping
1157 operations would lead to slow code but not to wrong code. Therefore we are
1158 somewhat optimistic if we cannot prove that the memory blocks are
1159 overlapping.
1160 That's why we return false here although this may accept operations on
1161 overlapping memory areas. */
1162 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1163 return false;
1164
1165 delta = INTVAL (addr_delta);
1166
1167 if (delta == 0
1168 || (delta > 0 && delta < size)
1169 || (delta < 0 && -delta < size))
1170 return true;
1171
1172 return false;
1173 }
1174
1175 /* Check whether the address of memory reference MEM2 equals exactly
1176 the address of memory reference MEM1 plus DELTA. Return true if
1177 we can prove this to be the case, false otherwise. */
1178
1179 bool
1180 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1181 {
1182 rtx addr1, addr2, addr_delta;
1183
1184 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1185 return false;
1186
1187 addr1 = XEXP (mem1, 0);
1188 addr2 = XEXP (mem2, 0);
1189
1190 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1191 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1192 return false;
1193
1194 return true;
1195 }
1196
1197 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1198
1199 void
1200 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1201 rtx *operands)
1202 {
1203 enum machine_mode wmode = mode;
1204 rtx dst = operands[0];
1205 rtx src1 = operands[1];
1206 rtx src2 = operands[2];
1207 rtx op, clob, tem;
1208
1209 /* If we cannot handle the operation directly, use a temp register. */
1210 if (!s390_logical_operator_ok_p (operands))
1211 dst = gen_reg_rtx (mode);
1212
1213 /* QImode and HImode patterns make sense only if we have a destination
1214 in memory. Otherwise perform the operation in SImode. */
1215 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1216 wmode = SImode;
1217
1218 /* Widen operands if required. */
1219 if (mode != wmode)
1220 {
1221 if (GET_CODE (dst) == SUBREG
1222 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1223 dst = tem;
1224 else if (REG_P (dst))
1225 dst = gen_rtx_SUBREG (wmode, dst, 0);
1226 else
1227 dst = gen_reg_rtx (wmode);
1228
1229 if (GET_CODE (src1) == SUBREG
1230 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1231 src1 = tem;
1232 else if (GET_MODE (src1) != VOIDmode)
1233 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1234
1235 if (GET_CODE (src2) == SUBREG
1236 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1237 src2 = tem;
1238 else if (GET_MODE (src2) != VOIDmode)
1239 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1240 }
1241
1242 /* Emit the instruction. */
1243 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1244 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1245 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1246
1247 /* Fix up the destination if needed. */
1248 if (dst != operands[0])
1249 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1250 }
1251
1252 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1253
1254 bool
1255 s390_logical_operator_ok_p (rtx *operands)
1256 {
1257 /* If the destination operand is in memory, it needs to coincide
1258 with one of the source operands. After reload, it has to be
1259 the first source operand. */
1260 if (GET_CODE (operands[0]) == MEM)
1261 return rtx_equal_p (operands[0], operands[1])
1262 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1263
1264 return true;
1265 }
1266
1267 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1268 operand IMMOP to switch from SS to SI type instructions. */
1269
1270 void
1271 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1272 {
1273 int def = code == AND ? -1 : 0;
1274 HOST_WIDE_INT mask;
1275 int part;
1276
1277 gcc_assert (GET_CODE (*memop) == MEM);
1278 gcc_assert (!MEM_VOLATILE_P (*memop));
1279
1280 mask = s390_extract_part (*immop, QImode, def);
1281 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1282 gcc_assert (part >= 0);
1283
1284 *memop = adjust_address (*memop, QImode, part);
1285 *immop = gen_int_mode (mask, QImode);
1286 }
1287
1288
1289 /* How to allocate a 'struct machine_function'. */
1290
1291 static struct machine_function *
1292 s390_init_machine_status (void)
1293 {
1294 return ggc_alloc_cleared (sizeof (struct machine_function));
1295 }
1296
1297 /* Change optimizations to be performed, depending on the
1298 optimization level.
1299
1300 LEVEL is the optimization level specified; 2 if `-O2' is
1301 specified, 1 if `-O' is specified, and 0 if neither is specified.
1302
1303 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1304
1305 void
1306 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1307 {
1308 /* ??? There are apparently still problems with -fcaller-saves. */
1309 flag_caller_saves = 0;
1310
1311 /* By default, always emit DWARF-2 unwind info. This allows debugging
1312 without maintaining a stack frame back-chain. */
1313 flag_asynchronous_unwind_tables = 1;
1314
1315 /* Use MVCLE instructions to decrease code size if requested. */
1316 if (size != 0)
1317 target_flags |= MASK_MVCLE;
1318 }
1319
1320 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1321 to the associated processor_type and processor_flags if so. */
1322
1323 static bool
1324 s390_handle_arch_option (const char *arg,
1325 enum processor_type *type,
1326 enum processor_flags *flags)
1327 {
1328 static struct pta
1329 {
1330 const char *const name; /* processor name or nickname. */
1331 const enum processor_type processor;
1332 const enum processor_flags flags;
1333 }
1334 const processor_alias_table[] =
1335 {
1336 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1337 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1338 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1339 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1340 | PF_LONG_DISPLACEMENT},
1341 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1342 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1343 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1344 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1345 };
1346 size_t i;
1347
1348 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1349 if (strcmp (arg, processor_alias_table[i].name) == 0)
1350 {
1351 *type = processor_alias_table[i].processor;
1352 *flags = processor_alias_table[i].flags;
1353 return true;
1354 }
1355 return false;
1356 }
1357
1358 /* Implement TARGET_HANDLE_OPTION. */
1359
1360 static bool
1361 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1362 {
1363 switch (code)
1364 {
1365 case OPT_march_:
1366 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1367
1368 case OPT_mstack_guard_:
1369 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1370 return false;
1371 if (exact_log2 (s390_stack_guard) == -1)
1372 error ("stack guard value must be an exact power of 2");
1373 return true;
1374
1375 case OPT_mstack_size_:
1376 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1377 return false;
1378 if (exact_log2 (s390_stack_size) == -1)
1379 error ("stack size must be an exact power of 2");
1380 return true;
1381
1382 case OPT_mtune_:
1383 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1384
1385 case OPT_mwarn_framesize_:
1386 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1387
1388 default:
1389 return true;
1390 }
1391 }
1392
1393 void
1394 override_options (void)
1395 {
1396 /* Set up function hooks. */
1397 init_machine_status = s390_init_machine_status;
1398
1399 /* Architecture mode defaults according to ABI. */
1400 if (!(target_flags_explicit & MASK_ZARCH))
1401 {
1402 if (TARGET_64BIT)
1403 target_flags |= MASK_ZARCH;
1404 else
1405 target_flags &= ~MASK_ZARCH;
1406 }
1407
1408 /* Determine processor architectural level. */
1409 if (!s390_arch_string)
1410 {
1411 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1412 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1413 }
1414
1415 /* Determine processor to tune for. */
1416 if (s390_tune == PROCESSOR_max)
1417 {
1418 s390_tune = s390_arch;
1419 s390_tune_flags = s390_arch_flags;
1420 }
1421
1422 /* Sanity checks. */
1423 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1424 error ("z/Architecture mode not supported on %s", s390_arch_string);
1425 if (TARGET_64BIT && !TARGET_ZARCH)
1426 error ("64-bit ABI not supported in ESA/390 mode");
1427
1428 if (TARGET_HARD_DFP && (!TARGET_CPU_DFP || !TARGET_ZARCH))
1429 {
1430 if (target_flags_explicit & MASK_SOFT_DFP)
1431 {
1432 if (!TARGET_CPU_DFP)
1433 error ("Hardware decimal floating point instructions"
1434 " not available on %s", s390_arch_string);
1435 if (!TARGET_ZARCH)
1436 error ("Hardware decimal floating point instructions"
1437 " not available in ESA/390 mode");
1438 }
1439 else
1440 target_flags |= MASK_SOFT_DFP;
1441 }
1442
1443 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1444 {
1445 if ((target_flags_explicit & MASK_SOFT_DFP) && TARGET_HARD_DFP)
1446 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1447
1448 target_flags |= MASK_SOFT_DFP;
1449 }
1450
1451 /* Set processor cost function. */
1452 if (s390_tune == PROCESSOR_2094_Z9_109)
1453 s390_cost = &z9_109_cost;
1454 else if (s390_tune == PROCESSOR_2084_Z990)
1455 s390_cost = &z990_cost;
1456 else
1457 s390_cost = &z900_cost;
1458
1459 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1460 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1461 "in combination");
1462
1463 if (s390_stack_size)
1464 {
1465 if (s390_stack_guard >= s390_stack_size)
1466 error ("stack size must be greater than the stack guard value");
1467 else if (s390_stack_size > 1 << 16)
1468 error ("stack size must not be greater than 64k");
1469 }
1470 else if (s390_stack_guard)
1471 error ("-mstack-guard implies use of -mstack-size");
1472
1473 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1474 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1475 target_flags |= MASK_LONG_DOUBLE_128;
1476 #endif
1477 }
1478
1479 /* Map for smallest class containing reg regno. */
1480
1481 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1482 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1483 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1484 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1485 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1486 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1487 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1488 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1489 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1490 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1491 ACCESS_REGS, ACCESS_REGS
1492 };
1493
1494 /* Return attribute type of insn. */
1495
1496 static enum attr_type
1497 s390_safe_attr_type (rtx insn)
1498 {
1499 if (recog_memoized (insn) >= 0)
1500 return get_attr_type (insn);
1501 else
1502 return TYPE_NONE;
1503 }
1504
1505 /* Return true if DISP is a valid short displacement. */
1506
1507 static bool
1508 s390_short_displacement (rtx disp)
1509 {
1510 /* No displacement is OK. */
1511 if (!disp)
1512 return true;
1513
1514 /* Integer displacement in range. */
1515 if (GET_CODE (disp) == CONST_INT)
1516 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1517
1518 /* GOT offset is not OK, the GOT can be large. */
1519 if (GET_CODE (disp) == CONST
1520 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1521 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1522 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1523 return false;
1524
1525 /* All other symbolic constants are literal pool references,
1526 which are OK as the literal pool must be small. */
1527 if (GET_CODE (disp) == CONST)
1528 return true;
1529
1530 return false;
1531 }
1532
1533 /* Decompose a RTL expression ADDR for a memory address into
1534 its components, returned in OUT.
1535
1536 Returns false if ADDR is not a valid memory address, true
1537 otherwise. If OUT is NULL, don't return the components,
1538 but check for validity only.
1539
1540 Note: Only addresses in canonical form are recognized.
1541 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1542 canonical form so that they will be recognized. */
1543
1544 static int
1545 s390_decompose_address (rtx addr, struct s390_address *out)
1546 {
1547 HOST_WIDE_INT offset = 0;
1548 rtx base = NULL_RTX;
1549 rtx indx = NULL_RTX;
1550 rtx disp = NULL_RTX;
1551 rtx orig_disp;
1552 bool pointer = false;
1553 bool base_ptr = false;
1554 bool indx_ptr = false;
1555 bool literal_pool = false;
1556
1557 /* We may need to substitute the literal pool base register into the address
1558 below. However, at this point we do not know which register is going to
1559 be used as base, so we substitute the arg pointer register. This is going
1560 to be treated as holding a pointer below -- it shouldn't be used for any
1561 other purpose. */
1562 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1563
1564 /* Decompose address into base + index + displacement. */
1565
1566 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1567 base = addr;
1568
1569 else if (GET_CODE (addr) == PLUS)
1570 {
1571 rtx op0 = XEXP (addr, 0);
1572 rtx op1 = XEXP (addr, 1);
1573 enum rtx_code code0 = GET_CODE (op0);
1574 enum rtx_code code1 = GET_CODE (op1);
1575
1576 if (code0 == REG || code0 == UNSPEC)
1577 {
1578 if (code1 == REG || code1 == UNSPEC)
1579 {
1580 indx = op0; /* index + base */
1581 base = op1;
1582 }
1583
1584 else
1585 {
1586 base = op0; /* base + displacement */
1587 disp = op1;
1588 }
1589 }
1590
1591 else if (code0 == PLUS)
1592 {
1593 indx = XEXP (op0, 0); /* index + base + disp */
1594 base = XEXP (op0, 1);
1595 disp = op1;
1596 }
1597
1598 else
1599 {
1600 return false;
1601 }
1602 }
1603
1604 else
1605 disp = addr; /* displacement */
1606
1607 /* Extract integer part of displacement. */
1608 orig_disp = disp;
1609 if (disp)
1610 {
1611 if (GET_CODE (disp) == CONST_INT)
1612 {
1613 offset = INTVAL (disp);
1614 disp = NULL_RTX;
1615 }
1616 else if (GET_CODE (disp) == CONST
1617 && GET_CODE (XEXP (disp, 0)) == PLUS
1618 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1619 {
1620 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1621 disp = XEXP (XEXP (disp, 0), 0);
1622 }
1623 }
1624
1625 /* Strip off CONST here to avoid special case tests later. */
1626 if (disp && GET_CODE (disp) == CONST)
1627 disp = XEXP (disp, 0);
1628
1629 /* We can convert literal pool addresses to
1630 displacements by basing them off the base register. */
1631 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1632 {
1633 /* Either base or index must be free to hold the base register. */
1634 if (!base)
1635 base = fake_pool_base, literal_pool = true;
1636 else if (!indx)
1637 indx = fake_pool_base, literal_pool = true;
1638 else
1639 return false;
1640
1641 /* Mark up the displacement. */
1642 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1643 UNSPEC_LTREL_OFFSET);
1644 }
1645
1646 /* Validate base register. */
1647 if (base)
1648 {
1649 if (GET_CODE (base) == UNSPEC)
1650 switch (XINT (base, 1))
1651 {
1652 case UNSPEC_LTREF:
1653 if (!disp)
1654 disp = gen_rtx_UNSPEC (Pmode,
1655 gen_rtvec (1, XVECEXP (base, 0, 0)),
1656 UNSPEC_LTREL_OFFSET);
1657 else
1658 return false;
1659
1660 base = XVECEXP (base, 0, 1);
1661 break;
1662
1663 case UNSPEC_LTREL_BASE:
1664 if (XVECLEN (base, 0) == 1)
1665 base = fake_pool_base, literal_pool = true;
1666 else
1667 base = XVECEXP (base, 0, 1);
1668 break;
1669
1670 default:
1671 return false;
1672 }
1673
1674 if (!REG_P (base)
1675 || (GET_MODE (base) != SImode
1676 && GET_MODE (base) != Pmode))
1677 return false;
1678
1679 if (REGNO (base) == STACK_POINTER_REGNUM
1680 || REGNO (base) == FRAME_POINTER_REGNUM
1681 || ((reload_completed || reload_in_progress)
1682 && frame_pointer_needed
1683 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1684 || REGNO (base) == ARG_POINTER_REGNUM
1685 || (flag_pic
1686 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1687 pointer = base_ptr = true;
1688
1689 if ((reload_completed || reload_in_progress)
1690 && base == cfun->machine->base_reg)
1691 pointer = base_ptr = literal_pool = true;
1692 }
1693
1694 /* Validate index register. */
1695 if (indx)
1696 {
1697 if (GET_CODE (indx) == UNSPEC)
1698 switch (XINT (indx, 1))
1699 {
1700 case UNSPEC_LTREF:
1701 if (!disp)
1702 disp = gen_rtx_UNSPEC (Pmode,
1703 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1704 UNSPEC_LTREL_OFFSET);
1705 else
1706 return false;
1707
1708 indx = XVECEXP (indx, 0, 1);
1709 break;
1710
1711 case UNSPEC_LTREL_BASE:
1712 if (XVECLEN (indx, 0) == 1)
1713 indx = fake_pool_base, literal_pool = true;
1714 else
1715 indx = XVECEXP (indx, 0, 1);
1716 break;
1717
1718 default:
1719 return false;
1720 }
1721
1722 if (!REG_P (indx)
1723 || (GET_MODE (indx) != SImode
1724 && GET_MODE (indx) != Pmode))
1725 return false;
1726
1727 if (REGNO (indx) == STACK_POINTER_REGNUM
1728 || REGNO (indx) == FRAME_POINTER_REGNUM
1729 || ((reload_completed || reload_in_progress)
1730 && frame_pointer_needed
1731 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1732 || REGNO (indx) == ARG_POINTER_REGNUM
1733 || (flag_pic
1734 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1735 pointer = indx_ptr = true;
1736
1737 if ((reload_completed || reload_in_progress)
1738 && indx == cfun->machine->base_reg)
1739 pointer = indx_ptr = literal_pool = true;
1740 }
1741
1742 /* Prefer to use pointer as base, not index. */
1743 if (base && indx && !base_ptr
1744 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1745 {
1746 rtx tmp = base;
1747 base = indx;
1748 indx = tmp;
1749 }
1750
1751 /* Validate displacement. */
1752 if (!disp)
1753 {
1754 /* If virtual registers are involved, the displacement will change later
1755 anyway as the virtual registers get eliminated. This could make a
1756 valid displacement invalid, but it is more likely to make an invalid
1757 displacement valid, because we sometimes access the register save area
1758 via negative offsets to one of those registers.
1759 Thus we don't check the displacement for validity here. If after
1760 elimination the displacement turns out to be invalid after all,
1761 this is fixed up by reload in any case. */
1762 if (base != arg_pointer_rtx
1763 && indx != arg_pointer_rtx
1764 && base != return_address_pointer_rtx
1765 && indx != return_address_pointer_rtx
1766 && base != frame_pointer_rtx
1767 && indx != frame_pointer_rtx
1768 && base != virtual_stack_vars_rtx
1769 && indx != virtual_stack_vars_rtx)
1770 if (!DISP_IN_RANGE (offset))
1771 return false;
1772 }
1773 else
1774 {
1775 /* All the special cases are pointers. */
1776 pointer = true;
1777
1778 /* In the small-PIC case, the linker converts @GOT
1779 and @GOTNTPOFF offsets to possible displacements. */
1780 if (GET_CODE (disp) == UNSPEC
1781 && (XINT (disp, 1) == UNSPEC_GOT
1782 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1783 && flag_pic == 1)
1784 {
1785 ;
1786 }
1787
1788 /* Accept chunkified literal pool symbol references. */
1789 else if (cfun && cfun->machine
1790 && cfun->machine->decomposed_literal_pool_addresses_ok_p
1791 && GET_CODE (disp) == MINUS
1792 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1793 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1794 {
1795 ;
1796 }
1797
1798 /* Accept literal pool references. */
1799 else if (GET_CODE (disp) == UNSPEC
1800 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1801 {
1802 orig_disp = gen_rtx_CONST (Pmode, disp);
1803 if (offset)
1804 {
1805 /* If we have an offset, make sure it does not
1806 exceed the size of the constant pool entry. */
1807 rtx sym = XVECEXP (disp, 0, 0);
1808 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1809 return false;
1810
1811 orig_disp = plus_constant (orig_disp, offset);
1812 }
1813 }
1814
1815 else
1816 return false;
1817 }
1818
1819 if (!base && !indx)
1820 pointer = true;
1821
1822 if (out)
1823 {
1824 out->base = base;
1825 out->indx = indx;
1826 out->disp = orig_disp;
1827 out->pointer = pointer;
1828 out->literal_pool = literal_pool;
1829 }
1830
1831 return true;
1832 }
1833
1834 /* Decompose a RTL expression OP for a shift count into its components,
1835 and return the base register in BASE and the offset in OFFSET.
1836
1837 Return true if OP is a valid shift count, false if not. */
1838
1839 bool
1840 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1841 {
1842 HOST_WIDE_INT off = 0;
1843
1844 /* We can have an integer constant, an address register,
1845 or a sum of the two. */
1846 if (GET_CODE (op) == CONST_INT)
1847 {
1848 off = INTVAL (op);
1849 op = NULL_RTX;
1850 }
1851 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1852 {
1853 off = INTVAL (XEXP (op, 1));
1854 op = XEXP (op, 0);
1855 }
1856 while (op && GET_CODE (op) == SUBREG)
1857 op = SUBREG_REG (op);
1858
1859 if (op && GET_CODE (op) != REG)
1860 return false;
1861
1862 if (offset)
1863 *offset = off;
1864 if (base)
1865 *base = op;
1866
1867 return true;
1868 }
1869
1870
1871 /* Return true if CODE is a valid address without index. */
1872
1873 bool
1874 s390_legitimate_address_without_index_p (rtx op)
1875 {
1876 struct s390_address addr;
1877
1878 if (!s390_decompose_address (XEXP (op, 0), &addr))
1879 return false;
1880 if (addr.indx)
1881 return false;
1882
1883 return true;
1884 }
1885
1886
1887 /* Evaluates constraint strings described by the regular expression
1888 ([A|B](Q|R|S|T))|U|W and returns 1 if OP is a valid operand for the
1889 constraint given in STR, or 0 else. */
1890
1891 int
1892 s390_mem_constraint (const char *str, rtx op)
1893 {
1894 struct s390_address addr;
1895 char c = str[0];
1896
1897 /* Check for offsettable variants of memory constraints. */
1898 if (c == 'A')
1899 {
1900 /* Only accept non-volatile MEMs. */
1901 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1902 return 0;
1903
1904 if ((reload_completed || reload_in_progress)
1905 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
1906 return 0;
1907
1908 c = str[1];
1909 }
1910
1911 /* Check for non-literal-pool variants of memory constraints. */
1912 else if (c == 'B')
1913 {
1914 if (GET_CODE (op) != MEM)
1915 return 0;
1916 if (!s390_decompose_address (XEXP (op, 0), &addr))
1917 return 0;
1918 if (addr.literal_pool)
1919 return 0;
1920
1921 c = str[1];
1922 }
1923
1924 switch (c)
1925 {
1926 case 'Q':
1927 if (GET_CODE (op) != MEM)
1928 return 0;
1929 if (!s390_decompose_address (XEXP (op, 0), &addr))
1930 return 0;
1931 if (addr.indx)
1932 return 0;
1933
1934 if (TARGET_LONG_DISPLACEMENT)
1935 {
1936 if (!s390_short_displacement (addr.disp))
1937 return 0;
1938 }
1939 break;
1940
1941 case 'R':
1942 if (GET_CODE (op) != MEM)
1943 return 0;
1944
1945 if (TARGET_LONG_DISPLACEMENT)
1946 {
1947 if (!s390_decompose_address (XEXP (op, 0), &addr))
1948 return 0;
1949 if (!s390_short_displacement (addr.disp))
1950 return 0;
1951 }
1952 break;
1953
1954 case 'S':
1955 if (!TARGET_LONG_DISPLACEMENT)
1956 return 0;
1957 if (GET_CODE (op) != MEM)
1958 return 0;
1959 if (!s390_decompose_address (XEXP (op, 0), &addr))
1960 return 0;
1961 if (addr.indx)
1962 return 0;
1963 if (s390_short_displacement (addr.disp))
1964 return 0;
1965 break;
1966
1967 case 'T':
1968 if (!TARGET_LONG_DISPLACEMENT)
1969 return 0;
1970 if (GET_CODE (op) != MEM)
1971 return 0;
1972 /* Any invalid address here will be fixed up by reload,
1973 so accept it for the most generic constraint. */
1974 if (s390_decompose_address (XEXP (op, 0), &addr)
1975 && s390_short_displacement (addr.disp))
1976 return 0;
1977 break;
1978
1979 case 'U':
1980 if (TARGET_LONG_DISPLACEMENT)
1981 {
1982 if (!s390_decompose_address (op, &addr))
1983 return 0;
1984 if (!s390_short_displacement (addr.disp))
1985 return 0;
1986 }
1987 break;
1988
1989 case 'W':
1990 if (!TARGET_LONG_DISPLACEMENT)
1991 return 0;
1992 /* Any invalid address here will be fixed up by reload,
1993 so accept it for the most generic constraint. */
1994 if (s390_decompose_address (op, &addr)
1995 && s390_short_displacement (addr.disp))
1996 return 0;
1997 break;
1998
1999 case 'Y':
2000 /* Simply check for the basic form of a shift count. Reload will
2001 take care of making sure we have a proper base register. */
2002 if (!s390_decompose_shift_count (op, NULL, NULL))
2003 return 0;
2004 break;
2005
2006 default:
2007 return 0;
2008 }
2009
2010 return 1;
2011 }
2012
2013
2014
2015 /* Evaluates constraint strings starting with letter O. Input
2016 parameter C is the second letter following the "O" in the constraint
2017 string. Returns 1 if VALUE meets the respective constraint and 0
2018 otherwise. */
2019
2020 int
2021 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2022 {
2023 if (!TARGET_EXTIMM)
2024 return 0;
2025
2026 switch (c)
2027 {
2028 case 's':
2029 return trunc_int_for_mode (value, SImode) == value;
2030
2031 case 'p':
2032 return value == 0
2033 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2034
2035 case 'n':
2036 return value == -1
2037 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
2038
2039 default:
2040 gcc_unreachable ();
2041 }
2042 }
2043
2044
2045 /* Evaluates constraint strings starting with letter N. Parameter STR
2046 contains the letters following letter "N" in the constraint string.
2047 Returns true if VALUE matches the constraint. */
2048
2049 int
2050 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2051 {
2052 enum machine_mode mode, part_mode;
2053 int def;
2054 int part, part_goal;
2055
2056
2057 if (str[0] == 'x')
2058 part_goal = -1;
2059 else
2060 part_goal = str[0] - '0';
2061
2062 switch (str[1])
2063 {
2064 case 'Q':
2065 part_mode = QImode;
2066 break;
2067 case 'H':
2068 part_mode = HImode;
2069 break;
2070 case 'S':
2071 part_mode = SImode;
2072 break;
2073 default:
2074 return 0;
2075 }
2076
2077 switch (str[2])
2078 {
2079 case 'H':
2080 mode = HImode;
2081 break;
2082 case 'S':
2083 mode = SImode;
2084 break;
2085 case 'D':
2086 mode = DImode;
2087 break;
2088 default:
2089 return 0;
2090 }
2091
2092 switch (str[3])
2093 {
2094 case '0':
2095 def = 0;
2096 break;
2097 case 'F':
2098 def = -1;
2099 break;
2100 default:
2101 return 0;
2102 }
2103
2104 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2105 return 0;
2106
2107 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2108 if (part < 0)
2109 return 0;
2110 if (part_goal != -1 && part_goal != part)
2111 return 0;
2112
2113 return 1;
2114 }
2115
2116
2117 /* Returns true if the input parameter VALUE is a float zero. */
2118
2119 int
2120 s390_float_const_zero_p (rtx value)
2121 {
2122 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2123 && value == CONST0_RTX (GET_MODE (value)));
2124 }
2125
2126
2127 /* Compute a (partial) cost for rtx X. Return true if the complete
2128 cost has been computed, and false if subexpressions should be
2129 scanned. In either case, *TOTAL contains the cost result.
2130 CODE contains GET_CODE (x), OUTER_CODE contains the code
2131 of the superexpression of x. */
2132
2133 static bool
2134 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2135 {
2136 switch (code)
2137 {
2138 case CONST:
2139 case CONST_INT:
2140 case LABEL_REF:
2141 case SYMBOL_REF:
2142 case CONST_DOUBLE:
2143 case MEM:
2144 *total = 0;
2145 return true;
2146
2147 case ASHIFT:
2148 case ASHIFTRT:
2149 case LSHIFTRT:
2150 case ROTATE:
2151 case ROTATERT:
2152 case AND:
2153 case IOR:
2154 case XOR:
2155 case NEG:
2156 case NOT:
2157 *total = COSTS_N_INSNS (1);
2158 return false;
2159
2160 case PLUS:
2161 case MINUS:
2162 /* Check for multiply and add. */
2163 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2164 && GET_CODE (XEXP (x, 0)) == MULT
2165 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2166 {
2167 /* This is the multiply and add case. */
2168 if (GET_MODE (x) == DFmode)
2169 *total = s390_cost->madbr;
2170 else
2171 *total = s390_cost->maebr;
2172 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2173 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2174 + rtx_cost (XEXP (x, 1), code);
2175 return true; /* Do not do an additional recursive descent. */
2176 }
2177 *total = COSTS_N_INSNS (1);
2178 return false;
2179
2180 case MULT:
2181 switch (GET_MODE (x))
2182 {
2183 case SImode:
2184 {
2185 rtx left = XEXP (x, 0);
2186 rtx right = XEXP (x, 1);
2187 if (GET_CODE (right) == CONST_INT
2188 && CONST_OK_FOR_K (INTVAL (right)))
2189 *total = s390_cost->mhi;
2190 else if (GET_CODE (left) == SIGN_EXTEND)
2191 *total = s390_cost->mh;
2192 else
2193 *total = s390_cost->ms; /* msr, ms, msy */
2194 break;
2195 }
2196 case DImode:
2197 {
2198 rtx left = XEXP (x, 0);
2199 rtx right = XEXP (x, 1);
2200 if (TARGET_64BIT)
2201 {
2202 if (GET_CODE (right) == CONST_INT
2203 && CONST_OK_FOR_K (INTVAL (right)))
2204 *total = s390_cost->mghi;
2205 else if (GET_CODE (left) == SIGN_EXTEND)
2206 *total = s390_cost->msgf;
2207 else
2208 *total = s390_cost->msg; /* msgr, msg */
2209 }
2210 else /* TARGET_31BIT */
2211 {
2212 if (GET_CODE (left) == SIGN_EXTEND
2213 && GET_CODE (right) == SIGN_EXTEND)
2214 /* mulsidi case: mr, m */
2215 *total = s390_cost->m;
2216 else if (GET_CODE (left) == ZERO_EXTEND
2217 && GET_CODE (right) == ZERO_EXTEND
2218 && TARGET_CPU_ZARCH)
2219 /* umulsidi case: ml, mlr */
2220 *total = s390_cost->ml;
2221 else
2222 /* Complex calculation is required. */
2223 *total = COSTS_N_INSNS (40);
2224 }
2225 break;
2226 }
2227 case SFmode:
2228 case DFmode:
2229 *total = s390_cost->mult_df;
2230 break;
2231 case TFmode:
2232 *total = s390_cost->mxbr;
2233 break;
2234 default:
2235 return false;
2236 }
2237 return false;
2238
2239 case UDIV:
2240 case UMOD:
2241 if (GET_MODE (x) == TImode) /* 128 bit division */
2242 *total = s390_cost->dlgr;
2243 else if (GET_MODE (x) == DImode)
2244 {
2245 rtx right = XEXP (x, 1);
2246 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2247 *total = s390_cost->dlr;
2248 else /* 64 by 64 bit division */
2249 *total = s390_cost->dlgr;
2250 }
2251 else if (GET_MODE (x) == SImode) /* 32 bit division */
2252 *total = s390_cost->dlr;
2253 return false;
2254
2255 case DIV:
2256 case MOD:
2257 if (GET_MODE (x) == DImode)
2258 {
2259 rtx right = XEXP (x, 1);
2260 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2261 if (TARGET_64BIT)
2262 *total = s390_cost->dsgfr;
2263 else
2264 *total = s390_cost->dr;
2265 else /* 64 by 64 bit division */
2266 *total = s390_cost->dsgr;
2267 }
2268 else if (GET_MODE (x) == SImode) /* 32 bit division */
2269 *total = s390_cost->dlr;
2270 else if (GET_MODE (x) == SFmode)
2271 {
2272 if (TARGET_IEEE_FLOAT)
2273 *total = s390_cost->debr;
2274 else /* TARGET_IBM_FLOAT */
2275 *total = s390_cost->der;
2276 }
2277 else if (GET_MODE (x) == DFmode)
2278 {
2279 if (TARGET_IEEE_FLOAT)
2280 *total = s390_cost->ddbr;
2281 else /* TARGET_IBM_FLOAT */
2282 *total = s390_cost->ddr;
2283 }
2284 else if (GET_MODE (x) == TFmode)
2285 {
2286 if (TARGET_IEEE_FLOAT)
2287 *total = s390_cost->dxbr;
2288 else /* TARGET_IBM_FLOAT */
2289 *total = s390_cost->dxr;
2290 }
2291 return false;
2292
2293 case SQRT:
2294 if (GET_MODE (x) == SFmode)
2295 *total = s390_cost->sqebr;
2296 else if (GET_MODE (x) == DFmode)
2297 *total = s390_cost->sqdbr;
2298 else /* TFmode */
2299 *total = s390_cost->sqxbr;
2300 return false;
2301
2302 case SIGN_EXTEND:
2303 case ZERO_EXTEND:
2304 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2305 || outer_code == PLUS || outer_code == MINUS
2306 || outer_code == COMPARE)
2307 *total = 0;
2308 return false;
2309
2310 case COMPARE:
2311 *total = COSTS_N_INSNS (1);
2312 if (GET_CODE (XEXP (x, 0)) == AND
2313 && GET_CODE (XEXP (x, 1)) == CONST_INT
2314 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2315 {
2316 rtx op0 = XEXP (XEXP (x, 0), 0);
2317 rtx op1 = XEXP (XEXP (x, 0), 1);
2318 rtx op2 = XEXP (x, 1);
2319
2320 if (memory_operand (op0, GET_MODE (op0))
2321 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2322 return true;
2323 if (register_operand (op0, GET_MODE (op0))
2324 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2325 return true;
2326 }
2327 return false;
2328
2329 default:
2330 return false;
2331 }
2332 }
2333
2334 /* Return the cost of an address rtx ADDR. */
2335
2336 static int
2337 s390_address_cost (rtx addr)
2338 {
2339 struct s390_address ad;
2340 if (!s390_decompose_address (addr, &ad))
2341 return 1000;
2342
2343 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2344 }
2345
2346 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2347 otherwise return 0. */
2348
2349 int
2350 tls_symbolic_operand (rtx op)
2351 {
2352 if (GET_CODE (op) != SYMBOL_REF)
2353 return 0;
2354 return SYMBOL_REF_TLS_MODEL (op);
2355 }
2356 \f
2357 /* Split DImode access register reference REG (on 64-bit) into its constituent
2358 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2359 gen_highpart cannot be used as they assume all registers are word-sized,
2360 while our access registers have only half that size. */
2361
2362 void
2363 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2364 {
2365 gcc_assert (TARGET_64BIT);
2366 gcc_assert (ACCESS_REG_P (reg));
2367 gcc_assert (GET_MODE (reg) == DImode);
2368 gcc_assert (!(REGNO (reg) & 1));
2369
2370 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2371 *hi = gen_rtx_REG (SImode, REGNO (reg));
2372 }
2373
2374 /* Return true if OP contains a symbol reference */
2375
2376 bool
2377 symbolic_reference_mentioned_p (rtx op)
2378 {
2379 const char *fmt;
2380 int i;
2381
2382 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2383 return 1;
2384
2385 fmt = GET_RTX_FORMAT (GET_CODE (op));
2386 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2387 {
2388 if (fmt[i] == 'E')
2389 {
2390 int j;
2391
2392 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2393 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2394 return 1;
2395 }
2396
2397 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2398 return 1;
2399 }
2400
2401 return 0;
2402 }
2403
2404 /* Return true if OP contains a reference to a thread-local symbol. */
2405
2406 bool
2407 tls_symbolic_reference_mentioned_p (rtx op)
2408 {
2409 const char *fmt;
2410 int i;
2411
2412 if (GET_CODE (op) == SYMBOL_REF)
2413 return tls_symbolic_operand (op);
2414
2415 fmt = GET_RTX_FORMAT (GET_CODE (op));
2416 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2417 {
2418 if (fmt[i] == 'E')
2419 {
2420 int j;
2421
2422 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2423 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2424 return true;
2425 }
2426
2427 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2428 return true;
2429 }
2430
2431 return false;
2432 }
2433
2434
2435 /* Return true if OP is a legitimate general operand when
2436 generating PIC code. It is given that flag_pic is on
2437 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2438
2439 int
2440 legitimate_pic_operand_p (rtx op)
2441 {
2442 /* Accept all non-symbolic constants. */
2443 if (!SYMBOLIC_CONST (op))
2444 return 1;
2445
2446 /* Reject everything else; must be handled
2447 via emit_symbolic_move. */
2448 return 0;
2449 }
2450
2451 /* Returns true if the constant value OP is a legitimate general operand.
2452 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2453
2454 int
2455 legitimate_constant_p (rtx op)
2456 {
2457 /* Accept all non-symbolic constants. */
2458 if (!SYMBOLIC_CONST (op))
2459 return 1;
2460
2461 /* Accept immediate LARL operands. */
2462 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2463 return 1;
2464
2465 /* Thread-local symbols are never legal constants. This is
2466 so that emit_call knows that computing such addresses
2467 might require a function call. */
2468 if (TLS_SYMBOLIC_CONST (op))
2469 return 0;
2470
2471 /* In the PIC case, symbolic constants must *not* be
2472 forced into the literal pool. We accept them here,
2473 so that they will be handled by emit_symbolic_move. */
2474 if (flag_pic)
2475 return 1;
2476
2477 /* All remaining non-PIC symbolic constants are
2478 forced into the literal pool. */
2479 return 0;
2480 }
2481
2482 /* Determine if it's legal to put X into the constant pool. This
2483 is not possible if X contains the address of a symbol that is
2484 not constant (TLS) or not known at final link time (PIC). */
2485
2486 static bool
2487 s390_cannot_force_const_mem (rtx x)
2488 {
2489 switch (GET_CODE (x))
2490 {
2491 case CONST_INT:
2492 case CONST_DOUBLE:
2493 /* Accept all non-symbolic constants. */
2494 return false;
2495
2496 case LABEL_REF:
2497 /* Labels are OK iff we are non-PIC. */
2498 return flag_pic != 0;
2499
2500 case SYMBOL_REF:
2501 /* 'Naked' TLS symbol references are never OK,
2502 non-TLS symbols are OK iff we are non-PIC. */
2503 if (tls_symbolic_operand (x))
2504 return true;
2505 else
2506 return flag_pic != 0;
2507
2508 case CONST:
2509 return s390_cannot_force_const_mem (XEXP (x, 0));
2510 case PLUS:
2511 case MINUS:
2512 return s390_cannot_force_const_mem (XEXP (x, 0))
2513 || s390_cannot_force_const_mem (XEXP (x, 1));
2514
2515 case UNSPEC:
2516 switch (XINT (x, 1))
2517 {
2518 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2519 case UNSPEC_LTREL_OFFSET:
2520 case UNSPEC_GOT:
2521 case UNSPEC_GOTOFF:
2522 case UNSPEC_PLTOFF:
2523 case UNSPEC_TLSGD:
2524 case UNSPEC_TLSLDM:
2525 case UNSPEC_NTPOFF:
2526 case UNSPEC_DTPOFF:
2527 case UNSPEC_GOTNTPOFF:
2528 case UNSPEC_INDNTPOFF:
2529 return false;
2530
2531 /* If the literal pool shares the code section, be put
2532 execute template placeholders into the pool as well. */
2533 case UNSPEC_INSN:
2534 return TARGET_CPU_ZARCH;
2535
2536 default:
2537 return true;
2538 }
2539 break;
2540
2541 default:
2542 gcc_unreachable ();
2543 }
2544 }
2545
2546 /* Returns true if the constant value OP is a legitimate general
2547 operand during and after reload. The difference to
2548 legitimate_constant_p is that this function will not accept
2549 a constant that would need to be forced to the literal pool
2550 before it can be used as operand. */
2551
2552 bool
2553 legitimate_reload_constant_p (rtx op)
2554 {
2555 /* Accept la(y) operands. */
2556 if (GET_CODE (op) == CONST_INT
2557 && DISP_IN_RANGE (INTVAL (op)))
2558 return true;
2559
2560 /* Accept l(g)hi/l(g)fi operands. */
2561 if (GET_CODE (op) == CONST_INT
2562 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2563 return true;
2564
2565 /* Accept lliXX operands. */
2566 if (TARGET_ZARCH
2567 && GET_CODE (op) == CONST_INT
2568 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2569 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2570 return true;
2571
2572 if (TARGET_EXTIMM
2573 && GET_CODE (op) == CONST_INT
2574 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2575 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2576 return true;
2577
2578 /* Accept larl operands. */
2579 if (TARGET_CPU_ZARCH
2580 && larl_operand (op, VOIDmode))
2581 return true;
2582
2583 /* Accept lzXX operands. */
2584 if (GET_CODE (op) == CONST_DOUBLE
2585 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2586 return true;
2587
2588 /* Accept double-word operands that can be split. */
2589 if (GET_CODE (op) == CONST_INT
2590 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2591 {
2592 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2593 rtx hi = operand_subword (op, 0, 0, dword_mode);
2594 rtx lo = operand_subword (op, 1, 0, dword_mode);
2595 return legitimate_reload_constant_p (hi)
2596 && legitimate_reload_constant_p (lo);
2597 }
2598
2599 /* Everything else cannot be handled without reload. */
2600 return false;
2601 }
2602
2603 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2604 return the class of reg to actually use. */
2605
2606 enum reg_class
2607 s390_preferred_reload_class (rtx op, enum reg_class class)
2608 {
2609 switch (GET_CODE (op))
2610 {
2611 /* Constants we cannot reload must be forced into the
2612 literal pool. */
2613
2614 case CONST_DOUBLE:
2615 case CONST_INT:
2616 if (legitimate_reload_constant_p (op))
2617 return class;
2618 else
2619 return NO_REGS;
2620
2621 /* If a symbolic constant or a PLUS is reloaded,
2622 it is most likely being used as an address, so
2623 prefer ADDR_REGS. If 'class' is not a superset
2624 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2625 case PLUS:
2626 case LABEL_REF:
2627 case SYMBOL_REF:
2628 case CONST:
2629 if (reg_class_subset_p (ADDR_REGS, class))
2630 return ADDR_REGS;
2631 else
2632 return NO_REGS;
2633
2634 default:
2635 break;
2636 }
2637
2638 return class;
2639 }
2640
2641 /* Return the register class of a scratch register needed to
2642 load IN into a register of class CLASS in MODE.
2643
2644 We need a temporary when loading a PLUS expression which
2645 is not a legitimate operand of the LOAD ADDRESS instruction. */
2646
2647 enum reg_class
2648 s390_secondary_input_reload_class (enum reg_class class,
2649 enum machine_mode mode, rtx in)
2650 {
2651 if (s390_plus_operand (in, mode))
2652 return ADDR_REGS;
2653
2654 if (reg_classes_intersect_p (FP_REGS, class)
2655 && mode == TFmode
2656 && GET_CODE (in) == MEM
2657 && GET_CODE (XEXP (in, 0)) == PLUS
2658 && GET_CODE (XEXP (XEXP (in, 0), 1)) == CONST_INT
2659 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (in, 0), 1))
2660 + GET_MODE_SIZE (mode) - 1))
2661 return ADDR_REGS;
2662
2663 if (reg_classes_intersect_p (CC_REGS, class))
2664 return GENERAL_REGS;
2665
2666 return NO_REGS;
2667 }
2668
2669 /* Return the register class of a scratch register needed to
2670 store a register of class CLASS in MODE into OUT:
2671
2672 We need a temporary when storing a double-word to a
2673 non-offsettable memory address. */
2674
2675 enum reg_class
2676 s390_secondary_output_reload_class (enum reg_class class,
2677 enum machine_mode mode, rtx out)
2678 {
2679 if ((TARGET_64BIT ? (mode == TImode || mode == TFmode)
2680 : (mode == DImode || mode == DFmode))
2681 && reg_classes_intersect_p (GENERAL_REGS, class)
2682 && GET_CODE (out) == MEM
2683 && GET_CODE (XEXP (out, 0)) == PLUS
2684 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2685 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2686 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2687 + GET_MODE_SIZE (mode) - 1))
2688 return ADDR_REGS;
2689
2690 if (reg_classes_intersect_p (FP_REGS, class)
2691 && mode == TFmode
2692 && GET_CODE (out) == MEM
2693 && GET_CODE (XEXP (out, 0)) == PLUS
2694 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2695 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2696 + GET_MODE_SIZE (mode) - 1))
2697 return ADDR_REGS;
2698
2699 if (reg_classes_intersect_p (CC_REGS, class))
2700 return GENERAL_REGS;
2701
2702 return NO_REGS;
2703 }
2704
2705 /* Generate code to load SRC, which is PLUS that is not a
2706 legitimate operand for the LA instruction, into TARGET.
2707 SCRATCH may be used as scratch register. */
2708
2709 void
2710 s390_expand_plus_operand (rtx target, rtx src,
2711 rtx scratch)
2712 {
2713 rtx sum1, sum2;
2714 struct s390_address ad;
2715
2716 /* src must be a PLUS; get its two operands. */
2717 gcc_assert (GET_CODE (src) == PLUS);
2718 gcc_assert (GET_MODE (src) == Pmode);
2719
2720 /* Check if any of the two operands is already scheduled
2721 for replacement by reload. This can happen e.g. when
2722 float registers occur in an address. */
2723 sum1 = find_replacement (&XEXP (src, 0));
2724 sum2 = find_replacement (&XEXP (src, 1));
2725 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2726
2727 /* If the address is already strictly valid, there's nothing to do. */
2728 if (!s390_decompose_address (src, &ad)
2729 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2730 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
2731 {
2732 /* Otherwise, one of the operands cannot be an address register;
2733 we reload its value into the scratch register. */
2734 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2735 {
2736 emit_move_insn (scratch, sum1);
2737 sum1 = scratch;
2738 }
2739 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2740 {
2741 emit_move_insn (scratch, sum2);
2742 sum2 = scratch;
2743 }
2744
2745 /* According to the way these invalid addresses are generated
2746 in reload.c, it should never happen (at least on s390) that
2747 *neither* of the PLUS components, after find_replacements
2748 was applied, is an address register. */
2749 if (sum1 == scratch && sum2 == scratch)
2750 {
2751 debug_rtx (src);
2752 gcc_unreachable ();
2753 }
2754
2755 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2756 }
2757
2758 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2759 is only ever performed on addresses, so we can mark the
2760 sum as legitimate for LA in any case. */
2761 s390_load_address (target, src);
2762 }
2763
2764
2765 /* Return true if ADDR is a valid memory address.
2766 STRICT specifies whether strict register checking applies. */
2767
2768 bool
2769 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2770 rtx addr, int strict)
2771 {
2772 struct s390_address ad;
2773 if (!s390_decompose_address (addr, &ad))
2774 return false;
2775
2776 if (strict)
2777 {
2778 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2779 return false;
2780
2781 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
2782 return false;
2783 }
2784 else
2785 {
2786 if (ad.base
2787 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
2788 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
2789 return false;
2790
2791 if (ad.indx
2792 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
2793 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
2794 return false;
2795 }
2796 return true;
2797 }
2798
2799 /* Return true if OP is a valid operand for the LA instruction.
2800 In 31-bit, we need to prove that the result is used as an
2801 address, as LA performs only a 31-bit addition. */
2802
2803 bool
2804 legitimate_la_operand_p (rtx op)
2805 {
2806 struct s390_address addr;
2807 if (!s390_decompose_address (op, &addr))
2808 return false;
2809
2810 return (TARGET_64BIT || addr.pointer);
2811 }
2812
2813 /* Return true if it is valid *and* preferable to use LA to
2814 compute the sum of OP1 and OP2. */
2815
2816 bool
2817 preferred_la_operand_p (rtx op1, rtx op2)
2818 {
2819 struct s390_address addr;
2820
2821 if (op2 != const0_rtx)
2822 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2823
2824 if (!s390_decompose_address (op1, &addr))
2825 return false;
2826 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
2827 return false;
2828 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
2829 return false;
2830
2831 if (!TARGET_64BIT && !addr.pointer)
2832 return false;
2833
2834 if (addr.pointer)
2835 return true;
2836
2837 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2838 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2839 return true;
2840
2841 return false;
2842 }
2843
2844 /* Emit a forced load-address operation to load SRC into DST.
2845 This will use the LOAD ADDRESS instruction even in situations
2846 where legitimate_la_operand_p (SRC) returns false. */
2847
2848 void
2849 s390_load_address (rtx dst, rtx src)
2850 {
2851 if (TARGET_64BIT)
2852 emit_move_insn (dst, src);
2853 else
2854 emit_insn (gen_force_la_31 (dst, src));
2855 }
2856
2857 /* Return a legitimate reference for ORIG (an address) using the
2858 register REG. If REG is 0, a new pseudo is generated.
2859
2860 There are two types of references that must be handled:
2861
2862 1. Global data references must load the address from the GOT, via
2863 the PIC reg. An insn is emitted to do this load, and the reg is
2864 returned.
2865
2866 2. Static data references, constant pool addresses, and code labels
2867 compute the address as an offset from the GOT, whose base is in
2868 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2869 differentiate them from global data objects. The returned
2870 address is the PIC reg + an unspec constant.
2871
2872 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2873 reg also appears in the address. */
2874
2875 rtx
2876 legitimize_pic_address (rtx orig, rtx reg)
2877 {
2878 rtx addr = orig;
2879 rtx new = orig;
2880 rtx base;
2881
2882 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
2883
2884 if (GET_CODE (addr) == LABEL_REF
2885 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2886 {
2887 /* This is a local symbol. */
2888 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2889 {
2890 /* Access local symbols PC-relative via LARL.
2891 This is the same as in the non-PIC case, so it is
2892 handled automatically ... */
2893 }
2894 else
2895 {
2896 /* Access local symbols relative to the GOT. */
2897
2898 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2899
2900 if (reload_in_progress || reload_completed)
2901 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2902
2903 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2904 addr = gen_rtx_CONST (Pmode, addr);
2905 addr = force_const_mem (Pmode, addr);
2906 emit_move_insn (temp, addr);
2907
2908 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2909 if (reg != 0)
2910 {
2911 s390_load_address (reg, new);
2912 new = reg;
2913 }
2914 }
2915 }
2916 else if (GET_CODE (addr) == SYMBOL_REF)
2917 {
2918 if (reg == 0)
2919 reg = gen_reg_rtx (Pmode);
2920
2921 if (flag_pic == 1)
2922 {
2923 /* Assume GOT offset < 4k. This is handled the same way
2924 in both 31- and 64-bit code (@GOT). */
2925
2926 if (reload_in_progress || reload_completed)
2927 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2928
2929 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2930 new = gen_rtx_CONST (Pmode, new);
2931 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2932 new = gen_const_mem (Pmode, new);
2933 emit_move_insn (reg, new);
2934 new = reg;
2935 }
2936 else if (TARGET_CPU_ZARCH)
2937 {
2938 /* If the GOT offset might be >= 4k, we determine the position
2939 of the GOT entry via a PC-relative LARL (@GOTENT). */
2940
2941 rtx temp = gen_reg_rtx (Pmode);
2942
2943 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2944 new = gen_rtx_CONST (Pmode, new);
2945 emit_move_insn (temp, new);
2946
2947 new = gen_const_mem (Pmode, temp);
2948 emit_move_insn (reg, new);
2949 new = reg;
2950 }
2951 else
2952 {
2953 /* If the GOT offset might be >= 4k, we have to load it
2954 from the literal pool (@GOT). */
2955
2956 rtx temp = gen_reg_rtx (Pmode);
2957
2958 if (reload_in_progress || reload_completed)
2959 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2960
2961 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2962 addr = gen_rtx_CONST (Pmode, addr);
2963 addr = force_const_mem (Pmode, addr);
2964 emit_move_insn (temp, addr);
2965
2966 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2967 new = gen_const_mem (Pmode, new);
2968 emit_move_insn (reg, new);
2969 new = reg;
2970 }
2971 }
2972 else
2973 {
2974 if (GET_CODE (addr) == CONST)
2975 {
2976 addr = XEXP (addr, 0);
2977 if (GET_CODE (addr) == UNSPEC)
2978 {
2979 gcc_assert (XVECLEN (addr, 0) == 1);
2980 switch (XINT (addr, 1))
2981 {
2982 /* If someone moved a GOT-relative UNSPEC
2983 out of the literal pool, force them back in. */
2984 case UNSPEC_GOTOFF:
2985 case UNSPEC_PLTOFF:
2986 new = force_const_mem (Pmode, orig);
2987 break;
2988
2989 /* @GOT is OK as is if small. */
2990 case UNSPEC_GOT:
2991 if (flag_pic == 2)
2992 new = force_const_mem (Pmode, orig);
2993 break;
2994
2995 /* @GOTENT is OK as is. */
2996 case UNSPEC_GOTENT:
2997 break;
2998
2999 /* @PLT is OK as is on 64-bit, must be converted to
3000 GOT-relative @PLTOFF on 31-bit. */
3001 case UNSPEC_PLT:
3002 if (!TARGET_CPU_ZARCH)
3003 {
3004 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3005
3006 if (reload_in_progress || reload_completed)
3007 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3008
3009 addr = XVECEXP (addr, 0, 0);
3010 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3011 UNSPEC_PLTOFF);
3012 addr = gen_rtx_CONST (Pmode, addr);
3013 addr = force_const_mem (Pmode, addr);
3014 emit_move_insn (temp, addr);
3015
3016 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3017 if (reg != 0)
3018 {
3019 s390_load_address (reg, new);
3020 new = reg;
3021 }
3022 }
3023 break;
3024
3025 /* Everything else cannot happen. */
3026 default:
3027 gcc_unreachable ();
3028 }
3029 }
3030 else
3031 gcc_assert (GET_CODE (addr) == PLUS);
3032 }
3033 if (GET_CODE (addr) == PLUS)
3034 {
3035 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3036
3037 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3038 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3039
3040 /* Check first to see if this is a constant offset
3041 from a local symbol reference. */
3042 if ((GET_CODE (op0) == LABEL_REF
3043 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3044 && GET_CODE (op1) == CONST_INT)
3045 {
3046 if (TARGET_CPU_ZARCH
3047 && larl_operand (op0, VOIDmode)
3048 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3049 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3050 {
3051 if (INTVAL (op1) & 1)
3052 {
3053 /* LARL can't handle odd offsets, so emit a
3054 pair of LARL and LA. */
3055 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3056
3057 if (!DISP_IN_RANGE (INTVAL (op1)))
3058 {
3059 HOST_WIDE_INT even = INTVAL (op1) - 1;
3060 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3061 op0 = gen_rtx_CONST (Pmode, op0);
3062 op1 = const1_rtx;
3063 }
3064
3065 emit_move_insn (temp, op0);
3066 new = gen_rtx_PLUS (Pmode, temp, op1);
3067
3068 if (reg != 0)
3069 {
3070 s390_load_address (reg, new);
3071 new = reg;
3072 }
3073 }
3074 else
3075 {
3076 /* If the offset is even, we can just use LARL.
3077 This will happen automatically. */
3078 }
3079 }
3080 else
3081 {
3082 /* Access local symbols relative to the GOT. */
3083
3084 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3085
3086 if (reload_in_progress || reload_completed)
3087 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3088
3089 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3090 UNSPEC_GOTOFF);
3091 addr = gen_rtx_PLUS (Pmode, addr, op1);
3092 addr = gen_rtx_CONST (Pmode, addr);
3093 addr = force_const_mem (Pmode, addr);
3094 emit_move_insn (temp, addr);
3095
3096 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3097 if (reg != 0)
3098 {
3099 s390_load_address (reg, new);
3100 new = reg;
3101 }
3102 }
3103 }
3104
3105 /* Now, check whether it is a GOT relative symbol plus offset
3106 that was pulled out of the literal pool. Force it back in. */
3107
3108 else if (GET_CODE (op0) == UNSPEC
3109 && GET_CODE (op1) == CONST_INT
3110 && XINT (op0, 1) == UNSPEC_GOTOFF)
3111 {
3112 gcc_assert (XVECLEN (op0, 0) == 1);
3113
3114 new = force_const_mem (Pmode, orig);
3115 }
3116
3117 /* Otherwise, compute the sum. */
3118 else
3119 {
3120 base = legitimize_pic_address (XEXP (addr, 0), reg);
3121 new = legitimize_pic_address (XEXP (addr, 1),
3122 base == reg ? NULL_RTX : reg);
3123 if (GET_CODE (new) == CONST_INT)
3124 new = plus_constant (base, INTVAL (new));
3125 else
3126 {
3127 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3128 {
3129 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3130 new = XEXP (new, 1);
3131 }
3132 new = gen_rtx_PLUS (Pmode, base, new);
3133 }
3134
3135 if (GET_CODE (new) == CONST)
3136 new = XEXP (new, 0);
3137 new = force_operand (new, 0);
3138 }
3139 }
3140 }
3141 return new;
3142 }
3143
3144 /* Load the thread pointer into a register. */
3145
3146 rtx
3147 s390_get_thread_pointer (void)
3148 {
3149 rtx tp = gen_reg_rtx (Pmode);
3150
3151 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3152 mark_reg_pointer (tp, BITS_PER_WORD);
3153
3154 return tp;
3155 }
3156
3157 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3158 in s390_tls_symbol which always refers to __tls_get_offset.
3159 The returned offset is written to RESULT_REG and an USE rtx is
3160 generated for TLS_CALL. */
3161
3162 static GTY(()) rtx s390_tls_symbol;
3163
3164 static void
3165 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3166 {
3167 rtx insn;
3168
3169 gcc_assert (flag_pic);
3170
3171 if (!s390_tls_symbol)
3172 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3173
3174 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3175 gen_rtx_REG (Pmode, RETURN_REGNUM));
3176
3177 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3178 CONST_OR_PURE_CALL_P (insn) = 1;
3179 }
3180
3181 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3182 this (thread-local) address. REG may be used as temporary. */
3183
3184 static rtx
3185 legitimize_tls_address (rtx addr, rtx reg)
3186 {
3187 rtx new, tls_call, temp, base, r2, insn;
3188
3189 if (GET_CODE (addr) == SYMBOL_REF)
3190 switch (tls_symbolic_operand (addr))
3191 {
3192 case TLS_MODEL_GLOBAL_DYNAMIC:
3193 start_sequence ();
3194 r2 = gen_rtx_REG (Pmode, 2);
3195 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3196 new = gen_rtx_CONST (Pmode, tls_call);
3197 new = force_const_mem (Pmode, new);
3198 emit_move_insn (r2, new);
3199 s390_emit_tls_call_insn (r2, tls_call);
3200 insn = get_insns ();
3201 end_sequence ();
3202
3203 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3204 temp = gen_reg_rtx (Pmode);
3205 emit_libcall_block (insn, temp, r2, new);
3206
3207 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3208 if (reg != 0)
3209 {
3210 s390_load_address (reg, new);
3211 new = reg;
3212 }
3213 break;
3214
3215 case TLS_MODEL_LOCAL_DYNAMIC:
3216 start_sequence ();
3217 r2 = gen_rtx_REG (Pmode, 2);
3218 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3219 new = gen_rtx_CONST (Pmode, tls_call);
3220 new = force_const_mem (Pmode, new);
3221 emit_move_insn (r2, new);
3222 s390_emit_tls_call_insn (r2, tls_call);
3223 insn = get_insns ();
3224 end_sequence ();
3225
3226 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3227 temp = gen_reg_rtx (Pmode);
3228 emit_libcall_block (insn, temp, r2, new);
3229
3230 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3231 base = gen_reg_rtx (Pmode);
3232 s390_load_address (base, new);
3233
3234 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3235 new = gen_rtx_CONST (Pmode, new);
3236 new = force_const_mem (Pmode, new);
3237 temp = gen_reg_rtx (Pmode);
3238 emit_move_insn (temp, new);
3239
3240 new = gen_rtx_PLUS (Pmode, base, temp);
3241 if (reg != 0)
3242 {
3243 s390_load_address (reg, new);
3244 new = reg;
3245 }
3246 break;
3247
3248 case TLS_MODEL_INITIAL_EXEC:
3249 if (flag_pic == 1)
3250 {
3251 /* Assume GOT offset < 4k. This is handled the same way
3252 in both 31- and 64-bit code. */
3253
3254 if (reload_in_progress || reload_completed)
3255 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3256
3257 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3258 new = gen_rtx_CONST (Pmode, new);
3259 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3260 new = gen_const_mem (Pmode, new);
3261 temp = gen_reg_rtx (Pmode);
3262 emit_move_insn (temp, new);
3263 }
3264 else if (TARGET_CPU_ZARCH)
3265 {
3266 /* If the GOT offset might be >= 4k, we determine the position
3267 of the GOT entry via a PC-relative LARL. */
3268
3269 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3270 new = gen_rtx_CONST (Pmode, new);
3271 temp = gen_reg_rtx (Pmode);
3272 emit_move_insn (temp, new);
3273
3274 new = gen_const_mem (Pmode, temp);
3275 temp = gen_reg_rtx (Pmode);
3276 emit_move_insn (temp, new);
3277 }
3278 else if (flag_pic)
3279 {
3280 /* If the GOT offset might be >= 4k, we have to load it
3281 from the literal pool. */
3282
3283 if (reload_in_progress || reload_completed)
3284 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3285
3286 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3287 new = gen_rtx_CONST (Pmode, new);
3288 new = force_const_mem (Pmode, new);
3289 temp = gen_reg_rtx (Pmode);
3290 emit_move_insn (temp, new);
3291
3292 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3293 new = gen_const_mem (Pmode, new);
3294
3295 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3296 temp = gen_reg_rtx (Pmode);
3297 emit_insn (gen_rtx_SET (Pmode, temp, new));
3298 }
3299 else
3300 {
3301 /* In position-dependent code, load the absolute address of
3302 the GOT entry from the literal pool. */
3303
3304 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3305 new = gen_rtx_CONST (Pmode, new);
3306 new = force_const_mem (Pmode, new);
3307 temp = gen_reg_rtx (Pmode);
3308 emit_move_insn (temp, new);
3309
3310 new = temp;
3311 new = gen_const_mem (Pmode, new);
3312 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3313 temp = gen_reg_rtx (Pmode);
3314 emit_insn (gen_rtx_SET (Pmode, temp, new));
3315 }
3316
3317 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3318 if (reg != 0)
3319 {
3320 s390_load_address (reg, new);
3321 new = reg;
3322 }
3323 break;
3324
3325 case TLS_MODEL_LOCAL_EXEC:
3326 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3327 new = gen_rtx_CONST (Pmode, new);
3328 new = force_const_mem (Pmode, new);
3329 temp = gen_reg_rtx (Pmode);
3330 emit_move_insn (temp, new);
3331
3332 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3333 if (reg != 0)
3334 {
3335 s390_load_address (reg, new);
3336 new = reg;
3337 }
3338 break;
3339
3340 default:
3341 gcc_unreachable ();
3342 }
3343
3344 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3345 {
3346 switch (XINT (XEXP (addr, 0), 1))
3347 {
3348 case UNSPEC_INDNTPOFF:
3349 gcc_assert (TARGET_CPU_ZARCH);
3350 new = addr;
3351 break;
3352
3353 default:
3354 gcc_unreachable ();
3355 }
3356 }
3357
3358 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3359 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3360 {
3361 new = XEXP (XEXP (addr, 0), 0);
3362 if (GET_CODE (new) != SYMBOL_REF)
3363 new = gen_rtx_CONST (Pmode, new);
3364
3365 new = legitimize_tls_address (new, reg);
3366 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3367 new = force_operand (new, 0);
3368 }
3369
3370 else
3371 gcc_unreachable (); /* for now ... */
3372
3373 return new;
3374 }
3375
3376 /* Emit insns to move operands[1] into operands[0]. */
3377
3378 void
3379 emit_symbolic_move (rtx *operands)
3380 {
3381 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3382
3383 if (GET_CODE (operands[0]) == MEM)
3384 operands[1] = force_reg (Pmode, operands[1]);
3385 else if (TLS_SYMBOLIC_CONST (operands[1]))
3386 operands[1] = legitimize_tls_address (operands[1], temp);
3387 else if (flag_pic)
3388 operands[1] = legitimize_pic_address (operands[1], temp);
3389 }
3390
3391 /* Try machine-dependent ways of modifying an illegitimate address X
3392 to be legitimate. If we find one, return the new, valid address.
3393
3394 OLDX is the address as it was before break_out_memory_refs was called.
3395 In some cases it is useful to look at this to decide what needs to be done.
3396
3397 MODE is the mode of the operand pointed to by X.
3398
3399 When -fpic is used, special handling is needed for symbolic references.
3400 See comments by legitimize_pic_address for details. */
3401
3402 rtx
3403 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3404 enum machine_mode mode ATTRIBUTE_UNUSED)
3405 {
3406 rtx constant_term = const0_rtx;
3407
3408 if (TLS_SYMBOLIC_CONST (x))
3409 {
3410 x = legitimize_tls_address (x, 0);
3411
3412 if (legitimate_address_p (mode, x, FALSE))
3413 return x;
3414 }
3415 else if (GET_CODE (x) == PLUS
3416 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3417 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3418 {
3419 return x;
3420 }
3421 else if (flag_pic)
3422 {
3423 if (SYMBOLIC_CONST (x)
3424 || (GET_CODE (x) == PLUS
3425 && (SYMBOLIC_CONST (XEXP (x, 0))
3426 || SYMBOLIC_CONST (XEXP (x, 1)))))
3427 x = legitimize_pic_address (x, 0);
3428
3429 if (legitimate_address_p (mode, x, FALSE))
3430 return x;
3431 }
3432
3433 x = eliminate_constant_term (x, &constant_term);
3434
3435 /* Optimize loading of large displacements by splitting them
3436 into the multiple of 4K and the rest; this allows the
3437 former to be CSE'd if possible.
3438
3439 Don't do this if the displacement is added to a register
3440 pointing into the stack frame, as the offsets will
3441 change later anyway. */
3442
3443 if (GET_CODE (constant_term) == CONST_INT
3444 && !TARGET_LONG_DISPLACEMENT
3445 && !DISP_IN_RANGE (INTVAL (constant_term))
3446 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3447 {
3448 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3449 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3450
3451 rtx temp = gen_reg_rtx (Pmode);
3452 rtx val = force_operand (GEN_INT (upper), temp);
3453 if (val != temp)
3454 emit_move_insn (temp, val);
3455
3456 x = gen_rtx_PLUS (Pmode, x, temp);
3457 constant_term = GEN_INT (lower);
3458 }
3459
3460 if (GET_CODE (x) == PLUS)
3461 {
3462 if (GET_CODE (XEXP (x, 0)) == REG)
3463 {
3464 rtx temp = gen_reg_rtx (Pmode);
3465 rtx val = force_operand (XEXP (x, 1), temp);
3466 if (val != temp)
3467 emit_move_insn (temp, val);
3468
3469 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3470 }
3471
3472 else if (GET_CODE (XEXP (x, 1)) == REG)
3473 {
3474 rtx temp = gen_reg_rtx (Pmode);
3475 rtx val = force_operand (XEXP (x, 0), temp);
3476 if (val != temp)
3477 emit_move_insn (temp, val);
3478
3479 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3480 }
3481 }
3482
3483 if (constant_term != const0_rtx)
3484 x = gen_rtx_PLUS (Pmode, x, constant_term);
3485
3486 return x;
3487 }
3488
3489 /* Try a machine-dependent way of reloading an illegitimate address AD
3490 operand. If we find one, push the reload and and return the new address.
3491
3492 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3493 and TYPE is the reload type of the current reload. */
3494
3495 rtx
3496 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3497 int opnum, int type)
3498 {
3499 if (!optimize || TARGET_LONG_DISPLACEMENT)
3500 return NULL_RTX;
3501
3502 if (GET_CODE (ad) == PLUS)
3503 {
3504 rtx tem = simplify_binary_operation (PLUS, Pmode,
3505 XEXP (ad, 0), XEXP (ad, 1));
3506 if (tem)
3507 ad = tem;
3508 }
3509
3510 if (GET_CODE (ad) == PLUS
3511 && GET_CODE (XEXP (ad, 0)) == REG
3512 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3513 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3514 {
3515 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3516 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3517 rtx cst, tem, new;
3518
3519 cst = GEN_INT (upper);
3520 if (!legitimate_reload_constant_p (cst))
3521 cst = force_const_mem (Pmode, cst);
3522
3523 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3524 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3525
3526 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3527 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3528 opnum, (enum reload_type) type);
3529 return new;
3530 }
3531
3532 return NULL_RTX;
3533 }
3534
3535 /* Emit code to move LEN bytes from DST to SRC. */
3536
3537 void
3538 s390_expand_movmem (rtx dst, rtx src, rtx len)
3539 {
3540 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3541 {
3542 if (INTVAL (len) > 0)
3543 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3544 }
3545
3546 else if (TARGET_MVCLE)
3547 {
3548 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3549 }
3550
3551 else
3552 {
3553 rtx dst_addr, src_addr, count, blocks, temp;
3554 rtx loop_start_label = gen_label_rtx ();
3555 rtx loop_end_label = gen_label_rtx ();
3556 rtx end_label = gen_label_rtx ();
3557 enum machine_mode mode;
3558
3559 mode = GET_MODE (len);
3560 if (mode == VOIDmode)
3561 mode = Pmode;
3562
3563 dst_addr = gen_reg_rtx (Pmode);
3564 src_addr = gen_reg_rtx (Pmode);
3565 count = gen_reg_rtx (mode);
3566 blocks = gen_reg_rtx (mode);
3567
3568 convert_move (count, len, 1);
3569 emit_cmp_and_jump_insns (count, const0_rtx,
3570 EQ, NULL_RTX, mode, 1, end_label);
3571
3572 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3573 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3574 dst = change_address (dst, VOIDmode, dst_addr);
3575 src = change_address (src, VOIDmode, src_addr);
3576
3577 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3578 if (temp != count)
3579 emit_move_insn (count, temp);
3580
3581 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3582 if (temp != blocks)
3583 emit_move_insn (blocks, temp);
3584
3585 emit_cmp_and_jump_insns (blocks, const0_rtx,
3586 EQ, NULL_RTX, mode, 1, loop_end_label);
3587
3588 emit_label (loop_start_label);
3589
3590 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3591 s390_load_address (dst_addr,
3592 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3593 s390_load_address (src_addr,
3594 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3595
3596 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3597 if (temp != blocks)
3598 emit_move_insn (blocks, temp);
3599
3600 emit_cmp_and_jump_insns (blocks, const0_rtx,
3601 EQ, NULL_RTX, mode, 1, loop_end_label);
3602
3603 emit_jump (loop_start_label);
3604 emit_label (loop_end_label);
3605
3606 emit_insn (gen_movmem_short (dst, src,
3607 convert_to_mode (Pmode, count, 1)));
3608 emit_label (end_label);
3609 }
3610 }
3611
3612 /* Emit code to set LEN bytes at DST to VAL.
3613 Make use of clrmem if VAL is zero. */
3614
3615 void
3616 s390_expand_setmem (rtx dst, rtx len, rtx val)
3617 {
3618 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3619 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3620
3621 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3622 {
3623 if (val == const0_rtx && INTVAL (len) <= 256)
3624 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3625 else
3626 {
3627 /* Initialize memory by storing the first byte. */
3628 emit_move_insn (adjust_address (dst, QImode, 0), val);
3629
3630 if (INTVAL (len) > 1)
3631 {
3632 /* Initiate 1 byte overlap move.
3633 The first byte of DST is propagated through DSTP1.
3634 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3635 DST is set to size 1 so the rest of the memory location
3636 does not count as source operand. */
3637 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3638 set_mem_size (dst, const1_rtx);
3639
3640 emit_insn (gen_movmem_short (dstp1, dst,
3641 GEN_INT (INTVAL (len) - 2)));
3642 }
3643 }
3644 }
3645
3646 else if (TARGET_MVCLE)
3647 {
3648 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3649 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3650 }
3651
3652 else
3653 {
3654 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3655 rtx loop_start_label = gen_label_rtx ();
3656 rtx loop_end_label = gen_label_rtx ();
3657 rtx end_label = gen_label_rtx ();
3658 enum machine_mode mode;
3659
3660 mode = GET_MODE (len);
3661 if (mode == VOIDmode)
3662 mode = Pmode;
3663
3664 dst_addr = gen_reg_rtx (Pmode);
3665 src_addr = gen_reg_rtx (Pmode);
3666 count = gen_reg_rtx (mode);
3667 blocks = gen_reg_rtx (mode);
3668
3669 convert_move (count, len, 1);
3670 emit_cmp_and_jump_insns (count, const0_rtx,
3671 EQ, NULL_RTX, mode, 1, end_label);
3672
3673 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3674 dst = change_address (dst, VOIDmode, dst_addr);
3675
3676 if (val == const0_rtx)
3677 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3678 else
3679 {
3680 dstp1 = adjust_address (dst, VOIDmode, 1);
3681 set_mem_size (dst, const1_rtx);
3682
3683 /* Initialize memory by storing the first byte. */
3684 emit_move_insn (adjust_address (dst, QImode, 0), val);
3685
3686 /* If count is 1 we are done. */
3687 emit_cmp_and_jump_insns (count, const1_rtx,
3688 EQ, NULL_RTX, mode, 1, end_label);
3689
3690 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3691 }
3692 if (temp != count)
3693 emit_move_insn (count, temp);
3694
3695 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3696 if (temp != blocks)
3697 emit_move_insn (blocks, temp);
3698
3699 emit_cmp_and_jump_insns (blocks, const0_rtx,
3700 EQ, NULL_RTX, mode, 1, loop_end_label);
3701
3702 emit_label (loop_start_label);
3703
3704 if (val == const0_rtx)
3705 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3706 else
3707 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3708 s390_load_address (dst_addr,
3709 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3710
3711 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3712 if (temp != blocks)
3713 emit_move_insn (blocks, temp);
3714
3715 emit_cmp_and_jump_insns (blocks, const0_rtx,
3716 EQ, NULL_RTX, mode, 1, loop_end_label);
3717
3718 emit_jump (loop_start_label);
3719 emit_label (loop_end_label);
3720
3721 if (val == const0_rtx)
3722 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3723 else
3724 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3725 emit_label (end_label);
3726 }
3727 }
3728
3729 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3730 and return the result in TARGET. */
3731
3732 void
3733 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3734 {
3735 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3736 rtx tmp;
3737
3738 /* As the result of CMPINT is inverted compared to what we need,
3739 we have to swap the operands. */
3740 tmp = op0; op0 = op1; op1 = tmp;
3741
3742 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3743 {
3744 if (INTVAL (len) > 0)
3745 {
3746 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3747 emit_insn (gen_cmpint (target, ccreg));
3748 }
3749 else
3750 emit_move_insn (target, const0_rtx);
3751 }
3752 else if (TARGET_MVCLE)
3753 {
3754 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3755 emit_insn (gen_cmpint (target, ccreg));
3756 }
3757 else
3758 {
3759 rtx addr0, addr1, count, blocks, temp;
3760 rtx loop_start_label = gen_label_rtx ();
3761 rtx loop_end_label = gen_label_rtx ();
3762 rtx end_label = gen_label_rtx ();
3763 enum machine_mode mode;
3764
3765 mode = GET_MODE (len);
3766 if (mode == VOIDmode)
3767 mode = Pmode;
3768
3769 addr0 = gen_reg_rtx (Pmode);
3770 addr1 = gen_reg_rtx (Pmode);
3771 count = gen_reg_rtx (mode);
3772 blocks = gen_reg_rtx (mode);
3773
3774 convert_move (count, len, 1);
3775 emit_cmp_and_jump_insns (count, const0_rtx,
3776 EQ, NULL_RTX, mode, 1, end_label);
3777
3778 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3779 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3780 op0 = change_address (op0, VOIDmode, addr0);
3781 op1 = change_address (op1, VOIDmode, addr1);
3782
3783 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3784 if (temp != count)
3785 emit_move_insn (count, temp);
3786
3787 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3788 if (temp != blocks)
3789 emit_move_insn (blocks, temp);
3790
3791 emit_cmp_and_jump_insns (blocks, const0_rtx,
3792 EQ, NULL_RTX, mode, 1, loop_end_label);
3793
3794 emit_label (loop_start_label);
3795
3796 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3797 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3798 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3799 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3800 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3801 emit_jump_insn (temp);
3802
3803 s390_load_address (addr0,
3804 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3805 s390_load_address (addr1,
3806 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3807
3808 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3809 if (temp != blocks)
3810 emit_move_insn (blocks, temp);
3811
3812 emit_cmp_and_jump_insns (blocks, const0_rtx,
3813 EQ, NULL_RTX, mode, 1, loop_end_label);
3814
3815 emit_jump (loop_start_label);
3816 emit_label (loop_end_label);
3817
3818 emit_insn (gen_cmpmem_short (op0, op1,
3819 convert_to_mode (Pmode, count, 1)));
3820 emit_label (end_label);
3821
3822 emit_insn (gen_cmpint (target, ccreg));
3823 }
3824 }
3825
3826
3827 /* Expand conditional increment or decrement using alc/slb instructions.
3828 Should generate code setting DST to either SRC or SRC + INCREMENT,
3829 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3830 Returns true if successful, false otherwise.
3831
3832 That makes it possible to implement some if-constructs without jumps e.g.:
3833 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3834 unsigned int a, b, c;
3835 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3836 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3837 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3838 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3839
3840 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3841 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3842 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3843 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3844 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3845
3846 bool
3847 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3848 rtx dst, rtx src, rtx increment)
3849 {
3850 enum machine_mode cmp_mode;
3851 enum machine_mode cc_mode;
3852 rtx op_res;
3853 rtx insn;
3854 rtvec p;
3855 int ret;
3856
3857 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3858 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3859 cmp_mode = SImode;
3860 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3861 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3862 cmp_mode = DImode;
3863 else
3864 return false;
3865
3866 /* Try ADD LOGICAL WITH CARRY. */
3867 if (increment == const1_rtx)
3868 {
3869 /* Determine CC mode to use. */
3870 if (cmp_code == EQ || cmp_code == NE)
3871 {
3872 if (cmp_op1 != const0_rtx)
3873 {
3874 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3875 NULL_RTX, 0, OPTAB_WIDEN);
3876 cmp_op1 = const0_rtx;
3877 }
3878
3879 cmp_code = cmp_code == EQ ? LEU : GTU;
3880 }
3881
3882 if (cmp_code == LTU || cmp_code == LEU)
3883 {
3884 rtx tem = cmp_op0;
3885 cmp_op0 = cmp_op1;
3886 cmp_op1 = tem;
3887 cmp_code = swap_condition (cmp_code);
3888 }
3889
3890 switch (cmp_code)
3891 {
3892 case GTU:
3893 cc_mode = CCUmode;
3894 break;
3895
3896 case GEU:
3897 cc_mode = CCL3mode;
3898 break;
3899
3900 default:
3901 return false;
3902 }
3903
3904 /* Emit comparison instruction pattern. */
3905 if (!register_operand (cmp_op0, cmp_mode))
3906 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3907
3908 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3909 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3910 /* We use insn_invalid_p here to add clobbers if required. */
3911 ret = insn_invalid_p (emit_insn (insn));
3912 gcc_assert (!ret);
3913
3914 /* Emit ALC instruction pattern. */
3915 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3916 gen_rtx_REG (cc_mode, CC_REGNUM),
3917 const0_rtx);
3918
3919 if (src != const0_rtx)
3920 {
3921 if (!register_operand (src, GET_MODE (dst)))
3922 src = force_reg (GET_MODE (dst), src);
3923
3924 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3925 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3926 }
3927
3928 p = rtvec_alloc (2);
3929 RTVEC_ELT (p, 0) =
3930 gen_rtx_SET (VOIDmode, dst, op_res);
3931 RTVEC_ELT (p, 1) =
3932 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3933 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3934
3935 return true;
3936 }
3937
3938 /* Try SUBTRACT LOGICAL WITH BORROW. */
3939 if (increment == constm1_rtx)
3940 {
3941 /* Determine CC mode to use. */
3942 if (cmp_code == EQ || cmp_code == NE)
3943 {
3944 if (cmp_op1 != const0_rtx)
3945 {
3946 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3947 NULL_RTX, 0, OPTAB_WIDEN);
3948 cmp_op1 = const0_rtx;
3949 }
3950
3951 cmp_code = cmp_code == EQ ? LEU : GTU;
3952 }
3953
3954 if (cmp_code == GTU || cmp_code == GEU)
3955 {
3956 rtx tem = cmp_op0;
3957 cmp_op0 = cmp_op1;
3958 cmp_op1 = tem;
3959 cmp_code = swap_condition (cmp_code);
3960 }
3961
3962 switch (cmp_code)
3963 {
3964 case LEU:
3965 cc_mode = CCUmode;
3966 break;
3967
3968 case LTU:
3969 cc_mode = CCL3mode;
3970 break;
3971
3972 default:
3973 return false;
3974 }
3975
3976 /* Emit comparison instruction pattern. */
3977 if (!register_operand (cmp_op0, cmp_mode))
3978 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3979
3980 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3981 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3982 /* We use insn_invalid_p here to add clobbers if required. */
3983 ret = insn_invalid_p (emit_insn (insn));
3984 gcc_assert (!ret);
3985
3986 /* Emit SLB instruction pattern. */
3987 if (!register_operand (src, GET_MODE (dst)))
3988 src = force_reg (GET_MODE (dst), src);
3989
3990 op_res = gen_rtx_MINUS (GET_MODE (dst),
3991 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3992 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3993 gen_rtx_REG (cc_mode, CC_REGNUM),
3994 const0_rtx));
3995 p = rtvec_alloc (2);
3996 RTVEC_ELT (p, 0) =
3997 gen_rtx_SET (VOIDmode, dst, op_res);
3998 RTVEC_ELT (p, 1) =
3999 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4000 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4001
4002 return true;
4003 }
4004
4005 return false;
4006 }
4007
4008 /* Expand code for the insv template. Return true if successful, false else. */
4009
4010 bool
4011 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4012 {
4013 int bitsize = INTVAL (op1);
4014 int bitpos = INTVAL (op2);
4015
4016 /* We need byte alignment. */
4017 if (bitsize % BITS_PER_UNIT)
4018 return false;
4019
4020 if (bitpos == 0
4021 && memory_operand (dest, VOIDmode)
4022 && (register_operand (src, word_mode)
4023 || const_int_operand (src, VOIDmode)))
4024 {
4025 /* Emit standard pattern if possible. */
4026 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4027 if (GET_MODE_BITSIZE (mode) == bitsize)
4028 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4029
4030 /* (set (ze (mem)) (const_int)). */
4031 else if (const_int_operand (src, VOIDmode))
4032 {
4033 int size = bitsize / BITS_PER_UNIT;
4034 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4035 GET_MODE_SIZE (word_mode) - size);
4036
4037 dest = adjust_address (dest, BLKmode, 0);
4038 set_mem_size (dest, GEN_INT (size));
4039 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4040 }
4041
4042 /* (set (ze (mem)) (reg)). */
4043 else if (register_operand (src, word_mode))
4044 {
4045 if (bitsize <= GET_MODE_BITSIZE (SImode))
4046 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4047 const0_rtx), src);
4048 else
4049 {
4050 /* Emit st,stcmh sequence. */
4051 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4052 int size = stcmh_width / BITS_PER_UNIT;
4053
4054 emit_move_insn (adjust_address (dest, SImode, size),
4055 gen_lowpart (SImode, src));
4056 set_mem_size (dest, GEN_INT (size));
4057 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4058 (stcmh_width), const0_rtx),
4059 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4060 (GET_MODE_BITSIZE (SImode))));
4061 }
4062 }
4063 else
4064 return false;
4065
4066 return true;
4067 }
4068
4069 /* (set (ze (reg)) (const_int)). */
4070 if (TARGET_ZARCH
4071 && register_operand (dest, word_mode)
4072 && (bitpos % 16) == 0
4073 && (bitsize % 16) == 0
4074 && const_int_operand (src, VOIDmode))
4075 {
4076 HOST_WIDE_INT val = INTVAL (src);
4077 int regpos = bitpos + bitsize;
4078
4079 while (regpos > bitpos)
4080 {
4081 enum machine_mode putmode;
4082 int putsize;
4083
4084 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4085 putmode = SImode;
4086 else
4087 putmode = HImode;
4088
4089 putsize = GET_MODE_BITSIZE (putmode);
4090 regpos -= putsize;
4091 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4092 GEN_INT (putsize),
4093 GEN_INT (regpos)),
4094 gen_int_mode (val, putmode));
4095 val >>= putsize;
4096 }
4097 gcc_assert (regpos == bitpos);
4098 return true;
4099 }
4100
4101 return false;
4102 }
4103
4104 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4105 register that holds VAL of mode MODE shifted by COUNT bits. */
4106
4107 static inline rtx
4108 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4109 {
4110 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4111 NULL_RTX, 1, OPTAB_DIRECT);
4112 return expand_simple_binop (SImode, ASHIFT, val, count,
4113 NULL_RTX, 1, OPTAB_DIRECT);
4114 }
4115
4116 /* Structure to hold the initial parameters for a compare_and_swap operation
4117 in HImode and QImode. */
4118
4119 struct alignment_context
4120 {
4121 rtx memsi; /* SI aligned memory location. */
4122 rtx shift; /* Bit offset with regard to lsb. */
4123 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4124 rtx modemaski; /* ~modemask */
4125 bool aligned; /* True if memory is aligned, false else. */
4126 };
4127
4128 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4129 structure AC for transparent simplifying, if the memory alignment is known
4130 to be at least 32bit. MEM is the memory location for the actual operation
4131 and MODE its mode. */
4132
4133 static void
4134 init_alignment_context (struct alignment_context *ac, rtx mem,
4135 enum machine_mode mode)
4136 {
4137 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4138 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4139
4140 if (ac->aligned)
4141 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4142 else
4143 {
4144 /* Alignment is unknown. */
4145 rtx byteoffset, addr, align;
4146
4147 /* Force the address into a register. */
4148 addr = force_reg (Pmode, XEXP (mem, 0));
4149
4150 /* Align it to SImode. */
4151 align = expand_simple_binop (Pmode, AND, addr,
4152 GEN_INT (-GET_MODE_SIZE (SImode)),
4153 NULL_RTX, 1, OPTAB_DIRECT);
4154 /* Generate MEM. */
4155 ac->memsi = gen_rtx_MEM (SImode, align);
4156 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4157 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4158 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4159
4160 /* Calculate shiftcount. */
4161 byteoffset = expand_simple_binop (Pmode, AND, addr,
4162 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4163 NULL_RTX, 1, OPTAB_DIRECT);
4164 /* As we already have some offset, evaluate the remaining distance. */
4165 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4166 NULL_RTX, 1, OPTAB_DIRECT);
4167
4168 }
4169 /* Shift is the byte count, but we need the bitcount. */
4170 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4171 NULL_RTX, 1, OPTAB_DIRECT);
4172 /* Calculate masks. */
4173 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4174 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4175 NULL_RTX, 1, OPTAB_DIRECT);
4176 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4177 }
4178
4179 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4180 the memory location, CMP the old value to compare MEM with and NEW the value
4181 to set if CMP == MEM.
4182 CMP is never in memory for compare_and_swap_cc because
4183 expand_bool_compare_and_swap puts it into a register for later compare. */
4184
4185 void
4186 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4187 {
4188 struct alignment_context ac;
4189 rtx cmpv, newv, val, resv, cc;
4190 rtx res = gen_reg_rtx (SImode);
4191 rtx csloop = gen_label_rtx ();
4192 rtx csend = gen_label_rtx ();
4193
4194 gcc_assert (register_operand (target, VOIDmode));
4195 gcc_assert (MEM_P (mem));
4196
4197 init_alignment_context (&ac, mem, mode);
4198
4199 /* Shift the values to the correct bit positions. */
4200 if (!(ac.aligned && MEM_P (cmp)))
4201 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4202 if (!(ac.aligned && MEM_P (new)))
4203 new = s390_expand_mask_and_shift (new, mode, ac.shift);
4204
4205 /* Load full word. Subsequent loads are performed by CS. */
4206 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4207 NULL_RTX, 1, OPTAB_DIRECT);
4208
4209 /* Start CS loop. */
4210 emit_label (csloop);
4211 /* val = "<mem>00..0<mem>"
4212 * cmp = "00..0<cmp>00..0"
4213 * new = "00..0<new>00..0"
4214 */
4215
4216 /* Patch cmp and new with val at correct position. */
4217 if (ac.aligned && MEM_P (cmp))
4218 {
4219 cmpv = force_reg (SImode, val);
4220 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4221 }
4222 else
4223 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4224 NULL_RTX, 1, OPTAB_DIRECT));
4225 if (ac.aligned && MEM_P (new))
4226 {
4227 newv = force_reg (SImode, val);
4228 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4229 }
4230 else
4231 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4232 NULL_RTX, 1, OPTAB_DIRECT));
4233
4234 /* Jump to end if we're done (likely?). */
4235 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4236 cmpv, newv));
4237
4238 /* Check for changes outside mode. */
4239 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4240 NULL_RTX, 1, OPTAB_DIRECT);
4241 cc = s390_emit_compare (NE, resv, val);
4242 emit_move_insn (val, resv);
4243 /* Loop internal if so. */
4244 s390_emit_jump (csloop, cc);
4245
4246 emit_label (csend);
4247
4248 /* Return the correct part of the bitfield. */
4249 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4250 NULL_RTX, 1, OPTAB_DIRECT), 1);
4251 }
4252
4253 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4254 and VAL the value to play with. If AFTER is true then store the value
4255 MEM holds after the operation, if AFTER is false then store the value MEM
4256 holds before the operation. If TARGET is zero then discard that value, else
4257 store it to TARGET. */
4258
4259 void
4260 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4261 rtx target, rtx mem, rtx val, bool after)
4262 {
4263 struct alignment_context ac;
4264 rtx cmp;
4265 rtx new = gen_reg_rtx (SImode);
4266 rtx orig = gen_reg_rtx (SImode);
4267 rtx csloop = gen_label_rtx ();
4268
4269 gcc_assert (!target || register_operand (target, VOIDmode));
4270 gcc_assert (MEM_P (mem));
4271
4272 init_alignment_context (&ac, mem, mode);
4273
4274 /* Shift val to the correct bit positions.
4275 Preserve "icm", but prevent "ex icm". */
4276 if (!(ac.aligned && code == SET && MEM_P (val)))
4277 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4278
4279 /* Further preparation insns. */
4280 if (code == PLUS || code == MINUS)
4281 emit_move_insn (orig, val);
4282 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4283 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4284 NULL_RTX, 1, OPTAB_DIRECT);
4285
4286 /* Load full word. Subsequent loads are performed by CS. */
4287 cmp = force_reg (SImode, ac.memsi);
4288
4289 /* Start CS loop. */
4290 emit_label (csloop);
4291 emit_move_insn (new, cmp);
4292
4293 /* Patch new with val at correct position. */
4294 switch (code)
4295 {
4296 case PLUS:
4297 case MINUS:
4298 val = expand_simple_binop (SImode, code, new, orig,
4299 NULL_RTX, 1, OPTAB_DIRECT);
4300 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4301 NULL_RTX, 1, OPTAB_DIRECT);
4302 /* FALLTHRU */
4303 case SET:
4304 if (ac.aligned && MEM_P (val))
4305 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4306 else
4307 {
4308 new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4309 NULL_RTX, 1, OPTAB_DIRECT);
4310 new = expand_simple_binop (SImode, IOR, new, val,
4311 NULL_RTX, 1, OPTAB_DIRECT);
4312 }
4313 break;
4314 case AND:
4315 case IOR:
4316 case XOR:
4317 new = expand_simple_binop (SImode, code, new, val,
4318 NULL_RTX, 1, OPTAB_DIRECT);
4319 break;
4320 case MULT: /* NAND */
4321 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4322 NULL_RTX, 1, OPTAB_DIRECT);
4323 new = expand_simple_binop (SImode, AND, new, val,
4324 NULL_RTX, 1, OPTAB_DIRECT);
4325 break;
4326 default:
4327 gcc_unreachable ();
4328 }
4329
4330 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4331 ac.memsi, cmp, new));
4332
4333 /* Return the correct part of the bitfield. */
4334 if (target)
4335 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4336 after ? new : cmp, ac.shift,
4337 NULL_RTX, 1, OPTAB_DIRECT), 1);
4338 }
4339
4340 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4341 We need to emit DTP-relative relocations. */
4342
4343 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4344
4345 static void
4346 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4347 {
4348 switch (size)
4349 {
4350 case 4:
4351 fputs ("\t.long\t", file);
4352 break;
4353 case 8:
4354 fputs ("\t.quad\t", file);
4355 break;
4356 default:
4357 gcc_unreachable ();
4358 }
4359 output_addr_const (file, x);
4360 fputs ("@DTPOFF", file);
4361 }
4362
4363 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4364 /* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */
4365
4366 static const char *
4367 s390_mangle_fundamental_type (tree type)
4368 {
4369 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4370 && TARGET_LONG_DOUBLE_128)
4371 return "g";
4372
4373 /* For all other types, use normal C++ mangling. */
4374 return NULL;
4375 }
4376 #endif
4377
4378 /* In the name of slightly smaller debug output, and to cater to
4379 general assembler lossage, recognize various UNSPEC sequences
4380 and turn them back into a direct symbol reference. */
4381
4382 static rtx
4383 s390_delegitimize_address (rtx orig_x)
4384 {
4385 rtx x = orig_x, y;
4386
4387 if (GET_CODE (x) != MEM)
4388 return orig_x;
4389
4390 x = XEXP (x, 0);
4391 if (GET_CODE (x) == PLUS
4392 && GET_CODE (XEXP (x, 1)) == CONST
4393 && GET_CODE (XEXP (x, 0)) == REG
4394 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4395 {
4396 y = XEXP (XEXP (x, 1), 0);
4397 if (GET_CODE (y) == UNSPEC
4398 && XINT (y, 1) == UNSPEC_GOT)
4399 return XVECEXP (y, 0, 0);
4400 return orig_x;
4401 }
4402
4403 if (GET_CODE (x) == CONST)
4404 {
4405 y = XEXP (x, 0);
4406 if (GET_CODE (y) == UNSPEC
4407 && XINT (y, 1) == UNSPEC_GOTENT)
4408 return XVECEXP (y, 0, 0);
4409 return orig_x;
4410 }
4411
4412 return orig_x;
4413 }
4414
4415 /* Output operand OP to stdio stream FILE.
4416 OP is an address (register + offset) which is not used to address data;
4417 instead the rightmost bits are interpreted as the value. */
4418
4419 static void
4420 print_shift_count_operand (FILE *file, rtx op)
4421 {
4422 HOST_WIDE_INT offset;
4423 rtx base;
4424
4425 /* Extract base register and offset. */
4426 if (!s390_decompose_shift_count (op, &base, &offset))
4427 gcc_unreachable ();
4428
4429 /* Sanity check. */
4430 if (base)
4431 {
4432 gcc_assert (GET_CODE (base) == REG);
4433 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4434 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4435 }
4436
4437 /* Offsets are constricted to twelve bits. */
4438 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4439 if (base)
4440 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4441 }
4442
4443 /* See 'get_some_local_dynamic_name'. */
4444
4445 static int
4446 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4447 {
4448 rtx x = *px;
4449
4450 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4451 {
4452 x = get_pool_constant (x);
4453 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4454 }
4455
4456 if (GET_CODE (x) == SYMBOL_REF
4457 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4458 {
4459 cfun->machine->some_ld_name = XSTR (x, 0);
4460 return 1;
4461 }
4462
4463 return 0;
4464 }
4465
4466 /* Locate some local-dynamic symbol still in use by this function
4467 so that we can print its name in local-dynamic base patterns. */
4468
4469 static const char *
4470 get_some_local_dynamic_name (void)
4471 {
4472 rtx insn;
4473
4474 if (cfun->machine->some_ld_name)
4475 return cfun->machine->some_ld_name;
4476
4477 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4478 if (INSN_P (insn)
4479 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4480 return cfun->machine->some_ld_name;
4481
4482 gcc_unreachable ();
4483 }
4484
4485 /* Output machine-dependent UNSPECs occurring in address constant X
4486 in assembler syntax to stdio stream FILE. Returns true if the
4487 constant X could be recognized, false otherwise. */
4488
4489 bool
4490 s390_output_addr_const_extra (FILE *file, rtx x)
4491 {
4492 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4493 switch (XINT (x, 1))
4494 {
4495 case UNSPEC_GOTENT:
4496 output_addr_const (file, XVECEXP (x, 0, 0));
4497 fprintf (file, "@GOTENT");
4498 return true;
4499 case UNSPEC_GOT:
4500 output_addr_const (file, XVECEXP (x, 0, 0));
4501 fprintf (file, "@GOT");
4502 return true;
4503 case UNSPEC_GOTOFF:
4504 output_addr_const (file, XVECEXP (x, 0, 0));
4505 fprintf (file, "@GOTOFF");
4506 return true;
4507 case UNSPEC_PLT:
4508 output_addr_const (file, XVECEXP (x, 0, 0));
4509 fprintf (file, "@PLT");
4510 return true;
4511 case UNSPEC_PLTOFF:
4512 output_addr_const (file, XVECEXP (x, 0, 0));
4513 fprintf (file, "@PLTOFF");
4514 return true;
4515 case UNSPEC_TLSGD:
4516 output_addr_const (file, XVECEXP (x, 0, 0));
4517 fprintf (file, "@TLSGD");
4518 return true;
4519 case UNSPEC_TLSLDM:
4520 assemble_name (file, get_some_local_dynamic_name ());
4521 fprintf (file, "@TLSLDM");
4522 return true;
4523 case UNSPEC_DTPOFF:
4524 output_addr_const (file, XVECEXP (x, 0, 0));
4525 fprintf (file, "@DTPOFF");
4526 return true;
4527 case UNSPEC_NTPOFF:
4528 output_addr_const (file, XVECEXP (x, 0, 0));
4529 fprintf (file, "@NTPOFF");
4530 return true;
4531 case UNSPEC_GOTNTPOFF:
4532 output_addr_const (file, XVECEXP (x, 0, 0));
4533 fprintf (file, "@GOTNTPOFF");
4534 return true;
4535 case UNSPEC_INDNTPOFF:
4536 output_addr_const (file, XVECEXP (x, 0, 0));
4537 fprintf (file, "@INDNTPOFF");
4538 return true;
4539 }
4540
4541 return false;
4542 }
4543
4544 /* Output address operand ADDR in assembler syntax to
4545 stdio stream FILE. */
4546
4547 void
4548 print_operand_address (FILE *file, rtx addr)
4549 {
4550 struct s390_address ad;
4551
4552 if (!s390_decompose_address (addr, &ad)
4553 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4554 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4555 output_operand_lossage ("cannot decompose address");
4556
4557 if (ad.disp)
4558 output_addr_const (file, ad.disp);
4559 else
4560 fprintf (file, "0");
4561
4562 if (ad.base && ad.indx)
4563 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4564 reg_names[REGNO (ad.base)]);
4565 else if (ad.base)
4566 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4567 }
4568
4569 /* Output operand X in assembler syntax to stdio stream FILE.
4570 CODE specified the format flag. The following format flags
4571 are recognized:
4572
4573 'C': print opcode suffix for branch condition.
4574 'D': print opcode suffix for inverse branch condition.
4575 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4576 'G': print the size of the operand in bytes.
4577 'O': print only the displacement of a memory reference.
4578 'R': print only the base register of a memory reference.
4579 'S': print S-type memory reference (base+displacement).
4580 'N': print the second word of a DImode operand.
4581 'M': print the second word of a TImode operand.
4582 'Y': print shift count operand.
4583
4584 'b': print integer X as if it's an unsigned byte.
4585 'x': print integer X as if it's an unsigned halfword.
4586 'h': print integer X as if it's a signed halfword.
4587 'i': print the first nonzero HImode part of X.
4588 'j': print the first HImode part unequal to -1 of X.
4589 'k': print the first nonzero SImode part of X.
4590 'm': print the first SImode part unequal to -1 of X.
4591 'o': print integer X as if it's an unsigned 32bit word. */
4592
4593 void
4594 print_operand (FILE *file, rtx x, int code)
4595 {
4596 switch (code)
4597 {
4598 case 'C':
4599 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4600 return;
4601
4602 case 'D':
4603 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4604 return;
4605
4606 case 'J':
4607 if (GET_CODE (x) == SYMBOL_REF)
4608 {
4609 fprintf (file, "%s", ":tls_load:");
4610 output_addr_const (file, x);
4611 }
4612 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4613 {
4614 fprintf (file, "%s", ":tls_gdcall:");
4615 output_addr_const (file, XVECEXP (x, 0, 0));
4616 }
4617 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4618 {
4619 fprintf (file, "%s", ":tls_ldcall:");
4620 assemble_name (file, get_some_local_dynamic_name ());
4621 }
4622 else
4623 gcc_unreachable ();
4624 return;
4625
4626 case 'G':
4627 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4628 return;
4629
4630 case 'O':
4631 {
4632 struct s390_address ad;
4633 int ret;
4634
4635 gcc_assert (GET_CODE (x) == MEM);
4636 ret = s390_decompose_address (XEXP (x, 0), &ad);
4637 gcc_assert (ret);
4638 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4639 gcc_assert (!ad.indx);
4640
4641 if (ad.disp)
4642 output_addr_const (file, ad.disp);
4643 else
4644 fprintf (file, "0");
4645 }
4646 return;
4647
4648 case 'R':
4649 {
4650 struct s390_address ad;
4651 int ret;
4652
4653 gcc_assert (GET_CODE (x) == MEM);
4654 ret = s390_decompose_address (XEXP (x, 0), &ad);
4655 gcc_assert (ret);
4656 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4657 gcc_assert (!ad.indx);
4658
4659 if (ad.base)
4660 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4661 else
4662 fprintf (file, "0");
4663 }
4664 return;
4665
4666 case 'S':
4667 {
4668 struct s390_address ad;
4669 int ret;
4670
4671 gcc_assert (GET_CODE (x) == MEM);
4672 ret = s390_decompose_address (XEXP (x, 0), &ad);
4673 gcc_assert (ret);
4674 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4675 gcc_assert (!ad.indx);
4676
4677 if (ad.disp)
4678 output_addr_const (file, ad.disp);
4679 else
4680 fprintf (file, "0");
4681
4682 if (ad.base)
4683 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4684 }
4685 return;
4686
4687 case 'N':
4688 if (GET_CODE (x) == REG)
4689 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4690 else if (GET_CODE (x) == MEM)
4691 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4692 else
4693 gcc_unreachable ();
4694 break;
4695
4696 case 'M':
4697 if (GET_CODE (x) == REG)
4698 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4699 else if (GET_CODE (x) == MEM)
4700 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4701 else
4702 gcc_unreachable ();
4703 break;
4704
4705 case 'Y':
4706 print_shift_count_operand (file, x);
4707 return;
4708 }
4709
4710 switch (GET_CODE (x))
4711 {
4712 case REG:
4713 fprintf (file, "%s", reg_names[REGNO (x)]);
4714 break;
4715
4716 case MEM:
4717 output_address (XEXP (x, 0));
4718 break;
4719
4720 case CONST:
4721 case CODE_LABEL:
4722 case LABEL_REF:
4723 case SYMBOL_REF:
4724 output_addr_const (file, x);
4725 break;
4726
4727 case CONST_INT:
4728 if (code == 'b')
4729 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4730 else if (code == 'x')
4731 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4732 else if (code == 'h')
4733 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4734 else if (code == 'i')
4735 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4736 s390_extract_part (x, HImode, 0));
4737 else if (code == 'j')
4738 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4739 s390_extract_part (x, HImode, -1));
4740 else if (code == 'k')
4741 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4742 s390_extract_part (x, SImode, 0));
4743 else if (code == 'm')
4744 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4745 s390_extract_part (x, SImode, -1));
4746 else if (code == 'o')
4747 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4748 else
4749 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4750 break;
4751
4752 case CONST_DOUBLE:
4753 gcc_assert (GET_MODE (x) == VOIDmode);
4754 if (code == 'b')
4755 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4756 else if (code == 'x')
4757 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4758 else if (code == 'h')
4759 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4760 else
4761 gcc_unreachable ();
4762 break;
4763
4764 default:
4765 fatal_insn ("UNKNOWN in print_operand !?", x);
4766 break;
4767 }
4768 }
4769
4770 /* Target hook for assembling integer objects. We need to define it
4771 here to work a round a bug in some versions of GAS, which couldn't
4772 handle values smaller than INT_MIN when printed in decimal. */
4773
4774 static bool
4775 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4776 {
4777 if (size == 8 && aligned_p
4778 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4779 {
4780 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4781 INTVAL (x));
4782 return true;
4783 }
4784 return default_assemble_integer (x, size, aligned_p);
4785 }
4786
4787 /* Returns true if register REGNO is used for forming
4788 a memory address in expression X. */
4789
4790 static bool
4791 reg_used_in_mem_p (int regno, rtx x)
4792 {
4793 enum rtx_code code = GET_CODE (x);
4794 int i, j;
4795 const char *fmt;
4796
4797 if (code == MEM)
4798 {
4799 if (refers_to_regno_p (regno, regno+1,
4800 XEXP (x, 0), 0))
4801 return true;
4802 }
4803 else if (code == SET
4804 && GET_CODE (SET_DEST (x)) == PC)
4805 {
4806 if (refers_to_regno_p (regno, regno+1,
4807 SET_SRC (x), 0))
4808 return true;
4809 }
4810
4811 fmt = GET_RTX_FORMAT (code);
4812 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4813 {
4814 if (fmt[i] == 'e'
4815 && reg_used_in_mem_p (regno, XEXP (x, i)))
4816 return true;
4817
4818 else if (fmt[i] == 'E')
4819 for (j = 0; j < XVECLEN (x, i); j++)
4820 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4821 return true;
4822 }
4823 return false;
4824 }
4825
4826 /* Returns true if expression DEP_RTX sets an address register
4827 used by instruction INSN to address memory. */
4828
4829 static bool
4830 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4831 {
4832 rtx target, pat;
4833
4834 if (GET_CODE (dep_rtx) == INSN)
4835 dep_rtx = PATTERN (dep_rtx);
4836
4837 if (GET_CODE (dep_rtx) == SET)
4838 {
4839 target = SET_DEST (dep_rtx);
4840 if (GET_CODE (target) == STRICT_LOW_PART)
4841 target = XEXP (target, 0);
4842 while (GET_CODE (target) == SUBREG)
4843 target = SUBREG_REG (target);
4844
4845 if (GET_CODE (target) == REG)
4846 {
4847 int regno = REGNO (target);
4848
4849 if (s390_safe_attr_type (insn) == TYPE_LA)
4850 {
4851 pat = PATTERN (insn);
4852 if (GET_CODE (pat) == PARALLEL)
4853 {
4854 gcc_assert (XVECLEN (pat, 0) == 2);
4855 pat = XVECEXP (pat, 0, 0);
4856 }
4857 gcc_assert (GET_CODE (pat) == SET);
4858 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4859 }
4860 else if (get_attr_atype (insn) == ATYPE_AGEN)
4861 return reg_used_in_mem_p (regno, PATTERN (insn));
4862 }
4863 }
4864 return false;
4865 }
4866
4867 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4868
4869 int
4870 s390_agen_dep_p (rtx dep_insn, rtx insn)
4871 {
4872 rtx dep_rtx = PATTERN (dep_insn);
4873 int i;
4874
4875 if (GET_CODE (dep_rtx) == SET
4876 && addr_generation_dependency_p (dep_rtx, insn))
4877 return 1;
4878 else if (GET_CODE (dep_rtx) == PARALLEL)
4879 {
4880 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4881 {
4882 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4883 return 1;
4884 }
4885 }
4886 return 0;
4887 }
4888
4889 /* A C statement (sans semicolon) to update the integer scheduling priority
4890 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4891 reduce the priority to execute INSN later. Do not define this macro if
4892 you do not need to adjust the scheduling priorities of insns.
4893
4894 A STD instruction should be scheduled earlier,
4895 in order to use the bypass. */
4896
4897 static int
4898 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4899 {
4900 if (! INSN_P (insn))
4901 return priority;
4902
4903 if (s390_tune != PROCESSOR_2084_Z990
4904 && s390_tune != PROCESSOR_2094_Z9_109)
4905 return priority;
4906
4907 switch (s390_safe_attr_type (insn))
4908 {
4909 case TYPE_FSTOREDF:
4910 case TYPE_FSTORESF:
4911 priority = priority << 3;
4912 break;
4913 case TYPE_STORE:
4914 case TYPE_STM:
4915 priority = priority << 1;
4916 break;
4917 default:
4918 break;
4919 }
4920 return priority;
4921 }
4922
4923 /* The number of instructions that can be issued per cycle. */
4924
4925 static int
4926 s390_issue_rate (void)
4927 {
4928 if (s390_tune == PROCESSOR_2084_Z990
4929 || s390_tune == PROCESSOR_2094_Z9_109)
4930 return 3;
4931 return 1;
4932 }
4933
4934 static int
4935 s390_first_cycle_multipass_dfa_lookahead (void)
4936 {
4937 return 4;
4938 }
4939
4940
4941 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4942 Fix up MEMs as required. */
4943
4944 static void
4945 annotate_constant_pool_refs (rtx *x)
4946 {
4947 int i, j;
4948 const char *fmt;
4949
4950 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4951 || !CONSTANT_POOL_ADDRESS_P (*x));
4952
4953 /* Literal pool references can only occur inside a MEM ... */
4954 if (GET_CODE (*x) == MEM)
4955 {
4956 rtx memref = XEXP (*x, 0);
4957
4958 if (GET_CODE (memref) == SYMBOL_REF
4959 && CONSTANT_POOL_ADDRESS_P (memref))
4960 {
4961 rtx base = cfun->machine->base_reg;
4962 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4963 UNSPEC_LTREF);
4964
4965 *x = replace_equiv_address (*x, addr);
4966 return;
4967 }
4968
4969 if (GET_CODE (memref) == CONST
4970 && GET_CODE (XEXP (memref, 0)) == PLUS
4971 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4972 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4973 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4974 {
4975 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4976 rtx sym = XEXP (XEXP (memref, 0), 0);
4977 rtx base = cfun->machine->base_reg;
4978 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4979 UNSPEC_LTREF);
4980
4981 *x = replace_equiv_address (*x, plus_constant (addr, off));
4982 return;
4983 }
4984 }
4985
4986 /* ... or a load-address type pattern. */
4987 if (GET_CODE (*x) == SET)
4988 {
4989 rtx addrref = SET_SRC (*x);
4990
4991 if (GET_CODE (addrref) == SYMBOL_REF
4992 && CONSTANT_POOL_ADDRESS_P (addrref))
4993 {
4994 rtx base = cfun->machine->base_reg;
4995 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4996 UNSPEC_LTREF);
4997
4998 SET_SRC (*x) = addr;
4999 return;
5000 }
5001
5002 if (GET_CODE (addrref) == CONST
5003 && GET_CODE (XEXP (addrref, 0)) == PLUS
5004 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5005 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5006 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5007 {
5008 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5009 rtx sym = XEXP (XEXP (addrref, 0), 0);
5010 rtx base = cfun->machine->base_reg;
5011 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5012 UNSPEC_LTREF);
5013
5014 SET_SRC (*x) = plus_constant (addr, off);
5015 return;
5016 }
5017 }
5018
5019 /* Annotate LTREL_BASE as well. */
5020 if (GET_CODE (*x) == UNSPEC
5021 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5022 {
5023 rtx base = cfun->machine->base_reg;
5024 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5025 UNSPEC_LTREL_BASE);
5026 return;
5027 }
5028
5029 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5030 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5031 {
5032 if (fmt[i] == 'e')
5033 {
5034 annotate_constant_pool_refs (&XEXP (*x, i));
5035 }
5036 else if (fmt[i] == 'E')
5037 {
5038 for (j = 0; j < XVECLEN (*x, i); j++)
5039 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5040 }
5041 }
5042 }
5043
5044 /* Split all branches that exceed the maximum distance.
5045 Returns true if this created a new literal pool entry. */
5046
5047 static int
5048 s390_split_branches (void)
5049 {
5050 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5051 int new_literal = 0, ret;
5052 rtx insn, pat, tmp, target;
5053 rtx *label;
5054
5055 /* We need correct insn addresses. */
5056
5057 shorten_branches (get_insns ());
5058
5059 /* Find all branches that exceed 64KB, and split them. */
5060
5061 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5062 {
5063 if (GET_CODE (insn) != JUMP_INSN)
5064 continue;
5065
5066 pat = PATTERN (insn);
5067 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5068 pat = XVECEXP (pat, 0, 0);
5069 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5070 continue;
5071
5072 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5073 {
5074 label = &SET_SRC (pat);
5075 }
5076 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5077 {
5078 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5079 label = &XEXP (SET_SRC (pat), 1);
5080 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5081 label = &XEXP (SET_SRC (pat), 2);
5082 else
5083 continue;
5084 }
5085 else
5086 continue;
5087
5088 if (get_attr_length (insn) <= 4)
5089 continue;
5090
5091 /* We are going to use the return register as scratch register,
5092 make sure it will be saved/restored by the prologue/epilogue. */
5093 cfun_frame_layout.save_return_addr_p = 1;
5094
5095 if (!flag_pic)
5096 {
5097 new_literal = 1;
5098 tmp = force_const_mem (Pmode, *label);
5099 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5100 INSN_ADDRESSES_NEW (tmp, -1);
5101 annotate_constant_pool_refs (&PATTERN (tmp));
5102
5103 target = temp_reg;
5104 }
5105 else
5106 {
5107 new_literal = 1;
5108 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5109 UNSPEC_LTREL_OFFSET);
5110 target = gen_rtx_CONST (Pmode, target);
5111 target = force_const_mem (Pmode, target);
5112 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5113 INSN_ADDRESSES_NEW (tmp, -1);
5114 annotate_constant_pool_refs (&PATTERN (tmp));
5115
5116 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5117 cfun->machine->base_reg),
5118 UNSPEC_LTREL_BASE);
5119 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5120 }
5121
5122 ret = validate_change (insn, label, target, 0);
5123 gcc_assert (ret);
5124 }
5125
5126 return new_literal;
5127 }
5128
5129
5130 /* Find an annotated literal pool symbol referenced in RTX X,
5131 and store it at REF. Will abort if X contains references to
5132 more than one such pool symbol; multiple references to the same
5133 symbol are allowed, however.
5134
5135 The rtx pointed to by REF must be initialized to NULL_RTX
5136 by the caller before calling this routine. */
5137
5138 static void
5139 find_constant_pool_ref (rtx x, rtx *ref)
5140 {
5141 int i, j;
5142 const char *fmt;
5143
5144 /* Ignore LTREL_BASE references. */
5145 if (GET_CODE (x) == UNSPEC
5146 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5147 return;
5148 /* Likewise POOL_ENTRY insns. */
5149 if (GET_CODE (x) == UNSPEC_VOLATILE
5150 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5151 return;
5152
5153 gcc_assert (GET_CODE (x) != SYMBOL_REF
5154 || !CONSTANT_POOL_ADDRESS_P (x));
5155
5156 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5157 {
5158 rtx sym = XVECEXP (x, 0, 0);
5159 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5160 && CONSTANT_POOL_ADDRESS_P (sym));
5161
5162 if (*ref == NULL_RTX)
5163 *ref = sym;
5164 else
5165 gcc_assert (*ref == sym);
5166
5167 return;
5168 }
5169
5170 fmt = GET_RTX_FORMAT (GET_CODE (x));
5171 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5172 {
5173 if (fmt[i] == 'e')
5174 {
5175 find_constant_pool_ref (XEXP (x, i), ref);
5176 }
5177 else if (fmt[i] == 'E')
5178 {
5179 for (j = 0; j < XVECLEN (x, i); j++)
5180 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5181 }
5182 }
5183 }
5184
5185 /* Replace every reference to the annotated literal pool
5186 symbol REF in X by its base plus OFFSET. */
5187
5188 static void
5189 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5190 {
5191 int i, j;
5192 const char *fmt;
5193
5194 gcc_assert (*x != ref);
5195
5196 if (GET_CODE (*x) == UNSPEC
5197 && XINT (*x, 1) == UNSPEC_LTREF
5198 && XVECEXP (*x, 0, 0) == ref)
5199 {
5200 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5201 return;
5202 }
5203
5204 if (GET_CODE (*x) == PLUS
5205 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5206 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5207 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5208 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5209 {
5210 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5211 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5212 return;
5213 }
5214
5215 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5216 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5217 {
5218 if (fmt[i] == 'e')
5219 {
5220 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5221 }
5222 else if (fmt[i] == 'E')
5223 {
5224 for (j = 0; j < XVECLEN (*x, i); j++)
5225 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5226 }
5227 }
5228 }
5229
5230 /* Check whether X contains an UNSPEC_LTREL_BASE.
5231 Return its constant pool symbol if found, NULL_RTX otherwise. */
5232
5233 static rtx
5234 find_ltrel_base (rtx x)
5235 {
5236 int i, j;
5237 const char *fmt;
5238
5239 if (GET_CODE (x) == UNSPEC
5240 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5241 return XVECEXP (x, 0, 0);
5242
5243 fmt = GET_RTX_FORMAT (GET_CODE (x));
5244 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5245 {
5246 if (fmt[i] == 'e')
5247 {
5248 rtx fnd = find_ltrel_base (XEXP (x, i));
5249 if (fnd)
5250 return fnd;
5251 }
5252 else if (fmt[i] == 'E')
5253 {
5254 for (j = 0; j < XVECLEN (x, i); j++)
5255 {
5256 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5257 if (fnd)
5258 return fnd;
5259 }
5260 }
5261 }
5262
5263 return NULL_RTX;
5264 }
5265
5266 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5267
5268 static void
5269 replace_ltrel_base (rtx *x)
5270 {
5271 int i, j;
5272 const char *fmt;
5273
5274 if (GET_CODE (*x) == UNSPEC
5275 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5276 {
5277 *x = XVECEXP (*x, 0, 1);
5278 return;
5279 }
5280
5281 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5282 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5283 {
5284 if (fmt[i] == 'e')
5285 {
5286 replace_ltrel_base (&XEXP (*x, i));
5287 }
5288 else if (fmt[i] == 'E')
5289 {
5290 for (j = 0; j < XVECLEN (*x, i); j++)
5291 replace_ltrel_base (&XVECEXP (*x, i, j));
5292 }
5293 }
5294 }
5295
5296
5297 /* We keep a list of constants which we have to add to internal
5298 constant tables in the middle of large functions. */
5299
5300 #define NR_C_MODES 11
5301 enum machine_mode constant_modes[NR_C_MODES] =
5302 {
5303 TFmode, TImode, TDmode,
5304 DFmode, DImode, DDmode,
5305 SFmode, SImode, SDmode,
5306 HImode,
5307 QImode
5308 };
5309
5310 struct constant
5311 {
5312 struct constant *next;
5313 rtx value;
5314 rtx label;
5315 };
5316
5317 struct constant_pool
5318 {
5319 struct constant_pool *next;
5320 rtx first_insn;
5321 rtx pool_insn;
5322 bitmap insns;
5323
5324 struct constant *constants[NR_C_MODES];
5325 struct constant *execute;
5326 rtx label;
5327 int size;
5328 };
5329
5330 /* Allocate new constant_pool structure. */
5331
5332 static struct constant_pool *
5333 s390_alloc_pool (void)
5334 {
5335 struct constant_pool *pool;
5336 int i;
5337
5338 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5339 pool->next = NULL;
5340 for (i = 0; i < NR_C_MODES; i++)
5341 pool->constants[i] = NULL;
5342
5343 pool->execute = NULL;
5344 pool->label = gen_label_rtx ();
5345 pool->first_insn = NULL_RTX;
5346 pool->pool_insn = NULL_RTX;
5347 pool->insns = BITMAP_ALLOC (NULL);
5348 pool->size = 0;
5349
5350 return pool;
5351 }
5352
5353 /* Create new constant pool covering instructions starting at INSN
5354 and chain it to the end of POOL_LIST. */
5355
5356 static struct constant_pool *
5357 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5358 {
5359 struct constant_pool *pool, **prev;
5360
5361 pool = s390_alloc_pool ();
5362 pool->first_insn = insn;
5363
5364 for (prev = pool_list; *prev; prev = &(*prev)->next)
5365 ;
5366 *prev = pool;
5367
5368 return pool;
5369 }
5370
5371 /* End range of instructions covered by POOL at INSN and emit
5372 placeholder insn representing the pool. */
5373
5374 static void
5375 s390_end_pool (struct constant_pool *pool, rtx insn)
5376 {
5377 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5378
5379 if (!insn)
5380 insn = get_last_insn ();
5381
5382 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5383 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5384 }
5385
5386 /* Add INSN to the list of insns covered by POOL. */
5387
5388 static void
5389 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5390 {
5391 bitmap_set_bit (pool->insns, INSN_UID (insn));
5392 }
5393
5394 /* Return pool out of POOL_LIST that covers INSN. */
5395
5396 static struct constant_pool *
5397 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5398 {
5399 struct constant_pool *pool;
5400
5401 for (pool = pool_list; pool; pool = pool->next)
5402 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5403 break;
5404
5405 return pool;
5406 }
5407
5408 /* Add constant VAL of mode MODE to the constant pool POOL. */
5409
5410 static void
5411 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5412 {
5413 struct constant *c;
5414 int i;
5415
5416 for (i = 0; i < NR_C_MODES; i++)
5417 if (constant_modes[i] == mode)
5418 break;
5419 gcc_assert (i != NR_C_MODES);
5420
5421 for (c = pool->constants[i]; c != NULL; c = c->next)
5422 if (rtx_equal_p (val, c->value))
5423 break;
5424
5425 if (c == NULL)
5426 {
5427 c = (struct constant *) xmalloc (sizeof *c);
5428 c->value = val;
5429 c->label = gen_label_rtx ();
5430 c->next = pool->constants[i];
5431 pool->constants[i] = c;
5432 pool->size += GET_MODE_SIZE (mode);
5433 }
5434 }
5435
5436 /* Find constant VAL of mode MODE in the constant pool POOL.
5437 Return an RTX describing the distance from the start of
5438 the pool to the location of the new constant. */
5439
5440 static rtx
5441 s390_find_constant (struct constant_pool *pool, rtx val,
5442 enum machine_mode mode)
5443 {
5444 struct constant *c;
5445 rtx offset;
5446 int i;
5447
5448 for (i = 0; i < NR_C_MODES; i++)
5449 if (constant_modes[i] == mode)
5450 break;
5451 gcc_assert (i != NR_C_MODES);
5452
5453 for (c = pool->constants[i]; c != NULL; c = c->next)
5454 if (rtx_equal_p (val, c->value))
5455 break;
5456
5457 gcc_assert (c);
5458
5459 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5460 gen_rtx_LABEL_REF (Pmode, pool->label));
5461 offset = gen_rtx_CONST (Pmode, offset);
5462 return offset;
5463 }
5464
5465 /* Check whether INSN is an execute. Return the label_ref to its
5466 execute target template if so, NULL_RTX otherwise. */
5467
5468 static rtx
5469 s390_execute_label (rtx insn)
5470 {
5471 if (GET_CODE (insn) == INSN
5472 && GET_CODE (PATTERN (insn)) == PARALLEL
5473 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5474 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5475 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5476
5477 return NULL_RTX;
5478 }
5479
5480 /* Add execute target for INSN to the constant pool POOL. */
5481
5482 static void
5483 s390_add_execute (struct constant_pool *pool, rtx insn)
5484 {
5485 struct constant *c;
5486
5487 for (c = pool->execute; c != NULL; c = c->next)
5488 if (INSN_UID (insn) == INSN_UID (c->value))
5489 break;
5490
5491 if (c == NULL)
5492 {
5493 c = (struct constant *) xmalloc (sizeof *c);
5494 c->value = insn;
5495 c->label = gen_label_rtx ();
5496 c->next = pool->execute;
5497 pool->execute = c;
5498 pool->size += 6;
5499 }
5500 }
5501
5502 /* Find execute target for INSN in the constant pool POOL.
5503 Return an RTX describing the distance from the start of
5504 the pool to the location of the execute target. */
5505
5506 static rtx
5507 s390_find_execute (struct constant_pool *pool, rtx insn)
5508 {
5509 struct constant *c;
5510 rtx offset;
5511
5512 for (c = pool->execute; c != NULL; c = c->next)
5513 if (INSN_UID (insn) == INSN_UID (c->value))
5514 break;
5515
5516 gcc_assert (c);
5517
5518 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5519 gen_rtx_LABEL_REF (Pmode, pool->label));
5520 offset = gen_rtx_CONST (Pmode, offset);
5521 return offset;
5522 }
5523
5524 /* For an execute INSN, extract the execute target template. */
5525
5526 static rtx
5527 s390_execute_target (rtx insn)
5528 {
5529 rtx pattern = PATTERN (insn);
5530 gcc_assert (s390_execute_label (insn));
5531
5532 if (XVECLEN (pattern, 0) == 2)
5533 {
5534 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5535 }
5536 else
5537 {
5538 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5539 int i;
5540
5541 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5542 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5543
5544 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5545 }
5546
5547 return pattern;
5548 }
5549
5550 /* Indicate that INSN cannot be duplicated. This is the case for
5551 execute insns that carry a unique label. */
5552
5553 static bool
5554 s390_cannot_copy_insn_p (rtx insn)
5555 {
5556 rtx label = s390_execute_label (insn);
5557 return label && label != const0_rtx;
5558 }
5559
5560 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5561 do not emit the pool base label. */
5562
5563 static void
5564 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5565 {
5566 struct constant *c;
5567 rtx insn = pool->pool_insn;
5568 int i;
5569
5570 /* Switch to rodata section. */
5571 if (TARGET_CPU_ZARCH)
5572 {
5573 insn = emit_insn_after (gen_pool_section_start (), insn);
5574 INSN_ADDRESSES_NEW (insn, -1);
5575 }
5576
5577 /* Ensure minimum pool alignment. */
5578 if (TARGET_CPU_ZARCH)
5579 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5580 else
5581 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5582 INSN_ADDRESSES_NEW (insn, -1);
5583
5584 /* Emit pool base label. */
5585 if (!remote_label)
5586 {
5587 insn = emit_label_after (pool->label, insn);
5588 INSN_ADDRESSES_NEW (insn, -1);
5589 }
5590
5591 /* Dump constants in descending alignment requirement order,
5592 ensuring proper alignment for every constant. */
5593 for (i = 0; i < NR_C_MODES; i++)
5594 for (c = pool->constants[i]; c; c = c->next)
5595 {
5596 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5597 rtx value = c->value;
5598 if (GET_CODE (value) == CONST
5599 && GET_CODE (XEXP (value, 0)) == UNSPEC
5600 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5601 && XVECLEN (XEXP (value, 0), 0) == 1)
5602 {
5603 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5604 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5605 value = gen_rtx_CONST (VOIDmode, value);
5606 }
5607
5608 insn = emit_label_after (c->label, insn);
5609 INSN_ADDRESSES_NEW (insn, -1);
5610
5611 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5612 gen_rtvec (1, value),
5613 UNSPECV_POOL_ENTRY);
5614 insn = emit_insn_after (value, insn);
5615 INSN_ADDRESSES_NEW (insn, -1);
5616 }
5617
5618 /* Ensure minimum alignment for instructions. */
5619 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5620 INSN_ADDRESSES_NEW (insn, -1);
5621
5622 /* Output in-pool execute template insns. */
5623 for (c = pool->execute; c; c = c->next)
5624 {
5625 insn = emit_label_after (c->label, insn);
5626 INSN_ADDRESSES_NEW (insn, -1);
5627
5628 insn = emit_insn_after (s390_execute_target (c->value), insn);
5629 INSN_ADDRESSES_NEW (insn, -1);
5630 }
5631
5632 /* Switch back to previous section. */
5633 if (TARGET_CPU_ZARCH)
5634 {
5635 insn = emit_insn_after (gen_pool_section_end (), insn);
5636 INSN_ADDRESSES_NEW (insn, -1);
5637 }
5638
5639 insn = emit_barrier_after (insn);
5640 INSN_ADDRESSES_NEW (insn, -1);
5641
5642 /* Remove placeholder insn. */
5643 remove_insn (pool->pool_insn);
5644 }
5645
5646 /* Free all memory used by POOL. */
5647
5648 static void
5649 s390_free_pool (struct constant_pool *pool)
5650 {
5651 struct constant *c, *next;
5652 int i;
5653
5654 for (i = 0; i < NR_C_MODES; i++)
5655 for (c = pool->constants[i]; c; c = next)
5656 {
5657 next = c->next;
5658 free (c);
5659 }
5660
5661 for (c = pool->execute; c; c = next)
5662 {
5663 next = c->next;
5664 free (c);
5665 }
5666
5667 BITMAP_FREE (pool->insns);
5668 free (pool);
5669 }
5670
5671
5672 /* Collect main literal pool. Return NULL on overflow. */
5673
5674 static struct constant_pool *
5675 s390_mainpool_start (void)
5676 {
5677 struct constant_pool *pool;
5678 rtx insn;
5679
5680 pool = s390_alloc_pool ();
5681
5682 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5683 {
5684 if (GET_CODE (insn) == INSN
5685 && GET_CODE (PATTERN (insn)) == SET
5686 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5687 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5688 {
5689 gcc_assert (!pool->pool_insn);
5690 pool->pool_insn = insn;
5691 }
5692
5693 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5694 {
5695 s390_add_execute (pool, insn);
5696 }
5697 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5698 {
5699 rtx pool_ref = NULL_RTX;
5700 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5701 if (pool_ref)
5702 {
5703 rtx constant = get_pool_constant (pool_ref);
5704 enum machine_mode mode = get_pool_mode (pool_ref);
5705 s390_add_constant (pool, constant, mode);
5706 }
5707 }
5708 }
5709
5710 gcc_assert (pool->pool_insn || pool->size == 0);
5711
5712 if (pool->size >= 4096)
5713 {
5714 /* We're going to chunkify the pool, so remove the main
5715 pool placeholder insn. */
5716 remove_insn (pool->pool_insn);
5717
5718 s390_free_pool (pool);
5719 pool = NULL;
5720 }
5721
5722 return pool;
5723 }
5724
5725 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5726 Modify the current function to output the pool constants as well as
5727 the pool register setup instruction. */
5728
5729 static void
5730 s390_mainpool_finish (struct constant_pool *pool)
5731 {
5732 rtx base_reg = cfun->machine->base_reg;
5733 rtx insn;
5734
5735 /* If the pool is empty, we're done. */
5736 if (pool->size == 0)
5737 {
5738 /* We don't actually need a base register after all. */
5739 cfun->machine->base_reg = NULL_RTX;
5740
5741 if (pool->pool_insn)
5742 remove_insn (pool->pool_insn);
5743 s390_free_pool (pool);
5744 return;
5745 }
5746
5747 /* We need correct insn addresses. */
5748 shorten_branches (get_insns ());
5749
5750 /* On zSeries, we use a LARL to load the pool register. The pool is
5751 located in the .rodata section, so we emit it after the function. */
5752 if (TARGET_CPU_ZARCH)
5753 {
5754 insn = gen_main_base_64 (base_reg, pool->label);
5755 insn = emit_insn_after (insn, pool->pool_insn);
5756 INSN_ADDRESSES_NEW (insn, -1);
5757 remove_insn (pool->pool_insn);
5758
5759 insn = get_last_insn ();
5760 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5761 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5762
5763 s390_dump_pool (pool, 0);
5764 }
5765
5766 /* On S/390, if the total size of the function's code plus literal pool
5767 does not exceed 4096 bytes, we use BASR to set up a function base
5768 pointer, and emit the literal pool at the end of the function. */
5769 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5770 + pool->size + 8 /* alignment slop */ < 4096)
5771 {
5772 insn = gen_main_base_31_small (base_reg, pool->label);
5773 insn = emit_insn_after (insn, pool->pool_insn);
5774 INSN_ADDRESSES_NEW (insn, -1);
5775 remove_insn (pool->pool_insn);
5776
5777 insn = emit_label_after (pool->label, insn);
5778 INSN_ADDRESSES_NEW (insn, -1);
5779
5780 insn = get_last_insn ();
5781 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5782 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5783
5784 s390_dump_pool (pool, 1);
5785 }
5786
5787 /* Otherwise, we emit an inline literal pool and use BASR to branch
5788 over it, setting up the pool register at the same time. */
5789 else
5790 {
5791 rtx pool_end = gen_label_rtx ();
5792
5793 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5794 insn = emit_insn_after (insn, pool->pool_insn);
5795 INSN_ADDRESSES_NEW (insn, -1);
5796 remove_insn (pool->pool_insn);
5797
5798 insn = emit_label_after (pool->label, insn);
5799 INSN_ADDRESSES_NEW (insn, -1);
5800
5801 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5802 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5803
5804 insn = emit_label_after (pool_end, pool->pool_insn);
5805 INSN_ADDRESSES_NEW (insn, -1);
5806
5807 s390_dump_pool (pool, 1);
5808 }
5809
5810
5811 /* Replace all literal pool references. */
5812
5813 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5814 {
5815 if (INSN_P (insn))
5816 replace_ltrel_base (&PATTERN (insn));
5817
5818 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5819 {
5820 rtx addr, pool_ref = NULL_RTX;
5821 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5822 if (pool_ref)
5823 {
5824 if (s390_execute_label (insn))
5825 addr = s390_find_execute (pool, insn);
5826 else
5827 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5828 get_pool_mode (pool_ref));
5829
5830 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5831 INSN_CODE (insn) = -1;
5832 }
5833 }
5834 }
5835
5836
5837 /* Free the pool. */
5838 s390_free_pool (pool);
5839 }
5840
5841 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5842 We have decided we cannot use this pool, so revert all changes
5843 to the current function that were done by s390_mainpool_start. */
5844 static void
5845 s390_mainpool_cancel (struct constant_pool *pool)
5846 {
5847 /* We didn't actually change the instruction stream, so simply
5848 free the pool memory. */
5849 s390_free_pool (pool);
5850 }
5851
5852
5853 /* Chunkify the literal pool. */
5854
5855 #define S390_POOL_CHUNK_MIN 0xc00
5856 #define S390_POOL_CHUNK_MAX 0xe00
5857
5858 static struct constant_pool *
5859 s390_chunkify_start (void)
5860 {
5861 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5862 int extra_size = 0;
5863 bitmap far_labels;
5864 rtx pending_ltrel = NULL_RTX;
5865 rtx insn;
5866
5867 rtx (*gen_reload_base) (rtx, rtx) =
5868 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5869
5870
5871 /* We need correct insn addresses. */
5872
5873 shorten_branches (get_insns ());
5874
5875 /* Scan all insns and move literals to pool chunks. */
5876
5877 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5878 {
5879 /* Check for pending LTREL_BASE. */
5880 if (INSN_P (insn))
5881 {
5882 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5883 if (ltrel_base)
5884 {
5885 gcc_assert (ltrel_base == pending_ltrel);
5886 pending_ltrel = NULL_RTX;
5887 }
5888 }
5889
5890 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5891 {
5892 if (!curr_pool)
5893 curr_pool = s390_start_pool (&pool_list, insn);
5894
5895 s390_add_execute (curr_pool, insn);
5896 s390_add_pool_insn (curr_pool, insn);
5897 }
5898 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5899 {
5900 rtx pool_ref = NULL_RTX;
5901 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5902 if (pool_ref)
5903 {
5904 rtx constant = get_pool_constant (pool_ref);
5905 enum machine_mode mode = get_pool_mode (pool_ref);
5906
5907 if (!curr_pool)
5908 curr_pool = s390_start_pool (&pool_list, insn);
5909
5910 s390_add_constant (curr_pool, constant, mode);
5911 s390_add_pool_insn (curr_pool, insn);
5912
5913 /* Don't split the pool chunk between a LTREL_OFFSET load
5914 and the corresponding LTREL_BASE. */
5915 if (GET_CODE (constant) == CONST
5916 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5917 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5918 {
5919 gcc_assert (!pending_ltrel);
5920 pending_ltrel = pool_ref;
5921 }
5922 }
5923 }
5924
5925 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5926 {
5927 if (curr_pool)
5928 s390_add_pool_insn (curr_pool, insn);
5929 /* An LTREL_BASE must follow within the same basic block. */
5930 gcc_assert (!pending_ltrel);
5931 }
5932
5933 if (!curr_pool
5934 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5935 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5936 continue;
5937
5938 if (TARGET_CPU_ZARCH)
5939 {
5940 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5941 continue;
5942
5943 s390_end_pool (curr_pool, NULL_RTX);
5944 curr_pool = NULL;
5945 }
5946 else
5947 {
5948 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5949 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5950 + extra_size;
5951
5952 /* We will later have to insert base register reload insns.
5953 Those will have an effect on code size, which we need to
5954 consider here. This calculation makes rather pessimistic
5955 worst-case assumptions. */
5956 if (GET_CODE (insn) == CODE_LABEL)
5957 extra_size += 6;
5958
5959 if (chunk_size < S390_POOL_CHUNK_MIN
5960 && curr_pool->size < S390_POOL_CHUNK_MIN)
5961 continue;
5962
5963 /* Pool chunks can only be inserted after BARRIERs ... */
5964 if (GET_CODE (insn) == BARRIER)
5965 {
5966 s390_end_pool (curr_pool, insn);
5967 curr_pool = NULL;
5968 extra_size = 0;
5969 }
5970
5971 /* ... so if we don't find one in time, create one. */
5972 else if ((chunk_size > S390_POOL_CHUNK_MAX
5973 || curr_pool->size > S390_POOL_CHUNK_MAX))
5974 {
5975 rtx label, jump, barrier;
5976
5977 /* We can insert the barrier only after a 'real' insn. */
5978 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5979 continue;
5980 if (get_attr_length (insn) == 0)
5981 continue;
5982
5983 /* Don't separate LTREL_BASE from the corresponding
5984 LTREL_OFFSET load. */
5985 if (pending_ltrel)
5986 continue;
5987
5988 label = gen_label_rtx ();
5989 jump = emit_jump_insn_after (gen_jump (label), insn);
5990 barrier = emit_barrier_after (jump);
5991 insn = emit_label_after (label, barrier);
5992 JUMP_LABEL (jump) = label;
5993 LABEL_NUSES (label) = 1;
5994
5995 INSN_ADDRESSES_NEW (jump, -1);
5996 INSN_ADDRESSES_NEW (barrier, -1);
5997 INSN_ADDRESSES_NEW (insn, -1);
5998
5999 s390_end_pool (curr_pool, barrier);
6000 curr_pool = NULL;
6001 extra_size = 0;
6002 }
6003 }
6004 }
6005
6006 if (curr_pool)
6007 s390_end_pool (curr_pool, NULL_RTX);
6008 gcc_assert (!pending_ltrel);
6009
6010 /* Find all labels that are branched into
6011 from an insn belonging to a different chunk. */
6012
6013 far_labels = BITMAP_ALLOC (NULL);
6014
6015 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6016 {
6017 /* Labels marked with LABEL_PRESERVE_P can be target
6018 of non-local jumps, so we have to mark them.
6019 The same holds for named labels.
6020
6021 Don't do that, however, if it is the label before
6022 a jump table. */
6023
6024 if (GET_CODE (insn) == CODE_LABEL
6025 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6026 {
6027 rtx vec_insn = next_real_insn (insn);
6028 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6029 PATTERN (vec_insn) : NULL_RTX;
6030 if (!vec_pat
6031 || !(GET_CODE (vec_pat) == ADDR_VEC
6032 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6033 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6034 }
6035
6036 /* If we have a direct jump (conditional or unconditional)
6037 or a casesi jump, check all potential targets. */
6038 else if (GET_CODE (insn) == JUMP_INSN)
6039 {
6040 rtx pat = PATTERN (insn);
6041 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6042 pat = XVECEXP (pat, 0, 0);
6043
6044 if (GET_CODE (pat) == SET)
6045 {
6046 rtx label = JUMP_LABEL (insn);
6047 if (label)
6048 {
6049 if (s390_find_pool (pool_list, label)
6050 != s390_find_pool (pool_list, insn))
6051 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6052 }
6053 }
6054 else if (GET_CODE (pat) == PARALLEL
6055 && XVECLEN (pat, 0) == 2
6056 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6057 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6058 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6059 {
6060 /* Find the jump table used by this casesi jump. */
6061 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6062 rtx vec_insn = next_real_insn (vec_label);
6063 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6064 PATTERN (vec_insn) : NULL_RTX;
6065 if (vec_pat
6066 && (GET_CODE (vec_pat) == ADDR_VEC
6067 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6068 {
6069 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6070
6071 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6072 {
6073 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6074
6075 if (s390_find_pool (pool_list, label)
6076 != s390_find_pool (pool_list, insn))
6077 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6078 }
6079 }
6080 }
6081 }
6082 }
6083
6084 /* Insert base register reload insns before every pool. */
6085
6086 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6087 {
6088 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6089 curr_pool->label);
6090 rtx insn = curr_pool->first_insn;
6091 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6092 }
6093
6094 /* Insert base register reload insns at every far label. */
6095
6096 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6097 if (GET_CODE (insn) == CODE_LABEL
6098 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6099 {
6100 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6101 if (pool)
6102 {
6103 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6104 pool->label);
6105 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6106 }
6107 }
6108
6109
6110 BITMAP_FREE (far_labels);
6111
6112
6113 /* Recompute insn addresses. */
6114
6115 init_insn_lengths ();
6116 shorten_branches (get_insns ());
6117
6118 return pool_list;
6119 }
6120
6121 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6122 After we have decided to use this list, finish implementing
6123 all changes to the current function as required. */
6124
6125 static void
6126 s390_chunkify_finish (struct constant_pool *pool_list)
6127 {
6128 struct constant_pool *curr_pool = NULL;
6129 rtx insn;
6130
6131
6132 /* Replace all literal pool references. */
6133
6134 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6135 {
6136 if (INSN_P (insn))
6137 replace_ltrel_base (&PATTERN (insn));
6138
6139 curr_pool = s390_find_pool (pool_list, insn);
6140 if (!curr_pool)
6141 continue;
6142
6143 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6144 {
6145 rtx addr, pool_ref = NULL_RTX;
6146 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6147 if (pool_ref)
6148 {
6149 if (s390_execute_label (insn))
6150 addr = s390_find_execute (curr_pool, insn);
6151 else
6152 addr = s390_find_constant (curr_pool,
6153 get_pool_constant (pool_ref),
6154 get_pool_mode (pool_ref));
6155
6156 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6157 INSN_CODE (insn) = -1;
6158 }
6159 }
6160 }
6161
6162 /* Dump out all literal pools. */
6163
6164 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6165 s390_dump_pool (curr_pool, 0);
6166
6167 /* Free pool list. */
6168
6169 while (pool_list)
6170 {
6171 struct constant_pool *next = pool_list->next;
6172 s390_free_pool (pool_list);
6173 pool_list = next;
6174 }
6175 }
6176
6177 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6178 We have decided we cannot use this list, so revert all changes
6179 to the current function that were done by s390_chunkify_start. */
6180
6181 static void
6182 s390_chunkify_cancel (struct constant_pool *pool_list)
6183 {
6184 struct constant_pool *curr_pool = NULL;
6185 rtx insn;
6186
6187 /* Remove all pool placeholder insns. */
6188
6189 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6190 {
6191 /* Did we insert an extra barrier? Remove it. */
6192 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6193 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6194 rtx label = NEXT_INSN (curr_pool->pool_insn);
6195
6196 if (jump && GET_CODE (jump) == JUMP_INSN
6197 && barrier && GET_CODE (barrier) == BARRIER
6198 && label && GET_CODE (label) == CODE_LABEL
6199 && GET_CODE (PATTERN (jump)) == SET
6200 && SET_DEST (PATTERN (jump)) == pc_rtx
6201 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6202 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6203 {
6204 remove_insn (jump);
6205 remove_insn (barrier);
6206 remove_insn (label);
6207 }
6208
6209 remove_insn (curr_pool->pool_insn);
6210 }
6211
6212 /* Remove all base register reload insns. */
6213
6214 for (insn = get_insns (); insn; )
6215 {
6216 rtx next_insn = NEXT_INSN (insn);
6217
6218 if (GET_CODE (insn) == INSN
6219 && GET_CODE (PATTERN (insn)) == SET
6220 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6221 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6222 remove_insn (insn);
6223
6224 insn = next_insn;
6225 }
6226
6227 /* Free pool list. */
6228
6229 while (pool_list)
6230 {
6231 struct constant_pool *next = pool_list->next;
6232 s390_free_pool (pool_list);
6233 pool_list = next;
6234 }
6235 }
6236
6237
6238 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6239
6240 void
6241 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6242 {
6243 REAL_VALUE_TYPE r;
6244
6245 switch (GET_MODE_CLASS (mode))
6246 {
6247 case MODE_FLOAT:
6248 case MODE_DECIMAL_FLOAT:
6249 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6250
6251 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6252 assemble_real (r, mode, align);
6253 break;
6254
6255 case MODE_INT:
6256 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6257 break;
6258
6259 default:
6260 gcc_unreachable ();
6261 }
6262 }
6263
6264
6265 /* Return an RTL expression representing the value of the return address
6266 for the frame COUNT steps up from the current frame. FRAME is the
6267 frame pointer of that frame. */
6268
6269 rtx
6270 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6271 {
6272 int offset;
6273 rtx addr;
6274
6275 /* Without backchain, we fail for all but the current frame. */
6276
6277 if (!TARGET_BACKCHAIN && count > 0)
6278 return NULL_RTX;
6279
6280 /* For the current frame, we need to make sure the initial
6281 value of RETURN_REGNUM is actually saved. */
6282
6283 if (count == 0)
6284 {
6285 /* On non-z architectures branch splitting could overwrite r14. */
6286 if (TARGET_CPU_ZARCH)
6287 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6288 else
6289 {
6290 cfun_frame_layout.save_return_addr_p = true;
6291 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6292 }
6293 }
6294
6295 if (TARGET_PACKED_STACK)
6296 offset = -2 * UNITS_PER_WORD;
6297 else
6298 offset = RETURN_REGNUM * UNITS_PER_WORD;
6299
6300 addr = plus_constant (frame, offset);
6301 addr = memory_address (Pmode, addr);
6302 return gen_rtx_MEM (Pmode, addr);
6303 }
6304
6305 /* Return an RTL expression representing the back chain stored in
6306 the current stack frame. */
6307
6308 rtx
6309 s390_back_chain_rtx (void)
6310 {
6311 rtx chain;
6312
6313 gcc_assert (TARGET_BACKCHAIN);
6314
6315 if (TARGET_PACKED_STACK)
6316 chain = plus_constant (stack_pointer_rtx,
6317 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6318 else
6319 chain = stack_pointer_rtx;
6320
6321 chain = gen_rtx_MEM (Pmode, chain);
6322 return chain;
6323 }
6324
6325 /* Find first call clobbered register unused in a function.
6326 This could be used as base register in a leaf function
6327 or for holding the return address before epilogue. */
6328
6329 static int
6330 find_unused_clobbered_reg (void)
6331 {
6332 int i;
6333 for (i = 0; i < 6; i++)
6334 if (!regs_ever_live[i])
6335 return i;
6336 return 0;
6337 }
6338
6339
6340 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6341 clobbered hard regs in SETREG. */
6342
6343 static void
6344 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6345 {
6346 int *regs_ever_clobbered = (int *)data;
6347 unsigned int i, regno;
6348 enum machine_mode mode = GET_MODE (setreg);
6349
6350 if (GET_CODE (setreg) == SUBREG)
6351 {
6352 rtx inner = SUBREG_REG (setreg);
6353 if (!GENERAL_REG_P (inner))
6354 return;
6355 regno = subreg_regno (setreg);
6356 }
6357 else if (GENERAL_REG_P (setreg))
6358 regno = REGNO (setreg);
6359 else
6360 return;
6361
6362 for (i = regno;
6363 i < regno + HARD_REGNO_NREGS (regno, mode);
6364 i++)
6365 regs_ever_clobbered[i] = 1;
6366 }
6367
6368 /* Walks through all basic blocks of the current function looking
6369 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6370 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6371 each of those regs. */
6372
6373 static void
6374 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6375 {
6376 basic_block cur_bb;
6377 rtx cur_insn;
6378 unsigned int i;
6379
6380 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6381
6382 /* For non-leaf functions we have to consider all call clobbered regs to be
6383 clobbered. */
6384 if (!current_function_is_leaf)
6385 {
6386 for (i = 0; i < 16; i++)
6387 regs_ever_clobbered[i] = call_really_used_regs[i];
6388 }
6389
6390 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6391 this work is done by liveness analysis (mark_regs_live_at_end).
6392 Special care is needed for functions containing landing pads. Landing pads
6393 may use the eh registers, but the code which sets these registers is not
6394 contained in that function. Hence s390_regs_ever_clobbered is not able to
6395 deal with this automatically. */
6396 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6397 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6398 if (current_function_calls_eh_return
6399 || (cfun->machine->has_landing_pad_p
6400 && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6401 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6402
6403 /* For nonlocal gotos all call-saved registers have to be saved.
6404 This flag is also set for the unwinding code in libgcc.
6405 See expand_builtin_unwind_init. For regs_ever_live this is done by
6406 reload. */
6407 if (current_function_has_nonlocal_label)
6408 for (i = 0; i < 16; i++)
6409 if (!call_really_used_regs[i])
6410 regs_ever_clobbered[i] = 1;
6411
6412 FOR_EACH_BB (cur_bb)
6413 {
6414 FOR_BB_INSNS (cur_bb, cur_insn)
6415 {
6416 if (INSN_P (cur_insn))
6417 note_stores (PATTERN (cur_insn),
6418 s390_reg_clobbered_rtx,
6419 regs_ever_clobbered);
6420 }
6421 }
6422 }
6423
6424 /* Determine the frame area which actually has to be accessed
6425 in the function epilogue. The values are stored at the
6426 given pointers AREA_BOTTOM (address of the lowest used stack
6427 address) and AREA_TOP (address of the first item which does
6428 not belong to the stack frame). */
6429
6430 static void
6431 s390_frame_area (int *area_bottom, int *area_top)
6432 {
6433 int b, t;
6434 int i;
6435
6436 b = INT_MAX;
6437 t = INT_MIN;
6438
6439 if (cfun_frame_layout.first_restore_gpr != -1)
6440 {
6441 b = (cfun_frame_layout.gprs_offset
6442 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6443 t = b + (cfun_frame_layout.last_restore_gpr
6444 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6445 }
6446
6447 if (TARGET_64BIT && cfun_save_high_fprs_p)
6448 {
6449 b = MIN (b, cfun_frame_layout.f8_offset);
6450 t = MAX (t, (cfun_frame_layout.f8_offset
6451 + cfun_frame_layout.high_fprs * 8));
6452 }
6453
6454 if (!TARGET_64BIT)
6455 for (i = 2; i < 4; i++)
6456 if (cfun_fpr_bit_p (i))
6457 {
6458 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6459 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6460 }
6461
6462 *area_bottom = b;
6463 *area_top = t;
6464 }
6465
6466 /* Fill cfun->machine with info about register usage of current function.
6467 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6468
6469 static void
6470 s390_register_info (int clobbered_regs[])
6471 {
6472 int i, j;
6473
6474 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6475 cfun_frame_layout.fpr_bitmap = 0;
6476 cfun_frame_layout.high_fprs = 0;
6477 if (TARGET_64BIT)
6478 for (i = 24; i < 32; i++)
6479 if (regs_ever_live[i] && !global_regs[i])
6480 {
6481 cfun_set_fpr_bit (i - 16);
6482 cfun_frame_layout.high_fprs++;
6483 }
6484
6485 /* Find first and last gpr to be saved. We trust regs_ever_live
6486 data, except that we don't save and restore global registers.
6487
6488 Also, all registers with special meaning to the compiler need
6489 to be handled extra. */
6490
6491 s390_regs_ever_clobbered (clobbered_regs);
6492
6493 for (i = 0; i < 16; i++)
6494 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6495
6496 if (frame_pointer_needed)
6497 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6498
6499 if (flag_pic)
6500 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6501 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6502
6503 clobbered_regs[BASE_REGNUM]
6504 |= (cfun->machine->base_reg
6505 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6506
6507 clobbered_regs[RETURN_REGNUM]
6508 |= (!current_function_is_leaf
6509 || TARGET_TPF_PROFILING
6510 || cfun->machine->split_branches_pending_p
6511 || cfun_frame_layout.save_return_addr_p
6512 || current_function_calls_eh_return
6513 || current_function_stdarg);
6514
6515 clobbered_regs[STACK_POINTER_REGNUM]
6516 |= (!current_function_is_leaf
6517 || TARGET_TPF_PROFILING
6518 || cfun_save_high_fprs_p
6519 || get_frame_size () > 0
6520 || current_function_calls_alloca
6521 || current_function_stdarg);
6522
6523 for (i = 6; i < 16; i++)
6524 if (regs_ever_live[i] || clobbered_regs[i])
6525 break;
6526 for (j = 15; j > i; j--)
6527 if (regs_ever_live[j] || clobbered_regs[j])
6528 break;
6529
6530 if (i == 16)
6531 {
6532 /* Nothing to save/restore. */
6533 cfun_frame_layout.first_save_gpr_slot = -1;
6534 cfun_frame_layout.last_save_gpr_slot = -1;
6535 cfun_frame_layout.first_save_gpr = -1;
6536 cfun_frame_layout.first_restore_gpr = -1;
6537 cfun_frame_layout.last_save_gpr = -1;
6538 cfun_frame_layout.last_restore_gpr = -1;
6539 }
6540 else
6541 {
6542 /* Save slots for gprs from i to j. */
6543 cfun_frame_layout.first_save_gpr_slot = i;
6544 cfun_frame_layout.last_save_gpr_slot = j;
6545
6546 for (i = cfun_frame_layout.first_save_gpr_slot;
6547 i < cfun_frame_layout.last_save_gpr_slot + 1;
6548 i++)
6549 if (clobbered_regs[i])
6550 break;
6551
6552 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6553 if (clobbered_regs[j])
6554 break;
6555
6556 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6557 {
6558 /* Nothing to save/restore. */
6559 cfun_frame_layout.first_save_gpr = -1;
6560 cfun_frame_layout.first_restore_gpr = -1;
6561 cfun_frame_layout.last_save_gpr = -1;
6562 cfun_frame_layout.last_restore_gpr = -1;
6563 }
6564 else
6565 {
6566 /* Save / Restore from gpr i to j. */
6567 cfun_frame_layout.first_save_gpr = i;
6568 cfun_frame_layout.first_restore_gpr = i;
6569 cfun_frame_layout.last_save_gpr = j;
6570 cfun_frame_layout.last_restore_gpr = j;
6571 }
6572 }
6573
6574 if (current_function_stdarg)
6575 {
6576 /* Varargs functions need to save gprs 2 to 6. */
6577 if (cfun->va_list_gpr_size
6578 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6579 {
6580 int min_gpr = current_function_args_info.gprs;
6581 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6582 if (max_gpr > GP_ARG_NUM_REG)
6583 max_gpr = GP_ARG_NUM_REG;
6584
6585 if (cfun_frame_layout.first_save_gpr == -1
6586 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6587 {
6588 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6589 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6590 }
6591
6592 if (cfun_frame_layout.last_save_gpr == -1
6593 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6594 {
6595 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6596 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6597 }
6598 }
6599
6600 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6601 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6602 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6603 {
6604 int min_fpr = current_function_args_info.fprs;
6605 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6606 if (max_fpr > FP_ARG_NUM_REG)
6607 max_fpr = FP_ARG_NUM_REG;
6608
6609 /* ??? This is currently required to ensure proper location
6610 of the fpr save slots within the va_list save area. */
6611 if (TARGET_PACKED_STACK)
6612 min_fpr = 0;
6613
6614 for (i = min_fpr; i < max_fpr; i++)
6615 cfun_set_fpr_bit (i);
6616 }
6617 }
6618
6619 if (!TARGET_64BIT)
6620 for (i = 2; i < 4; i++)
6621 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6622 cfun_set_fpr_bit (i);
6623 }
6624
6625 /* Fill cfun->machine with info about frame of current function. */
6626
6627 static void
6628 s390_frame_info (void)
6629 {
6630 int i;
6631
6632 cfun_frame_layout.frame_size = get_frame_size ();
6633 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6634 fatal_error ("total size of local variables exceeds architecture limit");
6635
6636 if (!TARGET_PACKED_STACK)
6637 {
6638 cfun_frame_layout.backchain_offset = 0;
6639 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6640 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6641 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6642 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6643 * UNITS_PER_WORD);
6644 }
6645 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6646 {
6647 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6648 - UNITS_PER_WORD);
6649 cfun_frame_layout.gprs_offset
6650 = (cfun_frame_layout.backchain_offset
6651 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6652 * UNITS_PER_WORD);
6653
6654 if (TARGET_64BIT)
6655 {
6656 cfun_frame_layout.f4_offset
6657 = (cfun_frame_layout.gprs_offset
6658 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6659
6660 cfun_frame_layout.f0_offset
6661 = (cfun_frame_layout.f4_offset
6662 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6663 }
6664 else
6665 {
6666 /* On 31 bit we have to care about alignment of the
6667 floating point regs to provide fastest access. */
6668 cfun_frame_layout.f0_offset
6669 = ((cfun_frame_layout.gprs_offset
6670 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6671 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6672
6673 cfun_frame_layout.f4_offset
6674 = (cfun_frame_layout.f0_offset
6675 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6676 }
6677 }
6678 else /* no backchain */
6679 {
6680 cfun_frame_layout.f4_offset
6681 = (STACK_POINTER_OFFSET
6682 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6683
6684 cfun_frame_layout.f0_offset
6685 = (cfun_frame_layout.f4_offset
6686 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6687
6688 cfun_frame_layout.gprs_offset
6689 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6690 }
6691
6692 if (current_function_is_leaf
6693 && !TARGET_TPF_PROFILING
6694 && cfun_frame_layout.frame_size == 0
6695 && !cfun_save_high_fprs_p
6696 && !current_function_calls_alloca
6697 && !current_function_stdarg)
6698 return;
6699
6700 if (!TARGET_PACKED_STACK)
6701 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6702 + current_function_outgoing_args_size
6703 + cfun_frame_layout.high_fprs * 8);
6704 else
6705 {
6706 if (TARGET_BACKCHAIN)
6707 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6708
6709 /* No alignment trouble here because f8-f15 are only saved under
6710 64 bit. */
6711 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6712 cfun_frame_layout.f4_offset),
6713 cfun_frame_layout.gprs_offset)
6714 - cfun_frame_layout.high_fprs * 8);
6715
6716 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6717
6718 for (i = 0; i < 8; i++)
6719 if (cfun_fpr_bit_p (i))
6720 cfun_frame_layout.frame_size += 8;
6721
6722 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6723
6724 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6725 the frame size to sustain 8 byte alignment of stack frames. */
6726 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6727 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6728 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6729
6730 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6731 }
6732 }
6733
6734 /* Generate frame layout. Fills in register and frame data for the current
6735 function in cfun->machine. This routine can be called multiple times;
6736 it will re-do the complete frame layout every time. */
6737
6738 static void
6739 s390_init_frame_layout (void)
6740 {
6741 HOST_WIDE_INT frame_size;
6742 int base_used;
6743 int clobbered_regs[16];
6744
6745 /* On S/390 machines, we may need to perform branch splitting, which
6746 will require both base and return address register. We have no
6747 choice but to assume we're going to need them until right at the
6748 end of the machine dependent reorg phase. */
6749 if (!TARGET_CPU_ZARCH)
6750 cfun->machine->split_branches_pending_p = true;
6751
6752 do
6753 {
6754 frame_size = cfun_frame_layout.frame_size;
6755
6756 /* Try to predict whether we'll need the base register. */
6757 base_used = cfun->machine->split_branches_pending_p
6758 || current_function_uses_const_pool
6759 || (!DISP_IN_RANGE (frame_size)
6760 && !CONST_OK_FOR_K (frame_size));
6761
6762 /* Decide which register to use as literal pool base. In small
6763 leaf functions, try to use an unused call-clobbered register
6764 as base register to avoid save/restore overhead. */
6765 if (!base_used)
6766 cfun->machine->base_reg = NULL_RTX;
6767 else if (current_function_is_leaf && !regs_ever_live[5])
6768 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6769 else
6770 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6771
6772 s390_register_info (clobbered_regs);
6773 s390_frame_info ();
6774 }
6775 while (frame_size != cfun_frame_layout.frame_size);
6776 }
6777
6778 /* Update frame layout. Recompute actual register save data based on
6779 current info and update regs_ever_live for the special registers.
6780 May be called multiple times, but may never cause *more* registers
6781 to be saved than s390_init_frame_layout allocated room for. */
6782
6783 static void
6784 s390_update_frame_layout (void)
6785 {
6786 int clobbered_regs[16];
6787
6788 s390_register_info (clobbered_regs);
6789
6790 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6791 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6792 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6793
6794 if (cfun->machine->base_reg)
6795 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6796 }
6797
6798 /* Return true if it is legal to put a value with MODE into REGNO. */
6799
6800 bool
6801 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
6802 {
6803 switch (REGNO_REG_CLASS (regno))
6804 {
6805 case FP_REGS:
6806 if (REGNO_PAIR_OK (regno, mode))
6807 {
6808 if (mode == SImode || mode == DImode)
6809 return true;
6810
6811 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
6812 return true;
6813 }
6814 break;
6815 case ADDR_REGS:
6816 if (FRAME_REGNO_P (regno) && mode == Pmode)
6817 return true;
6818
6819 /* fallthrough */
6820 case GENERAL_REGS:
6821 if (REGNO_PAIR_OK (regno, mode))
6822 {
6823 if (TARGET_64BIT
6824 || (mode != TFmode && mode != TCmode && mode != TDmode))
6825 return true;
6826 }
6827 break;
6828 case CC_REGS:
6829 if (GET_MODE_CLASS (mode) == MODE_CC)
6830 return true;
6831 break;
6832 case ACCESS_REGS:
6833 if (REGNO_PAIR_OK (regno, mode))
6834 {
6835 if (mode == SImode || mode == Pmode)
6836 return true;
6837 }
6838 break;
6839 default:
6840 return false;
6841 }
6842
6843 return false;
6844 }
6845
6846 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6847
6848 bool
6849 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6850 {
6851 /* Once we've decided upon a register to use as base register, it must
6852 no longer be used for any other purpose. */
6853 if (cfun->machine->base_reg)
6854 if (REGNO (cfun->machine->base_reg) == old_reg
6855 || REGNO (cfun->machine->base_reg) == new_reg)
6856 return false;
6857
6858 return true;
6859 }
6860
6861 /* Maximum number of registers to represent a value of mode MODE
6862 in a register of class CLASS. */
6863
6864 bool
6865 s390_class_max_nregs (enum reg_class class, enum machine_mode mode)
6866 {
6867 switch (class)
6868 {
6869 case FP_REGS:
6870 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6871 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
6872 else
6873 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
6874 case ACCESS_REGS:
6875 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
6876 default:
6877 break;
6878 }
6879 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6880 }
6881
6882 /* Return true if register FROM can be eliminated via register TO. */
6883
6884 bool
6885 s390_can_eliminate (int from, int to)
6886 {
6887 /* On zSeries machines, we have not marked the base register as fixed.
6888 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6889 If a function requires the base register, we say here that this
6890 elimination cannot be performed. This will cause reload to free
6891 up the base register (as if it were fixed). On the other hand,
6892 if the current function does *not* require the base register, we
6893 say here the elimination succeeds, which in turn allows reload
6894 to allocate the base register for any other purpose. */
6895 if (from == BASE_REGNUM && to == BASE_REGNUM)
6896 {
6897 if (TARGET_CPU_ZARCH)
6898 {
6899 s390_init_frame_layout ();
6900 return cfun->machine->base_reg == NULL_RTX;
6901 }
6902
6903 return false;
6904 }
6905
6906 /* Everything else must point into the stack frame. */
6907 gcc_assert (to == STACK_POINTER_REGNUM
6908 || to == HARD_FRAME_POINTER_REGNUM);
6909
6910 gcc_assert (from == FRAME_POINTER_REGNUM
6911 || from == ARG_POINTER_REGNUM
6912 || from == RETURN_ADDRESS_POINTER_REGNUM);
6913
6914 /* Make sure we actually saved the return address. */
6915 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6916 if (!current_function_calls_eh_return
6917 && !current_function_stdarg
6918 && !cfun_frame_layout.save_return_addr_p)
6919 return false;
6920
6921 return true;
6922 }
6923
6924 /* Return offset between register FROM and TO initially after prolog. */
6925
6926 HOST_WIDE_INT
6927 s390_initial_elimination_offset (int from, int to)
6928 {
6929 HOST_WIDE_INT offset;
6930 int index;
6931
6932 /* ??? Why are we called for non-eliminable pairs? */
6933 if (!s390_can_eliminate (from, to))
6934 return 0;
6935
6936 switch (from)
6937 {
6938 case FRAME_POINTER_REGNUM:
6939 offset = (get_frame_size()
6940 + STACK_POINTER_OFFSET
6941 + current_function_outgoing_args_size);
6942 break;
6943
6944 case ARG_POINTER_REGNUM:
6945 s390_init_frame_layout ();
6946 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6947 break;
6948
6949 case RETURN_ADDRESS_POINTER_REGNUM:
6950 s390_init_frame_layout ();
6951 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6952 gcc_assert (index >= 0);
6953 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6954 offset += index * UNITS_PER_WORD;
6955 break;
6956
6957 case BASE_REGNUM:
6958 offset = 0;
6959 break;
6960
6961 default:
6962 gcc_unreachable ();
6963 }
6964
6965 return offset;
6966 }
6967
6968 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6969 to register BASE. Return generated insn. */
6970
6971 static rtx
6972 save_fpr (rtx base, int offset, int regnum)
6973 {
6974 rtx addr;
6975 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6976
6977 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6978 set_mem_alias_set (addr, get_varargs_alias_set ());
6979 else
6980 set_mem_alias_set (addr, get_frame_alias_set ());
6981
6982 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6983 }
6984
6985 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6986 to register BASE. Return generated insn. */
6987
6988 static rtx
6989 restore_fpr (rtx base, int offset, int regnum)
6990 {
6991 rtx addr;
6992 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6993 set_mem_alias_set (addr, get_frame_alias_set ());
6994
6995 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6996 }
6997
6998 /* Generate insn to save registers FIRST to LAST into
6999 the register save area located at offset OFFSET
7000 relative to register BASE. */
7001
7002 static rtx
7003 save_gprs (rtx base, int offset, int first, int last)
7004 {
7005 rtx addr, insn, note;
7006 int i;
7007
7008 addr = plus_constant (base, offset);
7009 addr = gen_rtx_MEM (Pmode, addr);
7010
7011 set_mem_alias_set (addr, get_frame_alias_set ());
7012
7013 /* Special-case single register. */
7014 if (first == last)
7015 {
7016 if (TARGET_64BIT)
7017 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7018 else
7019 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7020
7021 RTX_FRAME_RELATED_P (insn) = 1;
7022 return insn;
7023 }
7024
7025
7026 insn = gen_store_multiple (addr,
7027 gen_rtx_REG (Pmode, first),
7028 GEN_INT (last - first + 1));
7029
7030 if (first <= 6 && current_function_stdarg)
7031 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7032 {
7033 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7034
7035 if (first + i <= 6)
7036 set_mem_alias_set (mem, get_varargs_alias_set ());
7037 }
7038
7039 /* We need to set the FRAME_RELATED flag on all SETs
7040 inside the store-multiple pattern.
7041
7042 However, we must not emit DWARF records for registers 2..5
7043 if they are stored for use by variable arguments ...
7044
7045 ??? Unfortunately, it is not enough to simply not the
7046 FRAME_RELATED flags for those SETs, because the first SET
7047 of the PARALLEL is always treated as if it had the flag
7048 set, even if it does not. Therefore we emit a new pattern
7049 without those registers as REG_FRAME_RELATED_EXPR note. */
7050
7051 if (first >= 6)
7052 {
7053 rtx pat = PATTERN (insn);
7054
7055 for (i = 0; i < XVECLEN (pat, 0); i++)
7056 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
7057 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7058
7059 RTX_FRAME_RELATED_P (insn) = 1;
7060 }
7061 else if (last >= 6)
7062 {
7063 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
7064 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7065 gen_rtx_REG (Pmode, 6),
7066 GEN_INT (last - 6 + 1));
7067 note = PATTERN (note);
7068
7069 REG_NOTES (insn) =
7070 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7071 note, REG_NOTES (insn));
7072
7073 for (i = 0; i < XVECLEN (note, 0); i++)
7074 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
7075 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7076
7077 RTX_FRAME_RELATED_P (insn) = 1;
7078 }
7079
7080 return insn;
7081 }
7082
7083 /* Generate insn to restore registers FIRST to LAST from
7084 the register save area located at offset OFFSET
7085 relative to register BASE. */
7086
7087 static rtx
7088 restore_gprs (rtx base, int offset, int first, int last)
7089 {
7090 rtx addr, insn;
7091
7092 addr = plus_constant (base, offset);
7093 addr = gen_rtx_MEM (Pmode, addr);
7094 set_mem_alias_set (addr, get_frame_alias_set ());
7095
7096 /* Special-case single register. */
7097 if (first == last)
7098 {
7099 if (TARGET_64BIT)
7100 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7101 else
7102 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7103
7104 return insn;
7105 }
7106
7107 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7108 addr,
7109 GEN_INT (last - first + 1));
7110 return insn;
7111 }
7112
7113 /* Return insn sequence to load the GOT register. */
7114
7115 static GTY(()) rtx got_symbol;
7116 rtx
7117 s390_load_got (void)
7118 {
7119 rtx insns;
7120
7121 if (!got_symbol)
7122 {
7123 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7124 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7125 }
7126
7127 start_sequence ();
7128
7129 if (TARGET_CPU_ZARCH)
7130 {
7131 emit_move_insn (pic_offset_table_rtx, got_symbol);
7132 }
7133 else
7134 {
7135 rtx offset;
7136
7137 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7138 UNSPEC_LTREL_OFFSET);
7139 offset = gen_rtx_CONST (Pmode, offset);
7140 offset = force_const_mem (Pmode, offset);
7141
7142 emit_move_insn (pic_offset_table_rtx, offset);
7143
7144 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7145 UNSPEC_LTREL_BASE);
7146 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7147
7148 emit_move_insn (pic_offset_table_rtx, offset);
7149 }
7150
7151 insns = get_insns ();
7152 end_sequence ();
7153 return insns;
7154 }
7155
7156 /* Expand the prologue into a bunch of separate insns. */
7157
7158 void
7159 s390_emit_prologue (void)
7160 {
7161 rtx insn, addr;
7162 rtx temp_reg;
7163 int i;
7164 int offset;
7165 int next_fpr = 0;
7166
7167 /* Complete frame layout. */
7168
7169 s390_update_frame_layout ();
7170
7171 /* Annotate all constant pool references to let the scheduler know
7172 they implicitly use the base register. */
7173
7174 push_topmost_sequence ();
7175
7176 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7177 if (INSN_P (insn))
7178 annotate_constant_pool_refs (&PATTERN (insn));
7179
7180 pop_topmost_sequence ();
7181
7182 /* Choose best register to use for temp use within prologue.
7183 See below for why TPF must use the register 1. */
7184
7185 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7186 && !current_function_is_leaf
7187 && !TARGET_TPF_PROFILING)
7188 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7189 else
7190 temp_reg = gen_rtx_REG (Pmode, 1);
7191
7192 /* Save call saved gprs. */
7193 if (cfun_frame_layout.first_save_gpr != -1)
7194 {
7195 insn = save_gprs (stack_pointer_rtx,
7196 cfun_frame_layout.gprs_offset +
7197 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7198 - cfun_frame_layout.first_save_gpr_slot),
7199 cfun_frame_layout.first_save_gpr,
7200 cfun_frame_layout.last_save_gpr);
7201 emit_insn (insn);
7202 }
7203
7204 /* Dummy insn to mark literal pool slot. */
7205
7206 if (cfun->machine->base_reg)
7207 emit_insn (gen_main_pool (cfun->machine->base_reg));
7208
7209 offset = cfun_frame_layout.f0_offset;
7210
7211 /* Save f0 and f2. */
7212 for (i = 0; i < 2; i++)
7213 {
7214 if (cfun_fpr_bit_p (i))
7215 {
7216 save_fpr (stack_pointer_rtx, offset, i + 16);
7217 offset += 8;
7218 }
7219 else if (!TARGET_PACKED_STACK)
7220 offset += 8;
7221 }
7222
7223 /* Save f4 and f6. */
7224 offset = cfun_frame_layout.f4_offset;
7225 for (i = 2; i < 4; i++)
7226 {
7227 if (cfun_fpr_bit_p (i))
7228 {
7229 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7230 offset += 8;
7231
7232 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7233 therefore are not frame related. */
7234 if (!call_really_used_regs[i + 16])
7235 RTX_FRAME_RELATED_P (insn) = 1;
7236 }
7237 else if (!TARGET_PACKED_STACK)
7238 offset += 8;
7239 }
7240
7241 if (TARGET_PACKED_STACK
7242 && cfun_save_high_fprs_p
7243 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7244 {
7245 offset = (cfun_frame_layout.f8_offset
7246 + (cfun_frame_layout.high_fprs - 1) * 8);
7247
7248 for (i = 15; i > 7 && offset >= 0; i--)
7249 if (cfun_fpr_bit_p (i))
7250 {
7251 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7252
7253 RTX_FRAME_RELATED_P (insn) = 1;
7254 offset -= 8;
7255 }
7256 if (offset >= cfun_frame_layout.f8_offset)
7257 next_fpr = i + 16;
7258 }
7259
7260 if (!TARGET_PACKED_STACK)
7261 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7262
7263 /* Decrement stack pointer. */
7264
7265 if (cfun_frame_layout.frame_size > 0)
7266 {
7267 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7268
7269 if (s390_stack_size)
7270 {
7271 HOST_WIDE_INT stack_guard;
7272
7273 if (s390_stack_guard)
7274 stack_guard = s390_stack_guard;
7275 else
7276 {
7277 /* If no value for stack guard is provided the smallest power of 2
7278 larger than the current frame size is chosen. */
7279 stack_guard = 1;
7280 while (stack_guard < cfun_frame_layout.frame_size)
7281 stack_guard <<= 1;
7282 }
7283
7284 if (cfun_frame_layout.frame_size >= s390_stack_size)
7285 {
7286 warning (0, "frame size of function %qs is "
7287 HOST_WIDE_INT_PRINT_DEC
7288 " bytes exceeding user provided stack limit of "
7289 HOST_WIDE_INT_PRINT_DEC " bytes. "
7290 "An unconditional trap is added.",
7291 current_function_name(), cfun_frame_layout.frame_size,
7292 s390_stack_size);
7293 emit_insn (gen_trap ());
7294 }
7295 else
7296 {
7297 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7298 & ~(stack_guard - 1));
7299 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7300 GEN_INT (stack_check_mask));
7301 if (TARGET_64BIT)
7302 gen_cmpdi (t, const0_rtx);
7303 else
7304 gen_cmpsi (t, const0_rtx);
7305
7306 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7307 gen_rtx_REG (CCmode,
7308 CC_REGNUM),
7309 const0_rtx),
7310 const0_rtx));
7311 }
7312 }
7313
7314 if (s390_warn_framesize > 0
7315 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7316 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7317 current_function_name (), cfun_frame_layout.frame_size);
7318
7319 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7320 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7321
7322 /* Save incoming stack pointer into temp reg. */
7323 if (TARGET_BACKCHAIN || next_fpr)
7324 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7325
7326 /* Subtract frame size from stack pointer. */
7327
7328 if (DISP_IN_RANGE (INTVAL (frame_off)))
7329 {
7330 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7331 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7332 frame_off));
7333 insn = emit_insn (insn);
7334 }
7335 else
7336 {
7337 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7338 frame_off = force_const_mem (Pmode, frame_off);
7339
7340 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7341 annotate_constant_pool_refs (&PATTERN (insn));
7342 }
7343
7344 RTX_FRAME_RELATED_P (insn) = 1;
7345 REG_NOTES (insn) =
7346 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7347 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7348 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7349 GEN_INT (-cfun_frame_layout.frame_size))),
7350 REG_NOTES (insn));
7351
7352 /* Set backchain. */
7353
7354 if (TARGET_BACKCHAIN)
7355 {
7356 if (cfun_frame_layout.backchain_offset)
7357 addr = gen_rtx_MEM (Pmode,
7358 plus_constant (stack_pointer_rtx,
7359 cfun_frame_layout.backchain_offset));
7360 else
7361 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7362 set_mem_alias_set (addr, get_frame_alias_set ());
7363 insn = emit_insn (gen_move_insn (addr, temp_reg));
7364 }
7365
7366 /* If we support asynchronous exceptions (e.g. for Java),
7367 we need to make sure the backchain pointer is set up
7368 before any possibly trapping memory access. */
7369
7370 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7371 {
7372 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7373 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7374 }
7375 }
7376
7377 /* Save fprs 8 - 15 (64 bit ABI). */
7378
7379 if (cfun_save_high_fprs_p && next_fpr)
7380 {
7381 insn = emit_insn (gen_add2_insn (temp_reg,
7382 GEN_INT (cfun_frame_layout.f8_offset)));
7383
7384 offset = 0;
7385
7386 for (i = 24; i <= next_fpr; i++)
7387 if (cfun_fpr_bit_p (i - 16))
7388 {
7389 rtx addr = plus_constant (stack_pointer_rtx,
7390 cfun_frame_layout.frame_size
7391 + cfun_frame_layout.f8_offset
7392 + offset);
7393
7394 insn = save_fpr (temp_reg, offset, i);
7395 offset += 8;
7396 RTX_FRAME_RELATED_P (insn) = 1;
7397 REG_NOTES (insn) =
7398 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7399 gen_rtx_SET (VOIDmode,
7400 gen_rtx_MEM (DFmode, addr),
7401 gen_rtx_REG (DFmode, i)),
7402 REG_NOTES (insn));
7403 }
7404 }
7405
7406 /* Set frame pointer, if needed. */
7407
7408 if (frame_pointer_needed)
7409 {
7410 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7411 RTX_FRAME_RELATED_P (insn) = 1;
7412 }
7413
7414 /* Set up got pointer, if needed. */
7415
7416 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7417 {
7418 rtx insns = s390_load_got ();
7419
7420 for (insn = insns; insn; insn = NEXT_INSN (insn))
7421 {
7422 annotate_constant_pool_refs (&PATTERN (insn));
7423
7424 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7425 REG_NOTES (insn));
7426 }
7427
7428 emit_insn (insns);
7429 }
7430
7431 if (TARGET_TPF_PROFILING)
7432 {
7433 /* Generate a BAS instruction to serve as a function
7434 entry intercept to facilitate the use of tracing
7435 algorithms located at the branch target. */
7436 emit_insn (gen_prologue_tpf ());
7437
7438 /* Emit a blockage here so that all code
7439 lies between the profiling mechanisms. */
7440 emit_insn (gen_blockage ());
7441 }
7442 }
7443
7444 /* Expand the epilogue into a bunch of separate insns. */
7445
7446 void
7447 s390_emit_epilogue (bool sibcall)
7448 {
7449 rtx frame_pointer, return_reg;
7450 int area_bottom, area_top, offset = 0;
7451 int next_offset;
7452 rtvec p;
7453 int i;
7454
7455 if (TARGET_TPF_PROFILING)
7456 {
7457
7458 /* Generate a BAS instruction to serve as a function
7459 entry intercept to facilitate the use of tracing
7460 algorithms located at the branch target. */
7461
7462 /* Emit a blockage here so that all code
7463 lies between the profiling mechanisms. */
7464 emit_insn (gen_blockage ());
7465
7466 emit_insn (gen_epilogue_tpf ());
7467 }
7468
7469 /* Check whether to use frame or stack pointer for restore. */
7470
7471 frame_pointer = (frame_pointer_needed
7472 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7473
7474 s390_frame_area (&area_bottom, &area_top);
7475
7476 /* Check whether we can access the register save area.
7477 If not, increment the frame pointer as required. */
7478
7479 if (area_top <= area_bottom)
7480 {
7481 /* Nothing to restore. */
7482 }
7483 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7484 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7485 {
7486 /* Area is in range. */
7487 offset = cfun_frame_layout.frame_size;
7488 }
7489 else
7490 {
7491 rtx insn, frame_off;
7492
7493 offset = area_bottom < 0 ? -area_bottom : 0;
7494 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7495
7496 if (DISP_IN_RANGE (INTVAL (frame_off)))
7497 {
7498 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7499 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7500 insn = emit_insn (insn);
7501 }
7502 else
7503 {
7504 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7505 frame_off = force_const_mem (Pmode, frame_off);
7506
7507 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7508 annotate_constant_pool_refs (&PATTERN (insn));
7509 }
7510 }
7511
7512 /* Restore call saved fprs. */
7513
7514 if (TARGET_64BIT)
7515 {
7516 if (cfun_save_high_fprs_p)
7517 {
7518 next_offset = cfun_frame_layout.f8_offset;
7519 for (i = 24; i < 32; i++)
7520 {
7521 if (cfun_fpr_bit_p (i - 16))
7522 {
7523 restore_fpr (frame_pointer,
7524 offset + next_offset, i);
7525 next_offset += 8;
7526 }
7527 }
7528 }
7529
7530 }
7531 else
7532 {
7533 next_offset = cfun_frame_layout.f4_offset;
7534 for (i = 18; i < 20; i++)
7535 {
7536 if (cfun_fpr_bit_p (i - 16))
7537 {
7538 restore_fpr (frame_pointer,
7539 offset + next_offset, i);
7540 next_offset += 8;
7541 }
7542 else if (!TARGET_PACKED_STACK)
7543 next_offset += 8;
7544 }
7545
7546 }
7547
7548 /* Return register. */
7549
7550 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7551
7552 /* Restore call saved gprs. */
7553
7554 if (cfun_frame_layout.first_restore_gpr != -1)
7555 {
7556 rtx insn, addr;
7557 int i;
7558
7559 /* Check for global register and save them
7560 to stack location from where they get restored. */
7561
7562 for (i = cfun_frame_layout.first_restore_gpr;
7563 i <= cfun_frame_layout.last_restore_gpr;
7564 i++)
7565 {
7566 /* These registers are special and need to be
7567 restored in any case. */
7568 if (i == STACK_POINTER_REGNUM
7569 || i == RETURN_REGNUM
7570 || i == BASE_REGNUM
7571 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7572 continue;
7573
7574 if (global_regs[i])
7575 {
7576 addr = plus_constant (frame_pointer,
7577 offset + cfun_frame_layout.gprs_offset
7578 + (i - cfun_frame_layout.first_save_gpr_slot)
7579 * UNITS_PER_WORD);
7580 addr = gen_rtx_MEM (Pmode, addr);
7581 set_mem_alias_set (addr, get_frame_alias_set ());
7582 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7583 }
7584 }
7585
7586 if (! sibcall)
7587 {
7588 /* Fetch return address from stack before load multiple,
7589 this will do good for scheduling. */
7590
7591 if (cfun_frame_layout.save_return_addr_p
7592 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7593 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7594 {
7595 int return_regnum = find_unused_clobbered_reg();
7596 if (!return_regnum)
7597 return_regnum = 4;
7598 return_reg = gen_rtx_REG (Pmode, return_regnum);
7599
7600 addr = plus_constant (frame_pointer,
7601 offset + cfun_frame_layout.gprs_offset
7602 + (RETURN_REGNUM
7603 - cfun_frame_layout.first_save_gpr_slot)
7604 * UNITS_PER_WORD);
7605 addr = gen_rtx_MEM (Pmode, addr);
7606 set_mem_alias_set (addr, get_frame_alias_set ());
7607 emit_move_insn (return_reg, addr);
7608 }
7609 }
7610
7611 insn = restore_gprs (frame_pointer,
7612 offset + cfun_frame_layout.gprs_offset
7613 + (cfun_frame_layout.first_restore_gpr
7614 - cfun_frame_layout.first_save_gpr_slot)
7615 * UNITS_PER_WORD,
7616 cfun_frame_layout.first_restore_gpr,
7617 cfun_frame_layout.last_restore_gpr);
7618 emit_insn (insn);
7619 }
7620
7621 if (! sibcall)
7622 {
7623
7624 /* Return to caller. */
7625
7626 p = rtvec_alloc (2);
7627
7628 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7629 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7630 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7631 }
7632 }
7633
7634
7635 /* Return the size in bytes of a function argument of
7636 type TYPE and/or mode MODE. At least one of TYPE or
7637 MODE must be specified. */
7638
7639 static int
7640 s390_function_arg_size (enum machine_mode mode, tree type)
7641 {
7642 if (type)
7643 return int_size_in_bytes (type);
7644
7645 /* No type info available for some library calls ... */
7646 if (mode != BLKmode)
7647 return GET_MODE_SIZE (mode);
7648
7649 /* If we have neither type nor mode, abort */
7650 gcc_unreachable ();
7651 }
7652
7653 /* Return true if a function argument of type TYPE and mode MODE
7654 is to be passed in a floating-point register, if available. */
7655
7656 static bool
7657 s390_function_arg_float (enum machine_mode mode, tree type)
7658 {
7659 int size = s390_function_arg_size (mode, type);
7660 if (size > 8)
7661 return false;
7662
7663 /* Soft-float changes the ABI: no floating-point registers are used. */
7664 if (TARGET_SOFT_FLOAT)
7665 return false;
7666
7667 /* No type info available for some library calls ... */
7668 if (!type)
7669 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
7670
7671 /* The ABI says that record types with a single member are treated
7672 just like that member would be. */
7673 while (TREE_CODE (type) == RECORD_TYPE)
7674 {
7675 tree field, single = NULL_TREE;
7676
7677 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7678 {
7679 if (TREE_CODE (field) != FIELD_DECL)
7680 continue;
7681
7682 if (single == NULL_TREE)
7683 single = TREE_TYPE (field);
7684 else
7685 return false;
7686 }
7687
7688 if (single == NULL_TREE)
7689 return false;
7690 else
7691 type = single;
7692 }
7693
7694 return TREE_CODE (type) == REAL_TYPE;
7695 }
7696
7697 /* Return true if a function argument of type TYPE and mode MODE
7698 is to be passed in an integer register, or a pair of integer
7699 registers, if available. */
7700
7701 static bool
7702 s390_function_arg_integer (enum machine_mode mode, tree type)
7703 {
7704 int size = s390_function_arg_size (mode, type);
7705 if (size > 8)
7706 return false;
7707
7708 /* No type info available for some library calls ... */
7709 if (!type)
7710 return GET_MODE_CLASS (mode) == MODE_INT
7711 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
7712
7713 /* We accept small integral (and similar) types. */
7714 if (INTEGRAL_TYPE_P (type)
7715 || POINTER_TYPE_P (type)
7716 || TREE_CODE (type) == OFFSET_TYPE
7717 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7718 return true;
7719
7720 /* We also accept structs of size 1, 2, 4, 8 that are not
7721 passed in floating-point registers. */
7722 if (AGGREGATE_TYPE_P (type)
7723 && exact_log2 (size) >= 0
7724 && !s390_function_arg_float (mode, type))
7725 return true;
7726
7727 return false;
7728 }
7729
7730 /* Return 1 if a function argument of type TYPE and mode MODE
7731 is to be passed by reference. The ABI specifies that only
7732 structures of size 1, 2, 4, or 8 bytes are passed by value,
7733 all other structures (and complex numbers) are passed by
7734 reference. */
7735
7736 static bool
7737 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7738 enum machine_mode mode, tree type,
7739 bool named ATTRIBUTE_UNUSED)
7740 {
7741 int size = s390_function_arg_size (mode, type);
7742 if (size > 8)
7743 return true;
7744
7745 if (type)
7746 {
7747 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7748 return 1;
7749
7750 if (TREE_CODE (type) == COMPLEX_TYPE
7751 || TREE_CODE (type) == VECTOR_TYPE)
7752 return 1;
7753 }
7754
7755 return 0;
7756 }
7757
7758 /* Update the data in CUM to advance over an argument of mode MODE and
7759 data type TYPE. (TYPE is null for libcalls where that information
7760 may not be available.). The boolean NAMED specifies whether the
7761 argument is a named argument (as opposed to an unnamed argument
7762 matching an ellipsis). */
7763
7764 void
7765 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7766 tree type, int named ATTRIBUTE_UNUSED)
7767 {
7768 if (s390_function_arg_float (mode, type))
7769 {
7770 cum->fprs += 1;
7771 }
7772 else if (s390_function_arg_integer (mode, type))
7773 {
7774 int size = s390_function_arg_size (mode, type);
7775 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7776 }
7777 else
7778 gcc_unreachable ();
7779 }
7780
7781 /* Define where to put the arguments to a function.
7782 Value is zero to push the argument on the stack,
7783 or a hard register in which to store the argument.
7784
7785 MODE is the argument's machine mode.
7786 TYPE is the data type of the argument (as a tree).
7787 This is null for libcalls where that information may
7788 not be available.
7789 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7790 the preceding args and about the function being called.
7791 NAMED is nonzero if this argument is a named parameter
7792 (otherwise it is an extra parameter matching an ellipsis).
7793
7794 On S/390, we use general purpose registers 2 through 6 to
7795 pass integer, pointer, and certain structure arguments, and
7796 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7797 to pass floating point arguments. All remaining arguments
7798 are pushed to the stack. */
7799
7800 rtx
7801 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7802 int named ATTRIBUTE_UNUSED)
7803 {
7804 if (s390_function_arg_float (mode, type))
7805 {
7806 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7807 return 0;
7808 else
7809 return gen_rtx_REG (mode, cum->fprs + 16);
7810 }
7811 else if (s390_function_arg_integer (mode, type))
7812 {
7813 int size = s390_function_arg_size (mode, type);
7814 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7815
7816 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7817 return 0;
7818 else
7819 return gen_rtx_REG (mode, cum->gprs + 2);
7820 }
7821
7822 /* After the real arguments, expand_call calls us once again
7823 with a void_type_node type. Whatever we return here is
7824 passed as operand 2 to the call expanders.
7825
7826 We don't need this feature ... */
7827 else if (type == void_type_node)
7828 return const0_rtx;
7829
7830 gcc_unreachable ();
7831 }
7832
7833 /* Return true if return values of type TYPE should be returned
7834 in a memory buffer whose address is passed by the caller as
7835 hidden first argument. */
7836
7837 static bool
7838 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7839 {
7840 /* We accept small integral (and similar) types. */
7841 if (INTEGRAL_TYPE_P (type)
7842 || POINTER_TYPE_P (type)
7843 || TREE_CODE (type) == OFFSET_TYPE
7844 || TREE_CODE (type) == REAL_TYPE)
7845 return int_size_in_bytes (type) > 8;
7846
7847 /* Aggregates and similar constructs are always returned
7848 in memory. */
7849 if (AGGREGATE_TYPE_P (type)
7850 || TREE_CODE (type) == COMPLEX_TYPE
7851 || TREE_CODE (type) == VECTOR_TYPE)
7852 return true;
7853
7854 /* ??? We get called on all sorts of random stuff from
7855 aggregate_value_p. We can't abort, but it's not clear
7856 what's safe to return. Pretend it's a struct I guess. */
7857 return true;
7858 }
7859
7860 /* Define where to return a (scalar) value of type TYPE.
7861 If TYPE is null, define where to return a (scalar)
7862 value of mode MODE from a libcall. */
7863
7864 rtx
7865 s390_function_value (tree type, enum machine_mode mode)
7866 {
7867 if (type)
7868 {
7869 int unsignedp = TYPE_UNSIGNED (type);
7870 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7871 }
7872
7873 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
7874 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7875
7876 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
7877 return gen_rtx_REG (mode, 16);
7878 else
7879 return gen_rtx_REG (mode, 2);
7880 }
7881
7882
7883 /* Create and return the va_list datatype.
7884
7885 On S/390, va_list is an array type equivalent to
7886
7887 typedef struct __va_list_tag
7888 {
7889 long __gpr;
7890 long __fpr;
7891 void *__overflow_arg_area;
7892 void *__reg_save_area;
7893 } va_list[1];
7894
7895 where __gpr and __fpr hold the number of general purpose
7896 or floating point arguments used up to now, respectively,
7897 __overflow_arg_area points to the stack location of the
7898 next argument passed on the stack, and __reg_save_area
7899 always points to the start of the register area in the
7900 call frame of the current function. The function prologue
7901 saves all registers used for argument passing into this
7902 area if the function uses variable arguments. */
7903
7904 static tree
7905 s390_build_builtin_va_list (void)
7906 {
7907 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7908
7909 record = lang_hooks.types.make_type (RECORD_TYPE);
7910
7911 type_decl =
7912 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7913
7914 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7915 long_integer_type_node);
7916 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7917 long_integer_type_node);
7918 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7919 ptr_type_node);
7920 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7921 ptr_type_node);
7922
7923 va_list_gpr_counter_field = f_gpr;
7924 va_list_fpr_counter_field = f_fpr;
7925
7926 DECL_FIELD_CONTEXT (f_gpr) = record;
7927 DECL_FIELD_CONTEXT (f_fpr) = record;
7928 DECL_FIELD_CONTEXT (f_ovf) = record;
7929 DECL_FIELD_CONTEXT (f_sav) = record;
7930
7931 TREE_CHAIN (record) = type_decl;
7932 TYPE_NAME (record) = type_decl;
7933 TYPE_FIELDS (record) = f_gpr;
7934 TREE_CHAIN (f_gpr) = f_fpr;
7935 TREE_CHAIN (f_fpr) = f_ovf;
7936 TREE_CHAIN (f_ovf) = f_sav;
7937
7938 layout_type (record);
7939
7940 /* The correct type is an array type of one element. */
7941 return build_array_type (record, build_index_type (size_zero_node));
7942 }
7943
7944 /* Implement va_start by filling the va_list structure VALIST.
7945 STDARG_P is always true, and ignored.
7946 NEXTARG points to the first anonymous stack argument.
7947
7948 The following global variables are used to initialize
7949 the va_list structure:
7950
7951 current_function_args_info:
7952 holds number of gprs and fprs used for named arguments.
7953 current_function_arg_offset_rtx:
7954 holds the offset of the first anonymous stack argument
7955 (relative to the virtual arg pointer). */
7956
7957 void
7958 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7959 {
7960 HOST_WIDE_INT n_gpr, n_fpr;
7961 int off;
7962 tree f_gpr, f_fpr, f_ovf, f_sav;
7963 tree gpr, fpr, ovf, sav, t;
7964
7965 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7966 f_fpr = TREE_CHAIN (f_gpr);
7967 f_ovf = TREE_CHAIN (f_fpr);
7968 f_sav = TREE_CHAIN (f_ovf);
7969
7970 valist = build_va_arg_indirect_ref (valist);
7971 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7972 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7973 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7974 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7975
7976 /* Count number of gp and fp argument registers used. */
7977
7978 n_gpr = current_function_args_info.gprs;
7979 n_fpr = current_function_args_info.fprs;
7980
7981 if (cfun->va_list_gpr_size)
7982 {
7983 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
7984 build_int_cst (NULL_TREE, n_gpr));
7985 TREE_SIDE_EFFECTS (t) = 1;
7986 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7987 }
7988
7989 if (cfun->va_list_fpr_size)
7990 {
7991 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
7992 build_int_cst (NULL_TREE, n_fpr));
7993 TREE_SIDE_EFFECTS (t) = 1;
7994 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7995 }
7996
7997 /* Find the overflow area. */
7998 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7999 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8000 {
8001 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8002
8003 off = INTVAL (current_function_arg_offset_rtx);
8004 off = off < 0 ? 0 : off;
8005 if (TARGET_DEBUG_ARG)
8006 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8007 (int)n_gpr, (int)n_fpr, off);
8008
8009 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
8010
8011 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
8012 TREE_SIDE_EFFECTS (t) = 1;
8013 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8014 }
8015
8016 /* Find the register save area. */
8017 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8018 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8019 {
8020 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8021 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
8022 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
8023
8024 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
8025 TREE_SIDE_EFFECTS (t) = 1;
8026 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8027 }
8028 }
8029
8030 /* Implement va_arg by updating the va_list structure
8031 VALIST as required to retrieve an argument of type
8032 TYPE, and returning that argument.
8033
8034 Generates code equivalent to:
8035
8036 if (integral value) {
8037 if (size <= 4 && args.gpr < 5 ||
8038 size > 4 && args.gpr < 4 )
8039 ret = args.reg_save_area[args.gpr+8]
8040 else
8041 ret = *args.overflow_arg_area++;
8042 } else if (float value) {
8043 if (args.fgpr < 2)
8044 ret = args.reg_save_area[args.fpr+64]
8045 else
8046 ret = *args.overflow_arg_area++;
8047 } else if (aggregate value) {
8048 if (args.gpr < 5)
8049 ret = *args.reg_save_area[args.gpr]
8050 else
8051 ret = **args.overflow_arg_area++;
8052 } */
8053
8054 static tree
8055 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
8056 tree *post_p ATTRIBUTE_UNUSED)
8057 {
8058 tree f_gpr, f_fpr, f_ovf, f_sav;
8059 tree gpr, fpr, ovf, sav, reg, t, u;
8060 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8061 tree lab_false, lab_over, addr;
8062
8063 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8064 f_fpr = TREE_CHAIN (f_gpr);
8065 f_ovf = TREE_CHAIN (f_fpr);
8066 f_sav = TREE_CHAIN (f_ovf);
8067
8068 valist = build_va_arg_indirect_ref (valist);
8069 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8070 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8071 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8072 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8073
8074 size = int_size_in_bytes (type);
8075
8076 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8077 {
8078 if (TARGET_DEBUG_ARG)
8079 {
8080 fprintf (stderr, "va_arg: aggregate type");
8081 debug_tree (type);
8082 }
8083
8084 /* Aggregates are passed by reference. */
8085 indirect_p = 1;
8086 reg = gpr;
8087 n_reg = 1;
8088
8089 /* kernel stack layout on 31 bit: It is assumed here that no padding
8090 will be added by s390_frame_info because for va_args always an even
8091 number of gprs has to be saved r15-r2 = 14 regs. */
8092 sav_ofs = 2 * UNITS_PER_WORD;
8093 sav_scale = UNITS_PER_WORD;
8094 size = UNITS_PER_WORD;
8095 max_reg = GP_ARG_NUM_REG - n_reg;
8096 }
8097 else if (s390_function_arg_float (TYPE_MODE (type), type))
8098 {
8099 if (TARGET_DEBUG_ARG)
8100 {
8101 fprintf (stderr, "va_arg: float type");
8102 debug_tree (type);
8103 }
8104
8105 /* FP args go in FP registers, if present. */
8106 indirect_p = 0;
8107 reg = fpr;
8108 n_reg = 1;
8109 sav_ofs = 16 * UNITS_PER_WORD;
8110 sav_scale = 8;
8111 max_reg = FP_ARG_NUM_REG - n_reg;
8112 }
8113 else
8114 {
8115 if (TARGET_DEBUG_ARG)
8116 {
8117 fprintf (stderr, "va_arg: other type");
8118 debug_tree (type);
8119 }
8120
8121 /* Otherwise into GP registers. */
8122 indirect_p = 0;
8123 reg = gpr;
8124 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8125
8126 /* kernel stack layout on 31 bit: It is assumed here that no padding
8127 will be added by s390_frame_info because for va_args always an even
8128 number of gprs has to be saved r15-r2 = 14 regs. */
8129 sav_ofs = 2 * UNITS_PER_WORD;
8130
8131 if (size < UNITS_PER_WORD)
8132 sav_ofs += UNITS_PER_WORD - size;
8133
8134 sav_scale = UNITS_PER_WORD;
8135 max_reg = GP_ARG_NUM_REG - n_reg;
8136 }
8137
8138 /* Pull the value out of the saved registers ... */
8139
8140 lab_false = create_artificial_label ();
8141 lab_over = create_artificial_label ();
8142 addr = create_tmp_var (ptr_type_node, "addr");
8143 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8144
8145 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8146 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8147 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8148 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8149 gimplify_and_add (t, pre_p);
8150
8151 t = build2 (PLUS_EXPR, ptr_type_node, sav,
8152 fold_convert (ptr_type_node, size_int (sav_ofs)));
8153 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8154 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8155 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
8156
8157 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
8158 gimplify_and_add (t, pre_p);
8159
8160 t = build1 (GOTO_EXPR, void_type_node, lab_over);
8161 gimplify_and_add (t, pre_p);
8162
8163 t = build1 (LABEL_EXPR, void_type_node, lab_false);
8164 append_to_statement_list (t, pre_p);
8165
8166
8167 /* ... Otherwise out of the overflow area. */
8168
8169 t = ovf;
8170 if (size < UNITS_PER_WORD)
8171 t = build2 (PLUS_EXPR, ptr_type_node, t,
8172 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
8173
8174 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8175
8176 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
8177 gimplify_and_add (u, pre_p);
8178
8179 t = build2 (PLUS_EXPR, ptr_type_node, t,
8180 fold_convert (ptr_type_node, size_int (size)));
8181 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, ovf, t);
8182 gimplify_and_add (t, pre_p);
8183
8184 t = build1 (LABEL_EXPR, void_type_node, lab_over);
8185 append_to_statement_list (t, pre_p);
8186
8187
8188 /* Increment register save count. */
8189
8190 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8191 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8192 gimplify_and_add (u, pre_p);
8193
8194 if (indirect_p)
8195 {
8196 t = build_pointer_type (build_pointer_type (type));
8197 addr = fold_convert (t, addr);
8198 addr = build_va_arg_indirect_ref (addr);
8199 }
8200 else
8201 {
8202 t = build_pointer_type (type);
8203 addr = fold_convert (t, addr);
8204 }
8205
8206 return build_va_arg_indirect_ref (addr);
8207 }
8208
8209
8210 /* Builtins. */
8211
8212 enum s390_builtin
8213 {
8214 S390_BUILTIN_THREAD_POINTER,
8215 S390_BUILTIN_SET_THREAD_POINTER,
8216
8217 S390_BUILTIN_max
8218 };
8219
8220 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8221 CODE_FOR_get_tp_64,
8222 CODE_FOR_set_tp_64
8223 };
8224
8225 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8226 CODE_FOR_get_tp_31,
8227 CODE_FOR_set_tp_31
8228 };
8229
8230 static void
8231 s390_init_builtins (void)
8232 {
8233 tree ftype;
8234
8235 ftype = build_function_type (ptr_type_node, void_list_node);
8236 add_builtin_function ("__builtin_thread_pointer", ftype,
8237 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8238 NULL, NULL_TREE);
8239
8240 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8241 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8242 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8243 NULL, NULL_TREE);
8244 }
8245
8246 /* Expand an expression EXP that calls a built-in function,
8247 with result going to TARGET if that's convenient
8248 (and in mode MODE if that's convenient).
8249 SUBTARGET may be used as the target for computing one of EXP's operands.
8250 IGNORE is nonzero if the value is to be ignored. */
8251
8252 static rtx
8253 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8254 enum machine_mode mode ATTRIBUTE_UNUSED,
8255 int ignore ATTRIBUTE_UNUSED)
8256 {
8257 #define MAX_ARGS 2
8258
8259 unsigned int const *code_for_builtin =
8260 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8261
8262 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8263 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8264 enum insn_code icode;
8265 rtx op[MAX_ARGS], pat;
8266 int arity;
8267 bool nonvoid;
8268 tree arg;
8269 call_expr_arg_iterator iter;
8270
8271 if (fcode >= S390_BUILTIN_max)
8272 internal_error ("bad builtin fcode");
8273 icode = code_for_builtin[fcode];
8274 if (icode == 0)
8275 internal_error ("bad builtin fcode");
8276
8277 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8278
8279 arity = 0;
8280 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8281 {
8282 const struct insn_operand_data *insn_op;
8283
8284 if (arg == error_mark_node)
8285 return NULL_RTX;
8286 if (arity > MAX_ARGS)
8287 return NULL_RTX;
8288
8289 insn_op = &insn_data[icode].operand[arity + nonvoid];
8290
8291 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8292
8293 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8294 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8295 arity++;
8296 }
8297
8298 if (nonvoid)
8299 {
8300 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8301 if (!target
8302 || GET_MODE (target) != tmode
8303 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8304 target = gen_reg_rtx (tmode);
8305 }
8306
8307 switch (arity)
8308 {
8309 case 0:
8310 pat = GEN_FCN (icode) (target);
8311 break;
8312 case 1:
8313 if (nonvoid)
8314 pat = GEN_FCN (icode) (target, op[0]);
8315 else
8316 pat = GEN_FCN (icode) (op[0]);
8317 break;
8318 case 2:
8319 pat = GEN_FCN (icode) (target, op[0], op[1]);
8320 break;
8321 default:
8322 gcc_unreachable ();
8323 }
8324 if (!pat)
8325 return NULL_RTX;
8326 emit_insn (pat);
8327
8328 if (nonvoid)
8329 return target;
8330 else
8331 return const0_rtx;
8332 }
8333
8334
8335 /* Output assembly code for the trampoline template to
8336 stdio stream FILE.
8337
8338 On S/390, we use gpr 1 internally in the trampoline code;
8339 gpr 0 is used to hold the static chain. */
8340
8341 void
8342 s390_trampoline_template (FILE *file)
8343 {
8344 rtx op[2];
8345 op[0] = gen_rtx_REG (Pmode, 0);
8346 op[1] = gen_rtx_REG (Pmode, 1);
8347
8348 if (TARGET_64BIT)
8349 {
8350 output_asm_insn ("basr\t%1,0", op);
8351 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8352 output_asm_insn ("br\t%1", op);
8353 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8354 }
8355 else
8356 {
8357 output_asm_insn ("basr\t%1,0", op);
8358 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8359 output_asm_insn ("br\t%1", op);
8360 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8361 }
8362 }
8363
8364 /* Emit RTL insns to initialize the variable parts of a trampoline.
8365 FNADDR is an RTX for the address of the function's pure code.
8366 CXT is an RTX for the static chain value for the function. */
8367
8368 void
8369 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8370 {
8371 emit_move_insn (gen_rtx_MEM (Pmode,
8372 memory_address (Pmode,
8373 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8374 emit_move_insn (gen_rtx_MEM (Pmode,
8375 memory_address (Pmode,
8376 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8377 }
8378
8379 /* Return rtx for 64-bit constant formed from the 32-bit subwords
8380 LOW and HIGH, independent of the host word size. */
8381
8382 rtx
8383 s390_gen_rtx_const_DI (int high, int low)
8384 {
8385 #if HOST_BITS_PER_WIDE_INT >= 64
8386 HOST_WIDE_INT val;
8387 val = (HOST_WIDE_INT)high;
8388 val <<= 32;
8389 val |= (HOST_WIDE_INT)low;
8390
8391 return GEN_INT (val);
8392 #else
8393 #if HOST_BITS_PER_WIDE_INT >= 32
8394 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8395 #else
8396 gcc_unreachable ();
8397 #endif
8398 #endif
8399 }
8400
8401 /* Output assembler code to FILE to increment profiler label # LABELNO
8402 for profiling a function entry. */
8403
8404 void
8405 s390_function_profiler (FILE *file, int labelno)
8406 {
8407 rtx op[7];
8408
8409 char label[128];
8410 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8411
8412 fprintf (file, "# function profiler \n");
8413
8414 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8415 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8416 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8417
8418 op[2] = gen_rtx_REG (Pmode, 1);
8419 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8420 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8421
8422 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8423 if (flag_pic)
8424 {
8425 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8426 op[4] = gen_rtx_CONST (Pmode, op[4]);
8427 }
8428
8429 if (TARGET_64BIT)
8430 {
8431 output_asm_insn ("stg\t%0,%1", op);
8432 output_asm_insn ("larl\t%2,%3", op);
8433 output_asm_insn ("brasl\t%0,%4", op);
8434 output_asm_insn ("lg\t%0,%1", op);
8435 }
8436 else if (!flag_pic)
8437 {
8438 op[6] = gen_label_rtx ();
8439
8440 output_asm_insn ("st\t%0,%1", op);
8441 output_asm_insn ("bras\t%2,%l6", op);
8442 output_asm_insn (".long\t%4", op);
8443 output_asm_insn (".long\t%3", op);
8444 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8445 output_asm_insn ("l\t%0,0(%2)", op);
8446 output_asm_insn ("l\t%2,4(%2)", op);
8447 output_asm_insn ("basr\t%0,%0", op);
8448 output_asm_insn ("l\t%0,%1", op);
8449 }
8450 else
8451 {
8452 op[5] = gen_label_rtx ();
8453 op[6] = gen_label_rtx ();
8454
8455 output_asm_insn ("st\t%0,%1", op);
8456 output_asm_insn ("bras\t%2,%l6", op);
8457 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8458 output_asm_insn (".long\t%4-%l5", op);
8459 output_asm_insn (".long\t%3-%l5", op);
8460 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8461 output_asm_insn ("lr\t%0,%2", op);
8462 output_asm_insn ("a\t%0,0(%2)", op);
8463 output_asm_insn ("a\t%2,4(%2)", op);
8464 output_asm_insn ("basr\t%0,%0", op);
8465 output_asm_insn ("l\t%0,%1", op);
8466 }
8467 }
8468
8469 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8470 into its SYMBOL_REF_FLAGS. */
8471
8472 static void
8473 s390_encode_section_info (tree decl, rtx rtl, int first)
8474 {
8475 default_encode_section_info (decl, rtl, first);
8476
8477 /* If a variable has a forced alignment to < 2 bytes, mark it with
8478 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8479 if (TREE_CODE (decl) == VAR_DECL
8480 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8481 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8482 }
8483
8484 /* Output thunk to FILE that implements a C++ virtual function call (with
8485 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8486 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8487 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8488 relative to the resulting this pointer. */
8489
8490 static void
8491 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8492 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8493 tree function)
8494 {
8495 rtx op[10];
8496 int nonlocal = 0;
8497
8498 /* Operand 0 is the target function. */
8499 op[0] = XEXP (DECL_RTL (function), 0);
8500 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8501 {
8502 nonlocal = 1;
8503 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8504 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8505 op[0] = gen_rtx_CONST (Pmode, op[0]);
8506 }
8507
8508 /* Operand 1 is the 'this' pointer. */
8509 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8510 op[1] = gen_rtx_REG (Pmode, 3);
8511 else
8512 op[1] = gen_rtx_REG (Pmode, 2);
8513
8514 /* Operand 2 is the delta. */
8515 op[2] = GEN_INT (delta);
8516
8517 /* Operand 3 is the vcall_offset. */
8518 op[3] = GEN_INT (vcall_offset);
8519
8520 /* Operand 4 is the temporary register. */
8521 op[4] = gen_rtx_REG (Pmode, 1);
8522
8523 /* Operands 5 to 8 can be used as labels. */
8524 op[5] = NULL_RTX;
8525 op[6] = NULL_RTX;
8526 op[7] = NULL_RTX;
8527 op[8] = NULL_RTX;
8528
8529 /* Operand 9 can be used for temporary register. */
8530 op[9] = NULL_RTX;
8531
8532 /* Generate code. */
8533 if (TARGET_64BIT)
8534 {
8535 /* Setup literal pool pointer if required. */
8536 if ((!DISP_IN_RANGE (delta)
8537 && !CONST_OK_FOR_K (delta)
8538 && !CONST_OK_FOR_Os (delta))
8539 || (!DISP_IN_RANGE (vcall_offset)
8540 && !CONST_OK_FOR_K (vcall_offset)
8541 && !CONST_OK_FOR_Os (vcall_offset)))
8542 {
8543 op[5] = gen_label_rtx ();
8544 output_asm_insn ("larl\t%4,%5", op);
8545 }
8546
8547 /* Add DELTA to this pointer. */
8548 if (delta)
8549 {
8550 if (CONST_OK_FOR_J (delta))
8551 output_asm_insn ("la\t%1,%2(%1)", op);
8552 else if (DISP_IN_RANGE (delta))
8553 output_asm_insn ("lay\t%1,%2(%1)", op);
8554 else if (CONST_OK_FOR_K (delta))
8555 output_asm_insn ("aghi\t%1,%2", op);
8556 else if (CONST_OK_FOR_Os (delta))
8557 output_asm_insn ("agfi\t%1,%2", op);
8558 else
8559 {
8560 op[6] = gen_label_rtx ();
8561 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8562 }
8563 }
8564
8565 /* Perform vcall adjustment. */
8566 if (vcall_offset)
8567 {
8568 if (DISP_IN_RANGE (vcall_offset))
8569 {
8570 output_asm_insn ("lg\t%4,0(%1)", op);
8571 output_asm_insn ("ag\t%1,%3(%4)", op);
8572 }
8573 else if (CONST_OK_FOR_K (vcall_offset))
8574 {
8575 output_asm_insn ("lghi\t%4,%3", op);
8576 output_asm_insn ("ag\t%4,0(%1)", op);
8577 output_asm_insn ("ag\t%1,0(%4)", op);
8578 }
8579 else if (CONST_OK_FOR_Os (vcall_offset))
8580 {
8581 output_asm_insn ("lgfi\t%4,%3", op);
8582 output_asm_insn ("ag\t%4,0(%1)", op);
8583 output_asm_insn ("ag\t%1,0(%4)", op);
8584 }
8585 else
8586 {
8587 op[7] = gen_label_rtx ();
8588 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8589 output_asm_insn ("ag\t%4,0(%1)", op);
8590 output_asm_insn ("ag\t%1,0(%4)", op);
8591 }
8592 }
8593
8594 /* Jump to target. */
8595 output_asm_insn ("jg\t%0", op);
8596
8597 /* Output literal pool if required. */
8598 if (op[5])
8599 {
8600 output_asm_insn (".align\t4", op);
8601 targetm.asm_out.internal_label (file, "L",
8602 CODE_LABEL_NUMBER (op[5]));
8603 }
8604 if (op[6])
8605 {
8606 targetm.asm_out.internal_label (file, "L",
8607 CODE_LABEL_NUMBER (op[6]));
8608 output_asm_insn (".long\t%2", op);
8609 }
8610 if (op[7])
8611 {
8612 targetm.asm_out.internal_label (file, "L",
8613 CODE_LABEL_NUMBER (op[7]));
8614 output_asm_insn (".long\t%3", op);
8615 }
8616 }
8617 else
8618 {
8619 /* Setup base pointer if required. */
8620 if (!vcall_offset
8621 || (!DISP_IN_RANGE (delta)
8622 && !CONST_OK_FOR_K (delta)
8623 && !CONST_OK_FOR_Os (delta))
8624 || (!DISP_IN_RANGE (delta)
8625 && !CONST_OK_FOR_K (vcall_offset)
8626 && !CONST_OK_FOR_Os (vcall_offset)))
8627 {
8628 op[5] = gen_label_rtx ();
8629 output_asm_insn ("basr\t%4,0", op);
8630 targetm.asm_out.internal_label (file, "L",
8631 CODE_LABEL_NUMBER (op[5]));
8632 }
8633
8634 /* Add DELTA to this pointer. */
8635 if (delta)
8636 {
8637 if (CONST_OK_FOR_J (delta))
8638 output_asm_insn ("la\t%1,%2(%1)", op);
8639 else if (DISP_IN_RANGE (delta))
8640 output_asm_insn ("lay\t%1,%2(%1)", op);
8641 else if (CONST_OK_FOR_K (delta))
8642 output_asm_insn ("ahi\t%1,%2", op);
8643 else if (CONST_OK_FOR_Os (delta))
8644 output_asm_insn ("afi\t%1,%2", op);
8645 else
8646 {
8647 op[6] = gen_label_rtx ();
8648 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8649 }
8650 }
8651
8652 /* Perform vcall adjustment. */
8653 if (vcall_offset)
8654 {
8655 if (CONST_OK_FOR_J (vcall_offset))
8656 {
8657 output_asm_insn ("l\t%4,0(%1)", op);
8658 output_asm_insn ("a\t%1,%3(%4)", op);
8659 }
8660 else if (DISP_IN_RANGE (vcall_offset))
8661 {
8662 output_asm_insn ("l\t%4,0(%1)", op);
8663 output_asm_insn ("ay\t%1,%3(%4)", op);
8664 }
8665 else if (CONST_OK_FOR_K (vcall_offset))
8666 {
8667 output_asm_insn ("lhi\t%4,%3", op);
8668 output_asm_insn ("a\t%4,0(%1)", op);
8669 output_asm_insn ("a\t%1,0(%4)", op);
8670 }
8671 else if (CONST_OK_FOR_Os (vcall_offset))
8672 {
8673 output_asm_insn ("iilf\t%4,%3", op);
8674 output_asm_insn ("a\t%4,0(%1)", op);
8675 output_asm_insn ("a\t%1,0(%4)", op);
8676 }
8677 else
8678 {
8679 op[7] = gen_label_rtx ();
8680 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8681 output_asm_insn ("a\t%4,0(%1)", op);
8682 output_asm_insn ("a\t%1,0(%4)", op);
8683 }
8684
8685 /* We had to clobber the base pointer register.
8686 Re-setup the base pointer (with a different base). */
8687 op[5] = gen_label_rtx ();
8688 output_asm_insn ("basr\t%4,0", op);
8689 targetm.asm_out.internal_label (file, "L",
8690 CODE_LABEL_NUMBER (op[5]));
8691 }
8692
8693 /* Jump to target. */
8694 op[8] = gen_label_rtx ();
8695
8696 if (!flag_pic)
8697 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8698 else if (!nonlocal)
8699 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8700 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8701 else if (flag_pic == 1)
8702 {
8703 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8704 output_asm_insn ("l\t%4,%0(%4)", op);
8705 }
8706 else if (flag_pic == 2)
8707 {
8708 op[9] = gen_rtx_REG (Pmode, 0);
8709 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8710 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8711 output_asm_insn ("ar\t%4,%9", op);
8712 output_asm_insn ("l\t%4,0(%4)", op);
8713 }
8714
8715 output_asm_insn ("br\t%4", op);
8716
8717 /* Output literal pool. */
8718 output_asm_insn (".align\t4", op);
8719
8720 if (nonlocal && flag_pic == 2)
8721 output_asm_insn (".long\t%0", op);
8722 if (nonlocal)
8723 {
8724 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8725 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8726 }
8727
8728 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8729 if (!flag_pic)
8730 output_asm_insn (".long\t%0", op);
8731 else
8732 output_asm_insn (".long\t%0-%5", op);
8733
8734 if (op[6])
8735 {
8736 targetm.asm_out.internal_label (file, "L",
8737 CODE_LABEL_NUMBER (op[6]));
8738 output_asm_insn (".long\t%2", op);
8739 }
8740 if (op[7])
8741 {
8742 targetm.asm_out.internal_label (file, "L",
8743 CODE_LABEL_NUMBER (op[7]));
8744 output_asm_insn (".long\t%3", op);
8745 }
8746 }
8747 }
8748
8749 static bool
8750 s390_valid_pointer_mode (enum machine_mode mode)
8751 {
8752 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8753 }
8754
8755 /* Checks whether the given CALL_EXPR would use a caller
8756 saved register. This is used to decide whether sibling call
8757 optimization could be performed on the respective function
8758 call. */
8759
8760 static bool
8761 s390_call_saved_register_used (tree call_expr)
8762 {
8763 CUMULATIVE_ARGS cum;
8764 tree parameter;
8765 enum machine_mode mode;
8766 tree type;
8767 rtx parm_rtx;
8768 int reg, i;
8769
8770 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8771
8772 for (i = 0; i < call_expr_nargs (call_expr); i++)
8773 {
8774 parameter = CALL_EXPR_ARG (call_expr, i);
8775 gcc_assert (parameter);
8776
8777 /* For an undeclared variable passed as parameter we will get
8778 an ERROR_MARK node here. */
8779 if (TREE_CODE (parameter) == ERROR_MARK)
8780 return true;
8781
8782 type = TREE_TYPE (parameter);
8783 gcc_assert (type);
8784
8785 mode = TYPE_MODE (type);
8786 gcc_assert (mode);
8787
8788 if (pass_by_reference (&cum, mode, type, true))
8789 {
8790 mode = Pmode;
8791 type = build_pointer_type (type);
8792 }
8793
8794 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8795
8796 s390_function_arg_advance (&cum, mode, type, 0);
8797
8798 if (parm_rtx && REG_P (parm_rtx))
8799 {
8800 for (reg = 0;
8801 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8802 reg++)
8803 if (! call_used_regs[reg + REGNO (parm_rtx)])
8804 return true;
8805 }
8806 }
8807 return false;
8808 }
8809
8810 /* Return true if the given call expression can be
8811 turned into a sibling call.
8812 DECL holds the declaration of the function to be called whereas
8813 EXP is the call expression itself. */
8814
8815 static bool
8816 s390_function_ok_for_sibcall (tree decl, tree exp)
8817 {
8818 /* The TPF epilogue uses register 1. */
8819 if (TARGET_TPF_PROFILING)
8820 return false;
8821
8822 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8823 which would have to be restored before the sibcall. */
8824 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
8825 return false;
8826
8827 /* Register 6 on s390 is available as an argument register but unfortunately
8828 "caller saved". This makes functions needing this register for arguments
8829 not suitable for sibcalls. */
8830 return !s390_call_saved_register_used (exp);
8831 }
8832
8833 /* Return the fixed registers used for condition codes. */
8834
8835 static bool
8836 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8837 {
8838 *p1 = CC_REGNUM;
8839 *p2 = INVALID_REGNUM;
8840
8841 return true;
8842 }
8843
8844 /* This function is used by the call expanders of the machine description.
8845 It emits the call insn itself together with the necessary operations
8846 to adjust the target address and returns the emitted insn.
8847 ADDR_LOCATION is the target address rtx
8848 TLS_CALL the location of the thread-local symbol
8849 RESULT_REG the register where the result of the call should be stored
8850 RETADDR_REG the register where the return address should be stored
8851 If this parameter is NULL_RTX the call is considered
8852 to be a sibling call. */
8853
8854 rtx
8855 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8856 rtx retaddr_reg)
8857 {
8858 bool plt_call = false;
8859 rtx insn;
8860 rtx call;
8861 rtx clobber;
8862 rtvec vec;
8863
8864 /* Direct function calls need special treatment. */
8865 if (GET_CODE (addr_location) == SYMBOL_REF)
8866 {
8867 /* When calling a global routine in PIC mode, we must
8868 replace the symbol itself with the PLT stub. */
8869 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8870 {
8871 addr_location = gen_rtx_UNSPEC (Pmode,
8872 gen_rtvec (1, addr_location),
8873 UNSPEC_PLT);
8874 addr_location = gen_rtx_CONST (Pmode, addr_location);
8875 plt_call = true;
8876 }
8877
8878 /* Unless we can use the bras(l) insn, force the
8879 routine address into a register. */
8880 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8881 {
8882 if (flag_pic)
8883 addr_location = legitimize_pic_address (addr_location, 0);
8884 else
8885 addr_location = force_reg (Pmode, addr_location);
8886 }
8887 }
8888
8889 /* If it is already an indirect call or the code above moved the
8890 SYMBOL_REF to somewhere else make sure the address can be found in
8891 register 1. */
8892 if (retaddr_reg == NULL_RTX
8893 && GET_CODE (addr_location) != SYMBOL_REF
8894 && !plt_call)
8895 {
8896 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8897 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8898 }
8899
8900 addr_location = gen_rtx_MEM (QImode, addr_location);
8901 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8902
8903 if (result_reg != NULL_RTX)
8904 call = gen_rtx_SET (VOIDmode, result_reg, call);
8905
8906 if (retaddr_reg != NULL_RTX)
8907 {
8908 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8909
8910 if (tls_call != NULL_RTX)
8911 vec = gen_rtvec (3, call, clobber,
8912 gen_rtx_USE (VOIDmode, tls_call));
8913 else
8914 vec = gen_rtvec (2, call, clobber);
8915
8916 call = gen_rtx_PARALLEL (VOIDmode, vec);
8917 }
8918
8919 insn = emit_call_insn (call);
8920
8921 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8922 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8923 {
8924 /* s390_function_ok_for_sibcall should
8925 have denied sibcalls in this case. */
8926 gcc_assert (retaddr_reg != NULL_RTX);
8927
8928 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8929 }
8930 return insn;
8931 }
8932
8933 /* Implement CONDITIONAL_REGISTER_USAGE. */
8934
8935 void
8936 s390_conditional_register_usage (void)
8937 {
8938 int i;
8939
8940 if (flag_pic)
8941 {
8942 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8943 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8944 }
8945 if (TARGET_CPU_ZARCH)
8946 {
8947 fixed_regs[BASE_REGNUM] = 0;
8948 call_used_regs[BASE_REGNUM] = 0;
8949 fixed_regs[RETURN_REGNUM] = 0;
8950 call_used_regs[RETURN_REGNUM] = 0;
8951 }
8952 if (TARGET_64BIT)
8953 {
8954 for (i = 24; i < 32; i++)
8955 call_used_regs[i] = call_really_used_regs[i] = 0;
8956 }
8957 else
8958 {
8959 for (i = 18; i < 20; i++)
8960 call_used_regs[i] = call_really_used_regs[i] = 0;
8961 }
8962
8963 if (TARGET_SOFT_FLOAT)
8964 {
8965 for (i = 16; i < 32; i++)
8966 call_used_regs[i] = fixed_regs[i] = 1;
8967 }
8968 }
8969
8970 /* Corresponding function to eh_return expander. */
8971
8972 static GTY(()) rtx s390_tpf_eh_return_symbol;
8973 void
8974 s390_emit_tpf_eh_return (rtx target)
8975 {
8976 rtx insn, reg;
8977
8978 if (!s390_tpf_eh_return_symbol)
8979 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8980
8981 reg = gen_rtx_REG (Pmode, 2);
8982
8983 emit_move_insn (reg, target);
8984 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8985 gen_rtx_REG (Pmode, RETURN_REGNUM));
8986 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8987
8988 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8989 }
8990
8991 /* Rework the prologue/epilogue to avoid saving/restoring
8992 registers unnecessarily. */
8993
8994 static void
8995 s390_optimize_prologue (void)
8996 {
8997 rtx insn, new_insn, next_insn;
8998
8999 /* Do a final recompute of the frame-related data. */
9000
9001 s390_update_frame_layout ();
9002
9003 /* If all special registers are in fact used, there's nothing we
9004 can do, so no point in walking the insn list. */
9005
9006 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9007 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9008 && (TARGET_CPU_ZARCH
9009 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9010 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9011 return;
9012
9013 /* Search for prologue/epilogue insns and replace them. */
9014
9015 for (insn = get_insns (); insn; insn = next_insn)
9016 {
9017 int first, last, off;
9018 rtx set, base, offset;
9019
9020 next_insn = NEXT_INSN (insn);
9021
9022 if (GET_CODE (insn) != INSN)
9023 continue;
9024
9025 if (GET_CODE (PATTERN (insn)) == PARALLEL
9026 && store_multiple_operation (PATTERN (insn), VOIDmode))
9027 {
9028 set = XVECEXP (PATTERN (insn), 0, 0);
9029 first = REGNO (SET_SRC (set));
9030 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9031 offset = const0_rtx;
9032 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9033 off = INTVAL (offset);
9034
9035 if (GET_CODE (base) != REG || off < 0)
9036 continue;
9037 if (cfun_frame_layout.first_save_gpr != -1
9038 && (cfun_frame_layout.first_save_gpr < first
9039 || cfun_frame_layout.last_save_gpr > last))
9040 continue;
9041 if (REGNO (base) != STACK_POINTER_REGNUM
9042 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9043 continue;
9044 if (first > BASE_REGNUM || last < BASE_REGNUM)
9045 continue;
9046
9047 if (cfun_frame_layout.first_save_gpr != -1)
9048 {
9049 new_insn = save_gprs (base,
9050 off + (cfun_frame_layout.first_save_gpr
9051 - first) * UNITS_PER_WORD,
9052 cfun_frame_layout.first_save_gpr,
9053 cfun_frame_layout.last_save_gpr);
9054 new_insn = emit_insn_before (new_insn, insn);
9055 INSN_ADDRESSES_NEW (new_insn, -1);
9056 }
9057
9058 remove_insn (insn);
9059 continue;
9060 }
9061
9062 if (cfun_frame_layout.first_save_gpr == -1
9063 && GET_CODE (PATTERN (insn)) == SET
9064 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9065 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9066 || (!TARGET_CPU_ZARCH
9067 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9068 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9069 {
9070 set = PATTERN (insn);
9071 first = REGNO (SET_SRC (set));
9072 offset = const0_rtx;
9073 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9074 off = INTVAL (offset);
9075
9076 if (GET_CODE (base) != REG || off < 0)
9077 continue;
9078 if (REGNO (base) != STACK_POINTER_REGNUM
9079 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9080 continue;
9081
9082 remove_insn (insn);
9083 continue;
9084 }
9085
9086 if (GET_CODE (PATTERN (insn)) == PARALLEL
9087 && load_multiple_operation (PATTERN (insn), VOIDmode))
9088 {
9089 set = XVECEXP (PATTERN (insn), 0, 0);
9090 first = REGNO (SET_DEST (set));
9091 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9092 offset = const0_rtx;
9093 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9094 off = INTVAL (offset);
9095
9096 if (GET_CODE (base) != REG || off < 0)
9097 continue;
9098 if (cfun_frame_layout.first_restore_gpr != -1
9099 && (cfun_frame_layout.first_restore_gpr < first
9100 || cfun_frame_layout.last_restore_gpr > last))
9101 continue;
9102 if (REGNO (base) != STACK_POINTER_REGNUM
9103 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9104 continue;
9105 if (first > BASE_REGNUM || last < BASE_REGNUM)
9106 continue;
9107
9108 if (cfun_frame_layout.first_restore_gpr != -1)
9109 {
9110 new_insn = restore_gprs (base,
9111 off + (cfun_frame_layout.first_restore_gpr
9112 - first) * UNITS_PER_WORD,
9113 cfun_frame_layout.first_restore_gpr,
9114 cfun_frame_layout.last_restore_gpr);
9115 new_insn = emit_insn_before (new_insn, insn);
9116 INSN_ADDRESSES_NEW (new_insn, -1);
9117 }
9118
9119 remove_insn (insn);
9120 continue;
9121 }
9122
9123 if (cfun_frame_layout.first_restore_gpr == -1
9124 && GET_CODE (PATTERN (insn)) == SET
9125 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9126 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9127 || (!TARGET_CPU_ZARCH
9128 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9129 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9130 {
9131 set = PATTERN (insn);
9132 first = REGNO (SET_DEST (set));
9133 offset = const0_rtx;
9134 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9135 off = INTVAL (offset);
9136
9137 if (GET_CODE (base) != REG || off < 0)
9138 continue;
9139 if (REGNO (base) != STACK_POINTER_REGNUM
9140 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9141 continue;
9142
9143 remove_insn (insn);
9144 continue;
9145 }
9146 }
9147 }
9148
9149 /* Perform machine-dependent processing. */
9150
9151 static void
9152 s390_reorg (void)
9153 {
9154 bool pool_overflow = false;
9155
9156 /* Make sure all splits have been performed; splits after
9157 machine_dependent_reorg might confuse insn length counts. */
9158 split_all_insns_noflow ();
9159
9160 /* From here on decomposed literal pool addresses must be accepted. */
9161 cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
9162
9163 /* Install the main literal pool and the associated base
9164 register load insns.
9165
9166 In addition, there are two problematic situations we need
9167 to correct:
9168
9169 - the literal pool might be > 4096 bytes in size, so that
9170 some of its elements cannot be directly accessed
9171
9172 - a branch target might be > 64K away from the branch, so that
9173 it is not possible to use a PC-relative instruction.
9174
9175 To fix those, we split the single literal pool into multiple
9176 pool chunks, reloading the pool base register at various
9177 points throughout the function to ensure it always points to
9178 the pool chunk the following code expects, and / or replace
9179 PC-relative branches by absolute branches.
9180
9181 However, the two problems are interdependent: splitting the
9182 literal pool can move a branch further away from its target,
9183 causing the 64K limit to overflow, and on the other hand,
9184 replacing a PC-relative branch by an absolute branch means
9185 we need to put the branch target address into the literal
9186 pool, possibly causing it to overflow.
9187
9188 So, we loop trying to fix up both problems until we manage
9189 to satisfy both conditions at the same time. Note that the
9190 loop is guaranteed to terminate as every pass of the loop
9191 strictly decreases the total number of PC-relative branches
9192 in the function. (This is not completely true as there
9193 might be branch-over-pool insns introduced by chunkify_start.
9194 Those never need to be split however.) */
9195
9196 for (;;)
9197 {
9198 struct constant_pool *pool = NULL;
9199
9200 /* Collect the literal pool. */
9201 if (!pool_overflow)
9202 {
9203 pool = s390_mainpool_start ();
9204 if (!pool)
9205 pool_overflow = true;
9206 }
9207
9208 /* If literal pool overflowed, start to chunkify it. */
9209 if (pool_overflow)
9210 pool = s390_chunkify_start ();
9211
9212 /* Split out-of-range branches. If this has created new
9213 literal pool entries, cancel current chunk list and
9214 recompute it. zSeries machines have large branch
9215 instructions, so we never need to split a branch. */
9216 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9217 {
9218 if (pool_overflow)
9219 s390_chunkify_cancel (pool);
9220 else
9221 s390_mainpool_cancel (pool);
9222
9223 continue;
9224 }
9225
9226 /* If we made it up to here, both conditions are satisfied.
9227 Finish up literal pool related changes. */
9228 if (pool_overflow)
9229 s390_chunkify_finish (pool);
9230 else
9231 s390_mainpool_finish (pool);
9232
9233 /* We're done splitting branches. */
9234 cfun->machine->split_branches_pending_p = false;
9235 break;
9236 }
9237
9238 /* Generate out-of-pool execute target insns. */
9239 if (TARGET_CPU_ZARCH)
9240 {
9241 rtx insn, label, target;
9242
9243 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9244 {
9245 label = s390_execute_label (insn);
9246 if (!label)
9247 continue;
9248
9249 gcc_assert (label != const0_rtx);
9250
9251 target = emit_label (XEXP (label, 0));
9252 INSN_ADDRESSES_NEW (target, -1);
9253
9254 target = emit_insn (s390_execute_target (insn));
9255 INSN_ADDRESSES_NEW (target, -1);
9256 }
9257 }
9258
9259 /* Try to optimize prologue and epilogue further. */
9260 s390_optimize_prologue ();
9261 }
9262
9263
9264 /* Initialize GCC target structure. */
9265
9266 #undef TARGET_ASM_ALIGNED_HI_OP
9267 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9268 #undef TARGET_ASM_ALIGNED_DI_OP
9269 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9270 #undef TARGET_ASM_INTEGER
9271 #define TARGET_ASM_INTEGER s390_assemble_integer
9272
9273 #undef TARGET_ASM_OPEN_PAREN
9274 #define TARGET_ASM_OPEN_PAREN ""
9275
9276 #undef TARGET_ASM_CLOSE_PAREN
9277 #define TARGET_ASM_CLOSE_PAREN ""
9278
9279 #undef TARGET_DEFAULT_TARGET_FLAGS
9280 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9281 #undef TARGET_HANDLE_OPTION
9282 #define TARGET_HANDLE_OPTION s390_handle_option
9283
9284 #undef TARGET_ENCODE_SECTION_INFO
9285 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9286
9287 #ifdef HAVE_AS_TLS
9288 #undef TARGET_HAVE_TLS
9289 #define TARGET_HAVE_TLS true
9290 #endif
9291 #undef TARGET_CANNOT_FORCE_CONST_MEM
9292 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9293
9294 #undef TARGET_DELEGITIMIZE_ADDRESS
9295 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9296
9297 #undef TARGET_RETURN_IN_MEMORY
9298 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9299
9300 #undef TARGET_INIT_BUILTINS
9301 #define TARGET_INIT_BUILTINS s390_init_builtins
9302 #undef TARGET_EXPAND_BUILTIN
9303 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9304
9305 #undef TARGET_ASM_OUTPUT_MI_THUNK
9306 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9307 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9308 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9309
9310 #undef TARGET_SCHED_ADJUST_PRIORITY
9311 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9312 #undef TARGET_SCHED_ISSUE_RATE
9313 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9314 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9315 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9316
9317 #undef TARGET_CANNOT_COPY_INSN_P
9318 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9319 #undef TARGET_RTX_COSTS
9320 #define TARGET_RTX_COSTS s390_rtx_costs
9321 #undef TARGET_ADDRESS_COST
9322 #define TARGET_ADDRESS_COST s390_address_cost
9323
9324 #undef TARGET_MACHINE_DEPENDENT_REORG
9325 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9326
9327 #undef TARGET_VALID_POINTER_MODE
9328 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9329
9330 #undef TARGET_BUILD_BUILTIN_VA_LIST
9331 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9332 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9333 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9334
9335 #undef TARGET_PROMOTE_FUNCTION_ARGS
9336 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9337 #undef TARGET_PROMOTE_FUNCTION_RETURN
9338 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9339 #undef TARGET_PASS_BY_REFERENCE
9340 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9341
9342 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9343 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9344
9345 #undef TARGET_FIXED_CONDITION_CODE_REGS
9346 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9347
9348 #undef TARGET_CC_MODES_COMPATIBLE
9349 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9350
9351 #undef TARGET_INVALID_WITHIN_DOLOOP
9352 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9353
9354 #ifdef HAVE_AS_TLS
9355 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9356 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9357 #endif
9358
9359 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9360 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
9361 #define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type
9362 #endif
9363
9364 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9365 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9366
9367 struct gcc_target targetm = TARGET_INITIALIZER;
9368
9369 #include "gt-s390.h"