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config.gcc (s390-*-linux-*, [...]): Add t-dfprules to tmake_file.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 02110-1301, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "tree-gimple.h"
54
55
56 /* Define the specific costs for a given cpu. */
57
58 struct processor_costs
59 {
60 /* multiplication */
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
74 const int mxbr;
75 /* square root */
76 const int sqxbr; /* cost of square root in TFmode. */
77 const int sqdbr; /* cost of square root in DFmode. */
78 const int sqebr; /* cost of square root in SFmode. */
79 /* multiply and add */
80 const int madbr; /* cost of multiply and add in DFmode. */
81 const int maebr; /* cost of multiply and add in SFmode. */
82 /* division */
83 const int dxbr;
84 const int dxr;
85 const int ddbr;
86 const int ddr;
87 const int debr;
88 const int der;
89 const int dlgr;
90 const int dlr;
91 const int dr;
92 const int dsgfr;
93 const int dsgr;
94 };
95
96 const struct processor_costs *s390_cost;
97
98 static const
99 struct processor_costs z900_cost =
100 {
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (135), /* DXR */
122 COSTS_N_INSNS (30), /* DDBR */
123 COSTS_N_INSNS (30), /* DDR */
124 COSTS_N_INSNS (27), /* DEBR */
125 COSTS_N_INSNS (26), /* DER */
126 COSTS_N_INSNS (220), /* DLGR */
127 COSTS_N_INSNS (34), /* DLR */
128 COSTS_N_INSNS (34), /* DR */
129 COSTS_N_INSNS (32), /* DSGFR */
130 COSTS_N_INSNS (32), /* DSGR */
131 };
132
133 static const
134 struct processor_costs z990_cost =
135 {
136 COSTS_N_INSNS (4), /* M */
137 COSTS_N_INSNS (2), /* MGHI */
138 COSTS_N_INSNS (2), /* MH */
139 COSTS_N_INSNS (2), /* MHI */
140 COSTS_N_INSNS (4), /* ML */
141 COSTS_N_INSNS (4), /* MR */
142 COSTS_N_INSNS (5), /* MS */
143 COSTS_N_INSNS (6), /* MSG */
144 COSTS_N_INSNS (4), /* MSGF */
145 COSTS_N_INSNS (4), /* MSGFR */
146 COSTS_N_INSNS (4), /* MSGR */
147 COSTS_N_INSNS (4), /* MSR */
148 COSTS_N_INSNS (1), /* multiplication in DFmode */
149 COSTS_N_INSNS (28), /* MXBR */
150 COSTS_N_INSNS (130), /* SQXBR */
151 COSTS_N_INSNS (66), /* SQDBR */
152 COSTS_N_INSNS (38), /* SQEBR */
153 COSTS_N_INSNS (1), /* MADBR */
154 COSTS_N_INSNS (1), /* MAEBR */
155 COSTS_N_INSNS (60), /* DXBR */
156 COSTS_N_INSNS (72), /* DXR */
157 COSTS_N_INSNS (40), /* DDBR */
158 COSTS_N_INSNS (44), /* DDR */
159 COSTS_N_INSNS (26), /* DDBR */
160 COSTS_N_INSNS (28), /* DER */
161 COSTS_N_INSNS (176), /* DLGR */
162 COSTS_N_INSNS (31), /* DLR */
163 COSTS_N_INSNS (31), /* DR */
164 COSTS_N_INSNS (31), /* DSGFR */
165 COSTS_N_INSNS (31), /* DSGR */
166 };
167
168 static const
169 struct processor_costs z9_109_cost =
170 {
171 COSTS_N_INSNS (4), /* M */
172 COSTS_N_INSNS (2), /* MGHI */
173 COSTS_N_INSNS (2), /* MH */
174 COSTS_N_INSNS (2), /* MHI */
175 COSTS_N_INSNS (4), /* ML */
176 COSTS_N_INSNS (4), /* MR */
177 COSTS_N_INSNS (5), /* MS */
178 COSTS_N_INSNS (6), /* MSG */
179 COSTS_N_INSNS (4), /* MSGF */
180 COSTS_N_INSNS (4), /* MSGFR */
181 COSTS_N_INSNS (4), /* MSGR */
182 COSTS_N_INSNS (4), /* MSR */
183 COSTS_N_INSNS (1), /* multiplication in DFmode */
184 COSTS_N_INSNS (28), /* MXBR */
185 COSTS_N_INSNS (130), /* SQXBR */
186 COSTS_N_INSNS (66), /* SQDBR */
187 COSTS_N_INSNS (38), /* SQEBR */
188 COSTS_N_INSNS (1), /* MADBR */
189 COSTS_N_INSNS (1), /* MAEBR */
190 COSTS_N_INSNS (60), /* DXBR */
191 COSTS_N_INSNS (72), /* DXR */
192 COSTS_N_INSNS (40), /* DDBR */
193 COSTS_N_INSNS (37), /* DDR */
194 COSTS_N_INSNS (26), /* DDBR */
195 COSTS_N_INSNS (28), /* DER */
196 COSTS_N_INSNS (30), /* DLGR */
197 COSTS_N_INSNS (23), /* DLR */
198 COSTS_N_INSNS (23), /* DR */
199 COSTS_N_INSNS (24), /* DSGFR */
200 COSTS_N_INSNS (24), /* DSGR */
201 };
202
203 extern int reload_completed;
204
205 /* Save information from a "cmpxx" operation until the branch or scc is
206 emitted. */
207 rtx s390_compare_op0, s390_compare_op1;
208
209 /* Save the result of a compare_and_swap until the branch or scc is
210 emitted. */
211 rtx s390_compare_emitted = NULL_RTX;
212
213 /* Structure used to hold the components of a S/390 memory
214 address. A legitimate address on S/390 is of the general
215 form
216 base + index + displacement
217 where any of the components is optional.
218
219 base and index are registers of the class ADDR_REGS,
220 displacement is an unsigned 12-bit immediate constant. */
221
222 struct s390_address
223 {
224 rtx base;
225 rtx indx;
226 rtx disp;
227 bool pointer;
228 bool literal_pool;
229 };
230
231 /* Which cpu are we tuning for. */
232 enum processor_type s390_tune = PROCESSOR_max;
233 enum processor_flags s390_tune_flags;
234 /* Which instruction set architecture to use. */
235 enum processor_type s390_arch;
236 enum processor_flags s390_arch_flags;
237
238 HOST_WIDE_INT s390_warn_framesize = 0;
239 HOST_WIDE_INT s390_stack_size = 0;
240 HOST_WIDE_INT s390_stack_guard = 0;
241
242 /* The following structure is embedded in the machine
243 specific part of struct function. */
244
245 struct s390_frame_layout GTY (())
246 {
247 /* Offset within stack frame. */
248 HOST_WIDE_INT gprs_offset;
249 HOST_WIDE_INT f0_offset;
250 HOST_WIDE_INT f4_offset;
251 HOST_WIDE_INT f8_offset;
252 HOST_WIDE_INT backchain_offset;
253
254 /* Number of first and last gpr where slots in the register
255 save area are reserved for. */
256 int first_save_gpr_slot;
257 int last_save_gpr_slot;
258
259 /* Number of first and last gpr to be saved, restored. */
260 int first_save_gpr;
261 int first_restore_gpr;
262 int last_save_gpr;
263 int last_restore_gpr;
264
265 /* Bits standing for floating point registers. Set, if the
266 respective register has to be saved. Starting with reg 16 (f0)
267 at the rightmost bit.
268 Bit 15 - 8 7 6 5 4 3 2 1 0
269 fpr 15 - 8 7 5 3 1 6 4 2 0
270 reg 31 - 24 23 22 21 20 19 18 17 16 */
271 unsigned int fpr_bitmap;
272
273 /* Number of floating point registers f8-f15 which must be saved. */
274 int high_fprs;
275
276 /* Set if return address needs to be saved.
277 This flag is set by s390_return_addr_rtx if it could not use
278 the initial value of r14 and therefore depends on r14 saved
279 to the stack. */
280 bool save_return_addr_p;
281
282 /* Size of stack frame. */
283 HOST_WIDE_INT frame_size;
284 };
285
286 /* Define the structure for the machine field in struct function. */
287
288 struct machine_function GTY(())
289 {
290 struct s390_frame_layout frame_layout;
291
292 /* Literal pool base register. */
293 rtx base_reg;
294
295 /* True if we may need to perform branch splitting. */
296 bool split_branches_pending_p;
297
298 /* True during final stage of literal pool processing. */
299 bool decomposed_literal_pool_addresses_ok_p;
300
301 /* Some local-dynamic TLS symbol name. */
302 const char *some_ld_name;
303
304 bool has_landing_pad_p;
305 };
306
307 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
308
309 #define cfun_frame_layout (cfun->machine->frame_layout)
310 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
311 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
312 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
313 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
314 (1 << (BITNUM)))
315 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
316 (1 << (BITNUM))))
317
318 /* Number of GPRs and FPRs used for argument passing. */
319 #define GP_ARG_NUM_REG 5
320 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
321
322 /* A couple of shortcuts. */
323 #define CONST_OK_FOR_J(x) \
324 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
325 #define CONST_OK_FOR_K(x) \
326 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
327 #define CONST_OK_FOR_Os(x) \
328 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
329 #define CONST_OK_FOR_Op(x) \
330 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
331 #define CONST_OK_FOR_On(x) \
332 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
333
334 #define REGNO_PAIR_OK(REGNO, MODE) \
335 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
336
337 /* Return true if the back end supports mode MODE. */
338 static bool
339 s390_scalar_mode_supported_p (enum machine_mode mode)
340 {
341 if (DECIMAL_FLOAT_MODE_P (mode))
342 return true;
343 else
344 return default_scalar_mode_supported_p (mode);
345 }
346
347 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
348
349 void
350 s390_set_has_landing_pad_p (bool value)
351 {
352 cfun->machine->has_landing_pad_p = value;
353 }
354
355 /* If two condition code modes are compatible, return a condition code
356 mode which is compatible with both. Otherwise, return
357 VOIDmode. */
358
359 static enum machine_mode
360 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
361 {
362 if (m1 == m2)
363 return m1;
364
365 switch (m1)
366 {
367 case CCZmode:
368 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
369 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
370 return m2;
371 return VOIDmode;
372
373 case CCSmode:
374 case CCUmode:
375 case CCTmode:
376 case CCSRmode:
377 case CCURmode:
378 case CCZ1mode:
379 if (m2 == CCZmode)
380 return m1;
381
382 return VOIDmode;
383
384 default:
385 return VOIDmode;
386 }
387 return VOIDmode;
388 }
389
390 /* Return true if SET either doesn't set the CC register, or else
391 the source and destination have matching CC modes and that
392 CC mode is at least as constrained as REQ_MODE. */
393
394 static bool
395 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
396 {
397 enum machine_mode set_mode;
398
399 gcc_assert (GET_CODE (set) == SET);
400
401 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
402 return 1;
403
404 set_mode = GET_MODE (SET_DEST (set));
405 switch (set_mode)
406 {
407 case CCSmode:
408 case CCSRmode:
409 case CCUmode:
410 case CCURmode:
411 case CCLmode:
412 case CCL1mode:
413 case CCL2mode:
414 case CCL3mode:
415 case CCT1mode:
416 case CCT2mode:
417 case CCT3mode:
418 if (req_mode != set_mode)
419 return 0;
420 break;
421
422 case CCZmode:
423 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
424 && req_mode != CCSRmode && req_mode != CCURmode)
425 return 0;
426 break;
427
428 case CCAPmode:
429 case CCANmode:
430 if (req_mode != CCAmode)
431 return 0;
432 break;
433
434 default:
435 gcc_unreachable ();
436 }
437
438 return (GET_MODE (SET_SRC (set)) == set_mode);
439 }
440
441 /* Return true if every SET in INSN that sets the CC register
442 has source and destination with matching CC modes and that
443 CC mode is at least as constrained as REQ_MODE.
444 If REQ_MODE is VOIDmode, always return false. */
445
446 bool
447 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
448 {
449 int i;
450
451 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
452 if (req_mode == VOIDmode)
453 return false;
454
455 if (GET_CODE (PATTERN (insn)) == SET)
456 return s390_match_ccmode_set (PATTERN (insn), req_mode);
457
458 if (GET_CODE (PATTERN (insn)) == PARALLEL)
459 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
460 {
461 rtx set = XVECEXP (PATTERN (insn), 0, i);
462 if (GET_CODE (set) == SET)
463 if (!s390_match_ccmode_set (set, req_mode))
464 return false;
465 }
466
467 return true;
468 }
469
470 /* If a test-under-mask instruction can be used to implement
471 (compare (and ... OP1) OP2), return the CC mode required
472 to do that. Otherwise, return VOIDmode.
473 MIXED is true if the instruction can distinguish between
474 CC1 and CC2 for mixed selected bits (TMxx), it is false
475 if the instruction cannot (TM). */
476
477 enum machine_mode
478 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
479 {
480 int bit0, bit1;
481
482 /* ??? Fixme: should work on CONST_DOUBLE as well. */
483 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
484 return VOIDmode;
485
486 /* Selected bits all zero: CC0.
487 e.g.: int a; if ((a & (16 + 128)) == 0) */
488 if (INTVAL (op2) == 0)
489 return CCTmode;
490
491 /* Selected bits all one: CC3.
492 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
493 if (INTVAL (op2) == INTVAL (op1))
494 return CCT3mode;
495
496 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
497 int a;
498 if ((a & (16 + 128)) == 16) -> CCT1
499 if ((a & (16 + 128)) == 128) -> CCT2 */
500 if (mixed)
501 {
502 bit1 = exact_log2 (INTVAL (op2));
503 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
504 if (bit0 != -1 && bit1 != -1)
505 return bit0 > bit1 ? CCT1mode : CCT2mode;
506 }
507
508 return VOIDmode;
509 }
510
511 /* Given a comparison code OP (EQ, NE, etc.) and the operands
512 OP0 and OP1 of a COMPARE, return the mode to be used for the
513 comparison. */
514
515 enum machine_mode
516 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
517 {
518 switch (code)
519 {
520 case EQ:
521 case NE:
522 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
523 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
524 return CCAPmode;
525 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
526 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
527 return CCAPmode;
528 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
529 || GET_CODE (op1) == NEG)
530 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
531 return CCLmode;
532
533 if (GET_CODE (op0) == AND)
534 {
535 /* Check whether we can potentially do it via TM. */
536 enum machine_mode ccmode;
537 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
538 if (ccmode != VOIDmode)
539 {
540 /* Relax CCTmode to CCZmode to allow fall-back to AND
541 if that turns out to be beneficial. */
542 return ccmode == CCTmode ? CCZmode : ccmode;
543 }
544 }
545
546 if (register_operand (op0, HImode)
547 && GET_CODE (op1) == CONST_INT
548 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
549 return CCT3mode;
550 if (register_operand (op0, QImode)
551 && GET_CODE (op1) == CONST_INT
552 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
553 return CCT3mode;
554
555 return CCZmode;
556
557 case LE:
558 case LT:
559 case GE:
560 case GT:
561 /* The only overflow condition of NEG and ABS happens when
562 -INT_MAX is used as parameter, which stays negative. So
563 we have an overflow from a positive value to a negative.
564 Using CCAP mode the resulting cc can be used for comparisons. */
565 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
566 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
567 return CCAPmode;
568
569 /* If constants are involved in an add instruction it is possible to use
570 the resulting cc for comparisons with zero. Knowing the sign of the
571 constant the overflow behavior gets predictable. e.g.:
572 int a, b; if ((b = a + c) > 0)
573 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
574 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
575 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
576 {
577 if (INTVAL (XEXP((op0), 1)) < 0)
578 return CCANmode;
579 else
580 return CCAPmode;
581 }
582 /* Fall through. */
583 case UNORDERED:
584 case ORDERED:
585 case UNEQ:
586 case UNLE:
587 case UNLT:
588 case UNGE:
589 case UNGT:
590 case LTGT:
591 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
592 && GET_CODE (op1) != CONST_INT)
593 return CCSRmode;
594 return CCSmode;
595
596 case LTU:
597 case GEU:
598 if (GET_CODE (op0) == PLUS
599 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
600 return CCL1mode;
601
602 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
603 && GET_CODE (op1) != CONST_INT)
604 return CCURmode;
605 return CCUmode;
606
607 case LEU:
608 case GTU:
609 if (GET_CODE (op0) == MINUS
610 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
611 return CCL2mode;
612
613 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
614 && GET_CODE (op1) != CONST_INT)
615 return CCURmode;
616 return CCUmode;
617
618 default:
619 gcc_unreachable ();
620 }
621 }
622
623 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
624 that we can implement more efficiently. */
625
626 void
627 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
628 {
629 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
630 if ((*code == EQ || *code == NE)
631 && *op1 == const0_rtx
632 && GET_CODE (*op0) == ZERO_EXTRACT
633 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
634 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
635 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
636 {
637 rtx inner = XEXP (*op0, 0);
638 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
639 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
640 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
641
642 if (len > 0 && len < modesize
643 && pos >= 0 && pos + len <= modesize
644 && modesize <= HOST_BITS_PER_WIDE_INT)
645 {
646 unsigned HOST_WIDE_INT block;
647 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
648 block <<= modesize - pos - len;
649
650 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
651 gen_int_mode (block, GET_MODE (inner)));
652 }
653 }
654
655 /* Narrow AND of memory against immediate to enable TM. */
656 if ((*code == EQ || *code == NE)
657 && *op1 == const0_rtx
658 && GET_CODE (*op0) == AND
659 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
660 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
661 {
662 rtx inner = XEXP (*op0, 0);
663 rtx mask = XEXP (*op0, 1);
664
665 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
666 if (GET_CODE (inner) == SUBREG
667 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
668 && (GET_MODE_SIZE (GET_MODE (inner))
669 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
670 && ((INTVAL (mask)
671 & GET_MODE_MASK (GET_MODE (inner))
672 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
673 == 0))
674 inner = SUBREG_REG (inner);
675
676 /* Do not change volatile MEMs. */
677 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
678 {
679 int part = s390_single_part (XEXP (*op0, 1),
680 GET_MODE (inner), QImode, 0);
681 if (part >= 0)
682 {
683 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
684 inner = adjust_address_nv (inner, QImode, part);
685 *op0 = gen_rtx_AND (QImode, inner, mask);
686 }
687 }
688 }
689
690 /* Narrow comparisons against 0xffff to HImode if possible. */
691 if ((*code == EQ || *code == NE)
692 && GET_CODE (*op1) == CONST_INT
693 && INTVAL (*op1) == 0xffff
694 && SCALAR_INT_MODE_P (GET_MODE (*op0))
695 && (nonzero_bits (*op0, GET_MODE (*op0))
696 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
697 {
698 *op0 = gen_lowpart (HImode, *op0);
699 *op1 = constm1_rtx;
700 }
701
702
703 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
704 if (GET_CODE (*op0) == UNSPEC
705 && XINT (*op0, 1) == UNSPEC_CMPINT
706 && XVECLEN (*op0, 0) == 1
707 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
708 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
709 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
710 && *op1 == const0_rtx)
711 {
712 enum rtx_code new_code = UNKNOWN;
713 switch (*code)
714 {
715 case EQ: new_code = EQ; break;
716 case NE: new_code = NE; break;
717 case LT: new_code = GTU; break;
718 case GT: new_code = LTU; break;
719 case LE: new_code = GEU; break;
720 case GE: new_code = LEU; break;
721 default: break;
722 }
723
724 if (new_code != UNKNOWN)
725 {
726 *op0 = XVECEXP (*op0, 0, 0);
727 *code = new_code;
728 }
729 }
730
731 /* Simplify cascaded EQ, NE with const0_rtx. */
732 if ((*code == NE || *code == EQ)
733 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
734 && GET_MODE (*op0) == SImode
735 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
736 && REG_P (XEXP (*op0, 0))
737 && XEXP (*op0, 1) == const0_rtx
738 && *op1 == const0_rtx)
739 {
740 if ((*code == EQ && GET_CODE (*op0) == NE)
741 || (*code == NE && GET_CODE (*op0) == EQ))
742 *code = EQ;
743 else
744 *code = NE;
745 *op0 = XEXP (*op0, 0);
746 }
747
748 /* Prefer register over memory as first operand. */
749 if (MEM_P (*op0) && REG_P (*op1))
750 {
751 rtx tem = *op0; *op0 = *op1; *op1 = tem;
752 *code = swap_condition (*code);
753 }
754 }
755
756 /* Emit a compare instruction suitable to implement the comparison
757 OP0 CODE OP1. Return the correct condition RTL to be placed in
758 the IF_THEN_ELSE of the conditional branch testing the result. */
759
760 rtx
761 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
762 {
763 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
764 rtx ret = NULL_RTX;
765
766 /* Do not output a redundant compare instruction if a compare_and_swap
767 pattern already computed the result and the machine modes are compatible. */
768 if (s390_compare_emitted
769 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
770 == GET_MODE (s390_compare_emitted)))
771 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
772 else
773 {
774 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
775
776 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
777 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
778 }
779 s390_compare_emitted = NULL_RTX;
780 return ret;
781 }
782
783 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
784 unconditional jump, else a conditional jump under condition COND. */
785
786 void
787 s390_emit_jump (rtx target, rtx cond)
788 {
789 rtx insn;
790
791 target = gen_rtx_LABEL_REF (VOIDmode, target);
792 if (cond)
793 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
794
795 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
796 emit_jump_insn (insn);
797 }
798
799 /* Return branch condition mask to implement a branch
800 specified by CODE. Return -1 for invalid comparisons. */
801
802 int
803 s390_branch_condition_mask (rtx code)
804 {
805 const int CC0 = 1 << 3;
806 const int CC1 = 1 << 2;
807 const int CC2 = 1 << 1;
808 const int CC3 = 1 << 0;
809
810 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
811 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
812 gcc_assert (XEXP (code, 1) == const0_rtx);
813
814 switch (GET_MODE (XEXP (code, 0)))
815 {
816 case CCZmode:
817 case CCZ1mode:
818 switch (GET_CODE (code))
819 {
820 case EQ: return CC0;
821 case NE: return CC1 | CC2 | CC3;
822 default: return -1;
823 }
824 break;
825
826 case CCT1mode:
827 switch (GET_CODE (code))
828 {
829 case EQ: return CC1;
830 case NE: return CC0 | CC2 | CC3;
831 default: return -1;
832 }
833 break;
834
835 case CCT2mode:
836 switch (GET_CODE (code))
837 {
838 case EQ: return CC2;
839 case NE: return CC0 | CC1 | CC3;
840 default: return -1;
841 }
842 break;
843
844 case CCT3mode:
845 switch (GET_CODE (code))
846 {
847 case EQ: return CC3;
848 case NE: return CC0 | CC1 | CC2;
849 default: return -1;
850 }
851 break;
852
853 case CCLmode:
854 switch (GET_CODE (code))
855 {
856 case EQ: return CC0 | CC2;
857 case NE: return CC1 | CC3;
858 default: return -1;
859 }
860 break;
861
862 case CCL1mode:
863 switch (GET_CODE (code))
864 {
865 case LTU: return CC2 | CC3; /* carry */
866 case GEU: return CC0 | CC1; /* no carry */
867 default: return -1;
868 }
869 break;
870
871 case CCL2mode:
872 switch (GET_CODE (code))
873 {
874 case GTU: return CC0 | CC1; /* borrow */
875 case LEU: return CC2 | CC3; /* no borrow */
876 default: return -1;
877 }
878 break;
879
880 case CCL3mode:
881 switch (GET_CODE (code))
882 {
883 case EQ: return CC0 | CC2;
884 case NE: return CC1 | CC3;
885 case LTU: return CC1;
886 case GTU: return CC3;
887 case LEU: return CC1 | CC2;
888 case GEU: return CC2 | CC3;
889 default: return -1;
890 }
891
892 case CCUmode:
893 switch (GET_CODE (code))
894 {
895 case EQ: return CC0;
896 case NE: return CC1 | CC2 | CC3;
897 case LTU: return CC1;
898 case GTU: return CC2;
899 case LEU: return CC0 | CC1;
900 case GEU: return CC0 | CC2;
901 default: return -1;
902 }
903 break;
904
905 case CCURmode:
906 switch (GET_CODE (code))
907 {
908 case EQ: return CC0;
909 case NE: return CC2 | CC1 | CC3;
910 case LTU: return CC2;
911 case GTU: return CC1;
912 case LEU: return CC0 | CC2;
913 case GEU: return CC0 | CC1;
914 default: return -1;
915 }
916 break;
917
918 case CCAPmode:
919 switch (GET_CODE (code))
920 {
921 case EQ: return CC0;
922 case NE: return CC1 | CC2 | CC3;
923 case LT: return CC1 | CC3;
924 case GT: return CC2;
925 case LE: return CC0 | CC1 | CC3;
926 case GE: return CC0 | CC2;
927 default: return -1;
928 }
929 break;
930
931 case CCANmode:
932 switch (GET_CODE (code))
933 {
934 case EQ: return CC0;
935 case NE: return CC1 | CC2 | CC3;
936 case LT: return CC1;
937 case GT: return CC2 | CC3;
938 case LE: return CC0 | CC1;
939 case GE: return CC0 | CC2 | CC3;
940 default: return -1;
941 }
942 break;
943
944 case CCSmode:
945 switch (GET_CODE (code))
946 {
947 case EQ: return CC0;
948 case NE: return CC1 | CC2 | CC3;
949 case LT: return CC1;
950 case GT: return CC2;
951 case LE: return CC0 | CC1;
952 case GE: return CC0 | CC2;
953 case UNORDERED: return CC3;
954 case ORDERED: return CC0 | CC1 | CC2;
955 case UNEQ: return CC0 | CC3;
956 case UNLT: return CC1 | CC3;
957 case UNGT: return CC2 | CC3;
958 case UNLE: return CC0 | CC1 | CC3;
959 case UNGE: return CC0 | CC2 | CC3;
960 case LTGT: return CC1 | CC2;
961 default: return -1;
962 }
963 break;
964
965 case CCSRmode:
966 switch (GET_CODE (code))
967 {
968 case EQ: return CC0;
969 case NE: return CC2 | CC1 | CC3;
970 case LT: return CC2;
971 case GT: return CC1;
972 case LE: return CC0 | CC2;
973 case GE: return CC0 | CC1;
974 case UNORDERED: return CC3;
975 case ORDERED: return CC0 | CC2 | CC1;
976 case UNEQ: return CC0 | CC3;
977 case UNLT: return CC2 | CC3;
978 case UNGT: return CC1 | CC3;
979 case UNLE: return CC0 | CC2 | CC3;
980 case UNGE: return CC0 | CC1 | CC3;
981 case LTGT: return CC2 | CC1;
982 default: return -1;
983 }
984 break;
985
986 default:
987 return -1;
988 }
989 }
990
991 /* If INV is false, return assembler mnemonic string to implement
992 a branch specified by CODE. If INV is true, return mnemonic
993 for the corresponding inverted branch. */
994
995 static const char *
996 s390_branch_condition_mnemonic (rtx code, int inv)
997 {
998 static const char *const mnemonic[16] =
999 {
1000 NULL, "o", "h", "nle",
1001 "l", "nhe", "lh", "ne",
1002 "e", "nlh", "he", "nl",
1003 "le", "nh", "no", NULL
1004 };
1005
1006 int mask = s390_branch_condition_mask (code);
1007 gcc_assert (mask >= 0);
1008
1009 if (inv)
1010 mask ^= 15;
1011
1012 gcc_assert (mask >= 1 && mask <= 14);
1013
1014 return mnemonic[mask];
1015 }
1016
1017 /* Return the part of op which has a value different from def.
1018 The size of the part is determined by mode.
1019 Use this function only if you already know that op really
1020 contains such a part. */
1021
1022 unsigned HOST_WIDE_INT
1023 s390_extract_part (rtx op, enum machine_mode mode, int def)
1024 {
1025 unsigned HOST_WIDE_INT value = 0;
1026 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1027 int part_bits = GET_MODE_BITSIZE (mode);
1028 unsigned HOST_WIDE_INT part_mask
1029 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1030 int i;
1031
1032 for (i = 0; i < max_parts; i++)
1033 {
1034 if (i == 0)
1035 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1036 else
1037 value >>= part_bits;
1038
1039 if ((value & part_mask) != (def & part_mask))
1040 return value & part_mask;
1041 }
1042
1043 gcc_unreachable ();
1044 }
1045
1046 /* If OP is an integer constant of mode MODE with exactly one
1047 part of mode PART_MODE unequal to DEF, return the number of that
1048 part. Otherwise, return -1. */
1049
1050 int
1051 s390_single_part (rtx op,
1052 enum machine_mode mode,
1053 enum machine_mode part_mode,
1054 int def)
1055 {
1056 unsigned HOST_WIDE_INT value = 0;
1057 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1058 unsigned HOST_WIDE_INT part_mask
1059 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1060 int i, part = -1;
1061
1062 if (GET_CODE (op) != CONST_INT)
1063 return -1;
1064
1065 for (i = 0; i < n_parts; i++)
1066 {
1067 if (i == 0)
1068 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1069 else
1070 value >>= GET_MODE_BITSIZE (part_mode);
1071
1072 if ((value & part_mask) != (def & part_mask))
1073 {
1074 if (part != -1)
1075 return -1;
1076 else
1077 part = i;
1078 }
1079 }
1080 return part == -1 ? -1 : n_parts - 1 - part;
1081 }
1082
1083 /* Check whether we can (and want to) split a double-word
1084 move in mode MODE from SRC to DST into two single-word
1085 moves, moving the subword FIRST_SUBWORD first. */
1086
1087 bool
1088 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1089 {
1090 /* Floating point registers cannot be split. */
1091 if (FP_REG_P (src) || FP_REG_P (dst))
1092 return false;
1093
1094 /* We don't need to split if operands are directly accessible. */
1095 if (s_operand (src, mode) || s_operand (dst, mode))
1096 return false;
1097
1098 /* Non-offsettable memory references cannot be split. */
1099 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1100 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1101 return false;
1102
1103 /* Moving the first subword must not clobber a register
1104 needed to move the second subword. */
1105 if (register_operand (dst, mode))
1106 {
1107 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1108 if (reg_overlap_mentioned_p (subreg, src))
1109 return false;
1110 }
1111
1112 return true;
1113 }
1114
1115 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1116 and [MEM2, MEM2 + SIZE] do overlap and false
1117 otherwise. */
1118
1119 bool
1120 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1121 {
1122 rtx addr1, addr2, addr_delta;
1123 HOST_WIDE_INT delta;
1124
1125 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1126 return true;
1127
1128 if (size == 0)
1129 return false;
1130
1131 addr1 = XEXP (mem1, 0);
1132 addr2 = XEXP (mem2, 0);
1133
1134 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1135
1136 /* This overlapping check is used by peepholes merging memory block operations.
1137 Overlapping operations would otherwise be recognized by the S/390 hardware
1138 and would fall back to a slower implementation. Allowing overlapping
1139 operations would lead to slow code but not to wrong code. Therefore we are
1140 somewhat optimistic if we cannot prove that the memory blocks are
1141 overlapping.
1142 That's why we return false here although this may accept operations on
1143 overlapping memory areas. */
1144 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1145 return false;
1146
1147 delta = INTVAL (addr_delta);
1148
1149 if (delta == 0
1150 || (delta > 0 && delta < size)
1151 || (delta < 0 && -delta < size))
1152 return true;
1153
1154 return false;
1155 }
1156
1157 /* Check whether the address of memory reference MEM2 equals exactly
1158 the address of memory reference MEM1 plus DELTA. Return true if
1159 we can prove this to be the case, false otherwise. */
1160
1161 bool
1162 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1163 {
1164 rtx addr1, addr2, addr_delta;
1165
1166 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1167 return false;
1168
1169 addr1 = XEXP (mem1, 0);
1170 addr2 = XEXP (mem2, 0);
1171
1172 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1173 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1174 return false;
1175
1176 return true;
1177 }
1178
1179 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1180
1181 void
1182 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1183 rtx *operands)
1184 {
1185 enum machine_mode wmode = mode;
1186 rtx dst = operands[0];
1187 rtx src1 = operands[1];
1188 rtx src2 = operands[2];
1189 rtx op, clob, tem;
1190
1191 /* If we cannot handle the operation directly, use a temp register. */
1192 if (!s390_logical_operator_ok_p (operands))
1193 dst = gen_reg_rtx (mode);
1194
1195 /* QImode and HImode patterns make sense only if we have a destination
1196 in memory. Otherwise perform the operation in SImode. */
1197 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1198 wmode = SImode;
1199
1200 /* Widen operands if required. */
1201 if (mode != wmode)
1202 {
1203 if (GET_CODE (dst) == SUBREG
1204 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1205 dst = tem;
1206 else if (REG_P (dst))
1207 dst = gen_rtx_SUBREG (wmode, dst, 0);
1208 else
1209 dst = gen_reg_rtx (wmode);
1210
1211 if (GET_CODE (src1) == SUBREG
1212 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1213 src1 = tem;
1214 else if (GET_MODE (src1) != VOIDmode)
1215 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1216
1217 if (GET_CODE (src2) == SUBREG
1218 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1219 src2 = tem;
1220 else if (GET_MODE (src2) != VOIDmode)
1221 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1222 }
1223
1224 /* Emit the instruction. */
1225 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1226 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1227 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1228
1229 /* Fix up the destination if needed. */
1230 if (dst != operands[0])
1231 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1232 }
1233
1234 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1235
1236 bool
1237 s390_logical_operator_ok_p (rtx *operands)
1238 {
1239 /* If the destination operand is in memory, it needs to coincide
1240 with one of the source operands. After reload, it has to be
1241 the first source operand. */
1242 if (GET_CODE (operands[0]) == MEM)
1243 return rtx_equal_p (operands[0], operands[1])
1244 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1245
1246 return true;
1247 }
1248
1249 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1250 operand IMMOP to switch from SS to SI type instructions. */
1251
1252 void
1253 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1254 {
1255 int def = code == AND ? -1 : 0;
1256 HOST_WIDE_INT mask;
1257 int part;
1258
1259 gcc_assert (GET_CODE (*memop) == MEM);
1260 gcc_assert (!MEM_VOLATILE_P (*memop));
1261
1262 mask = s390_extract_part (*immop, QImode, def);
1263 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1264 gcc_assert (part >= 0);
1265
1266 *memop = adjust_address (*memop, QImode, part);
1267 *immop = gen_int_mode (mask, QImode);
1268 }
1269
1270
1271 /* How to allocate a 'struct machine_function'. */
1272
1273 static struct machine_function *
1274 s390_init_machine_status (void)
1275 {
1276 return ggc_alloc_cleared (sizeof (struct machine_function));
1277 }
1278
1279 /* Change optimizations to be performed, depending on the
1280 optimization level.
1281
1282 LEVEL is the optimization level specified; 2 if `-O2' is
1283 specified, 1 if `-O' is specified, and 0 if neither is specified.
1284
1285 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1286
1287 void
1288 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1289 {
1290 /* ??? There are apparently still problems with -fcaller-saves. */
1291 flag_caller_saves = 0;
1292
1293 /* By default, always emit DWARF-2 unwind info. This allows debugging
1294 without maintaining a stack frame back-chain. */
1295 flag_asynchronous_unwind_tables = 1;
1296
1297 /* Use MVCLE instructions to decrease code size if requested. */
1298 if (size != 0)
1299 target_flags |= MASK_MVCLE;
1300 }
1301
1302 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1303 to the associated processor_type and processor_flags if so. */
1304
1305 static bool
1306 s390_handle_arch_option (const char *arg,
1307 enum processor_type *type,
1308 enum processor_flags *flags)
1309 {
1310 static struct pta
1311 {
1312 const char *const name; /* processor name or nickname. */
1313 const enum processor_type processor;
1314 const enum processor_flags flags;
1315 }
1316 const processor_alias_table[] =
1317 {
1318 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1319 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1320 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1321 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1322 | PF_LONG_DISPLACEMENT},
1323 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1324 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1325 };
1326 size_t i;
1327
1328 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1329 if (strcmp (arg, processor_alias_table[i].name) == 0)
1330 {
1331 *type = processor_alias_table[i].processor;
1332 *flags = processor_alias_table[i].flags;
1333 return true;
1334 }
1335 return false;
1336 }
1337
1338 /* Implement TARGET_HANDLE_OPTION. */
1339
1340 static bool
1341 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1342 {
1343 switch (code)
1344 {
1345 case OPT_march_:
1346 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1347
1348 case OPT_mstack_guard_:
1349 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1350 return false;
1351 if (exact_log2 (s390_stack_guard) == -1)
1352 error ("stack guard value must be an exact power of 2");
1353 return true;
1354
1355 case OPT_mstack_size_:
1356 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1357 return false;
1358 if (exact_log2 (s390_stack_size) == -1)
1359 error ("stack size must be an exact power of 2");
1360 return true;
1361
1362 case OPT_mtune_:
1363 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1364
1365 case OPT_mwarn_framesize_:
1366 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1367
1368 default:
1369 return true;
1370 }
1371 }
1372
1373 void
1374 override_options (void)
1375 {
1376 /* Set up function hooks. */
1377 init_machine_status = s390_init_machine_status;
1378
1379 /* Architecture mode defaults according to ABI. */
1380 if (!(target_flags_explicit & MASK_ZARCH))
1381 {
1382 if (TARGET_64BIT)
1383 target_flags |= MASK_ZARCH;
1384 else
1385 target_flags &= ~MASK_ZARCH;
1386 }
1387
1388 /* Determine processor architectural level. */
1389 if (!s390_arch_string)
1390 {
1391 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1392 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1393 }
1394
1395 /* Determine processor to tune for. */
1396 if (s390_tune == PROCESSOR_max)
1397 {
1398 s390_tune = s390_arch;
1399 s390_tune_flags = s390_arch_flags;
1400 }
1401
1402 /* Sanity checks. */
1403 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1404 error ("z/Architecture mode not supported on %s", s390_arch_string);
1405 if (TARGET_64BIT && !TARGET_ZARCH)
1406 error ("64-bit ABI not supported in ESA/390 mode");
1407
1408 /* Set processor cost function. */
1409 if (s390_tune == PROCESSOR_2094_Z9_109)
1410 s390_cost = &z9_109_cost;
1411 else if (s390_tune == PROCESSOR_2084_Z990)
1412 s390_cost = &z990_cost;
1413 else
1414 s390_cost = &z900_cost;
1415
1416 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1417 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1418 "in combination");
1419
1420 if (s390_stack_size)
1421 {
1422 if (!s390_stack_guard)
1423 error ("-mstack-size implies use of -mstack-guard");
1424 else if (s390_stack_guard >= s390_stack_size)
1425 error ("stack size must be greater than the stack guard value");
1426 else if (s390_stack_size > 1 << 16)
1427 error ("stack size must not be greater than 64k");
1428 }
1429 else if (s390_stack_guard)
1430 error ("-mstack-guard implies use of -mstack-size");
1431
1432 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1433 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1434 target_flags |= MASK_LONG_DOUBLE_128;
1435 #endif
1436 }
1437
1438 /* Map for smallest class containing reg regno. */
1439
1440 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1441 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1442 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1443 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1444 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1445 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1446 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1447 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1448 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1449 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1450 ACCESS_REGS, ACCESS_REGS
1451 };
1452
1453 /* Return attribute type of insn. */
1454
1455 static enum attr_type
1456 s390_safe_attr_type (rtx insn)
1457 {
1458 if (recog_memoized (insn) >= 0)
1459 return get_attr_type (insn);
1460 else
1461 return TYPE_NONE;
1462 }
1463
1464 /* Return true if DISP is a valid short displacement. */
1465
1466 static bool
1467 s390_short_displacement (rtx disp)
1468 {
1469 /* No displacement is OK. */
1470 if (!disp)
1471 return true;
1472
1473 /* Integer displacement in range. */
1474 if (GET_CODE (disp) == CONST_INT)
1475 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1476
1477 /* GOT offset is not OK, the GOT can be large. */
1478 if (GET_CODE (disp) == CONST
1479 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1480 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1481 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1482 return false;
1483
1484 /* All other symbolic constants are literal pool references,
1485 which are OK as the literal pool must be small. */
1486 if (GET_CODE (disp) == CONST)
1487 return true;
1488
1489 return false;
1490 }
1491
1492 /* Decompose a RTL expression ADDR for a memory address into
1493 its components, returned in OUT.
1494
1495 Returns false if ADDR is not a valid memory address, true
1496 otherwise. If OUT is NULL, don't return the components,
1497 but check for validity only.
1498
1499 Note: Only addresses in canonical form are recognized.
1500 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1501 canonical form so that they will be recognized. */
1502
1503 static int
1504 s390_decompose_address (rtx addr, struct s390_address *out)
1505 {
1506 HOST_WIDE_INT offset = 0;
1507 rtx base = NULL_RTX;
1508 rtx indx = NULL_RTX;
1509 rtx disp = NULL_RTX;
1510 rtx orig_disp;
1511 bool pointer = false;
1512 bool base_ptr = false;
1513 bool indx_ptr = false;
1514 bool literal_pool = false;
1515
1516 /* We may need to substitute the literal pool base register into the address
1517 below. However, at this point we do not know which register is going to
1518 be used as base, so we substitute the arg pointer register. This is going
1519 to be treated as holding a pointer below -- it shouldn't be used for any
1520 other purpose. */
1521 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1522
1523 /* Decompose address into base + index + displacement. */
1524
1525 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1526 base = addr;
1527
1528 else if (GET_CODE (addr) == PLUS)
1529 {
1530 rtx op0 = XEXP (addr, 0);
1531 rtx op1 = XEXP (addr, 1);
1532 enum rtx_code code0 = GET_CODE (op0);
1533 enum rtx_code code1 = GET_CODE (op1);
1534
1535 if (code0 == REG || code0 == UNSPEC)
1536 {
1537 if (code1 == REG || code1 == UNSPEC)
1538 {
1539 indx = op0; /* index + base */
1540 base = op1;
1541 }
1542
1543 else
1544 {
1545 base = op0; /* base + displacement */
1546 disp = op1;
1547 }
1548 }
1549
1550 else if (code0 == PLUS)
1551 {
1552 indx = XEXP (op0, 0); /* index + base + disp */
1553 base = XEXP (op0, 1);
1554 disp = op1;
1555 }
1556
1557 else
1558 {
1559 return false;
1560 }
1561 }
1562
1563 else
1564 disp = addr; /* displacement */
1565
1566 /* Extract integer part of displacement. */
1567 orig_disp = disp;
1568 if (disp)
1569 {
1570 if (GET_CODE (disp) == CONST_INT)
1571 {
1572 offset = INTVAL (disp);
1573 disp = NULL_RTX;
1574 }
1575 else if (GET_CODE (disp) == CONST
1576 && GET_CODE (XEXP (disp, 0)) == PLUS
1577 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1578 {
1579 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1580 disp = XEXP (XEXP (disp, 0), 0);
1581 }
1582 }
1583
1584 /* Strip off CONST here to avoid special case tests later. */
1585 if (disp && GET_CODE (disp) == CONST)
1586 disp = XEXP (disp, 0);
1587
1588 /* We can convert literal pool addresses to
1589 displacements by basing them off the base register. */
1590 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1591 {
1592 /* Either base or index must be free to hold the base register. */
1593 if (!base)
1594 base = fake_pool_base, literal_pool = true;
1595 else if (!indx)
1596 indx = fake_pool_base, literal_pool = true;
1597 else
1598 return false;
1599
1600 /* Mark up the displacement. */
1601 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1602 UNSPEC_LTREL_OFFSET);
1603 }
1604
1605 /* Validate base register. */
1606 if (base)
1607 {
1608 if (GET_CODE (base) == UNSPEC)
1609 switch (XINT (base, 1))
1610 {
1611 case UNSPEC_LTREF:
1612 if (!disp)
1613 disp = gen_rtx_UNSPEC (Pmode,
1614 gen_rtvec (1, XVECEXP (base, 0, 0)),
1615 UNSPEC_LTREL_OFFSET);
1616 else
1617 return false;
1618
1619 base = XVECEXP (base, 0, 1);
1620 break;
1621
1622 case UNSPEC_LTREL_BASE:
1623 if (XVECLEN (base, 0) == 1)
1624 base = fake_pool_base, literal_pool = true;
1625 else
1626 base = XVECEXP (base, 0, 1);
1627 break;
1628
1629 default:
1630 return false;
1631 }
1632
1633 if (!REG_P (base)
1634 || (GET_MODE (base) != SImode
1635 && GET_MODE (base) != Pmode))
1636 return false;
1637
1638 if (REGNO (base) == STACK_POINTER_REGNUM
1639 || REGNO (base) == FRAME_POINTER_REGNUM
1640 || ((reload_completed || reload_in_progress)
1641 && frame_pointer_needed
1642 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1643 || REGNO (base) == ARG_POINTER_REGNUM
1644 || (flag_pic
1645 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1646 pointer = base_ptr = true;
1647
1648 if ((reload_completed || reload_in_progress)
1649 && base == cfun->machine->base_reg)
1650 pointer = base_ptr = literal_pool = true;
1651 }
1652
1653 /* Validate index register. */
1654 if (indx)
1655 {
1656 if (GET_CODE (indx) == UNSPEC)
1657 switch (XINT (indx, 1))
1658 {
1659 case UNSPEC_LTREF:
1660 if (!disp)
1661 disp = gen_rtx_UNSPEC (Pmode,
1662 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1663 UNSPEC_LTREL_OFFSET);
1664 else
1665 return false;
1666
1667 indx = XVECEXP (indx, 0, 1);
1668 break;
1669
1670 case UNSPEC_LTREL_BASE:
1671 if (XVECLEN (indx, 0) == 1)
1672 indx = fake_pool_base, literal_pool = true;
1673 else
1674 indx = XVECEXP (indx, 0, 1);
1675 break;
1676
1677 default:
1678 return false;
1679 }
1680
1681 if (!REG_P (indx)
1682 || (GET_MODE (indx) != SImode
1683 && GET_MODE (indx) != Pmode))
1684 return false;
1685
1686 if (REGNO (indx) == STACK_POINTER_REGNUM
1687 || REGNO (indx) == FRAME_POINTER_REGNUM
1688 || ((reload_completed || reload_in_progress)
1689 && frame_pointer_needed
1690 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1691 || REGNO (indx) == ARG_POINTER_REGNUM
1692 || (flag_pic
1693 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1694 pointer = indx_ptr = true;
1695
1696 if ((reload_completed || reload_in_progress)
1697 && indx == cfun->machine->base_reg)
1698 pointer = indx_ptr = literal_pool = true;
1699 }
1700
1701 /* Prefer to use pointer as base, not index. */
1702 if (base && indx && !base_ptr
1703 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1704 {
1705 rtx tmp = base;
1706 base = indx;
1707 indx = tmp;
1708 }
1709
1710 /* Validate displacement. */
1711 if (!disp)
1712 {
1713 /* If virtual registers are involved, the displacement will change later
1714 anyway as the virtual registers get eliminated. This could make a
1715 valid displacement invalid, but it is more likely to make an invalid
1716 displacement valid, because we sometimes access the register save area
1717 via negative offsets to one of those registers.
1718 Thus we don't check the displacement for validity here. If after
1719 elimination the displacement turns out to be invalid after all,
1720 this is fixed up by reload in any case. */
1721 if (base != arg_pointer_rtx
1722 && indx != arg_pointer_rtx
1723 && base != return_address_pointer_rtx
1724 && indx != return_address_pointer_rtx
1725 && base != frame_pointer_rtx
1726 && indx != frame_pointer_rtx
1727 && base != virtual_stack_vars_rtx
1728 && indx != virtual_stack_vars_rtx)
1729 if (!DISP_IN_RANGE (offset))
1730 return false;
1731 }
1732 else
1733 {
1734 /* All the special cases are pointers. */
1735 pointer = true;
1736
1737 /* In the small-PIC case, the linker converts @GOT
1738 and @GOTNTPOFF offsets to possible displacements. */
1739 if (GET_CODE (disp) == UNSPEC
1740 && (XINT (disp, 1) == UNSPEC_GOT
1741 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1742 && offset == 0
1743 && flag_pic == 1)
1744 {
1745 ;
1746 }
1747
1748 /* Accept chunkified literal pool symbol references. */
1749 else if (cfun && cfun->machine
1750 && cfun->machine->decomposed_literal_pool_addresses_ok_p
1751 && GET_CODE (disp) == MINUS
1752 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1753 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1754 {
1755 ;
1756 }
1757
1758 /* Accept literal pool references. */
1759 else if (GET_CODE (disp) == UNSPEC
1760 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1761 {
1762 orig_disp = gen_rtx_CONST (Pmode, disp);
1763 if (offset)
1764 {
1765 /* If we have an offset, make sure it does not
1766 exceed the size of the constant pool entry. */
1767 rtx sym = XVECEXP (disp, 0, 0);
1768 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1769 return false;
1770
1771 orig_disp = plus_constant (orig_disp, offset);
1772 }
1773 }
1774
1775 else
1776 return false;
1777 }
1778
1779 if (!base && !indx)
1780 pointer = true;
1781
1782 if (out)
1783 {
1784 out->base = base;
1785 out->indx = indx;
1786 out->disp = orig_disp;
1787 out->pointer = pointer;
1788 out->literal_pool = literal_pool;
1789 }
1790
1791 return true;
1792 }
1793
1794 /* Decompose a RTL expression OP for a shift count into its components,
1795 and return the base register in BASE and the offset in OFFSET.
1796
1797 Return true if OP is a valid shift count, false if not. */
1798
1799 bool
1800 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1801 {
1802 HOST_WIDE_INT off = 0;
1803
1804 /* We can have an integer constant, an address register,
1805 or a sum of the two. */
1806 if (GET_CODE (op) == CONST_INT)
1807 {
1808 off = INTVAL (op);
1809 op = NULL_RTX;
1810 }
1811 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1812 {
1813 off = INTVAL (XEXP (op, 1));
1814 op = XEXP (op, 0);
1815 }
1816 while (op && GET_CODE (op) == SUBREG)
1817 op = SUBREG_REG (op);
1818
1819 if (op && GET_CODE (op) != REG)
1820 return false;
1821
1822 if (offset)
1823 *offset = off;
1824 if (base)
1825 *base = op;
1826
1827 return true;
1828 }
1829
1830
1831 /* Return true if CODE is a valid address without index. */
1832
1833 bool
1834 s390_legitimate_address_without_index_p (rtx op)
1835 {
1836 struct s390_address addr;
1837
1838 if (!s390_decompose_address (XEXP (op, 0), &addr))
1839 return false;
1840 if (addr.indx)
1841 return false;
1842
1843 return true;
1844 }
1845
1846 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1847
1848 int
1849 s390_extra_constraint_str (rtx op, int c, const char * str)
1850 {
1851 struct s390_address addr;
1852
1853 gcc_assert (c == str[0]);
1854
1855 /* Check for offsettable variants of memory constraints. */
1856 if (c == 'A')
1857 {
1858 /* Only accept non-volatile MEMs. */
1859 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1860 return 0;
1861
1862 if ((reload_completed || reload_in_progress)
1863 ? !offsettable_memref_p (op)
1864 : !offsettable_nonstrict_memref_p (op))
1865 return 0;
1866
1867 c = str[1];
1868 }
1869
1870 /* Check for non-literal-pool variants of memory constraints. */
1871 else if (c == 'B')
1872 {
1873 if (GET_CODE (op) != MEM)
1874 return 0;
1875 if (!s390_decompose_address (XEXP (op, 0), &addr))
1876 return 0;
1877 if (addr.literal_pool)
1878 return 0;
1879
1880 c = str[1];
1881 }
1882
1883 switch (c)
1884 {
1885 case 'Q':
1886 if (GET_CODE (op) != MEM)
1887 return 0;
1888 if (!s390_decompose_address (XEXP (op, 0), &addr))
1889 return 0;
1890 if (addr.indx)
1891 return 0;
1892
1893 if (TARGET_LONG_DISPLACEMENT)
1894 {
1895 if (!s390_short_displacement (addr.disp))
1896 return 0;
1897 }
1898 break;
1899
1900 case 'R':
1901 if (GET_CODE (op) != MEM)
1902 return 0;
1903
1904 if (TARGET_LONG_DISPLACEMENT)
1905 {
1906 if (!s390_decompose_address (XEXP (op, 0), &addr))
1907 return 0;
1908 if (!s390_short_displacement (addr.disp))
1909 return 0;
1910 }
1911 break;
1912
1913 case 'S':
1914 if (!TARGET_LONG_DISPLACEMENT)
1915 return 0;
1916 if (GET_CODE (op) != MEM)
1917 return 0;
1918 if (!s390_decompose_address (XEXP (op, 0), &addr))
1919 return 0;
1920 if (addr.indx)
1921 return 0;
1922 if (s390_short_displacement (addr.disp))
1923 return 0;
1924 break;
1925
1926 case 'T':
1927 if (!TARGET_LONG_DISPLACEMENT)
1928 return 0;
1929 if (GET_CODE (op) != MEM)
1930 return 0;
1931 /* Any invalid address here will be fixed up by reload,
1932 so accept it for the most generic constraint. */
1933 if (s390_decompose_address (XEXP (op, 0), &addr)
1934 && s390_short_displacement (addr.disp))
1935 return 0;
1936 break;
1937
1938 case 'U':
1939 if (TARGET_LONG_DISPLACEMENT)
1940 {
1941 if (!s390_decompose_address (op, &addr))
1942 return 0;
1943 if (!s390_short_displacement (addr.disp))
1944 return 0;
1945 }
1946 break;
1947
1948 case 'W':
1949 if (!TARGET_LONG_DISPLACEMENT)
1950 return 0;
1951 /* Any invalid address here will be fixed up by reload,
1952 so accept it for the most generic constraint. */
1953 if (s390_decompose_address (op, &addr)
1954 && s390_short_displacement (addr.disp))
1955 return 0;
1956 break;
1957
1958 case 'Y':
1959 /* Simply check for the basic form of a shift count. Reload will
1960 take care of making sure we have a proper base register. */
1961 if (!s390_decompose_shift_count (op, NULL, NULL))
1962 return 0;
1963 break;
1964
1965 default:
1966 return 0;
1967 }
1968
1969 return 1;
1970 }
1971
1972 /* Return true if VALUE matches the constraint STR. */
1973
1974 int
1975 s390_const_double_ok_for_constraint_p (rtx value,
1976 int c,
1977 const char * str)
1978 {
1979 gcc_assert (c == str[0]);
1980
1981 switch (str[0])
1982 {
1983 case 'G':
1984 /* The floating point zero constant. */
1985 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1986 && value == CONST0_RTX (GET_MODE (value)));
1987
1988 default:
1989 return 0;
1990 }
1991 }
1992
1993 /* Return true if VALUE matches the constraint STR. */
1994
1995 int
1996 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1997 int c,
1998 const char * str)
1999 {
2000 enum machine_mode mode, part_mode;
2001 int def;
2002 int part, part_goal;
2003
2004 gcc_assert (c == str[0]);
2005
2006 switch (str[0])
2007 {
2008 case 'I':
2009 return (unsigned int)value < 256;
2010
2011 case 'J':
2012 return (unsigned int)value < 4096;
2013
2014 case 'K':
2015 return value >= -32768 && value < 32768;
2016
2017 case 'L':
2018 return (TARGET_LONG_DISPLACEMENT ?
2019 (value >= -524288 && value <= 524287)
2020 : (value >= 0 && value <= 4095));
2021 case 'M':
2022 return value == 2147483647;
2023
2024 case 'N':
2025 if (str[1] == 'x')
2026 part_goal = -1;
2027 else
2028 part_goal = str[1] - '0';
2029
2030 switch (str[2])
2031 {
2032 case 'Q': part_mode = QImode; break;
2033 case 'H': part_mode = HImode; break;
2034 case 'S': part_mode = SImode; break;
2035 default: return 0;
2036 }
2037
2038 switch (str[3])
2039 {
2040 case 'H': mode = HImode; break;
2041 case 'S': mode = SImode; break;
2042 case 'D': mode = DImode; break;
2043 default: return 0;
2044 }
2045
2046 switch (str[4])
2047 {
2048 case '0': def = 0; break;
2049 case 'F': def = -1; break;
2050 default: return 0;
2051 }
2052
2053 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2054 return 0;
2055
2056 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2057 if (part < 0)
2058 return 0;
2059 if (part_goal != -1 && part_goal != part)
2060 return 0;
2061
2062 break;
2063
2064 case 'O':
2065 if (!TARGET_EXTIMM)
2066 return 0;
2067
2068 switch (str[1])
2069 {
2070 case 's':
2071 return trunc_int_for_mode (value, SImode) == value;
2072
2073 case 'p':
2074 return value == 0
2075 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2076
2077 case 'n':
2078 return value == -1
2079 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
2080
2081 default:
2082 gcc_unreachable ();
2083 }
2084 break;
2085
2086 case 'P':
2087 return legitimate_reload_constant_p (GEN_INT (value));
2088
2089 default:
2090 return 0;
2091 }
2092
2093 return 1;
2094 }
2095
2096 /* Compute a (partial) cost for rtx X. Return true if the complete
2097 cost has been computed, and false if subexpressions should be
2098 scanned. In either case, *TOTAL contains the cost result.
2099 CODE contains GET_CODE (x), OUTER_CODE contains the code
2100 of the superexpression of x. */
2101
2102 static bool
2103 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2104 {
2105 switch (code)
2106 {
2107 case CONST:
2108 case CONST_INT:
2109 case LABEL_REF:
2110 case SYMBOL_REF:
2111 case CONST_DOUBLE:
2112 case MEM:
2113 *total = 0;
2114 return true;
2115
2116 case ASHIFT:
2117 case ASHIFTRT:
2118 case LSHIFTRT:
2119 case ROTATE:
2120 case ROTATERT:
2121 case AND:
2122 case IOR:
2123 case XOR:
2124 case NEG:
2125 case NOT:
2126 *total = COSTS_N_INSNS (1);
2127 return false;
2128
2129 case PLUS:
2130 case MINUS:
2131 /* Check for multiply and add. */
2132 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2133 && GET_CODE (XEXP (x, 0)) == MULT
2134 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2135 {
2136 /* This is the multiply and add case. */
2137 if (GET_MODE (x) == DFmode)
2138 *total = s390_cost->madbr;
2139 else
2140 *total = s390_cost->maebr;
2141 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2142 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2143 + rtx_cost (XEXP (x, 1), code);
2144 return true; /* Do not do an additional recursive descent. */
2145 }
2146 *total = COSTS_N_INSNS (1);
2147 return false;
2148
2149 case MULT:
2150 switch (GET_MODE (x))
2151 {
2152 case SImode:
2153 {
2154 rtx left = XEXP (x, 0);
2155 rtx right = XEXP (x, 1);
2156 if (GET_CODE (right) == CONST_INT
2157 && CONST_OK_FOR_K (INTVAL (right)))
2158 *total = s390_cost->mhi;
2159 else if (GET_CODE (left) == SIGN_EXTEND)
2160 *total = s390_cost->mh;
2161 else
2162 *total = s390_cost->ms; /* msr, ms, msy */
2163 break;
2164 }
2165 case DImode:
2166 {
2167 rtx left = XEXP (x, 0);
2168 rtx right = XEXP (x, 1);
2169 if (TARGET_64BIT)
2170 {
2171 if (GET_CODE (right) == CONST_INT
2172 && CONST_OK_FOR_K (INTVAL (right)))
2173 *total = s390_cost->mghi;
2174 else if (GET_CODE (left) == SIGN_EXTEND)
2175 *total = s390_cost->msgf;
2176 else
2177 *total = s390_cost->msg; /* msgr, msg */
2178 }
2179 else /* TARGET_31BIT */
2180 {
2181 if (GET_CODE (left) == SIGN_EXTEND
2182 && GET_CODE (right) == SIGN_EXTEND)
2183 /* mulsidi case: mr, m */
2184 *total = s390_cost->m;
2185 else if (GET_CODE (left) == ZERO_EXTEND
2186 && GET_CODE (right) == ZERO_EXTEND
2187 && TARGET_CPU_ZARCH)
2188 /* umulsidi case: ml, mlr */
2189 *total = s390_cost->ml;
2190 else
2191 /* Complex calculation is required. */
2192 *total = COSTS_N_INSNS (40);
2193 }
2194 break;
2195 }
2196 case SFmode:
2197 case DFmode:
2198 *total = s390_cost->mult_df;
2199 break;
2200 case TFmode:
2201 *total = s390_cost->mxbr;
2202 break;
2203 default:
2204 return false;
2205 }
2206 return false;
2207
2208 case UDIV:
2209 case UMOD:
2210 if (GET_MODE (x) == TImode) /* 128 bit division */
2211 *total = s390_cost->dlgr;
2212 else if (GET_MODE (x) == DImode)
2213 {
2214 rtx right = XEXP (x, 1);
2215 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2216 *total = s390_cost->dlr;
2217 else /* 64 by 64 bit division */
2218 *total = s390_cost->dlgr;
2219 }
2220 else if (GET_MODE (x) == SImode) /* 32 bit division */
2221 *total = s390_cost->dlr;
2222 return false;
2223
2224 case DIV:
2225 case MOD:
2226 if (GET_MODE (x) == DImode)
2227 {
2228 rtx right = XEXP (x, 1);
2229 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2230 if (TARGET_64BIT)
2231 *total = s390_cost->dsgfr;
2232 else
2233 *total = s390_cost->dr;
2234 else /* 64 by 64 bit division */
2235 *total = s390_cost->dsgr;
2236 }
2237 else if (GET_MODE (x) == SImode) /* 32 bit division */
2238 *total = s390_cost->dlr;
2239 else if (GET_MODE (x) == SFmode)
2240 {
2241 if (TARGET_IEEE_FLOAT)
2242 *total = s390_cost->debr;
2243 else /* TARGET_IBM_FLOAT */
2244 *total = s390_cost->der;
2245 }
2246 else if (GET_MODE (x) == DFmode)
2247 {
2248 if (TARGET_IEEE_FLOAT)
2249 *total = s390_cost->ddbr;
2250 else /* TARGET_IBM_FLOAT */
2251 *total = s390_cost->ddr;
2252 }
2253 else if (GET_MODE (x) == TFmode)
2254 {
2255 if (TARGET_IEEE_FLOAT)
2256 *total = s390_cost->dxbr;
2257 else /* TARGET_IBM_FLOAT */
2258 *total = s390_cost->dxr;
2259 }
2260 return false;
2261
2262 case SQRT:
2263 if (GET_MODE (x) == SFmode)
2264 *total = s390_cost->sqebr;
2265 else if (GET_MODE (x) == DFmode)
2266 *total = s390_cost->sqdbr;
2267 else /* TFmode */
2268 *total = s390_cost->sqxbr;
2269 return false;
2270
2271 case SIGN_EXTEND:
2272 case ZERO_EXTEND:
2273 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2274 || outer_code == PLUS || outer_code == MINUS
2275 || outer_code == COMPARE)
2276 *total = 0;
2277 return false;
2278
2279 case COMPARE:
2280 *total = COSTS_N_INSNS (1);
2281 if (GET_CODE (XEXP (x, 0)) == AND
2282 && GET_CODE (XEXP (x, 1)) == CONST_INT
2283 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2284 {
2285 rtx op0 = XEXP (XEXP (x, 0), 0);
2286 rtx op1 = XEXP (XEXP (x, 0), 1);
2287 rtx op2 = XEXP (x, 1);
2288
2289 if (memory_operand (op0, GET_MODE (op0))
2290 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2291 return true;
2292 if (register_operand (op0, GET_MODE (op0))
2293 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2294 return true;
2295 }
2296 return false;
2297
2298 default:
2299 return false;
2300 }
2301 }
2302
2303 /* Return the cost of an address rtx ADDR. */
2304
2305 static int
2306 s390_address_cost (rtx addr)
2307 {
2308 struct s390_address ad;
2309 if (!s390_decompose_address (addr, &ad))
2310 return 1000;
2311
2312 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2313 }
2314
2315 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2316 otherwise return 0. */
2317
2318 int
2319 tls_symbolic_operand (rtx op)
2320 {
2321 if (GET_CODE (op) != SYMBOL_REF)
2322 return 0;
2323 return SYMBOL_REF_TLS_MODEL (op);
2324 }
2325 \f
2326 /* Split DImode access register reference REG (on 64-bit) into its constituent
2327 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2328 gen_highpart cannot be used as they assume all registers are word-sized,
2329 while our access registers have only half that size. */
2330
2331 void
2332 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2333 {
2334 gcc_assert (TARGET_64BIT);
2335 gcc_assert (ACCESS_REG_P (reg));
2336 gcc_assert (GET_MODE (reg) == DImode);
2337 gcc_assert (!(REGNO (reg) & 1));
2338
2339 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2340 *hi = gen_rtx_REG (SImode, REGNO (reg));
2341 }
2342
2343 /* Return true if OP contains a symbol reference */
2344
2345 bool
2346 symbolic_reference_mentioned_p (rtx op)
2347 {
2348 const char *fmt;
2349 int i;
2350
2351 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2352 return 1;
2353
2354 fmt = GET_RTX_FORMAT (GET_CODE (op));
2355 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2356 {
2357 if (fmt[i] == 'E')
2358 {
2359 int j;
2360
2361 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2362 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2363 return 1;
2364 }
2365
2366 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2367 return 1;
2368 }
2369
2370 return 0;
2371 }
2372
2373 /* Return true if OP contains a reference to a thread-local symbol. */
2374
2375 bool
2376 tls_symbolic_reference_mentioned_p (rtx op)
2377 {
2378 const char *fmt;
2379 int i;
2380
2381 if (GET_CODE (op) == SYMBOL_REF)
2382 return tls_symbolic_operand (op);
2383
2384 fmt = GET_RTX_FORMAT (GET_CODE (op));
2385 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2386 {
2387 if (fmt[i] == 'E')
2388 {
2389 int j;
2390
2391 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2392 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2393 return true;
2394 }
2395
2396 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2397 return true;
2398 }
2399
2400 return false;
2401 }
2402
2403
2404 /* Return true if OP is a legitimate general operand when
2405 generating PIC code. It is given that flag_pic is on
2406 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2407
2408 int
2409 legitimate_pic_operand_p (rtx op)
2410 {
2411 /* Accept all non-symbolic constants. */
2412 if (!SYMBOLIC_CONST (op))
2413 return 1;
2414
2415 /* Reject everything else; must be handled
2416 via emit_symbolic_move. */
2417 return 0;
2418 }
2419
2420 /* Returns true if the constant value OP is a legitimate general operand.
2421 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2422
2423 int
2424 legitimate_constant_p (rtx op)
2425 {
2426 /* Accept all non-symbolic constants. */
2427 if (!SYMBOLIC_CONST (op))
2428 return 1;
2429
2430 /* Accept immediate LARL operands. */
2431 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2432 return 1;
2433
2434 /* Thread-local symbols are never legal constants. This is
2435 so that emit_call knows that computing such addresses
2436 might require a function call. */
2437 if (TLS_SYMBOLIC_CONST (op))
2438 return 0;
2439
2440 /* In the PIC case, symbolic constants must *not* be
2441 forced into the literal pool. We accept them here,
2442 so that they will be handled by emit_symbolic_move. */
2443 if (flag_pic)
2444 return 1;
2445
2446 /* All remaining non-PIC symbolic constants are
2447 forced into the literal pool. */
2448 return 0;
2449 }
2450
2451 /* Determine if it's legal to put X into the constant pool. This
2452 is not possible if X contains the address of a symbol that is
2453 not constant (TLS) or not known at final link time (PIC). */
2454
2455 static bool
2456 s390_cannot_force_const_mem (rtx x)
2457 {
2458 switch (GET_CODE (x))
2459 {
2460 case CONST_INT:
2461 case CONST_DOUBLE:
2462 /* Accept all non-symbolic constants. */
2463 return false;
2464
2465 case LABEL_REF:
2466 /* Labels are OK iff we are non-PIC. */
2467 return flag_pic != 0;
2468
2469 case SYMBOL_REF:
2470 /* 'Naked' TLS symbol references are never OK,
2471 non-TLS symbols are OK iff we are non-PIC. */
2472 if (tls_symbolic_operand (x))
2473 return true;
2474 else
2475 return flag_pic != 0;
2476
2477 case CONST:
2478 return s390_cannot_force_const_mem (XEXP (x, 0));
2479 case PLUS:
2480 case MINUS:
2481 return s390_cannot_force_const_mem (XEXP (x, 0))
2482 || s390_cannot_force_const_mem (XEXP (x, 1));
2483
2484 case UNSPEC:
2485 switch (XINT (x, 1))
2486 {
2487 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2488 case UNSPEC_LTREL_OFFSET:
2489 case UNSPEC_GOT:
2490 case UNSPEC_GOTOFF:
2491 case UNSPEC_PLTOFF:
2492 case UNSPEC_TLSGD:
2493 case UNSPEC_TLSLDM:
2494 case UNSPEC_NTPOFF:
2495 case UNSPEC_DTPOFF:
2496 case UNSPEC_GOTNTPOFF:
2497 case UNSPEC_INDNTPOFF:
2498 return false;
2499
2500 /* If the literal pool shares the code section, be put
2501 execute template placeholders into the pool as well. */
2502 case UNSPEC_INSN:
2503 return TARGET_CPU_ZARCH;
2504
2505 default:
2506 return true;
2507 }
2508 break;
2509
2510 default:
2511 gcc_unreachable ();
2512 }
2513 }
2514
2515 /* Returns true if the constant value OP is a legitimate general
2516 operand during and after reload. The difference to
2517 legitimate_constant_p is that this function will not accept
2518 a constant that would need to be forced to the literal pool
2519 before it can be used as operand. */
2520
2521 bool
2522 legitimate_reload_constant_p (rtx op)
2523 {
2524 /* Accept la(y) operands. */
2525 if (GET_CODE (op) == CONST_INT
2526 && DISP_IN_RANGE (INTVAL (op)))
2527 return true;
2528
2529 /* Accept l(g)hi/l(g)fi operands. */
2530 if (GET_CODE (op) == CONST_INT
2531 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2532 return true;
2533
2534 /* Accept lliXX operands. */
2535 if (TARGET_ZARCH
2536 && GET_CODE (op) == CONST_INT
2537 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2538 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2539 return true;
2540
2541 if (TARGET_EXTIMM
2542 && GET_CODE (op) == CONST_INT
2543 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2544 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2545 return true;
2546
2547 /* Accept larl operands. */
2548 if (TARGET_CPU_ZARCH
2549 && larl_operand (op, VOIDmode))
2550 return true;
2551
2552 /* Accept lzXX operands. */
2553 if (GET_CODE (op) == CONST_DOUBLE
2554 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2555 return true;
2556
2557 /* Accept double-word operands that can be split. */
2558 if (GET_CODE (op) == CONST_INT
2559 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2560 {
2561 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2562 rtx hi = operand_subword (op, 0, 0, dword_mode);
2563 rtx lo = operand_subword (op, 1, 0, dword_mode);
2564 return legitimate_reload_constant_p (hi)
2565 && legitimate_reload_constant_p (lo);
2566 }
2567
2568 /* Everything else cannot be handled without reload. */
2569 return false;
2570 }
2571
2572 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2573 return the class of reg to actually use. */
2574
2575 enum reg_class
2576 s390_preferred_reload_class (rtx op, enum reg_class class)
2577 {
2578 switch (GET_CODE (op))
2579 {
2580 /* Constants we cannot reload must be forced into the
2581 literal pool. */
2582
2583 case CONST_DOUBLE:
2584 case CONST_INT:
2585 if (legitimate_reload_constant_p (op))
2586 return class;
2587 else
2588 return NO_REGS;
2589
2590 /* If a symbolic constant or a PLUS is reloaded,
2591 it is most likely being used as an address, so
2592 prefer ADDR_REGS. If 'class' is not a superset
2593 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2594 case PLUS:
2595 case LABEL_REF:
2596 case SYMBOL_REF:
2597 case CONST:
2598 if (reg_class_subset_p (ADDR_REGS, class))
2599 return ADDR_REGS;
2600 else
2601 return NO_REGS;
2602
2603 default:
2604 break;
2605 }
2606
2607 return class;
2608 }
2609
2610 /* Return the register class of a scratch register needed to
2611 load IN into a register of class CLASS in MODE.
2612
2613 We need a temporary when loading a PLUS expression which
2614 is not a legitimate operand of the LOAD ADDRESS instruction. */
2615
2616 enum reg_class
2617 s390_secondary_input_reload_class (enum reg_class class,
2618 enum machine_mode mode, rtx in)
2619 {
2620 if (s390_plus_operand (in, mode))
2621 return ADDR_REGS;
2622
2623 if (reg_classes_intersect_p (FP_REGS, class)
2624 && mode == TFmode
2625 && GET_CODE (in) == MEM
2626 && GET_CODE (XEXP (in, 0)) == PLUS
2627 && GET_CODE (XEXP (XEXP (in, 0), 1)) == CONST_INT
2628 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (in, 0), 1))
2629 + GET_MODE_SIZE (mode) - 1))
2630 return ADDR_REGS;
2631
2632 if (reg_classes_intersect_p (CC_REGS, class))
2633 return GENERAL_REGS;
2634
2635 return NO_REGS;
2636 }
2637
2638 /* Return the register class of a scratch register needed to
2639 store a register of class CLASS in MODE into OUT:
2640
2641 We need a temporary when storing a double-word to a
2642 non-offsettable memory address. */
2643
2644 enum reg_class
2645 s390_secondary_output_reload_class (enum reg_class class,
2646 enum machine_mode mode, rtx out)
2647 {
2648 if ((TARGET_64BIT ? (mode == TImode || mode == TFmode)
2649 : (mode == DImode || mode == DFmode))
2650 && reg_classes_intersect_p (GENERAL_REGS, class)
2651 && GET_CODE (out) == MEM
2652 && GET_CODE (XEXP (out, 0)) == PLUS
2653 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2654 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2655 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2656 + GET_MODE_SIZE (mode) - 1))
2657 return ADDR_REGS;
2658
2659 if (reg_classes_intersect_p (FP_REGS, class)
2660 && mode == TFmode
2661 && GET_CODE (out) == MEM
2662 && GET_CODE (XEXP (out, 0)) == PLUS
2663 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2664 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2665 + GET_MODE_SIZE (mode) - 1))
2666 return ADDR_REGS;
2667
2668 if (reg_classes_intersect_p (CC_REGS, class))
2669 return GENERAL_REGS;
2670
2671 return NO_REGS;
2672 }
2673
2674 /* Generate code to load SRC, which is PLUS that is not a
2675 legitimate operand for the LA instruction, into TARGET.
2676 SCRATCH may be used as scratch register. */
2677
2678 void
2679 s390_expand_plus_operand (rtx target, rtx src,
2680 rtx scratch)
2681 {
2682 rtx sum1, sum2;
2683 struct s390_address ad;
2684
2685 /* src must be a PLUS; get its two operands. */
2686 gcc_assert (GET_CODE (src) == PLUS);
2687 gcc_assert (GET_MODE (src) == Pmode);
2688
2689 /* Check if any of the two operands is already scheduled
2690 for replacement by reload. This can happen e.g. when
2691 float registers occur in an address. */
2692 sum1 = find_replacement (&XEXP (src, 0));
2693 sum2 = find_replacement (&XEXP (src, 1));
2694 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2695
2696 /* If the address is already strictly valid, there's nothing to do. */
2697 if (!s390_decompose_address (src, &ad)
2698 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2699 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
2700 {
2701 /* Otherwise, one of the operands cannot be an address register;
2702 we reload its value into the scratch register. */
2703 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2704 {
2705 emit_move_insn (scratch, sum1);
2706 sum1 = scratch;
2707 }
2708 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2709 {
2710 emit_move_insn (scratch, sum2);
2711 sum2 = scratch;
2712 }
2713
2714 /* According to the way these invalid addresses are generated
2715 in reload.c, it should never happen (at least on s390) that
2716 *neither* of the PLUS components, after find_replacements
2717 was applied, is an address register. */
2718 if (sum1 == scratch && sum2 == scratch)
2719 {
2720 debug_rtx (src);
2721 gcc_unreachable ();
2722 }
2723
2724 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2725 }
2726
2727 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2728 is only ever performed on addresses, so we can mark the
2729 sum as legitimate for LA in any case. */
2730 s390_load_address (target, src);
2731 }
2732
2733
2734 /* Return true if ADDR is a valid memory address.
2735 STRICT specifies whether strict register checking applies. */
2736
2737 bool
2738 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2739 rtx addr, int strict)
2740 {
2741 struct s390_address ad;
2742 if (!s390_decompose_address (addr, &ad))
2743 return false;
2744
2745 if (strict)
2746 {
2747 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2748 return false;
2749
2750 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
2751 return false;
2752 }
2753 else
2754 {
2755 if (ad.base
2756 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
2757 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
2758 return false;
2759
2760 if (ad.indx
2761 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
2762 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
2763 return false;
2764 }
2765 return true;
2766 }
2767
2768 /* Return true if OP is a valid operand for the LA instruction.
2769 In 31-bit, we need to prove that the result is used as an
2770 address, as LA performs only a 31-bit addition. */
2771
2772 bool
2773 legitimate_la_operand_p (rtx op)
2774 {
2775 struct s390_address addr;
2776 if (!s390_decompose_address (op, &addr))
2777 return false;
2778
2779 return (TARGET_64BIT || addr.pointer);
2780 }
2781
2782 /* Return true if it is valid *and* preferable to use LA to
2783 compute the sum of OP1 and OP2. */
2784
2785 bool
2786 preferred_la_operand_p (rtx op1, rtx op2)
2787 {
2788 struct s390_address addr;
2789
2790 if (op2 != const0_rtx)
2791 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2792
2793 if (!s390_decompose_address (op1, &addr))
2794 return false;
2795 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
2796 return false;
2797 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
2798 return false;
2799
2800 if (!TARGET_64BIT && !addr.pointer)
2801 return false;
2802
2803 if (addr.pointer)
2804 return true;
2805
2806 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2807 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2808 return true;
2809
2810 return false;
2811 }
2812
2813 /* Emit a forced load-address operation to load SRC into DST.
2814 This will use the LOAD ADDRESS instruction even in situations
2815 where legitimate_la_operand_p (SRC) returns false. */
2816
2817 void
2818 s390_load_address (rtx dst, rtx src)
2819 {
2820 if (TARGET_64BIT)
2821 emit_move_insn (dst, src);
2822 else
2823 emit_insn (gen_force_la_31 (dst, src));
2824 }
2825
2826 /* Return a legitimate reference for ORIG (an address) using the
2827 register REG. If REG is 0, a new pseudo is generated.
2828
2829 There are two types of references that must be handled:
2830
2831 1. Global data references must load the address from the GOT, via
2832 the PIC reg. An insn is emitted to do this load, and the reg is
2833 returned.
2834
2835 2. Static data references, constant pool addresses, and code labels
2836 compute the address as an offset from the GOT, whose base is in
2837 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2838 differentiate them from global data objects. The returned
2839 address is the PIC reg + an unspec constant.
2840
2841 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2842 reg also appears in the address. */
2843
2844 rtx
2845 legitimize_pic_address (rtx orig, rtx reg)
2846 {
2847 rtx addr = orig;
2848 rtx new = orig;
2849 rtx base;
2850
2851 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
2852
2853 if (GET_CODE (addr) == LABEL_REF
2854 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2855 {
2856 /* This is a local symbol. */
2857 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2858 {
2859 /* Access local symbols PC-relative via LARL.
2860 This is the same as in the non-PIC case, so it is
2861 handled automatically ... */
2862 }
2863 else
2864 {
2865 /* Access local symbols relative to the GOT. */
2866
2867 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2868
2869 if (reload_in_progress || reload_completed)
2870 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2871
2872 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2873 addr = gen_rtx_CONST (Pmode, addr);
2874 addr = force_const_mem (Pmode, addr);
2875 emit_move_insn (temp, addr);
2876
2877 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2878 if (reg != 0)
2879 {
2880 s390_load_address (reg, new);
2881 new = reg;
2882 }
2883 }
2884 }
2885 else if (GET_CODE (addr) == SYMBOL_REF)
2886 {
2887 if (reg == 0)
2888 reg = gen_reg_rtx (Pmode);
2889
2890 if (flag_pic == 1)
2891 {
2892 /* Assume GOT offset < 4k. This is handled the same way
2893 in both 31- and 64-bit code (@GOT). */
2894
2895 if (reload_in_progress || reload_completed)
2896 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2897
2898 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2899 new = gen_rtx_CONST (Pmode, new);
2900 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2901 new = gen_const_mem (Pmode, new);
2902 emit_move_insn (reg, new);
2903 new = reg;
2904 }
2905 else if (TARGET_CPU_ZARCH)
2906 {
2907 /* If the GOT offset might be >= 4k, we determine the position
2908 of the GOT entry via a PC-relative LARL (@GOTENT). */
2909
2910 rtx temp = gen_reg_rtx (Pmode);
2911
2912 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2913 new = gen_rtx_CONST (Pmode, new);
2914 emit_move_insn (temp, new);
2915
2916 new = gen_const_mem (Pmode, temp);
2917 emit_move_insn (reg, new);
2918 new = reg;
2919 }
2920 else
2921 {
2922 /* If the GOT offset might be >= 4k, we have to load it
2923 from the literal pool (@GOT). */
2924
2925 rtx temp = gen_reg_rtx (Pmode);
2926
2927 if (reload_in_progress || reload_completed)
2928 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2929
2930 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2931 addr = gen_rtx_CONST (Pmode, addr);
2932 addr = force_const_mem (Pmode, addr);
2933 emit_move_insn (temp, addr);
2934
2935 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2936 new = gen_const_mem (Pmode, new);
2937 emit_move_insn (reg, new);
2938 new = reg;
2939 }
2940 }
2941 else
2942 {
2943 if (GET_CODE (addr) == CONST)
2944 {
2945 addr = XEXP (addr, 0);
2946 if (GET_CODE (addr) == UNSPEC)
2947 {
2948 gcc_assert (XVECLEN (addr, 0) == 1);
2949 switch (XINT (addr, 1))
2950 {
2951 /* If someone moved a GOT-relative UNSPEC
2952 out of the literal pool, force them back in. */
2953 case UNSPEC_GOTOFF:
2954 case UNSPEC_PLTOFF:
2955 new = force_const_mem (Pmode, orig);
2956 break;
2957
2958 /* @GOT is OK as is if small. */
2959 case UNSPEC_GOT:
2960 if (flag_pic == 2)
2961 new = force_const_mem (Pmode, orig);
2962 break;
2963
2964 /* @GOTENT is OK as is. */
2965 case UNSPEC_GOTENT:
2966 break;
2967
2968 /* @PLT is OK as is on 64-bit, must be converted to
2969 GOT-relative @PLTOFF on 31-bit. */
2970 case UNSPEC_PLT:
2971 if (!TARGET_CPU_ZARCH)
2972 {
2973 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2974
2975 if (reload_in_progress || reload_completed)
2976 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2977
2978 addr = XVECEXP (addr, 0, 0);
2979 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2980 UNSPEC_PLTOFF);
2981 addr = gen_rtx_CONST (Pmode, addr);
2982 addr = force_const_mem (Pmode, addr);
2983 emit_move_insn (temp, addr);
2984
2985 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2986 if (reg != 0)
2987 {
2988 s390_load_address (reg, new);
2989 new = reg;
2990 }
2991 }
2992 break;
2993
2994 /* Everything else cannot happen. */
2995 default:
2996 gcc_unreachable ();
2997 }
2998 }
2999 else
3000 gcc_assert (GET_CODE (addr) == PLUS);
3001 }
3002 if (GET_CODE (addr) == PLUS)
3003 {
3004 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3005
3006 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3007 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3008
3009 /* Check first to see if this is a constant offset
3010 from a local symbol reference. */
3011 if ((GET_CODE (op0) == LABEL_REF
3012 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3013 && GET_CODE (op1) == CONST_INT)
3014 {
3015 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
3016 {
3017 if (INTVAL (op1) & 1)
3018 {
3019 /* LARL can't handle odd offsets, so emit a
3020 pair of LARL and LA. */
3021 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3022
3023 if (!DISP_IN_RANGE (INTVAL (op1)))
3024 {
3025 int even = INTVAL (op1) - 1;
3026 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3027 op0 = gen_rtx_CONST (Pmode, op0);
3028 op1 = const1_rtx;
3029 }
3030
3031 emit_move_insn (temp, op0);
3032 new = gen_rtx_PLUS (Pmode, temp, op1);
3033
3034 if (reg != 0)
3035 {
3036 s390_load_address (reg, new);
3037 new = reg;
3038 }
3039 }
3040 else
3041 {
3042 /* If the offset is even, we can just use LARL.
3043 This will happen automatically. */
3044 }
3045 }
3046 else
3047 {
3048 /* Access local symbols relative to the GOT. */
3049
3050 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3051
3052 if (reload_in_progress || reload_completed)
3053 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3054
3055 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3056 UNSPEC_GOTOFF);
3057 addr = gen_rtx_PLUS (Pmode, addr, op1);
3058 addr = gen_rtx_CONST (Pmode, addr);
3059 addr = force_const_mem (Pmode, addr);
3060 emit_move_insn (temp, addr);
3061
3062 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3063 if (reg != 0)
3064 {
3065 s390_load_address (reg, new);
3066 new = reg;
3067 }
3068 }
3069 }
3070
3071 /* Now, check whether it is a GOT relative symbol plus offset
3072 that was pulled out of the literal pool. Force it back in. */
3073
3074 else if (GET_CODE (op0) == UNSPEC
3075 && GET_CODE (op1) == CONST_INT
3076 && XINT (op0, 1) == UNSPEC_GOTOFF)
3077 {
3078 gcc_assert (XVECLEN (op0, 0) == 1);
3079
3080 new = force_const_mem (Pmode, orig);
3081 }
3082
3083 /* Otherwise, compute the sum. */
3084 else
3085 {
3086 base = legitimize_pic_address (XEXP (addr, 0), reg);
3087 new = legitimize_pic_address (XEXP (addr, 1),
3088 base == reg ? NULL_RTX : reg);
3089 if (GET_CODE (new) == CONST_INT)
3090 new = plus_constant (base, INTVAL (new));
3091 else
3092 {
3093 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3094 {
3095 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3096 new = XEXP (new, 1);
3097 }
3098 new = gen_rtx_PLUS (Pmode, base, new);
3099 }
3100
3101 if (GET_CODE (new) == CONST)
3102 new = XEXP (new, 0);
3103 new = force_operand (new, 0);
3104 }
3105 }
3106 }
3107 return new;
3108 }
3109
3110 /* Load the thread pointer into a register. */
3111
3112 rtx
3113 s390_get_thread_pointer (void)
3114 {
3115 rtx tp = gen_reg_rtx (Pmode);
3116
3117 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3118 mark_reg_pointer (tp, BITS_PER_WORD);
3119
3120 return tp;
3121 }
3122
3123 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3124 in s390_tls_symbol which always refers to __tls_get_offset.
3125 The returned offset is written to RESULT_REG and an USE rtx is
3126 generated for TLS_CALL. */
3127
3128 static GTY(()) rtx s390_tls_symbol;
3129
3130 static void
3131 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3132 {
3133 rtx insn;
3134
3135 gcc_assert (flag_pic);
3136
3137 if (!s390_tls_symbol)
3138 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3139
3140 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3141 gen_rtx_REG (Pmode, RETURN_REGNUM));
3142
3143 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3144 CONST_OR_PURE_CALL_P (insn) = 1;
3145 }
3146
3147 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3148 this (thread-local) address. REG may be used as temporary. */
3149
3150 static rtx
3151 legitimize_tls_address (rtx addr, rtx reg)
3152 {
3153 rtx new, tls_call, temp, base, r2, insn;
3154
3155 if (GET_CODE (addr) == SYMBOL_REF)
3156 switch (tls_symbolic_operand (addr))
3157 {
3158 case TLS_MODEL_GLOBAL_DYNAMIC:
3159 start_sequence ();
3160 r2 = gen_rtx_REG (Pmode, 2);
3161 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3162 new = gen_rtx_CONST (Pmode, tls_call);
3163 new = force_const_mem (Pmode, new);
3164 emit_move_insn (r2, new);
3165 s390_emit_tls_call_insn (r2, tls_call);
3166 insn = get_insns ();
3167 end_sequence ();
3168
3169 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3170 temp = gen_reg_rtx (Pmode);
3171 emit_libcall_block (insn, temp, r2, new);
3172
3173 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3174 if (reg != 0)
3175 {
3176 s390_load_address (reg, new);
3177 new = reg;
3178 }
3179 break;
3180
3181 case TLS_MODEL_LOCAL_DYNAMIC:
3182 start_sequence ();
3183 r2 = gen_rtx_REG (Pmode, 2);
3184 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3185 new = gen_rtx_CONST (Pmode, tls_call);
3186 new = force_const_mem (Pmode, new);
3187 emit_move_insn (r2, new);
3188 s390_emit_tls_call_insn (r2, tls_call);
3189 insn = get_insns ();
3190 end_sequence ();
3191
3192 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3193 temp = gen_reg_rtx (Pmode);
3194 emit_libcall_block (insn, temp, r2, new);
3195
3196 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3197 base = gen_reg_rtx (Pmode);
3198 s390_load_address (base, new);
3199
3200 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3201 new = gen_rtx_CONST (Pmode, new);
3202 new = force_const_mem (Pmode, new);
3203 temp = gen_reg_rtx (Pmode);
3204 emit_move_insn (temp, new);
3205
3206 new = gen_rtx_PLUS (Pmode, base, temp);
3207 if (reg != 0)
3208 {
3209 s390_load_address (reg, new);
3210 new = reg;
3211 }
3212 break;
3213
3214 case TLS_MODEL_INITIAL_EXEC:
3215 if (flag_pic == 1)
3216 {
3217 /* Assume GOT offset < 4k. This is handled the same way
3218 in both 31- and 64-bit code. */
3219
3220 if (reload_in_progress || reload_completed)
3221 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3222
3223 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3224 new = gen_rtx_CONST (Pmode, new);
3225 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3226 new = gen_const_mem (Pmode, new);
3227 temp = gen_reg_rtx (Pmode);
3228 emit_move_insn (temp, new);
3229 }
3230 else if (TARGET_CPU_ZARCH)
3231 {
3232 /* If the GOT offset might be >= 4k, we determine the position
3233 of the GOT entry via a PC-relative LARL. */
3234
3235 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3236 new = gen_rtx_CONST (Pmode, new);
3237 temp = gen_reg_rtx (Pmode);
3238 emit_move_insn (temp, new);
3239
3240 new = gen_const_mem (Pmode, temp);
3241 temp = gen_reg_rtx (Pmode);
3242 emit_move_insn (temp, new);
3243 }
3244 else if (flag_pic)
3245 {
3246 /* If the GOT offset might be >= 4k, we have to load it
3247 from the literal pool. */
3248
3249 if (reload_in_progress || reload_completed)
3250 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3251
3252 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3253 new = gen_rtx_CONST (Pmode, new);
3254 new = force_const_mem (Pmode, new);
3255 temp = gen_reg_rtx (Pmode);
3256 emit_move_insn (temp, new);
3257
3258 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3259 new = gen_const_mem (Pmode, new);
3260
3261 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3262 temp = gen_reg_rtx (Pmode);
3263 emit_insn (gen_rtx_SET (Pmode, temp, new));
3264 }
3265 else
3266 {
3267 /* In position-dependent code, load the absolute address of
3268 the GOT entry from the literal pool. */
3269
3270 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3271 new = gen_rtx_CONST (Pmode, new);
3272 new = force_const_mem (Pmode, new);
3273 temp = gen_reg_rtx (Pmode);
3274 emit_move_insn (temp, new);
3275
3276 new = temp;
3277 new = gen_const_mem (Pmode, new);
3278 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3279 temp = gen_reg_rtx (Pmode);
3280 emit_insn (gen_rtx_SET (Pmode, temp, new));
3281 }
3282
3283 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3284 if (reg != 0)
3285 {
3286 s390_load_address (reg, new);
3287 new = reg;
3288 }
3289 break;
3290
3291 case TLS_MODEL_LOCAL_EXEC:
3292 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3293 new = gen_rtx_CONST (Pmode, new);
3294 new = force_const_mem (Pmode, new);
3295 temp = gen_reg_rtx (Pmode);
3296 emit_move_insn (temp, new);
3297
3298 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3299 if (reg != 0)
3300 {
3301 s390_load_address (reg, new);
3302 new = reg;
3303 }
3304 break;
3305
3306 default:
3307 gcc_unreachable ();
3308 }
3309
3310 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3311 {
3312 switch (XINT (XEXP (addr, 0), 1))
3313 {
3314 case UNSPEC_INDNTPOFF:
3315 gcc_assert (TARGET_CPU_ZARCH);
3316 new = addr;
3317 break;
3318
3319 default:
3320 gcc_unreachable ();
3321 }
3322 }
3323
3324 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3325 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3326 {
3327 new = XEXP (XEXP (addr, 0), 0);
3328 if (GET_CODE (new) != SYMBOL_REF)
3329 new = gen_rtx_CONST (Pmode, new);
3330
3331 new = legitimize_tls_address (new, reg);
3332 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3333 new = force_operand (new, 0);
3334 }
3335
3336 else
3337 gcc_unreachable (); /* for now ... */
3338
3339 return new;
3340 }
3341
3342 /* Emit insns to move operands[1] into operands[0]. */
3343
3344 void
3345 emit_symbolic_move (rtx *operands)
3346 {
3347 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3348
3349 if (GET_CODE (operands[0]) == MEM)
3350 operands[1] = force_reg (Pmode, operands[1]);
3351 else if (TLS_SYMBOLIC_CONST (operands[1]))
3352 operands[1] = legitimize_tls_address (operands[1], temp);
3353 else if (flag_pic)
3354 operands[1] = legitimize_pic_address (operands[1], temp);
3355 }
3356
3357 /* Try machine-dependent ways of modifying an illegitimate address X
3358 to be legitimate. If we find one, return the new, valid address.
3359
3360 OLDX is the address as it was before break_out_memory_refs was called.
3361 In some cases it is useful to look at this to decide what needs to be done.
3362
3363 MODE is the mode of the operand pointed to by X.
3364
3365 When -fpic is used, special handling is needed for symbolic references.
3366 See comments by legitimize_pic_address for details. */
3367
3368 rtx
3369 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3370 enum machine_mode mode ATTRIBUTE_UNUSED)
3371 {
3372 rtx constant_term = const0_rtx;
3373
3374 if (TLS_SYMBOLIC_CONST (x))
3375 {
3376 x = legitimize_tls_address (x, 0);
3377
3378 if (legitimate_address_p (mode, x, FALSE))
3379 return x;
3380 }
3381 else if (GET_CODE (x) == PLUS
3382 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3383 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3384 {
3385 return x;
3386 }
3387 else if (flag_pic)
3388 {
3389 if (SYMBOLIC_CONST (x)
3390 || (GET_CODE (x) == PLUS
3391 && (SYMBOLIC_CONST (XEXP (x, 0))
3392 || SYMBOLIC_CONST (XEXP (x, 1)))))
3393 x = legitimize_pic_address (x, 0);
3394
3395 if (legitimate_address_p (mode, x, FALSE))
3396 return x;
3397 }
3398
3399 x = eliminate_constant_term (x, &constant_term);
3400
3401 /* Optimize loading of large displacements by splitting them
3402 into the multiple of 4K and the rest; this allows the
3403 former to be CSE'd if possible.
3404
3405 Don't do this if the displacement is added to a register
3406 pointing into the stack frame, as the offsets will
3407 change later anyway. */
3408
3409 if (GET_CODE (constant_term) == CONST_INT
3410 && !TARGET_LONG_DISPLACEMENT
3411 && !DISP_IN_RANGE (INTVAL (constant_term))
3412 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3413 {
3414 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3415 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3416
3417 rtx temp = gen_reg_rtx (Pmode);
3418 rtx val = force_operand (GEN_INT (upper), temp);
3419 if (val != temp)
3420 emit_move_insn (temp, val);
3421
3422 x = gen_rtx_PLUS (Pmode, x, temp);
3423 constant_term = GEN_INT (lower);
3424 }
3425
3426 if (GET_CODE (x) == PLUS)
3427 {
3428 if (GET_CODE (XEXP (x, 0)) == REG)
3429 {
3430 rtx temp = gen_reg_rtx (Pmode);
3431 rtx val = force_operand (XEXP (x, 1), temp);
3432 if (val != temp)
3433 emit_move_insn (temp, val);
3434
3435 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3436 }
3437
3438 else if (GET_CODE (XEXP (x, 1)) == REG)
3439 {
3440 rtx temp = gen_reg_rtx (Pmode);
3441 rtx val = force_operand (XEXP (x, 0), temp);
3442 if (val != temp)
3443 emit_move_insn (temp, val);
3444
3445 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3446 }
3447 }
3448
3449 if (constant_term != const0_rtx)
3450 x = gen_rtx_PLUS (Pmode, x, constant_term);
3451
3452 return x;
3453 }
3454
3455 /* Try a machine-dependent way of reloading an illegitimate address AD
3456 operand. If we find one, push the reload and and return the new address.
3457
3458 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3459 and TYPE is the reload type of the current reload. */
3460
3461 rtx
3462 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3463 int opnum, int type)
3464 {
3465 if (!optimize || TARGET_LONG_DISPLACEMENT)
3466 return NULL_RTX;
3467
3468 if (GET_CODE (ad) == PLUS)
3469 {
3470 rtx tem = simplify_binary_operation (PLUS, Pmode,
3471 XEXP (ad, 0), XEXP (ad, 1));
3472 if (tem)
3473 ad = tem;
3474 }
3475
3476 if (GET_CODE (ad) == PLUS
3477 && GET_CODE (XEXP (ad, 0)) == REG
3478 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3479 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3480 {
3481 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3482 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3483 rtx cst, tem, new;
3484
3485 cst = GEN_INT (upper);
3486 if (!legitimate_reload_constant_p (cst))
3487 cst = force_const_mem (Pmode, cst);
3488
3489 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3490 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3491
3492 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3493 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3494 opnum, (enum reload_type) type);
3495 return new;
3496 }
3497
3498 return NULL_RTX;
3499 }
3500
3501 /* Emit code to move LEN bytes from DST to SRC. */
3502
3503 void
3504 s390_expand_movmem (rtx dst, rtx src, rtx len)
3505 {
3506 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3507 {
3508 if (INTVAL (len) > 0)
3509 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3510 }
3511
3512 else if (TARGET_MVCLE)
3513 {
3514 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3515 }
3516
3517 else
3518 {
3519 rtx dst_addr, src_addr, count, blocks, temp;
3520 rtx loop_start_label = gen_label_rtx ();
3521 rtx loop_end_label = gen_label_rtx ();
3522 rtx end_label = gen_label_rtx ();
3523 enum machine_mode mode;
3524
3525 mode = GET_MODE (len);
3526 if (mode == VOIDmode)
3527 mode = Pmode;
3528
3529 dst_addr = gen_reg_rtx (Pmode);
3530 src_addr = gen_reg_rtx (Pmode);
3531 count = gen_reg_rtx (mode);
3532 blocks = gen_reg_rtx (mode);
3533
3534 convert_move (count, len, 1);
3535 emit_cmp_and_jump_insns (count, const0_rtx,
3536 EQ, NULL_RTX, mode, 1, end_label);
3537
3538 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3539 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3540 dst = change_address (dst, VOIDmode, dst_addr);
3541 src = change_address (src, VOIDmode, src_addr);
3542
3543 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3544 if (temp != count)
3545 emit_move_insn (count, temp);
3546
3547 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3548 if (temp != blocks)
3549 emit_move_insn (blocks, temp);
3550
3551 emit_cmp_and_jump_insns (blocks, const0_rtx,
3552 EQ, NULL_RTX, mode, 1, loop_end_label);
3553
3554 emit_label (loop_start_label);
3555
3556 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3557 s390_load_address (dst_addr,
3558 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3559 s390_load_address (src_addr,
3560 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3561
3562 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3563 if (temp != blocks)
3564 emit_move_insn (blocks, temp);
3565
3566 emit_cmp_and_jump_insns (blocks, const0_rtx,
3567 EQ, NULL_RTX, mode, 1, loop_end_label);
3568
3569 emit_jump (loop_start_label);
3570 emit_label (loop_end_label);
3571
3572 emit_insn (gen_movmem_short (dst, src,
3573 convert_to_mode (Pmode, count, 1)));
3574 emit_label (end_label);
3575 }
3576 }
3577
3578 /* Emit code to set LEN bytes at DST to VAL.
3579 Make use of clrmem if VAL is zero. */
3580
3581 void
3582 s390_expand_setmem (rtx dst, rtx len, rtx val)
3583 {
3584 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3585 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3586
3587 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3588 {
3589 if (val == const0_rtx && INTVAL (len) <= 256)
3590 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3591 else
3592 {
3593 /* Initialize memory by storing the first byte. */
3594 emit_move_insn (adjust_address (dst, QImode, 0), val);
3595
3596 if (INTVAL (len) > 1)
3597 {
3598 /* Initiate 1 byte overlap move.
3599 The first byte of DST is propagated through DSTP1.
3600 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3601 DST is set to size 1 so the rest of the memory location
3602 does not count as source operand. */
3603 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3604 set_mem_size (dst, const1_rtx);
3605
3606 emit_insn (gen_movmem_short (dstp1, dst,
3607 GEN_INT (INTVAL (len) - 2)));
3608 }
3609 }
3610 }
3611
3612 else if (TARGET_MVCLE)
3613 {
3614 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3615 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3616 }
3617
3618 else
3619 {
3620 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3621 rtx loop_start_label = gen_label_rtx ();
3622 rtx loop_end_label = gen_label_rtx ();
3623 rtx end_label = gen_label_rtx ();
3624 enum machine_mode mode;
3625
3626 mode = GET_MODE (len);
3627 if (mode == VOIDmode)
3628 mode = Pmode;
3629
3630 dst_addr = gen_reg_rtx (Pmode);
3631 src_addr = gen_reg_rtx (Pmode);
3632 count = gen_reg_rtx (mode);
3633 blocks = gen_reg_rtx (mode);
3634
3635 convert_move (count, len, 1);
3636 emit_cmp_and_jump_insns (count, const0_rtx,
3637 EQ, NULL_RTX, mode, 1, end_label);
3638
3639 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3640 dst = change_address (dst, VOIDmode, dst_addr);
3641
3642 if (val == const0_rtx)
3643 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3644 else
3645 {
3646 dstp1 = adjust_address (dst, VOIDmode, 1);
3647 set_mem_size (dst, const1_rtx);
3648
3649 /* Initialize memory by storing the first byte. */
3650 emit_move_insn (adjust_address (dst, QImode, 0), val);
3651
3652 /* If count is 1 we are done. */
3653 emit_cmp_and_jump_insns (count, const1_rtx,
3654 EQ, NULL_RTX, mode, 1, end_label);
3655
3656 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3657 }
3658 if (temp != count)
3659 emit_move_insn (count, temp);
3660
3661 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3662 if (temp != blocks)
3663 emit_move_insn (blocks, temp);
3664
3665 emit_cmp_and_jump_insns (blocks, const0_rtx,
3666 EQ, NULL_RTX, mode, 1, loop_end_label);
3667
3668 emit_label (loop_start_label);
3669
3670 if (val == const0_rtx)
3671 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3672 else
3673 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3674 s390_load_address (dst_addr,
3675 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3676
3677 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3678 if (temp != blocks)
3679 emit_move_insn (blocks, temp);
3680
3681 emit_cmp_and_jump_insns (blocks, const0_rtx,
3682 EQ, NULL_RTX, mode, 1, loop_end_label);
3683
3684 emit_jump (loop_start_label);
3685 emit_label (loop_end_label);
3686
3687 if (val == const0_rtx)
3688 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3689 else
3690 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3691 emit_label (end_label);
3692 }
3693 }
3694
3695 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3696 and return the result in TARGET. */
3697
3698 void
3699 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3700 {
3701 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3702 rtx tmp;
3703
3704 /* As the result of CMPINT is inverted compared to what we need,
3705 we have to swap the operands. */
3706 tmp = op0; op0 = op1; op1 = tmp;
3707
3708 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3709 {
3710 if (INTVAL (len) > 0)
3711 {
3712 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3713 emit_insn (gen_cmpint (target, ccreg));
3714 }
3715 else
3716 emit_move_insn (target, const0_rtx);
3717 }
3718 else if (TARGET_MVCLE)
3719 {
3720 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3721 emit_insn (gen_cmpint (target, ccreg));
3722 }
3723 else
3724 {
3725 rtx addr0, addr1, count, blocks, temp;
3726 rtx loop_start_label = gen_label_rtx ();
3727 rtx loop_end_label = gen_label_rtx ();
3728 rtx end_label = gen_label_rtx ();
3729 enum machine_mode mode;
3730
3731 mode = GET_MODE (len);
3732 if (mode == VOIDmode)
3733 mode = Pmode;
3734
3735 addr0 = gen_reg_rtx (Pmode);
3736 addr1 = gen_reg_rtx (Pmode);
3737 count = gen_reg_rtx (mode);
3738 blocks = gen_reg_rtx (mode);
3739
3740 convert_move (count, len, 1);
3741 emit_cmp_and_jump_insns (count, const0_rtx,
3742 EQ, NULL_RTX, mode, 1, end_label);
3743
3744 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3745 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3746 op0 = change_address (op0, VOIDmode, addr0);
3747 op1 = change_address (op1, VOIDmode, addr1);
3748
3749 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3750 if (temp != count)
3751 emit_move_insn (count, temp);
3752
3753 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3754 if (temp != blocks)
3755 emit_move_insn (blocks, temp);
3756
3757 emit_cmp_and_jump_insns (blocks, const0_rtx,
3758 EQ, NULL_RTX, mode, 1, loop_end_label);
3759
3760 emit_label (loop_start_label);
3761
3762 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3763 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3764 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3765 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3766 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3767 emit_jump_insn (temp);
3768
3769 s390_load_address (addr0,
3770 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3771 s390_load_address (addr1,
3772 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3773
3774 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3775 if (temp != blocks)
3776 emit_move_insn (blocks, temp);
3777
3778 emit_cmp_and_jump_insns (blocks, const0_rtx,
3779 EQ, NULL_RTX, mode, 1, loop_end_label);
3780
3781 emit_jump (loop_start_label);
3782 emit_label (loop_end_label);
3783
3784 emit_insn (gen_cmpmem_short (op0, op1,
3785 convert_to_mode (Pmode, count, 1)));
3786 emit_label (end_label);
3787
3788 emit_insn (gen_cmpint (target, ccreg));
3789 }
3790 }
3791
3792
3793 /* Expand conditional increment or decrement using alc/slb instructions.
3794 Should generate code setting DST to either SRC or SRC + INCREMENT,
3795 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3796 Returns true if successful, false otherwise.
3797
3798 That makes it possible to implement some if-constructs without jumps e.g.:
3799 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3800 unsigned int a, b, c;
3801 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3802 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3803 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3804 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3805
3806 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3807 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3808 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3809 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3810 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3811
3812 bool
3813 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3814 rtx dst, rtx src, rtx increment)
3815 {
3816 enum machine_mode cmp_mode;
3817 enum machine_mode cc_mode;
3818 rtx op_res;
3819 rtx insn;
3820 rtvec p;
3821 int ret;
3822
3823 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3824 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3825 cmp_mode = SImode;
3826 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3827 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3828 cmp_mode = DImode;
3829 else
3830 return false;
3831
3832 /* Try ADD LOGICAL WITH CARRY. */
3833 if (increment == const1_rtx)
3834 {
3835 /* Determine CC mode to use. */
3836 if (cmp_code == EQ || cmp_code == NE)
3837 {
3838 if (cmp_op1 != const0_rtx)
3839 {
3840 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3841 NULL_RTX, 0, OPTAB_WIDEN);
3842 cmp_op1 = const0_rtx;
3843 }
3844
3845 cmp_code = cmp_code == EQ ? LEU : GTU;
3846 }
3847
3848 if (cmp_code == LTU || cmp_code == LEU)
3849 {
3850 rtx tem = cmp_op0;
3851 cmp_op0 = cmp_op1;
3852 cmp_op1 = tem;
3853 cmp_code = swap_condition (cmp_code);
3854 }
3855
3856 switch (cmp_code)
3857 {
3858 case GTU:
3859 cc_mode = CCUmode;
3860 break;
3861
3862 case GEU:
3863 cc_mode = CCL3mode;
3864 break;
3865
3866 default:
3867 return false;
3868 }
3869
3870 /* Emit comparison instruction pattern. */
3871 if (!register_operand (cmp_op0, cmp_mode))
3872 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3873
3874 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3875 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3876 /* We use insn_invalid_p here to add clobbers if required. */
3877 ret = insn_invalid_p (emit_insn (insn));
3878 gcc_assert (!ret);
3879
3880 /* Emit ALC instruction pattern. */
3881 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3882 gen_rtx_REG (cc_mode, CC_REGNUM),
3883 const0_rtx);
3884
3885 if (src != const0_rtx)
3886 {
3887 if (!register_operand (src, GET_MODE (dst)))
3888 src = force_reg (GET_MODE (dst), src);
3889
3890 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3891 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3892 }
3893
3894 p = rtvec_alloc (2);
3895 RTVEC_ELT (p, 0) =
3896 gen_rtx_SET (VOIDmode, dst, op_res);
3897 RTVEC_ELT (p, 1) =
3898 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3899 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3900
3901 return true;
3902 }
3903
3904 /* Try SUBTRACT LOGICAL WITH BORROW. */
3905 if (increment == constm1_rtx)
3906 {
3907 /* Determine CC mode to use. */
3908 if (cmp_code == EQ || cmp_code == NE)
3909 {
3910 if (cmp_op1 != const0_rtx)
3911 {
3912 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3913 NULL_RTX, 0, OPTAB_WIDEN);
3914 cmp_op1 = const0_rtx;
3915 }
3916
3917 cmp_code = cmp_code == EQ ? LEU : GTU;
3918 }
3919
3920 if (cmp_code == GTU || cmp_code == GEU)
3921 {
3922 rtx tem = cmp_op0;
3923 cmp_op0 = cmp_op1;
3924 cmp_op1 = tem;
3925 cmp_code = swap_condition (cmp_code);
3926 }
3927
3928 switch (cmp_code)
3929 {
3930 case LEU:
3931 cc_mode = CCUmode;
3932 break;
3933
3934 case LTU:
3935 cc_mode = CCL3mode;
3936 break;
3937
3938 default:
3939 return false;
3940 }
3941
3942 /* Emit comparison instruction pattern. */
3943 if (!register_operand (cmp_op0, cmp_mode))
3944 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3945
3946 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3947 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3948 /* We use insn_invalid_p here to add clobbers if required. */
3949 ret = insn_invalid_p (emit_insn (insn));
3950 gcc_assert (!ret);
3951
3952 /* Emit SLB instruction pattern. */
3953 if (!register_operand (src, GET_MODE (dst)))
3954 src = force_reg (GET_MODE (dst), src);
3955
3956 op_res = gen_rtx_MINUS (GET_MODE (dst),
3957 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3958 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3959 gen_rtx_REG (cc_mode, CC_REGNUM),
3960 const0_rtx));
3961 p = rtvec_alloc (2);
3962 RTVEC_ELT (p, 0) =
3963 gen_rtx_SET (VOIDmode, dst, op_res);
3964 RTVEC_ELT (p, 1) =
3965 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3966 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3967
3968 return true;
3969 }
3970
3971 return false;
3972 }
3973
3974 /* Expand code for the insv template. Return true if successful, false else. */
3975
3976 bool
3977 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3978 {
3979 int bitsize = INTVAL (op1);
3980 int bitpos = INTVAL (op2);
3981
3982 /* We need byte alignment. */
3983 if (bitsize % BITS_PER_UNIT)
3984 return false;
3985
3986 if (bitpos == 0
3987 && memory_operand (dest, VOIDmode)
3988 && (register_operand (src, word_mode)
3989 || const_int_operand (src, VOIDmode)))
3990 {
3991 /* Emit standard pattern if possible. */
3992 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3993 if (GET_MODE_BITSIZE (mode) == bitsize)
3994 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3995
3996 /* (set (ze (mem)) (const_int)). */
3997 else if (const_int_operand (src, VOIDmode))
3998 {
3999 int size = bitsize / BITS_PER_UNIT;
4000 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4001 GET_MODE_SIZE (word_mode) - size);
4002
4003 dest = adjust_address (dest, BLKmode, 0);
4004 set_mem_size (dest, GEN_INT (size));
4005 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4006 }
4007
4008 /* (set (ze (mem)) (reg)). */
4009 else if (register_operand (src, word_mode))
4010 {
4011 if (bitsize <= GET_MODE_BITSIZE (SImode))
4012 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4013 const0_rtx), src);
4014 else
4015 {
4016 /* Emit st,stcmh sequence. */
4017 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4018 int size = stcmh_width / BITS_PER_UNIT;
4019
4020 emit_move_insn (adjust_address (dest, SImode, size),
4021 gen_lowpart (SImode, src));
4022 set_mem_size (dest, GEN_INT (size));
4023 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4024 (stcmh_width), const0_rtx),
4025 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4026 (GET_MODE_BITSIZE (SImode))));
4027 }
4028 }
4029 else
4030 return false;
4031
4032 return true;
4033 }
4034
4035 /* (set (ze (reg)) (const_int)). */
4036 if (TARGET_ZARCH
4037 && register_operand (dest, word_mode)
4038 && (bitpos % 16) == 0
4039 && (bitsize % 16) == 0
4040 && const_int_operand (src, VOIDmode))
4041 {
4042 HOST_WIDE_INT val = INTVAL (src);
4043 int regpos = bitpos + bitsize;
4044
4045 while (regpos > bitpos)
4046 {
4047 enum machine_mode putmode;
4048 int putsize;
4049
4050 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4051 putmode = SImode;
4052 else
4053 putmode = HImode;
4054
4055 putsize = GET_MODE_BITSIZE (putmode);
4056 regpos -= putsize;
4057 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4058 GEN_INT (putsize),
4059 GEN_INT (regpos)),
4060 gen_int_mode (val, putmode));
4061 val >>= putsize;
4062 }
4063 gcc_assert (regpos == bitpos);
4064 return true;
4065 }
4066
4067 return false;
4068 }
4069
4070 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4071 register that holds VAL of mode MODE shifted by COUNT bits. */
4072
4073 static inline rtx
4074 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4075 {
4076 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4077 NULL_RTX, 1, OPTAB_DIRECT);
4078 return expand_simple_binop (SImode, ASHIFT, val, count,
4079 NULL_RTX, 1, OPTAB_DIRECT);
4080 }
4081
4082 /* Structure to hold the initial parameters for a compare_and_swap operation
4083 in HImode and QImode. */
4084
4085 struct alignment_context
4086 {
4087 rtx memsi; /* SI aligned memory location. */
4088 rtx shift; /* Bit offset with regard to lsb. */
4089 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4090 rtx modemaski; /* ~modemask */
4091 bool aligned; /* True if memory is aligned, false else. */
4092 };
4093
4094 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4095 structure AC for transparent simplifying, if the memory alignment is known
4096 to be at least 32bit. MEM is the memory location for the actual operation
4097 and MODE its mode. */
4098
4099 static void
4100 init_alignment_context (struct alignment_context *ac, rtx mem,
4101 enum machine_mode mode)
4102 {
4103 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4104 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4105
4106 if (ac->aligned)
4107 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4108 else
4109 {
4110 /* Alignment is unknown. */
4111 rtx byteoffset, addr, align;
4112
4113 /* Force the address into a register. */
4114 addr = force_reg (Pmode, XEXP (mem, 0));
4115
4116 /* Align it to SImode. */
4117 align = expand_simple_binop (Pmode, AND, addr,
4118 GEN_INT (-GET_MODE_SIZE (SImode)),
4119 NULL_RTX, 1, OPTAB_DIRECT);
4120 /* Generate MEM. */
4121 ac->memsi = gen_rtx_MEM (SImode, align);
4122 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4123 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4124 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4125
4126 /* Calculate shiftcount. */
4127 byteoffset = expand_simple_binop (Pmode, AND, addr,
4128 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4129 NULL_RTX, 1, OPTAB_DIRECT);
4130 /* As we already have some offset, evaluate the remaining distance. */
4131 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4132 NULL_RTX, 1, OPTAB_DIRECT);
4133
4134 }
4135 /* Shift is the byte count, but we need the bitcount. */
4136 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4137 NULL_RTX, 1, OPTAB_DIRECT);
4138 /* Calculate masks. */
4139 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4140 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4141 NULL_RTX, 1, OPTAB_DIRECT);
4142 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4143 }
4144
4145 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4146 the memory location, CMP the old value to compare MEM with and NEW the value
4147 to set if CMP == MEM.
4148 CMP is never in memory for compare_and_swap_cc because
4149 expand_bool_compare_and_swap puts it into a register for later compare. */
4150
4151 void
4152 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4153 {
4154 struct alignment_context ac;
4155 rtx cmpv, newv, val, resv, cc;
4156 rtx res = gen_reg_rtx (SImode);
4157 rtx csloop = gen_label_rtx ();
4158 rtx csend = gen_label_rtx ();
4159
4160 gcc_assert (register_operand (target, VOIDmode));
4161 gcc_assert (MEM_P (mem));
4162
4163 init_alignment_context (&ac, mem, mode);
4164
4165 /* Shift the values to the correct bit positions. */
4166 if (!(ac.aligned && MEM_P (cmp)))
4167 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4168 if (!(ac.aligned && MEM_P (new)))
4169 new = s390_expand_mask_and_shift (new, mode, ac.shift);
4170
4171 /* Load full word. Subsequent loads are performed by CS. */
4172 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4173 NULL_RTX, 1, OPTAB_DIRECT);
4174
4175 /* Start CS loop. */
4176 emit_label (csloop);
4177 /* val = "<mem>00..0<mem>"
4178 * cmp = "00..0<cmp>00..0"
4179 * new = "00..0<new>00..0"
4180 */
4181
4182 /* Patch cmp and new with val at correct position. */
4183 if (ac.aligned && MEM_P (cmp))
4184 {
4185 cmpv = force_reg (SImode, val);
4186 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4187 }
4188 else
4189 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4190 NULL_RTX, 1, OPTAB_DIRECT));
4191 if (ac.aligned && MEM_P (new))
4192 {
4193 newv = force_reg (SImode, val);
4194 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4195 }
4196 else
4197 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4198 NULL_RTX, 1, OPTAB_DIRECT));
4199
4200 /* Emit compare_and_swap pattern. */
4201 emit_insn (gen_sync_compare_and_swap_ccsi (res, ac.memsi, cmpv, newv));
4202
4203 /* Jump to end if we're done (likely?). */
4204 s390_emit_jump (csend, s390_emit_compare (EQ, cmpv, ac.memsi));
4205
4206 /* Check for changes outside mode. */
4207 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4208 NULL_RTX, 1, OPTAB_DIRECT);
4209 cc = s390_emit_compare (NE, resv, val);
4210 emit_move_insn (val, resv);
4211 /* Loop internal if so. */
4212 s390_emit_jump (csloop, cc);
4213
4214 emit_label (csend);
4215
4216 /* Return the correct part of the bitfield. */
4217 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4218 NULL_RTX, 1, OPTAB_DIRECT), 1);
4219 }
4220
4221 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4222 and VAL the value to play with. If AFTER is true then store the the value
4223 MEM holds after the operation, if AFTER is false then store the value MEM
4224 holds before the operation. If TARGET is zero then discard that value, else
4225 store it to TARGET. */
4226
4227 void
4228 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4229 rtx target, rtx mem, rtx val, bool after)
4230 {
4231 struct alignment_context ac;
4232 rtx cmp;
4233 rtx new = gen_reg_rtx (SImode);
4234 rtx orig = gen_reg_rtx (SImode);
4235 rtx csloop = gen_label_rtx ();
4236
4237 gcc_assert (!target || register_operand (target, VOIDmode));
4238 gcc_assert (MEM_P (mem));
4239
4240 init_alignment_context (&ac, mem, mode);
4241
4242 /* Shift val to the correct bit positions.
4243 Preserve "icm", but prevent "ex icm". */
4244 if (!(ac.aligned && code == SET && MEM_P (val)))
4245 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4246
4247 /* Further preparation insns. */
4248 if (code == PLUS || code == MINUS)
4249 emit_move_insn (orig, val);
4250 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4251 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4252 NULL_RTX, 1, OPTAB_DIRECT);
4253
4254 /* Load full word. Subsequent loads are performed by CS. */
4255 cmp = force_reg (SImode, ac.memsi);
4256
4257 /* Start CS loop. */
4258 emit_label (csloop);
4259 emit_move_insn (new, cmp);
4260
4261 /* Patch new with val at correct position. */
4262 switch (code)
4263 {
4264 case PLUS:
4265 case MINUS:
4266 val = expand_simple_binop (SImode, code, new, orig,
4267 NULL_RTX, 1, OPTAB_DIRECT);
4268 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4269 NULL_RTX, 1, OPTAB_DIRECT);
4270 /* FALLTHRU */
4271 case SET:
4272 if (ac.aligned && MEM_P (val))
4273 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4274 else
4275 {
4276 new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4277 NULL_RTX, 1, OPTAB_DIRECT);
4278 new = expand_simple_binop (SImode, IOR, new, val,
4279 NULL_RTX, 1, OPTAB_DIRECT);
4280 }
4281 break;
4282 case AND:
4283 case IOR:
4284 case XOR:
4285 new = expand_simple_binop (SImode, code, new, val,
4286 NULL_RTX, 1, OPTAB_DIRECT);
4287 break;
4288 case MULT: /* NAND */
4289 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4290 NULL_RTX, 1, OPTAB_DIRECT);
4291 new = expand_simple_binop (SImode, AND, new, val,
4292 NULL_RTX, 1, OPTAB_DIRECT);
4293 break;
4294 default:
4295 gcc_unreachable ();
4296 }
4297 /* Emit compare_and_swap pattern. */
4298 emit_insn (gen_sync_compare_and_swap_ccsi (cmp, ac.memsi, cmp, new));
4299
4300 /* Loop until swapped (unlikely?). */
4301 s390_emit_jump (csloop, gen_rtx_fmt_ee (NE, CCZ1mode,
4302 gen_rtx_REG (CCZ1mode, CC_REGNUM),
4303 const0_rtx));
4304
4305 /* Return the correct part of the bitfield. */
4306 if (target)
4307 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4308 after ? new : cmp, ac.shift,
4309 NULL_RTX, 1, OPTAB_DIRECT), 1);
4310 }
4311
4312 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4313 We need to emit DTP-relative relocations. */
4314
4315 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4316
4317 static void
4318 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4319 {
4320 switch (size)
4321 {
4322 case 4:
4323 fputs ("\t.long\t", file);
4324 break;
4325 case 8:
4326 fputs ("\t.quad\t", file);
4327 break;
4328 default:
4329 gcc_unreachable ();
4330 }
4331 output_addr_const (file, x);
4332 fputs ("@DTPOFF", file);
4333 }
4334
4335 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4336 /* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */
4337
4338 static const char *
4339 s390_mangle_fundamental_type (tree type)
4340 {
4341 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4342 && TARGET_LONG_DOUBLE_128)
4343 return "g";
4344
4345 /* For all other types, use normal C++ mangling. */
4346 return NULL;
4347 }
4348 #endif
4349
4350 /* In the name of slightly smaller debug output, and to cater to
4351 general assembler lossage, recognize various UNSPEC sequences
4352 and turn them back into a direct symbol reference. */
4353
4354 static rtx
4355 s390_delegitimize_address (rtx orig_x)
4356 {
4357 rtx x = orig_x, y;
4358
4359 if (GET_CODE (x) != MEM)
4360 return orig_x;
4361
4362 x = XEXP (x, 0);
4363 if (GET_CODE (x) == PLUS
4364 && GET_CODE (XEXP (x, 1)) == CONST
4365 && GET_CODE (XEXP (x, 0)) == REG
4366 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4367 {
4368 y = XEXP (XEXP (x, 1), 0);
4369 if (GET_CODE (y) == UNSPEC
4370 && XINT (y, 1) == UNSPEC_GOT)
4371 return XVECEXP (y, 0, 0);
4372 return orig_x;
4373 }
4374
4375 if (GET_CODE (x) == CONST)
4376 {
4377 y = XEXP (x, 0);
4378 if (GET_CODE (y) == UNSPEC
4379 && XINT (y, 1) == UNSPEC_GOTENT)
4380 return XVECEXP (y, 0, 0);
4381 return orig_x;
4382 }
4383
4384 return orig_x;
4385 }
4386
4387 /* Output operand OP to stdio stream FILE.
4388 OP is an address (register + offset) which is not used to address data;
4389 instead the rightmost bits are interpreted as the value. */
4390
4391 static void
4392 print_shift_count_operand (FILE *file, rtx op)
4393 {
4394 HOST_WIDE_INT offset;
4395 rtx base;
4396
4397 /* Extract base register and offset. */
4398 if (!s390_decompose_shift_count (op, &base, &offset))
4399 gcc_unreachable ();
4400
4401 /* Sanity check. */
4402 if (base)
4403 {
4404 gcc_assert (GET_CODE (base) == REG);
4405 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4406 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4407 }
4408
4409 /* Offsets are constricted to twelve bits. */
4410 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4411 if (base)
4412 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4413 }
4414
4415 /* See 'get_some_local_dynamic_name'. */
4416
4417 static int
4418 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4419 {
4420 rtx x = *px;
4421
4422 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4423 {
4424 x = get_pool_constant (x);
4425 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4426 }
4427
4428 if (GET_CODE (x) == SYMBOL_REF
4429 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4430 {
4431 cfun->machine->some_ld_name = XSTR (x, 0);
4432 return 1;
4433 }
4434
4435 return 0;
4436 }
4437
4438 /* Locate some local-dynamic symbol still in use by this function
4439 so that we can print its name in local-dynamic base patterns. */
4440
4441 static const char *
4442 get_some_local_dynamic_name (void)
4443 {
4444 rtx insn;
4445
4446 if (cfun->machine->some_ld_name)
4447 return cfun->machine->some_ld_name;
4448
4449 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4450 if (INSN_P (insn)
4451 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4452 return cfun->machine->some_ld_name;
4453
4454 gcc_unreachable ();
4455 }
4456
4457 /* Output machine-dependent UNSPECs occurring in address constant X
4458 in assembler syntax to stdio stream FILE. Returns true if the
4459 constant X could be recognized, false otherwise. */
4460
4461 bool
4462 s390_output_addr_const_extra (FILE *file, rtx x)
4463 {
4464 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4465 switch (XINT (x, 1))
4466 {
4467 case UNSPEC_GOTENT:
4468 output_addr_const (file, XVECEXP (x, 0, 0));
4469 fprintf (file, "@GOTENT");
4470 return true;
4471 case UNSPEC_GOT:
4472 output_addr_const (file, XVECEXP (x, 0, 0));
4473 fprintf (file, "@GOT");
4474 return true;
4475 case UNSPEC_GOTOFF:
4476 output_addr_const (file, XVECEXP (x, 0, 0));
4477 fprintf (file, "@GOTOFF");
4478 return true;
4479 case UNSPEC_PLT:
4480 output_addr_const (file, XVECEXP (x, 0, 0));
4481 fprintf (file, "@PLT");
4482 return true;
4483 case UNSPEC_PLTOFF:
4484 output_addr_const (file, XVECEXP (x, 0, 0));
4485 fprintf (file, "@PLTOFF");
4486 return true;
4487 case UNSPEC_TLSGD:
4488 output_addr_const (file, XVECEXP (x, 0, 0));
4489 fprintf (file, "@TLSGD");
4490 return true;
4491 case UNSPEC_TLSLDM:
4492 assemble_name (file, get_some_local_dynamic_name ());
4493 fprintf (file, "@TLSLDM");
4494 return true;
4495 case UNSPEC_DTPOFF:
4496 output_addr_const (file, XVECEXP (x, 0, 0));
4497 fprintf (file, "@DTPOFF");
4498 return true;
4499 case UNSPEC_NTPOFF:
4500 output_addr_const (file, XVECEXP (x, 0, 0));
4501 fprintf (file, "@NTPOFF");
4502 return true;
4503 case UNSPEC_GOTNTPOFF:
4504 output_addr_const (file, XVECEXP (x, 0, 0));
4505 fprintf (file, "@GOTNTPOFF");
4506 return true;
4507 case UNSPEC_INDNTPOFF:
4508 output_addr_const (file, XVECEXP (x, 0, 0));
4509 fprintf (file, "@INDNTPOFF");
4510 return true;
4511 }
4512
4513 return false;
4514 }
4515
4516 /* Output address operand ADDR in assembler syntax to
4517 stdio stream FILE. */
4518
4519 void
4520 print_operand_address (FILE *file, rtx addr)
4521 {
4522 struct s390_address ad;
4523
4524 if (!s390_decompose_address (addr, &ad)
4525 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4526 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4527 output_operand_lossage ("cannot decompose address");
4528
4529 if (ad.disp)
4530 output_addr_const (file, ad.disp);
4531 else
4532 fprintf (file, "0");
4533
4534 if (ad.base && ad.indx)
4535 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4536 reg_names[REGNO (ad.base)]);
4537 else if (ad.base)
4538 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4539 }
4540
4541 /* Output operand X in assembler syntax to stdio stream FILE.
4542 CODE specified the format flag. The following format flags
4543 are recognized:
4544
4545 'C': print opcode suffix for branch condition.
4546 'D': print opcode suffix for inverse branch condition.
4547 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4548 'G': print the size of the operand in bytes.
4549 'O': print only the displacement of a memory reference.
4550 'R': print only the base register of a memory reference.
4551 'S': print S-type memory reference (base+displacement).
4552 'N': print the second word of a DImode operand.
4553 'M': print the second word of a TImode operand.
4554 'Y': print shift count operand.
4555
4556 'b': print integer X as if it's an unsigned byte.
4557 'x': print integer X as if it's an unsigned halfword.
4558 'h': print integer X as if it's a signed halfword.
4559 'i': print the first nonzero HImode part of X.
4560 'j': print the first HImode part unequal to -1 of X.
4561 'k': print the first nonzero SImode part of X.
4562 'm': print the first SImode part unequal to -1 of X.
4563 'o': print integer X as if it's an unsigned 32bit word. */
4564
4565 void
4566 print_operand (FILE *file, rtx x, int code)
4567 {
4568 switch (code)
4569 {
4570 case 'C':
4571 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4572 return;
4573
4574 case 'D':
4575 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4576 return;
4577
4578 case 'J':
4579 if (GET_CODE (x) == SYMBOL_REF)
4580 {
4581 fprintf (file, "%s", ":tls_load:");
4582 output_addr_const (file, x);
4583 }
4584 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4585 {
4586 fprintf (file, "%s", ":tls_gdcall:");
4587 output_addr_const (file, XVECEXP (x, 0, 0));
4588 }
4589 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4590 {
4591 fprintf (file, "%s", ":tls_ldcall:");
4592 assemble_name (file, get_some_local_dynamic_name ());
4593 }
4594 else
4595 gcc_unreachable ();
4596 return;
4597
4598 case 'G':
4599 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4600 return;
4601
4602 case 'O':
4603 {
4604 struct s390_address ad;
4605 int ret;
4606
4607 gcc_assert (GET_CODE (x) == MEM);
4608 ret = s390_decompose_address (XEXP (x, 0), &ad);
4609 gcc_assert (ret);
4610 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4611 gcc_assert (!ad.indx);
4612
4613 if (ad.disp)
4614 output_addr_const (file, ad.disp);
4615 else
4616 fprintf (file, "0");
4617 }
4618 return;
4619
4620 case 'R':
4621 {
4622 struct s390_address ad;
4623 int ret;
4624
4625 gcc_assert (GET_CODE (x) == MEM);
4626 ret = s390_decompose_address (XEXP (x, 0), &ad);
4627 gcc_assert (ret);
4628 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4629 gcc_assert (!ad.indx);
4630
4631 if (ad.base)
4632 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4633 else
4634 fprintf (file, "0");
4635 }
4636 return;
4637
4638 case 'S':
4639 {
4640 struct s390_address ad;
4641 int ret;
4642
4643 gcc_assert (GET_CODE (x) == MEM);
4644 ret = s390_decompose_address (XEXP (x, 0), &ad);
4645 gcc_assert (ret);
4646 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4647 gcc_assert (!ad.indx);
4648
4649 if (ad.disp)
4650 output_addr_const (file, ad.disp);
4651 else
4652 fprintf (file, "0");
4653
4654 if (ad.base)
4655 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4656 }
4657 return;
4658
4659 case 'N':
4660 if (GET_CODE (x) == REG)
4661 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4662 else if (GET_CODE (x) == MEM)
4663 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4664 else
4665 gcc_unreachable ();
4666 break;
4667
4668 case 'M':
4669 if (GET_CODE (x) == REG)
4670 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4671 else if (GET_CODE (x) == MEM)
4672 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4673 else
4674 gcc_unreachable ();
4675 break;
4676
4677 case 'Y':
4678 print_shift_count_operand (file, x);
4679 return;
4680 }
4681
4682 switch (GET_CODE (x))
4683 {
4684 case REG:
4685 fprintf (file, "%s", reg_names[REGNO (x)]);
4686 break;
4687
4688 case MEM:
4689 output_address (XEXP (x, 0));
4690 break;
4691
4692 case CONST:
4693 case CODE_LABEL:
4694 case LABEL_REF:
4695 case SYMBOL_REF:
4696 output_addr_const (file, x);
4697 break;
4698
4699 case CONST_INT:
4700 if (code == 'b')
4701 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4702 else if (code == 'x')
4703 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4704 else if (code == 'h')
4705 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4706 else if (code == 'i')
4707 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4708 s390_extract_part (x, HImode, 0));
4709 else if (code == 'j')
4710 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4711 s390_extract_part (x, HImode, -1));
4712 else if (code == 'k')
4713 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4714 s390_extract_part (x, SImode, 0));
4715 else if (code == 'm')
4716 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4717 s390_extract_part (x, SImode, -1));
4718 else if (code == 'o')
4719 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4720 else
4721 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4722 break;
4723
4724 case CONST_DOUBLE:
4725 gcc_assert (GET_MODE (x) == VOIDmode);
4726 if (code == 'b')
4727 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4728 else if (code == 'x')
4729 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4730 else if (code == 'h')
4731 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4732 else
4733 gcc_unreachable ();
4734 break;
4735
4736 default:
4737 fatal_insn ("UNKNOWN in print_operand !?", x);
4738 break;
4739 }
4740 }
4741
4742 /* Target hook for assembling integer objects. We need to define it
4743 here to work a round a bug in some versions of GAS, which couldn't
4744 handle values smaller than INT_MIN when printed in decimal. */
4745
4746 static bool
4747 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4748 {
4749 if (size == 8 && aligned_p
4750 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4751 {
4752 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4753 INTVAL (x));
4754 return true;
4755 }
4756 return default_assemble_integer (x, size, aligned_p);
4757 }
4758
4759 /* Returns true if register REGNO is used for forming
4760 a memory address in expression X. */
4761
4762 static bool
4763 reg_used_in_mem_p (int regno, rtx x)
4764 {
4765 enum rtx_code code = GET_CODE (x);
4766 int i, j;
4767 const char *fmt;
4768
4769 if (code == MEM)
4770 {
4771 if (refers_to_regno_p (regno, regno+1,
4772 XEXP (x, 0), 0))
4773 return true;
4774 }
4775 else if (code == SET
4776 && GET_CODE (SET_DEST (x)) == PC)
4777 {
4778 if (refers_to_regno_p (regno, regno+1,
4779 SET_SRC (x), 0))
4780 return true;
4781 }
4782
4783 fmt = GET_RTX_FORMAT (code);
4784 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4785 {
4786 if (fmt[i] == 'e'
4787 && reg_used_in_mem_p (regno, XEXP (x, i)))
4788 return true;
4789
4790 else if (fmt[i] == 'E')
4791 for (j = 0; j < XVECLEN (x, i); j++)
4792 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4793 return true;
4794 }
4795 return false;
4796 }
4797
4798 /* Returns true if expression DEP_RTX sets an address register
4799 used by instruction INSN to address memory. */
4800
4801 static bool
4802 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4803 {
4804 rtx target, pat;
4805
4806 if (GET_CODE (dep_rtx) == INSN)
4807 dep_rtx = PATTERN (dep_rtx);
4808
4809 if (GET_CODE (dep_rtx) == SET)
4810 {
4811 target = SET_DEST (dep_rtx);
4812 if (GET_CODE (target) == STRICT_LOW_PART)
4813 target = XEXP (target, 0);
4814 while (GET_CODE (target) == SUBREG)
4815 target = SUBREG_REG (target);
4816
4817 if (GET_CODE (target) == REG)
4818 {
4819 int regno = REGNO (target);
4820
4821 if (s390_safe_attr_type (insn) == TYPE_LA)
4822 {
4823 pat = PATTERN (insn);
4824 if (GET_CODE (pat) == PARALLEL)
4825 {
4826 gcc_assert (XVECLEN (pat, 0) == 2);
4827 pat = XVECEXP (pat, 0, 0);
4828 }
4829 gcc_assert (GET_CODE (pat) == SET);
4830 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4831 }
4832 else if (get_attr_atype (insn) == ATYPE_AGEN)
4833 return reg_used_in_mem_p (regno, PATTERN (insn));
4834 }
4835 }
4836 return false;
4837 }
4838
4839 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4840
4841 int
4842 s390_agen_dep_p (rtx dep_insn, rtx insn)
4843 {
4844 rtx dep_rtx = PATTERN (dep_insn);
4845 int i;
4846
4847 if (GET_CODE (dep_rtx) == SET
4848 && addr_generation_dependency_p (dep_rtx, insn))
4849 return 1;
4850 else if (GET_CODE (dep_rtx) == PARALLEL)
4851 {
4852 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4853 {
4854 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4855 return 1;
4856 }
4857 }
4858 return 0;
4859 }
4860
4861 /* A C statement (sans semicolon) to update the integer scheduling priority
4862 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4863 reduce the priority to execute INSN later. Do not define this macro if
4864 you do not need to adjust the scheduling priorities of insns.
4865
4866 A STD instruction should be scheduled earlier,
4867 in order to use the bypass. */
4868
4869 static int
4870 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4871 {
4872 if (! INSN_P (insn))
4873 return priority;
4874
4875 if (s390_tune != PROCESSOR_2084_Z990
4876 && s390_tune != PROCESSOR_2094_Z9_109)
4877 return priority;
4878
4879 switch (s390_safe_attr_type (insn))
4880 {
4881 case TYPE_FSTOREDF:
4882 case TYPE_FSTORESF:
4883 priority = priority << 3;
4884 break;
4885 case TYPE_STORE:
4886 case TYPE_STM:
4887 priority = priority << 1;
4888 break;
4889 default:
4890 break;
4891 }
4892 return priority;
4893 }
4894
4895 /* The number of instructions that can be issued per cycle. */
4896
4897 static int
4898 s390_issue_rate (void)
4899 {
4900 if (s390_tune == PROCESSOR_2084_Z990
4901 || s390_tune == PROCESSOR_2094_Z9_109)
4902 return 3;
4903 return 1;
4904 }
4905
4906 static int
4907 s390_first_cycle_multipass_dfa_lookahead (void)
4908 {
4909 return 4;
4910 }
4911
4912
4913 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4914 Fix up MEMs as required. */
4915
4916 static void
4917 annotate_constant_pool_refs (rtx *x)
4918 {
4919 int i, j;
4920 const char *fmt;
4921
4922 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4923 || !CONSTANT_POOL_ADDRESS_P (*x));
4924
4925 /* Literal pool references can only occur inside a MEM ... */
4926 if (GET_CODE (*x) == MEM)
4927 {
4928 rtx memref = XEXP (*x, 0);
4929
4930 if (GET_CODE (memref) == SYMBOL_REF
4931 && CONSTANT_POOL_ADDRESS_P (memref))
4932 {
4933 rtx base = cfun->machine->base_reg;
4934 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4935 UNSPEC_LTREF);
4936
4937 *x = replace_equiv_address (*x, addr);
4938 return;
4939 }
4940
4941 if (GET_CODE (memref) == CONST
4942 && GET_CODE (XEXP (memref, 0)) == PLUS
4943 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4944 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4945 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4946 {
4947 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4948 rtx sym = XEXP (XEXP (memref, 0), 0);
4949 rtx base = cfun->machine->base_reg;
4950 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4951 UNSPEC_LTREF);
4952
4953 *x = replace_equiv_address (*x, plus_constant (addr, off));
4954 return;
4955 }
4956 }
4957
4958 /* ... or a load-address type pattern. */
4959 if (GET_CODE (*x) == SET)
4960 {
4961 rtx addrref = SET_SRC (*x);
4962
4963 if (GET_CODE (addrref) == SYMBOL_REF
4964 && CONSTANT_POOL_ADDRESS_P (addrref))
4965 {
4966 rtx base = cfun->machine->base_reg;
4967 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4968 UNSPEC_LTREF);
4969
4970 SET_SRC (*x) = addr;
4971 return;
4972 }
4973
4974 if (GET_CODE (addrref) == CONST
4975 && GET_CODE (XEXP (addrref, 0)) == PLUS
4976 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4977 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4978 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4979 {
4980 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4981 rtx sym = XEXP (XEXP (addrref, 0), 0);
4982 rtx base = cfun->machine->base_reg;
4983 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4984 UNSPEC_LTREF);
4985
4986 SET_SRC (*x) = plus_constant (addr, off);
4987 return;
4988 }
4989 }
4990
4991 /* Annotate LTREL_BASE as well. */
4992 if (GET_CODE (*x) == UNSPEC
4993 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4994 {
4995 rtx base = cfun->machine->base_reg;
4996 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4997 UNSPEC_LTREL_BASE);
4998 return;
4999 }
5000
5001 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5002 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5003 {
5004 if (fmt[i] == 'e')
5005 {
5006 annotate_constant_pool_refs (&XEXP (*x, i));
5007 }
5008 else if (fmt[i] == 'E')
5009 {
5010 for (j = 0; j < XVECLEN (*x, i); j++)
5011 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5012 }
5013 }
5014 }
5015
5016 /* Split all branches that exceed the maximum distance.
5017 Returns true if this created a new literal pool entry. */
5018
5019 static int
5020 s390_split_branches (void)
5021 {
5022 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5023 int new_literal = 0, ret;
5024 rtx insn, pat, tmp, target;
5025 rtx *label;
5026
5027 /* We need correct insn addresses. */
5028
5029 shorten_branches (get_insns ());
5030
5031 /* Find all branches that exceed 64KB, and split them. */
5032
5033 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5034 {
5035 if (GET_CODE (insn) != JUMP_INSN)
5036 continue;
5037
5038 pat = PATTERN (insn);
5039 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5040 pat = XVECEXP (pat, 0, 0);
5041 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5042 continue;
5043
5044 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5045 {
5046 label = &SET_SRC (pat);
5047 }
5048 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5049 {
5050 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5051 label = &XEXP (SET_SRC (pat), 1);
5052 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5053 label = &XEXP (SET_SRC (pat), 2);
5054 else
5055 continue;
5056 }
5057 else
5058 continue;
5059
5060 if (get_attr_length (insn) <= 4)
5061 continue;
5062
5063 /* We are going to use the return register as scratch register,
5064 make sure it will be saved/restored by the prologue/epilogue. */
5065 cfun_frame_layout.save_return_addr_p = 1;
5066
5067 if (!flag_pic)
5068 {
5069 new_literal = 1;
5070 tmp = force_const_mem (Pmode, *label);
5071 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5072 INSN_ADDRESSES_NEW (tmp, -1);
5073 annotate_constant_pool_refs (&PATTERN (tmp));
5074
5075 target = temp_reg;
5076 }
5077 else
5078 {
5079 new_literal = 1;
5080 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5081 UNSPEC_LTREL_OFFSET);
5082 target = gen_rtx_CONST (Pmode, target);
5083 target = force_const_mem (Pmode, target);
5084 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5085 INSN_ADDRESSES_NEW (tmp, -1);
5086 annotate_constant_pool_refs (&PATTERN (tmp));
5087
5088 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5089 cfun->machine->base_reg),
5090 UNSPEC_LTREL_BASE);
5091 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5092 }
5093
5094 ret = validate_change (insn, label, target, 0);
5095 gcc_assert (ret);
5096 }
5097
5098 return new_literal;
5099 }
5100
5101
5102 /* Find an annotated literal pool symbol referenced in RTX X,
5103 and store it at REF. Will abort if X contains references to
5104 more than one such pool symbol; multiple references to the same
5105 symbol are allowed, however.
5106
5107 The rtx pointed to by REF must be initialized to NULL_RTX
5108 by the caller before calling this routine. */
5109
5110 static void
5111 find_constant_pool_ref (rtx x, rtx *ref)
5112 {
5113 int i, j;
5114 const char *fmt;
5115
5116 /* Ignore LTREL_BASE references. */
5117 if (GET_CODE (x) == UNSPEC
5118 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5119 return;
5120 /* Likewise POOL_ENTRY insns. */
5121 if (GET_CODE (x) == UNSPEC_VOLATILE
5122 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5123 return;
5124
5125 gcc_assert (GET_CODE (x) != SYMBOL_REF
5126 || !CONSTANT_POOL_ADDRESS_P (x));
5127
5128 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5129 {
5130 rtx sym = XVECEXP (x, 0, 0);
5131 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5132 && CONSTANT_POOL_ADDRESS_P (sym));
5133
5134 if (*ref == NULL_RTX)
5135 *ref = sym;
5136 else
5137 gcc_assert (*ref == sym);
5138
5139 return;
5140 }
5141
5142 fmt = GET_RTX_FORMAT (GET_CODE (x));
5143 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5144 {
5145 if (fmt[i] == 'e')
5146 {
5147 find_constant_pool_ref (XEXP (x, i), ref);
5148 }
5149 else if (fmt[i] == 'E')
5150 {
5151 for (j = 0; j < XVECLEN (x, i); j++)
5152 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5153 }
5154 }
5155 }
5156
5157 /* Replace every reference to the annotated literal pool
5158 symbol REF in X by its base plus OFFSET. */
5159
5160 static void
5161 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5162 {
5163 int i, j;
5164 const char *fmt;
5165
5166 gcc_assert (*x != ref);
5167
5168 if (GET_CODE (*x) == UNSPEC
5169 && XINT (*x, 1) == UNSPEC_LTREF
5170 && XVECEXP (*x, 0, 0) == ref)
5171 {
5172 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5173 return;
5174 }
5175
5176 if (GET_CODE (*x) == PLUS
5177 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5178 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5179 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5180 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5181 {
5182 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5183 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5184 return;
5185 }
5186
5187 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5188 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5189 {
5190 if (fmt[i] == 'e')
5191 {
5192 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5193 }
5194 else if (fmt[i] == 'E')
5195 {
5196 for (j = 0; j < XVECLEN (*x, i); j++)
5197 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5198 }
5199 }
5200 }
5201
5202 /* Check whether X contains an UNSPEC_LTREL_BASE.
5203 Return its constant pool symbol if found, NULL_RTX otherwise. */
5204
5205 static rtx
5206 find_ltrel_base (rtx x)
5207 {
5208 int i, j;
5209 const char *fmt;
5210
5211 if (GET_CODE (x) == UNSPEC
5212 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5213 return XVECEXP (x, 0, 0);
5214
5215 fmt = GET_RTX_FORMAT (GET_CODE (x));
5216 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5217 {
5218 if (fmt[i] == 'e')
5219 {
5220 rtx fnd = find_ltrel_base (XEXP (x, i));
5221 if (fnd)
5222 return fnd;
5223 }
5224 else if (fmt[i] == 'E')
5225 {
5226 for (j = 0; j < XVECLEN (x, i); j++)
5227 {
5228 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5229 if (fnd)
5230 return fnd;
5231 }
5232 }
5233 }
5234
5235 return NULL_RTX;
5236 }
5237
5238 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5239
5240 static void
5241 replace_ltrel_base (rtx *x)
5242 {
5243 int i, j;
5244 const char *fmt;
5245
5246 if (GET_CODE (*x) == UNSPEC
5247 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5248 {
5249 *x = XVECEXP (*x, 0, 1);
5250 return;
5251 }
5252
5253 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5254 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5255 {
5256 if (fmt[i] == 'e')
5257 {
5258 replace_ltrel_base (&XEXP (*x, i));
5259 }
5260 else if (fmt[i] == 'E')
5261 {
5262 for (j = 0; j < XVECLEN (*x, i); j++)
5263 replace_ltrel_base (&XVECEXP (*x, i, j));
5264 }
5265 }
5266 }
5267
5268
5269 /* We keep a list of constants which we have to add to internal
5270 constant tables in the middle of large functions. */
5271
5272 #define NR_C_MODES 11
5273 enum machine_mode constant_modes[NR_C_MODES] =
5274 {
5275 TFmode, TImode, TDmode,
5276 DFmode, DImode, DDmode,
5277 SFmode, SImode, SDmode,
5278 HImode,
5279 QImode
5280 };
5281
5282 struct constant
5283 {
5284 struct constant *next;
5285 rtx value;
5286 rtx label;
5287 };
5288
5289 struct constant_pool
5290 {
5291 struct constant_pool *next;
5292 rtx first_insn;
5293 rtx pool_insn;
5294 bitmap insns;
5295
5296 struct constant *constants[NR_C_MODES];
5297 struct constant *execute;
5298 rtx label;
5299 int size;
5300 };
5301
5302 /* Allocate new constant_pool structure. */
5303
5304 static struct constant_pool *
5305 s390_alloc_pool (void)
5306 {
5307 struct constant_pool *pool;
5308 int i;
5309
5310 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5311 pool->next = NULL;
5312 for (i = 0; i < NR_C_MODES; i++)
5313 pool->constants[i] = NULL;
5314
5315 pool->execute = NULL;
5316 pool->label = gen_label_rtx ();
5317 pool->first_insn = NULL_RTX;
5318 pool->pool_insn = NULL_RTX;
5319 pool->insns = BITMAP_ALLOC (NULL);
5320 pool->size = 0;
5321
5322 return pool;
5323 }
5324
5325 /* Create new constant pool covering instructions starting at INSN
5326 and chain it to the end of POOL_LIST. */
5327
5328 static struct constant_pool *
5329 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5330 {
5331 struct constant_pool *pool, **prev;
5332
5333 pool = s390_alloc_pool ();
5334 pool->first_insn = insn;
5335
5336 for (prev = pool_list; *prev; prev = &(*prev)->next)
5337 ;
5338 *prev = pool;
5339
5340 return pool;
5341 }
5342
5343 /* End range of instructions covered by POOL at INSN and emit
5344 placeholder insn representing the pool. */
5345
5346 static void
5347 s390_end_pool (struct constant_pool *pool, rtx insn)
5348 {
5349 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5350
5351 if (!insn)
5352 insn = get_last_insn ();
5353
5354 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5355 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5356 }
5357
5358 /* Add INSN to the list of insns covered by POOL. */
5359
5360 static void
5361 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5362 {
5363 bitmap_set_bit (pool->insns, INSN_UID (insn));
5364 }
5365
5366 /* Return pool out of POOL_LIST that covers INSN. */
5367
5368 static struct constant_pool *
5369 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5370 {
5371 struct constant_pool *pool;
5372
5373 for (pool = pool_list; pool; pool = pool->next)
5374 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5375 break;
5376
5377 return pool;
5378 }
5379
5380 /* Add constant VAL of mode MODE to the constant pool POOL. */
5381
5382 static void
5383 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5384 {
5385 struct constant *c;
5386 int i;
5387
5388 for (i = 0; i < NR_C_MODES; i++)
5389 if (constant_modes[i] == mode)
5390 break;
5391 gcc_assert (i != NR_C_MODES);
5392
5393 for (c = pool->constants[i]; c != NULL; c = c->next)
5394 if (rtx_equal_p (val, c->value))
5395 break;
5396
5397 if (c == NULL)
5398 {
5399 c = (struct constant *) xmalloc (sizeof *c);
5400 c->value = val;
5401 c->label = gen_label_rtx ();
5402 c->next = pool->constants[i];
5403 pool->constants[i] = c;
5404 pool->size += GET_MODE_SIZE (mode);
5405 }
5406 }
5407
5408 /* Find constant VAL of mode MODE in the constant pool POOL.
5409 Return an RTX describing the distance from the start of
5410 the pool to the location of the new constant. */
5411
5412 static rtx
5413 s390_find_constant (struct constant_pool *pool, rtx val,
5414 enum machine_mode mode)
5415 {
5416 struct constant *c;
5417 rtx offset;
5418 int i;
5419
5420 for (i = 0; i < NR_C_MODES; i++)
5421 if (constant_modes[i] == mode)
5422 break;
5423 gcc_assert (i != NR_C_MODES);
5424
5425 for (c = pool->constants[i]; c != NULL; c = c->next)
5426 if (rtx_equal_p (val, c->value))
5427 break;
5428
5429 gcc_assert (c);
5430
5431 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5432 gen_rtx_LABEL_REF (Pmode, pool->label));
5433 offset = gen_rtx_CONST (Pmode, offset);
5434 return offset;
5435 }
5436
5437 /* Check whether INSN is an execute. Return the label_ref to its
5438 execute target template if so, NULL_RTX otherwise. */
5439
5440 static rtx
5441 s390_execute_label (rtx insn)
5442 {
5443 if (GET_CODE (insn) == INSN
5444 && GET_CODE (PATTERN (insn)) == PARALLEL
5445 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5446 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5447 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5448
5449 return NULL_RTX;
5450 }
5451
5452 /* Add execute target for INSN to the constant pool POOL. */
5453
5454 static void
5455 s390_add_execute (struct constant_pool *pool, rtx insn)
5456 {
5457 struct constant *c;
5458
5459 for (c = pool->execute; c != NULL; c = c->next)
5460 if (INSN_UID (insn) == INSN_UID (c->value))
5461 break;
5462
5463 if (c == NULL)
5464 {
5465 c = (struct constant *) xmalloc (sizeof *c);
5466 c->value = insn;
5467 c->label = gen_label_rtx ();
5468 c->next = pool->execute;
5469 pool->execute = c;
5470 pool->size += 6;
5471 }
5472 }
5473
5474 /* Find execute target for INSN in the constant pool POOL.
5475 Return an RTX describing the distance from the start of
5476 the pool to the location of the execute target. */
5477
5478 static rtx
5479 s390_find_execute (struct constant_pool *pool, rtx insn)
5480 {
5481 struct constant *c;
5482 rtx offset;
5483
5484 for (c = pool->execute; c != NULL; c = c->next)
5485 if (INSN_UID (insn) == INSN_UID (c->value))
5486 break;
5487
5488 gcc_assert (c);
5489
5490 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5491 gen_rtx_LABEL_REF (Pmode, pool->label));
5492 offset = gen_rtx_CONST (Pmode, offset);
5493 return offset;
5494 }
5495
5496 /* For an execute INSN, extract the execute target template. */
5497
5498 static rtx
5499 s390_execute_target (rtx insn)
5500 {
5501 rtx pattern = PATTERN (insn);
5502 gcc_assert (s390_execute_label (insn));
5503
5504 if (XVECLEN (pattern, 0) == 2)
5505 {
5506 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5507 }
5508 else
5509 {
5510 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5511 int i;
5512
5513 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5514 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5515
5516 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5517 }
5518
5519 return pattern;
5520 }
5521
5522 /* Indicate that INSN cannot be duplicated. This is the case for
5523 execute insns that carry a unique label. */
5524
5525 static bool
5526 s390_cannot_copy_insn_p (rtx insn)
5527 {
5528 rtx label = s390_execute_label (insn);
5529 return label && label != const0_rtx;
5530 }
5531
5532 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5533 do not emit the pool base label. */
5534
5535 static void
5536 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5537 {
5538 struct constant *c;
5539 rtx insn = pool->pool_insn;
5540 int i;
5541
5542 /* Switch to rodata section. */
5543 if (TARGET_CPU_ZARCH)
5544 {
5545 insn = emit_insn_after (gen_pool_section_start (), insn);
5546 INSN_ADDRESSES_NEW (insn, -1);
5547 }
5548
5549 /* Ensure minimum pool alignment. */
5550 if (TARGET_CPU_ZARCH)
5551 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5552 else
5553 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5554 INSN_ADDRESSES_NEW (insn, -1);
5555
5556 /* Emit pool base label. */
5557 if (!remote_label)
5558 {
5559 insn = emit_label_after (pool->label, insn);
5560 INSN_ADDRESSES_NEW (insn, -1);
5561 }
5562
5563 /* Dump constants in descending alignment requirement order,
5564 ensuring proper alignment for every constant. */
5565 for (i = 0; i < NR_C_MODES; i++)
5566 for (c = pool->constants[i]; c; c = c->next)
5567 {
5568 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5569 rtx value = c->value;
5570 if (GET_CODE (value) == CONST
5571 && GET_CODE (XEXP (value, 0)) == UNSPEC
5572 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5573 && XVECLEN (XEXP (value, 0), 0) == 1)
5574 {
5575 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5576 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5577 value = gen_rtx_CONST (VOIDmode, value);
5578 }
5579
5580 insn = emit_label_after (c->label, insn);
5581 INSN_ADDRESSES_NEW (insn, -1);
5582
5583 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5584 gen_rtvec (1, value),
5585 UNSPECV_POOL_ENTRY);
5586 insn = emit_insn_after (value, insn);
5587 INSN_ADDRESSES_NEW (insn, -1);
5588 }
5589
5590 /* Ensure minimum alignment for instructions. */
5591 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5592 INSN_ADDRESSES_NEW (insn, -1);
5593
5594 /* Output in-pool execute template insns. */
5595 for (c = pool->execute; c; c = c->next)
5596 {
5597 insn = emit_label_after (c->label, insn);
5598 INSN_ADDRESSES_NEW (insn, -1);
5599
5600 insn = emit_insn_after (s390_execute_target (c->value), insn);
5601 INSN_ADDRESSES_NEW (insn, -1);
5602 }
5603
5604 /* Switch back to previous section. */
5605 if (TARGET_CPU_ZARCH)
5606 {
5607 insn = emit_insn_after (gen_pool_section_end (), insn);
5608 INSN_ADDRESSES_NEW (insn, -1);
5609 }
5610
5611 insn = emit_barrier_after (insn);
5612 INSN_ADDRESSES_NEW (insn, -1);
5613
5614 /* Remove placeholder insn. */
5615 remove_insn (pool->pool_insn);
5616 }
5617
5618 /* Free all memory used by POOL. */
5619
5620 static void
5621 s390_free_pool (struct constant_pool *pool)
5622 {
5623 struct constant *c, *next;
5624 int i;
5625
5626 for (i = 0; i < NR_C_MODES; i++)
5627 for (c = pool->constants[i]; c; c = next)
5628 {
5629 next = c->next;
5630 free (c);
5631 }
5632
5633 for (c = pool->execute; c; c = next)
5634 {
5635 next = c->next;
5636 free (c);
5637 }
5638
5639 BITMAP_FREE (pool->insns);
5640 free (pool);
5641 }
5642
5643
5644 /* Collect main literal pool. Return NULL on overflow. */
5645
5646 static struct constant_pool *
5647 s390_mainpool_start (void)
5648 {
5649 struct constant_pool *pool;
5650 rtx insn;
5651
5652 pool = s390_alloc_pool ();
5653
5654 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5655 {
5656 if (GET_CODE (insn) == INSN
5657 && GET_CODE (PATTERN (insn)) == SET
5658 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5659 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5660 {
5661 gcc_assert (!pool->pool_insn);
5662 pool->pool_insn = insn;
5663 }
5664
5665 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5666 {
5667 s390_add_execute (pool, insn);
5668 }
5669 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5670 {
5671 rtx pool_ref = NULL_RTX;
5672 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5673 if (pool_ref)
5674 {
5675 rtx constant = get_pool_constant (pool_ref);
5676 enum machine_mode mode = get_pool_mode (pool_ref);
5677 s390_add_constant (pool, constant, mode);
5678 }
5679 }
5680 }
5681
5682 gcc_assert (pool->pool_insn || pool->size == 0);
5683
5684 if (pool->size >= 4096)
5685 {
5686 /* We're going to chunkify the pool, so remove the main
5687 pool placeholder insn. */
5688 remove_insn (pool->pool_insn);
5689
5690 s390_free_pool (pool);
5691 pool = NULL;
5692 }
5693
5694 return pool;
5695 }
5696
5697 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5698 Modify the current function to output the pool constants as well as
5699 the pool register setup instruction. */
5700
5701 static void
5702 s390_mainpool_finish (struct constant_pool *pool)
5703 {
5704 rtx base_reg = cfun->machine->base_reg;
5705 rtx insn;
5706
5707 /* If the pool is empty, we're done. */
5708 if (pool->size == 0)
5709 {
5710 /* We don't actually need a base register after all. */
5711 cfun->machine->base_reg = NULL_RTX;
5712
5713 if (pool->pool_insn)
5714 remove_insn (pool->pool_insn);
5715 s390_free_pool (pool);
5716 return;
5717 }
5718
5719 /* We need correct insn addresses. */
5720 shorten_branches (get_insns ());
5721
5722 /* On zSeries, we use a LARL to load the pool register. The pool is
5723 located in the .rodata section, so we emit it after the function. */
5724 if (TARGET_CPU_ZARCH)
5725 {
5726 insn = gen_main_base_64 (base_reg, pool->label);
5727 insn = emit_insn_after (insn, pool->pool_insn);
5728 INSN_ADDRESSES_NEW (insn, -1);
5729 remove_insn (pool->pool_insn);
5730
5731 insn = get_last_insn ();
5732 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5733 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5734
5735 s390_dump_pool (pool, 0);
5736 }
5737
5738 /* On S/390, if the total size of the function's code plus literal pool
5739 does not exceed 4096 bytes, we use BASR to set up a function base
5740 pointer, and emit the literal pool at the end of the function. */
5741 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5742 + pool->size + 8 /* alignment slop */ < 4096)
5743 {
5744 insn = gen_main_base_31_small (base_reg, pool->label);
5745 insn = emit_insn_after (insn, pool->pool_insn);
5746 INSN_ADDRESSES_NEW (insn, -1);
5747 remove_insn (pool->pool_insn);
5748
5749 insn = emit_label_after (pool->label, insn);
5750 INSN_ADDRESSES_NEW (insn, -1);
5751
5752 insn = get_last_insn ();
5753 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5754 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5755
5756 s390_dump_pool (pool, 1);
5757 }
5758
5759 /* Otherwise, we emit an inline literal pool and use BASR to branch
5760 over it, setting up the pool register at the same time. */
5761 else
5762 {
5763 rtx pool_end = gen_label_rtx ();
5764
5765 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5766 insn = emit_insn_after (insn, pool->pool_insn);
5767 INSN_ADDRESSES_NEW (insn, -1);
5768 remove_insn (pool->pool_insn);
5769
5770 insn = emit_label_after (pool->label, insn);
5771 INSN_ADDRESSES_NEW (insn, -1);
5772
5773 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5774 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5775
5776 insn = emit_label_after (pool_end, pool->pool_insn);
5777 INSN_ADDRESSES_NEW (insn, -1);
5778
5779 s390_dump_pool (pool, 1);
5780 }
5781
5782
5783 /* Replace all literal pool references. */
5784
5785 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5786 {
5787 if (INSN_P (insn))
5788 replace_ltrel_base (&PATTERN (insn));
5789
5790 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5791 {
5792 rtx addr, pool_ref = NULL_RTX;
5793 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5794 if (pool_ref)
5795 {
5796 if (s390_execute_label (insn))
5797 addr = s390_find_execute (pool, insn);
5798 else
5799 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5800 get_pool_mode (pool_ref));
5801
5802 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5803 INSN_CODE (insn) = -1;
5804 }
5805 }
5806 }
5807
5808
5809 /* Free the pool. */
5810 s390_free_pool (pool);
5811 }
5812
5813 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5814 We have decided we cannot use this pool, so revert all changes
5815 to the current function that were done by s390_mainpool_start. */
5816 static void
5817 s390_mainpool_cancel (struct constant_pool *pool)
5818 {
5819 /* We didn't actually change the instruction stream, so simply
5820 free the pool memory. */
5821 s390_free_pool (pool);
5822 }
5823
5824
5825 /* Chunkify the literal pool. */
5826
5827 #define S390_POOL_CHUNK_MIN 0xc00
5828 #define S390_POOL_CHUNK_MAX 0xe00
5829
5830 static struct constant_pool *
5831 s390_chunkify_start (void)
5832 {
5833 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5834 int extra_size = 0;
5835 bitmap far_labels;
5836 rtx pending_ltrel = NULL_RTX;
5837 rtx insn;
5838
5839 rtx (*gen_reload_base) (rtx, rtx) =
5840 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5841
5842
5843 /* We need correct insn addresses. */
5844
5845 shorten_branches (get_insns ());
5846
5847 /* Scan all insns and move literals to pool chunks. */
5848
5849 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5850 {
5851 /* Check for pending LTREL_BASE. */
5852 if (INSN_P (insn))
5853 {
5854 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5855 if (ltrel_base)
5856 {
5857 gcc_assert (ltrel_base == pending_ltrel);
5858 pending_ltrel = NULL_RTX;
5859 }
5860 }
5861
5862 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5863 {
5864 if (!curr_pool)
5865 curr_pool = s390_start_pool (&pool_list, insn);
5866
5867 s390_add_execute (curr_pool, insn);
5868 s390_add_pool_insn (curr_pool, insn);
5869 }
5870 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5871 {
5872 rtx pool_ref = NULL_RTX;
5873 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5874 if (pool_ref)
5875 {
5876 rtx constant = get_pool_constant (pool_ref);
5877 enum machine_mode mode = get_pool_mode (pool_ref);
5878
5879 if (!curr_pool)
5880 curr_pool = s390_start_pool (&pool_list, insn);
5881
5882 s390_add_constant (curr_pool, constant, mode);
5883 s390_add_pool_insn (curr_pool, insn);
5884
5885 /* Don't split the pool chunk between a LTREL_OFFSET load
5886 and the corresponding LTREL_BASE. */
5887 if (GET_CODE (constant) == CONST
5888 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5889 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5890 {
5891 gcc_assert (!pending_ltrel);
5892 pending_ltrel = pool_ref;
5893 }
5894 }
5895 }
5896
5897 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5898 {
5899 if (curr_pool)
5900 s390_add_pool_insn (curr_pool, insn);
5901 /* An LTREL_BASE must follow within the same basic block. */
5902 gcc_assert (!pending_ltrel);
5903 }
5904
5905 if (!curr_pool
5906 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5907 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5908 continue;
5909
5910 if (TARGET_CPU_ZARCH)
5911 {
5912 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5913 continue;
5914
5915 s390_end_pool (curr_pool, NULL_RTX);
5916 curr_pool = NULL;
5917 }
5918 else
5919 {
5920 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5921 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5922 + extra_size;
5923
5924 /* We will later have to insert base register reload insns.
5925 Those will have an effect on code size, which we need to
5926 consider here. This calculation makes rather pessimistic
5927 worst-case assumptions. */
5928 if (GET_CODE (insn) == CODE_LABEL)
5929 extra_size += 6;
5930
5931 if (chunk_size < S390_POOL_CHUNK_MIN
5932 && curr_pool->size < S390_POOL_CHUNK_MIN)
5933 continue;
5934
5935 /* Pool chunks can only be inserted after BARRIERs ... */
5936 if (GET_CODE (insn) == BARRIER)
5937 {
5938 s390_end_pool (curr_pool, insn);
5939 curr_pool = NULL;
5940 extra_size = 0;
5941 }
5942
5943 /* ... so if we don't find one in time, create one. */
5944 else if ((chunk_size > S390_POOL_CHUNK_MAX
5945 || curr_pool->size > S390_POOL_CHUNK_MAX))
5946 {
5947 rtx label, jump, barrier;
5948
5949 /* We can insert the barrier only after a 'real' insn. */
5950 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5951 continue;
5952 if (get_attr_length (insn) == 0)
5953 continue;
5954
5955 /* Don't separate LTREL_BASE from the corresponding
5956 LTREL_OFFSET load. */
5957 if (pending_ltrel)
5958 continue;
5959
5960 label = gen_label_rtx ();
5961 jump = emit_jump_insn_after (gen_jump (label), insn);
5962 barrier = emit_barrier_after (jump);
5963 insn = emit_label_after (label, barrier);
5964 JUMP_LABEL (jump) = label;
5965 LABEL_NUSES (label) = 1;
5966
5967 INSN_ADDRESSES_NEW (jump, -1);
5968 INSN_ADDRESSES_NEW (barrier, -1);
5969 INSN_ADDRESSES_NEW (insn, -1);
5970
5971 s390_end_pool (curr_pool, barrier);
5972 curr_pool = NULL;
5973 extra_size = 0;
5974 }
5975 }
5976 }
5977
5978 if (curr_pool)
5979 s390_end_pool (curr_pool, NULL_RTX);
5980 gcc_assert (!pending_ltrel);
5981
5982 /* Find all labels that are branched into
5983 from an insn belonging to a different chunk. */
5984
5985 far_labels = BITMAP_ALLOC (NULL);
5986
5987 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5988 {
5989 /* Labels marked with LABEL_PRESERVE_P can be target
5990 of non-local jumps, so we have to mark them.
5991 The same holds for named labels.
5992
5993 Don't do that, however, if it is the label before
5994 a jump table. */
5995
5996 if (GET_CODE (insn) == CODE_LABEL
5997 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5998 {
5999 rtx vec_insn = next_real_insn (insn);
6000 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6001 PATTERN (vec_insn) : NULL_RTX;
6002 if (!vec_pat
6003 || !(GET_CODE (vec_pat) == ADDR_VEC
6004 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6005 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6006 }
6007
6008 /* If we have a direct jump (conditional or unconditional)
6009 or a casesi jump, check all potential targets. */
6010 else if (GET_CODE (insn) == JUMP_INSN)
6011 {
6012 rtx pat = PATTERN (insn);
6013 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6014 pat = XVECEXP (pat, 0, 0);
6015
6016 if (GET_CODE (pat) == SET)
6017 {
6018 rtx label = JUMP_LABEL (insn);
6019 if (label)
6020 {
6021 if (s390_find_pool (pool_list, label)
6022 != s390_find_pool (pool_list, insn))
6023 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6024 }
6025 }
6026 else if (GET_CODE (pat) == PARALLEL
6027 && XVECLEN (pat, 0) == 2
6028 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6029 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6030 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6031 {
6032 /* Find the jump table used by this casesi jump. */
6033 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6034 rtx vec_insn = next_real_insn (vec_label);
6035 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6036 PATTERN (vec_insn) : NULL_RTX;
6037 if (vec_pat
6038 && (GET_CODE (vec_pat) == ADDR_VEC
6039 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6040 {
6041 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6042
6043 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6044 {
6045 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6046
6047 if (s390_find_pool (pool_list, label)
6048 != s390_find_pool (pool_list, insn))
6049 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6050 }
6051 }
6052 }
6053 }
6054 }
6055
6056 /* Insert base register reload insns before every pool. */
6057
6058 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6059 {
6060 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6061 curr_pool->label);
6062 rtx insn = curr_pool->first_insn;
6063 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6064 }
6065
6066 /* Insert base register reload insns at every far label. */
6067
6068 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6069 if (GET_CODE (insn) == CODE_LABEL
6070 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6071 {
6072 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6073 if (pool)
6074 {
6075 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6076 pool->label);
6077 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6078 }
6079 }
6080
6081
6082 BITMAP_FREE (far_labels);
6083
6084
6085 /* Recompute insn addresses. */
6086
6087 init_insn_lengths ();
6088 shorten_branches (get_insns ());
6089
6090 return pool_list;
6091 }
6092
6093 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6094 After we have decided to use this list, finish implementing
6095 all changes to the current function as required. */
6096
6097 static void
6098 s390_chunkify_finish (struct constant_pool *pool_list)
6099 {
6100 struct constant_pool *curr_pool = NULL;
6101 rtx insn;
6102
6103
6104 /* Replace all literal pool references. */
6105
6106 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6107 {
6108 if (INSN_P (insn))
6109 replace_ltrel_base (&PATTERN (insn));
6110
6111 curr_pool = s390_find_pool (pool_list, insn);
6112 if (!curr_pool)
6113 continue;
6114
6115 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6116 {
6117 rtx addr, pool_ref = NULL_RTX;
6118 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6119 if (pool_ref)
6120 {
6121 if (s390_execute_label (insn))
6122 addr = s390_find_execute (curr_pool, insn);
6123 else
6124 addr = s390_find_constant (curr_pool,
6125 get_pool_constant (pool_ref),
6126 get_pool_mode (pool_ref));
6127
6128 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6129 INSN_CODE (insn) = -1;
6130 }
6131 }
6132 }
6133
6134 /* Dump out all literal pools. */
6135
6136 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6137 s390_dump_pool (curr_pool, 0);
6138
6139 /* Free pool list. */
6140
6141 while (pool_list)
6142 {
6143 struct constant_pool *next = pool_list->next;
6144 s390_free_pool (pool_list);
6145 pool_list = next;
6146 }
6147 }
6148
6149 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6150 We have decided we cannot use this list, so revert all changes
6151 to the current function that were done by s390_chunkify_start. */
6152
6153 static void
6154 s390_chunkify_cancel (struct constant_pool *pool_list)
6155 {
6156 struct constant_pool *curr_pool = NULL;
6157 rtx insn;
6158
6159 /* Remove all pool placeholder insns. */
6160
6161 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6162 {
6163 /* Did we insert an extra barrier? Remove it. */
6164 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6165 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6166 rtx label = NEXT_INSN (curr_pool->pool_insn);
6167
6168 if (jump && GET_CODE (jump) == JUMP_INSN
6169 && barrier && GET_CODE (barrier) == BARRIER
6170 && label && GET_CODE (label) == CODE_LABEL
6171 && GET_CODE (PATTERN (jump)) == SET
6172 && SET_DEST (PATTERN (jump)) == pc_rtx
6173 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6174 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6175 {
6176 remove_insn (jump);
6177 remove_insn (barrier);
6178 remove_insn (label);
6179 }
6180
6181 remove_insn (curr_pool->pool_insn);
6182 }
6183
6184 /* Remove all base register reload insns. */
6185
6186 for (insn = get_insns (); insn; )
6187 {
6188 rtx next_insn = NEXT_INSN (insn);
6189
6190 if (GET_CODE (insn) == INSN
6191 && GET_CODE (PATTERN (insn)) == SET
6192 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6193 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6194 remove_insn (insn);
6195
6196 insn = next_insn;
6197 }
6198
6199 /* Free pool list. */
6200
6201 while (pool_list)
6202 {
6203 struct constant_pool *next = pool_list->next;
6204 s390_free_pool (pool_list);
6205 pool_list = next;
6206 }
6207 }
6208
6209
6210 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6211
6212 void
6213 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6214 {
6215 REAL_VALUE_TYPE r;
6216
6217 switch (GET_MODE_CLASS (mode))
6218 {
6219 case MODE_FLOAT:
6220 case MODE_DECIMAL_FLOAT:
6221 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6222
6223 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6224 assemble_real (r, mode, align);
6225 break;
6226
6227 case MODE_INT:
6228 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6229 break;
6230
6231 default:
6232 gcc_unreachable ();
6233 }
6234 }
6235
6236
6237 /* Return an RTL expression representing the value of the return address
6238 for the frame COUNT steps up from the current frame. FRAME is the
6239 frame pointer of that frame. */
6240
6241 rtx
6242 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6243 {
6244 int offset;
6245 rtx addr;
6246
6247 /* Without backchain, we fail for all but the current frame. */
6248
6249 if (!TARGET_BACKCHAIN && count > 0)
6250 return NULL_RTX;
6251
6252 /* For the current frame, we need to make sure the initial
6253 value of RETURN_REGNUM is actually saved. */
6254
6255 if (count == 0)
6256 {
6257 /* On non-z architectures branch splitting could overwrite r14. */
6258 if (TARGET_CPU_ZARCH)
6259 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6260 else
6261 {
6262 cfun_frame_layout.save_return_addr_p = true;
6263 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6264 }
6265 }
6266
6267 if (TARGET_PACKED_STACK)
6268 offset = -2 * UNITS_PER_WORD;
6269 else
6270 offset = RETURN_REGNUM * UNITS_PER_WORD;
6271
6272 addr = plus_constant (frame, offset);
6273 addr = memory_address (Pmode, addr);
6274 return gen_rtx_MEM (Pmode, addr);
6275 }
6276
6277 /* Return an RTL expression representing the back chain stored in
6278 the current stack frame. */
6279
6280 rtx
6281 s390_back_chain_rtx (void)
6282 {
6283 rtx chain;
6284
6285 gcc_assert (TARGET_BACKCHAIN);
6286
6287 if (TARGET_PACKED_STACK)
6288 chain = plus_constant (stack_pointer_rtx,
6289 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6290 else
6291 chain = stack_pointer_rtx;
6292
6293 chain = gen_rtx_MEM (Pmode, chain);
6294 return chain;
6295 }
6296
6297 /* Find first call clobbered register unused in a function.
6298 This could be used as base register in a leaf function
6299 or for holding the return address before epilogue. */
6300
6301 static int
6302 find_unused_clobbered_reg (void)
6303 {
6304 int i;
6305 for (i = 0; i < 6; i++)
6306 if (!regs_ever_live[i])
6307 return i;
6308 return 0;
6309 }
6310
6311
6312 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6313 clobbered hard regs in SETREG. */
6314
6315 static void
6316 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6317 {
6318 int *regs_ever_clobbered = (int *)data;
6319 unsigned int i, regno;
6320 enum machine_mode mode = GET_MODE (setreg);
6321
6322 if (GET_CODE (setreg) == SUBREG)
6323 {
6324 rtx inner = SUBREG_REG (setreg);
6325 if (!GENERAL_REG_P (inner))
6326 return;
6327 regno = subreg_regno (setreg);
6328 }
6329 else if (GENERAL_REG_P (setreg))
6330 regno = REGNO (setreg);
6331 else
6332 return;
6333
6334 for (i = regno;
6335 i < regno + HARD_REGNO_NREGS (regno, mode);
6336 i++)
6337 regs_ever_clobbered[i] = 1;
6338 }
6339
6340 /* Walks through all basic blocks of the current function looking
6341 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6342 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6343 each of those regs. */
6344
6345 static void
6346 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6347 {
6348 basic_block cur_bb;
6349 rtx cur_insn;
6350 unsigned int i;
6351
6352 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6353
6354 /* For non-leaf functions we have to consider all call clobbered regs to be
6355 clobbered. */
6356 if (!current_function_is_leaf)
6357 {
6358 for (i = 0; i < 16; i++)
6359 regs_ever_clobbered[i] = call_really_used_regs[i];
6360 }
6361
6362 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6363 this work is done by liveness analysis (mark_regs_live_at_end).
6364 Special care is needed for functions containing landing pads. Landing pads
6365 may use the eh registers, but the code which sets these registers is not
6366 contained in that function. Hence s390_regs_ever_clobbered is not able to
6367 deal with this automatically. */
6368 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6369 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6370 if (current_function_calls_eh_return
6371 || (cfun->machine->has_landing_pad_p
6372 && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6373 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6374
6375 /* For nonlocal gotos all call-saved registers have to be saved.
6376 This flag is also set for the unwinding code in libgcc.
6377 See expand_builtin_unwind_init. For regs_ever_live this is done by
6378 reload. */
6379 if (current_function_has_nonlocal_label)
6380 for (i = 0; i < 16; i++)
6381 if (!call_really_used_regs[i])
6382 regs_ever_clobbered[i] = 1;
6383
6384 FOR_EACH_BB (cur_bb)
6385 {
6386 FOR_BB_INSNS (cur_bb, cur_insn)
6387 {
6388 if (INSN_P (cur_insn))
6389 note_stores (PATTERN (cur_insn),
6390 s390_reg_clobbered_rtx,
6391 regs_ever_clobbered);
6392 }
6393 }
6394 }
6395
6396 /* Determine the frame area which actually has to be accessed
6397 in the function epilogue. The values are stored at the
6398 given pointers AREA_BOTTOM (address of the lowest used stack
6399 address) and AREA_TOP (address of the first item which does
6400 not belong to the stack frame). */
6401
6402 static void
6403 s390_frame_area (int *area_bottom, int *area_top)
6404 {
6405 int b, t;
6406 int i;
6407
6408 b = INT_MAX;
6409 t = INT_MIN;
6410
6411 if (cfun_frame_layout.first_restore_gpr != -1)
6412 {
6413 b = (cfun_frame_layout.gprs_offset
6414 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6415 t = b + (cfun_frame_layout.last_restore_gpr
6416 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6417 }
6418
6419 if (TARGET_64BIT && cfun_save_high_fprs_p)
6420 {
6421 b = MIN (b, cfun_frame_layout.f8_offset);
6422 t = MAX (t, (cfun_frame_layout.f8_offset
6423 + cfun_frame_layout.high_fprs * 8));
6424 }
6425
6426 if (!TARGET_64BIT)
6427 for (i = 2; i < 4; i++)
6428 if (cfun_fpr_bit_p (i))
6429 {
6430 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6431 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6432 }
6433
6434 *area_bottom = b;
6435 *area_top = t;
6436 }
6437
6438 /* Fill cfun->machine with info about register usage of current function.
6439 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6440
6441 static void
6442 s390_register_info (int clobbered_regs[])
6443 {
6444 int i, j;
6445
6446 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6447 cfun_frame_layout.fpr_bitmap = 0;
6448 cfun_frame_layout.high_fprs = 0;
6449 if (TARGET_64BIT)
6450 for (i = 24; i < 32; i++)
6451 if (regs_ever_live[i] && !global_regs[i])
6452 {
6453 cfun_set_fpr_bit (i - 16);
6454 cfun_frame_layout.high_fprs++;
6455 }
6456
6457 /* Find first and last gpr to be saved. We trust regs_ever_live
6458 data, except that we don't save and restore global registers.
6459
6460 Also, all registers with special meaning to the compiler need
6461 to be handled extra. */
6462
6463 s390_regs_ever_clobbered (clobbered_regs);
6464
6465 for (i = 0; i < 16; i++)
6466 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6467
6468 if (frame_pointer_needed)
6469 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6470
6471 if (flag_pic)
6472 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6473 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6474
6475 clobbered_regs[BASE_REGNUM]
6476 |= (cfun->machine->base_reg
6477 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6478
6479 clobbered_regs[RETURN_REGNUM]
6480 |= (!current_function_is_leaf
6481 || TARGET_TPF_PROFILING
6482 || cfun->machine->split_branches_pending_p
6483 || cfun_frame_layout.save_return_addr_p
6484 || current_function_calls_eh_return
6485 || current_function_stdarg);
6486
6487 clobbered_regs[STACK_POINTER_REGNUM]
6488 |= (!current_function_is_leaf
6489 || TARGET_TPF_PROFILING
6490 || cfun_save_high_fprs_p
6491 || get_frame_size () > 0
6492 || current_function_calls_alloca
6493 || current_function_stdarg);
6494
6495 for (i = 6; i < 16; i++)
6496 if (regs_ever_live[i] || clobbered_regs[i])
6497 break;
6498 for (j = 15; j > i; j--)
6499 if (regs_ever_live[j] || clobbered_regs[j])
6500 break;
6501
6502 if (i == 16)
6503 {
6504 /* Nothing to save/restore. */
6505 cfun_frame_layout.first_save_gpr_slot = -1;
6506 cfun_frame_layout.last_save_gpr_slot = -1;
6507 cfun_frame_layout.first_save_gpr = -1;
6508 cfun_frame_layout.first_restore_gpr = -1;
6509 cfun_frame_layout.last_save_gpr = -1;
6510 cfun_frame_layout.last_restore_gpr = -1;
6511 }
6512 else
6513 {
6514 /* Save slots for gprs from i to j. */
6515 cfun_frame_layout.first_save_gpr_slot = i;
6516 cfun_frame_layout.last_save_gpr_slot = j;
6517
6518 for (i = cfun_frame_layout.first_save_gpr_slot;
6519 i < cfun_frame_layout.last_save_gpr_slot + 1;
6520 i++)
6521 if (clobbered_regs[i])
6522 break;
6523
6524 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6525 if (clobbered_regs[j])
6526 break;
6527
6528 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6529 {
6530 /* Nothing to save/restore. */
6531 cfun_frame_layout.first_save_gpr = -1;
6532 cfun_frame_layout.first_restore_gpr = -1;
6533 cfun_frame_layout.last_save_gpr = -1;
6534 cfun_frame_layout.last_restore_gpr = -1;
6535 }
6536 else
6537 {
6538 /* Save / Restore from gpr i to j. */
6539 cfun_frame_layout.first_save_gpr = i;
6540 cfun_frame_layout.first_restore_gpr = i;
6541 cfun_frame_layout.last_save_gpr = j;
6542 cfun_frame_layout.last_restore_gpr = j;
6543 }
6544 }
6545
6546 if (current_function_stdarg)
6547 {
6548 /* Varargs functions need to save gprs 2 to 6. */
6549 if (cfun->va_list_gpr_size
6550 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6551 {
6552 int min_gpr = current_function_args_info.gprs;
6553 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6554 if (max_gpr > GP_ARG_NUM_REG)
6555 max_gpr = GP_ARG_NUM_REG;
6556
6557 if (cfun_frame_layout.first_save_gpr == -1
6558 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6559 {
6560 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6561 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6562 }
6563
6564 if (cfun_frame_layout.last_save_gpr == -1
6565 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6566 {
6567 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6568 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6569 }
6570 }
6571
6572 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6573 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6574 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6575 {
6576 int min_fpr = current_function_args_info.fprs;
6577 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6578 if (max_fpr > FP_ARG_NUM_REG)
6579 max_fpr = FP_ARG_NUM_REG;
6580
6581 /* ??? This is currently required to ensure proper location
6582 of the fpr save slots within the va_list save area. */
6583 if (TARGET_PACKED_STACK)
6584 min_fpr = 0;
6585
6586 for (i = min_fpr; i < max_fpr; i++)
6587 cfun_set_fpr_bit (i);
6588 }
6589 }
6590
6591 if (!TARGET_64BIT)
6592 for (i = 2; i < 4; i++)
6593 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6594 cfun_set_fpr_bit (i);
6595 }
6596
6597 /* Fill cfun->machine with info about frame of current function. */
6598
6599 static void
6600 s390_frame_info (void)
6601 {
6602 int i;
6603
6604 cfun_frame_layout.frame_size = get_frame_size ();
6605 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6606 fatal_error ("total size of local variables exceeds architecture limit");
6607
6608 if (!TARGET_PACKED_STACK)
6609 {
6610 cfun_frame_layout.backchain_offset = 0;
6611 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6612 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6613 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6614 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6615 * UNITS_PER_WORD);
6616 }
6617 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6618 {
6619 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6620 - UNITS_PER_WORD);
6621 cfun_frame_layout.gprs_offset
6622 = (cfun_frame_layout.backchain_offset
6623 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6624 * UNITS_PER_WORD);
6625
6626 if (TARGET_64BIT)
6627 {
6628 cfun_frame_layout.f4_offset
6629 = (cfun_frame_layout.gprs_offset
6630 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6631
6632 cfun_frame_layout.f0_offset
6633 = (cfun_frame_layout.f4_offset
6634 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6635 }
6636 else
6637 {
6638 /* On 31 bit we have to care about alignment of the
6639 floating point regs to provide fastest access. */
6640 cfun_frame_layout.f0_offset
6641 = ((cfun_frame_layout.gprs_offset
6642 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6643 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6644
6645 cfun_frame_layout.f4_offset
6646 = (cfun_frame_layout.f0_offset
6647 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6648 }
6649 }
6650 else /* no backchain */
6651 {
6652 cfun_frame_layout.f4_offset
6653 = (STACK_POINTER_OFFSET
6654 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6655
6656 cfun_frame_layout.f0_offset
6657 = (cfun_frame_layout.f4_offset
6658 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6659
6660 cfun_frame_layout.gprs_offset
6661 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6662 }
6663
6664 if (current_function_is_leaf
6665 && !TARGET_TPF_PROFILING
6666 && cfun_frame_layout.frame_size == 0
6667 && !cfun_save_high_fprs_p
6668 && !current_function_calls_alloca
6669 && !current_function_stdarg)
6670 return;
6671
6672 if (!TARGET_PACKED_STACK)
6673 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6674 + current_function_outgoing_args_size
6675 + cfun_frame_layout.high_fprs * 8);
6676 else
6677 {
6678 if (TARGET_BACKCHAIN)
6679 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6680
6681 /* No alignment trouble here because f8-f15 are only saved under
6682 64 bit. */
6683 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6684 cfun_frame_layout.f4_offset),
6685 cfun_frame_layout.gprs_offset)
6686 - cfun_frame_layout.high_fprs * 8);
6687
6688 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6689
6690 for (i = 0; i < 8; i++)
6691 if (cfun_fpr_bit_p (i))
6692 cfun_frame_layout.frame_size += 8;
6693
6694 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6695
6696 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6697 the frame size to sustain 8 byte alignment of stack frames. */
6698 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6699 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6700 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6701
6702 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6703 }
6704 }
6705
6706 /* Generate frame layout. Fills in register and frame data for the current
6707 function in cfun->machine. This routine can be called multiple times;
6708 it will re-do the complete frame layout every time. */
6709
6710 static void
6711 s390_init_frame_layout (void)
6712 {
6713 HOST_WIDE_INT frame_size;
6714 int base_used;
6715 int clobbered_regs[16];
6716
6717 /* On S/390 machines, we may need to perform branch splitting, which
6718 will require both base and return address register. We have no
6719 choice but to assume we're going to need them until right at the
6720 end of the machine dependent reorg phase. */
6721 if (!TARGET_CPU_ZARCH)
6722 cfun->machine->split_branches_pending_p = true;
6723
6724 do
6725 {
6726 frame_size = cfun_frame_layout.frame_size;
6727
6728 /* Try to predict whether we'll need the base register. */
6729 base_used = cfun->machine->split_branches_pending_p
6730 || current_function_uses_const_pool
6731 || (!DISP_IN_RANGE (-frame_size)
6732 && !CONST_OK_FOR_K (-frame_size));
6733
6734 /* Decide which register to use as literal pool base. In small
6735 leaf functions, try to use an unused call-clobbered register
6736 as base register to avoid save/restore overhead. */
6737 if (!base_used)
6738 cfun->machine->base_reg = NULL_RTX;
6739 else if (current_function_is_leaf && !regs_ever_live[5])
6740 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6741 else
6742 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6743
6744 s390_register_info (clobbered_regs);
6745 s390_frame_info ();
6746 }
6747 while (frame_size != cfun_frame_layout.frame_size);
6748 }
6749
6750 /* Update frame layout. Recompute actual register save data based on
6751 current info and update regs_ever_live for the special registers.
6752 May be called multiple times, but may never cause *more* registers
6753 to be saved than s390_init_frame_layout allocated room for. */
6754
6755 static void
6756 s390_update_frame_layout (void)
6757 {
6758 int clobbered_regs[16];
6759
6760 s390_register_info (clobbered_regs);
6761
6762 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6763 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6764 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6765
6766 if (cfun->machine->base_reg)
6767 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6768 }
6769
6770 /* Return true if it is legal to put a value with MODE into REGNO. */
6771
6772 bool
6773 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
6774 {
6775 switch (REGNO_REG_CLASS (regno))
6776 {
6777 case FP_REGS:
6778 if (REGNO_PAIR_OK (regno, mode))
6779 {
6780 if (mode == SImode || mode == DImode)
6781 return true;
6782
6783 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
6784 return true;
6785 }
6786 break;
6787 case ADDR_REGS:
6788 if (FRAME_REGNO_P (regno) && mode == Pmode)
6789 return true;
6790
6791 /* fallthrough */
6792 case GENERAL_REGS:
6793 if (REGNO_PAIR_OK (regno, mode))
6794 {
6795 if (TARGET_64BIT
6796 || (mode != TFmode && mode != TCmode && mode != TDmode))
6797 return true;
6798 }
6799 break;
6800 case CC_REGS:
6801 if (GET_MODE_CLASS (mode) == MODE_CC)
6802 return true;
6803 break;
6804 case ACCESS_REGS:
6805 if (REGNO_PAIR_OK (regno, mode))
6806 {
6807 if (mode == SImode || mode == Pmode)
6808 return true;
6809 }
6810 break;
6811 default:
6812 return false;
6813 }
6814
6815 return false;
6816 }
6817
6818 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6819
6820 bool
6821 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6822 {
6823 /* Once we've decided upon a register to use as base register, it must
6824 no longer be used for any other purpose. */
6825 if (cfun->machine->base_reg)
6826 if (REGNO (cfun->machine->base_reg) == old_reg
6827 || REGNO (cfun->machine->base_reg) == new_reg)
6828 return false;
6829
6830 return true;
6831 }
6832
6833 /* Maximum number of registers to represent a value of mode MODE
6834 in a register of class CLASS. */
6835
6836 bool
6837 s390_class_max_nregs (enum reg_class class, enum machine_mode mode)
6838 {
6839 switch (class)
6840 {
6841 case FP_REGS:
6842 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6843 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
6844 else
6845 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
6846 case ACCESS_REGS:
6847 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
6848 default:
6849 break;
6850 }
6851 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6852 }
6853
6854 /* Return true if register FROM can be eliminated via register TO. */
6855
6856 bool
6857 s390_can_eliminate (int from, int to)
6858 {
6859 /* On zSeries machines, we have not marked the base register as fixed.
6860 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6861 If a function requires the base register, we say here that this
6862 elimination cannot be performed. This will cause reload to free
6863 up the base register (as if it were fixed). On the other hand,
6864 if the current function does *not* require the base register, we
6865 say here the elimination succeeds, which in turn allows reload
6866 to allocate the base register for any other purpose. */
6867 if (from == BASE_REGNUM && to == BASE_REGNUM)
6868 {
6869 if (TARGET_CPU_ZARCH)
6870 {
6871 s390_init_frame_layout ();
6872 return cfun->machine->base_reg == NULL_RTX;
6873 }
6874
6875 return false;
6876 }
6877
6878 /* Everything else must point into the stack frame. */
6879 gcc_assert (to == STACK_POINTER_REGNUM
6880 || to == HARD_FRAME_POINTER_REGNUM);
6881
6882 gcc_assert (from == FRAME_POINTER_REGNUM
6883 || from == ARG_POINTER_REGNUM
6884 || from == RETURN_ADDRESS_POINTER_REGNUM);
6885
6886 /* Make sure we actually saved the return address. */
6887 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6888 if (!current_function_calls_eh_return
6889 && !current_function_stdarg
6890 && !cfun_frame_layout.save_return_addr_p)
6891 return false;
6892
6893 return true;
6894 }
6895
6896 /* Return offset between register FROM and TO initially after prolog. */
6897
6898 HOST_WIDE_INT
6899 s390_initial_elimination_offset (int from, int to)
6900 {
6901 HOST_WIDE_INT offset;
6902 int index;
6903
6904 /* ??? Why are we called for non-eliminable pairs? */
6905 if (!s390_can_eliminate (from, to))
6906 return 0;
6907
6908 switch (from)
6909 {
6910 case FRAME_POINTER_REGNUM:
6911 offset = (get_frame_size()
6912 + STACK_POINTER_OFFSET
6913 + current_function_outgoing_args_size);
6914 break;
6915
6916 case ARG_POINTER_REGNUM:
6917 s390_init_frame_layout ();
6918 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6919 break;
6920
6921 case RETURN_ADDRESS_POINTER_REGNUM:
6922 s390_init_frame_layout ();
6923 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6924 gcc_assert (index >= 0);
6925 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6926 offset += index * UNITS_PER_WORD;
6927 break;
6928
6929 case BASE_REGNUM:
6930 offset = 0;
6931 break;
6932
6933 default:
6934 gcc_unreachable ();
6935 }
6936
6937 return offset;
6938 }
6939
6940 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6941 to register BASE. Return generated insn. */
6942
6943 static rtx
6944 save_fpr (rtx base, int offset, int regnum)
6945 {
6946 rtx addr;
6947 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6948
6949 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6950 set_mem_alias_set (addr, get_varargs_alias_set ());
6951 else
6952 set_mem_alias_set (addr, get_frame_alias_set ());
6953
6954 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6955 }
6956
6957 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6958 to register BASE. Return generated insn. */
6959
6960 static rtx
6961 restore_fpr (rtx base, int offset, int regnum)
6962 {
6963 rtx addr;
6964 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6965 set_mem_alias_set (addr, get_frame_alias_set ());
6966
6967 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6968 }
6969
6970 /* Generate insn to save registers FIRST to LAST into
6971 the register save area located at offset OFFSET
6972 relative to register BASE. */
6973
6974 static rtx
6975 save_gprs (rtx base, int offset, int first, int last)
6976 {
6977 rtx addr, insn, note;
6978 int i;
6979
6980 addr = plus_constant (base, offset);
6981 addr = gen_rtx_MEM (Pmode, addr);
6982
6983 set_mem_alias_set (addr, get_frame_alias_set ());
6984
6985 /* Special-case single register. */
6986 if (first == last)
6987 {
6988 if (TARGET_64BIT)
6989 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6990 else
6991 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6992
6993 RTX_FRAME_RELATED_P (insn) = 1;
6994 return insn;
6995 }
6996
6997
6998 insn = gen_store_multiple (addr,
6999 gen_rtx_REG (Pmode, first),
7000 GEN_INT (last - first + 1));
7001
7002 if (first <= 6 && current_function_stdarg)
7003 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7004 {
7005 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7006
7007 if (first + i <= 6)
7008 set_mem_alias_set (mem, get_varargs_alias_set ());
7009 }
7010
7011 /* We need to set the FRAME_RELATED flag on all SETs
7012 inside the store-multiple pattern.
7013
7014 However, we must not emit DWARF records for registers 2..5
7015 if they are stored for use by variable arguments ...
7016
7017 ??? Unfortunately, it is not enough to simply not the
7018 FRAME_RELATED flags for those SETs, because the first SET
7019 of the PARALLEL is always treated as if it had the flag
7020 set, even if it does not. Therefore we emit a new pattern
7021 without those registers as REG_FRAME_RELATED_EXPR note. */
7022
7023 if (first >= 6)
7024 {
7025 rtx pat = PATTERN (insn);
7026
7027 for (i = 0; i < XVECLEN (pat, 0); i++)
7028 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
7029 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7030
7031 RTX_FRAME_RELATED_P (insn) = 1;
7032 }
7033 else if (last >= 6)
7034 {
7035 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
7036 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7037 gen_rtx_REG (Pmode, 6),
7038 GEN_INT (last - 6 + 1));
7039 note = PATTERN (note);
7040
7041 REG_NOTES (insn) =
7042 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7043 note, REG_NOTES (insn));
7044
7045 for (i = 0; i < XVECLEN (note, 0); i++)
7046 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
7047 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7048
7049 RTX_FRAME_RELATED_P (insn) = 1;
7050 }
7051
7052 return insn;
7053 }
7054
7055 /* Generate insn to restore registers FIRST to LAST from
7056 the register save area located at offset OFFSET
7057 relative to register BASE. */
7058
7059 static rtx
7060 restore_gprs (rtx base, int offset, int first, int last)
7061 {
7062 rtx addr, insn;
7063
7064 addr = plus_constant (base, offset);
7065 addr = gen_rtx_MEM (Pmode, addr);
7066 set_mem_alias_set (addr, get_frame_alias_set ());
7067
7068 /* Special-case single register. */
7069 if (first == last)
7070 {
7071 if (TARGET_64BIT)
7072 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7073 else
7074 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7075
7076 return insn;
7077 }
7078
7079 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7080 addr,
7081 GEN_INT (last - first + 1));
7082 return insn;
7083 }
7084
7085 /* Return insn sequence to load the GOT register. */
7086
7087 static GTY(()) rtx got_symbol;
7088 rtx
7089 s390_load_got (void)
7090 {
7091 rtx insns;
7092
7093 if (!got_symbol)
7094 {
7095 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7096 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7097 }
7098
7099 start_sequence ();
7100
7101 if (TARGET_CPU_ZARCH)
7102 {
7103 emit_move_insn (pic_offset_table_rtx, got_symbol);
7104 }
7105 else
7106 {
7107 rtx offset;
7108
7109 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7110 UNSPEC_LTREL_OFFSET);
7111 offset = gen_rtx_CONST (Pmode, offset);
7112 offset = force_const_mem (Pmode, offset);
7113
7114 emit_move_insn (pic_offset_table_rtx, offset);
7115
7116 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7117 UNSPEC_LTREL_BASE);
7118 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7119
7120 emit_move_insn (pic_offset_table_rtx, offset);
7121 }
7122
7123 insns = get_insns ();
7124 end_sequence ();
7125 return insns;
7126 }
7127
7128 /* Expand the prologue into a bunch of separate insns. */
7129
7130 void
7131 s390_emit_prologue (void)
7132 {
7133 rtx insn, addr;
7134 rtx temp_reg;
7135 int i;
7136 int offset;
7137 int next_fpr = 0;
7138
7139 /* Complete frame layout. */
7140
7141 s390_update_frame_layout ();
7142
7143 /* Annotate all constant pool references to let the scheduler know
7144 they implicitly use the base register. */
7145
7146 push_topmost_sequence ();
7147
7148 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7149 if (INSN_P (insn))
7150 annotate_constant_pool_refs (&PATTERN (insn));
7151
7152 pop_topmost_sequence ();
7153
7154 /* Choose best register to use for temp use within prologue.
7155 See below for why TPF must use the register 1. */
7156
7157 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7158 && !current_function_is_leaf
7159 && !TARGET_TPF_PROFILING)
7160 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7161 else
7162 temp_reg = gen_rtx_REG (Pmode, 1);
7163
7164 /* Save call saved gprs. */
7165 if (cfun_frame_layout.first_save_gpr != -1)
7166 {
7167 insn = save_gprs (stack_pointer_rtx,
7168 cfun_frame_layout.gprs_offset +
7169 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7170 - cfun_frame_layout.first_save_gpr_slot),
7171 cfun_frame_layout.first_save_gpr,
7172 cfun_frame_layout.last_save_gpr);
7173 emit_insn (insn);
7174 }
7175
7176 /* Dummy insn to mark literal pool slot. */
7177
7178 if (cfun->machine->base_reg)
7179 emit_insn (gen_main_pool (cfun->machine->base_reg));
7180
7181 offset = cfun_frame_layout.f0_offset;
7182
7183 /* Save f0 and f2. */
7184 for (i = 0; i < 2; i++)
7185 {
7186 if (cfun_fpr_bit_p (i))
7187 {
7188 save_fpr (stack_pointer_rtx, offset, i + 16);
7189 offset += 8;
7190 }
7191 else if (!TARGET_PACKED_STACK)
7192 offset += 8;
7193 }
7194
7195 /* Save f4 and f6. */
7196 offset = cfun_frame_layout.f4_offset;
7197 for (i = 2; i < 4; i++)
7198 {
7199 if (cfun_fpr_bit_p (i))
7200 {
7201 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7202 offset += 8;
7203
7204 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7205 therefore are not frame related. */
7206 if (!call_really_used_regs[i + 16])
7207 RTX_FRAME_RELATED_P (insn) = 1;
7208 }
7209 else if (!TARGET_PACKED_STACK)
7210 offset += 8;
7211 }
7212
7213 if (TARGET_PACKED_STACK
7214 && cfun_save_high_fprs_p
7215 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7216 {
7217 offset = (cfun_frame_layout.f8_offset
7218 + (cfun_frame_layout.high_fprs - 1) * 8);
7219
7220 for (i = 15; i > 7 && offset >= 0; i--)
7221 if (cfun_fpr_bit_p (i))
7222 {
7223 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7224
7225 RTX_FRAME_RELATED_P (insn) = 1;
7226 offset -= 8;
7227 }
7228 if (offset >= cfun_frame_layout.f8_offset)
7229 next_fpr = i + 16;
7230 }
7231
7232 if (!TARGET_PACKED_STACK)
7233 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7234
7235 /* Decrement stack pointer. */
7236
7237 if (cfun_frame_layout.frame_size > 0)
7238 {
7239 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7240
7241 if (s390_stack_size)
7242 {
7243 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7244 & ~(s390_stack_guard - 1));
7245 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7246 GEN_INT (stack_check_mask));
7247
7248 if (TARGET_64BIT)
7249 gen_cmpdi (t, const0_rtx);
7250 else
7251 gen_cmpsi (t, const0_rtx);
7252
7253 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7254 gen_rtx_REG (CCmode,
7255 CC_REGNUM),
7256 const0_rtx),
7257 const0_rtx));
7258 }
7259
7260 if (s390_warn_framesize > 0
7261 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7262 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7263 current_function_name (), cfun_frame_layout.frame_size);
7264
7265 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7266 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7267
7268 /* Save incoming stack pointer into temp reg. */
7269 if (TARGET_BACKCHAIN || next_fpr)
7270 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7271
7272 /* Subtract frame size from stack pointer. */
7273
7274 if (DISP_IN_RANGE (INTVAL (frame_off)))
7275 {
7276 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7277 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7278 frame_off));
7279 insn = emit_insn (insn);
7280 }
7281 else
7282 {
7283 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7284 frame_off = force_const_mem (Pmode, frame_off);
7285
7286 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7287 annotate_constant_pool_refs (&PATTERN (insn));
7288 }
7289
7290 RTX_FRAME_RELATED_P (insn) = 1;
7291 REG_NOTES (insn) =
7292 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7293 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7294 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7295 GEN_INT (-cfun_frame_layout.frame_size))),
7296 REG_NOTES (insn));
7297
7298 /* Set backchain. */
7299
7300 if (TARGET_BACKCHAIN)
7301 {
7302 if (cfun_frame_layout.backchain_offset)
7303 addr = gen_rtx_MEM (Pmode,
7304 plus_constant (stack_pointer_rtx,
7305 cfun_frame_layout.backchain_offset));
7306 else
7307 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7308 set_mem_alias_set (addr, get_frame_alias_set ());
7309 insn = emit_insn (gen_move_insn (addr, temp_reg));
7310 }
7311
7312 /* If we support asynchronous exceptions (e.g. for Java),
7313 we need to make sure the backchain pointer is set up
7314 before any possibly trapping memory access. */
7315
7316 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7317 {
7318 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7319 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7320 }
7321 }
7322
7323 /* Save fprs 8 - 15 (64 bit ABI). */
7324
7325 if (cfun_save_high_fprs_p && next_fpr)
7326 {
7327 insn = emit_insn (gen_add2_insn (temp_reg,
7328 GEN_INT (cfun_frame_layout.f8_offset)));
7329
7330 offset = 0;
7331
7332 for (i = 24; i <= next_fpr; i++)
7333 if (cfun_fpr_bit_p (i - 16))
7334 {
7335 rtx addr = plus_constant (stack_pointer_rtx,
7336 cfun_frame_layout.frame_size
7337 + cfun_frame_layout.f8_offset
7338 + offset);
7339
7340 insn = save_fpr (temp_reg, offset, i);
7341 offset += 8;
7342 RTX_FRAME_RELATED_P (insn) = 1;
7343 REG_NOTES (insn) =
7344 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7345 gen_rtx_SET (VOIDmode,
7346 gen_rtx_MEM (DFmode, addr),
7347 gen_rtx_REG (DFmode, i)),
7348 REG_NOTES (insn));
7349 }
7350 }
7351
7352 /* Set frame pointer, if needed. */
7353
7354 if (frame_pointer_needed)
7355 {
7356 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7357 RTX_FRAME_RELATED_P (insn) = 1;
7358 }
7359
7360 /* Set up got pointer, if needed. */
7361
7362 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7363 {
7364 rtx insns = s390_load_got ();
7365
7366 for (insn = insns; insn; insn = NEXT_INSN (insn))
7367 {
7368 annotate_constant_pool_refs (&PATTERN (insn));
7369
7370 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7371 REG_NOTES (insn));
7372 }
7373
7374 emit_insn (insns);
7375 }
7376
7377 if (TARGET_TPF_PROFILING)
7378 {
7379 /* Generate a BAS instruction to serve as a function
7380 entry intercept to facilitate the use of tracing
7381 algorithms located at the branch target. */
7382 emit_insn (gen_prologue_tpf ());
7383
7384 /* Emit a blockage here so that all code
7385 lies between the profiling mechanisms. */
7386 emit_insn (gen_blockage ());
7387 }
7388 }
7389
7390 /* Expand the epilogue into a bunch of separate insns. */
7391
7392 void
7393 s390_emit_epilogue (bool sibcall)
7394 {
7395 rtx frame_pointer, return_reg;
7396 int area_bottom, area_top, offset = 0;
7397 int next_offset;
7398 rtvec p;
7399 int i;
7400
7401 if (TARGET_TPF_PROFILING)
7402 {
7403
7404 /* Generate a BAS instruction to serve as a function
7405 entry intercept to facilitate the use of tracing
7406 algorithms located at the branch target. */
7407
7408 /* Emit a blockage here so that all code
7409 lies between the profiling mechanisms. */
7410 emit_insn (gen_blockage ());
7411
7412 emit_insn (gen_epilogue_tpf ());
7413 }
7414
7415 /* Check whether to use frame or stack pointer for restore. */
7416
7417 frame_pointer = (frame_pointer_needed
7418 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7419
7420 s390_frame_area (&area_bottom, &area_top);
7421
7422 /* Check whether we can access the register save area.
7423 If not, increment the frame pointer as required. */
7424
7425 if (area_top <= area_bottom)
7426 {
7427 /* Nothing to restore. */
7428 }
7429 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7430 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7431 {
7432 /* Area is in range. */
7433 offset = cfun_frame_layout.frame_size;
7434 }
7435 else
7436 {
7437 rtx insn, frame_off;
7438
7439 offset = area_bottom < 0 ? -area_bottom : 0;
7440 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7441
7442 if (DISP_IN_RANGE (INTVAL (frame_off)))
7443 {
7444 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7445 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7446 insn = emit_insn (insn);
7447 }
7448 else
7449 {
7450 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7451 frame_off = force_const_mem (Pmode, frame_off);
7452
7453 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7454 annotate_constant_pool_refs (&PATTERN (insn));
7455 }
7456 }
7457
7458 /* Restore call saved fprs. */
7459
7460 if (TARGET_64BIT)
7461 {
7462 if (cfun_save_high_fprs_p)
7463 {
7464 next_offset = cfun_frame_layout.f8_offset;
7465 for (i = 24; i < 32; i++)
7466 {
7467 if (cfun_fpr_bit_p (i - 16))
7468 {
7469 restore_fpr (frame_pointer,
7470 offset + next_offset, i);
7471 next_offset += 8;
7472 }
7473 }
7474 }
7475
7476 }
7477 else
7478 {
7479 next_offset = cfun_frame_layout.f4_offset;
7480 for (i = 18; i < 20; i++)
7481 {
7482 if (cfun_fpr_bit_p (i - 16))
7483 {
7484 restore_fpr (frame_pointer,
7485 offset + next_offset, i);
7486 next_offset += 8;
7487 }
7488 else if (!TARGET_PACKED_STACK)
7489 next_offset += 8;
7490 }
7491
7492 }
7493
7494 /* Return register. */
7495
7496 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7497
7498 /* Restore call saved gprs. */
7499
7500 if (cfun_frame_layout.first_restore_gpr != -1)
7501 {
7502 rtx insn, addr;
7503 int i;
7504
7505 /* Check for global register and save them
7506 to stack location from where they get restored. */
7507
7508 for (i = cfun_frame_layout.first_restore_gpr;
7509 i <= cfun_frame_layout.last_restore_gpr;
7510 i++)
7511 {
7512 /* These registers are special and need to be
7513 restored in any case. */
7514 if (i == STACK_POINTER_REGNUM
7515 || i == RETURN_REGNUM
7516 || i == BASE_REGNUM
7517 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7518 continue;
7519
7520 if (global_regs[i])
7521 {
7522 addr = plus_constant (frame_pointer,
7523 offset + cfun_frame_layout.gprs_offset
7524 + (i - cfun_frame_layout.first_save_gpr_slot)
7525 * UNITS_PER_WORD);
7526 addr = gen_rtx_MEM (Pmode, addr);
7527 set_mem_alias_set (addr, get_frame_alias_set ());
7528 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7529 }
7530 }
7531
7532 if (! sibcall)
7533 {
7534 /* Fetch return address from stack before load multiple,
7535 this will do good for scheduling. */
7536
7537 if (cfun_frame_layout.save_return_addr_p
7538 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7539 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7540 {
7541 int return_regnum = find_unused_clobbered_reg();
7542 if (!return_regnum)
7543 return_regnum = 4;
7544 return_reg = gen_rtx_REG (Pmode, return_regnum);
7545
7546 addr = plus_constant (frame_pointer,
7547 offset + cfun_frame_layout.gprs_offset
7548 + (RETURN_REGNUM
7549 - cfun_frame_layout.first_save_gpr_slot)
7550 * UNITS_PER_WORD);
7551 addr = gen_rtx_MEM (Pmode, addr);
7552 set_mem_alias_set (addr, get_frame_alias_set ());
7553 emit_move_insn (return_reg, addr);
7554 }
7555 }
7556
7557 insn = restore_gprs (frame_pointer,
7558 offset + cfun_frame_layout.gprs_offset
7559 + (cfun_frame_layout.first_restore_gpr
7560 - cfun_frame_layout.first_save_gpr_slot)
7561 * UNITS_PER_WORD,
7562 cfun_frame_layout.first_restore_gpr,
7563 cfun_frame_layout.last_restore_gpr);
7564 emit_insn (insn);
7565 }
7566
7567 if (! sibcall)
7568 {
7569
7570 /* Return to caller. */
7571
7572 p = rtvec_alloc (2);
7573
7574 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7575 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7576 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7577 }
7578 }
7579
7580
7581 /* Return the size in bytes of a function argument of
7582 type TYPE and/or mode MODE. At least one of TYPE or
7583 MODE must be specified. */
7584
7585 static int
7586 s390_function_arg_size (enum machine_mode mode, tree type)
7587 {
7588 if (type)
7589 return int_size_in_bytes (type);
7590
7591 /* No type info available for some library calls ... */
7592 if (mode != BLKmode)
7593 return GET_MODE_SIZE (mode);
7594
7595 /* If we have neither type nor mode, abort */
7596 gcc_unreachable ();
7597 }
7598
7599 /* Return true if a function argument of type TYPE and mode MODE
7600 is to be passed in a floating-point register, if available. */
7601
7602 static bool
7603 s390_function_arg_float (enum machine_mode mode, tree type)
7604 {
7605 int size = s390_function_arg_size (mode, type);
7606 if (size > 8)
7607 return false;
7608
7609 /* Soft-float changes the ABI: no floating-point registers are used. */
7610 if (TARGET_SOFT_FLOAT)
7611 return false;
7612
7613 /* No type info available for some library calls ... */
7614 if (!type)
7615 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
7616
7617 /* The ABI says that record types with a single member are treated
7618 just like that member would be. */
7619 while (TREE_CODE (type) == RECORD_TYPE)
7620 {
7621 tree field, single = NULL_TREE;
7622
7623 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7624 {
7625 if (TREE_CODE (field) != FIELD_DECL)
7626 continue;
7627
7628 if (single == NULL_TREE)
7629 single = TREE_TYPE (field);
7630 else
7631 return false;
7632 }
7633
7634 if (single == NULL_TREE)
7635 return false;
7636 else
7637 type = single;
7638 }
7639
7640 return TREE_CODE (type) == REAL_TYPE;
7641 }
7642
7643 /* Return true if a function argument of type TYPE and mode MODE
7644 is to be passed in an integer register, or a pair of integer
7645 registers, if available. */
7646
7647 static bool
7648 s390_function_arg_integer (enum machine_mode mode, tree type)
7649 {
7650 int size = s390_function_arg_size (mode, type);
7651 if (size > 8)
7652 return false;
7653
7654 /* No type info available for some library calls ... */
7655 if (!type)
7656 return GET_MODE_CLASS (mode) == MODE_INT
7657 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
7658
7659 /* We accept small integral (and similar) types. */
7660 if (INTEGRAL_TYPE_P (type)
7661 || POINTER_TYPE_P (type)
7662 || TREE_CODE (type) == OFFSET_TYPE
7663 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7664 return true;
7665
7666 /* We also accept structs of size 1, 2, 4, 8 that are not
7667 passed in floating-point registers. */
7668 if (AGGREGATE_TYPE_P (type)
7669 && exact_log2 (size) >= 0
7670 && !s390_function_arg_float (mode, type))
7671 return true;
7672
7673 return false;
7674 }
7675
7676 /* Return 1 if a function argument of type TYPE and mode MODE
7677 is to be passed by reference. The ABI specifies that only
7678 structures of size 1, 2, 4, or 8 bytes are passed by value,
7679 all other structures (and complex numbers) are passed by
7680 reference. */
7681
7682 static bool
7683 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7684 enum machine_mode mode, tree type,
7685 bool named ATTRIBUTE_UNUSED)
7686 {
7687 int size = s390_function_arg_size (mode, type);
7688 if (size > 8)
7689 return true;
7690
7691 if (type)
7692 {
7693 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7694 return 1;
7695
7696 if (TREE_CODE (type) == COMPLEX_TYPE
7697 || TREE_CODE (type) == VECTOR_TYPE)
7698 return 1;
7699 }
7700
7701 return 0;
7702 }
7703
7704 /* Update the data in CUM to advance over an argument of mode MODE and
7705 data type TYPE. (TYPE is null for libcalls where that information
7706 may not be available.). The boolean NAMED specifies whether the
7707 argument is a named argument (as opposed to an unnamed argument
7708 matching an ellipsis). */
7709
7710 void
7711 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7712 tree type, int named ATTRIBUTE_UNUSED)
7713 {
7714 if (s390_function_arg_float (mode, type))
7715 {
7716 cum->fprs += 1;
7717 }
7718 else if (s390_function_arg_integer (mode, type))
7719 {
7720 int size = s390_function_arg_size (mode, type);
7721 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7722 }
7723 else
7724 gcc_unreachable ();
7725 }
7726
7727 /* Define where to put the arguments to a function.
7728 Value is zero to push the argument on the stack,
7729 or a hard register in which to store the argument.
7730
7731 MODE is the argument's machine mode.
7732 TYPE is the data type of the argument (as a tree).
7733 This is null for libcalls where that information may
7734 not be available.
7735 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7736 the preceding args and about the function being called.
7737 NAMED is nonzero if this argument is a named parameter
7738 (otherwise it is an extra parameter matching an ellipsis).
7739
7740 On S/390, we use general purpose registers 2 through 6 to
7741 pass integer, pointer, and certain structure arguments, and
7742 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7743 to pass floating point arguments. All remaining arguments
7744 are pushed to the stack. */
7745
7746 rtx
7747 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7748 int named ATTRIBUTE_UNUSED)
7749 {
7750 if (s390_function_arg_float (mode, type))
7751 {
7752 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7753 return 0;
7754 else
7755 return gen_rtx_REG (mode, cum->fprs + 16);
7756 }
7757 else if (s390_function_arg_integer (mode, type))
7758 {
7759 int size = s390_function_arg_size (mode, type);
7760 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7761
7762 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7763 return 0;
7764 else
7765 return gen_rtx_REG (mode, cum->gprs + 2);
7766 }
7767
7768 /* After the real arguments, expand_call calls us once again
7769 with a void_type_node type. Whatever we return here is
7770 passed as operand 2 to the call expanders.
7771
7772 We don't need this feature ... */
7773 else if (type == void_type_node)
7774 return const0_rtx;
7775
7776 gcc_unreachable ();
7777 }
7778
7779 /* Return true if return values of type TYPE should be returned
7780 in a memory buffer whose address is passed by the caller as
7781 hidden first argument. */
7782
7783 static bool
7784 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7785 {
7786 /* We accept small integral (and similar) types. */
7787 if (INTEGRAL_TYPE_P (type)
7788 || POINTER_TYPE_P (type)
7789 || TREE_CODE (type) == OFFSET_TYPE
7790 || TREE_CODE (type) == REAL_TYPE)
7791 return int_size_in_bytes (type) > 8;
7792
7793 /* Aggregates and similar constructs are always returned
7794 in memory. */
7795 if (AGGREGATE_TYPE_P (type)
7796 || TREE_CODE (type) == COMPLEX_TYPE
7797 || TREE_CODE (type) == VECTOR_TYPE)
7798 return true;
7799
7800 /* ??? We get called on all sorts of random stuff from
7801 aggregate_value_p. We can't abort, but it's not clear
7802 what's safe to return. Pretend it's a struct I guess. */
7803 return true;
7804 }
7805
7806 /* Define where to return a (scalar) value of type TYPE.
7807 If TYPE is null, define where to return a (scalar)
7808 value of mode MODE from a libcall. */
7809
7810 rtx
7811 s390_function_value (tree type, enum machine_mode mode)
7812 {
7813 if (type)
7814 {
7815 int unsignedp = TYPE_UNSIGNED (type);
7816 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7817 }
7818
7819 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
7820 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7821
7822 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
7823 return gen_rtx_REG (mode, 16);
7824 else
7825 return gen_rtx_REG (mode, 2);
7826 }
7827
7828
7829 /* Create and return the va_list datatype.
7830
7831 On S/390, va_list is an array type equivalent to
7832
7833 typedef struct __va_list_tag
7834 {
7835 long __gpr;
7836 long __fpr;
7837 void *__overflow_arg_area;
7838 void *__reg_save_area;
7839 } va_list[1];
7840
7841 where __gpr and __fpr hold the number of general purpose
7842 or floating point arguments used up to now, respectively,
7843 __overflow_arg_area points to the stack location of the
7844 next argument passed on the stack, and __reg_save_area
7845 always points to the start of the register area in the
7846 call frame of the current function. The function prologue
7847 saves all registers used for argument passing into this
7848 area if the function uses variable arguments. */
7849
7850 static tree
7851 s390_build_builtin_va_list (void)
7852 {
7853 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7854
7855 record = lang_hooks.types.make_type (RECORD_TYPE);
7856
7857 type_decl =
7858 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7859
7860 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7861 long_integer_type_node);
7862 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7863 long_integer_type_node);
7864 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7865 ptr_type_node);
7866 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7867 ptr_type_node);
7868
7869 va_list_gpr_counter_field = f_gpr;
7870 va_list_fpr_counter_field = f_fpr;
7871
7872 DECL_FIELD_CONTEXT (f_gpr) = record;
7873 DECL_FIELD_CONTEXT (f_fpr) = record;
7874 DECL_FIELD_CONTEXT (f_ovf) = record;
7875 DECL_FIELD_CONTEXT (f_sav) = record;
7876
7877 TREE_CHAIN (record) = type_decl;
7878 TYPE_NAME (record) = type_decl;
7879 TYPE_FIELDS (record) = f_gpr;
7880 TREE_CHAIN (f_gpr) = f_fpr;
7881 TREE_CHAIN (f_fpr) = f_ovf;
7882 TREE_CHAIN (f_ovf) = f_sav;
7883
7884 layout_type (record);
7885
7886 /* The correct type is an array type of one element. */
7887 return build_array_type (record, build_index_type (size_zero_node));
7888 }
7889
7890 /* Implement va_start by filling the va_list structure VALIST.
7891 STDARG_P is always true, and ignored.
7892 NEXTARG points to the first anonymous stack argument.
7893
7894 The following global variables are used to initialize
7895 the va_list structure:
7896
7897 current_function_args_info:
7898 holds number of gprs and fprs used for named arguments.
7899 current_function_arg_offset_rtx:
7900 holds the offset of the first anonymous stack argument
7901 (relative to the virtual arg pointer). */
7902
7903 void
7904 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7905 {
7906 HOST_WIDE_INT n_gpr, n_fpr;
7907 int off;
7908 tree f_gpr, f_fpr, f_ovf, f_sav;
7909 tree gpr, fpr, ovf, sav, t;
7910
7911 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7912 f_fpr = TREE_CHAIN (f_gpr);
7913 f_ovf = TREE_CHAIN (f_fpr);
7914 f_sav = TREE_CHAIN (f_ovf);
7915
7916 valist = build_va_arg_indirect_ref (valist);
7917 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7918 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7919 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7920 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7921
7922 /* Count number of gp and fp argument registers used. */
7923
7924 n_gpr = current_function_args_info.gprs;
7925 n_fpr = current_function_args_info.fprs;
7926
7927 if (cfun->va_list_gpr_size)
7928 {
7929 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7930 build_int_cst (NULL_TREE, n_gpr));
7931 TREE_SIDE_EFFECTS (t) = 1;
7932 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7933 }
7934
7935 if (cfun->va_list_fpr_size)
7936 {
7937 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7938 build_int_cst (NULL_TREE, n_fpr));
7939 TREE_SIDE_EFFECTS (t) = 1;
7940 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7941 }
7942
7943 /* Find the overflow area. */
7944 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7945 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7946 {
7947 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7948
7949 off = INTVAL (current_function_arg_offset_rtx);
7950 off = off < 0 ? 0 : off;
7951 if (TARGET_DEBUG_ARG)
7952 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7953 (int)n_gpr, (int)n_fpr, off);
7954
7955 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7956
7957 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7958 TREE_SIDE_EFFECTS (t) = 1;
7959 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7960 }
7961
7962 /* Find the register save area. */
7963 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7964 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7965 {
7966 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7967 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
7968 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7969
7970 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7971 TREE_SIDE_EFFECTS (t) = 1;
7972 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7973 }
7974 }
7975
7976 /* Implement va_arg by updating the va_list structure
7977 VALIST as required to retrieve an argument of type
7978 TYPE, and returning that argument.
7979
7980 Generates code equivalent to:
7981
7982 if (integral value) {
7983 if (size <= 4 && args.gpr < 5 ||
7984 size > 4 && args.gpr < 4 )
7985 ret = args.reg_save_area[args.gpr+8]
7986 else
7987 ret = *args.overflow_arg_area++;
7988 } else if (float value) {
7989 if (args.fgpr < 2)
7990 ret = args.reg_save_area[args.fpr+64]
7991 else
7992 ret = *args.overflow_arg_area++;
7993 } else if (aggregate value) {
7994 if (args.gpr < 5)
7995 ret = *args.reg_save_area[args.gpr]
7996 else
7997 ret = **args.overflow_arg_area++;
7998 } */
7999
8000 static tree
8001 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
8002 tree *post_p ATTRIBUTE_UNUSED)
8003 {
8004 tree f_gpr, f_fpr, f_ovf, f_sav;
8005 tree gpr, fpr, ovf, sav, reg, t, u;
8006 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8007 tree lab_false, lab_over, addr;
8008
8009 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8010 f_fpr = TREE_CHAIN (f_gpr);
8011 f_ovf = TREE_CHAIN (f_fpr);
8012 f_sav = TREE_CHAIN (f_ovf);
8013
8014 valist = build_va_arg_indirect_ref (valist);
8015 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8016 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8017 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8018 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8019
8020 size = int_size_in_bytes (type);
8021
8022 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8023 {
8024 if (TARGET_DEBUG_ARG)
8025 {
8026 fprintf (stderr, "va_arg: aggregate type");
8027 debug_tree (type);
8028 }
8029
8030 /* Aggregates are passed by reference. */
8031 indirect_p = 1;
8032 reg = gpr;
8033 n_reg = 1;
8034
8035 /* kernel stack layout on 31 bit: It is assumed here that no padding
8036 will be added by s390_frame_info because for va_args always an even
8037 number of gprs has to be saved r15-r2 = 14 regs. */
8038 sav_ofs = 2 * UNITS_PER_WORD;
8039 sav_scale = UNITS_PER_WORD;
8040 size = UNITS_PER_WORD;
8041 max_reg = GP_ARG_NUM_REG - n_reg;
8042 }
8043 else if (s390_function_arg_float (TYPE_MODE (type), type))
8044 {
8045 if (TARGET_DEBUG_ARG)
8046 {
8047 fprintf (stderr, "va_arg: float type");
8048 debug_tree (type);
8049 }
8050
8051 /* FP args go in FP registers, if present. */
8052 indirect_p = 0;
8053 reg = fpr;
8054 n_reg = 1;
8055 sav_ofs = 16 * UNITS_PER_WORD;
8056 sav_scale = 8;
8057 max_reg = FP_ARG_NUM_REG - n_reg;
8058 }
8059 else
8060 {
8061 if (TARGET_DEBUG_ARG)
8062 {
8063 fprintf (stderr, "va_arg: other type");
8064 debug_tree (type);
8065 }
8066
8067 /* Otherwise into GP registers. */
8068 indirect_p = 0;
8069 reg = gpr;
8070 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8071
8072 /* kernel stack layout on 31 bit: It is assumed here that no padding
8073 will be added by s390_frame_info because for va_args always an even
8074 number of gprs has to be saved r15-r2 = 14 regs. */
8075 sav_ofs = 2 * UNITS_PER_WORD;
8076
8077 if (size < UNITS_PER_WORD)
8078 sav_ofs += UNITS_PER_WORD - size;
8079
8080 sav_scale = UNITS_PER_WORD;
8081 max_reg = GP_ARG_NUM_REG - n_reg;
8082 }
8083
8084 /* Pull the value out of the saved registers ... */
8085
8086 lab_false = create_artificial_label ();
8087 lab_over = create_artificial_label ();
8088 addr = create_tmp_var (ptr_type_node, "addr");
8089 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8090
8091 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8092 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8093 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8094 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8095 gimplify_and_add (t, pre_p);
8096
8097 t = build2 (PLUS_EXPR, ptr_type_node, sav,
8098 fold_convert (ptr_type_node, size_int (sav_ofs)));
8099 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8100 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8101 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
8102
8103 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
8104 gimplify_and_add (t, pre_p);
8105
8106 t = build1 (GOTO_EXPR, void_type_node, lab_over);
8107 gimplify_and_add (t, pre_p);
8108
8109 t = build1 (LABEL_EXPR, void_type_node, lab_false);
8110 append_to_statement_list (t, pre_p);
8111
8112
8113 /* ... Otherwise out of the overflow area. */
8114
8115 t = ovf;
8116 if (size < UNITS_PER_WORD)
8117 t = build2 (PLUS_EXPR, ptr_type_node, t,
8118 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
8119
8120 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8121
8122 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
8123 gimplify_and_add (u, pre_p);
8124
8125 t = build2 (PLUS_EXPR, ptr_type_node, t,
8126 fold_convert (ptr_type_node, size_int (size)));
8127 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
8128 gimplify_and_add (t, pre_p);
8129
8130 t = build1 (LABEL_EXPR, void_type_node, lab_over);
8131 append_to_statement_list (t, pre_p);
8132
8133
8134 /* Increment register save count. */
8135
8136 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8137 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8138 gimplify_and_add (u, pre_p);
8139
8140 if (indirect_p)
8141 {
8142 t = build_pointer_type (build_pointer_type (type));
8143 addr = fold_convert (t, addr);
8144 addr = build_va_arg_indirect_ref (addr);
8145 }
8146 else
8147 {
8148 t = build_pointer_type (type);
8149 addr = fold_convert (t, addr);
8150 }
8151
8152 return build_va_arg_indirect_ref (addr);
8153 }
8154
8155
8156 /* Builtins. */
8157
8158 enum s390_builtin
8159 {
8160 S390_BUILTIN_THREAD_POINTER,
8161 S390_BUILTIN_SET_THREAD_POINTER,
8162
8163 S390_BUILTIN_max
8164 };
8165
8166 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8167 CODE_FOR_get_tp_64,
8168 CODE_FOR_set_tp_64
8169 };
8170
8171 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8172 CODE_FOR_get_tp_31,
8173 CODE_FOR_set_tp_31
8174 };
8175
8176 static void
8177 s390_init_builtins (void)
8178 {
8179 tree ftype;
8180
8181 ftype = build_function_type (ptr_type_node, void_list_node);
8182 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
8183 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8184 NULL, NULL_TREE);
8185
8186 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8187 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
8188 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8189 NULL, NULL_TREE);
8190 }
8191
8192 /* Expand an expression EXP that calls a built-in function,
8193 with result going to TARGET if that's convenient
8194 (and in mode MODE if that's convenient).
8195 SUBTARGET may be used as the target for computing one of EXP's operands.
8196 IGNORE is nonzero if the value is to be ignored. */
8197
8198 static rtx
8199 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8200 enum machine_mode mode ATTRIBUTE_UNUSED,
8201 int ignore ATTRIBUTE_UNUSED)
8202 {
8203 #define MAX_ARGS 2
8204
8205 unsigned int const *code_for_builtin =
8206 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8207
8208 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8209 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8210 tree arglist = TREE_OPERAND (exp, 1);
8211 enum insn_code icode;
8212 rtx op[MAX_ARGS], pat;
8213 int arity;
8214 bool nonvoid;
8215
8216 if (fcode >= S390_BUILTIN_max)
8217 internal_error ("bad builtin fcode");
8218 icode = code_for_builtin[fcode];
8219 if (icode == 0)
8220 internal_error ("bad builtin fcode");
8221
8222 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8223
8224 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
8225 arglist;
8226 arglist = TREE_CHAIN (arglist), arity++)
8227 {
8228 const struct insn_operand_data *insn_op;
8229
8230 tree arg = TREE_VALUE (arglist);
8231 if (arg == error_mark_node)
8232 return NULL_RTX;
8233 if (arity > MAX_ARGS)
8234 return NULL_RTX;
8235
8236 insn_op = &insn_data[icode].operand[arity + nonvoid];
8237
8238 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8239
8240 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8241 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8242 }
8243
8244 if (nonvoid)
8245 {
8246 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8247 if (!target
8248 || GET_MODE (target) != tmode
8249 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8250 target = gen_reg_rtx (tmode);
8251 }
8252
8253 switch (arity)
8254 {
8255 case 0:
8256 pat = GEN_FCN (icode) (target);
8257 break;
8258 case 1:
8259 if (nonvoid)
8260 pat = GEN_FCN (icode) (target, op[0]);
8261 else
8262 pat = GEN_FCN (icode) (op[0]);
8263 break;
8264 case 2:
8265 pat = GEN_FCN (icode) (target, op[0], op[1]);
8266 break;
8267 default:
8268 gcc_unreachable ();
8269 }
8270 if (!pat)
8271 return NULL_RTX;
8272 emit_insn (pat);
8273
8274 if (nonvoid)
8275 return target;
8276 else
8277 return const0_rtx;
8278 }
8279
8280
8281 /* Output assembly code for the trampoline template to
8282 stdio stream FILE.
8283
8284 On S/390, we use gpr 1 internally in the trampoline code;
8285 gpr 0 is used to hold the static chain. */
8286
8287 void
8288 s390_trampoline_template (FILE *file)
8289 {
8290 rtx op[2];
8291 op[0] = gen_rtx_REG (Pmode, 0);
8292 op[1] = gen_rtx_REG (Pmode, 1);
8293
8294 if (TARGET_64BIT)
8295 {
8296 output_asm_insn ("basr\t%1,0", op);
8297 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8298 output_asm_insn ("br\t%1", op);
8299 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8300 }
8301 else
8302 {
8303 output_asm_insn ("basr\t%1,0", op);
8304 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8305 output_asm_insn ("br\t%1", op);
8306 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8307 }
8308 }
8309
8310 /* Emit RTL insns to initialize the variable parts of a trampoline.
8311 FNADDR is an RTX for the address of the function's pure code.
8312 CXT is an RTX for the static chain value for the function. */
8313
8314 void
8315 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8316 {
8317 emit_move_insn (gen_rtx_MEM (Pmode,
8318 memory_address (Pmode,
8319 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8320 emit_move_insn (gen_rtx_MEM (Pmode,
8321 memory_address (Pmode,
8322 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8323 }
8324
8325 /* Return rtx for 64-bit constant formed from the 32-bit subwords
8326 LOW and HIGH, independent of the host word size. */
8327
8328 rtx
8329 s390_gen_rtx_const_DI (int high, int low)
8330 {
8331 #if HOST_BITS_PER_WIDE_INT >= 64
8332 HOST_WIDE_INT val;
8333 val = (HOST_WIDE_INT)high;
8334 val <<= 32;
8335 val |= (HOST_WIDE_INT)low;
8336
8337 return GEN_INT (val);
8338 #else
8339 #if HOST_BITS_PER_WIDE_INT >= 32
8340 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8341 #else
8342 gcc_unreachable ();
8343 #endif
8344 #endif
8345 }
8346
8347 /* Output assembler code to FILE to increment profiler label # LABELNO
8348 for profiling a function entry. */
8349
8350 void
8351 s390_function_profiler (FILE *file, int labelno)
8352 {
8353 rtx op[7];
8354
8355 char label[128];
8356 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8357
8358 fprintf (file, "# function profiler \n");
8359
8360 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8361 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8362 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8363
8364 op[2] = gen_rtx_REG (Pmode, 1);
8365 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8366 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8367
8368 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8369 if (flag_pic)
8370 {
8371 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8372 op[4] = gen_rtx_CONST (Pmode, op[4]);
8373 }
8374
8375 if (TARGET_64BIT)
8376 {
8377 output_asm_insn ("stg\t%0,%1", op);
8378 output_asm_insn ("larl\t%2,%3", op);
8379 output_asm_insn ("brasl\t%0,%4", op);
8380 output_asm_insn ("lg\t%0,%1", op);
8381 }
8382 else if (!flag_pic)
8383 {
8384 op[6] = gen_label_rtx ();
8385
8386 output_asm_insn ("st\t%0,%1", op);
8387 output_asm_insn ("bras\t%2,%l6", op);
8388 output_asm_insn (".long\t%4", op);
8389 output_asm_insn (".long\t%3", op);
8390 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8391 output_asm_insn ("l\t%0,0(%2)", op);
8392 output_asm_insn ("l\t%2,4(%2)", op);
8393 output_asm_insn ("basr\t%0,%0", op);
8394 output_asm_insn ("l\t%0,%1", op);
8395 }
8396 else
8397 {
8398 op[5] = gen_label_rtx ();
8399 op[6] = gen_label_rtx ();
8400
8401 output_asm_insn ("st\t%0,%1", op);
8402 output_asm_insn ("bras\t%2,%l6", op);
8403 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8404 output_asm_insn (".long\t%4-%l5", op);
8405 output_asm_insn (".long\t%3-%l5", op);
8406 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8407 output_asm_insn ("lr\t%0,%2", op);
8408 output_asm_insn ("a\t%0,0(%2)", op);
8409 output_asm_insn ("a\t%2,4(%2)", op);
8410 output_asm_insn ("basr\t%0,%0", op);
8411 output_asm_insn ("l\t%0,%1", op);
8412 }
8413 }
8414
8415 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8416 into its SYMBOL_REF_FLAGS. */
8417
8418 static void
8419 s390_encode_section_info (tree decl, rtx rtl, int first)
8420 {
8421 default_encode_section_info (decl, rtl, first);
8422
8423 /* If a variable has a forced alignment to < 2 bytes, mark it with
8424 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8425 if (TREE_CODE (decl) == VAR_DECL
8426 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8427 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8428 }
8429
8430 /* Output thunk to FILE that implements a C++ virtual function call (with
8431 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8432 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8433 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8434 relative to the resulting this pointer. */
8435
8436 static void
8437 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8438 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8439 tree function)
8440 {
8441 rtx op[10];
8442 int nonlocal = 0;
8443
8444 /* Operand 0 is the target function. */
8445 op[0] = XEXP (DECL_RTL (function), 0);
8446 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8447 {
8448 nonlocal = 1;
8449 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8450 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8451 op[0] = gen_rtx_CONST (Pmode, op[0]);
8452 }
8453
8454 /* Operand 1 is the 'this' pointer. */
8455 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8456 op[1] = gen_rtx_REG (Pmode, 3);
8457 else
8458 op[1] = gen_rtx_REG (Pmode, 2);
8459
8460 /* Operand 2 is the delta. */
8461 op[2] = GEN_INT (delta);
8462
8463 /* Operand 3 is the vcall_offset. */
8464 op[3] = GEN_INT (vcall_offset);
8465
8466 /* Operand 4 is the temporary register. */
8467 op[4] = gen_rtx_REG (Pmode, 1);
8468
8469 /* Operands 5 to 8 can be used as labels. */
8470 op[5] = NULL_RTX;
8471 op[6] = NULL_RTX;
8472 op[7] = NULL_RTX;
8473 op[8] = NULL_RTX;
8474
8475 /* Operand 9 can be used for temporary register. */
8476 op[9] = NULL_RTX;
8477
8478 /* Generate code. */
8479 if (TARGET_64BIT)
8480 {
8481 /* Setup literal pool pointer if required. */
8482 if ((!DISP_IN_RANGE (delta)
8483 && !CONST_OK_FOR_K (delta)
8484 && !CONST_OK_FOR_Os (delta))
8485 || (!DISP_IN_RANGE (vcall_offset)
8486 && !CONST_OK_FOR_K (vcall_offset)
8487 && !CONST_OK_FOR_Os (vcall_offset)))
8488 {
8489 op[5] = gen_label_rtx ();
8490 output_asm_insn ("larl\t%4,%5", op);
8491 }
8492
8493 /* Add DELTA to this pointer. */
8494 if (delta)
8495 {
8496 if (CONST_OK_FOR_J (delta))
8497 output_asm_insn ("la\t%1,%2(%1)", op);
8498 else if (DISP_IN_RANGE (delta))
8499 output_asm_insn ("lay\t%1,%2(%1)", op);
8500 else if (CONST_OK_FOR_K (delta))
8501 output_asm_insn ("aghi\t%1,%2", op);
8502 else if (CONST_OK_FOR_Os (delta))
8503 output_asm_insn ("agfi\t%1,%2", op);
8504 else
8505 {
8506 op[6] = gen_label_rtx ();
8507 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8508 }
8509 }
8510
8511 /* Perform vcall adjustment. */
8512 if (vcall_offset)
8513 {
8514 if (DISP_IN_RANGE (vcall_offset))
8515 {
8516 output_asm_insn ("lg\t%4,0(%1)", op);
8517 output_asm_insn ("ag\t%1,%3(%4)", op);
8518 }
8519 else if (CONST_OK_FOR_K (vcall_offset))
8520 {
8521 output_asm_insn ("lghi\t%4,%3", op);
8522 output_asm_insn ("ag\t%4,0(%1)", op);
8523 output_asm_insn ("ag\t%1,0(%4)", op);
8524 }
8525 else if (CONST_OK_FOR_Os (vcall_offset))
8526 {
8527 output_asm_insn ("lgfi\t%4,%3", op);
8528 output_asm_insn ("ag\t%4,0(%1)", op);
8529 output_asm_insn ("ag\t%1,0(%4)", op);
8530 }
8531 else
8532 {
8533 op[7] = gen_label_rtx ();
8534 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8535 output_asm_insn ("ag\t%4,0(%1)", op);
8536 output_asm_insn ("ag\t%1,0(%4)", op);
8537 }
8538 }
8539
8540 /* Jump to target. */
8541 output_asm_insn ("jg\t%0", op);
8542
8543 /* Output literal pool if required. */
8544 if (op[5])
8545 {
8546 output_asm_insn (".align\t4", op);
8547 targetm.asm_out.internal_label (file, "L",
8548 CODE_LABEL_NUMBER (op[5]));
8549 }
8550 if (op[6])
8551 {
8552 targetm.asm_out.internal_label (file, "L",
8553 CODE_LABEL_NUMBER (op[6]));
8554 output_asm_insn (".long\t%2", op);
8555 }
8556 if (op[7])
8557 {
8558 targetm.asm_out.internal_label (file, "L",
8559 CODE_LABEL_NUMBER (op[7]));
8560 output_asm_insn (".long\t%3", op);
8561 }
8562 }
8563 else
8564 {
8565 /* Setup base pointer if required. */
8566 if (!vcall_offset
8567 || (!DISP_IN_RANGE (delta)
8568 && !CONST_OK_FOR_K (delta)
8569 && !CONST_OK_FOR_Os (delta))
8570 || (!DISP_IN_RANGE (delta)
8571 && !CONST_OK_FOR_K (vcall_offset)
8572 && !CONST_OK_FOR_Os (vcall_offset)))
8573 {
8574 op[5] = gen_label_rtx ();
8575 output_asm_insn ("basr\t%4,0", op);
8576 targetm.asm_out.internal_label (file, "L",
8577 CODE_LABEL_NUMBER (op[5]));
8578 }
8579
8580 /* Add DELTA to this pointer. */
8581 if (delta)
8582 {
8583 if (CONST_OK_FOR_J (delta))
8584 output_asm_insn ("la\t%1,%2(%1)", op);
8585 else if (DISP_IN_RANGE (delta))
8586 output_asm_insn ("lay\t%1,%2(%1)", op);
8587 else if (CONST_OK_FOR_K (delta))
8588 output_asm_insn ("ahi\t%1,%2", op);
8589 else if (CONST_OK_FOR_Os (delta))
8590 output_asm_insn ("afi\t%1,%2", op);
8591 else
8592 {
8593 op[6] = gen_label_rtx ();
8594 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8595 }
8596 }
8597
8598 /* Perform vcall adjustment. */
8599 if (vcall_offset)
8600 {
8601 if (CONST_OK_FOR_J (vcall_offset))
8602 {
8603 output_asm_insn ("l\t%4,0(%1)", op);
8604 output_asm_insn ("a\t%1,%3(%4)", op);
8605 }
8606 else if (DISP_IN_RANGE (vcall_offset))
8607 {
8608 output_asm_insn ("l\t%4,0(%1)", op);
8609 output_asm_insn ("ay\t%1,%3(%4)", op);
8610 }
8611 else if (CONST_OK_FOR_K (vcall_offset))
8612 {
8613 output_asm_insn ("lhi\t%4,%3", op);
8614 output_asm_insn ("a\t%4,0(%1)", op);
8615 output_asm_insn ("a\t%1,0(%4)", op);
8616 }
8617 else if (CONST_OK_FOR_Os (vcall_offset))
8618 {
8619 output_asm_insn ("iilf\t%4,%3", op);
8620 output_asm_insn ("a\t%4,0(%1)", op);
8621 output_asm_insn ("a\t%1,0(%4)", op);
8622 }
8623 else
8624 {
8625 op[7] = gen_label_rtx ();
8626 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8627 output_asm_insn ("a\t%4,0(%1)", op);
8628 output_asm_insn ("a\t%1,0(%4)", op);
8629 }
8630
8631 /* We had to clobber the base pointer register.
8632 Re-setup the base pointer (with a different base). */
8633 op[5] = gen_label_rtx ();
8634 output_asm_insn ("basr\t%4,0", op);
8635 targetm.asm_out.internal_label (file, "L",
8636 CODE_LABEL_NUMBER (op[5]));
8637 }
8638
8639 /* Jump to target. */
8640 op[8] = gen_label_rtx ();
8641
8642 if (!flag_pic)
8643 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8644 else if (!nonlocal)
8645 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8646 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8647 else if (flag_pic == 1)
8648 {
8649 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8650 output_asm_insn ("l\t%4,%0(%4)", op);
8651 }
8652 else if (flag_pic == 2)
8653 {
8654 op[9] = gen_rtx_REG (Pmode, 0);
8655 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8656 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8657 output_asm_insn ("ar\t%4,%9", op);
8658 output_asm_insn ("l\t%4,0(%4)", op);
8659 }
8660
8661 output_asm_insn ("br\t%4", op);
8662
8663 /* Output literal pool. */
8664 output_asm_insn (".align\t4", op);
8665
8666 if (nonlocal && flag_pic == 2)
8667 output_asm_insn (".long\t%0", op);
8668 if (nonlocal)
8669 {
8670 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8671 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8672 }
8673
8674 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8675 if (!flag_pic)
8676 output_asm_insn (".long\t%0", op);
8677 else
8678 output_asm_insn (".long\t%0-%5", op);
8679
8680 if (op[6])
8681 {
8682 targetm.asm_out.internal_label (file, "L",
8683 CODE_LABEL_NUMBER (op[6]));
8684 output_asm_insn (".long\t%2", op);
8685 }
8686 if (op[7])
8687 {
8688 targetm.asm_out.internal_label (file, "L",
8689 CODE_LABEL_NUMBER (op[7]));
8690 output_asm_insn (".long\t%3", op);
8691 }
8692 }
8693 }
8694
8695 static bool
8696 s390_valid_pointer_mode (enum machine_mode mode)
8697 {
8698 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8699 }
8700
8701 /* Checks whether the given ARGUMENT_LIST would use a caller
8702 saved register. This is used to decide whether sibling call
8703 optimization could be performed on the respective function
8704 call. */
8705
8706 static bool
8707 s390_call_saved_register_used (tree argument_list)
8708 {
8709 CUMULATIVE_ARGS cum;
8710 tree parameter;
8711 enum machine_mode mode;
8712 tree type;
8713 rtx parm_rtx;
8714 int reg;
8715
8716 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8717
8718 while (argument_list)
8719 {
8720 parameter = TREE_VALUE (argument_list);
8721 argument_list = TREE_CHAIN (argument_list);
8722
8723 gcc_assert (parameter);
8724
8725 /* For an undeclared variable passed as parameter we will get
8726 an ERROR_MARK node here. */
8727 if (TREE_CODE (parameter) == ERROR_MARK)
8728 return true;
8729
8730 type = TREE_TYPE (parameter);
8731 gcc_assert (type);
8732
8733 mode = TYPE_MODE (type);
8734 gcc_assert (mode);
8735
8736 if (pass_by_reference (&cum, mode, type, true))
8737 {
8738 mode = Pmode;
8739 type = build_pointer_type (type);
8740 }
8741
8742 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8743
8744 s390_function_arg_advance (&cum, mode, type, 0);
8745
8746 if (parm_rtx && REG_P (parm_rtx))
8747 {
8748 for (reg = 0;
8749 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8750 reg++)
8751 if (! call_used_regs[reg + REGNO (parm_rtx)])
8752 return true;
8753 }
8754 }
8755 return false;
8756 }
8757
8758 /* Return true if the given call expression can be
8759 turned into a sibling call.
8760 DECL holds the declaration of the function to be called whereas
8761 EXP is the call expression itself. */
8762
8763 static bool
8764 s390_function_ok_for_sibcall (tree decl, tree exp)
8765 {
8766 /* The TPF epilogue uses register 1. */
8767 if (TARGET_TPF_PROFILING)
8768 return false;
8769
8770 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8771 which would have to be restored before the sibcall. */
8772 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
8773 return false;
8774
8775 /* Register 6 on s390 is available as an argument register but unfortunately
8776 "caller saved". This makes functions needing this register for arguments
8777 not suitable for sibcalls. */
8778 if (TREE_OPERAND (exp, 1)
8779 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8780 return false;
8781
8782 return true;
8783 }
8784
8785 /* Return the fixed registers used for condition codes. */
8786
8787 static bool
8788 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8789 {
8790 *p1 = CC_REGNUM;
8791 *p2 = INVALID_REGNUM;
8792
8793 return true;
8794 }
8795
8796 /* This function is used by the call expanders of the machine description.
8797 It emits the call insn itself together with the necessary operations
8798 to adjust the target address and returns the emitted insn.
8799 ADDR_LOCATION is the target address rtx
8800 TLS_CALL the location of the thread-local symbol
8801 RESULT_REG the register where the result of the call should be stored
8802 RETADDR_REG the register where the return address should be stored
8803 If this parameter is NULL_RTX the call is considered
8804 to be a sibling call. */
8805
8806 rtx
8807 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8808 rtx retaddr_reg)
8809 {
8810 bool plt_call = false;
8811 rtx insn;
8812 rtx call;
8813 rtx clobber;
8814 rtvec vec;
8815
8816 /* Direct function calls need special treatment. */
8817 if (GET_CODE (addr_location) == SYMBOL_REF)
8818 {
8819 /* When calling a global routine in PIC mode, we must
8820 replace the symbol itself with the PLT stub. */
8821 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8822 {
8823 addr_location = gen_rtx_UNSPEC (Pmode,
8824 gen_rtvec (1, addr_location),
8825 UNSPEC_PLT);
8826 addr_location = gen_rtx_CONST (Pmode, addr_location);
8827 plt_call = true;
8828 }
8829
8830 /* Unless we can use the bras(l) insn, force the
8831 routine address into a register. */
8832 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8833 {
8834 if (flag_pic)
8835 addr_location = legitimize_pic_address (addr_location, 0);
8836 else
8837 addr_location = force_reg (Pmode, addr_location);
8838 }
8839 }
8840
8841 /* If it is already an indirect call or the code above moved the
8842 SYMBOL_REF to somewhere else make sure the address can be found in
8843 register 1. */
8844 if (retaddr_reg == NULL_RTX
8845 && GET_CODE (addr_location) != SYMBOL_REF
8846 && !plt_call)
8847 {
8848 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8849 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8850 }
8851
8852 addr_location = gen_rtx_MEM (QImode, addr_location);
8853 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8854
8855 if (result_reg != NULL_RTX)
8856 call = gen_rtx_SET (VOIDmode, result_reg, call);
8857
8858 if (retaddr_reg != NULL_RTX)
8859 {
8860 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8861
8862 if (tls_call != NULL_RTX)
8863 vec = gen_rtvec (3, call, clobber,
8864 gen_rtx_USE (VOIDmode, tls_call));
8865 else
8866 vec = gen_rtvec (2, call, clobber);
8867
8868 call = gen_rtx_PARALLEL (VOIDmode, vec);
8869 }
8870
8871 insn = emit_call_insn (call);
8872
8873 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8874 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8875 {
8876 /* s390_function_ok_for_sibcall should
8877 have denied sibcalls in this case. */
8878 gcc_assert (retaddr_reg != NULL_RTX);
8879
8880 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8881 }
8882 return insn;
8883 }
8884
8885 /* Implement CONDITIONAL_REGISTER_USAGE. */
8886
8887 void
8888 s390_conditional_register_usage (void)
8889 {
8890 int i;
8891
8892 if (flag_pic)
8893 {
8894 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8895 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8896 }
8897 if (TARGET_CPU_ZARCH)
8898 {
8899 fixed_regs[BASE_REGNUM] = 0;
8900 call_used_regs[BASE_REGNUM] = 0;
8901 fixed_regs[RETURN_REGNUM] = 0;
8902 call_used_regs[RETURN_REGNUM] = 0;
8903 }
8904 if (TARGET_64BIT)
8905 {
8906 for (i = 24; i < 32; i++)
8907 call_used_regs[i] = call_really_used_regs[i] = 0;
8908 }
8909 else
8910 {
8911 for (i = 18; i < 20; i++)
8912 call_used_regs[i] = call_really_used_regs[i] = 0;
8913 }
8914
8915 if (TARGET_SOFT_FLOAT)
8916 {
8917 for (i = 16; i < 32; i++)
8918 call_used_regs[i] = fixed_regs[i] = 1;
8919 }
8920 }
8921
8922 /* Corresponding function to eh_return expander. */
8923
8924 static GTY(()) rtx s390_tpf_eh_return_symbol;
8925 void
8926 s390_emit_tpf_eh_return (rtx target)
8927 {
8928 rtx insn, reg;
8929
8930 if (!s390_tpf_eh_return_symbol)
8931 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8932
8933 reg = gen_rtx_REG (Pmode, 2);
8934
8935 emit_move_insn (reg, target);
8936 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8937 gen_rtx_REG (Pmode, RETURN_REGNUM));
8938 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8939
8940 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8941 }
8942
8943 /* Rework the prologue/epilogue to avoid saving/restoring
8944 registers unnecessarily. */
8945
8946 static void
8947 s390_optimize_prologue (void)
8948 {
8949 rtx insn, new_insn, next_insn;
8950
8951 /* Do a final recompute of the frame-related data. */
8952
8953 s390_update_frame_layout ();
8954
8955 /* If all special registers are in fact used, there's nothing we
8956 can do, so no point in walking the insn list. */
8957
8958 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8959 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8960 && (TARGET_CPU_ZARCH
8961 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8962 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8963 return;
8964
8965 /* Search for prologue/epilogue insns and replace them. */
8966
8967 for (insn = get_insns (); insn; insn = next_insn)
8968 {
8969 int first, last, off;
8970 rtx set, base, offset;
8971
8972 next_insn = NEXT_INSN (insn);
8973
8974 if (GET_CODE (insn) != INSN)
8975 continue;
8976
8977 if (GET_CODE (PATTERN (insn)) == PARALLEL
8978 && store_multiple_operation (PATTERN (insn), VOIDmode))
8979 {
8980 set = XVECEXP (PATTERN (insn), 0, 0);
8981 first = REGNO (SET_SRC (set));
8982 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8983 offset = const0_rtx;
8984 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8985 off = INTVAL (offset);
8986
8987 if (GET_CODE (base) != REG || off < 0)
8988 continue;
8989 if (cfun_frame_layout.first_save_gpr != -1
8990 && (cfun_frame_layout.first_save_gpr < first
8991 || cfun_frame_layout.last_save_gpr > last))
8992 continue;
8993 if (REGNO (base) != STACK_POINTER_REGNUM
8994 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8995 continue;
8996 if (first > BASE_REGNUM || last < BASE_REGNUM)
8997 continue;
8998
8999 if (cfun_frame_layout.first_save_gpr != -1)
9000 {
9001 new_insn = save_gprs (base,
9002 off + (cfun_frame_layout.first_save_gpr
9003 - first) * UNITS_PER_WORD,
9004 cfun_frame_layout.first_save_gpr,
9005 cfun_frame_layout.last_save_gpr);
9006 new_insn = emit_insn_before (new_insn, insn);
9007 INSN_ADDRESSES_NEW (new_insn, -1);
9008 }
9009
9010 remove_insn (insn);
9011 continue;
9012 }
9013
9014 if (cfun_frame_layout.first_save_gpr == -1
9015 && GET_CODE (PATTERN (insn)) == SET
9016 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9017 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9018 || (!TARGET_CPU_ZARCH
9019 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9020 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9021 {
9022 set = PATTERN (insn);
9023 first = REGNO (SET_SRC (set));
9024 offset = const0_rtx;
9025 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9026 off = INTVAL (offset);
9027
9028 if (GET_CODE (base) != REG || off < 0)
9029 continue;
9030 if (REGNO (base) != STACK_POINTER_REGNUM
9031 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9032 continue;
9033
9034 remove_insn (insn);
9035 continue;
9036 }
9037
9038 if (GET_CODE (PATTERN (insn)) == PARALLEL
9039 && load_multiple_operation (PATTERN (insn), VOIDmode))
9040 {
9041 set = XVECEXP (PATTERN (insn), 0, 0);
9042 first = REGNO (SET_DEST (set));
9043 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9044 offset = const0_rtx;
9045 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9046 off = INTVAL (offset);
9047
9048 if (GET_CODE (base) != REG || off < 0)
9049 continue;
9050 if (cfun_frame_layout.first_restore_gpr != -1
9051 && (cfun_frame_layout.first_restore_gpr < first
9052 || cfun_frame_layout.last_restore_gpr > last))
9053 continue;
9054 if (REGNO (base) != STACK_POINTER_REGNUM
9055 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9056 continue;
9057 if (first > BASE_REGNUM || last < BASE_REGNUM)
9058 continue;
9059
9060 if (cfun_frame_layout.first_restore_gpr != -1)
9061 {
9062 new_insn = restore_gprs (base,
9063 off + (cfun_frame_layout.first_restore_gpr
9064 - first) * UNITS_PER_WORD,
9065 cfun_frame_layout.first_restore_gpr,
9066 cfun_frame_layout.last_restore_gpr);
9067 new_insn = emit_insn_before (new_insn, insn);
9068 INSN_ADDRESSES_NEW (new_insn, -1);
9069 }
9070
9071 remove_insn (insn);
9072 continue;
9073 }
9074
9075 if (cfun_frame_layout.first_restore_gpr == -1
9076 && GET_CODE (PATTERN (insn)) == SET
9077 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9078 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9079 || (!TARGET_CPU_ZARCH
9080 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9081 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9082 {
9083 set = PATTERN (insn);
9084 first = REGNO (SET_DEST (set));
9085 offset = const0_rtx;
9086 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9087 off = INTVAL (offset);
9088
9089 if (GET_CODE (base) != REG || off < 0)
9090 continue;
9091 if (REGNO (base) != STACK_POINTER_REGNUM
9092 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9093 continue;
9094
9095 remove_insn (insn);
9096 continue;
9097 }
9098 }
9099 }
9100
9101 /* Perform machine-dependent processing. */
9102
9103 static void
9104 s390_reorg (void)
9105 {
9106 bool pool_overflow = false;
9107
9108 /* Make sure all splits have been performed; splits after
9109 machine_dependent_reorg might confuse insn length counts. */
9110 split_all_insns_noflow ();
9111
9112 /* From here on decomposed literal pool addresses must be accepted. */
9113 cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
9114
9115 /* Install the main literal pool and the associated base
9116 register load insns.
9117
9118 In addition, there are two problematic situations we need
9119 to correct:
9120
9121 - the literal pool might be > 4096 bytes in size, so that
9122 some of its elements cannot be directly accessed
9123
9124 - a branch target might be > 64K away from the branch, so that
9125 it is not possible to use a PC-relative instruction.
9126
9127 To fix those, we split the single literal pool into multiple
9128 pool chunks, reloading the pool base register at various
9129 points throughout the function to ensure it always points to
9130 the pool chunk the following code expects, and / or replace
9131 PC-relative branches by absolute branches.
9132
9133 However, the two problems are interdependent: splitting the
9134 literal pool can move a branch further away from its target,
9135 causing the 64K limit to overflow, and on the other hand,
9136 replacing a PC-relative branch by an absolute branch means
9137 we need to put the branch target address into the literal
9138 pool, possibly causing it to overflow.
9139
9140 So, we loop trying to fix up both problems until we manage
9141 to satisfy both conditions at the same time. Note that the
9142 loop is guaranteed to terminate as every pass of the loop
9143 strictly decreases the total number of PC-relative branches
9144 in the function. (This is not completely true as there
9145 might be branch-over-pool insns introduced by chunkify_start.
9146 Those never need to be split however.) */
9147
9148 for (;;)
9149 {
9150 struct constant_pool *pool = NULL;
9151
9152 /* Collect the literal pool. */
9153 if (!pool_overflow)
9154 {
9155 pool = s390_mainpool_start ();
9156 if (!pool)
9157 pool_overflow = true;
9158 }
9159
9160 /* If literal pool overflowed, start to chunkify it. */
9161 if (pool_overflow)
9162 pool = s390_chunkify_start ();
9163
9164 /* Split out-of-range branches. If this has created new
9165 literal pool entries, cancel current chunk list and
9166 recompute it. zSeries machines have large branch
9167 instructions, so we never need to split a branch. */
9168 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9169 {
9170 if (pool_overflow)
9171 s390_chunkify_cancel (pool);
9172 else
9173 s390_mainpool_cancel (pool);
9174
9175 continue;
9176 }
9177
9178 /* If we made it up to here, both conditions are satisfied.
9179 Finish up literal pool related changes. */
9180 if (pool_overflow)
9181 s390_chunkify_finish (pool);
9182 else
9183 s390_mainpool_finish (pool);
9184
9185 /* We're done splitting branches. */
9186 cfun->machine->split_branches_pending_p = false;
9187 break;
9188 }
9189
9190 /* Generate out-of-pool execute target insns. */
9191 if (TARGET_CPU_ZARCH)
9192 {
9193 rtx insn, label, target;
9194
9195 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9196 {
9197 label = s390_execute_label (insn);
9198 if (!label)
9199 continue;
9200
9201 gcc_assert (label != const0_rtx);
9202
9203 target = emit_label (XEXP (label, 0));
9204 INSN_ADDRESSES_NEW (target, -1);
9205
9206 target = emit_insn (s390_execute_target (insn));
9207 INSN_ADDRESSES_NEW (target, -1);
9208 }
9209 }
9210
9211 /* Try to optimize prologue and epilogue further. */
9212 s390_optimize_prologue ();
9213 }
9214
9215
9216 /* Initialize GCC target structure. */
9217
9218 #undef TARGET_ASM_ALIGNED_HI_OP
9219 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9220 #undef TARGET_ASM_ALIGNED_DI_OP
9221 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9222 #undef TARGET_ASM_INTEGER
9223 #define TARGET_ASM_INTEGER s390_assemble_integer
9224
9225 #undef TARGET_ASM_OPEN_PAREN
9226 #define TARGET_ASM_OPEN_PAREN ""
9227
9228 #undef TARGET_ASM_CLOSE_PAREN
9229 #define TARGET_ASM_CLOSE_PAREN ""
9230
9231 #undef TARGET_DEFAULT_TARGET_FLAGS
9232 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9233 #undef TARGET_HANDLE_OPTION
9234 #define TARGET_HANDLE_OPTION s390_handle_option
9235
9236 #undef TARGET_ENCODE_SECTION_INFO
9237 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9238
9239 #ifdef HAVE_AS_TLS
9240 #undef TARGET_HAVE_TLS
9241 #define TARGET_HAVE_TLS true
9242 #endif
9243 #undef TARGET_CANNOT_FORCE_CONST_MEM
9244 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9245
9246 #undef TARGET_DELEGITIMIZE_ADDRESS
9247 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9248
9249 #undef TARGET_RETURN_IN_MEMORY
9250 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9251
9252 #undef TARGET_INIT_BUILTINS
9253 #define TARGET_INIT_BUILTINS s390_init_builtins
9254 #undef TARGET_EXPAND_BUILTIN
9255 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9256
9257 #undef TARGET_ASM_OUTPUT_MI_THUNK
9258 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9259 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9260 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9261
9262 #undef TARGET_SCHED_ADJUST_PRIORITY
9263 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9264 #undef TARGET_SCHED_ISSUE_RATE
9265 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9266 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9267 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9268
9269 #undef TARGET_CANNOT_COPY_INSN_P
9270 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9271 #undef TARGET_RTX_COSTS
9272 #define TARGET_RTX_COSTS s390_rtx_costs
9273 #undef TARGET_ADDRESS_COST
9274 #define TARGET_ADDRESS_COST s390_address_cost
9275
9276 #undef TARGET_MACHINE_DEPENDENT_REORG
9277 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9278
9279 #undef TARGET_VALID_POINTER_MODE
9280 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9281
9282 #undef TARGET_BUILD_BUILTIN_VA_LIST
9283 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9284 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9285 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9286
9287 #undef TARGET_PROMOTE_FUNCTION_ARGS
9288 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9289 #undef TARGET_PROMOTE_FUNCTION_RETURN
9290 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9291 #undef TARGET_PASS_BY_REFERENCE
9292 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9293
9294 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9295 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9296
9297 #undef TARGET_FIXED_CONDITION_CODE_REGS
9298 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9299
9300 #undef TARGET_CC_MODES_COMPATIBLE
9301 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9302
9303 #undef TARGET_INVALID_WITHIN_DOLOOP
9304 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9305
9306 #ifdef HAVE_AS_TLS
9307 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9308 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9309 #endif
9310
9311 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9312 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
9313 #define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type
9314 #endif
9315
9316 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9317 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9318
9319 struct gcc_target targetm = TARGET_INITIALIZER;
9320
9321 #include "gt-s390.h"