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s390.c: Rename UNSPEC_CCU_TO_INT to UNSPEC_STRCMPCC_TO_INT and UNSPEC_CCZ_TO_INT...
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "tm_p.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "flags.h"
37 #include "except.h"
38 #include "function.h"
39 #include "recog.h"
40 #include "expr.h"
41 #include "reload.h"
42 #include "diagnostic-core.h"
43 #include "basic-block.h"
44 #include "ggc.h"
45 #include "target.h"
46 #include "target-def.h"
47 #include "debug.h"
48 #include "langhooks.h"
49 #include "optabs.h"
50 #include "gimple.h"
51 #include "df.h"
52 #include "params.h"
53 #include "cfgloop.h"
54 #include "opts.h"
55
56 /* Define the specific costs for a given cpu. */
57
58 struct processor_costs
59 {
60 /* multiplication */
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
74 const int mxbr;
75 /* square root */
76 const int sqxbr; /* cost of square root in TFmode. */
77 const int sqdbr; /* cost of square root in DFmode. */
78 const int sqebr; /* cost of square root in SFmode. */
79 /* multiply and add */
80 const int madbr; /* cost of multiply and add in DFmode. */
81 const int maebr; /* cost of multiply and add in SFmode. */
82 /* division */
83 const int dxbr;
84 const int ddbr;
85 const int debr;
86 const int dlgr;
87 const int dlr;
88 const int dr;
89 const int dsgfr;
90 const int dsgr;
91 };
92
93 const struct processor_costs *s390_cost;
94
95 static const
96 struct processor_costs z900_cost =
97 {
98 COSTS_N_INSNS (5), /* M */
99 COSTS_N_INSNS (10), /* MGHI */
100 COSTS_N_INSNS (5), /* MH */
101 COSTS_N_INSNS (4), /* MHI */
102 COSTS_N_INSNS (5), /* ML */
103 COSTS_N_INSNS (5), /* MR */
104 COSTS_N_INSNS (4), /* MS */
105 COSTS_N_INSNS (15), /* MSG */
106 COSTS_N_INSNS (7), /* MSGF */
107 COSTS_N_INSNS (7), /* MSGFR */
108 COSTS_N_INSNS (10), /* MSGR */
109 COSTS_N_INSNS (4), /* MSR */
110 COSTS_N_INSNS (7), /* multiplication in DFmode */
111 COSTS_N_INSNS (13), /* MXBR */
112 COSTS_N_INSNS (136), /* SQXBR */
113 COSTS_N_INSNS (44), /* SQDBR */
114 COSTS_N_INSNS (35), /* SQEBR */
115 COSTS_N_INSNS (18), /* MADBR */
116 COSTS_N_INSNS (13), /* MAEBR */
117 COSTS_N_INSNS (134), /* DXBR */
118 COSTS_N_INSNS (30), /* DDBR */
119 COSTS_N_INSNS (27), /* DEBR */
120 COSTS_N_INSNS (220), /* DLGR */
121 COSTS_N_INSNS (34), /* DLR */
122 COSTS_N_INSNS (34), /* DR */
123 COSTS_N_INSNS (32), /* DSGFR */
124 COSTS_N_INSNS (32), /* DSGR */
125 };
126
127 static const
128 struct processor_costs z990_cost =
129 {
130 COSTS_N_INSNS (4), /* M */
131 COSTS_N_INSNS (2), /* MGHI */
132 COSTS_N_INSNS (2), /* MH */
133 COSTS_N_INSNS (2), /* MHI */
134 COSTS_N_INSNS (4), /* ML */
135 COSTS_N_INSNS (4), /* MR */
136 COSTS_N_INSNS (5), /* MS */
137 COSTS_N_INSNS (6), /* MSG */
138 COSTS_N_INSNS (4), /* MSGF */
139 COSTS_N_INSNS (4), /* MSGFR */
140 COSTS_N_INSNS (4), /* MSGR */
141 COSTS_N_INSNS (4), /* MSR */
142 COSTS_N_INSNS (1), /* multiplication in DFmode */
143 COSTS_N_INSNS (28), /* MXBR */
144 COSTS_N_INSNS (130), /* SQXBR */
145 COSTS_N_INSNS (66), /* SQDBR */
146 COSTS_N_INSNS (38), /* SQEBR */
147 COSTS_N_INSNS (1), /* MADBR */
148 COSTS_N_INSNS (1), /* MAEBR */
149 COSTS_N_INSNS (60), /* DXBR */
150 COSTS_N_INSNS (40), /* DDBR */
151 COSTS_N_INSNS (26), /* DEBR */
152 COSTS_N_INSNS (176), /* DLGR */
153 COSTS_N_INSNS (31), /* DLR */
154 COSTS_N_INSNS (31), /* DR */
155 COSTS_N_INSNS (31), /* DSGFR */
156 COSTS_N_INSNS (31), /* DSGR */
157 };
158
159 static const
160 struct processor_costs z9_109_cost =
161 {
162 COSTS_N_INSNS (4), /* M */
163 COSTS_N_INSNS (2), /* MGHI */
164 COSTS_N_INSNS (2), /* MH */
165 COSTS_N_INSNS (2), /* MHI */
166 COSTS_N_INSNS (4), /* ML */
167 COSTS_N_INSNS (4), /* MR */
168 COSTS_N_INSNS (5), /* MS */
169 COSTS_N_INSNS (6), /* MSG */
170 COSTS_N_INSNS (4), /* MSGF */
171 COSTS_N_INSNS (4), /* MSGFR */
172 COSTS_N_INSNS (4), /* MSGR */
173 COSTS_N_INSNS (4), /* MSR */
174 COSTS_N_INSNS (1), /* multiplication in DFmode */
175 COSTS_N_INSNS (28), /* MXBR */
176 COSTS_N_INSNS (130), /* SQXBR */
177 COSTS_N_INSNS (66), /* SQDBR */
178 COSTS_N_INSNS (38), /* SQEBR */
179 COSTS_N_INSNS (1), /* MADBR */
180 COSTS_N_INSNS (1), /* MAEBR */
181 COSTS_N_INSNS (60), /* DXBR */
182 COSTS_N_INSNS (40), /* DDBR */
183 COSTS_N_INSNS (26), /* DEBR */
184 COSTS_N_INSNS (30), /* DLGR */
185 COSTS_N_INSNS (23), /* DLR */
186 COSTS_N_INSNS (23), /* DR */
187 COSTS_N_INSNS (24), /* DSGFR */
188 COSTS_N_INSNS (24), /* DSGR */
189 };
190
191 static const
192 struct processor_costs z10_cost =
193 {
194 COSTS_N_INSNS (10), /* M */
195 COSTS_N_INSNS (10), /* MGHI */
196 COSTS_N_INSNS (10), /* MH */
197 COSTS_N_INSNS (10), /* MHI */
198 COSTS_N_INSNS (10), /* ML */
199 COSTS_N_INSNS (10), /* MR */
200 COSTS_N_INSNS (10), /* MS */
201 COSTS_N_INSNS (10), /* MSG */
202 COSTS_N_INSNS (10), /* MSGF */
203 COSTS_N_INSNS (10), /* MSGFR */
204 COSTS_N_INSNS (10), /* MSGR */
205 COSTS_N_INSNS (10), /* MSR */
206 COSTS_N_INSNS (1) , /* multiplication in DFmode */
207 COSTS_N_INSNS (50), /* MXBR */
208 COSTS_N_INSNS (120), /* SQXBR */
209 COSTS_N_INSNS (52), /* SQDBR */
210 COSTS_N_INSNS (38), /* SQEBR */
211 COSTS_N_INSNS (1), /* MADBR */
212 COSTS_N_INSNS (1), /* MAEBR */
213 COSTS_N_INSNS (111), /* DXBR */
214 COSTS_N_INSNS (39), /* DDBR */
215 COSTS_N_INSNS (32), /* DEBR */
216 COSTS_N_INSNS (160), /* DLGR */
217 COSTS_N_INSNS (71), /* DLR */
218 COSTS_N_INSNS (71), /* DR */
219 COSTS_N_INSNS (71), /* DSGFR */
220 COSTS_N_INSNS (71), /* DSGR */
221 };
222
223 static const
224 struct processor_costs z196_cost =
225 {
226 COSTS_N_INSNS (7), /* M */
227 COSTS_N_INSNS (5), /* MGHI */
228 COSTS_N_INSNS (5), /* MH */
229 COSTS_N_INSNS (5), /* MHI */
230 COSTS_N_INSNS (7), /* ML */
231 COSTS_N_INSNS (7), /* MR */
232 COSTS_N_INSNS (6), /* MS */
233 COSTS_N_INSNS (8), /* MSG */
234 COSTS_N_INSNS (6), /* MSGF */
235 COSTS_N_INSNS (6), /* MSGFR */
236 COSTS_N_INSNS (8), /* MSGR */
237 COSTS_N_INSNS (6), /* MSR */
238 COSTS_N_INSNS (1) , /* multiplication in DFmode */
239 COSTS_N_INSNS (40), /* MXBR B+40 */
240 COSTS_N_INSNS (100), /* SQXBR B+100 */
241 COSTS_N_INSNS (42), /* SQDBR B+42 */
242 COSTS_N_INSNS (28), /* SQEBR B+28 */
243 COSTS_N_INSNS (1), /* MADBR B */
244 COSTS_N_INSNS (1), /* MAEBR B */
245 COSTS_N_INSNS (101), /* DXBR B+101 */
246 COSTS_N_INSNS (29), /* DDBR */
247 COSTS_N_INSNS (22), /* DEBR */
248 COSTS_N_INSNS (160), /* DLGR cracked */
249 COSTS_N_INSNS (160), /* DLR cracked */
250 COSTS_N_INSNS (160), /* DR expanded */
251 COSTS_N_INSNS (160), /* DSGFR cracked */
252 COSTS_N_INSNS (160), /* DSGR cracked */
253 };
254
255 static const
256 struct processor_costs zEC12_cost =
257 {
258 COSTS_N_INSNS (7), /* M */
259 COSTS_N_INSNS (5), /* MGHI */
260 COSTS_N_INSNS (5), /* MH */
261 COSTS_N_INSNS (5), /* MHI */
262 COSTS_N_INSNS (7), /* ML */
263 COSTS_N_INSNS (7), /* MR */
264 COSTS_N_INSNS (6), /* MS */
265 COSTS_N_INSNS (8), /* MSG */
266 COSTS_N_INSNS (6), /* MSGF */
267 COSTS_N_INSNS (6), /* MSGFR */
268 COSTS_N_INSNS (8), /* MSGR */
269 COSTS_N_INSNS (6), /* MSR */
270 COSTS_N_INSNS (1) , /* multiplication in DFmode */
271 COSTS_N_INSNS (40), /* MXBR B+40 */
272 COSTS_N_INSNS (100), /* SQXBR B+100 */
273 COSTS_N_INSNS (42), /* SQDBR B+42 */
274 COSTS_N_INSNS (28), /* SQEBR B+28 */
275 COSTS_N_INSNS (1), /* MADBR B */
276 COSTS_N_INSNS (1), /* MAEBR B */
277 COSTS_N_INSNS (131), /* DXBR B+131 */
278 COSTS_N_INSNS (29), /* DDBR */
279 COSTS_N_INSNS (22), /* DEBR */
280 COSTS_N_INSNS (160), /* DLGR cracked */
281 COSTS_N_INSNS (160), /* DLR cracked */
282 COSTS_N_INSNS (160), /* DR expanded */
283 COSTS_N_INSNS (160), /* DSGFR cracked */
284 COSTS_N_INSNS (160), /* DSGR cracked */
285 };
286
287 extern int reload_completed;
288
289 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
290 static rtx last_scheduled_insn;
291
292 /* Structure used to hold the components of a S/390 memory
293 address. A legitimate address on S/390 is of the general
294 form
295 base + index + displacement
296 where any of the components is optional.
297
298 base and index are registers of the class ADDR_REGS,
299 displacement is an unsigned 12-bit immediate constant. */
300
301 struct s390_address
302 {
303 rtx base;
304 rtx indx;
305 rtx disp;
306 bool pointer;
307 bool literal_pool;
308 };
309
310 /* The following structure is embedded in the machine
311 specific part of struct function. */
312
313 struct GTY (()) s390_frame_layout
314 {
315 /* Offset within stack frame. */
316 HOST_WIDE_INT gprs_offset;
317 HOST_WIDE_INT f0_offset;
318 HOST_WIDE_INT f4_offset;
319 HOST_WIDE_INT f8_offset;
320 HOST_WIDE_INT backchain_offset;
321
322 /* Number of first and last gpr where slots in the register
323 save area are reserved for. */
324 int first_save_gpr_slot;
325 int last_save_gpr_slot;
326
327 /* Number of first and last gpr to be saved, restored. */
328 int first_save_gpr;
329 int first_restore_gpr;
330 int last_save_gpr;
331 int last_restore_gpr;
332
333 /* Bits standing for floating point registers. Set, if the
334 respective register has to be saved. Starting with reg 16 (f0)
335 at the rightmost bit.
336 Bit 15 - 8 7 6 5 4 3 2 1 0
337 fpr 15 - 8 7 5 3 1 6 4 2 0
338 reg 31 - 24 23 22 21 20 19 18 17 16 */
339 unsigned int fpr_bitmap;
340
341 /* Number of floating point registers f8-f15 which must be saved. */
342 int high_fprs;
343
344 /* Set if return address needs to be saved.
345 This flag is set by s390_return_addr_rtx if it could not use
346 the initial value of r14 and therefore depends on r14 saved
347 to the stack. */
348 bool save_return_addr_p;
349
350 /* Size of stack frame. */
351 HOST_WIDE_INT frame_size;
352 };
353
354 /* Define the structure for the machine field in struct function. */
355
356 struct GTY(()) machine_function
357 {
358 struct s390_frame_layout frame_layout;
359
360 /* Literal pool base register. */
361 rtx base_reg;
362
363 /* True if we may need to perform branch splitting. */
364 bool split_branches_pending_p;
365
366 /* Some local-dynamic TLS symbol name. */
367 const char *some_ld_name;
368
369 bool has_landing_pad_p;
370
371 /* True if the current function may contain a tbegin clobbering
372 FPRs. */
373 bool tbegin_p;
374 };
375
376 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
377
378 #define cfun_frame_layout (cfun->machine->frame_layout)
379 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
380 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
381 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
382 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
383 (1 << (BITNUM)))
384 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
385 (1 << (BITNUM))))
386
387 /* Number of GPRs and FPRs used for argument passing. */
388 #define GP_ARG_NUM_REG 5
389 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
390
391 /* A couple of shortcuts. */
392 #define CONST_OK_FOR_J(x) \
393 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
394 #define CONST_OK_FOR_K(x) \
395 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
396 #define CONST_OK_FOR_Os(x) \
397 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
398 #define CONST_OK_FOR_Op(x) \
399 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
400 #define CONST_OK_FOR_On(x) \
401 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
402
403 #define REGNO_PAIR_OK(REGNO, MODE) \
404 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
405
406 /* That's the read ahead of the dynamic branch prediction unit in
407 bytes on a z10 (or higher) CPU. */
408 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
409
410 /* Return the alignment for LABEL. We default to the -falign-labels
411 value except for the literal pool base label. */
412 int
413 s390_label_align (rtx label)
414 {
415 rtx prev_insn = prev_active_insn (label);
416
417 if (prev_insn == NULL_RTX)
418 goto old;
419
420 prev_insn = single_set (prev_insn);
421
422 if (prev_insn == NULL_RTX)
423 goto old;
424
425 prev_insn = SET_SRC (prev_insn);
426
427 /* Don't align literal pool base labels. */
428 if (GET_CODE (prev_insn) == UNSPEC
429 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
430 return 0;
431
432 old:
433 return align_labels_log;
434 }
435
436 static enum machine_mode
437 s390_libgcc_cmp_return_mode (void)
438 {
439 return TARGET_64BIT ? DImode : SImode;
440 }
441
442 static enum machine_mode
443 s390_libgcc_shift_count_mode (void)
444 {
445 return TARGET_64BIT ? DImode : SImode;
446 }
447
448 static enum machine_mode
449 s390_unwind_word_mode (void)
450 {
451 return TARGET_64BIT ? DImode : SImode;
452 }
453
454 /* Return true if the back end supports mode MODE. */
455 static bool
456 s390_scalar_mode_supported_p (enum machine_mode mode)
457 {
458 /* In contrast to the default implementation reject TImode constants on 31bit
459 TARGET_ZARCH for ABI compliance. */
460 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
461 return false;
462
463 if (DECIMAL_FLOAT_MODE_P (mode))
464 return default_decimal_float_supported_p ();
465
466 return default_scalar_mode_supported_p (mode);
467 }
468
469 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
470
471 void
472 s390_set_has_landing_pad_p (bool value)
473 {
474 cfun->machine->has_landing_pad_p = value;
475 }
476
477 /* If two condition code modes are compatible, return a condition code
478 mode which is compatible with both. Otherwise, return
479 VOIDmode. */
480
481 static enum machine_mode
482 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
483 {
484 if (m1 == m2)
485 return m1;
486
487 switch (m1)
488 {
489 case CCZmode:
490 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
491 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
492 return m2;
493 return VOIDmode;
494
495 case CCSmode:
496 case CCUmode:
497 case CCTmode:
498 case CCSRmode:
499 case CCURmode:
500 case CCZ1mode:
501 if (m2 == CCZmode)
502 return m1;
503
504 return VOIDmode;
505
506 default:
507 return VOIDmode;
508 }
509 return VOIDmode;
510 }
511
512 /* Return true if SET either doesn't set the CC register, or else
513 the source and destination have matching CC modes and that
514 CC mode is at least as constrained as REQ_MODE. */
515
516 static bool
517 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
518 {
519 enum machine_mode set_mode;
520
521 gcc_assert (GET_CODE (set) == SET);
522
523 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
524 return 1;
525
526 set_mode = GET_MODE (SET_DEST (set));
527 switch (set_mode)
528 {
529 case CCSmode:
530 case CCSRmode:
531 case CCUmode:
532 case CCURmode:
533 case CCLmode:
534 case CCL1mode:
535 case CCL2mode:
536 case CCL3mode:
537 case CCT1mode:
538 case CCT2mode:
539 case CCT3mode:
540 if (req_mode != set_mode)
541 return 0;
542 break;
543
544 case CCZmode:
545 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
546 && req_mode != CCSRmode && req_mode != CCURmode)
547 return 0;
548 break;
549
550 case CCAPmode:
551 case CCANmode:
552 if (req_mode != CCAmode)
553 return 0;
554 break;
555
556 default:
557 gcc_unreachable ();
558 }
559
560 return (GET_MODE (SET_SRC (set)) == set_mode);
561 }
562
563 /* Return true if every SET in INSN that sets the CC register
564 has source and destination with matching CC modes and that
565 CC mode is at least as constrained as REQ_MODE.
566 If REQ_MODE is VOIDmode, always return false. */
567
568 bool
569 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
570 {
571 int i;
572
573 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
574 if (req_mode == VOIDmode)
575 return false;
576
577 if (GET_CODE (PATTERN (insn)) == SET)
578 return s390_match_ccmode_set (PATTERN (insn), req_mode);
579
580 if (GET_CODE (PATTERN (insn)) == PARALLEL)
581 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
582 {
583 rtx set = XVECEXP (PATTERN (insn), 0, i);
584 if (GET_CODE (set) == SET)
585 if (!s390_match_ccmode_set (set, req_mode))
586 return false;
587 }
588
589 return true;
590 }
591
592 /* If a test-under-mask instruction can be used to implement
593 (compare (and ... OP1) OP2), return the CC mode required
594 to do that. Otherwise, return VOIDmode.
595 MIXED is true if the instruction can distinguish between
596 CC1 and CC2 for mixed selected bits (TMxx), it is false
597 if the instruction cannot (TM). */
598
599 enum machine_mode
600 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
601 {
602 int bit0, bit1;
603
604 /* ??? Fixme: should work on CONST_DOUBLE as well. */
605 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
606 return VOIDmode;
607
608 /* Selected bits all zero: CC0.
609 e.g.: int a; if ((a & (16 + 128)) == 0) */
610 if (INTVAL (op2) == 0)
611 return CCTmode;
612
613 /* Selected bits all one: CC3.
614 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
615 if (INTVAL (op2) == INTVAL (op1))
616 return CCT3mode;
617
618 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
619 int a;
620 if ((a & (16 + 128)) == 16) -> CCT1
621 if ((a & (16 + 128)) == 128) -> CCT2 */
622 if (mixed)
623 {
624 bit1 = exact_log2 (INTVAL (op2));
625 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
626 if (bit0 != -1 && bit1 != -1)
627 return bit0 > bit1 ? CCT1mode : CCT2mode;
628 }
629
630 return VOIDmode;
631 }
632
633 /* Given a comparison code OP (EQ, NE, etc.) and the operands
634 OP0 and OP1 of a COMPARE, return the mode to be used for the
635 comparison. */
636
637 enum machine_mode
638 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
639 {
640 switch (code)
641 {
642 case EQ:
643 case NE:
644 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
645 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
646 return CCAPmode;
647 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
648 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
649 return CCAPmode;
650 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
651 || GET_CODE (op1) == NEG)
652 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
653 return CCLmode;
654
655 if (GET_CODE (op0) == AND)
656 {
657 /* Check whether we can potentially do it via TM. */
658 enum machine_mode ccmode;
659 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
660 if (ccmode != VOIDmode)
661 {
662 /* Relax CCTmode to CCZmode to allow fall-back to AND
663 if that turns out to be beneficial. */
664 return ccmode == CCTmode ? CCZmode : ccmode;
665 }
666 }
667
668 if (register_operand (op0, HImode)
669 && GET_CODE (op1) == CONST_INT
670 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
671 return CCT3mode;
672 if (register_operand (op0, QImode)
673 && GET_CODE (op1) == CONST_INT
674 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
675 return CCT3mode;
676
677 return CCZmode;
678
679 case LE:
680 case LT:
681 case GE:
682 case GT:
683 /* The only overflow condition of NEG and ABS happens when
684 -INT_MAX is used as parameter, which stays negative. So
685 we have an overflow from a positive value to a negative.
686 Using CCAP mode the resulting cc can be used for comparisons. */
687 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
688 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
689 return CCAPmode;
690
691 /* If constants are involved in an add instruction it is possible to use
692 the resulting cc for comparisons with zero. Knowing the sign of the
693 constant the overflow behavior gets predictable. e.g.:
694 int a, b; if ((b = a + c) > 0)
695 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
696 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
697 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
698 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
699 /* Avoid INT32_MIN on 32 bit. */
700 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
701 {
702 if (INTVAL (XEXP((op0), 1)) < 0)
703 return CCANmode;
704 else
705 return CCAPmode;
706 }
707 /* Fall through. */
708 case UNORDERED:
709 case ORDERED:
710 case UNEQ:
711 case UNLE:
712 case UNLT:
713 case UNGE:
714 case UNGT:
715 case LTGT:
716 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
717 && GET_CODE (op1) != CONST_INT)
718 return CCSRmode;
719 return CCSmode;
720
721 case LTU:
722 case GEU:
723 if (GET_CODE (op0) == PLUS
724 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
725 return CCL1mode;
726
727 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
728 && GET_CODE (op1) != CONST_INT)
729 return CCURmode;
730 return CCUmode;
731
732 case LEU:
733 case GTU:
734 if (GET_CODE (op0) == MINUS
735 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
736 return CCL2mode;
737
738 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
739 && GET_CODE (op1) != CONST_INT)
740 return CCURmode;
741 return CCUmode;
742
743 default:
744 gcc_unreachable ();
745 }
746 }
747
748 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
749 that we can implement more efficiently. */
750
751 static void
752 s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
753 bool op0_preserve_value)
754 {
755 if (op0_preserve_value)
756 return;
757
758 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
759 if ((*code == EQ || *code == NE)
760 && *op1 == const0_rtx
761 && GET_CODE (*op0) == ZERO_EXTRACT
762 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
763 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
764 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
765 {
766 rtx inner = XEXP (*op0, 0);
767 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
768 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
769 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
770
771 if (len > 0 && len < modesize
772 && pos >= 0 && pos + len <= modesize
773 && modesize <= HOST_BITS_PER_WIDE_INT)
774 {
775 unsigned HOST_WIDE_INT block;
776 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
777 block <<= modesize - pos - len;
778
779 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
780 gen_int_mode (block, GET_MODE (inner)));
781 }
782 }
783
784 /* Narrow AND of memory against immediate to enable TM. */
785 if ((*code == EQ || *code == NE)
786 && *op1 == const0_rtx
787 && GET_CODE (*op0) == AND
788 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
789 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
790 {
791 rtx inner = XEXP (*op0, 0);
792 rtx mask = XEXP (*op0, 1);
793
794 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
795 if (GET_CODE (inner) == SUBREG
796 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
797 && (GET_MODE_SIZE (GET_MODE (inner))
798 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
799 && ((INTVAL (mask)
800 & GET_MODE_MASK (GET_MODE (inner))
801 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
802 == 0))
803 inner = SUBREG_REG (inner);
804
805 /* Do not change volatile MEMs. */
806 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
807 {
808 int part = s390_single_part (XEXP (*op0, 1),
809 GET_MODE (inner), QImode, 0);
810 if (part >= 0)
811 {
812 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
813 inner = adjust_address_nv (inner, QImode, part);
814 *op0 = gen_rtx_AND (QImode, inner, mask);
815 }
816 }
817 }
818
819 /* Narrow comparisons against 0xffff to HImode if possible. */
820 if ((*code == EQ || *code == NE)
821 && GET_CODE (*op1) == CONST_INT
822 && INTVAL (*op1) == 0xffff
823 && SCALAR_INT_MODE_P (GET_MODE (*op0))
824 && (nonzero_bits (*op0, GET_MODE (*op0))
825 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
826 {
827 *op0 = gen_lowpart (HImode, *op0);
828 *op1 = constm1_rtx;
829 }
830
831 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
832 if (GET_CODE (*op0) == UNSPEC
833 && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
834 && XVECLEN (*op0, 0) == 1
835 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
836 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
837 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
838 && *op1 == const0_rtx)
839 {
840 enum rtx_code new_code = UNKNOWN;
841 switch (*code)
842 {
843 case EQ: new_code = EQ; break;
844 case NE: new_code = NE; break;
845 case LT: new_code = GTU; break;
846 case GT: new_code = LTU; break;
847 case LE: new_code = GEU; break;
848 case GE: new_code = LEU; break;
849 default: break;
850 }
851
852 if (new_code != UNKNOWN)
853 {
854 *op0 = XVECEXP (*op0, 0, 0);
855 *code = new_code;
856 }
857 }
858
859 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
860 if (GET_CODE (*op0) == UNSPEC
861 && XINT (*op0, 1) == UNSPEC_CC_TO_INT
862 && XVECLEN (*op0, 0) == 1
863 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
864 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
865 && CONST_INT_P (*op1))
866 {
867 enum rtx_code new_code = UNKNOWN;
868 switch (GET_MODE (XVECEXP (*op0, 0, 0)))
869 {
870 case CCZmode:
871 case CCRAWmode:
872 switch (*code)
873 {
874 case EQ: new_code = EQ; break;
875 case NE: new_code = NE; break;
876 default: break;
877 }
878 break;
879 default: break;
880 }
881
882 if (new_code != UNKNOWN)
883 {
884 /* For CCRAWmode put the required cc mask into the second
885 operand. */
886 if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode)
887 *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
888 *op0 = XVECEXP (*op0, 0, 0);
889 *code = new_code;
890 }
891 }
892
893 /* Simplify cascaded EQ, NE with const0_rtx. */
894 if ((*code == NE || *code == EQ)
895 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
896 && GET_MODE (*op0) == SImode
897 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
898 && REG_P (XEXP (*op0, 0))
899 && XEXP (*op0, 1) == const0_rtx
900 && *op1 == const0_rtx)
901 {
902 if ((*code == EQ && GET_CODE (*op0) == NE)
903 || (*code == NE && GET_CODE (*op0) == EQ))
904 *code = EQ;
905 else
906 *code = NE;
907 *op0 = XEXP (*op0, 0);
908 }
909
910 /* Prefer register over memory as first operand. */
911 if (MEM_P (*op0) && REG_P (*op1))
912 {
913 rtx tem = *op0; *op0 = *op1; *op1 = tem;
914 *code = (int)swap_condition ((enum rtx_code)*code);
915 }
916 }
917
918 /* Emit a compare instruction suitable to implement the comparison
919 OP0 CODE OP1. Return the correct condition RTL to be placed in
920 the IF_THEN_ELSE of the conditional branch testing the result. */
921
922 rtx
923 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
924 {
925 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
926 rtx cc;
927
928 /* Do not output a redundant compare instruction if a compare_and_swap
929 pattern already computed the result and the machine modes are compatible. */
930 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
931 {
932 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
933 == GET_MODE (op0));
934 cc = op0;
935 }
936 else
937 {
938 cc = gen_rtx_REG (mode, CC_REGNUM);
939 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
940 }
941
942 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
943 }
944
945 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
946 matches CMP.
947 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
948 conditional branch testing the result. */
949
950 static rtx
951 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
952 rtx cmp, rtx new_rtx)
953 {
954 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
955 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
956 const0_rtx);
957 }
958
959 /* Emit a jump instruction to TARGET and return it. If COND is
960 NULL_RTX, emit an unconditional jump, else a conditional jump under
961 condition COND. */
962
963 rtx
964 s390_emit_jump (rtx target, rtx cond)
965 {
966 rtx insn;
967
968 target = gen_rtx_LABEL_REF (VOIDmode, target);
969 if (cond)
970 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
971
972 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
973 return emit_jump_insn (insn);
974 }
975
976 /* Return branch condition mask to implement a branch
977 specified by CODE. Return -1 for invalid comparisons. */
978
979 int
980 s390_branch_condition_mask (rtx code)
981 {
982 const int CC0 = 1 << 3;
983 const int CC1 = 1 << 2;
984 const int CC2 = 1 << 1;
985 const int CC3 = 1 << 0;
986
987 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
988 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
989 gcc_assert (XEXP (code, 1) == const0_rtx
990 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
991 && CONST_INT_P (XEXP (code, 1))));
992
993
994 switch (GET_MODE (XEXP (code, 0)))
995 {
996 case CCZmode:
997 case CCZ1mode:
998 switch (GET_CODE (code))
999 {
1000 case EQ: return CC0;
1001 case NE: return CC1 | CC2 | CC3;
1002 default: return -1;
1003 }
1004 break;
1005
1006 case CCT1mode:
1007 switch (GET_CODE (code))
1008 {
1009 case EQ: return CC1;
1010 case NE: return CC0 | CC2 | CC3;
1011 default: return -1;
1012 }
1013 break;
1014
1015 case CCT2mode:
1016 switch (GET_CODE (code))
1017 {
1018 case EQ: return CC2;
1019 case NE: return CC0 | CC1 | CC3;
1020 default: return -1;
1021 }
1022 break;
1023
1024 case CCT3mode:
1025 switch (GET_CODE (code))
1026 {
1027 case EQ: return CC3;
1028 case NE: return CC0 | CC1 | CC2;
1029 default: return -1;
1030 }
1031 break;
1032
1033 case CCLmode:
1034 switch (GET_CODE (code))
1035 {
1036 case EQ: return CC0 | CC2;
1037 case NE: return CC1 | CC3;
1038 default: return -1;
1039 }
1040 break;
1041
1042 case CCL1mode:
1043 switch (GET_CODE (code))
1044 {
1045 case LTU: return CC2 | CC3; /* carry */
1046 case GEU: return CC0 | CC1; /* no carry */
1047 default: return -1;
1048 }
1049 break;
1050
1051 case CCL2mode:
1052 switch (GET_CODE (code))
1053 {
1054 case GTU: return CC0 | CC1; /* borrow */
1055 case LEU: return CC2 | CC3; /* no borrow */
1056 default: return -1;
1057 }
1058 break;
1059
1060 case CCL3mode:
1061 switch (GET_CODE (code))
1062 {
1063 case EQ: return CC0 | CC2;
1064 case NE: return CC1 | CC3;
1065 case LTU: return CC1;
1066 case GTU: return CC3;
1067 case LEU: return CC1 | CC2;
1068 case GEU: return CC2 | CC3;
1069 default: return -1;
1070 }
1071
1072 case CCUmode:
1073 switch (GET_CODE (code))
1074 {
1075 case EQ: return CC0;
1076 case NE: return CC1 | CC2 | CC3;
1077 case LTU: return CC1;
1078 case GTU: return CC2;
1079 case LEU: return CC0 | CC1;
1080 case GEU: return CC0 | CC2;
1081 default: return -1;
1082 }
1083 break;
1084
1085 case CCURmode:
1086 switch (GET_CODE (code))
1087 {
1088 case EQ: return CC0;
1089 case NE: return CC2 | CC1 | CC3;
1090 case LTU: return CC2;
1091 case GTU: return CC1;
1092 case LEU: return CC0 | CC2;
1093 case GEU: return CC0 | CC1;
1094 default: return -1;
1095 }
1096 break;
1097
1098 case CCAPmode:
1099 switch (GET_CODE (code))
1100 {
1101 case EQ: return CC0;
1102 case NE: return CC1 | CC2 | CC3;
1103 case LT: return CC1 | CC3;
1104 case GT: return CC2;
1105 case LE: return CC0 | CC1 | CC3;
1106 case GE: return CC0 | CC2;
1107 default: return -1;
1108 }
1109 break;
1110
1111 case CCANmode:
1112 switch (GET_CODE (code))
1113 {
1114 case EQ: return CC0;
1115 case NE: return CC1 | CC2 | CC3;
1116 case LT: return CC1;
1117 case GT: return CC2 | CC3;
1118 case LE: return CC0 | CC1;
1119 case GE: return CC0 | CC2 | CC3;
1120 default: return -1;
1121 }
1122 break;
1123
1124 case CCSmode:
1125 switch (GET_CODE (code))
1126 {
1127 case EQ: return CC0;
1128 case NE: return CC1 | CC2 | CC3;
1129 case LT: return CC1;
1130 case GT: return CC2;
1131 case LE: return CC0 | CC1;
1132 case GE: return CC0 | CC2;
1133 case UNORDERED: return CC3;
1134 case ORDERED: return CC0 | CC1 | CC2;
1135 case UNEQ: return CC0 | CC3;
1136 case UNLT: return CC1 | CC3;
1137 case UNGT: return CC2 | CC3;
1138 case UNLE: return CC0 | CC1 | CC3;
1139 case UNGE: return CC0 | CC2 | CC3;
1140 case LTGT: return CC1 | CC2;
1141 default: return -1;
1142 }
1143 break;
1144
1145 case CCSRmode:
1146 switch (GET_CODE (code))
1147 {
1148 case EQ: return CC0;
1149 case NE: return CC2 | CC1 | CC3;
1150 case LT: return CC2;
1151 case GT: return CC1;
1152 case LE: return CC0 | CC2;
1153 case GE: return CC0 | CC1;
1154 case UNORDERED: return CC3;
1155 case ORDERED: return CC0 | CC2 | CC1;
1156 case UNEQ: return CC0 | CC3;
1157 case UNLT: return CC2 | CC3;
1158 case UNGT: return CC1 | CC3;
1159 case UNLE: return CC0 | CC2 | CC3;
1160 case UNGE: return CC0 | CC1 | CC3;
1161 case LTGT: return CC2 | CC1;
1162 default: return -1;
1163 }
1164 break;
1165
1166 case CCRAWmode:
1167 switch (GET_CODE (code))
1168 {
1169 case EQ:
1170 return INTVAL (XEXP (code, 1));
1171 case NE:
1172 return (INTVAL (XEXP (code, 1))) ^ 0xf;
1173 default:
1174 gcc_unreachable ();
1175 }
1176
1177 default:
1178 return -1;
1179 }
1180 }
1181
1182
1183 /* Return branch condition mask to implement a compare and branch
1184 specified by CODE. Return -1 for invalid comparisons. */
1185
1186 int
1187 s390_compare_and_branch_condition_mask (rtx code)
1188 {
1189 const int CC0 = 1 << 3;
1190 const int CC1 = 1 << 2;
1191 const int CC2 = 1 << 1;
1192
1193 switch (GET_CODE (code))
1194 {
1195 case EQ:
1196 return CC0;
1197 case NE:
1198 return CC1 | CC2;
1199 case LT:
1200 case LTU:
1201 return CC1;
1202 case GT:
1203 case GTU:
1204 return CC2;
1205 case LE:
1206 case LEU:
1207 return CC0 | CC1;
1208 case GE:
1209 case GEU:
1210 return CC0 | CC2;
1211 default:
1212 gcc_unreachable ();
1213 }
1214 return -1;
1215 }
1216
1217 /* If INV is false, return assembler mnemonic string to implement
1218 a branch specified by CODE. If INV is true, return mnemonic
1219 for the corresponding inverted branch. */
1220
1221 static const char *
1222 s390_branch_condition_mnemonic (rtx code, int inv)
1223 {
1224 int mask;
1225
1226 static const char *const mnemonic[16] =
1227 {
1228 NULL, "o", "h", "nle",
1229 "l", "nhe", "lh", "ne",
1230 "e", "nlh", "he", "nl",
1231 "le", "nh", "no", NULL
1232 };
1233
1234 if (GET_CODE (XEXP (code, 0)) == REG
1235 && REGNO (XEXP (code, 0)) == CC_REGNUM
1236 && (XEXP (code, 1) == const0_rtx
1237 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1238 && CONST_INT_P (XEXP (code, 1)))))
1239 mask = s390_branch_condition_mask (code);
1240 else
1241 mask = s390_compare_and_branch_condition_mask (code);
1242
1243 gcc_assert (mask >= 0);
1244
1245 if (inv)
1246 mask ^= 15;
1247
1248 gcc_assert (mask >= 1 && mask <= 14);
1249
1250 return mnemonic[mask];
1251 }
1252
1253 /* Return the part of op which has a value different from def.
1254 The size of the part is determined by mode.
1255 Use this function only if you already know that op really
1256 contains such a part. */
1257
1258 unsigned HOST_WIDE_INT
1259 s390_extract_part (rtx op, enum machine_mode mode, int def)
1260 {
1261 unsigned HOST_WIDE_INT value = 0;
1262 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1263 int part_bits = GET_MODE_BITSIZE (mode);
1264 unsigned HOST_WIDE_INT part_mask
1265 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1266 int i;
1267
1268 for (i = 0; i < max_parts; i++)
1269 {
1270 if (i == 0)
1271 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1272 else
1273 value >>= part_bits;
1274
1275 if ((value & part_mask) != (def & part_mask))
1276 return value & part_mask;
1277 }
1278
1279 gcc_unreachable ();
1280 }
1281
1282 /* If OP is an integer constant of mode MODE with exactly one
1283 part of mode PART_MODE unequal to DEF, return the number of that
1284 part. Otherwise, return -1. */
1285
1286 int
1287 s390_single_part (rtx op,
1288 enum machine_mode mode,
1289 enum machine_mode part_mode,
1290 int def)
1291 {
1292 unsigned HOST_WIDE_INT value = 0;
1293 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1294 unsigned HOST_WIDE_INT part_mask
1295 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1296 int i, part = -1;
1297
1298 if (GET_CODE (op) != CONST_INT)
1299 return -1;
1300
1301 for (i = 0; i < n_parts; i++)
1302 {
1303 if (i == 0)
1304 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1305 else
1306 value >>= GET_MODE_BITSIZE (part_mode);
1307
1308 if ((value & part_mask) != (def & part_mask))
1309 {
1310 if (part != -1)
1311 return -1;
1312 else
1313 part = i;
1314 }
1315 }
1316 return part == -1 ? -1 : n_parts - 1 - part;
1317 }
1318
1319 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1320 bits and no other bits are set in IN. POS and LENGTH can be used
1321 to obtain the start position and the length of the bitfield.
1322
1323 POS gives the position of the first bit of the bitfield counting
1324 from the lowest order bit starting with zero. In order to use this
1325 value for S/390 instructions this has to be converted to "bits big
1326 endian" style. */
1327
1328 bool
1329 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1330 int *pos, int *length)
1331 {
1332 int tmp_pos = 0;
1333 int tmp_length = 0;
1334 int i;
1335 unsigned HOST_WIDE_INT mask = 1ULL;
1336 bool contiguous = false;
1337
1338 for (i = 0; i < size; mask <<= 1, i++)
1339 {
1340 if (contiguous)
1341 {
1342 if (mask & in)
1343 tmp_length++;
1344 else
1345 break;
1346 }
1347 else
1348 {
1349 if (mask & in)
1350 {
1351 contiguous = true;
1352 tmp_length++;
1353 }
1354 else
1355 tmp_pos++;
1356 }
1357 }
1358
1359 if (!tmp_length)
1360 return false;
1361
1362 /* Calculate a mask for all bits beyond the contiguous bits. */
1363 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1364
1365 if (mask & in)
1366 return false;
1367
1368 if (tmp_length + tmp_pos - 1 > size)
1369 return false;
1370
1371 if (length)
1372 *length = tmp_length;
1373
1374 if (pos)
1375 *pos = tmp_pos;
1376
1377 return true;
1378 }
1379
1380 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
1381 equivalent to a shift followed by the AND. In particular, CONTIG
1382 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1383 for ROTL indicate a rotate to the right. */
1384
1385 bool
1386 s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
1387 {
1388 int pos, len;
1389 bool ok;
1390
1391 ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
1392 gcc_assert (ok);
1393
1394 return ((rotl >= 0 && rotl <= pos)
1395 || (rotl < 0 && -rotl <= bitsize - len - pos));
1396 }
1397
1398 /* Check whether we can (and want to) split a double-word
1399 move in mode MODE from SRC to DST into two single-word
1400 moves, moving the subword FIRST_SUBWORD first. */
1401
1402 bool
1403 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1404 {
1405 /* Floating point registers cannot be split. */
1406 if (FP_REG_P (src) || FP_REG_P (dst))
1407 return false;
1408
1409 /* We don't need to split if operands are directly accessible. */
1410 if (s_operand (src, mode) || s_operand (dst, mode))
1411 return false;
1412
1413 /* Non-offsettable memory references cannot be split. */
1414 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1415 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1416 return false;
1417
1418 /* Moving the first subword must not clobber a register
1419 needed to move the second subword. */
1420 if (register_operand (dst, mode))
1421 {
1422 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1423 if (reg_overlap_mentioned_p (subreg, src))
1424 return false;
1425 }
1426
1427 return true;
1428 }
1429
1430 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1431 and [MEM2, MEM2 + SIZE] do overlap and false
1432 otherwise. */
1433
1434 bool
1435 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1436 {
1437 rtx addr1, addr2, addr_delta;
1438 HOST_WIDE_INT delta;
1439
1440 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1441 return true;
1442
1443 if (size == 0)
1444 return false;
1445
1446 addr1 = XEXP (mem1, 0);
1447 addr2 = XEXP (mem2, 0);
1448
1449 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1450
1451 /* This overlapping check is used by peepholes merging memory block operations.
1452 Overlapping operations would otherwise be recognized by the S/390 hardware
1453 and would fall back to a slower implementation. Allowing overlapping
1454 operations would lead to slow code but not to wrong code. Therefore we are
1455 somewhat optimistic if we cannot prove that the memory blocks are
1456 overlapping.
1457 That's why we return false here although this may accept operations on
1458 overlapping memory areas. */
1459 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1460 return false;
1461
1462 delta = INTVAL (addr_delta);
1463
1464 if (delta == 0
1465 || (delta > 0 && delta < size)
1466 || (delta < 0 && -delta < size))
1467 return true;
1468
1469 return false;
1470 }
1471
1472 /* Check whether the address of memory reference MEM2 equals exactly
1473 the address of memory reference MEM1 plus DELTA. Return true if
1474 we can prove this to be the case, false otherwise. */
1475
1476 bool
1477 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1478 {
1479 rtx addr1, addr2, addr_delta;
1480
1481 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1482 return false;
1483
1484 addr1 = XEXP (mem1, 0);
1485 addr2 = XEXP (mem2, 0);
1486
1487 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1488 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1489 return false;
1490
1491 return true;
1492 }
1493
1494 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1495
1496 void
1497 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1498 rtx *operands)
1499 {
1500 enum machine_mode wmode = mode;
1501 rtx dst = operands[0];
1502 rtx src1 = operands[1];
1503 rtx src2 = operands[2];
1504 rtx op, clob, tem;
1505
1506 /* If we cannot handle the operation directly, use a temp register. */
1507 if (!s390_logical_operator_ok_p (operands))
1508 dst = gen_reg_rtx (mode);
1509
1510 /* QImode and HImode patterns make sense only if we have a destination
1511 in memory. Otherwise perform the operation in SImode. */
1512 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1513 wmode = SImode;
1514
1515 /* Widen operands if required. */
1516 if (mode != wmode)
1517 {
1518 if (GET_CODE (dst) == SUBREG
1519 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1520 dst = tem;
1521 else if (REG_P (dst))
1522 dst = gen_rtx_SUBREG (wmode, dst, 0);
1523 else
1524 dst = gen_reg_rtx (wmode);
1525
1526 if (GET_CODE (src1) == SUBREG
1527 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1528 src1 = tem;
1529 else if (GET_MODE (src1) != VOIDmode)
1530 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1531
1532 if (GET_CODE (src2) == SUBREG
1533 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1534 src2 = tem;
1535 else if (GET_MODE (src2) != VOIDmode)
1536 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1537 }
1538
1539 /* Emit the instruction. */
1540 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1541 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1542 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1543
1544 /* Fix up the destination if needed. */
1545 if (dst != operands[0])
1546 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1547 }
1548
1549 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1550
1551 bool
1552 s390_logical_operator_ok_p (rtx *operands)
1553 {
1554 /* If the destination operand is in memory, it needs to coincide
1555 with one of the source operands. After reload, it has to be
1556 the first source operand. */
1557 if (GET_CODE (operands[0]) == MEM)
1558 return rtx_equal_p (operands[0], operands[1])
1559 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1560
1561 return true;
1562 }
1563
1564 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1565 operand IMMOP to switch from SS to SI type instructions. */
1566
1567 void
1568 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1569 {
1570 int def = code == AND ? -1 : 0;
1571 HOST_WIDE_INT mask;
1572 int part;
1573
1574 gcc_assert (GET_CODE (*memop) == MEM);
1575 gcc_assert (!MEM_VOLATILE_P (*memop));
1576
1577 mask = s390_extract_part (*immop, QImode, def);
1578 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1579 gcc_assert (part >= 0);
1580
1581 *memop = adjust_address (*memop, QImode, part);
1582 *immop = gen_int_mode (mask, QImode);
1583 }
1584
1585
1586 /* How to allocate a 'struct machine_function'. */
1587
1588 static struct machine_function *
1589 s390_init_machine_status (void)
1590 {
1591 return ggc_alloc_cleared_machine_function ();
1592 }
1593
1594 static void
1595 s390_option_override (void)
1596 {
1597 /* Set up function hooks. */
1598 init_machine_status = s390_init_machine_status;
1599
1600 /* Architecture mode defaults according to ABI. */
1601 if (!(target_flags_explicit & MASK_ZARCH))
1602 {
1603 if (TARGET_64BIT)
1604 target_flags |= MASK_ZARCH;
1605 else
1606 target_flags &= ~MASK_ZARCH;
1607 }
1608
1609 /* Set the march default in case it hasn't been specified on
1610 cmdline. */
1611 if (s390_arch == PROCESSOR_max)
1612 {
1613 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1614 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1615 s390_arch_flags = processor_flags_table[(int)s390_arch];
1616 }
1617
1618 /* Determine processor to tune for. */
1619 if (s390_tune == PROCESSOR_max)
1620 {
1621 s390_tune = s390_arch;
1622 s390_tune_flags = s390_arch_flags;
1623 }
1624
1625 /* Sanity checks. */
1626 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1627 error ("z/Architecture mode not supported on %s", s390_arch_string);
1628 if (TARGET_64BIT && !TARGET_ZARCH)
1629 error ("64-bit ABI not supported in ESA/390 mode");
1630
1631 /* Use hardware DFP if available and not explicitly disabled by
1632 user. E.g. with -m31 -march=z10 -mzarch */
1633 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1634 target_flags |= MASK_HARD_DFP;
1635
1636 /* Enable hardware transactions if available and not explicitly
1637 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
1638 if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH)
1639 target_flags |= MASK_OPT_HTM;
1640
1641 if (TARGET_HARD_DFP && !TARGET_DFP)
1642 {
1643 if (target_flags_explicit & MASK_HARD_DFP)
1644 {
1645 if (!TARGET_CPU_DFP)
1646 error ("hardware decimal floating point instructions"
1647 " not available on %s", s390_arch_string);
1648 if (!TARGET_ZARCH)
1649 error ("hardware decimal floating point instructions"
1650 " not available in ESA/390 mode");
1651 }
1652 else
1653 target_flags &= ~MASK_HARD_DFP;
1654 }
1655
1656 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1657 {
1658 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1659 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1660
1661 target_flags &= ~MASK_HARD_DFP;
1662 }
1663
1664 /* Set processor cost function. */
1665 switch (s390_tune)
1666 {
1667 case PROCESSOR_2084_Z990:
1668 s390_cost = &z990_cost;
1669 break;
1670 case PROCESSOR_2094_Z9_109:
1671 s390_cost = &z9_109_cost;
1672 break;
1673 case PROCESSOR_2097_Z10:
1674 s390_cost = &z10_cost;
1675 break;
1676 case PROCESSOR_2817_Z196:
1677 s390_cost = &z196_cost;
1678 break;
1679 case PROCESSOR_2827_ZEC12:
1680 s390_cost = &zEC12_cost;
1681 break;
1682 default:
1683 s390_cost = &z900_cost;
1684 }
1685
1686 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1687 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1688 "in combination");
1689
1690 if (s390_stack_size)
1691 {
1692 if (s390_stack_guard >= s390_stack_size)
1693 error ("stack size must be greater than the stack guard value");
1694 else if (s390_stack_size > 1 << 16)
1695 error ("stack size must not be greater than 64k");
1696 }
1697 else if (s390_stack_guard)
1698 error ("-mstack-guard implies use of -mstack-size");
1699
1700 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1701 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1702 target_flags |= MASK_LONG_DOUBLE_128;
1703 #endif
1704
1705 if (s390_tune == PROCESSOR_2097_Z10
1706 || s390_tune == PROCESSOR_2817_Z196
1707 || s390_tune == PROCESSOR_2827_ZEC12)
1708 {
1709 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1710 global_options.x_param_values,
1711 global_options_set.x_param_values);
1712 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1713 global_options.x_param_values,
1714 global_options_set.x_param_values);
1715 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1716 global_options.x_param_values,
1717 global_options_set.x_param_values);
1718 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1719 global_options.x_param_values,
1720 global_options_set.x_param_values);
1721 }
1722
1723 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1724 global_options.x_param_values,
1725 global_options_set.x_param_values);
1726 /* values for loop prefetching */
1727 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1728 global_options.x_param_values,
1729 global_options_set.x_param_values);
1730 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1731 global_options.x_param_values,
1732 global_options_set.x_param_values);
1733 /* s390 has more than 2 levels and the size is much larger. Since
1734 we are always running virtualized assume that we only get a small
1735 part of the caches above l1. */
1736 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1737 global_options.x_param_values,
1738 global_options_set.x_param_values);
1739 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1740 global_options.x_param_values,
1741 global_options_set.x_param_values);
1742 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1743 global_options.x_param_values,
1744 global_options_set.x_param_values);
1745
1746 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1747 requires the arch flags to be evaluated already. Since prefetching
1748 is beneficial on s390, we enable it if available. */
1749 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1750 flag_prefetch_loop_arrays = 1;
1751
1752 /* Use the alternative scheduling-pressure algorithm by default. */
1753 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
1754 global_options.x_param_values,
1755 global_options_set.x_param_values);
1756
1757 if (TARGET_TPF)
1758 {
1759 /* Don't emit DWARF3/4 unless specifically selected. The TPF
1760 debuggers do not yet support DWARF 3/4. */
1761 if (!global_options_set.x_dwarf_strict)
1762 dwarf_strict = 1;
1763 if (!global_options_set.x_dwarf_version)
1764 dwarf_version = 2;
1765 }
1766 }
1767
1768 /* Map for smallest class containing reg regno. */
1769
1770 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1771 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1772 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1773 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1774 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1775 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1776 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1777 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1778 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1779 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1780 ACCESS_REGS, ACCESS_REGS
1781 };
1782
1783 /* Return attribute type of insn. */
1784
1785 static enum attr_type
1786 s390_safe_attr_type (rtx insn)
1787 {
1788 if (recog_memoized (insn) >= 0)
1789 return get_attr_type (insn);
1790 else
1791 return TYPE_NONE;
1792 }
1793
1794 /* Return true if DISP is a valid short displacement. */
1795
1796 static bool
1797 s390_short_displacement (rtx disp)
1798 {
1799 /* No displacement is OK. */
1800 if (!disp)
1801 return true;
1802
1803 /* Without the long displacement facility we don't need to
1804 distingiush between long and short displacement. */
1805 if (!TARGET_LONG_DISPLACEMENT)
1806 return true;
1807
1808 /* Integer displacement in range. */
1809 if (GET_CODE (disp) == CONST_INT)
1810 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1811
1812 /* GOT offset is not OK, the GOT can be large. */
1813 if (GET_CODE (disp) == CONST
1814 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1815 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1816 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1817 return false;
1818
1819 /* All other symbolic constants are literal pool references,
1820 which are OK as the literal pool must be small. */
1821 if (GET_CODE (disp) == CONST)
1822 return true;
1823
1824 return false;
1825 }
1826
1827 /* Decompose a RTL expression ADDR for a memory address into
1828 its components, returned in OUT.
1829
1830 Returns false if ADDR is not a valid memory address, true
1831 otherwise. If OUT is NULL, don't return the components,
1832 but check for validity only.
1833
1834 Note: Only addresses in canonical form are recognized.
1835 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1836 canonical form so that they will be recognized. */
1837
1838 static int
1839 s390_decompose_address (rtx addr, struct s390_address *out)
1840 {
1841 HOST_WIDE_INT offset = 0;
1842 rtx base = NULL_RTX;
1843 rtx indx = NULL_RTX;
1844 rtx disp = NULL_RTX;
1845 rtx orig_disp;
1846 bool pointer = false;
1847 bool base_ptr = false;
1848 bool indx_ptr = false;
1849 bool literal_pool = false;
1850
1851 /* We may need to substitute the literal pool base register into the address
1852 below. However, at this point we do not know which register is going to
1853 be used as base, so we substitute the arg pointer register. This is going
1854 to be treated as holding a pointer below -- it shouldn't be used for any
1855 other purpose. */
1856 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1857
1858 /* Decompose address into base + index + displacement. */
1859
1860 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1861 base = addr;
1862
1863 else if (GET_CODE (addr) == PLUS)
1864 {
1865 rtx op0 = XEXP (addr, 0);
1866 rtx op1 = XEXP (addr, 1);
1867 enum rtx_code code0 = GET_CODE (op0);
1868 enum rtx_code code1 = GET_CODE (op1);
1869
1870 if (code0 == REG || code0 == UNSPEC)
1871 {
1872 if (code1 == REG || code1 == UNSPEC)
1873 {
1874 indx = op0; /* index + base */
1875 base = op1;
1876 }
1877
1878 else
1879 {
1880 base = op0; /* base + displacement */
1881 disp = op1;
1882 }
1883 }
1884
1885 else if (code0 == PLUS)
1886 {
1887 indx = XEXP (op0, 0); /* index + base + disp */
1888 base = XEXP (op0, 1);
1889 disp = op1;
1890 }
1891
1892 else
1893 {
1894 return false;
1895 }
1896 }
1897
1898 else
1899 disp = addr; /* displacement */
1900
1901 /* Extract integer part of displacement. */
1902 orig_disp = disp;
1903 if (disp)
1904 {
1905 if (GET_CODE (disp) == CONST_INT)
1906 {
1907 offset = INTVAL (disp);
1908 disp = NULL_RTX;
1909 }
1910 else if (GET_CODE (disp) == CONST
1911 && GET_CODE (XEXP (disp, 0)) == PLUS
1912 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1913 {
1914 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1915 disp = XEXP (XEXP (disp, 0), 0);
1916 }
1917 }
1918
1919 /* Strip off CONST here to avoid special case tests later. */
1920 if (disp && GET_CODE (disp) == CONST)
1921 disp = XEXP (disp, 0);
1922
1923 /* We can convert literal pool addresses to
1924 displacements by basing them off the base register. */
1925 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1926 {
1927 /* Either base or index must be free to hold the base register. */
1928 if (!base)
1929 base = fake_pool_base, literal_pool = true;
1930 else if (!indx)
1931 indx = fake_pool_base, literal_pool = true;
1932 else
1933 return false;
1934
1935 /* Mark up the displacement. */
1936 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1937 UNSPEC_LTREL_OFFSET);
1938 }
1939
1940 /* Validate base register. */
1941 if (base)
1942 {
1943 if (GET_CODE (base) == UNSPEC)
1944 switch (XINT (base, 1))
1945 {
1946 case UNSPEC_LTREF:
1947 if (!disp)
1948 disp = gen_rtx_UNSPEC (Pmode,
1949 gen_rtvec (1, XVECEXP (base, 0, 0)),
1950 UNSPEC_LTREL_OFFSET);
1951 else
1952 return false;
1953
1954 base = XVECEXP (base, 0, 1);
1955 break;
1956
1957 case UNSPEC_LTREL_BASE:
1958 if (XVECLEN (base, 0) == 1)
1959 base = fake_pool_base, literal_pool = true;
1960 else
1961 base = XVECEXP (base, 0, 1);
1962 break;
1963
1964 default:
1965 return false;
1966 }
1967
1968 if (!REG_P (base)
1969 || (GET_MODE (base) != SImode
1970 && GET_MODE (base) != Pmode))
1971 return false;
1972
1973 if (REGNO (base) == STACK_POINTER_REGNUM
1974 || REGNO (base) == FRAME_POINTER_REGNUM
1975 || ((reload_completed || reload_in_progress)
1976 && frame_pointer_needed
1977 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1978 || REGNO (base) == ARG_POINTER_REGNUM
1979 || (flag_pic
1980 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1981 pointer = base_ptr = true;
1982
1983 if ((reload_completed || reload_in_progress)
1984 && base == cfun->machine->base_reg)
1985 pointer = base_ptr = literal_pool = true;
1986 }
1987
1988 /* Validate index register. */
1989 if (indx)
1990 {
1991 if (GET_CODE (indx) == UNSPEC)
1992 switch (XINT (indx, 1))
1993 {
1994 case UNSPEC_LTREF:
1995 if (!disp)
1996 disp = gen_rtx_UNSPEC (Pmode,
1997 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1998 UNSPEC_LTREL_OFFSET);
1999 else
2000 return false;
2001
2002 indx = XVECEXP (indx, 0, 1);
2003 break;
2004
2005 case UNSPEC_LTREL_BASE:
2006 if (XVECLEN (indx, 0) == 1)
2007 indx = fake_pool_base, literal_pool = true;
2008 else
2009 indx = XVECEXP (indx, 0, 1);
2010 break;
2011
2012 default:
2013 return false;
2014 }
2015
2016 if (!REG_P (indx)
2017 || (GET_MODE (indx) != SImode
2018 && GET_MODE (indx) != Pmode))
2019 return false;
2020
2021 if (REGNO (indx) == STACK_POINTER_REGNUM
2022 || REGNO (indx) == FRAME_POINTER_REGNUM
2023 || ((reload_completed || reload_in_progress)
2024 && frame_pointer_needed
2025 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
2026 || REGNO (indx) == ARG_POINTER_REGNUM
2027 || (flag_pic
2028 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
2029 pointer = indx_ptr = true;
2030
2031 if ((reload_completed || reload_in_progress)
2032 && indx == cfun->machine->base_reg)
2033 pointer = indx_ptr = literal_pool = true;
2034 }
2035
2036 /* Prefer to use pointer as base, not index. */
2037 if (base && indx && !base_ptr
2038 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
2039 {
2040 rtx tmp = base;
2041 base = indx;
2042 indx = tmp;
2043 }
2044
2045 /* Validate displacement. */
2046 if (!disp)
2047 {
2048 /* If virtual registers are involved, the displacement will change later
2049 anyway as the virtual registers get eliminated. This could make a
2050 valid displacement invalid, but it is more likely to make an invalid
2051 displacement valid, because we sometimes access the register save area
2052 via negative offsets to one of those registers.
2053 Thus we don't check the displacement for validity here. If after
2054 elimination the displacement turns out to be invalid after all,
2055 this is fixed up by reload in any case. */
2056 /* LRA maintains always displacements up to date and we need to
2057 know the displacement is right during all LRA not only at the
2058 final elimination. */
2059 if (lra_in_progress
2060 || (base != arg_pointer_rtx
2061 && indx != arg_pointer_rtx
2062 && base != return_address_pointer_rtx
2063 && indx != return_address_pointer_rtx
2064 && base != frame_pointer_rtx
2065 && indx != frame_pointer_rtx
2066 && base != virtual_stack_vars_rtx
2067 && indx != virtual_stack_vars_rtx))
2068 if (!DISP_IN_RANGE (offset))
2069 return false;
2070 }
2071 else
2072 {
2073 /* All the special cases are pointers. */
2074 pointer = true;
2075
2076 /* In the small-PIC case, the linker converts @GOT
2077 and @GOTNTPOFF offsets to possible displacements. */
2078 if (GET_CODE (disp) == UNSPEC
2079 && (XINT (disp, 1) == UNSPEC_GOT
2080 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2081 && flag_pic == 1)
2082 {
2083 ;
2084 }
2085
2086 /* Accept pool label offsets. */
2087 else if (GET_CODE (disp) == UNSPEC
2088 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2089 ;
2090
2091 /* Accept literal pool references. */
2092 else if (GET_CODE (disp) == UNSPEC
2093 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2094 {
2095 /* In case CSE pulled a non literal pool reference out of
2096 the pool we have to reject the address. This is
2097 especially important when loading the GOT pointer on non
2098 zarch CPUs. In this case the literal pool contains an lt
2099 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2100 will most likely exceed the displacement. */
2101 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2102 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2103 return false;
2104
2105 orig_disp = gen_rtx_CONST (Pmode, disp);
2106 if (offset)
2107 {
2108 /* If we have an offset, make sure it does not
2109 exceed the size of the constant pool entry. */
2110 rtx sym = XVECEXP (disp, 0, 0);
2111 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2112 return false;
2113
2114 orig_disp = plus_constant (Pmode, orig_disp, offset);
2115 }
2116 }
2117
2118 else
2119 return false;
2120 }
2121
2122 if (!base && !indx)
2123 pointer = true;
2124
2125 if (out)
2126 {
2127 out->base = base;
2128 out->indx = indx;
2129 out->disp = orig_disp;
2130 out->pointer = pointer;
2131 out->literal_pool = literal_pool;
2132 }
2133
2134 return true;
2135 }
2136
2137 /* Decompose a RTL expression OP for a shift count into its components,
2138 and return the base register in BASE and the offset in OFFSET.
2139
2140 Return true if OP is a valid shift count, false if not. */
2141
2142 bool
2143 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2144 {
2145 HOST_WIDE_INT off = 0;
2146
2147 /* We can have an integer constant, an address register,
2148 or a sum of the two. */
2149 if (GET_CODE (op) == CONST_INT)
2150 {
2151 off = INTVAL (op);
2152 op = NULL_RTX;
2153 }
2154 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2155 {
2156 off = INTVAL (XEXP (op, 1));
2157 op = XEXP (op, 0);
2158 }
2159 while (op && GET_CODE (op) == SUBREG)
2160 op = SUBREG_REG (op);
2161
2162 if (op && GET_CODE (op) != REG)
2163 return false;
2164
2165 if (offset)
2166 *offset = off;
2167 if (base)
2168 *base = op;
2169
2170 return true;
2171 }
2172
2173
2174 /* Return true if CODE is a valid address without index. */
2175
2176 bool
2177 s390_legitimate_address_without_index_p (rtx op)
2178 {
2179 struct s390_address addr;
2180
2181 if (!s390_decompose_address (XEXP (op, 0), &addr))
2182 return false;
2183 if (addr.indx)
2184 return false;
2185
2186 return true;
2187 }
2188
2189
2190 /* Return TRUE if ADDR is an operand valid for a load/store relative
2191 instruction. Be aware that the alignment of the operand needs to
2192 be checked separately.
2193 Valid addresses are single references or a sum of a reference and a
2194 constant integer. Return these parts in SYMREF and ADDEND. You can
2195 pass NULL in REF and/or ADDEND if you are not interested in these
2196 values. Literal pool references are *not* considered symbol
2197 references. */
2198
2199 static bool
2200 s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2201 {
2202 HOST_WIDE_INT tmpaddend = 0;
2203
2204 if (GET_CODE (addr) == CONST)
2205 addr = XEXP (addr, 0);
2206
2207 if (GET_CODE (addr) == PLUS)
2208 {
2209 if (!CONST_INT_P (XEXP (addr, 1)))
2210 return false;
2211
2212 tmpaddend = INTVAL (XEXP (addr, 1));
2213 addr = XEXP (addr, 0);
2214 }
2215
2216 if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr))
2217 || (GET_CODE (addr) == UNSPEC
2218 && (XINT (addr, 1) == UNSPEC_GOTENT
2219 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
2220 {
2221 if (symref)
2222 *symref = addr;
2223 if (addend)
2224 *addend = tmpaddend;
2225
2226 return true;
2227 }
2228 return false;
2229 }
2230
2231 /* Return true if the address in OP is valid for constraint letter C
2232 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2233 pool MEMs should be accepted. Only the Q, R, S, T constraint
2234 letters are allowed for C. */
2235
2236 static int
2237 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2238 {
2239 struct s390_address addr;
2240 bool decomposed = false;
2241
2242 /* This check makes sure that no symbolic address (except literal
2243 pool references) are accepted by the R or T constraints. */
2244 if (s390_loadrelative_operand_p (op, NULL, NULL))
2245 return 0;
2246
2247 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2248 if (!lit_pool_ok)
2249 {
2250 if (!s390_decompose_address (op, &addr))
2251 return 0;
2252 if (addr.literal_pool)
2253 return 0;
2254 decomposed = true;
2255 }
2256
2257 switch (c)
2258 {
2259 case 'Q': /* no index short displacement */
2260 if (!decomposed && !s390_decompose_address (op, &addr))
2261 return 0;
2262 if (addr.indx)
2263 return 0;
2264 if (!s390_short_displacement (addr.disp))
2265 return 0;
2266 break;
2267
2268 case 'R': /* with index short displacement */
2269 if (TARGET_LONG_DISPLACEMENT)
2270 {
2271 if (!decomposed && !s390_decompose_address (op, &addr))
2272 return 0;
2273 if (!s390_short_displacement (addr.disp))
2274 return 0;
2275 }
2276 /* Any invalid address here will be fixed up by reload,
2277 so accept it for the most generic constraint. */
2278 break;
2279
2280 case 'S': /* no index long displacement */
2281 if (!TARGET_LONG_DISPLACEMENT)
2282 return 0;
2283 if (!decomposed && !s390_decompose_address (op, &addr))
2284 return 0;
2285 if (addr.indx)
2286 return 0;
2287 if (s390_short_displacement (addr.disp))
2288 return 0;
2289 break;
2290
2291 case 'T': /* with index long displacement */
2292 if (!TARGET_LONG_DISPLACEMENT)
2293 return 0;
2294 /* Any invalid address here will be fixed up by reload,
2295 so accept it for the most generic constraint. */
2296 if ((decomposed || s390_decompose_address (op, &addr))
2297 && s390_short_displacement (addr.disp))
2298 return 0;
2299 break;
2300 default:
2301 return 0;
2302 }
2303 return 1;
2304 }
2305
2306
2307 /* Evaluates constraint strings described by the regular expression
2308 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2309 the constraint given in STR, or 0 else. */
2310
2311 int
2312 s390_mem_constraint (const char *str, rtx op)
2313 {
2314 char c = str[0];
2315
2316 switch (c)
2317 {
2318 case 'A':
2319 /* Check for offsettable variants of memory constraints. */
2320 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2321 return 0;
2322 if ((reload_completed || reload_in_progress)
2323 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2324 return 0;
2325 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2326 case 'B':
2327 /* Check for non-literal-pool variants of memory constraints. */
2328 if (!MEM_P (op))
2329 return 0;
2330 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2331 case 'Q':
2332 case 'R':
2333 case 'S':
2334 case 'T':
2335 if (GET_CODE (op) != MEM)
2336 return 0;
2337 return s390_check_qrst_address (c, XEXP (op, 0), true);
2338 case 'U':
2339 return (s390_check_qrst_address ('Q', op, true)
2340 || s390_check_qrst_address ('R', op, true));
2341 case 'W':
2342 return (s390_check_qrst_address ('S', op, true)
2343 || s390_check_qrst_address ('T', op, true));
2344 case 'Y':
2345 /* Simply check for the basic form of a shift count. Reload will
2346 take care of making sure we have a proper base register. */
2347 if (!s390_decompose_shift_count (op, NULL, NULL))
2348 return 0;
2349 break;
2350 case 'Z':
2351 return s390_check_qrst_address (str[1], op, true);
2352 default:
2353 return 0;
2354 }
2355 return 1;
2356 }
2357
2358
2359 /* Evaluates constraint strings starting with letter O. Input
2360 parameter C is the second letter following the "O" in the constraint
2361 string. Returns 1 if VALUE meets the respective constraint and 0
2362 otherwise. */
2363
2364 int
2365 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2366 {
2367 if (!TARGET_EXTIMM)
2368 return 0;
2369
2370 switch (c)
2371 {
2372 case 's':
2373 return trunc_int_for_mode (value, SImode) == value;
2374
2375 case 'p':
2376 return value == 0
2377 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2378
2379 case 'n':
2380 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2381
2382 default:
2383 gcc_unreachable ();
2384 }
2385 }
2386
2387
2388 /* Evaluates constraint strings starting with letter N. Parameter STR
2389 contains the letters following letter "N" in the constraint string.
2390 Returns true if VALUE matches the constraint. */
2391
2392 int
2393 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2394 {
2395 enum machine_mode mode, part_mode;
2396 int def;
2397 int part, part_goal;
2398
2399
2400 if (str[0] == 'x')
2401 part_goal = -1;
2402 else
2403 part_goal = str[0] - '0';
2404
2405 switch (str[1])
2406 {
2407 case 'Q':
2408 part_mode = QImode;
2409 break;
2410 case 'H':
2411 part_mode = HImode;
2412 break;
2413 case 'S':
2414 part_mode = SImode;
2415 break;
2416 default:
2417 return 0;
2418 }
2419
2420 switch (str[2])
2421 {
2422 case 'H':
2423 mode = HImode;
2424 break;
2425 case 'S':
2426 mode = SImode;
2427 break;
2428 case 'D':
2429 mode = DImode;
2430 break;
2431 default:
2432 return 0;
2433 }
2434
2435 switch (str[3])
2436 {
2437 case '0':
2438 def = 0;
2439 break;
2440 case 'F':
2441 def = -1;
2442 break;
2443 default:
2444 return 0;
2445 }
2446
2447 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2448 return 0;
2449
2450 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2451 if (part < 0)
2452 return 0;
2453 if (part_goal != -1 && part_goal != part)
2454 return 0;
2455
2456 return 1;
2457 }
2458
2459
2460 /* Returns true if the input parameter VALUE is a float zero. */
2461
2462 int
2463 s390_float_const_zero_p (rtx value)
2464 {
2465 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2466 && value == CONST0_RTX (GET_MODE (value)));
2467 }
2468
2469 /* Implement TARGET_REGISTER_MOVE_COST. */
2470
2471 static int
2472 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2473 reg_class_t from, reg_class_t to)
2474 {
2475 /* On s390, copy between fprs and gprs is expensive as long as no
2476 ldgr/lgdr can be used. */
2477 if ((!TARGET_Z10 || GET_MODE_SIZE (mode) != 8)
2478 && ((reg_classes_intersect_p (from, GENERAL_REGS)
2479 && reg_classes_intersect_p (to, FP_REGS))
2480 || (reg_classes_intersect_p (from, FP_REGS)
2481 && reg_classes_intersect_p (to, GENERAL_REGS))))
2482 return 10;
2483
2484 return 1;
2485 }
2486
2487 /* Implement TARGET_MEMORY_MOVE_COST. */
2488
2489 static int
2490 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2491 reg_class_t rclass ATTRIBUTE_UNUSED,
2492 bool in ATTRIBUTE_UNUSED)
2493 {
2494 return 1;
2495 }
2496
2497 /* Compute a (partial) cost for rtx X. Return true if the complete
2498 cost has been computed, and false if subexpressions should be
2499 scanned. In either case, *TOTAL contains the cost result.
2500 CODE contains GET_CODE (x), OUTER_CODE contains the code
2501 of the superexpression of x. */
2502
2503 static bool
2504 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2505 int *total, bool speed ATTRIBUTE_UNUSED)
2506 {
2507 switch (code)
2508 {
2509 case CONST:
2510 case CONST_INT:
2511 case LABEL_REF:
2512 case SYMBOL_REF:
2513 case CONST_DOUBLE:
2514 case MEM:
2515 *total = 0;
2516 return true;
2517
2518 case ASHIFT:
2519 case ASHIFTRT:
2520 case LSHIFTRT:
2521 case ROTATE:
2522 case ROTATERT:
2523 case AND:
2524 case IOR:
2525 case XOR:
2526 case NEG:
2527 case NOT:
2528 *total = COSTS_N_INSNS (1);
2529 return false;
2530
2531 case PLUS:
2532 case MINUS:
2533 *total = COSTS_N_INSNS (1);
2534 return false;
2535
2536 case MULT:
2537 switch (GET_MODE (x))
2538 {
2539 case SImode:
2540 {
2541 rtx left = XEXP (x, 0);
2542 rtx right = XEXP (x, 1);
2543 if (GET_CODE (right) == CONST_INT
2544 && CONST_OK_FOR_K (INTVAL (right)))
2545 *total = s390_cost->mhi;
2546 else if (GET_CODE (left) == SIGN_EXTEND)
2547 *total = s390_cost->mh;
2548 else
2549 *total = s390_cost->ms; /* msr, ms, msy */
2550 break;
2551 }
2552 case DImode:
2553 {
2554 rtx left = XEXP (x, 0);
2555 rtx right = XEXP (x, 1);
2556 if (TARGET_ZARCH)
2557 {
2558 if (GET_CODE (right) == CONST_INT
2559 && CONST_OK_FOR_K (INTVAL (right)))
2560 *total = s390_cost->mghi;
2561 else if (GET_CODE (left) == SIGN_EXTEND)
2562 *total = s390_cost->msgf;
2563 else
2564 *total = s390_cost->msg; /* msgr, msg */
2565 }
2566 else /* TARGET_31BIT */
2567 {
2568 if (GET_CODE (left) == SIGN_EXTEND
2569 && GET_CODE (right) == SIGN_EXTEND)
2570 /* mulsidi case: mr, m */
2571 *total = s390_cost->m;
2572 else if (GET_CODE (left) == ZERO_EXTEND
2573 && GET_CODE (right) == ZERO_EXTEND
2574 && TARGET_CPU_ZARCH)
2575 /* umulsidi case: ml, mlr */
2576 *total = s390_cost->ml;
2577 else
2578 /* Complex calculation is required. */
2579 *total = COSTS_N_INSNS (40);
2580 }
2581 break;
2582 }
2583 case SFmode:
2584 case DFmode:
2585 *total = s390_cost->mult_df;
2586 break;
2587 case TFmode:
2588 *total = s390_cost->mxbr;
2589 break;
2590 default:
2591 return false;
2592 }
2593 return false;
2594
2595 case FMA:
2596 switch (GET_MODE (x))
2597 {
2598 case DFmode:
2599 *total = s390_cost->madbr;
2600 break;
2601 case SFmode:
2602 *total = s390_cost->maebr;
2603 break;
2604 default:
2605 return false;
2606 }
2607 /* Negate in the third argument is free: FMSUB. */
2608 if (GET_CODE (XEXP (x, 2)) == NEG)
2609 {
2610 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2611 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2612 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2613 return true;
2614 }
2615 return false;
2616
2617 case UDIV:
2618 case UMOD:
2619 if (GET_MODE (x) == TImode) /* 128 bit division */
2620 *total = s390_cost->dlgr;
2621 else if (GET_MODE (x) == DImode)
2622 {
2623 rtx right = XEXP (x, 1);
2624 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2625 *total = s390_cost->dlr;
2626 else /* 64 by 64 bit division */
2627 *total = s390_cost->dlgr;
2628 }
2629 else if (GET_MODE (x) == SImode) /* 32 bit division */
2630 *total = s390_cost->dlr;
2631 return false;
2632
2633 case DIV:
2634 case MOD:
2635 if (GET_MODE (x) == DImode)
2636 {
2637 rtx right = XEXP (x, 1);
2638 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2639 if (TARGET_ZARCH)
2640 *total = s390_cost->dsgfr;
2641 else
2642 *total = s390_cost->dr;
2643 else /* 64 by 64 bit division */
2644 *total = s390_cost->dsgr;
2645 }
2646 else if (GET_MODE (x) == SImode) /* 32 bit division */
2647 *total = s390_cost->dlr;
2648 else if (GET_MODE (x) == SFmode)
2649 {
2650 *total = s390_cost->debr;
2651 }
2652 else if (GET_MODE (x) == DFmode)
2653 {
2654 *total = s390_cost->ddbr;
2655 }
2656 else if (GET_MODE (x) == TFmode)
2657 {
2658 *total = s390_cost->dxbr;
2659 }
2660 return false;
2661
2662 case SQRT:
2663 if (GET_MODE (x) == SFmode)
2664 *total = s390_cost->sqebr;
2665 else if (GET_MODE (x) == DFmode)
2666 *total = s390_cost->sqdbr;
2667 else /* TFmode */
2668 *total = s390_cost->sqxbr;
2669 return false;
2670
2671 case SIGN_EXTEND:
2672 case ZERO_EXTEND:
2673 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2674 || outer_code == PLUS || outer_code == MINUS
2675 || outer_code == COMPARE)
2676 *total = 0;
2677 return false;
2678
2679 case COMPARE:
2680 *total = COSTS_N_INSNS (1);
2681 if (GET_CODE (XEXP (x, 0)) == AND
2682 && GET_CODE (XEXP (x, 1)) == CONST_INT
2683 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2684 {
2685 rtx op0 = XEXP (XEXP (x, 0), 0);
2686 rtx op1 = XEXP (XEXP (x, 0), 1);
2687 rtx op2 = XEXP (x, 1);
2688
2689 if (memory_operand (op0, GET_MODE (op0))
2690 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2691 return true;
2692 if (register_operand (op0, GET_MODE (op0))
2693 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2694 return true;
2695 }
2696 return false;
2697
2698 default:
2699 return false;
2700 }
2701 }
2702
2703 /* Return the cost of an address rtx ADDR. */
2704
2705 static int
2706 s390_address_cost (rtx addr, enum machine_mode mode ATTRIBUTE_UNUSED,
2707 addr_space_t as ATTRIBUTE_UNUSED,
2708 bool speed ATTRIBUTE_UNUSED)
2709 {
2710 struct s390_address ad;
2711 if (!s390_decompose_address (addr, &ad))
2712 return 1000;
2713
2714 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2715 }
2716
2717 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2718 otherwise return 0. */
2719
2720 int
2721 tls_symbolic_operand (rtx op)
2722 {
2723 if (GET_CODE (op) != SYMBOL_REF)
2724 return 0;
2725 return SYMBOL_REF_TLS_MODEL (op);
2726 }
2727 \f
2728 /* Split DImode access register reference REG (on 64-bit) into its constituent
2729 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2730 gen_highpart cannot be used as they assume all registers are word-sized,
2731 while our access registers have only half that size. */
2732
2733 void
2734 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2735 {
2736 gcc_assert (TARGET_64BIT);
2737 gcc_assert (ACCESS_REG_P (reg));
2738 gcc_assert (GET_MODE (reg) == DImode);
2739 gcc_assert (!(REGNO (reg) & 1));
2740
2741 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2742 *hi = gen_rtx_REG (SImode, REGNO (reg));
2743 }
2744
2745 /* Return true if OP contains a symbol reference */
2746
2747 bool
2748 symbolic_reference_mentioned_p (rtx op)
2749 {
2750 const char *fmt;
2751 int i;
2752
2753 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2754 return 1;
2755
2756 fmt = GET_RTX_FORMAT (GET_CODE (op));
2757 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2758 {
2759 if (fmt[i] == 'E')
2760 {
2761 int j;
2762
2763 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2764 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2765 return 1;
2766 }
2767
2768 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2769 return 1;
2770 }
2771
2772 return 0;
2773 }
2774
2775 /* Return true if OP contains a reference to a thread-local symbol. */
2776
2777 bool
2778 tls_symbolic_reference_mentioned_p (rtx op)
2779 {
2780 const char *fmt;
2781 int i;
2782
2783 if (GET_CODE (op) == SYMBOL_REF)
2784 return tls_symbolic_operand (op);
2785
2786 fmt = GET_RTX_FORMAT (GET_CODE (op));
2787 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2788 {
2789 if (fmt[i] == 'E')
2790 {
2791 int j;
2792
2793 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2794 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2795 return true;
2796 }
2797
2798 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2799 return true;
2800 }
2801
2802 return false;
2803 }
2804
2805
2806 /* Return true if OP is a legitimate general operand when
2807 generating PIC code. It is given that flag_pic is on
2808 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2809
2810 int
2811 legitimate_pic_operand_p (rtx op)
2812 {
2813 /* Accept all non-symbolic constants. */
2814 if (!SYMBOLIC_CONST (op))
2815 return 1;
2816
2817 /* Reject everything else; must be handled
2818 via emit_symbolic_move. */
2819 return 0;
2820 }
2821
2822 /* Returns true if the constant value OP is a legitimate general operand.
2823 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2824
2825 static bool
2826 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2827 {
2828 /* Accept all non-symbolic constants. */
2829 if (!SYMBOLIC_CONST (op))
2830 return 1;
2831
2832 /* Accept immediate LARL operands. */
2833 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2834 return 1;
2835
2836 /* Thread-local symbols are never legal constants. This is
2837 so that emit_call knows that computing such addresses
2838 might require a function call. */
2839 if (TLS_SYMBOLIC_CONST (op))
2840 return 0;
2841
2842 /* In the PIC case, symbolic constants must *not* be
2843 forced into the literal pool. We accept them here,
2844 so that they will be handled by emit_symbolic_move. */
2845 if (flag_pic)
2846 return 1;
2847
2848 /* All remaining non-PIC symbolic constants are
2849 forced into the literal pool. */
2850 return 0;
2851 }
2852
2853 /* Determine if it's legal to put X into the constant pool. This
2854 is not possible if X contains the address of a symbol that is
2855 not constant (TLS) or not known at final link time (PIC). */
2856
2857 static bool
2858 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2859 {
2860 switch (GET_CODE (x))
2861 {
2862 case CONST_INT:
2863 case CONST_DOUBLE:
2864 /* Accept all non-symbolic constants. */
2865 return false;
2866
2867 case LABEL_REF:
2868 /* Labels are OK iff we are non-PIC. */
2869 return flag_pic != 0;
2870
2871 case SYMBOL_REF:
2872 /* 'Naked' TLS symbol references are never OK,
2873 non-TLS symbols are OK iff we are non-PIC. */
2874 if (tls_symbolic_operand (x))
2875 return true;
2876 else
2877 return flag_pic != 0;
2878
2879 case CONST:
2880 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2881 case PLUS:
2882 case MINUS:
2883 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2884 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2885
2886 case UNSPEC:
2887 switch (XINT (x, 1))
2888 {
2889 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2890 case UNSPEC_LTREL_OFFSET:
2891 case UNSPEC_GOT:
2892 case UNSPEC_GOTOFF:
2893 case UNSPEC_PLTOFF:
2894 case UNSPEC_TLSGD:
2895 case UNSPEC_TLSLDM:
2896 case UNSPEC_NTPOFF:
2897 case UNSPEC_DTPOFF:
2898 case UNSPEC_GOTNTPOFF:
2899 case UNSPEC_INDNTPOFF:
2900 return false;
2901
2902 /* If the literal pool shares the code section, be put
2903 execute template placeholders into the pool as well. */
2904 case UNSPEC_INSN:
2905 return TARGET_CPU_ZARCH;
2906
2907 default:
2908 return true;
2909 }
2910 break;
2911
2912 default:
2913 gcc_unreachable ();
2914 }
2915 }
2916
2917 /* Returns true if the constant value OP is a legitimate general
2918 operand during and after reload. The difference to
2919 legitimate_constant_p is that this function will not accept
2920 a constant that would need to be forced to the literal pool
2921 before it can be used as operand.
2922 This function accepts all constants which can be loaded directly
2923 into a GPR. */
2924
2925 bool
2926 legitimate_reload_constant_p (rtx op)
2927 {
2928 /* Accept la(y) operands. */
2929 if (GET_CODE (op) == CONST_INT
2930 && DISP_IN_RANGE (INTVAL (op)))
2931 return true;
2932
2933 /* Accept l(g)hi/l(g)fi operands. */
2934 if (GET_CODE (op) == CONST_INT
2935 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2936 return true;
2937
2938 /* Accept lliXX operands. */
2939 if (TARGET_ZARCH
2940 && GET_CODE (op) == CONST_INT
2941 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2942 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2943 return true;
2944
2945 if (TARGET_EXTIMM
2946 && GET_CODE (op) == CONST_INT
2947 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2948 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2949 return true;
2950
2951 /* Accept larl operands. */
2952 if (TARGET_CPU_ZARCH
2953 && larl_operand (op, VOIDmode))
2954 return true;
2955
2956 /* Accept floating-point zero operands that fit into a single GPR. */
2957 if (GET_CODE (op) == CONST_DOUBLE
2958 && s390_float_const_zero_p (op)
2959 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2960 return true;
2961
2962 /* Accept double-word operands that can be split. */
2963 if (GET_CODE (op) == CONST_INT
2964 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2965 {
2966 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2967 rtx hi = operand_subword (op, 0, 0, dword_mode);
2968 rtx lo = operand_subword (op, 1, 0, dword_mode);
2969 return legitimate_reload_constant_p (hi)
2970 && legitimate_reload_constant_p (lo);
2971 }
2972
2973 /* Everything else cannot be handled without reload. */
2974 return false;
2975 }
2976
2977 /* Returns true if the constant value OP is a legitimate fp operand
2978 during and after reload.
2979 This function accepts all constants which can be loaded directly
2980 into an FPR. */
2981
2982 static bool
2983 legitimate_reload_fp_constant_p (rtx op)
2984 {
2985 /* Accept floating-point zero operands if the load zero instruction
2986 can be used. Prior to z196 the load fp zero instruction caused a
2987 performance penalty if the result is used as BFP number. */
2988 if (TARGET_Z196
2989 && GET_CODE (op) == CONST_DOUBLE
2990 && s390_float_const_zero_p (op))
2991 return true;
2992
2993 return false;
2994 }
2995
2996 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2997 return the class of reg to actually use. */
2998
2999 static reg_class_t
3000 s390_preferred_reload_class (rtx op, reg_class_t rclass)
3001 {
3002 switch (GET_CODE (op))
3003 {
3004 /* Constants we cannot reload into general registers
3005 must be forced into the literal pool. */
3006 case CONST_DOUBLE:
3007 case CONST_INT:
3008 if (reg_class_subset_p (GENERAL_REGS, rclass)
3009 && legitimate_reload_constant_p (op))
3010 return GENERAL_REGS;
3011 else if (reg_class_subset_p (ADDR_REGS, rclass)
3012 && legitimate_reload_constant_p (op))
3013 return ADDR_REGS;
3014 else if (reg_class_subset_p (FP_REGS, rclass)
3015 && legitimate_reload_fp_constant_p (op))
3016 return FP_REGS;
3017 return NO_REGS;
3018
3019 /* If a symbolic constant or a PLUS is reloaded,
3020 it is most likely being used as an address, so
3021 prefer ADDR_REGS. If 'class' is not a superset
3022 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
3023 case CONST:
3024 /* A larl operand with odd addend will get fixed via secondary
3025 reload. So don't request it to be pushed into literal
3026 pool. */
3027 if (TARGET_CPU_ZARCH
3028 && GET_CODE (XEXP (op, 0)) == PLUS
3029 && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
3030 && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
3031 {
3032 if (reg_class_subset_p (ADDR_REGS, rclass))
3033 return ADDR_REGS;
3034 else
3035 return NO_REGS;
3036 }
3037 /* fallthrough */
3038 case LABEL_REF:
3039 case SYMBOL_REF:
3040 if (!legitimate_reload_constant_p (op))
3041 return NO_REGS;
3042 /* fallthrough */
3043 case PLUS:
3044 /* load address will be used. */
3045 if (reg_class_subset_p (ADDR_REGS, rclass))
3046 return ADDR_REGS;
3047 else
3048 return NO_REGS;
3049
3050 default:
3051 break;
3052 }
3053
3054 return rclass;
3055 }
3056
3057 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
3058 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3059 aligned. */
3060
3061 bool
3062 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
3063 {
3064 HOST_WIDE_INT addend;
3065 rtx symref;
3066
3067 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
3068 return false;
3069
3070 if (addend & (alignment - 1))
3071 return false;
3072
3073 if (GET_CODE (symref) == SYMBOL_REF
3074 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref))
3075 return true;
3076
3077 if (GET_CODE (symref) == UNSPEC
3078 && alignment <= UNITS_PER_LONG)
3079 return true;
3080
3081 return false;
3082 }
3083
3084 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3085 operand SCRATCH is used to reload the even part of the address and
3086 adding one. */
3087
3088 void
3089 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3090 {
3091 HOST_WIDE_INT addend;
3092 rtx symref;
3093
3094 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
3095 gcc_unreachable ();
3096
3097 if (!(addend & 1))
3098 /* Easy case. The addend is even so larl will do fine. */
3099 emit_move_insn (reg, addr);
3100 else
3101 {
3102 /* We can leave the scratch register untouched if the target
3103 register is a valid base register. */
3104 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3105 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3106 scratch = reg;
3107
3108 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3109 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3110
3111 if (addend != 1)
3112 emit_move_insn (scratch,
3113 gen_rtx_CONST (Pmode,
3114 gen_rtx_PLUS (Pmode, symref,
3115 GEN_INT (addend - 1))));
3116 else
3117 emit_move_insn (scratch, symref);
3118
3119 /* Increment the address using la in order to avoid clobbering cc. */
3120 s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3121 }
3122 }
3123
3124 /* Generate what is necessary to move between REG and MEM using
3125 SCRATCH. The direction is given by TOMEM. */
3126
3127 void
3128 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3129 {
3130 /* Reload might have pulled a constant out of the literal pool.
3131 Force it back in. */
3132 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3133 || GET_CODE (mem) == CONST)
3134 mem = force_const_mem (GET_MODE (reg), mem);
3135
3136 gcc_assert (MEM_P (mem));
3137
3138 /* For a load from memory we can leave the scratch register
3139 untouched if the target register is a valid base register. */
3140 if (!tomem
3141 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3142 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3143 && GET_MODE (reg) == GET_MODE (scratch))
3144 scratch = reg;
3145
3146 /* Load address into scratch register. Since we can't have a
3147 secondary reload for a secondary reload we have to cover the case
3148 where larl would need a secondary reload here as well. */
3149 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3150
3151 /* Now we can use a standard load/store to do the move. */
3152 if (tomem)
3153 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3154 else
3155 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3156 }
3157
3158 /* Inform reload about cases where moving X with a mode MODE to a register in
3159 RCLASS requires an extra scratch or immediate register. Return the class
3160 needed for the immediate register. */
3161
3162 static reg_class_t
3163 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3164 enum machine_mode mode, secondary_reload_info *sri)
3165 {
3166 enum reg_class rclass = (enum reg_class) rclass_i;
3167
3168 /* Intermediate register needed. */
3169 if (reg_classes_intersect_p (CC_REGS, rclass))
3170 return GENERAL_REGS;
3171
3172 if (TARGET_Z10)
3173 {
3174 HOST_WIDE_INT offset;
3175 rtx symref;
3176
3177 /* On z10 several optimizer steps may generate larl operands with
3178 an odd addend. */
3179 if (in_p
3180 && s390_loadrelative_operand_p (x, &symref, &offset)
3181 && mode == Pmode
3182 && !SYMBOL_REF_ALIGN1_P (symref)
3183 && (offset & 1) == 1)
3184 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3185 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3186
3187 /* On z10 we need a scratch register when moving QI, TI or floating
3188 point mode values from or to a memory location with a SYMBOL_REF
3189 or if the symref addend of a SI or DI move is not aligned to the
3190 width of the access. */
3191 if (MEM_P (x)
3192 && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL)
3193 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3194 || (!TARGET_ZARCH && mode == DImode)
3195 || ((mode == HImode || mode == SImode || mode == DImode)
3196 && (!s390_check_symref_alignment (XEXP (x, 0),
3197 GET_MODE_SIZE (mode))))))
3198 {
3199 #define __SECONDARY_RELOAD_CASE(M,m) \
3200 case M##mode: \
3201 if (TARGET_64BIT) \
3202 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3203 CODE_FOR_reload##m##di_tomem_z10; \
3204 else \
3205 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3206 CODE_FOR_reload##m##si_tomem_z10; \
3207 break;
3208
3209 switch (GET_MODE (x))
3210 {
3211 __SECONDARY_RELOAD_CASE (QI, qi);
3212 __SECONDARY_RELOAD_CASE (HI, hi);
3213 __SECONDARY_RELOAD_CASE (SI, si);
3214 __SECONDARY_RELOAD_CASE (DI, di);
3215 __SECONDARY_RELOAD_CASE (TI, ti);
3216 __SECONDARY_RELOAD_CASE (SF, sf);
3217 __SECONDARY_RELOAD_CASE (DF, df);
3218 __SECONDARY_RELOAD_CASE (TF, tf);
3219 __SECONDARY_RELOAD_CASE (SD, sd);
3220 __SECONDARY_RELOAD_CASE (DD, dd);
3221 __SECONDARY_RELOAD_CASE (TD, td);
3222
3223 default:
3224 gcc_unreachable ();
3225 }
3226 #undef __SECONDARY_RELOAD_CASE
3227 }
3228 }
3229
3230 /* We need a scratch register when loading a PLUS expression which
3231 is not a legitimate operand of the LOAD ADDRESS instruction. */
3232 /* LRA can deal with transformation of plus op very well -- so we
3233 don't need to prompt LRA in this case. */
3234 if (! lra_in_progress && in_p && s390_plus_operand (x, mode))
3235 sri->icode = (TARGET_64BIT ?
3236 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3237
3238 /* Performing a multiword move from or to memory we have to make sure the
3239 second chunk in memory is addressable without causing a displacement
3240 overflow. If that would be the case we calculate the address in
3241 a scratch register. */
3242 if (MEM_P (x)
3243 && GET_CODE (XEXP (x, 0)) == PLUS
3244 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3245 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3246 + GET_MODE_SIZE (mode) - 1))
3247 {
3248 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3249 in a s_operand address since we may fallback to lm/stm. So we only
3250 have to care about overflows in the b+i+d case. */
3251 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3252 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3253 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3254 /* For FP_REGS no lm/stm is available so this check is triggered
3255 for displacement overflows in b+i+d and b+d like addresses. */
3256 || (reg_classes_intersect_p (FP_REGS, rclass)
3257 && s390_class_max_nregs (FP_REGS, mode) > 1))
3258 {
3259 if (in_p)
3260 sri->icode = (TARGET_64BIT ?
3261 CODE_FOR_reloaddi_nonoffmem_in :
3262 CODE_FOR_reloadsi_nonoffmem_in);
3263 else
3264 sri->icode = (TARGET_64BIT ?
3265 CODE_FOR_reloaddi_nonoffmem_out :
3266 CODE_FOR_reloadsi_nonoffmem_out);
3267 }
3268 }
3269
3270 /* A scratch address register is needed when a symbolic constant is
3271 copied to r0 compiling with -fPIC. In other cases the target
3272 register might be used as temporary (see legitimize_pic_address). */
3273 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3274 sri->icode = (TARGET_64BIT ?
3275 CODE_FOR_reloaddi_PIC_addr :
3276 CODE_FOR_reloadsi_PIC_addr);
3277
3278 /* Either scratch or no register needed. */
3279 return NO_REGS;
3280 }
3281
3282 /* Generate code to load SRC, which is PLUS that is not a
3283 legitimate operand for the LA instruction, into TARGET.
3284 SCRATCH may be used as scratch register. */
3285
3286 void
3287 s390_expand_plus_operand (rtx target, rtx src,
3288 rtx scratch)
3289 {
3290 rtx sum1, sum2;
3291 struct s390_address ad;
3292
3293 /* src must be a PLUS; get its two operands. */
3294 gcc_assert (GET_CODE (src) == PLUS);
3295 gcc_assert (GET_MODE (src) == Pmode);
3296
3297 /* Check if any of the two operands is already scheduled
3298 for replacement by reload. This can happen e.g. when
3299 float registers occur in an address. */
3300 sum1 = find_replacement (&XEXP (src, 0));
3301 sum2 = find_replacement (&XEXP (src, 1));
3302 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3303
3304 /* If the address is already strictly valid, there's nothing to do. */
3305 if (!s390_decompose_address (src, &ad)
3306 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3307 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3308 {
3309 /* Otherwise, one of the operands cannot be an address register;
3310 we reload its value into the scratch register. */
3311 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3312 {
3313 emit_move_insn (scratch, sum1);
3314 sum1 = scratch;
3315 }
3316 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3317 {
3318 emit_move_insn (scratch, sum2);
3319 sum2 = scratch;
3320 }
3321
3322 /* According to the way these invalid addresses are generated
3323 in reload.c, it should never happen (at least on s390) that
3324 *neither* of the PLUS components, after find_replacements
3325 was applied, is an address register. */
3326 if (sum1 == scratch && sum2 == scratch)
3327 {
3328 debug_rtx (src);
3329 gcc_unreachable ();
3330 }
3331
3332 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3333 }
3334
3335 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3336 is only ever performed on addresses, so we can mark the
3337 sum as legitimate for LA in any case. */
3338 s390_load_address (target, src);
3339 }
3340
3341
3342 /* Return true if ADDR is a valid memory address.
3343 STRICT specifies whether strict register checking applies. */
3344
3345 static bool
3346 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3347 {
3348 struct s390_address ad;
3349
3350 if (TARGET_Z10
3351 && larl_operand (addr, VOIDmode)
3352 && (mode == VOIDmode
3353 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3354 return true;
3355
3356 if (!s390_decompose_address (addr, &ad))
3357 return false;
3358
3359 if (strict)
3360 {
3361 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3362 return false;
3363
3364 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3365 return false;
3366 }
3367 else
3368 {
3369 if (ad.base
3370 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3371 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3372 return false;
3373
3374 if (ad.indx
3375 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3376 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3377 return false;
3378 }
3379 return true;
3380 }
3381
3382 /* Return true if OP is a valid operand for the LA instruction.
3383 In 31-bit, we need to prove that the result is used as an
3384 address, as LA performs only a 31-bit addition. */
3385
3386 bool
3387 legitimate_la_operand_p (rtx op)
3388 {
3389 struct s390_address addr;
3390 if (!s390_decompose_address (op, &addr))
3391 return false;
3392
3393 return (TARGET_64BIT || addr.pointer);
3394 }
3395
3396 /* Return true if it is valid *and* preferable to use LA to
3397 compute the sum of OP1 and OP2. */
3398
3399 bool
3400 preferred_la_operand_p (rtx op1, rtx op2)
3401 {
3402 struct s390_address addr;
3403
3404 if (op2 != const0_rtx)
3405 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3406
3407 if (!s390_decompose_address (op1, &addr))
3408 return false;
3409 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3410 return false;
3411 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3412 return false;
3413
3414 /* Avoid LA instructions with index register on z196; it is
3415 preferable to use regular add instructions when possible.
3416 Starting with zEC12 the la with index register is "uncracked"
3417 again. */
3418 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3419 return false;
3420
3421 if (!TARGET_64BIT && !addr.pointer)
3422 return false;
3423
3424 if (addr.pointer)
3425 return true;
3426
3427 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3428 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3429 return true;
3430
3431 return false;
3432 }
3433
3434 /* Emit a forced load-address operation to load SRC into DST.
3435 This will use the LOAD ADDRESS instruction even in situations
3436 where legitimate_la_operand_p (SRC) returns false. */
3437
3438 void
3439 s390_load_address (rtx dst, rtx src)
3440 {
3441 if (TARGET_64BIT)
3442 emit_move_insn (dst, src);
3443 else
3444 emit_insn (gen_force_la_31 (dst, src));
3445 }
3446
3447 /* Return a legitimate reference for ORIG (an address) using the
3448 register REG. If REG is 0, a new pseudo is generated.
3449
3450 There are two types of references that must be handled:
3451
3452 1. Global data references must load the address from the GOT, via
3453 the PIC reg. An insn is emitted to do this load, and the reg is
3454 returned.
3455
3456 2. Static data references, constant pool addresses, and code labels
3457 compute the address as an offset from the GOT, whose base is in
3458 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3459 differentiate them from global data objects. The returned
3460 address is the PIC reg + an unspec constant.
3461
3462 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3463 reg also appears in the address. */
3464
3465 rtx
3466 legitimize_pic_address (rtx orig, rtx reg)
3467 {
3468 rtx addr = orig;
3469 rtx addend = const0_rtx;
3470 rtx new_rtx = orig;
3471
3472 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3473
3474 if (GET_CODE (addr) == CONST)
3475 addr = XEXP (addr, 0);
3476
3477 if (GET_CODE (addr) == PLUS)
3478 {
3479 addend = XEXP (addr, 1);
3480 addr = XEXP (addr, 0);
3481 }
3482
3483 if ((GET_CODE (addr) == LABEL_REF
3484 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))
3485 || (GET_CODE (addr) == UNSPEC &&
3486 (XINT (addr, 1) == UNSPEC_GOTENT
3487 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
3488 && GET_CODE (addend) == CONST_INT)
3489 {
3490 /* This can be locally addressed. */
3491
3492 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3493 rtx const_addr = (GET_CODE (addr) == UNSPEC ?
3494 gen_rtx_CONST (Pmode, addr) : addr);
3495
3496 if (TARGET_CPU_ZARCH
3497 && larl_operand (const_addr, VOIDmode)
3498 && INTVAL (addend) < (HOST_WIDE_INT)1 << 31
3499 && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31))
3500 {
3501 if (INTVAL (addend) & 1)
3502 {
3503 /* LARL can't handle odd offsets, so emit a pair of LARL
3504 and LA. */
3505 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3506
3507 if (!DISP_IN_RANGE (INTVAL (addend)))
3508 {
3509 HOST_WIDE_INT even = INTVAL (addend) - 1;
3510 addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even));
3511 addr = gen_rtx_CONST (Pmode, addr);
3512 addend = const1_rtx;
3513 }
3514
3515 emit_move_insn (temp, addr);
3516 new_rtx = gen_rtx_PLUS (Pmode, temp, addend);
3517
3518 if (reg != 0)
3519 {
3520 s390_load_address (reg, new_rtx);
3521 new_rtx = reg;
3522 }
3523 }
3524 else
3525 {
3526 /* If the offset is even, we can just use LARL. This
3527 will happen automatically. */
3528 }
3529 }
3530 else
3531 {
3532 /* No larl - Access local symbols relative to the GOT. */
3533
3534 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3535
3536 if (reload_in_progress || reload_completed)
3537 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3538
3539 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3540 if (addend != const0_rtx)
3541 addr = gen_rtx_PLUS (Pmode, addr, addend);
3542 addr = gen_rtx_CONST (Pmode, addr);
3543 addr = force_const_mem (Pmode, addr);
3544 emit_move_insn (temp, addr);
3545
3546 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3547 if (reg != 0)
3548 {
3549 s390_load_address (reg, new_rtx);
3550 new_rtx = reg;
3551 }
3552 }
3553 }
3554 else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
3555 {
3556 /* A non-local symbol reference without addend.
3557
3558 The symbol ref is wrapped into an UNSPEC to make sure the
3559 proper operand modifier (@GOT or @GOTENT) will be emitted.
3560 This will tell the linker to put the symbol into the GOT.
3561
3562 Additionally the code dereferencing the GOT slot is emitted here.
3563
3564 An addend to the symref needs to be added afterwards.
3565 legitimize_pic_address calls itself recursively to handle
3566 that case. So no need to do it here. */
3567
3568 if (reg == 0)
3569 reg = gen_reg_rtx (Pmode);
3570
3571 if (TARGET_Z10)
3572 {
3573 /* Use load relative if possible.
3574 lgrl <target>, sym@GOTENT */
3575 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3576 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3577 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3578
3579 emit_move_insn (reg, new_rtx);
3580 new_rtx = reg;
3581 }
3582 else if (flag_pic == 1)
3583 {
3584 /* Assume GOT offset is a valid displacement operand (< 4k
3585 or < 512k with z990). This is handled the same way in
3586 both 31- and 64-bit code (@GOT).
3587 lg <target>, sym@GOT(r12) */
3588
3589 if (reload_in_progress || reload_completed)
3590 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3591
3592 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3593 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3594 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3595 new_rtx = gen_const_mem (Pmode, new_rtx);
3596 emit_move_insn (reg, new_rtx);
3597 new_rtx = reg;
3598 }
3599 else if (TARGET_CPU_ZARCH)
3600 {
3601 /* If the GOT offset might be >= 4k, we determine the position
3602 of the GOT entry via a PC-relative LARL (@GOTENT).
3603 larl temp, sym@GOTENT
3604 lg <target>, 0(temp) */
3605
3606 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3607
3608 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3609 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3610
3611 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3612 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3613 emit_move_insn (temp, new_rtx);
3614
3615 new_rtx = gen_const_mem (Pmode, temp);
3616 emit_move_insn (reg, new_rtx);
3617
3618 new_rtx = reg;
3619 }
3620 else
3621 {
3622 /* If the GOT offset might be >= 4k, we have to load it
3623 from the literal pool (@GOT).
3624
3625 lg temp, lit-litbase(r13)
3626 lg <target>, 0(temp)
3627 lit: .long sym@GOT */
3628
3629 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3630
3631 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3632 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3633
3634 if (reload_in_progress || reload_completed)
3635 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3636
3637 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3638 addr = gen_rtx_CONST (Pmode, addr);
3639 addr = force_const_mem (Pmode, addr);
3640 emit_move_insn (temp, addr);
3641
3642 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3643 new_rtx = gen_const_mem (Pmode, new_rtx);
3644 emit_move_insn (reg, new_rtx);
3645 new_rtx = reg;
3646 }
3647 }
3648 else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
3649 {
3650 gcc_assert (XVECLEN (addr, 0) == 1);
3651 switch (XINT (addr, 1))
3652 {
3653 /* These address symbols (or PLT slots) relative to the GOT
3654 (not GOT slots!). In general this will exceed the
3655 displacement range so these value belong into the literal
3656 pool. */
3657 case UNSPEC_GOTOFF:
3658 case UNSPEC_PLTOFF:
3659 new_rtx = force_const_mem (Pmode, orig);
3660 break;
3661
3662 /* For -fPIC the GOT size might exceed the displacement
3663 range so make sure the value is in the literal pool. */
3664 case UNSPEC_GOT:
3665 if (flag_pic == 2)
3666 new_rtx = force_const_mem (Pmode, orig);
3667 break;
3668
3669 /* For @GOTENT larl is used. This is handled like local
3670 symbol refs. */
3671 case UNSPEC_GOTENT:
3672 gcc_unreachable ();
3673 break;
3674
3675 /* @PLT is OK as is on 64-bit, must be converted to
3676 GOT-relative @PLTOFF on 31-bit. */
3677 case UNSPEC_PLT:
3678 if (!TARGET_CPU_ZARCH)
3679 {
3680 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3681
3682 if (reload_in_progress || reload_completed)
3683 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3684
3685 addr = XVECEXP (addr, 0, 0);
3686 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3687 UNSPEC_PLTOFF);
3688 if (addend != const0_rtx)
3689 addr = gen_rtx_PLUS (Pmode, addr, addend);
3690 addr = gen_rtx_CONST (Pmode, addr);
3691 addr = force_const_mem (Pmode, addr);
3692 emit_move_insn (temp, addr);
3693
3694 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3695 if (reg != 0)
3696 {
3697 s390_load_address (reg, new_rtx);
3698 new_rtx = reg;
3699 }
3700 }
3701 else
3702 /* On 64 bit larl can be used. This case is handled like
3703 local symbol refs. */
3704 gcc_unreachable ();
3705 break;
3706
3707 /* Everything else cannot happen. */
3708 default:
3709 gcc_unreachable ();
3710 }
3711 }
3712 else if (addend != const0_rtx)
3713 {
3714 /* Otherwise, compute the sum. */
3715
3716 rtx base = legitimize_pic_address (addr, reg);
3717 new_rtx = legitimize_pic_address (addend,
3718 base == reg ? NULL_RTX : reg);
3719 if (GET_CODE (new_rtx) == CONST_INT)
3720 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3721 else
3722 {
3723 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3724 {
3725 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3726 new_rtx = XEXP (new_rtx, 1);
3727 }
3728 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3729 }
3730
3731 if (GET_CODE (new_rtx) == CONST)
3732 new_rtx = XEXP (new_rtx, 0);
3733 new_rtx = force_operand (new_rtx, 0);
3734 }
3735
3736 return new_rtx;
3737 }
3738
3739 /* Load the thread pointer into a register. */
3740
3741 rtx
3742 s390_get_thread_pointer (void)
3743 {
3744 rtx tp = gen_reg_rtx (Pmode);
3745
3746 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3747 mark_reg_pointer (tp, BITS_PER_WORD);
3748
3749 return tp;
3750 }
3751
3752 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3753 in s390_tls_symbol which always refers to __tls_get_offset.
3754 The returned offset is written to RESULT_REG and an USE rtx is
3755 generated for TLS_CALL. */
3756
3757 static GTY(()) rtx s390_tls_symbol;
3758
3759 static void
3760 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3761 {
3762 rtx insn;
3763
3764 if (!flag_pic)
3765 emit_insn (s390_load_got ());
3766
3767 if (!s390_tls_symbol)
3768 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3769
3770 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3771 gen_rtx_REG (Pmode, RETURN_REGNUM));
3772
3773 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3774 RTL_CONST_CALL_P (insn) = 1;
3775 }
3776
3777 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3778 this (thread-local) address. REG may be used as temporary. */
3779
3780 static rtx
3781 legitimize_tls_address (rtx addr, rtx reg)
3782 {
3783 rtx new_rtx, tls_call, temp, base, r2, insn;
3784
3785 if (GET_CODE (addr) == SYMBOL_REF)
3786 switch (tls_symbolic_operand (addr))
3787 {
3788 case TLS_MODEL_GLOBAL_DYNAMIC:
3789 start_sequence ();
3790 r2 = gen_rtx_REG (Pmode, 2);
3791 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3792 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3793 new_rtx = force_const_mem (Pmode, new_rtx);
3794 emit_move_insn (r2, new_rtx);
3795 s390_emit_tls_call_insn (r2, tls_call);
3796 insn = get_insns ();
3797 end_sequence ();
3798
3799 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3800 temp = gen_reg_rtx (Pmode);
3801 emit_libcall_block (insn, temp, r2, new_rtx);
3802
3803 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3804 if (reg != 0)
3805 {
3806 s390_load_address (reg, new_rtx);
3807 new_rtx = reg;
3808 }
3809 break;
3810
3811 case TLS_MODEL_LOCAL_DYNAMIC:
3812 start_sequence ();
3813 r2 = gen_rtx_REG (Pmode, 2);
3814 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3815 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3816 new_rtx = force_const_mem (Pmode, new_rtx);
3817 emit_move_insn (r2, new_rtx);
3818 s390_emit_tls_call_insn (r2, tls_call);
3819 insn = get_insns ();
3820 end_sequence ();
3821
3822 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3823 temp = gen_reg_rtx (Pmode);
3824 emit_libcall_block (insn, temp, r2, new_rtx);
3825
3826 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3827 base = gen_reg_rtx (Pmode);
3828 s390_load_address (base, new_rtx);
3829
3830 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3831 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3832 new_rtx = force_const_mem (Pmode, new_rtx);
3833 temp = gen_reg_rtx (Pmode);
3834 emit_move_insn (temp, new_rtx);
3835
3836 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3837 if (reg != 0)
3838 {
3839 s390_load_address (reg, new_rtx);
3840 new_rtx = reg;
3841 }
3842 break;
3843
3844 case TLS_MODEL_INITIAL_EXEC:
3845 if (flag_pic == 1)
3846 {
3847 /* Assume GOT offset < 4k. This is handled the same way
3848 in both 31- and 64-bit code. */
3849
3850 if (reload_in_progress || reload_completed)
3851 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3852
3853 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3854 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3855 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3856 new_rtx = gen_const_mem (Pmode, new_rtx);
3857 temp = gen_reg_rtx (Pmode);
3858 emit_move_insn (temp, new_rtx);
3859 }
3860 else if (TARGET_CPU_ZARCH)
3861 {
3862 /* If the GOT offset might be >= 4k, we determine the position
3863 of the GOT entry via a PC-relative LARL. */
3864
3865 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3866 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3867 temp = gen_reg_rtx (Pmode);
3868 emit_move_insn (temp, new_rtx);
3869
3870 new_rtx = gen_const_mem (Pmode, temp);
3871 temp = gen_reg_rtx (Pmode);
3872 emit_move_insn (temp, new_rtx);
3873 }
3874 else if (flag_pic)
3875 {
3876 /* If the GOT offset might be >= 4k, we have to load it
3877 from the literal pool. */
3878
3879 if (reload_in_progress || reload_completed)
3880 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3881
3882 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3883 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3884 new_rtx = force_const_mem (Pmode, new_rtx);
3885 temp = gen_reg_rtx (Pmode);
3886 emit_move_insn (temp, new_rtx);
3887
3888 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3889 new_rtx = gen_const_mem (Pmode, new_rtx);
3890
3891 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3892 temp = gen_reg_rtx (Pmode);
3893 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3894 }
3895 else
3896 {
3897 /* In position-dependent code, load the absolute address of
3898 the GOT entry from the literal pool. */
3899
3900 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3901 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3902 new_rtx = force_const_mem (Pmode, new_rtx);
3903 temp = gen_reg_rtx (Pmode);
3904 emit_move_insn (temp, new_rtx);
3905
3906 new_rtx = temp;
3907 new_rtx = gen_const_mem (Pmode, new_rtx);
3908 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3909 temp = gen_reg_rtx (Pmode);
3910 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3911 }
3912
3913 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3914 if (reg != 0)
3915 {
3916 s390_load_address (reg, new_rtx);
3917 new_rtx = reg;
3918 }
3919 break;
3920
3921 case TLS_MODEL_LOCAL_EXEC:
3922 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3923 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3924 new_rtx = force_const_mem (Pmode, new_rtx);
3925 temp = gen_reg_rtx (Pmode);
3926 emit_move_insn (temp, new_rtx);
3927
3928 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3929 if (reg != 0)
3930 {
3931 s390_load_address (reg, new_rtx);
3932 new_rtx = reg;
3933 }
3934 break;
3935
3936 default:
3937 gcc_unreachable ();
3938 }
3939
3940 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3941 {
3942 switch (XINT (XEXP (addr, 0), 1))
3943 {
3944 case UNSPEC_INDNTPOFF:
3945 gcc_assert (TARGET_CPU_ZARCH);
3946 new_rtx = addr;
3947 break;
3948
3949 default:
3950 gcc_unreachable ();
3951 }
3952 }
3953
3954 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3955 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3956 {
3957 new_rtx = XEXP (XEXP (addr, 0), 0);
3958 if (GET_CODE (new_rtx) != SYMBOL_REF)
3959 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3960
3961 new_rtx = legitimize_tls_address (new_rtx, reg);
3962 new_rtx = plus_constant (Pmode, new_rtx,
3963 INTVAL (XEXP (XEXP (addr, 0), 1)));
3964 new_rtx = force_operand (new_rtx, 0);
3965 }
3966
3967 else
3968 gcc_unreachable (); /* for now ... */
3969
3970 return new_rtx;
3971 }
3972
3973 /* Emit insns making the address in operands[1] valid for a standard
3974 move to operands[0]. operands[1] is replaced by an address which
3975 should be used instead of the former RTX to emit the move
3976 pattern. */
3977
3978 void
3979 emit_symbolic_move (rtx *operands)
3980 {
3981 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3982
3983 if (GET_CODE (operands[0]) == MEM)
3984 operands[1] = force_reg (Pmode, operands[1]);
3985 else if (TLS_SYMBOLIC_CONST (operands[1]))
3986 operands[1] = legitimize_tls_address (operands[1], temp);
3987 else if (flag_pic)
3988 operands[1] = legitimize_pic_address (operands[1], temp);
3989 }
3990
3991 /* Try machine-dependent ways of modifying an illegitimate address X
3992 to be legitimate. If we find one, return the new, valid address.
3993
3994 OLDX is the address as it was before break_out_memory_refs was called.
3995 In some cases it is useful to look at this to decide what needs to be done.
3996
3997 MODE is the mode of the operand pointed to by X.
3998
3999 When -fpic is used, special handling is needed for symbolic references.
4000 See comments by legitimize_pic_address for details. */
4001
4002 static rtx
4003 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
4004 enum machine_mode mode ATTRIBUTE_UNUSED)
4005 {
4006 rtx constant_term = const0_rtx;
4007
4008 if (TLS_SYMBOLIC_CONST (x))
4009 {
4010 x = legitimize_tls_address (x, 0);
4011
4012 if (s390_legitimate_address_p (mode, x, FALSE))
4013 return x;
4014 }
4015 else if (GET_CODE (x) == PLUS
4016 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
4017 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
4018 {
4019 return x;
4020 }
4021 else if (flag_pic)
4022 {
4023 if (SYMBOLIC_CONST (x)
4024 || (GET_CODE (x) == PLUS
4025 && (SYMBOLIC_CONST (XEXP (x, 0))
4026 || SYMBOLIC_CONST (XEXP (x, 1)))))
4027 x = legitimize_pic_address (x, 0);
4028
4029 if (s390_legitimate_address_p (mode, x, FALSE))
4030 return x;
4031 }
4032
4033 x = eliminate_constant_term (x, &constant_term);
4034
4035 /* Optimize loading of large displacements by splitting them
4036 into the multiple of 4K and the rest; this allows the
4037 former to be CSE'd if possible.
4038
4039 Don't do this if the displacement is added to a register
4040 pointing into the stack frame, as the offsets will
4041 change later anyway. */
4042
4043 if (GET_CODE (constant_term) == CONST_INT
4044 && !TARGET_LONG_DISPLACEMENT
4045 && !DISP_IN_RANGE (INTVAL (constant_term))
4046 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
4047 {
4048 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
4049 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
4050
4051 rtx temp = gen_reg_rtx (Pmode);
4052 rtx val = force_operand (GEN_INT (upper), temp);
4053 if (val != temp)
4054 emit_move_insn (temp, val);
4055
4056 x = gen_rtx_PLUS (Pmode, x, temp);
4057 constant_term = GEN_INT (lower);
4058 }
4059
4060 if (GET_CODE (x) == PLUS)
4061 {
4062 if (GET_CODE (XEXP (x, 0)) == REG)
4063 {
4064 rtx temp = gen_reg_rtx (Pmode);
4065 rtx val = force_operand (XEXP (x, 1), temp);
4066 if (val != temp)
4067 emit_move_insn (temp, val);
4068
4069 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4070 }
4071
4072 else if (GET_CODE (XEXP (x, 1)) == REG)
4073 {
4074 rtx temp = gen_reg_rtx (Pmode);
4075 rtx val = force_operand (XEXP (x, 0), temp);
4076 if (val != temp)
4077 emit_move_insn (temp, val);
4078
4079 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4080 }
4081 }
4082
4083 if (constant_term != const0_rtx)
4084 x = gen_rtx_PLUS (Pmode, x, constant_term);
4085
4086 return x;
4087 }
4088
4089 /* Try a machine-dependent way of reloading an illegitimate address AD
4090 operand. If we find one, push the reload and return the new address.
4091
4092 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4093 and TYPE is the reload type of the current reload. */
4094
4095 rtx
4096 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
4097 int opnum, int type)
4098 {
4099 if (!optimize || TARGET_LONG_DISPLACEMENT)
4100 return NULL_RTX;
4101
4102 if (GET_CODE (ad) == PLUS)
4103 {
4104 rtx tem = simplify_binary_operation (PLUS, Pmode,
4105 XEXP (ad, 0), XEXP (ad, 1));
4106 if (tem)
4107 ad = tem;
4108 }
4109
4110 if (GET_CODE (ad) == PLUS
4111 && GET_CODE (XEXP (ad, 0)) == REG
4112 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4113 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4114 {
4115 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4116 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4117 rtx cst, tem, new_rtx;
4118
4119 cst = GEN_INT (upper);
4120 if (!legitimate_reload_constant_p (cst))
4121 cst = force_const_mem (Pmode, cst);
4122
4123 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4124 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4125
4126 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4127 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4128 opnum, (enum reload_type) type);
4129 return new_rtx;
4130 }
4131
4132 return NULL_RTX;
4133 }
4134
4135 /* Emit code to move LEN bytes from DST to SRC. */
4136
4137 bool
4138 s390_expand_movmem (rtx dst, rtx src, rtx len)
4139 {
4140 /* When tuning for z10 or higher we rely on the Glibc functions to
4141 do the right thing. Only for constant lengths below 64k we will
4142 generate inline code. */
4143 if (s390_tune >= PROCESSOR_2097_Z10
4144 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4145 return false;
4146
4147 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4148 {
4149 if (INTVAL (len) > 0)
4150 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4151 }
4152
4153 else if (TARGET_MVCLE)
4154 {
4155 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4156 }
4157
4158 else
4159 {
4160 rtx dst_addr, src_addr, count, blocks, temp;
4161 rtx loop_start_label = gen_label_rtx ();
4162 rtx loop_end_label = gen_label_rtx ();
4163 rtx end_label = gen_label_rtx ();
4164 enum machine_mode mode;
4165
4166 mode = GET_MODE (len);
4167 if (mode == VOIDmode)
4168 mode = Pmode;
4169
4170 dst_addr = gen_reg_rtx (Pmode);
4171 src_addr = gen_reg_rtx (Pmode);
4172 count = gen_reg_rtx (mode);
4173 blocks = gen_reg_rtx (mode);
4174
4175 convert_move (count, len, 1);
4176 emit_cmp_and_jump_insns (count, const0_rtx,
4177 EQ, NULL_RTX, mode, 1, end_label);
4178
4179 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4180 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4181 dst = change_address (dst, VOIDmode, dst_addr);
4182 src = change_address (src, VOIDmode, src_addr);
4183
4184 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4185 OPTAB_DIRECT);
4186 if (temp != count)
4187 emit_move_insn (count, temp);
4188
4189 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4190 OPTAB_DIRECT);
4191 if (temp != blocks)
4192 emit_move_insn (blocks, temp);
4193
4194 emit_cmp_and_jump_insns (blocks, const0_rtx,
4195 EQ, NULL_RTX, mode, 1, loop_end_label);
4196
4197 emit_label (loop_start_label);
4198
4199 if (TARGET_Z10
4200 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4201 {
4202 rtx prefetch;
4203
4204 /* Issue a read prefetch for the +3 cache line. */
4205 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4206 const0_rtx, const0_rtx);
4207 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4208 emit_insn (prefetch);
4209
4210 /* Issue a write prefetch for the +3 cache line. */
4211 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4212 const1_rtx, const0_rtx);
4213 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4214 emit_insn (prefetch);
4215 }
4216
4217 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4218 s390_load_address (dst_addr,
4219 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4220 s390_load_address (src_addr,
4221 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4222
4223 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4224 OPTAB_DIRECT);
4225 if (temp != blocks)
4226 emit_move_insn (blocks, temp);
4227
4228 emit_cmp_and_jump_insns (blocks, const0_rtx,
4229 EQ, NULL_RTX, mode, 1, loop_end_label);
4230
4231 emit_jump (loop_start_label);
4232 emit_label (loop_end_label);
4233
4234 emit_insn (gen_movmem_short (dst, src,
4235 convert_to_mode (Pmode, count, 1)));
4236 emit_label (end_label);
4237 }
4238 return true;
4239 }
4240
4241 /* Emit code to set LEN bytes at DST to VAL.
4242 Make use of clrmem if VAL is zero. */
4243
4244 void
4245 s390_expand_setmem (rtx dst, rtx len, rtx val)
4246 {
4247 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4248 return;
4249
4250 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4251
4252 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4253 {
4254 if (val == const0_rtx && INTVAL (len) <= 256)
4255 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4256 else
4257 {
4258 /* Initialize memory by storing the first byte. */
4259 emit_move_insn (adjust_address (dst, QImode, 0), val);
4260
4261 if (INTVAL (len) > 1)
4262 {
4263 /* Initiate 1 byte overlap move.
4264 The first byte of DST is propagated through DSTP1.
4265 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4266 DST is set to size 1 so the rest of the memory location
4267 does not count as source operand. */
4268 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4269 set_mem_size (dst, 1);
4270
4271 emit_insn (gen_movmem_short (dstp1, dst,
4272 GEN_INT (INTVAL (len) - 2)));
4273 }
4274 }
4275 }
4276
4277 else if (TARGET_MVCLE)
4278 {
4279 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4280 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4281 }
4282
4283 else
4284 {
4285 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4286 rtx loop_start_label = gen_label_rtx ();
4287 rtx loop_end_label = gen_label_rtx ();
4288 rtx end_label = gen_label_rtx ();
4289 enum machine_mode mode;
4290
4291 mode = GET_MODE (len);
4292 if (mode == VOIDmode)
4293 mode = Pmode;
4294
4295 dst_addr = gen_reg_rtx (Pmode);
4296 count = gen_reg_rtx (mode);
4297 blocks = gen_reg_rtx (mode);
4298
4299 convert_move (count, len, 1);
4300 emit_cmp_and_jump_insns (count, const0_rtx,
4301 EQ, NULL_RTX, mode, 1, end_label);
4302
4303 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4304 dst = change_address (dst, VOIDmode, dst_addr);
4305
4306 if (val == const0_rtx)
4307 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4308 OPTAB_DIRECT);
4309 else
4310 {
4311 dstp1 = adjust_address (dst, VOIDmode, 1);
4312 set_mem_size (dst, 1);
4313
4314 /* Initialize memory by storing the first byte. */
4315 emit_move_insn (adjust_address (dst, QImode, 0), val);
4316
4317 /* If count is 1 we are done. */
4318 emit_cmp_and_jump_insns (count, const1_rtx,
4319 EQ, NULL_RTX, mode, 1, end_label);
4320
4321 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4322 OPTAB_DIRECT);
4323 }
4324 if (temp != count)
4325 emit_move_insn (count, temp);
4326
4327 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4328 OPTAB_DIRECT);
4329 if (temp != blocks)
4330 emit_move_insn (blocks, temp);
4331
4332 emit_cmp_and_jump_insns (blocks, const0_rtx,
4333 EQ, NULL_RTX, mode, 1, loop_end_label);
4334
4335 emit_label (loop_start_label);
4336
4337 if (TARGET_Z10
4338 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4339 {
4340 /* Issue a write prefetch for the +4 cache line. */
4341 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4342 GEN_INT (1024)),
4343 const1_rtx, const0_rtx);
4344 emit_insn (prefetch);
4345 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4346 }
4347
4348 if (val == const0_rtx)
4349 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4350 else
4351 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4352 s390_load_address (dst_addr,
4353 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4354
4355 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4356 OPTAB_DIRECT);
4357 if (temp != blocks)
4358 emit_move_insn (blocks, temp);
4359
4360 emit_cmp_and_jump_insns (blocks, const0_rtx,
4361 EQ, NULL_RTX, mode, 1, loop_end_label);
4362
4363 emit_jump (loop_start_label);
4364 emit_label (loop_end_label);
4365
4366 if (val == const0_rtx)
4367 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4368 else
4369 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4370 emit_label (end_label);
4371 }
4372 }
4373
4374 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4375 and return the result in TARGET. */
4376
4377 bool
4378 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4379 {
4380 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4381 rtx tmp;
4382
4383 /* When tuning for z10 or higher we rely on the Glibc functions to
4384 do the right thing. Only for constant lengths below 64k we will
4385 generate inline code. */
4386 if (s390_tune >= PROCESSOR_2097_Z10
4387 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4388 return false;
4389
4390 /* As the result of CMPINT is inverted compared to what we need,
4391 we have to swap the operands. */
4392 tmp = op0; op0 = op1; op1 = tmp;
4393
4394 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4395 {
4396 if (INTVAL (len) > 0)
4397 {
4398 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4399 emit_insn (gen_cmpint (target, ccreg));
4400 }
4401 else
4402 emit_move_insn (target, const0_rtx);
4403 }
4404 else if (TARGET_MVCLE)
4405 {
4406 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4407 emit_insn (gen_cmpint (target, ccreg));
4408 }
4409 else
4410 {
4411 rtx addr0, addr1, count, blocks, temp;
4412 rtx loop_start_label = gen_label_rtx ();
4413 rtx loop_end_label = gen_label_rtx ();
4414 rtx end_label = gen_label_rtx ();
4415 enum machine_mode mode;
4416
4417 mode = GET_MODE (len);
4418 if (mode == VOIDmode)
4419 mode = Pmode;
4420
4421 addr0 = gen_reg_rtx (Pmode);
4422 addr1 = gen_reg_rtx (Pmode);
4423 count = gen_reg_rtx (mode);
4424 blocks = gen_reg_rtx (mode);
4425
4426 convert_move (count, len, 1);
4427 emit_cmp_and_jump_insns (count, const0_rtx,
4428 EQ, NULL_RTX, mode, 1, end_label);
4429
4430 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4431 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4432 op0 = change_address (op0, VOIDmode, addr0);
4433 op1 = change_address (op1, VOIDmode, addr1);
4434
4435 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4436 OPTAB_DIRECT);
4437 if (temp != count)
4438 emit_move_insn (count, temp);
4439
4440 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4441 OPTAB_DIRECT);
4442 if (temp != blocks)
4443 emit_move_insn (blocks, temp);
4444
4445 emit_cmp_and_jump_insns (blocks, const0_rtx,
4446 EQ, NULL_RTX, mode, 1, loop_end_label);
4447
4448 emit_label (loop_start_label);
4449
4450 if (TARGET_Z10
4451 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4452 {
4453 rtx prefetch;
4454
4455 /* Issue a read prefetch for the +2 cache line of operand 1. */
4456 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4457 const0_rtx, const0_rtx);
4458 emit_insn (prefetch);
4459 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4460
4461 /* Issue a read prefetch for the +2 cache line of operand 2. */
4462 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4463 const0_rtx, const0_rtx);
4464 emit_insn (prefetch);
4465 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4466 }
4467
4468 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4469 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4470 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4471 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4472 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4473 emit_jump_insn (temp);
4474
4475 s390_load_address (addr0,
4476 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4477 s390_load_address (addr1,
4478 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4479
4480 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4481 OPTAB_DIRECT);
4482 if (temp != blocks)
4483 emit_move_insn (blocks, temp);
4484
4485 emit_cmp_and_jump_insns (blocks, const0_rtx,
4486 EQ, NULL_RTX, mode, 1, loop_end_label);
4487
4488 emit_jump (loop_start_label);
4489 emit_label (loop_end_label);
4490
4491 emit_insn (gen_cmpmem_short (op0, op1,
4492 convert_to_mode (Pmode, count, 1)));
4493 emit_label (end_label);
4494
4495 emit_insn (gen_cmpint (target, ccreg));
4496 }
4497 return true;
4498 }
4499
4500
4501 /* Expand conditional increment or decrement using alc/slb instructions.
4502 Should generate code setting DST to either SRC or SRC + INCREMENT,
4503 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4504 Returns true if successful, false otherwise.
4505
4506 That makes it possible to implement some if-constructs without jumps e.g.:
4507 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4508 unsigned int a, b, c;
4509 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4510 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4511 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4512 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4513
4514 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4515 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4516 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4517 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4518 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4519
4520 bool
4521 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4522 rtx dst, rtx src, rtx increment)
4523 {
4524 enum machine_mode cmp_mode;
4525 enum machine_mode cc_mode;
4526 rtx op_res;
4527 rtx insn;
4528 rtvec p;
4529 int ret;
4530
4531 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4532 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4533 cmp_mode = SImode;
4534 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4535 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4536 cmp_mode = DImode;
4537 else
4538 return false;
4539
4540 /* Try ADD LOGICAL WITH CARRY. */
4541 if (increment == const1_rtx)
4542 {
4543 /* Determine CC mode to use. */
4544 if (cmp_code == EQ || cmp_code == NE)
4545 {
4546 if (cmp_op1 != const0_rtx)
4547 {
4548 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4549 NULL_RTX, 0, OPTAB_WIDEN);
4550 cmp_op1 = const0_rtx;
4551 }
4552
4553 cmp_code = cmp_code == EQ ? LEU : GTU;
4554 }
4555
4556 if (cmp_code == LTU || cmp_code == LEU)
4557 {
4558 rtx tem = cmp_op0;
4559 cmp_op0 = cmp_op1;
4560 cmp_op1 = tem;
4561 cmp_code = swap_condition (cmp_code);
4562 }
4563
4564 switch (cmp_code)
4565 {
4566 case GTU:
4567 cc_mode = CCUmode;
4568 break;
4569
4570 case GEU:
4571 cc_mode = CCL3mode;
4572 break;
4573
4574 default:
4575 return false;
4576 }
4577
4578 /* Emit comparison instruction pattern. */
4579 if (!register_operand (cmp_op0, cmp_mode))
4580 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4581
4582 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4583 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4584 /* We use insn_invalid_p here to add clobbers if required. */
4585 ret = insn_invalid_p (emit_insn (insn), false);
4586 gcc_assert (!ret);
4587
4588 /* Emit ALC instruction pattern. */
4589 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4590 gen_rtx_REG (cc_mode, CC_REGNUM),
4591 const0_rtx);
4592
4593 if (src != const0_rtx)
4594 {
4595 if (!register_operand (src, GET_MODE (dst)))
4596 src = force_reg (GET_MODE (dst), src);
4597
4598 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4599 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4600 }
4601
4602 p = rtvec_alloc (2);
4603 RTVEC_ELT (p, 0) =
4604 gen_rtx_SET (VOIDmode, dst, op_res);
4605 RTVEC_ELT (p, 1) =
4606 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4607 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4608
4609 return true;
4610 }
4611
4612 /* Try SUBTRACT LOGICAL WITH BORROW. */
4613 if (increment == constm1_rtx)
4614 {
4615 /* Determine CC mode to use. */
4616 if (cmp_code == EQ || cmp_code == NE)
4617 {
4618 if (cmp_op1 != const0_rtx)
4619 {
4620 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4621 NULL_RTX, 0, OPTAB_WIDEN);
4622 cmp_op1 = const0_rtx;
4623 }
4624
4625 cmp_code = cmp_code == EQ ? LEU : GTU;
4626 }
4627
4628 if (cmp_code == GTU || cmp_code == GEU)
4629 {
4630 rtx tem = cmp_op0;
4631 cmp_op0 = cmp_op1;
4632 cmp_op1 = tem;
4633 cmp_code = swap_condition (cmp_code);
4634 }
4635
4636 switch (cmp_code)
4637 {
4638 case LEU:
4639 cc_mode = CCUmode;
4640 break;
4641
4642 case LTU:
4643 cc_mode = CCL3mode;
4644 break;
4645
4646 default:
4647 return false;
4648 }
4649
4650 /* Emit comparison instruction pattern. */
4651 if (!register_operand (cmp_op0, cmp_mode))
4652 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4653
4654 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4655 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4656 /* We use insn_invalid_p here to add clobbers if required. */
4657 ret = insn_invalid_p (emit_insn (insn), false);
4658 gcc_assert (!ret);
4659
4660 /* Emit SLB instruction pattern. */
4661 if (!register_operand (src, GET_MODE (dst)))
4662 src = force_reg (GET_MODE (dst), src);
4663
4664 op_res = gen_rtx_MINUS (GET_MODE (dst),
4665 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4666 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4667 gen_rtx_REG (cc_mode, CC_REGNUM),
4668 const0_rtx));
4669 p = rtvec_alloc (2);
4670 RTVEC_ELT (p, 0) =
4671 gen_rtx_SET (VOIDmode, dst, op_res);
4672 RTVEC_ELT (p, 1) =
4673 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4674 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4675
4676 return true;
4677 }
4678
4679 return false;
4680 }
4681
4682 /* Expand code for the insv template. Return true if successful. */
4683
4684 bool
4685 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4686 {
4687 int bitsize = INTVAL (op1);
4688 int bitpos = INTVAL (op2);
4689 enum machine_mode mode = GET_MODE (dest);
4690 enum machine_mode smode;
4691 int smode_bsize, mode_bsize;
4692 rtx op, clobber;
4693
4694 if (bitsize + bitpos > GET_MODE_SIZE (mode))
4695 return false;
4696
4697 /* Generate INSERT IMMEDIATE (IILL et al). */
4698 /* (set (ze (reg)) (const_int)). */
4699 if (TARGET_ZARCH
4700 && register_operand (dest, word_mode)
4701 && (bitpos % 16) == 0
4702 && (bitsize % 16) == 0
4703 && const_int_operand (src, VOIDmode))
4704 {
4705 HOST_WIDE_INT val = INTVAL (src);
4706 int regpos = bitpos + bitsize;
4707
4708 while (regpos > bitpos)
4709 {
4710 enum machine_mode putmode;
4711 int putsize;
4712
4713 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4714 putmode = SImode;
4715 else
4716 putmode = HImode;
4717
4718 putsize = GET_MODE_BITSIZE (putmode);
4719 regpos -= putsize;
4720 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4721 GEN_INT (putsize),
4722 GEN_INT (regpos)),
4723 gen_int_mode (val, putmode));
4724 val >>= putsize;
4725 }
4726 gcc_assert (regpos == bitpos);
4727 return true;
4728 }
4729
4730 smode = smallest_mode_for_size (bitsize, MODE_INT);
4731 smode_bsize = GET_MODE_BITSIZE (smode);
4732 mode_bsize = GET_MODE_BITSIZE (mode);
4733
4734 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4735 if (bitpos == 0
4736 && (bitsize % BITS_PER_UNIT) == 0
4737 && MEM_P (dest)
4738 && (register_operand (src, word_mode)
4739 || const_int_operand (src, VOIDmode)))
4740 {
4741 /* Emit standard pattern if possible. */
4742 if (smode_bsize == bitsize)
4743 {
4744 emit_move_insn (adjust_address (dest, smode, 0),
4745 gen_lowpart (smode, src));
4746 return true;
4747 }
4748
4749 /* (set (ze (mem)) (const_int)). */
4750 else if (const_int_operand (src, VOIDmode))
4751 {
4752 int size = bitsize / BITS_PER_UNIT;
4753 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4754 BLKmode,
4755 UNITS_PER_WORD - size);
4756
4757 dest = adjust_address (dest, BLKmode, 0);
4758 set_mem_size (dest, size);
4759 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4760 return true;
4761 }
4762
4763 /* (set (ze (mem)) (reg)). */
4764 else if (register_operand (src, word_mode))
4765 {
4766 if (bitsize <= 32)
4767 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4768 const0_rtx), src);
4769 else
4770 {
4771 /* Emit st,stcmh sequence. */
4772 int stcmh_width = bitsize - 32;
4773 int size = stcmh_width / BITS_PER_UNIT;
4774
4775 emit_move_insn (adjust_address (dest, SImode, size),
4776 gen_lowpart (SImode, src));
4777 set_mem_size (dest, size);
4778 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4779 GEN_INT (stcmh_width),
4780 const0_rtx),
4781 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
4782 }
4783 return true;
4784 }
4785 }
4786
4787 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4788 if ((bitpos % BITS_PER_UNIT) == 0
4789 && (bitsize % BITS_PER_UNIT) == 0
4790 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4791 && MEM_P (src)
4792 && (mode == DImode || mode == SImode)
4793 && register_operand (dest, mode))
4794 {
4795 /* Emit a strict_low_part pattern if possible. */
4796 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4797 {
4798 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4799 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4800 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4801 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4802 return true;
4803 }
4804
4805 /* ??? There are more powerful versions of ICM that are not
4806 completely represented in the md file. */
4807 }
4808
4809 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4810 if (TARGET_Z10 && (mode == DImode || mode == SImode))
4811 {
4812 enum machine_mode mode_s = GET_MODE (src);
4813
4814 if (mode_s == VOIDmode)
4815 {
4816 /* Assume const_int etc already in the proper mode. */
4817 src = force_reg (mode, src);
4818 }
4819 else if (mode_s != mode)
4820 {
4821 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4822 src = force_reg (mode_s, src);
4823 src = gen_lowpart (mode, src);
4824 }
4825
4826 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4827 op = gen_rtx_SET (VOIDmode, op, src);
4828
4829 if (!TARGET_ZEC12)
4830 {
4831 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4832 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4833 }
4834 emit_insn (op);
4835
4836 return true;
4837 }
4838
4839 return false;
4840 }
4841
4842 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4843 register that holds VAL of mode MODE shifted by COUNT bits. */
4844
4845 static inline rtx
4846 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4847 {
4848 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4849 NULL_RTX, 1, OPTAB_DIRECT);
4850 return expand_simple_binop (SImode, ASHIFT, val, count,
4851 NULL_RTX, 1, OPTAB_DIRECT);
4852 }
4853
4854 /* Structure to hold the initial parameters for a compare_and_swap operation
4855 in HImode and QImode. */
4856
4857 struct alignment_context
4858 {
4859 rtx memsi; /* SI aligned memory location. */
4860 rtx shift; /* Bit offset with regard to lsb. */
4861 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4862 rtx modemaski; /* ~modemask */
4863 bool aligned; /* True if memory is aligned, false else. */
4864 };
4865
4866 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4867 structure AC for transparent simplifying, if the memory alignment is known
4868 to be at least 32bit. MEM is the memory location for the actual operation
4869 and MODE its mode. */
4870
4871 static void
4872 init_alignment_context (struct alignment_context *ac, rtx mem,
4873 enum machine_mode mode)
4874 {
4875 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4876 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4877
4878 if (ac->aligned)
4879 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4880 else
4881 {
4882 /* Alignment is unknown. */
4883 rtx byteoffset, addr, align;
4884
4885 /* Force the address into a register. */
4886 addr = force_reg (Pmode, XEXP (mem, 0));
4887
4888 /* Align it to SImode. */
4889 align = expand_simple_binop (Pmode, AND, addr,
4890 GEN_INT (-GET_MODE_SIZE (SImode)),
4891 NULL_RTX, 1, OPTAB_DIRECT);
4892 /* Generate MEM. */
4893 ac->memsi = gen_rtx_MEM (SImode, align);
4894 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4895 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4896 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4897
4898 /* Calculate shiftcount. */
4899 byteoffset = expand_simple_binop (Pmode, AND, addr,
4900 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4901 NULL_RTX, 1, OPTAB_DIRECT);
4902 /* As we already have some offset, evaluate the remaining distance. */
4903 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4904 NULL_RTX, 1, OPTAB_DIRECT);
4905 }
4906
4907 /* Shift is the byte count, but we need the bitcount. */
4908 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4909 NULL_RTX, 1, OPTAB_DIRECT);
4910
4911 /* Calculate masks. */
4912 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4913 GEN_INT (GET_MODE_MASK (mode)),
4914 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4915 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4916 NULL_RTX, 1);
4917 }
4918
4919 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4920 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4921 perform the merge in SEQ2. */
4922
4923 static rtx
4924 s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4925 enum machine_mode mode, rtx val, rtx ins)
4926 {
4927 rtx tmp;
4928
4929 if (ac->aligned)
4930 {
4931 start_sequence ();
4932 tmp = copy_to_mode_reg (SImode, val);
4933 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4934 const0_rtx, ins))
4935 {
4936 *seq1 = NULL;
4937 *seq2 = get_insns ();
4938 end_sequence ();
4939 return tmp;
4940 }
4941 end_sequence ();
4942 }
4943
4944 /* Failed to use insv. Generate a two part shift and mask. */
4945 start_sequence ();
4946 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4947 *seq1 = get_insns ();
4948 end_sequence ();
4949
4950 start_sequence ();
4951 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4952 *seq2 = get_insns ();
4953 end_sequence ();
4954
4955 return tmp;
4956 }
4957
4958 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4959 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4960 value to set if CMP == MEM. */
4961
4962 void
4963 s390_expand_cs_hqi (enum machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4964 rtx cmp, rtx new_rtx, bool is_weak)
4965 {
4966 struct alignment_context ac;
4967 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
4968 rtx res = gen_reg_rtx (SImode);
4969 rtx csloop = NULL, csend = NULL;
4970
4971 gcc_assert (MEM_P (mem));
4972
4973 init_alignment_context (&ac, mem, mode);
4974
4975 /* Load full word. Subsequent loads are performed by CS. */
4976 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4977 NULL_RTX, 1, OPTAB_DIRECT);
4978
4979 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4980 possible, we try to use insv to make this happen efficiently. If
4981 that fails we'll generate code both inside and outside the loop. */
4982 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4983 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4984
4985 if (seq0)
4986 emit_insn (seq0);
4987 if (seq1)
4988 emit_insn (seq1);
4989
4990 /* Start CS loop. */
4991 if (!is_weak)
4992 {
4993 /* Begin assuming success. */
4994 emit_move_insn (btarget, const1_rtx);
4995
4996 csloop = gen_label_rtx ();
4997 csend = gen_label_rtx ();
4998 emit_label (csloop);
4999 }
5000
5001 /* val = "<mem>00..0<mem>"
5002 * cmp = "00..0<cmp>00..0"
5003 * new = "00..0<new>00..0"
5004 */
5005
5006 emit_insn (seq2);
5007 emit_insn (seq3);
5008
5009 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
5010 if (is_weak)
5011 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
5012 else
5013 {
5014 rtx tmp;
5015
5016 /* Jump to end if we're done (likely?). */
5017 s390_emit_jump (csend, cc);
5018
5019 /* Check for changes outside mode, and loop internal if so.
5020 Arrange the moves so that the compare is adjacent to the
5021 branch so that we can generate CRJ. */
5022 tmp = copy_to_reg (val);
5023 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
5024 1, OPTAB_DIRECT);
5025 cc = s390_emit_compare (NE, val, tmp);
5026 s390_emit_jump (csloop, cc);
5027
5028 /* Failed. */
5029 emit_move_insn (btarget, const0_rtx);
5030 emit_label (csend);
5031 }
5032
5033 /* Return the correct part of the bitfield. */
5034 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
5035 NULL_RTX, 1, OPTAB_DIRECT), 1);
5036 }
5037
5038 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
5039 and VAL the value to play with. If AFTER is true then store the value
5040 MEM holds after the operation, if AFTER is false then store the value MEM
5041 holds before the operation. If TARGET is zero then discard that value, else
5042 store it to TARGET. */
5043
5044 void
5045 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
5046 rtx target, rtx mem, rtx val, bool after)
5047 {
5048 struct alignment_context ac;
5049 rtx cmp;
5050 rtx new_rtx = gen_reg_rtx (SImode);
5051 rtx orig = gen_reg_rtx (SImode);
5052 rtx csloop = gen_label_rtx ();
5053
5054 gcc_assert (!target || register_operand (target, VOIDmode));
5055 gcc_assert (MEM_P (mem));
5056
5057 init_alignment_context (&ac, mem, mode);
5058
5059 /* Shift val to the correct bit positions.
5060 Preserve "icm", but prevent "ex icm". */
5061 if (!(ac.aligned && code == SET && MEM_P (val)))
5062 val = s390_expand_mask_and_shift (val, mode, ac.shift);
5063
5064 /* Further preparation insns. */
5065 if (code == PLUS || code == MINUS)
5066 emit_move_insn (orig, val);
5067 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
5068 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
5069 NULL_RTX, 1, OPTAB_DIRECT);
5070
5071 /* Load full word. Subsequent loads are performed by CS. */
5072 cmp = force_reg (SImode, ac.memsi);
5073
5074 /* Start CS loop. */
5075 emit_label (csloop);
5076 emit_move_insn (new_rtx, cmp);
5077
5078 /* Patch new with val at correct position. */
5079 switch (code)
5080 {
5081 case PLUS:
5082 case MINUS:
5083 val = expand_simple_binop (SImode, code, new_rtx, orig,
5084 NULL_RTX, 1, OPTAB_DIRECT);
5085 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5086 NULL_RTX, 1, OPTAB_DIRECT);
5087 /* FALLTHRU */
5088 case SET:
5089 if (ac.aligned && MEM_P (val))
5090 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5091 0, 0, SImode, val);
5092 else
5093 {
5094 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
5095 NULL_RTX, 1, OPTAB_DIRECT);
5096 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
5097 NULL_RTX, 1, OPTAB_DIRECT);
5098 }
5099 break;
5100 case AND:
5101 case IOR:
5102 case XOR:
5103 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
5104 NULL_RTX, 1, OPTAB_DIRECT);
5105 break;
5106 case MULT: /* NAND */
5107 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
5108 NULL_RTX, 1, OPTAB_DIRECT);
5109 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5110 NULL_RTX, 1, OPTAB_DIRECT);
5111 break;
5112 default:
5113 gcc_unreachable ();
5114 }
5115
5116 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
5117 ac.memsi, cmp, new_rtx));
5118
5119 /* Return the correct part of the bitfield. */
5120 if (target)
5121 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
5122 after ? new_rtx : cmp, ac.shift,
5123 NULL_RTX, 1, OPTAB_DIRECT), 1);
5124 }
5125
5126 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5127 We need to emit DTP-relative relocations. */
5128
5129 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5130
5131 static void
5132 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
5133 {
5134 switch (size)
5135 {
5136 case 4:
5137 fputs ("\t.long\t", file);
5138 break;
5139 case 8:
5140 fputs ("\t.quad\t", file);
5141 break;
5142 default:
5143 gcc_unreachable ();
5144 }
5145 output_addr_const (file, x);
5146 fputs ("@DTPOFF", file);
5147 }
5148
5149 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5150 /* Implement TARGET_MANGLE_TYPE. */
5151
5152 static const char *
5153 s390_mangle_type (const_tree type)
5154 {
5155 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5156 && TARGET_LONG_DOUBLE_128)
5157 return "g";
5158
5159 /* For all other types, use normal C++ mangling. */
5160 return NULL;
5161 }
5162 #endif
5163
5164 /* In the name of slightly smaller debug output, and to cater to
5165 general assembler lossage, recognize various UNSPEC sequences
5166 and turn them back into a direct symbol reference. */
5167
5168 static rtx
5169 s390_delegitimize_address (rtx orig_x)
5170 {
5171 rtx x, y;
5172
5173 orig_x = delegitimize_mem_from_attrs (orig_x);
5174 x = orig_x;
5175
5176 /* Extract the symbol ref from:
5177 (plus:SI (reg:SI 12 %r12)
5178 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5179 UNSPEC_GOTOFF/PLTOFF)))
5180 and
5181 (plus:SI (reg:SI 12 %r12)
5182 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5183 UNSPEC_GOTOFF/PLTOFF)
5184 (const_int 4 [0x4])))) */
5185 if (GET_CODE (x) == PLUS
5186 && REG_P (XEXP (x, 0))
5187 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5188 && GET_CODE (XEXP (x, 1)) == CONST)
5189 {
5190 HOST_WIDE_INT offset = 0;
5191
5192 /* The const operand. */
5193 y = XEXP (XEXP (x, 1), 0);
5194
5195 if (GET_CODE (y) == PLUS
5196 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5197 {
5198 offset = INTVAL (XEXP (y, 1));
5199 y = XEXP (y, 0);
5200 }
5201
5202 if (GET_CODE (y) == UNSPEC
5203 && (XINT (y, 1) == UNSPEC_GOTOFF
5204 || XINT (y, 1) == UNSPEC_PLTOFF))
5205 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
5206 }
5207
5208 if (GET_CODE (x) != MEM)
5209 return orig_x;
5210
5211 x = XEXP (x, 0);
5212 if (GET_CODE (x) == PLUS
5213 && GET_CODE (XEXP (x, 1)) == CONST
5214 && GET_CODE (XEXP (x, 0)) == REG
5215 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5216 {
5217 y = XEXP (XEXP (x, 1), 0);
5218 if (GET_CODE (y) == UNSPEC
5219 && XINT (y, 1) == UNSPEC_GOT)
5220 y = XVECEXP (y, 0, 0);
5221 else
5222 return orig_x;
5223 }
5224 else if (GET_CODE (x) == CONST)
5225 {
5226 /* Extract the symbol ref from:
5227 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5228 UNSPEC_PLT/GOTENT))) */
5229
5230 y = XEXP (x, 0);
5231 if (GET_CODE (y) == UNSPEC
5232 && (XINT (y, 1) == UNSPEC_GOTENT
5233 || XINT (y, 1) == UNSPEC_PLT))
5234 y = XVECEXP (y, 0, 0);
5235 else
5236 return orig_x;
5237 }
5238 else
5239 return orig_x;
5240
5241 if (GET_MODE (orig_x) != Pmode)
5242 {
5243 if (GET_MODE (orig_x) == BLKmode)
5244 return orig_x;
5245 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5246 if (y == NULL_RTX)
5247 return orig_x;
5248 }
5249 return y;
5250 }
5251
5252 /* Output operand OP to stdio stream FILE.
5253 OP is an address (register + offset) which is not used to address data;
5254 instead the rightmost bits are interpreted as the value. */
5255
5256 static void
5257 print_shift_count_operand (FILE *file, rtx op)
5258 {
5259 HOST_WIDE_INT offset;
5260 rtx base;
5261
5262 /* Extract base register and offset. */
5263 if (!s390_decompose_shift_count (op, &base, &offset))
5264 gcc_unreachable ();
5265
5266 /* Sanity check. */
5267 if (base)
5268 {
5269 gcc_assert (GET_CODE (base) == REG);
5270 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5271 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5272 }
5273
5274 /* Offsets are constricted to twelve bits. */
5275 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5276 if (base)
5277 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5278 }
5279
5280 /* See 'get_some_local_dynamic_name'. */
5281
5282 static int
5283 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5284 {
5285 rtx x = *px;
5286
5287 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5288 {
5289 x = get_pool_constant (x);
5290 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5291 }
5292
5293 if (GET_CODE (x) == SYMBOL_REF
5294 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5295 {
5296 cfun->machine->some_ld_name = XSTR (x, 0);
5297 return 1;
5298 }
5299
5300 return 0;
5301 }
5302
5303 /* Locate some local-dynamic symbol still in use by this function
5304 so that we can print its name in local-dynamic base patterns. */
5305
5306 static const char *
5307 get_some_local_dynamic_name (void)
5308 {
5309 rtx insn;
5310
5311 if (cfun->machine->some_ld_name)
5312 return cfun->machine->some_ld_name;
5313
5314 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5315 if (INSN_P (insn)
5316 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5317 return cfun->machine->some_ld_name;
5318
5319 gcc_unreachable ();
5320 }
5321
5322 /* Output machine-dependent UNSPECs occurring in address constant X
5323 in assembler syntax to stdio stream FILE. Returns true if the
5324 constant X could be recognized, false otherwise. */
5325
5326 static bool
5327 s390_output_addr_const_extra (FILE *file, rtx x)
5328 {
5329 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5330 switch (XINT (x, 1))
5331 {
5332 case UNSPEC_GOTENT:
5333 output_addr_const (file, XVECEXP (x, 0, 0));
5334 fprintf (file, "@GOTENT");
5335 return true;
5336 case UNSPEC_GOT:
5337 output_addr_const (file, XVECEXP (x, 0, 0));
5338 fprintf (file, "@GOT");
5339 return true;
5340 case UNSPEC_GOTOFF:
5341 output_addr_const (file, XVECEXP (x, 0, 0));
5342 fprintf (file, "@GOTOFF");
5343 return true;
5344 case UNSPEC_PLT:
5345 output_addr_const (file, XVECEXP (x, 0, 0));
5346 fprintf (file, "@PLT");
5347 return true;
5348 case UNSPEC_PLTOFF:
5349 output_addr_const (file, XVECEXP (x, 0, 0));
5350 fprintf (file, "@PLTOFF");
5351 return true;
5352 case UNSPEC_TLSGD:
5353 output_addr_const (file, XVECEXP (x, 0, 0));
5354 fprintf (file, "@TLSGD");
5355 return true;
5356 case UNSPEC_TLSLDM:
5357 assemble_name (file, get_some_local_dynamic_name ());
5358 fprintf (file, "@TLSLDM");
5359 return true;
5360 case UNSPEC_DTPOFF:
5361 output_addr_const (file, XVECEXP (x, 0, 0));
5362 fprintf (file, "@DTPOFF");
5363 return true;
5364 case UNSPEC_NTPOFF:
5365 output_addr_const (file, XVECEXP (x, 0, 0));
5366 fprintf (file, "@NTPOFF");
5367 return true;
5368 case UNSPEC_GOTNTPOFF:
5369 output_addr_const (file, XVECEXP (x, 0, 0));
5370 fprintf (file, "@GOTNTPOFF");
5371 return true;
5372 case UNSPEC_INDNTPOFF:
5373 output_addr_const (file, XVECEXP (x, 0, 0));
5374 fprintf (file, "@INDNTPOFF");
5375 return true;
5376 }
5377
5378 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5379 switch (XINT (x, 1))
5380 {
5381 case UNSPEC_POOL_OFFSET:
5382 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5383 output_addr_const (file, x);
5384 return true;
5385 }
5386 return false;
5387 }
5388
5389 /* Output address operand ADDR in assembler syntax to
5390 stdio stream FILE. */
5391
5392 void
5393 print_operand_address (FILE *file, rtx addr)
5394 {
5395 struct s390_address ad;
5396
5397 if (s390_loadrelative_operand_p (addr, NULL, NULL))
5398 {
5399 if (!TARGET_Z10)
5400 {
5401 output_operand_lossage ("symbolic memory references are "
5402 "only supported on z10 or later");
5403 return;
5404 }
5405 output_addr_const (file, addr);
5406 return;
5407 }
5408
5409 if (!s390_decompose_address (addr, &ad)
5410 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5411 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5412 output_operand_lossage ("cannot decompose address");
5413
5414 if (ad.disp)
5415 output_addr_const (file, ad.disp);
5416 else
5417 fprintf (file, "0");
5418
5419 if (ad.base && ad.indx)
5420 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5421 reg_names[REGNO (ad.base)]);
5422 else if (ad.base)
5423 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5424 }
5425
5426 /* Output operand X in assembler syntax to stdio stream FILE.
5427 CODE specified the format flag. The following format flags
5428 are recognized:
5429
5430 'C': print opcode suffix for branch condition.
5431 'D': print opcode suffix for inverse branch condition.
5432 'E': print opcode suffix for branch on index instruction.
5433 'G': print the size of the operand in bytes.
5434 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5435 'M': print the second word of a TImode operand.
5436 'N': print the second word of a DImode operand.
5437 'O': print only the displacement of a memory reference.
5438 'R': print only the base register of a memory reference.
5439 'S': print S-type memory reference (base+displacement).
5440 'Y': print shift count operand.
5441
5442 'b': print integer X as if it's an unsigned byte.
5443 'c': print integer X as if it's an signed byte.
5444 'e': "end" of DImode contiguous bitmask X.
5445 'f': "end" of SImode contiguous bitmask X.
5446 'h': print integer X as if it's a signed halfword.
5447 'i': print the first nonzero HImode part of X.
5448 'j': print the first HImode part unequal to -1 of X.
5449 'k': print the first nonzero SImode part of X.
5450 'm': print the first SImode part unequal to -1 of X.
5451 'o': print integer X as if it's an unsigned 32bit word.
5452 's': "start" of DImode contiguous bitmask X.
5453 't': "start" of SImode contiguous bitmask X.
5454 'x': print integer X as if it's an unsigned halfword.
5455 */
5456
5457 void
5458 print_operand (FILE *file, rtx x, int code)
5459 {
5460 HOST_WIDE_INT ival;
5461
5462 switch (code)
5463 {
5464 case 'C':
5465 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5466 return;
5467
5468 case 'D':
5469 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5470 return;
5471
5472 case 'E':
5473 if (GET_CODE (x) == LE)
5474 fprintf (file, "l");
5475 else if (GET_CODE (x) == GT)
5476 fprintf (file, "h");
5477 else
5478 output_operand_lossage ("invalid comparison operator "
5479 "for 'E' output modifier");
5480 return;
5481
5482 case 'J':
5483 if (GET_CODE (x) == SYMBOL_REF)
5484 {
5485 fprintf (file, "%s", ":tls_load:");
5486 output_addr_const (file, x);
5487 }
5488 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5489 {
5490 fprintf (file, "%s", ":tls_gdcall:");
5491 output_addr_const (file, XVECEXP (x, 0, 0));
5492 }
5493 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5494 {
5495 fprintf (file, "%s", ":tls_ldcall:");
5496 assemble_name (file, get_some_local_dynamic_name ());
5497 }
5498 else
5499 output_operand_lossage ("invalid reference for 'J' output modifier");
5500 return;
5501
5502 case 'G':
5503 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5504 return;
5505
5506 case 'O':
5507 {
5508 struct s390_address ad;
5509 int ret;
5510
5511 if (!MEM_P (x))
5512 {
5513 output_operand_lossage ("memory reference expected for "
5514 "'O' output modifier");
5515 return;
5516 }
5517
5518 ret = s390_decompose_address (XEXP (x, 0), &ad);
5519
5520 if (!ret
5521 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5522 || ad.indx)
5523 {
5524 output_operand_lossage ("invalid address for 'O' output modifier");
5525 return;
5526 }
5527
5528 if (ad.disp)
5529 output_addr_const (file, ad.disp);
5530 else
5531 fprintf (file, "0");
5532 }
5533 return;
5534
5535 case 'R':
5536 {
5537 struct s390_address ad;
5538 int ret;
5539
5540 if (!MEM_P (x))
5541 {
5542 output_operand_lossage ("memory reference expected for "
5543 "'R' output modifier");
5544 return;
5545 }
5546
5547 ret = s390_decompose_address (XEXP (x, 0), &ad);
5548
5549 if (!ret
5550 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5551 || ad.indx)
5552 {
5553 output_operand_lossage ("invalid address for 'R' output modifier");
5554 return;
5555 }
5556
5557 if (ad.base)
5558 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5559 else
5560 fprintf (file, "0");
5561 }
5562 return;
5563
5564 case 'S':
5565 {
5566 struct s390_address ad;
5567 int ret;
5568
5569 if (!MEM_P (x))
5570 {
5571 output_operand_lossage ("memory reference expected for "
5572 "'S' output modifier");
5573 return;
5574 }
5575 ret = s390_decompose_address (XEXP (x, 0), &ad);
5576
5577 if (!ret
5578 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5579 || ad.indx)
5580 {
5581 output_operand_lossage ("invalid address for 'S' output modifier");
5582 return;
5583 }
5584
5585 if (ad.disp)
5586 output_addr_const (file, ad.disp);
5587 else
5588 fprintf (file, "0");
5589
5590 if (ad.base)
5591 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5592 }
5593 return;
5594
5595 case 'N':
5596 if (GET_CODE (x) == REG)
5597 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5598 else if (GET_CODE (x) == MEM)
5599 x = change_address (x, VOIDmode,
5600 plus_constant (Pmode, XEXP (x, 0), 4));
5601 else
5602 output_operand_lossage ("register or memory expression expected "
5603 "for 'N' output modifier");
5604 break;
5605
5606 case 'M':
5607 if (GET_CODE (x) == REG)
5608 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5609 else if (GET_CODE (x) == MEM)
5610 x = change_address (x, VOIDmode,
5611 plus_constant (Pmode, XEXP (x, 0), 8));
5612 else
5613 output_operand_lossage ("register or memory expression expected "
5614 "for 'M' output modifier");
5615 break;
5616
5617 case 'Y':
5618 print_shift_count_operand (file, x);
5619 return;
5620 }
5621
5622 switch (GET_CODE (x))
5623 {
5624 case REG:
5625 fprintf (file, "%s", reg_names[REGNO (x)]);
5626 break;
5627
5628 case MEM:
5629 output_address (XEXP (x, 0));
5630 break;
5631
5632 case CONST:
5633 case CODE_LABEL:
5634 case LABEL_REF:
5635 case SYMBOL_REF:
5636 output_addr_const (file, x);
5637 break;
5638
5639 case CONST_INT:
5640 ival = INTVAL (x);
5641 switch (code)
5642 {
5643 case 0:
5644 break;
5645 case 'b':
5646 ival &= 0xff;
5647 break;
5648 case 'c':
5649 ival = ((ival & 0xff) ^ 0x80) - 0x80;
5650 break;
5651 case 'x':
5652 ival &= 0xffff;
5653 break;
5654 case 'h':
5655 ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
5656 break;
5657 case 'i':
5658 ival = s390_extract_part (x, HImode, 0);
5659 break;
5660 case 'j':
5661 ival = s390_extract_part (x, HImode, -1);
5662 break;
5663 case 'k':
5664 ival = s390_extract_part (x, SImode, 0);
5665 break;
5666 case 'm':
5667 ival = s390_extract_part (x, SImode, -1);
5668 break;
5669 case 'o':
5670 ival &= 0xffffffff;
5671 break;
5672 case 'e': case 'f':
5673 case 's': case 't':
5674 {
5675 int pos, len;
5676 bool ok;
5677
5678 len = (code == 's' || code == 'e' ? 64 : 32);
5679 ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
5680 gcc_assert (ok);
5681 if (code == 's' || code == 't')
5682 ival = 64 - pos - len;
5683 else
5684 ival = 64 - 1 - pos;
5685 }
5686 break;
5687 default:
5688 output_operand_lossage ("invalid constant for output modifier '%c'", code);
5689 }
5690 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
5691 break;
5692
5693 case CONST_DOUBLE:
5694 gcc_assert (GET_MODE (x) == VOIDmode);
5695 if (code == 'b')
5696 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5697 else if (code == 'x')
5698 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5699 else if (code == 'h')
5700 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5701 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5702 else
5703 {
5704 if (code == 0)
5705 output_operand_lossage ("invalid constant - try using "
5706 "an output modifier");
5707 else
5708 output_operand_lossage ("invalid constant for output modifier '%c'",
5709 code);
5710 }
5711 break;
5712
5713 default:
5714 if (code == 0)
5715 output_operand_lossage ("invalid expression - try using "
5716 "an output modifier");
5717 else
5718 output_operand_lossage ("invalid expression for output "
5719 "modifier '%c'", code);
5720 break;
5721 }
5722 }
5723
5724 /* Target hook for assembling integer objects. We need to define it
5725 here to work a round a bug in some versions of GAS, which couldn't
5726 handle values smaller than INT_MIN when printed in decimal. */
5727
5728 static bool
5729 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5730 {
5731 if (size == 8 && aligned_p
5732 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5733 {
5734 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5735 INTVAL (x));
5736 return true;
5737 }
5738 return default_assemble_integer (x, size, aligned_p);
5739 }
5740
5741 /* Returns true if register REGNO is used for forming
5742 a memory address in expression X. */
5743
5744 static bool
5745 reg_used_in_mem_p (int regno, rtx x)
5746 {
5747 enum rtx_code code = GET_CODE (x);
5748 int i, j;
5749 const char *fmt;
5750
5751 if (code == MEM)
5752 {
5753 if (refers_to_regno_p (regno, regno+1,
5754 XEXP (x, 0), 0))
5755 return true;
5756 }
5757 else if (code == SET
5758 && GET_CODE (SET_DEST (x)) == PC)
5759 {
5760 if (refers_to_regno_p (regno, regno+1,
5761 SET_SRC (x), 0))
5762 return true;
5763 }
5764
5765 fmt = GET_RTX_FORMAT (code);
5766 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5767 {
5768 if (fmt[i] == 'e'
5769 && reg_used_in_mem_p (regno, XEXP (x, i)))
5770 return true;
5771
5772 else if (fmt[i] == 'E')
5773 for (j = 0; j < XVECLEN (x, i); j++)
5774 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5775 return true;
5776 }
5777 return false;
5778 }
5779
5780 /* Returns true if expression DEP_RTX sets an address register
5781 used by instruction INSN to address memory. */
5782
5783 static bool
5784 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5785 {
5786 rtx target, pat;
5787
5788 if (NONJUMP_INSN_P (dep_rtx))
5789 dep_rtx = PATTERN (dep_rtx);
5790
5791 if (GET_CODE (dep_rtx) == SET)
5792 {
5793 target = SET_DEST (dep_rtx);
5794 if (GET_CODE (target) == STRICT_LOW_PART)
5795 target = XEXP (target, 0);
5796 while (GET_CODE (target) == SUBREG)
5797 target = SUBREG_REG (target);
5798
5799 if (GET_CODE (target) == REG)
5800 {
5801 int regno = REGNO (target);
5802
5803 if (s390_safe_attr_type (insn) == TYPE_LA)
5804 {
5805 pat = PATTERN (insn);
5806 if (GET_CODE (pat) == PARALLEL)
5807 {
5808 gcc_assert (XVECLEN (pat, 0) == 2);
5809 pat = XVECEXP (pat, 0, 0);
5810 }
5811 gcc_assert (GET_CODE (pat) == SET);
5812 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5813 }
5814 else if (get_attr_atype (insn) == ATYPE_AGEN)
5815 return reg_used_in_mem_p (regno, PATTERN (insn));
5816 }
5817 }
5818 return false;
5819 }
5820
5821 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5822
5823 int
5824 s390_agen_dep_p (rtx dep_insn, rtx insn)
5825 {
5826 rtx dep_rtx = PATTERN (dep_insn);
5827 int i;
5828
5829 if (GET_CODE (dep_rtx) == SET
5830 && addr_generation_dependency_p (dep_rtx, insn))
5831 return 1;
5832 else if (GET_CODE (dep_rtx) == PARALLEL)
5833 {
5834 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5835 {
5836 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5837 return 1;
5838 }
5839 }
5840 return 0;
5841 }
5842
5843
5844 /* A C statement (sans semicolon) to update the integer scheduling priority
5845 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5846 reduce the priority to execute INSN later. Do not define this macro if
5847 you do not need to adjust the scheduling priorities of insns.
5848
5849 A STD instruction should be scheduled earlier,
5850 in order to use the bypass. */
5851 static int
5852 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5853 {
5854 if (! INSN_P (insn))
5855 return priority;
5856
5857 if (s390_tune != PROCESSOR_2084_Z990
5858 && s390_tune != PROCESSOR_2094_Z9_109
5859 && s390_tune != PROCESSOR_2097_Z10
5860 && s390_tune != PROCESSOR_2817_Z196
5861 && s390_tune != PROCESSOR_2827_ZEC12)
5862 return priority;
5863
5864 switch (s390_safe_attr_type (insn))
5865 {
5866 case TYPE_FSTOREDF:
5867 case TYPE_FSTORESF:
5868 priority = priority << 3;
5869 break;
5870 case TYPE_STORE:
5871 case TYPE_STM:
5872 priority = priority << 1;
5873 break;
5874 default:
5875 break;
5876 }
5877 return priority;
5878 }
5879
5880
5881 /* The number of instructions that can be issued per cycle. */
5882
5883 static int
5884 s390_issue_rate (void)
5885 {
5886 switch (s390_tune)
5887 {
5888 case PROCESSOR_2084_Z990:
5889 case PROCESSOR_2094_Z9_109:
5890 case PROCESSOR_2817_Z196:
5891 return 3;
5892 case PROCESSOR_2097_Z10:
5893 case PROCESSOR_2827_ZEC12:
5894 return 2;
5895 default:
5896 return 1;
5897 }
5898 }
5899
5900 static int
5901 s390_first_cycle_multipass_dfa_lookahead (void)
5902 {
5903 return 4;
5904 }
5905
5906 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5907 Fix up MEMs as required. */
5908
5909 static void
5910 annotate_constant_pool_refs (rtx *x)
5911 {
5912 int i, j;
5913 const char *fmt;
5914
5915 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5916 || !CONSTANT_POOL_ADDRESS_P (*x));
5917
5918 /* Literal pool references can only occur inside a MEM ... */
5919 if (GET_CODE (*x) == MEM)
5920 {
5921 rtx memref = XEXP (*x, 0);
5922
5923 if (GET_CODE (memref) == SYMBOL_REF
5924 && CONSTANT_POOL_ADDRESS_P (memref))
5925 {
5926 rtx base = cfun->machine->base_reg;
5927 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5928 UNSPEC_LTREF);
5929
5930 *x = replace_equiv_address (*x, addr);
5931 return;
5932 }
5933
5934 if (GET_CODE (memref) == CONST
5935 && GET_CODE (XEXP (memref, 0)) == PLUS
5936 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5937 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5938 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5939 {
5940 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5941 rtx sym = XEXP (XEXP (memref, 0), 0);
5942 rtx base = cfun->machine->base_reg;
5943 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5944 UNSPEC_LTREF);
5945
5946 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5947 return;
5948 }
5949 }
5950
5951 /* ... or a load-address type pattern. */
5952 if (GET_CODE (*x) == SET)
5953 {
5954 rtx addrref = SET_SRC (*x);
5955
5956 if (GET_CODE (addrref) == SYMBOL_REF
5957 && CONSTANT_POOL_ADDRESS_P (addrref))
5958 {
5959 rtx base = cfun->machine->base_reg;
5960 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5961 UNSPEC_LTREF);
5962
5963 SET_SRC (*x) = addr;
5964 return;
5965 }
5966
5967 if (GET_CODE (addrref) == CONST
5968 && GET_CODE (XEXP (addrref, 0)) == PLUS
5969 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5970 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5971 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5972 {
5973 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5974 rtx sym = XEXP (XEXP (addrref, 0), 0);
5975 rtx base = cfun->machine->base_reg;
5976 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5977 UNSPEC_LTREF);
5978
5979 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5980 return;
5981 }
5982 }
5983
5984 /* Annotate LTREL_BASE as well. */
5985 if (GET_CODE (*x) == UNSPEC
5986 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5987 {
5988 rtx base = cfun->machine->base_reg;
5989 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5990 UNSPEC_LTREL_BASE);
5991 return;
5992 }
5993
5994 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5995 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5996 {
5997 if (fmt[i] == 'e')
5998 {
5999 annotate_constant_pool_refs (&XEXP (*x, i));
6000 }
6001 else if (fmt[i] == 'E')
6002 {
6003 for (j = 0; j < XVECLEN (*x, i); j++)
6004 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
6005 }
6006 }
6007 }
6008
6009 /* Split all branches that exceed the maximum distance.
6010 Returns true if this created a new literal pool entry. */
6011
6012 static int
6013 s390_split_branches (void)
6014 {
6015 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6016 int new_literal = 0, ret;
6017 rtx insn, pat, tmp, target;
6018 rtx *label;
6019
6020 /* We need correct insn addresses. */
6021
6022 shorten_branches (get_insns ());
6023
6024 /* Find all branches that exceed 64KB, and split them. */
6025
6026 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6027 {
6028 if (! JUMP_P (insn))
6029 continue;
6030
6031 pat = PATTERN (insn);
6032 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6033 pat = XVECEXP (pat, 0, 0);
6034 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
6035 continue;
6036
6037 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
6038 {
6039 label = &SET_SRC (pat);
6040 }
6041 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
6042 {
6043 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
6044 label = &XEXP (SET_SRC (pat), 1);
6045 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
6046 label = &XEXP (SET_SRC (pat), 2);
6047 else
6048 continue;
6049 }
6050 else
6051 continue;
6052
6053 if (get_attr_length (insn) <= 4)
6054 continue;
6055
6056 /* We are going to use the return register as scratch register,
6057 make sure it will be saved/restored by the prologue/epilogue. */
6058 cfun_frame_layout.save_return_addr_p = 1;
6059
6060 if (!flag_pic)
6061 {
6062 new_literal = 1;
6063 tmp = force_const_mem (Pmode, *label);
6064 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
6065 INSN_ADDRESSES_NEW (tmp, -1);
6066 annotate_constant_pool_refs (&PATTERN (tmp));
6067
6068 target = temp_reg;
6069 }
6070 else
6071 {
6072 new_literal = 1;
6073 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
6074 UNSPEC_LTREL_OFFSET);
6075 target = gen_rtx_CONST (Pmode, target);
6076 target = force_const_mem (Pmode, target);
6077 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
6078 INSN_ADDRESSES_NEW (tmp, -1);
6079 annotate_constant_pool_refs (&PATTERN (tmp));
6080
6081 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
6082 cfun->machine->base_reg),
6083 UNSPEC_LTREL_BASE);
6084 target = gen_rtx_PLUS (Pmode, temp_reg, target);
6085 }
6086
6087 ret = validate_change (insn, label, target, 0);
6088 gcc_assert (ret);
6089 }
6090
6091 return new_literal;
6092 }
6093
6094
6095 /* Find an annotated literal pool symbol referenced in RTX X,
6096 and store it at REF. Will abort if X contains references to
6097 more than one such pool symbol; multiple references to the same
6098 symbol are allowed, however.
6099
6100 The rtx pointed to by REF must be initialized to NULL_RTX
6101 by the caller before calling this routine. */
6102
6103 static void
6104 find_constant_pool_ref (rtx x, rtx *ref)
6105 {
6106 int i, j;
6107 const char *fmt;
6108
6109 /* Ignore LTREL_BASE references. */
6110 if (GET_CODE (x) == UNSPEC
6111 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6112 return;
6113 /* Likewise POOL_ENTRY insns. */
6114 if (GET_CODE (x) == UNSPEC_VOLATILE
6115 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6116 return;
6117
6118 gcc_assert (GET_CODE (x) != SYMBOL_REF
6119 || !CONSTANT_POOL_ADDRESS_P (x));
6120
6121 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
6122 {
6123 rtx sym = XVECEXP (x, 0, 0);
6124 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6125 && CONSTANT_POOL_ADDRESS_P (sym));
6126
6127 if (*ref == NULL_RTX)
6128 *ref = sym;
6129 else
6130 gcc_assert (*ref == sym);
6131
6132 return;
6133 }
6134
6135 fmt = GET_RTX_FORMAT (GET_CODE (x));
6136 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6137 {
6138 if (fmt[i] == 'e')
6139 {
6140 find_constant_pool_ref (XEXP (x, i), ref);
6141 }
6142 else if (fmt[i] == 'E')
6143 {
6144 for (j = 0; j < XVECLEN (x, i); j++)
6145 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6146 }
6147 }
6148 }
6149
6150 /* Replace every reference to the annotated literal pool
6151 symbol REF in X by its base plus OFFSET. */
6152
6153 static void
6154 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
6155 {
6156 int i, j;
6157 const char *fmt;
6158
6159 gcc_assert (*x != ref);
6160
6161 if (GET_CODE (*x) == UNSPEC
6162 && XINT (*x, 1) == UNSPEC_LTREF
6163 && XVECEXP (*x, 0, 0) == ref)
6164 {
6165 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6166 return;
6167 }
6168
6169 if (GET_CODE (*x) == PLUS
6170 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6171 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6172 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6173 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
6174 {
6175 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
6176 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
6177 return;
6178 }
6179
6180 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6181 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6182 {
6183 if (fmt[i] == 'e')
6184 {
6185 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
6186 }
6187 else if (fmt[i] == 'E')
6188 {
6189 for (j = 0; j < XVECLEN (*x, i); j++)
6190 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
6191 }
6192 }
6193 }
6194
6195 /* Check whether X contains an UNSPEC_LTREL_BASE.
6196 Return its constant pool symbol if found, NULL_RTX otherwise. */
6197
6198 static rtx
6199 find_ltrel_base (rtx x)
6200 {
6201 int i, j;
6202 const char *fmt;
6203
6204 if (GET_CODE (x) == UNSPEC
6205 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6206 return XVECEXP (x, 0, 0);
6207
6208 fmt = GET_RTX_FORMAT (GET_CODE (x));
6209 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6210 {
6211 if (fmt[i] == 'e')
6212 {
6213 rtx fnd = find_ltrel_base (XEXP (x, i));
6214 if (fnd)
6215 return fnd;
6216 }
6217 else if (fmt[i] == 'E')
6218 {
6219 for (j = 0; j < XVECLEN (x, i); j++)
6220 {
6221 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6222 if (fnd)
6223 return fnd;
6224 }
6225 }
6226 }
6227
6228 return NULL_RTX;
6229 }
6230
6231 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6232
6233 static void
6234 replace_ltrel_base (rtx *x)
6235 {
6236 int i, j;
6237 const char *fmt;
6238
6239 if (GET_CODE (*x) == UNSPEC
6240 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6241 {
6242 *x = XVECEXP (*x, 0, 1);
6243 return;
6244 }
6245
6246 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6247 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6248 {
6249 if (fmt[i] == 'e')
6250 {
6251 replace_ltrel_base (&XEXP (*x, i));
6252 }
6253 else if (fmt[i] == 'E')
6254 {
6255 for (j = 0; j < XVECLEN (*x, i); j++)
6256 replace_ltrel_base (&XVECEXP (*x, i, j));
6257 }
6258 }
6259 }
6260
6261
6262 /* We keep a list of constants which we have to add to internal
6263 constant tables in the middle of large functions. */
6264
6265 #define NR_C_MODES 11
6266 enum machine_mode constant_modes[NR_C_MODES] =
6267 {
6268 TFmode, TImode, TDmode,
6269 DFmode, DImode, DDmode,
6270 SFmode, SImode, SDmode,
6271 HImode,
6272 QImode
6273 };
6274
6275 struct constant
6276 {
6277 struct constant *next;
6278 rtx value;
6279 rtx label;
6280 };
6281
6282 struct constant_pool
6283 {
6284 struct constant_pool *next;
6285 rtx first_insn;
6286 rtx pool_insn;
6287 bitmap insns;
6288 rtx emit_pool_after;
6289
6290 struct constant *constants[NR_C_MODES];
6291 struct constant *execute;
6292 rtx label;
6293 int size;
6294 };
6295
6296 /* Allocate new constant_pool structure. */
6297
6298 static struct constant_pool *
6299 s390_alloc_pool (void)
6300 {
6301 struct constant_pool *pool;
6302 int i;
6303
6304 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6305 pool->next = NULL;
6306 for (i = 0; i < NR_C_MODES; i++)
6307 pool->constants[i] = NULL;
6308
6309 pool->execute = NULL;
6310 pool->label = gen_label_rtx ();
6311 pool->first_insn = NULL_RTX;
6312 pool->pool_insn = NULL_RTX;
6313 pool->insns = BITMAP_ALLOC (NULL);
6314 pool->size = 0;
6315 pool->emit_pool_after = NULL_RTX;
6316
6317 return pool;
6318 }
6319
6320 /* Create new constant pool covering instructions starting at INSN
6321 and chain it to the end of POOL_LIST. */
6322
6323 static struct constant_pool *
6324 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6325 {
6326 struct constant_pool *pool, **prev;
6327
6328 pool = s390_alloc_pool ();
6329 pool->first_insn = insn;
6330
6331 for (prev = pool_list; *prev; prev = &(*prev)->next)
6332 ;
6333 *prev = pool;
6334
6335 return pool;
6336 }
6337
6338 /* End range of instructions covered by POOL at INSN and emit
6339 placeholder insn representing the pool. */
6340
6341 static void
6342 s390_end_pool (struct constant_pool *pool, rtx insn)
6343 {
6344 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6345
6346 if (!insn)
6347 insn = get_last_insn ();
6348
6349 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6350 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6351 }
6352
6353 /* Add INSN to the list of insns covered by POOL. */
6354
6355 static void
6356 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6357 {
6358 bitmap_set_bit (pool->insns, INSN_UID (insn));
6359 }
6360
6361 /* Return pool out of POOL_LIST that covers INSN. */
6362
6363 static struct constant_pool *
6364 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6365 {
6366 struct constant_pool *pool;
6367
6368 for (pool = pool_list; pool; pool = pool->next)
6369 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6370 break;
6371
6372 return pool;
6373 }
6374
6375 /* Add constant VAL of mode MODE to the constant pool POOL. */
6376
6377 static void
6378 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6379 {
6380 struct constant *c;
6381 int i;
6382
6383 for (i = 0; i < NR_C_MODES; i++)
6384 if (constant_modes[i] == mode)
6385 break;
6386 gcc_assert (i != NR_C_MODES);
6387
6388 for (c = pool->constants[i]; c != NULL; c = c->next)
6389 if (rtx_equal_p (val, c->value))
6390 break;
6391
6392 if (c == NULL)
6393 {
6394 c = (struct constant *) xmalloc (sizeof *c);
6395 c->value = val;
6396 c->label = gen_label_rtx ();
6397 c->next = pool->constants[i];
6398 pool->constants[i] = c;
6399 pool->size += GET_MODE_SIZE (mode);
6400 }
6401 }
6402
6403 /* Return an rtx that represents the offset of X from the start of
6404 pool POOL. */
6405
6406 static rtx
6407 s390_pool_offset (struct constant_pool *pool, rtx x)
6408 {
6409 rtx label;
6410
6411 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6412 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6413 UNSPEC_POOL_OFFSET);
6414 return gen_rtx_CONST (GET_MODE (x), x);
6415 }
6416
6417 /* Find constant VAL of mode MODE in the constant pool POOL.
6418 Return an RTX describing the distance from the start of
6419 the pool to the location of the new constant. */
6420
6421 static rtx
6422 s390_find_constant (struct constant_pool *pool, rtx val,
6423 enum machine_mode mode)
6424 {
6425 struct constant *c;
6426 int i;
6427
6428 for (i = 0; i < NR_C_MODES; i++)
6429 if (constant_modes[i] == mode)
6430 break;
6431 gcc_assert (i != NR_C_MODES);
6432
6433 for (c = pool->constants[i]; c != NULL; c = c->next)
6434 if (rtx_equal_p (val, c->value))
6435 break;
6436
6437 gcc_assert (c);
6438
6439 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6440 }
6441
6442 /* Check whether INSN is an execute. Return the label_ref to its
6443 execute target template if so, NULL_RTX otherwise. */
6444
6445 static rtx
6446 s390_execute_label (rtx insn)
6447 {
6448 if (NONJUMP_INSN_P (insn)
6449 && GET_CODE (PATTERN (insn)) == PARALLEL
6450 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6451 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6452 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6453
6454 return NULL_RTX;
6455 }
6456
6457 /* Add execute target for INSN to the constant pool POOL. */
6458
6459 static void
6460 s390_add_execute (struct constant_pool *pool, rtx insn)
6461 {
6462 struct constant *c;
6463
6464 for (c = pool->execute; c != NULL; c = c->next)
6465 if (INSN_UID (insn) == INSN_UID (c->value))
6466 break;
6467
6468 if (c == NULL)
6469 {
6470 c = (struct constant *) xmalloc (sizeof *c);
6471 c->value = insn;
6472 c->label = gen_label_rtx ();
6473 c->next = pool->execute;
6474 pool->execute = c;
6475 pool->size += 6;
6476 }
6477 }
6478
6479 /* Find execute target for INSN in the constant pool POOL.
6480 Return an RTX describing the distance from the start of
6481 the pool to the location of the execute target. */
6482
6483 static rtx
6484 s390_find_execute (struct constant_pool *pool, rtx insn)
6485 {
6486 struct constant *c;
6487
6488 for (c = pool->execute; c != NULL; c = c->next)
6489 if (INSN_UID (insn) == INSN_UID (c->value))
6490 break;
6491
6492 gcc_assert (c);
6493
6494 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6495 }
6496
6497 /* For an execute INSN, extract the execute target template. */
6498
6499 static rtx
6500 s390_execute_target (rtx insn)
6501 {
6502 rtx pattern = PATTERN (insn);
6503 gcc_assert (s390_execute_label (insn));
6504
6505 if (XVECLEN (pattern, 0) == 2)
6506 {
6507 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6508 }
6509 else
6510 {
6511 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6512 int i;
6513
6514 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6515 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6516
6517 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6518 }
6519
6520 return pattern;
6521 }
6522
6523 /* Indicate that INSN cannot be duplicated. This is the case for
6524 execute insns that carry a unique label. */
6525
6526 static bool
6527 s390_cannot_copy_insn_p (rtx insn)
6528 {
6529 rtx label = s390_execute_label (insn);
6530 return label && label != const0_rtx;
6531 }
6532
6533 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6534 do not emit the pool base label. */
6535
6536 static void
6537 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6538 {
6539 struct constant *c;
6540 rtx insn = pool->pool_insn;
6541 int i;
6542
6543 /* Switch to rodata section. */
6544 if (TARGET_CPU_ZARCH)
6545 {
6546 insn = emit_insn_after (gen_pool_section_start (), insn);
6547 INSN_ADDRESSES_NEW (insn, -1);
6548 }
6549
6550 /* Ensure minimum pool alignment. */
6551 if (TARGET_CPU_ZARCH)
6552 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6553 else
6554 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6555 INSN_ADDRESSES_NEW (insn, -1);
6556
6557 /* Emit pool base label. */
6558 if (!remote_label)
6559 {
6560 insn = emit_label_after (pool->label, insn);
6561 INSN_ADDRESSES_NEW (insn, -1);
6562 }
6563
6564 /* Dump constants in descending alignment requirement order,
6565 ensuring proper alignment for every constant. */
6566 for (i = 0; i < NR_C_MODES; i++)
6567 for (c = pool->constants[i]; c; c = c->next)
6568 {
6569 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6570 rtx value = copy_rtx (c->value);
6571 if (GET_CODE (value) == CONST
6572 && GET_CODE (XEXP (value, 0)) == UNSPEC
6573 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6574 && XVECLEN (XEXP (value, 0), 0) == 1)
6575 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6576
6577 insn = emit_label_after (c->label, insn);
6578 INSN_ADDRESSES_NEW (insn, -1);
6579
6580 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6581 gen_rtvec (1, value),
6582 UNSPECV_POOL_ENTRY);
6583 insn = emit_insn_after (value, insn);
6584 INSN_ADDRESSES_NEW (insn, -1);
6585 }
6586
6587 /* Ensure minimum alignment for instructions. */
6588 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6589 INSN_ADDRESSES_NEW (insn, -1);
6590
6591 /* Output in-pool execute template insns. */
6592 for (c = pool->execute; c; c = c->next)
6593 {
6594 insn = emit_label_after (c->label, insn);
6595 INSN_ADDRESSES_NEW (insn, -1);
6596
6597 insn = emit_insn_after (s390_execute_target (c->value), insn);
6598 INSN_ADDRESSES_NEW (insn, -1);
6599 }
6600
6601 /* Switch back to previous section. */
6602 if (TARGET_CPU_ZARCH)
6603 {
6604 insn = emit_insn_after (gen_pool_section_end (), insn);
6605 INSN_ADDRESSES_NEW (insn, -1);
6606 }
6607
6608 insn = emit_barrier_after (insn);
6609 INSN_ADDRESSES_NEW (insn, -1);
6610
6611 /* Remove placeholder insn. */
6612 remove_insn (pool->pool_insn);
6613 }
6614
6615 /* Free all memory used by POOL. */
6616
6617 static void
6618 s390_free_pool (struct constant_pool *pool)
6619 {
6620 struct constant *c, *next;
6621 int i;
6622
6623 for (i = 0; i < NR_C_MODES; i++)
6624 for (c = pool->constants[i]; c; c = next)
6625 {
6626 next = c->next;
6627 free (c);
6628 }
6629
6630 for (c = pool->execute; c; c = next)
6631 {
6632 next = c->next;
6633 free (c);
6634 }
6635
6636 BITMAP_FREE (pool->insns);
6637 free (pool);
6638 }
6639
6640
6641 /* Collect main literal pool. Return NULL on overflow. */
6642
6643 static struct constant_pool *
6644 s390_mainpool_start (void)
6645 {
6646 struct constant_pool *pool;
6647 rtx insn;
6648
6649 pool = s390_alloc_pool ();
6650
6651 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6652 {
6653 if (NONJUMP_INSN_P (insn)
6654 && GET_CODE (PATTERN (insn)) == SET
6655 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6656 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6657 {
6658 gcc_assert (!pool->pool_insn);
6659 pool->pool_insn = insn;
6660 }
6661
6662 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6663 {
6664 s390_add_execute (pool, insn);
6665 }
6666 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6667 {
6668 rtx pool_ref = NULL_RTX;
6669 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6670 if (pool_ref)
6671 {
6672 rtx constant = get_pool_constant (pool_ref);
6673 enum machine_mode mode = get_pool_mode (pool_ref);
6674 s390_add_constant (pool, constant, mode);
6675 }
6676 }
6677
6678 /* If hot/cold partitioning is enabled we have to make sure that
6679 the literal pool is emitted in the same section where the
6680 initialization of the literal pool base pointer takes place.
6681 emit_pool_after is only used in the non-overflow case on non
6682 Z cpus where we can emit the literal pool at the end of the
6683 function body within the text section. */
6684 if (NOTE_P (insn)
6685 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6686 && !pool->emit_pool_after)
6687 pool->emit_pool_after = PREV_INSN (insn);
6688 }
6689
6690 gcc_assert (pool->pool_insn || pool->size == 0);
6691
6692 if (pool->size >= 4096)
6693 {
6694 /* We're going to chunkify the pool, so remove the main
6695 pool placeholder insn. */
6696 remove_insn (pool->pool_insn);
6697
6698 s390_free_pool (pool);
6699 pool = NULL;
6700 }
6701
6702 /* If the functions ends with the section where the literal pool
6703 should be emitted set the marker to its end. */
6704 if (pool && !pool->emit_pool_after)
6705 pool->emit_pool_after = get_last_insn ();
6706
6707 return pool;
6708 }
6709
6710 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6711 Modify the current function to output the pool constants as well as
6712 the pool register setup instruction. */
6713
6714 static void
6715 s390_mainpool_finish (struct constant_pool *pool)
6716 {
6717 rtx base_reg = cfun->machine->base_reg;
6718 rtx insn;
6719
6720 /* If the pool is empty, we're done. */
6721 if (pool->size == 0)
6722 {
6723 /* We don't actually need a base register after all. */
6724 cfun->machine->base_reg = NULL_RTX;
6725
6726 if (pool->pool_insn)
6727 remove_insn (pool->pool_insn);
6728 s390_free_pool (pool);
6729 return;
6730 }
6731
6732 /* We need correct insn addresses. */
6733 shorten_branches (get_insns ());
6734
6735 /* On zSeries, we use a LARL to load the pool register. The pool is
6736 located in the .rodata section, so we emit it after the function. */
6737 if (TARGET_CPU_ZARCH)
6738 {
6739 insn = gen_main_base_64 (base_reg, pool->label);
6740 insn = emit_insn_after (insn, pool->pool_insn);
6741 INSN_ADDRESSES_NEW (insn, -1);
6742 remove_insn (pool->pool_insn);
6743
6744 insn = get_last_insn ();
6745 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6746 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6747
6748 s390_dump_pool (pool, 0);
6749 }
6750
6751 /* On S/390, if the total size of the function's code plus literal pool
6752 does not exceed 4096 bytes, we use BASR to set up a function base
6753 pointer, and emit the literal pool at the end of the function. */
6754 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6755 + pool->size + 8 /* alignment slop */ < 4096)
6756 {
6757 insn = gen_main_base_31_small (base_reg, pool->label);
6758 insn = emit_insn_after (insn, pool->pool_insn);
6759 INSN_ADDRESSES_NEW (insn, -1);
6760 remove_insn (pool->pool_insn);
6761
6762 insn = emit_label_after (pool->label, insn);
6763 INSN_ADDRESSES_NEW (insn, -1);
6764
6765 /* emit_pool_after will be set by s390_mainpool_start to the
6766 last insn of the section where the literal pool should be
6767 emitted. */
6768 insn = pool->emit_pool_after;
6769
6770 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6771 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6772
6773 s390_dump_pool (pool, 1);
6774 }
6775
6776 /* Otherwise, we emit an inline literal pool and use BASR to branch
6777 over it, setting up the pool register at the same time. */
6778 else
6779 {
6780 rtx pool_end = gen_label_rtx ();
6781
6782 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6783 insn = emit_jump_insn_after (insn, pool->pool_insn);
6784 JUMP_LABEL (insn) = pool_end;
6785 INSN_ADDRESSES_NEW (insn, -1);
6786 remove_insn (pool->pool_insn);
6787
6788 insn = emit_label_after (pool->label, insn);
6789 INSN_ADDRESSES_NEW (insn, -1);
6790
6791 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6792 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6793
6794 insn = emit_label_after (pool_end, pool->pool_insn);
6795 INSN_ADDRESSES_NEW (insn, -1);
6796
6797 s390_dump_pool (pool, 1);
6798 }
6799
6800
6801 /* Replace all literal pool references. */
6802
6803 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6804 {
6805 if (INSN_P (insn))
6806 replace_ltrel_base (&PATTERN (insn));
6807
6808 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6809 {
6810 rtx addr, pool_ref = NULL_RTX;
6811 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6812 if (pool_ref)
6813 {
6814 if (s390_execute_label (insn))
6815 addr = s390_find_execute (pool, insn);
6816 else
6817 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6818 get_pool_mode (pool_ref));
6819
6820 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6821 INSN_CODE (insn) = -1;
6822 }
6823 }
6824 }
6825
6826
6827 /* Free the pool. */
6828 s390_free_pool (pool);
6829 }
6830
6831 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6832 We have decided we cannot use this pool, so revert all changes
6833 to the current function that were done by s390_mainpool_start. */
6834 static void
6835 s390_mainpool_cancel (struct constant_pool *pool)
6836 {
6837 /* We didn't actually change the instruction stream, so simply
6838 free the pool memory. */
6839 s390_free_pool (pool);
6840 }
6841
6842
6843 /* Chunkify the literal pool. */
6844
6845 #define S390_POOL_CHUNK_MIN 0xc00
6846 #define S390_POOL_CHUNK_MAX 0xe00
6847
6848 static struct constant_pool *
6849 s390_chunkify_start (void)
6850 {
6851 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6852 int extra_size = 0;
6853 bitmap far_labels;
6854 rtx pending_ltrel = NULL_RTX;
6855 rtx insn;
6856
6857 rtx (*gen_reload_base) (rtx, rtx) =
6858 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6859
6860
6861 /* We need correct insn addresses. */
6862
6863 shorten_branches (get_insns ());
6864
6865 /* Scan all insns and move literals to pool chunks. */
6866
6867 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6868 {
6869 bool section_switch_p = false;
6870
6871 /* Check for pending LTREL_BASE. */
6872 if (INSN_P (insn))
6873 {
6874 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6875 if (ltrel_base)
6876 {
6877 gcc_assert (ltrel_base == pending_ltrel);
6878 pending_ltrel = NULL_RTX;
6879 }
6880 }
6881
6882 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6883 {
6884 if (!curr_pool)
6885 curr_pool = s390_start_pool (&pool_list, insn);
6886
6887 s390_add_execute (curr_pool, insn);
6888 s390_add_pool_insn (curr_pool, insn);
6889 }
6890 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6891 {
6892 rtx pool_ref = NULL_RTX;
6893 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6894 if (pool_ref)
6895 {
6896 rtx constant = get_pool_constant (pool_ref);
6897 enum machine_mode mode = get_pool_mode (pool_ref);
6898
6899 if (!curr_pool)
6900 curr_pool = s390_start_pool (&pool_list, insn);
6901
6902 s390_add_constant (curr_pool, constant, mode);
6903 s390_add_pool_insn (curr_pool, insn);
6904
6905 /* Don't split the pool chunk between a LTREL_OFFSET load
6906 and the corresponding LTREL_BASE. */
6907 if (GET_CODE (constant) == CONST
6908 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6909 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6910 {
6911 gcc_assert (!pending_ltrel);
6912 pending_ltrel = pool_ref;
6913 }
6914 }
6915 }
6916
6917 if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn))
6918 {
6919 if (curr_pool)
6920 s390_add_pool_insn (curr_pool, insn);
6921 /* An LTREL_BASE must follow within the same basic block. */
6922 gcc_assert (!pending_ltrel);
6923 }
6924
6925 if (NOTE_P (insn))
6926 switch (NOTE_KIND (insn))
6927 {
6928 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6929 section_switch_p = true;
6930 break;
6931 case NOTE_INSN_VAR_LOCATION:
6932 case NOTE_INSN_CALL_ARG_LOCATION:
6933 continue;
6934 default:
6935 break;
6936 }
6937
6938 if (!curr_pool
6939 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6940 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6941 continue;
6942
6943 if (TARGET_CPU_ZARCH)
6944 {
6945 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6946 continue;
6947
6948 s390_end_pool (curr_pool, NULL_RTX);
6949 curr_pool = NULL;
6950 }
6951 else
6952 {
6953 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6954 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6955 + extra_size;
6956
6957 /* We will later have to insert base register reload insns.
6958 Those will have an effect on code size, which we need to
6959 consider here. This calculation makes rather pessimistic
6960 worst-case assumptions. */
6961 if (LABEL_P (insn))
6962 extra_size += 6;
6963
6964 if (chunk_size < S390_POOL_CHUNK_MIN
6965 && curr_pool->size < S390_POOL_CHUNK_MIN
6966 && !section_switch_p)
6967 continue;
6968
6969 /* Pool chunks can only be inserted after BARRIERs ... */
6970 if (BARRIER_P (insn))
6971 {
6972 s390_end_pool (curr_pool, insn);
6973 curr_pool = NULL;
6974 extra_size = 0;
6975 }
6976
6977 /* ... so if we don't find one in time, create one. */
6978 else if (chunk_size > S390_POOL_CHUNK_MAX
6979 || curr_pool->size > S390_POOL_CHUNK_MAX
6980 || section_switch_p)
6981 {
6982 rtx label, jump, barrier, next, prev;
6983
6984 if (!section_switch_p)
6985 {
6986 /* We can insert the barrier only after a 'real' insn. */
6987 if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn))
6988 continue;
6989 if (get_attr_length (insn) == 0)
6990 continue;
6991 /* Don't separate LTREL_BASE from the corresponding
6992 LTREL_OFFSET load. */
6993 if (pending_ltrel)
6994 continue;
6995 next = insn;
6996 do
6997 {
6998 insn = next;
6999 next = NEXT_INSN (insn);
7000 }
7001 while (next
7002 && NOTE_P (next)
7003 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
7004 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
7005 }
7006 else
7007 {
7008 gcc_assert (!pending_ltrel);
7009
7010 /* The old pool has to end before the section switch
7011 note in order to make it part of the current
7012 section. */
7013 insn = PREV_INSN (insn);
7014 }
7015
7016 label = gen_label_rtx ();
7017 prev = insn;
7018 if (prev && NOTE_P (prev))
7019 prev = prev_nonnote_insn (prev);
7020 if (prev)
7021 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
7022 INSN_LOCATION (prev));
7023 else
7024 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
7025 barrier = emit_barrier_after (jump);
7026 insn = emit_label_after (label, barrier);
7027 JUMP_LABEL (jump) = label;
7028 LABEL_NUSES (label) = 1;
7029
7030 INSN_ADDRESSES_NEW (jump, -1);
7031 INSN_ADDRESSES_NEW (barrier, -1);
7032 INSN_ADDRESSES_NEW (insn, -1);
7033
7034 s390_end_pool (curr_pool, barrier);
7035 curr_pool = NULL;
7036 extra_size = 0;
7037 }
7038 }
7039 }
7040
7041 if (curr_pool)
7042 s390_end_pool (curr_pool, NULL_RTX);
7043 gcc_assert (!pending_ltrel);
7044
7045 /* Find all labels that are branched into
7046 from an insn belonging to a different chunk. */
7047
7048 far_labels = BITMAP_ALLOC (NULL);
7049
7050 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7051 {
7052 /* Labels marked with LABEL_PRESERVE_P can be target
7053 of non-local jumps, so we have to mark them.
7054 The same holds for named labels.
7055
7056 Don't do that, however, if it is the label before
7057 a jump table. */
7058
7059 if (LABEL_P (insn)
7060 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
7061 {
7062 rtx vec_insn = NEXT_INSN (insn);
7063 if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn))
7064 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
7065 }
7066
7067 /* If we have a direct jump (conditional or unconditional)
7068 or a casesi jump, check all potential targets. */
7069 else if (JUMP_P (insn))
7070 {
7071 rtx pat = PATTERN (insn);
7072 rtx table;
7073
7074 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
7075 pat = XVECEXP (pat, 0, 0);
7076
7077 if (GET_CODE (pat) == SET)
7078 {
7079 rtx label = JUMP_LABEL (insn);
7080 if (label)
7081 {
7082 if (s390_find_pool (pool_list, label)
7083 != s390_find_pool (pool_list, insn))
7084 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7085 }
7086 }
7087 else if (tablejump_p (insn, NULL, &table))
7088 {
7089 rtx vec_pat = PATTERN (table);
7090 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7091
7092 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7093 {
7094 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
7095
7096 if (s390_find_pool (pool_list, label)
7097 != s390_find_pool (pool_list, insn))
7098 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7099 }
7100 }
7101 }
7102 }
7103
7104 /* Insert base register reload insns before every pool. */
7105
7106 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7107 {
7108 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7109 curr_pool->label);
7110 rtx insn = curr_pool->first_insn;
7111 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7112 }
7113
7114 /* Insert base register reload insns at every far label. */
7115
7116 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7117 if (LABEL_P (insn)
7118 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7119 {
7120 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7121 if (pool)
7122 {
7123 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7124 pool->label);
7125 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
7126 }
7127 }
7128
7129
7130 BITMAP_FREE (far_labels);
7131
7132
7133 /* Recompute insn addresses. */
7134
7135 init_insn_lengths ();
7136 shorten_branches (get_insns ());
7137
7138 return pool_list;
7139 }
7140
7141 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7142 After we have decided to use this list, finish implementing
7143 all changes to the current function as required. */
7144
7145 static void
7146 s390_chunkify_finish (struct constant_pool *pool_list)
7147 {
7148 struct constant_pool *curr_pool = NULL;
7149 rtx insn;
7150
7151
7152 /* Replace all literal pool references. */
7153
7154 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7155 {
7156 if (INSN_P (insn))
7157 replace_ltrel_base (&PATTERN (insn));
7158
7159 curr_pool = s390_find_pool (pool_list, insn);
7160 if (!curr_pool)
7161 continue;
7162
7163 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
7164 {
7165 rtx addr, pool_ref = NULL_RTX;
7166 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7167 if (pool_ref)
7168 {
7169 if (s390_execute_label (insn))
7170 addr = s390_find_execute (curr_pool, insn);
7171 else
7172 addr = s390_find_constant (curr_pool,
7173 get_pool_constant (pool_ref),
7174 get_pool_mode (pool_ref));
7175
7176 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7177 INSN_CODE (insn) = -1;
7178 }
7179 }
7180 }
7181
7182 /* Dump out all literal pools. */
7183
7184 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7185 s390_dump_pool (curr_pool, 0);
7186
7187 /* Free pool list. */
7188
7189 while (pool_list)
7190 {
7191 struct constant_pool *next = pool_list->next;
7192 s390_free_pool (pool_list);
7193 pool_list = next;
7194 }
7195 }
7196
7197 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7198 We have decided we cannot use this list, so revert all changes
7199 to the current function that were done by s390_chunkify_start. */
7200
7201 static void
7202 s390_chunkify_cancel (struct constant_pool *pool_list)
7203 {
7204 struct constant_pool *curr_pool = NULL;
7205 rtx insn;
7206
7207 /* Remove all pool placeholder insns. */
7208
7209 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7210 {
7211 /* Did we insert an extra barrier? Remove it. */
7212 rtx barrier = PREV_INSN (curr_pool->pool_insn);
7213 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
7214 rtx label = NEXT_INSN (curr_pool->pool_insn);
7215
7216 if (jump && JUMP_P (jump)
7217 && barrier && BARRIER_P (barrier)
7218 && label && LABEL_P (label)
7219 && GET_CODE (PATTERN (jump)) == SET
7220 && SET_DEST (PATTERN (jump)) == pc_rtx
7221 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7222 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7223 {
7224 remove_insn (jump);
7225 remove_insn (barrier);
7226 remove_insn (label);
7227 }
7228
7229 remove_insn (curr_pool->pool_insn);
7230 }
7231
7232 /* Remove all base register reload insns. */
7233
7234 for (insn = get_insns (); insn; )
7235 {
7236 rtx next_insn = NEXT_INSN (insn);
7237
7238 if (NONJUMP_INSN_P (insn)
7239 && GET_CODE (PATTERN (insn)) == SET
7240 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7241 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7242 remove_insn (insn);
7243
7244 insn = next_insn;
7245 }
7246
7247 /* Free pool list. */
7248
7249 while (pool_list)
7250 {
7251 struct constant_pool *next = pool_list->next;
7252 s390_free_pool (pool_list);
7253 pool_list = next;
7254 }
7255 }
7256
7257 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7258
7259 void
7260 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
7261 {
7262 REAL_VALUE_TYPE r;
7263
7264 switch (GET_MODE_CLASS (mode))
7265 {
7266 case MODE_FLOAT:
7267 case MODE_DECIMAL_FLOAT:
7268 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7269
7270 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7271 assemble_real (r, mode, align);
7272 break;
7273
7274 case MODE_INT:
7275 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7276 mark_symbol_refs_as_used (exp);
7277 break;
7278
7279 default:
7280 gcc_unreachable ();
7281 }
7282 }
7283
7284
7285 /* Return an RTL expression representing the value of the return address
7286 for the frame COUNT steps up from the current frame. FRAME is the
7287 frame pointer of that frame. */
7288
7289 rtx
7290 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7291 {
7292 int offset;
7293 rtx addr;
7294
7295 /* Without backchain, we fail for all but the current frame. */
7296
7297 if (!TARGET_BACKCHAIN && count > 0)
7298 return NULL_RTX;
7299
7300 /* For the current frame, we need to make sure the initial
7301 value of RETURN_REGNUM is actually saved. */
7302
7303 if (count == 0)
7304 {
7305 /* On non-z architectures branch splitting could overwrite r14. */
7306 if (TARGET_CPU_ZARCH)
7307 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7308 else
7309 {
7310 cfun_frame_layout.save_return_addr_p = true;
7311 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7312 }
7313 }
7314
7315 if (TARGET_PACKED_STACK)
7316 offset = -2 * UNITS_PER_LONG;
7317 else
7318 offset = RETURN_REGNUM * UNITS_PER_LONG;
7319
7320 addr = plus_constant (Pmode, frame, offset);
7321 addr = memory_address (Pmode, addr);
7322 return gen_rtx_MEM (Pmode, addr);
7323 }
7324
7325 /* Return an RTL expression representing the back chain stored in
7326 the current stack frame. */
7327
7328 rtx
7329 s390_back_chain_rtx (void)
7330 {
7331 rtx chain;
7332
7333 gcc_assert (TARGET_BACKCHAIN);
7334
7335 if (TARGET_PACKED_STACK)
7336 chain = plus_constant (Pmode, stack_pointer_rtx,
7337 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7338 else
7339 chain = stack_pointer_rtx;
7340
7341 chain = gen_rtx_MEM (Pmode, chain);
7342 return chain;
7343 }
7344
7345 /* Find first call clobbered register unused in a function.
7346 This could be used as base register in a leaf function
7347 or for holding the return address before epilogue. */
7348
7349 static int
7350 find_unused_clobbered_reg (void)
7351 {
7352 int i;
7353 for (i = 0; i < 6; i++)
7354 if (!df_regs_ever_live_p (i))
7355 return i;
7356 return 0;
7357 }
7358
7359
7360 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7361 clobbered hard regs in SETREG. */
7362
7363 static void
7364 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7365 {
7366 int *regs_ever_clobbered = (int *)data;
7367 unsigned int i, regno;
7368 enum machine_mode mode = GET_MODE (setreg);
7369
7370 if (GET_CODE (setreg) == SUBREG)
7371 {
7372 rtx inner = SUBREG_REG (setreg);
7373 if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
7374 return;
7375 regno = subreg_regno (setreg);
7376 }
7377 else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg))
7378 regno = REGNO (setreg);
7379 else
7380 return;
7381
7382 for (i = regno;
7383 i < regno + HARD_REGNO_NREGS (regno, mode);
7384 i++)
7385 regs_ever_clobbered[i] = 1;
7386 }
7387
7388 /* Walks through all basic blocks of the current function looking
7389 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7390 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7391 each of those regs. */
7392
7393 static void
7394 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7395 {
7396 basic_block cur_bb;
7397 rtx cur_insn;
7398 unsigned int i;
7399
7400 memset (regs_ever_clobbered, 0, 32 * sizeof (int));
7401
7402 /* For non-leaf functions we have to consider all call clobbered regs to be
7403 clobbered. */
7404 if (!crtl->is_leaf)
7405 {
7406 for (i = 0; i < 32; i++)
7407 regs_ever_clobbered[i] = call_really_used_regs[i];
7408 }
7409
7410 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7411 this work is done by liveness analysis (mark_regs_live_at_end).
7412 Special care is needed for functions containing landing pads. Landing pads
7413 may use the eh registers, but the code which sets these registers is not
7414 contained in that function. Hence s390_regs_ever_clobbered is not able to
7415 deal with this automatically. */
7416 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7417 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7418 if (crtl->calls_eh_return
7419 || (cfun->machine->has_landing_pad_p
7420 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7421 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7422
7423 /* For nonlocal gotos all call-saved registers have to be saved.
7424 This flag is also set for the unwinding code in libgcc.
7425 See expand_builtin_unwind_init. For regs_ever_live this is done by
7426 reload. */
7427 if (cfun->has_nonlocal_label)
7428 for (i = 0; i < 32; i++)
7429 if (!call_really_used_regs[i])
7430 regs_ever_clobbered[i] = 1;
7431
7432 FOR_EACH_BB (cur_bb)
7433 {
7434 FOR_BB_INSNS (cur_bb, cur_insn)
7435 {
7436 if (INSN_P (cur_insn))
7437 note_stores (PATTERN (cur_insn),
7438 s390_reg_clobbered_rtx,
7439 regs_ever_clobbered);
7440 }
7441 }
7442 }
7443
7444 /* Determine the frame area which actually has to be accessed
7445 in the function epilogue. The values are stored at the
7446 given pointers AREA_BOTTOM (address of the lowest used stack
7447 address) and AREA_TOP (address of the first item which does
7448 not belong to the stack frame). */
7449
7450 static void
7451 s390_frame_area (int *area_bottom, int *area_top)
7452 {
7453 int b, t;
7454 int i;
7455
7456 b = INT_MAX;
7457 t = INT_MIN;
7458
7459 if (cfun_frame_layout.first_restore_gpr != -1)
7460 {
7461 b = (cfun_frame_layout.gprs_offset
7462 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7463 t = b + (cfun_frame_layout.last_restore_gpr
7464 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7465 }
7466
7467 if (TARGET_64BIT && cfun_save_high_fprs_p)
7468 {
7469 b = MIN (b, cfun_frame_layout.f8_offset);
7470 t = MAX (t, (cfun_frame_layout.f8_offset
7471 + cfun_frame_layout.high_fprs * 8));
7472 }
7473
7474 if (!TARGET_64BIT)
7475 for (i = 2; i < 4; i++)
7476 if (cfun_fpr_bit_p (i))
7477 {
7478 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7479 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7480 }
7481
7482 *area_bottom = b;
7483 *area_top = t;
7484 }
7485
7486 /* Fill cfun->machine with info about register usage of current function.
7487 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7488
7489 static void
7490 s390_register_info (int clobbered_regs[])
7491 {
7492 int i, j;
7493
7494 /* Find first and last gpr to be saved. We trust regs_ever_live
7495 data, except that we don't save and restore global registers.
7496
7497 Also, all registers with special meaning to the compiler need
7498 to be handled extra. */
7499
7500 s390_regs_ever_clobbered (clobbered_regs);
7501
7502 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7503 if (!epilogue_completed)
7504 {
7505 cfun_frame_layout.fpr_bitmap = 0;
7506 cfun_frame_layout.high_fprs = 0;
7507 if (TARGET_64BIT)
7508 for (i = 24; i < 32; i++)
7509 /* During reload we have to use the df_regs_ever_live infos
7510 since reload is marking FPRs used as spill slots there as
7511 live before actually making the code changes. Without
7512 this we fail during elimination offset verification. */
7513 if ((clobbered_regs[i]
7514 || (df_regs_ever_live_p (i)
7515 && (lra_in_progress
7516 || reload_in_progress
7517 || crtl->saves_all_registers)))
7518 && !global_regs[i])
7519 {
7520 cfun_set_fpr_bit (i - 16);
7521 cfun_frame_layout.high_fprs++;
7522 }
7523 }
7524
7525 for (i = 0; i < 16; i++)
7526 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7527
7528 if (frame_pointer_needed)
7529 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7530
7531 if (flag_pic)
7532 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7533 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7534
7535 clobbered_regs[BASE_REGNUM]
7536 |= (cfun->machine->base_reg
7537 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7538
7539 clobbered_regs[RETURN_REGNUM]
7540 |= (!crtl->is_leaf
7541 || TARGET_TPF_PROFILING
7542 || cfun->machine->split_branches_pending_p
7543 || cfun_frame_layout.save_return_addr_p
7544 || crtl->calls_eh_return
7545 || cfun->stdarg);
7546
7547 clobbered_regs[STACK_POINTER_REGNUM]
7548 |= (!crtl->is_leaf
7549 || TARGET_TPF_PROFILING
7550 || cfun_save_high_fprs_p
7551 || get_frame_size () > 0
7552 || cfun->calls_alloca
7553 || cfun->stdarg);
7554
7555 for (i = 6; i < 16; i++)
7556 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7557 break;
7558 for (j = 15; j > i; j--)
7559 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7560 break;
7561
7562 if (i == 16)
7563 {
7564 /* Nothing to save/restore. */
7565 cfun_frame_layout.first_save_gpr_slot = -1;
7566 cfun_frame_layout.last_save_gpr_slot = -1;
7567 cfun_frame_layout.first_save_gpr = -1;
7568 cfun_frame_layout.first_restore_gpr = -1;
7569 cfun_frame_layout.last_save_gpr = -1;
7570 cfun_frame_layout.last_restore_gpr = -1;
7571 }
7572 else
7573 {
7574 /* Save slots for gprs from i to j. */
7575 cfun_frame_layout.first_save_gpr_slot = i;
7576 cfun_frame_layout.last_save_gpr_slot = j;
7577
7578 for (i = cfun_frame_layout.first_save_gpr_slot;
7579 i < cfun_frame_layout.last_save_gpr_slot + 1;
7580 i++)
7581 if (clobbered_regs[i])
7582 break;
7583
7584 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7585 if (clobbered_regs[j])
7586 break;
7587
7588 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7589 {
7590 /* Nothing to save/restore. */
7591 cfun_frame_layout.first_save_gpr = -1;
7592 cfun_frame_layout.first_restore_gpr = -1;
7593 cfun_frame_layout.last_save_gpr = -1;
7594 cfun_frame_layout.last_restore_gpr = -1;
7595 }
7596 else
7597 {
7598 /* Save / Restore from gpr i to j. */
7599 cfun_frame_layout.first_save_gpr = i;
7600 cfun_frame_layout.first_restore_gpr = i;
7601 cfun_frame_layout.last_save_gpr = j;
7602 cfun_frame_layout.last_restore_gpr = j;
7603 }
7604 }
7605
7606 if (cfun->stdarg)
7607 {
7608 /* Varargs functions need to save gprs 2 to 6. */
7609 if (cfun->va_list_gpr_size
7610 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7611 {
7612 int min_gpr = crtl->args.info.gprs;
7613 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7614 if (max_gpr > GP_ARG_NUM_REG)
7615 max_gpr = GP_ARG_NUM_REG;
7616
7617 if (cfun_frame_layout.first_save_gpr == -1
7618 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7619 {
7620 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7621 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7622 }
7623
7624 if (cfun_frame_layout.last_save_gpr == -1
7625 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7626 {
7627 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7628 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7629 }
7630 }
7631
7632 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7633 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7634 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7635 {
7636 int min_fpr = crtl->args.info.fprs;
7637 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7638 if (max_fpr > FP_ARG_NUM_REG)
7639 max_fpr = FP_ARG_NUM_REG;
7640
7641 /* ??? This is currently required to ensure proper location
7642 of the fpr save slots within the va_list save area. */
7643 if (TARGET_PACKED_STACK)
7644 min_fpr = 0;
7645
7646 for (i = min_fpr; i < max_fpr; i++)
7647 cfun_set_fpr_bit (i);
7648 }
7649 }
7650
7651 if (!TARGET_64BIT)
7652 for (i = 2; i < 4; i++)
7653 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7654 cfun_set_fpr_bit (i);
7655 }
7656
7657 /* Fill cfun->machine with info about frame of current function. */
7658
7659 static void
7660 s390_frame_info (void)
7661 {
7662 int i;
7663
7664 cfun_frame_layout.frame_size = get_frame_size ();
7665 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7666 fatal_error ("total size of local variables exceeds architecture limit");
7667
7668 if (!TARGET_PACKED_STACK)
7669 {
7670 cfun_frame_layout.backchain_offset = 0;
7671 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7672 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7673 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7674 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7675 * UNITS_PER_LONG);
7676 }
7677 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7678 {
7679 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7680 - UNITS_PER_LONG);
7681 cfun_frame_layout.gprs_offset
7682 = (cfun_frame_layout.backchain_offset
7683 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7684 * UNITS_PER_LONG);
7685
7686 if (TARGET_64BIT)
7687 {
7688 cfun_frame_layout.f4_offset
7689 = (cfun_frame_layout.gprs_offset
7690 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7691
7692 cfun_frame_layout.f0_offset
7693 = (cfun_frame_layout.f4_offset
7694 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7695 }
7696 else
7697 {
7698 /* On 31 bit we have to care about alignment of the
7699 floating point regs to provide fastest access. */
7700 cfun_frame_layout.f0_offset
7701 = ((cfun_frame_layout.gprs_offset
7702 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7703 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7704
7705 cfun_frame_layout.f4_offset
7706 = (cfun_frame_layout.f0_offset
7707 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7708 }
7709 }
7710 else /* no backchain */
7711 {
7712 cfun_frame_layout.f4_offset
7713 = (STACK_POINTER_OFFSET
7714 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7715
7716 cfun_frame_layout.f0_offset
7717 = (cfun_frame_layout.f4_offset
7718 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7719
7720 cfun_frame_layout.gprs_offset
7721 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7722 }
7723
7724 if (crtl->is_leaf
7725 && !TARGET_TPF_PROFILING
7726 && cfun_frame_layout.frame_size == 0
7727 && !cfun_save_high_fprs_p
7728 && !cfun->calls_alloca
7729 && !cfun->stdarg)
7730 return;
7731
7732 if (!TARGET_PACKED_STACK)
7733 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7734 + crtl->outgoing_args_size
7735 + cfun_frame_layout.high_fprs * 8);
7736 else
7737 {
7738 if (TARGET_BACKCHAIN)
7739 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7740
7741 /* No alignment trouble here because f8-f15 are only saved under
7742 64 bit. */
7743 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7744 cfun_frame_layout.f4_offset),
7745 cfun_frame_layout.gprs_offset)
7746 - cfun_frame_layout.high_fprs * 8);
7747
7748 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7749
7750 for (i = 0; i < 8; i++)
7751 if (cfun_fpr_bit_p (i))
7752 cfun_frame_layout.frame_size += 8;
7753
7754 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7755
7756 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7757 the frame size to sustain 8 byte alignment of stack frames. */
7758 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7759 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7760 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7761
7762 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7763 }
7764 }
7765
7766 /* Generate frame layout. Fills in register and frame data for the current
7767 function in cfun->machine. This routine can be called multiple times;
7768 it will re-do the complete frame layout every time. */
7769
7770 static void
7771 s390_init_frame_layout (void)
7772 {
7773 HOST_WIDE_INT frame_size;
7774 int base_used;
7775 int clobbered_regs[32];
7776
7777 /* On S/390 machines, we may need to perform branch splitting, which
7778 will require both base and return address register. We have no
7779 choice but to assume we're going to need them until right at the
7780 end of the machine dependent reorg phase. */
7781 if (!TARGET_CPU_ZARCH)
7782 cfun->machine->split_branches_pending_p = true;
7783
7784 do
7785 {
7786 frame_size = cfun_frame_layout.frame_size;
7787
7788 /* Try to predict whether we'll need the base register. */
7789 base_used = cfun->machine->split_branches_pending_p
7790 || crtl->uses_const_pool
7791 || (!DISP_IN_RANGE (frame_size)
7792 && !CONST_OK_FOR_K (frame_size));
7793
7794 /* Decide which register to use as literal pool base. In small
7795 leaf functions, try to use an unused call-clobbered register
7796 as base register to avoid save/restore overhead. */
7797 if (!base_used)
7798 cfun->machine->base_reg = NULL_RTX;
7799 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7800 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7801 else
7802 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7803
7804 s390_register_info (clobbered_regs);
7805 s390_frame_info ();
7806 }
7807 while (frame_size != cfun_frame_layout.frame_size);
7808 }
7809
7810 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
7811 the TX is nonescaping. A transaction is considered escaping if
7812 there is at least one path from tbegin returning CC0 to the
7813 function exit block without an tend.
7814
7815 The check so far has some limitations:
7816 - only single tbegin/tend BBs are supported
7817 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7818 - when CC is copied to a GPR and the CC0 check is done with the GPR
7819 this is not supported
7820 */
7821
7822 static void
7823 s390_optimize_nonescaping_tx (void)
7824 {
7825 const unsigned int CC0 = 1 << 3;
7826 basic_block tbegin_bb = NULL;
7827 basic_block tend_bb = NULL;
7828 basic_block bb;
7829 rtx insn;
7830 bool result = true;
7831 int bb_index;
7832 rtx tbegin_insn = NULL_RTX;
7833
7834 if (!cfun->machine->tbegin_p)
7835 return;
7836
7837 for (bb_index = 0; bb_index < n_basic_blocks; bb_index++)
7838 {
7839 bb = BASIC_BLOCK (bb_index);
7840
7841 FOR_BB_INSNS (bb, insn)
7842 {
7843 rtx ite, cc, pat, target;
7844 unsigned HOST_WIDE_INT mask;
7845
7846 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
7847 continue;
7848
7849 pat = PATTERN (insn);
7850
7851 if (GET_CODE (pat) == PARALLEL)
7852 pat = XVECEXP (pat, 0, 0);
7853
7854 if (GET_CODE (pat) != SET
7855 || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE)
7856 continue;
7857
7858 if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN)
7859 {
7860 rtx tmp;
7861
7862 tbegin_insn = insn;
7863
7864 /* Just return if the tbegin doesn't have clobbers. */
7865 if (GET_CODE (PATTERN (insn)) != PARALLEL)
7866 return;
7867
7868 if (tbegin_bb != NULL)
7869 return;
7870
7871 /* Find the next conditional jump. */
7872 for (tmp = NEXT_INSN (insn);
7873 tmp != NULL_RTX;
7874 tmp = NEXT_INSN (tmp))
7875 {
7876 if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp))
7877 return;
7878 if (!JUMP_P (tmp))
7879 continue;
7880
7881 ite = SET_SRC (PATTERN (tmp));
7882 if (GET_CODE (ite) != IF_THEN_ELSE)
7883 continue;
7884
7885 cc = XEXP (XEXP (ite, 0), 0);
7886 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
7887 || GET_MODE (cc) != CCRAWmode
7888 || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
7889 return;
7890
7891 if (bb->succs->length () != 2)
7892 return;
7893
7894 mask = INTVAL (XEXP (XEXP (ite, 0), 1));
7895 if (GET_CODE (XEXP (ite, 0)) == NE)
7896 mask ^= 0xf;
7897
7898 if (mask == CC0)
7899 target = XEXP (ite, 1);
7900 else if (mask == (CC0 ^ 0xf))
7901 target = XEXP (ite, 2);
7902 else
7903 return;
7904
7905 {
7906 edge_iterator ei;
7907 edge e1, e2;
7908
7909 ei = ei_start (bb->succs);
7910 e1 = ei_safe_edge (ei);
7911 ei_next (&ei);
7912 e2 = ei_safe_edge (ei);
7913
7914 if (e2->flags & EDGE_FALLTHRU)
7915 {
7916 e2 = e1;
7917 e1 = ei_safe_edge (ei);
7918 }
7919
7920 if (!(e1->flags & EDGE_FALLTHRU))
7921 return;
7922
7923 tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest;
7924 }
7925 if (tmp == BB_END (bb))
7926 break;
7927 }
7928 }
7929
7930 if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND)
7931 {
7932 if (tend_bb != NULL)
7933 return;
7934 tend_bb = bb;
7935 }
7936 }
7937 }
7938
7939 /* Either we successfully remove the FPR clobbers here or we are not
7940 able to do anything for this TX. Both cases don't qualify for
7941 another look. */
7942 cfun->machine->tbegin_p = false;
7943
7944 if (tbegin_bb == NULL || tend_bb == NULL)
7945 return;
7946
7947 calculate_dominance_info (CDI_POST_DOMINATORS);
7948 result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb);
7949 free_dominance_info (CDI_POST_DOMINATORS);
7950
7951 if (!result)
7952 return;
7953
7954 PATTERN (tbegin_insn) = XVECEXP (PATTERN (tbegin_insn), 0, 0);
7955 INSN_CODE (tbegin_insn) = -1;
7956 df_insn_rescan (tbegin_insn);
7957
7958 return;
7959 }
7960
7961 /* Update frame layout. Recompute actual register save data based on
7962 current info and update regs_ever_live for the special registers.
7963 May be called multiple times, but may never cause *more* registers
7964 to be saved than s390_init_frame_layout allocated room for. */
7965
7966 static void
7967 s390_update_frame_layout (void)
7968 {
7969 int clobbered_regs[32];
7970
7971 s390_register_info (clobbered_regs);
7972
7973 df_set_regs_ever_live (BASE_REGNUM,
7974 clobbered_regs[BASE_REGNUM] ? true : false);
7975 df_set_regs_ever_live (RETURN_REGNUM,
7976 clobbered_regs[RETURN_REGNUM] ? true : false);
7977 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7978 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7979
7980 if (cfun->machine->base_reg)
7981 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7982 }
7983
7984 /* Return true if it is legal to put a value with MODE into REGNO. */
7985
7986 bool
7987 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7988 {
7989 switch (REGNO_REG_CLASS (regno))
7990 {
7991 case FP_REGS:
7992 if (REGNO_PAIR_OK (regno, mode))
7993 {
7994 if (mode == SImode || mode == DImode)
7995 return true;
7996
7997 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7998 return true;
7999 }
8000 break;
8001 case ADDR_REGS:
8002 if (FRAME_REGNO_P (regno) && mode == Pmode)
8003 return true;
8004
8005 /* fallthrough */
8006 case GENERAL_REGS:
8007 if (REGNO_PAIR_OK (regno, mode))
8008 {
8009 if (TARGET_ZARCH
8010 || (mode != TFmode && mode != TCmode && mode != TDmode))
8011 return true;
8012 }
8013 break;
8014 case CC_REGS:
8015 if (GET_MODE_CLASS (mode) == MODE_CC)
8016 return true;
8017 break;
8018 case ACCESS_REGS:
8019 if (REGNO_PAIR_OK (regno, mode))
8020 {
8021 if (mode == SImode || mode == Pmode)
8022 return true;
8023 }
8024 break;
8025 default:
8026 return false;
8027 }
8028
8029 return false;
8030 }
8031
8032 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8033
8034 bool
8035 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
8036 {
8037 /* Once we've decided upon a register to use as base register, it must
8038 no longer be used for any other purpose. */
8039 if (cfun->machine->base_reg)
8040 if (REGNO (cfun->machine->base_reg) == old_reg
8041 || REGNO (cfun->machine->base_reg) == new_reg)
8042 return false;
8043
8044 return true;
8045 }
8046
8047 /* Maximum number of registers to represent a value of mode MODE
8048 in a register of class RCLASS. */
8049
8050 int
8051 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
8052 {
8053 switch (rclass)
8054 {
8055 case FP_REGS:
8056 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8057 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
8058 else
8059 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
8060 case ACCESS_REGS:
8061 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
8062 default:
8063 break;
8064 }
8065 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8066 }
8067
8068 /* Return true if we use LRA instead of reload pass. */
8069 static bool
8070 s390_lra_p (void)
8071 {
8072 return s390_lra_flag;
8073 }
8074
8075 /* Return true if register FROM can be eliminated via register TO. */
8076
8077 static bool
8078 s390_can_eliminate (const int from, const int to)
8079 {
8080 /* On zSeries machines, we have not marked the base register as fixed.
8081 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8082 If a function requires the base register, we say here that this
8083 elimination cannot be performed. This will cause reload to free
8084 up the base register (as if it were fixed). On the other hand,
8085 if the current function does *not* require the base register, we
8086 say here the elimination succeeds, which in turn allows reload
8087 to allocate the base register for any other purpose. */
8088 if (from == BASE_REGNUM && to == BASE_REGNUM)
8089 {
8090 if (TARGET_CPU_ZARCH)
8091 {
8092 s390_init_frame_layout ();
8093 return cfun->machine->base_reg == NULL_RTX;
8094 }
8095
8096 return false;
8097 }
8098
8099 /* Everything else must point into the stack frame. */
8100 gcc_assert (to == STACK_POINTER_REGNUM
8101 || to == HARD_FRAME_POINTER_REGNUM);
8102
8103 gcc_assert (from == FRAME_POINTER_REGNUM
8104 || from == ARG_POINTER_REGNUM
8105 || from == RETURN_ADDRESS_POINTER_REGNUM);
8106
8107 /* Make sure we actually saved the return address. */
8108 if (from == RETURN_ADDRESS_POINTER_REGNUM)
8109 if (!crtl->calls_eh_return
8110 && !cfun->stdarg
8111 && !cfun_frame_layout.save_return_addr_p)
8112 return false;
8113
8114 return true;
8115 }
8116
8117 /* Return offset between register FROM and TO initially after prolog. */
8118
8119 HOST_WIDE_INT
8120 s390_initial_elimination_offset (int from, int to)
8121 {
8122 HOST_WIDE_INT offset;
8123 int index;
8124
8125 /* ??? Why are we called for non-eliminable pairs? */
8126 if (!s390_can_eliminate (from, to))
8127 return 0;
8128
8129 switch (from)
8130 {
8131 case FRAME_POINTER_REGNUM:
8132 offset = (get_frame_size()
8133 + STACK_POINTER_OFFSET
8134 + crtl->outgoing_args_size);
8135 break;
8136
8137 case ARG_POINTER_REGNUM:
8138 s390_init_frame_layout ();
8139 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
8140 break;
8141
8142 case RETURN_ADDRESS_POINTER_REGNUM:
8143 s390_init_frame_layout ();
8144 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
8145 gcc_assert (index >= 0);
8146 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
8147 offset += index * UNITS_PER_LONG;
8148 break;
8149
8150 case BASE_REGNUM:
8151 offset = 0;
8152 break;
8153
8154 default:
8155 gcc_unreachable ();
8156 }
8157
8158 return offset;
8159 }
8160
8161 /* Emit insn to save fpr REGNUM at offset OFFSET relative
8162 to register BASE. Return generated insn. */
8163
8164 static rtx
8165 save_fpr (rtx base, int offset, int regnum)
8166 {
8167 rtx addr;
8168 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8169
8170 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
8171 set_mem_alias_set (addr, get_varargs_alias_set ());
8172 else
8173 set_mem_alias_set (addr, get_frame_alias_set ());
8174
8175 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
8176 }
8177
8178 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
8179 to register BASE. Return generated insn. */
8180
8181 static rtx
8182 restore_fpr (rtx base, int offset, int regnum)
8183 {
8184 rtx addr;
8185 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8186 set_mem_alias_set (addr, get_frame_alias_set ());
8187
8188 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
8189 }
8190
8191 /* Return true if REGNO is a global register, but not one
8192 of the special ones that need to be saved/restored in anyway. */
8193
8194 static inline bool
8195 global_not_special_regno_p (int regno)
8196 {
8197 return (global_regs[regno]
8198 /* These registers are special and need to be
8199 restored in any case. */
8200 && !(regno == STACK_POINTER_REGNUM
8201 || regno == RETURN_REGNUM
8202 || regno == BASE_REGNUM
8203 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
8204 }
8205
8206 /* Generate insn to save registers FIRST to LAST into
8207 the register save area located at offset OFFSET
8208 relative to register BASE. */
8209
8210 static rtx
8211 save_gprs (rtx base, int offset, int first, int last)
8212 {
8213 rtx addr, insn, note;
8214 int i;
8215
8216 addr = plus_constant (Pmode, base, offset);
8217 addr = gen_rtx_MEM (Pmode, addr);
8218
8219 set_mem_alias_set (addr, get_frame_alias_set ());
8220
8221 /* Special-case single register. */
8222 if (first == last)
8223 {
8224 if (TARGET_64BIT)
8225 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
8226 else
8227 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
8228
8229 if (!global_not_special_regno_p (first))
8230 RTX_FRAME_RELATED_P (insn) = 1;
8231 return insn;
8232 }
8233
8234
8235 insn = gen_store_multiple (addr,
8236 gen_rtx_REG (Pmode, first),
8237 GEN_INT (last - first + 1));
8238
8239 if (first <= 6 && cfun->stdarg)
8240 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8241 {
8242 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
8243
8244 if (first + i <= 6)
8245 set_mem_alias_set (mem, get_varargs_alias_set ());
8246 }
8247
8248 /* We need to set the FRAME_RELATED flag on all SETs
8249 inside the store-multiple pattern.
8250
8251 However, we must not emit DWARF records for registers 2..5
8252 if they are stored for use by variable arguments ...
8253
8254 ??? Unfortunately, it is not enough to simply not the
8255 FRAME_RELATED flags for those SETs, because the first SET
8256 of the PARALLEL is always treated as if it had the flag
8257 set, even if it does not. Therefore we emit a new pattern
8258 without those registers as REG_FRAME_RELATED_EXPR note. */
8259
8260 if (first >= 6 && !global_not_special_regno_p (first))
8261 {
8262 rtx pat = PATTERN (insn);
8263
8264 for (i = 0; i < XVECLEN (pat, 0); i++)
8265 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8266 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8267 0, i)))))
8268 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8269
8270 RTX_FRAME_RELATED_P (insn) = 1;
8271 }
8272 else if (last >= 6)
8273 {
8274 int start;
8275
8276 for (start = first >= 6 ? first : 6; start <= last; start++)
8277 if (!global_not_special_regno_p (start))
8278 break;
8279
8280 if (start > last)
8281 return insn;
8282
8283 addr = plus_constant (Pmode, base,
8284 offset + (start - first) * UNITS_PER_LONG);
8285 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
8286 gen_rtx_REG (Pmode, start),
8287 GEN_INT (last - start + 1));
8288 note = PATTERN (note);
8289
8290 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8291
8292 for (i = 0; i < XVECLEN (note, 0); i++)
8293 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8294 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8295 0, i)))))
8296 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8297
8298 RTX_FRAME_RELATED_P (insn) = 1;
8299 }
8300
8301 return insn;
8302 }
8303
8304 /* Generate insn to restore registers FIRST to LAST from
8305 the register save area located at offset OFFSET
8306 relative to register BASE. */
8307
8308 static rtx
8309 restore_gprs (rtx base, int offset, int first, int last)
8310 {
8311 rtx addr, insn;
8312
8313 addr = plus_constant (Pmode, base, offset);
8314 addr = gen_rtx_MEM (Pmode, addr);
8315 set_mem_alias_set (addr, get_frame_alias_set ());
8316
8317 /* Special-case single register. */
8318 if (first == last)
8319 {
8320 if (TARGET_64BIT)
8321 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8322 else
8323 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8324
8325 return insn;
8326 }
8327
8328 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8329 addr,
8330 GEN_INT (last - first + 1));
8331 return insn;
8332 }
8333
8334 /* Return insn sequence to load the GOT register. */
8335
8336 static GTY(()) rtx got_symbol;
8337 rtx
8338 s390_load_got (void)
8339 {
8340 rtx insns;
8341
8342 /* We cannot use pic_offset_table_rtx here since we use this
8343 function also for non-pic if __tls_get_offset is called and in
8344 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8345 aren't usable. */
8346 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8347
8348 if (!got_symbol)
8349 {
8350 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8351 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8352 }
8353
8354 start_sequence ();
8355
8356 if (TARGET_CPU_ZARCH)
8357 {
8358 emit_move_insn (got_rtx, got_symbol);
8359 }
8360 else
8361 {
8362 rtx offset;
8363
8364 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
8365 UNSPEC_LTREL_OFFSET);
8366 offset = gen_rtx_CONST (Pmode, offset);
8367 offset = force_const_mem (Pmode, offset);
8368
8369 emit_move_insn (got_rtx, offset);
8370
8371 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
8372 UNSPEC_LTREL_BASE);
8373 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
8374
8375 emit_move_insn (got_rtx, offset);
8376 }
8377
8378 insns = get_insns ();
8379 end_sequence ();
8380 return insns;
8381 }
8382
8383 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8384 and the change to the stack pointer. */
8385
8386 static void
8387 s390_emit_stack_tie (void)
8388 {
8389 rtx mem = gen_frame_mem (BLKmode,
8390 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8391
8392 emit_insn (gen_stack_tie (mem));
8393 }
8394
8395 /* Expand the prologue into a bunch of separate insns. */
8396
8397 void
8398 s390_emit_prologue (void)
8399 {
8400 rtx insn, addr;
8401 rtx temp_reg;
8402 int i;
8403 int offset;
8404 int next_fpr = 0;
8405
8406 /* Try to get rid of the FPR clobbers. */
8407 s390_optimize_nonescaping_tx ();
8408
8409 /* Complete frame layout. */
8410 s390_update_frame_layout ();
8411
8412 /* Annotate all constant pool references to let the scheduler know
8413 they implicitly use the base register. */
8414
8415 push_topmost_sequence ();
8416
8417 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8418 if (INSN_P (insn))
8419 {
8420 annotate_constant_pool_refs (&PATTERN (insn));
8421 df_insn_rescan (insn);
8422 }
8423
8424 pop_topmost_sequence ();
8425
8426 /* Choose best register to use for temp use within prologue.
8427 See below for why TPF must use the register 1. */
8428
8429 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8430 && !crtl->is_leaf
8431 && !TARGET_TPF_PROFILING)
8432 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8433 else
8434 temp_reg = gen_rtx_REG (Pmode, 1);
8435
8436 /* Save call saved gprs. */
8437 if (cfun_frame_layout.first_save_gpr != -1)
8438 {
8439 insn = save_gprs (stack_pointer_rtx,
8440 cfun_frame_layout.gprs_offset +
8441 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8442 - cfun_frame_layout.first_save_gpr_slot),
8443 cfun_frame_layout.first_save_gpr,
8444 cfun_frame_layout.last_save_gpr);
8445 emit_insn (insn);
8446 }
8447
8448 /* Dummy insn to mark literal pool slot. */
8449
8450 if (cfun->machine->base_reg)
8451 emit_insn (gen_main_pool (cfun->machine->base_reg));
8452
8453 offset = cfun_frame_layout.f0_offset;
8454
8455 /* Save f0 and f2. */
8456 for (i = 0; i < 2; i++)
8457 {
8458 if (cfun_fpr_bit_p (i))
8459 {
8460 save_fpr (stack_pointer_rtx, offset, i + 16);
8461 offset += 8;
8462 }
8463 else if (!TARGET_PACKED_STACK)
8464 offset += 8;
8465 }
8466
8467 /* Save f4 and f6. */
8468 offset = cfun_frame_layout.f4_offset;
8469 for (i = 2; i < 4; i++)
8470 {
8471 if (cfun_fpr_bit_p (i))
8472 {
8473 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8474 offset += 8;
8475
8476 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8477 therefore are not frame related. */
8478 if (!call_really_used_regs[i + 16])
8479 RTX_FRAME_RELATED_P (insn) = 1;
8480 }
8481 else if (!TARGET_PACKED_STACK)
8482 offset += 8;
8483 }
8484
8485 if (TARGET_PACKED_STACK
8486 && cfun_save_high_fprs_p
8487 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8488 {
8489 offset = (cfun_frame_layout.f8_offset
8490 + (cfun_frame_layout.high_fprs - 1) * 8);
8491
8492 for (i = 15; i > 7 && offset >= 0; i--)
8493 if (cfun_fpr_bit_p (i))
8494 {
8495 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8496
8497 RTX_FRAME_RELATED_P (insn) = 1;
8498 offset -= 8;
8499 }
8500 if (offset >= cfun_frame_layout.f8_offset)
8501 next_fpr = i + 16;
8502 }
8503
8504 if (!TARGET_PACKED_STACK)
8505 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8506
8507 if (flag_stack_usage_info)
8508 current_function_static_stack_size = cfun_frame_layout.frame_size;
8509
8510 /* Decrement stack pointer. */
8511
8512 if (cfun_frame_layout.frame_size > 0)
8513 {
8514 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8515 rtx real_frame_off;
8516
8517 if (s390_stack_size)
8518 {
8519 HOST_WIDE_INT stack_guard;
8520
8521 if (s390_stack_guard)
8522 stack_guard = s390_stack_guard;
8523 else
8524 {
8525 /* If no value for stack guard is provided the smallest power of 2
8526 larger than the current frame size is chosen. */
8527 stack_guard = 1;
8528 while (stack_guard < cfun_frame_layout.frame_size)
8529 stack_guard <<= 1;
8530 }
8531
8532 if (cfun_frame_layout.frame_size >= s390_stack_size)
8533 {
8534 warning (0, "frame size of function %qs is %wd"
8535 " bytes exceeding user provided stack limit of "
8536 "%d bytes. "
8537 "An unconditional trap is added.",
8538 current_function_name(), cfun_frame_layout.frame_size,
8539 s390_stack_size);
8540 emit_insn (gen_trap ());
8541 }
8542 else
8543 {
8544 /* stack_guard has to be smaller than s390_stack_size.
8545 Otherwise we would emit an AND with zero which would
8546 not match the test under mask pattern. */
8547 if (stack_guard >= s390_stack_size)
8548 {
8549 warning (0, "frame size of function %qs is %wd"
8550 " bytes which is more than half the stack size. "
8551 "The dynamic check would not be reliable. "
8552 "No check emitted for this function.",
8553 current_function_name(),
8554 cfun_frame_layout.frame_size);
8555 }
8556 else
8557 {
8558 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8559 & ~(stack_guard - 1));
8560
8561 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8562 GEN_INT (stack_check_mask));
8563 if (TARGET_64BIT)
8564 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8565 t, const0_rtx),
8566 t, const0_rtx, const0_rtx));
8567 else
8568 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8569 t, const0_rtx),
8570 t, const0_rtx, const0_rtx));
8571 }
8572 }
8573 }
8574
8575 if (s390_warn_framesize > 0
8576 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8577 warning (0, "frame size of %qs is %wd bytes",
8578 current_function_name (), cfun_frame_layout.frame_size);
8579
8580 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8581 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8582
8583 /* Save incoming stack pointer into temp reg. */
8584 if (TARGET_BACKCHAIN || next_fpr)
8585 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8586
8587 /* Subtract frame size from stack pointer. */
8588
8589 if (DISP_IN_RANGE (INTVAL (frame_off)))
8590 {
8591 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8592 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8593 frame_off));
8594 insn = emit_insn (insn);
8595 }
8596 else
8597 {
8598 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8599 frame_off = force_const_mem (Pmode, frame_off);
8600
8601 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8602 annotate_constant_pool_refs (&PATTERN (insn));
8603 }
8604
8605 RTX_FRAME_RELATED_P (insn) = 1;
8606 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8607 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8608 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8609 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8610 real_frame_off)));
8611
8612 /* Set backchain. */
8613
8614 if (TARGET_BACKCHAIN)
8615 {
8616 if (cfun_frame_layout.backchain_offset)
8617 addr = gen_rtx_MEM (Pmode,
8618 plus_constant (Pmode, stack_pointer_rtx,
8619 cfun_frame_layout.backchain_offset));
8620 else
8621 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8622 set_mem_alias_set (addr, get_frame_alias_set ());
8623 insn = emit_insn (gen_move_insn (addr, temp_reg));
8624 }
8625
8626 /* If we support non-call exceptions (e.g. for Java),
8627 we need to make sure the backchain pointer is set up
8628 before any possibly trapping memory access. */
8629 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8630 {
8631 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8632 emit_clobber (addr);
8633 }
8634 }
8635
8636 /* Save fprs 8 - 15 (64 bit ABI). */
8637
8638 if (cfun_save_high_fprs_p && next_fpr)
8639 {
8640 /* If the stack might be accessed through a different register
8641 we have to make sure that the stack pointer decrement is not
8642 moved below the use of the stack slots. */
8643 s390_emit_stack_tie ();
8644
8645 insn = emit_insn (gen_add2_insn (temp_reg,
8646 GEN_INT (cfun_frame_layout.f8_offset)));
8647
8648 offset = 0;
8649
8650 for (i = 24; i <= next_fpr; i++)
8651 if (cfun_fpr_bit_p (i - 16))
8652 {
8653 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8654 cfun_frame_layout.frame_size
8655 + cfun_frame_layout.f8_offset
8656 + offset);
8657
8658 insn = save_fpr (temp_reg, offset, i);
8659 offset += 8;
8660 RTX_FRAME_RELATED_P (insn) = 1;
8661 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8662 gen_rtx_SET (VOIDmode,
8663 gen_rtx_MEM (DFmode, addr),
8664 gen_rtx_REG (DFmode, i)));
8665 }
8666 }
8667
8668 /* Set frame pointer, if needed. */
8669
8670 if (frame_pointer_needed)
8671 {
8672 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8673 RTX_FRAME_RELATED_P (insn) = 1;
8674 }
8675
8676 /* Set up got pointer, if needed. */
8677
8678 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8679 {
8680 rtx insns = s390_load_got ();
8681
8682 for (insn = insns; insn; insn = NEXT_INSN (insn))
8683 annotate_constant_pool_refs (&PATTERN (insn));
8684
8685 emit_insn (insns);
8686 }
8687
8688 if (TARGET_TPF_PROFILING)
8689 {
8690 /* Generate a BAS instruction to serve as a function
8691 entry intercept to facilitate the use of tracing
8692 algorithms located at the branch target. */
8693 emit_insn (gen_prologue_tpf ());
8694
8695 /* Emit a blockage here so that all code
8696 lies between the profiling mechanisms. */
8697 emit_insn (gen_blockage ());
8698 }
8699 }
8700
8701 /* Expand the epilogue into a bunch of separate insns. */
8702
8703 void
8704 s390_emit_epilogue (bool sibcall)
8705 {
8706 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8707 int area_bottom, area_top, offset = 0;
8708 int next_offset;
8709 rtvec p;
8710 int i;
8711
8712 if (TARGET_TPF_PROFILING)
8713 {
8714
8715 /* Generate a BAS instruction to serve as a function
8716 entry intercept to facilitate the use of tracing
8717 algorithms located at the branch target. */
8718
8719 /* Emit a blockage here so that all code
8720 lies between the profiling mechanisms. */
8721 emit_insn (gen_blockage ());
8722
8723 emit_insn (gen_epilogue_tpf ());
8724 }
8725
8726 /* Check whether to use frame or stack pointer for restore. */
8727
8728 frame_pointer = (frame_pointer_needed
8729 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8730
8731 s390_frame_area (&area_bottom, &area_top);
8732
8733 /* Check whether we can access the register save area.
8734 If not, increment the frame pointer as required. */
8735
8736 if (area_top <= area_bottom)
8737 {
8738 /* Nothing to restore. */
8739 }
8740 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8741 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8742 {
8743 /* Area is in range. */
8744 offset = cfun_frame_layout.frame_size;
8745 }
8746 else
8747 {
8748 rtx insn, frame_off, cfa;
8749
8750 offset = area_bottom < 0 ? -area_bottom : 0;
8751 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8752
8753 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8754 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8755 if (DISP_IN_RANGE (INTVAL (frame_off)))
8756 {
8757 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8758 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8759 insn = emit_insn (insn);
8760 }
8761 else
8762 {
8763 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8764 frame_off = force_const_mem (Pmode, frame_off);
8765
8766 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8767 annotate_constant_pool_refs (&PATTERN (insn));
8768 }
8769 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8770 RTX_FRAME_RELATED_P (insn) = 1;
8771 }
8772
8773 /* Restore call saved fprs. */
8774
8775 if (TARGET_64BIT)
8776 {
8777 if (cfun_save_high_fprs_p)
8778 {
8779 next_offset = cfun_frame_layout.f8_offset;
8780 for (i = 24; i < 32; i++)
8781 {
8782 if (cfun_fpr_bit_p (i - 16))
8783 {
8784 restore_fpr (frame_pointer,
8785 offset + next_offset, i);
8786 cfa_restores
8787 = alloc_reg_note (REG_CFA_RESTORE,
8788 gen_rtx_REG (DFmode, i), cfa_restores);
8789 next_offset += 8;
8790 }
8791 }
8792 }
8793
8794 }
8795 else
8796 {
8797 next_offset = cfun_frame_layout.f4_offset;
8798 for (i = 18; i < 20; i++)
8799 {
8800 if (cfun_fpr_bit_p (i - 16))
8801 {
8802 restore_fpr (frame_pointer,
8803 offset + next_offset, i);
8804 cfa_restores
8805 = alloc_reg_note (REG_CFA_RESTORE,
8806 gen_rtx_REG (DFmode, i), cfa_restores);
8807 next_offset += 8;
8808 }
8809 else if (!TARGET_PACKED_STACK)
8810 next_offset += 8;
8811 }
8812
8813 }
8814
8815 /* Return register. */
8816
8817 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8818
8819 /* Restore call saved gprs. */
8820
8821 if (cfun_frame_layout.first_restore_gpr != -1)
8822 {
8823 rtx insn, addr;
8824 int i;
8825
8826 /* Check for global register and save them
8827 to stack location from where they get restored. */
8828
8829 for (i = cfun_frame_layout.first_restore_gpr;
8830 i <= cfun_frame_layout.last_restore_gpr;
8831 i++)
8832 {
8833 if (global_not_special_regno_p (i))
8834 {
8835 addr = plus_constant (Pmode, frame_pointer,
8836 offset + cfun_frame_layout.gprs_offset
8837 + (i - cfun_frame_layout.first_save_gpr_slot)
8838 * UNITS_PER_LONG);
8839 addr = gen_rtx_MEM (Pmode, addr);
8840 set_mem_alias_set (addr, get_frame_alias_set ());
8841 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8842 }
8843 else
8844 cfa_restores
8845 = alloc_reg_note (REG_CFA_RESTORE,
8846 gen_rtx_REG (Pmode, i), cfa_restores);
8847 }
8848
8849 if (! sibcall)
8850 {
8851 /* Fetch return address from stack before load multiple,
8852 this will do good for scheduling. */
8853
8854 if (cfun_frame_layout.save_return_addr_p
8855 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8856 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8857 {
8858 int return_regnum = find_unused_clobbered_reg();
8859 if (!return_regnum)
8860 return_regnum = 4;
8861 return_reg = gen_rtx_REG (Pmode, return_regnum);
8862
8863 addr = plus_constant (Pmode, frame_pointer,
8864 offset + cfun_frame_layout.gprs_offset
8865 + (RETURN_REGNUM
8866 - cfun_frame_layout.first_save_gpr_slot)
8867 * UNITS_PER_LONG);
8868 addr = gen_rtx_MEM (Pmode, addr);
8869 set_mem_alias_set (addr, get_frame_alias_set ());
8870 emit_move_insn (return_reg, addr);
8871 }
8872 }
8873
8874 insn = restore_gprs (frame_pointer,
8875 offset + cfun_frame_layout.gprs_offset
8876 + (cfun_frame_layout.first_restore_gpr
8877 - cfun_frame_layout.first_save_gpr_slot)
8878 * UNITS_PER_LONG,
8879 cfun_frame_layout.first_restore_gpr,
8880 cfun_frame_layout.last_restore_gpr);
8881 insn = emit_insn (insn);
8882 REG_NOTES (insn) = cfa_restores;
8883 add_reg_note (insn, REG_CFA_DEF_CFA,
8884 plus_constant (Pmode, stack_pointer_rtx,
8885 STACK_POINTER_OFFSET));
8886 RTX_FRAME_RELATED_P (insn) = 1;
8887 }
8888
8889 if (! sibcall)
8890 {
8891
8892 /* Return to caller. */
8893
8894 p = rtvec_alloc (2);
8895
8896 RTVEC_ELT (p, 0) = ret_rtx;
8897 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8898 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8899 }
8900 }
8901
8902
8903 /* Return the size in bytes of a function argument of
8904 type TYPE and/or mode MODE. At least one of TYPE or
8905 MODE must be specified. */
8906
8907 static int
8908 s390_function_arg_size (enum machine_mode mode, const_tree type)
8909 {
8910 if (type)
8911 return int_size_in_bytes (type);
8912
8913 /* No type info available for some library calls ... */
8914 if (mode != BLKmode)
8915 return GET_MODE_SIZE (mode);
8916
8917 /* If we have neither type nor mode, abort */
8918 gcc_unreachable ();
8919 }
8920
8921 /* Return true if a function argument of type TYPE and mode MODE
8922 is to be passed in a floating-point register, if available. */
8923
8924 static bool
8925 s390_function_arg_float (enum machine_mode mode, const_tree type)
8926 {
8927 int size = s390_function_arg_size (mode, type);
8928 if (size > 8)
8929 return false;
8930
8931 /* Soft-float changes the ABI: no floating-point registers are used. */
8932 if (TARGET_SOFT_FLOAT)
8933 return false;
8934
8935 /* No type info available for some library calls ... */
8936 if (!type)
8937 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8938
8939 /* The ABI says that record types with a single member are treated
8940 just like that member would be. */
8941 while (TREE_CODE (type) == RECORD_TYPE)
8942 {
8943 tree field, single = NULL_TREE;
8944
8945 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8946 {
8947 if (TREE_CODE (field) != FIELD_DECL)
8948 continue;
8949
8950 if (single == NULL_TREE)
8951 single = TREE_TYPE (field);
8952 else
8953 return false;
8954 }
8955
8956 if (single == NULL_TREE)
8957 return false;
8958 else
8959 type = single;
8960 }
8961
8962 return TREE_CODE (type) == REAL_TYPE;
8963 }
8964
8965 /* Return true if a function argument of type TYPE and mode MODE
8966 is to be passed in an integer register, or a pair of integer
8967 registers, if available. */
8968
8969 static bool
8970 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8971 {
8972 int size = s390_function_arg_size (mode, type);
8973 if (size > 8)
8974 return false;
8975
8976 /* No type info available for some library calls ... */
8977 if (!type)
8978 return GET_MODE_CLASS (mode) == MODE_INT
8979 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8980
8981 /* We accept small integral (and similar) types. */
8982 if (INTEGRAL_TYPE_P (type)
8983 || POINTER_TYPE_P (type)
8984 || TREE_CODE (type) == NULLPTR_TYPE
8985 || TREE_CODE (type) == OFFSET_TYPE
8986 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8987 return true;
8988
8989 /* We also accept structs of size 1, 2, 4, 8 that are not
8990 passed in floating-point registers. */
8991 if (AGGREGATE_TYPE_P (type)
8992 && exact_log2 (size) >= 0
8993 && !s390_function_arg_float (mode, type))
8994 return true;
8995
8996 return false;
8997 }
8998
8999 /* Return 1 if a function argument of type TYPE and mode MODE
9000 is to be passed by reference. The ABI specifies that only
9001 structures of size 1, 2, 4, or 8 bytes are passed by value,
9002 all other structures (and complex numbers) are passed by
9003 reference. */
9004
9005 static bool
9006 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
9007 enum machine_mode mode, const_tree type,
9008 bool named ATTRIBUTE_UNUSED)
9009 {
9010 int size = s390_function_arg_size (mode, type);
9011 if (size > 8)
9012 return true;
9013
9014 if (type)
9015 {
9016 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
9017 return 1;
9018
9019 if (TREE_CODE (type) == COMPLEX_TYPE
9020 || TREE_CODE (type) == VECTOR_TYPE)
9021 return 1;
9022 }
9023
9024 return 0;
9025 }
9026
9027 /* Update the data in CUM to advance over an argument of mode MODE and
9028 data type TYPE. (TYPE is null for libcalls where that information
9029 may not be available.). The boolean NAMED specifies whether the
9030 argument is a named argument (as opposed to an unnamed argument
9031 matching an ellipsis). */
9032
9033 static void
9034 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
9035 const_tree type, bool named ATTRIBUTE_UNUSED)
9036 {
9037 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9038
9039 if (s390_function_arg_float (mode, type))
9040 {
9041 cum->fprs += 1;
9042 }
9043 else if (s390_function_arg_integer (mode, type))
9044 {
9045 int size = s390_function_arg_size (mode, type);
9046 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
9047 }
9048 else
9049 gcc_unreachable ();
9050 }
9051
9052 /* Define where to put the arguments to a function.
9053 Value is zero to push the argument on the stack,
9054 or a hard register in which to store the argument.
9055
9056 MODE is the argument's machine mode.
9057 TYPE is the data type of the argument (as a tree).
9058 This is null for libcalls where that information may
9059 not be available.
9060 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9061 the preceding args and about the function being called.
9062 NAMED is nonzero if this argument is a named parameter
9063 (otherwise it is an extra parameter matching an ellipsis).
9064
9065 On S/390, we use general purpose registers 2 through 6 to
9066 pass integer, pointer, and certain structure arguments, and
9067 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9068 to pass floating point arguments. All remaining arguments
9069 are pushed to the stack. */
9070
9071 static rtx
9072 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
9073 const_tree type, bool named ATTRIBUTE_UNUSED)
9074 {
9075 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9076
9077 if (s390_function_arg_float (mode, type))
9078 {
9079 if (cum->fprs + 1 > FP_ARG_NUM_REG)
9080 return 0;
9081 else
9082 return gen_rtx_REG (mode, cum->fprs + 16);
9083 }
9084 else if (s390_function_arg_integer (mode, type))
9085 {
9086 int size = s390_function_arg_size (mode, type);
9087 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9088
9089 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
9090 return 0;
9091 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
9092 return gen_rtx_REG (mode, cum->gprs + 2);
9093 else if (n_gprs == 2)
9094 {
9095 rtvec p = rtvec_alloc (2);
9096
9097 RTVEC_ELT (p, 0)
9098 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
9099 const0_rtx);
9100 RTVEC_ELT (p, 1)
9101 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
9102 GEN_INT (4));
9103
9104 return gen_rtx_PARALLEL (mode, p);
9105 }
9106 }
9107
9108 /* After the real arguments, expand_call calls us once again
9109 with a void_type_node type. Whatever we return here is
9110 passed as operand 2 to the call expanders.
9111
9112 We don't need this feature ... */
9113 else if (type == void_type_node)
9114 return const0_rtx;
9115
9116 gcc_unreachable ();
9117 }
9118
9119 /* Return true if return values of type TYPE should be returned
9120 in a memory buffer whose address is passed by the caller as
9121 hidden first argument. */
9122
9123 static bool
9124 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
9125 {
9126 /* We accept small integral (and similar) types. */
9127 if (INTEGRAL_TYPE_P (type)
9128 || POINTER_TYPE_P (type)
9129 || TREE_CODE (type) == OFFSET_TYPE
9130 || TREE_CODE (type) == REAL_TYPE)
9131 return int_size_in_bytes (type) > 8;
9132
9133 /* Aggregates and similar constructs are always returned
9134 in memory. */
9135 if (AGGREGATE_TYPE_P (type)
9136 || TREE_CODE (type) == COMPLEX_TYPE
9137 || TREE_CODE (type) == VECTOR_TYPE)
9138 return true;
9139
9140 /* ??? We get called on all sorts of random stuff from
9141 aggregate_value_p. We can't abort, but it's not clear
9142 what's safe to return. Pretend it's a struct I guess. */
9143 return true;
9144 }
9145
9146 /* Function arguments and return values are promoted to word size. */
9147
9148 static enum machine_mode
9149 s390_promote_function_mode (const_tree type, enum machine_mode mode,
9150 int *punsignedp,
9151 const_tree fntype ATTRIBUTE_UNUSED,
9152 int for_return ATTRIBUTE_UNUSED)
9153 {
9154 if (INTEGRAL_MODE_P (mode)
9155 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
9156 {
9157 if (type != NULL_TREE && POINTER_TYPE_P (type))
9158 *punsignedp = POINTERS_EXTEND_UNSIGNED;
9159 return Pmode;
9160 }
9161
9162 return mode;
9163 }
9164
9165 /* Define where to return a (scalar) value of type RET_TYPE.
9166 If RET_TYPE is null, define where to return a (scalar)
9167 value of mode MODE from a libcall. */
9168
9169 static rtx
9170 s390_function_and_libcall_value (enum machine_mode mode,
9171 const_tree ret_type,
9172 const_tree fntype_or_decl,
9173 bool outgoing ATTRIBUTE_UNUSED)
9174 {
9175 /* For normal functions perform the promotion as
9176 promote_function_mode would do. */
9177 if (ret_type)
9178 {
9179 int unsignedp = TYPE_UNSIGNED (ret_type);
9180 mode = promote_function_mode (ret_type, mode, &unsignedp,
9181 fntype_or_decl, 1);
9182 }
9183
9184 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
9185 gcc_assert (GET_MODE_SIZE (mode) <= 8);
9186
9187 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
9188 return gen_rtx_REG (mode, 16);
9189 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
9190 || UNITS_PER_LONG == UNITS_PER_WORD)
9191 return gen_rtx_REG (mode, 2);
9192 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
9193 {
9194 /* This case is triggered when returning a 64 bit value with
9195 -m31 -mzarch. Although the value would fit into a single
9196 register it has to be forced into a 32 bit register pair in
9197 order to match the ABI. */
9198 rtvec p = rtvec_alloc (2);
9199
9200 RTVEC_ELT (p, 0)
9201 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
9202 RTVEC_ELT (p, 1)
9203 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
9204
9205 return gen_rtx_PARALLEL (mode, p);
9206 }
9207
9208 gcc_unreachable ();
9209 }
9210
9211 /* Define where to return a scalar return value of type RET_TYPE. */
9212
9213 static rtx
9214 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
9215 bool outgoing)
9216 {
9217 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
9218 fn_decl_or_type, outgoing);
9219 }
9220
9221 /* Define where to return a scalar libcall return value of mode
9222 MODE. */
9223
9224 static rtx
9225 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9226 {
9227 return s390_function_and_libcall_value (mode, NULL_TREE,
9228 NULL_TREE, true);
9229 }
9230
9231
9232 /* Create and return the va_list datatype.
9233
9234 On S/390, va_list is an array type equivalent to
9235
9236 typedef struct __va_list_tag
9237 {
9238 long __gpr;
9239 long __fpr;
9240 void *__overflow_arg_area;
9241 void *__reg_save_area;
9242 } va_list[1];
9243
9244 where __gpr and __fpr hold the number of general purpose
9245 or floating point arguments used up to now, respectively,
9246 __overflow_arg_area points to the stack location of the
9247 next argument passed on the stack, and __reg_save_area
9248 always points to the start of the register area in the
9249 call frame of the current function. The function prologue
9250 saves all registers used for argument passing into this
9251 area if the function uses variable arguments. */
9252
9253 static tree
9254 s390_build_builtin_va_list (void)
9255 {
9256 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9257
9258 record = lang_hooks.types.make_type (RECORD_TYPE);
9259
9260 type_decl =
9261 build_decl (BUILTINS_LOCATION,
9262 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9263
9264 f_gpr = build_decl (BUILTINS_LOCATION,
9265 FIELD_DECL, get_identifier ("__gpr"),
9266 long_integer_type_node);
9267 f_fpr = build_decl (BUILTINS_LOCATION,
9268 FIELD_DECL, get_identifier ("__fpr"),
9269 long_integer_type_node);
9270 f_ovf = build_decl (BUILTINS_LOCATION,
9271 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9272 ptr_type_node);
9273 f_sav = build_decl (BUILTINS_LOCATION,
9274 FIELD_DECL, get_identifier ("__reg_save_area"),
9275 ptr_type_node);
9276
9277 va_list_gpr_counter_field = f_gpr;
9278 va_list_fpr_counter_field = f_fpr;
9279
9280 DECL_FIELD_CONTEXT (f_gpr) = record;
9281 DECL_FIELD_CONTEXT (f_fpr) = record;
9282 DECL_FIELD_CONTEXT (f_ovf) = record;
9283 DECL_FIELD_CONTEXT (f_sav) = record;
9284
9285 TYPE_STUB_DECL (record) = type_decl;
9286 TYPE_NAME (record) = type_decl;
9287 TYPE_FIELDS (record) = f_gpr;
9288 DECL_CHAIN (f_gpr) = f_fpr;
9289 DECL_CHAIN (f_fpr) = f_ovf;
9290 DECL_CHAIN (f_ovf) = f_sav;
9291
9292 layout_type (record);
9293
9294 /* The correct type is an array type of one element. */
9295 return build_array_type (record, build_index_type (size_zero_node));
9296 }
9297
9298 /* Implement va_start by filling the va_list structure VALIST.
9299 STDARG_P is always true, and ignored.
9300 NEXTARG points to the first anonymous stack argument.
9301
9302 The following global variables are used to initialize
9303 the va_list structure:
9304
9305 crtl->args.info:
9306 holds number of gprs and fprs used for named arguments.
9307 crtl->args.arg_offset_rtx:
9308 holds the offset of the first anonymous stack argument
9309 (relative to the virtual arg pointer). */
9310
9311 static void
9312 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9313 {
9314 HOST_WIDE_INT n_gpr, n_fpr;
9315 int off;
9316 tree f_gpr, f_fpr, f_ovf, f_sav;
9317 tree gpr, fpr, ovf, sav, t;
9318
9319 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9320 f_fpr = DECL_CHAIN (f_gpr);
9321 f_ovf = DECL_CHAIN (f_fpr);
9322 f_sav = DECL_CHAIN (f_ovf);
9323
9324 valist = build_simple_mem_ref (valist);
9325 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9326 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9327 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9328 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9329
9330 /* Count number of gp and fp argument registers used. */
9331
9332 n_gpr = crtl->args.info.gprs;
9333 n_fpr = crtl->args.info.fprs;
9334
9335 if (cfun->va_list_gpr_size)
9336 {
9337 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9338 build_int_cst (NULL_TREE, n_gpr));
9339 TREE_SIDE_EFFECTS (t) = 1;
9340 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9341 }
9342
9343 if (cfun->va_list_fpr_size)
9344 {
9345 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9346 build_int_cst (NULL_TREE, n_fpr));
9347 TREE_SIDE_EFFECTS (t) = 1;
9348 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9349 }
9350
9351 /* Find the overflow area. */
9352 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9353 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9354 {
9355 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9356
9357 off = INTVAL (crtl->args.arg_offset_rtx);
9358 off = off < 0 ? 0 : off;
9359 if (TARGET_DEBUG_ARG)
9360 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9361 (int)n_gpr, (int)n_fpr, off);
9362
9363 t = fold_build_pointer_plus_hwi (t, off);
9364
9365 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9366 TREE_SIDE_EFFECTS (t) = 1;
9367 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9368 }
9369
9370 /* Find the register save area. */
9371 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9372 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9373 {
9374 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
9375 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
9376
9377 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9378 TREE_SIDE_EFFECTS (t) = 1;
9379 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9380 }
9381 }
9382
9383 /* Implement va_arg by updating the va_list structure
9384 VALIST as required to retrieve an argument of type
9385 TYPE, and returning that argument.
9386
9387 Generates code equivalent to:
9388
9389 if (integral value) {
9390 if (size <= 4 && args.gpr < 5 ||
9391 size > 4 && args.gpr < 4 )
9392 ret = args.reg_save_area[args.gpr+8]
9393 else
9394 ret = *args.overflow_arg_area++;
9395 } else if (float value) {
9396 if (args.fgpr < 2)
9397 ret = args.reg_save_area[args.fpr+64]
9398 else
9399 ret = *args.overflow_arg_area++;
9400 } else if (aggregate value) {
9401 if (args.gpr < 5)
9402 ret = *args.reg_save_area[args.gpr]
9403 else
9404 ret = **args.overflow_arg_area++;
9405 } */
9406
9407 static tree
9408 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9409 gimple_seq *post_p ATTRIBUTE_UNUSED)
9410 {
9411 tree f_gpr, f_fpr, f_ovf, f_sav;
9412 tree gpr, fpr, ovf, sav, reg, t, u;
9413 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
9414 tree lab_false, lab_over, addr;
9415
9416 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9417 f_fpr = DECL_CHAIN (f_gpr);
9418 f_ovf = DECL_CHAIN (f_fpr);
9419 f_sav = DECL_CHAIN (f_ovf);
9420
9421 valist = build_va_arg_indirect_ref (valist);
9422 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9423 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9424 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9425
9426 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9427 both appear on a lhs. */
9428 valist = unshare_expr (valist);
9429 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9430
9431 size = int_size_in_bytes (type);
9432
9433 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9434 {
9435 if (TARGET_DEBUG_ARG)
9436 {
9437 fprintf (stderr, "va_arg: aggregate type");
9438 debug_tree (type);
9439 }
9440
9441 /* Aggregates are passed by reference. */
9442 indirect_p = 1;
9443 reg = gpr;
9444 n_reg = 1;
9445
9446 /* kernel stack layout on 31 bit: It is assumed here that no padding
9447 will be added by s390_frame_info because for va_args always an even
9448 number of gprs has to be saved r15-r2 = 14 regs. */
9449 sav_ofs = 2 * UNITS_PER_LONG;
9450 sav_scale = UNITS_PER_LONG;
9451 size = UNITS_PER_LONG;
9452 max_reg = GP_ARG_NUM_REG - n_reg;
9453 }
9454 else if (s390_function_arg_float (TYPE_MODE (type), type))
9455 {
9456 if (TARGET_DEBUG_ARG)
9457 {
9458 fprintf (stderr, "va_arg: float type");
9459 debug_tree (type);
9460 }
9461
9462 /* FP args go in FP registers, if present. */
9463 indirect_p = 0;
9464 reg = fpr;
9465 n_reg = 1;
9466 sav_ofs = 16 * UNITS_PER_LONG;
9467 sav_scale = 8;
9468 max_reg = FP_ARG_NUM_REG - n_reg;
9469 }
9470 else
9471 {
9472 if (TARGET_DEBUG_ARG)
9473 {
9474 fprintf (stderr, "va_arg: other type");
9475 debug_tree (type);
9476 }
9477
9478 /* Otherwise into GP registers. */
9479 indirect_p = 0;
9480 reg = gpr;
9481 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9482
9483 /* kernel stack layout on 31 bit: It is assumed here that no padding
9484 will be added by s390_frame_info because for va_args always an even
9485 number of gprs has to be saved r15-r2 = 14 regs. */
9486 sav_ofs = 2 * UNITS_PER_LONG;
9487
9488 if (size < UNITS_PER_LONG)
9489 sav_ofs += UNITS_PER_LONG - size;
9490
9491 sav_scale = UNITS_PER_LONG;
9492 max_reg = GP_ARG_NUM_REG - n_reg;
9493 }
9494
9495 /* Pull the value out of the saved registers ... */
9496
9497 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9498 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9499 addr = create_tmp_var (ptr_type_node, "addr");
9500
9501 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9502 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9503 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9504 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9505 gimplify_and_add (t, pre_p);
9506
9507 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9508 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9509 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9510 t = fold_build_pointer_plus (t, u);
9511
9512 gimplify_assign (addr, t, pre_p);
9513
9514 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9515
9516 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9517
9518
9519 /* ... Otherwise out of the overflow area. */
9520
9521 t = ovf;
9522 if (size < UNITS_PER_LONG)
9523 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9524
9525 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9526
9527 gimplify_assign (addr, t, pre_p);
9528
9529 t = fold_build_pointer_plus_hwi (t, size);
9530 gimplify_assign (ovf, t, pre_p);
9531
9532 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9533
9534
9535 /* Increment register save count. */
9536
9537 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9538 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9539 gimplify_and_add (u, pre_p);
9540
9541 if (indirect_p)
9542 {
9543 t = build_pointer_type_for_mode (build_pointer_type (type),
9544 ptr_mode, true);
9545 addr = fold_convert (t, addr);
9546 addr = build_va_arg_indirect_ref (addr);
9547 }
9548 else
9549 {
9550 t = build_pointer_type_for_mode (type, ptr_mode, true);
9551 addr = fold_convert (t, addr);
9552 }
9553
9554 return build_va_arg_indirect_ref (addr);
9555 }
9556
9557 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9558 expanders.
9559 DEST - Register location where CC will be stored.
9560 TDB - Pointer to a 256 byte area where to store the transaction.
9561 diagnostic block. NULL if TDB is not needed.
9562 RETRY - Retry count value. If non-NULL a retry loop for CC2
9563 is emitted
9564 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9565 of the tbegin instruction pattern. */
9566
9567 void
9568 s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
9569 {
9570 const int CC0 = 1 << 3;
9571 const int CC1 = 1 << 2;
9572 const int CC3 = 1 << 0;
9573 rtx abort_label = gen_label_rtx ();
9574 rtx leave_label = gen_label_rtx ();
9575 rtx retry_reg = gen_reg_rtx (SImode);
9576 rtx retry_label = NULL_RTX;
9577 rtx jump;
9578 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
9579
9580 if (retry != NULL_RTX)
9581 {
9582 emit_move_insn (retry_reg, retry);
9583 retry_label = gen_label_rtx ();
9584 emit_label (retry_label);
9585 }
9586
9587 if (clobber_fprs_p)
9588 emit_insn (gen_tbegin_1 (tdb,
9589 gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));
9590 else
9591 emit_insn (gen_tbegin_nofloat_1 (tdb,
9592 gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK)));
9593
9594 jump = s390_emit_jump (abort_label,
9595 gen_rtx_NE (VOIDmode,
9596 gen_rtx_REG (CCRAWmode, CC_REGNUM),
9597 gen_rtx_CONST_INT (VOIDmode, CC0)));
9598
9599 JUMP_LABEL (jump) = abort_label;
9600 LABEL_NUSES (abort_label) = 1;
9601 add_reg_note (jump, REG_BR_PROB, very_unlikely);
9602
9603 /* Initialize CC return value. */
9604 emit_move_insn (dest, const0_rtx);
9605
9606 s390_emit_jump (leave_label, NULL_RTX);
9607 LABEL_NUSES (leave_label) = 1;
9608 emit_barrier ();
9609
9610 /* Abort handler code. */
9611
9612 emit_label (abort_label);
9613 if (retry != NULL_RTX)
9614 {
9615 rtx count = gen_reg_rtx (SImode);
9616 jump = s390_emit_jump (leave_label,
9617 gen_rtx_EQ (VOIDmode,
9618 gen_rtx_REG (CCRAWmode, CC_REGNUM),
9619 gen_rtx_CONST_INT (VOIDmode, CC1 | CC3)));
9620 LABEL_NUSES (leave_label) = 2;
9621 add_reg_note (jump, REG_BR_PROB, very_unlikely);
9622
9623 /* CC2 - transient failure. Perform retry with ppa. */
9624 emit_move_insn (count, retry);
9625 emit_insn (gen_subsi3 (count, count, retry_reg));
9626 emit_insn (gen_tx_assist (count));
9627 jump = emit_jump_insn (gen_doloop_si64 (retry_label,
9628 retry_reg,
9629 retry_reg));
9630 JUMP_LABEL (jump) = retry_label;
9631 LABEL_NUSES (retry_label) = 1;
9632 }
9633
9634 emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
9635 gen_rtvec (1, gen_rtx_REG (CCRAWmode,
9636 CC_REGNUM)),
9637 UNSPEC_CC_TO_INT));
9638 emit_label (leave_label);
9639 }
9640
9641 /* Builtins. */
9642
9643 enum s390_builtin
9644 {
9645 S390_BUILTIN_TBEGIN,
9646 S390_BUILTIN_TBEGIN_NOFLOAT,
9647 S390_BUILTIN_TBEGIN_RETRY,
9648 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9649 S390_BUILTIN_TBEGINC,
9650 S390_BUILTIN_TEND,
9651 S390_BUILTIN_TABORT,
9652 S390_BUILTIN_NON_TX_STORE,
9653 S390_BUILTIN_TX_NESTING_DEPTH,
9654 S390_BUILTIN_TX_ASSIST,
9655
9656 S390_BUILTIN_max
9657 };
9658
9659 static enum insn_code const code_for_builtin[S390_BUILTIN_max] = {
9660 CODE_FOR_tbegin,
9661 CODE_FOR_tbegin_nofloat,
9662 CODE_FOR_tbegin_retry,
9663 CODE_FOR_tbegin_retry_nofloat,
9664 CODE_FOR_tbeginc,
9665 CODE_FOR_tend,
9666 CODE_FOR_tabort,
9667 CODE_FOR_ntstg,
9668 CODE_FOR_etnd,
9669 CODE_FOR_tx_assist
9670 };
9671
9672 static void
9673 s390_init_builtins (void)
9674 {
9675 tree ftype, uint64_type;
9676
9677 /* void foo (void) */
9678 ftype = build_function_type_list (void_type_node, NULL_TREE);
9679 add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC,
9680 BUILT_IN_MD, NULL, NULL_TREE);
9681
9682 /* void foo (int) */
9683 ftype = build_function_type_list (void_type_node, integer_type_node,
9684 NULL_TREE);
9685 add_builtin_function ("__builtin_tabort", ftype,
9686 S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, NULL_TREE);
9687 add_builtin_function ("__builtin_tx_assist", ftype,
9688 S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
9689
9690 /* int foo (void *) */
9691 ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
9692 add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
9693 BUILT_IN_MD, NULL, NULL_TREE);
9694 add_builtin_function ("__builtin_tbegin_nofloat", ftype,
9695 S390_BUILTIN_TBEGIN_NOFLOAT,
9696 BUILT_IN_MD, NULL, NULL_TREE);
9697
9698 /* int foo (void *, int) */
9699 ftype = build_function_type_list (integer_type_node, ptr_type_node,
9700 integer_type_node, NULL_TREE);
9701 add_builtin_function ("__builtin_tbegin_retry", ftype,
9702 S390_BUILTIN_TBEGIN_RETRY,
9703 BUILT_IN_MD,
9704 NULL, NULL_TREE);
9705 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
9706 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9707 BUILT_IN_MD,
9708 NULL, NULL_TREE);
9709
9710 /* int foo (void) */
9711 ftype = build_function_type_list (integer_type_node, NULL_TREE);
9712 add_builtin_function ("__builtin_tx_nesting_depth", ftype,
9713 S390_BUILTIN_TX_NESTING_DEPTH,
9714 BUILT_IN_MD, NULL, NULL_TREE);
9715 add_builtin_function ("__builtin_tend", ftype,
9716 S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE);
9717
9718 /* void foo (uint64_t *, uint64_t) */
9719 if (TARGET_64BIT)
9720 uint64_type = long_unsigned_type_node;
9721 else
9722 uint64_type = long_long_unsigned_type_node;
9723
9724 ftype = build_function_type_list (void_type_node,
9725 build_pointer_type (uint64_type),
9726 uint64_type, NULL_TREE);
9727 add_builtin_function ("__builtin_non_tx_store", ftype,
9728 S390_BUILTIN_NON_TX_STORE,
9729 BUILT_IN_MD, NULL, NULL_TREE);
9730 }
9731
9732 /* Expand an expression EXP that calls a built-in function,
9733 with result going to TARGET if that's convenient
9734 (and in mode MODE if that's convenient).
9735 SUBTARGET may be used as the target for computing one of EXP's operands.
9736 IGNORE is nonzero if the value is to be ignored. */
9737
9738 static rtx
9739 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9740 enum machine_mode mode ATTRIBUTE_UNUSED,
9741 int ignore ATTRIBUTE_UNUSED)
9742 {
9743 #define MAX_ARGS 2
9744
9745 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9746 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9747 enum insn_code icode;
9748 rtx op[MAX_ARGS], pat;
9749 int arity;
9750 bool nonvoid;
9751 tree arg;
9752 call_expr_arg_iterator iter;
9753
9754 if (fcode >= S390_BUILTIN_max)
9755 internal_error ("bad builtin fcode");
9756 icode = code_for_builtin[fcode];
9757 if (icode == 0)
9758 internal_error ("bad builtin fcode");
9759
9760 if (!TARGET_ZEC12)
9761 error ("Transactional execution builtins require zEC12 or later\n");
9762
9763 if (!TARGET_HTM && TARGET_ZEC12)
9764 error ("Transactional execution builtins not enabled (-mtx)\n");
9765
9766 /* Set a flag in the machine specific cfun part in order to support
9767 saving/restoring of FPRs. */
9768 if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY)
9769 cfun->machine->tbegin_p = true;
9770
9771 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9772
9773 arity = 0;
9774 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9775 {
9776 const struct insn_operand_data *insn_op;
9777
9778 if (arg == error_mark_node)
9779 return NULL_RTX;
9780 if (arity >= MAX_ARGS)
9781 return NULL_RTX;
9782
9783 insn_op = &insn_data[icode].operand[arity + nonvoid];
9784
9785 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9786
9787 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9788 {
9789 if (insn_op->predicate == memory_operand)
9790 {
9791 /* Don't move a NULL pointer into a register. Otherwise
9792 we have to rely on combine being able to move it back
9793 in order to get an immediate 0 in the instruction. */
9794 if (op[arity] != const0_rtx)
9795 op[arity] = copy_to_mode_reg (Pmode, op[arity]);
9796 op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]);
9797 }
9798 else
9799 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9800 }
9801
9802 arity++;
9803 }
9804
9805 if (nonvoid)
9806 {
9807 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9808 if (!target
9809 || GET_MODE (target) != tmode
9810 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9811 target = gen_reg_rtx (tmode);
9812 }
9813
9814 switch (arity)
9815 {
9816 case 0:
9817 pat = GEN_FCN (icode) (target);
9818 break;
9819 case 1:
9820 if (nonvoid)
9821 pat = GEN_FCN (icode) (target, op[0]);
9822 else
9823 pat = GEN_FCN (icode) (op[0]);
9824 break;
9825 case 2:
9826 if (nonvoid)
9827 pat = GEN_FCN (icode) (target, op[0], op[1]);
9828 else
9829 pat = GEN_FCN (icode) (op[0], op[1]);
9830 break;
9831 default:
9832 gcc_unreachable ();
9833 }
9834 if (!pat)
9835 return NULL_RTX;
9836 emit_insn (pat);
9837
9838 if (nonvoid)
9839 return target;
9840 else
9841 return const0_rtx;
9842 }
9843
9844
9845 /* Output assembly code for the trampoline template to
9846 stdio stream FILE.
9847
9848 On S/390, we use gpr 1 internally in the trampoline code;
9849 gpr 0 is used to hold the static chain. */
9850
9851 static void
9852 s390_asm_trampoline_template (FILE *file)
9853 {
9854 rtx op[2];
9855 op[0] = gen_rtx_REG (Pmode, 0);
9856 op[1] = gen_rtx_REG (Pmode, 1);
9857
9858 if (TARGET_64BIT)
9859 {
9860 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9861 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9862 output_asm_insn ("br\t%1", op); /* 2 byte */
9863 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9864 }
9865 else
9866 {
9867 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9868 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9869 output_asm_insn ("br\t%1", op); /* 2 byte */
9870 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9871 }
9872 }
9873
9874 /* Emit RTL insns to initialize the variable parts of a trampoline.
9875 FNADDR is an RTX for the address of the function's pure code.
9876 CXT is an RTX for the static chain value for the function. */
9877
9878 static void
9879 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9880 {
9881 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9882 rtx mem;
9883
9884 emit_block_move (m_tramp, assemble_trampoline_template (),
9885 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9886
9887 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9888 emit_move_insn (mem, cxt);
9889 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9890 emit_move_insn (mem, fnaddr);
9891 }
9892
9893 /* Output assembler code to FILE to increment profiler label # LABELNO
9894 for profiling a function entry. */
9895
9896 void
9897 s390_function_profiler (FILE *file, int labelno)
9898 {
9899 rtx op[7];
9900
9901 char label[128];
9902 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9903
9904 fprintf (file, "# function profiler \n");
9905
9906 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9907 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9908 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9909
9910 op[2] = gen_rtx_REG (Pmode, 1);
9911 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9912 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9913
9914 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9915 if (flag_pic)
9916 {
9917 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9918 op[4] = gen_rtx_CONST (Pmode, op[4]);
9919 }
9920
9921 if (TARGET_64BIT)
9922 {
9923 output_asm_insn ("stg\t%0,%1", op);
9924 output_asm_insn ("larl\t%2,%3", op);
9925 output_asm_insn ("brasl\t%0,%4", op);
9926 output_asm_insn ("lg\t%0,%1", op);
9927 }
9928 else if (!flag_pic)
9929 {
9930 op[6] = gen_label_rtx ();
9931
9932 output_asm_insn ("st\t%0,%1", op);
9933 output_asm_insn ("bras\t%2,%l6", op);
9934 output_asm_insn (".long\t%4", op);
9935 output_asm_insn (".long\t%3", op);
9936 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9937 output_asm_insn ("l\t%0,0(%2)", op);
9938 output_asm_insn ("l\t%2,4(%2)", op);
9939 output_asm_insn ("basr\t%0,%0", op);
9940 output_asm_insn ("l\t%0,%1", op);
9941 }
9942 else
9943 {
9944 op[5] = gen_label_rtx ();
9945 op[6] = gen_label_rtx ();
9946
9947 output_asm_insn ("st\t%0,%1", op);
9948 output_asm_insn ("bras\t%2,%l6", op);
9949 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9950 output_asm_insn (".long\t%4-%l5", op);
9951 output_asm_insn (".long\t%3-%l5", op);
9952 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9953 output_asm_insn ("lr\t%0,%2", op);
9954 output_asm_insn ("a\t%0,0(%2)", op);
9955 output_asm_insn ("a\t%2,4(%2)", op);
9956 output_asm_insn ("basr\t%0,%0", op);
9957 output_asm_insn ("l\t%0,%1", op);
9958 }
9959 }
9960
9961 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9962 into its SYMBOL_REF_FLAGS. */
9963
9964 static void
9965 s390_encode_section_info (tree decl, rtx rtl, int first)
9966 {
9967 default_encode_section_info (decl, rtl, first);
9968
9969 if (TREE_CODE (decl) == VAR_DECL)
9970 {
9971 /* If a variable has a forced alignment to < 2 bytes, mark it
9972 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9973 operand. */
9974 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9975 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9976 if (!DECL_SIZE (decl)
9977 || !DECL_ALIGN (decl)
9978 || !host_integerp (DECL_SIZE (decl), 0)
9979 || (DECL_ALIGN (decl) <= 64
9980 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9981 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9982 }
9983
9984 /* Literal pool references don't have a decl so they are handled
9985 differently here. We rely on the information in the MEM_ALIGN
9986 entry to decide upon natural alignment. */
9987 if (MEM_P (rtl)
9988 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9989 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9990 && (MEM_ALIGN (rtl) == 0
9991 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9992 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9993 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9994 }
9995
9996 /* Output thunk to FILE that implements a C++ virtual function call (with
9997 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9998 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9999 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10000 relative to the resulting this pointer. */
10001
10002 static void
10003 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10004 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10005 tree function)
10006 {
10007 rtx op[10];
10008 int nonlocal = 0;
10009
10010 /* Make sure unwind info is emitted for the thunk if needed. */
10011 final_start_function (emit_barrier (), file, 1);
10012
10013 /* Operand 0 is the target function. */
10014 op[0] = XEXP (DECL_RTL (function), 0);
10015 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
10016 {
10017 nonlocal = 1;
10018 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
10019 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
10020 op[0] = gen_rtx_CONST (Pmode, op[0]);
10021 }
10022
10023 /* Operand 1 is the 'this' pointer. */
10024 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10025 op[1] = gen_rtx_REG (Pmode, 3);
10026 else
10027 op[1] = gen_rtx_REG (Pmode, 2);
10028
10029 /* Operand 2 is the delta. */
10030 op[2] = GEN_INT (delta);
10031
10032 /* Operand 3 is the vcall_offset. */
10033 op[3] = GEN_INT (vcall_offset);
10034
10035 /* Operand 4 is the temporary register. */
10036 op[4] = gen_rtx_REG (Pmode, 1);
10037
10038 /* Operands 5 to 8 can be used as labels. */
10039 op[5] = NULL_RTX;
10040 op[6] = NULL_RTX;
10041 op[7] = NULL_RTX;
10042 op[8] = NULL_RTX;
10043
10044 /* Operand 9 can be used for temporary register. */
10045 op[9] = NULL_RTX;
10046
10047 /* Generate code. */
10048 if (TARGET_64BIT)
10049 {
10050 /* Setup literal pool pointer if required. */
10051 if ((!DISP_IN_RANGE (delta)
10052 && !CONST_OK_FOR_K (delta)
10053 && !CONST_OK_FOR_Os (delta))
10054 || (!DISP_IN_RANGE (vcall_offset)
10055 && !CONST_OK_FOR_K (vcall_offset)
10056 && !CONST_OK_FOR_Os (vcall_offset)))
10057 {
10058 op[5] = gen_label_rtx ();
10059 output_asm_insn ("larl\t%4,%5", op);
10060 }
10061
10062 /* Add DELTA to this pointer. */
10063 if (delta)
10064 {
10065 if (CONST_OK_FOR_J (delta))
10066 output_asm_insn ("la\t%1,%2(%1)", op);
10067 else if (DISP_IN_RANGE (delta))
10068 output_asm_insn ("lay\t%1,%2(%1)", op);
10069 else if (CONST_OK_FOR_K (delta))
10070 output_asm_insn ("aghi\t%1,%2", op);
10071 else if (CONST_OK_FOR_Os (delta))
10072 output_asm_insn ("agfi\t%1,%2", op);
10073 else
10074 {
10075 op[6] = gen_label_rtx ();
10076 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
10077 }
10078 }
10079
10080 /* Perform vcall adjustment. */
10081 if (vcall_offset)
10082 {
10083 if (DISP_IN_RANGE (vcall_offset))
10084 {
10085 output_asm_insn ("lg\t%4,0(%1)", op);
10086 output_asm_insn ("ag\t%1,%3(%4)", op);
10087 }
10088 else if (CONST_OK_FOR_K (vcall_offset))
10089 {
10090 output_asm_insn ("lghi\t%4,%3", op);
10091 output_asm_insn ("ag\t%4,0(%1)", op);
10092 output_asm_insn ("ag\t%1,0(%4)", op);
10093 }
10094 else if (CONST_OK_FOR_Os (vcall_offset))
10095 {
10096 output_asm_insn ("lgfi\t%4,%3", op);
10097 output_asm_insn ("ag\t%4,0(%1)", op);
10098 output_asm_insn ("ag\t%1,0(%4)", op);
10099 }
10100 else
10101 {
10102 op[7] = gen_label_rtx ();
10103 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
10104 output_asm_insn ("ag\t%4,0(%1)", op);
10105 output_asm_insn ("ag\t%1,0(%4)", op);
10106 }
10107 }
10108
10109 /* Jump to target. */
10110 output_asm_insn ("jg\t%0", op);
10111
10112 /* Output literal pool if required. */
10113 if (op[5])
10114 {
10115 output_asm_insn (".align\t4", op);
10116 targetm.asm_out.internal_label (file, "L",
10117 CODE_LABEL_NUMBER (op[5]));
10118 }
10119 if (op[6])
10120 {
10121 targetm.asm_out.internal_label (file, "L",
10122 CODE_LABEL_NUMBER (op[6]));
10123 output_asm_insn (".long\t%2", op);
10124 }
10125 if (op[7])
10126 {
10127 targetm.asm_out.internal_label (file, "L",
10128 CODE_LABEL_NUMBER (op[7]));
10129 output_asm_insn (".long\t%3", op);
10130 }
10131 }
10132 else
10133 {
10134 /* Setup base pointer if required. */
10135 if (!vcall_offset
10136 || (!DISP_IN_RANGE (delta)
10137 && !CONST_OK_FOR_K (delta)
10138 && !CONST_OK_FOR_Os (delta))
10139 || (!DISP_IN_RANGE (delta)
10140 && !CONST_OK_FOR_K (vcall_offset)
10141 && !CONST_OK_FOR_Os (vcall_offset)))
10142 {
10143 op[5] = gen_label_rtx ();
10144 output_asm_insn ("basr\t%4,0", op);
10145 targetm.asm_out.internal_label (file, "L",
10146 CODE_LABEL_NUMBER (op[5]));
10147 }
10148
10149 /* Add DELTA to this pointer. */
10150 if (delta)
10151 {
10152 if (CONST_OK_FOR_J (delta))
10153 output_asm_insn ("la\t%1,%2(%1)", op);
10154 else if (DISP_IN_RANGE (delta))
10155 output_asm_insn ("lay\t%1,%2(%1)", op);
10156 else if (CONST_OK_FOR_K (delta))
10157 output_asm_insn ("ahi\t%1,%2", op);
10158 else if (CONST_OK_FOR_Os (delta))
10159 output_asm_insn ("afi\t%1,%2", op);
10160 else
10161 {
10162 op[6] = gen_label_rtx ();
10163 output_asm_insn ("a\t%1,%6-%5(%4)", op);
10164 }
10165 }
10166
10167 /* Perform vcall adjustment. */
10168 if (vcall_offset)
10169 {
10170 if (CONST_OK_FOR_J (vcall_offset))
10171 {
10172 output_asm_insn ("l\t%4,0(%1)", op);
10173 output_asm_insn ("a\t%1,%3(%4)", op);
10174 }
10175 else if (DISP_IN_RANGE (vcall_offset))
10176 {
10177 output_asm_insn ("l\t%4,0(%1)", op);
10178 output_asm_insn ("ay\t%1,%3(%4)", op);
10179 }
10180 else if (CONST_OK_FOR_K (vcall_offset))
10181 {
10182 output_asm_insn ("lhi\t%4,%3", op);
10183 output_asm_insn ("a\t%4,0(%1)", op);
10184 output_asm_insn ("a\t%1,0(%4)", op);
10185 }
10186 else if (CONST_OK_FOR_Os (vcall_offset))
10187 {
10188 output_asm_insn ("iilf\t%4,%3", op);
10189 output_asm_insn ("a\t%4,0(%1)", op);
10190 output_asm_insn ("a\t%1,0(%4)", op);
10191 }
10192 else
10193 {
10194 op[7] = gen_label_rtx ();
10195 output_asm_insn ("l\t%4,%7-%5(%4)", op);
10196 output_asm_insn ("a\t%4,0(%1)", op);
10197 output_asm_insn ("a\t%1,0(%4)", op);
10198 }
10199
10200 /* We had to clobber the base pointer register.
10201 Re-setup the base pointer (with a different base). */
10202 op[5] = gen_label_rtx ();
10203 output_asm_insn ("basr\t%4,0", op);
10204 targetm.asm_out.internal_label (file, "L",
10205 CODE_LABEL_NUMBER (op[5]));
10206 }
10207
10208 /* Jump to target. */
10209 op[8] = gen_label_rtx ();
10210
10211 if (!flag_pic)
10212 output_asm_insn ("l\t%4,%8-%5(%4)", op);
10213 else if (!nonlocal)
10214 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10215 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10216 else if (flag_pic == 1)
10217 {
10218 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10219 output_asm_insn ("l\t%4,%0(%4)", op);
10220 }
10221 else if (flag_pic == 2)
10222 {
10223 op[9] = gen_rtx_REG (Pmode, 0);
10224 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
10225 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10226 output_asm_insn ("ar\t%4,%9", op);
10227 output_asm_insn ("l\t%4,0(%4)", op);
10228 }
10229
10230 output_asm_insn ("br\t%4", op);
10231
10232 /* Output literal pool. */
10233 output_asm_insn (".align\t4", op);
10234
10235 if (nonlocal && flag_pic == 2)
10236 output_asm_insn (".long\t%0", op);
10237 if (nonlocal)
10238 {
10239 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
10240 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
10241 }
10242
10243 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
10244 if (!flag_pic)
10245 output_asm_insn (".long\t%0", op);
10246 else
10247 output_asm_insn (".long\t%0-%5", op);
10248
10249 if (op[6])
10250 {
10251 targetm.asm_out.internal_label (file, "L",
10252 CODE_LABEL_NUMBER (op[6]));
10253 output_asm_insn (".long\t%2", op);
10254 }
10255 if (op[7])
10256 {
10257 targetm.asm_out.internal_label (file, "L",
10258 CODE_LABEL_NUMBER (op[7]));
10259 output_asm_insn (".long\t%3", op);
10260 }
10261 }
10262 final_end_function ();
10263 }
10264
10265 static bool
10266 s390_valid_pointer_mode (enum machine_mode mode)
10267 {
10268 return (mode == SImode || (TARGET_64BIT && mode == DImode));
10269 }
10270
10271 /* Checks whether the given CALL_EXPR would use a caller
10272 saved register. This is used to decide whether sibling call
10273 optimization could be performed on the respective function
10274 call. */
10275
10276 static bool
10277 s390_call_saved_register_used (tree call_expr)
10278 {
10279 CUMULATIVE_ARGS cum_v;
10280 cumulative_args_t cum;
10281 tree parameter;
10282 enum machine_mode mode;
10283 tree type;
10284 rtx parm_rtx;
10285 int reg, i;
10286
10287 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
10288 cum = pack_cumulative_args (&cum_v);
10289
10290 for (i = 0; i < call_expr_nargs (call_expr); i++)
10291 {
10292 parameter = CALL_EXPR_ARG (call_expr, i);
10293 gcc_assert (parameter);
10294
10295 /* For an undeclared variable passed as parameter we will get
10296 an ERROR_MARK node here. */
10297 if (TREE_CODE (parameter) == ERROR_MARK)
10298 return true;
10299
10300 type = TREE_TYPE (parameter);
10301 gcc_assert (type);
10302
10303 mode = TYPE_MODE (type);
10304 gcc_assert (mode);
10305
10306 if (pass_by_reference (&cum_v, mode, type, true))
10307 {
10308 mode = Pmode;
10309 type = build_pointer_type (type);
10310 }
10311
10312 parm_rtx = s390_function_arg (cum, mode, type, 0);
10313
10314 s390_function_arg_advance (cum, mode, type, 0);
10315
10316 if (!parm_rtx)
10317 continue;
10318
10319 if (REG_P (parm_rtx))
10320 {
10321 for (reg = 0;
10322 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
10323 reg++)
10324 if (!call_used_regs[reg + REGNO (parm_rtx)])
10325 return true;
10326 }
10327
10328 if (GET_CODE (parm_rtx) == PARALLEL)
10329 {
10330 int i;
10331
10332 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
10333 {
10334 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
10335
10336 gcc_assert (REG_P (r));
10337
10338 for (reg = 0;
10339 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
10340 reg++)
10341 if (!call_used_regs[reg + REGNO (r)])
10342 return true;
10343 }
10344 }
10345
10346 }
10347 return false;
10348 }
10349
10350 /* Return true if the given call expression can be
10351 turned into a sibling call.
10352 DECL holds the declaration of the function to be called whereas
10353 EXP is the call expression itself. */
10354
10355 static bool
10356 s390_function_ok_for_sibcall (tree decl, tree exp)
10357 {
10358 /* The TPF epilogue uses register 1. */
10359 if (TARGET_TPF_PROFILING)
10360 return false;
10361
10362 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10363 which would have to be restored before the sibcall. */
10364 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
10365 return false;
10366
10367 /* Register 6 on s390 is available as an argument register but unfortunately
10368 "caller saved". This makes functions needing this register for arguments
10369 not suitable for sibcalls. */
10370 return !s390_call_saved_register_used (exp);
10371 }
10372
10373 /* Return the fixed registers used for condition codes. */
10374
10375 static bool
10376 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10377 {
10378 *p1 = CC_REGNUM;
10379 *p2 = INVALID_REGNUM;
10380
10381 return true;
10382 }
10383
10384 /* This function is used by the call expanders of the machine description.
10385 It emits the call insn itself together with the necessary operations
10386 to adjust the target address and returns the emitted insn.
10387 ADDR_LOCATION is the target address rtx
10388 TLS_CALL the location of the thread-local symbol
10389 RESULT_REG the register where the result of the call should be stored
10390 RETADDR_REG the register where the return address should be stored
10391 If this parameter is NULL_RTX the call is considered
10392 to be a sibling call. */
10393
10394 rtx
10395 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
10396 rtx retaddr_reg)
10397 {
10398 bool plt_call = false;
10399 rtx insn;
10400 rtx call;
10401 rtx clobber;
10402 rtvec vec;
10403
10404 /* Direct function calls need special treatment. */
10405 if (GET_CODE (addr_location) == SYMBOL_REF)
10406 {
10407 /* When calling a global routine in PIC mode, we must
10408 replace the symbol itself with the PLT stub. */
10409 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
10410 {
10411 if (retaddr_reg != NULL_RTX)
10412 {
10413 addr_location = gen_rtx_UNSPEC (Pmode,
10414 gen_rtvec (1, addr_location),
10415 UNSPEC_PLT);
10416 addr_location = gen_rtx_CONST (Pmode, addr_location);
10417 plt_call = true;
10418 }
10419 else
10420 /* For -fpic code the PLT entries might use r12 which is
10421 call-saved. Therefore we cannot do a sibcall when
10422 calling directly using a symbol ref. When reaching
10423 this point we decided (in s390_function_ok_for_sibcall)
10424 to do a sibcall for a function pointer but one of the
10425 optimizers was able to get rid of the function pointer
10426 by propagating the symbol ref into the call. This
10427 optimization is illegal for S/390 so we turn the direct
10428 call into a indirect call again. */
10429 addr_location = force_reg (Pmode, addr_location);
10430 }
10431
10432 /* Unless we can use the bras(l) insn, force the
10433 routine address into a register. */
10434 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10435 {
10436 if (flag_pic)
10437 addr_location = legitimize_pic_address (addr_location, 0);
10438 else
10439 addr_location = force_reg (Pmode, addr_location);
10440 }
10441 }
10442
10443 /* If it is already an indirect call or the code above moved the
10444 SYMBOL_REF to somewhere else make sure the address can be found in
10445 register 1. */
10446 if (retaddr_reg == NULL_RTX
10447 && GET_CODE (addr_location) != SYMBOL_REF
10448 && !plt_call)
10449 {
10450 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10451 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
10452 }
10453
10454 addr_location = gen_rtx_MEM (QImode, addr_location);
10455 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
10456
10457 if (result_reg != NULL_RTX)
10458 call = gen_rtx_SET (VOIDmode, result_reg, call);
10459
10460 if (retaddr_reg != NULL_RTX)
10461 {
10462 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
10463
10464 if (tls_call != NULL_RTX)
10465 vec = gen_rtvec (3, call, clobber,
10466 gen_rtx_USE (VOIDmode, tls_call));
10467 else
10468 vec = gen_rtvec (2, call, clobber);
10469
10470 call = gen_rtx_PARALLEL (VOIDmode, vec);
10471 }
10472
10473 insn = emit_call_insn (call);
10474
10475 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10476 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10477 {
10478 /* s390_function_ok_for_sibcall should
10479 have denied sibcalls in this case. */
10480 gcc_assert (retaddr_reg != NULL_RTX);
10481 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
10482 }
10483 return insn;
10484 }
10485
10486 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10487
10488 static void
10489 s390_conditional_register_usage (void)
10490 {
10491 int i;
10492
10493 if (flag_pic)
10494 {
10495 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10496 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10497 }
10498 if (TARGET_CPU_ZARCH)
10499 {
10500 fixed_regs[BASE_REGNUM] = 0;
10501 call_used_regs[BASE_REGNUM] = 0;
10502 fixed_regs[RETURN_REGNUM] = 0;
10503 call_used_regs[RETURN_REGNUM] = 0;
10504 }
10505 if (TARGET_64BIT)
10506 {
10507 for (i = 24; i < 32; i++)
10508 call_used_regs[i] = call_really_used_regs[i] = 0;
10509 }
10510 else
10511 {
10512 for (i = 18; i < 20; i++)
10513 call_used_regs[i] = call_really_used_regs[i] = 0;
10514 }
10515
10516 if (TARGET_SOFT_FLOAT)
10517 {
10518 for (i = 16; i < 32; i++)
10519 call_used_regs[i] = fixed_regs[i] = 1;
10520 }
10521 }
10522
10523 /* Corresponding function to eh_return expander. */
10524
10525 static GTY(()) rtx s390_tpf_eh_return_symbol;
10526 void
10527 s390_emit_tpf_eh_return (rtx target)
10528 {
10529 rtx insn, reg;
10530
10531 if (!s390_tpf_eh_return_symbol)
10532 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10533
10534 reg = gen_rtx_REG (Pmode, 2);
10535
10536 emit_move_insn (reg, target);
10537 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10538 gen_rtx_REG (Pmode, RETURN_REGNUM));
10539 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
10540
10541 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
10542 }
10543
10544 /* Rework the prologue/epilogue to avoid saving/restoring
10545 registers unnecessarily. */
10546
10547 static void
10548 s390_optimize_prologue (void)
10549 {
10550 rtx insn, new_insn, next_insn;
10551
10552 /* Do a final recompute of the frame-related data. */
10553
10554 s390_update_frame_layout ();
10555
10556 /* If all special registers are in fact used, there's nothing we
10557 can do, so no point in walking the insn list. */
10558
10559 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
10560 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
10561 && (TARGET_CPU_ZARCH
10562 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
10563 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10564 return;
10565
10566 /* Search for prologue/epilogue insns and replace them. */
10567
10568 for (insn = get_insns (); insn; insn = next_insn)
10569 {
10570 int first, last, off;
10571 rtx set, base, offset;
10572
10573 next_insn = NEXT_INSN (insn);
10574
10575 if (! NONJUMP_INSN_P (insn))
10576 continue;
10577
10578 if (GET_CODE (PATTERN (insn)) == PARALLEL
10579 && store_multiple_operation (PATTERN (insn), VOIDmode))
10580 {
10581 set = XVECEXP (PATTERN (insn), 0, 0);
10582 first = REGNO (SET_SRC (set));
10583 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10584 offset = const0_rtx;
10585 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10586 off = INTVAL (offset);
10587
10588 if (GET_CODE (base) != REG || off < 0)
10589 continue;
10590 if (cfun_frame_layout.first_save_gpr != -1
10591 && (cfun_frame_layout.first_save_gpr < first
10592 || cfun_frame_layout.last_save_gpr > last))
10593 continue;
10594 if (REGNO (base) != STACK_POINTER_REGNUM
10595 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10596 continue;
10597 if (first > BASE_REGNUM || last < BASE_REGNUM)
10598 continue;
10599
10600 if (cfun_frame_layout.first_save_gpr != -1)
10601 {
10602 new_insn = save_gprs (base,
10603 off + (cfun_frame_layout.first_save_gpr
10604 - first) * UNITS_PER_LONG,
10605 cfun_frame_layout.first_save_gpr,
10606 cfun_frame_layout.last_save_gpr);
10607 new_insn = emit_insn_before (new_insn, insn);
10608 INSN_ADDRESSES_NEW (new_insn, -1);
10609 }
10610
10611 remove_insn (insn);
10612 continue;
10613 }
10614
10615 if (cfun_frame_layout.first_save_gpr == -1
10616 && GET_CODE (PATTERN (insn)) == SET
10617 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10618 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10619 || (!TARGET_CPU_ZARCH
10620 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10621 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10622 {
10623 set = PATTERN (insn);
10624 first = REGNO (SET_SRC (set));
10625 offset = const0_rtx;
10626 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10627 off = INTVAL (offset);
10628
10629 if (GET_CODE (base) != REG || off < 0)
10630 continue;
10631 if (REGNO (base) != STACK_POINTER_REGNUM
10632 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10633 continue;
10634
10635 remove_insn (insn);
10636 continue;
10637 }
10638
10639 if (GET_CODE (PATTERN (insn)) == PARALLEL
10640 && load_multiple_operation (PATTERN (insn), VOIDmode))
10641 {
10642 set = XVECEXP (PATTERN (insn), 0, 0);
10643 first = REGNO (SET_DEST (set));
10644 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10645 offset = const0_rtx;
10646 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10647 off = INTVAL (offset);
10648
10649 if (GET_CODE (base) != REG || off < 0)
10650 continue;
10651 if (cfun_frame_layout.first_restore_gpr != -1
10652 && (cfun_frame_layout.first_restore_gpr < first
10653 || cfun_frame_layout.last_restore_gpr > last))
10654 continue;
10655 if (REGNO (base) != STACK_POINTER_REGNUM
10656 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10657 continue;
10658 if (first > BASE_REGNUM || last < BASE_REGNUM)
10659 continue;
10660
10661 if (cfun_frame_layout.first_restore_gpr != -1)
10662 {
10663 new_insn = restore_gprs (base,
10664 off + (cfun_frame_layout.first_restore_gpr
10665 - first) * UNITS_PER_LONG,
10666 cfun_frame_layout.first_restore_gpr,
10667 cfun_frame_layout.last_restore_gpr);
10668 new_insn = emit_insn_before (new_insn, insn);
10669 INSN_ADDRESSES_NEW (new_insn, -1);
10670 }
10671
10672 remove_insn (insn);
10673 continue;
10674 }
10675
10676 if (cfun_frame_layout.first_restore_gpr == -1
10677 && GET_CODE (PATTERN (insn)) == SET
10678 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10679 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10680 || (!TARGET_CPU_ZARCH
10681 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10682 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10683 {
10684 set = PATTERN (insn);
10685 first = REGNO (SET_DEST (set));
10686 offset = const0_rtx;
10687 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10688 off = INTVAL (offset);
10689
10690 if (GET_CODE (base) != REG || off < 0)
10691 continue;
10692 if (REGNO (base) != STACK_POINTER_REGNUM
10693 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10694 continue;
10695
10696 remove_insn (insn);
10697 continue;
10698 }
10699 }
10700 }
10701
10702 /* On z10 and later the dynamic branch prediction must see the
10703 backward jump within a certain windows. If not it falls back to
10704 the static prediction. This function rearranges the loop backward
10705 branch in a way which makes the static prediction always correct.
10706 The function returns true if it added an instruction. */
10707 static bool
10708 s390_fix_long_loop_prediction (rtx insn)
10709 {
10710 rtx set = single_set (insn);
10711 rtx code_label, label_ref, new_label;
10712 rtx uncond_jump;
10713 rtx cur_insn;
10714 rtx tmp;
10715 int distance;
10716
10717 /* This will exclude branch on count and branch on index patterns
10718 since these are correctly statically predicted. */
10719 if (!set
10720 || SET_DEST (set) != pc_rtx
10721 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10722 return false;
10723
10724 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10725 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10726
10727 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10728
10729 code_label = XEXP (label_ref, 0);
10730
10731 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10732 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10733 || (INSN_ADDRESSES (INSN_UID (insn))
10734 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10735 return false;
10736
10737 for (distance = 0, cur_insn = PREV_INSN (insn);
10738 distance < PREDICT_DISTANCE - 6;
10739 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10740 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10741 return false;
10742
10743 new_label = gen_label_rtx ();
10744 uncond_jump = emit_jump_insn_after (
10745 gen_rtx_SET (VOIDmode, pc_rtx,
10746 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10747 insn);
10748 emit_label_after (new_label, uncond_jump);
10749
10750 tmp = XEXP (SET_SRC (set), 1);
10751 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10752 XEXP (SET_SRC (set), 2) = tmp;
10753 INSN_CODE (insn) = -1;
10754
10755 XEXP (label_ref, 0) = new_label;
10756 JUMP_LABEL (insn) = new_label;
10757 JUMP_LABEL (uncond_jump) = code_label;
10758
10759 return true;
10760 }
10761
10762 /* Returns 1 if INSN reads the value of REG for purposes not related
10763 to addressing of memory, and 0 otherwise. */
10764 static int
10765 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10766 {
10767 return reg_referenced_p (reg, PATTERN (insn))
10768 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10769 }
10770
10771 /* Starting from INSN find_cond_jump looks downwards in the insn
10772 stream for a single jump insn which is the last user of the
10773 condition code set in INSN. */
10774 static rtx
10775 find_cond_jump (rtx insn)
10776 {
10777 for (; insn; insn = NEXT_INSN (insn))
10778 {
10779 rtx ite, cc;
10780
10781 if (LABEL_P (insn))
10782 break;
10783
10784 if (!JUMP_P (insn))
10785 {
10786 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10787 break;
10788 continue;
10789 }
10790
10791 /* This will be triggered by a return. */
10792 if (GET_CODE (PATTERN (insn)) != SET)
10793 break;
10794
10795 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10796 ite = SET_SRC (PATTERN (insn));
10797
10798 if (GET_CODE (ite) != IF_THEN_ELSE)
10799 break;
10800
10801 cc = XEXP (XEXP (ite, 0), 0);
10802 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10803 break;
10804
10805 if (find_reg_note (insn, REG_DEAD, cc))
10806 return insn;
10807 break;
10808 }
10809
10810 return NULL_RTX;
10811 }
10812
10813 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10814 the semantics does not change. If NULL_RTX is passed as COND the
10815 function tries to find the conditional jump starting with INSN. */
10816 static void
10817 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10818 {
10819 rtx tmp = *op0;
10820
10821 if (cond == NULL_RTX)
10822 {
10823 rtx jump = find_cond_jump (NEXT_INSN (insn));
10824 jump = jump ? single_set (jump) : NULL_RTX;
10825
10826 if (jump == NULL_RTX)
10827 return;
10828
10829 cond = XEXP (XEXP (jump, 1), 0);
10830 }
10831
10832 *op0 = *op1;
10833 *op1 = tmp;
10834 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10835 }
10836
10837 /* On z10, instructions of the compare-and-branch family have the
10838 property to access the register occurring as second operand with
10839 its bits complemented. If such a compare is grouped with a second
10840 instruction that accesses the same register non-complemented, and
10841 if that register's value is delivered via a bypass, then the
10842 pipeline recycles, thereby causing significant performance decline.
10843 This function locates such situations and exchanges the two
10844 operands of the compare. The function return true whenever it
10845 added an insn. */
10846 static bool
10847 s390_z10_optimize_cmp (rtx insn)
10848 {
10849 rtx prev_insn, next_insn;
10850 bool insn_added_p = false;
10851 rtx cond, *op0, *op1;
10852
10853 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10854 {
10855 /* Handle compare and branch and branch on count
10856 instructions. */
10857 rtx pattern = single_set (insn);
10858
10859 if (!pattern
10860 || SET_DEST (pattern) != pc_rtx
10861 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10862 return false;
10863
10864 cond = XEXP (SET_SRC (pattern), 0);
10865 op0 = &XEXP (cond, 0);
10866 op1 = &XEXP (cond, 1);
10867 }
10868 else if (GET_CODE (PATTERN (insn)) == SET)
10869 {
10870 rtx src, dest;
10871
10872 /* Handle normal compare instructions. */
10873 src = SET_SRC (PATTERN (insn));
10874 dest = SET_DEST (PATTERN (insn));
10875
10876 if (!REG_P (dest)
10877 || !CC_REGNO_P (REGNO (dest))
10878 || GET_CODE (src) != COMPARE)
10879 return false;
10880
10881 /* s390_swap_cmp will try to find the conditional
10882 jump when passing NULL_RTX as condition. */
10883 cond = NULL_RTX;
10884 op0 = &XEXP (src, 0);
10885 op1 = &XEXP (src, 1);
10886 }
10887 else
10888 return false;
10889
10890 if (!REG_P (*op0) || !REG_P (*op1))
10891 return false;
10892
10893 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10894 return false;
10895
10896 /* Swap the COMPARE arguments and its mask if there is a
10897 conflicting access in the previous insn. */
10898 prev_insn = prev_active_insn (insn);
10899 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10900 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10901 s390_swap_cmp (cond, op0, op1, insn);
10902
10903 /* Check if there is a conflict with the next insn. If there
10904 was no conflict with the previous insn, then swap the
10905 COMPARE arguments and its mask. If we already swapped
10906 the operands, or if swapping them would cause a conflict
10907 with the previous insn, issue a NOP after the COMPARE in
10908 order to separate the two instuctions. */
10909 next_insn = next_active_insn (insn);
10910 if (next_insn != NULL_RTX && INSN_P (next_insn)
10911 && s390_non_addr_reg_read_p (*op1, next_insn))
10912 {
10913 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10914 && s390_non_addr_reg_read_p (*op0, prev_insn))
10915 {
10916 if (REGNO (*op1) == 0)
10917 emit_insn_after (gen_nop1 (), insn);
10918 else
10919 emit_insn_after (gen_nop (), insn);
10920 insn_added_p = true;
10921 }
10922 else
10923 s390_swap_cmp (cond, op0, op1, insn);
10924 }
10925 return insn_added_p;
10926 }
10927
10928 /* Perform machine-dependent processing. */
10929
10930 static void
10931 s390_reorg (void)
10932 {
10933 bool pool_overflow = false;
10934
10935 /* Make sure all splits have been performed; splits after
10936 machine_dependent_reorg might confuse insn length counts. */
10937 split_all_insns_noflow ();
10938
10939 /* Install the main literal pool and the associated base
10940 register load insns.
10941
10942 In addition, there are two problematic situations we need
10943 to correct:
10944
10945 - the literal pool might be > 4096 bytes in size, so that
10946 some of its elements cannot be directly accessed
10947
10948 - a branch target might be > 64K away from the branch, so that
10949 it is not possible to use a PC-relative instruction.
10950
10951 To fix those, we split the single literal pool into multiple
10952 pool chunks, reloading the pool base register at various
10953 points throughout the function to ensure it always points to
10954 the pool chunk the following code expects, and / or replace
10955 PC-relative branches by absolute branches.
10956
10957 However, the two problems are interdependent: splitting the
10958 literal pool can move a branch further away from its target,
10959 causing the 64K limit to overflow, and on the other hand,
10960 replacing a PC-relative branch by an absolute branch means
10961 we need to put the branch target address into the literal
10962 pool, possibly causing it to overflow.
10963
10964 So, we loop trying to fix up both problems until we manage
10965 to satisfy both conditions at the same time. Note that the
10966 loop is guaranteed to terminate as every pass of the loop
10967 strictly decreases the total number of PC-relative branches
10968 in the function. (This is not completely true as there
10969 might be branch-over-pool insns introduced by chunkify_start.
10970 Those never need to be split however.) */
10971
10972 for (;;)
10973 {
10974 struct constant_pool *pool = NULL;
10975
10976 /* Collect the literal pool. */
10977 if (!pool_overflow)
10978 {
10979 pool = s390_mainpool_start ();
10980 if (!pool)
10981 pool_overflow = true;
10982 }
10983
10984 /* If literal pool overflowed, start to chunkify it. */
10985 if (pool_overflow)
10986 pool = s390_chunkify_start ();
10987
10988 /* Split out-of-range branches. If this has created new
10989 literal pool entries, cancel current chunk list and
10990 recompute it. zSeries machines have large branch
10991 instructions, so we never need to split a branch. */
10992 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10993 {
10994 if (pool_overflow)
10995 s390_chunkify_cancel (pool);
10996 else
10997 s390_mainpool_cancel (pool);
10998
10999 continue;
11000 }
11001
11002 /* If we made it up to here, both conditions are satisfied.
11003 Finish up literal pool related changes. */
11004 if (pool_overflow)
11005 s390_chunkify_finish (pool);
11006 else
11007 s390_mainpool_finish (pool);
11008
11009 /* We're done splitting branches. */
11010 cfun->machine->split_branches_pending_p = false;
11011 break;
11012 }
11013
11014 /* Generate out-of-pool execute target insns. */
11015 if (TARGET_CPU_ZARCH)
11016 {
11017 rtx insn, label, target;
11018
11019 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11020 {
11021 label = s390_execute_label (insn);
11022 if (!label)
11023 continue;
11024
11025 gcc_assert (label != const0_rtx);
11026
11027 target = emit_label (XEXP (label, 0));
11028 INSN_ADDRESSES_NEW (target, -1);
11029
11030 target = emit_insn (s390_execute_target (insn));
11031 INSN_ADDRESSES_NEW (target, -1);
11032 }
11033 }
11034
11035 /* Try to optimize prologue and epilogue further. */
11036 s390_optimize_prologue ();
11037
11038 /* Walk over the insns and do some >=z10 specific changes. */
11039 if (s390_tune == PROCESSOR_2097_Z10
11040 || s390_tune == PROCESSOR_2817_Z196
11041 || s390_tune == PROCESSOR_2827_ZEC12)
11042 {
11043 rtx insn;
11044 bool insn_added_p = false;
11045
11046 /* The insn lengths and addresses have to be up to date for the
11047 following manipulations. */
11048 shorten_branches (get_insns ());
11049
11050 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11051 {
11052 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
11053 continue;
11054
11055 if (JUMP_P (insn))
11056 insn_added_p |= s390_fix_long_loop_prediction (insn);
11057
11058 if ((GET_CODE (PATTERN (insn)) == PARALLEL
11059 || GET_CODE (PATTERN (insn)) == SET)
11060 && s390_tune == PROCESSOR_2097_Z10)
11061 insn_added_p |= s390_z10_optimize_cmp (insn);
11062 }
11063
11064 /* Adjust branches if we added new instructions. */
11065 if (insn_added_p)
11066 shorten_branches (get_insns ());
11067 }
11068 }
11069
11070 /* Return true if INSN is a fp load insn writing register REGNO. */
11071 static inline bool
11072 s390_fpload_toreg (rtx insn, unsigned int regno)
11073 {
11074 rtx set;
11075 enum attr_type flag = s390_safe_attr_type (insn);
11076
11077 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
11078 return false;
11079
11080 set = single_set (insn);
11081
11082 if (set == NULL_RTX)
11083 return false;
11084
11085 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
11086 return false;
11087
11088 if (REGNO (SET_DEST (set)) != regno)
11089 return false;
11090
11091 return true;
11092 }
11093
11094 /* This value describes the distance to be avoided between an
11095 aritmetic fp instruction and an fp load writing the same register.
11096 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11097 fine but the exact value has to be avoided. Otherwise the FP
11098 pipeline will throw an exception causing a major penalty. */
11099 #define Z10_EARLYLOAD_DISTANCE 7
11100
11101 /* Rearrange the ready list in order to avoid the situation described
11102 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11103 moved to the very end of the ready list. */
11104 static void
11105 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
11106 {
11107 unsigned int regno;
11108 int nready = *nready_p;
11109 rtx tmp;
11110 int i;
11111 rtx insn;
11112 rtx set;
11113 enum attr_type flag;
11114 int distance;
11115
11116 /* Skip DISTANCE - 1 active insns. */
11117 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
11118 distance > 0 && insn != NULL_RTX;
11119 distance--, insn = prev_active_insn (insn))
11120 if (CALL_P (insn) || JUMP_P (insn))
11121 return;
11122
11123 if (insn == NULL_RTX)
11124 return;
11125
11126 set = single_set (insn);
11127
11128 if (set == NULL_RTX || !REG_P (SET_DEST (set))
11129 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
11130 return;
11131
11132 flag = s390_safe_attr_type (insn);
11133
11134 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
11135 return;
11136
11137 regno = REGNO (SET_DEST (set));
11138 i = nready - 1;
11139
11140 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
11141 i--;
11142
11143 if (!i)
11144 return;
11145
11146 tmp = ready[i];
11147 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
11148 ready[0] = tmp;
11149 }
11150
11151
11152 /* The s390_sched_state variable tracks the state of the current or
11153 the last instruction group.
11154
11155 0,1,2 number of instructions scheduled in the current group
11156 3 the last group is complete - normal insns
11157 4 the last group was a cracked/expanded insn */
11158
11159 static int s390_sched_state;
11160
11161 #define S390_OOO_SCHED_STATE_NORMAL 3
11162 #define S390_OOO_SCHED_STATE_CRACKED 4
11163
11164 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11165 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11166 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11167 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11168
11169 static unsigned int
11170 s390_get_sched_attrmask (rtx insn)
11171 {
11172 unsigned int mask = 0;
11173
11174 if (get_attr_ooo_cracked (insn))
11175 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
11176 if (get_attr_ooo_expanded (insn))
11177 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
11178 if (get_attr_ooo_endgroup (insn))
11179 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
11180 if (get_attr_ooo_groupalone (insn))
11181 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
11182 return mask;
11183 }
11184
11185 /* Return the scheduling score for INSN. The higher the score the
11186 better. The score is calculated from the OOO scheduling attributes
11187 of INSN and the scheduling state s390_sched_state. */
11188 static int
11189 s390_sched_score (rtx insn)
11190 {
11191 unsigned int mask = s390_get_sched_attrmask (insn);
11192 int score = 0;
11193
11194 switch (s390_sched_state)
11195 {
11196 case 0:
11197 /* Try to put insns into the first slot which would otherwise
11198 break a group. */
11199 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11200 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11201 score += 5;
11202 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11203 score += 10;
11204 case 1:
11205 /* Prefer not cracked insns while trying to put together a
11206 group. */
11207 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11208 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11209 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11210 score += 10;
11211 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
11212 score += 5;
11213 break;
11214 case 2:
11215 /* Prefer not cracked insns while trying to put together a
11216 group. */
11217 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11218 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11219 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11220 score += 10;
11221 /* Prefer endgroup insns in the last slot. */
11222 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
11223 score += 10;
11224 break;
11225 case S390_OOO_SCHED_STATE_NORMAL:
11226 /* Prefer not cracked insns if the last was not cracked. */
11227 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11228 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
11229 score += 5;
11230 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11231 score += 10;
11232 break;
11233 case S390_OOO_SCHED_STATE_CRACKED:
11234 /* Try to keep cracked insns together to prevent them from
11235 interrupting groups. */
11236 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11237 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11238 score += 5;
11239 break;
11240 }
11241 return score;
11242 }
11243
11244 /* This function is called via hook TARGET_SCHED_REORDER before
11245 issueing one insn from list READY which contains *NREADYP entries.
11246 For target z10 it reorders load instructions to avoid early load
11247 conflicts in the floating point pipeline */
11248 static int
11249 s390_sched_reorder (FILE *file, int verbose,
11250 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
11251 {
11252 if (s390_tune == PROCESSOR_2097_Z10)
11253 if (reload_completed && *nreadyp > 1)
11254 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
11255
11256 if (s390_tune == PROCESSOR_2827_ZEC12
11257 && reload_completed
11258 && *nreadyp > 1)
11259 {
11260 int i;
11261 int last_index = *nreadyp - 1;
11262 int max_index = -1;
11263 int max_score = -1;
11264 rtx tmp;
11265
11266 /* Just move the insn with the highest score to the top (the
11267 end) of the list. A full sort is not needed since a conflict
11268 in the hazard recognition cannot happen. So the top insn in
11269 the ready list will always be taken. */
11270 for (i = last_index; i >= 0; i--)
11271 {
11272 int score;
11273
11274 if (recog_memoized (ready[i]) < 0)
11275 continue;
11276
11277 score = s390_sched_score (ready[i]);
11278 if (score > max_score)
11279 {
11280 max_score = score;
11281 max_index = i;
11282 }
11283 }
11284
11285 if (max_index != -1)
11286 {
11287 if (max_index != last_index)
11288 {
11289 tmp = ready[max_index];
11290 ready[max_index] = ready[last_index];
11291 ready[last_index] = tmp;
11292
11293 if (verbose > 5)
11294 fprintf (file,
11295 "move insn %d to the top of list\n",
11296 INSN_UID (ready[last_index]));
11297 }
11298 else if (verbose > 5)
11299 fprintf (file,
11300 "best insn %d already on top\n",
11301 INSN_UID (ready[last_index]));
11302 }
11303
11304 if (verbose > 5)
11305 {
11306 fprintf (file, "ready list ooo attributes - sched state: %d\n",
11307 s390_sched_state);
11308
11309 for (i = last_index; i >= 0; i--)
11310 {
11311 if (recog_memoized (ready[i]) < 0)
11312 continue;
11313 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
11314 s390_sched_score (ready[i]));
11315 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11316 PRINT_OOO_ATTR (ooo_cracked);
11317 PRINT_OOO_ATTR (ooo_expanded);
11318 PRINT_OOO_ATTR (ooo_endgroup);
11319 PRINT_OOO_ATTR (ooo_groupalone);
11320 #undef PRINT_OOO_ATTR
11321 fprintf (file, "\n");
11322 }
11323 }
11324 }
11325
11326 return s390_issue_rate ();
11327 }
11328
11329
11330 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11331 the scheduler has issued INSN. It stores the last issued insn into
11332 last_scheduled_insn in order to make it available for
11333 s390_sched_reorder. */
11334 static int
11335 s390_sched_variable_issue (FILE *file, int verbose, rtx insn, int more)
11336 {
11337 last_scheduled_insn = insn;
11338
11339 if (s390_tune == PROCESSOR_2827_ZEC12
11340 && reload_completed
11341 && recog_memoized (insn) >= 0)
11342 {
11343 unsigned int mask = s390_get_sched_attrmask (insn);
11344
11345 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11346 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11347 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
11348 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
11349 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11350 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11351 else
11352 {
11353 /* Only normal insns are left (mask == 0). */
11354 switch (s390_sched_state)
11355 {
11356 case 0:
11357 case 1:
11358 case 2:
11359 case S390_OOO_SCHED_STATE_NORMAL:
11360 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
11361 s390_sched_state = 1;
11362 else
11363 s390_sched_state++;
11364
11365 break;
11366 case S390_OOO_SCHED_STATE_CRACKED:
11367 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11368 break;
11369 }
11370 }
11371 if (verbose > 5)
11372 {
11373 fprintf (file, "insn %d: ", INSN_UID (insn));
11374 #define PRINT_OOO_ATTR(ATTR) \
11375 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11376 PRINT_OOO_ATTR (ooo_cracked);
11377 PRINT_OOO_ATTR (ooo_expanded);
11378 PRINT_OOO_ATTR (ooo_endgroup);
11379 PRINT_OOO_ATTR (ooo_groupalone);
11380 #undef PRINT_OOO_ATTR
11381 fprintf (file, "\n");
11382 fprintf (file, "sched state: %d\n", s390_sched_state);
11383 }
11384 }
11385
11386 if (GET_CODE (PATTERN (insn)) != USE
11387 && GET_CODE (PATTERN (insn)) != CLOBBER)
11388 return more - 1;
11389 else
11390 return more;
11391 }
11392
11393 static void
11394 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
11395 int verbose ATTRIBUTE_UNUSED,
11396 int max_ready ATTRIBUTE_UNUSED)
11397 {
11398 last_scheduled_insn = NULL_RTX;
11399 s390_sched_state = 0;
11400 }
11401
11402 /* This function checks the whole of insn X for memory references. The
11403 function always returns zero because the framework it is called
11404 from would stop recursively analyzing the insn upon a return value
11405 other than zero. The real result of this function is updating
11406 counter variable MEM_COUNT. */
11407 static int
11408 check_dpu (rtx *x, unsigned *mem_count)
11409 {
11410 if (*x != NULL_RTX && MEM_P (*x))
11411 (*mem_count)++;
11412 return 0;
11413 }
11414
11415 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
11416 a new number struct loop *loop should be unrolled if tuned for cpus with
11417 a built-in stride prefetcher.
11418 The loop is analyzed for memory accesses by calling check_dpu for
11419 each rtx of the loop. Depending on the loop_depth and the amount of
11420 memory accesses a new number <=nunroll is returned to improve the
11421 behaviour of the hardware prefetch unit. */
11422 static unsigned
11423 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11424 {
11425 basic_block *bbs;
11426 rtx insn;
11427 unsigned i;
11428 unsigned mem_count = 0;
11429
11430 if (s390_tune != PROCESSOR_2097_Z10
11431 && s390_tune != PROCESSOR_2817_Z196
11432 && s390_tune != PROCESSOR_2827_ZEC12)
11433 return nunroll;
11434
11435 /* Count the number of memory references within the loop body. */
11436 bbs = get_loop_body (loop);
11437 for (i = 0; i < loop->num_nodes; i++)
11438 {
11439 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
11440 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11441 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
11442 }
11443 free (bbs);
11444
11445 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11446 if (mem_count == 0)
11447 return nunroll;
11448
11449 switch (loop_depth(loop))
11450 {
11451 case 1:
11452 return MIN (nunroll, 28 / mem_count);
11453 case 2:
11454 return MIN (nunroll, 22 / mem_count);
11455 default:
11456 return MIN (nunroll, 16 / mem_count);
11457 }
11458 }
11459
11460 /* Initialize GCC target structure. */
11461
11462 #undef TARGET_ASM_ALIGNED_HI_OP
11463 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
11464 #undef TARGET_ASM_ALIGNED_DI_OP
11465 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
11466 #undef TARGET_ASM_INTEGER
11467 #define TARGET_ASM_INTEGER s390_assemble_integer
11468
11469 #undef TARGET_ASM_OPEN_PAREN
11470 #define TARGET_ASM_OPEN_PAREN ""
11471
11472 #undef TARGET_ASM_CLOSE_PAREN
11473 #define TARGET_ASM_CLOSE_PAREN ""
11474
11475 #undef TARGET_OPTION_OVERRIDE
11476 #define TARGET_OPTION_OVERRIDE s390_option_override
11477
11478 #undef TARGET_ENCODE_SECTION_INFO
11479 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
11480
11481 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11482 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11483
11484 #ifdef HAVE_AS_TLS
11485 #undef TARGET_HAVE_TLS
11486 #define TARGET_HAVE_TLS true
11487 #endif
11488 #undef TARGET_CANNOT_FORCE_CONST_MEM
11489 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
11490
11491 #undef TARGET_DELEGITIMIZE_ADDRESS
11492 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
11493
11494 #undef TARGET_LEGITIMIZE_ADDRESS
11495 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
11496
11497 #undef TARGET_RETURN_IN_MEMORY
11498 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
11499
11500 #undef TARGET_INIT_BUILTINS
11501 #define TARGET_INIT_BUILTINS s390_init_builtins
11502 #undef TARGET_EXPAND_BUILTIN
11503 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
11504
11505 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
11506 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
11507
11508 #undef TARGET_ASM_OUTPUT_MI_THUNK
11509 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
11510 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11511 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
11512
11513 #undef TARGET_SCHED_ADJUST_PRIORITY
11514 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
11515 #undef TARGET_SCHED_ISSUE_RATE
11516 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
11517 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
11518 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
11519
11520 #undef TARGET_SCHED_VARIABLE_ISSUE
11521 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
11522 #undef TARGET_SCHED_REORDER
11523 #define TARGET_SCHED_REORDER s390_sched_reorder
11524 #undef TARGET_SCHED_INIT
11525 #define TARGET_SCHED_INIT s390_sched_init
11526
11527 #undef TARGET_CANNOT_COPY_INSN_P
11528 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
11529 #undef TARGET_RTX_COSTS
11530 #define TARGET_RTX_COSTS s390_rtx_costs
11531 #undef TARGET_ADDRESS_COST
11532 #define TARGET_ADDRESS_COST s390_address_cost
11533 #undef TARGET_REGISTER_MOVE_COST
11534 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
11535 #undef TARGET_MEMORY_MOVE_COST
11536 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
11537
11538 #undef TARGET_MACHINE_DEPENDENT_REORG
11539 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
11540
11541 #undef TARGET_VALID_POINTER_MODE
11542 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
11543
11544 #undef TARGET_BUILD_BUILTIN_VA_LIST
11545 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
11546 #undef TARGET_EXPAND_BUILTIN_VA_START
11547 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
11548 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11549 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
11550
11551 #undef TARGET_PROMOTE_FUNCTION_MODE
11552 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
11553 #undef TARGET_PASS_BY_REFERENCE
11554 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
11555
11556 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11557 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
11558 #undef TARGET_FUNCTION_ARG
11559 #define TARGET_FUNCTION_ARG s390_function_arg
11560 #undef TARGET_FUNCTION_ARG_ADVANCE
11561 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
11562 #undef TARGET_FUNCTION_VALUE
11563 #define TARGET_FUNCTION_VALUE s390_function_value
11564 #undef TARGET_LIBCALL_VALUE
11565 #define TARGET_LIBCALL_VALUE s390_libcall_value
11566
11567 #undef TARGET_FIXED_CONDITION_CODE_REGS
11568 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
11569
11570 #undef TARGET_CC_MODES_COMPATIBLE
11571 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
11572
11573 #undef TARGET_INVALID_WITHIN_DOLOOP
11574 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
11575
11576 #ifdef HAVE_AS_TLS
11577 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
11578 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
11579 #endif
11580
11581 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11582 #undef TARGET_MANGLE_TYPE
11583 #define TARGET_MANGLE_TYPE s390_mangle_type
11584 #endif
11585
11586 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11587 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11588
11589 #undef TARGET_PREFERRED_RELOAD_CLASS
11590 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
11591
11592 #undef TARGET_SECONDARY_RELOAD
11593 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
11594
11595 #undef TARGET_LIBGCC_CMP_RETURN_MODE
11596 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
11597
11598 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
11599 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
11600
11601 #undef TARGET_LEGITIMATE_ADDRESS_P
11602 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
11603
11604 #undef TARGET_LEGITIMATE_CONSTANT_P
11605 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
11606
11607 #undef TARGET_LRA_P
11608 #define TARGET_LRA_P s390_lra_p
11609
11610 #undef TARGET_CAN_ELIMINATE
11611 #define TARGET_CAN_ELIMINATE s390_can_eliminate
11612
11613 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11614 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
11615
11616 #undef TARGET_LOOP_UNROLL_ADJUST
11617 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
11618
11619 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11620 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
11621 #undef TARGET_TRAMPOLINE_INIT
11622 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
11623
11624 #undef TARGET_UNWIND_WORD_MODE
11625 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
11626
11627 #undef TARGET_CANONICALIZE_COMPARISON
11628 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
11629
11630 struct gcc_target targetm = TARGET_INITIALIZER;
11631
11632 #include "gt-s390.h"