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target.def (conditional_register_usage): Define.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55 #include "params.h"
56 #include "cfgloop.h"
57
58
59 /* Define the specific costs for a given cpu. */
60
61 struct processor_costs
62 {
63 /* multiplication */
64 const int m; /* cost of an M instruction. */
65 const int mghi; /* cost of an MGHI instruction. */
66 const int mh; /* cost of an MH instruction. */
67 const int mhi; /* cost of an MHI instruction. */
68 const int ml; /* cost of an ML instruction. */
69 const int mr; /* cost of an MR instruction. */
70 const int ms; /* cost of an MS instruction. */
71 const int msg; /* cost of an MSG instruction. */
72 const int msgf; /* cost of an MSGF instruction. */
73 const int msgfr; /* cost of an MSGFR instruction. */
74 const int msgr; /* cost of an MSGR instruction. */
75 const int msr; /* cost of an MSR instruction. */
76 const int mult_df; /* cost of multiplication in DFmode. */
77 const int mxbr;
78 /* square root */
79 const int sqxbr; /* cost of square root in TFmode. */
80 const int sqdbr; /* cost of square root in DFmode. */
81 const int sqebr; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr; /* cost of multiply and add in DFmode. */
84 const int maebr; /* cost of multiply and add in SFmode. */
85 /* division */
86 const int dxbr;
87 const int ddbr;
88 const int debr;
89 const int dlgr;
90 const int dlr;
91 const int dr;
92 const int dsgfr;
93 const int dsgr;
94 };
95
96 const struct processor_costs *s390_cost;
97
98 static const
99 struct processor_costs z900_cost =
100 {
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
128 };
129
130 static const
131 struct processor_costs z990_cost =
132 {
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
160 };
161
162 static const
163 struct processor_costs z9_109_cost =
164 {
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
192 };
193
194 static const
195 struct processor_costs z10_cost =
196 {
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
224 };
225
226 static const
227 struct processor_costs z196_cost =
228 {
229 COSTS_N_INSNS (7), /* M */
230 COSTS_N_INSNS (5), /* MGHI */
231 COSTS_N_INSNS (5), /* MH */
232 COSTS_N_INSNS (5), /* MHI */
233 COSTS_N_INSNS (7), /* ML */
234 COSTS_N_INSNS (7), /* MR */
235 COSTS_N_INSNS (6), /* MS */
236 COSTS_N_INSNS (8), /* MSG */
237 COSTS_N_INSNS (6), /* MSGF */
238 COSTS_N_INSNS (6), /* MSGFR */
239 COSTS_N_INSNS (8), /* MSGR */
240 COSTS_N_INSNS (6), /* MSR */
241 COSTS_N_INSNS (1) , /* multiplication in DFmode */
242 COSTS_N_INSNS (40), /* MXBR B+40 */
243 COSTS_N_INSNS (100), /* SQXBR B+100 */
244 COSTS_N_INSNS (42), /* SQDBR B+42 */
245 COSTS_N_INSNS (28), /* SQEBR B+28 */
246 COSTS_N_INSNS (1), /* MADBR B */
247 COSTS_N_INSNS (1), /* MAEBR B */
248 COSTS_N_INSNS (101), /* DXBR B+101 */
249 COSTS_N_INSNS (29), /* DDBR */
250 COSTS_N_INSNS (22), /* DEBR */
251 COSTS_N_INSNS (160), /* DLGR cracked */
252 COSTS_N_INSNS (160), /* DLR cracked */
253 COSTS_N_INSNS (160), /* DR expanded */
254 COSTS_N_INSNS (160), /* DSGFR cracked */
255 COSTS_N_INSNS (160), /* DSGR cracked */
256 };
257
258 extern int reload_completed;
259
260 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
261 static rtx last_scheduled_insn;
262
263 /* Structure used to hold the components of a S/390 memory
264 address. A legitimate address on S/390 is of the general
265 form
266 base + index + displacement
267 where any of the components is optional.
268
269 base and index are registers of the class ADDR_REGS,
270 displacement is an unsigned 12-bit immediate constant. */
271
272 struct s390_address
273 {
274 rtx base;
275 rtx indx;
276 rtx disp;
277 bool pointer;
278 bool literal_pool;
279 };
280
281 /* Which cpu are we tuning for. */
282 enum processor_type s390_tune = PROCESSOR_max;
283 int s390_tune_flags;
284 /* Which instruction set architecture to use. */
285 enum processor_type s390_arch;
286 int s390_arch_flags;
287
288 HOST_WIDE_INT s390_warn_framesize = 0;
289 HOST_WIDE_INT s390_stack_size = 0;
290 HOST_WIDE_INT s390_stack_guard = 0;
291
292 /* The following structure is embedded in the machine
293 specific part of struct function. */
294
295 struct GTY (()) s390_frame_layout
296 {
297 /* Offset within stack frame. */
298 HOST_WIDE_INT gprs_offset;
299 HOST_WIDE_INT f0_offset;
300 HOST_WIDE_INT f4_offset;
301 HOST_WIDE_INT f8_offset;
302 HOST_WIDE_INT backchain_offset;
303
304 /* Number of first and last gpr where slots in the register
305 save area are reserved for. */
306 int first_save_gpr_slot;
307 int last_save_gpr_slot;
308
309 /* Number of first and last gpr to be saved, restored. */
310 int first_save_gpr;
311 int first_restore_gpr;
312 int last_save_gpr;
313 int last_restore_gpr;
314
315 /* Bits standing for floating point registers. Set, if the
316 respective register has to be saved. Starting with reg 16 (f0)
317 at the rightmost bit.
318 Bit 15 - 8 7 6 5 4 3 2 1 0
319 fpr 15 - 8 7 5 3 1 6 4 2 0
320 reg 31 - 24 23 22 21 20 19 18 17 16 */
321 unsigned int fpr_bitmap;
322
323 /* Number of floating point registers f8-f15 which must be saved. */
324 int high_fprs;
325
326 /* Set if return address needs to be saved.
327 This flag is set by s390_return_addr_rtx if it could not use
328 the initial value of r14 and therefore depends on r14 saved
329 to the stack. */
330 bool save_return_addr_p;
331
332 /* Size of stack frame. */
333 HOST_WIDE_INT frame_size;
334 };
335
336 /* Define the structure for the machine field in struct function. */
337
338 struct GTY(()) machine_function
339 {
340 struct s390_frame_layout frame_layout;
341
342 /* Literal pool base register. */
343 rtx base_reg;
344
345 /* True if we may need to perform branch splitting. */
346 bool split_branches_pending_p;
347
348 /* Some local-dynamic TLS symbol name. */
349 const char *some_ld_name;
350
351 bool has_landing_pad_p;
352 };
353
354 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
355
356 #define cfun_frame_layout (cfun->machine->frame_layout)
357 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
358 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
359 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
360 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
361 (1 << (BITNUM)))
362 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
363 (1 << (BITNUM))))
364
365 /* Number of GPRs and FPRs used for argument passing. */
366 #define GP_ARG_NUM_REG 5
367 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
368
369 /* A couple of shortcuts. */
370 #define CONST_OK_FOR_J(x) \
371 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
372 #define CONST_OK_FOR_K(x) \
373 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
374 #define CONST_OK_FOR_Os(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
376 #define CONST_OK_FOR_Op(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
378 #define CONST_OK_FOR_On(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
380
381 #define REGNO_PAIR_OK(REGNO, MODE) \
382 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
383
384 /* That's the read ahead of the dynamic branch prediction unit in
385 bytes on a z10 (or higher) CPU. */
386 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
387
388 static enum machine_mode
389 s390_libgcc_cmp_return_mode (void)
390 {
391 return TARGET_64BIT ? DImode : SImode;
392 }
393
394 static enum machine_mode
395 s390_libgcc_shift_count_mode (void)
396 {
397 return TARGET_64BIT ? DImode : SImode;
398 }
399
400 static enum machine_mode
401 s390_unwind_word_mode (void)
402 {
403 return TARGET_64BIT ? DImode : SImode;
404 }
405
406 /* Return true if the back end supports mode MODE. */
407 static bool
408 s390_scalar_mode_supported_p (enum machine_mode mode)
409 {
410 /* In contrast to the default implementation reject TImode constants on 31bit
411 TARGET_ZARCH for ABI compliance. */
412 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
413 return false;
414
415 if (DECIMAL_FLOAT_MODE_P (mode))
416 return default_decimal_float_supported_p ();
417
418 return default_scalar_mode_supported_p (mode);
419 }
420
421 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
422
423 void
424 s390_set_has_landing_pad_p (bool value)
425 {
426 cfun->machine->has_landing_pad_p = value;
427 }
428
429 /* If two condition code modes are compatible, return a condition code
430 mode which is compatible with both. Otherwise, return
431 VOIDmode. */
432
433 static enum machine_mode
434 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
435 {
436 if (m1 == m2)
437 return m1;
438
439 switch (m1)
440 {
441 case CCZmode:
442 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
443 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
444 return m2;
445 return VOIDmode;
446
447 case CCSmode:
448 case CCUmode:
449 case CCTmode:
450 case CCSRmode:
451 case CCURmode:
452 case CCZ1mode:
453 if (m2 == CCZmode)
454 return m1;
455
456 return VOIDmode;
457
458 default:
459 return VOIDmode;
460 }
461 return VOIDmode;
462 }
463
464 /* Return true if SET either doesn't set the CC register, or else
465 the source and destination have matching CC modes and that
466 CC mode is at least as constrained as REQ_MODE. */
467
468 static bool
469 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
470 {
471 enum machine_mode set_mode;
472
473 gcc_assert (GET_CODE (set) == SET);
474
475 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
476 return 1;
477
478 set_mode = GET_MODE (SET_DEST (set));
479 switch (set_mode)
480 {
481 case CCSmode:
482 case CCSRmode:
483 case CCUmode:
484 case CCURmode:
485 case CCLmode:
486 case CCL1mode:
487 case CCL2mode:
488 case CCL3mode:
489 case CCT1mode:
490 case CCT2mode:
491 case CCT3mode:
492 if (req_mode != set_mode)
493 return 0;
494 break;
495
496 case CCZmode:
497 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
498 && req_mode != CCSRmode && req_mode != CCURmode)
499 return 0;
500 break;
501
502 case CCAPmode:
503 case CCANmode:
504 if (req_mode != CCAmode)
505 return 0;
506 break;
507
508 default:
509 gcc_unreachable ();
510 }
511
512 return (GET_MODE (SET_SRC (set)) == set_mode);
513 }
514
515 /* Return true if every SET in INSN that sets the CC register
516 has source and destination with matching CC modes and that
517 CC mode is at least as constrained as REQ_MODE.
518 If REQ_MODE is VOIDmode, always return false. */
519
520 bool
521 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
522 {
523 int i;
524
525 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
526 if (req_mode == VOIDmode)
527 return false;
528
529 if (GET_CODE (PATTERN (insn)) == SET)
530 return s390_match_ccmode_set (PATTERN (insn), req_mode);
531
532 if (GET_CODE (PATTERN (insn)) == PARALLEL)
533 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
534 {
535 rtx set = XVECEXP (PATTERN (insn), 0, i);
536 if (GET_CODE (set) == SET)
537 if (!s390_match_ccmode_set (set, req_mode))
538 return false;
539 }
540
541 return true;
542 }
543
544 /* If a test-under-mask instruction can be used to implement
545 (compare (and ... OP1) OP2), return the CC mode required
546 to do that. Otherwise, return VOIDmode.
547 MIXED is true if the instruction can distinguish between
548 CC1 and CC2 for mixed selected bits (TMxx), it is false
549 if the instruction cannot (TM). */
550
551 enum machine_mode
552 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
553 {
554 int bit0, bit1;
555
556 /* ??? Fixme: should work on CONST_DOUBLE as well. */
557 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
558 return VOIDmode;
559
560 /* Selected bits all zero: CC0.
561 e.g.: int a; if ((a & (16 + 128)) == 0) */
562 if (INTVAL (op2) == 0)
563 return CCTmode;
564
565 /* Selected bits all one: CC3.
566 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
567 if (INTVAL (op2) == INTVAL (op1))
568 return CCT3mode;
569
570 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
571 int a;
572 if ((a & (16 + 128)) == 16) -> CCT1
573 if ((a & (16 + 128)) == 128) -> CCT2 */
574 if (mixed)
575 {
576 bit1 = exact_log2 (INTVAL (op2));
577 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
578 if (bit0 != -1 && bit1 != -1)
579 return bit0 > bit1 ? CCT1mode : CCT2mode;
580 }
581
582 return VOIDmode;
583 }
584
585 /* Given a comparison code OP (EQ, NE, etc.) and the operands
586 OP0 and OP1 of a COMPARE, return the mode to be used for the
587 comparison. */
588
589 enum machine_mode
590 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
591 {
592 switch (code)
593 {
594 case EQ:
595 case NE:
596 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
597 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
598 return CCAPmode;
599 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
600 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
601 return CCAPmode;
602 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
603 || GET_CODE (op1) == NEG)
604 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
605 return CCLmode;
606
607 if (GET_CODE (op0) == AND)
608 {
609 /* Check whether we can potentially do it via TM. */
610 enum machine_mode ccmode;
611 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
612 if (ccmode != VOIDmode)
613 {
614 /* Relax CCTmode to CCZmode to allow fall-back to AND
615 if that turns out to be beneficial. */
616 return ccmode == CCTmode ? CCZmode : ccmode;
617 }
618 }
619
620 if (register_operand (op0, HImode)
621 && GET_CODE (op1) == CONST_INT
622 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
623 return CCT3mode;
624 if (register_operand (op0, QImode)
625 && GET_CODE (op1) == CONST_INT
626 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
627 return CCT3mode;
628
629 return CCZmode;
630
631 case LE:
632 case LT:
633 case GE:
634 case GT:
635 /* The only overflow condition of NEG and ABS happens when
636 -INT_MAX is used as parameter, which stays negative. So
637 we have an overflow from a positive value to a negative.
638 Using CCAP mode the resulting cc can be used for comparisons. */
639 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
640 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
641 return CCAPmode;
642
643 /* If constants are involved in an add instruction it is possible to use
644 the resulting cc for comparisons with zero. Knowing the sign of the
645 constant the overflow behavior gets predictable. e.g.:
646 int a, b; if ((b = a + c) > 0)
647 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
648 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
649 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
650 {
651 if (INTVAL (XEXP((op0), 1)) < 0)
652 return CCANmode;
653 else
654 return CCAPmode;
655 }
656 /* Fall through. */
657 case UNORDERED:
658 case ORDERED:
659 case UNEQ:
660 case UNLE:
661 case UNLT:
662 case UNGE:
663 case UNGT:
664 case LTGT:
665 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
666 && GET_CODE (op1) != CONST_INT)
667 return CCSRmode;
668 return CCSmode;
669
670 case LTU:
671 case GEU:
672 if (GET_CODE (op0) == PLUS
673 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
674 return CCL1mode;
675
676 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
677 && GET_CODE (op1) != CONST_INT)
678 return CCURmode;
679 return CCUmode;
680
681 case LEU:
682 case GTU:
683 if (GET_CODE (op0) == MINUS
684 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
685 return CCL2mode;
686
687 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
688 && GET_CODE (op1) != CONST_INT)
689 return CCURmode;
690 return CCUmode;
691
692 default:
693 gcc_unreachable ();
694 }
695 }
696
697 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
698 that we can implement more efficiently. */
699
700 void
701 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
702 {
703 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
704 if ((*code == EQ || *code == NE)
705 && *op1 == const0_rtx
706 && GET_CODE (*op0) == ZERO_EXTRACT
707 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
708 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
709 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
710 {
711 rtx inner = XEXP (*op0, 0);
712 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
713 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
714 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
715
716 if (len > 0 && len < modesize
717 && pos >= 0 && pos + len <= modesize
718 && modesize <= HOST_BITS_PER_WIDE_INT)
719 {
720 unsigned HOST_WIDE_INT block;
721 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
722 block <<= modesize - pos - len;
723
724 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
725 gen_int_mode (block, GET_MODE (inner)));
726 }
727 }
728
729 /* Narrow AND of memory against immediate to enable TM. */
730 if ((*code == EQ || *code == NE)
731 && *op1 == const0_rtx
732 && GET_CODE (*op0) == AND
733 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
734 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
735 {
736 rtx inner = XEXP (*op0, 0);
737 rtx mask = XEXP (*op0, 1);
738
739 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
740 if (GET_CODE (inner) == SUBREG
741 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
742 && (GET_MODE_SIZE (GET_MODE (inner))
743 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
744 && ((INTVAL (mask)
745 & GET_MODE_MASK (GET_MODE (inner))
746 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
747 == 0))
748 inner = SUBREG_REG (inner);
749
750 /* Do not change volatile MEMs. */
751 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
752 {
753 int part = s390_single_part (XEXP (*op0, 1),
754 GET_MODE (inner), QImode, 0);
755 if (part >= 0)
756 {
757 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
758 inner = adjust_address_nv (inner, QImode, part);
759 *op0 = gen_rtx_AND (QImode, inner, mask);
760 }
761 }
762 }
763
764 /* Narrow comparisons against 0xffff to HImode if possible. */
765 if ((*code == EQ || *code == NE)
766 && GET_CODE (*op1) == CONST_INT
767 && INTVAL (*op1) == 0xffff
768 && SCALAR_INT_MODE_P (GET_MODE (*op0))
769 && (nonzero_bits (*op0, GET_MODE (*op0))
770 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
771 {
772 *op0 = gen_lowpart (HImode, *op0);
773 *op1 = constm1_rtx;
774 }
775
776 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
777 if (GET_CODE (*op0) == UNSPEC
778 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
779 && XVECLEN (*op0, 0) == 1
780 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
781 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
782 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
783 && *op1 == const0_rtx)
784 {
785 enum rtx_code new_code = UNKNOWN;
786 switch (*code)
787 {
788 case EQ: new_code = EQ; break;
789 case NE: new_code = NE; break;
790 case LT: new_code = GTU; break;
791 case GT: new_code = LTU; break;
792 case LE: new_code = GEU; break;
793 case GE: new_code = LEU; break;
794 default: break;
795 }
796
797 if (new_code != UNKNOWN)
798 {
799 *op0 = XVECEXP (*op0, 0, 0);
800 *code = new_code;
801 }
802 }
803
804 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
805 if (GET_CODE (*op0) == UNSPEC
806 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
807 && XVECLEN (*op0, 0) == 1
808 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
809 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
810 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
811 && *op1 == const0_rtx)
812 {
813 enum rtx_code new_code = UNKNOWN;
814 switch (*code)
815 {
816 case EQ: new_code = EQ; break;
817 case NE: new_code = NE; break;
818 default: break;
819 }
820
821 if (new_code != UNKNOWN)
822 {
823 *op0 = XVECEXP (*op0, 0, 0);
824 *code = new_code;
825 }
826 }
827
828 /* Simplify cascaded EQ, NE with const0_rtx. */
829 if ((*code == NE || *code == EQ)
830 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
831 && GET_MODE (*op0) == SImode
832 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
833 && REG_P (XEXP (*op0, 0))
834 && XEXP (*op0, 1) == const0_rtx
835 && *op1 == const0_rtx)
836 {
837 if ((*code == EQ && GET_CODE (*op0) == NE)
838 || (*code == NE && GET_CODE (*op0) == EQ))
839 *code = EQ;
840 else
841 *code = NE;
842 *op0 = XEXP (*op0, 0);
843 }
844
845 /* Prefer register over memory as first operand. */
846 if (MEM_P (*op0) && REG_P (*op1))
847 {
848 rtx tem = *op0; *op0 = *op1; *op1 = tem;
849 *code = swap_condition (*code);
850 }
851 }
852
853 /* Emit a compare instruction suitable to implement the comparison
854 OP0 CODE OP1. Return the correct condition RTL to be placed in
855 the IF_THEN_ELSE of the conditional branch testing the result. */
856
857 rtx
858 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
859 {
860 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
861 rtx cc;
862
863 /* Do not output a redundant compare instruction if a compare_and_swap
864 pattern already computed the result and the machine modes are compatible. */
865 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
866 {
867 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
868 == GET_MODE (op0));
869 cc = op0;
870 }
871 else
872 {
873 cc = gen_rtx_REG (mode, CC_REGNUM);
874 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
875 }
876
877 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
878 }
879
880 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
881 matches CMP.
882 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
883 conditional branch testing the result. */
884
885 static rtx
886 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
887 {
888 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
889 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
890 }
891
892 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
893 unconditional jump, else a conditional jump under condition COND. */
894
895 void
896 s390_emit_jump (rtx target, rtx cond)
897 {
898 rtx insn;
899
900 target = gen_rtx_LABEL_REF (VOIDmode, target);
901 if (cond)
902 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
903
904 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
905 emit_jump_insn (insn);
906 }
907
908 /* Return branch condition mask to implement a branch
909 specified by CODE. Return -1 for invalid comparisons. */
910
911 int
912 s390_branch_condition_mask (rtx code)
913 {
914 const int CC0 = 1 << 3;
915 const int CC1 = 1 << 2;
916 const int CC2 = 1 << 1;
917 const int CC3 = 1 << 0;
918
919 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
920 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
921 gcc_assert (XEXP (code, 1) == const0_rtx);
922
923 switch (GET_MODE (XEXP (code, 0)))
924 {
925 case CCZmode:
926 case CCZ1mode:
927 switch (GET_CODE (code))
928 {
929 case EQ: return CC0;
930 case NE: return CC1 | CC2 | CC3;
931 default: return -1;
932 }
933 break;
934
935 case CCT1mode:
936 switch (GET_CODE (code))
937 {
938 case EQ: return CC1;
939 case NE: return CC0 | CC2 | CC3;
940 default: return -1;
941 }
942 break;
943
944 case CCT2mode:
945 switch (GET_CODE (code))
946 {
947 case EQ: return CC2;
948 case NE: return CC0 | CC1 | CC3;
949 default: return -1;
950 }
951 break;
952
953 case CCT3mode:
954 switch (GET_CODE (code))
955 {
956 case EQ: return CC3;
957 case NE: return CC0 | CC1 | CC2;
958 default: return -1;
959 }
960 break;
961
962 case CCLmode:
963 switch (GET_CODE (code))
964 {
965 case EQ: return CC0 | CC2;
966 case NE: return CC1 | CC3;
967 default: return -1;
968 }
969 break;
970
971 case CCL1mode:
972 switch (GET_CODE (code))
973 {
974 case LTU: return CC2 | CC3; /* carry */
975 case GEU: return CC0 | CC1; /* no carry */
976 default: return -1;
977 }
978 break;
979
980 case CCL2mode:
981 switch (GET_CODE (code))
982 {
983 case GTU: return CC0 | CC1; /* borrow */
984 case LEU: return CC2 | CC3; /* no borrow */
985 default: return -1;
986 }
987 break;
988
989 case CCL3mode:
990 switch (GET_CODE (code))
991 {
992 case EQ: return CC0 | CC2;
993 case NE: return CC1 | CC3;
994 case LTU: return CC1;
995 case GTU: return CC3;
996 case LEU: return CC1 | CC2;
997 case GEU: return CC2 | CC3;
998 default: return -1;
999 }
1000
1001 case CCUmode:
1002 switch (GET_CODE (code))
1003 {
1004 case EQ: return CC0;
1005 case NE: return CC1 | CC2 | CC3;
1006 case LTU: return CC1;
1007 case GTU: return CC2;
1008 case LEU: return CC0 | CC1;
1009 case GEU: return CC0 | CC2;
1010 default: return -1;
1011 }
1012 break;
1013
1014 case CCURmode:
1015 switch (GET_CODE (code))
1016 {
1017 case EQ: return CC0;
1018 case NE: return CC2 | CC1 | CC3;
1019 case LTU: return CC2;
1020 case GTU: return CC1;
1021 case LEU: return CC0 | CC2;
1022 case GEU: return CC0 | CC1;
1023 default: return -1;
1024 }
1025 break;
1026
1027 case CCAPmode:
1028 switch (GET_CODE (code))
1029 {
1030 case EQ: return CC0;
1031 case NE: return CC1 | CC2 | CC3;
1032 case LT: return CC1 | CC3;
1033 case GT: return CC2;
1034 case LE: return CC0 | CC1 | CC3;
1035 case GE: return CC0 | CC2;
1036 default: return -1;
1037 }
1038 break;
1039
1040 case CCANmode:
1041 switch (GET_CODE (code))
1042 {
1043 case EQ: return CC0;
1044 case NE: return CC1 | CC2 | CC3;
1045 case LT: return CC1;
1046 case GT: return CC2 | CC3;
1047 case LE: return CC0 | CC1;
1048 case GE: return CC0 | CC2 | CC3;
1049 default: return -1;
1050 }
1051 break;
1052
1053 case CCSmode:
1054 switch (GET_CODE (code))
1055 {
1056 case EQ: return CC0;
1057 case NE: return CC1 | CC2 | CC3;
1058 case LT: return CC1;
1059 case GT: return CC2;
1060 case LE: return CC0 | CC1;
1061 case GE: return CC0 | CC2;
1062 case UNORDERED: return CC3;
1063 case ORDERED: return CC0 | CC1 | CC2;
1064 case UNEQ: return CC0 | CC3;
1065 case UNLT: return CC1 | CC3;
1066 case UNGT: return CC2 | CC3;
1067 case UNLE: return CC0 | CC1 | CC3;
1068 case UNGE: return CC0 | CC2 | CC3;
1069 case LTGT: return CC1 | CC2;
1070 default: return -1;
1071 }
1072 break;
1073
1074 case CCSRmode:
1075 switch (GET_CODE (code))
1076 {
1077 case EQ: return CC0;
1078 case NE: return CC2 | CC1 | CC3;
1079 case LT: return CC2;
1080 case GT: return CC1;
1081 case LE: return CC0 | CC2;
1082 case GE: return CC0 | CC1;
1083 case UNORDERED: return CC3;
1084 case ORDERED: return CC0 | CC2 | CC1;
1085 case UNEQ: return CC0 | CC3;
1086 case UNLT: return CC2 | CC3;
1087 case UNGT: return CC1 | CC3;
1088 case UNLE: return CC0 | CC2 | CC3;
1089 case UNGE: return CC0 | CC1 | CC3;
1090 case LTGT: return CC2 | CC1;
1091 default: return -1;
1092 }
1093 break;
1094
1095 default:
1096 return -1;
1097 }
1098 }
1099
1100
1101 /* Return branch condition mask to implement a compare and branch
1102 specified by CODE. Return -1 for invalid comparisons. */
1103
1104 int
1105 s390_compare_and_branch_condition_mask (rtx code)
1106 {
1107 const int CC0 = 1 << 3;
1108 const int CC1 = 1 << 2;
1109 const int CC2 = 1 << 1;
1110
1111 switch (GET_CODE (code))
1112 {
1113 case EQ:
1114 return CC0;
1115 case NE:
1116 return CC1 | CC2;
1117 case LT:
1118 case LTU:
1119 return CC1;
1120 case GT:
1121 case GTU:
1122 return CC2;
1123 case LE:
1124 case LEU:
1125 return CC0 | CC1;
1126 case GE:
1127 case GEU:
1128 return CC0 | CC2;
1129 default:
1130 gcc_unreachable ();
1131 }
1132 return -1;
1133 }
1134
1135 /* If INV is false, return assembler mnemonic string to implement
1136 a branch specified by CODE. If INV is true, return mnemonic
1137 for the corresponding inverted branch. */
1138
1139 static const char *
1140 s390_branch_condition_mnemonic (rtx code, int inv)
1141 {
1142 int mask;
1143
1144 static const char *const mnemonic[16] =
1145 {
1146 NULL, "o", "h", "nle",
1147 "l", "nhe", "lh", "ne",
1148 "e", "nlh", "he", "nl",
1149 "le", "nh", "no", NULL
1150 };
1151
1152 if (GET_CODE (XEXP (code, 0)) == REG
1153 && REGNO (XEXP (code, 0)) == CC_REGNUM
1154 && XEXP (code, 1) == const0_rtx)
1155 mask = s390_branch_condition_mask (code);
1156 else
1157 mask = s390_compare_and_branch_condition_mask (code);
1158
1159 gcc_assert (mask >= 0);
1160
1161 if (inv)
1162 mask ^= 15;
1163
1164 gcc_assert (mask >= 1 && mask <= 14);
1165
1166 return mnemonic[mask];
1167 }
1168
1169 /* Return the part of op which has a value different from def.
1170 The size of the part is determined by mode.
1171 Use this function only if you already know that op really
1172 contains such a part. */
1173
1174 unsigned HOST_WIDE_INT
1175 s390_extract_part (rtx op, enum machine_mode mode, int def)
1176 {
1177 unsigned HOST_WIDE_INT value = 0;
1178 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1179 int part_bits = GET_MODE_BITSIZE (mode);
1180 unsigned HOST_WIDE_INT part_mask
1181 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1182 int i;
1183
1184 for (i = 0; i < max_parts; i++)
1185 {
1186 if (i == 0)
1187 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1188 else
1189 value >>= part_bits;
1190
1191 if ((value & part_mask) != (def & part_mask))
1192 return value & part_mask;
1193 }
1194
1195 gcc_unreachable ();
1196 }
1197
1198 /* If OP is an integer constant of mode MODE with exactly one
1199 part of mode PART_MODE unequal to DEF, return the number of that
1200 part. Otherwise, return -1. */
1201
1202 int
1203 s390_single_part (rtx op,
1204 enum machine_mode mode,
1205 enum machine_mode part_mode,
1206 int def)
1207 {
1208 unsigned HOST_WIDE_INT value = 0;
1209 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1210 unsigned HOST_WIDE_INT part_mask
1211 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1212 int i, part = -1;
1213
1214 if (GET_CODE (op) != CONST_INT)
1215 return -1;
1216
1217 for (i = 0; i < n_parts; i++)
1218 {
1219 if (i == 0)
1220 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1221 else
1222 value >>= GET_MODE_BITSIZE (part_mode);
1223
1224 if ((value & part_mask) != (def & part_mask))
1225 {
1226 if (part != -1)
1227 return -1;
1228 else
1229 part = i;
1230 }
1231 }
1232 return part == -1 ? -1 : n_parts - 1 - part;
1233 }
1234
1235 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1236 bits and no other bits are set in IN. POS and LENGTH can be used
1237 to obtain the start position and the length of the bitfield.
1238
1239 POS gives the position of the first bit of the bitfield counting
1240 from the lowest order bit starting with zero. In order to use this
1241 value for S/390 instructions this has to be converted to "bits big
1242 endian" style. */
1243
1244 bool
1245 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1246 int *pos, int *length)
1247 {
1248 int tmp_pos = 0;
1249 int tmp_length = 0;
1250 int i;
1251 unsigned HOST_WIDE_INT mask = 1ULL;
1252 bool contiguous = false;
1253
1254 for (i = 0; i < size; mask <<= 1, i++)
1255 {
1256 if (contiguous)
1257 {
1258 if (mask & in)
1259 tmp_length++;
1260 else
1261 break;
1262 }
1263 else
1264 {
1265 if (mask & in)
1266 {
1267 contiguous = true;
1268 tmp_length++;
1269 }
1270 else
1271 tmp_pos++;
1272 }
1273 }
1274
1275 if (!tmp_length)
1276 return false;
1277
1278 /* Calculate a mask for all bits beyond the contiguous bits. */
1279 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1280
1281 if (mask & in)
1282 return false;
1283
1284 if (tmp_length + tmp_pos - 1 > size)
1285 return false;
1286
1287 if (length)
1288 *length = tmp_length;
1289
1290 if (pos)
1291 *pos = tmp_pos;
1292
1293 return true;
1294 }
1295
1296 /* Check whether we can (and want to) split a double-word
1297 move in mode MODE from SRC to DST into two single-word
1298 moves, moving the subword FIRST_SUBWORD first. */
1299
1300 bool
1301 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1302 {
1303 /* Floating point registers cannot be split. */
1304 if (FP_REG_P (src) || FP_REG_P (dst))
1305 return false;
1306
1307 /* We don't need to split if operands are directly accessible. */
1308 if (s_operand (src, mode) || s_operand (dst, mode))
1309 return false;
1310
1311 /* Non-offsettable memory references cannot be split. */
1312 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1313 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1314 return false;
1315
1316 /* Moving the first subword must not clobber a register
1317 needed to move the second subword. */
1318 if (register_operand (dst, mode))
1319 {
1320 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1321 if (reg_overlap_mentioned_p (subreg, src))
1322 return false;
1323 }
1324
1325 return true;
1326 }
1327
1328 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1329 and [MEM2, MEM2 + SIZE] do overlap and false
1330 otherwise. */
1331
1332 bool
1333 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1334 {
1335 rtx addr1, addr2, addr_delta;
1336 HOST_WIDE_INT delta;
1337
1338 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1339 return true;
1340
1341 if (size == 0)
1342 return false;
1343
1344 addr1 = XEXP (mem1, 0);
1345 addr2 = XEXP (mem2, 0);
1346
1347 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1348
1349 /* This overlapping check is used by peepholes merging memory block operations.
1350 Overlapping operations would otherwise be recognized by the S/390 hardware
1351 and would fall back to a slower implementation. Allowing overlapping
1352 operations would lead to slow code but not to wrong code. Therefore we are
1353 somewhat optimistic if we cannot prove that the memory blocks are
1354 overlapping.
1355 That's why we return false here although this may accept operations on
1356 overlapping memory areas. */
1357 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1358 return false;
1359
1360 delta = INTVAL (addr_delta);
1361
1362 if (delta == 0
1363 || (delta > 0 && delta < size)
1364 || (delta < 0 && -delta < size))
1365 return true;
1366
1367 return false;
1368 }
1369
1370 /* Check whether the address of memory reference MEM2 equals exactly
1371 the address of memory reference MEM1 plus DELTA. Return true if
1372 we can prove this to be the case, false otherwise. */
1373
1374 bool
1375 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1376 {
1377 rtx addr1, addr2, addr_delta;
1378
1379 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1380 return false;
1381
1382 addr1 = XEXP (mem1, 0);
1383 addr2 = XEXP (mem2, 0);
1384
1385 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1386 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1387 return false;
1388
1389 return true;
1390 }
1391
1392 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1393
1394 void
1395 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1396 rtx *operands)
1397 {
1398 enum machine_mode wmode = mode;
1399 rtx dst = operands[0];
1400 rtx src1 = operands[1];
1401 rtx src2 = operands[2];
1402 rtx op, clob, tem;
1403
1404 /* If we cannot handle the operation directly, use a temp register. */
1405 if (!s390_logical_operator_ok_p (operands))
1406 dst = gen_reg_rtx (mode);
1407
1408 /* QImode and HImode patterns make sense only if we have a destination
1409 in memory. Otherwise perform the operation in SImode. */
1410 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1411 wmode = SImode;
1412
1413 /* Widen operands if required. */
1414 if (mode != wmode)
1415 {
1416 if (GET_CODE (dst) == SUBREG
1417 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1418 dst = tem;
1419 else if (REG_P (dst))
1420 dst = gen_rtx_SUBREG (wmode, dst, 0);
1421 else
1422 dst = gen_reg_rtx (wmode);
1423
1424 if (GET_CODE (src1) == SUBREG
1425 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1426 src1 = tem;
1427 else if (GET_MODE (src1) != VOIDmode)
1428 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1429
1430 if (GET_CODE (src2) == SUBREG
1431 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1432 src2 = tem;
1433 else if (GET_MODE (src2) != VOIDmode)
1434 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1435 }
1436
1437 /* Emit the instruction. */
1438 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1439 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1440 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1441
1442 /* Fix up the destination if needed. */
1443 if (dst != operands[0])
1444 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1445 }
1446
1447 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1448
1449 bool
1450 s390_logical_operator_ok_p (rtx *operands)
1451 {
1452 /* If the destination operand is in memory, it needs to coincide
1453 with one of the source operands. After reload, it has to be
1454 the first source operand. */
1455 if (GET_CODE (operands[0]) == MEM)
1456 return rtx_equal_p (operands[0], operands[1])
1457 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1458
1459 return true;
1460 }
1461
1462 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1463 operand IMMOP to switch from SS to SI type instructions. */
1464
1465 void
1466 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1467 {
1468 int def = code == AND ? -1 : 0;
1469 HOST_WIDE_INT mask;
1470 int part;
1471
1472 gcc_assert (GET_CODE (*memop) == MEM);
1473 gcc_assert (!MEM_VOLATILE_P (*memop));
1474
1475 mask = s390_extract_part (*immop, QImode, def);
1476 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1477 gcc_assert (part >= 0);
1478
1479 *memop = adjust_address (*memop, QImode, part);
1480 *immop = gen_int_mode (mask, QImode);
1481 }
1482
1483
1484 /* How to allocate a 'struct machine_function'. */
1485
1486 static struct machine_function *
1487 s390_init_machine_status (void)
1488 {
1489 return ggc_alloc_cleared_machine_function ();
1490 }
1491
1492 /* Change optimizations to be performed, depending on the
1493 optimization level. */
1494
1495 static const struct default_options s390_option_optimization_table[] =
1496 {
1497 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
1498
1499 /* ??? There are apparently still problems with -fcaller-saves. */
1500 { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 },
1501
1502 /* Use MVCLE instructions to decrease code size if requested. */
1503 { OPT_LEVELS_SIZE, OPT_mmvcle, NULL, 1 },
1504
1505 { OPT_LEVELS_NONE, 0, NULL, 0 }
1506 };
1507
1508 /* Implement TARGET_OPTION_INIT_STRUCT. */
1509
1510 static void
1511 s390_option_init_struct (struct gcc_options *opts)
1512 {
1513 /* By default, always emit DWARF-2 unwind info. This allows debugging
1514 without maintaining a stack frame back-chain. */
1515 opts->x_flag_asynchronous_unwind_tables = 1;
1516 }
1517
1518 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1519 to the associated processor_type and processor_flags if so. */
1520
1521 static bool
1522 s390_handle_arch_option (const char *arg,
1523 enum processor_type *type,
1524 int *flags)
1525 {
1526 static struct pta
1527 {
1528 const char *const name; /* processor name or nickname. */
1529 const enum processor_type processor;
1530 const int flags; /* From enum processor_flags. */
1531 }
1532 const processor_alias_table[] =
1533 {
1534 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1535 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1536 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1537 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1538 | PF_LONG_DISPLACEMENT},
1539 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1540 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1541 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1542 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1543 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1544 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1545 {"z196", PROCESSOR_2817_Z196, PF_IEEE_FLOAT | PF_ZARCH
1546 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 },
1547 };
1548 size_t i;
1549
1550 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1551 if (strcmp (arg, processor_alias_table[i].name) == 0)
1552 {
1553 *type = processor_alias_table[i].processor;
1554 *flags = processor_alias_table[i].flags;
1555 return true;
1556 }
1557
1558 *type = PROCESSOR_max;
1559 *flags = 0;
1560 return false;
1561 }
1562
1563 /* Implement TARGET_HANDLE_OPTION. */
1564
1565 static bool
1566 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1567 {
1568 switch (code)
1569 {
1570 case OPT_march_:
1571 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1572
1573 case OPT_mstack_guard_:
1574 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1575 return false;
1576 if (exact_log2 (s390_stack_guard) == -1)
1577 error ("stack guard value must be an exact power of 2");
1578 return true;
1579
1580 case OPT_mstack_size_:
1581 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1582 return false;
1583 if (exact_log2 (s390_stack_size) == -1)
1584 error ("stack size must be an exact power of 2");
1585 return true;
1586
1587 case OPT_mtune_:
1588 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1589
1590 case OPT_mwarn_framesize_:
1591 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1592
1593 default:
1594 return true;
1595 }
1596 }
1597
1598 static void
1599 s390_option_override (void)
1600 {
1601 /* Set up function hooks. */
1602 init_machine_status = s390_init_machine_status;
1603
1604 /* Architecture mode defaults according to ABI. */
1605 if (!(target_flags_explicit & MASK_ZARCH))
1606 {
1607 if (TARGET_64BIT)
1608 target_flags |= MASK_ZARCH;
1609 else
1610 target_flags &= ~MASK_ZARCH;
1611 }
1612
1613 /* Determine processor architectural level. */
1614 if (!s390_arch_string)
1615 {
1616 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1617 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1618 }
1619
1620 /* This check is triggered when the user specified a wrong -march=
1621 string and prevents subsequent error messages from being
1622 issued. */
1623 if (s390_arch == PROCESSOR_max)
1624 return;
1625
1626 /* Determine processor to tune for. */
1627 if (s390_tune == PROCESSOR_max)
1628 {
1629 s390_tune = s390_arch;
1630 s390_tune_flags = s390_arch_flags;
1631 }
1632
1633 /* Sanity checks. */
1634 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1635 error ("z/Architecture mode not supported on %s", s390_arch_string);
1636 if (TARGET_64BIT && !TARGET_ZARCH)
1637 error ("64-bit ABI not supported in ESA/390 mode");
1638
1639 if (TARGET_HARD_DFP && !TARGET_DFP)
1640 {
1641 if (target_flags_explicit & MASK_HARD_DFP)
1642 {
1643 if (!TARGET_CPU_DFP)
1644 error ("hardware decimal floating point instructions"
1645 " not available on %s", s390_arch_string);
1646 if (!TARGET_ZARCH)
1647 error ("hardware decimal floating point instructions"
1648 " not available in ESA/390 mode");
1649 }
1650 else
1651 target_flags &= ~MASK_HARD_DFP;
1652 }
1653
1654 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1655 {
1656 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1657 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1658
1659 target_flags &= ~MASK_HARD_DFP;
1660 }
1661
1662 /* Set processor cost function. */
1663 switch (s390_tune)
1664 {
1665 case PROCESSOR_2084_Z990:
1666 s390_cost = &z990_cost;
1667 break;
1668 case PROCESSOR_2094_Z9_109:
1669 s390_cost = &z9_109_cost;
1670 break;
1671 case PROCESSOR_2097_Z10:
1672 s390_cost = &z10_cost;
1673 case PROCESSOR_2817_Z196:
1674 s390_cost = &z196_cost;
1675 break;
1676 default:
1677 s390_cost = &z900_cost;
1678 }
1679
1680 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1681 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1682 "in combination");
1683
1684 if (s390_stack_size)
1685 {
1686 if (s390_stack_guard >= s390_stack_size)
1687 error ("stack size must be greater than the stack guard value");
1688 else if (s390_stack_size > 1 << 16)
1689 error ("stack size must not be greater than 64k");
1690 }
1691 else if (s390_stack_guard)
1692 error ("-mstack-guard implies use of -mstack-size");
1693
1694 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1695 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1696 target_flags |= MASK_LONG_DOUBLE_128;
1697 #endif
1698
1699 if (s390_tune == PROCESSOR_2097_Z10
1700 || s390_tune == PROCESSOR_2817_Z196)
1701 {
1702 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1703 global_options.x_param_values,
1704 global_options_set.x_param_values);
1705 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1706 global_options.x_param_values,
1707 global_options_set.x_param_values);
1708 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1709 global_options.x_param_values,
1710 global_options_set.x_param_values);
1711 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1712 global_options.x_param_values,
1713 global_options_set.x_param_values);
1714 }
1715
1716 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1717 global_options.x_param_values,
1718 global_options_set.x_param_values);
1719 /* values for loop prefetching */
1720 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1721 global_options.x_param_values,
1722 global_options_set.x_param_values);
1723 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1724 global_options.x_param_values,
1725 global_options_set.x_param_values);
1726 /* s390 has more than 2 levels and the size is much larger. Since
1727 we are always running virtualized assume that we only get a small
1728 part of the caches above l1. */
1729 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1730 global_options.x_param_values,
1731 global_options_set.x_param_values);
1732 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1733 global_options.x_param_values,
1734 global_options_set.x_param_values);
1735 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1736 global_options.x_param_values,
1737 global_options_set.x_param_values);
1738
1739 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1740 requires the arch flags to be evaluated already. Since prefetching
1741 is beneficial on s390, we enable it if available. */
1742 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1743 flag_prefetch_loop_arrays = 1;
1744 }
1745
1746 /* Map for smallest class containing reg regno. */
1747
1748 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1749 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1750 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1751 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1752 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1753 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1754 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1755 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1756 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1757 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1758 ACCESS_REGS, ACCESS_REGS
1759 };
1760
1761 /* Return attribute type of insn. */
1762
1763 static enum attr_type
1764 s390_safe_attr_type (rtx insn)
1765 {
1766 if (recog_memoized (insn) >= 0)
1767 return get_attr_type (insn);
1768 else
1769 return TYPE_NONE;
1770 }
1771
1772 /* Return true if DISP is a valid short displacement. */
1773
1774 static bool
1775 s390_short_displacement (rtx disp)
1776 {
1777 /* No displacement is OK. */
1778 if (!disp)
1779 return true;
1780
1781 /* Without the long displacement facility we don't need to
1782 distingiush between long and short displacement. */
1783 if (!TARGET_LONG_DISPLACEMENT)
1784 return true;
1785
1786 /* Integer displacement in range. */
1787 if (GET_CODE (disp) == CONST_INT)
1788 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1789
1790 /* GOT offset is not OK, the GOT can be large. */
1791 if (GET_CODE (disp) == CONST
1792 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1793 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1794 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1795 return false;
1796
1797 /* All other symbolic constants are literal pool references,
1798 which are OK as the literal pool must be small. */
1799 if (GET_CODE (disp) == CONST)
1800 return true;
1801
1802 return false;
1803 }
1804
1805 /* Decompose a RTL expression ADDR for a memory address into
1806 its components, returned in OUT.
1807
1808 Returns false if ADDR is not a valid memory address, true
1809 otherwise. If OUT is NULL, don't return the components,
1810 but check for validity only.
1811
1812 Note: Only addresses in canonical form are recognized.
1813 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1814 canonical form so that they will be recognized. */
1815
1816 static int
1817 s390_decompose_address (rtx addr, struct s390_address *out)
1818 {
1819 HOST_WIDE_INT offset = 0;
1820 rtx base = NULL_RTX;
1821 rtx indx = NULL_RTX;
1822 rtx disp = NULL_RTX;
1823 rtx orig_disp;
1824 bool pointer = false;
1825 bool base_ptr = false;
1826 bool indx_ptr = false;
1827 bool literal_pool = false;
1828
1829 /* We may need to substitute the literal pool base register into the address
1830 below. However, at this point we do not know which register is going to
1831 be used as base, so we substitute the arg pointer register. This is going
1832 to be treated as holding a pointer below -- it shouldn't be used for any
1833 other purpose. */
1834 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1835
1836 /* Decompose address into base + index + displacement. */
1837
1838 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1839 base = addr;
1840
1841 else if (GET_CODE (addr) == PLUS)
1842 {
1843 rtx op0 = XEXP (addr, 0);
1844 rtx op1 = XEXP (addr, 1);
1845 enum rtx_code code0 = GET_CODE (op0);
1846 enum rtx_code code1 = GET_CODE (op1);
1847
1848 if (code0 == REG || code0 == UNSPEC)
1849 {
1850 if (code1 == REG || code1 == UNSPEC)
1851 {
1852 indx = op0; /* index + base */
1853 base = op1;
1854 }
1855
1856 else
1857 {
1858 base = op0; /* base + displacement */
1859 disp = op1;
1860 }
1861 }
1862
1863 else if (code0 == PLUS)
1864 {
1865 indx = XEXP (op0, 0); /* index + base + disp */
1866 base = XEXP (op0, 1);
1867 disp = op1;
1868 }
1869
1870 else
1871 {
1872 return false;
1873 }
1874 }
1875
1876 else
1877 disp = addr; /* displacement */
1878
1879 /* Extract integer part of displacement. */
1880 orig_disp = disp;
1881 if (disp)
1882 {
1883 if (GET_CODE (disp) == CONST_INT)
1884 {
1885 offset = INTVAL (disp);
1886 disp = NULL_RTX;
1887 }
1888 else if (GET_CODE (disp) == CONST
1889 && GET_CODE (XEXP (disp, 0)) == PLUS
1890 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1891 {
1892 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1893 disp = XEXP (XEXP (disp, 0), 0);
1894 }
1895 }
1896
1897 /* Strip off CONST here to avoid special case tests later. */
1898 if (disp && GET_CODE (disp) == CONST)
1899 disp = XEXP (disp, 0);
1900
1901 /* We can convert literal pool addresses to
1902 displacements by basing them off the base register. */
1903 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1904 {
1905 /* Either base or index must be free to hold the base register. */
1906 if (!base)
1907 base = fake_pool_base, literal_pool = true;
1908 else if (!indx)
1909 indx = fake_pool_base, literal_pool = true;
1910 else
1911 return false;
1912
1913 /* Mark up the displacement. */
1914 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1915 UNSPEC_LTREL_OFFSET);
1916 }
1917
1918 /* Validate base register. */
1919 if (base)
1920 {
1921 if (GET_CODE (base) == UNSPEC)
1922 switch (XINT (base, 1))
1923 {
1924 case UNSPEC_LTREF:
1925 if (!disp)
1926 disp = gen_rtx_UNSPEC (Pmode,
1927 gen_rtvec (1, XVECEXP (base, 0, 0)),
1928 UNSPEC_LTREL_OFFSET);
1929 else
1930 return false;
1931
1932 base = XVECEXP (base, 0, 1);
1933 break;
1934
1935 case UNSPEC_LTREL_BASE:
1936 if (XVECLEN (base, 0) == 1)
1937 base = fake_pool_base, literal_pool = true;
1938 else
1939 base = XVECEXP (base, 0, 1);
1940 break;
1941
1942 default:
1943 return false;
1944 }
1945
1946 if (!REG_P (base)
1947 || (GET_MODE (base) != SImode
1948 && GET_MODE (base) != Pmode))
1949 return false;
1950
1951 if (REGNO (base) == STACK_POINTER_REGNUM
1952 || REGNO (base) == FRAME_POINTER_REGNUM
1953 || ((reload_completed || reload_in_progress)
1954 && frame_pointer_needed
1955 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1956 || REGNO (base) == ARG_POINTER_REGNUM
1957 || (flag_pic
1958 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1959 pointer = base_ptr = true;
1960
1961 if ((reload_completed || reload_in_progress)
1962 && base == cfun->machine->base_reg)
1963 pointer = base_ptr = literal_pool = true;
1964 }
1965
1966 /* Validate index register. */
1967 if (indx)
1968 {
1969 if (GET_CODE (indx) == UNSPEC)
1970 switch (XINT (indx, 1))
1971 {
1972 case UNSPEC_LTREF:
1973 if (!disp)
1974 disp = gen_rtx_UNSPEC (Pmode,
1975 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1976 UNSPEC_LTREL_OFFSET);
1977 else
1978 return false;
1979
1980 indx = XVECEXP (indx, 0, 1);
1981 break;
1982
1983 case UNSPEC_LTREL_BASE:
1984 if (XVECLEN (indx, 0) == 1)
1985 indx = fake_pool_base, literal_pool = true;
1986 else
1987 indx = XVECEXP (indx, 0, 1);
1988 break;
1989
1990 default:
1991 return false;
1992 }
1993
1994 if (!REG_P (indx)
1995 || (GET_MODE (indx) != SImode
1996 && GET_MODE (indx) != Pmode))
1997 return false;
1998
1999 if (REGNO (indx) == STACK_POINTER_REGNUM
2000 || REGNO (indx) == FRAME_POINTER_REGNUM
2001 || ((reload_completed || reload_in_progress)
2002 && frame_pointer_needed
2003 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
2004 || REGNO (indx) == ARG_POINTER_REGNUM
2005 || (flag_pic
2006 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
2007 pointer = indx_ptr = true;
2008
2009 if ((reload_completed || reload_in_progress)
2010 && indx == cfun->machine->base_reg)
2011 pointer = indx_ptr = literal_pool = true;
2012 }
2013
2014 /* Prefer to use pointer as base, not index. */
2015 if (base && indx && !base_ptr
2016 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
2017 {
2018 rtx tmp = base;
2019 base = indx;
2020 indx = tmp;
2021 }
2022
2023 /* Validate displacement. */
2024 if (!disp)
2025 {
2026 /* If virtual registers are involved, the displacement will change later
2027 anyway as the virtual registers get eliminated. This could make a
2028 valid displacement invalid, but it is more likely to make an invalid
2029 displacement valid, because we sometimes access the register save area
2030 via negative offsets to one of those registers.
2031 Thus we don't check the displacement for validity here. If after
2032 elimination the displacement turns out to be invalid after all,
2033 this is fixed up by reload in any case. */
2034 if (base != arg_pointer_rtx
2035 && indx != arg_pointer_rtx
2036 && base != return_address_pointer_rtx
2037 && indx != return_address_pointer_rtx
2038 && base != frame_pointer_rtx
2039 && indx != frame_pointer_rtx
2040 && base != virtual_stack_vars_rtx
2041 && indx != virtual_stack_vars_rtx)
2042 if (!DISP_IN_RANGE (offset))
2043 return false;
2044 }
2045 else
2046 {
2047 /* All the special cases are pointers. */
2048 pointer = true;
2049
2050 /* In the small-PIC case, the linker converts @GOT
2051 and @GOTNTPOFF offsets to possible displacements. */
2052 if (GET_CODE (disp) == UNSPEC
2053 && (XINT (disp, 1) == UNSPEC_GOT
2054 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2055 && flag_pic == 1)
2056 {
2057 ;
2058 }
2059
2060 /* Accept pool label offsets. */
2061 else if (GET_CODE (disp) == UNSPEC
2062 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2063 ;
2064
2065 /* Accept literal pool references. */
2066 else if (GET_CODE (disp) == UNSPEC
2067 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2068 {
2069 orig_disp = gen_rtx_CONST (Pmode, disp);
2070 if (offset)
2071 {
2072 /* If we have an offset, make sure it does not
2073 exceed the size of the constant pool entry. */
2074 rtx sym = XVECEXP (disp, 0, 0);
2075 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2076 return false;
2077
2078 orig_disp = plus_constant (orig_disp, offset);
2079 }
2080 }
2081
2082 else
2083 return false;
2084 }
2085
2086 if (!base && !indx)
2087 pointer = true;
2088
2089 if (out)
2090 {
2091 out->base = base;
2092 out->indx = indx;
2093 out->disp = orig_disp;
2094 out->pointer = pointer;
2095 out->literal_pool = literal_pool;
2096 }
2097
2098 return true;
2099 }
2100
2101 /* Decompose a RTL expression OP for a shift count into its components,
2102 and return the base register in BASE and the offset in OFFSET.
2103
2104 Return true if OP is a valid shift count, false if not. */
2105
2106 bool
2107 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2108 {
2109 HOST_WIDE_INT off = 0;
2110
2111 /* We can have an integer constant, an address register,
2112 or a sum of the two. */
2113 if (GET_CODE (op) == CONST_INT)
2114 {
2115 off = INTVAL (op);
2116 op = NULL_RTX;
2117 }
2118 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2119 {
2120 off = INTVAL (XEXP (op, 1));
2121 op = XEXP (op, 0);
2122 }
2123 while (op && GET_CODE (op) == SUBREG)
2124 op = SUBREG_REG (op);
2125
2126 if (op && GET_CODE (op) != REG)
2127 return false;
2128
2129 if (offset)
2130 *offset = off;
2131 if (base)
2132 *base = op;
2133
2134 return true;
2135 }
2136
2137
2138 /* Return true if CODE is a valid address without index. */
2139
2140 bool
2141 s390_legitimate_address_without_index_p (rtx op)
2142 {
2143 struct s390_address addr;
2144
2145 if (!s390_decompose_address (XEXP (op, 0), &addr))
2146 return false;
2147 if (addr.indx)
2148 return false;
2149
2150 return true;
2151 }
2152
2153
2154 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2155 and return these parts in SYMREF and ADDEND. You can pass NULL in
2156 SYMREF and/or ADDEND if you are not interested in these values.
2157 Literal pool references are *not* considered symbol references. */
2158
2159 static bool
2160 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2161 {
2162 HOST_WIDE_INT tmpaddend = 0;
2163
2164 if (GET_CODE (addr) == CONST)
2165 addr = XEXP (addr, 0);
2166
2167 if (GET_CODE (addr) == PLUS)
2168 {
2169 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2170 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2171 && CONST_INT_P (XEXP (addr, 1)))
2172 {
2173 tmpaddend = INTVAL (XEXP (addr, 1));
2174 addr = XEXP (addr, 0);
2175 }
2176 else
2177 return false;
2178 }
2179 else
2180 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2181 return false;
2182
2183 if (symref)
2184 *symref = addr;
2185 if (addend)
2186 *addend = tmpaddend;
2187
2188 return true;
2189 }
2190
2191
2192 /* Return true if the address in OP is valid for constraint letter C
2193 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2194 pool MEMs should be accepted. Only the Q, R, S, T constraint
2195 letters are allowed for C. */
2196
2197 static int
2198 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2199 {
2200 struct s390_address addr;
2201 bool decomposed = false;
2202
2203 /* This check makes sure that no symbolic address (except literal
2204 pool references) are accepted by the R or T constraints. */
2205 if (s390_symref_operand_p (op, NULL, NULL))
2206 return 0;
2207
2208 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2209 if (!lit_pool_ok)
2210 {
2211 if (!s390_decompose_address (op, &addr))
2212 return 0;
2213 if (addr.literal_pool)
2214 return 0;
2215 decomposed = true;
2216 }
2217
2218 switch (c)
2219 {
2220 case 'Q': /* no index short displacement */
2221 if (!decomposed && !s390_decompose_address (op, &addr))
2222 return 0;
2223 if (addr.indx)
2224 return 0;
2225 if (!s390_short_displacement (addr.disp))
2226 return 0;
2227 break;
2228
2229 case 'R': /* with index short displacement */
2230 if (TARGET_LONG_DISPLACEMENT)
2231 {
2232 if (!decomposed && !s390_decompose_address (op, &addr))
2233 return 0;
2234 if (!s390_short_displacement (addr.disp))
2235 return 0;
2236 }
2237 /* Any invalid address here will be fixed up by reload,
2238 so accept it for the most generic constraint. */
2239 break;
2240
2241 case 'S': /* no index long displacement */
2242 if (!TARGET_LONG_DISPLACEMENT)
2243 return 0;
2244 if (!decomposed && !s390_decompose_address (op, &addr))
2245 return 0;
2246 if (addr.indx)
2247 return 0;
2248 if (s390_short_displacement (addr.disp))
2249 return 0;
2250 break;
2251
2252 case 'T': /* with index long displacement */
2253 if (!TARGET_LONG_DISPLACEMENT)
2254 return 0;
2255 /* Any invalid address here will be fixed up by reload,
2256 so accept it for the most generic constraint. */
2257 if ((decomposed || s390_decompose_address (op, &addr))
2258 && s390_short_displacement (addr.disp))
2259 return 0;
2260 break;
2261 default:
2262 return 0;
2263 }
2264 return 1;
2265 }
2266
2267
2268 /* Evaluates constraint strings described by the regular expression
2269 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2270 the constraint given in STR, or 0 else. */
2271
2272 int
2273 s390_mem_constraint (const char *str, rtx op)
2274 {
2275 char c = str[0];
2276
2277 switch (c)
2278 {
2279 case 'A':
2280 /* Check for offsettable variants of memory constraints. */
2281 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2282 return 0;
2283 if ((reload_completed || reload_in_progress)
2284 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2285 return 0;
2286 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2287 case 'B':
2288 /* Check for non-literal-pool variants of memory constraints. */
2289 if (!MEM_P (op))
2290 return 0;
2291 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2292 case 'Q':
2293 case 'R':
2294 case 'S':
2295 case 'T':
2296 if (GET_CODE (op) != MEM)
2297 return 0;
2298 return s390_check_qrst_address (c, XEXP (op, 0), true);
2299 case 'U':
2300 return (s390_check_qrst_address ('Q', op, true)
2301 || s390_check_qrst_address ('R', op, true));
2302 case 'W':
2303 return (s390_check_qrst_address ('S', op, true)
2304 || s390_check_qrst_address ('T', op, true));
2305 case 'Y':
2306 /* Simply check for the basic form of a shift count. Reload will
2307 take care of making sure we have a proper base register. */
2308 if (!s390_decompose_shift_count (op, NULL, NULL))
2309 return 0;
2310 break;
2311 case 'Z':
2312 return s390_check_qrst_address (str[1], op, true);
2313 default:
2314 return 0;
2315 }
2316 return 1;
2317 }
2318
2319
2320 /* Evaluates constraint strings starting with letter O. Input
2321 parameter C is the second letter following the "O" in the constraint
2322 string. Returns 1 if VALUE meets the respective constraint and 0
2323 otherwise. */
2324
2325 int
2326 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2327 {
2328 if (!TARGET_EXTIMM)
2329 return 0;
2330
2331 switch (c)
2332 {
2333 case 's':
2334 return trunc_int_for_mode (value, SImode) == value;
2335
2336 case 'p':
2337 return value == 0
2338 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2339
2340 case 'n':
2341 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2342
2343 default:
2344 gcc_unreachable ();
2345 }
2346 }
2347
2348
2349 /* Evaluates constraint strings starting with letter N. Parameter STR
2350 contains the letters following letter "N" in the constraint string.
2351 Returns true if VALUE matches the constraint. */
2352
2353 int
2354 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2355 {
2356 enum machine_mode mode, part_mode;
2357 int def;
2358 int part, part_goal;
2359
2360
2361 if (str[0] == 'x')
2362 part_goal = -1;
2363 else
2364 part_goal = str[0] - '0';
2365
2366 switch (str[1])
2367 {
2368 case 'Q':
2369 part_mode = QImode;
2370 break;
2371 case 'H':
2372 part_mode = HImode;
2373 break;
2374 case 'S':
2375 part_mode = SImode;
2376 break;
2377 default:
2378 return 0;
2379 }
2380
2381 switch (str[2])
2382 {
2383 case 'H':
2384 mode = HImode;
2385 break;
2386 case 'S':
2387 mode = SImode;
2388 break;
2389 case 'D':
2390 mode = DImode;
2391 break;
2392 default:
2393 return 0;
2394 }
2395
2396 switch (str[3])
2397 {
2398 case '0':
2399 def = 0;
2400 break;
2401 case 'F':
2402 def = -1;
2403 break;
2404 default:
2405 return 0;
2406 }
2407
2408 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2409 return 0;
2410
2411 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2412 if (part < 0)
2413 return 0;
2414 if (part_goal != -1 && part_goal != part)
2415 return 0;
2416
2417 return 1;
2418 }
2419
2420
2421 /* Returns true if the input parameter VALUE is a float zero. */
2422
2423 int
2424 s390_float_const_zero_p (rtx value)
2425 {
2426 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2427 && value == CONST0_RTX (GET_MODE (value)));
2428 }
2429
2430
2431 /* Compute a (partial) cost for rtx X. Return true if the complete
2432 cost has been computed, and false if subexpressions should be
2433 scanned. In either case, *TOTAL contains the cost result.
2434 CODE contains GET_CODE (x), OUTER_CODE contains the code
2435 of the superexpression of x. */
2436
2437 static bool
2438 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2439 bool speed ATTRIBUTE_UNUSED)
2440 {
2441 switch (code)
2442 {
2443 case CONST:
2444 case CONST_INT:
2445 case LABEL_REF:
2446 case SYMBOL_REF:
2447 case CONST_DOUBLE:
2448 case MEM:
2449 *total = 0;
2450 return true;
2451
2452 case ASHIFT:
2453 case ASHIFTRT:
2454 case LSHIFTRT:
2455 case ROTATE:
2456 case ROTATERT:
2457 case AND:
2458 case IOR:
2459 case XOR:
2460 case NEG:
2461 case NOT:
2462 *total = COSTS_N_INSNS (1);
2463 return false;
2464
2465 case PLUS:
2466 case MINUS:
2467 *total = COSTS_N_INSNS (1);
2468 return false;
2469
2470 case MULT:
2471 switch (GET_MODE (x))
2472 {
2473 case SImode:
2474 {
2475 rtx left = XEXP (x, 0);
2476 rtx right = XEXP (x, 1);
2477 if (GET_CODE (right) == CONST_INT
2478 && CONST_OK_FOR_K (INTVAL (right)))
2479 *total = s390_cost->mhi;
2480 else if (GET_CODE (left) == SIGN_EXTEND)
2481 *total = s390_cost->mh;
2482 else
2483 *total = s390_cost->ms; /* msr, ms, msy */
2484 break;
2485 }
2486 case DImode:
2487 {
2488 rtx left = XEXP (x, 0);
2489 rtx right = XEXP (x, 1);
2490 if (TARGET_ZARCH)
2491 {
2492 if (GET_CODE (right) == CONST_INT
2493 && CONST_OK_FOR_K (INTVAL (right)))
2494 *total = s390_cost->mghi;
2495 else if (GET_CODE (left) == SIGN_EXTEND)
2496 *total = s390_cost->msgf;
2497 else
2498 *total = s390_cost->msg; /* msgr, msg */
2499 }
2500 else /* TARGET_31BIT */
2501 {
2502 if (GET_CODE (left) == SIGN_EXTEND
2503 && GET_CODE (right) == SIGN_EXTEND)
2504 /* mulsidi case: mr, m */
2505 *total = s390_cost->m;
2506 else if (GET_CODE (left) == ZERO_EXTEND
2507 && GET_CODE (right) == ZERO_EXTEND
2508 && TARGET_CPU_ZARCH)
2509 /* umulsidi case: ml, mlr */
2510 *total = s390_cost->ml;
2511 else
2512 /* Complex calculation is required. */
2513 *total = COSTS_N_INSNS (40);
2514 }
2515 break;
2516 }
2517 case SFmode:
2518 case DFmode:
2519 *total = s390_cost->mult_df;
2520 break;
2521 case TFmode:
2522 *total = s390_cost->mxbr;
2523 break;
2524 default:
2525 return false;
2526 }
2527 return false;
2528
2529 case FMA:
2530 switch (GET_MODE (x))
2531 {
2532 case DFmode:
2533 *total = s390_cost->madbr;
2534 break;
2535 case SFmode:
2536 *total = s390_cost->maebr;
2537 break;
2538 default:
2539 return false;
2540 }
2541 /* Negate in the third argument is free: FMSUB. */
2542 if (GET_CODE (XEXP (x, 2)) == NEG)
2543 {
2544 *total += (rtx_cost (XEXP (x, 0), FMA, speed)
2545 + rtx_cost (XEXP (x, 1), FMA, speed)
2546 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, speed));
2547 return true;
2548 }
2549 return false;
2550
2551 case UDIV:
2552 case UMOD:
2553 if (GET_MODE (x) == TImode) /* 128 bit division */
2554 *total = s390_cost->dlgr;
2555 else if (GET_MODE (x) == DImode)
2556 {
2557 rtx right = XEXP (x, 1);
2558 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2559 *total = s390_cost->dlr;
2560 else /* 64 by 64 bit division */
2561 *total = s390_cost->dlgr;
2562 }
2563 else if (GET_MODE (x) == SImode) /* 32 bit division */
2564 *total = s390_cost->dlr;
2565 return false;
2566
2567 case DIV:
2568 case MOD:
2569 if (GET_MODE (x) == DImode)
2570 {
2571 rtx right = XEXP (x, 1);
2572 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2573 if (TARGET_ZARCH)
2574 *total = s390_cost->dsgfr;
2575 else
2576 *total = s390_cost->dr;
2577 else /* 64 by 64 bit division */
2578 *total = s390_cost->dsgr;
2579 }
2580 else if (GET_MODE (x) == SImode) /* 32 bit division */
2581 *total = s390_cost->dlr;
2582 else if (GET_MODE (x) == SFmode)
2583 {
2584 *total = s390_cost->debr;
2585 }
2586 else if (GET_MODE (x) == DFmode)
2587 {
2588 *total = s390_cost->ddbr;
2589 }
2590 else if (GET_MODE (x) == TFmode)
2591 {
2592 *total = s390_cost->dxbr;
2593 }
2594 return false;
2595
2596 case SQRT:
2597 if (GET_MODE (x) == SFmode)
2598 *total = s390_cost->sqebr;
2599 else if (GET_MODE (x) == DFmode)
2600 *total = s390_cost->sqdbr;
2601 else /* TFmode */
2602 *total = s390_cost->sqxbr;
2603 return false;
2604
2605 case SIGN_EXTEND:
2606 case ZERO_EXTEND:
2607 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2608 || outer_code == PLUS || outer_code == MINUS
2609 || outer_code == COMPARE)
2610 *total = 0;
2611 return false;
2612
2613 case COMPARE:
2614 *total = COSTS_N_INSNS (1);
2615 if (GET_CODE (XEXP (x, 0)) == AND
2616 && GET_CODE (XEXP (x, 1)) == CONST_INT
2617 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2618 {
2619 rtx op0 = XEXP (XEXP (x, 0), 0);
2620 rtx op1 = XEXP (XEXP (x, 0), 1);
2621 rtx op2 = XEXP (x, 1);
2622
2623 if (memory_operand (op0, GET_MODE (op0))
2624 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2625 return true;
2626 if (register_operand (op0, GET_MODE (op0))
2627 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2628 return true;
2629 }
2630 return false;
2631
2632 default:
2633 return false;
2634 }
2635 }
2636
2637 /* Return the cost of an address rtx ADDR. */
2638
2639 static int
2640 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2641 {
2642 struct s390_address ad;
2643 if (!s390_decompose_address (addr, &ad))
2644 return 1000;
2645
2646 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2647 }
2648
2649 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2650 otherwise return 0. */
2651
2652 int
2653 tls_symbolic_operand (rtx op)
2654 {
2655 if (GET_CODE (op) != SYMBOL_REF)
2656 return 0;
2657 return SYMBOL_REF_TLS_MODEL (op);
2658 }
2659 \f
2660 /* Split DImode access register reference REG (on 64-bit) into its constituent
2661 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2662 gen_highpart cannot be used as they assume all registers are word-sized,
2663 while our access registers have only half that size. */
2664
2665 void
2666 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2667 {
2668 gcc_assert (TARGET_64BIT);
2669 gcc_assert (ACCESS_REG_P (reg));
2670 gcc_assert (GET_MODE (reg) == DImode);
2671 gcc_assert (!(REGNO (reg) & 1));
2672
2673 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2674 *hi = gen_rtx_REG (SImode, REGNO (reg));
2675 }
2676
2677 /* Return true if OP contains a symbol reference */
2678
2679 bool
2680 symbolic_reference_mentioned_p (rtx op)
2681 {
2682 const char *fmt;
2683 int i;
2684
2685 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2686 return 1;
2687
2688 fmt = GET_RTX_FORMAT (GET_CODE (op));
2689 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2690 {
2691 if (fmt[i] == 'E')
2692 {
2693 int j;
2694
2695 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2696 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2697 return 1;
2698 }
2699
2700 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2701 return 1;
2702 }
2703
2704 return 0;
2705 }
2706
2707 /* Return true if OP contains a reference to a thread-local symbol. */
2708
2709 bool
2710 tls_symbolic_reference_mentioned_p (rtx op)
2711 {
2712 const char *fmt;
2713 int i;
2714
2715 if (GET_CODE (op) == SYMBOL_REF)
2716 return tls_symbolic_operand (op);
2717
2718 fmt = GET_RTX_FORMAT (GET_CODE (op));
2719 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2720 {
2721 if (fmt[i] == 'E')
2722 {
2723 int j;
2724
2725 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2726 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2727 return true;
2728 }
2729
2730 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2731 return true;
2732 }
2733
2734 return false;
2735 }
2736
2737
2738 /* Return true if OP is a legitimate general operand when
2739 generating PIC code. It is given that flag_pic is on
2740 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2741
2742 int
2743 legitimate_pic_operand_p (rtx op)
2744 {
2745 /* Accept all non-symbolic constants. */
2746 if (!SYMBOLIC_CONST (op))
2747 return 1;
2748
2749 /* Reject everything else; must be handled
2750 via emit_symbolic_move. */
2751 return 0;
2752 }
2753
2754 /* Returns true if the constant value OP is a legitimate general operand.
2755 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2756
2757 int
2758 legitimate_constant_p (rtx op)
2759 {
2760 /* Accept all non-symbolic constants. */
2761 if (!SYMBOLIC_CONST (op))
2762 return 1;
2763
2764 /* Accept immediate LARL operands. */
2765 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2766 return 1;
2767
2768 /* Thread-local symbols are never legal constants. This is
2769 so that emit_call knows that computing such addresses
2770 might require a function call. */
2771 if (TLS_SYMBOLIC_CONST (op))
2772 return 0;
2773
2774 /* In the PIC case, symbolic constants must *not* be
2775 forced into the literal pool. We accept them here,
2776 so that they will be handled by emit_symbolic_move. */
2777 if (flag_pic)
2778 return 1;
2779
2780 /* All remaining non-PIC symbolic constants are
2781 forced into the literal pool. */
2782 return 0;
2783 }
2784
2785 /* Determine if it's legal to put X into the constant pool. This
2786 is not possible if X contains the address of a symbol that is
2787 not constant (TLS) or not known at final link time (PIC). */
2788
2789 static bool
2790 s390_cannot_force_const_mem (rtx x)
2791 {
2792 switch (GET_CODE (x))
2793 {
2794 case CONST_INT:
2795 case CONST_DOUBLE:
2796 /* Accept all non-symbolic constants. */
2797 return false;
2798
2799 case LABEL_REF:
2800 /* Labels are OK iff we are non-PIC. */
2801 return flag_pic != 0;
2802
2803 case SYMBOL_REF:
2804 /* 'Naked' TLS symbol references are never OK,
2805 non-TLS symbols are OK iff we are non-PIC. */
2806 if (tls_symbolic_operand (x))
2807 return true;
2808 else
2809 return flag_pic != 0;
2810
2811 case CONST:
2812 return s390_cannot_force_const_mem (XEXP (x, 0));
2813 case PLUS:
2814 case MINUS:
2815 return s390_cannot_force_const_mem (XEXP (x, 0))
2816 || s390_cannot_force_const_mem (XEXP (x, 1));
2817
2818 case UNSPEC:
2819 switch (XINT (x, 1))
2820 {
2821 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2822 case UNSPEC_LTREL_OFFSET:
2823 case UNSPEC_GOT:
2824 case UNSPEC_GOTOFF:
2825 case UNSPEC_PLTOFF:
2826 case UNSPEC_TLSGD:
2827 case UNSPEC_TLSLDM:
2828 case UNSPEC_NTPOFF:
2829 case UNSPEC_DTPOFF:
2830 case UNSPEC_GOTNTPOFF:
2831 case UNSPEC_INDNTPOFF:
2832 return false;
2833
2834 /* If the literal pool shares the code section, be put
2835 execute template placeholders into the pool as well. */
2836 case UNSPEC_INSN:
2837 return TARGET_CPU_ZARCH;
2838
2839 default:
2840 return true;
2841 }
2842 break;
2843
2844 default:
2845 gcc_unreachable ();
2846 }
2847 }
2848
2849 /* Returns true if the constant value OP is a legitimate general
2850 operand during and after reload. The difference to
2851 legitimate_constant_p is that this function will not accept
2852 a constant that would need to be forced to the literal pool
2853 before it can be used as operand.
2854 This function accepts all constants which can be loaded directly
2855 into a GPR. */
2856
2857 bool
2858 legitimate_reload_constant_p (rtx op)
2859 {
2860 /* Accept la(y) operands. */
2861 if (GET_CODE (op) == CONST_INT
2862 && DISP_IN_RANGE (INTVAL (op)))
2863 return true;
2864
2865 /* Accept l(g)hi/l(g)fi operands. */
2866 if (GET_CODE (op) == CONST_INT
2867 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2868 return true;
2869
2870 /* Accept lliXX operands. */
2871 if (TARGET_ZARCH
2872 && GET_CODE (op) == CONST_INT
2873 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2874 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2875 return true;
2876
2877 if (TARGET_EXTIMM
2878 && GET_CODE (op) == CONST_INT
2879 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2880 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2881 return true;
2882
2883 /* Accept larl operands. */
2884 if (TARGET_CPU_ZARCH
2885 && larl_operand (op, VOIDmode))
2886 return true;
2887
2888 /* Accept floating-point zero operands that fit into a single GPR. */
2889 if (GET_CODE (op) == CONST_DOUBLE
2890 && s390_float_const_zero_p (op)
2891 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2892 return true;
2893
2894 /* Accept double-word operands that can be split. */
2895 if (GET_CODE (op) == CONST_INT
2896 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2897 {
2898 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2899 rtx hi = operand_subword (op, 0, 0, dword_mode);
2900 rtx lo = operand_subword (op, 1, 0, dword_mode);
2901 return legitimate_reload_constant_p (hi)
2902 && legitimate_reload_constant_p (lo);
2903 }
2904
2905 /* Everything else cannot be handled without reload. */
2906 return false;
2907 }
2908
2909 /* Returns true if the constant value OP is a legitimate fp operand
2910 during and after reload.
2911 This function accepts all constants which can be loaded directly
2912 into an FPR. */
2913
2914 static bool
2915 legitimate_reload_fp_constant_p (rtx op)
2916 {
2917 /* Accept floating-point zero operands if the load zero instruction
2918 can be used. */
2919 if (TARGET_Z196
2920 && GET_CODE (op) == CONST_DOUBLE
2921 && s390_float_const_zero_p (op))
2922 return true;
2923
2924 return false;
2925 }
2926
2927 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2928 return the class of reg to actually use. */
2929
2930 enum reg_class
2931 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2932 {
2933 switch (GET_CODE (op))
2934 {
2935 /* Constants we cannot reload into general registers
2936 must be forced into the literal pool. */
2937 case CONST_DOUBLE:
2938 case CONST_INT:
2939 if (reg_class_subset_p (GENERAL_REGS, rclass)
2940 && legitimate_reload_constant_p (op))
2941 return GENERAL_REGS;
2942 else if (reg_class_subset_p (ADDR_REGS, rclass)
2943 && legitimate_reload_constant_p (op))
2944 return ADDR_REGS;
2945 else if (reg_class_subset_p (FP_REGS, rclass)
2946 && legitimate_reload_fp_constant_p (op))
2947 return FP_REGS;
2948 return NO_REGS;
2949
2950 /* If a symbolic constant or a PLUS is reloaded,
2951 it is most likely being used as an address, so
2952 prefer ADDR_REGS. If 'class' is not a superset
2953 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2954 case PLUS:
2955 case LABEL_REF:
2956 case SYMBOL_REF:
2957 case CONST:
2958 if (reg_class_subset_p (ADDR_REGS, rclass))
2959 return ADDR_REGS;
2960 else
2961 return NO_REGS;
2962
2963 default:
2964 break;
2965 }
2966
2967 return rclass;
2968 }
2969
2970 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2971 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2972 aligned. */
2973
2974 bool
2975 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2976 {
2977 HOST_WIDE_INT addend;
2978 rtx symref;
2979
2980 if (!s390_symref_operand_p (addr, &symref, &addend))
2981 return false;
2982
2983 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2984 && !(addend & (alignment - 1)));
2985 }
2986
2987 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2988 operand SCRATCH is used to reload the even part of the address and
2989 adding one. */
2990
2991 void
2992 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2993 {
2994 HOST_WIDE_INT addend;
2995 rtx symref;
2996
2997 if (!s390_symref_operand_p (addr, &symref, &addend))
2998 gcc_unreachable ();
2999
3000 if (!(addend & 1))
3001 /* Easy case. The addend is even so larl will do fine. */
3002 emit_move_insn (reg, addr);
3003 else
3004 {
3005 /* We can leave the scratch register untouched if the target
3006 register is a valid base register. */
3007 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3008 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3009 scratch = reg;
3010
3011 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3012 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3013
3014 if (addend != 1)
3015 emit_move_insn (scratch,
3016 gen_rtx_CONST (Pmode,
3017 gen_rtx_PLUS (Pmode, symref,
3018 GEN_INT (addend - 1))));
3019 else
3020 emit_move_insn (scratch, symref);
3021
3022 /* Increment the address using la in order to avoid clobbering cc. */
3023 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3024 }
3025 }
3026
3027 /* Generate what is necessary to move between REG and MEM using
3028 SCRATCH. The direction is given by TOMEM. */
3029
3030 void
3031 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3032 {
3033 /* Reload might have pulled a constant out of the literal pool.
3034 Force it back in. */
3035 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3036 || GET_CODE (mem) == CONST)
3037 mem = force_const_mem (GET_MODE (reg), mem);
3038
3039 gcc_assert (MEM_P (mem));
3040
3041 /* For a load from memory we can leave the scratch register
3042 untouched if the target register is a valid base register. */
3043 if (!tomem
3044 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3045 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3046 && GET_MODE (reg) == GET_MODE (scratch))
3047 scratch = reg;
3048
3049 /* Load address into scratch register. Since we can't have a
3050 secondary reload for a secondary reload we have to cover the case
3051 where larl would need a secondary reload here as well. */
3052 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3053
3054 /* Now we can use a standard load/store to do the move. */
3055 if (tomem)
3056 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3057 else
3058 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3059 }
3060
3061 /* Inform reload about cases where moving X with a mode MODE to a register in
3062 RCLASS requires an extra scratch or immediate register. Return the class
3063 needed for the immediate register. */
3064
3065 static reg_class_t
3066 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3067 enum machine_mode mode, secondary_reload_info *sri)
3068 {
3069 enum reg_class rclass = (enum reg_class) rclass_i;
3070
3071 /* Intermediate register needed. */
3072 if (reg_classes_intersect_p (CC_REGS, rclass))
3073 return GENERAL_REGS;
3074
3075 if (TARGET_Z10)
3076 {
3077 /* On z10 several optimizer steps may generate larl operands with
3078 an odd addend. */
3079 if (in_p
3080 && s390_symref_operand_p (x, NULL, NULL)
3081 && mode == Pmode
3082 && !s390_check_symref_alignment (x, 2))
3083 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3084 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3085
3086 /* On z10 we need a scratch register when moving QI, TI or floating
3087 point mode values from or to a memory location with a SYMBOL_REF
3088 or if the symref addend of a SI or DI move is not aligned to the
3089 width of the access. */
3090 if (MEM_P (x)
3091 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3092 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3093 || (!TARGET_ZARCH && mode == DImode)
3094 || ((mode == HImode || mode == SImode || mode == DImode)
3095 && (!s390_check_symref_alignment (XEXP (x, 0),
3096 GET_MODE_SIZE (mode))))))
3097 {
3098 #define __SECONDARY_RELOAD_CASE(M,m) \
3099 case M##mode: \
3100 if (TARGET_64BIT) \
3101 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3102 CODE_FOR_reload##m##di_tomem_z10; \
3103 else \
3104 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3105 CODE_FOR_reload##m##si_tomem_z10; \
3106 break;
3107
3108 switch (GET_MODE (x))
3109 {
3110 __SECONDARY_RELOAD_CASE (QI, qi);
3111 __SECONDARY_RELOAD_CASE (HI, hi);
3112 __SECONDARY_RELOAD_CASE (SI, si);
3113 __SECONDARY_RELOAD_CASE (DI, di);
3114 __SECONDARY_RELOAD_CASE (TI, ti);
3115 __SECONDARY_RELOAD_CASE (SF, sf);
3116 __SECONDARY_RELOAD_CASE (DF, df);
3117 __SECONDARY_RELOAD_CASE (TF, tf);
3118 __SECONDARY_RELOAD_CASE (SD, sd);
3119 __SECONDARY_RELOAD_CASE (DD, dd);
3120 __SECONDARY_RELOAD_CASE (TD, td);
3121
3122 default:
3123 gcc_unreachable ();
3124 }
3125 #undef __SECONDARY_RELOAD_CASE
3126 }
3127 }
3128
3129 /* We need a scratch register when loading a PLUS expression which
3130 is not a legitimate operand of the LOAD ADDRESS instruction. */
3131 if (in_p && s390_plus_operand (x, mode))
3132 sri->icode = (TARGET_64BIT ?
3133 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3134
3135 /* Performing a multiword move from or to memory we have to make sure the
3136 second chunk in memory is addressable without causing a displacement
3137 overflow. If that would be the case we calculate the address in
3138 a scratch register. */
3139 if (MEM_P (x)
3140 && GET_CODE (XEXP (x, 0)) == PLUS
3141 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3142 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3143 + GET_MODE_SIZE (mode) - 1))
3144 {
3145 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3146 in a s_operand address since we may fallback to lm/stm. So we only
3147 have to care about overflows in the b+i+d case. */
3148 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3149 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3150 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3151 /* For FP_REGS no lm/stm is available so this check is triggered
3152 for displacement overflows in b+i+d and b+d like addresses. */
3153 || (reg_classes_intersect_p (FP_REGS, rclass)
3154 && s390_class_max_nregs (FP_REGS, mode) > 1))
3155 {
3156 if (in_p)
3157 sri->icode = (TARGET_64BIT ?
3158 CODE_FOR_reloaddi_nonoffmem_in :
3159 CODE_FOR_reloadsi_nonoffmem_in);
3160 else
3161 sri->icode = (TARGET_64BIT ?
3162 CODE_FOR_reloaddi_nonoffmem_out :
3163 CODE_FOR_reloadsi_nonoffmem_out);
3164 }
3165 }
3166
3167 /* A scratch address register is needed when a symbolic constant is
3168 copied to r0 compiling with -fPIC. In other cases the target
3169 register might be used as temporary (see legitimize_pic_address). */
3170 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3171 sri->icode = (TARGET_64BIT ?
3172 CODE_FOR_reloaddi_PIC_addr :
3173 CODE_FOR_reloadsi_PIC_addr);
3174
3175 /* Either scratch or no register needed. */
3176 return NO_REGS;
3177 }
3178
3179 /* Generate code to load SRC, which is PLUS that is not a
3180 legitimate operand for the LA instruction, into TARGET.
3181 SCRATCH may be used as scratch register. */
3182
3183 void
3184 s390_expand_plus_operand (rtx target, rtx src,
3185 rtx scratch)
3186 {
3187 rtx sum1, sum2;
3188 struct s390_address ad;
3189
3190 /* src must be a PLUS; get its two operands. */
3191 gcc_assert (GET_CODE (src) == PLUS);
3192 gcc_assert (GET_MODE (src) == Pmode);
3193
3194 /* Check if any of the two operands is already scheduled
3195 for replacement by reload. This can happen e.g. when
3196 float registers occur in an address. */
3197 sum1 = find_replacement (&XEXP (src, 0));
3198 sum2 = find_replacement (&XEXP (src, 1));
3199 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3200
3201 /* If the address is already strictly valid, there's nothing to do. */
3202 if (!s390_decompose_address (src, &ad)
3203 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3204 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3205 {
3206 /* Otherwise, one of the operands cannot be an address register;
3207 we reload its value into the scratch register. */
3208 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3209 {
3210 emit_move_insn (scratch, sum1);
3211 sum1 = scratch;
3212 }
3213 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3214 {
3215 emit_move_insn (scratch, sum2);
3216 sum2 = scratch;
3217 }
3218
3219 /* According to the way these invalid addresses are generated
3220 in reload.c, it should never happen (at least on s390) that
3221 *neither* of the PLUS components, after find_replacements
3222 was applied, is an address register. */
3223 if (sum1 == scratch && sum2 == scratch)
3224 {
3225 debug_rtx (src);
3226 gcc_unreachable ();
3227 }
3228
3229 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3230 }
3231
3232 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3233 is only ever performed on addresses, so we can mark the
3234 sum as legitimate for LA in any case. */
3235 s390_load_address (target, src);
3236 }
3237
3238
3239 /* Return true if ADDR is a valid memory address.
3240 STRICT specifies whether strict register checking applies. */
3241
3242 static bool
3243 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3244 {
3245 struct s390_address ad;
3246
3247 if (TARGET_Z10
3248 && larl_operand (addr, VOIDmode)
3249 && (mode == VOIDmode
3250 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3251 return true;
3252
3253 if (!s390_decompose_address (addr, &ad))
3254 return false;
3255
3256 if (strict)
3257 {
3258 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3259 return false;
3260
3261 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3262 return false;
3263 }
3264 else
3265 {
3266 if (ad.base
3267 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3268 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3269 return false;
3270
3271 if (ad.indx
3272 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3273 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3274 return false;
3275 }
3276 return true;
3277 }
3278
3279 /* Return true if OP is a valid operand for the LA instruction.
3280 In 31-bit, we need to prove that the result is used as an
3281 address, as LA performs only a 31-bit addition. */
3282
3283 bool
3284 legitimate_la_operand_p (rtx op)
3285 {
3286 struct s390_address addr;
3287 if (!s390_decompose_address (op, &addr))
3288 return false;
3289
3290 return (TARGET_64BIT || addr.pointer);
3291 }
3292
3293 /* Return true if it is valid *and* preferable to use LA to
3294 compute the sum of OP1 and OP2. */
3295
3296 bool
3297 preferred_la_operand_p (rtx op1, rtx op2)
3298 {
3299 struct s390_address addr;
3300
3301 if (op2 != const0_rtx)
3302 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3303
3304 if (!s390_decompose_address (op1, &addr))
3305 return false;
3306 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3307 return false;
3308 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3309 return false;
3310
3311 /* Avoid LA instructions with index register on z196; it is
3312 preferable to use regular add instructions when possible. */
3313 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3314 return false;
3315
3316 if (!TARGET_64BIT && !addr.pointer)
3317 return false;
3318
3319 if (addr.pointer)
3320 return true;
3321
3322 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3323 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3324 return true;
3325
3326 return false;
3327 }
3328
3329 /* Emit a forced load-address operation to load SRC into DST.
3330 This will use the LOAD ADDRESS instruction even in situations
3331 where legitimate_la_operand_p (SRC) returns false. */
3332
3333 void
3334 s390_load_address (rtx dst, rtx src)
3335 {
3336 if (TARGET_64BIT)
3337 emit_move_insn (dst, src);
3338 else
3339 emit_insn (gen_force_la_31 (dst, src));
3340 }
3341
3342 /* Return a legitimate reference for ORIG (an address) using the
3343 register REG. If REG is 0, a new pseudo is generated.
3344
3345 There are two types of references that must be handled:
3346
3347 1. Global data references must load the address from the GOT, via
3348 the PIC reg. An insn is emitted to do this load, and the reg is
3349 returned.
3350
3351 2. Static data references, constant pool addresses, and code labels
3352 compute the address as an offset from the GOT, whose base is in
3353 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3354 differentiate them from global data objects. The returned
3355 address is the PIC reg + an unspec constant.
3356
3357 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3358 reg also appears in the address. */
3359
3360 rtx
3361 legitimize_pic_address (rtx orig, rtx reg)
3362 {
3363 rtx addr = orig;
3364 rtx new_rtx = orig;
3365 rtx base;
3366
3367 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3368
3369 if (GET_CODE (addr) == LABEL_REF
3370 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3371 {
3372 /* This is a local symbol. */
3373 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3374 {
3375 /* Access local symbols PC-relative via LARL.
3376 This is the same as in the non-PIC case, so it is
3377 handled automatically ... */
3378 }
3379 else
3380 {
3381 /* Access local symbols relative to the GOT. */
3382
3383 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3384
3385 if (reload_in_progress || reload_completed)
3386 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3387
3388 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3389 addr = gen_rtx_CONST (Pmode, addr);
3390 addr = force_const_mem (Pmode, addr);
3391 emit_move_insn (temp, addr);
3392
3393 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3394 if (reg != 0)
3395 {
3396 s390_load_address (reg, new_rtx);
3397 new_rtx = reg;
3398 }
3399 }
3400 }
3401 else if (GET_CODE (addr) == SYMBOL_REF)
3402 {
3403 if (reg == 0)
3404 reg = gen_reg_rtx (Pmode);
3405
3406 if (flag_pic == 1)
3407 {
3408 /* Assume GOT offset < 4k. This is handled the same way
3409 in both 31- and 64-bit code (@GOT). */
3410
3411 if (reload_in_progress || reload_completed)
3412 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3413
3414 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3415 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3416 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3417 new_rtx = gen_const_mem (Pmode, new_rtx);
3418 emit_move_insn (reg, new_rtx);
3419 new_rtx = reg;
3420 }
3421 else if (TARGET_CPU_ZARCH)
3422 {
3423 /* If the GOT offset might be >= 4k, we determine the position
3424 of the GOT entry via a PC-relative LARL (@GOTENT). */
3425
3426 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3427
3428 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3429 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3430
3431 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3432 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3433 emit_move_insn (temp, new_rtx);
3434
3435 new_rtx = gen_const_mem (Pmode, temp);
3436 emit_move_insn (reg, new_rtx);
3437 new_rtx = reg;
3438 }
3439 else
3440 {
3441 /* If the GOT offset might be >= 4k, we have to load it
3442 from the literal pool (@GOT). */
3443
3444 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3445
3446 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3447 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3448
3449 if (reload_in_progress || reload_completed)
3450 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3451
3452 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3453 addr = gen_rtx_CONST (Pmode, addr);
3454 addr = force_const_mem (Pmode, addr);
3455 emit_move_insn (temp, addr);
3456
3457 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3458 new_rtx = gen_const_mem (Pmode, new_rtx);
3459 emit_move_insn (reg, new_rtx);
3460 new_rtx = reg;
3461 }
3462 }
3463 else
3464 {
3465 if (GET_CODE (addr) == CONST)
3466 {
3467 addr = XEXP (addr, 0);
3468 if (GET_CODE (addr) == UNSPEC)
3469 {
3470 gcc_assert (XVECLEN (addr, 0) == 1);
3471 switch (XINT (addr, 1))
3472 {
3473 /* If someone moved a GOT-relative UNSPEC
3474 out of the literal pool, force them back in. */
3475 case UNSPEC_GOTOFF:
3476 case UNSPEC_PLTOFF:
3477 new_rtx = force_const_mem (Pmode, orig);
3478 break;
3479
3480 /* @GOT is OK as is if small. */
3481 case UNSPEC_GOT:
3482 if (flag_pic == 2)
3483 new_rtx = force_const_mem (Pmode, orig);
3484 break;
3485
3486 /* @GOTENT is OK as is. */
3487 case UNSPEC_GOTENT:
3488 break;
3489
3490 /* @PLT is OK as is on 64-bit, must be converted to
3491 GOT-relative @PLTOFF on 31-bit. */
3492 case UNSPEC_PLT:
3493 if (!TARGET_CPU_ZARCH)
3494 {
3495 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3496
3497 if (reload_in_progress || reload_completed)
3498 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3499
3500 addr = XVECEXP (addr, 0, 0);
3501 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3502 UNSPEC_PLTOFF);
3503 addr = gen_rtx_CONST (Pmode, addr);
3504 addr = force_const_mem (Pmode, addr);
3505 emit_move_insn (temp, addr);
3506
3507 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3508 if (reg != 0)
3509 {
3510 s390_load_address (reg, new_rtx);
3511 new_rtx = reg;
3512 }
3513 }
3514 break;
3515
3516 /* Everything else cannot happen. */
3517 default:
3518 gcc_unreachable ();
3519 }
3520 }
3521 else
3522 gcc_assert (GET_CODE (addr) == PLUS);
3523 }
3524 if (GET_CODE (addr) == PLUS)
3525 {
3526 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3527
3528 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3529 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3530
3531 /* Check first to see if this is a constant offset
3532 from a local symbol reference. */
3533 if ((GET_CODE (op0) == LABEL_REF
3534 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3535 && GET_CODE (op1) == CONST_INT)
3536 {
3537 if (TARGET_CPU_ZARCH
3538 && larl_operand (op0, VOIDmode)
3539 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3540 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3541 {
3542 if (INTVAL (op1) & 1)
3543 {
3544 /* LARL can't handle odd offsets, so emit a
3545 pair of LARL and LA. */
3546 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3547
3548 if (!DISP_IN_RANGE (INTVAL (op1)))
3549 {
3550 HOST_WIDE_INT even = INTVAL (op1) - 1;
3551 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3552 op0 = gen_rtx_CONST (Pmode, op0);
3553 op1 = const1_rtx;
3554 }
3555
3556 emit_move_insn (temp, op0);
3557 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3558
3559 if (reg != 0)
3560 {
3561 s390_load_address (reg, new_rtx);
3562 new_rtx = reg;
3563 }
3564 }
3565 else
3566 {
3567 /* If the offset is even, we can just use LARL.
3568 This will happen automatically. */
3569 }
3570 }
3571 else
3572 {
3573 /* Access local symbols relative to the GOT. */
3574
3575 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3576
3577 if (reload_in_progress || reload_completed)
3578 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3579
3580 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3581 UNSPEC_GOTOFF);
3582 addr = gen_rtx_PLUS (Pmode, addr, op1);
3583 addr = gen_rtx_CONST (Pmode, addr);
3584 addr = force_const_mem (Pmode, addr);
3585 emit_move_insn (temp, addr);
3586
3587 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3588 if (reg != 0)
3589 {
3590 s390_load_address (reg, new_rtx);
3591 new_rtx = reg;
3592 }
3593 }
3594 }
3595
3596 /* Now, check whether it is a GOT relative symbol plus offset
3597 that was pulled out of the literal pool. Force it back in. */
3598
3599 else if (GET_CODE (op0) == UNSPEC
3600 && GET_CODE (op1) == CONST_INT
3601 && XINT (op0, 1) == UNSPEC_GOTOFF)
3602 {
3603 gcc_assert (XVECLEN (op0, 0) == 1);
3604
3605 new_rtx = force_const_mem (Pmode, orig);
3606 }
3607
3608 /* Otherwise, compute the sum. */
3609 else
3610 {
3611 base = legitimize_pic_address (XEXP (addr, 0), reg);
3612 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3613 base == reg ? NULL_RTX : reg);
3614 if (GET_CODE (new_rtx) == CONST_INT)
3615 new_rtx = plus_constant (base, INTVAL (new_rtx));
3616 else
3617 {
3618 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3619 {
3620 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3621 new_rtx = XEXP (new_rtx, 1);
3622 }
3623 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3624 }
3625
3626 if (GET_CODE (new_rtx) == CONST)
3627 new_rtx = XEXP (new_rtx, 0);
3628 new_rtx = force_operand (new_rtx, 0);
3629 }
3630 }
3631 }
3632 return new_rtx;
3633 }
3634
3635 /* Load the thread pointer into a register. */
3636
3637 rtx
3638 s390_get_thread_pointer (void)
3639 {
3640 rtx tp = gen_reg_rtx (Pmode);
3641
3642 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3643 mark_reg_pointer (tp, BITS_PER_WORD);
3644
3645 return tp;
3646 }
3647
3648 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3649 in s390_tls_symbol which always refers to __tls_get_offset.
3650 The returned offset is written to RESULT_REG and an USE rtx is
3651 generated for TLS_CALL. */
3652
3653 static GTY(()) rtx s390_tls_symbol;
3654
3655 static void
3656 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3657 {
3658 rtx insn;
3659
3660 gcc_assert (flag_pic);
3661
3662 if (!s390_tls_symbol)
3663 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3664
3665 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3666 gen_rtx_REG (Pmode, RETURN_REGNUM));
3667
3668 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3669 RTL_CONST_CALL_P (insn) = 1;
3670 }
3671
3672 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3673 this (thread-local) address. REG may be used as temporary. */
3674
3675 static rtx
3676 legitimize_tls_address (rtx addr, rtx reg)
3677 {
3678 rtx new_rtx, tls_call, temp, base, r2, insn;
3679
3680 if (GET_CODE (addr) == SYMBOL_REF)
3681 switch (tls_symbolic_operand (addr))
3682 {
3683 case TLS_MODEL_GLOBAL_DYNAMIC:
3684 start_sequence ();
3685 r2 = gen_rtx_REG (Pmode, 2);
3686 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3687 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3688 new_rtx = force_const_mem (Pmode, new_rtx);
3689 emit_move_insn (r2, new_rtx);
3690 s390_emit_tls_call_insn (r2, tls_call);
3691 insn = get_insns ();
3692 end_sequence ();
3693
3694 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3695 temp = gen_reg_rtx (Pmode);
3696 emit_libcall_block (insn, temp, r2, new_rtx);
3697
3698 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3699 if (reg != 0)
3700 {
3701 s390_load_address (reg, new_rtx);
3702 new_rtx = reg;
3703 }
3704 break;
3705
3706 case TLS_MODEL_LOCAL_DYNAMIC:
3707 start_sequence ();
3708 r2 = gen_rtx_REG (Pmode, 2);
3709 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3710 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3711 new_rtx = force_const_mem (Pmode, new_rtx);
3712 emit_move_insn (r2, new_rtx);
3713 s390_emit_tls_call_insn (r2, tls_call);
3714 insn = get_insns ();
3715 end_sequence ();
3716
3717 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3718 temp = gen_reg_rtx (Pmode);
3719 emit_libcall_block (insn, temp, r2, new_rtx);
3720
3721 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3722 base = gen_reg_rtx (Pmode);
3723 s390_load_address (base, new_rtx);
3724
3725 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3726 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3727 new_rtx = force_const_mem (Pmode, new_rtx);
3728 temp = gen_reg_rtx (Pmode);
3729 emit_move_insn (temp, new_rtx);
3730
3731 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3732 if (reg != 0)
3733 {
3734 s390_load_address (reg, new_rtx);
3735 new_rtx = reg;
3736 }
3737 break;
3738
3739 case TLS_MODEL_INITIAL_EXEC:
3740 if (flag_pic == 1)
3741 {
3742 /* Assume GOT offset < 4k. This is handled the same way
3743 in both 31- and 64-bit code. */
3744
3745 if (reload_in_progress || reload_completed)
3746 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3747
3748 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3749 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3750 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3751 new_rtx = gen_const_mem (Pmode, new_rtx);
3752 temp = gen_reg_rtx (Pmode);
3753 emit_move_insn (temp, new_rtx);
3754 }
3755 else if (TARGET_CPU_ZARCH)
3756 {
3757 /* If the GOT offset might be >= 4k, we determine the position
3758 of the GOT entry via a PC-relative LARL. */
3759
3760 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3761 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3762 temp = gen_reg_rtx (Pmode);
3763 emit_move_insn (temp, new_rtx);
3764
3765 new_rtx = gen_const_mem (Pmode, temp);
3766 temp = gen_reg_rtx (Pmode);
3767 emit_move_insn (temp, new_rtx);
3768 }
3769 else if (flag_pic)
3770 {
3771 /* If the GOT offset might be >= 4k, we have to load it
3772 from the literal pool. */
3773
3774 if (reload_in_progress || reload_completed)
3775 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3776
3777 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3778 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3779 new_rtx = force_const_mem (Pmode, new_rtx);
3780 temp = gen_reg_rtx (Pmode);
3781 emit_move_insn (temp, new_rtx);
3782
3783 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3784 new_rtx = gen_const_mem (Pmode, new_rtx);
3785
3786 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3787 temp = gen_reg_rtx (Pmode);
3788 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3789 }
3790 else
3791 {
3792 /* In position-dependent code, load the absolute address of
3793 the GOT entry from the literal pool. */
3794
3795 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3796 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3797 new_rtx = force_const_mem (Pmode, new_rtx);
3798 temp = gen_reg_rtx (Pmode);
3799 emit_move_insn (temp, new_rtx);
3800
3801 new_rtx = temp;
3802 new_rtx = gen_const_mem (Pmode, new_rtx);
3803 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3804 temp = gen_reg_rtx (Pmode);
3805 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3806 }
3807
3808 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3809 if (reg != 0)
3810 {
3811 s390_load_address (reg, new_rtx);
3812 new_rtx = reg;
3813 }
3814 break;
3815
3816 case TLS_MODEL_LOCAL_EXEC:
3817 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3818 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3819 new_rtx = force_const_mem (Pmode, new_rtx);
3820 temp = gen_reg_rtx (Pmode);
3821 emit_move_insn (temp, new_rtx);
3822
3823 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3824 if (reg != 0)
3825 {
3826 s390_load_address (reg, new_rtx);
3827 new_rtx = reg;
3828 }
3829 break;
3830
3831 default:
3832 gcc_unreachable ();
3833 }
3834
3835 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3836 {
3837 switch (XINT (XEXP (addr, 0), 1))
3838 {
3839 case UNSPEC_INDNTPOFF:
3840 gcc_assert (TARGET_CPU_ZARCH);
3841 new_rtx = addr;
3842 break;
3843
3844 default:
3845 gcc_unreachable ();
3846 }
3847 }
3848
3849 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3850 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3851 {
3852 new_rtx = XEXP (XEXP (addr, 0), 0);
3853 if (GET_CODE (new_rtx) != SYMBOL_REF)
3854 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3855
3856 new_rtx = legitimize_tls_address (new_rtx, reg);
3857 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3858 new_rtx = force_operand (new_rtx, 0);
3859 }
3860
3861 else
3862 gcc_unreachable (); /* for now ... */
3863
3864 return new_rtx;
3865 }
3866
3867 /* Emit insns making the address in operands[1] valid for a standard
3868 move to operands[0]. operands[1] is replaced by an address which
3869 should be used instead of the former RTX to emit the move
3870 pattern. */
3871
3872 void
3873 emit_symbolic_move (rtx *operands)
3874 {
3875 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3876
3877 if (GET_CODE (operands[0]) == MEM)
3878 operands[1] = force_reg (Pmode, operands[1]);
3879 else if (TLS_SYMBOLIC_CONST (operands[1]))
3880 operands[1] = legitimize_tls_address (operands[1], temp);
3881 else if (flag_pic)
3882 operands[1] = legitimize_pic_address (operands[1], temp);
3883 }
3884
3885 /* Try machine-dependent ways of modifying an illegitimate address X
3886 to be legitimate. If we find one, return the new, valid address.
3887
3888 OLDX is the address as it was before break_out_memory_refs was called.
3889 In some cases it is useful to look at this to decide what needs to be done.
3890
3891 MODE is the mode of the operand pointed to by X.
3892
3893 When -fpic is used, special handling is needed for symbolic references.
3894 See comments by legitimize_pic_address for details. */
3895
3896 static rtx
3897 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3898 enum machine_mode mode ATTRIBUTE_UNUSED)
3899 {
3900 rtx constant_term = const0_rtx;
3901
3902 if (TLS_SYMBOLIC_CONST (x))
3903 {
3904 x = legitimize_tls_address (x, 0);
3905
3906 if (s390_legitimate_address_p (mode, x, FALSE))
3907 return x;
3908 }
3909 else if (GET_CODE (x) == PLUS
3910 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3911 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3912 {
3913 return x;
3914 }
3915 else if (flag_pic)
3916 {
3917 if (SYMBOLIC_CONST (x)
3918 || (GET_CODE (x) == PLUS
3919 && (SYMBOLIC_CONST (XEXP (x, 0))
3920 || SYMBOLIC_CONST (XEXP (x, 1)))))
3921 x = legitimize_pic_address (x, 0);
3922
3923 if (s390_legitimate_address_p (mode, x, FALSE))
3924 return x;
3925 }
3926
3927 x = eliminate_constant_term (x, &constant_term);
3928
3929 /* Optimize loading of large displacements by splitting them
3930 into the multiple of 4K and the rest; this allows the
3931 former to be CSE'd if possible.
3932
3933 Don't do this if the displacement is added to a register
3934 pointing into the stack frame, as the offsets will
3935 change later anyway. */
3936
3937 if (GET_CODE (constant_term) == CONST_INT
3938 && !TARGET_LONG_DISPLACEMENT
3939 && !DISP_IN_RANGE (INTVAL (constant_term))
3940 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3941 {
3942 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3943 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3944
3945 rtx temp = gen_reg_rtx (Pmode);
3946 rtx val = force_operand (GEN_INT (upper), temp);
3947 if (val != temp)
3948 emit_move_insn (temp, val);
3949
3950 x = gen_rtx_PLUS (Pmode, x, temp);
3951 constant_term = GEN_INT (lower);
3952 }
3953
3954 if (GET_CODE (x) == PLUS)
3955 {
3956 if (GET_CODE (XEXP (x, 0)) == REG)
3957 {
3958 rtx temp = gen_reg_rtx (Pmode);
3959 rtx val = force_operand (XEXP (x, 1), temp);
3960 if (val != temp)
3961 emit_move_insn (temp, val);
3962
3963 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3964 }
3965
3966 else if (GET_CODE (XEXP (x, 1)) == REG)
3967 {
3968 rtx temp = gen_reg_rtx (Pmode);
3969 rtx val = force_operand (XEXP (x, 0), temp);
3970 if (val != temp)
3971 emit_move_insn (temp, val);
3972
3973 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3974 }
3975 }
3976
3977 if (constant_term != const0_rtx)
3978 x = gen_rtx_PLUS (Pmode, x, constant_term);
3979
3980 return x;
3981 }
3982
3983 /* Try a machine-dependent way of reloading an illegitimate address AD
3984 operand. If we find one, push the reload and and return the new address.
3985
3986 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3987 and TYPE is the reload type of the current reload. */
3988
3989 rtx
3990 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3991 int opnum, int type)
3992 {
3993 if (!optimize || TARGET_LONG_DISPLACEMENT)
3994 return NULL_RTX;
3995
3996 if (GET_CODE (ad) == PLUS)
3997 {
3998 rtx tem = simplify_binary_operation (PLUS, Pmode,
3999 XEXP (ad, 0), XEXP (ad, 1));
4000 if (tem)
4001 ad = tem;
4002 }
4003
4004 if (GET_CODE (ad) == PLUS
4005 && GET_CODE (XEXP (ad, 0)) == REG
4006 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4007 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4008 {
4009 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4010 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4011 rtx cst, tem, new_rtx;
4012
4013 cst = GEN_INT (upper);
4014 if (!legitimate_reload_constant_p (cst))
4015 cst = force_const_mem (Pmode, cst);
4016
4017 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4018 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4019
4020 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4021 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4022 opnum, (enum reload_type) type);
4023 return new_rtx;
4024 }
4025
4026 return NULL_RTX;
4027 }
4028
4029 /* Emit code to move LEN bytes from DST to SRC. */
4030
4031 void
4032 s390_expand_movmem (rtx dst, rtx src, rtx len)
4033 {
4034 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4035 {
4036 if (INTVAL (len) > 0)
4037 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4038 }
4039
4040 else if (TARGET_MVCLE)
4041 {
4042 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4043 }
4044
4045 else
4046 {
4047 rtx dst_addr, src_addr, count, blocks, temp;
4048 rtx loop_start_label = gen_label_rtx ();
4049 rtx loop_end_label = gen_label_rtx ();
4050 rtx end_label = gen_label_rtx ();
4051 enum machine_mode mode;
4052
4053 mode = GET_MODE (len);
4054 if (mode == VOIDmode)
4055 mode = Pmode;
4056
4057 dst_addr = gen_reg_rtx (Pmode);
4058 src_addr = gen_reg_rtx (Pmode);
4059 count = gen_reg_rtx (mode);
4060 blocks = gen_reg_rtx (mode);
4061
4062 convert_move (count, len, 1);
4063 emit_cmp_and_jump_insns (count, const0_rtx,
4064 EQ, NULL_RTX, mode, 1, end_label);
4065
4066 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4067 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4068 dst = change_address (dst, VOIDmode, dst_addr);
4069 src = change_address (src, VOIDmode, src_addr);
4070
4071 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4072 OPTAB_DIRECT);
4073 if (temp != count)
4074 emit_move_insn (count, temp);
4075
4076 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4077 OPTAB_DIRECT);
4078 if (temp != blocks)
4079 emit_move_insn (blocks, temp);
4080
4081 emit_cmp_and_jump_insns (blocks, const0_rtx,
4082 EQ, NULL_RTX, mode, 1, loop_end_label);
4083
4084 emit_label (loop_start_label);
4085
4086 if (TARGET_Z10
4087 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4088 {
4089 rtx prefetch;
4090
4091 /* Issue a read prefetch for the +3 cache line. */
4092 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4093 const0_rtx, const0_rtx);
4094 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4095 emit_insn (prefetch);
4096
4097 /* Issue a write prefetch for the +3 cache line. */
4098 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4099 const1_rtx, const0_rtx);
4100 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4101 emit_insn (prefetch);
4102 }
4103
4104 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4105 s390_load_address (dst_addr,
4106 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4107 s390_load_address (src_addr,
4108 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4109
4110 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4111 OPTAB_DIRECT);
4112 if (temp != blocks)
4113 emit_move_insn (blocks, temp);
4114
4115 emit_cmp_and_jump_insns (blocks, const0_rtx,
4116 EQ, NULL_RTX, mode, 1, loop_end_label);
4117
4118 emit_jump (loop_start_label);
4119 emit_label (loop_end_label);
4120
4121 emit_insn (gen_movmem_short (dst, src,
4122 convert_to_mode (Pmode, count, 1)));
4123 emit_label (end_label);
4124 }
4125 }
4126
4127 /* Emit code to set LEN bytes at DST to VAL.
4128 Make use of clrmem if VAL is zero. */
4129
4130 void
4131 s390_expand_setmem (rtx dst, rtx len, rtx val)
4132 {
4133 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4134 return;
4135
4136 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4137
4138 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4139 {
4140 if (val == const0_rtx && INTVAL (len) <= 256)
4141 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4142 else
4143 {
4144 /* Initialize memory by storing the first byte. */
4145 emit_move_insn (adjust_address (dst, QImode, 0), val);
4146
4147 if (INTVAL (len) > 1)
4148 {
4149 /* Initiate 1 byte overlap move.
4150 The first byte of DST is propagated through DSTP1.
4151 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4152 DST is set to size 1 so the rest of the memory location
4153 does not count as source operand. */
4154 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4155 set_mem_size (dst, const1_rtx);
4156
4157 emit_insn (gen_movmem_short (dstp1, dst,
4158 GEN_INT (INTVAL (len) - 2)));
4159 }
4160 }
4161 }
4162
4163 else if (TARGET_MVCLE)
4164 {
4165 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4166 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4167 }
4168
4169 else
4170 {
4171 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4172 rtx loop_start_label = gen_label_rtx ();
4173 rtx loop_end_label = gen_label_rtx ();
4174 rtx end_label = gen_label_rtx ();
4175 enum machine_mode mode;
4176
4177 mode = GET_MODE (len);
4178 if (mode == VOIDmode)
4179 mode = Pmode;
4180
4181 dst_addr = gen_reg_rtx (Pmode);
4182 count = gen_reg_rtx (mode);
4183 blocks = gen_reg_rtx (mode);
4184
4185 convert_move (count, len, 1);
4186 emit_cmp_and_jump_insns (count, const0_rtx,
4187 EQ, NULL_RTX, mode, 1, end_label);
4188
4189 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4190 dst = change_address (dst, VOIDmode, dst_addr);
4191
4192 if (val == const0_rtx)
4193 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4194 OPTAB_DIRECT);
4195 else
4196 {
4197 dstp1 = adjust_address (dst, VOIDmode, 1);
4198 set_mem_size (dst, const1_rtx);
4199
4200 /* Initialize memory by storing the first byte. */
4201 emit_move_insn (adjust_address (dst, QImode, 0), val);
4202
4203 /* If count is 1 we are done. */
4204 emit_cmp_and_jump_insns (count, const1_rtx,
4205 EQ, NULL_RTX, mode, 1, end_label);
4206
4207 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4208 OPTAB_DIRECT);
4209 }
4210 if (temp != count)
4211 emit_move_insn (count, temp);
4212
4213 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4214 OPTAB_DIRECT);
4215 if (temp != blocks)
4216 emit_move_insn (blocks, temp);
4217
4218 emit_cmp_and_jump_insns (blocks, const0_rtx,
4219 EQ, NULL_RTX, mode, 1, loop_end_label);
4220
4221 emit_label (loop_start_label);
4222
4223 if (TARGET_Z10
4224 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4225 {
4226 /* Issue a write prefetch for the +4 cache line. */
4227 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4228 GEN_INT (1024)),
4229 const1_rtx, const0_rtx);
4230 emit_insn (prefetch);
4231 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4232 }
4233
4234 if (val == const0_rtx)
4235 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4236 else
4237 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4238 s390_load_address (dst_addr,
4239 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4240
4241 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4242 OPTAB_DIRECT);
4243 if (temp != blocks)
4244 emit_move_insn (blocks, temp);
4245
4246 emit_cmp_and_jump_insns (blocks, const0_rtx,
4247 EQ, NULL_RTX, mode, 1, loop_end_label);
4248
4249 emit_jump (loop_start_label);
4250 emit_label (loop_end_label);
4251
4252 if (val == const0_rtx)
4253 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4254 else
4255 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4256 emit_label (end_label);
4257 }
4258 }
4259
4260 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4261 and return the result in TARGET. */
4262
4263 void
4264 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4265 {
4266 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4267 rtx tmp;
4268
4269 /* As the result of CMPINT is inverted compared to what we need,
4270 we have to swap the operands. */
4271 tmp = op0; op0 = op1; op1 = tmp;
4272
4273 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4274 {
4275 if (INTVAL (len) > 0)
4276 {
4277 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4278 emit_insn (gen_cmpint (target, ccreg));
4279 }
4280 else
4281 emit_move_insn (target, const0_rtx);
4282 }
4283 else if (TARGET_MVCLE)
4284 {
4285 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4286 emit_insn (gen_cmpint (target, ccreg));
4287 }
4288 else
4289 {
4290 rtx addr0, addr1, count, blocks, temp;
4291 rtx loop_start_label = gen_label_rtx ();
4292 rtx loop_end_label = gen_label_rtx ();
4293 rtx end_label = gen_label_rtx ();
4294 enum machine_mode mode;
4295
4296 mode = GET_MODE (len);
4297 if (mode == VOIDmode)
4298 mode = Pmode;
4299
4300 addr0 = gen_reg_rtx (Pmode);
4301 addr1 = gen_reg_rtx (Pmode);
4302 count = gen_reg_rtx (mode);
4303 blocks = gen_reg_rtx (mode);
4304
4305 convert_move (count, len, 1);
4306 emit_cmp_and_jump_insns (count, const0_rtx,
4307 EQ, NULL_RTX, mode, 1, end_label);
4308
4309 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4310 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4311 op0 = change_address (op0, VOIDmode, addr0);
4312 op1 = change_address (op1, VOIDmode, addr1);
4313
4314 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4315 OPTAB_DIRECT);
4316 if (temp != count)
4317 emit_move_insn (count, temp);
4318
4319 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4320 OPTAB_DIRECT);
4321 if (temp != blocks)
4322 emit_move_insn (blocks, temp);
4323
4324 emit_cmp_and_jump_insns (blocks, const0_rtx,
4325 EQ, NULL_RTX, mode, 1, loop_end_label);
4326
4327 emit_label (loop_start_label);
4328
4329 if (TARGET_Z10
4330 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4331 {
4332 rtx prefetch;
4333
4334 /* Issue a read prefetch for the +2 cache line of operand 1. */
4335 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4336 const0_rtx, const0_rtx);
4337 emit_insn (prefetch);
4338 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4339
4340 /* Issue a read prefetch for the +2 cache line of operand 2. */
4341 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4342 const0_rtx, const0_rtx);
4343 emit_insn (prefetch);
4344 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4345 }
4346
4347 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4348 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4349 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4350 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4351 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4352 emit_jump_insn (temp);
4353
4354 s390_load_address (addr0,
4355 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4356 s390_load_address (addr1,
4357 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4358
4359 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4360 OPTAB_DIRECT);
4361 if (temp != blocks)
4362 emit_move_insn (blocks, temp);
4363
4364 emit_cmp_and_jump_insns (blocks, const0_rtx,
4365 EQ, NULL_RTX, mode, 1, loop_end_label);
4366
4367 emit_jump (loop_start_label);
4368 emit_label (loop_end_label);
4369
4370 emit_insn (gen_cmpmem_short (op0, op1,
4371 convert_to_mode (Pmode, count, 1)));
4372 emit_label (end_label);
4373
4374 emit_insn (gen_cmpint (target, ccreg));
4375 }
4376 }
4377
4378
4379 /* Expand conditional increment or decrement using alc/slb instructions.
4380 Should generate code setting DST to either SRC or SRC + INCREMENT,
4381 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4382 Returns true if successful, false otherwise.
4383
4384 That makes it possible to implement some if-constructs without jumps e.g.:
4385 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4386 unsigned int a, b, c;
4387 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4388 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4389 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4390 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4391
4392 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4393 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4394 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4395 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4396 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4397
4398 bool
4399 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4400 rtx dst, rtx src, rtx increment)
4401 {
4402 enum machine_mode cmp_mode;
4403 enum machine_mode cc_mode;
4404 rtx op_res;
4405 rtx insn;
4406 rtvec p;
4407 int ret;
4408
4409 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4410 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4411 cmp_mode = SImode;
4412 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4413 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4414 cmp_mode = DImode;
4415 else
4416 return false;
4417
4418 /* Try ADD LOGICAL WITH CARRY. */
4419 if (increment == const1_rtx)
4420 {
4421 /* Determine CC mode to use. */
4422 if (cmp_code == EQ || cmp_code == NE)
4423 {
4424 if (cmp_op1 != const0_rtx)
4425 {
4426 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4427 NULL_RTX, 0, OPTAB_WIDEN);
4428 cmp_op1 = const0_rtx;
4429 }
4430
4431 cmp_code = cmp_code == EQ ? LEU : GTU;
4432 }
4433
4434 if (cmp_code == LTU || cmp_code == LEU)
4435 {
4436 rtx tem = cmp_op0;
4437 cmp_op0 = cmp_op1;
4438 cmp_op1 = tem;
4439 cmp_code = swap_condition (cmp_code);
4440 }
4441
4442 switch (cmp_code)
4443 {
4444 case GTU:
4445 cc_mode = CCUmode;
4446 break;
4447
4448 case GEU:
4449 cc_mode = CCL3mode;
4450 break;
4451
4452 default:
4453 return false;
4454 }
4455
4456 /* Emit comparison instruction pattern. */
4457 if (!register_operand (cmp_op0, cmp_mode))
4458 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4459
4460 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4461 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4462 /* We use insn_invalid_p here to add clobbers if required. */
4463 ret = insn_invalid_p (emit_insn (insn));
4464 gcc_assert (!ret);
4465
4466 /* Emit ALC instruction pattern. */
4467 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4468 gen_rtx_REG (cc_mode, CC_REGNUM),
4469 const0_rtx);
4470
4471 if (src != const0_rtx)
4472 {
4473 if (!register_operand (src, GET_MODE (dst)))
4474 src = force_reg (GET_MODE (dst), src);
4475
4476 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4477 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4478 }
4479
4480 p = rtvec_alloc (2);
4481 RTVEC_ELT (p, 0) =
4482 gen_rtx_SET (VOIDmode, dst, op_res);
4483 RTVEC_ELT (p, 1) =
4484 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4485 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4486
4487 return true;
4488 }
4489
4490 /* Try SUBTRACT LOGICAL WITH BORROW. */
4491 if (increment == constm1_rtx)
4492 {
4493 /* Determine CC mode to use. */
4494 if (cmp_code == EQ || cmp_code == NE)
4495 {
4496 if (cmp_op1 != const0_rtx)
4497 {
4498 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4499 NULL_RTX, 0, OPTAB_WIDEN);
4500 cmp_op1 = const0_rtx;
4501 }
4502
4503 cmp_code = cmp_code == EQ ? LEU : GTU;
4504 }
4505
4506 if (cmp_code == GTU || cmp_code == GEU)
4507 {
4508 rtx tem = cmp_op0;
4509 cmp_op0 = cmp_op1;
4510 cmp_op1 = tem;
4511 cmp_code = swap_condition (cmp_code);
4512 }
4513
4514 switch (cmp_code)
4515 {
4516 case LEU:
4517 cc_mode = CCUmode;
4518 break;
4519
4520 case LTU:
4521 cc_mode = CCL3mode;
4522 break;
4523
4524 default:
4525 return false;
4526 }
4527
4528 /* Emit comparison instruction pattern. */
4529 if (!register_operand (cmp_op0, cmp_mode))
4530 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4531
4532 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4533 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4534 /* We use insn_invalid_p here to add clobbers if required. */
4535 ret = insn_invalid_p (emit_insn (insn));
4536 gcc_assert (!ret);
4537
4538 /* Emit SLB instruction pattern. */
4539 if (!register_operand (src, GET_MODE (dst)))
4540 src = force_reg (GET_MODE (dst), src);
4541
4542 op_res = gen_rtx_MINUS (GET_MODE (dst),
4543 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4544 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4545 gen_rtx_REG (cc_mode, CC_REGNUM),
4546 const0_rtx));
4547 p = rtvec_alloc (2);
4548 RTVEC_ELT (p, 0) =
4549 gen_rtx_SET (VOIDmode, dst, op_res);
4550 RTVEC_ELT (p, 1) =
4551 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4552 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4553
4554 return true;
4555 }
4556
4557 return false;
4558 }
4559
4560 /* Expand code for the insv template. Return true if successful. */
4561
4562 bool
4563 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4564 {
4565 int bitsize = INTVAL (op1);
4566 int bitpos = INTVAL (op2);
4567
4568 /* On z10 we can use the risbg instruction to implement insv. */
4569 if (TARGET_Z10
4570 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4571 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4572 {
4573 rtx op;
4574 rtx clobber;
4575
4576 op = gen_rtx_SET (GET_MODE(src),
4577 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4578 src);
4579 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4580 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4581
4582 return true;
4583 }
4584
4585 /* We need byte alignment. */
4586 if (bitsize % BITS_PER_UNIT)
4587 return false;
4588
4589 if (bitpos == 0
4590 && memory_operand (dest, VOIDmode)
4591 && (register_operand (src, word_mode)
4592 || const_int_operand (src, VOIDmode)))
4593 {
4594 /* Emit standard pattern if possible. */
4595 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4596 if (GET_MODE_BITSIZE (mode) == bitsize)
4597 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4598
4599 /* (set (ze (mem)) (const_int)). */
4600 else if (const_int_operand (src, VOIDmode))
4601 {
4602 int size = bitsize / BITS_PER_UNIT;
4603 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4604 GET_MODE_SIZE (word_mode) - size);
4605
4606 dest = adjust_address (dest, BLKmode, 0);
4607 set_mem_size (dest, GEN_INT (size));
4608 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4609 }
4610
4611 /* (set (ze (mem)) (reg)). */
4612 else if (register_operand (src, word_mode))
4613 {
4614 if (bitsize <= GET_MODE_BITSIZE (SImode))
4615 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4616 const0_rtx), src);
4617 else
4618 {
4619 /* Emit st,stcmh sequence. */
4620 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4621 int size = stcmh_width / BITS_PER_UNIT;
4622
4623 emit_move_insn (adjust_address (dest, SImode, size),
4624 gen_lowpart (SImode, src));
4625 set_mem_size (dest, GEN_INT (size));
4626 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4627 (stcmh_width), const0_rtx),
4628 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4629 (GET_MODE_BITSIZE (SImode))));
4630 }
4631 }
4632 else
4633 return false;
4634
4635 return true;
4636 }
4637
4638 /* (set (ze (reg)) (const_int)). */
4639 if (TARGET_ZARCH
4640 && register_operand (dest, word_mode)
4641 && (bitpos % 16) == 0
4642 && (bitsize % 16) == 0
4643 && const_int_operand (src, VOIDmode))
4644 {
4645 HOST_WIDE_INT val = INTVAL (src);
4646 int regpos = bitpos + bitsize;
4647
4648 while (regpos > bitpos)
4649 {
4650 enum machine_mode putmode;
4651 int putsize;
4652
4653 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4654 putmode = SImode;
4655 else
4656 putmode = HImode;
4657
4658 putsize = GET_MODE_BITSIZE (putmode);
4659 regpos -= putsize;
4660 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4661 GEN_INT (putsize),
4662 GEN_INT (regpos)),
4663 gen_int_mode (val, putmode));
4664 val >>= putsize;
4665 }
4666 gcc_assert (regpos == bitpos);
4667 return true;
4668 }
4669
4670 return false;
4671 }
4672
4673 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4674 register that holds VAL of mode MODE shifted by COUNT bits. */
4675
4676 static inline rtx
4677 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4678 {
4679 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4680 NULL_RTX, 1, OPTAB_DIRECT);
4681 return expand_simple_binop (SImode, ASHIFT, val, count,
4682 NULL_RTX, 1, OPTAB_DIRECT);
4683 }
4684
4685 /* Structure to hold the initial parameters for a compare_and_swap operation
4686 in HImode and QImode. */
4687
4688 struct alignment_context
4689 {
4690 rtx memsi; /* SI aligned memory location. */
4691 rtx shift; /* Bit offset with regard to lsb. */
4692 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4693 rtx modemaski; /* ~modemask */
4694 bool aligned; /* True if memory is aligned, false else. */
4695 };
4696
4697 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4698 structure AC for transparent simplifying, if the memory alignment is known
4699 to be at least 32bit. MEM is the memory location for the actual operation
4700 and MODE its mode. */
4701
4702 static void
4703 init_alignment_context (struct alignment_context *ac, rtx mem,
4704 enum machine_mode mode)
4705 {
4706 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4707 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4708
4709 if (ac->aligned)
4710 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4711 else
4712 {
4713 /* Alignment is unknown. */
4714 rtx byteoffset, addr, align;
4715
4716 /* Force the address into a register. */
4717 addr = force_reg (Pmode, XEXP (mem, 0));
4718
4719 /* Align it to SImode. */
4720 align = expand_simple_binop (Pmode, AND, addr,
4721 GEN_INT (-GET_MODE_SIZE (SImode)),
4722 NULL_RTX, 1, OPTAB_DIRECT);
4723 /* Generate MEM. */
4724 ac->memsi = gen_rtx_MEM (SImode, align);
4725 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4726 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4727 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4728
4729 /* Calculate shiftcount. */
4730 byteoffset = expand_simple_binop (Pmode, AND, addr,
4731 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4732 NULL_RTX, 1, OPTAB_DIRECT);
4733 /* As we already have some offset, evaluate the remaining distance. */
4734 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4735 NULL_RTX, 1, OPTAB_DIRECT);
4736
4737 }
4738 /* Shift is the byte count, but we need the bitcount. */
4739 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4740 NULL_RTX, 1, OPTAB_DIRECT);
4741 /* Calculate masks. */
4742 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4743 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4744 NULL_RTX, 1, OPTAB_DIRECT);
4745 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4746 }
4747
4748 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4749 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4750 to set if CMP == MEM.
4751 CMP is never in memory for compare_and_swap_cc because
4752 expand_bool_compare_and_swap puts it into a register for later compare. */
4753
4754 void
4755 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4756 {
4757 struct alignment_context ac;
4758 rtx cmpv, newv, val, resv, cc;
4759 rtx res = gen_reg_rtx (SImode);
4760 rtx csloop = gen_label_rtx ();
4761 rtx csend = gen_label_rtx ();
4762
4763 gcc_assert (register_operand (target, VOIDmode));
4764 gcc_assert (MEM_P (mem));
4765
4766 init_alignment_context (&ac, mem, mode);
4767
4768 /* Shift the values to the correct bit positions. */
4769 if (!(ac.aligned && MEM_P (cmp)))
4770 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4771 if (!(ac.aligned && MEM_P (new_rtx)))
4772 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4773
4774 /* Load full word. Subsequent loads are performed by CS. */
4775 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4776 NULL_RTX, 1, OPTAB_DIRECT);
4777
4778 /* Start CS loop. */
4779 emit_label (csloop);
4780 /* val = "<mem>00..0<mem>"
4781 * cmp = "00..0<cmp>00..0"
4782 * new = "00..0<new>00..0"
4783 */
4784
4785 /* Patch cmp and new with val at correct position. */
4786 if (ac.aligned && MEM_P (cmp))
4787 {
4788 cmpv = force_reg (SImode, val);
4789 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4790 }
4791 else
4792 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4793 NULL_RTX, 1, OPTAB_DIRECT));
4794 if (ac.aligned && MEM_P (new_rtx))
4795 {
4796 newv = force_reg (SImode, val);
4797 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4798 }
4799 else
4800 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4801 NULL_RTX, 1, OPTAB_DIRECT));
4802
4803 /* Jump to end if we're done (likely?). */
4804 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4805 cmpv, newv));
4806
4807 /* Check for changes outside mode. */
4808 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4809 NULL_RTX, 1, OPTAB_DIRECT);
4810 cc = s390_emit_compare (NE, resv, val);
4811 emit_move_insn (val, resv);
4812 /* Loop internal if so. */
4813 s390_emit_jump (csloop, cc);
4814
4815 emit_label (csend);
4816
4817 /* Return the correct part of the bitfield. */
4818 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4819 NULL_RTX, 1, OPTAB_DIRECT), 1);
4820 }
4821
4822 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4823 and VAL the value to play with. If AFTER is true then store the value
4824 MEM holds after the operation, if AFTER is false then store the value MEM
4825 holds before the operation. If TARGET is zero then discard that value, else
4826 store it to TARGET. */
4827
4828 void
4829 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4830 rtx target, rtx mem, rtx val, bool after)
4831 {
4832 struct alignment_context ac;
4833 rtx cmp;
4834 rtx new_rtx = gen_reg_rtx (SImode);
4835 rtx orig = gen_reg_rtx (SImode);
4836 rtx csloop = gen_label_rtx ();
4837
4838 gcc_assert (!target || register_operand (target, VOIDmode));
4839 gcc_assert (MEM_P (mem));
4840
4841 init_alignment_context (&ac, mem, mode);
4842
4843 /* Shift val to the correct bit positions.
4844 Preserve "icm", but prevent "ex icm". */
4845 if (!(ac.aligned && code == SET && MEM_P (val)))
4846 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4847
4848 /* Further preparation insns. */
4849 if (code == PLUS || code == MINUS)
4850 emit_move_insn (orig, val);
4851 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4852 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4853 NULL_RTX, 1, OPTAB_DIRECT);
4854
4855 /* Load full word. Subsequent loads are performed by CS. */
4856 cmp = force_reg (SImode, ac.memsi);
4857
4858 /* Start CS loop. */
4859 emit_label (csloop);
4860 emit_move_insn (new_rtx, cmp);
4861
4862 /* Patch new with val at correct position. */
4863 switch (code)
4864 {
4865 case PLUS:
4866 case MINUS:
4867 val = expand_simple_binop (SImode, code, new_rtx, orig,
4868 NULL_RTX, 1, OPTAB_DIRECT);
4869 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4870 NULL_RTX, 1, OPTAB_DIRECT);
4871 /* FALLTHRU */
4872 case SET:
4873 if (ac.aligned && MEM_P (val))
4874 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4875 else
4876 {
4877 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4878 NULL_RTX, 1, OPTAB_DIRECT);
4879 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4880 NULL_RTX, 1, OPTAB_DIRECT);
4881 }
4882 break;
4883 case AND:
4884 case IOR:
4885 case XOR:
4886 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4887 NULL_RTX, 1, OPTAB_DIRECT);
4888 break;
4889 case MULT: /* NAND */
4890 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4891 NULL_RTX, 1, OPTAB_DIRECT);
4892 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4893 NULL_RTX, 1, OPTAB_DIRECT);
4894 break;
4895 default:
4896 gcc_unreachable ();
4897 }
4898
4899 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4900 ac.memsi, cmp, new_rtx));
4901
4902 /* Return the correct part of the bitfield. */
4903 if (target)
4904 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4905 after ? new_rtx : cmp, ac.shift,
4906 NULL_RTX, 1, OPTAB_DIRECT), 1);
4907 }
4908
4909 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4910 We need to emit DTP-relative relocations. */
4911
4912 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4913
4914 static void
4915 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4916 {
4917 switch (size)
4918 {
4919 case 4:
4920 fputs ("\t.long\t", file);
4921 break;
4922 case 8:
4923 fputs ("\t.quad\t", file);
4924 break;
4925 default:
4926 gcc_unreachable ();
4927 }
4928 output_addr_const (file, x);
4929 fputs ("@DTPOFF", file);
4930 }
4931
4932 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4933 /* Implement TARGET_MANGLE_TYPE. */
4934
4935 static const char *
4936 s390_mangle_type (const_tree type)
4937 {
4938 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4939 && TARGET_LONG_DOUBLE_128)
4940 return "g";
4941
4942 /* For all other types, use normal C++ mangling. */
4943 return NULL;
4944 }
4945 #endif
4946
4947 /* In the name of slightly smaller debug output, and to cater to
4948 general assembler lossage, recognize various UNSPEC sequences
4949 and turn them back into a direct symbol reference. */
4950
4951 static rtx
4952 s390_delegitimize_address (rtx orig_x)
4953 {
4954 rtx x, y;
4955
4956 orig_x = delegitimize_mem_from_attrs (orig_x);
4957 x = orig_x;
4958 if (GET_CODE (x) != MEM)
4959 return orig_x;
4960
4961 x = XEXP (x, 0);
4962 if (GET_CODE (x) == PLUS
4963 && GET_CODE (XEXP (x, 1)) == CONST
4964 && GET_CODE (XEXP (x, 0)) == REG
4965 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4966 {
4967 y = XEXP (XEXP (x, 1), 0);
4968 if (GET_CODE (y) == UNSPEC
4969 && XINT (y, 1) == UNSPEC_GOT)
4970 return XVECEXP (y, 0, 0);
4971 return orig_x;
4972 }
4973
4974 if (GET_CODE (x) == CONST)
4975 {
4976 y = XEXP (x, 0);
4977 if (GET_CODE (y) == UNSPEC
4978 && XINT (y, 1) == UNSPEC_GOTENT)
4979 return XVECEXP (y, 0, 0);
4980 return orig_x;
4981 }
4982
4983 return orig_x;
4984 }
4985
4986 /* Output operand OP to stdio stream FILE.
4987 OP is an address (register + offset) which is not used to address data;
4988 instead the rightmost bits are interpreted as the value. */
4989
4990 static void
4991 print_shift_count_operand (FILE *file, rtx op)
4992 {
4993 HOST_WIDE_INT offset;
4994 rtx base;
4995
4996 /* Extract base register and offset. */
4997 if (!s390_decompose_shift_count (op, &base, &offset))
4998 gcc_unreachable ();
4999
5000 /* Sanity check. */
5001 if (base)
5002 {
5003 gcc_assert (GET_CODE (base) == REG);
5004 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5005 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5006 }
5007
5008 /* Offsets are constricted to twelve bits. */
5009 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5010 if (base)
5011 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5012 }
5013
5014 /* See 'get_some_local_dynamic_name'. */
5015
5016 static int
5017 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5018 {
5019 rtx x = *px;
5020
5021 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5022 {
5023 x = get_pool_constant (x);
5024 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5025 }
5026
5027 if (GET_CODE (x) == SYMBOL_REF
5028 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5029 {
5030 cfun->machine->some_ld_name = XSTR (x, 0);
5031 return 1;
5032 }
5033
5034 return 0;
5035 }
5036
5037 /* Locate some local-dynamic symbol still in use by this function
5038 so that we can print its name in local-dynamic base patterns. */
5039
5040 static const char *
5041 get_some_local_dynamic_name (void)
5042 {
5043 rtx insn;
5044
5045 if (cfun->machine->some_ld_name)
5046 return cfun->machine->some_ld_name;
5047
5048 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5049 if (INSN_P (insn)
5050 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5051 return cfun->machine->some_ld_name;
5052
5053 gcc_unreachable ();
5054 }
5055
5056 /* Output machine-dependent UNSPECs occurring in address constant X
5057 in assembler syntax to stdio stream FILE. Returns true if the
5058 constant X could be recognized, false otherwise. */
5059
5060 bool
5061 s390_output_addr_const_extra (FILE *file, rtx x)
5062 {
5063 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5064 switch (XINT (x, 1))
5065 {
5066 case UNSPEC_GOTENT:
5067 output_addr_const (file, XVECEXP (x, 0, 0));
5068 fprintf (file, "@GOTENT");
5069 return true;
5070 case UNSPEC_GOT:
5071 output_addr_const (file, XVECEXP (x, 0, 0));
5072 fprintf (file, "@GOT");
5073 return true;
5074 case UNSPEC_GOTOFF:
5075 output_addr_const (file, XVECEXP (x, 0, 0));
5076 fprintf (file, "@GOTOFF");
5077 return true;
5078 case UNSPEC_PLT:
5079 output_addr_const (file, XVECEXP (x, 0, 0));
5080 fprintf (file, "@PLT");
5081 return true;
5082 case UNSPEC_PLTOFF:
5083 output_addr_const (file, XVECEXP (x, 0, 0));
5084 fprintf (file, "@PLTOFF");
5085 return true;
5086 case UNSPEC_TLSGD:
5087 output_addr_const (file, XVECEXP (x, 0, 0));
5088 fprintf (file, "@TLSGD");
5089 return true;
5090 case UNSPEC_TLSLDM:
5091 assemble_name (file, get_some_local_dynamic_name ());
5092 fprintf (file, "@TLSLDM");
5093 return true;
5094 case UNSPEC_DTPOFF:
5095 output_addr_const (file, XVECEXP (x, 0, 0));
5096 fprintf (file, "@DTPOFF");
5097 return true;
5098 case UNSPEC_NTPOFF:
5099 output_addr_const (file, XVECEXP (x, 0, 0));
5100 fprintf (file, "@NTPOFF");
5101 return true;
5102 case UNSPEC_GOTNTPOFF:
5103 output_addr_const (file, XVECEXP (x, 0, 0));
5104 fprintf (file, "@GOTNTPOFF");
5105 return true;
5106 case UNSPEC_INDNTPOFF:
5107 output_addr_const (file, XVECEXP (x, 0, 0));
5108 fprintf (file, "@INDNTPOFF");
5109 return true;
5110 }
5111
5112 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5113 switch (XINT (x, 1))
5114 {
5115 case UNSPEC_POOL_OFFSET:
5116 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5117 output_addr_const (file, x);
5118 return true;
5119 }
5120 return false;
5121 }
5122
5123 /* Output address operand ADDR in assembler syntax to
5124 stdio stream FILE. */
5125
5126 void
5127 print_operand_address (FILE *file, rtx addr)
5128 {
5129 struct s390_address ad;
5130
5131 if (s390_symref_operand_p (addr, NULL, NULL))
5132 {
5133 gcc_assert (TARGET_Z10);
5134 output_addr_const (file, addr);
5135 return;
5136 }
5137
5138 if (!s390_decompose_address (addr, &ad)
5139 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5140 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5141 output_operand_lossage ("cannot decompose address");
5142
5143 if (ad.disp)
5144 output_addr_const (file, ad.disp);
5145 else
5146 fprintf (file, "0");
5147
5148 if (ad.base && ad.indx)
5149 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5150 reg_names[REGNO (ad.base)]);
5151 else if (ad.base)
5152 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5153 }
5154
5155 /* Output operand X in assembler syntax to stdio stream FILE.
5156 CODE specified the format flag. The following format flags
5157 are recognized:
5158
5159 'C': print opcode suffix for branch condition.
5160 'D': print opcode suffix for inverse branch condition.
5161 'E': print opcode suffix for branch on index instruction.
5162 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5163 'G': print the size of the operand in bytes.
5164 'O': print only the displacement of a memory reference.
5165 'R': print only the base register of a memory reference.
5166 'S': print S-type memory reference (base+displacement).
5167 'N': print the second word of a DImode operand.
5168 'M': print the second word of a TImode operand.
5169 'Y': print shift count operand.
5170
5171 'b': print integer X as if it's an unsigned byte.
5172 'c': print integer X as if it's an signed byte.
5173 'x': print integer X as if it's an unsigned halfword.
5174 'h': print integer X as if it's a signed halfword.
5175 'i': print the first nonzero HImode part of X.
5176 'j': print the first HImode part unequal to -1 of X.
5177 'k': print the first nonzero SImode part of X.
5178 'm': print the first SImode part unequal to -1 of X.
5179 'o': print integer X as if it's an unsigned 32bit word. */
5180
5181 void
5182 print_operand (FILE *file, rtx x, int code)
5183 {
5184 switch (code)
5185 {
5186 case 'C':
5187 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5188 return;
5189
5190 case 'D':
5191 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5192 return;
5193
5194 case 'E':
5195 if (GET_CODE (x) == LE)
5196 fprintf (file, "l");
5197 else if (GET_CODE (x) == GT)
5198 fprintf (file, "h");
5199 else
5200 gcc_unreachable ();
5201 return;
5202
5203 case 'J':
5204 if (GET_CODE (x) == SYMBOL_REF)
5205 {
5206 fprintf (file, "%s", ":tls_load:");
5207 output_addr_const (file, x);
5208 }
5209 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5210 {
5211 fprintf (file, "%s", ":tls_gdcall:");
5212 output_addr_const (file, XVECEXP (x, 0, 0));
5213 }
5214 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5215 {
5216 fprintf (file, "%s", ":tls_ldcall:");
5217 assemble_name (file, get_some_local_dynamic_name ());
5218 }
5219 else
5220 gcc_unreachable ();
5221 return;
5222
5223 case 'G':
5224 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5225 return;
5226
5227 case 'O':
5228 {
5229 struct s390_address ad;
5230 int ret;
5231
5232 gcc_assert (GET_CODE (x) == MEM);
5233 ret = s390_decompose_address (XEXP (x, 0), &ad);
5234 gcc_assert (ret);
5235 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5236 gcc_assert (!ad.indx);
5237
5238 if (ad.disp)
5239 output_addr_const (file, ad.disp);
5240 else
5241 fprintf (file, "0");
5242 }
5243 return;
5244
5245 case 'R':
5246 {
5247 struct s390_address ad;
5248 int ret;
5249
5250 gcc_assert (GET_CODE (x) == MEM);
5251 ret = s390_decompose_address (XEXP (x, 0), &ad);
5252 gcc_assert (ret);
5253 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5254 gcc_assert (!ad.indx);
5255
5256 if (ad.base)
5257 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5258 else
5259 fprintf (file, "0");
5260 }
5261 return;
5262
5263 case 'S':
5264 {
5265 struct s390_address ad;
5266 int ret;
5267
5268 gcc_assert (GET_CODE (x) == MEM);
5269 ret = s390_decompose_address (XEXP (x, 0), &ad);
5270 gcc_assert (ret);
5271 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5272 gcc_assert (!ad.indx);
5273
5274 if (ad.disp)
5275 output_addr_const (file, ad.disp);
5276 else
5277 fprintf (file, "0");
5278
5279 if (ad.base)
5280 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5281 }
5282 return;
5283
5284 case 'N':
5285 if (GET_CODE (x) == REG)
5286 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5287 else if (GET_CODE (x) == MEM)
5288 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5289 else
5290 gcc_unreachable ();
5291 break;
5292
5293 case 'M':
5294 if (GET_CODE (x) == REG)
5295 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5296 else if (GET_CODE (x) == MEM)
5297 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5298 else
5299 gcc_unreachable ();
5300 break;
5301
5302 case 'Y':
5303 print_shift_count_operand (file, x);
5304 return;
5305 }
5306
5307 switch (GET_CODE (x))
5308 {
5309 case REG:
5310 fprintf (file, "%s", reg_names[REGNO (x)]);
5311 break;
5312
5313 case MEM:
5314 output_address (XEXP (x, 0));
5315 break;
5316
5317 case CONST:
5318 case CODE_LABEL:
5319 case LABEL_REF:
5320 case SYMBOL_REF:
5321 output_addr_const (file, x);
5322 break;
5323
5324 case CONST_INT:
5325 if (code == 'b')
5326 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5327 else if (code == 'c')
5328 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5329 else if (code == 'x')
5330 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5331 else if (code == 'h')
5332 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5333 else if (code == 'i')
5334 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5335 s390_extract_part (x, HImode, 0));
5336 else if (code == 'j')
5337 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5338 s390_extract_part (x, HImode, -1));
5339 else if (code == 'k')
5340 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5341 s390_extract_part (x, SImode, 0));
5342 else if (code == 'm')
5343 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5344 s390_extract_part (x, SImode, -1));
5345 else if (code == 'o')
5346 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5347 else
5348 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5349 break;
5350
5351 case CONST_DOUBLE:
5352 gcc_assert (GET_MODE (x) == VOIDmode);
5353 if (code == 'b')
5354 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5355 else if (code == 'x')
5356 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5357 else if (code == 'h')
5358 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5359 else
5360 gcc_unreachable ();
5361 break;
5362
5363 default:
5364 fatal_insn ("UNKNOWN in print_operand !?", x);
5365 break;
5366 }
5367 }
5368
5369 /* Target hook for assembling integer objects. We need to define it
5370 here to work a round a bug in some versions of GAS, which couldn't
5371 handle values smaller than INT_MIN when printed in decimal. */
5372
5373 static bool
5374 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5375 {
5376 if (size == 8 && aligned_p
5377 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5378 {
5379 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5380 INTVAL (x));
5381 return true;
5382 }
5383 return default_assemble_integer (x, size, aligned_p);
5384 }
5385
5386 /* Returns true if register REGNO is used for forming
5387 a memory address in expression X. */
5388
5389 static bool
5390 reg_used_in_mem_p (int regno, rtx x)
5391 {
5392 enum rtx_code code = GET_CODE (x);
5393 int i, j;
5394 const char *fmt;
5395
5396 if (code == MEM)
5397 {
5398 if (refers_to_regno_p (regno, regno+1,
5399 XEXP (x, 0), 0))
5400 return true;
5401 }
5402 else if (code == SET
5403 && GET_CODE (SET_DEST (x)) == PC)
5404 {
5405 if (refers_to_regno_p (regno, regno+1,
5406 SET_SRC (x), 0))
5407 return true;
5408 }
5409
5410 fmt = GET_RTX_FORMAT (code);
5411 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5412 {
5413 if (fmt[i] == 'e'
5414 && reg_used_in_mem_p (regno, XEXP (x, i)))
5415 return true;
5416
5417 else if (fmt[i] == 'E')
5418 for (j = 0; j < XVECLEN (x, i); j++)
5419 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5420 return true;
5421 }
5422 return false;
5423 }
5424
5425 /* Returns true if expression DEP_RTX sets an address register
5426 used by instruction INSN to address memory. */
5427
5428 static bool
5429 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5430 {
5431 rtx target, pat;
5432
5433 if (GET_CODE (dep_rtx) == INSN)
5434 dep_rtx = PATTERN (dep_rtx);
5435
5436 if (GET_CODE (dep_rtx) == SET)
5437 {
5438 target = SET_DEST (dep_rtx);
5439 if (GET_CODE (target) == STRICT_LOW_PART)
5440 target = XEXP (target, 0);
5441 while (GET_CODE (target) == SUBREG)
5442 target = SUBREG_REG (target);
5443
5444 if (GET_CODE (target) == REG)
5445 {
5446 int regno = REGNO (target);
5447
5448 if (s390_safe_attr_type (insn) == TYPE_LA)
5449 {
5450 pat = PATTERN (insn);
5451 if (GET_CODE (pat) == PARALLEL)
5452 {
5453 gcc_assert (XVECLEN (pat, 0) == 2);
5454 pat = XVECEXP (pat, 0, 0);
5455 }
5456 gcc_assert (GET_CODE (pat) == SET);
5457 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5458 }
5459 else if (get_attr_atype (insn) == ATYPE_AGEN)
5460 return reg_used_in_mem_p (regno, PATTERN (insn));
5461 }
5462 }
5463 return false;
5464 }
5465
5466 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5467
5468 int
5469 s390_agen_dep_p (rtx dep_insn, rtx insn)
5470 {
5471 rtx dep_rtx = PATTERN (dep_insn);
5472 int i;
5473
5474 if (GET_CODE (dep_rtx) == SET
5475 && addr_generation_dependency_p (dep_rtx, insn))
5476 return 1;
5477 else if (GET_CODE (dep_rtx) == PARALLEL)
5478 {
5479 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5480 {
5481 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5482 return 1;
5483 }
5484 }
5485 return 0;
5486 }
5487
5488
5489 /* A C statement (sans semicolon) to update the integer scheduling priority
5490 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5491 reduce the priority to execute INSN later. Do not define this macro if
5492 you do not need to adjust the scheduling priorities of insns.
5493
5494 A STD instruction should be scheduled earlier,
5495 in order to use the bypass. */
5496 static int
5497 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5498 {
5499 if (! INSN_P (insn))
5500 return priority;
5501
5502 if (s390_tune != PROCESSOR_2084_Z990
5503 && s390_tune != PROCESSOR_2094_Z9_109
5504 && s390_tune != PROCESSOR_2097_Z10
5505 && s390_tune != PROCESSOR_2817_Z196)
5506 return priority;
5507
5508 switch (s390_safe_attr_type (insn))
5509 {
5510 case TYPE_FSTOREDF:
5511 case TYPE_FSTORESF:
5512 priority = priority << 3;
5513 break;
5514 case TYPE_STORE:
5515 case TYPE_STM:
5516 priority = priority << 1;
5517 break;
5518 default:
5519 break;
5520 }
5521 return priority;
5522 }
5523
5524
5525 /* The number of instructions that can be issued per cycle. */
5526
5527 static int
5528 s390_issue_rate (void)
5529 {
5530 switch (s390_tune)
5531 {
5532 case PROCESSOR_2084_Z990:
5533 case PROCESSOR_2094_Z9_109:
5534 case PROCESSOR_2817_Z196:
5535 return 3;
5536 case PROCESSOR_2097_Z10:
5537 return 2;
5538 default:
5539 return 1;
5540 }
5541 }
5542
5543 static int
5544 s390_first_cycle_multipass_dfa_lookahead (void)
5545 {
5546 return 4;
5547 }
5548
5549 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5550 Fix up MEMs as required. */
5551
5552 static void
5553 annotate_constant_pool_refs (rtx *x)
5554 {
5555 int i, j;
5556 const char *fmt;
5557
5558 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5559 || !CONSTANT_POOL_ADDRESS_P (*x));
5560
5561 /* Literal pool references can only occur inside a MEM ... */
5562 if (GET_CODE (*x) == MEM)
5563 {
5564 rtx memref = XEXP (*x, 0);
5565
5566 if (GET_CODE (memref) == SYMBOL_REF
5567 && CONSTANT_POOL_ADDRESS_P (memref))
5568 {
5569 rtx base = cfun->machine->base_reg;
5570 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5571 UNSPEC_LTREF);
5572
5573 *x = replace_equiv_address (*x, addr);
5574 return;
5575 }
5576
5577 if (GET_CODE (memref) == CONST
5578 && GET_CODE (XEXP (memref, 0)) == PLUS
5579 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5580 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5581 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5582 {
5583 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5584 rtx sym = XEXP (XEXP (memref, 0), 0);
5585 rtx base = cfun->machine->base_reg;
5586 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5587 UNSPEC_LTREF);
5588
5589 *x = replace_equiv_address (*x, plus_constant (addr, off));
5590 return;
5591 }
5592 }
5593
5594 /* ... or a load-address type pattern. */
5595 if (GET_CODE (*x) == SET)
5596 {
5597 rtx addrref = SET_SRC (*x);
5598
5599 if (GET_CODE (addrref) == SYMBOL_REF
5600 && CONSTANT_POOL_ADDRESS_P (addrref))
5601 {
5602 rtx base = cfun->machine->base_reg;
5603 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5604 UNSPEC_LTREF);
5605
5606 SET_SRC (*x) = addr;
5607 return;
5608 }
5609
5610 if (GET_CODE (addrref) == CONST
5611 && GET_CODE (XEXP (addrref, 0)) == PLUS
5612 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5613 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5614 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5615 {
5616 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5617 rtx sym = XEXP (XEXP (addrref, 0), 0);
5618 rtx base = cfun->machine->base_reg;
5619 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5620 UNSPEC_LTREF);
5621
5622 SET_SRC (*x) = plus_constant (addr, off);
5623 return;
5624 }
5625 }
5626
5627 /* Annotate LTREL_BASE as well. */
5628 if (GET_CODE (*x) == UNSPEC
5629 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5630 {
5631 rtx base = cfun->machine->base_reg;
5632 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5633 UNSPEC_LTREL_BASE);
5634 return;
5635 }
5636
5637 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5638 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5639 {
5640 if (fmt[i] == 'e')
5641 {
5642 annotate_constant_pool_refs (&XEXP (*x, i));
5643 }
5644 else if (fmt[i] == 'E')
5645 {
5646 for (j = 0; j < XVECLEN (*x, i); j++)
5647 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5648 }
5649 }
5650 }
5651
5652 /* Split all branches that exceed the maximum distance.
5653 Returns true if this created a new literal pool entry. */
5654
5655 static int
5656 s390_split_branches (void)
5657 {
5658 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5659 int new_literal = 0, ret;
5660 rtx insn, pat, tmp, target;
5661 rtx *label;
5662
5663 /* We need correct insn addresses. */
5664
5665 shorten_branches (get_insns ());
5666
5667 /* Find all branches that exceed 64KB, and split them. */
5668
5669 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5670 {
5671 if (GET_CODE (insn) != JUMP_INSN)
5672 continue;
5673
5674 pat = PATTERN (insn);
5675 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5676 pat = XVECEXP (pat, 0, 0);
5677 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5678 continue;
5679
5680 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5681 {
5682 label = &SET_SRC (pat);
5683 }
5684 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5685 {
5686 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5687 label = &XEXP (SET_SRC (pat), 1);
5688 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5689 label = &XEXP (SET_SRC (pat), 2);
5690 else
5691 continue;
5692 }
5693 else
5694 continue;
5695
5696 if (get_attr_length (insn) <= 4)
5697 continue;
5698
5699 /* We are going to use the return register as scratch register,
5700 make sure it will be saved/restored by the prologue/epilogue. */
5701 cfun_frame_layout.save_return_addr_p = 1;
5702
5703 if (!flag_pic)
5704 {
5705 new_literal = 1;
5706 tmp = force_const_mem (Pmode, *label);
5707 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5708 INSN_ADDRESSES_NEW (tmp, -1);
5709 annotate_constant_pool_refs (&PATTERN (tmp));
5710
5711 target = temp_reg;
5712 }
5713 else
5714 {
5715 new_literal = 1;
5716 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5717 UNSPEC_LTREL_OFFSET);
5718 target = gen_rtx_CONST (Pmode, target);
5719 target = force_const_mem (Pmode, target);
5720 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5721 INSN_ADDRESSES_NEW (tmp, -1);
5722 annotate_constant_pool_refs (&PATTERN (tmp));
5723
5724 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5725 cfun->machine->base_reg),
5726 UNSPEC_LTREL_BASE);
5727 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5728 }
5729
5730 ret = validate_change (insn, label, target, 0);
5731 gcc_assert (ret);
5732 }
5733
5734 return new_literal;
5735 }
5736
5737
5738 /* Find an annotated literal pool symbol referenced in RTX X,
5739 and store it at REF. Will abort if X contains references to
5740 more than one such pool symbol; multiple references to the same
5741 symbol are allowed, however.
5742
5743 The rtx pointed to by REF must be initialized to NULL_RTX
5744 by the caller before calling this routine. */
5745
5746 static void
5747 find_constant_pool_ref (rtx x, rtx *ref)
5748 {
5749 int i, j;
5750 const char *fmt;
5751
5752 /* Ignore LTREL_BASE references. */
5753 if (GET_CODE (x) == UNSPEC
5754 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5755 return;
5756 /* Likewise POOL_ENTRY insns. */
5757 if (GET_CODE (x) == UNSPEC_VOLATILE
5758 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5759 return;
5760
5761 gcc_assert (GET_CODE (x) != SYMBOL_REF
5762 || !CONSTANT_POOL_ADDRESS_P (x));
5763
5764 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5765 {
5766 rtx sym = XVECEXP (x, 0, 0);
5767 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5768 && CONSTANT_POOL_ADDRESS_P (sym));
5769
5770 if (*ref == NULL_RTX)
5771 *ref = sym;
5772 else
5773 gcc_assert (*ref == sym);
5774
5775 return;
5776 }
5777
5778 fmt = GET_RTX_FORMAT (GET_CODE (x));
5779 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5780 {
5781 if (fmt[i] == 'e')
5782 {
5783 find_constant_pool_ref (XEXP (x, i), ref);
5784 }
5785 else if (fmt[i] == 'E')
5786 {
5787 for (j = 0; j < XVECLEN (x, i); j++)
5788 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5789 }
5790 }
5791 }
5792
5793 /* Replace every reference to the annotated literal pool
5794 symbol REF in X by its base plus OFFSET. */
5795
5796 static void
5797 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5798 {
5799 int i, j;
5800 const char *fmt;
5801
5802 gcc_assert (*x != ref);
5803
5804 if (GET_CODE (*x) == UNSPEC
5805 && XINT (*x, 1) == UNSPEC_LTREF
5806 && XVECEXP (*x, 0, 0) == ref)
5807 {
5808 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5809 return;
5810 }
5811
5812 if (GET_CODE (*x) == PLUS
5813 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5814 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5815 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5816 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5817 {
5818 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5819 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5820 return;
5821 }
5822
5823 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5824 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5825 {
5826 if (fmt[i] == 'e')
5827 {
5828 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5829 }
5830 else if (fmt[i] == 'E')
5831 {
5832 for (j = 0; j < XVECLEN (*x, i); j++)
5833 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5834 }
5835 }
5836 }
5837
5838 /* Check whether X contains an UNSPEC_LTREL_BASE.
5839 Return its constant pool symbol if found, NULL_RTX otherwise. */
5840
5841 static rtx
5842 find_ltrel_base (rtx x)
5843 {
5844 int i, j;
5845 const char *fmt;
5846
5847 if (GET_CODE (x) == UNSPEC
5848 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5849 return XVECEXP (x, 0, 0);
5850
5851 fmt = GET_RTX_FORMAT (GET_CODE (x));
5852 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5853 {
5854 if (fmt[i] == 'e')
5855 {
5856 rtx fnd = find_ltrel_base (XEXP (x, i));
5857 if (fnd)
5858 return fnd;
5859 }
5860 else if (fmt[i] == 'E')
5861 {
5862 for (j = 0; j < XVECLEN (x, i); j++)
5863 {
5864 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5865 if (fnd)
5866 return fnd;
5867 }
5868 }
5869 }
5870
5871 return NULL_RTX;
5872 }
5873
5874 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5875
5876 static void
5877 replace_ltrel_base (rtx *x)
5878 {
5879 int i, j;
5880 const char *fmt;
5881
5882 if (GET_CODE (*x) == UNSPEC
5883 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5884 {
5885 *x = XVECEXP (*x, 0, 1);
5886 return;
5887 }
5888
5889 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5890 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5891 {
5892 if (fmt[i] == 'e')
5893 {
5894 replace_ltrel_base (&XEXP (*x, i));
5895 }
5896 else if (fmt[i] == 'E')
5897 {
5898 for (j = 0; j < XVECLEN (*x, i); j++)
5899 replace_ltrel_base (&XVECEXP (*x, i, j));
5900 }
5901 }
5902 }
5903
5904
5905 /* We keep a list of constants which we have to add to internal
5906 constant tables in the middle of large functions. */
5907
5908 #define NR_C_MODES 11
5909 enum machine_mode constant_modes[NR_C_MODES] =
5910 {
5911 TFmode, TImode, TDmode,
5912 DFmode, DImode, DDmode,
5913 SFmode, SImode, SDmode,
5914 HImode,
5915 QImode
5916 };
5917
5918 struct constant
5919 {
5920 struct constant *next;
5921 rtx value;
5922 rtx label;
5923 };
5924
5925 struct constant_pool
5926 {
5927 struct constant_pool *next;
5928 rtx first_insn;
5929 rtx pool_insn;
5930 bitmap insns;
5931 rtx emit_pool_after;
5932
5933 struct constant *constants[NR_C_MODES];
5934 struct constant *execute;
5935 rtx label;
5936 int size;
5937 };
5938
5939 /* Allocate new constant_pool structure. */
5940
5941 static struct constant_pool *
5942 s390_alloc_pool (void)
5943 {
5944 struct constant_pool *pool;
5945 int i;
5946
5947 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5948 pool->next = NULL;
5949 for (i = 0; i < NR_C_MODES; i++)
5950 pool->constants[i] = NULL;
5951
5952 pool->execute = NULL;
5953 pool->label = gen_label_rtx ();
5954 pool->first_insn = NULL_RTX;
5955 pool->pool_insn = NULL_RTX;
5956 pool->insns = BITMAP_ALLOC (NULL);
5957 pool->size = 0;
5958 pool->emit_pool_after = NULL_RTX;
5959
5960 return pool;
5961 }
5962
5963 /* Create new constant pool covering instructions starting at INSN
5964 and chain it to the end of POOL_LIST. */
5965
5966 static struct constant_pool *
5967 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5968 {
5969 struct constant_pool *pool, **prev;
5970
5971 pool = s390_alloc_pool ();
5972 pool->first_insn = insn;
5973
5974 for (prev = pool_list; *prev; prev = &(*prev)->next)
5975 ;
5976 *prev = pool;
5977
5978 return pool;
5979 }
5980
5981 /* End range of instructions covered by POOL at INSN and emit
5982 placeholder insn representing the pool. */
5983
5984 static void
5985 s390_end_pool (struct constant_pool *pool, rtx insn)
5986 {
5987 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5988
5989 if (!insn)
5990 insn = get_last_insn ();
5991
5992 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5993 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5994 }
5995
5996 /* Add INSN to the list of insns covered by POOL. */
5997
5998 static void
5999 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6000 {
6001 bitmap_set_bit (pool->insns, INSN_UID (insn));
6002 }
6003
6004 /* Return pool out of POOL_LIST that covers INSN. */
6005
6006 static struct constant_pool *
6007 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6008 {
6009 struct constant_pool *pool;
6010
6011 for (pool = pool_list; pool; pool = pool->next)
6012 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6013 break;
6014
6015 return pool;
6016 }
6017
6018 /* Add constant VAL of mode MODE to the constant pool POOL. */
6019
6020 static void
6021 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6022 {
6023 struct constant *c;
6024 int i;
6025
6026 for (i = 0; i < NR_C_MODES; i++)
6027 if (constant_modes[i] == mode)
6028 break;
6029 gcc_assert (i != NR_C_MODES);
6030
6031 for (c = pool->constants[i]; c != NULL; c = c->next)
6032 if (rtx_equal_p (val, c->value))
6033 break;
6034
6035 if (c == NULL)
6036 {
6037 c = (struct constant *) xmalloc (sizeof *c);
6038 c->value = val;
6039 c->label = gen_label_rtx ();
6040 c->next = pool->constants[i];
6041 pool->constants[i] = c;
6042 pool->size += GET_MODE_SIZE (mode);
6043 }
6044 }
6045
6046 /* Return an rtx that represents the offset of X from the start of
6047 pool POOL. */
6048
6049 static rtx
6050 s390_pool_offset (struct constant_pool *pool, rtx x)
6051 {
6052 rtx label;
6053
6054 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6055 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6056 UNSPEC_POOL_OFFSET);
6057 return gen_rtx_CONST (GET_MODE (x), x);
6058 }
6059
6060 /* Find constant VAL of mode MODE in the constant pool POOL.
6061 Return an RTX describing the distance from the start of
6062 the pool to the location of the new constant. */
6063
6064 static rtx
6065 s390_find_constant (struct constant_pool *pool, rtx val,
6066 enum machine_mode mode)
6067 {
6068 struct constant *c;
6069 int i;
6070
6071 for (i = 0; i < NR_C_MODES; i++)
6072 if (constant_modes[i] == mode)
6073 break;
6074 gcc_assert (i != NR_C_MODES);
6075
6076 for (c = pool->constants[i]; c != NULL; c = c->next)
6077 if (rtx_equal_p (val, c->value))
6078 break;
6079
6080 gcc_assert (c);
6081
6082 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6083 }
6084
6085 /* Check whether INSN is an execute. Return the label_ref to its
6086 execute target template if so, NULL_RTX otherwise. */
6087
6088 static rtx
6089 s390_execute_label (rtx insn)
6090 {
6091 if (GET_CODE (insn) == INSN
6092 && GET_CODE (PATTERN (insn)) == PARALLEL
6093 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6094 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6095 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6096
6097 return NULL_RTX;
6098 }
6099
6100 /* Add execute target for INSN to the constant pool POOL. */
6101
6102 static void
6103 s390_add_execute (struct constant_pool *pool, rtx insn)
6104 {
6105 struct constant *c;
6106
6107 for (c = pool->execute; c != NULL; c = c->next)
6108 if (INSN_UID (insn) == INSN_UID (c->value))
6109 break;
6110
6111 if (c == NULL)
6112 {
6113 c = (struct constant *) xmalloc (sizeof *c);
6114 c->value = insn;
6115 c->label = gen_label_rtx ();
6116 c->next = pool->execute;
6117 pool->execute = c;
6118 pool->size += 6;
6119 }
6120 }
6121
6122 /* Find execute target for INSN in the constant pool POOL.
6123 Return an RTX describing the distance from the start of
6124 the pool to the location of the execute target. */
6125
6126 static rtx
6127 s390_find_execute (struct constant_pool *pool, rtx insn)
6128 {
6129 struct constant *c;
6130
6131 for (c = pool->execute; c != NULL; c = c->next)
6132 if (INSN_UID (insn) == INSN_UID (c->value))
6133 break;
6134
6135 gcc_assert (c);
6136
6137 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6138 }
6139
6140 /* For an execute INSN, extract the execute target template. */
6141
6142 static rtx
6143 s390_execute_target (rtx insn)
6144 {
6145 rtx pattern = PATTERN (insn);
6146 gcc_assert (s390_execute_label (insn));
6147
6148 if (XVECLEN (pattern, 0) == 2)
6149 {
6150 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6151 }
6152 else
6153 {
6154 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6155 int i;
6156
6157 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6158 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6159
6160 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6161 }
6162
6163 return pattern;
6164 }
6165
6166 /* Indicate that INSN cannot be duplicated. This is the case for
6167 execute insns that carry a unique label. */
6168
6169 static bool
6170 s390_cannot_copy_insn_p (rtx insn)
6171 {
6172 rtx label = s390_execute_label (insn);
6173 return label && label != const0_rtx;
6174 }
6175
6176 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6177 do not emit the pool base label. */
6178
6179 static void
6180 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6181 {
6182 struct constant *c;
6183 rtx insn = pool->pool_insn;
6184 int i;
6185
6186 /* Switch to rodata section. */
6187 if (TARGET_CPU_ZARCH)
6188 {
6189 insn = emit_insn_after (gen_pool_section_start (), insn);
6190 INSN_ADDRESSES_NEW (insn, -1);
6191 }
6192
6193 /* Ensure minimum pool alignment. */
6194 if (TARGET_CPU_ZARCH)
6195 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6196 else
6197 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6198 INSN_ADDRESSES_NEW (insn, -1);
6199
6200 /* Emit pool base label. */
6201 if (!remote_label)
6202 {
6203 insn = emit_label_after (pool->label, insn);
6204 INSN_ADDRESSES_NEW (insn, -1);
6205 }
6206
6207 /* Dump constants in descending alignment requirement order,
6208 ensuring proper alignment for every constant. */
6209 for (i = 0; i < NR_C_MODES; i++)
6210 for (c = pool->constants[i]; c; c = c->next)
6211 {
6212 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6213 rtx value = copy_rtx (c->value);
6214 if (GET_CODE (value) == CONST
6215 && GET_CODE (XEXP (value, 0)) == UNSPEC
6216 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6217 && XVECLEN (XEXP (value, 0), 0) == 1)
6218 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6219
6220 insn = emit_label_after (c->label, insn);
6221 INSN_ADDRESSES_NEW (insn, -1);
6222
6223 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6224 gen_rtvec (1, value),
6225 UNSPECV_POOL_ENTRY);
6226 insn = emit_insn_after (value, insn);
6227 INSN_ADDRESSES_NEW (insn, -1);
6228 }
6229
6230 /* Ensure minimum alignment for instructions. */
6231 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6232 INSN_ADDRESSES_NEW (insn, -1);
6233
6234 /* Output in-pool execute template insns. */
6235 for (c = pool->execute; c; c = c->next)
6236 {
6237 insn = emit_label_after (c->label, insn);
6238 INSN_ADDRESSES_NEW (insn, -1);
6239
6240 insn = emit_insn_after (s390_execute_target (c->value), insn);
6241 INSN_ADDRESSES_NEW (insn, -1);
6242 }
6243
6244 /* Switch back to previous section. */
6245 if (TARGET_CPU_ZARCH)
6246 {
6247 insn = emit_insn_after (gen_pool_section_end (), insn);
6248 INSN_ADDRESSES_NEW (insn, -1);
6249 }
6250
6251 insn = emit_barrier_after (insn);
6252 INSN_ADDRESSES_NEW (insn, -1);
6253
6254 /* Remove placeholder insn. */
6255 remove_insn (pool->pool_insn);
6256 }
6257
6258 /* Free all memory used by POOL. */
6259
6260 static void
6261 s390_free_pool (struct constant_pool *pool)
6262 {
6263 struct constant *c, *next;
6264 int i;
6265
6266 for (i = 0; i < NR_C_MODES; i++)
6267 for (c = pool->constants[i]; c; c = next)
6268 {
6269 next = c->next;
6270 free (c);
6271 }
6272
6273 for (c = pool->execute; c; c = next)
6274 {
6275 next = c->next;
6276 free (c);
6277 }
6278
6279 BITMAP_FREE (pool->insns);
6280 free (pool);
6281 }
6282
6283
6284 /* Collect main literal pool. Return NULL on overflow. */
6285
6286 static struct constant_pool *
6287 s390_mainpool_start (void)
6288 {
6289 struct constant_pool *pool;
6290 rtx insn;
6291
6292 pool = s390_alloc_pool ();
6293
6294 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6295 {
6296 if (GET_CODE (insn) == INSN
6297 && GET_CODE (PATTERN (insn)) == SET
6298 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6299 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6300 {
6301 gcc_assert (!pool->pool_insn);
6302 pool->pool_insn = insn;
6303 }
6304
6305 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6306 {
6307 s390_add_execute (pool, insn);
6308 }
6309 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6310 {
6311 rtx pool_ref = NULL_RTX;
6312 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6313 if (pool_ref)
6314 {
6315 rtx constant = get_pool_constant (pool_ref);
6316 enum machine_mode mode = get_pool_mode (pool_ref);
6317 s390_add_constant (pool, constant, mode);
6318 }
6319 }
6320
6321 /* If hot/cold partitioning is enabled we have to make sure that
6322 the literal pool is emitted in the same section where the
6323 initialization of the literal pool base pointer takes place.
6324 emit_pool_after is only used in the non-overflow case on non
6325 Z cpus where we can emit the literal pool at the end of the
6326 function body within the text section. */
6327 if (NOTE_P (insn)
6328 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6329 && !pool->emit_pool_after)
6330 pool->emit_pool_after = PREV_INSN (insn);
6331 }
6332
6333 gcc_assert (pool->pool_insn || pool->size == 0);
6334
6335 if (pool->size >= 4096)
6336 {
6337 /* We're going to chunkify the pool, so remove the main
6338 pool placeholder insn. */
6339 remove_insn (pool->pool_insn);
6340
6341 s390_free_pool (pool);
6342 pool = NULL;
6343 }
6344
6345 /* If the functions ends with the section where the literal pool
6346 should be emitted set the marker to its end. */
6347 if (pool && !pool->emit_pool_after)
6348 pool->emit_pool_after = get_last_insn ();
6349
6350 return pool;
6351 }
6352
6353 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6354 Modify the current function to output the pool constants as well as
6355 the pool register setup instruction. */
6356
6357 static void
6358 s390_mainpool_finish (struct constant_pool *pool)
6359 {
6360 rtx base_reg = cfun->machine->base_reg;
6361 rtx insn;
6362
6363 /* If the pool is empty, we're done. */
6364 if (pool->size == 0)
6365 {
6366 /* We don't actually need a base register after all. */
6367 cfun->machine->base_reg = NULL_RTX;
6368
6369 if (pool->pool_insn)
6370 remove_insn (pool->pool_insn);
6371 s390_free_pool (pool);
6372 return;
6373 }
6374
6375 /* We need correct insn addresses. */
6376 shorten_branches (get_insns ());
6377
6378 /* On zSeries, we use a LARL to load the pool register. The pool is
6379 located in the .rodata section, so we emit it after the function. */
6380 if (TARGET_CPU_ZARCH)
6381 {
6382 insn = gen_main_base_64 (base_reg, pool->label);
6383 insn = emit_insn_after (insn, pool->pool_insn);
6384 INSN_ADDRESSES_NEW (insn, -1);
6385 remove_insn (pool->pool_insn);
6386
6387 insn = get_last_insn ();
6388 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6389 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6390
6391 s390_dump_pool (pool, 0);
6392 }
6393
6394 /* On S/390, if the total size of the function's code plus literal pool
6395 does not exceed 4096 bytes, we use BASR to set up a function base
6396 pointer, and emit the literal pool at the end of the function. */
6397 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6398 + pool->size + 8 /* alignment slop */ < 4096)
6399 {
6400 insn = gen_main_base_31_small (base_reg, pool->label);
6401 insn = emit_insn_after (insn, pool->pool_insn);
6402 INSN_ADDRESSES_NEW (insn, -1);
6403 remove_insn (pool->pool_insn);
6404
6405 insn = emit_label_after (pool->label, insn);
6406 INSN_ADDRESSES_NEW (insn, -1);
6407
6408 /* emit_pool_after will be set by s390_mainpool_start to the
6409 last insn of the section where the literal pool should be
6410 emitted. */
6411 insn = pool->emit_pool_after;
6412
6413 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6414 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6415
6416 s390_dump_pool (pool, 1);
6417 }
6418
6419 /* Otherwise, we emit an inline literal pool and use BASR to branch
6420 over it, setting up the pool register at the same time. */
6421 else
6422 {
6423 rtx pool_end = gen_label_rtx ();
6424
6425 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6426 insn = emit_insn_after (insn, pool->pool_insn);
6427 INSN_ADDRESSES_NEW (insn, -1);
6428 remove_insn (pool->pool_insn);
6429
6430 insn = emit_label_after (pool->label, insn);
6431 INSN_ADDRESSES_NEW (insn, -1);
6432
6433 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6434 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6435
6436 insn = emit_label_after (pool_end, pool->pool_insn);
6437 INSN_ADDRESSES_NEW (insn, -1);
6438
6439 s390_dump_pool (pool, 1);
6440 }
6441
6442
6443 /* Replace all literal pool references. */
6444
6445 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6446 {
6447 if (INSN_P (insn))
6448 replace_ltrel_base (&PATTERN (insn));
6449
6450 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6451 {
6452 rtx addr, pool_ref = NULL_RTX;
6453 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6454 if (pool_ref)
6455 {
6456 if (s390_execute_label (insn))
6457 addr = s390_find_execute (pool, insn);
6458 else
6459 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6460 get_pool_mode (pool_ref));
6461
6462 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6463 INSN_CODE (insn) = -1;
6464 }
6465 }
6466 }
6467
6468
6469 /* Free the pool. */
6470 s390_free_pool (pool);
6471 }
6472
6473 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6474 We have decided we cannot use this pool, so revert all changes
6475 to the current function that were done by s390_mainpool_start. */
6476 static void
6477 s390_mainpool_cancel (struct constant_pool *pool)
6478 {
6479 /* We didn't actually change the instruction stream, so simply
6480 free the pool memory. */
6481 s390_free_pool (pool);
6482 }
6483
6484
6485 /* Chunkify the literal pool. */
6486
6487 #define S390_POOL_CHUNK_MIN 0xc00
6488 #define S390_POOL_CHUNK_MAX 0xe00
6489
6490 static struct constant_pool *
6491 s390_chunkify_start (void)
6492 {
6493 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6494 int extra_size = 0;
6495 bitmap far_labels;
6496 rtx pending_ltrel = NULL_RTX;
6497 rtx insn;
6498
6499 rtx (*gen_reload_base) (rtx, rtx) =
6500 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6501
6502
6503 /* We need correct insn addresses. */
6504
6505 shorten_branches (get_insns ());
6506
6507 /* Scan all insns and move literals to pool chunks. */
6508
6509 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6510 {
6511 bool section_switch_p = false;
6512
6513 /* Check for pending LTREL_BASE. */
6514 if (INSN_P (insn))
6515 {
6516 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6517 if (ltrel_base)
6518 {
6519 gcc_assert (ltrel_base == pending_ltrel);
6520 pending_ltrel = NULL_RTX;
6521 }
6522 }
6523
6524 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6525 {
6526 if (!curr_pool)
6527 curr_pool = s390_start_pool (&pool_list, insn);
6528
6529 s390_add_execute (curr_pool, insn);
6530 s390_add_pool_insn (curr_pool, insn);
6531 }
6532 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6533 {
6534 rtx pool_ref = NULL_RTX;
6535 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6536 if (pool_ref)
6537 {
6538 rtx constant = get_pool_constant (pool_ref);
6539 enum machine_mode mode = get_pool_mode (pool_ref);
6540
6541 if (!curr_pool)
6542 curr_pool = s390_start_pool (&pool_list, insn);
6543
6544 s390_add_constant (curr_pool, constant, mode);
6545 s390_add_pool_insn (curr_pool, insn);
6546
6547 /* Don't split the pool chunk between a LTREL_OFFSET load
6548 and the corresponding LTREL_BASE. */
6549 if (GET_CODE (constant) == CONST
6550 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6551 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6552 {
6553 gcc_assert (!pending_ltrel);
6554 pending_ltrel = pool_ref;
6555 }
6556 }
6557 }
6558
6559 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6560 {
6561 if (curr_pool)
6562 s390_add_pool_insn (curr_pool, insn);
6563 /* An LTREL_BASE must follow within the same basic block. */
6564 gcc_assert (!pending_ltrel);
6565 }
6566
6567 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6568 section_switch_p = true;
6569
6570 if (!curr_pool
6571 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6572 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6573 continue;
6574
6575 if (TARGET_CPU_ZARCH)
6576 {
6577 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6578 continue;
6579
6580 s390_end_pool (curr_pool, NULL_RTX);
6581 curr_pool = NULL;
6582 }
6583 else
6584 {
6585 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6586 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6587 + extra_size;
6588
6589 /* We will later have to insert base register reload insns.
6590 Those will have an effect on code size, which we need to
6591 consider here. This calculation makes rather pessimistic
6592 worst-case assumptions. */
6593 if (GET_CODE (insn) == CODE_LABEL)
6594 extra_size += 6;
6595
6596 if (chunk_size < S390_POOL_CHUNK_MIN
6597 && curr_pool->size < S390_POOL_CHUNK_MIN
6598 && !section_switch_p)
6599 continue;
6600
6601 /* Pool chunks can only be inserted after BARRIERs ... */
6602 if (GET_CODE (insn) == BARRIER)
6603 {
6604 s390_end_pool (curr_pool, insn);
6605 curr_pool = NULL;
6606 extra_size = 0;
6607 }
6608
6609 /* ... so if we don't find one in time, create one. */
6610 else if (chunk_size > S390_POOL_CHUNK_MAX
6611 || curr_pool->size > S390_POOL_CHUNK_MAX
6612 || section_switch_p)
6613 {
6614 rtx label, jump, barrier;
6615
6616 if (!section_switch_p)
6617 {
6618 /* We can insert the barrier only after a 'real' insn. */
6619 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6620 continue;
6621 if (get_attr_length (insn) == 0)
6622 continue;
6623 /* Don't separate LTREL_BASE from the corresponding
6624 LTREL_OFFSET load. */
6625 if (pending_ltrel)
6626 continue;
6627 }
6628 else
6629 {
6630 gcc_assert (!pending_ltrel);
6631
6632 /* The old pool has to end before the section switch
6633 note in order to make it part of the current
6634 section. */
6635 insn = PREV_INSN (insn);
6636 }
6637
6638 label = gen_label_rtx ();
6639 jump = emit_jump_insn_after (gen_jump (label), insn);
6640 barrier = emit_barrier_after (jump);
6641 insn = emit_label_after (label, barrier);
6642 JUMP_LABEL (jump) = label;
6643 LABEL_NUSES (label) = 1;
6644
6645 INSN_ADDRESSES_NEW (jump, -1);
6646 INSN_ADDRESSES_NEW (barrier, -1);
6647 INSN_ADDRESSES_NEW (insn, -1);
6648
6649 s390_end_pool (curr_pool, barrier);
6650 curr_pool = NULL;
6651 extra_size = 0;
6652 }
6653 }
6654 }
6655
6656 if (curr_pool)
6657 s390_end_pool (curr_pool, NULL_RTX);
6658 gcc_assert (!pending_ltrel);
6659
6660 /* Find all labels that are branched into
6661 from an insn belonging to a different chunk. */
6662
6663 far_labels = BITMAP_ALLOC (NULL);
6664
6665 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6666 {
6667 /* Labels marked with LABEL_PRESERVE_P can be target
6668 of non-local jumps, so we have to mark them.
6669 The same holds for named labels.
6670
6671 Don't do that, however, if it is the label before
6672 a jump table. */
6673
6674 if (GET_CODE (insn) == CODE_LABEL
6675 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6676 {
6677 rtx vec_insn = next_real_insn (insn);
6678 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6679 PATTERN (vec_insn) : NULL_RTX;
6680 if (!vec_pat
6681 || !(GET_CODE (vec_pat) == ADDR_VEC
6682 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6683 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6684 }
6685
6686 /* If we have a direct jump (conditional or unconditional)
6687 or a casesi jump, check all potential targets. */
6688 else if (GET_CODE (insn) == JUMP_INSN)
6689 {
6690 rtx pat = PATTERN (insn);
6691 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6692 pat = XVECEXP (pat, 0, 0);
6693
6694 if (GET_CODE (pat) == SET)
6695 {
6696 rtx label = JUMP_LABEL (insn);
6697 if (label)
6698 {
6699 if (s390_find_pool (pool_list, label)
6700 != s390_find_pool (pool_list, insn))
6701 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6702 }
6703 }
6704 else if (GET_CODE (pat) == PARALLEL
6705 && XVECLEN (pat, 0) == 2
6706 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6707 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6708 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6709 {
6710 /* Find the jump table used by this casesi jump. */
6711 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6712 rtx vec_insn = next_real_insn (vec_label);
6713 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6714 PATTERN (vec_insn) : NULL_RTX;
6715 if (vec_pat
6716 && (GET_CODE (vec_pat) == ADDR_VEC
6717 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6718 {
6719 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6720
6721 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6722 {
6723 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6724
6725 if (s390_find_pool (pool_list, label)
6726 != s390_find_pool (pool_list, insn))
6727 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6728 }
6729 }
6730 }
6731 }
6732 }
6733
6734 /* Insert base register reload insns before every pool. */
6735
6736 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6737 {
6738 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6739 curr_pool->label);
6740 rtx insn = curr_pool->first_insn;
6741 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6742 }
6743
6744 /* Insert base register reload insns at every far label. */
6745
6746 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6747 if (GET_CODE (insn) == CODE_LABEL
6748 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6749 {
6750 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6751 if (pool)
6752 {
6753 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6754 pool->label);
6755 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6756 }
6757 }
6758
6759
6760 BITMAP_FREE (far_labels);
6761
6762
6763 /* Recompute insn addresses. */
6764
6765 init_insn_lengths ();
6766 shorten_branches (get_insns ());
6767
6768 return pool_list;
6769 }
6770
6771 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6772 After we have decided to use this list, finish implementing
6773 all changes to the current function as required. */
6774
6775 static void
6776 s390_chunkify_finish (struct constant_pool *pool_list)
6777 {
6778 struct constant_pool *curr_pool = NULL;
6779 rtx insn;
6780
6781
6782 /* Replace all literal pool references. */
6783
6784 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6785 {
6786 if (INSN_P (insn))
6787 replace_ltrel_base (&PATTERN (insn));
6788
6789 curr_pool = s390_find_pool (pool_list, insn);
6790 if (!curr_pool)
6791 continue;
6792
6793 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6794 {
6795 rtx addr, pool_ref = NULL_RTX;
6796 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6797 if (pool_ref)
6798 {
6799 if (s390_execute_label (insn))
6800 addr = s390_find_execute (curr_pool, insn);
6801 else
6802 addr = s390_find_constant (curr_pool,
6803 get_pool_constant (pool_ref),
6804 get_pool_mode (pool_ref));
6805
6806 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6807 INSN_CODE (insn) = -1;
6808 }
6809 }
6810 }
6811
6812 /* Dump out all literal pools. */
6813
6814 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6815 s390_dump_pool (curr_pool, 0);
6816
6817 /* Free pool list. */
6818
6819 while (pool_list)
6820 {
6821 struct constant_pool *next = pool_list->next;
6822 s390_free_pool (pool_list);
6823 pool_list = next;
6824 }
6825 }
6826
6827 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6828 We have decided we cannot use this list, so revert all changes
6829 to the current function that were done by s390_chunkify_start. */
6830
6831 static void
6832 s390_chunkify_cancel (struct constant_pool *pool_list)
6833 {
6834 struct constant_pool *curr_pool = NULL;
6835 rtx insn;
6836
6837 /* Remove all pool placeholder insns. */
6838
6839 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6840 {
6841 /* Did we insert an extra barrier? Remove it. */
6842 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6843 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6844 rtx label = NEXT_INSN (curr_pool->pool_insn);
6845
6846 if (jump && GET_CODE (jump) == JUMP_INSN
6847 && barrier && GET_CODE (barrier) == BARRIER
6848 && label && GET_CODE (label) == CODE_LABEL
6849 && GET_CODE (PATTERN (jump)) == SET
6850 && SET_DEST (PATTERN (jump)) == pc_rtx
6851 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6852 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6853 {
6854 remove_insn (jump);
6855 remove_insn (barrier);
6856 remove_insn (label);
6857 }
6858
6859 remove_insn (curr_pool->pool_insn);
6860 }
6861
6862 /* Remove all base register reload insns. */
6863
6864 for (insn = get_insns (); insn; )
6865 {
6866 rtx next_insn = NEXT_INSN (insn);
6867
6868 if (GET_CODE (insn) == INSN
6869 && GET_CODE (PATTERN (insn)) == SET
6870 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6871 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6872 remove_insn (insn);
6873
6874 insn = next_insn;
6875 }
6876
6877 /* Free pool list. */
6878
6879 while (pool_list)
6880 {
6881 struct constant_pool *next = pool_list->next;
6882 s390_free_pool (pool_list);
6883 pool_list = next;
6884 }
6885 }
6886
6887 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6888
6889 void
6890 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6891 {
6892 REAL_VALUE_TYPE r;
6893
6894 switch (GET_MODE_CLASS (mode))
6895 {
6896 case MODE_FLOAT:
6897 case MODE_DECIMAL_FLOAT:
6898 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6899
6900 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6901 assemble_real (r, mode, align);
6902 break;
6903
6904 case MODE_INT:
6905 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6906 mark_symbol_refs_as_used (exp);
6907 break;
6908
6909 default:
6910 gcc_unreachable ();
6911 }
6912 }
6913
6914
6915 /* Return an RTL expression representing the value of the return address
6916 for the frame COUNT steps up from the current frame. FRAME is the
6917 frame pointer of that frame. */
6918
6919 rtx
6920 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6921 {
6922 int offset;
6923 rtx addr;
6924
6925 /* Without backchain, we fail for all but the current frame. */
6926
6927 if (!TARGET_BACKCHAIN && count > 0)
6928 return NULL_RTX;
6929
6930 /* For the current frame, we need to make sure the initial
6931 value of RETURN_REGNUM is actually saved. */
6932
6933 if (count == 0)
6934 {
6935 /* On non-z architectures branch splitting could overwrite r14. */
6936 if (TARGET_CPU_ZARCH)
6937 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6938 else
6939 {
6940 cfun_frame_layout.save_return_addr_p = true;
6941 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6942 }
6943 }
6944
6945 if (TARGET_PACKED_STACK)
6946 offset = -2 * UNITS_PER_LONG;
6947 else
6948 offset = RETURN_REGNUM * UNITS_PER_LONG;
6949
6950 addr = plus_constant (frame, offset);
6951 addr = memory_address (Pmode, addr);
6952 return gen_rtx_MEM (Pmode, addr);
6953 }
6954
6955 /* Return an RTL expression representing the back chain stored in
6956 the current stack frame. */
6957
6958 rtx
6959 s390_back_chain_rtx (void)
6960 {
6961 rtx chain;
6962
6963 gcc_assert (TARGET_BACKCHAIN);
6964
6965 if (TARGET_PACKED_STACK)
6966 chain = plus_constant (stack_pointer_rtx,
6967 STACK_POINTER_OFFSET - UNITS_PER_LONG);
6968 else
6969 chain = stack_pointer_rtx;
6970
6971 chain = gen_rtx_MEM (Pmode, chain);
6972 return chain;
6973 }
6974
6975 /* Find first call clobbered register unused in a function.
6976 This could be used as base register in a leaf function
6977 or for holding the return address before epilogue. */
6978
6979 static int
6980 find_unused_clobbered_reg (void)
6981 {
6982 int i;
6983 for (i = 0; i < 6; i++)
6984 if (!df_regs_ever_live_p (i))
6985 return i;
6986 return 0;
6987 }
6988
6989
6990 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6991 clobbered hard regs in SETREG. */
6992
6993 static void
6994 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6995 {
6996 int *regs_ever_clobbered = (int *)data;
6997 unsigned int i, regno;
6998 enum machine_mode mode = GET_MODE (setreg);
6999
7000 if (GET_CODE (setreg) == SUBREG)
7001 {
7002 rtx inner = SUBREG_REG (setreg);
7003 if (!GENERAL_REG_P (inner))
7004 return;
7005 regno = subreg_regno (setreg);
7006 }
7007 else if (GENERAL_REG_P (setreg))
7008 regno = REGNO (setreg);
7009 else
7010 return;
7011
7012 for (i = regno;
7013 i < regno + HARD_REGNO_NREGS (regno, mode);
7014 i++)
7015 regs_ever_clobbered[i] = 1;
7016 }
7017
7018 /* Walks through all basic blocks of the current function looking
7019 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7020 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7021 each of those regs. */
7022
7023 static void
7024 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7025 {
7026 basic_block cur_bb;
7027 rtx cur_insn;
7028 unsigned int i;
7029
7030 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7031
7032 /* For non-leaf functions we have to consider all call clobbered regs to be
7033 clobbered. */
7034 if (!current_function_is_leaf)
7035 {
7036 for (i = 0; i < 16; i++)
7037 regs_ever_clobbered[i] = call_really_used_regs[i];
7038 }
7039
7040 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7041 this work is done by liveness analysis (mark_regs_live_at_end).
7042 Special care is needed for functions containing landing pads. Landing pads
7043 may use the eh registers, but the code which sets these registers is not
7044 contained in that function. Hence s390_regs_ever_clobbered is not able to
7045 deal with this automatically. */
7046 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7047 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7048 if (crtl->calls_eh_return
7049 || (cfun->machine->has_landing_pad_p
7050 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7051 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7052
7053 /* For nonlocal gotos all call-saved registers have to be saved.
7054 This flag is also set for the unwinding code in libgcc.
7055 See expand_builtin_unwind_init. For regs_ever_live this is done by
7056 reload. */
7057 if (cfun->has_nonlocal_label)
7058 for (i = 0; i < 16; i++)
7059 if (!call_really_used_regs[i])
7060 regs_ever_clobbered[i] = 1;
7061
7062 FOR_EACH_BB (cur_bb)
7063 {
7064 FOR_BB_INSNS (cur_bb, cur_insn)
7065 {
7066 if (INSN_P (cur_insn))
7067 note_stores (PATTERN (cur_insn),
7068 s390_reg_clobbered_rtx,
7069 regs_ever_clobbered);
7070 }
7071 }
7072 }
7073
7074 /* Determine the frame area which actually has to be accessed
7075 in the function epilogue. The values are stored at the
7076 given pointers AREA_BOTTOM (address of the lowest used stack
7077 address) and AREA_TOP (address of the first item which does
7078 not belong to the stack frame). */
7079
7080 static void
7081 s390_frame_area (int *area_bottom, int *area_top)
7082 {
7083 int b, t;
7084 int i;
7085
7086 b = INT_MAX;
7087 t = INT_MIN;
7088
7089 if (cfun_frame_layout.first_restore_gpr != -1)
7090 {
7091 b = (cfun_frame_layout.gprs_offset
7092 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7093 t = b + (cfun_frame_layout.last_restore_gpr
7094 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7095 }
7096
7097 if (TARGET_64BIT && cfun_save_high_fprs_p)
7098 {
7099 b = MIN (b, cfun_frame_layout.f8_offset);
7100 t = MAX (t, (cfun_frame_layout.f8_offset
7101 + cfun_frame_layout.high_fprs * 8));
7102 }
7103
7104 if (!TARGET_64BIT)
7105 for (i = 2; i < 4; i++)
7106 if (cfun_fpr_bit_p (i))
7107 {
7108 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7109 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7110 }
7111
7112 *area_bottom = b;
7113 *area_top = t;
7114 }
7115
7116 /* Fill cfun->machine with info about register usage of current function.
7117 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7118
7119 static void
7120 s390_register_info (int clobbered_regs[])
7121 {
7122 int i, j;
7123
7124 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7125 cfun_frame_layout.fpr_bitmap = 0;
7126 cfun_frame_layout.high_fprs = 0;
7127 if (TARGET_64BIT)
7128 for (i = 24; i < 32; i++)
7129 if (df_regs_ever_live_p (i) && !global_regs[i])
7130 {
7131 cfun_set_fpr_bit (i - 16);
7132 cfun_frame_layout.high_fprs++;
7133 }
7134
7135 /* Find first and last gpr to be saved. We trust regs_ever_live
7136 data, except that we don't save and restore global registers.
7137
7138 Also, all registers with special meaning to the compiler need
7139 to be handled extra. */
7140
7141 s390_regs_ever_clobbered (clobbered_regs);
7142
7143 for (i = 0; i < 16; i++)
7144 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7145
7146 if (frame_pointer_needed)
7147 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7148
7149 if (flag_pic)
7150 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7151 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7152
7153 clobbered_regs[BASE_REGNUM]
7154 |= (cfun->machine->base_reg
7155 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7156
7157 clobbered_regs[RETURN_REGNUM]
7158 |= (!current_function_is_leaf
7159 || TARGET_TPF_PROFILING
7160 || cfun->machine->split_branches_pending_p
7161 || cfun_frame_layout.save_return_addr_p
7162 || crtl->calls_eh_return
7163 || cfun->stdarg);
7164
7165 clobbered_regs[STACK_POINTER_REGNUM]
7166 |= (!current_function_is_leaf
7167 || TARGET_TPF_PROFILING
7168 || cfun_save_high_fprs_p
7169 || get_frame_size () > 0
7170 || cfun->calls_alloca
7171 || cfun->stdarg);
7172
7173 for (i = 6; i < 16; i++)
7174 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7175 break;
7176 for (j = 15; j > i; j--)
7177 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7178 break;
7179
7180 if (i == 16)
7181 {
7182 /* Nothing to save/restore. */
7183 cfun_frame_layout.first_save_gpr_slot = -1;
7184 cfun_frame_layout.last_save_gpr_slot = -1;
7185 cfun_frame_layout.first_save_gpr = -1;
7186 cfun_frame_layout.first_restore_gpr = -1;
7187 cfun_frame_layout.last_save_gpr = -1;
7188 cfun_frame_layout.last_restore_gpr = -1;
7189 }
7190 else
7191 {
7192 /* Save slots for gprs from i to j. */
7193 cfun_frame_layout.first_save_gpr_slot = i;
7194 cfun_frame_layout.last_save_gpr_slot = j;
7195
7196 for (i = cfun_frame_layout.first_save_gpr_slot;
7197 i < cfun_frame_layout.last_save_gpr_slot + 1;
7198 i++)
7199 if (clobbered_regs[i])
7200 break;
7201
7202 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7203 if (clobbered_regs[j])
7204 break;
7205
7206 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7207 {
7208 /* Nothing to save/restore. */
7209 cfun_frame_layout.first_save_gpr = -1;
7210 cfun_frame_layout.first_restore_gpr = -1;
7211 cfun_frame_layout.last_save_gpr = -1;
7212 cfun_frame_layout.last_restore_gpr = -1;
7213 }
7214 else
7215 {
7216 /* Save / Restore from gpr i to j. */
7217 cfun_frame_layout.first_save_gpr = i;
7218 cfun_frame_layout.first_restore_gpr = i;
7219 cfun_frame_layout.last_save_gpr = j;
7220 cfun_frame_layout.last_restore_gpr = j;
7221 }
7222 }
7223
7224 if (cfun->stdarg)
7225 {
7226 /* Varargs functions need to save gprs 2 to 6. */
7227 if (cfun->va_list_gpr_size
7228 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7229 {
7230 int min_gpr = crtl->args.info.gprs;
7231 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7232 if (max_gpr > GP_ARG_NUM_REG)
7233 max_gpr = GP_ARG_NUM_REG;
7234
7235 if (cfun_frame_layout.first_save_gpr == -1
7236 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7237 {
7238 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7239 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7240 }
7241
7242 if (cfun_frame_layout.last_save_gpr == -1
7243 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7244 {
7245 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7246 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7247 }
7248 }
7249
7250 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7251 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7252 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7253 {
7254 int min_fpr = crtl->args.info.fprs;
7255 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7256 if (max_fpr > FP_ARG_NUM_REG)
7257 max_fpr = FP_ARG_NUM_REG;
7258
7259 /* ??? This is currently required to ensure proper location
7260 of the fpr save slots within the va_list save area. */
7261 if (TARGET_PACKED_STACK)
7262 min_fpr = 0;
7263
7264 for (i = min_fpr; i < max_fpr; i++)
7265 cfun_set_fpr_bit (i);
7266 }
7267 }
7268
7269 if (!TARGET_64BIT)
7270 for (i = 2; i < 4; i++)
7271 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7272 cfun_set_fpr_bit (i);
7273 }
7274
7275 /* Fill cfun->machine with info about frame of current function. */
7276
7277 static void
7278 s390_frame_info (void)
7279 {
7280 int i;
7281
7282 cfun_frame_layout.frame_size = get_frame_size ();
7283 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7284 fatal_error ("total size of local variables exceeds architecture limit");
7285
7286 if (!TARGET_PACKED_STACK)
7287 {
7288 cfun_frame_layout.backchain_offset = 0;
7289 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7290 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7291 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7292 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7293 * UNITS_PER_LONG);
7294 }
7295 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7296 {
7297 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7298 - UNITS_PER_LONG);
7299 cfun_frame_layout.gprs_offset
7300 = (cfun_frame_layout.backchain_offset
7301 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7302 * UNITS_PER_LONG);
7303
7304 if (TARGET_64BIT)
7305 {
7306 cfun_frame_layout.f4_offset
7307 = (cfun_frame_layout.gprs_offset
7308 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7309
7310 cfun_frame_layout.f0_offset
7311 = (cfun_frame_layout.f4_offset
7312 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7313 }
7314 else
7315 {
7316 /* On 31 bit we have to care about alignment of the
7317 floating point regs to provide fastest access. */
7318 cfun_frame_layout.f0_offset
7319 = ((cfun_frame_layout.gprs_offset
7320 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7321 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7322
7323 cfun_frame_layout.f4_offset
7324 = (cfun_frame_layout.f0_offset
7325 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7326 }
7327 }
7328 else /* no backchain */
7329 {
7330 cfun_frame_layout.f4_offset
7331 = (STACK_POINTER_OFFSET
7332 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7333
7334 cfun_frame_layout.f0_offset
7335 = (cfun_frame_layout.f4_offset
7336 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7337
7338 cfun_frame_layout.gprs_offset
7339 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7340 }
7341
7342 if (current_function_is_leaf
7343 && !TARGET_TPF_PROFILING
7344 && cfun_frame_layout.frame_size == 0
7345 && !cfun_save_high_fprs_p
7346 && !cfun->calls_alloca
7347 && !cfun->stdarg)
7348 return;
7349
7350 if (!TARGET_PACKED_STACK)
7351 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7352 + crtl->outgoing_args_size
7353 + cfun_frame_layout.high_fprs * 8);
7354 else
7355 {
7356 if (TARGET_BACKCHAIN)
7357 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7358
7359 /* No alignment trouble here because f8-f15 are only saved under
7360 64 bit. */
7361 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7362 cfun_frame_layout.f4_offset),
7363 cfun_frame_layout.gprs_offset)
7364 - cfun_frame_layout.high_fprs * 8);
7365
7366 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7367
7368 for (i = 0; i < 8; i++)
7369 if (cfun_fpr_bit_p (i))
7370 cfun_frame_layout.frame_size += 8;
7371
7372 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7373
7374 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7375 the frame size to sustain 8 byte alignment of stack frames. */
7376 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7377 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7378 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7379
7380 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7381 }
7382 }
7383
7384 /* Generate frame layout. Fills in register and frame data for the current
7385 function in cfun->machine. This routine can be called multiple times;
7386 it will re-do the complete frame layout every time. */
7387
7388 static void
7389 s390_init_frame_layout (void)
7390 {
7391 HOST_WIDE_INT frame_size;
7392 int base_used;
7393 int clobbered_regs[16];
7394
7395 /* On S/390 machines, we may need to perform branch splitting, which
7396 will require both base and return address register. We have no
7397 choice but to assume we're going to need them until right at the
7398 end of the machine dependent reorg phase. */
7399 if (!TARGET_CPU_ZARCH)
7400 cfun->machine->split_branches_pending_p = true;
7401
7402 do
7403 {
7404 frame_size = cfun_frame_layout.frame_size;
7405
7406 /* Try to predict whether we'll need the base register. */
7407 base_used = cfun->machine->split_branches_pending_p
7408 || crtl->uses_const_pool
7409 || (!DISP_IN_RANGE (frame_size)
7410 && !CONST_OK_FOR_K (frame_size));
7411
7412 /* Decide which register to use as literal pool base. In small
7413 leaf functions, try to use an unused call-clobbered register
7414 as base register to avoid save/restore overhead. */
7415 if (!base_used)
7416 cfun->machine->base_reg = NULL_RTX;
7417 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7418 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7419 else
7420 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7421
7422 s390_register_info (clobbered_regs);
7423 s390_frame_info ();
7424 }
7425 while (frame_size != cfun_frame_layout.frame_size);
7426 }
7427
7428 /* Update frame layout. Recompute actual register save data based on
7429 current info and update regs_ever_live for the special registers.
7430 May be called multiple times, but may never cause *more* registers
7431 to be saved than s390_init_frame_layout allocated room for. */
7432
7433 static void
7434 s390_update_frame_layout (void)
7435 {
7436 int clobbered_regs[16];
7437
7438 s390_register_info (clobbered_regs);
7439
7440 df_set_regs_ever_live (BASE_REGNUM,
7441 clobbered_regs[BASE_REGNUM] ? true : false);
7442 df_set_regs_ever_live (RETURN_REGNUM,
7443 clobbered_regs[RETURN_REGNUM] ? true : false);
7444 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7445 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7446
7447 if (cfun->machine->base_reg)
7448 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7449 }
7450
7451 /* Return true if it is legal to put a value with MODE into REGNO. */
7452
7453 bool
7454 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7455 {
7456 switch (REGNO_REG_CLASS (regno))
7457 {
7458 case FP_REGS:
7459 if (REGNO_PAIR_OK (regno, mode))
7460 {
7461 if (mode == SImode || mode == DImode)
7462 return true;
7463
7464 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7465 return true;
7466 }
7467 break;
7468 case ADDR_REGS:
7469 if (FRAME_REGNO_P (regno) && mode == Pmode)
7470 return true;
7471
7472 /* fallthrough */
7473 case GENERAL_REGS:
7474 if (REGNO_PAIR_OK (regno, mode))
7475 {
7476 if (TARGET_ZARCH
7477 || (mode != TFmode && mode != TCmode && mode != TDmode))
7478 return true;
7479 }
7480 break;
7481 case CC_REGS:
7482 if (GET_MODE_CLASS (mode) == MODE_CC)
7483 return true;
7484 break;
7485 case ACCESS_REGS:
7486 if (REGNO_PAIR_OK (regno, mode))
7487 {
7488 if (mode == SImode || mode == Pmode)
7489 return true;
7490 }
7491 break;
7492 default:
7493 return false;
7494 }
7495
7496 return false;
7497 }
7498
7499 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7500
7501 bool
7502 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7503 {
7504 /* Once we've decided upon a register to use as base register, it must
7505 no longer be used for any other purpose. */
7506 if (cfun->machine->base_reg)
7507 if (REGNO (cfun->machine->base_reg) == old_reg
7508 || REGNO (cfun->machine->base_reg) == new_reg)
7509 return false;
7510
7511 return true;
7512 }
7513
7514 /* Maximum number of registers to represent a value of mode MODE
7515 in a register of class RCLASS. */
7516
7517 bool
7518 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7519 {
7520 switch (rclass)
7521 {
7522 case FP_REGS:
7523 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7524 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7525 else
7526 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7527 case ACCESS_REGS:
7528 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7529 default:
7530 break;
7531 }
7532 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7533 }
7534
7535 /* Return true if register FROM can be eliminated via register TO. */
7536
7537 static bool
7538 s390_can_eliminate (const int from, const int to)
7539 {
7540 /* On zSeries machines, we have not marked the base register as fixed.
7541 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7542 If a function requires the base register, we say here that this
7543 elimination cannot be performed. This will cause reload to free
7544 up the base register (as if it were fixed). On the other hand,
7545 if the current function does *not* require the base register, we
7546 say here the elimination succeeds, which in turn allows reload
7547 to allocate the base register for any other purpose. */
7548 if (from == BASE_REGNUM && to == BASE_REGNUM)
7549 {
7550 if (TARGET_CPU_ZARCH)
7551 {
7552 s390_init_frame_layout ();
7553 return cfun->machine->base_reg == NULL_RTX;
7554 }
7555
7556 return false;
7557 }
7558
7559 /* Everything else must point into the stack frame. */
7560 gcc_assert (to == STACK_POINTER_REGNUM
7561 || to == HARD_FRAME_POINTER_REGNUM);
7562
7563 gcc_assert (from == FRAME_POINTER_REGNUM
7564 || from == ARG_POINTER_REGNUM
7565 || from == RETURN_ADDRESS_POINTER_REGNUM);
7566
7567 /* Make sure we actually saved the return address. */
7568 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7569 if (!crtl->calls_eh_return
7570 && !cfun->stdarg
7571 && !cfun_frame_layout.save_return_addr_p)
7572 return false;
7573
7574 return true;
7575 }
7576
7577 /* Return offset between register FROM and TO initially after prolog. */
7578
7579 HOST_WIDE_INT
7580 s390_initial_elimination_offset (int from, int to)
7581 {
7582 HOST_WIDE_INT offset;
7583 int index;
7584
7585 /* ??? Why are we called for non-eliminable pairs? */
7586 if (!s390_can_eliminate (from, to))
7587 return 0;
7588
7589 switch (from)
7590 {
7591 case FRAME_POINTER_REGNUM:
7592 offset = (get_frame_size()
7593 + STACK_POINTER_OFFSET
7594 + crtl->outgoing_args_size);
7595 break;
7596
7597 case ARG_POINTER_REGNUM:
7598 s390_init_frame_layout ();
7599 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7600 break;
7601
7602 case RETURN_ADDRESS_POINTER_REGNUM:
7603 s390_init_frame_layout ();
7604 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7605 gcc_assert (index >= 0);
7606 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7607 offset += index * UNITS_PER_LONG;
7608 break;
7609
7610 case BASE_REGNUM:
7611 offset = 0;
7612 break;
7613
7614 default:
7615 gcc_unreachable ();
7616 }
7617
7618 return offset;
7619 }
7620
7621 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7622 to register BASE. Return generated insn. */
7623
7624 static rtx
7625 save_fpr (rtx base, int offset, int regnum)
7626 {
7627 rtx addr;
7628 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7629
7630 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7631 set_mem_alias_set (addr, get_varargs_alias_set ());
7632 else
7633 set_mem_alias_set (addr, get_frame_alias_set ());
7634
7635 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7636 }
7637
7638 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7639 to register BASE. Return generated insn. */
7640
7641 static rtx
7642 restore_fpr (rtx base, int offset, int regnum)
7643 {
7644 rtx addr;
7645 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7646 set_mem_alias_set (addr, get_frame_alias_set ());
7647
7648 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7649 }
7650
7651 /* Return true if REGNO is a global register, but not one
7652 of the special ones that need to be saved/restored in anyway. */
7653
7654 static inline bool
7655 global_not_special_regno_p (int regno)
7656 {
7657 return (global_regs[regno]
7658 /* These registers are special and need to be
7659 restored in any case. */
7660 && !(regno == STACK_POINTER_REGNUM
7661 || regno == RETURN_REGNUM
7662 || regno == BASE_REGNUM
7663 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7664 }
7665
7666 /* Generate insn to save registers FIRST to LAST into
7667 the register save area located at offset OFFSET
7668 relative to register BASE. */
7669
7670 static rtx
7671 save_gprs (rtx base, int offset, int first, int last)
7672 {
7673 rtx addr, insn, note;
7674 int i;
7675
7676 addr = plus_constant (base, offset);
7677 addr = gen_rtx_MEM (Pmode, addr);
7678
7679 set_mem_alias_set (addr, get_frame_alias_set ());
7680
7681 /* Special-case single register. */
7682 if (first == last)
7683 {
7684 if (TARGET_64BIT)
7685 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7686 else
7687 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7688
7689 if (!global_not_special_regno_p (first))
7690 RTX_FRAME_RELATED_P (insn) = 1;
7691 return insn;
7692 }
7693
7694
7695 insn = gen_store_multiple (addr,
7696 gen_rtx_REG (Pmode, first),
7697 GEN_INT (last - first + 1));
7698
7699 if (first <= 6 && cfun->stdarg)
7700 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7701 {
7702 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7703
7704 if (first + i <= 6)
7705 set_mem_alias_set (mem, get_varargs_alias_set ());
7706 }
7707
7708 /* We need to set the FRAME_RELATED flag on all SETs
7709 inside the store-multiple pattern.
7710
7711 However, we must not emit DWARF records for registers 2..5
7712 if they are stored for use by variable arguments ...
7713
7714 ??? Unfortunately, it is not enough to simply not the
7715 FRAME_RELATED flags for those SETs, because the first SET
7716 of the PARALLEL is always treated as if it had the flag
7717 set, even if it does not. Therefore we emit a new pattern
7718 without those registers as REG_FRAME_RELATED_EXPR note. */
7719
7720 if (first >= 6 && !global_not_special_regno_p (first))
7721 {
7722 rtx pat = PATTERN (insn);
7723
7724 for (i = 0; i < XVECLEN (pat, 0); i++)
7725 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7726 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7727 0, i)))))
7728 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7729
7730 RTX_FRAME_RELATED_P (insn) = 1;
7731 }
7732 else if (last >= 6)
7733 {
7734 int start;
7735
7736 for (start = first >= 6 ? first : 6; start <= last; start++)
7737 if (!global_not_special_regno_p (start))
7738 break;
7739
7740 if (start > last)
7741 return insn;
7742
7743 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7744 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7745 gen_rtx_REG (Pmode, start),
7746 GEN_INT (last - start + 1));
7747 note = PATTERN (note);
7748
7749 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7750
7751 for (i = 0; i < XVECLEN (note, 0); i++)
7752 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7753 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7754 0, i)))))
7755 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7756
7757 RTX_FRAME_RELATED_P (insn) = 1;
7758 }
7759
7760 return insn;
7761 }
7762
7763 /* Generate insn to restore registers FIRST to LAST from
7764 the register save area located at offset OFFSET
7765 relative to register BASE. */
7766
7767 static rtx
7768 restore_gprs (rtx base, int offset, int first, int last)
7769 {
7770 rtx addr, insn;
7771
7772 addr = plus_constant (base, offset);
7773 addr = gen_rtx_MEM (Pmode, addr);
7774 set_mem_alias_set (addr, get_frame_alias_set ());
7775
7776 /* Special-case single register. */
7777 if (first == last)
7778 {
7779 if (TARGET_64BIT)
7780 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7781 else
7782 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7783
7784 return insn;
7785 }
7786
7787 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7788 addr,
7789 GEN_INT (last - first + 1));
7790 return insn;
7791 }
7792
7793 /* Return insn sequence to load the GOT register. */
7794
7795 static GTY(()) rtx got_symbol;
7796 rtx
7797 s390_load_got (void)
7798 {
7799 rtx insns;
7800
7801 if (!got_symbol)
7802 {
7803 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7804 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7805 }
7806
7807 start_sequence ();
7808
7809 if (TARGET_CPU_ZARCH)
7810 {
7811 emit_move_insn (pic_offset_table_rtx, got_symbol);
7812 }
7813 else
7814 {
7815 rtx offset;
7816
7817 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7818 UNSPEC_LTREL_OFFSET);
7819 offset = gen_rtx_CONST (Pmode, offset);
7820 offset = force_const_mem (Pmode, offset);
7821
7822 emit_move_insn (pic_offset_table_rtx, offset);
7823
7824 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7825 UNSPEC_LTREL_BASE);
7826 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7827
7828 emit_move_insn (pic_offset_table_rtx, offset);
7829 }
7830
7831 insns = get_insns ();
7832 end_sequence ();
7833 return insns;
7834 }
7835
7836 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7837 and the change to the stack pointer. */
7838
7839 static void
7840 s390_emit_stack_tie (void)
7841 {
7842 rtx mem = gen_frame_mem (BLKmode,
7843 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7844
7845 emit_insn (gen_stack_tie (mem));
7846 }
7847
7848 /* Expand the prologue into a bunch of separate insns. */
7849
7850 void
7851 s390_emit_prologue (void)
7852 {
7853 rtx insn, addr;
7854 rtx temp_reg;
7855 int i;
7856 int offset;
7857 int next_fpr = 0;
7858
7859 /* Complete frame layout. */
7860
7861 s390_update_frame_layout ();
7862
7863 /* Annotate all constant pool references to let the scheduler know
7864 they implicitly use the base register. */
7865
7866 push_topmost_sequence ();
7867
7868 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7869 if (INSN_P (insn))
7870 {
7871 annotate_constant_pool_refs (&PATTERN (insn));
7872 df_insn_rescan (insn);
7873 }
7874
7875 pop_topmost_sequence ();
7876
7877 /* Choose best register to use for temp use within prologue.
7878 See below for why TPF must use the register 1. */
7879
7880 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7881 && !current_function_is_leaf
7882 && !TARGET_TPF_PROFILING)
7883 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7884 else
7885 temp_reg = gen_rtx_REG (Pmode, 1);
7886
7887 /* Save call saved gprs. */
7888 if (cfun_frame_layout.first_save_gpr != -1)
7889 {
7890 insn = save_gprs (stack_pointer_rtx,
7891 cfun_frame_layout.gprs_offset +
7892 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7893 - cfun_frame_layout.first_save_gpr_slot),
7894 cfun_frame_layout.first_save_gpr,
7895 cfun_frame_layout.last_save_gpr);
7896 emit_insn (insn);
7897 }
7898
7899 /* Dummy insn to mark literal pool slot. */
7900
7901 if (cfun->machine->base_reg)
7902 emit_insn (gen_main_pool (cfun->machine->base_reg));
7903
7904 offset = cfun_frame_layout.f0_offset;
7905
7906 /* Save f0 and f2. */
7907 for (i = 0; i < 2; i++)
7908 {
7909 if (cfun_fpr_bit_p (i))
7910 {
7911 save_fpr (stack_pointer_rtx, offset, i + 16);
7912 offset += 8;
7913 }
7914 else if (!TARGET_PACKED_STACK)
7915 offset += 8;
7916 }
7917
7918 /* Save f4 and f6. */
7919 offset = cfun_frame_layout.f4_offset;
7920 for (i = 2; i < 4; i++)
7921 {
7922 if (cfun_fpr_bit_p (i))
7923 {
7924 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7925 offset += 8;
7926
7927 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7928 therefore are not frame related. */
7929 if (!call_really_used_regs[i + 16])
7930 RTX_FRAME_RELATED_P (insn) = 1;
7931 }
7932 else if (!TARGET_PACKED_STACK)
7933 offset += 8;
7934 }
7935
7936 if (TARGET_PACKED_STACK
7937 && cfun_save_high_fprs_p
7938 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7939 {
7940 offset = (cfun_frame_layout.f8_offset
7941 + (cfun_frame_layout.high_fprs - 1) * 8);
7942
7943 for (i = 15; i > 7 && offset >= 0; i--)
7944 if (cfun_fpr_bit_p (i))
7945 {
7946 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7947
7948 RTX_FRAME_RELATED_P (insn) = 1;
7949 offset -= 8;
7950 }
7951 if (offset >= cfun_frame_layout.f8_offset)
7952 next_fpr = i + 16;
7953 }
7954
7955 if (!TARGET_PACKED_STACK)
7956 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7957
7958 if (flag_stack_usage)
7959 current_function_static_stack_size = cfun_frame_layout.frame_size;
7960
7961 /* Decrement stack pointer. */
7962
7963 if (cfun_frame_layout.frame_size > 0)
7964 {
7965 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7966 rtx real_frame_off;
7967
7968 if (s390_stack_size)
7969 {
7970 HOST_WIDE_INT stack_guard;
7971
7972 if (s390_stack_guard)
7973 stack_guard = s390_stack_guard;
7974 else
7975 {
7976 /* If no value for stack guard is provided the smallest power of 2
7977 larger than the current frame size is chosen. */
7978 stack_guard = 1;
7979 while (stack_guard < cfun_frame_layout.frame_size)
7980 stack_guard <<= 1;
7981 }
7982
7983 if (cfun_frame_layout.frame_size >= s390_stack_size)
7984 {
7985 warning (0, "frame size of function %qs is "
7986 HOST_WIDE_INT_PRINT_DEC
7987 " bytes exceeding user provided stack limit of "
7988 HOST_WIDE_INT_PRINT_DEC " bytes. "
7989 "An unconditional trap is added.",
7990 current_function_name(), cfun_frame_layout.frame_size,
7991 s390_stack_size);
7992 emit_insn (gen_trap ());
7993 }
7994 else
7995 {
7996 /* stack_guard has to be smaller than s390_stack_size.
7997 Otherwise we would emit an AND with zero which would
7998 not match the test under mask pattern. */
7999 if (stack_guard >= s390_stack_size)
8000 {
8001 warning (0, "frame size of function %qs is "
8002 HOST_WIDE_INT_PRINT_DEC
8003 " bytes which is more than half the stack size. "
8004 "The dynamic check would not be reliable. "
8005 "No check emitted for this function.",
8006 current_function_name(),
8007 cfun_frame_layout.frame_size);
8008 }
8009 else
8010 {
8011 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8012 & ~(stack_guard - 1));
8013
8014 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8015 GEN_INT (stack_check_mask));
8016 if (TARGET_64BIT)
8017 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8018 t, const0_rtx),
8019 t, const0_rtx, const0_rtx));
8020 else
8021 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8022 t, const0_rtx),
8023 t, const0_rtx, const0_rtx));
8024 }
8025 }
8026 }
8027
8028 if (s390_warn_framesize > 0
8029 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8030 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
8031 current_function_name (), cfun_frame_layout.frame_size);
8032
8033 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8034 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8035
8036 /* Save incoming stack pointer into temp reg. */
8037 if (TARGET_BACKCHAIN || next_fpr)
8038 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8039
8040 /* Subtract frame size from stack pointer. */
8041
8042 if (DISP_IN_RANGE (INTVAL (frame_off)))
8043 {
8044 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8045 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8046 frame_off));
8047 insn = emit_insn (insn);
8048 }
8049 else
8050 {
8051 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8052 frame_off = force_const_mem (Pmode, frame_off);
8053
8054 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8055 annotate_constant_pool_refs (&PATTERN (insn));
8056 }
8057
8058 RTX_FRAME_RELATED_P (insn) = 1;
8059 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8060 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8061 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8062 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8063 real_frame_off)));
8064
8065 /* Set backchain. */
8066
8067 if (TARGET_BACKCHAIN)
8068 {
8069 if (cfun_frame_layout.backchain_offset)
8070 addr = gen_rtx_MEM (Pmode,
8071 plus_constant (stack_pointer_rtx,
8072 cfun_frame_layout.backchain_offset));
8073 else
8074 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8075 set_mem_alias_set (addr, get_frame_alias_set ());
8076 insn = emit_insn (gen_move_insn (addr, temp_reg));
8077 }
8078
8079 /* If we support non-call exceptions (e.g. for Java),
8080 we need to make sure the backchain pointer is set up
8081 before any possibly trapping memory access. */
8082 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8083 {
8084 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8085 emit_clobber (addr);
8086 }
8087 }
8088
8089 /* Save fprs 8 - 15 (64 bit ABI). */
8090
8091 if (cfun_save_high_fprs_p && next_fpr)
8092 {
8093 /* If the stack might be accessed through a different register
8094 we have to make sure that the stack pointer decrement is not
8095 moved below the use of the stack slots. */
8096 s390_emit_stack_tie ();
8097
8098 insn = emit_insn (gen_add2_insn (temp_reg,
8099 GEN_INT (cfun_frame_layout.f8_offset)));
8100
8101 offset = 0;
8102
8103 for (i = 24; i <= next_fpr; i++)
8104 if (cfun_fpr_bit_p (i - 16))
8105 {
8106 rtx addr = plus_constant (stack_pointer_rtx,
8107 cfun_frame_layout.frame_size
8108 + cfun_frame_layout.f8_offset
8109 + offset);
8110
8111 insn = save_fpr (temp_reg, offset, i);
8112 offset += 8;
8113 RTX_FRAME_RELATED_P (insn) = 1;
8114 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8115 gen_rtx_SET (VOIDmode,
8116 gen_rtx_MEM (DFmode, addr),
8117 gen_rtx_REG (DFmode, i)));
8118 }
8119 }
8120
8121 /* Set frame pointer, if needed. */
8122
8123 if (frame_pointer_needed)
8124 {
8125 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8126 RTX_FRAME_RELATED_P (insn) = 1;
8127 }
8128
8129 /* Set up got pointer, if needed. */
8130
8131 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8132 {
8133 rtx insns = s390_load_got ();
8134
8135 for (insn = insns; insn; insn = NEXT_INSN (insn))
8136 annotate_constant_pool_refs (&PATTERN (insn));
8137
8138 emit_insn (insns);
8139 }
8140
8141 if (TARGET_TPF_PROFILING)
8142 {
8143 /* Generate a BAS instruction to serve as a function
8144 entry intercept to facilitate the use of tracing
8145 algorithms located at the branch target. */
8146 emit_insn (gen_prologue_tpf ());
8147
8148 /* Emit a blockage here so that all code
8149 lies between the profiling mechanisms. */
8150 emit_insn (gen_blockage ());
8151 }
8152 }
8153
8154 /* Expand the epilogue into a bunch of separate insns. */
8155
8156 void
8157 s390_emit_epilogue (bool sibcall)
8158 {
8159 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8160 int area_bottom, area_top, offset = 0;
8161 int next_offset;
8162 rtvec p;
8163 int i;
8164
8165 if (TARGET_TPF_PROFILING)
8166 {
8167
8168 /* Generate a BAS instruction to serve as a function
8169 entry intercept to facilitate the use of tracing
8170 algorithms located at the branch target. */
8171
8172 /* Emit a blockage here so that all code
8173 lies between the profiling mechanisms. */
8174 emit_insn (gen_blockage ());
8175
8176 emit_insn (gen_epilogue_tpf ());
8177 }
8178
8179 /* Check whether to use frame or stack pointer for restore. */
8180
8181 frame_pointer = (frame_pointer_needed
8182 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8183
8184 s390_frame_area (&area_bottom, &area_top);
8185
8186 /* Check whether we can access the register save area.
8187 If not, increment the frame pointer as required. */
8188
8189 if (area_top <= area_bottom)
8190 {
8191 /* Nothing to restore. */
8192 }
8193 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8194 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8195 {
8196 /* Area is in range. */
8197 offset = cfun_frame_layout.frame_size;
8198 }
8199 else
8200 {
8201 rtx insn, frame_off, cfa;
8202
8203 offset = area_bottom < 0 ? -area_bottom : 0;
8204 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8205
8206 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8207 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8208 if (DISP_IN_RANGE (INTVAL (frame_off)))
8209 {
8210 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8211 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8212 insn = emit_insn (insn);
8213 }
8214 else
8215 {
8216 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8217 frame_off = force_const_mem (Pmode, frame_off);
8218
8219 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8220 annotate_constant_pool_refs (&PATTERN (insn));
8221 }
8222 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8223 RTX_FRAME_RELATED_P (insn) = 1;
8224 }
8225
8226 /* Restore call saved fprs. */
8227
8228 if (TARGET_64BIT)
8229 {
8230 if (cfun_save_high_fprs_p)
8231 {
8232 next_offset = cfun_frame_layout.f8_offset;
8233 for (i = 24; i < 32; i++)
8234 {
8235 if (cfun_fpr_bit_p (i - 16))
8236 {
8237 restore_fpr (frame_pointer,
8238 offset + next_offset, i);
8239 cfa_restores
8240 = alloc_reg_note (REG_CFA_RESTORE,
8241 gen_rtx_REG (DFmode, i), cfa_restores);
8242 next_offset += 8;
8243 }
8244 }
8245 }
8246
8247 }
8248 else
8249 {
8250 next_offset = cfun_frame_layout.f4_offset;
8251 for (i = 18; i < 20; i++)
8252 {
8253 if (cfun_fpr_bit_p (i - 16))
8254 {
8255 restore_fpr (frame_pointer,
8256 offset + next_offset, i);
8257 cfa_restores
8258 = alloc_reg_note (REG_CFA_RESTORE,
8259 gen_rtx_REG (DFmode, i), cfa_restores);
8260 next_offset += 8;
8261 }
8262 else if (!TARGET_PACKED_STACK)
8263 next_offset += 8;
8264 }
8265
8266 }
8267
8268 /* Return register. */
8269
8270 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8271
8272 /* Restore call saved gprs. */
8273
8274 if (cfun_frame_layout.first_restore_gpr != -1)
8275 {
8276 rtx insn, addr;
8277 int i;
8278
8279 /* Check for global register and save them
8280 to stack location from where they get restored. */
8281
8282 for (i = cfun_frame_layout.first_restore_gpr;
8283 i <= cfun_frame_layout.last_restore_gpr;
8284 i++)
8285 {
8286 if (global_not_special_regno_p (i))
8287 {
8288 addr = plus_constant (frame_pointer,
8289 offset + cfun_frame_layout.gprs_offset
8290 + (i - cfun_frame_layout.first_save_gpr_slot)
8291 * UNITS_PER_LONG);
8292 addr = gen_rtx_MEM (Pmode, addr);
8293 set_mem_alias_set (addr, get_frame_alias_set ());
8294 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8295 }
8296 else
8297 cfa_restores
8298 = alloc_reg_note (REG_CFA_RESTORE,
8299 gen_rtx_REG (Pmode, i), cfa_restores);
8300 }
8301
8302 if (! sibcall)
8303 {
8304 /* Fetch return address from stack before load multiple,
8305 this will do good for scheduling. */
8306
8307 if (cfun_frame_layout.save_return_addr_p
8308 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8309 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8310 {
8311 int return_regnum = find_unused_clobbered_reg();
8312 if (!return_regnum)
8313 return_regnum = 4;
8314 return_reg = gen_rtx_REG (Pmode, return_regnum);
8315
8316 addr = plus_constant (frame_pointer,
8317 offset + cfun_frame_layout.gprs_offset
8318 + (RETURN_REGNUM
8319 - cfun_frame_layout.first_save_gpr_slot)
8320 * UNITS_PER_LONG);
8321 addr = gen_rtx_MEM (Pmode, addr);
8322 set_mem_alias_set (addr, get_frame_alias_set ());
8323 emit_move_insn (return_reg, addr);
8324 }
8325 }
8326
8327 insn = restore_gprs (frame_pointer,
8328 offset + cfun_frame_layout.gprs_offset
8329 + (cfun_frame_layout.first_restore_gpr
8330 - cfun_frame_layout.first_save_gpr_slot)
8331 * UNITS_PER_LONG,
8332 cfun_frame_layout.first_restore_gpr,
8333 cfun_frame_layout.last_restore_gpr);
8334 insn = emit_insn (insn);
8335 REG_NOTES (insn) = cfa_restores;
8336 add_reg_note (insn, REG_CFA_DEF_CFA,
8337 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8338 RTX_FRAME_RELATED_P (insn) = 1;
8339 }
8340
8341 if (! sibcall)
8342 {
8343
8344 /* Return to caller. */
8345
8346 p = rtvec_alloc (2);
8347
8348 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8349 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8350 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8351 }
8352 }
8353
8354
8355 /* Return the size in bytes of a function argument of
8356 type TYPE and/or mode MODE. At least one of TYPE or
8357 MODE must be specified. */
8358
8359 static int
8360 s390_function_arg_size (enum machine_mode mode, const_tree type)
8361 {
8362 if (type)
8363 return int_size_in_bytes (type);
8364
8365 /* No type info available for some library calls ... */
8366 if (mode != BLKmode)
8367 return GET_MODE_SIZE (mode);
8368
8369 /* If we have neither type nor mode, abort */
8370 gcc_unreachable ();
8371 }
8372
8373 /* Return true if a function argument of type TYPE and mode MODE
8374 is to be passed in a floating-point register, if available. */
8375
8376 static bool
8377 s390_function_arg_float (enum machine_mode mode, const_tree type)
8378 {
8379 int size = s390_function_arg_size (mode, type);
8380 if (size > 8)
8381 return false;
8382
8383 /* Soft-float changes the ABI: no floating-point registers are used. */
8384 if (TARGET_SOFT_FLOAT)
8385 return false;
8386
8387 /* No type info available for some library calls ... */
8388 if (!type)
8389 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8390
8391 /* The ABI says that record types with a single member are treated
8392 just like that member would be. */
8393 while (TREE_CODE (type) == RECORD_TYPE)
8394 {
8395 tree field, single = NULL_TREE;
8396
8397 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8398 {
8399 if (TREE_CODE (field) != FIELD_DECL)
8400 continue;
8401
8402 if (single == NULL_TREE)
8403 single = TREE_TYPE (field);
8404 else
8405 return false;
8406 }
8407
8408 if (single == NULL_TREE)
8409 return false;
8410 else
8411 type = single;
8412 }
8413
8414 return TREE_CODE (type) == REAL_TYPE;
8415 }
8416
8417 /* Return true if a function argument of type TYPE and mode MODE
8418 is to be passed in an integer register, or a pair of integer
8419 registers, if available. */
8420
8421 static bool
8422 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8423 {
8424 int size = s390_function_arg_size (mode, type);
8425 if (size > 8)
8426 return false;
8427
8428 /* No type info available for some library calls ... */
8429 if (!type)
8430 return GET_MODE_CLASS (mode) == MODE_INT
8431 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8432
8433 /* We accept small integral (and similar) types. */
8434 if (INTEGRAL_TYPE_P (type)
8435 || POINTER_TYPE_P (type)
8436 || TREE_CODE (type) == NULLPTR_TYPE
8437 || TREE_CODE (type) == OFFSET_TYPE
8438 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8439 return true;
8440
8441 /* We also accept structs of size 1, 2, 4, 8 that are not
8442 passed in floating-point registers. */
8443 if (AGGREGATE_TYPE_P (type)
8444 && exact_log2 (size) >= 0
8445 && !s390_function_arg_float (mode, type))
8446 return true;
8447
8448 return false;
8449 }
8450
8451 /* Return 1 if a function argument of type TYPE and mode MODE
8452 is to be passed by reference. The ABI specifies that only
8453 structures of size 1, 2, 4, or 8 bytes are passed by value,
8454 all other structures (and complex numbers) are passed by
8455 reference. */
8456
8457 static bool
8458 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8459 enum machine_mode mode, const_tree type,
8460 bool named ATTRIBUTE_UNUSED)
8461 {
8462 int size = s390_function_arg_size (mode, type);
8463 if (size > 8)
8464 return true;
8465
8466 if (type)
8467 {
8468 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8469 return 1;
8470
8471 if (TREE_CODE (type) == COMPLEX_TYPE
8472 || TREE_CODE (type) == VECTOR_TYPE)
8473 return 1;
8474 }
8475
8476 return 0;
8477 }
8478
8479 /* Update the data in CUM to advance over an argument of mode MODE and
8480 data type TYPE. (TYPE is null for libcalls where that information
8481 may not be available.). The boolean NAMED specifies whether the
8482 argument is a named argument (as opposed to an unnamed argument
8483 matching an ellipsis). */
8484
8485 static void
8486 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8487 const_tree type, bool named ATTRIBUTE_UNUSED)
8488 {
8489 if (s390_function_arg_float (mode, type))
8490 {
8491 cum->fprs += 1;
8492 }
8493 else if (s390_function_arg_integer (mode, type))
8494 {
8495 int size = s390_function_arg_size (mode, type);
8496 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8497 }
8498 else
8499 gcc_unreachable ();
8500 }
8501
8502 /* Define where to put the arguments to a function.
8503 Value is zero to push the argument on the stack,
8504 or a hard register in which to store the argument.
8505
8506 MODE is the argument's machine mode.
8507 TYPE is the data type of the argument (as a tree).
8508 This is null for libcalls where that information may
8509 not be available.
8510 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8511 the preceding args and about the function being called.
8512 NAMED is nonzero if this argument is a named parameter
8513 (otherwise it is an extra parameter matching an ellipsis).
8514
8515 On S/390, we use general purpose registers 2 through 6 to
8516 pass integer, pointer, and certain structure arguments, and
8517 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8518 to pass floating point arguments. All remaining arguments
8519 are pushed to the stack. */
8520
8521 static rtx
8522 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8523 const_tree type, bool named ATTRIBUTE_UNUSED)
8524 {
8525 if (s390_function_arg_float (mode, type))
8526 {
8527 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8528 return 0;
8529 else
8530 return gen_rtx_REG (mode, cum->fprs + 16);
8531 }
8532 else if (s390_function_arg_integer (mode, type))
8533 {
8534 int size = s390_function_arg_size (mode, type);
8535 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8536
8537 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8538 return 0;
8539 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8540 return gen_rtx_REG (mode, cum->gprs + 2);
8541 else if (n_gprs == 2)
8542 {
8543 rtvec p = rtvec_alloc (2);
8544
8545 RTVEC_ELT (p, 0)
8546 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8547 const0_rtx);
8548 RTVEC_ELT (p, 1)
8549 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8550 GEN_INT (4));
8551
8552 return gen_rtx_PARALLEL (mode, p);
8553 }
8554 }
8555
8556 /* After the real arguments, expand_call calls us once again
8557 with a void_type_node type. Whatever we return here is
8558 passed as operand 2 to the call expanders.
8559
8560 We don't need this feature ... */
8561 else if (type == void_type_node)
8562 return const0_rtx;
8563
8564 gcc_unreachable ();
8565 }
8566
8567 /* Return true if return values of type TYPE should be returned
8568 in a memory buffer whose address is passed by the caller as
8569 hidden first argument. */
8570
8571 static bool
8572 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8573 {
8574 /* We accept small integral (and similar) types. */
8575 if (INTEGRAL_TYPE_P (type)
8576 || POINTER_TYPE_P (type)
8577 || TREE_CODE (type) == OFFSET_TYPE
8578 || TREE_CODE (type) == REAL_TYPE)
8579 return int_size_in_bytes (type) > 8;
8580
8581 /* Aggregates and similar constructs are always returned
8582 in memory. */
8583 if (AGGREGATE_TYPE_P (type)
8584 || TREE_CODE (type) == COMPLEX_TYPE
8585 || TREE_CODE (type) == VECTOR_TYPE)
8586 return true;
8587
8588 /* ??? We get called on all sorts of random stuff from
8589 aggregate_value_p. We can't abort, but it's not clear
8590 what's safe to return. Pretend it's a struct I guess. */
8591 return true;
8592 }
8593
8594 /* Function arguments and return values are promoted to word size. */
8595
8596 static enum machine_mode
8597 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8598 int *punsignedp,
8599 const_tree fntype ATTRIBUTE_UNUSED,
8600 int for_return ATTRIBUTE_UNUSED)
8601 {
8602 if (INTEGRAL_MODE_P (mode)
8603 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8604 {
8605 if (POINTER_TYPE_P (type))
8606 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8607 return Pmode;
8608 }
8609
8610 return mode;
8611 }
8612
8613 /* Define where to return a (scalar) value of type TYPE.
8614 If TYPE is null, define where to return a (scalar)
8615 value of mode MODE from a libcall. */
8616
8617 rtx
8618 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8619 {
8620 if (type)
8621 {
8622 int unsignedp = TYPE_UNSIGNED (type);
8623 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8624 }
8625
8626 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8627 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8628
8629 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8630 return gen_rtx_REG (mode, 16);
8631 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8632 || UNITS_PER_LONG == UNITS_PER_WORD)
8633 return gen_rtx_REG (mode, 2);
8634 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8635 {
8636 rtvec p = rtvec_alloc (2);
8637
8638 RTVEC_ELT (p, 0)
8639 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8640 RTVEC_ELT (p, 1)
8641 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8642
8643 return gen_rtx_PARALLEL (mode, p);
8644 }
8645
8646 gcc_unreachable ();
8647 }
8648
8649
8650 /* Create and return the va_list datatype.
8651
8652 On S/390, va_list is an array type equivalent to
8653
8654 typedef struct __va_list_tag
8655 {
8656 long __gpr;
8657 long __fpr;
8658 void *__overflow_arg_area;
8659 void *__reg_save_area;
8660 } va_list[1];
8661
8662 where __gpr and __fpr hold the number of general purpose
8663 or floating point arguments used up to now, respectively,
8664 __overflow_arg_area points to the stack location of the
8665 next argument passed on the stack, and __reg_save_area
8666 always points to the start of the register area in the
8667 call frame of the current function. The function prologue
8668 saves all registers used for argument passing into this
8669 area if the function uses variable arguments. */
8670
8671 static tree
8672 s390_build_builtin_va_list (void)
8673 {
8674 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8675
8676 record = lang_hooks.types.make_type (RECORD_TYPE);
8677
8678 type_decl =
8679 build_decl (BUILTINS_LOCATION,
8680 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8681
8682 f_gpr = build_decl (BUILTINS_LOCATION,
8683 FIELD_DECL, get_identifier ("__gpr"),
8684 long_integer_type_node);
8685 f_fpr = build_decl (BUILTINS_LOCATION,
8686 FIELD_DECL, get_identifier ("__fpr"),
8687 long_integer_type_node);
8688 f_ovf = build_decl (BUILTINS_LOCATION,
8689 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8690 ptr_type_node);
8691 f_sav = build_decl (BUILTINS_LOCATION,
8692 FIELD_DECL, get_identifier ("__reg_save_area"),
8693 ptr_type_node);
8694
8695 va_list_gpr_counter_field = f_gpr;
8696 va_list_fpr_counter_field = f_fpr;
8697
8698 DECL_FIELD_CONTEXT (f_gpr) = record;
8699 DECL_FIELD_CONTEXT (f_fpr) = record;
8700 DECL_FIELD_CONTEXT (f_ovf) = record;
8701 DECL_FIELD_CONTEXT (f_sav) = record;
8702
8703 TYPE_STUB_DECL (record) = type_decl;
8704 TYPE_NAME (record) = type_decl;
8705 TYPE_FIELDS (record) = f_gpr;
8706 DECL_CHAIN (f_gpr) = f_fpr;
8707 DECL_CHAIN (f_fpr) = f_ovf;
8708 DECL_CHAIN (f_ovf) = f_sav;
8709
8710 layout_type (record);
8711
8712 /* The correct type is an array type of one element. */
8713 return build_array_type (record, build_index_type (size_zero_node));
8714 }
8715
8716 /* Implement va_start by filling the va_list structure VALIST.
8717 STDARG_P is always true, and ignored.
8718 NEXTARG points to the first anonymous stack argument.
8719
8720 The following global variables are used to initialize
8721 the va_list structure:
8722
8723 crtl->args.info:
8724 holds number of gprs and fprs used for named arguments.
8725 crtl->args.arg_offset_rtx:
8726 holds the offset of the first anonymous stack argument
8727 (relative to the virtual arg pointer). */
8728
8729 static void
8730 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8731 {
8732 HOST_WIDE_INT n_gpr, n_fpr;
8733 int off;
8734 tree f_gpr, f_fpr, f_ovf, f_sav;
8735 tree gpr, fpr, ovf, sav, t;
8736
8737 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8738 f_fpr = DECL_CHAIN (f_gpr);
8739 f_ovf = DECL_CHAIN (f_fpr);
8740 f_sav = DECL_CHAIN (f_ovf);
8741
8742 valist = build_simple_mem_ref (valist);
8743 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8744 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8745 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8746 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8747
8748 /* Count number of gp and fp argument registers used. */
8749
8750 n_gpr = crtl->args.info.gprs;
8751 n_fpr = crtl->args.info.fprs;
8752
8753 if (cfun->va_list_gpr_size)
8754 {
8755 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8756 build_int_cst (NULL_TREE, n_gpr));
8757 TREE_SIDE_EFFECTS (t) = 1;
8758 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8759 }
8760
8761 if (cfun->va_list_fpr_size)
8762 {
8763 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8764 build_int_cst (NULL_TREE, n_fpr));
8765 TREE_SIDE_EFFECTS (t) = 1;
8766 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8767 }
8768
8769 /* Find the overflow area. */
8770 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8771 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8772 {
8773 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8774
8775 off = INTVAL (crtl->args.arg_offset_rtx);
8776 off = off < 0 ? 0 : off;
8777 if (TARGET_DEBUG_ARG)
8778 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8779 (int)n_gpr, (int)n_fpr, off);
8780
8781 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8782
8783 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8784 TREE_SIDE_EFFECTS (t) = 1;
8785 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8786 }
8787
8788 /* Find the register save area. */
8789 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8790 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8791 {
8792 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8793 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8794 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8795
8796 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8797 TREE_SIDE_EFFECTS (t) = 1;
8798 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8799 }
8800 }
8801
8802 /* Implement va_arg by updating the va_list structure
8803 VALIST as required to retrieve an argument of type
8804 TYPE, and returning that argument.
8805
8806 Generates code equivalent to:
8807
8808 if (integral value) {
8809 if (size <= 4 && args.gpr < 5 ||
8810 size > 4 && args.gpr < 4 )
8811 ret = args.reg_save_area[args.gpr+8]
8812 else
8813 ret = *args.overflow_arg_area++;
8814 } else if (float value) {
8815 if (args.fgpr < 2)
8816 ret = args.reg_save_area[args.fpr+64]
8817 else
8818 ret = *args.overflow_arg_area++;
8819 } else if (aggregate value) {
8820 if (args.gpr < 5)
8821 ret = *args.reg_save_area[args.gpr]
8822 else
8823 ret = **args.overflow_arg_area++;
8824 } */
8825
8826 static tree
8827 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8828 gimple_seq *post_p ATTRIBUTE_UNUSED)
8829 {
8830 tree f_gpr, f_fpr, f_ovf, f_sav;
8831 tree gpr, fpr, ovf, sav, reg, t, u;
8832 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8833 tree lab_false, lab_over, addr;
8834
8835 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8836 f_fpr = DECL_CHAIN (f_gpr);
8837 f_ovf = DECL_CHAIN (f_fpr);
8838 f_sav = DECL_CHAIN (f_ovf);
8839
8840 valist = build_va_arg_indirect_ref (valist);
8841 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8842 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8843 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8844
8845 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8846 both appear on a lhs. */
8847 valist = unshare_expr (valist);
8848 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8849
8850 size = int_size_in_bytes (type);
8851
8852 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8853 {
8854 if (TARGET_DEBUG_ARG)
8855 {
8856 fprintf (stderr, "va_arg: aggregate type");
8857 debug_tree (type);
8858 }
8859
8860 /* Aggregates are passed by reference. */
8861 indirect_p = 1;
8862 reg = gpr;
8863 n_reg = 1;
8864
8865 /* kernel stack layout on 31 bit: It is assumed here that no padding
8866 will be added by s390_frame_info because for va_args always an even
8867 number of gprs has to be saved r15-r2 = 14 regs. */
8868 sav_ofs = 2 * UNITS_PER_LONG;
8869 sav_scale = UNITS_PER_LONG;
8870 size = UNITS_PER_LONG;
8871 max_reg = GP_ARG_NUM_REG - n_reg;
8872 }
8873 else if (s390_function_arg_float (TYPE_MODE (type), type))
8874 {
8875 if (TARGET_DEBUG_ARG)
8876 {
8877 fprintf (stderr, "va_arg: float type");
8878 debug_tree (type);
8879 }
8880
8881 /* FP args go in FP registers, if present. */
8882 indirect_p = 0;
8883 reg = fpr;
8884 n_reg = 1;
8885 sav_ofs = 16 * UNITS_PER_LONG;
8886 sav_scale = 8;
8887 max_reg = FP_ARG_NUM_REG - n_reg;
8888 }
8889 else
8890 {
8891 if (TARGET_DEBUG_ARG)
8892 {
8893 fprintf (stderr, "va_arg: other type");
8894 debug_tree (type);
8895 }
8896
8897 /* Otherwise into GP registers. */
8898 indirect_p = 0;
8899 reg = gpr;
8900 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8901
8902 /* kernel stack layout on 31 bit: It is assumed here that no padding
8903 will be added by s390_frame_info because for va_args always an even
8904 number of gprs has to be saved r15-r2 = 14 regs. */
8905 sav_ofs = 2 * UNITS_PER_LONG;
8906
8907 if (size < UNITS_PER_LONG)
8908 sav_ofs += UNITS_PER_LONG - size;
8909
8910 sav_scale = UNITS_PER_LONG;
8911 max_reg = GP_ARG_NUM_REG - n_reg;
8912 }
8913
8914 /* Pull the value out of the saved registers ... */
8915
8916 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8917 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8918 addr = create_tmp_var (ptr_type_node, "addr");
8919
8920 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8921 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8922 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8923 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8924 gimplify_and_add (t, pre_p);
8925
8926 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8927 size_int (sav_ofs));
8928 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8929 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8930 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8931
8932 gimplify_assign (addr, t, pre_p);
8933
8934 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8935
8936 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8937
8938
8939 /* ... Otherwise out of the overflow area. */
8940
8941 t = ovf;
8942 if (size < UNITS_PER_LONG)
8943 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8944 size_int (UNITS_PER_LONG - size));
8945
8946 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8947
8948 gimplify_assign (addr, t, pre_p);
8949
8950 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8951 size_int (size));
8952 gimplify_assign (ovf, t, pre_p);
8953
8954 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8955
8956
8957 /* Increment register save count. */
8958
8959 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8960 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8961 gimplify_and_add (u, pre_p);
8962
8963 if (indirect_p)
8964 {
8965 t = build_pointer_type_for_mode (build_pointer_type (type),
8966 ptr_mode, true);
8967 addr = fold_convert (t, addr);
8968 addr = build_va_arg_indirect_ref (addr);
8969 }
8970 else
8971 {
8972 t = build_pointer_type_for_mode (type, ptr_mode, true);
8973 addr = fold_convert (t, addr);
8974 }
8975
8976 return build_va_arg_indirect_ref (addr);
8977 }
8978
8979
8980 /* Builtins. */
8981
8982 enum s390_builtin
8983 {
8984 S390_BUILTIN_THREAD_POINTER,
8985 S390_BUILTIN_SET_THREAD_POINTER,
8986
8987 S390_BUILTIN_max
8988 };
8989
8990 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8991 CODE_FOR_get_tp_64,
8992 CODE_FOR_set_tp_64
8993 };
8994
8995 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8996 CODE_FOR_get_tp_31,
8997 CODE_FOR_set_tp_31
8998 };
8999
9000 static void
9001 s390_init_builtins (void)
9002 {
9003 tree ftype;
9004
9005 ftype = build_function_type (ptr_type_node, void_list_node);
9006 add_builtin_function ("__builtin_thread_pointer", ftype,
9007 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9008 NULL, NULL_TREE);
9009
9010 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9011 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9012 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9013 NULL, NULL_TREE);
9014 }
9015
9016 /* Expand an expression EXP that calls a built-in function,
9017 with result going to TARGET if that's convenient
9018 (and in mode MODE if that's convenient).
9019 SUBTARGET may be used as the target for computing one of EXP's operands.
9020 IGNORE is nonzero if the value is to be ignored. */
9021
9022 static rtx
9023 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9024 enum machine_mode mode ATTRIBUTE_UNUSED,
9025 int ignore ATTRIBUTE_UNUSED)
9026 {
9027 #define MAX_ARGS 2
9028
9029 enum insn_code const *code_for_builtin =
9030 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9031
9032 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9033 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9034 enum insn_code icode;
9035 rtx op[MAX_ARGS], pat;
9036 int arity;
9037 bool nonvoid;
9038 tree arg;
9039 call_expr_arg_iterator iter;
9040
9041 if (fcode >= S390_BUILTIN_max)
9042 internal_error ("bad builtin fcode");
9043 icode = code_for_builtin[fcode];
9044 if (icode == 0)
9045 internal_error ("bad builtin fcode");
9046
9047 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9048
9049 arity = 0;
9050 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9051 {
9052 const struct insn_operand_data *insn_op;
9053
9054 if (arg == error_mark_node)
9055 return NULL_RTX;
9056 if (arity > MAX_ARGS)
9057 return NULL_RTX;
9058
9059 insn_op = &insn_data[icode].operand[arity + nonvoid];
9060
9061 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9062
9063 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9064 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9065 arity++;
9066 }
9067
9068 if (nonvoid)
9069 {
9070 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9071 if (!target
9072 || GET_MODE (target) != tmode
9073 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9074 target = gen_reg_rtx (tmode);
9075 }
9076
9077 switch (arity)
9078 {
9079 case 0:
9080 pat = GEN_FCN (icode) (target);
9081 break;
9082 case 1:
9083 if (nonvoid)
9084 pat = GEN_FCN (icode) (target, op[0]);
9085 else
9086 pat = GEN_FCN (icode) (op[0]);
9087 break;
9088 case 2:
9089 pat = GEN_FCN (icode) (target, op[0], op[1]);
9090 break;
9091 default:
9092 gcc_unreachable ();
9093 }
9094 if (!pat)
9095 return NULL_RTX;
9096 emit_insn (pat);
9097
9098 if (nonvoid)
9099 return target;
9100 else
9101 return const0_rtx;
9102 }
9103
9104
9105 /* Output assembly code for the trampoline template to
9106 stdio stream FILE.
9107
9108 On S/390, we use gpr 1 internally in the trampoline code;
9109 gpr 0 is used to hold the static chain. */
9110
9111 static void
9112 s390_asm_trampoline_template (FILE *file)
9113 {
9114 rtx op[2];
9115 op[0] = gen_rtx_REG (Pmode, 0);
9116 op[1] = gen_rtx_REG (Pmode, 1);
9117
9118 if (TARGET_64BIT)
9119 {
9120 output_asm_insn ("basr\t%1,0", op);
9121 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9122 output_asm_insn ("br\t%1", op);
9123 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9124 }
9125 else
9126 {
9127 output_asm_insn ("basr\t%1,0", op);
9128 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9129 output_asm_insn ("br\t%1", op);
9130 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9131 }
9132 }
9133
9134 /* Emit RTL insns to initialize the variable parts of a trampoline.
9135 FNADDR is an RTX for the address of the function's pure code.
9136 CXT is an RTX for the static chain value for the function. */
9137
9138 static void
9139 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9140 {
9141 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9142 rtx mem;
9143
9144 emit_block_move (m_tramp, assemble_trampoline_template (),
9145 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9146
9147 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9148 emit_move_insn (mem, cxt);
9149 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9150 emit_move_insn (mem, fnaddr);
9151 }
9152
9153 /* Output assembler code to FILE to increment profiler label # LABELNO
9154 for profiling a function entry. */
9155
9156 void
9157 s390_function_profiler (FILE *file, int labelno)
9158 {
9159 rtx op[7];
9160
9161 char label[128];
9162 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9163
9164 fprintf (file, "# function profiler \n");
9165
9166 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9167 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9168 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9169
9170 op[2] = gen_rtx_REG (Pmode, 1);
9171 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9172 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9173
9174 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9175 if (flag_pic)
9176 {
9177 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9178 op[4] = gen_rtx_CONST (Pmode, op[4]);
9179 }
9180
9181 if (TARGET_64BIT)
9182 {
9183 output_asm_insn ("stg\t%0,%1", op);
9184 output_asm_insn ("larl\t%2,%3", op);
9185 output_asm_insn ("brasl\t%0,%4", op);
9186 output_asm_insn ("lg\t%0,%1", op);
9187 }
9188 else if (!flag_pic)
9189 {
9190 op[6] = gen_label_rtx ();
9191
9192 output_asm_insn ("st\t%0,%1", op);
9193 output_asm_insn ("bras\t%2,%l6", op);
9194 output_asm_insn (".long\t%4", op);
9195 output_asm_insn (".long\t%3", op);
9196 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9197 output_asm_insn ("l\t%0,0(%2)", op);
9198 output_asm_insn ("l\t%2,4(%2)", op);
9199 output_asm_insn ("basr\t%0,%0", op);
9200 output_asm_insn ("l\t%0,%1", op);
9201 }
9202 else
9203 {
9204 op[5] = gen_label_rtx ();
9205 op[6] = gen_label_rtx ();
9206
9207 output_asm_insn ("st\t%0,%1", op);
9208 output_asm_insn ("bras\t%2,%l6", op);
9209 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9210 output_asm_insn (".long\t%4-%l5", op);
9211 output_asm_insn (".long\t%3-%l5", op);
9212 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9213 output_asm_insn ("lr\t%0,%2", op);
9214 output_asm_insn ("a\t%0,0(%2)", op);
9215 output_asm_insn ("a\t%2,4(%2)", op);
9216 output_asm_insn ("basr\t%0,%0", op);
9217 output_asm_insn ("l\t%0,%1", op);
9218 }
9219 }
9220
9221 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9222 into its SYMBOL_REF_FLAGS. */
9223
9224 static void
9225 s390_encode_section_info (tree decl, rtx rtl, int first)
9226 {
9227 default_encode_section_info (decl, rtl, first);
9228
9229 if (TREE_CODE (decl) == VAR_DECL)
9230 {
9231 /* If a variable has a forced alignment to < 2 bytes, mark it
9232 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9233 operand. */
9234 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9235 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9236 if (!DECL_SIZE (decl)
9237 || !DECL_ALIGN (decl)
9238 || !host_integerp (DECL_SIZE (decl), 0)
9239 || (DECL_ALIGN (decl) <= 64
9240 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9241 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9242 }
9243
9244 /* Literal pool references don't have a decl so they are handled
9245 differently here. We rely on the information in the MEM_ALIGN
9246 entry to decide upon natural alignment. */
9247 if (MEM_P (rtl)
9248 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9249 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9250 && (MEM_ALIGN (rtl) == 0
9251 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9252 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9253 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9254 }
9255
9256 /* Output thunk to FILE that implements a C++ virtual function call (with
9257 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9258 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9259 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9260 relative to the resulting this pointer. */
9261
9262 static void
9263 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9264 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9265 tree function)
9266 {
9267 rtx op[10];
9268 int nonlocal = 0;
9269
9270 /* Make sure unwind info is emitted for the thunk if needed. */
9271 final_start_function (emit_barrier (), file, 1);
9272
9273 /* Operand 0 is the target function. */
9274 op[0] = XEXP (DECL_RTL (function), 0);
9275 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9276 {
9277 nonlocal = 1;
9278 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9279 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9280 op[0] = gen_rtx_CONST (Pmode, op[0]);
9281 }
9282
9283 /* Operand 1 is the 'this' pointer. */
9284 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9285 op[1] = gen_rtx_REG (Pmode, 3);
9286 else
9287 op[1] = gen_rtx_REG (Pmode, 2);
9288
9289 /* Operand 2 is the delta. */
9290 op[2] = GEN_INT (delta);
9291
9292 /* Operand 3 is the vcall_offset. */
9293 op[3] = GEN_INT (vcall_offset);
9294
9295 /* Operand 4 is the temporary register. */
9296 op[4] = gen_rtx_REG (Pmode, 1);
9297
9298 /* Operands 5 to 8 can be used as labels. */
9299 op[5] = NULL_RTX;
9300 op[6] = NULL_RTX;
9301 op[7] = NULL_RTX;
9302 op[8] = NULL_RTX;
9303
9304 /* Operand 9 can be used for temporary register. */
9305 op[9] = NULL_RTX;
9306
9307 /* Generate code. */
9308 if (TARGET_64BIT)
9309 {
9310 /* Setup literal pool pointer if required. */
9311 if ((!DISP_IN_RANGE (delta)
9312 && !CONST_OK_FOR_K (delta)
9313 && !CONST_OK_FOR_Os (delta))
9314 || (!DISP_IN_RANGE (vcall_offset)
9315 && !CONST_OK_FOR_K (vcall_offset)
9316 && !CONST_OK_FOR_Os (vcall_offset)))
9317 {
9318 op[5] = gen_label_rtx ();
9319 output_asm_insn ("larl\t%4,%5", op);
9320 }
9321
9322 /* Add DELTA to this pointer. */
9323 if (delta)
9324 {
9325 if (CONST_OK_FOR_J (delta))
9326 output_asm_insn ("la\t%1,%2(%1)", op);
9327 else if (DISP_IN_RANGE (delta))
9328 output_asm_insn ("lay\t%1,%2(%1)", op);
9329 else if (CONST_OK_FOR_K (delta))
9330 output_asm_insn ("aghi\t%1,%2", op);
9331 else if (CONST_OK_FOR_Os (delta))
9332 output_asm_insn ("agfi\t%1,%2", op);
9333 else
9334 {
9335 op[6] = gen_label_rtx ();
9336 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9337 }
9338 }
9339
9340 /* Perform vcall adjustment. */
9341 if (vcall_offset)
9342 {
9343 if (DISP_IN_RANGE (vcall_offset))
9344 {
9345 output_asm_insn ("lg\t%4,0(%1)", op);
9346 output_asm_insn ("ag\t%1,%3(%4)", op);
9347 }
9348 else if (CONST_OK_FOR_K (vcall_offset))
9349 {
9350 output_asm_insn ("lghi\t%4,%3", op);
9351 output_asm_insn ("ag\t%4,0(%1)", op);
9352 output_asm_insn ("ag\t%1,0(%4)", op);
9353 }
9354 else if (CONST_OK_FOR_Os (vcall_offset))
9355 {
9356 output_asm_insn ("lgfi\t%4,%3", op);
9357 output_asm_insn ("ag\t%4,0(%1)", op);
9358 output_asm_insn ("ag\t%1,0(%4)", op);
9359 }
9360 else
9361 {
9362 op[7] = gen_label_rtx ();
9363 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9364 output_asm_insn ("ag\t%4,0(%1)", op);
9365 output_asm_insn ("ag\t%1,0(%4)", op);
9366 }
9367 }
9368
9369 /* Jump to target. */
9370 output_asm_insn ("jg\t%0", op);
9371
9372 /* Output literal pool if required. */
9373 if (op[5])
9374 {
9375 output_asm_insn (".align\t4", op);
9376 targetm.asm_out.internal_label (file, "L",
9377 CODE_LABEL_NUMBER (op[5]));
9378 }
9379 if (op[6])
9380 {
9381 targetm.asm_out.internal_label (file, "L",
9382 CODE_LABEL_NUMBER (op[6]));
9383 output_asm_insn (".long\t%2", op);
9384 }
9385 if (op[7])
9386 {
9387 targetm.asm_out.internal_label (file, "L",
9388 CODE_LABEL_NUMBER (op[7]));
9389 output_asm_insn (".long\t%3", op);
9390 }
9391 }
9392 else
9393 {
9394 /* Setup base pointer if required. */
9395 if (!vcall_offset
9396 || (!DISP_IN_RANGE (delta)
9397 && !CONST_OK_FOR_K (delta)
9398 && !CONST_OK_FOR_Os (delta))
9399 || (!DISP_IN_RANGE (delta)
9400 && !CONST_OK_FOR_K (vcall_offset)
9401 && !CONST_OK_FOR_Os (vcall_offset)))
9402 {
9403 op[5] = gen_label_rtx ();
9404 output_asm_insn ("basr\t%4,0", op);
9405 targetm.asm_out.internal_label (file, "L",
9406 CODE_LABEL_NUMBER (op[5]));
9407 }
9408
9409 /* Add DELTA to this pointer. */
9410 if (delta)
9411 {
9412 if (CONST_OK_FOR_J (delta))
9413 output_asm_insn ("la\t%1,%2(%1)", op);
9414 else if (DISP_IN_RANGE (delta))
9415 output_asm_insn ("lay\t%1,%2(%1)", op);
9416 else if (CONST_OK_FOR_K (delta))
9417 output_asm_insn ("ahi\t%1,%2", op);
9418 else if (CONST_OK_FOR_Os (delta))
9419 output_asm_insn ("afi\t%1,%2", op);
9420 else
9421 {
9422 op[6] = gen_label_rtx ();
9423 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9424 }
9425 }
9426
9427 /* Perform vcall adjustment. */
9428 if (vcall_offset)
9429 {
9430 if (CONST_OK_FOR_J (vcall_offset))
9431 {
9432 output_asm_insn ("l\t%4,0(%1)", op);
9433 output_asm_insn ("a\t%1,%3(%4)", op);
9434 }
9435 else if (DISP_IN_RANGE (vcall_offset))
9436 {
9437 output_asm_insn ("l\t%4,0(%1)", op);
9438 output_asm_insn ("ay\t%1,%3(%4)", op);
9439 }
9440 else if (CONST_OK_FOR_K (vcall_offset))
9441 {
9442 output_asm_insn ("lhi\t%4,%3", op);
9443 output_asm_insn ("a\t%4,0(%1)", op);
9444 output_asm_insn ("a\t%1,0(%4)", op);
9445 }
9446 else if (CONST_OK_FOR_Os (vcall_offset))
9447 {
9448 output_asm_insn ("iilf\t%4,%3", op);
9449 output_asm_insn ("a\t%4,0(%1)", op);
9450 output_asm_insn ("a\t%1,0(%4)", op);
9451 }
9452 else
9453 {
9454 op[7] = gen_label_rtx ();
9455 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9456 output_asm_insn ("a\t%4,0(%1)", op);
9457 output_asm_insn ("a\t%1,0(%4)", op);
9458 }
9459
9460 /* We had to clobber the base pointer register.
9461 Re-setup the base pointer (with a different base). */
9462 op[5] = gen_label_rtx ();
9463 output_asm_insn ("basr\t%4,0", op);
9464 targetm.asm_out.internal_label (file, "L",
9465 CODE_LABEL_NUMBER (op[5]));
9466 }
9467
9468 /* Jump to target. */
9469 op[8] = gen_label_rtx ();
9470
9471 if (!flag_pic)
9472 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9473 else if (!nonlocal)
9474 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9475 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9476 else if (flag_pic == 1)
9477 {
9478 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9479 output_asm_insn ("l\t%4,%0(%4)", op);
9480 }
9481 else if (flag_pic == 2)
9482 {
9483 op[9] = gen_rtx_REG (Pmode, 0);
9484 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9485 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9486 output_asm_insn ("ar\t%4,%9", op);
9487 output_asm_insn ("l\t%4,0(%4)", op);
9488 }
9489
9490 output_asm_insn ("br\t%4", op);
9491
9492 /* Output literal pool. */
9493 output_asm_insn (".align\t4", op);
9494
9495 if (nonlocal && flag_pic == 2)
9496 output_asm_insn (".long\t%0", op);
9497 if (nonlocal)
9498 {
9499 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9500 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9501 }
9502
9503 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9504 if (!flag_pic)
9505 output_asm_insn (".long\t%0", op);
9506 else
9507 output_asm_insn (".long\t%0-%5", op);
9508
9509 if (op[6])
9510 {
9511 targetm.asm_out.internal_label (file, "L",
9512 CODE_LABEL_NUMBER (op[6]));
9513 output_asm_insn (".long\t%2", op);
9514 }
9515 if (op[7])
9516 {
9517 targetm.asm_out.internal_label (file, "L",
9518 CODE_LABEL_NUMBER (op[7]));
9519 output_asm_insn (".long\t%3", op);
9520 }
9521 }
9522 final_end_function ();
9523 }
9524
9525 static bool
9526 s390_valid_pointer_mode (enum machine_mode mode)
9527 {
9528 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9529 }
9530
9531 /* Checks whether the given CALL_EXPR would use a caller
9532 saved register. This is used to decide whether sibling call
9533 optimization could be performed on the respective function
9534 call. */
9535
9536 static bool
9537 s390_call_saved_register_used (tree call_expr)
9538 {
9539 CUMULATIVE_ARGS cum;
9540 tree parameter;
9541 enum machine_mode mode;
9542 tree type;
9543 rtx parm_rtx;
9544 int reg, i;
9545
9546 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9547
9548 for (i = 0; i < call_expr_nargs (call_expr); i++)
9549 {
9550 parameter = CALL_EXPR_ARG (call_expr, i);
9551 gcc_assert (parameter);
9552
9553 /* For an undeclared variable passed as parameter we will get
9554 an ERROR_MARK node here. */
9555 if (TREE_CODE (parameter) == ERROR_MARK)
9556 return true;
9557
9558 type = TREE_TYPE (parameter);
9559 gcc_assert (type);
9560
9561 mode = TYPE_MODE (type);
9562 gcc_assert (mode);
9563
9564 if (pass_by_reference (&cum, mode, type, true))
9565 {
9566 mode = Pmode;
9567 type = build_pointer_type (type);
9568 }
9569
9570 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9571
9572 s390_function_arg_advance (&cum, mode, type, 0);
9573
9574 if (!parm_rtx)
9575 continue;
9576
9577 if (REG_P (parm_rtx))
9578 {
9579 for (reg = 0;
9580 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9581 reg++)
9582 if (!call_used_regs[reg + REGNO (parm_rtx)])
9583 return true;
9584 }
9585
9586 if (GET_CODE (parm_rtx) == PARALLEL)
9587 {
9588 int i;
9589
9590 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9591 {
9592 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9593
9594 gcc_assert (REG_P (r));
9595
9596 for (reg = 0;
9597 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9598 reg++)
9599 if (!call_used_regs[reg + REGNO (r)])
9600 return true;
9601 }
9602 }
9603
9604 }
9605 return false;
9606 }
9607
9608 /* Return true if the given call expression can be
9609 turned into a sibling call.
9610 DECL holds the declaration of the function to be called whereas
9611 EXP is the call expression itself. */
9612
9613 static bool
9614 s390_function_ok_for_sibcall (tree decl, tree exp)
9615 {
9616 /* The TPF epilogue uses register 1. */
9617 if (TARGET_TPF_PROFILING)
9618 return false;
9619
9620 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9621 which would have to be restored before the sibcall. */
9622 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9623 return false;
9624
9625 /* Register 6 on s390 is available as an argument register but unfortunately
9626 "caller saved". This makes functions needing this register for arguments
9627 not suitable for sibcalls. */
9628 return !s390_call_saved_register_used (exp);
9629 }
9630
9631 /* Return the fixed registers used for condition codes. */
9632
9633 static bool
9634 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9635 {
9636 *p1 = CC_REGNUM;
9637 *p2 = INVALID_REGNUM;
9638
9639 return true;
9640 }
9641
9642 /* This function is used by the call expanders of the machine description.
9643 It emits the call insn itself together with the necessary operations
9644 to adjust the target address and returns the emitted insn.
9645 ADDR_LOCATION is the target address rtx
9646 TLS_CALL the location of the thread-local symbol
9647 RESULT_REG the register where the result of the call should be stored
9648 RETADDR_REG the register where the return address should be stored
9649 If this parameter is NULL_RTX the call is considered
9650 to be a sibling call. */
9651
9652 rtx
9653 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9654 rtx retaddr_reg)
9655 {
9656 bool plt_call = false;
9657 rtx insn;
9658 rtx call;
9659 rtx clobber;
9660 rtvec vec;
9661
9662 /* Direct function calls need special treatment. */
9663 if (GET_CODE (addr_location) == SYMBOL_REF)
9664 {
9665 /* When calling a global routine in PIC mode, we must
9666 replace the symbol itself with the PLT stub. */
9667 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9668 {
9669 if (retaddr_reg != NULL_RTX)
9670 {
9671 addr_location = gen_rtx_UNSPEC (Pmode,
9672 gen_rtvec (1, addr_location),
9673 UNSPEC_PLT);
9674 addr_location = gen_rtx_CONST (Pmode, addr_location);
9675 plt_call = true;
9676 }
9677 else
9678 /* For -fpic code the PLT entries might use r12 which is
9679 call-saved. Therefore we cannot do a sibcall when
9680 calling directly using a symbol ref. When reaching
9681 this point we decided (in s390_function_ok_for_sibcall)
9682 to do a sibcall for a function pointer but one of the
9683 optimizers was able to get rid of the function pointer
9684 by propagating the symbol ref into the call. This
9685 optimization is illegal for S/390 so we turn the direct
9686 call into a indirect call again. */
9687 addr_location = force_reg (Pmode, addr_location);
9688 }
9689
9690 /* Unless we can use the bras(l) insn, force the
9691 routine address into a register. */
9692 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9693 {
9694 if (flag_pic)
9695 addr_location = legitimize_pic_address (addr_location, 0);
9696 else
9697 addr_location = force_reg (Pmode, addr_location);
9698 }
9699 }
9700
9701 /* If it is already an indirect call or the code above moved the
9702 SYMBOL_REF to somewhere else make sure the address can be found in
9703 register 1. */
9704 if (retaddr_reg == NULL_RTX
9705 && GET_CODE (addr_location) != SYMBOL_REF
9706 && !plt_call)
9707 {
9708 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9709 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9710 }
9711
9712 addr_location = gen_rtx_MEM (QImode, addr_location);
9713 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9714
9715 if (result_reg != NULL_RTX)
9716 call = gen_rtx_SET (VOIDmode, result_reg, call);
9717
9718 if (retaddr_reg != NULL_RTX)
9719 {
9720 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9721
9722 if (tls_call != NULL_RTX)
9723 vec = gen_rtvec (3, call, clobber,
9724 gen_rtx_USE (VOIDmode, tls_call));
9725 else
9726 vec = gen_rtvec (2, call, clobber);
9727
9728 call = gen_rtx_PARALLEL (VOIDmode, vec);
9729 }
9730
9731 insn = emit_call_insn (call);
9732
9733 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9734 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9735 {
9736 /* s390_function_ok_for_sibcall should
9737 have denied sibcalls in this case. */
9738 gcc_assert (retaddr_reg != NULL_RTX);
9739
9740 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9741 }
9742 return insn;
9743 }
9744
9745 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9746
9747 static void
9748 s390_conditional_register_usage (void)
9749 {
9750 int i;
9751
9752 if (flag_pic)
9753 {
9754 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9755 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9756 }
9757 if (TARGET_CPU_ZARCH)
9758 {
9759 fixed_regs[BASE_REGNUM] = 0;
9760 call_used_regs[BASE_REGNUM] = 0;
9761 fixed_regs[RETURN_REGNUM] = 0;
9762 call_used_regs[RETURN_REGNUM] = 0;
9763 }
9764 if (TARGET_64BIT)
9765 {
9766 for (i = 24; i < 32; i++)
9767 call_used_regs[i] = call_really_used_regs[i] = 0;
9768 }
9769 else
9770 {
9771 for (i = 18; i < 20; i++)
9772 call_used_regs[i] = call_really_used_regs[i] = 0;
9773 }
9774
9775 if (TARGET_SOFT_FLOAT)
9776 {
9777 for (i = 16; i < 32; i++)
9778 call_used_regs[i] = fixed_regs[i] = 1;
9779 }
9780 }
9781
9782 /* Corresponding function to eh_return expander. */
9783
9784 static GTY(()) rtx s390_tpf_eh_return_symbol;
9785 void
9786 s390_emit_tpf_eh_return (rtx target)
9787 {
9788 rtx insn, reg;
9789
9790 if (!s390_tpf_eh_return_symbol)
9791 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9792
9793 reg = gen_rtx_REG (Pmode, 2);
9794
9795 emit_move_insn (reg, target);
9796 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9797 gen_rtx_REG (Pmode, RETURN_REGNUM));
9798 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9799
9800 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9801 }
9802
9803 /* Rework the prologue/epilogue to avoid saving/restoring
9804 registers unnecessarily. */
9805
9806 static void
9807 s390_optimize_prologue (void)
9808 {
9809 rtx insn, new_insn, next_insn;
9810
9811 /* Do a final recompute of the frame-related data. */
9812
9813 s390_update_frame_layout ();
9814
9815 /* If all special registers are in fact used, there's nothing we
9816 can do, so no point in walking the insn list. */
9817
9818 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9819 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9820 && (TARGET_CPU_ZARCH
9821 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9822 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9823 return;
9824
9825 /* Search for prologue/epilogue insns and replace them. */
9826
9827 for (insn = get_insns (); insn; insn = next_insn)
9828 {
9829 int first, last, off;
9830 rtx set, base, offset;
9831
9832 next_insn = NEXT_INSN (insn);
9833
9834 if (GET_CODE (insn) != INSN)
9835 continue;
9836
9837 if (GET_CODE (PATTERN (insn)) == PARALLEL
9838 && store_multiple_operation (PATTERN (insn), VOIDmode))
9839 {
9840 set = XVECEXP (PATTERN (insn), 0, 0);
9841 first = REGNO (SET_SRC (set));
9842 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9843 offset = const0_rtx;
9844 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9845 off = INTVAL (offset);
9846
9847 if (GET_CODE (base) != REG || off < 0)
9848 continue;
9849 if (cfun_frame_layout.first_save_gpr != -1
9850 && (cfun_frame_layout.first_save_gpr < first
9851 || cfun_frame_layout.last_save_gpr > last))
9852 continue;
9853 if (REGNO (base) != STACK_POINTER_REGNUM
9854 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9855 continue;
9856 if (first > BASE_REGNUM || last < BASE_REGNUM)
9857 continue;
9858
9859 if (cfun_frame_layout.first_save_gpr != -1)
9860 {
9861 new_insn = save_gprs (base,
9862 off + (cfun_frame_layout.first_save_gpr
9863 - first) * UNITS_PER_LONG,
9864 cfun_frame_layout.first_save_gpr,
9865 cfun_frame_layout.last_save_gpr);
9866 new_insn = emit_insn_before (new_insn, insn);
9867 INSN_ADDRESSES_NEW (new_insn, -1);
9868 }
9869
9870 remove_insn (insn);
9871 continue;
9872 }
9873
9874 if (cfun_frame_layout.first_save_gpr == -1
9875 && GET_CODE (PATTERN (insn)) == SET
9876 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9877 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9878 || (!TARGET_CPU_ZARCH
9879 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9880 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9881 {
9882 set = PATTERN (insn);
9883 first = REGNO (SET_SRC (set));
9884 offset = const0_rtx;
9885 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9886 off = INTVAL (offset);
9887
9888 if (GET_CODE (base) != REG || off < 0)
9889 continue;
9890 if (REGNO (base) != STACK_POINTER_REGNUM
9891 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9892 continue;
9893
9894 remove_insn (insn);
9895 continue;
9896 }
9897
9898 if (GET_CODE (PATTERN (insn)) == PARALLEL
9899 && load_multiple_operation (PATTERN (insn), VOIDmode))
9900 {
9901 set = XVECEXP (PATTERN (insn), 0, 0);
9902 first = REGNO (SET_DEST (set));
9903 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9904 offset = const0_rtx;
9905 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9906 off = INTVAL (offset);
9907
9908 if (GET_CODE (base) != REG || off < 0)
9909 continue;
9910 if (cfun_frame_layout.first_restore_gpr != -1
9911 && (cfun_frame_layout.first_restore_gpr < first
9912 || cfun_frame_layout.last_restore_gpr > last))
9913 continue;
9914 if (REGNO (base) != STACK_POINTER_REGNUM
9915 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9916 continue;
9917 if (first > BASE_REGNUM || last < BASE_REGNUM)
9918 continue;
9919
9920 if (cfun_frame_layout.first_restore_gpr != -1)
9921 {
9922 new_insn = restore_gprs (base,
9923 off + (cfun_frame_layout.first_restore_gpr
9924 - first) * UNITS_PER_LONG,
9925 cfun_frame_layout.first_restore_gpr,
9926 cfun_frame_layout.last_restore_gpr);
9927 new_insn = emit_insn_before (new_insn, insn);
9928 INSN_ADDRESSES_NEW (new_insn, -1);
9929 }
9930
9931 remove_insn (insn);
9932 continue;
9933 }
9934
9935 if (cfun_frame_layout.first_restore_gpr == -1
9936 && GET_CODE (PATTERN (insn)) == SET
9937 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9938 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9939 || (!TARGET_CPU_ZARCH
9940 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9941 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9942 {
9943 set = PATTERN (insn);
9944 first = REGNO (SET_DEST (set));
9945 offset = const0_rtx;
9946 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9947 off = INTVAL (offset);
9948
9949 if (GET_CODE (base) != REG || off < 0)
9950 continue;
9951 if (REGNO (base) != STACK_POINTER_REGNUM
9952 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9953 continue;
9954
9955 remove_insn (insn);
9956 continue;
9957 }
9958 }
9959 }
9960
9961 /* On z10 and later the dynamic branch prediction must see the
9962 backward jump within a certain windows. If not it falls back to
9963 the static prediction. This function rearranges the loop backward
9964 branch in a way which makes the static prediction always correct.
9965 The function returns true if it added an instruction. */
9966 static bool
9967 s390_fix_long_loop_prediction (rtx insn)
9968 {
9969 rtx set = single_set (insn);
9970 rtx code_label, label_ref, new_label;
9971 rtx uncond_jump;
9972 rtx cur_insn;
9973 rtx tmp;
9974 int distance;
9975
9976 /* This will exclude branch on count and branch on index patterns
9977 since these are correctly statically predicted. */
9978 if (!set
9979 || SET_DEST (set) != pc_rtx
9980 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9981 return false;
9982
9983 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9984 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9985
9986 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9987
9988 code_label = XEXP (label_ref, 0);
9989
9990 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9991 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9992 || (INSN_ADDRESSES (INSN_UID (insn))
9993 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
9994 return false;
9995
9996 for (distance = 0, cur_insn = PREV_INSN (insn);
9997 distance < PREDICT_DISTANCE - 6;
9998 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9999 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10000 return false;
10001
10002 new_label = gen_label_rtx ();
10003 uncond_jump = emit_jump_insn_after (
10004 gen_rtx_SET (VOIDmode, pc_rtx,
10005 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10006 insn);
10007 emit_label_after (new_label, uncond_jump);
10008
10009 tmp = XEXP (SET_SRC (set), 1);
10010 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10011 XEXP (SET_SRC (set), 2) = tmp;
10012 INSN_CODE (insn) = -1;
10013
10014 XEXP (label_ref, 0) = new_label;
10015 JUMP_LABEL (insn) = new_label;
10016 JUMP_LABEL (uncond_jump) = code_label;
10017
10018 return true;
10019 }
10020
10021 /* Returns 1 if INSN reads the value of REG for purposes not related
10022 to addressing of memory, and 0 otherwise. */
10023 static int
10024 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10025 {
10026 return reg_referenced_p (reg, PATTERN (insn))
10027 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10028 }
10029
10030 /* Starting from INSN find_cond_jump looks downwards in the insn
10031 stream for a single jump insn which is the last user of the
10032 condition code set in INSN. */
10033 static rtx
10034 find_cond_jump (rtx insn)
10035 {
10036 for (; insn; insn = NEXT_INSN (insn))
10037 {
10038 rtx ite, cc;
10039
10040 if (LABEL_P (insn))
10041 break;
10042
10043 if (!JUMP_P (insn))
10044 {
10045 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10046 break;
10047 continue;
10048 }
10049
10050 /* This will be triggered by a return. */
10051 if (GET_CODE (PATTERN (insn)) != SET)
10052 break;
10053
10054 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10055 ite = SET_SRC (PATTERN (insn));
10056
10057 if (GET_CODE (ite) != IF_THEN_ELSE)
10058 break;
10059
10060 cc = XEXP (XEXP (ite, 0), 0);
10061 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10062 break;
10063
10064 if (find_reg_note (insn, REG_DEAD, cc))
10065 return insn;
10066 break;
10067 }
10068
10069 return NULL_RTX;
10070 }
10071
10072 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10073 the semantics does not change. If NULL_RTX is passed as COND the
10074 function tries to find the conditional jump starting with INSN. */
10075 static void
10076 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10077 {
10078 rtx tmp = *op0;
10079
10080 if (cond == NULL_RTX)
10081 {
10082 rtx jump = find_cond_jump (NEXT_INSN (insn));
10083 jump = jump ? single_set (jump) : NULL_RTX;
10084
10085 if (jump == NULL_RTX)
10086 return;
10087
10088 cond = XEXP (XEXP (jump, 1), 0);
10089 }
10090
10091 *op0 = *op1;
10092 *op1 = tmp;
10093 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10094 }
10095
10096 /* On z10, instructions of the compare-and-branch family have the
10097 property to access the register occurring as second operand with
10098 its bits complemented. If such a compare is grouped with a second
10099 instruction that accesses the same register non-complemented, and
10100 if that register's value is delivered via a bypass, then the
10101 pipeline recycles, thereby causing significant performance decline.
10102 This function locates such situations and exchanges the two
10103 operands of the compare. The function return true whenever it
10104 added an insn. */
10105 static bool
10106 s390_z10_optimize_cmp (rtx insn)
10107 {
10108 rtx prev_insn, next_insn;
10109 bool insn_added_p = false;
10110 rtx cond, *op0, *op1;
10111
10112 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10113 {
10114 /* Handle compare and branch and branch on count
10115 instructions. */
10116 rtx pattern = single_set (insn);
10117
10118 if (!pattern
10119 || SET_DEST (pattern) != pc_rtx
10120 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10121 return false;
10122
10123 cond = XEXP (SET_SRC (pattern), 0);
10124 op0 = &XEXP (cond, 0);
10125 op1 = &XEXP (cond, 1);
10126 }
10127 else if (GET_CODE (PATTERN (insn)) == SET)
10128 {
10129 rtx src, dest;
10130
10131 /* Handle normal compare instructions. */
10132 src = SET_SRC (PATTERN (insn));
10133 dest = SET_DEST (PATTERN (insn));
10134
10135 if (!REG_P (dest)
10136 || !CC_REGNO_P (REGNO (dest))
10137 || GET_CODE (src) != COMPARE)
10138 return false;
10139
10140 /* s390_swap_cmp will try to find the conditional
10141 jump when passing NULL_RTX as condition. */
10142 cond = NULL_RTX;
10143 op0 = &XEXP (src, 0);
10144 op1 = &XEXP (src, 1);
10145 }
10146 else
10147 return false;
10148
10149 if (!REG_P (*op0) || !REG_P (*op1))
10150 return false;
10151
10152 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10153 return false;
10154
10155 /* Swap the COMPARE arguments and its mask if there is a
10156 conflicting access in the previous insn. */
10157 prev_insn = prev_active_insn (insn);
10158 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10159 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10160 s390_swap_cmp (cond, op0, op1, insn);
10161
10162 /* Check if there is a conflict with the next insn. If there
10163 was no conflict with the previous insn, then swap the
10164 COMPARE arguments and its mask. If we already swapped
10165 the operands, or if swapping them would cause a conflict
10166 with the previous insn, issue a NOP after the COMPARE in
10167 order to separate the two instuctions. */
10168 next_insn = next_active_insn (insn);
10169 if (next_insn != NULL_RTX && INSN_P (next_insn)
10170 && s390_non_addr_reg_read_p (*op1, next_insn))
10171 {
10172 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10173 && s390_non_addr_reg_read_p (*op0, prev_insn))
10174 {
10175 if (REGNO (*op1) == 0)
10176 emit_insn_after (gen_nop1 (), insn);
10177 else
10178 emit_insn_after (gen_nop (), insn);
10179 insn_added_p = true;
10180 }
10181 else
10182 s390_swap_cmp (cond, op0, op1, insn);
10183 }
10184 return insn_added_p;
10185 }
10186
10187 /* Perform machine-dependent processing. */
10188
10189 static void
10190 s390_reorg (void)
10191 {
10192 bool pool_overflow = false;
10193
10194 /* Make sure all splits have been performed; splits after
10195 machine_dependent_reorg might confuse insn length counts. */
10196 split_all_insns_noflow ();
10197
10198 /* Install the main literal pool and the associated base
10199 register load insns.
10200
10201 In addition, there are two problematic situations we need
10202 to correct:
10203
10204 - the literal pool might be > 4096 bytes in size, so that
10205 some of its elements cannot be directly accessed
10206
10207 - a branch target might be > 64K away from the branch, so that
10208 it is not possible to use a PC-relative instruction.
10209
10210 To fix those, we split the single literal pool into multiple
10211 pool chunks, reloading the pool base register at various
10212 points throughout the function to ensure it always points to
10213 the pool chunk the following code expects, and / or replace
10214 PC-relative branches by absolute branches.
10215
10216 However, the two problems are interdependent: splitting the
10217 literal pool can move a branch further away from its target,
10218 causing the 64K limit to overflow, and on the other hand,
10219 replacing a PC-relative branch by an absolute branch means
10220 we need to put the branch target address into the literal
10221 pool, possibly causing it to overflow.
10222
10223 So, we loop trying to fix up both problems until we manage
10224 to satisfy both conditions at the same time. Note that the
10225 loop is guaranteed to terminate as every pass of the loop
10226 strictly decreases the total number of PC-relative branches
10227 in the function. (This is not completely true as there
10228 might be branch-over-pool insns introduced by chunkify_start.
10229 Those never need to be split however.) */
10230
10231 for (;;)
10232 {
10233 struct constant_pool *pool = NULL;
10234
10235 /* Collect the literal pool. */
10236 if (!pool_overflow)
10237 {
10238 pool = s390_mainpool_start ();
10239 if (!pool)
10240 pool_overflow = true;
10241 }
10242
10243 /* If literal pool overflowed, start to chunkify it. */
10244 if (pool_overflow)
10245 pool = s390_chunkify_start ();
10246
10247 /* Split out-of-range branches. If this has created new
10248 literal pool entries, cancel current chunk list and
10249 recompute it. zSeries machines have large branch
10250 instructions, so we never need to split a branch. */
10251 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10252 {
10253 if (pool_overflow)
10254 s390_chunkify_cancel (pool);
10255 else
10256 s390_mainpool_cancel (pool);
10257
10258 continue;
10259 }
10260
10261 /* If we made it up to here, both conditions are satisfied.
10262 Finish up literal pool related changes. */
10263 if (pool_overflow)
10264 s390_chunkify_finish (pool);
10265 else
10266 s390_mainpool_finish (pool);
10267
10268 /* We're done splitting branches. */
10269 cfun->machine->split_branches_pending_p = false;
10270 break;
10271 }
10272
10273 /* Generate out-of-pool execute target insns. */
10274 if (TARGET_CPU_ZARCH)
10275 {
10276 rtx insn, label, target;
10277
10278 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10279 {
10280 label = s390_execute_label (insn);
10281 if (!label)
10282 continue;
10283
10284 gcc_assert (label != const0_rtx);
10285
10286 target = emit_label (XEXP (label, 0));
10287 INSN_ADDRESSES_NEW (target, -1);
10288
10289 target = emit_insn (s390_execute_target (insn));
10290 INSN_ADDRESSES_NEW (target, -1);
10291 }
10292 }
10293
10294 /* Try to optimize prologue and epilogue further. */
10295 s390_optimize_prologue ();
10296
10297 /* Walk over the insns and do some >=z10 specific changes. */
10298 if (s390_tune == PROCESSOR_2097_Z10
10299 || s390_tune == PROCESSOR_2817_Z196)
10300 {
10301 rtx insn;
10302 bool insn_added_p = false;
10303
10304 /* The insn lengths and addresses have to be up to date for the
10305 following manipulations. */
10306 shorten_branches (get_insns ());
10307
10308 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10309 {
10310 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10311 continue;
10312
10313 if (JUMP_P (insn))
10314 insn_added_p |= s390_fix_long_loop_prediction (insn);
10315
10316 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10317 || GET_CODE (PATTERN (insn)) == SET)
10318 && s390_tune == PROCESSOR_2097_Z10)
10319 insn_added_p |= s390_z10_optimize_cmp (insn);
10320 }
10321
10322 /* Adjust branches if we added new instructions. */
10323 if (insn_added_p)
10324 shorten_branches (get_insns ());
10325 }
10326 }
10327
10328 /* Return true if INSN is a fp load insn writing register REGNO. */
10329 static inline bool
10330 s390_fpload_toreg (rtx insn, unsigned int regno)
10331 {
10332 rtx set;
10333 enum attr_type flag = s390_safe_attr_type (insn);
10334
10335 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10336 return false;
10337
10338 set = single_set (insn);
10339
10340 if (set == NULL_RTX)
10341 return false;
10342
10343 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10344 return false;
10345
10346 if (REGNO (SET_DEST (set)) != regno)
10347 return false;
10348
10349 return true;
10350 }
10351
10352 /* This value describes the distance to be avoided between an
10353 aritmetic fp instruction and an fp load writing the same register.
10354 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10355 fine but the exact value has to be avoided. Otherwise the FP
10356 pipeline will throw an exception causing a major penalty. */
10357 #define Z10_EARLYLOAD_DISTANCE 7
10358
10359 /* Rearrange the ready list in order to avoid the situation described
10360 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10361 moved to the very end of the ready list. */
10362 static void
10363 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10364 {
10365 unsigned int regno;
10366 int nready = *nready_p;
10367 rtx tmp;
10368 int i;
10369 rtx insn;
10370 rtx set;
10371 enum attr_type flag;
10372 int distance;
10373
10374 /* Skip DISTANCE - 1 active insns. */
10375 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10376 distance > 0 && insn != NULL_RTX;
10377 distance--, insn = prev_active_insn (insn))
10378 if (CALL_P (insn) || JUMP_P (insn))
10379 return;
10380
10381 if (insn == NULL_RTX)
10382 return;
10383
10384 set = single_set (insn);
10385
10386 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10387 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10388 return;
10389
10390 flag = s390_safe_attr_type (insn);
10391
10392 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10393 return;
10394
10395 regno = REGNO (SET_DEST (set));
10396 i = nready - 1;
10397
10398 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10399 i--;
10400
10401 if (!i)
10402 return;
10403
10404 tmp = ready[i];
10405 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10406 ready[0] = tmp;
10407 }
10408
10409 /* This function is called via hook TARGET_SCHED_REORDER before
10410 issueing one insn from list READY which contains *NREADYP entries.
10411 For target z10 it reorders load instructions to avoid early load
10412 conflicts in the floating point pipeline */
10413 static int
10414 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10415 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10416 {
10417 if (s390_tune == PROCESSOR_2097_Z10)
10418 if (reload_completed && *nreadyp > 1)
10419 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10420
10421 return s390_issue_rate ();
10422 }
10423
10424 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10425 the scheduler has issued INSN. It stores the last issued insn into
10426 last_scheduled_insn in order to make it available for
10427 s390_sched_reorder. */
10428 static int
10429 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10430 int verbose ATTRIBUTE_UNUSED,
10431 rtx insn, int more)
10432 {
10433 last_scheduled_insn = insn;
10434
10435 if (GET_CODE (PATTERN (insn)) != USE
10436 && GET_CODE (PATTERN (insn)) != CLOBBER)
10437 return more - 1;
10438 else
10439 return more;
10440 }
10441
10442 static void
10443 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10444 int verbose ATTRIBUTE_UNUSED,
10445 int max_ready ATTRIBUTE_UNUSED)
10446 {
10447 last_scheduled_insn = NULL_RTX;
10448 }
10449
10450 /* This function checks the whole of insn X for memory references. The
10451 function always returns zero because the framework it is called
10452 from would stop recursively analyzing the insn upon a return value
10453 other than zero. The real result of this function is updating
10454 counter variable MEM_COUNT. */
10455 static int
10456 check_dpu (rtx *x, unsigned *mem_count)
10457 {
10458 if (*x != NULL_RTX && MEM_P (*x))
10459 (*mem_count)++;
10460 return 0;
10461 }
10462
10463 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10464 a new number struct loop *loop should be unrolled if tuned for cpus with
10465 a built-in stride prefetcher.
10466 The loop is analyzed for memory accesses by calling check_dpu for
10467 each rtx of the loop. Depending on the loop_depth and the amount of
10468 memory accesses a new number <=nunroll is returned to improve the
10469 behaviour of the hardware prefetch unit. */
10470 static unsigned
10471 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10472 {
10473 basic_block *bbs;
10474 rtx insn;
10475 unsigned i;
10476 unsigned mem_count = 0;
10477
10478 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10479 return nunroll;
10480
10481 /* Count the number of memory references within the loop body. */
10482 bbs = get_loop_body (loop);
10483 for (i = 0; i < loop->num_nodes; i++)
10484 {
10485 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10486 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10487 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10488 }
10489 free (bbs);
10490
10491 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10492 if (mem_count == 0)
10493 return nunroll;
10494
10495 switch (loop_depth(loop))
10496 {
10497 case 1:
10498 return MIN (nunroll, 28 / mem_count);
10499 case 2:
10500 return MIN (nunroll, 22 / mem_count);
10501 default:
10502 return MIN (nunroll, 16 / mem_count);
10503 }
10504 }
10505
10506 /* Initialize GCC target structure. */
10507
10508 #undef TARGET_ASM_ALIGNED_HI_OP
10509 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10510 #undef TARGET_ASM_ALIGNED_DI_OP
10511 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10512 #undef TARGET_ASM_INTEGER
10513 #define TARGET_ASM_INTEGER s390_assemble_integer
10514
10515 #undef TARGET_ASM_OPEN_PAREN
10516 #define TARGET_ASM_OPEN_PAREN ""
10517
10518 #undef TARGET_ASM_CLOSE_PAREN
10519 #define TARGET_ASM_CLOSE_PAREN ""
10520
10521 #undef TARGET_DEFAULT_TARGET_FLAGS
10522 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
10523
10524 #undef TARGET_HANDLE_OPTION
10525 #define TARGET_HANDLE_OPTION s390_handle_option
10526
10527 #undef TARGET_OPTION_OVERRIDE
10528 #define TARGET_OPTION_OVERRIDE s390_option_override
10529
10530 #undef TARGET_OPTION_OPTIMIZATION_TABLE
10531 #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table
10532
10533 #undef TARGET_OPTION_INIT_STRUCT
10534 #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct
10535
10536 #undef TARGET_ENCODE_SECTION_INFO
10537 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10538
10539 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10540 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10541
10542 #ifdef HAVE_AS_TLS
10543 #undef TARGET_HAVE_TLS
10544 #define TARGET_HAVE_TLS true
10545 #endif
10546 #undef TARGET_CANNOT_FORCE_CONST_MEM
10547 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10548
10549 #undef TARGET_DELEGITIMIZE_ADDRESS
10550 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10551
10552 #undef TARGET_LEGITIMIZE_ADDRESS
10553 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10554
10555 #undef TARGET_RETURN_IN_MEMORY
10556 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10557
10558 #undef TARGET_INIT_BUILTINS
10559 #define TARGET_INIT_BUILTINS s390_init_builtins
10560 #undef TARGET_EXPAND_BUILTIN
10561 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10562
10563 #undef TARGET_ASM_OUTPUT_MI_THUNK
10564 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10565 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10566 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10567
10568 #undef TARGET_SCHED_ADJUST_PRIORITY
10569 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10570 #undef TARGET_SCHED_ISSUE_RATE
10571 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10572 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10573 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10574
10575 #undef TARGET_SCHED_VARIABLE_ISSUE
10576 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10577 #undef TARGET_SCHED_REORDER
10578 #define TARGET_SCHED_REORDER s390_sched_reorder
10579 #undef TARGET_SCHED_INIT
10580 #define TARGET_SCHED_INIT s390_sched_init
10581
10582 #undef TARGET_CANNOT_COPY_INSN_P
10583 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10584 #undef TARGET_RTX_COSTS
10585 #define TARGET_RTX_COSTS s390_rtx_costs
10586 #undef TARGET_ADDRESS_COST
10587 #define TARGET_ADDRESS_COST s390_address_cost
10588
10589 #undef TARGET_MACHINE_DEPENDENT_REORG
10590 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10591
10592 #undef TARGET_VALID_POINTER_MODE
10593 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10594
10595 #undef TARGET_BUILD_BUILTIN_VA_LIST
10596 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10597 #undef TARGET_EXPAND_BUILTIN_VA_START
10598 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10599 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10600 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10601
10602 #undef TARGET_PROMOTE_FUNCTION_MODE
10603 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10604 #undef TARGET_PASS_BY_REFERENCE
10605 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10606
10607 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10608 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10609 #undef TARGET_FUNCTION_ARG
10610 #define TARGET_FUNCTION_ARG s390_function_arg
10611 #undef TARGET_FUNCTION_ARG_ADVANCE
10612 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10613
10614 #undef TARGET_FIXED_CONDITION_CODE_REGS
10615 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10616
10617 #undef TARGET_CC_MODES_COMPATIBLE
10618 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10619
10620 #undef TARGET_INVALID_WITHIN_DOLOOP
10621 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10622
10623 #ifdef HAVE_AS_TLS
10624 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10625 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10626 #endif
10627
10628 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10629 #undef TARGET_MANGLE_TYPE
10630 #define TARGET_MANGLE_TYPE s390_mangle_type
10631 #endif
10632
10633 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10634 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10635
10636 #undef TARGET_SECONDARY_RELOAD
10637 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10638
10639 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10640 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10641
10642 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10643 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10644
10645 #undef TARGET_LEGITIMATE_ADDRESS_P
10646 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10647
10648 #undef TARGET_CAN_ELIMINATE
10649 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10650
10651 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10652 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10653
10654 #undef TARGET_LOOP_UNROLL_ADJUST
10655 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10656
10657 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10658 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10659 #undef TARGET_TRAMPOLINE_INIT
10660 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10661
10662 #undef TARGET_UNWIND_WORD_MODE
10663 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10664
10665 struct gcc_target targetm = TARGET_INITIALIZER;
10666
10667 #include "gt-s390.h"