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[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48 #include "debug.h"
49 #include "langhooks.h"
50 #include "optabs.h"
51 #include "gimple.h"
52 #include "df.h"
53 #include "params.h"
54 #include "cfgloop.h"
55 #include "opts.h"
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 static const
225 struct processor_costs z196_cost =
226 {
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
254 };
255
256 extern int reload_completed;
257
258 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
259 static rtx last_scheduled_insn;
260
261 /* Structure used to hold the components of a S/390 memory
262 address. A legitimate address on S/390 is of the general
263 form
264 base + index + displacement
265 where any of the components is optional.
266
267 base and index are registers of the class ADDR_REGS,
268 displacement is an unsigned 12-bit immediate constant. */
269
270 struct s390_address
271 {
272 rtx base;
273 rtx indx;
274 rtx disp;
275 bool pointer;
276 bool literal_pool;
277 };
278
279 /* The following structure is embedded in the machine
280 specific part of struct function. */
281
282 struct GTY (()) s390_frame_layout
283 {
284 /* Offset within stack frame. */
285 HOST_WIDE_INT gprs_offset;
286 HOST_WIDE_INT f0_offset;
287 HOST_WIDE_INT f4_offset;
288 HOST_WIDE_INT f8_offset;
289 HOST_WIDE_INT backchain_offset;
290
291 /* Number of first and last gpr where slots in the register
292 save area are reserved for. */
293 int first_save_gpr_slot;
294 int last_save_gpr_slot;
295
296 /* Number of first and last gpr to be saved, restored. */
297 int first_save_gpr;
298 int first_restore_gpr;
299 int last_save_gpr;
300 int last_restore_gpr;
301
302 /* Bits standing for floating point registers. Set, if the
303 respective register has to be saved. Starting with reg 16 (f0)
304 at the rightmost bit.
305 Bit 15 - 8 7 6 5 4 3 2 1 0
306 fpr 15 - 8 7 5 3 1 6 4 2 0
307 reg 31 - 24 23 22 21 20 19 18 17 16 */
308 unsigned int fpr_bitmap;
309
310 /* Number of floating point registers f8-f15 which must be saved. */
311 int high_fprs;
312
313 /* Set if return address needs to be saved.
314 This flag is set by s390_return_addr_rtx if it could not use
315 the initial value of r14 and therefore depends on r14 saved
316 to the stack. */
317 bool save_return_addr_p;
318
319 /* Size of stack frame. */
320 HOST_WIDE_INT frame_size;
321 };
322
323 /* Define the structure for the machine field in struct function. */
324
325 struct GTY(()) machine_function
326 {
327 struct s390_frame_layout frame_layout;
328
329 /* Literal pool base register. */
330 rtx base_reg;
331
332 /* True if we may need to perform branch splitting. */
333 bool split_branches_pending_p;
334
335 /* Some local-dynamic TLS symbol name. */
336 const char *some_ld_name;
337
338 bool has_landing_pad_p;
339 };
340
341 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
342
343 #define cfun_frame_layout (cfun->machine->frame_layout)
344 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
345 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
346 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
347 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
348 (1 << (BITNUM)))
349 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
350 (1 << (BITNUM))))
351
352 /* Number of GPRs and FPRs used for argument passing. */
353 #define GP_ARG_NUM_REG 5
354 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
355
356 /* A couple of shortcuts. */
357 #define CONST_OK_FOR_J(x) \
358 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
359 #define CONST_OK_FOR_K(x) \
360 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
361 #define CONST_OK_FOR_Os(x) \
362 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
363 #define CONST_OK_FOR_Op(x) \
364 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
365 #define CONST_OK_FOR_On(x) \
366 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
367
368 #define REGNO_PAIR_OK(REGNO, MODE) \
369 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
370
371 /* That's the read ahead of the dynamic branch prediction unit in
372 bytes on a z10 (or higher) CPU. */
373 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
374
375 /* Return the alignment for LABEL. We default to the -falign-labels
376 value except for the literal pool base label. */
377 int
378 s390_label_align (rtx label)
379 {
380 rtx prev_insn = prev_active_insn (label);
381
382 if (prev_insn == NULL_RTX)
383 goto old;
384
385 prev_insn = single_set (prev_insn);
386
387 if (prev_insn == NULL_RTX)
388 goto old;
389
390 prev_insn = SET_SRC (prev_insn);
391
392 /* Don't align literal pool base labels. */
393 if (GET_CODE (prev_insn) == UNSPEC
394 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
395 return 0;
396
397 old:
398 return align_labels_log;
399 }
400
401 static enum machine_mode
402 s390_libgcc_cmp_return_mode (void)
403 {
404 return TARGET_64BIT ? DImode : SImode;
405 }
406
407 static enum machine_mode
408 s390_libgcc_shift_count_mode (void)
409 {
410 return TARGET_64BIT ? DImode : SImode;
411 }
412
413 static enum machine_mode
414 s390_unwind_word_mode (void)
415 {
416 return TARGET_64BIT ? DImode : SImode;
417 }
418
419 /* Return true if the back end supports mode MODE. */
420 static bool
421 s390_scalar_mode_supported_p (enum machine_mode mode)
422 {
423 /* In contrast to the default implementation reject TImode constants on 31bit
424 TARGET_ZARCH for ABI compliance. */
425 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
426 return false;
427
428 if (DECIMAL_FLOAT_MODE_P (mode))
429 return default_decimal_float_supported_p ();
430
431 return default_scalar_mode_supported_p (mode);
432 }
433
434 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
435
436 void
437 s390_set_has_landing_pad_p (bool value)
438 {
439 cfun->machine->has_landing_pad_p = value;
440 }
441
442 /* If two condition code modes are compatible, return a condition code
443 mode which is compatible with both. Otherwise, return
444 VOIDmode. */
445
446 static enum machine_mode
447 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
448 {
449 if (m1 == m2)
450 return m1;
451
452 switch (m1)
453 {
454 case CCZmode:
455 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
456 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
457 return m2;
458 return VOIDmode;
459
460 case CCSmode:
461 case CCUmode:
462 case CCTmode:
463 case CCSRmode:
464 case CCURmode:
465 case CCZ1mode:
466 if (m2 == CCZmode)
467 return m1;
468
469 return VOIDmode;
470
471 default:
472 return VOIDmode;
473 }
474 return VOIDmode;
475 }
476
477 /* Return true if SET either doesn't set the CC register, or else
478 the source and destination have matching CC modes and that
479 CC mode is at least as constrained as REQ_MODE. */
480
481 static bool
482 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
483 {
484 enum machine_mode set_mode;
485
486 gcc_assert (GET_CODE (set) == SET);
487
488 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
489 return 1;
490
491 set_mode = GET_MODE (SET_DEST (set));
492 switch (set_mode)
493 {
494 case CCSmode:
495 case CCSRmode:
496 case CCUmode:
497 case CCURmode:
498 case CCLmode:
499 case CCL1mode:
500 case CCL2mode:
501 case CCL3mode:
502 case CCT1mode:
503 case CCT2mode:
504 case CCT3mode:
505 if (req_mode != set_mode)
506 return 0;
507 break;
508
509 case CCZmode:
510 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
511 && req_mode != CCSRmode && req_mode != CCURmode)
512 return 0;
513 break;
514
515 case CCAPmode:
516 case CCANmode:
517 if (req_mode != CCAmode)
518 return 0;
519 break;
520
521 default:
522 gcc_unreachable ();
523 }
524
525 return (GET_MODE (SET_SRC (set)) == set_mode);
526 }
527
528 /* Return true if every SET in INSN that sets the CC register
529 has source and destination with matching CC modes and that
530 CC mode is at least as constrained as REQ_MODE.
531 If REQ_MODE is VOIDmode, always return false. */
532
533 bool
534 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
535 {
536 int i;
537
538 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
539 if (req_mode == VOIDmode)
540 return false;
541
542 if (GET_CODE (PATTERN (insn)) == SET)
543 return s390_match_ccmode_set (PATTERN (insn), req_mode);
544
545 if (GET_CODE (PATTERN (insn)) == PARALLEL)
546 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
547 {
548 rtx set = XVECEXP (PATTERN (insn), 0, i);
549 if (GET_CODE (set) == SET)
550 if (!s390_match_ccmode_set (set, req_mode))
551 return false;
552 }
553
554 return true;
555 }
556
557 /* If a test-under-mask instruction can be used to implement
558 (compare (and ... OP1) OP2), return the CC mode required
559 to do that. Otherwise, return VOIDmode.
560 MIXED is true if the instruction can distinguish between
561 CC1 and CC2 for mixed selected bits (TMxx), it is false
562 if the instruction cannot (TM). */
563
564 enum machine_mode
565 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
566 {
567 int bit0, bit1;
568
569 /* ??? Fixme: should work on CONST_DOUBLE as well. */
570 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
571 return VOIDmode;
572
573 /* Selected bits all zero: CC0.
574 e.g.: int a; if ((a & (16 + 128)) == 0) */
575 if (INTVAL (op2) == 0)
576 return CCTmode;
577
578 /* Selected bits all one: CC3.
579 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
580 if (INTVAL (op2) == INTVAL (op1))
581 return CCT3mode;
582
583 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
584 int a;
585 if ((a & (16 + 128)) == 16) -> CCT1
586 if ((a & (16 + 128)) == 128) -> CCT2 */
587 if (mixed)
588 {
589 bit1 = exact_log2 (INTVAL (op2));
590 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
591 if (bit0 != -1 && bit1 != -1)
592 return bit0 > bit1 ? CCT1mode : CCT2mode;
593 }
594
595 return VOIDmode;
596 }
597
598 /* Given a comparison code OP (EQ, NE, etc.) and the operands
599 OP0 and OP1 of a COMPARE, return the mode to be used for the
600 comparison. */
601
602 enum machine_mode
603 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
604 {
605 switch (code)
606 {
607 case EQ:
608 case NE:
609 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
610 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
611 return CCAPmode;
612 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
613 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
614 return CCAPmode;
615 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
616 || GET_CODE (op1) == NEG)
617 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
618 return CCLmode;
619
620 if (GET_CODE (op0) == AND)
621 {
622 /* Check whether we can potentially do it via TM. */
623 enum machine_mode ccmode;
624 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
625 if (ccmode != VOIDmode)
626 {
627 /* Relax CCTmode to CCZmode to allow fall-back to AND
628 if that turns out to be beneficial. */
629 return ccmode == CCTmode ? CCZmode : ccmode;
630 }
631 }
632
633 if (register_operand (op0, HImode)
634 && GET_CODE (op1) == CONST_INT
635 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
636 return CCT3mode;
637 if (register_operand (op0, QImode)
638 && GET_CODE (op1) == CONST_INT
639 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
640 return CCT3mode;
641
642 return CCZmode;
643
644 case LE:
645 case LT:
646 case GE:
647 case GT:
648 /* The only overflow condition of NEG and ABS happens when
649 -INT_MAX is used as parameter, which stays negative. So
650 we have an overflow from a positive value to a negative.
651 Using CCAP mode the resulting cc can be used for comparisons. */
652 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
653 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
654 return CCAPmode;
655
656 /* If constants are involved in an add instruction it is possible to use
657 the resulting cc for comparisons with zero. Knowing the sign of the
658 constant the overflow behavior gets predictable. e.g.:
659 int a, b; if ((b = a + c) > 0)
660 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
661 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
662 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
663 {
664 if (INTVAL (XEXP((op0), 1)) < 0)
665 return CCANmode;
666 else
667 return CCAPmode;
668 }
669 /* Fall through. */
670 case UNORDERED:
671 case ORDERED:
672 case UNEQ:
673 case UNLE:
674 case UNLT:
675 case UNGE:
676 case UNGT:
677 case LTGT:
678 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
679 && GET_CODE (op1) != CONST_INT)
680 return CCSRmode;
681 return CCSmode;
682
683 case LTU:
684 case GEU:
685 if (GET_CODE (op0) == PLUS
686 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
687 return CCL1mode;
688
689 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
690 && GET_CODE (op1) != CONST_INT)
691 return CCURmode;
692 return CCUmode;
693
694 case LEU:
695 case GTU:
696 if (GET_CODE (op0) == MINUS
697 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
698 return CCL2mode;
699
700 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
701 && GET_CODE (op1) != CONST_INT)
702 return CCURmode;
703 return CCUmode;
704
705 default:
706 gcc_unreachable ();
707 }
708 }
709
710 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
711 that we can implement more efficiently. */
712
713 void
714 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
715 {
716 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
717 if ((*code == EQ || *code == NE)
718 && *op1 == const0_rtx
719 && GET_CODE (*op0) == ZERO_EXTRACT
720 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
721 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
722 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
723 {
724 rtx inner = XEXP (*op0, 0);
725 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
726 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
727 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
728
729 if (len > 0 && len < modesize
730 && pos >= 0 && pos + len <= modesize
731 && modesize <= HOST_BITS_PER_WIDE_INT)
732 {
733 unsigned HOST_WIDE_INT block;
734 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
735 block <<= modesize - pos - len;
736
737 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
738 gen_int_mode (block, GET_MODE (inner)));
739 }
740 }
741
742 /* Narrow AND of memory against immediate to enable TM. */
743 if ((*code == EQ || *code == NE)
744 && *op1 == const0_rtx
745 && GET_CODE (*op0) == AND
746 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
747 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
748 {
749 rtx inner = XEXP (*op0, 0);
750 rtx mask = XEXP (*op0, 1);
751
752 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
753 if (GET_CODE (inner) == SUBREG
754 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
755 && (GET_MODE_SIZE (GET_MODE (inner))
756 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
757 && ((INTVAL (mask)
758 & GET_MODE_MASK (GET_MODE (inner))
759 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
760 == 0))
761 inner = SUBREG_REG (inner);
762
763 /* Do not change volatile MEMs. */
764 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
765 {
766 int part = s390_single_part (XEXP (*op0, 1),
767 GET_MODE (inner), QImode, 0);
768 if (part >= 0)
769 {
770 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
771 inner = adjust_address_nv (inner, QImode, part);
772 *op0 = gen_rtx_AND (QImode, inner, mask);
773 }
774 }
775 }
776
777 /* Narrow comparisons against 0xffff to HImode if possible. */
778 if ((*code == EQ || *code == NE)
779 && GET_CODE (*op1) == CONST_INT
780 && INTVAL (*op1) == 0xffff
781 && SCALAR_INT_MODE_P (GET_MODE (*op0))
782 && (nonzero_bits (*op0, GET_MODE (*op0))
783 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
784 {
785 *op0 = gen_lowpart (HImode, *op0);
786 *op1 = constm1_rtx;
787 }
788
789 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
790 if (GET_CODE (*op0) == UNSPEC
791 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
792 && XVECLEN (*op0, 0) == 1
793 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
794 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
795 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
796 && *op1 == const0_rtx)
797 {
798 enum rtx_code new_code = UNKNOWN;
799 switch (*code)
800 {
801 case EQ: new_code = EQ; break;
802 case NE: new_code = NE; break;
803 case LT: new_code = GTU; break;
804 case GT: new_code = LTU; break;
805 case LE: new_code = GEU; break;
806 case GE: new_code = LEU; break;
807 default: break;
808 }
809
810 if (new_code != UNKNOWN)
811 {
812 *op0 = XVECEXP (*op0, 0, 0);
813 *code = new_code;
814 }
815 }
816
817 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
818 if (GET_CODE (*op0) == UNSPEC
819 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
820 && XVECLEN (*op0, 0) == 1
821 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
822 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
823 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
824 && *op1 == const0_rtx)
825 {
826 enum rtx_code new_code = UNKNOWN;
827 switch (*code)
828 {
829 case EQ: new_code = EQ; break;
830 case NE: new_code = NE; break;
831 default: break;
832 }
833
834 if (new_code != UNKNOWN)
835 {
836 *op0 = XVECEXP (*op0, 0, 0);
837 *code = new_code;
838 }
839 }
840
841 /* Simplify cascaded EQ, NE with const0_rtx. */
842 if ((*code == NE || *code == EQ)
843 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
844 && GET_MODE (*op0) == SImode
845 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
846 && REG_P (XEXP (*op0, 0))
847 && XEXP (*op0, 1) == const0_rtx
848 && *op1 == const0_rtx)
849 {
850 if ((*code == EQ && GET_CODE (*op0) == NE)
851 || (*code == NE && GET_CODE (*op0) == EQ))
852 *code = EQ;
853 else
854 *code = NE;
855 *op0 = XEXP (*op0, 0);
856 }
857
858 /* Prefer register over memory as first operand. */
859 if (MEM_P (*op0) && REG_P (*op1))
860 {
861 rtx tem = *op0; *op0 = *op1; *op1 = tem;
862 *code = swap_condition (*code);
863 }
864 }
865
866 /* Emit a compare instruction suitable to implement the comparison
867 OP0 CODE OP1. Return the correct condition RTL to be placed in
868 the IF_THEN_ELSE of the conditional branch testing the result. */
869
870 rtx
871 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
872 {
873 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
874 rtx cc;
875
876 /* Do not output a redundant compare instruction if a compare_and_swap
877 pattern already computed the result and the machine modes are compatible. */
878 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
879 {
880 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
881 == GET_MODE (op0));
882 cc = op0;
883 }
884 else
885 {
886 cc = gen_rtx_REG (mode, CC_REGNUM);
887 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
888 }
889
890 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
891 }
892
893 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
894 matches CMP.
895 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
896 conditional branch testing the result. */
897
898 static rtx
899 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
900 {
901 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
902 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
903 }
904
905 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
906 unconditional jump, else a conditional jump under condition COND. */
907
908 void
909 s390_emit_jump (rtx target, rtx cond)
910 {
911 rtx insn;
912
913 target = gen_rtx_LABEL_REF (VOIDmode, target);
914 if (cond)
915 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
916
917 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
918 emit_jump_insn (insn);
919 }
920
921 /* Return branch condition mask to implement a branch
922 specified by CODE. Return -1 for invalid comparisons. */
923
924 int
925 s390_branch_condition_mask (rtx code)
926 {
927 const int CC0 = 1 << 3;
928 const int CC1 = 1 << 2;
929 const int CC2 = 1 << 1;
930 const int CC3 = 1 << 0;
931
932 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
933 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
934 gcc_assert (XEXP (code, 1) == const0_rtx);
935
936 switch (GET_MODE (XEXP (code, 0)))
937 {
938 case CCZmode:
939 case CCZ1mode:
940 switch (GET_CODE (code))
941 {
942 case EQ: return CC0;
943 case NE: return CC1 | CC2 | CC3;
944 default: return -1;
945 }
946 break;
947
948 case CCT1mode:
949 switch (GET_CODE (code))
950 {
951 case EQ: return CC1;
952 case NE: return CC0 | CC2 | CC3;
953 default: return -1;
954 }
955 break;
956
957 case CCT2mode:
958 switch (GET_CODE (code))
959 {
960 case EQ: return CC2;
961 case NE: return CC0 | CC1 | CC3;
962 default: return -1;
963 }
964 break;
965
966 case CCT3mode:
967 switch (GET_CODE (code))
968 {
969 case EQ: return CC3;
970 case NE: return CC0 | CC1 | CC2;
971 default: return -1;
972 }
973 break;
974
975 case CCLmode:
976 switch (GET_CODE (code))
977 {
978 case EQ: return CC0 | CC2;
979 case NE: return CC1 | CC3;
980 default: return -1;
981 }
982 break;
983
984 case CCL1mode:
985 switch (GET_CODE (code))
986 {
987 case LTU: return CC2 | CC3; /* carry */
988 case GEU: return CC0 | CC1; /* no carry */
989 default: return -1;
990 }
991 break;
992
993 case CCL2mode:
994 switch (GET_CODE (code))
995 {
996 case GTU: return CC0 | CC1; /* borrow */
997 case LEU: return CC2 | CC3; /* no borrow */
998 default: return -1;
999 }
1000 break;
1001
1002 case CCL3mode:
1003 switch (GET_CODE (code))
1004 {
1005 case EQ: return CC0 | CC2;
1006 case NE: return CC1 | CC3;
1007 case LTU: return CC1;
1008 case GTU: return CC3;
1009 case LEU: return CC1 | CC2;
1010 case GEU: return CC2 | CC3;
1011 default: return -1;
1012 }
1013
1014 case CCUmode:
1015 switch (GET_CODE (code))
1016 {
1017 case EQ: return CC0;
1018 case NE: return CC1 | CC2 | CC3;
1019 case LTU: return CC1;
1020 case GTU: return CC2;
1021 case LEU: return CC0 | CC1;
1022 case GEU: return CC0 | CC2;
1023 default: return -1;
1024 }
1025 break;
1026
1027 case CCURmode:
1028 switch (GET_CODE (code))
1029 {
1030 case EQ: return CC0;
1031 case NE: return CC2 | CC1 | CC3;
1032 case LTU: return CC2;
1033 case GTU: return CC1;
1034 case LEU: return CC0 | CC2;
1035 case GEU: return CC0 | CC1;
1036 default: return -1;
1037 }
1038 break;
1039
1040 case CCAPmode:
1041 switch (GET_CODE (code))
1042 {
1043 case EQ: return CC0;
1044 case NE: return CC1 | CC2 | CC3;
1045 case LT: return CC1 | CC3;
1046 case GT: return CC2;
1047 case LE: return CC0 | CC1 | CC3;
1048 case GE: return CC0 | CC2;
1049 default: return -1;
1050 }
1051 break;
1052
1053 case CCANmode:
1054 switch (GET_CODE (code))
1055 {
1056 case EQ: return CC0;
1057 case NE: return CC1 | CC2 | CC3;
1058 case LT: return CC1;
1059 case GT: return CC2 | CC3;
1060 case LE: return CC0 | CC1;
1061 case GE: return CC0 | CC2 | CC3;
1062 default: return -1;
1063 }
1064 break;
1065
1066 case CCSmode:
1067 switch (GET_CODE (code))
1068 {
1069 case EQ: return CC0;
1070 case NE: return CC1 | CC2 | CC3;
1071 case LT: return CC1;
1072 case GT: return CC2;
1073 case LE: return CC0 | CC1;
1074 case GE: return CC0 | CC2;
1075 case UNORDERED: return CC3;
1076 case ORDERED: return CC0 | CC1 | CC2;
1077 case UNEQ: return CC0 | CC3;
1078 case UNLT: return CC1 | CC3;
1079 case UNGT: return CC2 | CC3;
1080 case UNLE: return CC0 | CC1 | CC3;
1081 case UNGE: return CC0 | CC2 | CC3;
1082 case LTGT: return CC1 | CC2;
1083 default: return -1;
1084 }
1085 break;
1086
1087 case CCSRmode:
1088 switch (GET_CODE (code))
1089 {
1090 case EQ: return CC0;
1091 case NE: return CC2 | CC1 | CC3;
1092 case LT: return CC2;
1093 case GT: return CC1;
1094 case LE: return CC0 | CC2;
1095 case GE: return CC0 | CC1;
1096 case UNORDERED: return CC3;
1097 case ORDERED: return CC0 | CC2 | CC1;
1098 case UNEQ: return CC0 | CC3;
1099 case UNLT: return CC2 | CC3;
1100 case UNGT: return CC1 | CC3;
1101 case UNLE: return CC0 | CC2 | CC3;
1102 case UNGE: return CC0 | CC1 | CC3;
1103 case LTGT: return CC2 | CC1;
1104 default: return -1;
1105 }
1106 break;
1107
1108 default:
1109 return -1;
1110 }
1111 }
1112
1113
1114 /* Return branch condition mask to implement a compare and branch
1115 specified by CODE. Return -1 for invalid comparisons. */
1116
1117 int
1118 s390_compare_and_branch_condition_mask (rtx code)
1119 {
1120 const int CC0 = 1 << 3;
1121 const int CC1 = 1 << 2;
1122 const int CC2 = 1 << 1;
1123
1124 switch (GET_CODE (code))
1125 {
1126 case EQ:
1127 return CC0;
1128 case NE:
1129 return CC1 | CC2;
1130 case LT:
1131 case LTU:
1132 return CC1;
1133 case GT:
1134 case GTU:
1135 return CC2;
1136 case LE:
1137 case LEU:
1138 return CC0 | CC1;
1139 case GE:
1140 case GEU:
1141 return CC0 | CC2;
1142 default:
1143 gcc_unreachable ();
1144 }
1145 return -1;
1146 }
1147
1148 /* If INV is false, return assembler mnemonic string to implement
1149 a branch specified by CODE. If INV is true, return mnemonic
1150 for the corresponding inverted branch. */
1151
1152 static const char *
1153 s390_branch_condition_mnemonic (rtx code, int inv)
1154 {
1155 int mask;
1156
1157 static const char *const mnemonic[16] =
1158 {
1159 NULL, "o", "h", "nle",
1160 "l", "nhe", "lh", "ne",
1161 "e", "nlh", "he", "nl",
1162 "le", "nh", "no", NULL
1163 };
1164
1165 if (GET_CODE (XEXP (code, 0)) == REG
1166 && REGNO (XEXP (code, 0)) == CC_REGNUM
1167 && XEXP (code, 1) == const0_rtx)
1168 mask = s390_branch_condition_mask (code);
1169 else
1170 mask = s390_compare_and_branch_condition_mask (code);
1171
1172 gcc_assert (mask >= 0);
1173
1174 if (inv)
1175 mask ^= 15;
1176
1177 gcc_assert (mask >= 1 && mask <= 14);
1178
1179 return mnemonic[mask];
1180 }
1181
1182 /* Return the part of op which has a value different from def.
1183 The size of the part is determined by mode.
1184 Use this function only if you already know that op really
1185 contains such a part. */
1186
1187 unsigned HOST_WIDE_INT
1188 s390_extract_part (rtx op, enum machine_mode mode, int def)
1189 {
1190 unsigned HOST_WIDE_INT value = 0;
1191 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1192 int part_bits = GET_MODE_BITSIZE (mode);
1193 unsigned HOST_WIDE_INT part_mask
1194 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1195 int i;
1196
1197 for (i = 0; i < max_parts; i++)
1198 {
1199 if (i == 0)
1200 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1201 else
1202 value >>= part_bits;
1203
1204 if ((value & part_mask) != (def & part_mask))
1205 return value & part_mask;
1206 }
1207
1208 gcc_unreachable ();
1209 }
1210
1211 /* If OP is an integer constant of mode MODE with exactly one
1212 part of mode PART_MODE unequal to DEF, return the number of that
1213 part. Otherwise, return -1. */
1214
1215 int
1216 s390_single_part (rtx op,
1217 enum machine_mode mode,
1218 enum machine_mode part_mode,
1219 int def)
1220 {
1221 unsigned HOST_WIDE_INT value = 0;
1222 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1223 unsigned HOST_WIDE_INT part_mask
1224 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1225 int i, part = -1;
1226
1227 if (GET_CODE (op) != CONST_INT)
1228 return -1;
1229
1230 for (i = 0; i < n_parts; i++)
1231 {
1232 if (i == 0)
1233 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1234 else
1235 value >>= GET_MODE_BITSIZE (part_mode);
1236
1237 if ((value & part_mask) != (def & part_mask))
1238 {
1239 if (part != -1)
1240 return -1;
1241 else
1242 part = i;
1243 }
1244 }
1245 return part == -1 ? -1 : n_parts - 1 - part;
1246 }
1247
1248 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1249 bits and no other bits are set in IN. POS and LENGTH can be used
1250 to obtain the start position and the length of the bitfield.
1251
1252 POS gives the position of the first bit of the bitfield counting
1253 from the lowest order bit starting with zero. In order to use this
1254 value for S/390 instructions this has to be converted to "bits big
1255 endian" style. */
1256
1257 bool
1258 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1259 int *pos, int *length)
1260 {
1261 int tmp_pos = 0;
1262 int tmp_length = 0;
1263 int i;
1264 unsigned HOST_WIDE_INT mask = 1ULL;
1265 bool contiguous = false;
1266
1267 for (i = 0; i < size; mask <<= 1, i++)
1268 {
1269 if (contiguous)
1270 {
1271 if (mask & in)
1272 tmp_length++;
1273 else
1274 break;
1275 }
1276 else
1277 {
1278 if (mask & in)
1279 {
1280 contiguous = true;
1281 tmp_length++;
1282 }
1283 else
1284 tmp_pos++;
1285 }
1286 }
1287
1288 if (!tmp_length)
1289 return false;
1290
1291 /* Calculate a mask for all bits beyond the contiguous bits. */
1292 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1293
1294 if (mask & in)
1295 return false;
1296
1297 if (tmp_length + tmp_pos - 1 > size)
1298 return false;
1299
1300 if (length)
1301 *length = tmp_length;
1302
1303 if (pos)
1304 *pos = tmp_pos;
1305
1306 return true;
1307 }
1308
1309 /* Check whether we can (and want to) split a double-word
1310 move in mode MODE from SRC to DST into two single-word
1311 moves, moving the subword FIRST_SUBWORD first. */
1312
1313 bool
1314 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1315 {
1316 /* Floating point registers cannot be split. */
1317 if (FP_REG_P (src) || FP_REG_P (dst))
1318 return false;
1319
1320 /* We don't need to split if operands are directly accessible. */
1321 if (s_operand (src, mode) || s_operand (dst, mode))
1322 return false;
1323
1324 /* Non-offsettable memory references cannot be split. */
1325 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1326 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1327 return false;
1328
1329 /* Moving the first subword must not clobber a register
1330 needed to move the second subword. */
1331 if (register_operand (dst, mode))
1332 {
1333 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1334 if (reg_overlap_mentioned_p (subreg, src))
1335 return false;
1336 }
1337
1338 return true;
1339 }
1340
1341 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1342 and [MEM2, MEM2 + SIZE] do overlap and false
1343 otherwise. */
1344
1345 bool
1346 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1347 {
1348 rtx addr1, addr2, addr_delta;
1349 HOST_WIDE_INT delta;
1350
1351 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1352 return true;
1353
1354 if (size == 0)
1355 return false;
1356
1357 addr1 = XEXP (mem1, 0);
1358 addr2 = XEXP (mem2, 0);
1359
1360 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1361
1362 /* This overlapping check is used by peepholes merging memory block operations.
1363 Overlapping operations would otherwise be recognized by the S/390 hardware
1364 and would fall back to a slower implementation. Allowing overlapping
1365 operations would lead to slow code but not to wrong code. Therefore we are
1366 somewhat optimistic if we cannot prove that the memory blocks are
1367 overlapping.
1368 That's why we return false here although this may accept operations on
1369 overlapping memory areas. */
1370 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1371 return false;
1372
1373 delta = INTVAL (addr_delta);
1374
1375 if (delta == 0
1376 || (delta > 0 && delta < size)
1377 || (delta < 0 && -delta < size))
1378 return true;
1379
1380 return false;
1381 }
1382
1383 /* Check whether the address of memory reference MEM2 equals exactly
1384 the address of memory reference MEM1 plus DELTA. Return true if
1385 we can prove this to be the case, false otherwise. */
1386
1387 bool
1388 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1389 {
1390 rtx addr1, addr2, addr_delta;
1391
1392 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1393 return false;
1394
1395 addr1 = XEXP (mem1, 0);
1396 addr2 = XEXP (mem2, 0);
1397
1398 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1399 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1400 return false;
1401
1402 return true;
1403 }
1404
1405 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1406
1407 void
1408 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1409 rtx *operands)
1410 {
1411 enum machine_mode wmode = mode;
1412 rtx dst = operands[0];
1413 rtx src1 = operands[1];
1414 rtx src2 = operands[2];
1415 rtx op, clob, tem;
1416
1417 /* If we cannot handle the operation directly, use a temp register. */
1418 if (!s390_logical_operator_ok_p (operands))
1419 dst = gen_reg_rtx (mode);
1420
1421 /* QImode and HImode patterns make sense only if we have a destination
1422 in memory. Otherwise perform the operation in SImode. */
1423 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1424 wmode = SImode;
1425
1426 /* Widen operands if required. */
1427 if (mode != wmode)
1428 {
1429 if (GET_CODE (dst) == SUBREG
1430 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1431 dst = tem;
1432 else if (REG_P (dst))
1433 dst = gen_rtx_SUBREG (wmode, dst, 0);
1434 else
1435 dst = gen_reg_rtx (wmode);
1436
1437 if (GET_CODE (src1) == SUBREG
1438 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1439 src1 = tem;
1440 else if (GET_MODE (src1) != VOIDmode)
1441 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1442
1443 if (GET_CODE (src2) == SUBREG
1444 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1445 src2 = tem;
1446 else if (GET_MODE (src2) != VOIDmode)
1447 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1448 }
1449
1450 /* Emit the instruction. */
1451 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1452 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1453 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1454
1455 /* Fix up the destination if needed. */
1456 if (dst != operands[0])
1457 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1458 }
1459
1460 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1461
1462 bool
1463 s390_logical_operator_ok_p (rtx *operands)
1464 {
1465 /* If the destination operand is in memory, it needs to coincide
1466 with one of the source operands. After reload, it has to be
1467 the first source operand. */
1468 if (GET_CODE (operands[0]) == MEM)
1469 return rtx_equal_p (operands[0], operands[1])
1470 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1471
1472 return true;
1473 }
1474
1475 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1476 operand IMMOP to switch from SS to SI type instructions. */
1477
1478 void
1479 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1480 {
1481 int def = code == AND ? -1 : 0;
1482 HOST_WIDE_INT mask;
1483 int part;
1484
1485 gcc_assert (GET_CODE (*memop) == MEM);
1486 gcc_assert (!MEM_VOLATILE_P (*memop));
1487
1488 mask = s390_extract_part (*immop, QImode, def);
1489 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1490 gcc_assert (part >= 0);
1491
1492 *memop = adjust_address (*memop, QImode, part);
1493 *immop = gen_int_mode (mask, QImode);
1494 }
1495
1496
1497 /* How to allocate a 'struct machine_function'. */
1498
1499 static struct machine_function *
1500 s390_init_machine_status (void)
1501 {
1502 return ggc_alloc_cleared_machine_function ();
1503 }
1504
1505 static void
1506 s390_option_override (void)
1507 {
1508 /* Set up function hooks. */
1509 init_machine_status = s390_init_machine_status;
1510
1511 /* Architecture mode defaults according to ABI. */
1512 if (!(target_flags_explicit & MASK_ZARCH))
1513 {
1514 if (TARGET_64BIT)
1515 target_flags |= MASK_ZARCH;
1516 else
1517 target_flags &= ~MASK_ZARCH;
1518 }
1519
1520 /* Set the march default in case it hasn't been specified on
1521 cmdline. */
1522 if (s390_arch == PROCESSOR_max)
1523 {
1524 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1525 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1526 s390_arch_flags = processor_flags_table[(int)s390_arch];
1527 }
1528
1529 /* Determine processor to tune for. */
1530 if (s390_tune == PROCESSOR_max)
1531 {
1532 s390_tune = s390_arch;
1533 s390_tune_flags = s390_arch_flags;
1534 }
1535
1536 /* Sanity checks. */
1537 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1538 error ("z/Architecture mode not supported on %s", s390_arch_string);
1539 if (TARGET_64BIT && !TARGET_ZARCH)
1540 error ("64-bit ABI not supported in ESA/390 mode");
1541
1542 /* Use hardware DFP if available and not explicitly disabled by
1543 user. E.g. with -m31 -march=z10 -mzarch */
1544 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1545 target_flags |= MASK_HARD_DFP;
1546
1547 if (TARGET_HARD_DFP && !TARGET_DFP)
1548 {
1549 if (target_flags_explicit & MASK_HARD_DFP)
1550 {
1551 if (!TARGET_CPU_DFP)
1552 error ("hardware decimal floating point instructions"
1553 " not available on %s", s390_arch_string);
1554 if (!TARGET_ZARCH)
1555 error ("hardware decimal floating point instructions"
1556 " not available in ESA/390 mode");
1557 }
1558 else
1559 target_flags &= ~MASK_HARD_DFP;
1560 }
1561
1562 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1563 {
1564 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1565 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1566
1567 target_flags &= ~MASK_HARD_DFP;
1568 }
1569
1570 /* Set processor cost function. */
1571 switch (s390_tune)
1572 {
1573 case PROCESSOR_2084_Z990:
1574 s390_cost = &z990_cost;
1575 break;
1576 case PROCESSOR_2094_Z9_109:
1577 s390_cost = &z9_109_cost;
1578 break;
1579 case PROCESSOR_2097_Z10:
1580 s390_cost = &z10_cost;
1581 case PROCESSOR_2817_Z196:
1582 s390_cost = &z196_cost;
1583 break;
1584 default:
1585 s390_cost = &z900_cost;
1586 }
1587
1588 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1589 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1590 "in combination");
1591
1592 if (s390_stack_size)
1593 {
1594 if (s390_stack_guard >= s390_stack_size)
1595 error ("stack size must be greater than the stack guard value");
1596 else if (s390_stack_size > 1 << 16)
1597 error ("stack size must not be greater than 64k");
1598 }
1599 else if (s390_stack_guard)
1600 error ("-mstack-guard implies use of -mstack-size");
1601
1602 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1603 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1604 target_flags |= MASK_LONG_DOUBLE_128;
1605 #endif
1606
1607 if (s390_tune == PROCESSOR_2097_Z10
1608 || s390_tune == PROCESSOR_2817_Z196)
1609 {
1610 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1611 global_options.x_param_values,
1612 global_options_set.x_param_values);
1613 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1614 global_options.x_param_values,
1615 global_options_set.x_param_values);
1616 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1617 global_options.x_param_values,
1618 global_options_set.x_param_values);
1619 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1620 global_options.x_param_values,
1621 global_options_set.x_param_values);
1622 }
1623
1624 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1625 global_options.x_param_values,
1626 global_options_set.x_param_values);
1627 /* values for loop prefetching */
1628 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1629 global_options.x_param_values,
1630 global_options_set.x_param_values);
1631 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1632 global_options.x_param_values,
1633 global_options_set.x_param_values);
1634 /* s390 has more than 2 levels and the size is much larger. Since
1635 we are always running virtualized assume that we only get a small
1636 part of the caches above l1. */
1637 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1638 global_options.x_param_values,
1639 global_options_set.x_param_values);
1640 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1641 global_options.x_param_values,
1642 global_options_set.x_param_values);
1643 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1644 global_options.x_param_values,
1645 global_options_set.x_param_values);
1646
1647 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1648 requires the arch flags to be evaluated already. Since prefetching
1649 is beneficial on s390, we enable it if available. */
1650 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1651 flag_prefetch_loop_arrays = 1;
1652 }
1653
1654 /* Map for smallest class containing reg regno. */
1655
1656 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1657 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1658 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1659 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1660 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1661 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1662 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1663 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1664 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1665 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1666 ACCESS_REGS, ACCESS_REGS
1667 };
1668
1669 /* Return attribute type of insn. */
1670
1671 static enum attr_type
1672 s390_safe_attr_type (rtx insn)
1673 {
1674 if (recog_memoized (insn) >= 0)
1675 return get_attr_type (insn);
1676 else
1677 return TYPE_NONE;
1678 }
1679
1680 /* Return true if DISP is a valid short displacement. */
1681
1682 static bool
1683 s390_short_displacement (rtx disp)
1684 {
1685 /* No displacement is OK. */
1686 if (!disp)
1687 return true;
1688
1689 /* Without the long displacement facility we don't need to
1690 distingiush between long and short displacement. */
1691 if (!TARGET_LONG_DISPLACEMENT)
1692 return true;
1693
1694 /* Integer displacement in range. */
1695 if (GET_CODE (disp) == CONST_INT)
1696 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1697
1698 /* GOT offset is not OK, the GOT can be large. */
1699 if (GET_CODE (disp) == CONST
1700 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1701 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1702 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1703 return false;
1704
1705 /* All other symbolic constants are literal pool references,
1706 which are OK as the literal pool must be small. */
1707 if (GET_CODE (disp) == CONST)
1708 return true;
1709
1710 return false;
1711 }
1712
1713 /* Decompose a RTL expression ADDR for a memory address into
1714 its components, returned in OUT.
1715
1716 Returns false if ADDR is not a valid memory address, true
1717 otherwise. If OUT is NULL, don't return the components,
1718 but check for validity only.
1719
1720 Note: Only addresses in canonical form are recognized.
1721 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1722 canonical form so that they will be recognized. */
1723
1724 static int
1725 s390_decompose_address (rtx addr, struct s390_address *out)
1726 {
1727 HOST_WIDE_INT offset = 0;
1728 rtx base = NULL_RTX;
1729 rtx indx = NULL_RTX;
1730 rtx disp = NULL_RTX;
1731 rtx orig_disp;
1732 bool pointer = false;
1733 bool base_ptr = false;
1734 bool indx_ptr = false;
1735 bool literal_pool = false;
1736
1737 /* We may need to substitute the literal pool base register into the address
1738 below. However, at this point we do not know which register is going to
1739 be used as base, so we substitute the arg pointer register. This is going
1740 to be treated as holding a pointer below -- it shouldn't be used for any
1741 other purpose. */
1742 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1743
1744 /* Decompose address into base + index + displacement. */
1745
1746 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1747 base = addr;
1748
1749 else if (GET_CODE (addr) == PLUS)
1750 {
1751 rtx op0 = XEXP (addr, 0);
1752 rtx op1 = XEXP (addr, 1);
1753 enum rtx_code code0 = GET_CODE (op0);
1754 enum rtx_code code1 = GET_CODE (op1);
1755
1756 if (code0 == REG || code0 == UNSPEC)
1757 {
1758 if (code1 == REG || code1 == UNSPEC)
1759 {
1760 indx = op0; /* index + base */
1761 base = op1;
1762 }
1763
1764 else
1765 {
1766 base = op0; /* base + displacement */
1767 disp = op1;
1768 }
1769 }
1770
1771 else if (code0 == PLUS)
1772 {
1773 indx = XEXP (op0, 0); /* index + base + disp */
1774 base = XEXP (op0, 1);
1775 disp = op1;
1776 }
1777
1778 else
1779 {
1780 return false;
1781 }
1782 }
1783
1784 else
1785 disp = addr; /* displacement */
1786
1787 /* Extract integer part of displacement. */
1788 orig_disp = disp;
1789 if (disp)
1790 {
1791 if (GET_CODE (disp) == CONST_INT)
1792 {
1793 offset = INTVAL (disp);
1794 disp = NULL_RTX;
1795 }
1796 else if (GET_CODE (disp) == CONST
1797 && GET_CODE (XEXP (disp, 0)) == PLUS
1798 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1799 {
1800 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1801 disp = XEXP (XEXP (disp, 0), 0);
1802 }
1803 }
1804
1805 /* Strip off CONST here to avoid special case tests later. */
1806 if (disp && GET_CODE (disp) == CONST)
1807 disp = XEXP (disp, 0);
1808
1809 /* We can convert literal pool addresses to
1810 displacements by basing them off the base register. */
1811 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1812 {
1813 /* Either base or index must be free to hold the base register. */
1814 if (!base)
1815 base = fake_pool_base, literal_pool = true;
1816 else if (!indx)
1817 indx = fake_pool_base, literal_pool = true;
1818 else
1819 return false;
1820
1821 /* Mark up the displacement. */
1822 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1823 UNSPEC_LTREL_OFFSET);
1824 }
1825
1826 /* Validate base register. */
1827 if (base)
1828 {
1829 if (GET_CODE (base) == UNSPEC)
1830 switch (XINT (base, 1))
1831 {
1832 case UNSPEC_LTREF:
1833 if (!disp)
1834 disp = gen_rtx_UNSPEC (Pmode,
1835 gen_rtvec (1, XVECEXP (base, 0, 0)),
1836 UNSPEC_LTREL_OFFSET);
1837 else
1838 return false;
1839
1840 base = XVECEXP (base, 0, 1);
1841 break;
1842
1843 case UNSPEC_LTREL_BASE:
1844 if (XVECLEN (base, 0) == 1)
1845 base = fake_pool_base, literal_pool = true;
1846 else
1847 base = XVECEXP (base, 0, 1);
1848 break;
1849
1850 default:
1851 return false;
1852 }
1853
1854 if (!REG_P (base)
1855 || (GET_MODE (base) != SImode
1856 && GET_MODE (base) != Pmode))
1857 return false;
1858
1859 if (REGNO (base) == STACK_POINTER_REGNUM
1860 || REGNO (base) == FRAME_POINTER_REGNUM
1861 || ((reload_completed || reload_in_progress)
1862 && frame_pointer_needed
1863 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1864 || REGNO (base) == ARG_POINTER_REGNUM
1865 || (flag_pic
1866 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1867 pointer = base_ptr = true;
1868
1869 if ((reload_completed || reload_in_progress)
1870 && base == cfun->machine->base_reg)
1871 pointer = base_ptr = literal_pool = true;
1872 }
1873
1874 /* Validate index register. */
1875 if (indx)
1876 {
1877 if (GET_CODE (indx) == UNSPEC)
1878 switch (XINT (indx, 1))
1879 {
1880 case UNSPEC_LTREF:
1881 if (!disp)
1882 disp = gen_rtx_UNSPEC (Pmode,
1883 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1884 UNSPEC_LTREL_OFFSET);
1885 else
1886 return false;
1887
1888 indx = XVECEXP (indx, 0, 1);
1889 break;
1890
1891 case UNSPEC_LTREL_BASE:
1892 if (XVECLEN (indx, 0) == 1)
1893 indx = fake_pool_base, literal_pool = true;
1894 else
1895 indx = XVECEXP (indx, 0, 1);
1896 break;
1897
1898 default:
1899 return false;
1900 }
1901
1902 if (!REG_P (indx)
1903 || (GET_MODE (indx) != SImode
1904 && GET_MODE (indx) != Pmode))
1905 return false;
1906
1907 if (REGNO (indx) == STACK_POINTER_REGNUM
1908 || REGNO (indx) == FRAME_POINTER_REGNUM
1909 || ((reload_completed || reload_in_progress)
1910 && frame_pointer_needed
1911 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1912 || REGNO (indx) == ARG_POINTER_REGNUM
1913 || (flag_pic
1914 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1915 pointer = indx_ptr = true;
1916
1917 if ((reload_completed || reload_in_progress)
1918 && indx == cfun->machine->base_reg)
1919 pointer = indx_ptr = literal_pool = true;
1920 }
1921
1922 /* Prefer to use pointer as base, not index. */
1923 if (base && indx && !base_ptr
1924 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1925 {
1926 rtx tmp = base;
1927 base = indx;
1928 indx = tmp;
1929 }
1930
1931 /* Validate displacement. */
1932 if (!disp)
1933 {
1934 /* If virtual registers are involved, the displacement will change later
1935 anyway as the virtual registers get eliminated. This could make a
1936 valid displacement invalid, but it is more likely to make an invalid
1937 displacement valid, because we sometimes access the register save area
1938 via negative offsets to one of those registers.
1939 Thus we don't check the displacement for validity here. If after
1940 elimination the displacement turns out to be invalid after all,
1941 this is fixed up by reload in any case. */
1942 if (base != arg_pointer_rtx
1943 && indx != arg_pointer_rtx
1944 && base != return_address_pointer_rtx
1945 && indx != return_address_pointer_rtx
1946 && base != frame_pointer_rtx
1947 && indx != frame_pointer_rtx
1948 && base != virtual_stack_vars_rtx
1949 && indx != virtual_stack_vars_rtx)
1950 if (!DISP_IN_RANGE (offset))
1951 return false;
1952 }
1953 else
1954 {
1955 /* All the special cases are pointers. */
1956 pointer = true;
1957
1958 /* In the small-PIC case, the linker converts @GOT
1959 and @GOTNTPOFF offsets to possible displacements. */
1960 if (GET_CODE (disp) == UNSPEC
1961 && (XINT (disp, 1) == UNSPEC_GOT
1962 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1963 && flag_pic == 1)
1964 {
1965 ;
1966 }
1967
1968 /* Accept pool label offsets. */
1969 else if (GET_CODE (disp) == UNSPEC
1970 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1971 ;
1972
1973 /* Accept literal pool references. */
1974 else if (GET_CODE (disp) == UNSPEC
1975 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1976 {
1977 /* In case CSE pulled a non literal pool reference out of
1978 the pool we have to reject the address. This is
1979 especially important when loading the GOT pointer on non
1980 zarch CPUs. In this case the literal pool contains an lt
1981 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1982 will most likely exceed the displacement. */
1983 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
1984 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
1985 return false;
1986
1987 orig_disp = gen_rtx_CONST (Pmode, disp);
1988 if (offset)
1989 {
1990 /* If we have an offset, make sure it does not
1991 exceed the size of the constant pool entry. */
1992 rtx sym = XVECEXP (disp, 0, 0);
1993 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1994 return false;
1995
1996 orig_disp = plus_constant (Pmode, orig_disp, offset);
1997 }
1998 }
1999
2000 else
2001 return false;
2002 }
2003
2004 if (!base && !indx)
2005 pointer = true;
2006
2007 if (out)
2008 {
2009 out->base = base;
2010 out->indx = indx;
2011 out->disp = orig_disp;
2012 out->pointer = pointer;
2013 out->literal_pool = literal_pool;
2014 }
2015
2016 return true;
2017 }
2018
2019 /* Decompose a RTL expression OP for a shift count into its components,
2020 and return the base register in BASE and the offset in OFFSET.
2021
2022 Return true if OP is a valid shift count, false if not. */
2023
2024 bool
2025 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2026 {
2027 HOST_WIDE_INT off = 0;
2028
2029 /* We can have an integer constant, an address register,
2030 or a sum of the two. */
2031 if (GET_CODE (op) == CONST_INT)
2032 {
2033 off = INTVAL (op);
2034 op = NULL_RTX;
2035 }
2036 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2037 {
2038 off = INTVAL (XEXP (op, 1));
2039 op = XEXP (op, 0);
2040 }
2041 while (op && GET_CODE (op) == SUBREG)
2042 op = SUBREG_REG (op);
2043
2044 if (op && GET_CODE (op) != REG)
2045 return false;
2046
2047 if (offset)
2048 *offset = off;
2049 if (base)
2050 *base = op;
2051
2052 return true;
2053 }
2054
2055
2056 /* Return true if CODE is a valid address without index. */
2057
2058 bool
2059 s390_legitimate_address_without_index_p (rtx op)
2060 {
2061 struct s390_address addr;
2062
2063 if (!s390_decompose_address (XEXP (op, 0), &addr))
2064 return false;
2065 if (addr.indx)
2066 return false;
2067
2068 return true;
2069 }
2070
2071
2072 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2073 and return these parts in SYMREF and ADDEND. You can pass NULL in
2074 SYMREF and/or ADDEND if you are not interested in these values.
2075 Literal pool references are *not* considered symbol references. */
2076
2077 static bool
2078 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2079 {
2080 HOST_WIDE_INT tmpaddend = 0;
2081
2082 if (GET_CODE (addr) == CONST)
2083 addr = XEXP (addr, 0);
2084
2085 if (GET_CODE (addr) == PLUS)
2086 {
2087 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2088 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2089 && CONST_INT_P (XEXP (addr, 1)))
2090 {
2091 tmpaddend = INTVAL (XEXP (addr, 1));
2092 addr = XEXP (addr, 0);
2093 }
2094 else
2095 return false;
2096 }
2097 else
2098 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2099 return false;
2100
2101 if (symref)
2102 *symref = addr;
2103 if (addend)
2104 *addend = tmpaddend;
2105
2106 return true;
2107 }
2108
2109
2110 /* Return true if the address in OP is valid for constraint letter C
2111 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2112 pool MEMs should be accepted. Only the Q, R, S, T constraint
2113 letters are allowed for C. */
2114
2115 static int
2116 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2117 {
2118 struct s390_address addr;
2119 bool decomposed = false;
2120
2121 /* This check makes sure that no symbolic address (except literal
2122 pool references) are accepted by the R or T constraints. */
2123 if (s390_symref_operand_p (op, NULL, NULL))
2124 return 0;
2125
2126 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2127 if (!lit_pool_ok)
2128 {
2129 if (!s390_decompose_address (op, &addr))
2130 return 0;
2131 if (addr.literal_pool)
2132 return 0;
2133 decomposed = true;
2134 }
2135
2136 switch (c)
2137 {
2138 case 'Q': /* no index short displacement */
2139 if (!decomposed && !s390_decompose_address (op, &addr))
2140 return 0;
2141 if (addr.indx)
2142 return 0;
2143 if (!s390_short_displacement (addr.disp))
2144 return 0;
2145 break;
2146
2147 case 'R': /* with index short displacement */
2148 if (TARGET_LONG_DISPLACEMENT)
2149 {
2150 if (!decomposed && !s390_decompose_address (op, &addr))
2151 return 0;
2152 if (!s390_short_displacement (addr.disp))
2153 return 0;
2154 }
2155 /* Any invalid address here will be fixed up by reload,
2156 so accept it for the most generic constraint. */
2157 break;
2158
2159 case 'S': /* no index long displacement */
2160 if (!TARGET_LONG_DISPLACEMENT)
2161 return 0;
2162 if (!decomposed && !s390_decompose_address (op, &addr))
2163 return 0;
2164 if (addr.indx)
2165 return 0;
2166 if (s390_short_displacement (addr.disp))
2167 return 0;
2168 break;
2169
2170 case 'T': /* with index long displacement */
2171 if (!TARGET_LONG_DISPLACEMENT)
2172 return 0;
2173 /* Any invalid address here will be fixed up by reload,
2174 so accept it for the most generic constraint. */
2175 if ((decomposed || s390_decompose_address (op, &addr))
2176 && s390_short_displacement (addr.disp))
2177 return 0;
2178 break;
2179 default:
2180 return 0;
2181 }
2182 return 1;
2183 }
2184
2185
2186 /* Evaluates constraint strings described by the regular expression
2187 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2188 the constraint given in STR, or 0 else. */
2189
2190 int
2191 s390_mem_constraint (const char *str, rtx op)
2192 {
2193 char c = str[0];
2194
2195 switch (c)
2196 {
2197 case 'A':
2198 /* Check for offsettable variants of memory constraints. */
2199 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2200 return 0;
2201 if ((reload_completed || reload_in_progress)
2202 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2203 return 0;
2204 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2205 case 'B':
2206 /* Check for non-literal-pool variants of memory constraints. */
2207 if (!MEM_P (op))
2208 return 0;
2209 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2210 case 'Q':
2211 case 'R':
2212 case 'S':
2213 case 'T':
2214 if (GET_CODE (op) != MEM)
2215 return 0;
2216 return s390_check_qrst_address (c, XEXP (op, 0), true);
2217 case 'U':
2218 return (s390_check_qrst_address ('Q', op, true)
2219 || s390_check_qrst_address ('R', op, true));
2220 case 'W':
2221 return (s390_check_qrst_address ('S', op, true)
2222 || s390_check_qrst_address ('T', op, true));
2223 case 'Y':
2224 /* Simply check for the basic form of a shift count. Reload will
2225 take care of making sure we have a proper base register. */
2226 if (!s390_decompose_shift_count (op, NULL, NULL))
2227 return 0;
2228 break;
2229 case 'Z':
2230 return s390_check_qrst_address (str[1], op, true);
2231 default:
2232 return 0;
2233 }
2234 return 1;
2235 }
2236
2237
2238 /* Evaluates constraint strings starting with letter O. Input
2239 parameter C is the second letter following the "O" in the constraint
2240 string. Returns 1 if VALUE meets the respective constraint and 0
2241 otherwise. */
2242
2243 int
2244 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2245 {
2246 if (!TARGET_EXTIMM)
2247 return 0;
2248
2249 switch (c)
2250 {
2251 case 's':
2252 return trunc_int_for_mode (value, SImode) == value;
2253
2254 case 'p':
2255 return value == 0
2256 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2257
2258 case 'n':
2259 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2260
2261 default:
2262 gcc_unreachable ();
2263 }
2264 }
2265
2266
2267 /* Evaluates constraint strings starting with letter N. Parameter STR
2268 contains the letters following letter "N" in the constraint string.
2269 Returns true if VALUE matches the constraint. */
2270
2271 int
2272 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2273 {
2274 enum machine_mode mode, part_mode;
2275 int def;
2276 int part, part_goal;
2277
2278
2279 if (str[0] == 'x')
2280 part_goal = -1;
2281 else
2282 part_goal = str[0] - '0';
2283
2284 switch (str[1])
2285 {
2286 case 'Q':
2287 part_mode = QImode;
2288 break;
2289 case 'H':
2290 part_mode = HImode;
2291 break;
2292 case 'S':
2293 part_mode = SImode;
2294 break;
2295 default:
2296 return 0;
2297 }
2298
2299 switch (str[2])
2300 {
2301 case 'H':
2302 mode = HImode;
2303 break;
2304 case 'S':
2305 mode = SImode;
2306 break;
2307 case 'D':
2308 mode = DImode;
2309 break;
2310 default:
2311 return 0;
2312 }
2313
2314 switch (str[3])
2315 {
2316 case '0':
2317 def = 0;
2318 break;
2319 case 'F':
2320 def = -1;
2321 break;
2322 default:
2323 return 0;
2324 }
2325
2326 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2327 return 0;
2328
2329 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2330 if (part < 0)
2331 return 0;
2332 if (part_goal != -1 && part_goal != part)
2333 return 0;
2334
2335 return 1;
2336 }
2337
2338
2339 /* Returns true if the input parameter VALUE is a float zero. */
2340
2341 int
2342 s390_float_const_zero_p (rtx value)
2343 {
2344 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2345 && value == CONST0_RTX (GET_MODE (value)));
2346 }
2347
2348 /* Implement TARGET_REGISTER_MOVE_COST. */
2349
2350 static int
2351 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2352 reg_class_t from, reg_class_t to)
2353 {
2354 /* On s390, copy between fprs and gprs is expensive. */
2355 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2356 && reg_classes_intersect_p (to, FP_REGS))
2357 || (reg_classes_intersect_p (from, FP_REGS)
2358 && reg_classes_intersect_p (to, GENERAL_REGS)))
2359 return 10;
2360
2361 return 1;
2362 }
2363
2364 /* Implement TARGET_MEMORY_MOVE_COST. */
2365
2366 static int
2367 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2368 reg_class_t rclass ATTRIBUTE_UNUSED,
2369 bool in ATTRIBUTE_UNUSED)
2370 {
2371 return 1;
2372 }
2373
2374 /* Compute a (partial) cost for rtx X. Return true if the complete
2375 cost has been computed, and false if subexpressions should be
2376 scanned. In either case, *TOTAL contains the cost result.
2377 CODE contains GET_CODE (x), OUTER_CODE contains the code
2378 of the superexpression of x. */
2379
2380 static bool
2381 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2382 int *total, bool speed ATTRIBUTE_UNUSED)
2383 {
2384 switch (code)
2385 {
2386 case CONST:
2387 case CONST_INT:
2388 case LABEL_REF:
2389 case SYMBOL_REF:
2390 case CONST_DOUBLE:
2391 case MEM:
2392 *total = 0;
2393 return true;
2394
2395 case ASHIFT:
2396 case ASHIFTRT:
2397 case LSHIFTRT:
2398 case ROTATE:
2399 case ROTATERT:
2400 case AND:
2401 case IOR:
2402 case XOR:
2403 case NEG:
2404 case NOT:
2405 *total = COSTS_N_INSNS (1);
2406 return false;
2407
2408 case PLUS:
2409 case MINUS:
2410 *total = COSTS_N_INSNS (1);
2411 return false;
2412
2413 case MULT:
2414 switch (GET_MODE (x))
2415 {
2416 case SImode:
2417 {
2418 rtx left = XEXP (x, 0);
2419 rtx right = XEXP (x, 1);
2420 if (GET_CODE (right) == CONST_INT
2421 && CONST_OK_FOR_K (INTVAL (right)))
2422 *total = s390_cost->mhi;
2423 else if (GET_CODE (left) == SIGN_EXTEND)
2424 *total = s390_cost->mh;
2425 else
2426 *total = s390_cost->ms; /* msr, ms, msy */
2427 break;
2428 }
2429 case DImode:
2430 {
2431 rtx left = XEXP (x, 0);
2432 rtx right = XEXP (x, 1);
2433 if (TARGET_ZARCH)
2434 {
2435 if (GET_CODE (right) == CONST_INT
2436 && CONST_OK_FOR_K (INTVAL (right)))
2437 *total = s390_cost->mghi;
2438 else if (GET_CODE (left) == SIGN_EXTEND)
2439 *total = s390_cost->msgf;
2440 else
2441 *total = s390_cost->msg; /* msgr, msg */
2442 }
2443 else /* TARGET_31BIT */
2444 {
2445 if (GET_CODE (left) == SIGN_EXTEND
2446 && GET_CODE (right) == SIGN_EXTEND)
2447 /* mulsidi case: mr, m */
2448 *total = s390_cost->m;
2449 else if (GET_CODE (left) == ZERO_EXTEND
2450 && GET_CODE (right) == ZERO_EXTEND
2451 && TARGET_CPU_ZARCH)
2452 /* umulsidi case: ml, mlr */
2453 *total = s390_cost->ml;
2454 else
2455 /* Complex calculation is required. */
2456 *total = COSTS_N_INSNS (40);
2457 }
2458 break;
2459 }
2460 case SFmode:
2461 case DFmode:
2462 *total = s390_cost->mult_df;
2463 break;
2464 case TFmode:
2465 *total = s390_cost->mxbr;
2466 break;
2467 default:
2468 return false;
2469 }
2470 return false;
2471
2472 case FMA:
2473 switch (GET_MODE (x))
2474 {
2475 case DFmode:
2476 *total = s390_cost->madbr;
2477 break;
2478 case SFmode:
2479 *total = s390_cost->maebr;
2480 break;
2481 default:
2482 return false;
2483 }
2484 /* Negate in the third argument is free: FMSUB. */
2485 if (GET_CODE (XEXP (x, 2)) == NEG)
2486 {
2487 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2488 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2489 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2490 return true;
2491 }
2492 return false;
2493
2494 case UDIV:
2495 case UMOD:
2496 if (GET_MODE (x) == TImode) /* 128 bit division */
2497 *total = s390_cost->dlgr;
2498 else if (GET_MODE (x) == DImode)
2499 {
2500 rtx right = XEXP (x, 1);
2501 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2502 *total = s390_cost->dlr;
2503 else /* 64 by 64 bit division */
2504 *total = s390_cost->dlgr;
2505 }
2506 else if (GET_MODE (x) == SImode) /* 32 bit division */
2507 *total = s390_cost->dlr;
2508 return false;
2509
2510 case DIV:
2511 case MOD:
2512 if (GET_MODE (x) == DImode)
2513 {
2514 rtx right = XEXP (x, 1);
2515 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2516 if (TARGET_ZARCH)
2517 *total = s390_cost->dsgfr;
2518 else
2519 *total = s390_cost->dr;
2520 else /* 64 by 64 bit division */
2521 *total = s390_cost->dsgr;
2522 }
2523 else if (GET_MODE (x) == SImode) /* 32 bit division */
2524 *total = s390_cost->dlr;
2525 else if (GET_MODE (x) == SFmode)
2526 {
2527 *total = s390_cost->debr;
2528 }
2529 else if (GET_MODE (x) == DFmode)
2530 {
2531 *total = s390_cost->ddbr;
2532 }
2533 else if (GET_MODE (x) == TFmode)
2534 {
2535 *total = s390_cost->dxbr;
2536 }
2537 return false;
2538
2539 case SQRT:
2540 if (GET_MODE (x) == SFmode)
2541 *total = s390_cost->sqebr;
2542 else if (GET_MODE (x) == DFmode)
2543 *total = s390_cost->sqdbr;
2544 else /* TFmode */
2545 *total = s390_cost->sqxbr;
2546 return false;
2547
2548 case SIGN_EXTEND:
2549 case ZERO_EXTEND:
2550 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2551 || outer_code == PLUS || outer_code == MINUS
2552 || outer_code == COMPARE)
2553 *total = 0;
2554 return false;
2555
2556 case COMPARE:
2557 *total = COSTS_N_INSNS (1);
2558 if (GET_CODE (XEXP (x, 0)) == AND
2559 && GET_CODE (XEXP (x, 1)) == CONST_INT
2560 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2561 {
2562 rtx op0 = XEXP (XEXP (x, 0), 0);
2563 rtx op1 = XEXP (XEXP (x, 0), 1);
2564 rtx op2 = XEXP (x, 1);
2565
2566 if (memory_operand (op0, GET_MODE (op0))
2567 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2568 return true;
2569 if (register_operand (op0, GET_MODE (op0))
2570 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2571 return true;
2572 }
2573 return false;
2574
2575 default:
2576 return false;
2577 }
2578 }
2579
2580 /* Return the cost of an address rtx ADDR. */
2581
2582 static int
2583 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2584 {
2585 struct s390_address ad;
2586 if (!s390_decompose_address (addr, &ad))
2587 return 1000;
2588
2589 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2590 }
2591
2592 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2593 otherwise return 0. */
2594
2595 int
2596 tls_symbolic_operand (rtx op)
2597 {
2598 if (GET_CODE (op) != SYMBOL_REF)
2599 return 0;
2600 return SYMBOL_REF_TLS_MODEL (op);
2601 }
2602 \f
2603 /* Split DImode access register reference REG (on 64-bit) into its constituent
2604 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2605 gen_highpart cannot be used as they assume all registers are word-sized,
2606 while our access registers have only half that size. */
2607
2608 void
2609 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2610 {
2611 gcc_assert (TARGET_64BIT);
2612 gcc_assert (ACCESS_REG_P (reg));
2613 gcc_assert (GET_MODE (reg) == DImode);
2614 gcc_assert (!(REGNO (reg) & 1));
2615
2616 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2617 *hi = gen_rtx_REG (SImode, REGNO (reg));
2618 }
2619
2620 /* Return true if OP contains a symbol reference */
2621
2622 bool
2623 symbolic_reference_mentioned_p (rtx op)
2624 {
2625 const char *fmt;
2626 int i;
2627
2628 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2629 return 1;
2630
2631 fmt = GET_RTX_FORMAT (GET_CODE (op));
2632 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2633 {
2634 if (fmt[i] == 'E')
2635 {
2636 int j;
2637
2638 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2639 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2640 return 1;
2641 }
2642
2643 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2644 return 1;
2645 }
2646
2647 return 0;
2648 }
2649
2650 /* Return true if OP contains a reference to a thread-local symbol. */
2651
2652 bool
2653 tls_symbolic_reference_mentioned_p (rtx op)
2654 {
2655 const char *fmt;
2656 int i;
2657
2658 if (GET_CODE (op) == SYMBOL_REF)
2659 return tls_symbolic_operand (op);
2660
2661 fmt = GET_RTX_FORMAT (GET_CODE (op));
2662 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2663 {
2664 if (fmt[i] == 'E')
2665 {
2666 int j;
2667
2668 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2669 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2670 return true;
2671 }
2672
2673 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2674 return true;
2675 }
2676
2677 return false;
2678 }
2679
2680
2681 /* Return true if OP is a legitimate general operand when
2682 generating PIC code. It is given that flag_pic is on
2683 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2684
2685 int
2686 legitimate_pic_operand_p (rtx op)
2687 {
2688 /* Accept all non-symbolic constants. */
2689 if (!SYMBOLIC_CONST (op))
2690 return 1;
2691
2692 /* Reject everything else; must be handled
2693 via emit_symbolic_move. */
2694 return 0;
2695 }
2696
2697 /* Returns true if the constant value OP is a legitimate general operand.
2698 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2699
2700 static bool
2701 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2702 {
2703 /* Accept all non-symbolic constants. */
2704 if (!SYMBOLIC_CONST (op))
2705 return 1;
2706
2707 /* Accept immediate LARL operands. */
2708 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2709 return 1;
2710
2711 /* Thread-local symbols are never legal constants. This is
2712 so that emit_call knows that computing such addresses
2713 might require a function call. */
2714 if (TLS_SYMBOLIC_CONST (op))
2715 return 0;
2716
2717 /* In the PIC case, symbolic constants must *not* be
2718 forced into the literal pool. We accept them here,
2719 so that they will be handled by emit_symbolic_move. */
2720 if (flag_pic)
2721 return 1;
2722
2723 /* All remaining non-PIC symbolic constants are
2724 forced into the literal pool. */
2725 return 0;
2726 }
2727
2728 /* Determine if it's legal to put X into the constant pool. This
2729 is not possible if X contains the address of a symbol that is
2730 not constant (TLS) or not known at final link time (PIC). */
2731
2732 static bool
2733 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2734 {
2735 switch (GET_CODE (x))
2736 {
2737 case CONST_INT:
2738 case CONST_DOUBLE:
2739 /* Accept all non-symbolic constants. */
2740 return false;
2741
2742 case LABEL_REF:
2743 /* Labels are OK iff we are non-PIC. */
2744 return flag_pic != 0;
2745
2746 case SYMBOL_REF:
2747 /* 'Naked' TLS symbol references are never OK,
2748 non-TLS symbols are OK iff we are non-PIC. */
2749 if (tls_symbolic_operand (x))
2750 return true;
2751 else
2752 return flag_pic != 0;
2753
2754 case CONST:
2755 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2756 case PLUS:
2757 case MINUS:
2758 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2759 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2760
2761 case UNSPEC:
2762 switch (XINT (x, 1))
2763 {
2764 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2765 case UNSPEC_LTREL_OFFSET:
2766 case UNSPEC_GOT:
2767 case UNSPEC_GOTOFF:
2768 case UNSPEC_PLTOFF:
2769 case UNSPEC_TLSGD:
2770 case UNSPEC_TLSLDM:
2771 case UNSPEC_NTPOFF:
2772 case UNSPEC_DTPOFF:
2773 case UNSPEC_GOTNTPOFF:
2774 case UNSPEC_INDNTPOFF:
2775 return false;
2776
2777 /* If the literal pool shares the code section, be put
2778 execute template placeholders into the pool as well. */
2779 case UNSPEC_INSN:
2780 return TARGET_CPU_ZARCH;
2781
2782 default:
2783 return true;
2784 }
2785 break;
2786
2787 default:
2788 gcc_unreachable ();
2789 }
2790 }
2791
2792 /* Returns true if the constant value OP is a legitimate general
2793 operand during and after reload. The difference to
2794 legitimate_constant_p is that this function will not accept
2795 a constant that would need to be forced to the literal pool
2796 before it can be used as operand.
2797 This function accepts all constants which can be loaded directly
2798 into a GPR. */
2799
2800 bool
2801 legitimate_reload_constant_p (rtx op)
2802 {
2803 /* Accept la(y) operands. */
2804 if (GET_CODE (op) == CONST_INT
2805 && DISP_IN_RANGE (INTVAL (op)))
2806 return true;
2807
2808 /* Accept l(g)hi/l(g)fi operands. */
2809 if (GET_CODE (op) == CONST_INT
2810 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2811 return true;
2812
2813 /* Accept lliXX operands. */
2814 if (TARGET_ZARCH
2815 && GET_CODE (op) == CONST_INT
2816 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2817 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2818 return true;
2819
2820 if (TARGET_EXTIMM
2821 && GET_CODE (op) == CONST_INT
2822 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2823 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2824 return true;
2825
2826 /* Accept larl operands. */
2827 if (TARGET_CPU_ZARCH
2828 && larl_operand (op, VOIDmode))
2829 return true;
2830
2831 /* Accept floating-point zero operands that fit into a single GPR. */
2832 if (GET_CODE (op) == CONST_DOUBLE
2833 && s390_float_const_zero_p (op)
2834 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2835 return true;
2836
2837 /* Accept double-word operands that can be split. */
2838 if (GET_CODE (op) == CONST_INT
2839 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2840 {
2841 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2842 rtx hi = operand_subword (op, 0, 0, dword_mode);
2843 rtx lo = operand_subword (op, 1, 0, dword_mode);
2844 return legitimate_reload_constant_p (hi)
2845 && legitimate_reload_constant_p (lo);
2846 }
2847
2848 /* Everything else cannot be handled without reload. */
2849 return false;
2850 }
2851
2852 /* Returns true if the constant value OP is a legitimate fp operand
2853 during and after reload.
2854 This function accepts all constants which can be loaded directly
2855 into an FPR. */
2856
2857 static bool
2858 legitimate_reload_fp_constant_p (rtx op)
2859 {
2860 /* Accept floating-point zero operands if the load zero instruction
2861 can be used. */
2862 if (TARGET_Z196
2863 && GET_CODE (op) == CONST_DOUBLE
2864 && s390_float_const_zero_p (op))
2865 return true;
2866
2867 return false;
2868 }
2869
2870 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2871 return the class of reg to actually use. */
2872
2873 static reg_class_t
2874 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2875 {
2876 switch (GET_CODE (op))
2877 {
2878 /* Constants we cannot reload into general registers
2879 must be forced into the literal pool. */
2880 case CONST_DOUBLE:
2881 case CONST_INT:
2882 if (reg_class_subset_p (GENERAL_REGS, rclass)
2883 && legitimate_reload_constant_p (op))
2884 return GENERAL_REGS;
2885 else if (reg_class_subset_p (ADDR_REGS, rclass)
2886 && legitimate_reload_constant_p (op))
2887 return ADDR_REGS;
2888 else if (reg_class_subset_p (FP_REGS, rclass)
2889 && legitimate_reload_fp_constant_p (op))
2890 return FP_REGS;
2891 return NO_REGS;
2892
2893 /* If a symbolic constant or a PLUS is reloaded,
2894 it is most likely being used as an address, so
2895 prefer ADDR_REGS. If 'class' is not a superset
2896 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2897 case LABEL_REF:
2898 case SYMBOL_REF:
2899 case CONST:
2900 if (!legitimate_reload_constant_p (op))
2901 return NO_REGS;
2902 /* fallthrough */
2903 case PLUS:
2904 /* load address will be used. */
2905 if (reg_class_subset_p (ADDR_REGS, rclass))
2906 return ADDR_REGS;
2907 else
2908 return NO_REGS;
2909
2910 default:
2911 break;
2912 }
2913
2914 return rclass;
2915 }
2916
2917 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2918 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2919 aligned. */
2920
2921 bool
2922 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2923 {
2924 HOST_WIDE_INT addend;
2925 rtx symref;
2926
2927 if (!s390_symref_operand_p (addr, &symref, &addend))
2928 return false;
2929
2930 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2931 && !(addend & (alignment - 1)));
2932 }
2933
2934 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2935 operand SCRATCH is used to reload the even part of the address and
2936 adding one. */
2937
2938 void
2939 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2940 {
2941 HOST_WIDE_INT addend;
2942 rtx symref;
2943
2944 if (!s390_symref_operand_p (addr, &symref, &addend))
2945 gcc_unreachable ();
2946
2947 if (!(addend & 1))
2948 /* Easy case. The addend is even so larl will do fine. */
2949 emit_move_insn (reg, addr);
2950 else
2951 {
2952 /* We can leave the scratch register untouched if the target
2953 register is a valid base register. */
2954 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2955 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2956 scratch = reg;
2957
2958 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2959 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2960
2961 if (addend != 1)
2962 emit_move_insn (scratch,
2963 gen_rtx_CONST (Pmode,
2964 gen_rtx_PLUS (Pmode, symref,
2965 GEN_INT (addend - 1))));
2966 else
2967 emit_move_insn (scratch, symref);
2968
2969 /* Increment the address using la in order to avoid clobbering cc. */
2970 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2971 }
2972 }
2973
2974 /* Generate what is necessary to move between REG and MEM using
2975 SCRATCH. The direction is given by TOMEM. */
2976
2977 void
2978 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2979 {
2980 /* Reload might have pulled a constant out of the literal pool.
2981 Force it back in. */
2982 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2983 || GET_CODE (mem) == CONST)
2984 mem = force_const_mem (GET_MODE (reg), mem);
2985
2986 gcc_assert (MEM_P (mem));
2987
2988 /* For a load from memory we can leave the scratch register
2989 untouched if the target register is a valid base register. */
2990 if (!tomem
2991 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2992 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2993 && GET_MODE (reg) == GET_MODE (scratch))
2994 scratch = reg;
2995
2996 /* Load address into scratch register. Since we can't have a
2997 secondary reload for a secondary reload we have to cover the case
2998 where larl would need a secondary reload here as well. */
2999 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3000
3001 /* Now we can use a standard load/store to do the move. */
3002 if (tomem)
3003 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3004 else
3005 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3006 }
3007
3008 /* Inform reload about cases where moving X with a mode MODE to a register in
3009 RCLASS requires an extra scratch or immediate register. Return the class
3010 needed for the immediate register. */
3011
3012 static reg_class_t
3013 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3014 enum machine_mode mode, secondary_reload_info *sri)
3015 {
3016 enum reg_class rclass = (enum reg_class) rclass_i;
3017
3018 /* Intermediate register needed. */
3019 if (reg_classes_intersect_p (CC_REGS, rclass))
3020 return GENERAL_REGS;
3021
3022 if (TARGET_Z10)
3023 {
3024 HOST_WIDE_INT offset;
3025 rtx symref;
3026
3027 /* On z10 several optimizer steps may generate larl operands with
3028 an odd addend. */
3029 if (in_p
3030 && s390_symref_operand_p (x, &symref, &offset)
3031 && mode == Pmode
3032 && !SYMBOL_REF_ALIGN1_P (symref)
3033 && (offset & 1) == 1)
3034 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3035 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3036
3037 /* On z10 we need a scratch register when moving QI, TI or floating
3038 point mode values from or to a memory location with a SYMBOL_REF
3039 or if the symref addend of a SI or DI move is not aligned to the
3040 width of the access. */
3041 if (MEM_P (x)
3042 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3043 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3044 || (!TARGET_ZARCH && mode == DImode)
3045 || ((mode == HImode || mode == SImode || mode == DImode)
3046 && (!s390_check_symref_alignment (XEXP (x, 0),
3047 GET_MODE_SIZE (mode))))))
3048 {
3049 #define __SECONDARY_RELOAD_CASE(M,m) \
3050 case M##mode: \
3051 if (TARGET_64BIT) \
3052 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3053 CODE_FOR_reload##m##di_tomem_z10; \
3054 else \
3055 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3056 CODE_FOR_reload##m##si_tomem_z10; \
3057 break;
3058
3059 switch (GET_MODE (x))
3060 {
3061 __SECONDARY_RELOAD_CASE (QI, qi);
3062 __SECONDARY_RELOAD_CASE (HI, hi);
3063 __SECONDARY_RELOAD_CASE (SI, si);
3064 __SECONDARY_RELOAD_CASE (DI, di);
3065 __SECONDARY_RELOAD_CASE (TI, ti);
3066 __SECONDARY_RELOAD_CASE (SF, sf);
3067 __SECONDARY_RELOAD_CASE (DF, df);
3068 __SECONDARY_RELOAD_CASE (TF, tf);
3069 __SECONDARY_RELOAD_CASE (SD, sd);
3070 __SECONDARY_RELOAD_CASE (DD, dd);
3071 __SECONDARY_RELOAD_CASE (TD, td);
3072
3073 default:
3074 gcc_unreachable ();
3075 }
3076 #undef __SECONDARY_RELOAD_CASE
3077 }
3078 }
3079
3080 /* We need a scratch register when loading a PLUS expression which
3081 is not a legitimate operand of the LOAD ADDRESS instruction. */
3082 if (in_p && s390_plus_operand (x, mode))
3083 sri->icode = (TARGET_64BIT ?
3084 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3085
3086 /* Performing a multiword move from or to memory we have to make sure the
3087 second chunk in memory is addressable without causing a displacement
3088 overflow. If that would be the case we calculate the address in
3089 a scratch register. */
3090 if (MEM_P (x)
3091 && GET_CODE (XEXP (x, 0)) == PLUS
3092 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3093 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3094 + GET_MODE_SIZE (mode) - 1))
3095 {
3096 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3097 in a s_operand address since we may fallback to lm/stm. So we only
3098 have to care about overflows in the b+i+d case. */
3099 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3100 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3101 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3102 /* For FP_REGS no lm/stm is available so this check is triggered
3103 for displacement overflows in b+i+d and b+d like addresses. */
3104 || (reg_classes_intersect_p (FP_REGS, rclass)
3105 && s390_class_max_nregs (FP_REGS, mode) > 1))
3106 {
3107 if (in_p)
3108 sri->icode = (TARGET_64BIT ?
3109 CODE_FOR_reloaddi_nonoffmem_in :
3110 CODE_FOR_reloadsi_nonoffmem_in);
3111 else
3112 sri->icode = (TARGET_64BIT ?
3113 CODE_FOR_reloaddi_nonoffmem_out :
3114 CODE_FOR_reloadsi_nonoffmem_out);
3115 }
3116 }
3117
3118 /* A scratch address register is needed when a symbolic constant is
3119 copied to r0 compiling with -fPIC. In other cases the target
3120 register might be used as temporary (see legitimize_pic_address). */
3121 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3122 sri->icode = (TARGET_64BIT ?
3123 CODE_FOR_reloaddi_PIC_addr :
3124 CODE_FOR_reloadsi_PIC_addr);
3125
3126 /* Either scratch or no register needed. */
3127 return NO_REGS;
3128 }
3129
3130 /* Generate code to load SRC, which is PLUS that is not a
3131 legitimate operand for the LA instruction, into TARGET.
3132 SCRATCH may be used as scratch register. */
3133
3134 void
3135 s390_expand_plus_operand (rtx target, rtx src,
3136 rtx scratch)
3137 {
3138 rtx sum1, sum2;
3139 struct s390_address ad;
3140
3141 /* src must be a PLUS; get its two operands. */
3142 gcc_assert (GET_CODE (src) == PLUS);
3143 gcc_assert (GET_MODE (src) == Pmode);
3144
3145 /* Check if any of the two operands is already scheduled
3146 for replacement by reload. This can happen e.g. when
3147 float registers occur in an address. */
3148 sum1 = find_replacement (&XEXP (src, 0));
3149 sum2 = find_replacement (&XEXP (src, 1));
3150 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3151
3152 /* If the address is already strictly valid, there's nothing to do. */
3153 if (!s390_decompose_address (src, &ad)
3154 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3155 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3156 {
3157 /* Otherwise, one of the operands cannot be an address register;
3158 we reload its value into the scratch register. */
3159 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3160 {
3161 emit_move_insn (scratch, sum1);
3162 sum1 = scratch;
3163 }
3164 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3165 {
3166 emit_move_insn (scratch, sum2);
3167 sum2 = scratch;
3168 }
3169
3170 /* According to the way these invalid addresses are generated
3171 in reload.c, it should never happen (at least on s390) that
3172 *neither* of the PLUS components, after find_replacements
3173 was applied, is an address register. */
3174 if (sum1 == scratch && sum2 == scratch)
3175 {
3176 debug_rtx (src);
3177 gcc_unreachable ();
3178 }
3179
3180 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3181 }
3182
3183 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3184 is only ever performed on addresses, so we can mark the
3185 sum as legitimate for LA in any case. */
3186 s390_load_address (target, src);
3187 }
3188
3189
3190 /* Return true if ADDR is a valid memory address.
3191 STRICT specifies whether strict register checking applies. */
3192
3193 static bool
3194 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3195 {
3196 struct s390_address ad;
3197
3198 if (TARGET_Z10
3199 && larl_operand (addr, VOIDmode)
3200 && (mode == VOIDmode
3201 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3202 return true;
3203
3204 if (!s390_decompose_address (addr, &ad))
3205 return false;
3206
3207 if (strict)
3208 {
3209 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3210 return false;
3211
3212 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3213 return false;
3214 }
3215 else
3216 {
3217 if (ad.base
3218 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3219 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3220 return false;
3221
3222 if (ad.indx
3223 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3224 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3225 return false;
3226 }
3227 return true;
3228 }
3229
3230 /* Return true if OP is a valid operand for the LA instruction.
3231 In 31-bit, we need to prove that the result is used as an
3232 address, as LA performs only a 31-bit addition. */
3233
3234 bool
3235 legitimate_la_operand_p (rtx op)
3236 {
3237 struct s390_address addr;
3238 if (!s390_decompose_address (op, &addr))
3239 return false;
3240
3241 return (TARGET_64BIT || addr.pointer);
3242 }
3243
3244 /* Return true if it is valid *and* preferable to use LA to
3245 compute the sum of OP1 and OP2. */
3246
3247 bool
3248 preferred_la_operand_p (rtx op1, rtx op2)
3249 {
3250 struct s390_address addr;
3251
3252 if (op2 != const0_rtx)
3253 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3254
3255 if (!s390_decompose_address (op1, &addr))
3256 return false;
3257 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3258 return false;
3259 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3260 return false;
3261
3262 /* Avoid LA instructions with index register on z196; it is
3263 preferable to use regular add instructions when possible. */
3264 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3265 return false;
3266
3267 if (!TARGET_64BIT && !addr.pointer)
3268 return false;
3269
3270 if (addr.pointer)
3271 return true;
3272
3273 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3274 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3275 return true;
3276
3277 return false;
3278 }
3279
3280 /* Emit a forced load-address operation to load SRC into DST.
3281 This will use the LOAD ADDRESS instruction even in situations
3282 where legitimate_la_operand_p (SRC) returns false. */
3283
3284 void
3285 s390_load_address (rtx dst, rtx src)
3286 {
3287 if (TARGET_64BIT)
3288 emit_move_insn (dst, src);
3289 else
3290 emit_insn (gen_force_la_31 (dst, src));
3291 }
3292
3293 /* Return a legitimate reference for ORIG (an address) using the
3294 register REG. If REG is 0, a new pseudo is generated.
3295
3296 There are two types of references that must be handled:
3297
3298 1. Global data references must load the address from the GOT, via
3299 the PIC reg. An insn is emitted to do this load, and the reg is
3300 returned.
3301
3302 2. Static data references, constant pool addresses, and code labels
3303 compute the address as an offset from the GOT, whose base is in
3304 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3305 differentiate them from global data objects. The returned
3306 address is the PIC reg + an unspec constant.
3307
3308 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3309 reg also appears in the address. */
3310
3311 rtx
3312 legitimize_pic_address (rtx orig, rtx reg)
3313 {
3314 rtx addr = orig;
3315 rtx new_rtx = orig;
3316 rtx base;
3317
3318 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3319
3320 if (GET_CODE (addr) == LABEL_REF
3321 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3322 {
3323 /* This is a local symbol. */
3324 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3325 {
3326 /* Access local symbols PC-relative via LARL.
3327 This is the same as in the non-PIC case, so it is
3328 handled automatically ... */
3329 }
3330 else
3331 {
3332 /* Access local symbols relative to the GOT. */
3333
3334 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3335
3336 if (reload_in_progress || reload_completed)
3337 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3338
3339 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3340 addr = gen_rtx_CONST (Pmode, addr);
3341 addr = force_const_mem (Pmode, addr);
3342 emit_move_insn (temp, addr);
3343
3344 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3345 if (reg != 0)
3346 {
3347 s390_load_address (reg, new_rtx);
3348 new_rtx = reg;
3349 }
3350 }
3351 }
3352 else if (GET_CODE (addr) == SYMBOL_REF)
3353 {
3354 if (reg == 0)
3355 reg = gen_reg_rtx (Pmode);
3356
3357 if (flag_pic == 1)
3358 {
3359 /* Assume GOT offset < 4k. This is handled the same way
3360 in both 31- and 64-bit code (@GOT). */
3361
3362 if (reload_in_progress || reload_completed)
3363 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3364
3365 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3366 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3367 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3368 new_rtx = gen_const_mem (Pmode, new_rtx);
3369 emit_move_insn (reg, new_rtx);
3370 new_rtx = reg;
3371 }
3372 else if (TARGET_CPU_ZARCH)
3373 {
3374 /* If the GOT offset might be >= 4k, we determine the position
3375 of the GOT entry via a PC-relative LARL (@GOTENT). */
3376
3377 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3378
3379 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3380 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3381
3382 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3383 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3384 emit_move_insn (temp, new_rtx);
3385
3386 new_rtx = gen_const_mem (Pmode, temp);
3387 emit_move_insn (reg, new_rtx);
3388 new_rtx = reg;
3389 }
3390 else
3391 {
3392 /* If the GOT offset might be >= 4k, we have to load it
3393 from the literal pool (@GOT). */
3394
3395 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3396
3397 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3398 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3399
3400 if (reload_in_progress || reload_completed)
3401 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3402
3403 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3404 addr = gen_rtx_CONST (Pmode, addr);
3405 addr = force_const_mem (Pmode, addr);
3406 emit_move_insn (temp, addr);
3407
3408 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3409 new_rtx = gen_const_mem (Pmode, new_rtx);
3410 emit_move_insn (reg, new_rtx);
3411 new_rtx = reg;
3412 }
3413 }
3414 else
3415 {
3416 if (GET_CODE (addr) == CONST)
3417 {
3418 addr = XEXP (addr, 0);
3419 if (GET_CODE (addr) == UNSPEC)
3420 {
3421 gcc_assert (XVECLEN (addr, 0) == 1);
3422 switch (XINT (addr, 1))
3423 {
3424 /* If someone moved a GOT-relative UNSPEC
3425 out of the literal pool, force them back in. */
3426 case UNSPEC_GOTOFF:
3427 case UNSPEC_PLTOFF:
3428 new_rtx = force_const_mem (Pmode, orig);
3429 break;
3430
3431 /* @GOT is OK as is if small. */
3432 case UNSPEC_GOT:
3433 if (flag_pic == 2)
3434 new_rtx = force_const_mem (Pmode, orig);
3435 break;
3436
3437 /* @GOTENT is OK as is. */
3438 case UNSPEC_GOTENT:
3439 break;
3440
3441 /* @PLT is OK as is on 64-bit, must be converted to
3442 GOT-relative @PLTOFF on 31-bit. */
3443 case UNSPEC_PLT:
3444 if (!TARGET_CPU_ZARCH)
3445 {
3446 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3447
3448 if (reload_in_progress || reload_completed)
3449 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3450
3451 addr = XVECEXP (addr, 0, 0);
3452 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3453 UNSPEC_PLTOFF);
3454 addr = gen_rtx_CONST (Pmode, addr);
3455 addr = force_const_mem (Pmode, addr);
3456 emit_move_insn (temp, addr);
3457
3458 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3459 if (reg != 0)
3460 {
3461 s390_load_address (reg, new_rtx);
3462 new_rtx = reg;
3463 }
3464 }
3465 break;
3466
3467 /* Everything else cannot happen. */
3468 default:
3469 gcc_unreachable ();
3470 }
3471 }
3472 else
3473 gcc_assert (GET_CODE (addr) == PLUS);
3474 }
3475 if (GET_CODE (addr) == PLUS)
3476 {
3477 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3478
3479 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3480 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3481
3482 /* Check first to see if this is a constant offset
3483 from a local symbol reference. */
3484 if ((GET_CODE (op0) == LABEL_REF
3485 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3486 && GET_CODE (op1) == CONST_INT)
3487 {
3488 if (TARGET_CPU_ZARCH
3489 && larl_operand (op0, VOIDmode)
3490 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3491 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3492 {
3493 if (INTVAL (op1) & 1)
3494 {
3495 /* LARL can't handle odd offsets, so emit a
3496 pair of LARL and LA. */
3497 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3498
3499 if (!DISP_IN_RANGE (INTVAL (op1)))
3500 {
3501 HOST_WIDE_INT even = INTVAL (op1) - 1;
3502 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3503 op0 = gen_rtx_CONST (Pmode, op0);
3504 op1 = const1_rtx;
3505 }
3506
3507 emit_move_insn (temp, op0);
3508 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3509
3510 if (reg != 0)
3511 {
3512 s390_load_address (reg, new_rtx);
3513 new_rtx = reg;
3514 }
3515 }
3516 else
3517 {
3518 /* If the offset is even, we can just use LARL.
3519 This will happen automatically. */
3520 }
3521 }
3522 else
3523 {
3524 /* Access local symbols relative to the GOT. */
3525
3526 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3527
3528 if (reload_in_progress || reload_completed)
3529 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3530
3531 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3532 UNSPEC_GOTOFF);
3533 addr = gen_rtx_PLUS (Pmode, addr, op1);
3534 addr = gen_rtx_CONST (Pmode, addr);
3535 addr = force_const_mem (Pmode, addr);
3536 emit_move_insn (temp, addr);
3537
3538 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3539 if (reg != 0)
3540 {
3541 s390_load_address (reg, new_rtx);
3542 new_rtx = reg;
3543 }
3544 }
3545 }
3546
3547 /* Now, check whether it is a GOT relative symbol plus offset
3548 that was pulled out of the literal pool. Force it back in. */
3549
3550 else if (GET_CODE (op0) == UNSPEC
3551 && GET_CODE (op1) == CONST_INT
3552 && XINT (op0, 1) == UNSPEC_GOTOFF)
3553 {
3554 gcc_assert (XVECLEN (op0, 0) == 1);
3555
3556 new_rtx = force_const_mem (Pmode, orig);
3557 }
3558
3559 /* Otherwise, compute the sum. */
3560 else
3561 {
3562 base = legitimize_pic_address (XEXP (addr, 0), reg);
3563 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3564 base == reg ? NULL_RTX : reg);
3565 if (GET_CODE (new_rtx) == CONST_INT)
3566 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3567 else
3568 {
3569 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3570 {
3571 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3572 new_rtx = XEXP (new_rtx, 1);
3573 }
3574 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3575 }
3576
3577 if (GET_CODE (new_rtx) == CONST)
3578 new_rtx = XEXP (new_rtx, 0);
3579 new_rtx = force_operand (new_rtx, 0);
3580 }
3581 }
3582 }
3583 return new_rtx;
3584 }
3585
3586 /* Load the thread pointer into a register. */
3587
3588 rtx
3589 s390_get_thread_pointer (void)
3590 {
3591 rtx tp = gen_reg_rtx (Pmode);
3592
3593 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3594 mark_reg_pointer (tp, BITS_PER_WORD);
3595
3596 return tp;
3597 }
3598
3599 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3600 in s390_tls_symbol which always refers to __tls_get_offset.
3601 The returned offset is written to RESULT_REG and an USE rtx is
3602 generated for TLS_CALL. */
3603
3604 static GTY(()) rtx s390_tls_symbol;
3605
3606 static void
3607 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3608 {
3609 rtx insn;
3610
3611 if (!flag_pic)
3612 emit_insn (s390_load_got ());
3613
3614 if (!s390_tls_symbol)
3615 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3616
3617 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3618 gen_rtx_REG (Pmode, RETURN_REGNUM));
3619
3620 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3621 RTL_CONST_CALL_P (insn) = 1;
3622 }
3623
3624 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3625 this (thread-local) address. REG may be used as temporary. */
3626
3627 static rtx
3628 legitimize_tls_address (rtx addr, rtx reg)
3629 {
3630 rtx new_rtx, tls_call, temp, base, r2, insn;
3631
3632 if (GET_CODE (addr) == SYMBOL_REF)
3633 switch (tls_symbolic_operand (addr))
3634 {
3635 case TLS_MODEL_GLOBAL_DYNAMIC:
3636 start_sequence ();
3637 r2 = gen_rtx_REG (Pmode, 2);
3638 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3639 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3640 new_rtx = force_const_mem (Pmode, new_rtx);
3641 emit_move_insn (r2, new_rtx);
3642 s390_emit_tls_call_insn (r2, tls_call);
3643 insn = get_insns ();
3644 end_sequence ();
3645
3646 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3647 temp = gen_reg_rtx (Pmode);
3648 emit_libcall_block (insn, temp, r2, new_rtx);
3649
3650 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3651 if (reg != 0)
3652 {
3653 s390_load_address (reg, new_rtx);
3654 new_rtx = reg;
3655 }
3656 break;
3657
3658 case TLS_MODEL_LOCAL_DYNAMIC:
3659 start_sequence ();
3660 r2 = gen_rtx_REG (Pmode, 2);
3661 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3662 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3663 new_rtx = force_const_mem (Pmode, new_rtx);
3664 emit_move_insn (r2, new_rtx);
3665 s390_emit_tls_call_insn (r2, tls_call);
3666 insn = get_insns ();
3667 end_sequence ();
3668
3669 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3670 temp = gen_reg_rtx (Pmode);
3671 emit_libcall_block (insn, temp, r2, new_rtx);
3672
3673 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3674 base = gen_reg_rtx (Pmode);
3675 s390_load_address (base, new_rtx);
3676
3677 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3678 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3679 new_rtx = force_const_mem (Pmode, new_rtx);
3680 temp = gen_reg_rtx (Pmode);
3681 emit_move_insn (temp, new_rtx);
3682
3683 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3684 if (reg != 0)
3685 {
3686 s390_load_address (reg, new_rtx);
3687 new_rtx = reg;
3688 }
3689 break;
3690
3691 case TLS_MODEL_INITIAL_EXEC:
3692 if (flag_pic == 1)
3693 {
3694 /* Assume GOT offset < 4k. This is handled the same way
3695 in both 31- and 64-bit code. */
3696
3697 if (reload_in_progress || reload_completed)
3698 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3699
3700 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3701 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3702 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3703 new_rtx = gen_const_mem (Pmode, new_rtx);
3704 temp = gen_reg_rtx (Pmode);
3705 emit_move_insn (temp, new_rtx);
3706 }
3707 else if (TARGET_CPU_ZARCH)
3708 {
3709 /* If the GOT offset might be >= 4k, we determine the position
3710 of the GOT entry via a PC-relative LARL. */
3711
3712 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3713 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3714 temp = gen_reg_rtx (Pmode);
3715 emit_move_insn (temp, new_rtx);
3716
3717 new_rtx = gen_const_mem (Pmode, temp);
3718 temp = gen_reg_rtx (Pmode);
3719 emit_move_insn (temp, new_rtx);
3720 }
3721 else if (flag_pic)
3722 {
3723 /* If the GOT offset might be >= 4k, we have to load it
3724 from the literal pool. */
3725
3726 if (reload_in_progress || reload_completed)
3727 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3728
3729 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3730 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3731 new_rtx = force_const_mem (Pmode, new_rtx);
3732 temp = gen_reg_rtx (Pmode);
3733 emit_move_insn (temp, new_rtx);
3734
3735 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3736 new_rtx = gen_const_mem (Pmode, new_rtx);
3737
3738 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3739 temp = gen_reg_rtx (Pmode);
3740 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3741 }
3742 else
3743 {
3744 /* In position-dependent code, load the absolute address of
3745 the GOT entry from the literal pool. */
3746
3747 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3748 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3749 new_rtx = force_const_mem (Pmode, new_rtx);
3750 temp = gen_reg_rtx (Pmode);
3751 emit_move_insn (temp, new_rtx);
3752
3753 new_rtx = temp;
3754 new_rtx = gen_const_mem (Pmode, new_rtx);
3755 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3756 temp = gen_reg_rtx (Pmode);
3757 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3758 }
3759
3760 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3761 if (reg != 0)
3762 {
3763 s390_load_address (reg, new_rtx);
3764 new_rtx = reg;
3765 }
3766 break;
3767
3768 case TLS_MODEL_LOCAL_EXEC:
3769 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3770 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3771 new_rtx = force_const_mem (Pmode, new_rtx);
3772 temp = gen_reg_rtx (Pmode);
3773 emit_move_insn (temp, new_rtx);
3774
3775 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3776 if (reg != 0)
3777 {
3778 s390_load_address (reg, new_rtx);
3779 new_rtx = reg;
3780 }
3781 break;
3782
3783 default:
3784 gcc_unreachable ();
3785 }
3786
3787 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3788 {
3789 switch (XINT (XEXP (addr, 0), 1))
3790 {
3791 case UNSPEC_INDNTPOFF:
3792 gcc_assert (TARGET_CPU_ZARCH);
3793 new_rtx = addr;
3794 break;
3795
3796 default:
3797 gcc_unreachable ();
3798 }
3799 }
3800
3801 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3802 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3803 {
3804 new_rtx = XEXP (XEXP (addr, 0), 0);
3805 if (GET_CODE (new_rtx) != SYMBOL_REF)
3806 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3807
3808 new_rtx = legitimize_tls_address (new_rtx, reg);
3809 new_rtx = plus_constant (Pmode, new_rtx,
3810 INTVAL (XEXP (XEXP (addr, 0), 1)));
3811 new_rtx = force_operand (new_rtx, 0);
3812 }
3813
3814 else
3815 gcc_unreachable (); /* for now ... */
3816
3817 return new_rtx;
3818 }
3819
3820 /* Emit insns making the address in operands[1] valid for a standard
3821 move to operands[0]. operands[1] is replaced by an address which
3822 should be used instead of the former RTX to emit the move
3823 pattern. */
3824
3825 void
3826 emit_symbolic_move (rtx *operands)
3827 {
3828 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3829
3830 if (GET_CODE (operands[0]) == MEM)
3831 operands[1] = force_reg (Pmode, operands[1]);
3832 else if (TLS_SYMBOLIC_CONST (operands[1]))
3833 operands[1] = legitimize_tls_address (operands[1], temp);
3834 else if (flag_pic)
3835 operands[1] = legitimize_pic_address (operands[1], temp);
3836 }
3837
3838 /* Try machine-dependent ways of modifying an illegitimate address X
3839 to be legitimate. If we find one, return the new, valid address.
3840
3841 OLDX is the address as it was before break_out_memory_refs was called.
3842 In some cases it is useful to look at this to decide what needs to be done.
3843
3844 MODE is the mode of the operand pointed to by X.
3845
3846 When -fpic is used, special handling is needed for symbolic references.
3847 See comments by legitimize_pic_address for details. */
3848
3849 static rtx
3850 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3851 enum machine_mode mode ATTRIBUTE_UNUSED)
3852 {
3853 rtx constant_term = const0_rtx;
3854
3855 if (TLS_SYMBOLIC_CONST (x))
3856 {
3857 x = legitimize_tls_address (x, 0);
3858
3859 if (s390_legitimate_address_p (mode, x, FALSE))
3860 return x;
3861 }
3862 else if (GET_CODE (x) == PLUS
3863 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3864 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3865 {
3866 return x;
3867 }
3868 else if (flag_pic)
3869 {
3870 if (SYMBOLIC_CONST (x)
3871 || (GET_CODE (x) == PLUS
3872 && (SYMBOLIC_CONST (XEXP (x, 0))
3873 || SYMBOLIC_CONST (XEXP (x, 1)))))
3874 x = legitimize_pic_address (x, 0);
3875
3876 if (s390_legitimate_address_p (mode, x, FALSE))
3877 return x;
3878 }
3879
3880 x = eliminate_constant_term (x, &constant_term);
3881
3882 /* Optimize loading of large displacements by splitting them
3883 into the multiple of 4K and the rest; this allows the
3884 former to be CSE'd if possible.
3885
3886 Don't do this if the displacement is added to a register
3887 pointing into the stack frame, as the offsets will
3888 change later anyway. */
3889
3890 if (GET_CODE (constant_term) == CONST_INT
3891 && !TARGET_LONG_DISPLACEMENT
3892 && !DISP_IN_RANGE (INTVAL (constant_term))
3893 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3894 {
3895 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3896 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3897
3898 rtx temp = gen_reg_rtx (Pmode);
3899 rtx val = force_operand (GEN_INT (upper), temp);
3900 if (val != temp)
3901 emit_move_insn (temp, val);
3902
3903 x = gen_rtx_PLUS (Pmode, x, temp);
3904 constant_term = GEN_INT (lower);
3905 }
3906
3907 if (GET_CODE (x) == PLUS)
3908 {
3909 if (GET_CODE (XEXP (x, 0)) == REG)
3910 {
3911 rtx temp = gen_reg_rtx (Pmode);
3912 rtx val = force_operand (XEXP (x, 1), temp);
3913 if (val != temp)
3914 emit_move_insn (temp, val);
3915
3916 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3917 }
3918
3919 else if (GET_CODE (XEXP (x, 1)) == REG)
3920 {
3921 rtx temp = gen_reg_rtx (Pmode);
3922 rtx val = force_operand (XEXP (x, 0), temp);
3923 if (val != temp)
3924 emit_move_insn (temp, val);
3925
3926 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3927 }
3928 }
3929
3930 if (constant_term != const0_rtx)
3931 x = gen_rtx_PLUS (Pmode, x, constant_term);
3932
3933 return x;
3934 }
3935
3936 /* Try a machine-dependent way of reloading an illegitimate address AD
3937 operand. If we find one, push the reload and return the new address.
3938
3939 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3940 and TYPE is the reload type of the current reload. */
3941
3942 rtx
3943 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3944 int opnum, int type)
3945 {
3946 if (!optimize || TARGET_LONG_DISPLACEMENT)
3947 return NULL_RTX;
3948
3949 if (GET_CODE (ad) == PLUS)
3950 {
3951 rtx tem = simplify_binary_operation (PLUS, Pmode,
3952 XEXP (ad, 0), XEXP (ad, 1));
3953 if (tem)
3954 ad = tem;
3955 }
3956
3957 if (GET_CODE (ad) == PLUS
3958 && GET_CODE (XEXP (ad, 0)) == REG
3959 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3960 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3961 {
3962 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3963 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3964 rtx cst, tem, new_rtx;
3965
3966 cst = GEN_INT (upper);
3967 if (!legitimate_reload_constant_p (cst))
3968 cst = force_const_mem (Pmode, cst);
3969
3970 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3971 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3972
3973 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3974 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3975 opnum, (enum reload_type) type);
3976 return new_rtx;
3977 }
3978
3979 return NULL_RTX;
3980 }
3981
3982 /* Emit code to move LEN bytes from DST to SRC. */
3983
3984 void
3985 s390_expand_movmem (rtx dst, rtx src, rtx len)
3986 {
3987 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3988 {
3989 if (INTVAL (len) > 0)
3990 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3991 }
3992
3993 else if (TARGET_MVCLE)
3994 {
3995 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3996 }
3997
3998 else
3999 {
4000 rtx dst_addr, src_addr, count, blocks, temp;
4001 rtx loop_start_label = gen_label_rtx ();
4002 rtx loop_end_label = gen_label_rtx ();
4003 rtx end_label = gen_label_rtx ();
4004 enum machine_mode mode;
4005
4006 mode = GET_MODE (len);
4007 if (mode == VOIDmode)
4008 mode = Pmode;
4009
4010 dst_addr = gen_reg_rtx (Pmode);
4011 src_addr = gen_reg_rtx (Pmode);
4012 count = gen_reg_rtx (mode);
4013 blocks = gen_reg_rtx (mode);
4014
4015 convert_move (count, len, 1);
4016 emit_cmp_and_jump_insns (count, const0_rtx,
4017 EQ, NULL_RTX, mode, 1, end_label);
4018
4019 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4020 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4021 dst = change_address (dst, VOIDmode, dst_addr);
4022 src = change_address (src, VOIDmode, src_addr);
4023
4024 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4025 OPTAB_DIRECT);
4026 if (temp != count)
4027 emit_move_insn (count, temp);
4028
4029 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4030 OPTAB_DIRECT);
4031 if (temp != blocks)
4032 emit_move_insn (blocks, temp);
4033
4034 emit_cmp_and_jump_insns (blocks, const0_rtx,
4035 EQ, NULL_RTX, mode, 1, loop_end_label);
4036
4037 emit_label (loop_start_label);
4038
4039 if (TARGET_Z10
4040 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4041 {
4042 rtx prefetch;
4043
4044 /* Issue a read prefetch for the +3 cache line. */
4045 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4046 const0_rtx, const0_rtx);
4047 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4048 emit_insn (prefetch);
4049
4050 /* Issue a write prefetch for the +3 cache line. */
4051 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4052 const1_rtx, const0_rtx);
4053 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4054 emit_insn (prefetch);
4055 }
4056
4057 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4058 s390_load_address (dst_addr,
4059 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4060 s390_load_address (src_addr,
4061 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4062
4063 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4064 OPTAB_DIRECT);
4065 if (temp != blocks)
4066 emit_move_insn (blocks, temp);
4067
4068 emit_cmp_and_jump_insns (blocks, const0_rtx,
4069 EQ, NULL_RTX, mode, 1, loop_end_label);
4070
4071 emit_jump (loop_start_label);
4072 emit_label (loop_end_label);
4073
4074 emit_insn (gen_movmem_short (dst, src,
4075 convert_to_mode (Pmode, count, 1)));
4076 emit_label (end_label);
4077 }
4078 }
4079
4080 /* Emit code to set LEN bytes at DST to VAL.
4081 Make use of clrmem if VAL is zero. */
4082
4083 void
4084 s390_expand_setmem (rtx dst, rtx len, rtx val)
4085 {
4086 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4087 return;
4088
4089 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4090
4091 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4092 {
4093 if (val == const0_rtx && INTVAL (len) <= 256)
4094 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4095 else
4096 {
4097 /* Initialize memory by storing the first byte. */
4098 emit_move_insn (adjust_address (dst, QImode, 0), val);
4099
4100 if (INTVAL (len) > 1)
4101 {
4102 /* Initiate 1 byte overlap move.
4103 The first byte of DST is propagated through DSTP1.
4104 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4105 DST is set to size 1 so the rest of the memory location
4106 does not count as source operand. */
4107 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4108 set_mem_size (dst, 1);
4109
4110 emit_insn (gen_movmem_short (dstp1, dst,
4111 GEN_INT (INTVAL (len) - 2)));
4112 }
4113 }
4114 }
4115
4116 else if (TARGET_MVCLE)
4117 {
4118 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4119 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4120 }
4121
4122 else
4123 {
4124 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4125 rtx loop_start_label = gen_label_rtx ();
4126 rtx loop_end_label = gen_label_rtx ();
4127 rtx end_label = gen_label_rtx ();
4128 enum machine_mode mode;
4129
4130 mode = GET_MODE (len);
4131 if (mode == VOIDmode)
4132 mode = Pmode;
4133
4134 dst_addr = gen_reg_rtx (Pmode);
4135 count = gen_reg_rtx (mode);
4136 blocks = gen_reg_rtx (mode);
4137
4138 convert_move (count, len, 1);
4139 emit_cmp_and_jump_insns (count, const0_rtx,
4140 EQ, NULL_RTX, mode, 1, end_label);
4141
4142 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4143 dst = change_address (dst, VOIDmode, dst_addr);
4144
4145 if (val == const0_rtx)
4146 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4147 OPTAB_DIRECT);
4148 else
4149 {
4150 dstp1 = adjust_address (dst, VOIDmode, 1);
4151 set_mem_size (dst, 1);
4152
4153 /* Initialize memory by storing the first byte. */
4154 emit_move_insn (adjust_address (dst, QImode, 0), val);
4155
4156 /* If count is 1 we are done. */
4157 emit_cmp_and_jump_insns (count, const1_rtx,
4158 EQ, NULL_RTX, mode, 1, end_label);
4159
4160 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4161 OPTAB_DIRECT);
4162 }
4163 if (temp != count)
4164 emit_move_insn (count, temp);
4165
4166 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4167 OPTAB_DIRECT);
4168 if (temp != blocks)
4169 emit_move_insn (blocks, temp);
4170
4171 emit_cmp_and_jump_insns (blocks, const0_rtx,
4172 EQ, NULL_RTX, mode, 1, loop_end_label);
4173
4174 emit_label (loop_start_label);
4175
4176 if (TARGET_Z10
4177 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4178 {
4179 /* Issue a write prefetch for the +4 cache line. */
4180 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4181 GEN_INT (1024)),
4182 const1_rtx, const0_rtx);
4183 emit_insn (prefetch);
4184 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4185 }
4186
4187 if (val == const0_rtx)
4188 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4189 else
4190 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4191 s390_load_address (dst_addr,
4192 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4193
4194 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4195 OPTAB_DIRECT);
4196 if (temp != blocks)
4197 emit_move_insn (blocks, temp);
4198
4199 emit_cmp_and_jump_insns (blocks, const0_rtx,
4200 EQ, NULL_RTX, mode, 1, loop_end_label);
4201
4202 emit_jump (loop_start_label);
4203 emit_label (loop_end_label);
4204
4205 if (val == const0_rtx)
4206 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4207 else
4208 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4209 emit_label (end_label);
4210 }
4211 }
4212
4213 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4214 and return the result in TARGET. */
4215
4216 void
4217 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4218 {
4219 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4220 rtx tmp;
4221
4222 /* As the result of CMPINT is inverted compared to what we need,
4223 we have to swap the operands. */
4224 tmp = op0; op0 = op1; op1 = tmp;
4225
4226 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4227 {
4228 if (INTVAL (len) > 0)
4229 {
4230 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4231 emit_insn (gen_cmpint (target, ccreg));
4232 }
4233 else
4234 emit_move_insn (target, const0_rtx);
4235 }
4236 else if (TARGET_MVCLE)
4237 {
4238 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4239 emit_insn (gen_cmpint (target, ccreg));
4240 }
4241 else
4242 {
4243 rtx addr0, addr1, count, blocks, temp;
4244 rtx loop_start_label = gen_label_rtx ();
4245 rtx loop_end_label = gen_label_rtx ();
4246 rtx end_label = gen_label_rtx ();
4247 enum machine_mode mode;
4248
4249 mode = GET_MODE (len);
4250 if (mode == VOIDmode)
4251 mode = Pmode;
4252
4253 addr0 = gen_reg_rtx (Pmode);
4254 addr1 = gen_reg_rtx (Pmode);
4255 count = gen_reg_rtx (mode);
4256 blocks = gen_reg_rtx (mode);
4257
4258 convert_move (count, len, 1);
4259 emit_cmp_and_jump_insns (count, const0_rtx,
4260 EQ, NULL_RTX, mode, 1, end_label);
4261
4262 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4263 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4264 op0 = change_address (op0, VOIDmode, addr0);
4265 op1 = change_address (op1, VOIDmode, addr1);
4266
4267 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4268 OPTAB_DIRECT);
4269 if (temp != count)
4270 emit_move_insn (count, temp);
4271
4272 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4273 OPTAB_DIRECT);
4274 if (temp != blocks)
4275 emit_move_insn (blocks, temp);
4276
4277 emit_cmp_and_jump_insns (blocks, const0_rtx,
4278 EQ, NULL_RTX, mode, 1, loop_end_label);
4279
4280 emit_label (loop_start_label);
4281
4282 if (TARGET_Z10
4283 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4284 {
4285 rtx prefetch;
4286
4287 /* Issue a read prefetch for the +2 cache line of operand 1. */
4288 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4289 const0_rtx, const0_rtx);
4290 emit_insn (prefetch);
4291 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4292
4293 /* Issue a read prefetch for the +2 cache line of operand 2. */
4294 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4295 const0_rtx, const0_rtx);
4296 emit_insn (prefetch);
4297 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4298 }
4299
4300 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4301 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4302 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4303 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4304 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4305 emit_jump_insn (temp);
4306
4307 s390_load_address (addr0,
4308 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4309 s390_load_address (addr1,
4310 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4311
4312 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4313 OPTAB_DIRECT);
4314 if (temp != blocks)
4315 emit_move_insn (blocks, temp);
4316
4317 emit_cmp_and_jump_insns (blocks, const0_rtx,
4318 EQ, NULL_RTX, mode, 1, loop_end_label);
4319
4320 emit_jump (loop_start_label);
4321 emit_label (loop_end_label);
4322
4323 emit_insn (gen_cmpmem_short (op0, op1,
4324 convert_to_mode (Pmode, count, 1)));
4325 emit_label (end_label);
4326
4327 emit_insn (gen_cmpint (target, ccreg));
4328 }
4329 }
4330
4331
4332 /* Expand conditional increment or decrement using alc/slb instructions.
4333 Should generate code setting DST to either SRC or SRC + INCREMENT,
4334 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4335 Returns true if successful, false otherwise.
4336
4337 That makes it possible to implement some if-constructs without jumps e.g.:
4338 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4339 unsigned int a, b, c;
4340 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4341 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4342 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4343 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4344
4345 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4346 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4347 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4348 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4349 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4350
4351 bool
4352 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4353 rtx dst, rtx src, rtx increment)
4354 {
4355 enum machine_mode cmp_mode;
4356 enum machine_mode cc_mode;
4357 rtx op_res;
4358 rtx insn;
4359 rtvec p;
4360 int ret;
4361
4362 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4363 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4364 cmp_mode = SImode;
4365 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4366 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4367 cmp_mode = DImode;
4368 else
4369 return false;
4370
4371 /* Try ADD LOGICAL WITH CARRY. */
4372 if (increment == const1_rtx)
4373 {
4374 /* Determine CC mode to use. */
4375 if (cmp_code == EQ || cmp_code == NE)
4376 {
4377 if (cmp_op1 != const0_rtx)
4378 {
4379 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4380 NULL_RTX, 0, OPTAB_WIDEN);
4381 cmp_op1 = const0_rtx;
4382 }
4383
4384 cmp_code = cmp_code == EQ ? LEU : GTU;
4385 }
4386
4387 if (cmp_code == LTU || cmp_code == LEU)
4388 {
4389 rtx tem = cmp_op0;
4390 cmp_op0 = cmp_op1;
4391 cmp_op1 = tem;
4392 cmp_code = swap_condition (cmp_code);
4393 }
4394
4395 switch (cmp_code)
4396 {
4397 case GTU:
4398 cc_mode = CCUmode;
4399 break;
4400
4401 case GEU:
4402 cc_mode = CCL3mode;
4403 break;
4404
4405 default:
4406 return false;
4407 }
4408
4409 /* Emit comparison instruction pattern. */
4410 if (!register_operand (cmp_op0, cmp_mode))
4411 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4412
4413 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4414 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4415 /* We use insn_invalid_p here to add clobbers if required. */
4416 ret = insn_invalid_p (emit_insn (insn), false);
4417 gcc_assert (!ret);
4418
4419 /* Emit ALC instruction pattern. */
4420 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4421 gen_rtx_REG (cc_mode, CC_REGNUM),
4422 const0_rtx);
4423
4424 if (src != const0_rtx)
4425 {
4426 if (!register_operand (src, GET_MODE (dst)))
4427 src = force_reg (GET_MODE (dst), src);
4428
4429 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4430 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4431 }
4432
4433 p = rtvec_alloc (2);
4434 RTVEC_ELT (p, 0) =
4435 gen_rtx_SET (VOIDmode, dst, op_res);
4436 RTVEC_ELT (p, 1) =
4437 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4438 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4439
4440 return true;
4441 }
4442
4443 /* Try SUBTRACT LOGICAL WITH BORROW. */
4444 if (increment == constm1_rtx)
4445 {
4446 /* Determine CC mode to use. */
4447 if (cmp_code == EQ || cmp_code == NE)
4448 {
4449 if (cmp_op1 != const0_rtx)
4450 {
4451 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4452 NULL_RTX, 0, OPTAB_WIDEN);
4453 cmp_op1 = const0_rtx;
4454 }
4455
4456 cmp_code = cmp_code == EQ ? LEU : GTU;
4457 }
4458
4459 if (cmp_code == GTU || cmp_code == GEU)
4460 {
4461 rtx tem = cmp_op0;
4462 cmp_op0 = cmp_op1;
4463 cmp_op1 = tem;
4464 cmp_code = swap_condition (cmp_code);
4465 }
4466
4467 switch (cmp_code)
4468 {
4469 case LEU:
4470 cc_mode = CCUmode;
4471 break;
4472
4473 case LTU:
4474 cc_mode = CCL3mode;
4475 break;
4476
4477 default:
4478 return false;
4479 }
4480
4481 /* Emit comparison instruction pattern. */
4482 if (!register_operand (cmp_op0, cmp_mode))
4483 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4484
4485 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4486 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4487 /* We use insn_invalid_p here to add clobbers if required. */
4488 ret = insn_invalid_p (emit_insn (insn), false);
4489 gcc_assert (!ret);
4490
4491 /* Emit SLB instruction pattern. */
4492 if (!register_operand (src, GET_MODE (dst)))
4493 src = force_reg (GET_MODE (dst), src);
4494
4495 op_res = gen_rtx_MINUS (GET_MODE (dst),
4496 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4497 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4498 gen_rtx_REG (cc_mode, CC_REGNUM),
4499 const0_rtx));
4500 p = rtvec_alloc (2);
4501 RTVEC_ELT (p, 0) =
4502 gen_rtx_SET (VOIDmode, dst, op_res);
4503 RTVEC_ELT (p, 1) =
4504 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4505 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4506
4507 return true;
4508 }
4509
4510 return false;
4511 }
4512
4513 /* Expand code for the insv template. Return true if successful. */
4514
4515 bool
4516 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4517 {
4518 int bitsize = INTVAL (op1);
4519 int bitpos = INTVAL (op2);
4520
4521 /* On z10 we can use the risbg instruction to implement insv. */
4522 if (TARGET_Z10
4523 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4524 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4525 {
4526 rtx op;
4527 rtx clobber;
4528
4529 op = gen_rtx_SET (GET_MODE(src),
4530 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4531 src);
4532 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4533 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4534
4535 return true;
4536 }
4537
4538 /* We need byte alignment. */
4539 if (bitsize % BITS_PER_UNIT)
4540 return false;
4541
4542 if (bitpos == 0
4543 && memory_operand (dest, VOIDmode)
4544 && (register_operand (src, word_mode)
4545 || const_int_operand (src, VOIDmode)))
4546 {
4547 /* Emit standard pattern if possible. */
4548 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4549 if (GET_MODE_BITSIZE (mode) == bitsize)
4550 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4551
4552 /* (set (ze (mem)) (const_int)). */
4553 else if (const_int_operand (src, VOIDmode))
4554 {
4555 int size = bitsize / BITS_PER_UNIT;
4556 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4557 GET_MODE_SIZE (word_mode) - size);
4558
4559 dest = adjust_address (dest, BLKmode, 0);
4560 set_mem_size (dest, size);
4561 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4562 }
4563
4564 /* (set (ze (mem)) (reg)). */
4565 else if (register_operand (src, word_mode))
4566 {
4567 if (bitsize <= GET_MODE_BITSIZE (SImode))
4568 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4569 const0_rtx), src);
4570 else
4571 {
4572 /* Emit st,stcmh sequence. */
4573 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4574 int size = stcmh_width / BITS_PER_UNIT;
4575
4576 emit_move_insn (adjust_address (dest, SImode, size),
4577 gen_lowpart (SImode, src));
4578 set_mem_size (dest, size);
4579 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4580 (stcmh_width), const0_rtx),
4581 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4582 (GET_MODE_BITSIZE (SImode))));
4583 }
4584 }
4585 else
4586 return false;
4587
4588 return true;
4589 }
4590
4591 /* (set (ze (reg)) (const_int)). */
4592 if (TARGET_ZARCH
4593 && register_operand (dest, word_mode)
4594 && (bitpos % 16) == 0
4595 && (bitsize % 16) == 0
4596 && const_int_operand (src, VOIDmode))
4597 {
4598 HOST_WIDE_INT val = INTVAL (src);
4599 int regpos = bitpos + bitsize;
4600
4601 while (regpos > bitpos)
4602 {
4603 enum machine_mode putmode;
4604 int putsize;
4605
4606 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4607 putmode = SImode;
4608 else
4609 putmode = HImode;
4610
4611 putsize = GET_MODE_BITSIZE (putmode);
4612 regpos -= putsize;
4613 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4614 GEN_INT (putsize),
4615 GEN_INT (regpos)),
4616 gen_int_mode (val, putmode));
4617 val >>= putsize;
4618 }
4619 gcc_assert (regpos == bitpos);
4620 return true;
4621 }
4622
4623 return false;
4624 }
4625
4626 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4627 register that holds VAL of mode MODE shifted by COUNT bits. */
4628
4629 static inline rtx
4630 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4631 {
4632 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4633 NULL_RTX, 1, OPTAB_DIRECT);
4634 return expand_simple_binop (SImode, ASHIFT, val, count,
4635 NULL_RTX, 1, OPTAB_DIRECT);
4636 }
4637
4638 /* Structure to hold the initial parameters for a compare_and_swap operation
4639 in HImode and QImode. */
4640
4641 struct alignment_context
4642 {
4643 rtx memsi; /* SI aligned memory location. */
4644 rtx shift; /* Bit offset with regard to lsb. */
4645 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4646 rtx modemaski; /* ~modemask */
4647 bool aligned; /* True if memory is aligned, false else. */
4648 };
4649
4650 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4651 structure AC for transparent simplifying, if the memory alignment is known
4652 to be at least 32bit. MEM is the memory location for the actual operation
4653 and MODE its mode. */
4654
4655 static void
4656 init_alignment_context (struct alignment_context *ac, rtx mem,
4657 enum machine_mode mode)
4658 {
4659 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4660 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4661
4662 if (ac->aligned)
4663 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4664 else
4665 {
4666 /* Alignment is unknown. */
4667 rtx byteoffset, addr, align;
4668
4669 /* Force the address into a register. */
4670 addr = force_reg (Pmode, XEXP (mem, 0));
4671
4672 /* Align it to SImode. */
4673 align = expand_simple_binop (Pmode, AND, addr,
4674 GEN_INT (-GET_MODE_SIZE (SImode)),
4675 NULL_RTX, 1, OPTAB_DIRECT);
4676 /* Generate MEM. */
4677 ac->memsi = gen_rtx_MEM (SImode, align);
4678 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4679 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4680 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4681
4682 /* Calculate shiftcount. */
4683 byteoffset = expand_simple_binop (Pmode, AND, addr,
4684 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4685 NULL_RTX, 1, OPTAB_DIRECT);
4686 /* As we already have some offset, evaluate the remaining distance. */
4687 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4688 NULL_RTX, 1, OPTAB_DIRECT);
4689
4690 }
4691 /* Shift is the byte count, but we need the bitcount. */
4692 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4693 NULL_RTX, 1, OPTAB_DIRECT);
4694 /* Calculate masks. */
4695 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4696 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4697 NULL_RTX, 1, OPTAB_DIRECT);
4698 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4699 }
4700
4701 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4702 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4703 to set if CMP == MEM.
4704 CMP is never in memory for compare_and_swap_cc because
4705 expand_bool_compare_and_swap puts it into a register for later compare. */
4706
4707 void
4708 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4709 {
4710 struct alignment_context ac;
4711 rtx cmpv, newv, val, resv, cc;
4712 rtx res = gen_reg_rtx (SImode);
4713 rtx csloop = gen_label_rtx ();
4714 rtx csend = gen_label_rtx ();
4715
4716 gcc_assert (register_operand (target, VOIDmode));
4717 gcc_assert (MEM_P (mem));
4718
4719 init_alignment_context (&ac, mem, mode);
4720
4721 /* Shift the values to the correct bit positions. */
4722 if (!(ac.aligned && MEM_P (cmp)))
4723 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4724 if (!(ac.aligned && MEM_P (new_rtx)))
4725 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4726
4727 /* Load full word. Subsequent loads are performed by CS. */
4728 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4729 NULL_RTX, 1, OPTAB_DIRECT);
4730
4731 /* Start CS loop. */
4732 emit_label (csloop);
4733 /* val = "<mem>00..0<mem>"
4734 * cmp = "00..0<cmp>00..0"
4735 * new = "00..0<new>00..0"
4736 */
4737
4738 /* Patch cmp and new with val at correct position. */
4739 if (ac.aligned && MEM_P (cmp))
4740 {
4741 cmpv = force_reg (SImode, val);
4742 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0,
4743 0, 0, SImode, cmp);
4744 }
4745 else
4746 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4747 NULL_RTX, 1, OPTAB_DIRECT));
4748 if (ac.aligned && MEM_P (new_rtx))
4749 {
4750 newv = force_reg (SImode, val);
4751 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0,
4752 0, 0, SImode, new_rtx);
4753 }
4754 else
4755 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4756 NULL_RTX, 1, OPTAB_DIRECT));
4757
4758 /* Jump to end if we're done (likely?). */
4759 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4760 cmpv, newv));
4761
4762 /* Check for changes outside mode. */
4763 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4764 NULL_RTX, 1, OPTAB_DIRECT);
4765 cc = s390_emit_compare (NE, resv, val);
4766 emit_move_insn (val, resv);
4767 /* Loop internal if so. */
4768 s390_emit_jump (csloop, cc);
4769
4770 emit_label (csend);
4771
4772 /* Return the correct part of the bitfield. */
4773 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4774 NULL_RTX, 1, OPTAB_DIRECT), 1);
4775 }
4776
4777 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4778 and VAL the value to play with. If AFTER is true then store the value
4779 MEM holds after the operation, if AFTER is false then store the value MEM
4780 holds before the operation. If TARGET is zero then discard that value, else
4781 store it to TARGET. */
4782
4783 void
4784 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4785 rtx target, rtx mem, rtx val, bool after)
4786 {
4787 struct alignment_context ac;
4788 rtx cmp;
4789 rtx new_rtx = gen_reg_rtx (SImode);
4790 rtx orig = gen_reg_rtx (SImode);
4791 rtx csloop = gen_label_rtx ();
4792
4793 gcc_assert (!target || register_operand (target, VOIDmode));
4794 gcc_assert (MEM_P (mem));
4795
4796 init_alignment_context (&ac, mem, mode);
4797
4798 /* Shift val to the correct bit positions.
4799 Preserve "icm", but prevent "ex icm". */
4800 if (!(ac.aligned && code == SET && MEM_P (val)))
4801 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4802
4803 /* Further preparation insns. */
4804 if (code == PLUS || code == MINUS)
4805 emit_move_insn (orig, val);
4806 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4807 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4808 NULL_RTX, 1, OPTAB_DIRECT);
4809
4810 /* Load full word. Subsequent loads are performed by CS. */
4811 cmp = force_reg (SImode, ac.memsi);
4812
4813 /* Start CS loop. */
4814 emit_label (csloop);
4815 emit_move_insn (new_rtx, cmp);
4816
4817 /* Patch new with val at correct position. */
4818 switch (code)
4819 {
4820 case PLUS:
4821 case MINUS:
4822 val = expand_simple_binop (SImode, code, new_rtx, orig,
4823 NULL_RTX, 1, OPTAB_DIRECT);
4824 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4825 NULL_RTX, 1, OPTAB_DIRECT);
4826 /* FALLTHRU */
4827 case SET:
4828 if (ac.aligned && MEM_P (val))
4829 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
4830 0, 0, SImode, val);
4831 else
4832 {
4833 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4834 NULL_RTX, 1, OPTAB_DIRECT);
4835 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4836 NULL_RTX, 1, OPTAB_DIRECT);
4837 }
4838 break;
4839 case AND:
4840 case IOR:
4841 case XOR:
4842 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4843 NULL_RTX, 1, OPTAB_DIRECT);
4844 break;
4845 case MULT: /* NAND */
4846 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4847 NULL_RTX, 1, OPTAB_DIRECT);
4848 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4849 NULL_RTX, 1, OPTAB_DIRECT);
4850 break;
4851 default:
4852 gcc_unreachable ();
4853 }
4854
4855 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4856 ac.memsi, cmp, new_rtx));
4857
4858 /* Return the correct part of the bitfield. */
4859 if (target)
4860 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4861 after ? new_rtx : cmp, ac.shift,
4862 NULL_RTX, 1, OPTAB_DIRECT), 1);
4863 }
4864
4865 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4866 We need to emit DTP-relative relocations. */
4867
4868 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4869
4870 static void
4871 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4872 {
4873 switch (size)
4874 {
4875 case 4:
4876 fputs ("\t.long\t", file);
4877 break;
4878 case 8:
4879 fputs ("\t.quad\t", file);
4880 break;
4881 default:
4882 gcc_unreachable ();
4883 }
4884 output_addr_const (file, x);
4885 fputs ("@DTPOFF", file);
4886 }
4887
4888 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4889 /* Implement TARGET_MANGLE_TYPE. */
4890
4891 static const char *
4892 s390_mangle_type (const_tree type)
4893 {
4894 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4895 && TARGET_LONG_DOUBLE_128)
4896 return "g";
4897
4898 /* For all other types, use normal C++ mangling. */
4899 return NULL;
4900 }
4901 #endif
4902
4903 /* In the name of slightly smaller debug output, and to cater to
4904 general assembler lossage, recognize various UNSPEC sequences
4905 and turn them back into a direct symbol reference. */
4906
4907 static rtx
4908 s390_delegitimize_address (rtx orig_x)
4909 {
4910 rtx x, y;
4911
4912 orig_x = delegitimize_mem_from_attrs (orig_x);
4913 x = orig_x;
4914
4915 /* Extract the symbol ref from:
4916 (plus:SI (reg:SI 12 %r12)
4917 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4918 UNSPEC_GOTOFF/PLTOFF)))
4919 and
4920 (plus:SI (reg:SI 12 %r12)
4921 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4922 UNSPEC_GOTOFF/PLTOFF)
4923 (const_int 4 [0x4])))) */
4924 if (GET_CODE (x) == PLUS
4925 && REG_P (XEXP (x, 0))
4926 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4927 && GET_CODE (XEXP (x, 1)) == CONST)
4928 {
4929 HOST_WIDE_INT offset = 0;
4930
4931 /* The const operand. */
4932 y = XEXP (XEXP (x, 1), 0);
4933
4934 if (GET_CODE (y) == PLUS
4935 && GET_CODE (XEXP (y, 1)) == CONST_INT)
4936 {
4937 offset = INTVAL (XEXP (y, 1));
4938 y = XEXP (y, 0);
4939 }
4940
4941 if (GET_CODE (y) == UNSPEC
4942 && (XINT (y, 1) == UNSPEC_GOTOFF
4943 || XINT (y, 1) == UNSPEC_PLTOFF))
4944 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
4945 }
4946
4947 if (GET_CODE (x) != MEM)
4948 return orig_x;
4949
4950 x = XEXP (x, 0);
4951 if (GET_CODE (x) == PLUS
4952 && GET_CODE (XEXP (x, 1)) == CONST
4953 && GET_CODE (XEXP (x, 0)) == REG
4954 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4955 {
4956 y = XEXP (XEXP (x, 1), 0);
4957 if (GET_CODE (y) == UNSPEC
4958 && XINT (y, 1) == UNSPEC_GOT)
4959 y = XVECEXP (y, 0, 0);
4960 else
4961 return orig_x;
4962 }
4963 else if (GET_CODE (x) == CONST)
4964 {
4965 /* Extract the symbol ref from:
4966 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
4967 UNSPEC_PLT/GOTENT))) */
4968
4969 y = XEXP (x, 0);
4970 if (GET_CODE (y) == UNSPEC
4971 && (XINT (y, 1) == UNSPEC_GOTENT
4972 || XINT (y, 1) == UNSPEC_PLT))
4973 y = XVECEXP (y, 0, 0);
4974 else
4975 return orig_x;
4976 }
4977 else
4978 return orig_x;
4979
4980 if (GET_MODE (orig_x) != Pmode)
4981 {
4982 if (GET_MODE (orig_x) == BLKmode)
4983 return orig_x;
4984 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
4985 if (y == NULL_RTX)
4986 return orig_x;
4987 }
4988 return y;
4989 }
4990
4991 /* Output operand OP to stdio stream FILE.
4992 OP is an address (register + offset) which is not used to address data;
4993 instead the rightmost bits are interpreted as the value. */
4994
4995 static void
4996 print_shift_count_operand (FILE *file, rtx op)
4997 {
4998 HOST_WIDE_INT offset;
4999 rtx base;
5000
5001 /* Extract base register and offset. */
5002 if (!s390_decompose_shift_count (op, &base, &offset))
5003 gcc_unreachable ();
5004
5005 /* Sanity check. */
5006 if (base)
5007 {
5008 gcc_assert (GET_CODE (base) == REG);
5009 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5010 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5011 }
5012
5013 /* Offsets are constricted to twelve bits. */
5014 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5015 if (base)
5016 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5017 }
5018
5019 /* See 'get_some_local_dynamic_name'. */
5020
5021 static int
5022 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5023 {
5024 rtx x = *px;
5025
5026 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5027 {
5028 x = get_pool_constant (x);
5029 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5030 }
5031
5032 if (GET_CODE (x) == SYMBOL_REF
5033 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5034 {
5035 cfun->machine->some_ld_name = XSTR (x, 0);
5036 return 1;
5037 }
5038
5039 return 0;
5040 }
5041
5042 /* Locate some local-dynamic symbol still in use by this function
5043 so that we can print its name in local-dynamic base patterns. */
5044
5045 static const char *
5046 get_some_local_dynamic_name (void)
5047 {
5048 rtx insn;
5049
5050 if (cfun->machine->some_ld_name)
5051 return cfun->machine->some_ld_name;
5052
5053 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5054 if (INSN_P (insn)
5055 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5056 return cfun->machine->some_ld_name;
5057
5058 gcc_unreachable ();
5059 }
5060
5061 /* Output machine-dependent UNSPECs occurring in address constant X
5062 in assembler syntax to stdio stream FILE. Returns true if the
5063 constant X could be recognized, false otherwise. */
5064
5065 static bool
5066 s390_output_addr_const_extra (FILE *file, rtx x)
5067 {
5068 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5069 switch (XINT (x, 1))
5070 {
5071 case UNSPEC_GOTENT:
5072 output_addr_const (file, XVECEXP (x, 0, 0));
5073 fprintf (file, "@GOTENT");
5074 return true;
5075 case UNSPEC_GOT:
5076 output_addr_const (file, XVECEXP (x, 0, 0));
5077 fprintf (file, "@GOT");
5078 return true;
5079 case UNSPEC_GOTOFF:
5080 output_addr_const (file, XVECEXP (x, 0, 0));
5081 fprintf (file, "@GOTOFF");
5082 return true;
5083 case UNSPEC_PLT:
5084 output_addr_const (file, XVECEXP (x, 0, 0));
5085 fprintf (file, "@PLT");
5086 return true;
5087 case UNSPEC_PLTOFF:
5088 output_addr_const (file, XVECEXP (x, 0, 0));
5089 fprintf (file, "@PLTOFF");
5090 return true;
5091 case UNSPEC_TLSGD:
5092 output_addr_const (file, XVECEXP (x, 0, 0));
5093 fprintf (file, "@TLSGD");
5094 return true;
5095 case UNSPEC_TLSLDM:
5096 assemble_name (file, get_some_local_dynamic_name ());
5097 fprintf (file, "@TLSLDM");
5098 return true;
5099 case UNSPEC_DTPOFF:
5100 output_addr_const (file, XVECEXP (x, 0, 0));
5101 fprintf (file, "@DTPOFF");
5102 return true;
5103 case UNSPEC_NTPOFF:
5104 output_addr_const (file, XVECEXP (x, 0, 0));
5105 fprintf (file, "@NTPOFF");
5106 return true;
5107 case UNSPEC_GOTNTPOFF:
5108 output_addr_const (file, XVECEXP (x, 0, 0));
5109 fprintf (file, "@GOTNTPOFF");
5110 return true;
5111 case UNSPEC_INDNTPOFF:
5112 output_addr_const (file, XVECEXP (x, 0, 0));
5113 fprintf (file, "@INDNTPOFF");
5114 return true;
5115 }
5116
5117 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5118 switch (XINT (x, 1))
5119 {
5120 case UNSPEC_POOL_OFFSET:
5121 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5122 output_addr_const (file, x);
5123 return true;
5124 }
5125 return false;
5126 }
5127
5128 /* Output address operand ADDR in assembler syntax to
5129 stdio stream FILE. */
5130
5131 void
5132 print_operand_address (FILE *file, rtx addr)
5133 {
5134 struct s390_address ad;
5135
5136 if (s390_symref_operand_p (addr, NULL, NULL))
5137 {
5138 if (!TARGET_Z10)
5139 {
5140 output_operand_lossage ("symbolic memory references are "
5141 "only supported on z10 or later");
5142 return;
5143 }
5144 output_addr_const (file, addr);
5145 return;
5146 }
5147
5148 if (!s390_decompose_address (addr, &ad)
5149 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5150 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5151 output_operand_lossage ("cannot decompose address");
5152
5153 if (ad.disp)
5154 output_addr_const (file, ad.disp);
5155 else
5156 fprintf (file, "0");
5157
5158 if (ad.base && ad.indx)
5159 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5160 reg_names[REGNO (ad.base)]);
5161 else if (ad.base)
5162 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5163 }
5164
5165 /* Output operand X in assembler syntax to stdio stream FILE.
5166 CODE specified the format flag. The following format flags
5167 are recognized:
5168
5169 'C': print opcode suffix for branch condition.
5170 'D': print opcode suffix for inverse branch condition.
5171 'E': print opcode suffix for branch on index instruction.
5172 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5173 'G': print the size of the operand in bytes.
5174 'O': print only the displacement of a memory reference.
5175 'R': print only the base register of a memory reference.
5176 'S': print S-type memory reference (base+displacement).
5177 'N': print the second word of a DImode operand.
5178 'M': print the second word of a TImode operand.
5179 'Y': print shift count operand.
5180
5181 'b': print integer X as if it's an unsigned byte.
5182 'c': print integer X as if it's an signed byte.
5183 'x': print integer X as if it's an unsigned halfword.
5184 'h': print integer X as if it's a signed halfword.
5185 'i': print the first nonzero HImode part of X.
5186 'j': print the first HImode part unequal to -1 of X.
5187 'k': print the first nonzero SImode part of X.
5188 'm': print the first SImode part unequal to -1 of X.
5189 'o': print integer X as if it's an unsigned 32bit word. */
5190
5191 void
5192 print_operand (FILE *file, rtx x, int code)
5193 {
5194 switch (code)
5195 {
5196 case 'C':
5197 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5198 return;
5199
5200 case 'D':
5201 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5202 return;
5203
5204 case 'E':
5205 if (GET_CODE (x) == LE)
5206 fprintf (file, "l");
5207 else if (GET_CODE (x) == GT)
5208 fprintf (file, "h");
5209 else
5210 output_operand_lossage ("invalid comparison operator "
5211 "for 'E' output modifier");
5212 return;
5213
5214 case 'J':
5215 if (GET_CODE (x) == SYMBOL_REF)
5216 {
5217 fprintf (file, "%s", ":tls_load:");
5218 output_addr_const (file, x);
5219 }
5220 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5221 {
5222 fprintf (file, "%s", ":tls_gdcall:");
5223 output_addr_const (file, XVECEXP (x, 0, 0));
5224 }
5225 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5226 {
5227 fprintf (file, "%s", ":tls_ldcall:");
5228 assemble_name (file, get_some_local_dynamic_name ());
5229 }
5230 else
5231 output_operand_lossage ("invalid reference for 'J' output modifier");
5232 return;
5233
5234 case 'G':
5235 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5236 return;
5237
5238 case 'O':
5239 {
5240 struct s390_address ad;
5241 int ret;
5242
5243 if (!MEM_P (x))
5244 {
5245 output_operand_lossage ("memory reference expected for "
5246 "'O' output modifier");
5247 return;
5248 }
5249
5250 ret = s390_decompose_address (XEXP (x, 0), &ad);
5251
5252 if (!ret
5253 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5254 || ad.indx)
5255 {
5256 output_operand_lossage ("invalid address for 'O' output modifier");
5257 return;
5258 }
5259
5260 if (ad.disp)
5261 output_addr_const (file, ad.disp);
5262 else
5263 fprintf (file, "0");
5264 }
5265 return;
5266
5267 case 'R':
5268 {
5269 struct s390_address ad;
5270 int ret;
5271
5272 if (!MEM_P (x))
5273 {
5274 output_operand_lossage ("memory reference expected for "
5275 "'R' output modifier");
5276 return;
5277 }
5278
5279 ret = s390_decompose_address (XEXP (x, 0), &ad);
5280
5281 if (!ret
5282 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5283 || ad.indx)
5284 {
5285 output_operand_lossage ("invalid address for 'R' output modifier");
5286 return;
5287 }
5288
5289 if (ad.base)
5290 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5291 else
5292 fprintf (file, "0");
5293 }
5294 return;
5295
5296 case 'S':
5297 {
5298 struct s390_address ad;
5299 int ret;
5300
5301 if (!MEM_P (x))
5302 {
5303 output_operand_lossage ("memory reference expected for "
5304 "'S' output modifier");
5305 return;
5306 }
5307 ret = s390_decompose_address (XEXP (x, 0), &ad);
5308
5309 if (!ret
5310 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5311 || ad.indx)
5312 {
5313 output_operand_lossage ("invalid address for 'S' output modifier");
5314 return;
5315 }
5316
5317 if (ad.disp)
5318 output_addr_const (file, ad.disp);
5319 else
5320 fprintf (file, "0");
5321
5322 if (ad.base)
5323 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5324 }
5325 return;
5326
5327 case 'N':
5328 if (GET_CODE (x) == REG)
5329 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5330 else if (GET_CODE (x) == MEM)
5331 x = change_address (x, VOIDmode,
5332 plus_constant (Pmode, XEXP (x, 0), 4));
5333 else
5334 output_operand_lossage ("register or memory expression expected "
5335 "for 'N' output modifier");
5336 break;
5337
5338 case 'M':
5339 if (GET_CODE (x) == REG)
5340 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5341 else if (GET_CODE (x) == MEM)
5342 x = change_address (x, VOIDmode,
5343 plus_constant (Pmode, XEXP (x, 0), 8));
5344 else
5345 output_operand_lossage ("register or memory expression expected "
5346 "for 'M' output modifier");
5347 break;
5348
5349 case 'Y':
5350 print_shift_count_operand (file, x);
5351 return;
5352 }
5353
5354 switch (GET_CODE (x))
5355 {
5356 case REG:
5357 fprintf (file, "%s", reg_names[REGNO (x)]);
5358 break;
5359
5360 case MEM:
5361 output_address (XEXP (x, 0));
5362 break;
5363
5364 case CONST:
5365 case CODE_LABEL:
5366 case LABEL_REF:
5367 case SYMBOL_REF:
5368 output_addr_const (file, x);
5369 break;
5370
5371 case CONST_INT:
5372 if (code == 'b')
5373 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5374 else if (code == 'c')
5375 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5376 else if (code == 'x')
5377 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5378 else if (code == 'h')
5379 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5380 else if (code == 'i')
5381 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5382 s390_extract_part (x, HImode, 0));
5383 else if (code == 'j')
5384 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5385 s390_extract_part (x, HImode, -1));
5386 else if (code == 'k')
5387 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5388 s390_extract_part (x, SImode, 0));
5389 else if (code == 'm')
5390 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5391 s390_extract_part (x, SImode, -1));
5392 else if (code == 'o')
5393 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5394 else
5395 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5396 break;
5397
5398 case CONST_DOUBLE:
5399 gcc_assert (GET_MODE (x) == VOIDmode);
5400 if (code == 'b')
5401 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5402 else if (code == 'x')
5403 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5404 else if (code == 'h')
5405 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5406 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5407 else
5408 {
5409 if (code == 0)
5410 output_operand_lossage ("invalid constant - try using "
5411 "an output modifier");
5412 else
5413 output_operand_lossage ("invalid constant for output modifier '%c'",
5414 code);
5415 }
5416 break;
5417
5418 default:
5419 if (code == 0)
5420 output_operand_lossage ("invalid expression - try using "
5421 "an output modifier");
5422 else
5423 output_operand_lossage ("invalid expression for output "
5424 "modifier '%c'", code);
5425 break;
5426 }
5427 }
5428
5429 /* Target hook for assembling integer objects. We need to define it
5430 here to work a round a bug in some versions of GAS, which couldn't
5431 handle values smaller than INT_MIN when printed in decimal. */
5432
5433 static bool
5434 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5435 {
5436 if (size == 8 && aligned_p
5437 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5438 {
5439 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5440 INTVAL (x));
5441 return true;
5442 }
5443 return default_assemble_integer (x, size, aligned_p);
5444 }
5445
5446 /* Returns true if register REGNO is used for forming
5447 a memory address in expression X. */
5448
5449 static bool
5450 reg_used_in_mem_p (int regno, rtx x)
5451 {
5452 enum rtx_code code = GET_CODE (x);
5453 int i, j;
5454 const char *fmt;
5455
5456 if (code == MEM)
5457 {
5458 if (refers_to_regno_p (regno, regno+1,
5459 XEXP (x, 0), 0))
5460 return true;
5461 }
5462 else if (code == SET
5463 && GET_CODE (SET_DEST (x)) == PC)
5464 {
5465 if (refers_to_regno_p (regno, regno+1,
5466 SET_SRC (x), 0))
5467 return true;
5468 }
5469
5470 fmt = GET_RTX_FORMAT (code);
5471 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5472 {
5473 if (fmt[i] == 'e'
5474 && reg_used_in_mem_p (regno, XEXP (x, i)))
5475 return true;
5476
5477 else if (fmt[i] == 'E')
5478 for (j = 0; j < XVECLEN (x, i); j++)
5479 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5480 return true;
5481 }
5482 return false;
5483 }
5484
5485 /* Returns true if expression DEP_RTX sets an address register
5486 used by instruction INSN to address memory. */
5487
5488 static bool
5489 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5490 {
5491 rtx target, pat;
5492
5493 if (GET_CODE (dep_rtx) == INSN)
5494 dep_rtx = PATTERN (dep_rtx);
5495
5496 if (GET_CODE (dep_rtx) == SET)
5497 {
5498 target = SET_DEST (dep_rtx);
5499 if (GET_CODE (target) == STRICT_LOW_PART)
5500 target = XEXP (target, 0);
5501 while (GET_CODE (target) == SUBREG)
5502 target = SUBREG_REG (target);
5503
5504 if (GET_CODE (target) == REG)
5505 {
5506 int regno = REGNO (target);
5507
5508 if (s390_safe_attr_type (insn) == TYPE_LA)
5509 {
5510 pat = PATTERN (insn);
5511 if (GET_CODE (pat) == PARALLEL)
5512 {
5513 gcc_assert (XVECLEN (pat, 0) == 2);
5514 pat = XVECEXP (pat, 0, 0);
5515 }
5516 gcc_assert (GET_CODE (pat) == SET);
5517 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5518 }
5519 else if (get_attr_atype (insn) == ATYPE_AGEN)
5520 return reg_used_in_mem_p (regno, PATTERN (insn));
5521 }
5522 }
5523 return false;
5524 }
5525
5526 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5527
5528 int
5529 s390_agen_dep_p (rtx dep_insn, rtx insn)
5530 {
5531 rtx dep_rtx = PATTERN (dep_insn);
5532 int i;
5533
5534 if (GET_CODE (dep_rtx) == SET
5535 && addr_generation_dependency_p (dep_rtx, insn))
5536 return 1;
5537 else if (GET_CODE (dep_rtx) == PARALLEL)
5538 {
5539 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5540 {
5541 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5542 return 1;
5543 }
5544 }
5545 return 0;
5546 }
5547
5548
5549 /* A C statement (sans semicolon) to update the integer scheduling priority
5550 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5551 reduce the priority to execute INSN later. Do not define this macro if
5552 you do not need to adjust the scheduling priorities of insns.
5553
5554 A STD instruction should be scheduled earlier,
5555 in order to use the bypass. */
5556 static int
5557 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5558 {
5559 if (! INSN_P (insn))
5560 return priority;
5561
5562 if (s390_tune != PROCESSOR_2084_Z990
5563 && s390_tune != PROCESSOR_2094_Z9_109
5564 && s390_tune != PROCESSOR_2097_Z10
5565 && s390_tune != PROCESSOR_2817_Z196)
5566 return priority;
5567
5568 switch (s390_safe_attr_type (insn))
5569 {
5570 case TYPE_FSTOREDF:
5571 case TYPE_FSTORESF:
5572 priority = priority << 3;
5573 break;
5574 case TYPE_STORE:
5575 case TYPE_STM:
5576 priority = priority << 1;
5577 break;
5578 default:
5579 break;
5580 }
5581 return priority;
5582 }
5583
5584
5585 /* The number of instructions that can be issued per cycle. */
5586
5587 static int
5588 s390_issue_rate (void)
5589 {
5590 switch (s390_tune)
5591 {
5592 case PROCESSOR_2084_Z990:
5593 case PROCESSOR_2094_Z9_109:
5594 case PROCESSOR_2817_Z196:
5595 return 3;
5596 case PROCESSOR_2097_Z10:
5597 return 2;
5598 default:
5599 return 1;
5600 }
5601 }
5602
5603 static int
5604 s390_first_cycle_multipass_dfa_lookahead (void)
5605 {
5606 return 4;
5607 }
5608
5609 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5610 Fix up MEMs as required. */
5611
5612 static void
5613 annotate_constant_pool_refs (rtx *x)
5614 {
5615 int i, j;
5616 const char *fmt;
5617
5618 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5619 || !CONSTANT_POOL_ADDRESS_P (*x));
5620
5621 /* Literal pool references can only occur inside a MEM ... */
5622 if (GET_CODE (*x) == MEM)
5623 {
5624 rtx memref = XEXP (*x, 0);
5625
5626 if (GET_CODE (memref) == SYMBOL_REF
5627 && CONSTANT_POOL_ADDRESS_P (memref))
5628 {
5629 rtx base = cfun->machine->base_reg;
5630 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5631 UNSPEC_LTREF);
5632
5633 *x = replace_equiv_address (*x, addr);
5634 return;
5635 }
5636
5637 if (GET_CODE (memref) == CONST
5638 && GET_CODE (XEXP (memref, 0)) == PLUS
5639 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5640 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5641 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5642 {
5643 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5644 rtx sym = XEXP (XEXP (memref, 0), 0);
5645 rtx base = cfun->machine->base_reg;
5646 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5647 UNSPEC_LTREF);
5648
5649 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5650 return;
5651 }
5652 }
5653
5654 /* ... or a load-address type pattern. */
5655 if (GET_CODE (*x) == SET)
5656 {
5657 rtx addrref = SET_SRC (*x);
5658
5659 if (GET_CODE (addrref) == SYMBOL_REF
5660 && CONSTANT_POOL_ADDRESS_P (addrref))
5661 {
5662 rtx base = cfun->machine->base_reg;
5663 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5664 UNSPEC_LTREF);
5665
5666 SET_SRC (*x) = addr;
5667 return;
5668 }
5669
5670 if (GET_CODE (addrref) == CONST
5671 && GET_CODE (XEXP (addrref, 0)) == PLUS
5672 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5673 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5674 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5675 {
5676 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5677 rtx sym = XEXP (XEXP (addrref, 0), 0);
5678 rtx base = cfun->machine->base_reg;
5679 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5680 UNSPEC_LTREF);
5681
5682 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5683 return;
5684 }
5685 }
5686
5687 /* Annotate LTREL_BASE as well. */
5688 if (GET_CODE (*x) == UNSPEC
5689 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5690 {
5691 rtx base = cfun->machine->base_reg;
5692 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5693 UNSPEC_LTREL_BASE);
5694 return;
5695 }
5696
5697 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5698 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5699 {
5700 if (fmt[i] == 'e')
5701 {
5702 annotate_constant_pool_refs (&XEXP (*x, i));
5703 }
5704 else if (fmt[i] == 'E')
5705 {
5706 for (j = 0; j < XVECLEN (*x, i); j++)
5707 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5708 }
5709 }
5710 }
5711
5712 /* Split all branches that exceed the maximum distance.
5713 Returns true if this created a new literal pool entry. */
5714
5715 static int
5716 s390_split_branches (void)
5717 {
5718 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5719 int new_literal = 0, ret;
5720 rtx insn, pat, tmp, target;
5721 rtx *label;
5722
5723 /* We need correct insn addresses. */
5724
5725 shorten_branches (get_insns ());
5726
5727 /* Find all branches that exceed 64KB, and split them. */
5728
5729 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5730 {
5731 if (GET_CODE (insn) != JUMP_INSN)
5732 continue;
5733
5734 pat = PATTERN (insn);
5735 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5736 pat = XVECEXP (pat, 0, 0);
5737 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5738 continue;
5739
5740 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5741 {
5742 label = &SET_SRC (pat);
5743 }
5744 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5745 {
5746 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5747 label = &XEXP (SET_SRC (pat), 1);
5748 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5749 label = &XEXP (SET_SRC (pat), 2);
5750 else
5751 continue;
5752 }
5753 else
5754 continue;
5755
5756 if (get_attr_length (insn) <= 4)
5757 continue;
5758
5759 /* We are going to use the return register as scratch register,
5760 make sure it will be saved/restored by the prologue/epilogue. */
5761 cfun_frame_layout.save_return_addr_p = 1;
5762
5763 if (!flag_pic)
5764 {
5765 new_literal = 1;
5766 tmp = force_const_mem (Pmode, *label);
5767 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5768 INSN_ADDRESSES_NEW (tmp, -1);
5769 annotate_constant_pool_refs (&PATTERN (tmp));
5770
5771 target = temp_reg;
5772 }
5773 else
5774 {
5775 new_literal = 1;
5776 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5777 UNSPEC_LTREL_OFFSET);
5778 target = gen_rtx_CONST (Pmode, target);
5779 target = force_const_mem (Pmode, target);
5780 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5781 INSN_ADDRESSES_NEW (tmp, -1);
5782 annotate_constant_pool_refs (&PATTERN (tmp));
5783
5784 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5785 cfun->machine->base_reg),
5786 UNSPEC_LTREL_BASE);
5787 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5788 }
5789
5790 ret = validate_change (insn, label, target, 0);
5791 gcc_assert (ret);
5792 }
5793
5794 return new_literal;
5795 }
5796
5797
5798 /* Find an annotated literal pool symbol referenced in RTX X,
5799 and store it at REF. Will abort if X contains references to
5800 more than one such pool symbol; multiple references to the same
5801 symbol are allowed, however.
5802
5803 The rtx pointed to by REF must be initialized to NULL_RTX
5804 by the caller before calling this routine. */
5805
5806 static void
5807 find_constant_pool_ref (rtx x, rtx *ref)
5808 {
5809 int i, j;
5810 const char *fmt;
5811
5812 /* Ignore LTREL_BASE references. */
5813 if (GET_CODE (x) == UNSPEC
5814 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5815 return;
5816 /* Likewise POOL_ENTRY insns. */
5817 if (GET_CODE (x) == UNSPEC_VOLATILE
5818 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5819 return;
5820
5821 gcc_assert (GET_CODE (x) != SYMBOL_REF
5822 || !CONSTANT_POOL_ADDRESS_P (x));
5823
5824 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5825 {
5826 rtx sym = XVECEXP (x, 0, 0);
5827 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5828 && CONSTANT_POOL_ADDRESS_P (sym));
5829
5830 if (*ref == NULL_RTX)
5831 *ref = sym;
5832 else
5833 gcc_assert (*ref == sym);
5834
5835 return;
5836 }
5837
5838 fmt = GET_RTX_FORMAT (GET_CODE (x));
5839 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5840 {
5841 if (fmt[i] == 'e')
5842 {
5843 find_constant_pool_ref (XEXP (x, i), ref);
5844 }
5845 else if (fmt[i] == 'E')
5846 {
5847 for (j = 0; j < XVECLEN (x, i); j++)
5848 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5849 }
5850 }
5851 }
5852
5853 /* Replace every reference to the annotated literal pool
5854 symbol REF in X by its base plus OFFSET. */
5855
5856 static void
5857 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5858 {
5859 int i, j;
5860 const char *fmt;
5861
5862 gcc_assert (*x != ref);
5863
5864 if (GET_CODE (*x) == UNSPEC
5865 && XINT (*x, 1) == UNSPEC_LTREF
5866 && XVECEXP (*x, 0, 0) == ref)
5867 {
5868 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5869 return;
5870 }
5871
5872 if (GET_CODE (*x) == PLUS
5873 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5874 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5875 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5876 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5877 {
5878 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5879 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
5880 return;
5881 }
5882
5883 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5884 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5885 {
5886 if (fmt[i] == 'e')
5887 {
5888 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5889 }
5890 else if (fmt[i] == 'E')
5891 {
5892 for (j = 0; j < XVECLEN (*x, i); j++)
5893 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5894 }
5895 }
5896 }
5897
5898 /* Check whether X contains an UNSPEC_LTREL_BASE.
5899 Return its constant pool symbol if found, NULL_RTX otherwise. */
5900
5901 static rtx
5902 find_ltrel_base (rtx x)
5903 {
5904 int i, j;
5905 const char *fmt;
5906
5907 if (GET_CODE (x) == UNSPEC
5908 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5909 return XVECEXP (x, 0, 0);
5910
5911 fmt = GET_RTX_FORMAT (GET_CODE (x));
5912 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5913 {
5914 if (fmt[i] == 'e')
5915 {
5916 rtx fnd = find_ltrel_base (XEXP (x, i));
5917 if (fnd)
5918 return fnd;
5919 }
5920 else if (fmt[i] == 'E')
5921 {
5922 for (j = 0; j < XVECLEN (x, i); j++)
5923 {
5924 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5925 if (fnd)
5926 return fnd;
5927 }
5928 }
5929 }
5930
5931 return NULL_RTX;
5932 }
5933
5934 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5935
5936 static void
5937 replace_ltrel_base (rtx *x)
5938 {
5939 int i, j;
5940 const char *fmt;
5941
5942 if (GET_CODE (*x) == UNSPEC
5943 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5944 {
5945 *x = XVECEXP (*x, 0, 1);
5946 return;
5947 }
5948
5949 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5950 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5951 {
5952 if (fmt[i] == 'e')
5953 {
5954 replace_ltrel_base (&XEXP (*x, i));
5955 }
5956 else if (fmt[i] == 'E')
5957 {
5958 for (j = 0; j < XVECLEN (*x, i); j++)
5959 replace_ltrel_base (&XVECEXP (*x, i, j));
5960 }
5961 }
5962 }
5963
5964
5965 /* We keep a list of constants which we have to add to internal
5966 constant tables in the middle of large functions. */
5967
5968 #define NR_C_MODES 11
5969 enum machine_mode constant_modes[NR_C_MODES] =
5970 {
5971 TFmode, TImode, TDmode,
5972 DFmode, DImode, DDmode,
5973 SFmode, SImode, SDmode,
5974 HImode,
5975 QImode
5976 };
5977
5978 struct constant
5979 {
5980 struct constant *next;
5981 rtx value;
5982 rtx label;
5983 };
5984
5985 struct constant_pool
5986 {
5987 struct constant_pool *next;
5988 rtx first_insn;
5989 rtx pool_insn;
5990 bitmap insns;
5991 rtx emit_pool_after;
5992
5993 struct constant *constants[NR_C_MODES];
5994 struct constant *execute;
5995 rtx label;
5996 int size;
5997 };
5998
5999 /* Allocate new constant_pool structure. */
6000
6001 static struct constant_pool *
6002 s390_alloc_pool (void)
6003 {
6004 struct constant_pool *pool;
6005 int i;
6006
6007 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6008 pool->next = NULL;
6009 for (i = 0; i < NR_C_MODES; i++)
6010 pool->constants[i] = NULL;
6011
6012 pool->execute = NULL;
6013 pool->label = gen_label_rtx ();
6014 pool->first_insn = NULL_RTX;
6015 pool->pool_insn = NULL_RTX;
6016 pool->insns = BITMAP_ALLOC (NULL);
6017 pool->size = 0;
6018 pool->emit_pool_after = NULL_RTX;
6019
6020 return pool;
6021 }
6022
6023 /* Create new constant pool covering instructions starting at INSN
6024 and chain it to the end of POOL_LIST. */
6025
6026 static struct constant_pool *
6027 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6028 {
6029 struct constant_pool *pool, **prev;
6030
6031 pool = s390_alloc_pool ();
6032 pool->first_insn = insn;
6033
6034 for (prev = pool_list; *prev; prev = &(*prev)->next)
6035 ;
6036 *prev = pool;
6037
6038 return pool;
6039 }
6040
6041 /* End range of instructions covered by POOL at INSN and emit
6042 placeholder insn representing the pool. */
6043
6044 static void
6045 s390_end_pool (struct constant_pool *pool, rtx insn)
6046 {
6047 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6048
6049 if (!insn)
6050 insn = get_last_insn ();
6051
6052 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6053 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6054 }
6055
6056 /* Add INSN to the list of insns covered by POOL. */
6057
6058 static void
6059 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6060 {
6061 bitmap_set_bit (pool->insns, INSN_UID (insn));
6062 }
6063
6064 /* Return pool out of POOL_LIST that covers INSN. */
6065
6066 static struct constant_pool *
6067 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6068 {
6069 struct constant_pool *pool;
6070
6071 for (pool = pool_list; pool; pool = pool->next)
6072 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6073 break;
6074
6075 return pool;
6076 }
6077
6078 /* Add constant VAL of mode MODE to the constant pool POOL. */
6079
6080 static void
6081 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6082 {
6083 struct constant *c;
6084 int i;
6085
6086 for (i = 0; i < NR_C_MODES; i++)
6087 if (constant_modes[i] == mode)
6088 break;
6089 gcc_assert (i != NR_C_MODES);
6090
6091 for (c = pool->constants[i]; c != NULL; c = c->next)
6092 if (rtx_equal_p (val, c->value))
6093 break;
6094
6095 if (c == NULL)
6096 {
6097 c = (struct constant *) xmalloc (sizeof *c);
6098 c->value = val;
6099 c->label = gen_label_rtx ();
6100 c->next = pool->constants[i];
6101 pool->constants[i] = c;
6102 pool->size += GET_MODE_SIZE (mode);
6103 }
6104 }
6105
6106 /* Return an rtx that represents the offset of X from the start of
6107 pool POOL. */
6108
6109 static rtx
6110 s390_pool_offset (struct constant_pool *pool, rtx x)
6111 {
6112 rtx label;
6113
6114 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6115 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6116 UNSPEC_POOL_OFFSET);
6117 return gen_rtx_CONST (GET_MODE (x), x);
6118 }
6119
6120 /* Find constant VAL of mode MODE in the constant pool POOL.
6121 Return an RTX describing the distance from the start of
6122 the pool to the location of the new constant. */
6123
6124 static rtx
6125 s390_find_constant (struct constant_pool *pool, rtx val,
6126 enum machine_mode mode)
6127 {
6128 struct constant *c;
6129 int i;
6130
6131 for (i = 0; i < NR_C_MODES; i++)
6132 if (constant_modes[i] == mode)
6133 break;
6134 gcc_assert (i != NR_C_MODES);
6135
6136 for (c = pool->constants[i]; c != NULL; c = c->next)
6137 if (rtx_equal_p (val, c->value))
6138 break;
6139
6140 gcc_assert (c);
6141
6142 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6143 }
6144
6145 /* Check whether INSN is an execute. Return the label_ref to its
6146 execute target template if so, NULL_RTX otherwise. */
6147
6148 static rtx
6149 s390_execute_label (rtx insn)
6150 {
6151 if (GET_CODE (insn) == INSN
6152 && GET_CODE (PATTERN (insn)) == PARALLEL
6153 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6154 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6155 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6156
6157 return NULL_RTX;
6158 }
6159
6160 /* Add execute target for INSN to the constant pool POOL. */
6161
6162 static void
6163 s390_add_execute (struct constant_pool *pool, rtx insn)
6164 {
6165 struct constant *c;
6166
6167 for (c = pool->execute; c != NULL; c = c->next)
6168 if (INSN_UID (insn) == INSN_UID (c->value))
6169 break;
6170
6171 if (c == NULL)
6172 {
6173 c = (struct constant *) xmalloc (sizeof *c);
6174 c->value = insn;
6175 c->label = gen_label_rtx ();
6176 c->next = pool->execute;
6177 pool->execute = c;
6178 pool->size += 6;
6179 }
6180 }
6181
6182 /* Find execute target for INSN in the constant pool POOL.
6183 Return an RTX describing the distance from the start of
6184 the pool to the location of the execute target. */
6185
6186 static rtx
6187 s390_find_execute (struct constant_pool *pool, rtx insn)
6188 {
6189 struct constant *c;
6190
6191 for (c = pool->execute; c != NULL; c = c->next)
6192 if (INSN_UID (insn) == INSN_UID (c->value))
6193 break;
6194
6195 gcc_assert (c);
6196
6197 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6198 }
6199
6200 /* For an execute INSN, extract the execute target template. */
6201
6202 static rtx
6203 s390_execute_target (rtx insn)
6204 {
6205 rtx pattern = PATTERN (insn);
6206 gcc_assert (s390_execute_label (insn));
6207
6208 if (XVECLEN (pattern, 0) == 2)
6209 {
6210 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6211 }
6212 else
6213 {
6214 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6215 int i;
6216
6217 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6218 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6219
6220 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6221 }
6222
6223 return pattern;
6224 }
6225
6226 /* Indicate that INSN cannot be duplicated. This is the case for
6227 execute insns that carry a unique label. */
6228
6229 static bool
6230 s390_cannot_copy_insn_p (rtx insn)
6231 {
6232 rtx label = s390_execute_label (insn);
6233 return label && label != const0_rtx;
6234 }
6235
6236 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6237 do not emit the pool base label. */
6238
6239 static void
6240 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6241 {
6242 struct constant *c;
6243 rtx insn = pool->pool_insn;
6244 int i;
6245
6246 /* Switch to rodata section. */
6247 if (TARGET_CPU_ZARCH)
6248 {
6249 insn = emit_insn_after (gen_pool_section_start (), insn);
6250 INSN_ADDRESSES_NEW (insn, -1);
6251 }
6252
6253 /* Ensure minimum pool alignment. */
6254 if (TARGET_CPU_ZARCH)
6255 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6256 else
6257 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6258 INSN_ADDRESSES_NEW (insn, -1);
6259
6260 /* Emit pool base label. */
6261 if (!remote_label)
6262 {
6263 insn = emit_label_after (pool->label, insn);
6264 INSN_ADDRESSES_NEW (insn, -1);
6265 }
6266
6267 /* Dump constants in descending alignment requirement order,
6268 ensuring proper alignment for every constant. */
6269 for (i = 0; i < NR_C_MODES; i++)
6270 for (c = pool->constants[i]; c; c = c->next)
6271 {
6272 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6273 rtx value = copy_rtx (c->value);
6274 if (GET_CODE (value) == CONST
6275 && GET_CODE (XEXP (value, 0)) == UNSPEC
6276 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6277 && XVECLEN (XEXP (value, 0), 0) == 1)
6278 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6279
6280 insn = emit_label_after (c->label, insn);
6281 INSN_ADDRESSES_NEW (insn, -1);
6282
6283 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6284 gen_rtvec (1, value),
6285 UNSPECV_POOL_ENTRY);
6286 insn = emit_insn_after (value, insn);
6287 INSN_ADDRESSES_NEW (insn, -1);
6288 }
6289
6290 /* Ensure minimum alignment for instructions. */
6291 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6292 INSN_ADDRESSES_NEW (insn, -1);
6293
6294 /* Output in-pool execute template insns. */
6295 for (c = pool->execute; c; c = c->next)
6296 {
6297 insn = emit_label_after (c->label, insn);
6298 INSN_ADDRESSES_NEW (insn, -1);
6299
6300 insn = emit_insn_after (s390_execute_target (c->value), insn);
6301 INSN_ADDRESSES_NEW (insn, -1);
6302 }
6303
6304 /* Switch back to previous section. */
6305 if (TARGET_CPU_ZARCH)
6306 {
6307 insn = emit_insn_after (gen_pool_section_end (), insn);
6308 INSN_ADDRESSES_NEW (insn, -1);
6309 }
6310
6311 insn = emit_barrier_after (insn);
6312 INSN_ADDRESSES_NEW (insn, -1);
6313
6314 /* Remove placeholder insn. */
6315 remove_insn (pool->pool_insn);
6316 }
6317
6318 /* Free all memory used by POOL. */
6319
6320 static void
6321 s390_free_pool (struct constant_pool *pool)
6322 {
6323 struct constant *c, *next;
6324 int i;
6325
6326 for (i = 0; i < NR_C_MODES; i++)
6327 for (c = pool->constants[i]; c; c = next)
6328 {
6329 next = c->next;
6330 free (c);
6331 }
6332
6333 for (c = pool->execute; c; c = next)
6334 {
6335 next = c->next;
6336 free (c);
6337 }
6338
6339 BITMAP_FREE (pool->insns);
6340 free (pool);
6341 }
6342
6343
6344 /* Collect main literal pool. Return NULL on overflow. */
6345
6346 static struct constant_pool *
6347 s390_mainpool_start (void)
6348 {
6349 struct constant_pool *pool;
6350 rtx insn;
6351
6352 pool = s390_alloc_pool ();
6353
6354 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6355 {
6356 if (GET_CODE (insn) == INSN
6357 && GET_CODE (PATTERN (insn)) == SET
6358 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6359 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6360 {
6361 gcc_assert (!pool->pool_insn);
6362 pool->pool_insn = insn;
6363 }
6364
6365 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6366 {
6367 s390_add_execute (pool, insn);
6368 }
6369 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6370 {
6371 rtx pool_ref = NULL_RTX;
6372 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6373 if (pool_ref)
6374 {
6375 rtx constant = get_pool_constant (pool_ref);
6376 enum machine_mode mode = get_pool_mode (pool_ref);
6377 s390_add_constant (pool, constant, mode);
6378 }
6379 }
6380
6381 /* If hot/cold partitioning is enabled we have to make sure that
6382 the literal pool is emitted in the same section where the
6383 initialization of the literal pool base pointer takes place.
6384 emit_pool_after is only used in the non-overflow case on non
6385 Z cpus where we can emit the literal pool at the end of the
6386 function body within the text section. */
6387 if (NOTE_P (insn)
6388 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6389 && !pool->emit_pool_after)
6390 pool->emit_pool_after = PREV_INSN (insn);
6391 }
6392
6393 gcc_assert (pool->pool_insn || pool->size == 0);
6394
6395 if (pool->size >= 4096)
6396 {
6397 /* We're going to chunkify the pool, so remove the main
6398 pool placeholder insn. */
6399 remove_insn (pool->pool_insn);
6400
6401 s390_free_pool (pool);
6402 pool = NULL;
6403 }
6404
6405 /* If the functions ends with the section where the literal pool
6406 should be emitted set the marker to its end. */
6407 if (pool && !pool->emit_pool_after)
6408 pool->emit_pool_after = get_last_insn ();
6409
6410 return pool;
6411 }
6412
6413 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6414 Modify the current function to output the pool constants as well as
6415 the pool register setup instruction. */
6416
6417 static void
6418 s390_mainpool_finish (struct constant_pool *pool)
6419 {
6420 rtx base_reg = cfun->machine->base_reg;
6421 rtx insn;
6422
6423 /* If the pool is empty, we're done. */
6424 if (pool->size == 0)
6425 {
6426 /* We don't actually need a base register after all. */
6427 cfun->machine->base_reg = NULL_RTX;
6428
6429 if (pool->pool_insn)
6430 remove_insn (pool->pool_insn);
6431 s390_free_pool (pool);
6432 return;
6433 }
6434
6435 /* We need correct insn addresses. */
6436 shorten_branches (get_insns ());
6437
6438 /* On zSeries, we use a LARL to load the pool register. The pool is
6439 located in the .rodata section, so we emit it after the function. */
6440 if (TARGET_CPU_ZARCH)
6441 {
6442 insn = gen_main_base_64 (base_reg, pool->label);
6443 insn = emit_insn_after (insn, pool->pool_insn);
6444 INSN_ADDRESSES_NEW (insn, -1);
6445 remove_insn (pool->pool_insn);
6446
6447 insn = get_last_insn ();
6448 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6449 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6450
6451 s390_dump_pool (pool, 0);
6452 }
6453
6454 /* On S/390, if the total size of the function's code plus literal pool
6455 does not exceed 4096 bytes, we use BASR to set up a function base
6456 pointer, and emit the literal pool at the end of the function. */
6457 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6458 + pool->size + 8 /* alignment slop */ < 4096)
6459 {
6460 insn = gen_main_base_31_small (base_reg, pool->label);
6461 insn = emit_insn_after (insn, pool->pool_insn);
6462 INSN_ADDRESSES_NEW (insn, -1);
6463 remove_insn (pool->pool_insn);
6464
6465 insn = emit_label_after (pool->label, insn);
6466 INSN_ADDRESSES_NEW (insn, -1);
6467
6468 /* emit_pool_after will be set by s390_mainpool_start to the
6469 last insn of the section where the literal pool should be
6470 emitted. */
6471 insn = pool->emit_pool_after;
6472
6473 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6474 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6475
6476 s390_dump_pool (pool, 1);
6477 }
6478
6479 /* Otherwise, we emit an inline literal pool and use BASR to branch
6480 over it, setting up the pool register at the same time. */
6481 else
6482 {
6483 rtx pool_end = gen_label_rtx ();
6484
6485 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6486 insn = emit_jump_insn_after (insn, pool->pool_insn);
6487 JUMP_LABEL (insn) = pool_end;
6488 INSN_ADDRESSES_NEW (insn, -1);
6489 remove_insn (pool->pool_insn);
6490
6491 insn = emit_label_after (pool->label, insn);
6492 INSN_ADDRESSES_NEW (insn, -1);
6493
6494 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6495 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6496
6497 insn = emit_label_after (pool_end, pool->pool_insn);
6498 INSN_ADDRESSES_NEW (insn, -1);
6499
6500 s390_dump_pool (pool, 1);
6501 }
6502
6503
6504 /* Replace all literal pool references. */
6505
6506 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6507 {
6508 if (INSN_P (insn))
6509 replace_ltrel_base (&PATTERN (insn));
6510
6511 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6512 {
6513 rtx addr, pool_ref = NULL_RTX;
6514 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6515 if (pool_ref)
6516 {
6517 if (s390_execute_label (insn))
6518 addr = s390_find_execute (pool, insn);
6519 else
6520 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6521 get_pool_mode (pool_ref));
6522
6523 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6524 INSN_CODE (insn) = -1;
6525 }
6526 }
6527 }
6528
6529
6530 /* Free the pool. */
6531 s390_free_pool (pool);
6532 }
6533
6534 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6535 We have decided we cannot use this pool, so revert all changes
6536 to the current function that were done by s390_mainpool_start. */
6537 static void
6538 s390_mainpool_cancel (struct constant_pool *pool)
6539 {
6540 /* We didn't actually change the instruction stream, so simply
6541 free the pool memory. */
6542 s390_free_pool (pool);
6543 }
6544
6545
6546 /* Chunkify the literal pool. */
6547
6548 #define S390_POOL_CHUNK_MIN 0xc00
6549 #define S390_POOL_CHUNK_MAX 0xe00
6550
6551 static struct constant_pool *
6552 s390_chunkify_start (void)
6553 {
6554 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6555 int extra_size = 0;
6556 bitmap far_labels;
6557 rtx pending_ltrel = NULL_RTX;
6558 rtx insn;
6559
6560 rtx (*gen_reload_base) (rtx, rtx) =
6561 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6562
6563
6564 /* We need correct insn addresses. */
6565
6566 shorten_branches (get_insns ());
6567
6568 /* Scan all insns and move literals to pool chunks. */
6569
6570 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6571 {
6572 bool section_switch_p = false;
6573
6574 /* Check for pending LTREL_BASE. */
6575 if (INSN_P (insn))
6576 {
6577 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6578 if (ltrel_base)
6579 {
6580 gcc_assert (ltrel_base == pending_ltrel);
6581 pending_ltrel = NULL_RTX;
6582 }
6583 }
6584
6585 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6586 {
6587 if (!curr_pool)
6588 curr_pool = s390_start_pool (&pool_list, insn);
6589
6590 s390_add_execute (curr_pool, insn);
6591 s390_add_pool_insn (curr_pool, insn);
6592 }
6593 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6594 {
6595 rtx pool_ref = NULL_RTX;
6596 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6597 if (pool_ref)
6598 {
6599 rtx constant = get_pool_constant (pool_ref);
6600 enum machine_mode mode = get_pool_mode (pool_ref);
6601
6602 if (!curr_pool)
6603 curr_pool = s390_start_pool (&pool_list, insn);
6604
6605 s390_add_constant (curr_pool, constant, mode);
6606 s390_add_pool_insn (curr_pool, insn);
6607
6608 /* Don't split the pool chunk between a LTREL_OFFSET load
6609 and the corresponding LTREL_BASE. */
6610 if (GET_CODE (constant) == CONST
6611 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6612 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6613 {
6614 gcc_assert (!pending_ltrel);
6615 pending_ltrel = pool_ref;
6616 }
6617 }
6618 }
6619
6620 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6621 {
6622 if (curr_pool)
6623 s390_add_pool_insn (curr_pool, insn);
6624 /* An LTREL_BASE must follow within the same basic block. */
6625 gcc_assert (!pending_ltrel);
6626 }
6627
6628 if (NOTE_P (insn))
6629 switch (NOTE_KIND (insn))
6630 {
6631 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6632 section_switch_p = true;
6633 break;
6634 case NOTE_INSN_VAR_LOCATION:
6635 case NOTE_INSN_CALL_ARG_LOCATION:
6636 continue;
6637 default:
6638 break;
6639 }
6640
6641 if (!curr_pool
6642 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6643 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6644 continue;
6645
6646 if (TARGET_CPU_ZARCH)
6647 {
6648 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6649 continue;
6650
6651 s390_end_pool (curr_pool, NULL_RTX);
6652 curr_pool = NULL;
6653 }
6654 else
6655 {
6656 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6657 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6658 + extra_size;
6659
6660 /* We will later have to insert base register reload insns.
6661 Those will have an effect on code size, which we need to
6662 consider here. This calculation makes rather pessimistic
6663 worst-case assumptions. */
6664 if (GET_CODE (insn) == CODE_LABEL)
6665 extra_size += 6;
6666
6667 if (chunk_size < S390_POOL_CHUNK_MIN
6668 && curr_pool->size < S390_POOL_CHUNK_MIN
6669 && !section_switch_p)
6670 continue;
6671
6672 /* Pool chunks can only be inserted after BARRIERs ... */
6673 if (GET_CODE (insn) == BARRIER)
6674 {
6675 s390_end_pool (curr_pool, insn);
6676 curr_pool = NULL;
6677 extra_size = 0;
6678 }
6679
6680 /* ... so if we don't find one in time, create one. */
6681 else if (chunk_size > S390_POOL_CHUNK_MAX
6682 || curr_pool->size > S390_POOL_CHUNK_MAX
6683 || section_switch_p)
6684 {
6685 rtx label, jump, barrier, next, prev;
6686
6687 if (!section_switch_p)
6688 {
6689 /* We can insert the barrier only after a 'real' insn. */
6690 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6691 continue;
6692 if (get_attr_length (insn) == 0)
6693 continue;
6694 /* Don't separate LTREL_BASE from the corresponding
6695 LTREL_OFFSET load. */
6696 if (pending_ltrel)
6697 continue;
6698 next = insn;
6699 do
6700 {
6701 insn = next;
6702 next = NEXT_INSN (insn);
6703 }
6704 while (next
6705 && NOTE_P (next)
6706 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6707 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6708 }
6709 else
6710 {
6711 gcc_assert (!pending_ltrel);
6712
6713 /* The old pool has to end before the section switch
6714 note in order to make it part of the current
6715 section. */
6716 insn = PREV_INSN (insn);
6717 }
6718
6719 label = gen_label_rtx ();
6720 prev = insn;
6721 if (prev && NOTE_P (prev))
6722 prev = prev_nonnote_insn (prev);
6723 if (prev)
6724 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6725 INSN_LOCATOR (prev));
6726 else
6727 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6728 barrier = emit_barrier_after (jump);
6729 insn = emit_label_after (label, barrier);
6730 JUMP_LABEL (jump) = label;
6731 LABEL_NUSES (label) = 1;
6732
6733 INSN_ADDRESSES_NEW (jump, -1);
6734 INSN_ADDRESSES_NEW (barrier, -1);
6735 INSN_ADDRESSES_NEW (insn, -1);
6736
6737 s390_end_pool (curr_pool, barrier);
6738 curr_pool = NULL;
6739 extra_size = 0;
6740 }
6741 }
6742 }
6743
6744 if (curr_pool)
6745 s390_end_pool (curr_pool, NULL_RTX);
6746 gcc_assert (!pending_ltrel);
6747
6748 /* Find all labels that are branched into
6749 from an insn belonging to a different chunk. */
6750
6751 far_labels = BITMAP_ALLOC (NULL);
6752
6753 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6754 {
6755 /* Labels marked with LABEL_PRESERVE_P can be target
6756 of non-local jumps, so we have to mark them.
6757 The same holds for named labels.
6758
6759 Don't do that, however, if it is the label before
6760 a jump table. */
6761
6762 if (GET_CODE (insn) == CODE_LABEL
6763 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6764 {
6765 rtx vec_insn = next_real_insn (insn);
6766 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6767 PATTERN (vec_insn) : NULL_RTX;
6768 if (!vec_pat
6769 || !(GET_CODE (vec_pat) == ADDR_VEC
6770 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6771 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6772 }
6773
6774 /* If we have a direct jump (conditional or unconditional)
6775 or a casesi jump, check all potential targets. */
6776 else if (GET_CODE (insn) == JUMP_INSN)
6777 {
6778 rtx pat = PATTERN (insn);
6779 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6780 pat = XVECEXP (pat, 0, 0);
6781
6782 if (GET_CODE (pat) == SET)
6783 {
6784 rtx label = JUMP_LABEL (insn);
6785 if (label)
6786 {
6787 if (s390_find_pool (pool_list, label)
6788 != s390_find_pool (pool_list, insn))
6789 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6790 }
6791 }
6792 else if (GET_CODE (pat) == PARALLEL
6793 && XVECLEN (pat, 0) == 2
6794 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6795 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6796 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6797 {
6798 /* Find the jump table used by this casesi jump. */
6799 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6800 rtx vec_insn = next_real_insn (vec_label);
6801 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6802 PATTERN (vec_insn) : NULL_RTX;
6803 if (vec_pat
6804 && (GET_CODE (vec_pat) == ADDR_VEC
6805 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6806 {
6807 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6808
6809 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6810 {
6811 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6812
6813 if (s390_find_pool (pool_list, label)
6814 != s390_find_pool (pool_list, insn))
6815 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6816 }
6817 }
6818 }
6819 }
6820 }
6821
6822 /* Insert base register reload insns before every pool. */
6823
6824 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6825 {
6826 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6827 curr_pool->label);
6828 rtx insn = curr_pool->first_insn;
6829 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6830 }
6831
6832 /* Insert base register reload insns at every far label. */
6833
6834 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6835 if (GET_CODE (insn) == CODE_LABEL
6836 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6837 {
6838 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6839 if (pool)
6840 {
6841 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6842 pool->label);
6843 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6844 }
6845 }
6846
6847
6848 BITMAP_FREE (far_labels);
6849
6850
6851 /* Recompute insn addresses. */
6852
6853 init_insn_lengths ();
6854 shorten_branches (get_insns ());
6855
6856 return pool_list;
6857 }
6858
6859 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6860 After we have decided to use this list, finish implementing
6861 all changes to the current function as required. */
6862
6863 static void
6864 s390_chunkify_finish (struct constant_pool *pool_list)
6865 {
6866 struct constant_pool *curr_pool = NULL;
6867 rtx insn;
6868
6869
6870 /* Replace all literal pool references. */
6871
6872 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6873 {
6874 if (INSN_P (insn))
6875 replace_ltrel_base (&PATTERN (insn));
6876
6877 curr_pool = s390_find_pool (pool_list, insn);
6878 if (!curr_pool)
6879 continue;
6880
6881 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6882 {
6883 rtx addr, pool_ref = NULL_RTX;
6884 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6885 if (pool_ref)
6886 {
6887 if (s390_execute_label (insn))
6888 addr = s390_find_execute (curr_pool, insn);
6889 else
6890 addr = s390_find_constant (curr_pool,
6891 get_pool_constant (pool_ref),
6892 get_pool_mode (pool_ref));
6893
6894 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6895 INSN_CODE (insn) = -1;
6896 }
6897 }
6898 }
6899
6900 /* Dump out all literal pools. */
6901
6902 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6903 s390_dump_pool (curr_pool, 0);
6904
6905 /* Free pool list. */
6906
6907 while (pool_list)
6908 {
6909 struct constant_pool *next = pool_list->next;
6910 s390_free_pool (pool_list);
6911 pool_list = next;
6912 }
6913 }
6914
6915 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6916 We have decided we cannot use this list, so revert all changes
6917 to the current function that were done by s390_chunkify_start. */
6918
6919 static void
6920 s390_chunkify_cancel (struct constant_pool *pool_list)
6921 {
6922 struct constant_pool *curr_pool = NULL;
6923 rtx insn;
6924
6925 /* Remove all pool placeholder insns. */
6926
6927 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6928 {
6929 /* Did we insert an extra barrier? Remove it. */
6930 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6931 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6932 rtx label = NEXT_INSN (curr_pool->pool_insn);
6933
6934 if (jump && GET_CODE (jump) == JUMP_INSN
6935 && barrier && GET_CODE (barrier) == BARRIER
6936 && label && GET_CODE (label) == CODE_LABEL
6937 && GET_CODE (PATTERN (jump)) == SET
6938 && SET_DEST (PATTERN (jump)) == pc_rtx
6939 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6940 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6941 {
6942 remove_insn (jump);
6943 remove_insn (barrier);
6944 remove_insn (label);
6945 }
6946
6947 remove_insn (curr_pool->pool_insn);
6948 }
6949
6950 /* Remove all base register reload insns. */
6951
6952 for (insn = get_insns (); insn; )
6953 {
6954 rtx next_insn = NEXT_INSN (insn);
6955
6956 if (GET_CODE (insn) == INSN
6957 && GET_CODE (PATTERN (insn)) == SET
6958 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6959 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6960 remove_insn (insn);
6961
6962 insn = next_insn;
6963 }
6964
6965 /* Free pool list. */
6966
6967 while (pool_list)
6968 {
6969 struct constant_pool *next = pool_list->next;
6970 s390_free_pool (pool_list);
6971 pool_list = next;
6972 }
6973 }
6974
6975 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6976
6977 void
6978 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6979 {
6980 REAL_VALUE_TYPE r;
6981
6982 switch (GET_MODE_CLASS (mode))
6983 {
6984 case MODE_FLOAT:
6985 case MODE_DECIMAL_FLOAT:
6986 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6987
6988 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6989 assemble_real (r, mode, align);
6990 break;
6991
6992 case MODE_INT:
6993 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6994 mark_symbol_refs_as_used (exp);
6995 break;
6996
6997 default:
6998 gcc_unreachable ();
6999 }
7000 }
7001
7002
7003 /* Return an RTL expression representing the value of the return address
7004 for the frame COUNT steps up from the current frame. FRAME is the
7005 frame pointer of that frame. */
7006
7007 rtx
7008 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7009 {
7010 int offset;
7011 rtx addr;
7012
7013 /* Without backchain, we fail for all but the current frame. */
7014
7015 if (!TARGET_BACKCHAIN && count > 0)
7016 return NULL_RTX;
7017
7018 /* For the current frame, we need to make sure the initial
7019 value of RETURN_REGNUM is actually saved. */
7020
7021 if (count == 0)
7022 {
7023 /* On non-z architectures branch splitting could overwrite r14. */
7024 if (TARGET_CPU_ZARCH)
7025 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7026 else
7027 {
7028 cfun_frame_layout.save_return_addr_p = true;
7029 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7030 }
7031 }
7032
7033 if (TARGET_PACKED_STACK)
7034 offset = -2 * UNITS_PER_LONG;
7035 else
7036 offset = RETURN_REGNUM * UNITS_PER_LONG;
7037
7038 addr = plus_constant (Pmode, frame, offset);
7039 addr = memory_address (Pmode, addr);
7040 return gen_rtx_MEM (Pmode, addr);
7041 }
7042
7043 /* Return an RTL expression representing the back chain stored in
7044 the current stack frame. */
7045
7046 rtx
7047 s390_back_chain_rtx (void)
7048 {
7049 rtx chain;
7050
7051 gcc_assert (TARGET_BACKCHAIN);
7052
7053 if (TARGET_PACKED_STACK)
7054 chain = plus_constant (Pmode, stack_pointer_rtx,
7055 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7056 else
7057 chain = stack_pointer_rtx;
7058
7059 chain = gen_rtx_MEM (Pmode, chain);
7060 return chain;
7061 }
7062
7063 /* Find first call clobbered register unused in a function.
7064 This could be used as base register in a leaf function
7065 or for holding the return address before epilogue. */
7066
7067 static int
7068 find_unused_clobbered_reg (void)
7069 {
7070 int i;
7071 for (i = 0; i < 6; i++)
7072 if (!df_regs_ever_live_p (i))
7073 return i;
7074 return 0;
7075 }
7076
7077
7078 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7079 clobbered hard regs in SETREG. */
7080
7081 static void
7082 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7083 {
7084 int *regs_ever_clobbered = (int *)data;
7085 unsigned int i, regno;
7086 enum machine_mode mode = GET_MODE (setreg);
7087
7088 if (GET_CODE (setreg) == SUBREG)
7089 {
7090 rtx inner = SUBREG_REG (setreg);
7091 if (!GENERAL_REG_P (inner))
7092 return;
7093 regno = subreg_regno (setreg);
7094 }
7095 else if (GENERAL_REG_P (setreg))
7096 regno = REGNO (setreg);
7097 else
7098 return;
7099
7100 for (i = regno;
7101 i < regno + HARD_REGNO_NREGS (regno, mode);
7102 i++)
7103 regs_ever_clobbered[i] = 1;
7104 }
7105
7106 /* Walks through all basic blocks of the current function looking
7107 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7108 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7109 each of those regs. */
7110
7111 static void
7112 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7113 {
7114 basic_block cur_bb;
7115 rtx cur_insn;
7116 unsigned int i;
7117
7118 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7119
7120 /* For non-leaf functions we have to consider all call clobbered regs to be
7121 clobbered. */
7122 if (!current_function_is_leaf)
7123 {
7124 for (i = 0; i < 16; i++)
7125 regs_ever_clobbered[i] = call_really_used_regs[i];
7126 }
7127
7128 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7129 this work is done by liveness analysis (mark_regs_live_at_end).
7130 Special care is needed for functions containing landing pads. Landing pads
7131 may use the eh registers, but the code which sets these registers is not
7132 contained in that function. Hence s390_regs_ever_clobbered is not able to
7133 deal with this automatically. */
7134 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7135 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7136 if (crtl->calls_eh_return
7137 || (cfun->machine->has_landing_pad_p
7138 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7139 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7140
7141 /* For nonlocal gotos all call-saved registers have to be saved.
7142 This flag is also set for the unwinding code in libgcc.
7143 See expand_builtin_unwind_init. For regs_ever_live this is done by
7144 reload. */
7145 if (cfun->has_nonlocal_label)
7146 for (i = 0; i < 16; i++)
7147 if (!call_really_used_regs[i])
7148 regs_ever_clobbered[i] = 1;
7149
7150 FOR_EACH_BB (cur_bb)
7151 {
7152 FOR_BB_INSNS (cur_bb, cur_insn)
7153 {
7154 if (INSN_P (cur_insn))
7155 note_stores (PATTERN (cur_insn),
7156 s390_reg_clobbered_rtx,
7157 regs_ever_clobbered);
7158 }
7159 }
7160 }
7161
7162 /* Determine the frame area which actually has to be accessed
7163 in the function epilogue. The values are stored at the
7164 given pointers AREA_BOTTOM (address of the lowest used stack
7165 address) and AREA_TOP (address of the first item which does
7166 not belong to the stack frame). */
7167
7168 static void
7169 s390_frame_area (int *area_bottom, int *area_top)
7170 {
7171 int b, t;
7172 int i;
7173
7174 b = INT_MAX;
7175 t = INT_MIN;
7176
7177 if (cfun_frame_layout.first_restore_gpr != -1)
7178 {
7179 b = (cfun_frame_layout.gprs_offset
7180 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7181 t = b + (cfun_frame_layout.last_restore_gpr
7182 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7183 }
7184
7185 if (TARGET_64BIT && cfun_save_high_fprs_p)
7186 {
7187 b = MIN (b, cfun_frame_layout.f8_offset);
7188 t = MAX (t, (cfun_frame_layout.f8_offset
7189 + cfun_frame_layout.high_fprs * 8));
7190 }
7191
7192 if (!TARGET_64BIT)
7193 for (i = 2; i < 4; i++)
7194 if (cfun_fpr_bit_p (i))
7195 {
7196 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7197 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7198 }
7199
7200 *area_bottom = b;
7201 *area_top = t;
7202 }
7203
7204 /* Fill cfun->machine with info about register usage of current function.
7205 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7206
7207 static void
7208 s390_register_info (int clobbered_regs[])
7209 {
7210 int i, j;
7211
7212 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7213 cfun_frame_layout.fpr_bitmap = 0;
7214 cfun_frame_layout.high_fprs = 0;
7215 if (TARGET_64BIT)
7216 for (i = 24; i < 32; i++)
7217 if (df_regs_ever_live_p (i) && !global_regs[i])
7218 {
7219 cfun_set_fpr_bit (i - 16);
7220 cfun_frame_layout.high_fprs++;
7221 }
7222
7223 /* Find first and last gpr to be saved. We trust regs_ever_live
7224 data, except that we don't save and restore global registers.
7225
7226 Also, all registers with special meaning to the compiler need
7227 to be handled extra. */
7228
7229 s390_regs_ever_clobbered (clobbered_regs);
7230
7231 for (i = 0; i < 16; i++)
7232 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7233
7234 if (frame_pointer_needed)
7235 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7236
7237 if (flag_pic)
7238 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7239 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7240
7241 clobbered_regs[BASE_REGNUM]
7242 |= (cfun->machine->base_reg
7243 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7244
7245 clobbered_regs[RETURN_REGNUM]
7246 |= (!current_function_is_leaf
7247 || TARGET_TPF_PROFILING
7248 || cfun->machine->split_branches_pending_p
7249 || cfun_frame_layout.save_return_addr_p
7250 || crtl->calls_eh_return
7251 || cfun->stdarg);
7252
7253 clobbered_regs[STACK_POINTER_REGNUM]
7254 |= (!current_function_is_leaf
7255 || TARGET_TPF_PROFILING
7256 || cfun_save_high_fprs_p
7257 || get_frame_size () > 0
7258 || cfun->calls_alloca
7259 || cfun->stdarg);
7260
7261 for (i = 6; i < 16; i++)
7262 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7263 break;
7264 for (j = 15; j > i; j--)
7265 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7266 break;
7267
7268 if (i == 16)
7269 {
7270 /* Nothing to save/restore. */
7271 cfun_frame_layout.first_save_gpr_slot = -1;
7272 cfun_frame_layout.last_save_gpr_slot = -1;
7273 cfun_frame_layout.first_save_gpr = -1;
7274 cfun_frame_layout.first_restore_gpr = -1;
7275 cfun_frame_layout.last_save_gpr = -1;
7276 cfun_frame_layout.last_restore_gpr = -1;
7277 }
7278 else
7279 {
7280 /* Save slots for gprs from i to j. */
7281 cfun_frame_layout.first_save_gpr_slot = i;
7282 cfun_frame_layout.last_save_gpr_slot = j;
7283
7284 for (i = cfun_frame_layout.first_save_gpr_slot;
7285 i < cfun_frame_layout.last_save_gpr_slot + 1;
7286 i++)
7287 if (clobbered_regs[i])
7288 break;
7289
7290 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7291 if (clobbered_regs[j])
7292 break;
7293
7294 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7295 {
7296 /* Nothing to save/restore. */
7297 cfun_frame_layout.first_save_gpr = -1;
7298 cfun_frame_layout.first_restore_gpr = -1;
7299 cfun_frame_layout.last_save_gpr = -1;
7300 cfun_frame_layout.last_restore_gpr = -1;
7301 }
7302 else
7303 {
7304 /* Save / Restore from gpr i to j. */
7305 cfun_frame_layout.first_save_gpr = i;
7306 cfun_frame_layout.first_restore_gpr = i;
7307 cfun_frame_layout.last_save_gpr = j;
7308 cfun_frame_layout.last_restore_gpr = j;
7309 }
7310 }
7311
7312 if (cfun->stdarg)
7313 {
7314 /* Varargs functions need to save gprs 2 to 6. */
7315 if (cfun->va_list_gpr_size
7316 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7317 {
7318 int min_gpr = crtl->args.info.gprs;
7319 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7320 if (max_gpr > GP_ARG_NUM_REG)
7321 max_gpr = GP_ARG_NUM_REG;
7322
7323 if (cfun_frame_layout.first_save_gpr == -1
7324 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7325 {
7326 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7327 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7328 }
7329
7330 if (cfun_frame_layout.last_save_gpr == -1
7331 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7332 {
7333 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7334 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7335 }
7336 }
7337
7338 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7339 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7340 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7341 {
7342 int min_fpr = crtl->args.info.fprs;
7343 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7344 if (max_fpr > FP_ARG_NUM_REG)
7345 max_fpr = FP_ARG_NUM_REG;
7346
7347 /* ??? This is currently required to ensure proper location
7348 of the fpr save slots within the va_list save area. */
7349 if (TARGET_PACKED_STACK)
7350 min_fpr = 0;
7351
7352 for (i = min_fpr; i < max_fpr; i++)
7353 cfun_set_fpr_bit (i);
7354 }
7355 }
7356
7357 if (!TARGET_64BIT)
7358 for (i = 2; i < 4; i++)
7359 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7360 cfun_set_fpr_bit (i);
7361 }
7362
7363 /* Fill cfun->machine with info about frame of current function. */
7364
7365 static void
7366 s390_frame_info (void)
7367 {
7368 int i;
7369
7370 cfun_frame_layout.frame_size = get_frame_size ();
7371 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7372 fatal_error ("total size of local variables exceeds architecture limit");
7373
7374 if (!TARGET_PACKED_STACK)
7375 {
7376 cfun_frame_layout.backchain_offset = 0;
7377 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7378 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7379 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7380 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7381 * UNITS_PER_LONG);
7382 }
7383 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7384 {
7385 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7386 - UNITS_PER_LONG);
7387 cfun_frame_layout.gprs_offset
7388 = (cfun_frame_layout.backchain_offset
7389 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7390 * UNITS_PER_LONG);
7391
7392 if (TARGET_64BIT)
7393 {
7394 cfun_frame_layout.f4_offset
7395 = (cfun_frame_layout.gprs_offset
7396 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7397
7398 cfun_frame_layout.f0_offset
7399 = (cfun_frame_layout.f4_offset
7400 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7401 }
7402 else
7403 {
7404 /* On 31 bit we have to care about alignment of the
7405 floating point regs to provide fastest access. */
7406 cfun_frame_layout.f0_offset
7407 = ((cfun_frame_layout.gprs_offset
7408 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7409 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7410
7411 cfun_frame_layout.f4_offset
7412 = (cfun_frame_layout.f0_offset
7413 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7414 }
7415 }
7416 else /* no backchain */
7417 {
7418 cfun_frame_layout.f4_offset
7419 = (STACK_POINTER_OFFSET
7420 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7421
7422 cfun_frame_layout.f0_offset
7423 = (cfun_frame_layout.f4_offset
7424 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7425
7426 cfun_frame_layout.gprs_offset
7427 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7428 }
7429
7430 if (current_function_is_leaf
7431 && !TARGET_TPF_PROFILING
7432 && cfun_frame_layout.frame_size == 0
7433 && !cfun_save_high_fprs_p
7434 && !cfun->calls_alloca
7435 && !cfun->stdarg)
7436 return;
7437
7438 if (!TARGET_PACKED_STACK)
7439 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7440 + crtl->outgoing_args_size
7441 + cfun_frame_layout.high_fprs * 8);
7442 else
7443 {
7444 if (TARGET_BACKCHAIN)
7445 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7446
7447 /* No alignment trouble here because f8-f15 are only saved under
7448 64 bit. */
7449 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7450 cfun_frame_layout.f4_offset),
7451 cfun_frame_layout.gprs_offset)
7452 - cfun_frame_layout.high_fprs * 8);
7453
7454 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7455
7456 for (i = 0; i < 8; i++)
7457 if (cfun_fpr_bit_p (i))
7458 cfun_frame_layout.frame_size += 8;
7459
7460 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7461
7462 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7463 the frame size to sustain 8 byte alignment of stack frames. */
7464 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7465 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7466 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7467
7468 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7469 }
7470 }
7471
7472 /* Generate frame layout. Fills in register and frame data for the current
7473 function in cfun->machine. This routine can be called multiple times;
7474 it will re-do the complete frame layout every time. */
7475
7476 static void
7477 s390_init_frame_layout (void)
7478 {
7479 HOST_WIDE_INT frame_size;
7480 int base_used;
7481 int clobbered_regs[16];
7482
7483 /* On S/390 machines, we may need to perform branch splitting, which
7484 will require both base and return address register. We have no
7485 choice but to assume we're going to need them until right at the
7486 end of the machine dependent reorg phase. */
7487 if (!TARGET_CPU_ZARCH)
7488 cfun->machine->split_branches_pending_p = true;
7489
7490 do
7491 {
7492 frame_size = cfun_frame_layout.frame_size;
7493
7494 /* Try to predict whether we'll need the base register. */
7495 base_used = cfun->machine->split_branches_pending_p
7496 || crtl->uses_const_pool
7497 || (!DISP_IN_RANGE (frame_size)
7498 && !CONST_OK_FOR_K (frame_size));
7499
7500 /* Decide which register to use as literal pool base. In small
7501 leaf functions, try to use an unused call-clobbered register
7502 as base register to avoid save/restore overhead. */
7503 if (!base_used)
7504 cfun->machine->base_reg = NULL_RTX;
7505 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7506 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7507 else
7508 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7509
7510 s390_register_info (clobbered_regs);
7511 s390_frame_info ();
7512 }
7513 while (frame_size != cfun_frame_layout.frame_size);
7514 }
7515
7516 /* Update frame layout. Recompute actual register save data based on
7517 current info and update regs_ever_live for the special registers.
7518 May be called multiple times, but may never cause *more* registers
7519 to be saved than s390_init_frame_layout allocated room for. */
7520
7521 static void
7522 s390_update_frame_layout (void)
7523 {
7524 int clobbered_regs[16];
7525
7526 s390_register_info (clobbered_regs);
7527
7528 df_set_regs_ever_live (BASE_REGNUM,
7529 clobbered_regs[BASE_REGNUM] ? true : false);
7530 df_set_regs_ever_live (RETURN_REGNUM,
7531 clobbered_regs[RETURN_REGNUM] ? true : false);
7532 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7533 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7534
7535 if (cfun->machine->base_reg)
7536 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7537 }
7538
7539 /* Return true if it is legal to put a value with MODE into REGNO. */
7540
7541 bool
7542 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7543 {
7544 switch (REGNO_REG_CLASS (regno))
7545 {
7546 case FP_REGS:
7547 if (REGNO_PAIR_OK (regno, mode))
7548 {
7549 if (mode == SImode || mode == DImode)
7550 return true;
7551
7552 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7553 return true;
7554 }
7555 break;
7556 case ADDR_REGS:
7557 if (FRAME_REGNO_P (regno) && mode == Pmode)
7558 return true;
7559
7560 /* fallthrough */
7561 case GENERAL_REGS:
7562 if (REGNO_PAIR_OK (regno, mode))
7563 {
7564 if (TARGET_ZARCH
7565 || (mode != TFmode && mode != TCmode && mode != TDmode))
7566 return true;
7567 }
7568 break;
7569 case CC_REGS:
7570 if (GET_MODE_CLASS (mode) == MODE_CC)
7571 return true;
7572 break;
7573 case ACCESS_REGS:
7574 if (REGNO_PAIR_OK (regno, mode))
7575 {
7576 if (mode == SImode || mode == Pmode)
7577 return true;
7578 }
7579 break;
7580 default:
7581 return false;
7582 }
7583
7584 return false;
7585 }
7586
7587 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7588
7589 bool
7590 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7591 {
7592 /* Once we've decided upon a register to use as base register, it must
7593 no longer be used for any other purpose. */
7594 if (cfun->machine->base_reg)
7595 if (REGNO (cfun->machine->base_reg) == old_reg
7596 || REGNO (cfun->machine->base_reg) == new_reg)
7597 return false;
7598
7599 return true;
7600 }
7601
7602 /* Maximum number of registers to represent a value of mode MODE
7603 in a register of class RCLASS. */
7604
7605 int
7606 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7607 {
7608 switch (rclass)
7609 {
7610 case FP_REGS:
7611 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7612 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7613 else
7614 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7615 case ACCESS_REGS:
7616 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7617 default:
7618 break;
7619 }
7620 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7621 }
7622
7623 /* Return true if register FROM can be eliminated via register TO. */
7624
7625 static bool
7626 s390_can_eliminate (const int from, const int to)
7627 {
7628 /* On zSeries machines, we have not marked the base register as fixed.
7629 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7630 If a function requires the base register, we say here that this
7631 elimination cannot be performed. This will cause reload to free
7632 up the base register (as if it were fixed). On the other hand,
7633 if the current function does *not* require the base register, we
7634 say here the elimination succeeds, which in turn allows reload
7635 to allocate the base register for any other purpose. */
7636 if (from == BASE_REGNUM && to == BASE_REGNUM)
7637 {
7638 if (TARGET_CPU_ZARCH)
7639 {
7640 s390_init_frame_layout ();
7641 return cfun->machine->base_reg == NULL_RTX;
7642 }
7643
7644 return false;
7645 }
7646
7647 /* Everything else must point into the stack frame. */
7648 gcc_assert (to == STACK_POINTER_REGNUM
7649 || to == HARD_FRAME_POINTER_REGNUM);
7650
7651 gcc_assert (from == FRAME_POINTER_REGNUM
7652 || from == ARG_POINTER_REGNUM
7653 || from == RETURN_ADDRESS_POINTER_REGNUM);
7654
7655 /* Make sure we actually saved the return address. */
7656 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7657 if (!crtl->calls_eh_return
7658 && !cfun->stdarg
7659 && !cfun_frame_layout.save_return_addr_p)
7660 return false;
7661
7662 return true;
7663 }
7664
7665 /* Return offset between register FROM and TO initially after prolog. */
7666
7667 HOST_WIDE_INT
7668 s390_initial_elimination_offset (int from, int to)
7669 {
7670 HOST_WIDE_INT offset;
7671 int index;
7672
7673 /* ??? Why are we called for non-eliminable pairs? */
7674 if (!s390_can_eliminate (from, to))
7675 return 0;
7676
7677 switch (from)
7678 {
7679 case FRAME_POINTER_REGNUM:
7680 offset = (get_frame_size()
7681 + STACK_POINTER_OFFSET
7682 + crtl->outgoing_args_size);
7683 break;
7684
7685 case ARG_POINTER_REGNUM:
7686 s390_init_frame_layout ();
7687 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7688 break;
7689
7690 case RETURN_ADDRESS_POINTER_REGNUM:
7691 s390_init_frame_layout ();
7692 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7693 gcc_assert (index >= 0);
7694 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7695 offset += index * UNITS_PER_LONG;
7696 break;
7697
7698 case BASE_REGNUM:
7699 offset = 0;
7700 break;
7701
7702 default:
7703 gcc_unreachable ();
7704 }
7705
7706 return offset;
7707 }
7708
7709 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7710 to register BASE. Return generated insn. */
7711
7712 static rtx
7713 save_fpr (rtx base, int offset, int regnum)
7714 {
7715 rtx addr;
7716 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7717
7718 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7719 set_mem_alias_set (addr, get_varargs_alias_set ());
7720 else
7721 set_mem_alias_set (addr, get_frame_alias_set ());
7722
7723 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7724 }
7725
7726 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7727 to register BASE. Return generated insn. */
7728
7729 static rtx
7730 restore_fpr (rtx base, int offset, int regnum)
7731 {
7732 rtx addr;
7733 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7734 set_mem_alias_set (addr, get_frame_alias_set ());
7735
7736 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7737 }
7738
7739 /* Return true if REGNO is a global register, but not one
7740 of the special ones that need to be saved/restored in anyway. */
7741
7742 static inline bool
7743 global_not_special_regno_p (int regno)
7744 {
7745 return (global_regs[regno]
7746 /* These registers are special and need to be
7747 restored in any case. */
7748 && !(regno == STACK_POINTER_REGNUM
7749 || regno == RETURN_REGNUM
7750 || regno == BASE_REGNUM
7751 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7752 }
7753
7754 /* Generate insn to save registers FIRST to LAST into
7755 the register save area located at offset OFFSET
7756 relative to register BASE. */
7757
7758 static rtx
7759 save_gprs (rtx base, int offset, int first, int last)
7760 {
7761 rtx addr, insn, note;
7762 int i;
7763
7764 addr = plus_constant (Pmode, base, offset);
7765 addr = gen_rtx_MEM (Pmode, addr);
7766
7767 set_mem_alias_set (addr, get_frame_alias_set ());
7768
7769 /* Special-case single register. */
7770 if (first == last)
7771 {
7772 if (TARGET_64BIT)
7773 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7774 else
7775 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7776
7777 if (!global_not_special_regno_p (first))
7778 RTX_FRAME_RELATED_P (insn) = 1;
7779 return insn;
7780 }
7781
7782
7783 insn = gen_store_multiple (addr,
7784 gen_rtx_REG (Pmode, first),
7785 GEN_INT (last - first + 1));
7786
7787 if (first <= 6 && cfun->stdarg)
7788 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7789 {
7790 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7791
7792 if (first + i <= 6)
7793 set_mem_alias_set (mem, get_varargs_alias_set ());
7794 }
7795
7796 /* We need to set the FRAME_RELATED flag on all SETs
7797 inside the store-multiple pattern.
7798
7799 However, we must not emit DWARF records for registers 2..5
7800 if they are stored for use by variable arguments ...
7801
7802 ??? Unfortunately, it is not enough to simply not the
7803 FRAME_RELATED flags for those SETs, because the first SET
7804 of the PARALLEL is always treated as if it had the flag
7805 set, even if it does not. Therefore we emit a new pattern
7806 without those registers as REG_FRAME_RELATED_EXPR note. */
7807
7808 if (first >= 6 && !global_not_special_regno_p (first))
7809 {
7810 rtx pat = PATTERN (insn);
7811
7812 for (i = 0; i < XVECLEN (pat, 0); i++)
7813 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7814 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7815 0, i)))))
7816 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7817
7818 RTX_FRAME_RELATED_P (insn) = 1;
7819 }
7820 else if (last >= 6)
7821 {
7822 int start;
7823
7824 for (start = first >= 6 ? first : 6; start <= last; start++)
7825 if (!global_not_special_regno_p (start))
7826 break;
7827
7828 if (start > last)
7829 return insn;
7830
7831 addr = plus_constant (Pmode, base,
7832 offset + (start - first) * UNITS_PER_LONG);
7833 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7834 gen_rtx_REG (Pmode, start),
7835 GEN_INT (last - start + 1));
7836 note = PATTERN (note);
7837
7838 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7839
7840 for (i = 0; i < XVECLEN (note, 0); i++)
7841 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7842 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7843 0, i)))))
7844 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7845
7846 RTX_FRAME_RELATED_P (insn) = 1;
7847 }
7848
7849 return insn;
7850 }
7851
7852 /* Generate insn to restore registers FIRST to LAST from
7853 the register save area located at offset OFFSET
7854 relative to register BASE. */
7855
7856 static rtx
7857 restore_gprs (rtx base, int offset, int first, int last)
7858 {
7859 rtx addr, insn;
7860
7861 addr = plus_constant (Pmode, base, offset);
7862 addr = gen_rtx_MEM (Pmode, addr);
7863 set_mem_alias_set (addr, get_frame_alias_set ());
7864
7865 /* Special-case single register. */
7866 if (first == last)
7867 {
7868 if (TARGET_64BIT)
7869 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7870 else
7871 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7872
7873 return insn;
7874 }
7875
7876 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7877 addr,
7878 GEN_INT (last - first + 1));
7879 return insn;
7880 }
7881
7882 /* Return insn sequence to load the GOT register. */
7883
7884 static GTY(()) rtx got_symbol;
7885 rtx
7886 s390_load_got (void)
7887 {
7888 rtx insns;
7889
7890 /* We cannot use pic_offset_table_rtx here since we use this
7891 function also for non-pic if __tls_get_offset is called and in
7892 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
7893 aren't usable. */
7894 rtx got_rtx = gen_rtx_REG (Pmode, 12);
7895
7896 if (!got_symbol)
7897 {
7898 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7899 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7900 }
7901
7902 start_sequence ();
7903
7904 if (TARGET_CPU_ZARCH)
7905 {
7906 emit_move_insn (got_rtx, got_symbol);
7907 }
7908 else
7909 {
7910 rtx offset;
7911
7912 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7913 UNSPEC_LTREL_OFFSET);
7914 offset = gen_rtx_CONST (Pmode, offset);
7915 offset = force_const_mem (Pmode, offset);
7916
7917 emit_move_insn (got_rtx, offset);
7918
7919 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7920 UNSPEC_LTREL_BASE);
7921 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
7922
7923 emit_move_insn (got_rtx, offset);
7924 }
7925
7926 insns = get_insns ();
7927 end_sequence ();
7928 return insns;
7929 }
7930
7931 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7932 and the change to the stack pointer. */
7933
7934 static void
7935 s390_emit_stack_tie (void)
7936 {
7937 rtx mem = gen_frame_mem (BLKmode,
7938 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7939
7940 emit_insn (gen_stack_tie (mem));
7941 }
7942
7943 /* Expand the prologue into a bunch of separate insns. */
7944
7945 void
7946 s390_emit_prologue (void)
7947 {
7948 rtx insn, addr;
7949 rtx temp_reg;
7950 int i;
7951 int offset;
7952 int next_fpr = 0;
7953
7954 /* Complete frame layout. */
7955
7956 s390_update_frame_layout ();
7957
7958 /* Annotate all constant pool references to let the scheduler know
7959 they implicitly use the base register. */
7960
7961 push_topmost_sequence ();
7962
7963 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7964 if (INSN_P (insn))
7965 {
7966 annotate_constant_pool_refs (&PATTERN (insn));
7967 df_insn_rescan (insn);
7968 }
7969
7970 pop_topmost_sequence ();
7971
7972 /* Choose best register to use for temp use within prologue.
7973 See below for why TPF must use the register 1. */
7974
7975 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7976 && !current_function_is_leaf
7977 && !TARGET_TPF_PROFILING)
7978 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7979 else
7980 temp_reg = gen_rtx_REG (Pmode, 1);
7981
7982 /* Save call saved gprs. */
7983 if (cfun_frame_layout.first_save_gpr != -1)
7984 {
7985 insn = save_gprs (stack_pointer_rtx,
7986 cfun_frame_layout.gprs_offset +
7987 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7988 - cfun_frame_layout.first_save_gpr_slot),
7989 cfun_frame_layout.first_save_gpr,
7990 cfun_frame_layout.last_save_gpr);
7991 emit_insn (insn);
7992 }
7993
7994 /* Dummy insn to mark literal pool slot. */
7995
7996 if (cfun->machine->base_reg)
7997 emit_insn (gen_main_pool (cfun->machine->base_reg));
7998
7999 offset = cfun_frame_layout.f0_offset;
8000
8001 /* Save f0 and f2. */
8002 for (i = 0; i < 2; i++)
8003 {
8004 if (cfun_fpr_bit_p (i))
8005 {
8006 save_fpr (stack_pointer_rtx, offset, i + 16);
8007 offset += 8;
8008 }
8009 else if (!TARGET_PACKED_STACK)
8010 offset += 8;
8011 }
8012
8013 /* Save f4 and f6. */
8014 offset = cfun_frame_layout.f4_offset;
8015 for (i = 2; i < 4; i++)
8016 {
8017 if (cfun_fpr_bit_p (i))
8018 {
8019 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8020 offset += 8;
8021
8022 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8023 therefore are not frame related. */
8024 if (!call_really_used_regs[i + 16])
8025 RTX_FRAME_RELATED_P (insn) = 1;
8026 }
8027 else if (!TARGET_PACKED_STACK)
8028 offset += 8;
8029 }
8030
8031 if (TARGET_PACKED_STACK
8032 && cfun_save_high_fprs_p
8033 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8034 {
8035 offset = (cfun_frame_layout.f8_offset
8036 + (cfun_frame_layout.high_fprs - 1) * 8);
8037
8038 for (i = 15; i > 7 && offset >= 0; i--)
8039 if (cfun_fpr_bit_p (i))
8040 {
8041 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8042
8043 RTX_FRAME_RELATED_P (insn) = 1;
8044 offset -= 8;
8045 }
8046 if (offset >= cfun_frame_layout.f8_offset)
8047 next_fpr = i + 16;
8048 }
8049
8050 if (!TARGET_PACKED_STACK)
8051 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8052
8053 if (flag_stack_usage_info)
8054 current_function_static_stack_size = cfun_frame_layout.frame_size;
8055
8056 /* Decrement stack pointer. */
8057
8058 if (cfun_frame_layout.frame_size > 0)
8059 {
8060 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8061 rtx real_frame_off;
8062
8063 if (s390_stack_size)
8064 {
8065 HOST_WIDE_INT stack_guard;
8066
8067 if (s390_stack_guard)
8068 stack_guard = s390_stack_guard;
8069 else
8070 {
8071 /* If no value for stack guard is provided the smallest power of 2
8072 larger than the current frame size is chosen. */
8073 stack_guard = 1;
8074 while (stack_guard < cfun_frame_layout.frame_size)
8075 stack_guard <<= 1;
8076 }
8077
8078 if (cfun_frame_layout.frame_size >= s390_stack_size)
8079 {
8080 warning (0, "frame size of function %qs is %wd"
8081 " bytes exceeding user provided stack limit of "
8082 "%d bytes. "
8083 "An unconditional trap is added.",
8084 current_function_name(), cfun_frame_layout.frame_size,
8085 s390_stack_size);
8086 emit_insn (gen_trap ());
8087 }
8088 else
8089 {
8090 /* stack_guard has to be smaller than s390_stack_size.
8091 Otherwise we would emit an AND with zero which would
8092 not match the test under mask pattern. */
8093 if (stack_guard >= s390_stack_size)
8094 {
8095 warning (0, "frame size of function %qs is %wd"
8096 " bytes which is more than half the stack size. "
8097 "The dynamic check would not be reliable. "
8098 "No check emitted for this function.",
8099 current_function_name(),
8100 cfun_frame_layout.frame_size);
8101 }
8102 else
8103 {
8104 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8105 & ~(stack_guard - 1));
8106
8107 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8108 GEN_INT (stack_check_mask));
8109 if (TARGET_64BIT)
8110 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8111 t, const0_rtx),
8112 t, const0_rtx, const0_rtx));
8113 else
8114 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8115 t, const0_rtx),
8116 t, const0_rtx, const0_rtx));
8117 }
8118 }
8119 }
8120
8121 if (s390_warn_framesize > 0
8122 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8123 warning (0, "frame size of %qs is %wd bytes",
8124 current_function_name (), cfun_frame_layout.frame_size);
8125
8126 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8127 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8128
8129 /* Save incoming stack pointer into temp reg. */
8130 if (TARGET_BACKCHAIN || next_fpr)
8131 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8132
8133 /* Subtract frame size from stack pointer. */
8134
8135 if (DISP_IN_RANGE (INTVAL (frame_off)))
8136 {
8137 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8138 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8139 frame_off));
8140 insn = emit_insn (insn);
8141 }
8142 else
8143 {
8144 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8145 frame_off = force_const_mem (Pmode, frame_off);
8146
8147 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8148 annotate_constant_pool_refs (&PATTERN (insn));
8149 }
8150
8151 RTX_FRAME_RELATED_P (insn) = 1;
8152 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8153 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8154 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8155 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8156 real_frame_off)));
8157
8158 /* Set backchain. */
8159
8160 if (TARGET_BACKCHAIN)
8161 {
8162 if (cfun_frame_layout.backchain_offset)
8163 addr = gen_rtx_MEM (Pmode,
8164 plus_constant (Pmode, stack_pointer_rtx,
8165 cfun_frame_layout.backchain_offset));
8166 else
8167 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8168 set_mem_alias_set (addr, get_frame_alias_set ());
8169 insn = emit_insn (gen_move_insn (addr, temp_reg));
8170 }
8171
8172 /* If we support non-call exceptions (e.g. for Java),
8173 we need to make sure the backchain pointer is set up
8174 before any possibly trapping memory access. */
8175 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8176 {
8177 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8178 emit_clobber (addr);
8179 }
8180 }
8181
8182 /* Save fprs 8 - 15 (64 bit ABI). */
8183
8184 if (cfun_save_high_fprs_p && next_fpr)
8185 {
8186 /* If the stack might be accessed through a different register
8187 we have to make sure that the stack pointer decrement is not
8188 moved below the use of the stack slots. */
8189 s390_emit_stack_tie ();
8190
8191 insn = emit_insn (gen_add2_insn (temp_reg,
8192 GEN_INT (cfun_frame_layout.f8_offset)));
8193
8194 offset = 0;
8195
8196 for (i = 24; i <= next_fpr; i++)
8197 if (cfun_fpr_bit_p (i - 16))
8198 {
8199 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8200 cfun_frame_layout.frame_size
8201 + cfun_frame_layout.f8_offset
8202 + offset);
8203
8204 insn = save_fpr (temp_reg, offset, i);
8205 offset += 8;
8206 RTX_FRAME_RELATED_P (insn) = 1;
8207 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8208 gen_rtx_SET (VOIDmode,
8209 gen_rtx_MEM (DFmode, addr),
8210 gen_rtx_REG (DFmode, i)));
8211 }
8212 }
8213
8214 /* Set frame pointer, if needed. */
8215
8216 if (frame_pointer_needed)
8217 {
8218 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8219 RTX_FRAME_RELATED_P (insn) = 1;
8220 }
8221
8222 /* Set up got pointer, if needed. */
8223
8224 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8225 {
8226 rtx insns = s390_load_got ();
8227
8228 for (insn = insns; insn; insn = NEXT_INSN (insn))
8229 annotate_constant_pool_refs (&PATTERN (insn));
8230
8231 emit_insn (insns);
8232 }
8233
8234 if (TARGET_TPF_PROFILING)
8235 {
8236 /* Generate a BAS instruction to serve as a function
8237 entry intercept to facilitate the use of tracing
8238 algorithms located at the branch target. */
8239 emit_insn (gen_prologue_tpf ());
8240
8241 /* Emit a blockage here so that all code
8242 lies between the profiling mechanisms. */
8243 emit_insn (gen_blockage ());
8244 }
8245 }
8246
8247 /* Expand the epilogue into a bunch of separate insns. */
8248
8249 void
8250 s390_emit_epilogue (bool sibcall)
8251 {
8252 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8253 int area_bottom, area_top, offset = 0;
8254 int next_offset;
8255 rtvec p;
8256 int i;
8257
8258 if (TARGET_TPF_PROFILING)
8259 {
8260
8261 /* Generate a BAS instruction to serve as a function
8262 entry intercept to facilitate the use of tracing
8263 algorithms located at the branch target. */
8264
8265 /* Emit a blockage here so that all code
8266 lies between the profiling mechanisms. */
8267 emit_insn (gen_blockage ());
8268
8269 emit_insn (gen_epilogue_tpf ());
8270 }
8271
8272 /* Check whether to use frame or stack pointer for restore. */
8273
8274 frame_pointer = (frame_pointer_needed
8275 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8276
8277 s390_frame_area (&area_bottom, &area_top);
8278
8279 /* Check whether we can access the register save area.
8280 If not, increment the frame pointer as required. */
8281
8282 if (area_top <= area_bottom)
8283 {
8284 /* Nothing to restore. */
8285 }
8286 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8287 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8288 {
8289 /* Area is in range. */
8290 offset = cfun_frame_layout.frame_size;
8291 }
8292 else
8293 {
8294 rtx insn, frame_off, cfa;
8295
8296 offset = area_bottom < 0 ? -area_bottom : 0;
8297 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8298
8299 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8300 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8301 if (DISP_IN_RANGE (INTVAL (frame_off)))
8302 {
8303 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8304 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8305 insn = emit_insn (insn);
8306 }
8307 else
8308 {
8309 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8310 frame_off = force_const_mem (Pmode, frame_off);
8311
8312 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8313 annotate_constant_pool_refs (&PATTERN (insn));
8314 }
8315 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8316 RTX_FRAME_RELATED_P (insn) = 1;
8317 }
8318
8319 /* Restore call saved fprs. */
8320
8321 if (TARGET_64BIT)
8322 {
8323 if (cfun_save_high_fprs_p)
8324 {
8325 next_offset = cfun_frame_layout.f8_offset;
8326 for (i = 24; i < 32; i++)
8327 {
8328 if (cfun_fpr_bit_p (i - 16))
8329 {
8330 restore_fpr (frame_pointer,
8331 offset + next_offset, i);
8332 cfa_restores
8333 = alloc_reg_note (REG_CFA_RESTORE,
8334 gen_rtx_REG (DFmode, i), cfa_restores);
8335 next_offset += 8;
8336 }
8337 }
8338 }
8339
8340 }
8341 else
8342 {
8343 next_offset = cfun_frame_layout.f4_offset;
8344 for (i = 18; i < 20; i++)
8345 {
8346 if (cfun_fpr_bit_p (i - 16))
8347 {
8348 restore_fpr (frame_pointer,
8349 offset + next_offset, i);
8350 cfa_restores
8351 = alloc_reg_note (REG_CFA_RESTORE,
8352 gen_rtx_REG (DFmode, i), cfa_restores);
8353 next_offset += 8;
8354 }
8355 else if (!TARGET_PACKED_STACK)
8356 next_offset += 8;
8357 }
8358
8359 }
8360
8361 /* Return register. */
8362
8363 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8364
8365 /* Restore call saved gprs. */
8366
8367 if (cfun_frame_layout.first_restore_gpr != -1)
8368 {
8369 rtx insn, addr;
8370 int i;
8371
8372 /* Check for global register and save them
8373 to stack location from where they get restored. */
8374
8375 for (i = cfun_frame_layout.first_restore_gpr;
8376 i <= cfun_frame_layout.last_restore_gpr;
8377 i++)
8378 {
8379 if (global_not_special_regno_p (i))
8380 {
8381 addr = plus_constant (Pmode, frame_pointer,
8382 offset + cfun_frame_layout.gprs_offset
8383 + (i - cfun_frame_layout.first_save_gpr_slot)
8384 * UNITS_PER_LONG);
8385 addr = gen_rtx_MEM (Pmode, addr);
8386 set_mem_alias_set (addr, get_frame_alias_set ());
8387 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8388 }
8389 else
8390 cfa_restores
8391 = alloc_reg_note (REG_CFA_RESTORE,
8392 gen_rtx_REG (Pmode, i), cfa_restores);
8393 }
8394
8395 if (! sibcall)
8396 {
8397 /* Fetch return address from stack before load multiple,
8398 this will do good for scheduling. */
8399
8400 if (cfun_frame_layout.save_return_addr_p
8401 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8402 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8403 {
8404 int return_regnum = find_unused_clobbered_reg();
8405 if (!return_regnum)
8406 return_regnum = 4;
8407 return_reg = gen_rtx_REG (Pmode, return_regnum);
8408
8409 addr = plus_constant (Pmode, frame_pointer,
8410 offset + cfun_frame_layout.gprs_offset
8411 + (RETURN_REGNUM
8412 - cfun_frame_layout.first_save_gpr_slot)
8413 * UNITS_PER_LONG);
8414 addr = gen_rtx_MEM (Pmode, addr);
8415 set_mem_alias_set (addr, get_frame_alias_set ());
8416 emit_move_insn (return_reg, addr);
8417 }
8418 }
8419
8420 insn = restore_gprs (frame_pointer,
8421 offset + cfun_frame_layout.gprs_offset
8422 + (cfun_frame_layout.first_restore_gpr
8423 - cfun_frame_layout.first_save_gpr_slot)
8424 * UNITS_PER_LONG,
8425 cfun_frame_layout.first_restore_gpr,
8426 cfun_frame_layout.last_restore_gpr);
8427 insn = emit_insn (insn);
8428 REG_NOTES (insn) = cfa_restores;
8429 add_reg_note (insn, REG_CFA_DEF_CFA,
8430 plus_constant (Pmode, stack_pointer_rtx,
8431 STACK_POINTER_OFFSET));
8432 RTX_FRAME_RELATED_P (insn) = 1;
8433 }
8434
8435 if (! sibcall)
8436 {
8437
8438 /* Return to caller. */
8439
8440 p = rtvec_alloc (2);
8441
8442 RTVEC_ELT (p, 0) = ret_rtx;
8443 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8444 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8445 }
8446 }
8447
8448
8449 /* Return the size in bytes of a function argument of
8450 type TYPE and/or mode MODE. At least one of TYPE or
8451 MODE must be specified. */
8452
8453 static int
8454 s390_function_arg_size (enum machine_mode mode, const_tree type)
8455 {
8456 if (type)
8457 return int_size_in_bytes (type);
8458
8459 /* No type info available for some library calls ... */
8460 if (mode != BLKmode)
8461 return GET_MODE_SIZE (mode);
8462
8463 /* If we have neither type nor mode, abort */
8464 gcc_unreachable ();
8465 }
8466
8467 /* Return true if a function argument of type TYPE and mode MODE
8468 is to be passed in a floating-point register, if available. */
8469
8470 static bool
8471 s390_function_arg_float (enum machine_mode mode, const_tree type)
8472 {
8473 int size = s390_function_arg_size (mode, type);
8474 if (size > 8)
8475 return false;
8476
8477 /* Soft-float changes the ABI: no floating-point registers are used. */
8478 if (TARGET_SOFT_FLOAT)
8479 return false;
8480
8481 /* No type info available for some library calls ... */
8482 if (!type)
8483 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8484
8485 /* The ABI says that record types with a single member are treated
8486 just like that member would be. */
8487 while (TREE_CODE (type) == RECORD_TYPE)
8488 {
8489 tree field, single = NULL_TREE;
8490
8491 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8492 {
8493 if (TREE_CODE (field) != FIELD_DECL)
8494 continue;
8495
8496 if (single == NULL_TREE)
8497 single = TREE_TYPE (field);
8498 else
8499 return false;
8500 }
8501
8502 if (single == NULL_TREE)
8503 return false;
8504 else
8505 type = single;
8506 }
8507
8508 return TREE_CODE (type) == REAL_TYPE;
8509 }
8510
8511 /* Return true if a function argument of type TYPE and mode MODE
8512 is to be passed in an integer register, or a pair of integer
8513 registers, if available. */
8514
8515 static bool
8516 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8517 {
8518 int size = s390_function_arg_size (mode, type);
8519 if (size > 8)
8520 return false;
8521
8522 /* No type info available for some library calls ... */
8523 if (!type)
8524 return GET_MODE_CLASS (mode) == MODE_INT
8525 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8526
8527 /* We accept small integral (and similar) types. */
8528 if (INTEGRAL_TYPE_P (type)
8529 || POINTER_TYPE_P (type)
8530 || TREE_CODE (type) == NULLPTR_TYPE
8531 || TREE_CODE (type) == OFFSET_TYPE
8532 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8533 return true;
8534
8535 /* We also accept structs of size 1, 2, 4, 8 that are not
8536 passed in floating-point registers. */
8537 if (AGGREGATE_TYPE_P (type)
8538 && exact_log2 (size) >= 0
8539 && !s390_function_arg_float (mode, type))
8540 return true;
8541
8542 return false;
8543 }
8544
8545 /* Return 1 if a function argument of type TYPE and mode MODE
8546 is to be passed by reference. The ABI specifies that only
8547 structures of size 1, 2, 4, or 8 bytes are passed by value,
8548 all other structures (and complex numbers) are passed by
8549 reference. */
8550
8551 static bool
8552 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8553 enum machine_mode mode, const_tree type,
8554 bool named ATTRIBUTE_UNUSED)
8555 {
8556 int size = s390_function_arg_size (mode, type);
8557 if (size > 8)
8558 return true;
8559
8560 if (type)
8561 {
8562 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8563 return 1;
8564
8565 if (TREE_CODE (type) == COMPLEX_TYPE
8566 || TREE_CODE (type) == VECTOR_TYPE)
8567 return 1;
8568 }
8569
8570 return 0;
8571 }
8572
8573 /* Update the data in CUM to advance over an argument of mode MODE and
8574 data type TYPE. (TYPE is null for libcalls where that information
8575 may not be available.). The boolean NAMED specifies whether the
8576 argument is a named argument (as opposed to an unnamed argument
8577 matching an ellipsis). */
8578
8579 static void
8580 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8581 const_tree type, bool named ATTRIBUTE_UNUSED)
8582 {
8583 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8584
8585 if (s390_function_arg_float (mode, type))
8586 {
8587 cum->fprs += 1;
8588 }
8589 else if (s390_function_arg_integer (mode, type))
8590 {
8591 int size = s390_function_arg_size (mode, type);
8592 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8593 }
8594 else
8595 gcc_unreachable ();
8596 }
8597
8598 /* Define where to put the arguments to a function.
8599 Value is zero to push the argument on the stack,
8600 or a hard register in which to store the argument.
8601
8602 MODE is the argument's machine mode.
8603 TYPE is the data type of the argument (as a tree).
8604 This is null for libcalls where that information may
8605 not be available.
8606 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8607 the preceding args and about the function being called.
8608 NAMED is nonzero if this argument is a named parameter
8609 (otherwise it is an extra parameter matching an ellipsis).
8610
8611 On S/390, we use general purpose registers 2 through 6 to
8612 pass integer, pointer, and certain structure arguments, and
8613 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8614 to pass floating point arguments. All remaining arguments
8615 are pushed to the stack. */
8616
8617 static rtx
8618 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8619 const_tree type, bool named ATTRIBUTE_UNUSED)
8620 {
8621 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8622
8623 if (s390_function_arg_float (mode, type))
8624 {
8625 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8626 return 0;
8627 else
8628 return gen_rtx_REG (mode, cum->fprs + 16);
8629 }
8630 else if (s390_function_arg_integer (mode, type))
8631 {
8632 int size = s390_function_arg_size (mode, type);
8633 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8634
8635 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8636 return 0;
8637 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8638 return gen_rtx_REG (mode, cum->gprs + 2);
8639 else if (n_gprs == 2)
8640 {
8641 rtvec p = rtvec_alloc (2);
8642
8643 RTVEC_ELT (p, 0)
8644 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8645 const0_rtx);
8646 RTVEC_ELT (p, 1)
8647 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8648 GEN_INT (4));
8649
8650 return gen_rtx_PARALLEL (mode, p);
8651 }
8652 }
8653
8654 /* After the real arguments, expand_call calls us once again
8655 with a void_type_node type. Whatever we return here is
8656 passed as operand 2 to the call expanders.
8657
8658 We don't need this feature ... */
8659 else if (type == void_type_node)
8660 return const0_rtx;
8661
8662 gcc_unreachable ();
8663 }
8664
8665 /* Return true if return values of type TYPE should be returned
8666 in a memory buffer whose address is passed by the caller as
8667 hidden first argument. */
8668
8669 static bool
8670 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8671 {
8672 /* We accept small integral (and similar) types. */
8673 if (INTEGRAL_TYPE_P (type)
8674 || POINTER_TYPE_P (type)
8675 || TREE_CODE (type) == OFFSET_TYPE
8676 || TREE_CODE (type) == REAL_TYPE)
8677 return int_size_in_bytes (type) > 8;
8678
8679 /* Aggregates and similar constructs are always returned
8680 in memory. */
8681 if (AGGREGATE_TYPE_P (type)
8682 || TREE_CODE (type) == COMPLEX_TYPE
8683 || TREE_CODE (type) == VECTOR_TYPE)
8684 return true;
8685
8686 /* ??? We get called on all sorts of random stuff from
8687 aggregate_value_p. We can't abort, but it's not clear
8688 what's safe to return. Pretend it's a struct I guess. */
8689 return true;
8690 }
8691
8692 /* Function arguments and return values are promoted to word size. */
8693
8694 static enum machine_mode
8695 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8696 int *punsignedp,
8697 const_tree fntype ATTRIBUTE_UNUSED,
8698 int for_return ATTRIBUTE_UNUSED)
8699 {
8700 if (INTEGRAL_MODE_P (mode)
8701 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8702 {
8703 if (type != NULL_TREE && POINTER_TYPE_P (type))
8704 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8705 return Pmode;
8706 }
8707
8708 return mode;
8709 }
8710
8711 /* Define where to return a (scalar) value of type RET_TYPE.
8712 If RET_TYPE is null, define where to return a (scalar)
8713 value of mode MODE from a libcall. */
8714
8715 static rtx
8716 s390_function_and_libcall_value (enum machine_mode mode,
8717 const_tree ret_type,
8718 const_tree fntype_or_decl,
8719 bool outgoing ATTRIBUTE_UNUSED)
8720 {
8721 /* For normal functions perform the promotion as
8722 promote_function_mode would do. */
8723 if (ret_type)
8724 {
8725 int unsignedp = TYPE_UNSIGNED (ret_type);
8726 mode = promote_function_mode (ret_type, mode, &unsignedp,
8727 fntype_or_decl, 1);
8728 }
8729
8730 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8731 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8732
8733 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8734 return gen_rtx_REG (mode, 16);
8735 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8736 || UNITS_PER_LONG == UNITS_PER_WORD)
8737 return gen_rtx_REG (mode, 2);
8738 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8739 {
8740 /* This case is triggered when returning a 64 bit value with
8741 -m31 -mzarch. Although the value would fit into a single
8742 register it has to be forced into a 32 bit register pair in
8743 order to match the ABI. */
8744 rtvec p = rtvec_alloc (2);
8745
8746 RTVEC_ELT (p, 0)
8747 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8748 RTVEC_ELT (p, 1)
8749 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8750
8751 return gen_rtx_PARALLEL (mode, p);
8752 }
8753
8754 gcc_unreachable ();
8755 }
8756
8757 /* Define where to return a scalar return value of type RET_TYPE. */
8758
8759 static rtx
8760 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8761 bool outgoing)
8762 {
8763 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8764 fn_decl_or_type, outgoing);
8765 }
8766
8767 /* Define where to return a scalar libcall return value of mode
8768 MODE. */
8769
8770 static rtx
8771 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8772 {
8773 return s390_function_and_libcall_value (mode, NULL_TREE,
8774 NULL_TREE, true);
8775 }
8776
8777
8778 /* Create and return the va_list datatype.
8779
8780 On S/390, va_list is an array type equivalent to
8781
8782 typedef struct __va_list_tag
8783 {
8784 long __gpr;
8785 long __fpr;
8786 void *__overflow_arg_area;
8787 void *__reg_save_area;
8788 } va_list[1];
8789
8790 where __gpr and __fpr hold the number of general purpose
8791 or floating point arguments used up to now, respectively,
8792 __overflow_arg_area points to the stack location of the
8793 next argument passed on the stack, and __reg_save_area
8794 always points to the start of the register area in the
8795 call frame of the current function. The function prologue
8796 saves all registers used for argument passing into this
8797 area if the function uses variable arguments. */
8798
8799 static tree
8800 s390_build_builtin_va_list (void)
8801 {
8802 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8803
8804 record = lang_hooks.types.make_type (RECORD_TYPE);
8805
8806 type_decl =
8807 build_decl (BUILTINS_LOCATION,
8808 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8809
8810 f_gpr = build_decl (BUILTINS_LOCATION,
8811 FIELD_DECL, get_identifier ("__gpr"),
8812 long_integer_type_node);
8813 f_fpr = build_decl (BUILTINS_LOCATION,
8814 FIELD_DECL, get_identifier ("__fpr"),
8815 long_integer_type_node);
8816 f_ovf = build_decl (BUILTINS_LOCATION,
8817 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8818 ptr_type_node);
8819 f_sav = build_decl (BUILTINS_LOCATION,
8820 FIELD_DECL, get_identifier ("__reg_save_area"),
8821 ptr_type_node);
8822
8823 va_list_gpr_counter_field = f_gpr;
8824 va_list_fpr_counter_field = f_fpr;
8825
8826 DECL_FIELD_CONTEXT (f_gpr) = record;
8827 DECL_FIELD_CONTEXT (f_fpr) = record;
8828 DECL_FIELD_CONTEXT (f_ovf) = record;
8829 DECL_FIELD_CONTEXT (f_sav) = record;
8830
8831 TYPE_STUB_DECL (record) = type_decl;
8832 TYPE_NAME (record) = type_decl;
8833 TYPE_FIELDS (record) = f_gpr;
8834 DECL_CHAIN (f_gpr) = f_fpr;
8835 DECL_CHAIN (f_fpr) = f_ovf;
8836 DECL_CHAIN (f_ovf) = f_sav;
8837
8838 layout_type (record);
8839
8840 /* The correct type is an array type of one element. */
8841 return build_array_type (record, build_index_type (size_zero_node));
8842 }
8843
8844 /* Implement va_start by filling the va_list structure VALIST.
8845 STDARG_P is always true, and ignored.
8846 NEXTARG points to the first anonymous stack argument.
8847
8848 The following global variables are used to initialize
8849 the va_list structure:
8850
8851 crtl->args.info:
8852 holds number of gprs and fprs used for named arguments.
8853 crtl->args.arg_offset_rtx:
8854 holds the offset of the first anonymous stack argument
8855 (relative to the virtual arg pointer). */
8856
8857 static void
8858 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8859 {
8860 HOST_WIDE_INT n_gpr, n_fpr;
8861 int off;
8862 tree f_gpr, f_fpr, f_ovf, f_sav;
8863 tree gpr, fpr, ovf, sav, t;
8864
8865 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8866 f_fpr = DECL_CHAIN (f_gpr);
8867 f_ovf = DECL_CHAIN (f_fpr);
8868 f_sav = DECL_CHAIN (f_ovf);
8869
8870 valist = build_simple_mem_ref (valist);
8871 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8872 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8873 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8874 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8875
8876 /* Count number of gp and fp argument registers used. */
8877
8878 n_gpr = crtl->args.info.gprs;
8879 n_fpr = crtl->args.info.fprs;
8880
8881 if (cfun->va_list_gpr_size)
8882 {
8883 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8884 build_int_cst (NULL_TREE, n_gpr));
8885 TREE_SIDE_EFFECTS (t) = 1;
8886 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8887 }
8888
8889 if (cfun->va_list_fpr_size)
8890 {
8891 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8892 build_int_cst (NULL_TREE, n_fpr));
8893 TREE_SIDE_EFFECTS (t) = 1;
8894 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8895 }
8896
8897 /* Find the overflow area. */
8898 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8899 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8900 {
8901 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8902
8903 off = INTVAL (crtl->args.arg_offset_rtx);
8904 off = off < 0 ? 0 : off;
8905 if (TARGET_DEBUG_ARG)
8906 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8907 (int)n_gpr, (int)n_fpr, off);
8908
8909 t = fold_build_pointer_plus_hwi (t, off);
8910
8911 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8912 TREE_SIDE_EFFECTS (t) = 1;
8913 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8914 }
8915
8916 /* Find the register save area. */
8917 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8918 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8919 {
8920 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8921 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
8922
8923 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8924 TREE_SIDE_EFFECTS (t) = 1;
8925 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8926 }
8927 }
8928
8929 /* Implement va_arg by updating the va_list structure
8930 VALIST as required to retrieve an argument of type
8931 TYPE, and returning that argument.
8932
8933 Generates code equivalent to:
8934
8935 if (integral value) {
8936 if (size <= 4 && args.gpr < 5 ||
8937 size > 4 && args.gpr < 4 )
8938 ret = args.reg_save_area[args.gpr+8]
8939 else
8940 ret = *args.overflow_arg_area++;
8941 } else if (float value) {
8942 if (args.fgpr < 2)
8943 ret = args.reg_save_area[args.fpr+64]
8944 else
8945 ret = *args.overflow_arg_area++;
8946 } else if (aggregate value) {
8947 if (args.gpr < 5)
8948 ret = *args.reg_save_area[args.gpr]
8949 else
8950 ret = **args.overflow_arg_area++;
8951 } */
8952
8953 static tree
8954 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8955 gimple_seq *post_p ATTRIBUTE_UNUSED)
8956 {
8957 tree f_gpr, f_fpr, f_ovf, f_sav;
8958 tree gpr, fpr, ovf, sav, reg, t, u;
8959 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8960 tree lab_false, lab_over, addr;
8961
8962 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8963 f_fpr = DECL_CHAIN (f_gpr);
8964 f_ovf = DECL_CHAIN (f_fpr);
8965 f_sav = DECL_CHAIN (f_ovf);
8966
8967 valist = build_va_arg_indirect_ref (valist);
8968 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8969 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8970 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8971
8972 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8973 both appear on a lhs. */
8974 valist = unshare_expr (valist);
8975 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8976
8977 size = int_size_in_bytes (type);
8978
8979 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8980 {
8981 if (TARGET_DEBUG_ARG)
8982 {
8983 fprintf (stderr, "va_arg: aggregate type");
8984 debug_tree (type);
8985 }
8986
8987 /* Aggregates are passed by reference. */
8988 indirect_p = 1;
8989 reg = gpr;
8990 n_reg = 1;
8991
8992 /* kernel stack layout on 31 bit: It is assumed here that no padding
8993 will be added by s390_frame_info because for va_args always an even
8994 number of gprs has to be saved r15-r2 = 14 regs. */
8995 sav_ofs = 2 * UNITS_PER_LONG;
8996 sav_scale = UNITS_PER_LONG;
8997 size = UNITS_PER_LONG;
8998 max_reg = GP_ARG_NUM_REG - n_reg;
8999 }
9000 else if (s390_function_arg_float (TYPE_MODE (type), type))
9001 {
9002 if (TARGET_DEBUG_ARG)
9003 {
9004 fprintf (stderr, "va_arg: float type");
9005 debug_tree (type);
9006 }
9007
9008 /* FP args go in FP registers, if present. */
9009 indirect_p = 0;
9010 reg = fpr;
9011 n_reg = 1;
9012 sav_ofs = 16 * UNITS_PER_LONG;
9013 sav_scale = 8;
9014 max_reg = FP_ARG_NUM_REG - n_reg;
9015 }
9016 else
9017 {
9018 if (TARGET_DEBUG_ARG)
9019 {
9020 fprintf (stderr, "va_arg: other type");
9021 debug_tree (type);
9022 }
9023
9024 /* Otherwise into GP registers. */
9025 indirect_p = 0;
9026 reg = gpr;
9027 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9028
9029 /* kernel stack layout on 31 bit: It is assumed here that no padding
9030 will be added by s390_frame_info because for va_args always an even
9031 number of gprs has to be saved r15-r2 = 14 regs. */
9032 sav_ofs = 2 * UNITS_PER_LONG;
9033
9034 if (size < UNITS_PER_LONG)
9035 sav_ofs += UNITS_PER_LONG - size;
9036
9037 sav_scale = UNITS_PER_LONG;
9038 max_reg = GP_ARG_NUM_REG - n_reg;
9039 }
9040
9041 /* Pull the value out of the saved registers ... */
9042
9043 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9044 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9045 addr = create_tmp_var (ptr_type_node, "addr");
9046 mark_sym_for_renaming (addr);
9047
9048 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9049 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9050 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9051 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9052 gimplify_and_add (t, pre_p);
9053
9054 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9055 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9056 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9057 t = fold_build_pointer_plus (t, u);
9058
9059 gimplify_assign (addr, t, pre_p);
9060
9061 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9062
9063 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9064
9065
9066 /* ... Otherwise out of the overflow area. */
9067
9068 t = ovf;
9069 if (size < UNITS_PER_LONG)
9070 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9071
9072 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9073
9074 gimplify_assign (addr, t, pre_p);
9075
9076 t = fold_build_pointer_plus_hwi (t, size);
9077 gimplify_assign (ovf, t, pre_p);
9078
9079 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9080
9081
9082 /* Increment register save count. */
9083
9084 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9085 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9086 gimplify_and_add (u, pre_p);
9087
9088 if (indirect_p)
9089 {
9090 t = build_pointer_type_for_mode (build_pointer_type (type),
9091 ptr_mode, true);
9092 addr = fold_convert (t, addr);
9093 addr = build_va_arg_indirect_ref (addr);
9094 }
9095 else
9096 {
9097 t = build_pointer_type_for_mode (type, ptr_mode, true);
9098 addr = fold_convert (t, addr);
9099 }
9100
9101 return build_va_arg_indirect_ref (addr);
9102 }
9103
9104
9105 /* Builtins. */
9106
9107 enum s390_builtin
9108 {
9109 S390_BUILTIN_THREAD_POINTER,
9110 S390_BUILTIN_SET_THREAD_POINTER,
9111
9112 S390_BUILTIN_max
9113 };
9114
9115 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9116 CODE_FOR_get_tp_64,
9117 CODE_FOR_set_tp_64
9118 };
9119
9120 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9121 CODE_FOR_get_tp_31,
9122 CODE_FOR_set_tp_31
9123 };
9124
9125 static void
9126 s390_init_builtins (void)
9127 {
9128 tree ftype;
9129
9130 ftype = build_function_type_list (ptr_type_node, NULL_TREE);
9131 add_builtin_function ("__builtin_thread_pointer", ftype,
9132 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9133 NULL, NULL_TREE);
9134
9135 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9136 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9137 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9138 NULL, NULL_TREE);
9139 }
9140
9141 /* Expand an expression EXP that calls a built-in function,
9142 with result going to TARGET if that's convenient
9143 (and in mode MODE if that's convenient).
9144 SUBTARGET may be used as the target for computing one of EXP's operands.
9145 IGNORE is nonzero if the value is to be ignored. */
9146
9147 static rtx
9148 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9149 enum machine_mode mode ATTRIBUTE_UNUSED,
9150 int ignore ATTRIBUTE_UNUSED)
9151 {
9152 #define MAX_ARGS 2
9153
9154 enum insn_code const *code_for_builtin =
9155 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9156
9157 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9158 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9159 enum insn_code icode;
9160 rtx op[MAX_ARGS], pat;
9161 int arity;
9162 bool nonvoid;
9163 tree arg;
9164 call_expr_arg_iterator iter;
9165
9166 if (fcode >= S390_BUILTIN_max)
9167 internal_error ("bad builtin fcode");
9168 icode = code_for_builtin[fcode];
9169 if (icode == 0)
9170 internal_error ("bad builtin fcode");
9171
9172 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9173
9174 arity = 0;
9175 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9176 {
9177 const struct insn_operand_data *insn_op;
9178
9179 if (arg == error_mark_node)
9180 return NULL_RTX;
9181 if (arity > MAX_ARGS)
9182 return NULL_RTX;
9183
9184 insn_op = &insn_data[icode].operand[arity + nonvoid];
9185
9186 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9187
9188 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9189 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9190 arity++;
9191 }
9192
9193 if (nonvoid)
9194 {
9195 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9196 if (!target
9197 || GET_MODE (target) != tmode
9198 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9199 target = gen_reg_rtx (tmode);
9200 }
9201
9202 switch (arity)
9203 {
9204 case 0:
9205 pat = GEN_FCN (icode) (target);
9206 break;
9207 case 1:
9208 if (nonvoid)
9209 pat = GEN_FCN (icode) (target, op[0]);
9210 else
9211 pat = GEN_FCN (icode) (op[0]);
9212 break;
9213 case 2:
9214 pat = GEN_FCN (icode) (target, op[0], op[1]);
9215 break;
9216 default:
9217 gcc_unreachable ();
9218 }
9219 if (!pat)
9220 return NULL_RTX;
9221 emit_insn (pat);
9222
9223 if (nonvoid)
9224 return target;
9225 else
9226 return const0_rtx;
9227 }
9228
9229
9230 /* Output assembly code for the trampoline template to
9231 stdio stream FILE.
9232
9233 On S/390, we use gpr 1 internally in the trampoline code;
9234 gpr 0 is used to hold the static chain. */
9235
9236 static void
9237 s390_asm_trampoline_template (FILE *file)
9238 {
9239 rtx op[2];
9240 op[0] = gen_rtx_REG (Pmode, 0);
9241 op[1] = gen_rtx_REG (Pmode, 1);
9242
9243 if (TARGET_64BIT)
9244 {
9245 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9246 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9247 output_asm_insn ("br\t%1", op); /* 2 byte */
9248 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9249 }
9250 else
9251 {
9252 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9253 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9254 output_asm_insn ("br\t%1", op); /* 2 byte */
9255 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9256 }
9257 }
9258
9259 /* Emit RTL insns to initialize the variable parts of a trampoline.
9260 FNADDR is an RTX for the address of the function's pure code.
9261 CXT is an RTX for the static chain value for the function. */
9262
9263 static void
9264 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9265 {
9266 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9267 rtx mem;
9268
9269 emit_block_move (m_tramp, assemble_trampoline_template (),
9270 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9271
9272 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9273 emit_move_insn (mem, cxt);
9274 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9275 emit_move_insn (mem, fnaddr);
9276 }
9277
9278 /* Output assembler code to FILE to increment profiler label # LABELNO
9279 for profiling a function entry. */
9280
9281 void
9282 s390_function_profiler (FILE *file, int labelno)
9283 {
9284 rtx op[7];
9285
9286 char label[128];
9287 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9288
9289 fprintf (file, "# function profiler \n");
9290
9291 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9292 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9293 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9294
9295 op[2] = gen_rtx_REG (Pmode, 1);
9296 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9297 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9298
9299 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9300 if (flag_pic)
9301 {
9302 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9303 op[4] = gen_rtx_CONST (Pmode, op[4]);
9304 }
9305
9306 if (TARGET_64BIT)
9307 {
9308 output_asm_insn ("stg\t%0,%1", op);
9309 output_asm_insn ("larl\t%2,%3", op);
9310 output_asm_insn ("brasl\t%0,%4", op);
9311 output_asm_insn ("lg\t%0,%1", op);
9312 }
9313 else if (!flag_pic)
9314 {
9315 op[6] = gen_label_rtx ();
9316
9317 output_asm_insn ("st\t%0,%1", op);
9318 output_asm_insn ("bras\t%2,%l6", op);
9319 output_asm_insn (".long\t%4", op);
9320 output_asm_insn (".long\t%3", op);
9321 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9322 output_asm_insn ("l\t%0,0(%2)", op);
9323 output_asm_insn ("l\t%2,4(%2)", op);
9324 output_asm_insn ("basr\t%0,%0", op);
9325 output_asm_insn ("l\t%0,%1", op);
9326 }
9327 else
9328 {
9329 op[5] = gen_label_rtx ();
9330 op[6] = gen_label_rtx ();
9331
9332 output_asm_insn ("st\t%0,%1", op);
9333 output_asm_insn ("bras\t%2,%l6", op);
9334 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9335 output_asm_insn (".long\t%4-%l5", op);
9336 output_asm_insn (".long\t%3-%l5", op);
9337 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9338 output_asm_insn ("lr\t%0,%2", op);
9339 output_asm_insn ("a\t%0,0(%2)", op);
9340 output_asm_insn ("a\t%2,4(%2)", op);
9341 output_asm_insn ("basr\t%0,%0", op);
9342 output_asm_insn ("l\t%0,%1", op);
9343 }
9344 }
9345
9346 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9347 into its SYMBOL_REF_FLAGS. */
9348
9349 static void
9350 s390_encode_section_info (tree decl, rtx rtl, int first)
9351 {
9352 default_encode_section_info (decl, rtl, first);
9353
9354 if (TREE_CODE (decl) == VAR_DECL)
9355 {
9356 /* If a variable has a forced alignment to < 2 bytes, mark it
9357 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9358 operand. */
9359 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9360 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9361 if (!DECL_SIZE (decl)
9362 || !DECL_ALIGN (decl)
9363 || !host_integerp (DECL_SIZE (decl), 0)
9364 || (DECL_ALIGN (decl) <= 64
9365 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9366 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9367 }
9368
9369 /* Literal pool references don't have a decl so they are handled
9370 differently here. We rely on the information in the MEM_ALIGN
9371 entry to decide upon natural alignment. */
9372 if (MEM_P (rtl)
9373 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9374 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9375 && (MEM_ALIGN (rtl) == 0
9376 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9377 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9378 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9379 }
9380
9381 /* Output thunk to FILE that implements a C++ virtual function call (with
9382 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9383 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9384 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9385 relative to the resulting this pointer. */
9386
9387 static void
9388 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9389 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9390 tree function)
9391 {
9392 rtx op[10];
9393 int nonlocal = 0;
9394
9395 /* Make sure unwind info is emitted for the thunk if needed. */
9396 final_start_function (emit_barrier (), file, 1);
9397
9398 /* Operand 0 is the target function. */
9399 op[0] = XEXP (DECL_RTL (function), 0);
9400 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9401 {
9402 nonlocal = 1;
9403 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9404 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9405 op[0] = gen_rtx_CONST (Pmode, op[0]);
9406 }
9407
9408 /* Operand 1 is the 'this' pointer. */
9409 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9410 op[1] = gen_rtx_REG (Pmode, 3);
9411 else
9412 op[1] = gen_rtx_REG (Pmode, 2);
9413
9414 /* Operand 2 is the delta. */
9415 op[2] = GEN_INT (delta);
9416
9417 /* Operand 3 is the vcall_offset. */
9418 op[3] = GEN_INT (vcall_offset);
9419
9420 /* Operand 4 is the temporary register. */
9421 op[4] = gen_rtx_REG (Pmode, 1);
9422
9423 /* Operands 5 to 8 can be used as labels. */
9424 op[5] = NULL_RTX;
9425 op[6] = NULL_RTX;
9426 op[7] = NULL_RTX;
9427 op[8] = NULL_RTX;
9428
9429 /* Operand 9 can be used for temporary register. */
9430 op[9] = NULL_RTX;
9431
9432 /* Generate code. */
9433 if (TARGET_64BIT)
9434 {
9435 /* Setup literal pool pointer if required. */
9436 if ((!DISP_IN_RANGE (delta)
9437 && !CONST_OK_FOR_K (delta)
9438 && !CONST_OK_FOR_Os (delta))
9439 || (!DISP_IN_RANGE (vcall_offset)
9440 && !CONST_OK_FOR_K (vcall_offset)
9441 && !CONST_OK_FOR_Os (vcall_offset)))
9442 {
9443 op[5] = gen_label_rtx ();
9444 output_asm_insn ("larl\t%4,%5", op);
9445 }
9446
9447 /* Add DELTA to this pointer. */
9448 if (delta)
9449 {
9450 if (CONST_OK_FOR_J (delta))
9451 output_asm_insn ("la\t%1,%2(%1)", op);
9452 else if (DISP_IN_RANGE (delta))
9453 output_asm_insn ("lay\t%1,%2(%1)", op);
9454 else if (CONST_OK_FOR_K (delta))
9455 output_asm_insn ("aghi\t%1,%2", op);
9456 else if (CONST_OK_FOR_Os (delta))
9457 output_asm_insn ("agfi\t%1,%2", op);
9458 else
9459 {
9460 op[6] = gen_label_rtx ();
9461 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9462 }
9463 }
9464
9465 /* Perform vcall adjustment. */
9466 if (vcall_offset)
9467 {
9468 if (DISP_IN_RANGE (vcall_offset))
9469 {
9470 output_asm_insn ("lg\t%4,0(%1)", op);
9471 output_asm_insn ("ag\t%1,%3(%4)", op);
9472 }
9473 else if (CONST_OK_FOR_K (vcall_offset))
9474 {
9475 output_asm_insn ("lghi\t%4,%3", op);
9476 output_asm_insn ("ag\t%4,0(%1)", op);
9477 output_asm_insn ("ag\t%1,0(%4)", op);
9478 }
9479 else if (CONST_OK_FOR_Os (vcall_offset))
9480 {
9481 output_asm_insn ("lgfi\t%4,%3", op);
9482 output_asm_insn ("ag\t%4,0(%1)", op);
9483 output_asm_insn ("ag\t%1,0(%4)", op);
9484 }
9485 else
9486 {
9487 op[7] = gen_label_rtx ();
9488 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9489 output_asm_insn ("ag\t%4,0(%1)", op);
9490 output_asm_insn ("ag\t%1,0(%4)", op);
9491 }
9492 }
9493
9494 /* Jump to target. */
9495 output_asm_insn ("jg\t%0", op);
9496
9497 /* Output literal pool if required. */
9498 if (op[5])
9499 {
9500 output_asm_insn (".align\t4", op);
9501 targetm.asm_out.internal_label (file, "L",
9502 CODE_LABEL_NUMBER (op[5]));
9503 }
9504 if (op[6])
9505 {
9506 targetm.asm_out.internal_label (file, "L",
9507 CODE_LABEL_NUMBER (op[6]));
9508 output_asm_insn (".long\t%2", op);
9509 }
9510 if (op[7])
9511 {
9512 targetm.asm_out.internal_label (file, "L",
9513 CODE_LABEL_NUMBER (op[7]));
9514 output_asm_insn (".long\t%3", op);
9515 }
9516 }
9517 else
9518 {
9519 /* Setup base pointer if required. */
9520 if (!vcall_offset
9521 || (!DISP_IN_RANGE (delta)
9522 && !CONST_OK_FOR_K (delta)
9523 && !CONST_OK_FOR_Os (delta))
9524 || (!DISP_IN_RANGE (delta)
9525 && !CONST_OK_FOR_K (vcall_offset)
9526 && !CONST_OK_FOR_Os (vcall_offset)))
9527 {
9528 op[5] = gen_label_rtx ();
9529 output_asm_insn ("basr\t%4,0", op);
9530 targetm.asm_out.internal_label (file, "L",
9531 CODE_LABEL_NUMBER (op[5]));
9532 }
9533
9534 /* Add DELTA to this pointer. */
9535 if (delta)
9536 {
9537 if (CONST_OK_FOR_J (delta))
9538 output_asm_insn ("la\t%1,%2(%1)", op);
9539 else if (DISP_IN_RANGE (delta))
9540 output_asm_insn ("lay\t%1,%2(%1)", op);
9541 else if (CONST_OK_FOR_K (delta))
9542 output_asm_insn ("ahi\t%1,%2", op);
9543 else if (CONST_OK_FOR_Os (delta))
9544 output_asm_insn ("afi\t%1,%2", op);
9545 else
9546 {
9547 op[6] = gen_label_rtx ();
9548 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9549 }
9550 }
9551
9552 /* Perform vcall adjustment. */
9553 if (vcall_offset)
9554 {
9555 if (CONST_OK_FOR_J (vcall_offset))
9556 {
9557 output_asm_insn ("l\t%4,0(%1)", op);
9558 output_asm_insn ("a\t%1,%3(%4)", op);
9559 }
9560 else if (DISP_IN_RANGE (vcall_offset))
9561 {
9562 output_asm_insn ("l\t%4,0(%1)", op);
9563 output_asm_insn ("ay\t%1,%3(%4)", op);
9564 }
9565 else if (CONST_OK_FOR_K (vcall_offset))
9566 {
9567 output_asm_insn ("lhi\t%4,%3", op);
9568 output_asm_insn ("a\t%4,0(%1)", op);
9569 output_asm_insn ("a\t%1,0(%4)", op);
9570 }
9571 else if (CONST_OK_FOR_Os (vcall_offset))
9572 {
9573 output_asm_insn ("iilf\t%4,%3", op);
9574 output_asm_insn ("a\t%4,0(%1)", op);
9575 output_asm_insn ("a\t%1,0(%4)", op);
9576 }
9577 else
9578 {
9579 op[7] = gen_label_rtx ();
9580 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9581 output_asm_insn ("a\t%4,0(%1)", op);
9582 output_asm_insn ("a\t%1,0(%4)", op);
9583 }
9584
9585 /* We had to clobber the base pointer register.
9586 Re-setup the base pointer (with a different base). */
9587 op[5] = gen_label_rtx ();
9588 output_asm_insn ("basr\t%4,0", op);
9589 targetm.asm_out.internal_label (file, "L",
9590 CODE_LABEL_NUMBER (op[5]));
9591 }
9592
9593 /* Jump to target. */
9594 op[8] = gen_label_rtx ();
9595
9596 if (!flag_pic)
9597 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9598 else if (!nonlocal)
9599 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9600 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9601 else if (flag_pic == 1)
9602 {
9603 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9604 output_asm_insn ("l\t%4,%0(%4)", op);
9605 }
9606 else if (flag_pic == 2)
9607 {
9608 op[9] = gen_rtx_REG (Pmode, 0);
9609 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9610 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9611 output_asm_insn ("ar\t%4,%9", op);
9612 output_asm_insn ("l\t%4,0(%4)", op);
9613 }
9614
9615 output_asm_insn ("br\t%4", op);
9616
9617 /* Output literal pool. */
9618 output_asm_insn (".align\t4", op);
9619
9620 if (nonlocal && flag_pic == 2)
9621 output_asm_insn (".long\t%0", op);
9622 if (nonlocal)
9623 {
9624 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9625 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9626 }
9627
9628 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9629 if (!flag_pic)
9630 output_asm_insn (".long\t%0", op);
9631 else
9632 output_asm_insn (".long\t%0-%5", op);
9633
9634 if (op[6])
9635 {
9636 targetm.asm_out.internal_label (file, "L",
9637 CODE_LABEL_NUMBER (op[6]));
9638 output_asm_insn (".long\t%2", op);
9639 }
9640 if (op[7])
9641 {
9642 targetm.asm_out.internal_label (file, "L",
9643 CODE_LABEL_NUMBER (op[7]));
9644 output_asm_insn (".long\t%3", op);
9645 }
9646 }
9647 final_end_function ();
9648 }
9649
9650 static bool
9651 s390_valid_pointer_mode (enum machine_mode mode)
9652 {
9653 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9654 }
9655
9656 /* Checks whether the given CALL_EXPR would use a caller
9657 saved register. This is used to decide whether sibling call
9658 optimization could be performed on the respective function
9659 call. */
9660
9661 static bool
9662 s390_call_saved_register_used (tree call_expr)
9663 {
9664 CUMULATIVE_ARGS cum_v;
9665 cumulative_args_t cum;
9666 tree parameter;
9667 enum machine_mode mode;
9668 tree type;
9669 rtx parm_rtx;
9670 int reg, i;
9671
9672 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9673 cum = pack_cumulative_args (&cum_v);
9674
9675 for (i = 0; i < call_expr_nargs (call_expr); i++)
9676 {
9677 parameter = CALL_EXPR_ARG (call_expr, i);
9678 gcc_assert (parameter);
9679
9680 /* For an undeclared variable passed as parameter we will get
9681 an ERROR_MARK node here. */
9682 if (TREE_CODE (parameter) == ERROR_MARK)
9683 return true;
9684
9685 type = TREE_TYPE (parameter);
9686 gcc_assert (type);
9687
9688 mode = TYPE_MODE (type);
9689 gcc_assert (mode);
9690
9691 if (pass_by_reference (&cum_v, mode, type, true))
9692 {
9693 mode = Pmode;
9694 type = build_pointer_type (type);
9695 }
9696
9697 parm_rtx = s390_function_arg (cum, mode, type, 0);
9698
9699 s390_function_arg_advance (cum, mode, type, 0);
9700
9701 if (!parm_rtx)
9702 continue;
9703
9704 if (REG_P (parm_rtx))
9705 {
9706 for (reg = 0;
9707 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9708 reg++)
9709 if (!call_used_regs[reg + REGNO (parm_rtx)])
9710 return true;
9711 }
9712
9713 if (GET_CODE (parm_rtx) == PARALLEL)
9714 {
9715 int i;
9716
9717 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9718 {
9719 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9720
9721 gcc_assert (REG_P (r));
9722
9723 for (reg = 0;
9724 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9725 reg++)
9726 if (!call_used_regs[reg + REGNO (r)])
9727 return true;
9728 }
9729 }
9730
9731 }
9732 return false;
9733 }
9734
9735 /* Return true if the given call expression can be
9736 turned into a sibling call.
9737 DECL holds the declaration of the function to be called whereas
9738 EXP is the call expression itself. */
9739
9740 static bool
9741 s390_function_ok_for_sibcall (tree decl, tree exp)
9742 {
9743 /* The TPF epilogue uses register 1. */
9744 if (TARGET_TPF_PROFILING)
9745 return false;
9746
9747 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9748 which would have to be restored before the sibcall. */
9749 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9750 return false;
9751
9752 /* Register 6 on s390 is available as an argument register but unfortunately
9753 "caller saved". This makes functions needing this register for arguments
9754 not suitable for sibcalls. */
9755 return !s390_call_saved_register_used (exp);
9756 }
9757
9758 /* Return the fixed registers used for condition codes. */
9759
9760 static bool
9761 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9762 {
9763 *p1 = CC_REGNUM;
9764 *p2 = INVALID_REGNUM;
9765
9766 return true;
9767 }
9768
9769 /* This function is used by the call expanders of the machine description.
9770 It emits the call insn itself together with the necessary operations
9771 to adjust the target address and returns the emitted insn.
9772 ADDR_LOCATION is the target address rtx
9773 TLS_CALL the location of the thread-local symbol
9774 RESULT_REG the register where the result of the call should be stored
9775 RETADDR_REG the register where the return address should be stored
9776 If this parameter is NULL_RTX the call is considered
9777 to be a sibling call. */
9778
9779 rtx
9780 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9781 rtx retaddr_reg)
9782 {
9783 bool plt_call = false;
9784 rtx insn;
9785 rtx call;
9786 rtx clobber;
9787 rtvec vec;
9788
9789 /* Direct function calls need special treatment. */
9790 if (GET_CODE (addr_location) == SYMBOL_REF)
9791 {
9792 /* When calling a global routine in PIC mode, we must
9793 replace the symbol itself with the PLT stub. */
9794 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9795 {
9796 if (retaddr_reg != NULL_RTX)
9797 {
9798 addr_location = gen_rtx_UNSPEC (Pmode,
9799 gen_rtvec (1, addr_location),
9800 UNSPEC_PLT);
9801 addr_location = gen_rtx_CONST (Pmode, addr_location);
9802 plt_call = true;
9803 }
9804 else
9805 /* For -fpic code the PLT entries might use r12 which is
9806 call-saved. Therefore we cannot do a sibcall when
9807 calling directly using a symbol ref. When reaching
9808 this point we decided (in s390_function_ok_for_sibcall)
9809 to do a sibcall for a function pointer but one of the
9810 optimizers was able to get rid of the function pointer
9811 by propagating the symbol ref into the call. This
9812 optimization is illegal for S/390 so we turn the direct
9813 call into a indirect call again. */
9814 addr_location = force_reg (Pmode, addr_location);
9815 }
9816
9817 /* Unless we can use the bras(l) insn, force the
9818 routine address into a register. */
9819 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9820 {
9821 if (flag_pic)
9822 addr_location = legitimize_pic_address (addr_location, 0);
9823 else
9824 addr_location = force_reg (Pmode, addr_location);
9825 }
9826 }
9827
9828 /* If it is already an indirect call or the code above moved the
9829 SYMBOL_REF to somewhere else make sure the address can be found in
9830 register 1. */
9831 if (retaddr_reg == NULL_RTX
9832 && GET_CODE (addr_location) != SYMBOL_REF
9833 && !plt_call)
9834 {
9835 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9836 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9837 }
9838
9839 addr_location = gen_rtx_MEM (QImode, addr_location);
9840 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9841
9842 if (result_reg != NULL_RTX)
9843 call = gen_rtx_SET (VOIDmode, result_reg, call);
9844
9845 if (retaddr_reg != NULL_RTX)
9846 {
9847 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9848
9849 if (tls_call != NULL_RTX)
9850 vec = gen_rtvec (3, call, clobber,
9851 gen_rtx_USE (VOIDmode, tls_call));
9852 else
9853 vec = gen_rtvec (2, call, clobber);
9854
9855 call = gen_rtx_PARALLEL (VOIDmode, vec);
9856 }
9857
9858 insn = emit_call_insn (call);
9859
9860 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9861 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9862 {
9863 /* s390_function_ok_for_sibcall should
9864 have denied sibcalls in this case. */
9865 gcc_assert (retaddr_reg != NULL_RTX);
9866 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
9867 }
9868 return insn;
9869 }
9870
9871 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9872
9873 static void
9874 s390_conditional_register_usage (void)
9875 {
9876 int i;
9877
9878 if (flag_pic)
9879 {
9880 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9881 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9882 }
9883 if (TARGET_CPU_ZARCH)
9884 {
9885 fixed_regs[BASE_REGNUM] = 0;
9886 call_used_regs[BASE_REGNUM] = 0;
9887 fixed_regs[RETURN_REGNUM] = 0;
9888 call_used_regs[RETURN_REGNUM] = 0;
9889 }
9890 if (TARGET_64BIT)
9891 {
9892 for (i = 24; i < 32; i++)
9893 call_used_regs[i] = call_really_used_regs[i] = 0;
9894 }
9895 else
9896 {
9897 for (i = 18; i < 20; i++)
9898 call_used_regs[i] = call_really_used_regs[i] = 0;
9899 }
9900
9901 if (TARGET_SOFT_FLOAT)
9902 {
9903 for (i = 16; i < 32; i++)
9904 call_used_regs[i] = fixed_regs[i] = 1;
9905 }
9906 }
9907
9908 /* Corresponding function to eh_return expander. */
9909
9910 static GTY(()) rtx s390_tpf_eh_return_symbol;
9911 void
9912 s390_emit_tpf_eh_return (rtx target)
9913 {
9914 rtx insn, reg;
9915
9916 if (!s390_tpf_eh_return_symbol)
9917 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9918
9919 reg = gen_rtx_REG (Pmode, 2);
9920
9921 emit_move_insn (reg, target);
9922 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9923 gen_rtx_REG (Pmode, RETURN_REGNUM));
9924 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9925
9926 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9927 }
9928
9929 /* Rework the prologue/epilogue to avoid saving/restoring
9930 registers unnecessarily. */
9931
9932 static void
9933 s390_optimize_prologue (void)
9934 {
9935 rtx insn, new_insn, next_insn;
9936
9937 /* Do a final recompute of the frame-related data. */
9938
9939 s390_update_frame_layout ();
9940
9941 /* If all special registers are in fact used, there's nothing we
9942 can do, so no point in walking the insn list. */
9943
9944 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9945 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9946 && (TARGET_CPU_ZARCH
9947 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9948 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9949 return;
9950
9951 /* Search for prologue/epilogue insns and replace them. */
9952
9953 for (insn = get_insns (); insn; insn = next_insn)
9954 {
9955 int first, last, off;
9956 rtx set, base, offset;
9957
9958 next_insn = NEXT_INSN (insn);
9959
9960 if (GET_CODE (insn) != INSN)
9961 continue;
9962
9963 if (GET_CODE (PATTERN (insn)) == PARALLEL
9964 && store_multiple_operation (PATTERN (insn), VOIDmode))
9965 {
9966 set = XVECEXP (PATTERN (insn), 0, 0);
9967 first = REGNO (SET_SRC (set));
9968 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9969 offset = const0_rtx;
9970 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9971 off = INTVAL (offset);
9972
9973 if (GET_CODE (base) != REG || off < 0)
9974 continue;
9975 if (cfun_frame_layout.first_save_gpr != -1
9976 && (cfun_frame_layout.first_save_gpr < first
9977 || cfun_frame_layout.last_save_gpr > last))
9978 continue;
9979 if (REGNO (base) != STACK_POINTER_REGNUM
9980 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9981 continue;
9982 if (first > BASE_REGNUM || last < BASE_REGNUM)
9983 continue;
9984
9985 if (cfun_frame_layout.first_save_gpr != -1)
9986 {
9987 new_insn = save_gprs (base,
9988 off + (cfun_frame_layout.first_save_gpr
9989 - first) * UNITS_PER_LONG,
9990 cfun_frame_layout.first_save_gpr,
9991 cfun_frame_layout.last_save_gpr);
9992 new_insn = emit_insn_before (new_insn, insn);
9993 INSN_ADDRESSES_NEW (new_insn, -1);
9994 }
9995
9996 remove_insn (insn);
9997 continue;
9998 }
9999
10000 if (cfun_frame_layout.first_save_gpr == -1
10001 && GET_CODE (PATTERN (insn)) == SET
10002 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10003 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10004 || (!TARGET_CPU_ZARCH
10005 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10006 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10007 {
10008 set = PATTERN (insn);
10009 first = REGNO (SET_SRC (set));
10010 offset = const0_rtx;
10011 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10012 off = INTVAL (offset);
10013
10014 if (GET_CODE (base) != REG || off < 0)
10015 continue;
10016 if (REGNO (base) != STACK_POINTER_REGNUM
10017 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10018 continue;
10019
10020 remove_insn (insn);
10021 continue;
10022 }
10023
10024 if (GET_CODE (PATTERN (insn)) == PARALLEL
10025 && load_multiple_operation (PATTERN (insn), VOIDmode))
10026 {
10027 set = XVECEXP (PATTERN (insn), 0, 0);
10028 first = REGNO (SET_DEST (set));
10029 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10030 offset = const0_rtx;
10031 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10032 off = INTVAL (offset);
10033
10034 if (GET_CODE (base) != REG || off < 0)
10035 continue;
10036 if (cfun_frame_layout.first_restore_gpr != -1
10037 && (cfun_frame_layout.first_restore_gpr < first
10038 || cfun_frame_layout.last_restore_gpr > last))
10039 continue;
10040 if (REGNO (base) != STACK_POINTER_REGNUM
10041 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10042 continue;
10043 if (first > BASE_REGNUM || last < BASE_REGNUM)
10044 continue;
10045
10046 if (cfun_frame_layout.first_restore_gpr != -1)
10047 {
10048 new_insn = restore_gprs (base,
10049 off + (cfun_frame_layout.first_restore_gpr
10050 - first) * UNITS_PER_LONG,
10051 cfun_frame_layout.first_restore_gpr,
10052 cfun_frame_layout.last_restore_gpr);
10053 new_insn = emit_insn_before (new_insn, insn);
10054 INSN_ADDRESSES_NEW (new_insn, -1);
10055 }
10056
10057 remove_insn (insn);
10058 continue;
10059 }
10060
10061 if (cfun_frame_layout.first_restore_gpr == -1
10062 && GET_CODE (PATTERN (insn)) == SET
10063 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10064 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10065 || (!TARGET_CPU_ZARCH
10066 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10067 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10068 {
10069 set = PATTERN (insn);
10070 first = REGNO (SET_DEST (set));
10071 offset = const0_rtx;
10072 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10073 off = INTVAL (offset);
10074
10075 if (GET_CODE (base) != REG || off < 0)
10076 continue;
10077 if (REGNO (base) != STACK_POINTER_REGNUM
10078 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10079 continue;
10080
10081 remove_insn (insn);
10082 continue;
10083 }
10084 }
10085 }
10086
10087 /* On z10 and later the dynamic branch prediction must see the
10088 backward jump within a certain windows. If not it falls back to
10089 the static prediction. This function rearranges the loop backward
10090 branch in a way which makes the static prediction always correct.
10091 The function returns true if it added an instruction. */
10092 static bool
10093 s390_fix_long_loop_prediction (rtx insn)
10094 {
10095 rtx set = single_set (insn);
10096 rtx code_label, label_ref, new_label;
10097 rtx uncond_jump;
10098 rtx cur_insn;
10099 rtx tmp;
10100 int distance;
10101
10102 /* This will exclude branch on count and branch on index patterns
10103 since these are correctly statically predicted. */
10104 if (!set
10105 || SET_DEST (set) != pc_rtx
10106 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10107 return false;
10108
10109 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10110 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10111
10112 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10113
10114 code_label = XEXP (label_ref, 0);
10115
10116 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10117 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10118 || (INSN_ADDRESSES (INSN_UID (insn))
10119 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10120 return false;
10121
10122 for (distance = 0, cur_insn = PREV_INSN (insn);
10123 distance < PREDICT_DISTANCE - 6;
10124 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10125 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10126 return false;
10127
10128 new_label = gen_label_rtx ();
10129 uncond_jump = emit_jump_insn_after (
10130 gen_rtx_SET (VOIDmode, pc_rtx,
10131 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10132 insn);
10133 emit_label_after (new_label, uncond_jump);
10134
10135 tmp = XEXP (SET_SRC (set), 1);
10136 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10137 XEXP (SET_SRC (set), 2) = tmp;
10138 INSN_CODE (insn) = -1;
10139
10140 XEXP (label_ref, 0) = new_label;
10141 JUMP_LABEL (insn) = new_label;
10142 JUMP_LABEL (uncond_jump) = code_label;
10143
10144 return true;
10145 }
10146
10147 /* Returns 1 if INSN reads the value of REG for purposes not related
10148 to addressing of memory, and 0 otherwise. */
10149 static int
10150 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10151 {
10152 return reg_referenced_p (reg, PATTERN (insn))
10153 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10154 }
10155
10156 /* Starting from INSN find_cond_jump looks downwards in the insn
10157 stream for a single jump insn which is the last user of the
10158 condition code set in INSN. */
10159 static rtx
10160 find_cond_jump (rtx insn)
10161 {
10162 for (; insn; insn = NEXT_INSN (insn))
10163 {
10164 rtx ite, cc;
10165
10166 if (LABEL_P (insn))
10167 break;
10168
10169 if (!JUMP_P (insn))
10170 {
10171 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10172 break;
10173 continue;
10174 }
10175
10176 /* This will be triggered by a return. */
10177 if (GET_CODE (PATTERN (insn)) != SET)
10178 break;
10179
10180 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10181 ite = SET_SRC (PATTERN (insn));
10182
10183 if (GET_CODE (ite) != IF_THEN_ELSE)
10184 break;
10185
10186 cc = XEXP (XEXP (ite, 0), 0);
10187 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10188 break;
10189
10190 if (find_reg_note (insn, REG_DEAD, cc))
10191 return insn;
10192 break;
10193 }
10194
10195 return NULL_RTX;
10196 }
10197
10198 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10199 the semantics does not change. If NULL_RTX is passed as COND the
10200 function tries to find the conditional jump starting with INSN. */
10201 static void
10202 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10203 {
10204 rtx tmp = *op0;
10205
10206 if (cond == NULL_RTX)
10207 {
10208 rtx jump = find_cond_jump (NEXT_INSN (insn));
10209 jump = jump ? single_set (jump) : NULL_RTX;
10210
10211 if (jump == NULL_RTX)
10212 return;
10213
10214 cond = XEXP (XEXP (jump, 1), 0);
10215 }
10216
10217 *op0 = *op1;
10218 *op1 = tmp;
10219 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10220 }
10221
10222 /* On z10, instructions of the compare-and-branch family have the
10223 property to access the register occurring as second operand with
10224 its bits complemented. If such a compare is grouped with a second
10225 instruction that accesses the same register non-complemented, and
10226 if that register's value is delivered via a bypass, then the
10227 pipeline recycles, thereby causing significant performance decline.
10228 This function locates such situations and exchanges the two
10229 operands of the compare. The function return true whenever it
10230 added an insn. */
10231 static bool
10232 s390_z10_optimize_cmp (rtx insn)
10233 {
10234 rtx prev_insn, next_insn;
10235 bool insn_added_p = false;
10236 rtx cond, *op0, *op1;
10237
10238 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10239 {
10240 /* Handle compare and branch and branch on count
10241 instructions. */
10242 rtx pattern = single_set (insn);
10243
10244 if (!pattern
10245 || SET_DEST (pattern) != pc_rtx
10246 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10247 return false;
10248
10249 cond = XEXP (SET_SRC (pattern), 0);
10250 op0 = &XEXP (cond, 0);
10251 op1 = &XEXP (cond, 1);
10252 }
10253 else if (GET_CODE (PATTERN (insn)) == SET)
10254 {
10255 rtx src, dest;
10256
10257 /* Handle normal compare instructions. */
10258 src = SET_SRC (PATTERN (insn));
10259 dest = SET_DEST (PATTERN (insn));
10260
10261 if (!REG_P (dest)
10262 || !CC_REGNO_P (REGNO (dest))
10263 || GET_CODE (src) != COMPARE)
10264 return false;
10265
10266 /* s390_swap_cmp will try to find the conditional
10267 jump when passing NULL_RTX as condition. */
10268 cond = NULL_RTX;
10269 op0 = &XEXP (src, 0);
10270 op1 = &XEXP (src, 1);
10271 }
10272 else
10273 return false;
10274
10275 if (!REG_P (*op0) || !REG_P (*op1))
10276 return false;
10277
10278 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10279 return false;
10280
10281 /* Swap the COMPARE arguments and its mask if there is a
10282 conflicting access in the previous insn. */
10283 prev_insn = prev_active_insn (insn);
10284 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10285 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10286 s390_swap_cmp (cond, op0, op1, insn);
10287
10288 /* Check if there is a conflict with the next insn. If there
10289 was no conflict with the previous insn, then swap the
10290 COMPARE arguments and its mask. If we already swapped
10291 the operands, or if swapping them would cause a conflict
10292 with the previous insn, issue a NOP after the COMPARE in
10293 order to separate the two instuctions. */
10294 next_insn = next_active_insn (insn);
10295 if (next_insn != NULL_RTX && INSN_P (next_insn)
10296 && s390_non_addr_reg_read_p (*op1, next_insn))
10297 {
10298 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10299 && s390_non_addr_reg_read_p (*op0, prev_insn))
10300 {
10301 if (REGNO (*op1) == 0)
10302 emit_insn_after (gen_nop1 (), insn);
10303 else
10304 emit_insn_after (gen_nop (), insn);
10305 insn_added_p = true;
10306 }
10307 else
10308 s390_swap_cmp (cond, op0, op1, insn);
10309 }
10310 return insn_added_p;
10311 }
10312
10313 /* Perform machine-dependent processing. */
10314
10315 static void
10316 s390_reorg (void)
10317 {
10318 bool pool_overflow = false;
10319
10320 /* Make sure all splits have been performed; splits after
10321 machine_dependent_reorg might confuse insn length counts. */
10322 split_all_insns_noflow ();
10323
10324 /* Install the main literal pool and the associated base
10325 register load insns.
10326
10327 In addition, there are two problematic situations we need
10328 to correct:
10329
10330 - the literal pool might be > 4096 bytes in size, so that
10331 some of its elements cannot be directly accessed
10332
10333 - a branch target might be > 64K away from the branch, so that
10334 it is not possible to use a PC-relative instruction.
10335
10336 To fix those, we split the single literal pool into multiple
10337 pool chunks, reloading the pool base register at various
10338 points throughout the function to ensure it always points to
10339 the pool chunk the following code expects, and / or replace
10340 PC-relative branches by absolute branches.
10341
10342 However, the two problems are interdependent: splitting the
10343 literal pool can move a branch further away from its target,
10344 causing the 64K limit to overflow, and on the other hand,
10345 replacing a PC-relative branch by an absolute branch means
10346 we need to put the branch target address into the literal
10347 pool, possibly causing it to overflow.
10348
10349 So, we loop trying to fix up both problems until we manage
10350 to satisfy both conditions at the same time. Note that the
10351 loop is guaranteed to terminate as every pass of the loop
10352 strictly decreases the total number of PC-relative branches
10353 in the function. (This is not completely true as there
10354 might be branch-over-pool insns introduced by chunkify_start.
10355 Those never need to be split however.) */
10356
10357 for (;;)
10358 {
10359 struct constant_pool *pool = NULL;
10360
10361 /* Collect the literal pool. */
10362 if (!pool_overflow)
10363 {
10364 pool = s390_mainpool_start ();
10365 if (!pool)
10366 pool_overflow = true;
10367 }
10368
10369 /* If literal pool overflowed, start to chunkify it. */
10370 if (pool_overflow)
10371 pool = s390_chunkify_start ();
10372
10373 /* Split out-of-range branches. If this has created new
10374 literal pool entries, cancel current chunk list and
10375 recompute it. zSeries machines have large branch
10376 instructions, so we never need to split a branch. */
10377 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10378 {
10379 if (pool_overflow)
10380 s390_chunkify_cancel (pool);
10381 else
10382 s390_mainpool_cancel (pool);
10383
10384 continue;
10385 }
10386
10387 /* If we made it up to here, both conditions are satisfied.
10388 Finish up literal pool related changes. */
10389 if (pool_overflow)
10390 s390_chunkify_finish (pool);
10391 else
10392 s390_mainpool_finish (pool);
10393
10394 /* We're done splitting branches. */
10395 cfun->machine->split_branches_pending_p = false;
10396 break;
10397 }
10398
10399 /* Generate out-of-pool execute target insns. */
10400 if (TARGET_CPU_ZARCH)
10401 {
10402 rtx insn, label, target;
10403
10404 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10405 {
10406 label = s390_execute_label (insn);
10407 if (!label)
10408 continue;
10409
10410 gcc_assert (label != const0_rtx);
10411
10412 target = emit_label (XEXP (label, 0));
10413 INSN_ADDRESSES_NEW (target, -1);
10414
10415 target = emit_insn (s390_execute_target (insn));
10416 INSN_ADDRESSES_NEW (target, -1);
10417 }
10418 }
10419
10420 /* Try to optimize prologue and epilogue further. */
10421 s390_optimize_prologue ();
10422
10423 /* Walk over the insns and do some >=z10 specific changes. */
10424 if (s390_tune == PROCESSOR_2097_Z10
10425 || s390_tune == PROCESSOR_2817_Z196)
10426 {
10427 rtx insn;
10428 bool insn_added_p = false;
10429
10430 /* The insn lengths and addresses have to be up to date for the
10431 following manipulations. */
10432 shorten_branches (get_insns ());
10433
10434 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10435 {
10436 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10437 continue;
10438
10439 if (JUMP_P (insn))
10440 insn_added_p |= s390_fix_long_loop_prediction (insn);
10441
10442 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10443 || GET_CODE (PATTERN (insn)) == SET)
10444 && s390_tune == PROCESSOR_2097_Z10)
10445 insn_added_p |= s390_z10_optimize_cmp (insn);
10446 }
10447
10448 /* Adjust branches if we added new instructions. */
10449 if (insn_added_p)
10450 shorten_branches (get_insns ());
10451 }
10452 }
10453
10454 /* Return true if INSN is a fp load insn writing register REGNO. */
10455 static inline bool
10456 s390_fpload_toreg (rtx insn, unsigned int regno)
10457 {
10458 rtx set;
10459 enum attr_type flag = s390_safe_attr_type (insn);
10460
10461 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10462 return false;
10463
10464 set = single_set (insn);
10465
10466 if (set == NULL_RTX)
10467 return false;
10468
10469 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10470 return false;
10471
10472 if (REGNO (SET_DEST (set)) != regno)
10473 return false;
10474
10475 return true;
10476 }
10477
10478 /* This value describes the distance to be avoided between an
10479 aritmetic fp instruction and an fp load writing the same register.
10480 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10481 fine but the exact value has to be avoided. Otherwise the FP
10482 pipeline will throw an exception causing a major penalty. */
10483 #define Z10_EARLYLOAD_DISTANCE 7
10484
10485 /* Rearrange the ready list in order to avoid the situation described
10486 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10487 moved to the very end of the ready list. */
10488 static void
10489 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10490 {
10491 unsigned int regno;
10492 int nready = *nready_p;
10493 rtx tmp;
10494 int i;
10495 rtx insn;
10496 rtx set;
10497 enum attr_type flag;
10498 int distance;
10499
10500 /* Skip DISTANCE - 1 active insns. */
10501 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10502 distance > 0 && insn != NULL_RTX;
10503 distance--, insn = prev_active_insn (insn))
10504 if (CALL_P (insn) || JUMP_P (insn))
10505 return;
10506
10507 if (insn == NULL_RTX)
10508 return;
10509
10510 set = single_set (insn);
10511
10512 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10513 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10514 return;
10515
10516 flag = s390_safe_attr_type (insn);
10517
10518 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10519 return;
10520
10521 regno = REGNO (SET_DEST (set));
10522 i = nready - 1;
10523
10524 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10525 i--;
10526
10527 if (!i)
10528 return;
10529
10530 tmp = ready[i];
10531 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10532 ready[0] = tmp;
10533 }
10534
10535 /* This function is called via hook TARGET_SCHED_REORDER before
10536 issuing one insn from list READY which contains *NREADYP entries.
10537 For target z10 it reorders load instructions to avoid early load
10538 conflicts in the floating point pipeline */
10539 static int
10540 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10541 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10542 {
10543 if (s390_tune == PROCESSOR_2097_Z10)
10544 if (reload_completed && *nreadyp > 1)
10545 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10546
10547 return s390_issue_rate ();
10548 }
10549
10550 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10551 the scheduler has issued INSN. It stores the last issued insn into
10552 last_scheduled_insn in order to make it available for
10553 s390_sched_reorder. */
10554 static int
10555 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10556 int verbose ATTRIBUTE_UNUSED,
10557 rtx insn, int more)
10558 {
10559 last_scheduled_insn = insn;
10560
10561 if (GET_CODE (PATTERN (insn)) != USE
10562 && GET_CODE (PATTERN (insn)) != CLOBBER)
10563 return more - 1;
10564 else
10565 return more;
10566 }
10567
10568 static void
10569 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10570 int verbose ATTRIBUTE_UNUSED,
10571 int max_ready ATTRIBUTE_UNUSED)
10572 {
10573 last_scheduled_insn = NULL_RTX;
10574 }
10575
10576 /* This function checks the whole of insn X for memory references. The
10577 function always returns zero because the framework it is called
10578 from would stop recursively analyzing the insn upon a return value
10579 other than zero. The real result of this function is updating
10580 counter variable MEM_COUNT. */
10581 static int
10582 check_dpu (rtx *x, unsigned *mem_count)
10583 {
10584 if (*x != NULL_RTX && MEM_P (*x))
10585 (*mem_count)++;
10586 return 0;
10587 }
10588
10589 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10590 a new number struct loop *loop should be unrolled if tuned for cpus with
10591 a built-in stride prefetcher.
10592 The loop is analyzed for memory accesses by calling check_dpu for
10593 each rtx of the loop. Depending on the loop_depth and the amount of
10594 memory accesses a new number <=nunroll is returned to improve the
10595 behaviour of the hardware prefetch unit. */
10596 static unsigned
10597 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10598 {
10599 basic_block *bbs;
10600 rtx insn;
10601 unsigned i;
10602 unsigned mem_count = 0;
10603
10604 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10605 return nunroll;
10606
10607 /* Count the number of memory references within the loop body. */
10608 bbs = get_loop_body (loop);
10609 for (i = 0; i < loop->num_nodes; i++)
10610 {
10611 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10612 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10613 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10614 }
10615 free (bbs);
10616
10617 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10618 if (mem_count == 0)
10619 return nunroll;
10620
10621 switch (loop_depth(loop))
10622 {
10623 case 1:
10624 return MIN (nunroll, 28 / mem_count);
10625 case 2:
10626 return MIN (nunroll, 22 / mem_count);
10627 default:
10628 return MIN (nunroll, 16 / mem_count);
10629 }
10630 }
10631
10632 /* Initialize GCC target structure. */
10633
10634 #undef TARGET_ASM_ALIGNED_HI_OP
10635 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10636 #undef TARGET_ASM_ALIGNED_DI_OP
10637 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10638 #undef TARGET_ASM_INTEGER
10639 #define TARGET_ASM_INTEGER s390_assemble_integer
10640
10641 #undef TARGET_ASM_OPEN_PAREN
10642 #define TARGET_ASM_OPEN_PAREN ""
10643
10644 #undef TARGET_ASM_CLOSE_PAREN
10645 #define TARGET_ASM_CLOSE_PAREN ""
10646
10647 #undef TARGET_OPTION_OVERRIDE
10648 #define TARGET_OPTION_OVERRIDE s390_option_override
10649
10650 #undef TARGET_ENCODE_SECTION_INFO
10651 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10652
10653 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10654 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10655
10656 #ifdef HAVE_AS_TLS
10657 #undef TARGET_HAVE_TLS
10658 #define TARGET_HAVE_TLS true
10659 #endif
10660 #undef TARGET_CANNOT_FORCE_CONST_MEM
10661 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10662
10663 #undef TARGET_DELEGITIMIZE_ADDRESS
10664 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10665
10666 #undef TARGET_LEGITIMIZE_ADDRESS
10667 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10668
10669 #undef TARGET_RETURN_IN_MEMORY
10670 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10671
10672 #undef TARGET_INIT_BUILTINS
10673 #define TARGET_INIT_BUILTINS s390_init_builtins
10674 #undef TARGET_EXPAND_BUILTIN
10675 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10676
10677 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10678 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10679
10680 #undef TARGET_ASM_OUTPUT_MI_THUNK
10681 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10682 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10683 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10684
10685 #undef TARGET_SCHED_ADJUST_PRIORITY
10686 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10687 #undef TARGET_SCHED_ISSUE_RATE
10688 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10689 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10690 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10691
10692 #undef TARGET_SCHED_VARIABLE_ISSUE
10693 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10694 #undef TARGET_SCHED_REORDER
10695 #define TARGET_SCHED_REORDER s390_sched_reorder
10696 #undef TARGET_SCHED_INIT
10697 #define TARGET_SCHED_INIT s390_sched_init
10698
10699 #undef TARGET_CANNOT_COPY_INSN_P
10700 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10701 #undef TARGET_RTX_COSTS
10702 #define TARGET_RTX_COSTS s390_rtx_costs
10703 #undef TARGET_ADDRESS_COST
10704 #define TARGET_ADDRESS_COST s390_address_cost
10705 #undef TARGET_REGISTER_MOVE_COST
10706 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10707 #undef TARGET_MEMORY_MOVE_COST
10708 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10709
10710 #undef TARGET_MACHINE_DEPENDENT_REORG
10711 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10712
10713 #undef TARGET_VALID_POINTER_MODE
10714 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10715
10716 #undef TARGET_BUILD_BUILTIN_VA_LIST
10717 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10718 #undef TARGET_EXPAND_BUILTIN_VA_START
10719 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10720 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10721 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10722
10723 #undef TARGET_PROMOTE_FUNCTION_MODE
10724 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10725 #undef TARGET_PASS_BY_REFERENCE
10726 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10727
10728 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10729 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10730 #undef TARGET_FUNCTION_ARG
10731 #define TARGET_FUNCTION_ARG s390_function_arg
10732 #undef TARGET_FUNCTION_ARG_ADVANCE
10733 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10734 #undef TARGET_FUNCTION_VALUE
10735 #define TARGET_FUNCTION_VALUE s390_function_value
10736 #undef TARGET_LIBCALL_VALUE
10737 #define TARGET_LIBCALL_VALUE s390_libcall_value
10738
10739 #undef TARGET_FIXED_CONDITION_CODE_REGS
10740 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10741
10742 #undef TARGET_CC_MODES_COMPATIBLE
10743 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10744
10745 #undef TARGET_INVALID_WITHIN_DOLOOP
10746 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10747
10748 #ifdef HAVE_AS_TLS
10749 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10750 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10751 #endif
10752
10753 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10754 #undef TARGET_MANGLE_TYPE
10755 #define TARGET_MANGLE_TYPE s390_mangle_type
10756 #endif
10757
10758 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10759 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10760
10761 #undef TARGET_PREFERRED_RELOAD_CLASS
10762 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10763
10764 #undef TARGET_SECONDARY_RELOAD
10765 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10766
10767 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10768 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10769
10770 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10771 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10772
10773 #undef TARGET_LEGITIMATE_ADDRESS_P
10774 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10775
10776 #undef TARGET_LEGITIMATE_CONSTANT_P
10777 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10778
10779 #undef TARGET_CAN_ELIMINATE
10780 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10781
10782 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10783 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10784
10785 #undef TARGET_LOOP_UNROLL_ADJUST
10786 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10787
10788 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10789 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10790 #undef TARGET_TRAMPOLINE_INIT
10791 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10792
10793 #undef TARGET_UNWIND_WORD_MODE
10794 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10795
10796 struct gcc_target targetm = TARGET_INITIALIZER;
10797
10798 #include "gt-s390.h"