1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
59 /* Define the specific costs for a given cpu. */
61 struct processor_costs
64 const int m
; /* cost of an M instruction. */
65 const int mghi
; /* cost of an MGHI instruction. */
66 const int mh
; /* cost of an MH instruction. */
67 const int mhi
; /* cost of an MHI instruction. */
68 const int ml
; /* cost of an ML instruction. */
69 const int mr
; /* cost of an MR instruction. */
70 const int ms
; /* cost of an MS instruction. */
71 const int msg
; /* cost of an MSG instruction. */
72 const int msgf
; /* cost of an MSGF instruction. */
73 const int msgfr
; /* cost of an MSGFR instruction. */
74 const int msgr
; /* cost of an MSGR instruction. */
75 const int msr
; /* cost of an MSR instruction. */
76 const int mult_df
; /* cost of multiplication in DFmode. */
79 const int sqxbr
; /* cost of square root in TFmode. */
80 const int sqdbr
; /* cost of square root in DFmode. */
81 const int sqebr
; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr
; /* cost of multiply and add in DFmode. */
84 const int maebr
; /* cost of multiply and add in SFmode. */
96 const struct processor_costs
*s390_cost
;
99 struct processor_costs z900_cost
=
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
131 struct processor_costs z990_cost
=
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
163 struct processor_costs z9_109_cost
=
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
195 struct processor_costs z10_cost
=
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
227 struct processor_costs z196_cost
=
229 COSTS_N_INSNS (7), /* M */
230 COSTS_N_INSNS (5), /* MGHI */
231 COSTS_N_INSNS (5), /* MH */
232 COSTS_N_INSNS (5), /* MHI */
233 COSTS_N_INSNS (7), /* ML */
234 COSTS_N_INSNS (7), /* MR */
235 COSTS_N_INSNS (6), /* MS */
236 COSTS_N_INSNS (8), /* MSG */
237 COSTS_N_INSNS (6), /* MSGF */
238 COSTS_N_INSNS (6), /* MSGFR */
239 COSTS_N_INSNS (8), /* MSGR */
240 COSTS_N_INSNS (6), /* MSR */
241 COSTS_N_INSNS (1) , /* multiplication in DFmode */
242 COSTS_N_INSNS (40), /* MXBR B+40 */
243 COSTS_N_INSNS (100), /* SQXBR B+100 */
244 COSTS_N_INSNS (42), /* SQDBR B+42 */
245 COSTS_N_INSNS (28), /* SQEBR B+28 */
246 COSTS_N_INSNS (1), /* MADBR B */
247 COSTS_N_INSNS (1), /* MAEBR B */
248 COSTS_N_INSNS (101), /* DXBR B+101 */
249 COSTS_N_INSNS (29), /* DDBR */
250 COSTS_N_INSNS (22), /* DEBR */
251 COSTS_N_INSNS (160), /* DLGR cracked */
252 COSTS_N_INSNS (160), /* DLR cracked */
253 COSTS_N_INSNS (160), /* DR expanded */
254 COSTS_N_INSNS (160), /* DSGFR cracked */
255 COSTS_N_INSNS (160), /* DSGR cracked */
258 extern int reload_completed
;
260 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
261 static rtx last_scheduled_insn
;
263 /* Structure used to hold the components of a S/390 memory
264 address. A legitimate address on S/390 is of the general
266 base + index + displacement
267 where any of the components is optional.
269 base and index are registers of the class ADDR_REGS,
270 displacement is an unsigned 12-bit immediate constant. */
281 /* Which cpu are we tuning for. */
282 enum processor_type s390_tune
= PROCESSOR_max
;
284 /* Which instruction set architecture to use. */
285 enum processor_type s390_arch
;
288 HOST_WIDE_INT s390_warn_framesize
= 0;
289 HOST_WIDE_INT s390_stack_size
= 0;
290 HOST_WIDE_INT s390_stack_guard
= 0;
292 /* The following structure is embedded in the machine
293 specific part of struct function. */
295 struct GTY (()) s390_frame_layout
297 /* Offset within stack frame. */
298 HOST_WIDE_INT gprs_offset
;
299 HOST_WIDE_INT f0_offset
;
300 HOST_WIDE_INT f4_offset
;
301 HOST_WIDE_INT f8_offset
;
302 HOST_WIDE_INT backchain_offset
;
304 /* Number of first and last gpr where slots in the register
305 save area are reserved for. */
306 int first_save_gpr_slot
;
307 int last_save_gpr_slot
;
309 /* Number of first and last gpr to be saved, restored. */
311 int first_restore_gpr
;
313 int last_restore_gpr
;
315 /* Bits standing for floating point registers. Set, if the
316 respective register has to be saved. Starting with reg 16 (f0)
317 at the rightmost bit.
318 Bit 15 - 8 7 6 5 4 3 2 1 0
319 fpr 15 - 8 7 5 3 1 6 4 2 0
320 reg 31 - 24 23 22 21 20 19 18 17 16 */
321 unsigned int fpr_bitmap
;
323 /* Number of floating point registers f8-f15 which must be saved. */
326 /* Set if return address needs to be saved.
327 This flag is set by s390_return_addr_rtx if it could not use
328 the initial value of r14 and therefore depends on r14 saved
330 bool save_return_addr_p
;
332 /* Size of stack frame. */
333 HOST_WIDE_INT frame_size
;
336 /* Define the structure for the machine field in struct function. */
338 struct GTY(()) machine_function
340 struct s390_frame_layout frame_layout
;
342 /* Literal pool base register. */
345 /* True if we may need to perform branch splitting. */
346 bool split_branches_pending_p
;
348 /* Some local-dynamic TLS symbol name. */
349 const char *some_ld_name
;
351 bool has_landing_pad_p
;
354 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
356 #define cfun_frame_layout (cfun->machine->frame_layout)
357 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
358 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
359 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
360 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
362 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
365 /* Number of GPRs and FPRs used for argument passing. */
366 #define GP_ARG_NUM_REG 5
367 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
369 /* A couple of shortcuts. */
370 #define CONST_OK_FOR_J(x) \
371 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
372 #define CONST_OK_FOR_K(x) \
373 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
374 #define CONST_OK_FOR_Os(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
376 #define CONST_OK_FOR_Op(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
378 #define CONST_OK_FOR_On(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
381 #define REGNO_PAIR_OK(REGNO, MODE) \
382 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
384 /* That's the read ahead of the dynamic branch prediction unit in
385 bytes on a z10 (or higher) CPU. */
386 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
388 static enum machine_mode
389 s390_libgcc_cmp_return_mode (void)
391 return TARGET_64BIT
? DImode
: SImode
;
394 static enum machine_mode
395 s390_libgcc_shift_count_mode (void)
397 return TARGET_64BIT
? DImode
: SImode
;
400 static enum machine_mode
401 s390_unwind_word_mode (void)
403 return TARGET_64BIT
? DImode
: SImode
;
406 /* Return true if the back end supports mode MODE. */
408 s390_scalar_mode_supported_p (enum machine_mode mode
)
410 /* In contrast to the default implementation reject TImode constants on 31bit
411 TARGET_ZARCH for ABI compliance. */
412 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
415 if (DECIMAL_FLOAT_MODE_P (mode
))
416 return default_decimal_float_supported_p ();
418 return default_scalar_mode_supported_p (mode
);
421 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
424 s390_set_has_landing_pad_p (bool value
)
426 cfun
->machine
->has_landing_pad_p
= value
;
429 /* If two condition code modes are compatible, return a condition code
430 mode which is compatible with both. Otherwise, return
433 static enum machine_mode
434 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
442 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
443 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
464 /* Return true if SET either doesn't set the CC register, or else
465 the source and destination have matching CC modes and that
466 CC mode is at least as constrained as REQ_MODE. */
469 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
471 enum machine_mode set_mode
;
473 gcc_assert (GET_CODE (set
) == SET
);
475 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
478 set_mode
= GET_MODE (SET_DEST (set
));
492 if (req_mode
!= set_mode
)
497 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
498 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
504 if (req_mode
!= CCAmode
)
512 return (GET_MODE (SET_SRC (set
)) == set_mode
);
515 /* Return true if every SET in INSN that sets the CC register
516 has source and destination with matching CC modes and that
517 CC mode is at least as constrained as REQ_MODE.
518 If REQ_MODE is VOIDmode, always return false. */
521 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
525 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
526 if (req_mode
== VOIDmode
)
529 if (GET_CODE (PATTERN (insn
)) == SET
)
530 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
532 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
533 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
535 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
536 if (GET_CODE (set
) == SET
)
537 if (!s390_match_ccmode_set (set
, req_mode
))
544 /* If a test-under-mask instruction can be used to implement
545 (compare (and ... OP1) OP2), return the CC mode required
546 to do that. Otherwise, return VOIDmode.
547 MIXED is true if the instruction can distinguish between
548 CC1 and CC2 for mixed selected bits (TMxx), it is false
549 if the instruction cannot (TM). */
552 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
556 /* ??? Fixme: should work on CONST_DOUBLE as well. */
557 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
560 /* Selected bits all zero: CC0.
561 e.g.: int a; if ((a & (16 + 128)) == 0) */
562 if (INTVAL (op2
) == 0)
565 /* Selected bits all one: CC3.
566 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
567 if (INTVAL (op2
) == INTVAL (op1
))
570 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
572 if ((a & (16 + 128)) == 16) -> CCT1
573 if ((a & (16 + 128)) == 128) -> CCT2 */
576 bit1
= exact_log2 (INTVAL (op2
));
577 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
578 if (bit0
!= -1 && bit1
!= -1)
579 return bit0
> bit1
? CCT1mode
: CCT2mode
;
585 /* Given a comparison code OP (EQ, NE, etc.) and the operands
586 OP0 and OP1 of a COMPARE, return the mode to be used for the
590 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
596 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
597 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
599 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
600 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
602 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
603 || GET_CODE (op1
) == NEG
)
604 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
607 if (GET_CODE (op0
) == AND
)
609 /* Check whether we can potentially do it via TM. */
610 enum machine_mode ccmode
;
611 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
612 if (ccmode
!= VOIDmode
)
614 /* Relax CCTmode to CCZmode to allow fall-back to AND
615 if that turns out to be beneficial. */
616 return ccmode
== CCTmode
? CCZmode
: ccmode
;
620 if (register_operand (op0
, HImode
)
621 && GET_CODE (op1
) == CONST_INT
622 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
624 if (register_operand (op0
, QImode
)
625 && GET_CODE (op1
) == CONST_INT
626 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
635 /* The only overflow condition of NEG and ABS happens when
636 -INT_MAX is used as parameter, which stays negative. So
637 we have an overflow from a positive value to a negative.
638 Using CCAP mode the resulting cc can be used for comparisons. */
639 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
640 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
643 /* If constants are involved in an add instruction it is possible to use
644 the resulting cc for comparisons with zero. Knowing the sign of the
645 constant the overflow behavior gets predictable. e.g.:
646 int a, b; if ((b = a + c) > 0)
647 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
648 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
649 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
651 if (INTVAL (XEXP((op0
), 1)) < 0)
665 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
666 && GET_CODE (op1
) != CONST_INT
)
672 if (GET_CODE (op0
) == PLUS
673 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
676 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
677 && GET_CODE (op1
) != CONST_INT
)
683 if (GET_CODE (op0
) == MINUS
684 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
687 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
688 && GET_CODE (op1
) != CONST_INT
)
697 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
698 that we can implement more efficiently. */
701 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
703 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
704 if ((*code
== EQ
|| *code
== NE
)
705 && *op1
== const0_rtx
706 && GET_CODE (*op0
) == ZERO_EXTRACT
707 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
708 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
709 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
711 rtx inner
= XEXP (*op0
, 0);
712 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
713 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
714 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
716 if (len
> 0 && len
< modesize
717 && pos
>= 0 && pos
+ len
<= modesize
718 && modesize
<= HOST_BITS_PER_WIDE_INT
)
720 unsigned HOST_WIDE_INT block
;
721 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
722 block
<<= modesize
- pos
- len
;
724 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
725 gen_int_mode (block
, GET_MODE (inner
)));
729 /* Narrow AND of memory against immediate to enable TM. */
730 if ((*code
== EQ
|| *code
== NE
)
731 && *op1
== const0_rtx
732 && GET_CODE (*op0
) == AND
733 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
734 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
736 rtx inner
= XEXP (*op0
, 0);
737 rtx mask
= XEXP (*op0
, 1);
739 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
740 if (GET_CODE (inner
) == SUBREG
741 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
742 && (GET_MODE_SIZE (GET_MODE (inner
))
743 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
745 & GET_MODE_MASK (GET_MODE (inner
))
746 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
748 inner
= SUBREG_REG (inner
);
750 /* Do not change volatile MEMs. */
751 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
753 int part
= s390_single_part (XEXP (*op0
, 1),
754 GET_MODE (inner
), QImode
, 0);
757 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
758 inner
= adjust_address_nv (inner
, QImode
, part
);
759 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
764 /* Narrow comparisons against 0xffff to HImode if possible. */
765 if ((*code
== EQ
|| *code
== NE
)
766 && GET_CODE (*op1
) == CONST_INT
767 && INTVAL (*op1
) == 0xffff
768 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
769 && (nonzero_bits (*op0
, GET_MODE (*op0
))
770 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
772 *op0
= gen_lowpart (HImode
, *op0
);
776 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
777 if (GET_CODE (*op0
) == UNSPEC
778 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
779 && XVECLEN (*op0
, 0) == 1
780 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
781 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
782 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
783 && *op1
== const0_rtx
)
785 enum rtx_code new_code
= UNKNOWN
;
788 case EQ
: new_code
= EQ
; break;
789 case NE
: new_code
= NE
; break;
790 case LT
: new_code
= GTU
; break;
791 case GT
: new_code
= LTU
; break;
792 case LE
: new_code
= GEU
; break;
793 case GE
: new_code
= LEU
; break;
797 if (new_code
!= UNKNOWN
)
799 *op0
= XVECEXP (*op0
, 0, 0);
804 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
805 if (GET_CODE (*op0
) == UNSPEC
806 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
807 && XVECLEN (*op0
, 0) == 1
808 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
809 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
810 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
811 && *op1
== const0_rtx
)
813 enum rtx_code new_code
= UNKNOWN
;
816 case EQ
: new_code
= EQ
; break;
817 case NE
: new_code
= NE
; break;
821 if (new_code
!= UNKNOWN
)
823 *op0
= XVECEXP (*op0
, 0, 0);
828 /* Simplify cascaded EQ, NE with const0_rtx. */
829 if ((*code
== NE
|| *code
== EQ
)
830 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
831 && GET_MODE (*op0
) == SImode
832 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
833 && REG_P (XEXP (*op0
, 0))
834 && XEXP (*op0
, 1) == const0_rtx
835 && *op1
== const0_rtx
)
837 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
838 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
842 *op0
= XEXP (*op0
, 0);
845 /* Prefer register over memory as first operand. */
846 if (MEM_P (*op0
) && REG_P (*op1
))
848 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
849 *code
= swap_condition (*code
);
853 /* Emit a compare instruction suitable to implement the comparison
854 OP0 CODE OP1. Return the correct condition RTL to be placed in
855 the IF_THEN_ELSE of the conditional branch testing the result. */
858 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
860 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
863 /* Do not output a redundant compare instruction if a compare_and_swap
864 pattern already computed the result and the machine modes are compatible. */
865 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
867 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
873 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
874 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
877 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
880 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
882 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
883 conditional branch testing the result. */
886 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
888 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
889 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
892 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
893 unconditional jump, else a conditional jump under condition COND. */
896 s390_emit_jump (rtx target
, rtx cond
)
900 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
902 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
904 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
905 emit_jump_insn (insn
);
908 /* Return branch condition mask to implement a branch
909 specified by CODE. Return -1 for invalid comparisons. */
912 s390_branch_condition_mask (rtx code
)
914 const int CC0
= 1 << 3;
915 const int CC1
= 1 << 2;
916 const int CC2
= 1 << 1;
917 const int CC3
= 1 << 0;
919 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
920 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
921 gcc_assert (XEXP (code
, 1) == const0_rtx
);
923 switch (GET_MODE (XEXP (code
, 0)))
927 switch (GET_CODE (code
))
930 case NE
: return CC1
| CC2
| CC3
;
936 switch (GET_CODE (code
))
939 case NE
: return CC0
| CC2
| CC3
;
945 switch (GET_CODE (code
))
948 case NE
: return CC0
| CC1
| CC3
;
954 switch (GET_CODE (code
))
957 case NE
: return CC0
| CC1
| CC2
;
963 switch (GET_CODE (code
))
965 case EQ
: return CC0
| CC2
;
966 case NE
: return CC1
| CC3
;
972 switch (GET_CODE (code
))
974 case LTU
: return CC2
| CC3
; /* carry */
975 case GEU
: return CC0
| CC1
; /* no carry */
981 switch (GET_CODE (code
))
983 case GTU
: return CC0
| CC1
; /* borrow */
984 case LEU
: return CC2
| CC3
; /* no borrow */
990 switch (GET_CODE (code
))
992 case EQ
: return CC0
| CC2
;
993 case NE
: return CC1
| CC3
;
994 case LTU
: return CC1
;
995 case GTU
: return CC3
;
996 case LEU
: return CC1
| CC2
;
997 case GEU
: return CC2
| CC3
;
1002 switch (GET_CODE (code
))
1004 case EQ
: return CC0
;
1005 case NE
: return CC1
| CC2
| CC3
;
1006 case LTU
: return CC1
;
1007 case GTU
: return CC2
;
1008 case LEU
: return CC0
| CC1
;
1009 case GEU
: return CC0
| CC2
;
1015 switch (GET_CODE (code
))
1017 case EQ
: return CC0
;
1018 case NE
: return CC2
| CC1
| CC3
;
1019 case LTU
: return CC2
;
1020 case GTU
: return CC1
;
1021 case LEU
: return CC0
| CC2
;
1022 case GEU
: return CC0
| CC1
;
1028 switch (GET_CODE (code
))
1030 case EQ
: return CC0
;
1031 case NE
: return CC1
| CC2
| CC3
;
1032 case LT
: return CC1
| CC3
;
1033 case GT
: return CC2
;
1034 case LE
: return CC0
| CC1
| CC3
;
1035 case GE
: return CC0
| CC2
;
1041 switch (GET_CODE (code
))
1043 case EQ
: return CC0
;
1044 case NE
: return CC1
| CC2
| CC3
;
1045 case LT
: return CC1
;
1046 case GT
: return CC2
| CC3
;
1047 case LE
: return CC0
| CC1
;
1048 case GE
: return CC0
| CC2
| CC3
;
1054 switch (GET_CODE (code
))
1056 case EQ
: return CC0
;
1057 case NE
: return CC1
| CC2
| CC3
;
1058 case LT
: return CC1
;
1059 case GT
: return CC2
;
1060 case LE
: return CC0
| CC1
;
1061 case GE
: return CC0
| CC2
;
1062 case UNORDERED
: return CC3
;
1063 case ORDERED
: return CC0
| CC1
| CC2
;
1064 case UNEQ
: return CC0
| CC3
;
1065 case UNLT
: return CC1
| CC3
;
1066 case UNGT
: return CC2
| CC3
;
1067 case UNLE
: return CC0
| CC1
| CC3
;
1068 case UNGE
: return CC0
| CC2
| CC3
;
1069 case LTGT
: return CC1
| CC2
;
1075 switch (GET_CODE (code
))
1077 case EQ
: return CC0
;
1078 case NE
: return CC2
| CC1
| CC3
;
1079 case LT
: return CC2
;
1080 case GT
: return CC1
;
1081 case LE
: return CC0
| CC2
;
1082 case GE
: return CC0
| CC1
;
1083 case UNORDERED
: return CC3
;
1084 case ORDERED
: return CC0
| CC2
| CC1
;
1085 case UNEQ
: return CC0
| CC3
;
1086 case UNLT
: return CC2
| CC3
;
1087 case UNGT
: return CC1
| CC3
;
1088 case UNLE
: return CC0
| CC2
| CC3
;
1089 case UNGE
: return CC0
| CC1
| CC3
;
1090 case LTGT
: return CC2
| CC1
;
1101 /* Return branch condition mask to implement a compare and branch
1102 specified by CODE. Return -1 for invalid comparisons. */
1105 s390_compare_and_branch_condition_mask (rtx code
)
1107 const int CC0
= 1 << 3;
1108 const int CC1
= 1 << 2;
1109 const int CC2
= 1 << 1;
1111 switch (GET_CODE (code
))
1135 /* If INV is false, return assembler mnemonic string to implement
1136 a branch specified by CODE. If INV is true, return mnemonic
1137 for the corresponding inverted branch. */
1140 s390_branch_condition_mnemonic (rtx code
, int inv
)
1144 static const char *const mnemonic
[16] =
1146 NULL
, "o", "h", "nle",
1147 "l", "nhe", "lh", "ne",
1148 "e", "nlh", "he", "nl",
1149 "le", "nh", "no", NULL
1152 if (GET_CODE (XEXP (code
, 0)) == REG
1153 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1154 && XEXP (code
, 1) == const0_rtx
)
1155 mask
= s390_branch_condition_mask (code
);
1157 mask
= s390_compare_and_branch_condition_mask (code
);
1159 gcc_assert (mask
>= 0);
1164 gcc_assert (mask
>= 1 && mask
<= 14);
1166 return mnemonic
[mask
];
1169 /* Return the part of op which has a value different from def.
1170 The size of the part is determined by mode.
1171 Use this function only if you already know that op really
1172 contains such a part. */
1174 unsigned HOST_WIDE_INT
1175 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1177 unsigned HOST_WIDE_INT value
= 0;
1178 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1179 int part_bits
= GET_MODE_BITSIZE (mode
);
1180 unsigned HOST_WIDE_INT part_mask
1181 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1184 for (i
= 0; i
< max_parts
; i
++)
1187 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1189 value
>>= part_bits
;
1191 if ((value
& part_mask
) != (def
& part_mask
))
1192 return value
& part_mask
;
1198 /* If OP is an integer constant of mode MODE with exactly one
1199 part of mode PART_MODE unequal to DEF, return the number of that
1200 part. Otherwise, return -1. */
1203 s390_single_part (rtx op
,
1204 enum machine_mode mode
,
1205 enum machine_mode part_mode
,
1208 unsigned HOST_WIDE_INT value
= 0;
1209 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1210 unsigned HOST_WIDE_INT part_mask
1211 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1214 if (GET_CODE (op
) != CONST_INT
)
1217 for (i
= 0; i
< n_parts
; i
++)
1220 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1222 value
>>= GET_MODE_BITSIZE (part_mode
);
1224 if ((value
& part_mask
) != (def
& part_mask
))
1232 return part
== -1 ? -1 : n_parts
- 1 - part
;
1235 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1236 bits and no other bits are set in IN. POS and LENGTH can be used
1237 to obtain the start position and the length of the bitfield.
1239 POS gives the position of the first bit of the bitfield counting
1240 from the lowest order bit starting with zero. In order to use this
1241 value for S/390 instructions this has to be converted to "bits big
1245 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1246 int *pos
, int *length
)
1251 unsigned HOST_WIDE_INT mask
= 1ULL;
1252 bool contiguous
= false;
1254 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1278 /* Calculate a mask for all bits beyond the contiguous bits. */
1279 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1284 if (tmp_length
+ tmp_pos
- 1 > size
)
1288 *length
= tmp_length
;
1296 /* Check whether we can (and want to) split a double-word
1297 move in mode MODE from SRC to DST into two single-word
1298 moves, moving the subword FIRST_SUBWORD first. */
1301 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1303 /* Floating point registers cannot be split. */
1304 if (FP_REG_P (src
) || FP_REG_P (dst
))
1307 /* We don't need to split if operands are directly accessible. */
1308 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1311 /* Non-offsettable memory references cannot be split. */
1312 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1313 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1316 /* Moving the first subword must not clobber a register
1317 needed to move the second subword. */
1318 if (register_operand (dst
, mode
))
1320 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1321 if (reg_overlap_mentioned_p (subreg
, src
))
1328 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1329 and [MEM2, MEM2 + SIZE] do overlap and false
1333 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1335 rtx addr1
, addr2
, addr_delta
;
1336 HOST_WIDE_INT delta
;
1338 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1344 addr1
= XEXP (mem1
, 0);
1345 addr2
= XEXP (mem2
, 0);
1347 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1349 /* This overlapping check is used by peepholes merging memory block operations.
1350 Overlapping operations would otherwise be recognized by the S/390 hardware
1351 and would fall back to a slower implementation. Allowing overlapping
1352 operations would lead to slow code but not to wrong code. Therefore we are
1353 somewhat optimistic if we cannot prove that the memory blocks are
1355 That's why we return false here although this may accept operations on
1356 overlapping memory areas. */
1357 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1360 delta
= INTVAL (addr_delta
);
1363 || (delta
> 0 && delta
< size
)
1364 || (delta
< 0 && -delta
< size
))
1370 /* Check whether the address of memory reference MEM2 equals exactly
1371 the address of memory reference MEM1 plus DELTA. Return true if
1372 we can prove this to be the case, false otherwise. */
1375 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1377 rtx addr1
, addr2
, addr_delta
;
1379 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1382 addr1
= XEXP (mem1
, 0);
1383 addr2
= XEXP (mem2
, 0);
1385 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1386 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1392 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1395 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1398 enum machine_mode wmode
= mode
;
1399 rtx dst
= operands
[0];
1400 rtx src1
= operands
[1];
1401 rtx src2
= operands
[2];
1404 /* If we cannot handle the operation directly, use a temp register. */
1405 if (!s390_logical_operator_ok_p (operands
))
1406 dst
= gen_reg_rtx (mode
);
1408 /* QImode and HImode patterns make sense only if we have a destination
1409 in memory. Otherwise perform the operation in SImode. */
1410 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1413 /* Widen operands if required. */
1416 if (GET_CODE (dst
) == SUBREG
1417 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1419 else if (REG_P (dst
))
1420 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1422 dst
= gen_reg_rtx (wmode
);
1424 if (GET_CODE (src1
) == SUBREG
1425 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1427 else if (GET_MODE (src1
) != VOIDmode
)
1428 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1430 if (GET_CODE (src2
) == SUBREG
1431 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1433 else if (GET_MODE (src2
) != VOIDmode
)
1434 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1437 /* Emit the instruction. */
1438 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1439 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1440 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1442 /* Fix up the destination if needed. */
1443 if (dst
!= operands
[0])
1444 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1447 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1450 s390_logical_operator_ok_p (rtx
*operands
)
1452 /* If the destination operand is in memory, it needs to coincide
1453 with one of the source operands. After reload, it has to be
1454 the first source operand. */
1455 if (GET_CODE (operands
[0]) == MEM
)
1456 return rtx_equal_p (operands
[0], operands
[1])
1457 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1462 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1463 operand IMMOP to switch from SS to SI type instructions. */
1466 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1468 int def
= code
== AND
? -1 : 0;
1472 gcc_assert (GET_CODE (*memop
) == MEM
);
1473 gcc_assert (!MEM_VOLATILE_P (*memop
));
1475 mask
= s390_extract_part (*immop
, QImode
, def
);
1476 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1477 gcc_assert (part
>= 0);
1479 *memop
= adjust_address (*memop
, QImode
, part
);
1480 *immop
= gen_int_mode (mask
, QImode
);
1484 /* How to allocate a 'struct machine_function'. */
1486 static struct machine_function
*
1487 s390_init_machine_status (void)
1489 return ggc_alloc_cleared_machine_function ();
1492 /* Change optimizations to be performed, depending on the
1495 LEVEL is the optimization level specified; 2 if `-O2' is
1496 specified, 1 if `-O' is specified, and 0 if neither is specified.
1498 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1501 s390_option_optimization (int level ATTRIBUTE_UNUSED
, int size
)
1503 /* ??? There are apparently still problems with -fcaller-saves. */
1504 flag_caller_saves
= 0;
1506 /* By default, always emit DWARF-2 unwind info. This allows debugging
1507 without maintaining a stack frame back-chain. */
1508 flag_asynchronous_unwind_tables
= 1;
1510 /* Use MVCLE instructions to decrease code size if requested. */
1512 target_flags
|= MASK_MVCLE
;
1515 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1516 to the associated processor_type and processor_flags if so. */
1519 s390_handle_arch_option (const char *arg
,
1520 enum processor_type
*type
,
1525 const char *const name
; /* processor name or nickname. */
1526 const enum processor_type processor
;
1527 const int flags
; /* From enum processor_flags. */
1529 const processor_alias_table
[] =
1531 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1532 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1533 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1534 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1535 | PF_LONG_DISPLACEMENT
},
1536 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1537 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1538 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1539 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1540 {"z10", PROCESSOR_2097_Z10
, PF_IEEE_FLOAT
| PF_ZARCH
1541 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
},
1542 {"z196", PROCESSOR_2817_Z196
, PF_IEEE_FLOAT
| PF_ZARCH
1543 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
| PF_Z196
},
1547 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1548 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1550 *type
= processor_alias_table
[i
].processor
;
1551 *flags
= processor_alias_table
[i
].flags
;
1557 /* Implement TARGET_HANDLE_OPTION. */
1560 s390_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1565 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1567 case OPT_mstack_guard_
:
1568 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1570 if (exact_log2 (s390_stack_guard
) == -1)
1571 error ("stack guard value must be an exact power of 2");
1574 case OPT_mstack_size_
:
1575 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1577 if (exact_log2 (s390_stack_size
) == -1)
1578 error ("stack size must be an exact power of 2");
1582 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1584 case OPT_mwarn_framesize_
:
1585 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1593 s390_option_override (void)
1595 /* Set up function hooks. */
1596 init_machine_status
= s390_init_machine_status
;
1598 /* Architecture mode defaults according to ABI. */
1599 if (!(target_flags_explicit
& MASK_ZARCH
))
1602 target_flags
|= MASK_ZARCH
;
1604 target_flags
&= ~MASK_ZARCH
;
1607 /* Determine processor architectural level. */
1608 if (!s390_arch_string
)
1610 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1611 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1614 /* Determine processor to tune for. */
1615 if (s390_tune
== PROCESSOR_max
)
1617 s390_tune
= s390_arch
;
1618 s390_tune_flags
= s390_arch_flags
;
1621 /* Sanity checks. */
1622 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1623 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1624 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1625 error ("64-bit ABI not supported in ESA/390 mode");
1627 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1629 if (target_flags_explicit
& MASK_HARD_DFP
)
1631 if (!TARGET_CPU_DFP
)
1632 error ("Hardware decimal floating point instructions"
1633 " not available on %s", s390_arch_string
);
1635 error ("Hardware decimal floating point instructions"
1636 " not available in ESA/390 mode");
1639 target_flags
&= ~MASK_HARD_DFP
;
1642 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1644 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1645 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1647 target_flags
&= ~MASK_HARD_DFP
;
1650 /* Set processor cost function. */
1653 case PROCESSOR_2084_Z990
:
1654 s390_cost
= &z990_cost
;
1656 case PROCESSOR_2094_Z9_109
:
1657 s390_cost
= &z9_109_cost
;
1659 case PROCESSOR_2097_Z10
:
1660 s390_cost
= &z10_cost
;
1661 case PROCESSOR_2817_Z196
:
1662 s390_cost
= &z196_cost
;
1665 s390_cost
= &z900_cost
;
1668 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1669 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1672 if (s390_stack_size
)
1674 if (s390_stack_guard
>= s390_stack_size
)
1675 error ("stack size must be greater than the stack guard value");
1676 else if (s390_stack_size
> 1 << 16)
1677 error ("stack size must not be greater than 64k");
1679 else if (s390_stack_guard
)
1680 error ("-mstack-guard implies use of -mstack-size");
1682 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1683 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1684 target_flags
|= MASK_LONG_DOUBLE_128
;
1687 if (s390_tune
== PROCESSOR_2097_Z10
1688 || s390_tune
== PROCESSOR_2817_Z196
)
1690 if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS
))
1691 set_param_value ("max-unrolled-insns", 100);
1692 if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES
))
1693 set_param_value ("max-unroll-times", 32);
1694 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEELED_INSNS
))
1695 set_param_value ("max-completely-peeled-insns", 2000);
1696 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEEL_TIMES
))
1697 set_param_value ("max-completely-peel-times", 64);
1700 set_param_value ("max-pending-list-length", 256);
1701 /* values for loop prefetching */
1702 set_param_value ("l1-cache-line-size", 256);
1703 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE
))
1704 set_param_value ("l1-cache-size", 128);
1705 /* s390 has more than 2 levels and the size is much larger. Since
1706 we are always running virtualized assume that we only get a small
1707 part of the caches above l1. */
1708 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE
))
1709 set_param_value ("l2-cache-size", 1500);
1710 if (!PARAM_SET_P (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
))
1711 set_param_value ("prefetch-min-insn-to-mem-ratio", 2);
1712 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
1713 set_param_value ("simultaneous-prefetches", 6);
1715 /* This cannot reside in s390_option_optimization since HAVE_prefetch
1716 requires the arch flags to be evaluated already. Since prefetching
1717 is beneficial on s390, we enable it if available. */
1718 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1719 flag_prefetch_loop_arrays
= 1;
1722 /* Map for smallest class containing reg regno. */
1724 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1725 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1726 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1727 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1728 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1729 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1730 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1731 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1732 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1733 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1734 ACCESS_REGS
, ACCESS_REGS
1737 /* Return attribute type of insn. */
1739 static enum attr_type
1740 s390_safe_attr_type (rtx insn
)
1742 if (recog_memoized (insn
) >= 0)
1743 return get_attr_type (insn
);
1748 /* Return true if DISP is a valid short displacement. */
1751 s390_short_displacement (rtx disp
)
1753 /* No displacement is OK. */
1757 /* Without the long displacement facility we don't need to
1758 distingiush between long and short displacement. */
1759 if (!TARGET_LONG_DISPLACEMENT
)
1762 /* Integer displacement in range. */
1763 if (GET_CODE (disp
) == CONST_INT
)
1764 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1766 /* GOT offset is not OK, the GOT can be large. */
1767 if (GET_CODE (disp
) == CONST
1768 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1769 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1770 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1773 /* All other symbolic constants are literal pool references,
1774 which are OK as the literal pool must be small. */
1775 if (GET_CODE (disp
) == CONST
)
1781 /* Decompose a RTL expression ADDR for a memory address into
1782 its components, returned in OUT.
1784 Returns false if ADDR is not a valid memory address, true
1785 otherwise. If OUT is NULL, don't return the components,
1786 but check for validity only.
1788 Note: Only addresses in canonical form are recognized.
1789 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1790 canonical form so that they will be recognized. */
1793 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1795 HOST_WIDE_INT offset
= 0;
1796 rtx base
= NULL_RTX
;
1797 rtx indx
= NULL_RTX
;
1798 rtx disp
= NULL_RTX
;
1800 bool pointer
= false;
1801 bool base_ptr
= false;
1802 bool indx_ptr
= false;
1803 bool literal_pool
= false;
1805 /* We may need to substitute the literal pool base register into the address
1806 below. However, at this point we do not know which register is going to
1807 be used as base, so we substitute the arg pointer register. This is going
1808 to be treated as holding a pointer below -- it shouldn't be used for any
1810 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1812 /* Decompose address into base + index + displacement. */
1814 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1817 else if (GET_CODE (addr
) == PLUS
)
1819 rtx op0
= XEXP (addr
, 0);
1820 rtx op1
= XEXP (addr
, 1);
1821 enum rtx_code code0
= GET_CODE (op0
);
1822 enum rtx_code code1
= GET_CODE (op1
);
1824 if (code0
== REG
|| code0
== UNSPEC
)
1826 if (code1
== REG
|| code1
== UNSPEC
)
1828 indx
= op0
; /* index + base */
1834 base
= op0
; /* base + displacement */
1839 else if (code0
== PLUS
)
1841 indx
= XEXP (op0
, 0); /* index + base + disp */
1842 base
= XEXP (op0
, 1);
1853 disp
= addr
; /* displacement */
1855 /* Extract integer part of displacement. */
1859 if (GET_CODE (disp
) == CONST_INT
)
1861 offset
= INTVAL (disp
);
1864 else if (GET_CODE (disp
) == CONST
1865 && GET_CODE (XEXP (disp
, 0)) == PLUS
1866 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1868 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1869 disp
= XEXP (XEXP (disp
, 0), 0);
1873 /* Strip off CONST here to avoid special case tests later. */
1874 if (disp
&& GET_CODE (disp
) == CONST
)
1875 disp
= XEXP (disp
, 0);
1877 /* We can convert literal pool addresses to
1878 displacements by basing them off the base register. */
1879 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1881 /* Either base or index must be free to hold the base register. */
1883 base
= fake_pool_base
, literal_pool
= true;
1885 indx
= fake_pool_base
, literal_pool
= true;
1889 /* Mark up the displacement. */
1890 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1891 UNSPEC_LTREL_OFFSET
);
1894 /* Validate base register. */
1897 if (GET_CODE (base
) == UNSPEC
)
1898 switch (XINT (base
, 1))
1902 disp
= gen_rtx_UNSPEC (Pmode
,
1903 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1904 UNSPEC_LTREL_OFFSET
);
1908 base
= XVECEXP (base
, 0, 1);
1911 case UNSPEC_LTREL_BASE
:
1912 if (XVECLEN (base
, 0) == 1)
1913 base
= fake_pool_base
, literal_pool
= true;
1915 base
= XVECEXP (base
, 0, 1);
1923 || (GET_MODE (base
) != SImode
1924 && GET_MODE (base
) != Pmode
))
1927 if (REGNO (base
) == STACK_POINTER_REGNUM
1928 || REGNO (base
) == FRAME_POINTER_REGNUM
1929 || ((reload_completed
|| reload_in_progress
)
1930 && frame_pointer_needed
1931 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1932 || REGNO (base
) == ARG_POINTER_REGNUM
1934 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1935 pointer
= base_ptr
= true;
1937 if ((reload_completed
|| reload_in_progress
)
1938 && base
== cfun
->machine
->base_reg
)
1939 pointer
= base_ptr
= literal_pool
= true;
1942 /* Validate index register. */
1945 if (GET_CODE (indx
) == UNSPEC
)
1946 switch (XINT (indx
, 1))
1950 disp
= gen_rtx_UNSPEC (Pmode
,
1951 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1952 UNSPEC_LTREL_OFFSET
);
1956 indx
= XVECEXP (indx
, 0, 1);
1959 case UNSPEC_LTREL_BASE
:
1960 if (XVECLEN (indx
, 0) == 1)
1961 indx
= fake_pool_base
, literal_pool
= true;
1963 indx
= XVECEXP (indx
, 0, 1);
1971 || (GET_MODE (indx
) != SImode
1972 && GET_MODE (indx
) != Pmode
))
1975 if (REGNO (indx
) == STACK_POINTER_REGNUM
1976 || REGNO (indx
) == FRAME_POINTER_REGNUM
1977 || ((reload_completed
|| reload_in_progress
)
1978 && frame_pointer_needed
1979 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1980 || REGNO (indx
) == ARG_POINTER_REGNUM
1982 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1983 pointer
= indx_ptr
= true;
1985 if ((reload_completed
|| reload_in_progress
)
1986 && indx
== cfun
->machine
->base_reg
)
1987 pointer
= indx_ptr
= literal_pool
= true;
1990 /* Prefer to use pointer as base, not index. */
1991 if (base
&& indx
&& !base_ptr
1992 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1999 /* Validate displacement. */
2002 /* If virtual registers are involved, the displacement will change later
2003 anyway as the virtual registers get eliminated. This could make a
2004 valid displacement invalid, but it is more likely to make an invalid
2005 displacement valid, because we sometimes access the register save area
2006 via negative offsets to one of those registers.
2007 Thus we don't check the displacement for validity here. If after
2008 elimination the displacement turns out to be invalid after all,
2009 this is fixed up by reload in any case. */
2010 if (base
!= arg_pointer_rtx
2011 && indx
!= arg_pointer_rtx
2012 && base
!= return_address_pointer_rtx
2013 && indx
!= return_address_pointer_rtx
2014 && base
!= frame_pointer_rtx
2015 && indx
!= frame_pointer_rtx
2016 && base
!= virtual_stack_vars_rtx
2017 && indx
!= virtual_stack_vars_rtx
)
2018 if (!DISP_IN_RANGE (offset
))
2023 /* All the special cases are pointers. */
2026 /* In the small-PIC case, the linker converts @GOT
2027 and @GOTNTPOFF offsets to possible displacements. */
2028 if (GET_CODE (disp
) == UNSPEC
2029 && (XINT (disp
, 1) == UNSPEC_GOT
2030 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2036 /* Accept pool label offsets. */
2037 else if (GET_CODE (disp
) == UNSPEC
2038 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2041 /* Accept literal pool references. */
2042 else if (GET_CODE (disp
) == UNSPEC
2043 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2045 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2048 /* If we have an offset, make sure it does not
2049 exceed the size of the constant pool entry. */
2050 rtx sym
= XVECEXP (disp
, 0, 0);
2051 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2054 orig_disp
= plus_constant (orig_disp
, offset
);
2069 out
->disp
= orig_disp
;
2070 out
->pointer
= pointer
;
2071 out
->literal_pool
= literal_pool
;
2077 /* Decompose a RTL expression OP for a shift count into its components,
2078 and return the base register in BASE and the offset in OFFSET.
2080 Return true if OP is a valid shift count, false if not. */
2083 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2085 HOST_WIDE_INT off
= 0;
2087 /* We can have an integer constant, an address register,
2088 or a sum of the two. */
2089 if (GET_CODE (op
) == CONST_INT
)
2094 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2096 off
= INTVAL (XEXP (op
, 1));
2099 while (op
&& GET_CODE (op
) == SUBREG
)
2100 op
= SUBREG_REG (op
);
2102 if (op
&& GET_CODE (op
) != REG
)
2114 /* Return true if CODE is a valid address without index. */
2117 s390_legitimate_address_without_index_p (rtx op
)
2119 struct s390_address addr
;
2121 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2130 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2131 and return these parts in SYMREF and ADDEND. You can pass NULL in
2132 SYMREF and/or ADDEND if you are not interested in these values.
2133 Literal pool references are *not* considered symbol references. */
2136 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2138 HOST_WIDE_INT tmpaddend
= 0;
2140 if (GET_CODE (addr
) == CONST
)
2141 addr
= XEXP (addr
, 0);
2143 if (GET_CODE (addr
) == PLUS
)
2145 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2146 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2147 && CONST_INT_P (XEXP (addr
, 1)))
2149 tmpaddend
= INTVAL (XEXP (addr
, 1));
2150 addr
= XEXP (addr
, 0);
2156 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2162 *addend
= tmpaddend
;
2168 /* Return true if the address in OP is valid for constraint letter C
2169 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2170 pool MEMs should be accepted. Only the Q, R, S, T constraint
2171 letters are allowed for C. */
2174 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2176 struct s390_address addr
;
2177 bool decomposed
= false;
2179 /* This check makes sure that no symbolic address (except literal
2180 pool references) are accepted by the R or T constraints. */
2181 if (s390_symref_operand_p (op
, NULL
, NULL
))
2184 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2187 if (!s390_decompose_address (op
, &addr
))
2189 if (addr
.literal_pool
)
2196 case 'Q': /* no index short displacement */
2197 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2201 if (!s390_short_displacement (addr
.disp
))
2205 case 'R': /* with index short displacement */
2206 if (TARGET_LONG_DISPLACEMENT
)
2208 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2210 if (!s390_short_displacement (addr
.disp
))
2213 /* Any invalid address here will be fixed up by reload,
2214 so accept it for the most generic constraint. */
2217 case 'S': /* no index long displacement */
2218 if (!TARGET_LONG_DISPLACEMENT
)
2220 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2224 if (s390_short_displacement (addr
.disp
))
2228 case 'T': /* with index long displacement */
2229 if (!TARGET_LONG_DISPLACEMENT
)
2231 /* Any invalid address here will be fixed up by reload,
2232 so accept it for the most generic constraint. */
2233 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2234 && s390_short_displacement (addr
.disp
))
2244 /* Evaluates constraint strings described by the regular expression
2245 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2246 the constraint given in STR, or 0 else. */
2249 s390_mem_constraint (const char *str
, rtx op
)
2256 /* Check for offsettable variants of memory constraints. */
2257 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2259 if ((reload_completed
|| reload_in_progress
)
2260 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2262 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2264 /* Check for non-literal-pool variants of memory constraints. */
2267 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2272 if (GET_CODE (op
) != MEM
)
2274 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2276 return (s390_check_qrst_address ('Q', op
, true)
2277 || s390_check_qrst_address ('R', op
, true));
2279 return (s390_check_qrst_address ('S', op
, true)
2280 || s390_check_qrst_address ('T', op
, true));
2282 /* Simply check for the basic form of a shift count. Reload will
2283 take care of making sure we have a proper base register. */
2284 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2288 return s390_check_qrst_address (str
[1], op
, true);
2296 /* Evaluates constraint strings starting with letter O. Input
2297 parameter C is the second letter following the "O" in the constraint
2298 string. Returns 1 if VALUE meets the respective constraint and 0
2302 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2310 return trunc_int_for_mode (value
, SImode
) == value
;
2314 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2317 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2325 /* Evaluates constraint strings starting with letter N. Parameter STR
2326 contains the letters following letter "N" in the constraint string.
2327 Returns true if VALUE matches the constraint. */
2330 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2332 enum machine_mode mode
, part_mode
;
2334 int part
, part_goal
;
2340 part_goal
= str
[0] - '0';
2384 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2387 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2390 if (part_goal
!= -1 && part_goal
!= part
)
2397 /* Returns true if the input parameter VALUE is a float zero. */
2400 s390_float_const_zero_p (rtx value
)
2402 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2403 && value
== CONST0_RTX (GET_MODE (value
)));
2407 /* Compute a (partial) cost for rtx X. Return true if the complete
2408 cost has been computed, and false if subexpressions should be
2409 scanned. In either case, *TOTAL contains the cost result.
2410 CODE contains GET_CODE (x), OUTER_CODE contains the code
2411 of the superexpression of x. */
2414 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2415 bool speed ATTRIBUTE_UNUSED
)
2438 *total
= COSTS_N_INSNS (1);
2443 /* Check for multiply and add. */
2444 if ((GET_MODE (x
) == DFmode
|| GET_MODE (x
) == SFmode
)
2445 && GET_CODE (XEXP (x
, 0)) == MULT
2446 && TARGET_HARD_FLOAT
&& TARGET_FUSED_MADD
)
2448 /* This is the multiply and add case. */
2449 if (GET_MODE (x
) == DFmode
)
2450 *total
= s390_cost
->madbr
;
2452 *total
= s390_cost
->maebr
;
2453 *total
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), MULT
, speed
)
2454 + rtx_cost (XEXP (XEXP (x
, 0), 1), MULT
, speed
)
2455 + rtx_cost (XEXP (x
, 1), (enum rtx_code
) code
, speed
));
2456 return true; /* Do not do an additional recursive descent. */
2458 *total
= COSTS_N_INSNS (1);
2462 switch (GET_MODE (x
))
2466 rtx left
= XEXP (x
, 0);
2467 rtx right
= XEXP (x
, 1);
2468 if (GET_CODE (right
) == CONST_INT
2469 && CONST_OK_FOR_K (INTVAL (right
)))
2470 *total
= s390_cost
->mhi
;
2471 else if (GET_CODE (left
) == SIGN_EXTEND
)
2472 *total
= s390_cost
->mh
;
2474 *total
= s390_cost
->ms
; /* msr, ms, msy */
2479 rtx left
= XEXP (x
, 0);
2480 rtx right
= XEXP (x
, 1);
2483 if (GET_CODE (right
) == CONST_INT
2484 && CONST_OK_FOR_K (INTVAL (right
)))
2485 *total
= s390_cost
->mghi
;
2486 else if (GET_CODE (left
) == SIGN_EXTEND
)
2487 *total
= s390_cost
->msgf
;
2489 *total
= s390_cost
->msg
; /* msgr, msg */
2491 else /* TARGET_31BIT */
2493 if (GET_CODE (left
) == SIGN_EXTEND
2494 && GET_CODE (right
) == SIGN_EXTEND
)
2495 /* mulsidi case: mr, m */
2496 *total
= s390_cost
->m
;
2497 else if (GET_CODE (left
) == ZERO_EXTEND
2498 && GET_CODE (right
) == ZERO_EXTEND
2499 && TARGET_CPU_ZARCH
)
2500 /* umulsidi case: ml, mlr */
2501 *total
= s390_cost
->ml
;
2503 /* Complex calculation is required. */
2504 *total
= COSTS_N_INSNS (40);
2510 *total
= s390_cost
->mult_df
;
2513 *total
= s390_cost
->mxbr
;
2522 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2523 *total
= s390_cost
->dlgr
;
2524 else if (GET_MODE (x
) == DImode
)
2526 rtx right
= XEXP (x
, 1);
2527 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2528 *total
= s390_cost
->dlr
;
2529 else /* 64 by 64 bit division */
2530 *total
= s390_cost
->dlgr
;
2532 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2533 *total
= s390_cost
->dlr
;
2538 if (GET_MODE (x
) == DImode
)
2540 rtx right
= XEXP (x
, 1);
2541 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2543 *total
= s390_cost
->dsgfr
;
2545 *total
= s390_cost
->dr
;
2546 else /* 64 by 64 bit division */
2547 *total
= s390_cost
->dsgr
;
2549 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2550 *total
= s390_cost
->dlr
;
2551 else if (GET_MODE (x
) == SFmode
)
2553 *total
= s390_cost
->debr
;
2555 else if (GET_MODE (x
) == DFmode
)
2557 *total
= s390_cost
->ddbr
;
2559 else if (GET_MODE (x
) == TFmode
)
2561 *total
= s390_cost
->dxbr
;
2566 if (GET_MODE (x
) == SFmode
)
2567 *total
= s390_cost
->sqebr
;
2568 else if (GET_MODE (x
) == DFmode
)
2569 *total
= s390_cost
->sqdbr
;
2571 *total
= s390_cost
->sqxbr
;
2576 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2577 || outer_code
== PLUS
|| outer_code
== MINUS
2578 || outer_code
== COMPARE
)
2583 *total
= COSTS_N_INSNS (1);
2584 if (GET_CODE (XEXP (x
, 0)) == AND
2585 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2586 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2588 rtx op0
= XEXP (XEXP (x
, 0), 0);
2589 rtx op1
= XEXP (XEXP (x
, 0), 1);
2590 rtx op2
= XEXP (x
, 1);
2592 if (memory_operand (op0
, GET_MODE (op0
))
2593 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2595 if (register_operand (op0
, GET_MODE (op0
))
2596 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2606 /* Return the cost of an address rtx ADDR. */
2609 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2611 struct s390_address ad
;
2612 if (!s390_decompose_address (addr
, &ad
))
2615 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2618 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2619 otherwise return 0. */
2622 tls_symbolic_operand (rtx op
)
2624 if (GET_CODE (op
) != SYMBOL_REF
)
2626 return SYMBOL_REF_TLS_MODEL (op
);
2629 /* Split DImode access register reference REG (on 64-bit) into its constituent
2630 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2631 gen_highpart cannot be used as they assume all registers are word-sized,
2632 while our access registers have only half that size. */
2635 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2637 gcc_assert (TARGET_64BIT
);
2638 gcc_assert (ACCESS_REG_P (reg
));
2639 gcc_assert (GET_MODE (reg
) == DImode
);
2640 gcc_assert (!(REGNO (reg
) & 1));
2642 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2643 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2646 /* Return true if OP contains a symbol reference */
2649 symbolic_reference_mentioned_p (rtx op
)
2654 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2657 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2658 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2664 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2665 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2669 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2676 /* Return true if OP contains a reference to a thread-local symbol. */
2679 tls_symbolic_reference_mentioned_p (rtx op
)
2684 if (GET_CODE (op
) == SYMBOL_REF
)
2685 return tls_symbolic_operand (op
);
2687 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2688 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2694 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2695 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2699 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2707 /* Return true if OP is a legitimate general operand when
2708 generating PIC code. It is given that flag_pic is on
2709 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2712 legitimate_pic_operand_p (rtx op
)
2714 /* Accept all non-symbolic constants. */
2715 if (!SYMBOLIC_CONST (op
))
2718 /* Reject everything else; must be handled
2719 via emit_symbolic_move. */
2723 /* Returns true if the constant value OP is a legitimate general operand.
2724 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2727 legitimate_constant_p (rtx op
)
2729 /* Accept all non-symbolic constants. */
2730 if (!SYMBOLIC_CONST (op
))
2733 /* Accept immediate LARL operands. */
2734 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2737 /* Thread-local symbols are never legal constants. This is
2738 so that emit_call knows that computing such addresses
2739 might require a function call. */
2740 if (TLS_SYMBOLIC_CONST (op
))
2743 /* In the PIC case, symbolic constants must *not* be
2744 forced into the literal pool. We accept them here,
2745 so that they will be handled by emit_symbolic_move. */
2749 /* All remaining non-PIC symbolic constants are
2750 forced into the literal pool. */
2754 /* Determine if it's legal to put X into the constant pool. This
2755 is not possible if X contains the address of a symbol that is
2756 not constant (TLS) or not known at final link time (PIC). */
2759 s390_cannot_force_const_mem (rtx x
)
2761 switch (GET_CODE (x
))
2765 /* Accept all non-symbolic constants. */
2769 /* Labels are OK iff we are non-PIC. */
2770 return flag_pic
!= 0;
2773 /* 'Naked' TLS symbol references are never OK,
2774 non-TLS symbols are OK iff we are non-PIC. */
2775 if (tls_symbolic_operand (x
))
2778 return flag_pic
!= 0;
2781 return s390_cannot_force_const_mem (XEXP (x
, 0));
2784 return s390_cannot_force_const_mem (XEXP (x
, 0))
2785 || s390_cannot_force_const_mem (XEXP (x
, 1));
2788 switch (XINT (x
, 1))
2790 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2791 case UNSPEC_LTREL_OFFSET
:
2799 case UNSPEC_GOTNTPOFF
:
2800 case UNSPEC_INDNTPOFF
:
2803 /* If the literal pool shares the code section, be put
2804 execute template placeholders into the pool as well. */
2806 return TARGET_CPU_ZARCH
;
2818 /* Returns true if the constant value OP is a legitimate general
2819 operand during and after reload. The difference to
2820 legitimate_constant_p is that this function will not accept
2821 a constant that would need to be forced to the literal pool
2822 before it can be used as operand.
2823 This function accepts all constants which can be loaded directly
2827 legitimate_reload_constant_p (rtx op
)
2829 /* Accept la(y) operands. */
2830 if (GET_CODE (op
) == CONST_INT
2831 && DISP_IN_RANGE (INTVAL (op
)))
2834 /* Accept l(g)hi/l(g)fi operands. */
2835 if (GET_CODE (op
) == CONST_INT
2836 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2839 /* Accept lliXX operands. */
2841 && GET_CODE (op
) == CONST_INT
2842 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2843 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2847 && GET_CODE (op
) == CONST_INT
2848 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2849 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2852 /* Accept larl operands. */
2853 if (TARGET_CPU_ZARCH
2854 && larl_operand (op
, VOIDmode
))
2857 /* Accept floating-point zero operands that fit into a single GPR. */
2858 if (GET_CODE (op
) == CONST_DOUBLE
2859 && s390_float_const_zero_p (op
)
2860 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2863 /* Accept double-word operands that can be split. */
2864 if (GET_CODE (op
) == CONST_INT
2865 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2867 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2868 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2869 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2870 return legitimate_reload_constant_p (hi
)
2871 && legitimate_reload_constant_p (lo
);
2874 /* Everything else cannot be handled without reload. */
2878 /* Returns true if the constant value OP is a legitimate fp operand
2879 during and after reload.
2880 This function accepts all constants which can be loaded directly
2884 legitimate_reload_fp_constant_p (rtx op
)
2886 /* Accept floating-point zero operands if the load zero instruction
2889 && GET_CODE (op
) == CONST_DOUBLE
2890 && s390_float_const_zero_p (op
))
2896 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2897 return the class of reg to actually use. */
2900 s390_preferred_reload_class (rtx op
, enum reg_class rclass
)
2902 switch (GET_CODE (op
))
2904 /* Constants we cannot reload into general registers
2905 must be forced into the literal pool. */
2908 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2909 && legitimate_reload_constant_p (op
))
2910 return GENERAL_REGS
;
2911 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2912 && legitimate_reload_constant_p (op
))
2914 else if (reg_class_subset_p (FP_REGS
, rclass
)
2915 && legitimate_reload_fp_constant_p (op
))
2919 /* If a symbolic constant or a PLUS is reloaded,
2920 it is most likely being used as an address, so
2921 prefer ADDR_REGS. If 'class' is not a superset
2922 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2927 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2939 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2940 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2944 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2946 HOST_WIDE_INT addend
;
2949 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2952 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
2953 && !(addend
& (alignment
- 1)));
2956 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2957 operand SCRATCH is used to reload the even part of the address and
2961 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
2963 HOST_WIDE_INT addend
;
2966 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2970 /* Easy case. The addend is even so larl will do fine. */
2971 emit_move_insn (reg
, addr
);
2974 /* We can leave the scratch register untouched if the target
2975 register is a valid base register. */
2976 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
2977 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
2980 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
2981 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
2984 emit_move_insn (scratch
,
2985 gen_rtx_CONST (Pmode
,
2986 gen_rtx_PLUS (Pmode
, symref
,
2987 GEN_INT (addend
- 1))));
2989 emit_move_insn (scratch
, symref
);
2991 /* Increment the address using la in order to avoid clobbering cc. */
2992 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
2996 /* Generate what is necessary to move between REG and MEM using
2997 SCRATCH. The direction is given by TOMEM. */
3000 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3002 /* Reload might have pulled a constant out of the literal pool.
3003 Force it back in. */
3004 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3005 || GET_CODE (mem
) == CONST
)
3006 mem
= force_const_mem (GET_MODE (reg
), mem
);
3008 gcc_assert (MEM_P (mem
));
3010 /* For a load from memory we can leave the scratch register
3011 untouched if the target register is a valid base register. */
3013 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3014 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3015 && GET_MODE (reg
) == GET_MODE (scratch
))
3018 /* Load address into scratch register. Since we can't have a
3019 secondary reload for a secondary reload we have to cover the case
3020 where larl would need a secondary reload here as well. */
3021 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3023 /* Now we can use a standard load/store to do the move. */
3025 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3027 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3030 /* Inform reload about cases where moving X with a mode MODE to a register in
3031 RCLASS requires an extra scratch or immediate register. Return the class
3032 needed for the immediate register. */
3035 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3036 enum machine_mode mode
, secondary_reload_info
*sri
)
3038 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3040 /* Intermediate register needed. */
3041 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3042 return GENERAL_REGS
;
3046 /* On z10 several optimizer steps may generate larl operands with
3049 && s390_symref_operand_p (x
, NULL
, NULL
)
3051 && !s390_check_symref_alignment (x
, 2))
3052 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3053 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3055 /* On z10 we need a scratch register when moving QI, TI or floating
3056 point mode values from or to a memory location with a SYMBOL_REF
3057 or if the symref addend of a SI or DI move is not aligned to the
3058 width of the access. */
3060 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3061 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3062 || (!TARGET_ZARCH
&& mode
== DImode
)
3063 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3064 && (!s390_check_symref_alignment (XEXP (x
, 0),
3065 GET_MODE_SIZE (mode
))))))
3067 #define __SECONDARY_RELOAD_CASE(M,m) \
3070 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3071 CODE_FOR_reload##m##di_tomem_z10; \
3073 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3074 CODE_FOR_reload##m##si_tomem_z10; \
3077 switch (GET_MODE (x
))
3079 __SECONDARY_RELOAD_CASE (QI
, qi
);
3080 __SECONDARY_RELOAD_CASE (HI
, hi
);
3081 __SECONDARY_RELOAD_CASE (SI
, si
);
3082 __SECONDARY_RELOAD_CASE (DI
, di
);
3083 __SECONDARY_RELOAD_CASE (TI
, ti
);
3084 __SECONDARY_RELOAD_CASE (SF
, sf
);
3085 __SECONDARY_RELOAD_CASE (DF
, df
);
3086 __SECONDARY_RELOAD_CASE (TF
, tf
);
3087 __SECONDARY_RELOAD_CASE (SD
, sd
);
3088 __SECONDARY_RELOAD_CASE (DD
, dd
);
3089 __SECONDARY_RELOAD_CASE (TD
, td
);
3094 #undef __SECONDARY_RELOAD_CASE
3098 /* We need a scratch register when loading a PLUS expression which
3099 is not a legitimate operand of the LOAD ADDRESS instruction. */
3100 if (in_p
&& s390_plus_operand (x
, mode
))
3101 sri
->icode
= (TARGET_64BIT
?
3102 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3104 /* Performing a multiword move from or to memory we have to make sure the
3105 second chunk in memory is addressable without causing a displacement
3106 overflow. If that would be the case we calculate the address in
3107 a scratch register. */
3109 && GET_CODE (XEXP (x
, 0)) == PLUS
3110 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3111 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3112 + GET_MODE_SIZE (mode
) - 1))
3114 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3115 in a s_operand address since we may fallback to lm/stm. So we only
3116 have to care about overflows in the b+i+d case. */
3117 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3118 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3119 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3120 /* For FP_REGS no lm/stm is available so this check is triggered
3121 for displacement overflows in b+i+d and b+d like addresses. */
3122 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3123 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3126 sri
->icode
= (TARGET_64BIT
?
3127 CODE_FOR_reloaddi_nonoffmem_in
:
3128 CODE_FOR_reloadsi_nonoffmem_in
);
3130 sri
->icode
= (TARGET_64BIT
?
3131 CODE_FOR_reloaddi_nonoffmem_out
:
3132 CODE_FOR_reloadsi_nonoffmem_out
);
3136 /* A scratch address register is needed when a symbolic constant is
3137 copied to r0 compiling with -fPIC. In other cases the target
3138 register might be used as temporary (see legitimize_pic_address). */
3139 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3140 sri
->icode
= (TARGET_64BIT
?
3141 CODE_FOR_reloaddi_PIC_addr
:
3142 CODE_FOR_reloadsi_PIC_addr
);
3144 /* Either scratch or no register needed. */
3148 /* Generate code to load SRC, which is PLUS that is not a
3149 legitimate operand for the LA instruction, into TARGET.
3150 SCRATCH may be used as scratch register. */
3153 s390_expand_plus_operand (rtx target
, rtx src
,
3157 struct s390_address ad
;
3159 /* src must be a PLUS; get its two operands. */
3160 gcc_assert (GET_CODE (src
) == PLUS
);
3161 gcc_assert (GET_MODE (src
) == Pmode
);
3163 /* Check if any of the two operands is already scheduled
3164 for replacement by reload. This can happen e.g. when
3165 float registers occur in an address. */
3166 sum1
= find_replacement (&XEXP (src
, 0));
3167 sum2
= find_replacement (&XEXP (src
, 1));
3168 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3170 /* If the address is already strictly valid, there's nothing to do. */
3171 if (!s390_decompose_address (src
, &ad
)
3172 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3173 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3175 /* Otherwise, one of the operands cannot be an address register;
3176 we reload its value into the scratch register. */
3177 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3179 emit_move_insn (scratch
, sum1
);
3182 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3184 emit_move_insn (scratch
, sum2
);
3188 /* According to the way these invalid addresses are generated
3189 in reload.c, it should never happen (at least on s390) that
3190 *neither* of the PLUS components, after find_replacements
3191 was applied, is an address register. */
3192 if (sum1
== scratch
&& sum2
== scratch
)
3198 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3201 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3202 is only ever performed on addresses, so we can mark the
3203 sum as legitimate for LA in any case. */
3204 s390_load_address (target
, src
);
3208 /* Return true if ADDR is a valid memory address.
3209 STRICT specifies whether strict register checking applies. */
3212 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3214 struct s390_address ad
;
3217 && larl_operand (addr
, VOIDmode
)
3218 && (mode
== VOIDmode
3219 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3222 if (!s390_decompose_address (addr
, &ad
))
3227 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3230 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3236 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3237 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3241 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3242 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3248 /* Return true if OP is a valid operand for the LA instruction.
3249 In 31-bit, we need to prove that the result is used as an
3250 address, as LA performs only a 31-bit addition. */
3253 legitimate_la_operand_p (rtx op
)
3255 struct s390_address addr
;
3256 if (!s390_decompose_address (op
, &addr
))
3259 return (TARGET_64BIT
|| addr
.pointer
);
3262 /* Return true if it is valid *and* preferable to use LA to
3263 compute the sum of OP1 and OP2. */
3266 preferred_la_operand_p (rtx op1
, rtx op2
)
3268 struct s390_address addr
;
3270 if (op2
!= const0_rtx
)
3271 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3273 if (!s390_decompose_address (op1
, &addr
))
3275 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3277 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3280 /* Avoid LA instructions with index register on z196; it is
3281 preferable to use regular add instructions when possible. */
3282 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3285 if (!TARGET_64BIT
&& !addr
.pointer
)
3291 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3292 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3298 /* Emit a forced load-address operation to load SRC into DST.
3299 This will use the LOAD ADDRESS instruction even in situations
3300 where legitimate_la_operand_p (SRC) returns false. */
3303 s390_load_address (rtx dst
, rtx src
)
3306 emit_move_insn (dst
, src
);
3308 emit_insn (gen_force_la_31 (dst
, src
));
3311 /* Return a legitimate reference for ORIG (an address) using the
3312 register REG. If REG is 0, a new pseudo is generated.
3314 There are two types of references that must be handled:
3316 1. Global data references must load the address from the GOT, via
3317 the PIC reg. An insn is emitted to do this load, and the reg is
3320 2. Static data references, constant pool addresses, and code labels
3321 compute the address as an offset from the GOT, whose base is in
3322 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3323 differentiate them from global data objects. The returned
3324 address is the PIC reg + an unspec constant.
3326 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3327 reg also appears in the address. */
3330 legitimize_pic_address (rtx orig
, rtx reg
)
3336 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3338 if (GET_CODE (addr
) == LABEL_REF
3339 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3341 /* This is a local symbol. */
3342 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3344 /* Access local symbols PC-relative via LARL.
3345 This is the same as in the non-PIC case, so it is
3346 handled automatically ... */
3350 /* Access local symbols relative to the GOT. */
3352 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3354 if (reload_in_progress
|| reload_completed
)
3355 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3357 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3358 addr
= gen_rtx_CONST (Pmode
, addr
);
3359 addr
= force_const_mem (Pmode
, addr
);
3360 emit_move_insn (temp
, addr
);
3362 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3365 s390_load_address (reg
, new_rtx
);
3370 else if (GET_CODE (addr
) == SYMBOL_REF
)
3373 reg
= gen_reg_rtx (Pmode
);
3377 /* Assume GOT offset < 4k. This is handled the same way
3378 in both 31- and 64-bit code (@GOT). */
3380 if (reload_in_progress
|| reload_completed
)
3381 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3383 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3384 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3385 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3386 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3387 emit_move_insn (reg
, new_rtx
);
3390 else if (TARGET_CPU_ZARCH
)
3392 /* If the GOT offset might be >= 4k, we determine the position
3393 of the GOT entry via a PC-relative LARL (@GOTENT). */
3395 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3397 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3398 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3400 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3401 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3402 emit_move_insn (temp
, new_rtx
);
3404 new_rtx
= gen_const_mem (Pmode
, temp
);
3405 emit_move_insn (reg
, new_rtx
);
3410 /* If the GOT offset might be >= 4k, we have to load it
3411 from the literal pool (@GOT). */
3413 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3415 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3416 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3418 if (reload_in_progress
|| reload_completed
)
3419 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3421 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3422 addr
= gen_rtx_CONST (Pmode
, addr
);
3423 addr
= force_const_mem (Pmode
, addr
);
3424 emit_move_insn (temp
, addr
);
3426 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3427 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3428 emit_move_insn (reg
, new_rtx
);
3434 if (GET_CODE (addr
) == CONST
)
3436 addr
= XEXP (addr
, 0);
3437 if (GET_CODE (addr
) == UNSPEC
)
3439 gcc_assert (XVECLEN (addr
, 0) == 1);
3440 switch (XINT (addr
, 1))
3442 /* If someone moved a GOT-relative UNSPEC
3443 out of the literal pool, force them back in. */
3446 new_rtx
= force_const_mem (Pmode
, orig
);
3449 /* @GOT is OK as is if small. */
3452 new_rtx
= force_const_mem (Pmode
, orig
);
3455 /* @GOTENT is OK as is. */
3459 /* @PLT is OK as is on 64-bit, must be converted to
3460 GOT-relative @PLTOFF on 31-bit. */
3462 if (!TARGET_CPU_ZARCH
)
3464 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3466 if (reload_in_progress
|| reload_completed
)
3467 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3469 addr
= XVECEXP (addr
, 0, 0);
3470 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3472 addr
= gen_rtx_CONST (Pmode
, addr
);
3473 addr
= force_const_mem (Pmode
, addr
);
3474 emit_move_insn (temp
, addr
);
3476 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3479 s390_load_address (reg
, new_rtx
);
3485 /* Everything else cannot happen. */
3491 gcc_assert (GET_CODE (addr
) == PLUS
);
3493 if (GET_CODE (addr
) == PLUS
)
3495 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3497 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3498 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3500 /* Check first to see if this is a constant offset
3501 from a local symbol reference. */
3502 if ((GET_CODE (op0
) == LABEL_REF
3503 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3504 && GET_CODE (op1
) == CONST_INT
)
3506 if (TARGET_CPU_ZARCH
3507 && larl_operand (op0
, VOIDmode
)
3508 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3509 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3511 if (INTVAL (op1
) & 1)
3513 /* LARL can't handle odd offsets, so emit a
3514 pair of LARL and LA. */
3515 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3517 if (!DISP_IN_RANGE (INTVAL (op1
)))
3519 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3520 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3521 op0
= gen_rtx_CONST (Pmode
, op0
);
3525 emit_move_insn (temp
, op0
);
3526 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3530 s390_load_address (reg
, new_rtx
);
3536 /* If the offset is even, we can just use LARL.
3537 This will happen automatically. */
3542 /* Access local symbols relative to the GOT. */
3544 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3546 if (reload_in_progress
|| reload_completed
)
3547 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3549 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3551 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3552 addr
= gen_rtx_CONST (Pmode
, addr
);
3553 addr
= force_const_mem (Pmode
, addr
);
3554 emit_move_insn (temp
, addr
);
3556 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3559 s390_load_address (reg
, new_rtx
);
3565 /* Now, check whether it is a GOT relative symbol plus offset
3566 that was pulled out of the literal pool. Force it back in. */
3568 else if (GET_CODE (op0
) == UNSPEC
3569 && GET_CODE (op1
) == CONST_INT
3570 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3572 gcc_assert (XVECLEN (op0
, 0) == 1);
3574 new_rtx
= force_const_mem (Pmode
, orig
);
3577 /* Otherwise, compute the sum. */
3580 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3581 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3582 base
== reg
? NULL_RTX
: reg
);
3583 if (GET_CODE (new_rtx
) == CONST_INT
)
3584 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3587 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3589 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3590 new_rtx
= XEXP (new_rtx
, 1);
3592 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3595 if (GET_CODE (new_rtx
) == CONST
)
3596 new_rtx
= XEXP (new_rtx
, 0);
3597 new_rtx
= force_operand (new_rtx
, 0);
3604 /* Load the thread pointer into a register. */
3607 s390_get_thread_pointer (void)
3609 rtx tp
= gen_reg_rtx (Pmode
);
3611 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3612 mark_reg_pointer (tp
, BITS_PER_WORD
);
3617 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3618 in s390_tls_symbol which always refers to __tls_get_offset.
3619 The returned offset is written to RESULT_REG and an USE rtx is
3620 generated for TLS_CALL. */
3622 static GTY(()) rtx s390_tls_symbol
;
3625 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3629 gcc_assert (flag_pic
);
3631 if (!s390_tls_symbol
)
3632 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3634 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3635 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3637 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3638 RTL_CONST_CALL_P (insn
) = 1;
3641 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3642 this (thread-local) address. REG may be used as temporary. */
3645 legitimize_tls_address (rtx addr
, rtx reg
)
3647 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3649 if (GET_CODE (addr
) == SYMBOL_REF
)
3650 switch (tls_symbolic_operand (addr
))
3652 case TLS_MODEL_GLOBAL_DYNAMIC
:
3654 r2
= gen_rtx_REG (Pmode
, 2);
3655 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3656 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3657 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3658 emit_move_insn (r2
, new_rtx
);
3659 s390_emit_tls_call_insn (r2
, tls_call
);
3660 insn
= get_insns ();
3663 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3664 temp
= gen_reg_rtx (Pmode
);
3665 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3667 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3670 s390_load_address (reg
, new_rtx
);
3675 case TLS_MODEL_LOCAL_DYNAMIC
:
3677 r2
= gen_rtx_REG (Pmode
, 2);
3678 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3679 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3680 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3681 emit_move_insn (r2
, new_rtx
);
3682 s390_emit_tls_call_insn (r2
, tls_call
);
3683 insn
= get_insns ();
3686 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3687 temp
= gen_reg_rtx (Pmode
);
3688 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3690 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3691 base
= gen_reg_rtx (Pmode
);
3692 s390_load_address (base
, new_rtx
);
3694 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3695 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3696 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3697 temp
= gen_reg_rtx (Pmode
);
3698 emit_move_insn (temp
, new_rtx
);
3700 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3703 s390_load_address (reg
, new_rtx
);
3708 case TLS_MODEL_INITIAL_EXEC
:
3711 /* Assume GOT offset < 4k. This is handled the same way
3712 in both 31- and 64-bit code. */
3714 if (reload_in_progress
|| reload_completed
)
3715 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3717 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3718 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3719 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3720 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3721 temp
= gen_reg_rtx (Pmode
);
3722 emit_move_insn (temp
, new_rtx
);
3724 else if (TARGET_CPU_ZARCH
)
3726 /* If the GOT offset might be >= 4k, we determine the position
3727 of the GOT entry via a PC-relative LARL. */
3729 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3730 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3731 temp
= gen_reg_rtx (Pmode
);
3732 emit_move_insn (temp
, new_rtx
);
3734 new_rtx
= gen_const_mem (Pmode
, temp
);
3735 temp
= gen_reg_rtx (Pmode
);
3736 emit_move_insn (temp
, new_rtx
);
3740 /* If the GOT offset might be >= 4k, we have to load it
3741 from the literal pool. */
3743 if (reload_in_progress
|| reload_completed
)
3744 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3746 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3747 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3748 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3749 temp
= gen_reg_rtx (Pmode
);
3750 emit_move_insn (temp
, new_rtx
);
3752 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3753 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3755 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3756 temp
= gen_reg_rtx (Pmode
);
3757 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3761 /* In position-dependent code, load the absolute address of
3762 the GOT entry from the literal pool. */
3764 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3765 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3766 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3767 temp
= gen_reg_rtx (Pmode
);
3768 emit_move_insn (temp
, new_rtx
);
3771 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3772 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3773 temp
= gen_reg_rtx (Pmode
);
3774 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3777 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3780 s390_load_address (reg
, new_rtx
);
3785 case TLS_MODEL_LOCAL_EXEC
:
3786 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3787 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3788 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3789 temp
= gen_reg_rtx (Pmode
);
3790 emit_move_insn (temp
, new_rtx
);
3792 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3795 s390_load_address (reg
, new_rtx
);
3804 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3806 switch (XINT (XEXP (addr
, 0), 1))
3808 case UNSPEC_INDNTPOFF
:
3809 gcc_assert (TARGET_CPU_ZARCH
);
3818 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3819 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3821 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3822 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3823 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3825 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3826 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3827 new_rtx
= force_operand (new_rtx
, 0);
3831 gcc_unreachable (); /* for now ... */
3836 /* Emit insns making the address in operands[1] valid for a standard
3837 move to operands[0]. operands[1] is replaced by an address which
3838 should be used instead of the former RTX to emit the move
3842 emit_symbolic_move (rtx
*operands
)
3844 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3846 if (GET_CODE (operands
[0]) == MEM
)
3847 operands
[1] = force_reg (Pmode
, operands
[1]);
3848 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3849 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3851 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3854 /* Try machine-dependent ways of modifying an illegitimate address X
3855 to be legitimate. If we find one, return the new, valid address.
3857 OLDX is the address as it was before break_out_memory_refs was called.
3858 In some cases it is useful to look at this to decide what needs to be done.
3860 MODE is the mode of the operand pointed to by X.
3862 When -fpic is used, special handling is needed for symbolic references.
3863 See comments by legitimize_pic_address for details. */
3866 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3867 enum machine_mode mode ATTRIBUTE_UNUSED
)
3869 rtx constant_term
= const0_rtx
;
3871 if (TLS_SYMBOLIC_CONST (x
))
3873 x
= legitimize_tls_address (x
, 0);
3875 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3878 else if (GET_CODE (x
) == PLUS
3879 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3880 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3886 if (SYMBOLIC_CONST (x
)
3887 || (GET_CODE (x
) == PLUS
3888 && (SYMBOLIC_CONST (XEXP (x
, 0))
3889 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3890 x
= legitimize_pic_address (x
, 0);
3892 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3896 x
= eliminate_constant_term (x
, &constant_term
);
3898 /* Optimize loading of large displacements by splitting them
3899 into the multiple of 4K and the rest; this allows the
3900 former to be CSE'd if possible.
3902 Don't do this if the displacement is added to a register
3903 pointing into the stack frame, as the offsets will
3904 change later anyway. */
3906 if (GET_CODE (constant_term
) == CONST_INT
3907 && !TARGET_LONG_DISPLACEMENT
3908 && !DISP_IN_RANGE (INTVAL (constant_term
))
3909 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3911 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3912 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3914 rtx temp
= gen_reg_rtx (Pmode
);
3915 rtx val
= force_operand (GEN_INT (upper
), temp
);
3917 emit_move_insn (temp
, val
);
3919 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3920 constant_term
= GEN_INT (lower
);
3923 if (GET_CODE (x
) == PLUS
)
3925 if (GET_CODE (XEXP (x
, 0)) == REG
)
3927 rtx temp
= gen_reg_rtx (Pmode
);
3928 rtx val
= force_operand (XEXP (x
, 1), temp
);
3930 emit_move_insn (temp
, val
);
3932 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3935 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3937 rtx temp
= gen_reg_rtx (Pmode
);
3938 rtx val
= force_operand (XEXP (x
, 0), temp
);
3940 emit_move_insn (temp
, val
);
3942 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3946 if (constant_term
!= const0_rtx
)
3947 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3952 /* Try a machine-dependent way of reloading an illegitimate address AD
3953 operand. If we find one, push the reload and and return the new address.
3955 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3956 and TYPE is the reload type of the current reload. */
3959 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3960 int opnum
, int type
)
3962 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3965 if (GET_CODE (ad
) == PLUS
)
3967 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3968 XEXP (ad
, 0), XEXP (ad
, 1));
3973 if (GET_CODE (ad
) == PLUS
3974 && GET_CODE (XEXP (ad
, 0)) == REG
3975 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3976 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3978 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3979 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3980 rtx cst
, tem
, new_rtx
;
3982 cst
= GEN_INT (upper
);
3983 if (!legitimate_reload_constant_p (cst
))
3984 cst
= force_const_mem (Pmode
, cst
);
3986 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3987 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3989 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3990 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3991 opnum
, (enum reload_type
) type
);
3998 /* Emit code to move LEN bytes from DST to SRC. */
4001 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
4003 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4005 if (INTVAL (len
) > 0)
4006 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4009 else if (TARGET_MVCLE
)
4011 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4016 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4017 rtx loop_start_label
= gen_label_rtx ();
4018 rtx loop_end_label
= gen_label_rtx ();
4019 rtx end_label
= gen_label_rtx ();
4020 enum machine_mode mode
;
4022 mode
= GET_MODE (len
);
4023 if (mode
== VOIDmode
)
4026 dst_addr
= gen_reg_rtx (Pmode
);
4027 src_addr
= gen_reg_rtx (Pmode
);
4028 count
= gen_reg_rtx (mode
);
4029 blocks
= gen_reg_rtx (mode
);
4031 convert_move (count
, len
, 1);
4032 emit_cmp_and_jump_insns (count
, const0_rtx
,
4033 EQ
, NULL_RTX
, mode
, 1, end_label
);
4035 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4036 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4037 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4038 src
= change_address (src
, VOIDmode
, src_addr
);
4040 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4043 emit_move_insn (count
, temp
);
4045 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4048 emit_move_insn (blocks
, temp
);
4050 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4051 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4053 emit_label (loop_start_label
);
4056 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4060 /* Issue a read prefetch for the +3 cache line. */
4061 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4062 const0_rtx
, const0_rtx
);
4063 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4064 emit_insn (prefetch
);
4066 /* Issue a write prefetch for the +3 cache line. */
4067 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4068 const1_rtx
, const0_rtx
);
4069 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4070 emit_insn (prefetch
);
4073 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4074 s390_load_address (dst_addr
,
4075 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4076 s390_load_address (src_addr
,
4077 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4079 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4082 emit_move_insn (blocks
, temp
);
4084 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4085 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4087 emit_jump (loop_start_label
);
4088 emit_label (loop_end_label
);
4090 emit_insn (gen_movmem_short (dst
, src
,
4091 convert_to_mode (Pmode
, count
, 1)));
4092 emit_label (end_label
);
4096 /* Emit code to set LEN bytes at DST to VAL.
4097 Make use of clrmem if VAL is zero. */
4100 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4102 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4105 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4107 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4109 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4110 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4113 /* Initialize memory by storing the first byte. */
4114 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4116 if (INTVAL (len
) > 1)
4118 /* Initiate 1 byte overlap move.
4119 The first byte of DST is propagated through DSTP1.
4120 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4121 DST is set to size 1 so the rest of the memory location
4122 does not count as source operand. */
4123 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4124 set_mem_size (dst
, const1_rtx
);
4126 emit_insn (gen_movmem_short (dstp1
, dst
,
4127 GEN_INT (INTVAL (len
) - 2)));
4132 else if (TARGET_MVCLE
)
4134 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4135 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4140 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4141 rtx loop_start_label
= gen_label_rtx ();
4142 rtx loop_end_label
= gen_label_rtx ();
4143 rtx end_label
= gen_label_rtx ();
4144 enum machine_mode mode
;
4146 mode
= GET_MODE (len
);
4147 if (mode
== VOIDmode
)
4150 dst_addr
= gen_reg_rtx (Pmode
);
4151 count
= gen_reg_rtx (mode
);
4152 blocks
= gen_reg_rtx (mode
);
4154 convert_move (count
, len
, 1);
4155 emit_cmp_and_jump_insns (count
, const0_rtx
,
4156 EQ
, NULL_RTX
, mode
, 1, end_label
);
4158 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4159 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4161 if (val
== const0_rtx
)
4162 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4166 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4167 set_mem_size (dst
, const1_rtx
);
4169 /* Initialize memory by storing the first byte. */
4170 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4172 /* If count is 1 we are done. */
4173 emit_cmp_and_jump_insns (count
, const1_rtx
,
4174 EQ
, NULL_RTX
, mode
, 1, end_label
);
4176 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4180 emit_move_insn (count
, temp
);
4182 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4185 emit_move_insn (blocks
, temp
);
4187 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4188 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4190 emit_label (loop_start_label
);
4193 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4195 /* Issue a write prefetch for the +4 cache line. */
4196 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4198 const1_rtx
, const0_rtx
);
4199 emit_insn (prefetch
);
4200 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4203 if (val
== const0_rtx
)
4204 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4206 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4207 s390_load_address (dst_addr
,
4208 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4210 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4213 emit_move_insn (blocks
, temp
);
4215 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4216 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4218 emit_jump (loop_start_label
);
4219 emit_label (loop_end_label
);
4221 if (val
== const0_rtx
)
4222 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4224 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4225 emit_label (end_label
);
4229 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4230 and return the result in TARGET. */
4233 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4235 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4238 /* As the result of CMPINT is inverted compared to what we need,
4239 we have to swap the operands. */
4240 tmp
= op0
; op0
= op1
; op1
= tmp
;
4242 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4244 if (INTVAL (len
) > 0)
4246 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4247 emit_insn (gen_cmpint (target
, ccreg
));
4250 emit_move_insn (target
, const0_rtx
);
4252 else if (TARGET_MVCLE
)
4254 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4255 emit_insn (gen_cmpint (target
, ccreg
));
4259 rtx addr0
, addr1
, count
, blocks
, temp
;
4260 rtx loop_start_label
= gen_label_rtx ();
4261 rtx loop_end_label
= gen_label_rtx ();
4262 rtx end_label
= gen_label_rtx ();
4263 enum machine_mode mode
;
4265 mode
= GET_MODE (len
);
4266 if (mode
== VOIDmode
)
4269 addr0
= gen_reg_rtx (Pmode
);
4270 addr1
= gen_reg_rtx (Pmode
);
4271 count
= gen_reg_rtx (mode
);
4272 blocks
= gen_reg_rtx (mode
);
4274 convert_move (count
, len
, 1);
4275 emit_cmp_and_jump_insns (count
, const0_rtx
,
4276 EQ
, NULL_RTX
, mode
, 1, end_label
);
4278 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4279 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4280 op0
= change_address (op0
, VOIDmode
, addr0
);
4281 op1
= change_address (op1
, VOIDmode
, addr1
);
4283 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4286 emit_move_insn (count
, temp
);
4288 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4291 emit_move_insn (blocks
, temp
);
4293 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4294 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4296 emit_label (loop_start_label
);
4299 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4303 /* Issue a read prefetch for the +2 cache line of operand 1. */
4304 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4305 const0_rtx
, const0_rtx
);
4306 emit_insn (prefetch
);
4307 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4309 /* Issue a read prefetch for the +2 cache line of operand 2. */
4310 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4311 const0_rtx
, const0_rtx
);
4312 emit_insn (prefetch
);
4313 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4316 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4317 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4318 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4319 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4320 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4321 emit_jump_insn (temp
);
4323 s390_load_address (addr0
,
4324 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4325 s390_load_address (addr1
,
4326 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4328 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4331 emit_move_insn (blocks
, temp
);
4333 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4334 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4336 emit_jump (loop_start_label
);
4337 emit_label (loop_end_label
);
4339 emit_insn (gen_cmpmem_short (op0
, op1
,
4340 convert_to_mode (Pmode
, count
, 1)));
4341 emit_label (end_label
);
4343 emit_insn (gen_cmpint (target
, ccreg
));
4348 /* Expand conditional increment or decrement using alc/slb instructions.
4349 Should generate code setting DST to either SRC or SRC + INCREMENT,
4350 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4351 Returns true if successful, false otherwise.
4353 That makes it possible to implement some if-constructs without jumps e.g.:
4354 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4355 unsigned int a, b, c;
4356 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4357 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4358 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4359 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4361 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4362 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4363 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4364 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4365 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4368 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4369 rtx dst
, rtx src
, rtx increment
)
4371 enum machine_mode cmp_mode
;
4372 enum machine_mode cc_mode
;
4378 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4379 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4381 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4382 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4387 /* Try ADD LOGICAL WITH CARRY. */
4388 if (increment
== const1_rtx
)
4390 /* Determine CC mode to use. */
4391 if (cmp_code
== EQ
|| cmp_code
== NE
)
4393 if (cmp_op1
!= const0_rtx
)
4395 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4396 NULL_RTX
, 0, OPTAB_WIDEN
);
4397 cmp_op1
= const0_rtx
;
4400 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4403 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4408 cmp_code
= swap_condition (cmp_code
);
4425 /* Emit comparison instruction pattern. */
4426 if (!register_operand (cmp_op0
, cmp_mode
))
4427 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4429 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4430 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4431 /* We use insn_invalid_p here to add clobbers if required. */
4432 ret
= insn_invalid_p (emit_insn (insn
));
4435 /* Emit ALC instruction pattern. */
4436 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4437 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4440 if (src
!= const0_rtx
)
4442 if (!register_operand (src
, GET_MODE (dst
)))
4443 src
= force_reg (GET_MODE (dst
), src
);
4445 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4446 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4449 p
= rtvec_alloc (2);
4451 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4453 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4454 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4459 /* Try SUBTRACT LOGICAL WITH BORROW. */
4460 if (increment
== constm1_rtx
)
4462 /* Determine CC mode to use. */
4463 if (cmp_code
== EQ
|| cmp_code
== NE
)
4465 if (cmp_op1
!= const0_rtx
)
4467 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4468 NULL_RTX
, 0, OPTAB_WIDEN
);
4469 cmp_op1
= const0_rtx
;
4472 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4475 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4480 cmp_code
= swap_condition (cmp_code
);
4497 /* Emit comparison instruction pattern. */
4498 if (!register_operand (cmp_op0
, cmp_mode
))
4499 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4501 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4502 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4503 /* We use insn_invalid_p here to add clobbers if required. */
4504 ret
= insn_invalid_p (emit_insn (insn
));
4507 /* Emit SLB instruction pattern. */
4508 if (!register_operand (src
, GET_MODE (dst
)))
4509 src
= force_reg (GET_MODE (dst
), src
);
4511 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4512 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4513 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4514 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4516 p
= rtvec_alloc (2);
4518 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4520 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4521 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4529 /* Expand code for the insv template. Return true if successful. */
4532 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4534 int bitsize
= INTVAL (op1
);
4535 int bitpos
= INTVAL (op2
);
4537 /* On z10 we can use the risbg instruction to implement insv. */
4539 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4540 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4545 op
= gen_rtx_SET (GET_MODE(src
),
4546 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4548 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4549 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4554 /* We need byte alignment. */
4555 if (bitsize
% BITS_PER_UNIT
)
4559 && memory_operand (dest
, VOIDmode
)
4560 && (register_operand (src
, word_mode
)
4561 || const_int_operand (src
, VOIDmode
)))
4563 /* Emit standard pattern if possible. */
4564 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4565 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4566 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4568 /* (set (ze (mem)) (const_int)). */
4569 else if (const_int_operand (src
, VOIDmode
))
4571 int size
= bitsize
/ BITS_PER_UNIT
;
4572 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4573 GET_MODE_SIZE (word_mode
) - size
);
4575 dest
= adjust_address (dest
, BLKmode
, 0);
4576 set_mem_size (dest
, GEN_INT (size
));
4577 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4580 /* (set (ze (mem)) (reg)). */
4581 else if (register_operand (src
, word_mode
))
4583 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4584 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4588 /* Emit st,stcmh sequence. */
4589 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4590 int size
= stcmh_width
/ BITS_PER_UNIT
;
4592 emit_move_insn (adjust_address (dest
, SImode
, size
),
4593 gen_lowpart (SImode
, src
));
4594 set_mem_size (dest
, GEN_INT (size
));
4595 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4596 (stcmh_width
), const0_rtx
),
4597 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4598 (GET_MODE_BITSIZE (SImode
))));
4607 /* (set (ze (reg)) (const_int)). */
4609 && register_operand (dest
, word_mode
)
4610 && (bitpos
% 16) == 0
4611 && (bitsize
% 16) == 0
4612 && const_int_operand (src
, VOIDmode
))
4614 HOST_WIDE_INT val
= INTVAL (src
);
4615 int regpos
= bitpos
+ bitsize
;
4617 while (regpos
> bitpos
)
4619 enum machine_mode putmode
;
4622 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4627 putsize
= GET_MODE_BITSIZE (putmode
);
4629 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4632 gen_int_mode (val
, putmode
));
4635 gcc_assert (regpos
== bitpos
);
4642 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4643 register that holds VAL of mode MODE shifted by COUNT bits. */
4646 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4648 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4649 NULL_RTX
, 1, OPTAB_DIRECT
);
4650 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4651 NULL_RTX
, 1, OPTAB_DIRECT
);
4654 /* Structure to hold the initial parameters for a compare_and_swap operation
4655 in HImode and QImode. */
4657 struct alignment_context
4659 rtx memsi
; /* SI aligned memory location. */
4660 rtx shift
; /* Bit offset with regard to lsb. */
4661 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4662 rtx modemaski
; /* ~modemask */
4663 bool aligned
; /* True if memory is aligned, false else. */
4666 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4667 structure AC for transparent simplifying, if the memory alignment is known
4668 to be at least 32bit. MEM is the memory location for the actual operation
4669 and MODE its mode. */
4672 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4673 enum machine_mode mode
)
4675 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4676 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4679 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4682 /* Alignment is unknown. */
4683 rtx byteoffset
, addr
, align
;
4685 /* Force the address into a register. */
4686 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4688 /* Align it to SImode. */
4689 align
= expand_simple_binop (Pmode
, AND
, addr
,
4690 GEN_INT (-GET_MODE_SIZE (SImode
)),
4691 NULL_RTX
, 1, OPTAB_DIRECT
);
4693 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4694 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4695 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4696 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4698 /* Calculate shiftcount. */
4699 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4700 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4701 NULL_RTX
, 1, OPTAB_DIRECT
);
4702 /* As we already have some offset, evaluate the remaining distance. */
4703 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4704 NULL_RTX
, 1, OPTAB_DIRECT
);
4707 /* Shift is the byte count, but we need the bitcount. */
4708 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4709 NULL_RTX
, 1, OPTAB_DIRECT
);
4710 /* Calculate masks. */
4711 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4712 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4713 NULL_RTX
, 1, OPTAB_DIRECT
);
4714 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4717 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4718 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4719 to set if CMP == MEM.
4720 CMP is never in memory for compare_and_swap_cc because
4721 expand_bool_compare_and_swap puts it into a register for later compare. */
4724 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4726 struct alignment_context ac
;
4727 rtx cmpv
, newv
, val
, resv
, cc
;
4728 rtx res
= gen_reg_rtx (SImode
);
4729 rtx csloop
= gen_label_rtx ();
4730 rtx csend
= gen_label_rtx ();
4732 gcc_assert (register_operand (target
, VOIDmode
));
4733 gcc_assert (MEM_P (mem
));
4735 init_alignment_context (&ac
, mem
, mode
);
4737 /* Shift the values to the correct bit positions. */
4738 if (!(ac
.aligned
&& MEM_P (cmp
)))
4739 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4740 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4741 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4743 /* Load full word. Subsequent loads are performed by CS. */
4744 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4745 NULL_RTX
, 1, OPTAB_DIRECT
);
4747 /* Start CS loop. */
4748 emit_label (csloop
);
4749 /* val = "<mem>00..0<mem>"
4750 * cmp = "00..0<cmp>00..0"
4751 * new = "00..0<new>00..0"
4754 /* Patch cmp and new with val at correct position. */
4755 if (ac
.aligned
&& MEM_P (cmp
))
4757 cmpv
= force_reg (SImode
, val
);
4758 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4761 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4762 NULL_RTX
, 1, OPTAB_DIRECT
));
4763 if (ac
.aligned
&& MEM_P (new_rtx
))
4765 newv
= force_reg (SImode
, val
);
4766 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new_rtx
);
4769 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4770 NULL_RTX
, 1, OPTAB_DIRECT
));
4772 /* Jump to end if we're done (likely?). */
4773 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4776 /* Check for changes outside mode. */
4777 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4778 NULL_RTX
, 1, OPTAB_DIRECT
);
4779 cc
= s390_emit_compare (NE
, resv
, val
);
4780 emit_move_insn (val
, resv
);
4781 /* Loop internal if so. */
4782 s390_emit_jump (csloop
, cc
);
4786 /* Return the correct part of the bitfield. */
4787 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4788 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4791 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4792 and VAL the value to play with. If AFTER is true then store the value
4793 MEM holds after the operation, if AFTER is false then store the value MEM
4794 holds before the operation. If TARGET is zero then discard that value, else
4795 store it to TARGET. */
4798 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4799 rtx target
, rtx mem
, rtx val
, bool after
)
4801 struct alignment_context ac
;
4803 rtx new_rtx
= gen_reg_rtx (SImode
);
4804 rtx orig
= gen_reg_rtx (SImode
);
4805 rtx csloop
= gen_label_rtx ();
4807 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4808 gcc_assert (MEM_P (mem
));
4810 init_alignment_context (&ac
, mem
, mode
);
4812 /* Shift val to the correct bit positions.
4813 Preserve "icm", but prevent "ex icm". */
4814 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4815 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4817 /* Further preparation insns. */
4818 if (code
== PLUS
|| code
== MINUS
)
4819 emit_move_insn (orig
, val
);
4820 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4821 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4822 NULL_RTX
, 1, OPTAB_DIRECT
);
4824 /* Load full word. Subsequent loads are performed by CS. */
4825 cmp
= force_reg (SImode
, ac
.memsi
);
4827 /* Start CS loop. */
4828 emit_label (csloop
);
4829 emit_move_insn (new_rtx
, cmp
);
4831 /* Patch new with val at correct position. */
4836 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4837 NULL_RTX
, 1, OPTAB_DIRECT
);
4838 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4839 NULL_RTX
, 1, OPTAB_DIRECT
);
4842 if (ac
.aligned
&& MEM_P (val
))
4843 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4846 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4847 NULL_RTX
, 1, OPTAB_DIRECT
);
4848 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4849 NULL_RTX
, 1, OPTAB_DIRECT
);
4855 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4856 NULL_RTX
, 1, OPTAB_DIRECT
);
4858 case MULT
: /* NAND */
4859 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4860 NULL_RTX
, 1, OPTAB_DIRECT
);
4861 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4862 NULL_RTX
, 1, OPTAB_DIRECT
);
4868 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4869 ac
.memsi
, cmp
, new_rtx
));
4871 /* Return the correct part of the bitfield. */
4873 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4874 after
? new_rtx
: cmp
, ac
.shift
,
4875 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4878 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4879 We need to emit DTP-relative relocations. */
4881 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4884 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4889 fputs ("\t.long\t", file
);
4892 fputs ("\t.quad\t", file
);
4897 output_addr_const (file
, x
);
4898 fputs ("@DTPOFF", file
);
4901 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4902 /* Implement TARGET_MANGLE_TYPE. */
4905 s390_mangle_type (const_tree type
)
4907 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4908 && TARGET_LONG_DOUBLE_128
)
4911 /* For all other types, use normal C++ mangling. */
4916 /* In the name of slightly smaller debug output, and to cater to
4917 general assembler lossage, recognize various UNSPEC sequences
4918 and turn them back into a direct symbol reference. */
4921 s390_delegitimize_address (rtx orig_x
)
4925 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4927 if (GET_CODE (x
) != MEM
)
4931 if (GET_CODE (x
) == PLUS
4932 && GET_CODE (XEXP (x
, 1)) == CONST
4933 && GET_CODE (XEXP (x
, 0)) == REG
4934 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4936 y
= XEXP (XEXP (x
, 1), 0);
4937 if (GET_CODE (y
) == UNSPEC
4938 && XINT (y
, 1) == UNSPEC_GOT
)
4939 return XVECEXP (y
, 0, 0);
4943 if (GET_CODE (x
) == CONST
)
4946 if (GET_CODE (y
) == UNSPEC
4947 && XINT (y
, 1) == UNSPEC_GOTENT
)
4948 return XVECEXP (y
, 0, 0);
4955 /* Output operand OP to stdio stream FILE.
4956 OP is an address (register + offset) which is not used to address data;
4957 instead the rightmost bits are interpreted as the value. */
4960 print_shift_count_operand (FILE *file
, rtx op
)
4962 HOST_WIDE_INT offset
;
4965 /* Extract base register and offset. */
4966 if (!s390_decompose_shift_count (op
, &base
, &offset
))
4972 gcc_assert (GET_CODE (base
) == REG
);
4973 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
4974 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
4977 /* Offsets are constricted to twelve bits. */
4978 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
4980 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
4983 /* See 'get_some_local_dynamic_name'. */
4986 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4990 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4992 x
= get_pool_constant (x
);
4993 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
4996 if (GET_CODE (x
) == SYMBOL_REF
4997 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4999 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5006 /* Locate some local-dynamic symbol still in use by this function
5007 so that we can print its name in local-dynamic base patterns. */
5010 get_some_local_dynamic_name (void)
5014 if (cfun
->machine
->some_ld_name
)
5015 return cfun
->machine
->some_ld_name
;
5017 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5019 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5020 return cfun
->machine
->some_ld_name
;
5025 /* Output machine-dependent UNSPECs occurring in address constant X
5026 in assembler syntax to stdio stream FILE. Returns true if the
5027 constant X could be recognized, false otherwise. */
5030 s390_output_addr_const_extra (FILE *file
, rtx x
)
5032 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5033 switch (XINT (x
, 1))
5036 output_addr_const (file
, XVECEXP (x
, 0, 0));
5037 fprintf (file
, "@GOTENT");
5040 output_addr_const (file
, XVECEXP (x
, 0, 0));
5041 fprintf (file
, "@GOT");
5044 output_addr_const (file
, XVECEXP (x
, 0, 0));
5045 fprintf (file
, "@GOTOFF");
5048 output_addr_const (file
, XVECEXP (x
, 0, 0));
5049 fprintf (file
, "@PLT");
5052 output_addr_const (file
, XVECEXP (x
, 0, 0));
5053 fprintf (file
, "@PLTOFF");
5056 output_addr_const (file
, XVECEXP (x
, 0, 0));
5057 fprintf (file
, "@TLSGD");
5060 assemble_name (file
, get_some_local_dynamic_name ());
5061 fprintf (file
, "@TLSLDM");
5064 output_addr_const (file
, XVECEXP (x
, 0, 0));
5065 fprintf (file
, "@DTPOFF");
5068 output_addr_const (file
, XVECEXP (x
, 0, 0));
5069 fprintf (file
, "@NTPOFF");
5071 case UNSPEC_GOTNTPOFF
:
5072 output_addr_const (file
, XVECEXP (x
, 0, 0));
5073 fprintf (file
, "@GOTNTPOFF");
5075 case UNSPEC_INDNTPOFF
:
5076 output_addr_const (file
, XVECEXP (x
, 0, 0));
5077 fprintf (file
, "@INDNTPOFF");
5081 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5082 switch (XINT (x
, 1))
5084 case UNSPEC_POOL_OFFSET
:
5085 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5086 output_addr_const (file
, x
);
5092 /* Output address operand ADDR in assembler syntax to
5093 stdio stream FILE. */
5096 print_operand_address (FILE *file
, rtx addr
)
5098 struct s390_address ad
;
5100 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5102 gcc_assert (TARGET_Z10
);
5103 output_addr_const (file
, addr
);
5107 if (!s390_decompose_address (addr
, &ad
)
5108 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5109 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5110 output_operand_lossage ("cannot decompose address");
5113 output_addr_const (file
, ad
.disp
);
5115 fprintf (file
, "0");
5117 if (ad
.base
&& ad
.indx
)
5118 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5119 reg_names
[REGNO (ad
.base
)]);
5121 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5124 /* Output operand X in assembler syntax to stdio stream FILE.
5125 CODE specified the format flag. The following format flags
5128 'C': print opcode suffix for branch condition.
5129 'D': print opcode suffix for inverse branch condition.
5130 'E': print opcode suffix for branch on index instruction.
5131 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5132 'G': print the size of the operand in bytes.
5133 'O': print only the displacement of a memory reference.
5134 'R': print only the base register of a memory reference.
5135 'S': print S-type memory reference (base+displacement).
5136 'N': print the second word of a DImode operand.
5137 'M': print the second word of a TImode operand.
5138 'Y': print shift count operand.
5140 'b': print integer X as if it's an unsigned byte.
5141 'c': print integer X as if it's an signed byte.
5142 'x': print integer X as if it's an unsigned halfword.
5143 'h': print integer X as if it's a signed halfword.
5144 'i': print the first nonzero HImode part of X.
5145 'j': print the first HImode part unequal to -1 of X.
5146 'k': print the first nonzero SImode part of X.
5147 'm': print the first SImode part unequal to -1 of X.
5148 'o': print integer X as if it's an unsigned 32bit word. */
5151 print_operand (FILE *file
, rtx x
, int code
)
5156 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5160 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5164 if (GET_CODE (x
) == LE
)
5165 fprintf (file
, "l");
5166 else if (GET_CODE (x
) == GT
)
5167 fprintf (file
, "h");
5173 if (GET_CODE (x
) == SYMBOL_REF
)
5175 fprintf (file
, "%s", ":tls_load:");
5176 output_addr_const (file
, x
);
5178 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5180 fprintf (file
, "%s", ":tls_gdcall:");
5181 output_addr_const (file
, XVECEXP (x
, 0, 0));
5183 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5185 fprintf (file
, "%s", ":tls_ldcall:");
5186 assemble_name (file
, get_some_local_dynamic_name ());
5193 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5198 struct s390_address ad
;
5201 gcc_assert (GET_CODE (x
) == MEM
);
5202 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5204 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5205 gcc_assert (!ad
.indx
);
5208 output_addr_const (file
, ad
.disp
);
5210 fprintf (file
, "0");
5216 struct s390_address ad
;
5219 gcc_assert (GET_CODE (x
) == MEM
);
5220 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5222 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5223 gcc_assert (!ad
.indx
);
5226 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5228 fprintf (file
, "0");
5234 struct s390_address ad
;
5237 gcc_assert (GET_CODE (x
) == MEM
);
5238 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5240 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5241 gcc_assert (!ad
.indx
);
5244 output_addr_const (file
, ad
.disp
);
5246 fprintf (file
, "0");
5249 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5254 if (GET_CODE (x
) == REG
)
5255 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5256 else if (GET_CODE (x
) == MEM
)
5257 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5263 if (GET_CODE (x
) == REG
)
5264 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5265 else if (GET_CODE (x
) == MEM
)
5266 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5272 print_shift_count_operand (file
, x
);
5276 switch (GET_CODE (x
))
5279 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5283 output_address (XEXP (x
, 0));
5290 output_addr_const (file
, x
);
5295 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5296 else if (code
== 'c')
5297 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5298 else if (code
== 'x')
5299 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5300 else if (code
== 'h')
5301 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5302 else if (code
== 'i')
5303 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5304 s390_extract_part (x
, HImode
, 0));
5305 else if (code
== 'j')
5306 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5307 s390_extract_part (x
, HImode
, -1));
5308 else if (code
== 'k')
5309 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5310 s390_extract_part (x
, SImode
, 0));
5311 else if (code
== 'm')
5312 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5313 s390_extract_part (x
, SImode
, -1));
5314 else if (code
== 'o')
5315 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5317 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5321 gcc_assert (GET_MODE (x
) == VOIDmode
);
5323 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5324 else if (code
== 'x')
5325 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5326 else if (code
== 'h')
5327 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5333 fatal_insn ("UNKNOWN in print_operand !?", x
);
5338 /* Target hook for assembling integer objects. We need to define it
5339 here to work a round a bug in some versions of GAS, which couldn't
5340 handle values smaller than INT_MIN when printed in decimal. */
5343 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5345 if (size
== 8 && aligned_p
5346 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5348 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5352 return default_assemble_integer (x
, size
, aligned_p
);
5355 /* Returns true if register REGNO is used for forming
5356 a memory address in expression X. */
5359 reg_used_in_mem_p (int regno
, rtx x
)
5361 enum rtx_code code
= GET_CODE (x
);
5367 if (refers_to_regno_p (regno
, regno
+1,
5371 else if (code
== SET
5372 && GET_CODE (SET_DEST (x
)) == PC
)
5374 if (refers_to_regno_p (regno
, regno
+1,
5379 fmt
= GET_RTX_FORMAT (code
);
5380 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5383 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5386 else if (fmt
[i
] == 'E')
5387 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5388 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5394 /* Returns true if expression DEP_RTX sets an address register
5395 used by instruction INSN to address memory. */
5398 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5402 if (GET_CODE (dep_rtx
) == INSN
)
5403 dep_rtx
= PATTERN (dep_rtx
);
5405 if (GET_CODE (dep_rtx
) == SET
)
5407 target
= SET_DEST (dep_rtx
);
5408 if (GET_CODE (target
) == STRICT_LOW_PART
)
5409 target
= XEXP (target
, 0);
5410 while (GET_CODE (target
) == SUBREG
)
5411 target
= SUBREG_REG (target
);
5413 if (GET_CODE (target
) == REG
)
5415 int regno
= REGNO (target
);
5417 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5419 pat
= PATTERN (insn
);
5420 if (GET_CODE (pat
) == PARALLEL
)
5422 gcc_assert (XVECLEN (pat
, 0) == 2);
5423 pat
= XVECEXP (pat
, 0, 0);
5425 gcc_assert (GET_CODE (pat
) == SET
);
5426 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5428 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5429 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5435 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5438 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5440 rtx dep_rtx
= PATTERN (dep_insn
);
5443 if (GET_CODE (dep_rtx
) == SET
5444 && addr_generation_dependency_p (dep_rtx
, insn
))
5446 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5448 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5450 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5458 /* A C statement (sans semicolon) to update the integer scheduling priority
5459 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5460 reduce the priority to execute INSN later. Do not define this macro if
5461 you do not need to adjust the scheduling priorities of insns.
5463 A STD instruction should be scheduled earlier,
5464 in order to use the bypass. */
5466 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5468 if (! INSN_P (insn
))
5471 if (s390_tune
!= PROCESSOR_2084_Z990
5472 && s390_tune
!= PROCESSOR_2094_Z9_109
5473 && s390_tune
!= PROCESSOR_2097_Z10
5474 && s390_tune
!= PROCESSOR_2817_Z196
)
5477 switch (s390_safe_attr_type (insn
))
5481 priority
= priority
<< 3;
5485 priority
= priority
<< 1;
5494 /* The number of instructions that can be issued per cycle. */
5497 s390_issue_rate (void)
5501 case PROCESSOR_2084_Z990
:
5502 case PROCESSOR_2094_Z9_109
:
5503 case PROCESSOR_2817_Z196
:
5505 case PROCESSOR_2097_Z10
:
5513 s390_first_cycle_multipass_dfa_lookahead (void)
5518 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5519 Fix up MEMs as required. */
5522 annotate_constant_pool_refs (rtx
*x
)
5527 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5528 || !CONSTANT_POOL_ADDRESS_P (*x
));
5530 /* Literal pool references can only occur inside a MEM ... */
5531 if (GET_CODE (*x
) == MEM
)
5533 rtx memref
= XEXP (*x
, 0);
5535 if (GET_CODE (memref
) == SYMBOL_REF
5536 && CONSTANT_POOL_ADDRESS_P (memref
))
5538 rtx base
= cfun
->machine
->base_reg
;
5539 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5542 *x
= replace_equiv_address (*x
, addr
);
5546 if (GET_CODE (memref
) == CONST
5547 && GET_CODE (XEXP (memref
, 0)) == PLUS
5548 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5549 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5550 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5552 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5553 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5554 rtx base
= cfun
->machine
->base_reg
;
5555 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5558 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5563 /* ... or a load-address type pattern. */
5564 if (GET_CODE (*x
) == SET
)
5566 rtx addrref
= SET_SRC (*x
);
5568 if (GET_CODE (addrref
) == SYMBOL_REF
5569 && CONSTANT_POOL_ADDRESS_P (addrref
))
5571 rtx base
= cfun
->machine
->base_reg
;
5572 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5575 SET_SRC (*x
) = addr
;
5579 if (GET_CODE (addrref
) == CONST
5580 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5581 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5582 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5583 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5585 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5586 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5587 rtx base
= cfun
->machine
->base_reg
;
5588 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5591 SET_SRC (*x
) = plus_constant (addr
, off
);
5596 /* Annotate LTREL_BASE as well. */
5597 if (GET_CODE (*x
) == UNSPEC
5598 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5600 rtx base
= cfun
->machine
->base_reg
;
5601 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5606 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5607 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5611 annotate_constant_pool_refs (&XEXP (*x
, i
));
5613 else if (fmt
[i
] == 'E')
5615 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5616 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5621 /* Split all branches that exceed the maximum distance.
5622 Returns true if this created a new literal pool entry. */
5625 s390_split_branches (void)
5627 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5628 int new_literal
= 0, ret
;
5629 rtx insn
, pat
, tmp
, target
;
5632 /* We need correct insn addresses. */
5634 shorten_branches (get_insns ());
5636 /* Find all branches that exceed 64KB, and split them. */
5638 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5640 if (GET_CODE (insn
) != JUMP_INSN
)
5643 pat
= PATTERN (insn
);
5644 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5645 pat
= XVECEXP (pat
, 0, 0);
5646 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5649 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5651 label
= &SET_SRC (pat
);
5653 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5655 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5656 label
= &XEXP (SET_SRC (pat
), 1);
5657 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5658 label
= &XEXP (SET_SRC (pat
), 2);
5665 if (get_attr_length (insn
) <= 4)
5668 /* We are going to use the return register as scratch register,
5669 make sure it will be saved/restored by the prologue/epilogue. */
5670 cfun_frame_layout
.save_return_addr_p
= 1;
5675 tmp
= force_const_mem (Pmode
, *label
);
5676 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5677 INSN_ADDRESSES_NEW (tmp
, -1);
5678 annotate_constant_pool_refs (&PATTERN (tmp
));
5685 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5686 UNSPEC_LTREL_OFFSET
);
5687 target
= gen_rtx_CONST (Pmode
, target
);
5688 target
= force_const_mem (Pmode
, target
);
5689 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5690 INSN_ADDRESSES_NEW (tmp
, -1);
5691 annotate_constant_pool_refs (&PATTERN (tmp
));
5693 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5694 cfun
->machine
->base_reg
),
5696 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5699 ret
= validate_change (insn
, label
, target
, 0);
5707 /* Find an annotated literal pool symbol referenced in RTX X,
5708 and store it at REF. Will abort if X contains references to
5709 more than one such pool symbol; multiple references to the same
5710 symbol are allowed, however.
5712 The rtx pointed to by REF must be initialized to NULL_RTX
5713 by the caller before calling this routine. */
5716 find_constant_pool_ref (rtx x
, rtx
*ref
)
5721 /* Ignore LTREL_BASE references. */
5722 if (GET_CODE (x
) == UNSPEC
5723 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5725 /* Likewise POOL_ENTRY insns. */
5726 if (GET_CODE (x
) == UNSPEC_VOLATILE
5727 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5730 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5731 || !CONSTANT_POOL_ADDRESS_P (x
));
5733 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5735 rtx sym
= XVECEXP (x
, 0, 0);
5736 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5737 && CONSTANT_POOL_ADDRESS_P (sym
));
5739 if (*ref
== NULL_RTX
)
5742 gcc_assert (*ref
== sym
);
5747 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5748 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5752 find_constant_pool_ref (XEXP (x
, i
), ref
);
5754 else if (fmt
[i
] == 'E')
5756 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5757 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5762 /* Replace every reference to the annotated literal pool
5763 symbol REF in X by its base plus OFFSET. */
5766 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5771 gcc_assert (*x
!= ref
);
5773 if (GET_CODE (*x
) == UNSPEC
5774 && XINT (*x
, 1) == UNSPEC_LTREF
5775 && XVECEXP (*x
, 0, 0) == ref
)
5777 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5781 if (GET_CODE (*x
) == PLUS
5782 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5783 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5784 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5785 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5787 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5788 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5792 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5793 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5797 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5799 else if (fmt
[i
] == 'E')
5801 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5802 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5807 /* Check whether X contains an UNSPEC_LTREL_BASE.
5808 Return its constant pool symbol if found, NULL_RTX otherwise. */
5811 find_ltrel_base (rtx x
)
5816 if (GET_CODE (x
) == UNSPEC
5817 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5818 return XVECEXP (x
, 0, 0);
5820 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5821 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5825 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5829 else if (fmt
[i
] == 'E')
5831 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5833 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5843 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5846 replace_ltrel_base (rtx
*x
)
5851 if (GET_CODE (*x
) == UNSPEC
5852 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5854 *x
= XVECEXP (*x
, 0, 1);
5858 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5859 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5863 replace_ltrel_base (&XEXP (*x
, i
));
5865 else if (fmt
[i
] == 'E')
5867 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5868 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5874 /* We keep a list of constants which we have to add to internal
5875 constant tables in the middle of large functions. */
5877 #define NR_C_MODES 11
5878 enum machine_mode constant_modes
[NR_C_MODES
] =
5880 TFmode
, TImode
, TDmode
,
5881 DFmode
, DImode
, DDmode
,
5882 SFmode
, SImode
, SDmode
,
5889 struct constant
*next
;
5894 struct constant_pool
5896 struct constant_pool
*next
;
5900 rtx emit_pool_after
;
5902 struct constant
*constants
[NR_C_MODES
];
5903 struct constant
*execute
;
5908 /* Allocate new constant_pool structure. */
5910 static struct constant_pool
*
5911 s390_alloc_pool (void)
5913 struct constant_pool
*pool
;
5916 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
5918 for (i
= 0; i
< NR_C_MODES
; i
++)
5919 pool
->constants
[i
] = NULL
;
5921 pool
->execute
= NULL
;
5922 pool
->label
= gen_label_rtx ();
5923 pool
->first_insn
= NULL_RTX
;
5924 pool
->pool_insn
= NULL_RTX
;
5925 pool
->insns
= BITMAP_ALLOC (NULL
);
5927 pool
->emit_pool_after
= NULL_RTX
;
5932 /* Create new constant pool covering instructions starting at INSN
5933 and chain it to the end of POOL_LIST. */
5935 static struct constant_pool
*
5936 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
5938 struct constant_pool
*pool
, **prev
;
5940 pool
= s390_alloc_pool ();
5941 pool
->first_insn
= insn
;
5943 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
5950 /* End range of instructions covered by POOL at INSN and emit
5951 placeholder insn representing the pool. */
5954 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
5956 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
5959 insn
= get_last_insn ();
5961 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
5962 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5965 /* Add INSN to the list of insns covered by POOL. */
5968 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
5970 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
5973 /* Return pool out of POOL_LIST that covers INSN. */
5975 static struct constant_pool
*
5976 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
5978 struct constant_pool
*pool
;
5980 for (pool
= pool_list
; pool
; pool
= pool
->next
)
5981 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
5987 /* Add constant VAL of mode MODE to the constant pool POOL. */
5990 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
5995 for (i
= 0; i
< NR_C_MODES
; i
++)
5996 if (constant_modes
[i
] == mode
)
5998 gcc_assert (i
!= NR_C_MODES
);
6000 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6001 if (rtx_equal_p (val
, c
->value
))
6006 c
= (struct constant
*) xmalloc (sizeof *c
);
6008 c
->label
= gen_label_rtx ();
6009 c
->next
= pool
->constants
[i
];
6010 pool
->constants
[i
] = c
;
6011 pool
->size
+= GET_MODE_SIZE (mode
);
6015 /* Return an rtx that represents the offset of X from the start of
6019 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6023 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6024 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6025 UNSPEC_POOL_OFFSET
);
6026 return gen_rtx_CONST (GET_MODE (x
), x
);
6029 /* Find constant VAL of mode MODE in the constant pool POOL.
6030 Return an RTX describing the distance from the start of
6031 the pool to the location of the new constant. */
6034 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6035 enum machine_mode mode
)
6040 for (i
= 0; i
< NR_C_MODES
; i
++)
6041 if (constant_modes
[i
] == mode
)
6043 gcc_assert (i
!= NR_C_MODES
);
6045 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6046 if (rtx_equal_p (val
, c
->value
))
6051 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6054 /* Check whether INSN is an execute. Return the label_ref to its
6055 execute target template if so, NULL_RTX otherwise. */
6058 s390_execute_label (rtx insn
)
6060 if (GET_CODE (insn
) == INSN
6061 && GET_CODE (PATTERN (insn
)) == PARALLEL
6062 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6063 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6064 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6069 /* Add execute target for INSN to the constant pool POOL. */
6072 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6076 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6077 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6082 c
= (struct constant
*) xmalloc (sizeof *c
);
6084 c
->label
= gen_label_rtx ();
6085 c
->next
= pool
->execute
;
6091 /* Find execute target for INSN in the constant pool POOL.
6092 Return an RTX describing the distance from the start of
6093 the pool to the location of the execute target. */
6096 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6100 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6101 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6106 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6109 /* For an execute INSN, extract the execute target template. */
6112 s390_execute_target (rtx insn
)
6114 rtx pattern
= PATTERN (insn
);
6115 gcc_assert (s390_execute_label (insn
));
6117 if (XVECLEN (pattern
, 0) == 2)
6119 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6123 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6126 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6127 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6129 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6135 /* Indicate that INSN cannot be duplicated. This is the case for
6136 execute insns that carry a unique label. */
6139 s390_cannot_copy_insn_p (rtx insn
)
6141 rtx label
= s390_execute_label (insn
);
6142 return label
&& label
!= const0_rtx
;
6145 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6146 do not emit the pool base label. */
6149 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6152 rtx insn
= pool
->pool_insn
;
6155 /* Switch to rodata section. */
6156 if (TARGET_CPU_ZARCH
)
6158 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6159 INSN_ADDRESSES_NEW (insn
, -1);
6162 /* Ensure minimum pool alignment. */
6163 if (TARGET_CPU_ZARCH
)
6164 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6166 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6167 INSN_ADDRESSES_NEW (insn
, -1);
6169 /* Emit pool base label. */
6172 insn
= emit_label_after (pool
->label
, insn
);
6173 INSN_ADDRESSES_NEW (insn
, -1);
6176 /* Dump constants in descending alignment requirement order,
6177 ensuring proper alignment for every constant. */
6178 for (i
= 0; i
< NR_C_MODES
; i
++)
6179 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6181 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6182 rtx value
= copy_rtx (c
->value
);
6183 if (GET_CODE (value
) == CONST
6184 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6185 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6186 && XVECLEN (XEXP (value
, 0), 0) == 1)
6187 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6189 insn
= emit_label_after (c
->label
, insn
);
6190 INSN_ADDRESSES_NEW (insn
, -1);
6192 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6193 gen_rtvec (1, value
),
6194 UNSPECV_POOL_ENTRY
);
6195 insn
= emit_insn_after (value
, insn
);
6196 INSN_ADDRESSES_NEW (insn
, -1);
6199 /* Ensure minimum alignment for instructions. */
6200 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6201 INSN_ADDRESSES_NEW (insn
, -1);
6203 /* Output in-pool execute template insns. */
6204 for (c
= pool
->execute
; c
; c
= c
->next
)
6206 insn
= emit_label_after (c
->label
, insn
);
6207 INSN_ADDRESSES_NEW (insn
, -1);
6209 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6210 INSN_ADDRESSES_NEW (insn
, -1);
6213 /* Switch back to previous section. */
6214 if (TARGET_CPU_ZARCH
)
6216 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6217 INSN_ADDRESSES_NEW (insn
, -1);
6220 insn
= emit_barrier_after (insn
);
6221 INSN_ADDRESSES_NEW (insn
, -1);
6223 /* Remove placeholder insn. */
6224 remove_insn (pool
->pool_insn
);
6227 /* Free all memory used by POOL. */
6230 s390_free_pool (struct constant_pool
*pool
)
6232 struct constant
*c
, *next
;
6235 for (i
= 0; i
< NR_C_MODES
; i
++)
6236 for (c
= pool
->constants
[i
]; c
; c
= next
)
6242 for (c
= pool
->execute
; c
; c
= next
)
6248 BITMAP_FREE (pool
->insns
);
6253 /* Collect main literal pool. Return NULL on overflow. */
6255 static struct constant_pool
*
6256 s390_mainpool_start (void)
6258 struct constant_pool
*pool
;
6261 pool
= s390_alloc_pool ();
6263 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6265 if (GET_CODE (insn
) == INSN
6266 && GET_CODE (PATTERN (insn
)) == SET
6267 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6268 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6270 gcc_assert (!pool
->pool_insn
);
6271 pool
->pool_insn
= insn
;
6274 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6276 s390_add_execute (pool
, insn
);
6278 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6280 rtx pool_ref
= NULL_RTX
;
6281 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6284 rtx constant
= get_pool_constant (pool_ref
);
6285 enum machine_mode mode
= get_pool_mode (pool_ref
);
6286 s390_add_constant (pool
, constant
, mode
);
6290 /* If hot/cold partitioning is enabled we have to make sure that
6291 the literal pool is emitted in the same section where the
6292 initialization of the literal pool base pointer takes place.
6293 emit_pool_after is only used in the non-overflow case on non
6294 Z cpus where we can emit the literal pool at the end of the
6295 function body within the text section. */
6297 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6298 && !pool
->emit_pool_after
)
6299 pool
->emit_pool_after
= PREV_INSN (insn
);
6302 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6304 if (pool
->size
>= 4096)
6306 /* We're going to chunkify the pool, so remove the main
6307 pool placeholder insn. */
6308 remove_insn (pool
->pool_insn
);
6310 s390_free_pool (pool
);
6314 /* If the functions ends with the section where the literal pool
6315 should be emitted set the marker to its end. */
6316 if (pool
&& !pool
->emit_pool_after
)
6317 pool
->emit_pool_after
= get_last_insn ();
6322 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6323 Modify the current function to output the pool constants as well as
6324 the pool register setup instruction. */
6327 s390_mainpool_finish (struct constant_pool
*pool
)
6329 rtx base_reg
= cfun
->machine
->base_reg
;
6332 /* If the pool is empty, we're done. */
6333 if (pool
->size
== 0)
6335 /* We don't actually need a base register after all. */
6336 cfun
->machine
->base_reg
= NULL_RTX
;
6338 if (pool
->pool_insn
)
6339 remove_insn (pool
->pool_insn
);
6340 s390_free_pool (pool
);
6344 /* We need correct insn addresses. */
6345 shorten_branches (get_insns ());
6347 /* On zSeries, we use a LARL to load the pool register. The pool is
6348 located in the .rodata section, so we emit it after the function. */
6349 if (TARGET_CPU_ZARCH
)
6351 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6352 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6353 INSN_ADDRESSES_NEW (insn
, -1);
6354 remove_insn (pool
->pool_insn
);
6356 insn
= get_last_insn ();
6357 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6358 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6360 s390_dump_pool (pool
, 0);
6363 /* On S/390, if the total size of the function's code plus literal pool
6364 does not exceed 4096 bytes, we use BASR to set up a function base
6365 pointer, and emit the literal pool at the end of the function. */
6366 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6367 + pool
->size
+ 8 /* alignment slop */ < 4096)
6369 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6370 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6371 INSN_ADDRESSES_NEW (insn
, -1);
6372 remove_insn (pool
->pool_insn
);
6374 insn
= emit_label_after (pool
->label
, insn
);
6375 INSN_ADDRESSES_NEW (insn
, -1);
6377 /* emit_pool_after will be set by s390_mainpool_start to the
6378 last insn of the section where the literal pool should be
6380 insn
= pool
->emit_pool_after
;
6382 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6383 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6385 s390_dump_pool (pool
, 1);
6388 /* Otherwise, we emit an inline literal pool and use BASR to branch
6389 over it, setting up the pool register at the same time. */
6392 rtx pool_end
= gen_label_rtx ();
6394 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6395 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6396 INSN_ADDRESSES_NEW (insn
, -1);
6397 remove_insn (pool
->pool_insn
);
6399 insn
= emit_label_after (pool
->label
, insn
);
6400 INSN_ADDRESSES_NEW (insn
, -1);
6402 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6403 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6405 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6406 INSN_ADDRESSES_NEW (insn
, -1);
6408 s390_dump_pool (pool
, 1);
6412 /* Replace all literal pool references. */
6414 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6417 replace_ltrel_base (&PATTERN (insn
));
6419 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6421 rtx addr
, pool_ref
= NULL_RTX
;
6422 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6425 if (s390_execute_label (insn
))
6426 addr
= s390_find_execute (pool
, insn
);
6428 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6429 get_pool_mode (pool_ref
));
6431 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6432 INSN_CODE (insn
) = -1;
6438 /* Free the pool. */
6439 s390_free_pool (pool
);
6442 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6443 We have decided we cannot use this pool, so revert all changes
6444 to the current function that were done by s390_mainpool_start. */
6446 s390_mainpool_cancel (struct constant_pool
*pool
)
6448 /* We didn't actually change the instruction stream, so simply
6449 free the pool memory. */
6450 s390_free_pool (pool
);
6454 /* Chunkify the literal pool. */
6456 #define S390_POOL_CHUNK_MIN 0xc00
6457 #define S390_POOL_CHUNK_MAX 0xe00
6459 static struct constant_pool
*
6460 s390_chunkify_start (void)
6462 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6465 rtx pending_ltrel
= NULL_RTX
;
6468 rtx (*gen_reload_base
) (rtx
, rtx
) =
6469 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6472 /* We need correct insn addresses. */
6474 shorten_branches (get_insns ());
6476 /* Scan all insns and move literals to pool chunks. */
6478 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6480 bool section_switch_p
= false;
6482 /* Check for pending LTREL_BASE. */
6485 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6488 gcc_assert (ltrel_base
== pending_ltrel
);
6489 pending_ltrel
= NULL_RTX
;
6493 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6496 curr_pool
= s390_start_pool (&pool_list
, insn
);
6498 s390_add_execute (curr_pool
, insn
);
6499 s390_add_pool_insn (curr_pool
, insn
);
6501 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6503 rtx pool_ref
= NULL_RTX
;
6504 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6507 rtx constant
= get_pool_constant (pool_ref
);
6508 enum machine_mode mode
= get_pool_mode (pool_ref
);
6511 curr_pool
= s390_start_pool (&pool_list
, insn
);
6513 s390_add_constant (curr_pool
, constant
, mode
);
6514 s390_add_pool_insn (curr_pool
, insn
);
6516 /* Don't split the pool chunk between a LTREL_OFFSET load
6517 and the corresponding LTREL_BASE. */
6518 if (GET_CODE (constant
) == CONST
6519 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6520 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6522 gcc_assert (!pending_ltrel
);
6523 pending_ltrel
= pool_ref
;
6528 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6531 s390_add_pool_insn (curr_pool
, insn
);
6532 /* An LTREL_BASE must follow within the same basic block. */
6533 gcc_assert (!pending_ltrel
);
6536 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6537 section_switch_p
= true;
6540 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6541 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6544 if (TARGET_CPU_ZARCH
)
6546 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6549 s390_end_pool (curr_pool
, NULL_RTX
);
6554 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6555 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6558 /* We will later have to insert base register reload insns.
6559 Those will have an effect on code size, which we need to
6560 consider here. This calculation makes rather pessimistic
6561 worst-case assumptions. */
6562 if (GET_CODE (insn
) == CODE_LABEL
)
6565 if (chunk_size
< S390_POOL_CHUNK_MIN
6566 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6567 && !section_switch_p
)
6570 /* Pool chunks can only be inserted after BARRIERs ... */
6571 if (GET_CODE (insn
) == BARRIER
)
6573 s390_end_pool (curr_pool
, insn
);
6578 /* ... so if we don't find one in time, create one. */
6579 else if (chunk_size
> S390_POOL_CHUNK_MAX
6580 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6581 || section_switch_p
)
6583 rtx label
, jump
, barrier
;
6585 if (!section_switch_p
)
6587 /* We can insert the barrier only after a 'real' insn. */
6588 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6590 if (get_attr_length (insn
) == 0)
6592 /* Don't separate LTREL_BASE from the corresponding
6593 LTREL_OFFSET load. */
6599 gcc_assert (!pending_ltrel
);
6601 /* The old pool has to end before the section switch
6602 note in order to make it part of the current
6604 insn
= PREV_INSN (insn
);
6607 label
= gen_label_rtx ();
6608 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6609 barrier
= emit_barrier_after (jump
);
6610 insn
= emit_label_after (label
, barrier
);
6611 JUMP_LABEL (jump
) = label
;
6612 LABEL_NUSES (label
) = 1;
6614 INSN_ADDRESSES_NEW (jump
, -1);
6615 INSN_ADDRESSES_NEW (barrier
, -1);
6616 INSN_ADDRESSES_NEW (insn
, -1);
6618 s390_end_pool (curr_pool
, barrier
);
6626 s390_end_pool (curr_pool
, NULL_RTX
);
6627 gcc_assert (!pending_ltrel
);
6629 /* Find all labels that are branched into
6630 from an insn belonging to a different chunk. */
6632 far_labels
= BITMAP_ALLOC (NULL
);
6634 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6636 /* Labels marked with LABEL_PRESERVE_P can be target
6637 of non-local jumps, so we have to mark them.
6638 The same holds for named labels.
6640 Don't do that, however, if it is the label before
6643 if (GET_CODE (insn
) == CODE_LABEL
6644 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6646 rtx vec_insn
= next_real_insn (insn
);
6647 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6648 PATTERN (vec_insn
) : NULL_RTX
;
6650 || !(GET_CODE (vec_pat
) == ADDR_VEC
6651 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6652 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6655 /* If we have a direct jump (conditional or unconditional)
6656 or a casesi jump, check all potential targets. */
6657 else if (GET_CODE (insn
) == JUMP_INSN
)
6659 rtx pat
= PATTERN (insn
);
6660 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6661 pat
= XVECEXP (pat
, 0, 0);
6663 if (GET_CODE (pat
) == SET
)
6665 rtx label
= JUMP_LABEL (insn
);
6668 if (s390_find_pool (pool_list
, label
)
6669 != s390_find_pool (pool_list
, insn
))
6670 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6673 else if (GET_CODE (pat
) == PARALLEL
6674 && XVECLEN (pat
, 0) == 2
6675 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6676 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6677 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6679 /* Find the jump table used by this casesi jump. */
6680 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6681 rtx vec_insn
= next_real_insn (vec_label
);
6682 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6683 PATTERN (vec_insn
) : NULL_RTX
;
6685 && (GET_CODE (vec_pat
) == ADDR_VEC
6686 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6688 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6690 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6692 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6694 if (s390_find_pool (pool_list
, label
)
6695 != s390_find_pool (pool_list
, insn
))
6696 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6703 /* Insert base register reload insns before every pool. */
6705 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6707 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6709 rtx insn
= curr_pool
->first_insn
;
6710 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6713 /* Insert base register reload insns at every far label. */
6715 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6716 if (GET_CODE (insn
) == CODE_LABEL
6717 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6719 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6722 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6724 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6729 BITMAP_FREE (far_labels
);
6732 /* Recompute insn addresses. */
6734 init_insn_lengths ();
6735 shorten_branches (get_insns ());
6740 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6741 After we have decided to use this list, finish implementing
6742 all changes to the current function as required. */
6745 s390_chunkify_finish (struct constant_pool
*pool_list
)
6747 struct constant_pool
*curr_pool
= NULL
;
6751 /* Replace all literal pool references. */
6753 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6756 replace_ltrel_base (&PATTERN (insn
));
6758 curr_pool
= s390_find_pool (pool_list
, insn
);
6762 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6764 rtx addr
, pool_ref
= NULL_RTX
;
6765 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6768 if (s390_execute_label (insn
))
6769 addr
= s390_find_execute (curr_pool
, insn
);
6771 addr
= s390_find_constant (curr_pool
,
6772 get_pool_constant (pool_ref
),
6773 get_pool_mode (pool_ref
));
6775 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6776 INSN_CODE (insn
) = -1;
6781 /* Dump out all literal pools. */
6783 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6784 s390_dump_pool (curr_pool
, 0);
6786 /* Free pool list. */
6790 struct constant_pool
*next
= pool_list
->next
;
6791 s390_free_pool (pool_list
);
6796 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6797 We have decided we cannot use this list, so revert all changes
6798 to the current function that were done by s390_chunkify_start. */
6801 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6803 struct constant_pool
*curr_pool
= NULL
;
6806 /* Remove all pool placeholder insns. */
6808 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6810 /* Did we insert an extra barrier? Remove it. */
6811 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6812 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6813 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6815 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6816 && barrier
&& GET_CODE (barrier
) == BARRIER
6817 && label
&& GET_CODE (label
) == CODE_LABEL
6818 && GET_CODE (PATTERN (jump
)) == SET
6819 && SET_DEST (PATTERN (jump
)) == pc_rtx
6820 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6821 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6824 remove_insn (barrier
);
6825 remove_insn (label
);
6828 remove_insn (curr_pool
->pool_insn
);
6831 /* Remove all base register reload insns. */
6833 for (insn
= get_insns (); insn
; )
6835 rtx next_insn
= NEXT_INSN (insn
);
6837 if (GET_CODE (insn
) == INSN
6838 && GET_CODE (PATTERN (insn
)) == SET
6839 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6840 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6846 /* Free pool list. */
6850 struct constant_pool
*next
= pool_list
->next
;
6851 s390_free_pool (pool_list
);
6856 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6859 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6863 switch (GET_MODE_CLASS (mode
))
6866 case MODE_DECIMAL_FLOAT
:
6867 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6869 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6870 assemble_real (r
, mode
, align
);
6874 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6875 mark_symbol_refs_as_used (exp
);
6884 /* Return an RTL expression representing the value of the return address
6885 for the frame COUNT steps up from the current frame. FRAME is the
6886 frame pointer of that frame. */
6889 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6894 /* Without backchain, we fail for all but the current frame. */
6896 if (!TARGET_BACKCHAIN
&& count
> 0)
6899 /* For the current frame, we need to make sure the initial
6900 value of RETURN_REGNUM is actually saved. */
6904 /* On non-z architectures branch splitting could overwrite r14. */
6905 if (TARGET_CPU_ZARCH
)
6906 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
6909 cfun_frame_layout
.save_return_addr_p
= true;
6910 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
6914 if (TARGET_PACKED_STACK
)
6915 offset
= -2 * UNITS_PER_LONG
;
6917 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
6919 addr
= plus_constant (frame
, offset
);
6920 addr
= memory_address (Pmode
, addr
);
6921 return gen_rtx_MEM (Pmode
, addr
);
6924 /* Return an RTL expression representing the back chain stored in
6925 the current stack frame. */
6928 s390_back_chain_rtx (void)
6932 gcc_assert (TARGET_BACKCHAIN
);
6934 if (TARGET_PACKED_STACK
)
6935 chain
= plus_constant (stack_pointer_rtx
,
6936 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
6938 chain
= stack_pointer_rtx
;
6940 chain
= gen_rtx_MEM (Pmode
, chain
);
6944 /* Find first call clobbered register unused in a function.
6945 This could be used as base register in a leaf function
6946 or for holding the return address before epilogue. */
6949 find_unused_clobbered_reg (void)
6952 for (i
= 0; i
< 6; i
++)
6953 if (!df_regs_ever_live_p (i
))
6959 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6960 clobbered hard regs in SETREG. */
6963 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
6965 int *regs_ever_clobbered
= (int *)data
;
6966 unsigned int i
, regno
;
6967 enum machine_mode mode
= GET_MODE (setreg
);
6969 if (GET_CODE (setreg
) == SUBREG
)
6971 rtx inner
= SUBREG_REG (setreg
);
6972 if (!GENERAL_REG_P (inner
))
6974 regno
= subreg_regno (setreg
);
6976 else if (GENERAL_REG_P (setreg
))
6977 regno
= REGNO (setreg
);
6982 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
6984 regs_ever_clobbered
[i
] = 1;
6987 /* Walks through all basic blocks of the current function looking
6988 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6989 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6990 each of those regs. */
6993 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
6999 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
7001 /* For non-leaf functions we have to consider all call clobbered regs to be
7003 if (!current_function_is_leaf
)
7005 for (i
= 0; i
< 16; i
++)
7006 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7009 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7010 this work is done by liveness analysis (mark_regs_live_at_end).
7011 Special care is needed for functions containing landing pads. Landing pads
7012 may use the eh registers, but the code which sets these registers is not
7013 contained in that function. Hence s390_regs_ever_clobbered is not able to
7014 deal with this automatically. */
7015 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7016 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7017 if (crtl
->calls_eh_return
7018 || (cfun
->machine
->has_landing_pad_p
7019 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7020 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7022 /* For nonlocal gotos all call-saved registers have to be saved.
7023 This flag is also set for the unwinding code in libgcc.
7024 See expand_builtin_unwind_init. For regs_ever_live this is done by
7026 if (cfun
->has_nonlocal_label
)
7027 for (i
= 0; i
< 16; i
++)
7028 if (!call_really_used_regs
[i
])
7029 regs_ever_clobbered
[i
] = 1;
7031 FOR_EACH_BB (cur_bb
)
7033 FOR_BB_INSNS (cur_bb
, cur_insn
)
7035 if (INSN_P (cur_insn
))
7036 note_stores (PATTERN (cur_insn
),
7037 s390_reg_clobbered_rtx
,
7038 regs_ever_clobbered
);
7043 /* Determine the frame area which actually has to be accessed
7044 in the function epilogue. The values are stored at the
7045 given pointers AREA_BOTTOM (address of the lowest used stack
7046 address) and AREA_TOP (address of the first item which does
7047 not belong to the stack frame). */
7050 s390_frame_area (int *area_bottom
, int *area_top
)
7058 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7060 b
= (cfun_frame_layout
.gprs_offset
7061 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7062 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7063 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7066 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7068 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7069 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7070 + cfun_frame_layout
.high_fprs
* 8));
7074 for (i
= 2; i
< 4; i
++)
7075 if (cfun_fpr_bit_p (i
))
7077 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7078 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7085 /* Fill cfun->machine with info about register usage of current function.
7086 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7089 s390_register_info (int clobbered_regs
[])
7093 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7094 cfun_frame_layout
.fpr_bitmap
= 0;
7095 cfun_frame_layout
.high_fprs
= 0;
7097 for (i
= 24; i
< 32; i
++)
7098 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7100 cfun_set_fpr_bit (i
- 16);
7101 cfun_frame_layout
.high_fprs
++;
7104 /* Find first and last gpr to be saved. We trust regs_ever_live
7105 data, except that we don't save and restore global registers.
7107 Also, all registers with special meaning to the compiler need
7108 to be handled extra. */
7110 s390_regs_ever_clobbered (clobbered_regs
);
7112 for (i
= 0; i
< 16; i
++)
7113 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7115 if (frame_pointer_needed
)
7116 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7119 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7120 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7122 clobbered_regs
[BASE_REGNUM
]
7123 |= (cfun
->machine
->base_reg
7124 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7126 clobbered_regs
[RETURN_REGNUM
]
7127 |= (!current_function_is_leaf
7128 || TARGET_TPF_PROFILING
7129 || cfun
->machine
->split_branches_pending_p
7130 || cfun_frame_layout
.save_return_addr_p
7131 || crtl
->calls_eh_return
7134 clobbered_regs
[STACK_POINTER_REGNUM
]
7135 |= (!current_function_is_leaf
7136 || TARGET_TPF_PROFILING
7137 || cfun_save_high_fprs_p
7138 || get_frame_size () > 0
7139 || cfun
->calls_alloca
7142 for (i
= 6; i
< 16; i
++)
7143 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7145 for (j
= 15; j
> i
; j
--)
7146 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7151 /* Nothing to save/restore. */
7152 cfun_frame_layout
.first_save_gpr_slot
= -1;
7153 cfun_frame_layout
.last_save_gpr_slot
= -1;
7154 cfun_frame_layout
.first_save_gpr
= -1;
7155 cfun_frame_layout
.first_restore_gpr
= -1;
7156 cfun_frame_layout
.last_save_gpr
= -1;
7157 cfun_frame_layout
.last_restore_gpr
= -1;
7161 /* Save slots for gprs from i to j. */
7162 cfun_frame_layout
.first_save_gpr_slot
= i
;
7163 cfun_frame_layout
.last_save_gpr_slot
= j
;
7165 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7166 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7168 if (clobbered_regs
[i
])
7171 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7172 if (clobbered_regs
[j
])
7175 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7177 /* Nothing to save/restore. */
7178 cfun_frame_layout
.first_save_gpr
= -1;
7179 cfun_frame_layout
.first_restore_gpr
= -1;
7180 cfun_frame_layout
.last_save_gpr
= -1;
7181 cfun_frame_layout
.last_restore_gpr
= -1;
7185 /* Save / Restore from gpr i to j. */
7186 cfun_frame_layout
.first_save_gpr
= i
;
7187 cfun_frame_layout
.first_restore_gpr
= i
;
7188 cfun_frame_layout
.last_save_gpr
= j
;
7189 cfun_frame_layout
.last_restore_gpr
= j
;
7195 /* Varargs functions need to save gprs 2 to 6. */
7196 if (cfun
->va_list_gpr_size
7197 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7199 int min_gpr
= crtl
->args
.info
.gprs
;
7200 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7201 if (max_gpr
> GP_ARG_NUM_REG
)
7202 max_gpr
= GP_ARG_NUM_REG
;
7204 if (cfun_frame_layout
.first_save_gpr
== -1
7205 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7207 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7208 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7211 if (cfun_frame_layout
.last_save_gpr
== -1
7212 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7214 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7215 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7219 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7220 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7221 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7223 int min_fpr
= crtl
->args
.info
.fprs
;
7224 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7225 if (max_fpr
> FP_ARG_NUM_REG
)
7226 max_fpr
= FP_ARG_NUM_REG
;
7228 /* ??? This is currently required to ensure proper location
7229 of the fpr save slots within the va_list save area. */
7230 if (TARGET_PACKED_STACK
)
7233 for (i
= min_fpr
; i
< max_fpr
; i
++)
7234 cfun_set_fpr_bit (i
);
7239 for (i
= 2; i
< 4; i
++)
7240 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7241 cfun_set_fpr_bit (i
);
7244 /* Fill cfun->machine with info about frame of current function. */
7247 s390_frame_info (void)
7251 cfun_frame_layout
.frame_size
= get_frame_size ();
7252 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7253 fatal_error ("total size of local variables exceeds architecture limit");
7255 if (!TARGET_PACKED_STACK
)
7257 cfun_frame_layout
.backchain_offset
= 0;
7258 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7259 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7260 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7261 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7264 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7266 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7268 cfun_frame_layout
.gprs_offset
7269 = (cfun_frame_layout
.backchain_offset
7270 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7275 cfun_frame_layout
.f4_offset
7276 = (cfun_frame_layout
.gprs_offset
7277 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7279 cfun_frame_layout
.f0_offset
7280 = (cfun_frame_layout
.f4_offset
7281 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7285 /* On 31 bit we have to care about alignment of the
7286 floating point regs to provide fastest access. */
7287 cfun_frame_layout
.f0_offset
7288 = ((cfun_frame_layout
.gprs_offset
7289 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7290 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7292 cfun_frame_layout
.f4_offset
7293 = (cfun_frame_layout
.f0_offset
7294 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7297 else /* no backchain */
7299 cfun_frame_layout
.f4_offset
7300 = (STACK_POINTER_OFFSET
7301 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7303 cfun_frame_layout
.f0_offset
7304 = (cfun_frame_layout
.f4_offset
7305 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7307 cfun_frame_layout
.gprs_offset
7308 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7311 if (current_function_is_leaf
7312 && !TARGET_TPF_PROFILING
7313 && cfun_frame_layout
.frame_size
== 0
7314 && !cfun_save_high_fprs_p
7315 && !cfun
->calls_alloca
7319 if (!TARGET_PACKED_STACK
)
7320 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7321 + crtl
->outgoing_args_size
7322 + cfun_frame_layout
.high_fprs
* 8);
7325 if (TARGET_BACKCHAIN
)
7326 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7328 /* No alignment trouble here because f8-f15 are only saved under
7330 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7331 cfun_frame_layout
.f4_offset
),
7332 cfun_frame_layout
.gprs_offset
)
7333 - cfun_frame_layout
.high_fprs
* 8);
7335 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7337 for (i
= 0; i
< 8; i
++)
7338 if (cfun_fpr_bit_p (i
))
7339 cfun_frame_layout
.frame_size
+= 8;
7341 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7343 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7344 the frame size to sustain 8 byte alignment of stack frames. */
7345 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7346 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7347 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7349 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7353 /* Generate frame layout. Fills in register and frame data for the current
7354 function in cfun->machine. This routine can be called multiple times;
7355 it will re-do the complete frame layout every time. */
7358 s390_init_frame_layout (void)
7360 HOST_WIDE_INT frame_size
;
7362 int clobbered_regs
[16];
7364 /* On S/390 machines, we may need to perform branch splitting, which
7365 will require both base and return address register. We have no
7366 choice but to assume we're going to need them until right at the
7367 end of the machine dependent reorg phase. */
7368 if (!TARGET_CPU_ZARCH
)
7369 cfun
->machine
->split_branches_pending_p
= true;
7373 frame_size
= cfun_frame_layout
.frame_size
;
7375 /* Try to predict whether we'll need the base register. */
7376 base_used
= cfun
->machine
->split_branches_pending_p
7377 || crtl
->uses_const_pool
7378 || (!DISP_IN_RANGE (frame_size
)
7379 && !CONST_OK_FOR_K (frame_size
));
7381 /* Decide which register to use as literal pool base. In small
7382 leaf functions, try to use an unused call-clobbered register
7383 as base register to avoid save/restore overhead. */
7385 cfun
->machine
->base_reg
= NULL_RTX
;
7386 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7387 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7389 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7391 s390_register_info (clobbered_regs
);
7394 while (frame_size
!= cfun_frame_layout
.frame_size
);
7397 /* Update frame layout. Recompute actual register save data based on
7398 current info and update regs_ever_live for the special registers.
7399 May be called multiple times, but may never cause *more* registers
7400 to be saved than s390_init_frame_layout allocated room for. */
7403 s390_update_frame_layout (void)
7405 int clobbered_regs
[16];
7407 s390_register_info (clobbered_regs
);
7409 df_set_regs_ever_live (BASE_REGNUM
,
7410 clobbered_regs
[BASE_REGNUM
] ? true : false);
7411 df_set_regs_ever_live (RETURN_REGNUM
,
7412 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7413 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7414 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7416 if (cfun
->machine
->base_reg
)
7417 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7420 /* Return true if it is legal to put a value with MODE into REGNO. */
7423 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7425 switch (REGNO_REG_CLASS (regno
))
7428 if (REGNO_PAIR_OK (regno
, mode
))
7430 if (mode
== SImode
|| mode
== DImode
)
7433 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7438 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7443 if (REGNO_PAIR_OK (regno
, mode
))
7446 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7451 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7455 if (REGNO_PAIR_OK (regno
, mode
))
7457 if (mode
== SImode
|| mode
== Pmode
)
7468 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7471 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7473 /* Once we've decided upon a register to use as base register, it must
7474 no longer be used for any other purpose. */
7475 if (cfun
->machine
->base_reg
)
7476 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7477 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7483 /* Maximum number of registers to represent a value of mode MODE
7484 in a register of class RCLASS. */
7487 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7492 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7493 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7495 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7497 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7501 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7504 /* Return true if register FROM can be eliminated via register TO. */
7507 s390_can_eliminate (const int from
, const int to
)
7509 /* On zSeries machines, we have not marked the base register as fixed.
7510 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7511 If a function requires the base register, we say here that this
7512 elimination cannot be performed. This will cause reload to free
7513 up the base register (as if it were fixed). On the other hand,
7514 if the current function does *not* require the base register, we
7515 say here the elimination succeeds, which in turn allows reload
7516 to allocate the base register for any other purpose. */
7517 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7519 if (TARGET_CPU_ZARCH
)
7521 s390_init_frame_layout ();
7522 return cfun
->machine
->base_reg
== NULL_RTX
;
7528 /* Everything else must point into the stack frame. */
7529 gcc_assert (to
== STACK_POINTER_REGNUM
7530 || to
== HARD_FRAME_POINTER_REGNUM
);
7532 gcc_assert (from
== FRAME_POINTER_REGNUM
7533 || from
== ARG_POINTER_REGNUM
7534 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7536 /* Make sure we actually saved the return address. */
7537 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7538 if (!crtl
->calls_eh_return
7540 && !cfun_frame_layout
.save_return_addr_p
)
7546 /* Return offset between register FROM and TO initially after prolog. */
7549 s390_initial_elimination_offset (int from
, int to
)
7551 HOST_WIDE_INT offset
;
7554 /* ??? Why are we called for non-eliminable pairs? */
7555 if (!s390_can_eliminate (from
, to
))
7560 case FRAME_POINTER_REGNUM
:
7561 offset
= (get_frame_size()
7562 + STACK_POINTER_OFFSET
7563 + crtl
->outgoing_args_size
);
7566 case ARG_POINTER_REGNUM
:
7567 s390_init_frame_layout ();
7568 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7571 case RETURN_ADDRESS_POINTER_REGNUM
:
7572 s390_init_frame_layout ();
7573 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7574 gcc_assert (index
>= 0);
7575 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7576 offset
+= index
* UNITS_PER_LONG
;
7590 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7591 to register BASE. Return generated insn. */
7594 save_fpr (rtx base
, int offset
, int regnum
)
7597 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7599 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7600 set_mem_alias_set (addr
, get_varargs_alias_set ());
7602 set_mem_alias_set (addr
, get_frame_alias_set ());
7604 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7607 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7608 to register BASE. Return generated insn. */
7611 restore_fpr (rtx base
, int offset
, int regnum
)
7614 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7615 set_mem_alias_set (addr
, get_frame_alias_set ());
7617 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7620 /* Return true if REGNO is a global register, but not one
7621 of the special ones that need to be saved/restored in anyway. */
7624 global_not_special_regno_p (int regno
)
7626 return (global_regs
[regno
]
7627 /* These registers are special and need to be
7628 restored in any case. */
7629 && !(regno
== STACK_POINTER_REGNUM
7630 || regno
== RETURN_REGNUM
7631 || regno
== BASE_REGNUM
7632 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7635 /* Generate insn to save registers FIRST to LAST into
7636 the register save area located at offset OFFSET
7637 relative to register BASE. */
7640 save_gprs (rtx base
, int offset
, int first
, int last
)
7642 rtx addr
, insn
, note
;
7645 addr
= plus_constant (base
, offset
);
7646 addr
= gen_rtx_MEM (Pmode
, addr
);
7648 set_mem_alias_set (addr
, get_frame_alias_set ());
7650 /* Special-case single register. */
7654 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7656 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7658 if (!global_not_special_regno_p (first
))
7659 RTX_FRAME_RELATED_P (insn
) = 1;
7664 insn
= gen_store_multiple (addr
,
7665 gen_rtx_REG (Pmode
, first
),
7666 GEN_INT (last
- first
+ 1));
7668 if (first
<= 6 && cfun
->stdarg
)
7669 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7671 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7674 set_mem_alias_set (mem
, get_varargs_alias_set ());
7677 /* We need to set the FRAME_RELATED flag on all SETs
7678 inside the store-multiple pattern.
7680 However, we must not emit DWARF records for registers 2..5
7681 if they are stored for use by variable arguments ...
7683 ??? Unfortunately, it is not enough to simply not the
7684 FRAME_RELATED flags for those SETs, because the first SET
7685 of the PARALLEL is always treated as if it had the flag
7686 set, even if it does not. Therefore we emit a new pattern
7687 without those registers as REG_FRAME_RELATED_EXPR note. */
7689 if (first
>= 6 && !global_not_special_regno_p (first
))
7691 rtx pat
= PATTERN (insn
);
7693 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7694 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7695 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7697 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7699 RTX_FRAME_RELATED_P (insn
) = 1;
7705 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7706 if (!global_not_special_regno_p (start
))
7712 addr
= plus_constant (base
, offset
+ (start
- first
) * UNITS_PER_LONG
);
7713 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7714 gen_rtx_REG (Pmode
, start
),
7715 GEN_INT (last
- start
+ 1));
7716 note
= PATTERN (note
);
7718 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7720 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7721 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7722 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7724 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7726 RTX_FRAME_RELATED_P (insn
) = 1;
7732 /* Generate insn to restore registers FIRST to LAST from
7733 the register save area located at offset OFFSET
7734 relative to register BASE. */
7737 restore_gprs (rtx base
, int offset
, int first
, int last
)
7741 addr
= plus_constant (base
, offset
);
7742 addr
= gen_rtx_MEM (Pmode
, addr
);
7743 set_mem_alias_set (addr
, get_frame_alias_set ());
7745 /* Special-case single register. */
7749 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7751 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7756 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7758 GEN_INT (last
- first
+ 1));
7762 /* Return insn sequence to load the GOT register. */
7764 static GTY(()) rtx got_symbol
;
7766 s390_load_got (void)
7772 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7773 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7778 if (TARGET_CPU_ZARCH
)
7780 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7786 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7787 UNSPEC_LTREL_OFFSET
);
7788 offset
= gen_rtx_CONST (Pmode
, offset
);
7789 offset
= force_const_mem (Pmode
, offset
);
7791 emit_move_insn (pic_offset_table_rtx
, offset
);
7793 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7795 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7797 emit_move_insn (pic_offset_table_rtx
, offset
);
7800 insns
= get_insns ();
7805 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7806 and the change to the stack pointer. */
7809 s390_emit_stack_tie (void)
7811 rtx mem
= gen_frame_mem (BLKmode
,
7812 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7814 emit_insn (gen_stack_tie (mem
));
7817 /* Expand the prologue into a bunch of separate insns. */
7820 s390_emit_prologue (void)
7828 /* Complete frame layout. */
7830 s390_update_frame_layout ();
7832 /* Annotate all constant pool references to let the scheduler know
7833 they implicitly use the base register. */
7835 push_topmost_sequence ();
7837 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7840 annotate_constant_pool_refs (&PATTERN (insn
));
7841 df_insn_rescan (insn
);
7844 pop_topmost_sequence ();
7846 /* Choose best register to use for temp use within prologue.
7847 See below for why TPF must use the register 1. */
7849 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7850 && !current_function_is_leaf
7851 && !TARGET_TPF_PROFILING
)
7852 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7854 temp_reg
= gen_rtx_REG (Pmode
, 1);
7856 /* Save call saved gprs. */
7857 if (cfun_frame_layout
.first_save_gpr
!= -1)
7859 insn
= save_gprs (stack_pointer_rtx
,
7860 cfun_frame_layout
.gprs_offset
+
7861 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
7862 - cfun_frame_layout
.first_save_gpr_slot
),
7863 cfun_frame_layout
.first_save_gpr
,
7864 cfun_frame_layout
.last_save_gpr
);
7868 /* Dummy insn to mark literal pool slot. */
7870 if (cfun
->machine
->base_reg
)
7871 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7873 offset
= cfun_frame_layout
.f0_offset
;
7875 /* Save f0 and f2. */
7876 for (i
= 0; i
< 2; i
++)
7878 if (cfun_fpr_bit_p (i
))
7880 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7883 else if (!TARGET_PACKED_STACK
)
7887 /* Save f4 and f6. */
7888 offset
= cfun_frame_layout
.f4_offset
;
7889 for (i
= 2; i
< 4; i
++)
7891 if (cfun_fpr_bit_p (i
))
7893 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7896 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7897 therefore are not frame related. */
7898 if (!call_really_used_regs
[i
+ 16])
7899 RTX_FRAME_RELATED_P (insn
) = 1;
7901 else if (!TARGET_PACKED_STACK
)
7905 if (TARGET_PACKED_STACK
7906 && cfun_save_high_fprs_p
7907 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
7909 offset
= (cfun_frame_layout
.f8_offset
7910 + (cfun_frame_layout
.high_fprs
- 1) * 8);
7912 for (i
= 15; i
> 7 && offset
>= 0; i
--)
7913 if (cfun_fpr_bit_p (i
))
7915 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7917 RTX_FRAME_RELATED_P (insn
) = 1;
7920 if (offset
>= cfun_frame_layout
.f8_offset
)
7924 if (!TARGET_PACKED_STACK
)
7925 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
7927 /* Decrement stack pointer. */
7929 if (cfun_frame_layout
.frame_size
> 0)
7931 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7934 if (s390_stack_size
)
7936 HOST_WIDE_INT stack_guard
;
7938 if (s390_stack_guard
)
7939 stack_guard
= s390_stack_guard
;
7942 /* If no value for stack guard is provided the smallest power of 2
7943 larger than the current frame size is chosen. */
7945 while (stack_guard
< cfun_frame_layout
.frame_size
)
7949 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
7951 warning (0, "frame size of function %qs is "
7952 HOST_WIDE_INT_PRINT_DEC
7953 " bytes exceeding user provided stack limit of "
7954 HOST_WIDE_INT_PRINT_DEC
" bytes. "
7955 "An unconditional trap is added.",
7956 current_function_name(), cfun_frame_layout
.frame_size
,
7958 emit_insn (gen_trap ());
7962 /* stack_guard has to be smaller than s390_stack_size.
7963 Otherwise we would emit an AND with zero which would
7964 not match the test under mask pattern. */
7965 if (stack_guard
>= s390_stack_size
)
7967 warning (0, "frame size of function %qs is "
7968 HOST_WIDE_INT_PRINT_DEC
7969 " bytes which is more than half the stack size. "
7970 "The dynamic check would not be reliable. "
7971 "No check emitted for this function.",
7972 current_function_name(),
7973 cfun_frame_layout
.frame_size
);
7977 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
7978 & ~(stack_guard
- 1));
7980 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
7981 GEN_INT (stack_check_mask
));
7983 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
7985 t
, const0_rtx
, const0_rtx
));
7987 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
7989 t
, const0_rtx
, const0_rtx
));
7994 if (s390_warn_framesize
> 0
7995 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
7996 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
7997 current_function_name (), cfun_frame_layout
.frame_size
);
7999 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8000 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8002 /* Save incoming stack pointer into temp reg. */
8003 if (TARGET_BACKCHAIN
|| next_fpr
)
8004 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8006 /* Subtract frame size from stack pointer. */
8008 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8010 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8011 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8013 insn
= emit_insn (insn
);
8017 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8018 frame_off
= force_const_mem (Pmode
, frame_off
);
8020 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8021 annotate_constant_pool_refs (&PATTERN (insn
));
8024 RTX_FRAME_RELATED_P (insn
) = 1;
8025 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8026 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8027 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8028 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8031 /* Set backchain. */
8033 if (TARGET_BACKCHAIN
)
8035 if (cfun_frame_layout
.backchain_offset
)
8036 addr
= gen_rtx_MEM (Pmode
,
8037 plus_constant (stack_pointer_rtx
,
8038 cfun_frame_layout
.backchain_offset
));
8040 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8041 set_mem_alias_set (addr
, get_frame_alias_set ());
8042 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8045 /* If we support non-call exceptions (e.g. for Java),
8046 we need to make sure the backchain pointer is set up
8047 before any possibly trapping memory access. */
8048 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8050 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8051 emit_clobber (addr
);
8055 /* Save fprs 8 - 15 (64 bit ABI). */
8057 if (cfun_save_high_fprs_p
&& next_fpr
)
8059 /* If the stack might be accessed through a different register
8060 we have to make sure that the stack pointer decrement is not
8061 moved below the use of the stack slots. */
8062 s390_emit_stack_tie ();
8064 insn
= emit_insn (gen_add2_insn (temp_reg
,
8065 GEN_INT (cfun_frame_layout
.f8_offset
)));
8069 for (i
= 24; i
<= next_fpr
; i
++)
8070 if (cfun_fpr_bit_p (i
- 16))
8072 rtx addr
= plus_constant (stack_pointer_rtx
,
8073 cfun_frame_layout
.frame_size
8074 + cfun_frame_layout
.f8_offset
8077 insn
= save_fpr (temp_reg
, offset
, i
);
8079 RTX_FRAME_RELATED_P (insn
) = 1;
8080 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8081 gen_rtx_SET (VOIDmode
,
8082 gen_rtx_MEM (DFmode
, addr
),
8083 gen_rtx_REG (DFmode
, i
)));
8087 /* Set frame pointer, if needed. */
8089 if (frame_pointer_needed
)
8091 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8092 RTX_FRAME_RELATED_P (insn
) = 1;
8095 /* Set up got pointer, if needed. */
8097 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8099 rtx insns
= s390_load_got ();
8101 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8102 annotate_constant_pool_refs (&PATTERN (insn
));
8107 if (TARGET_TPF_PROFILING
)
8109 /* Generate a BAS instruction to serve as a function
8110 entry intercept to facilitate the use of tracing
8111 algorithms located at the branch target. */
8112 emit_insn (gen_prologue_tpf ());
8114 /* Emit a blockage here so that all code
8115 lies between the profiling mechanisms. */
8116 emit_insn (gen_blockage ());
8120 /* Expand the epilogue into a bunch of separate insns. */
8123 s390_emit_epilogue (bool sibcall
)
8125 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8126 int area_bottom
, area_top
, offset
= 0;
8131 if (TARGET_TPF_PROFILING
)
8134 /* Generate a BAS instruction to serve as a function
8135 entry intercept to facilitate the use of tracing
8136 algorithms located at the branch target. */
8138 /* Emit a blockage here so that all code
8139 lies between the profiling mechanisms. */
8140 emit_insn (gen_blockage ());
8142 emit_insn (gen_epilogue_tpf ());
8145 /* Check whether to use frame or stack pointer for restore. */
8147 frame_pointer
= (frame_pointer_needed
8148 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8150 s390_frame_area (&area_bottom
, &area_top
);
8152 /* Check whether we can access the register save area.
8153 If not, increment the frame pointer as required. */
8155 if (area_top
<= area_bottom
)
8157 /* Nothing to restore. */
8159 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8160 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8162 /* Area is in range. */
8163 offset
= cfun_frame_layout
.frame_size
;
8167 rtx insn
, frame_off
, cfa
;
8169 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8170 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8172 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8173 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8174 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8176 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8177 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8178 insn
= emit_insn (insn
);
8182 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8183 frame_off
= force_const_mem (Pmode
, frame_off
);
8185 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8186 annotate_constant_pool_refs (&PATTERN (insn
));
8188 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8189 RTX_FRAME_RELATED_P (insn
) = 1;
8192 /* Restore call saved fprs. */
8196 if (cfun_save_high_fprs_p
)
8198 next_offset
= cfun_frame_layout
.f8_offset
;
8199 for (i
= 24; i
< 32; i
++)
8201 if (cfun_fpr_bit_p (i
- 16))
8203 restore_fpr (frame_pointer
,
8204 offset
+ next_offset
, i
);
8206 = alloc_reg_note (REG_CFA_RESTORE
,
8207 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8216 next_offset
= cfun_frame_layout
.f4_offset
;
8217 for (i
= 18; i
< 20; i
++)
8219 if (cfun_fpr_bit_p (i
- 16))
8221 restore_fpr (frame_pointer
,
8222 offset
+ next_offset
, i
);
8224 = alloc_reg_note (REG_CFA_RESTORE
,
8225 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8228 else if (!TARGET_PACKED_STACK
)
8234 /* Return register. */
8236 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8238 /* Restore call saved gprs. */
8240 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8245 /* Check for global register and save them
8246 to stack location from where they get restored. */
8248 for (i
= cfun_frame_layout
.first_restore_gpr
;
8249 i
<= cfun_frame_layout
.last_restore_gpr
;
8252 if (global_not_special_regno_p (i
))
8254 addr
= plus_constant (frame_pointer
,
8255 offset
+ cfun_frame_layout
.gprs_offset
8256 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8258 addr
= gen_rtx_MEM (Pmode
, addr
);
8259 set_mem_alias_set (addr
, get_frame_alias_set ());
8260 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8264 = alloc_reg_note (REG_CFA_RESTORE
,
8265 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8270 /* Fetch return address from stack before load multiple,
8271 this will do good for scheduling. */
8273 if (cfun_frame_layout
.save_return_addr_p
8274 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8275 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8277 int return_regnum
= find_unused_clobbered_reg();
8280 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8282 addr
= plus_constant (frame_pointer
,
8283 offset
+ cfun_frame_layout
.gprs_offset
8285 - cfun_frame_layout
.first_save_gpr_slot
)
8287 addr
= gen_rtx_MEM (Pmode
, addr
);
8288 set_mem_alias_set (addr
, get_frame_alias_set ());
8289 emit_move_insn (return_reg
, addr
);
8293 insn
= restore_gprs (frame_pointer
,
8294 offset
+ cfun_frame_layout
.gprs_offset
8295 + (cfun_frame_layout
.first_restore_gpr
8296 - cfun_frame_layout
.first_save_gpr_slot
)
8298 cfun_frame_layout
.first_restore_gpr
,
8299 cfun_frame_layout
.last_restore_gpr
);
8300 insn
= emit_insn (insn
);
8301 REG_NOTES (insn
) = cfa_restores
;
8302 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8303 plus_constant (stack_pointer_rtx
, STACK_POINTER_OFFSET
));
8304 RTX_FRAME_RELATED_P (insn
) = 1;
8310 /* Return to caller. */
8312 p
= rtvec_alloc (2);
8314 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
8315 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8316 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8321 /* Return the size in bytes of a function argument of
8322 type TYPE and/or mode MODE. At least one of TYPE or
8323 MODE must be specified. */
8326 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8329 return int_size_in_bytes (type
);
8331 /* No type info available for some library calls ... */
8332 if (mode
!= BLKmode
)
8333 return GET_MODE_SIZE (mode
);
8335 /* If we have neither type nor mode, abort */
8339 /* Return true if a function argument of type TYPE and mode MODE
8340 is to be passed in a floating-point register, if available. */
8343 s390_function_arg_float (enum machine_mode mode
, tree type
)
8345 int size
= s390_function_arg_size (mode
, type
);
8349 /* Soft-float changes the ABI: no floating-point registers are used. */
8350 if (TARGET_SOFT_FLOAT
)
8353 /* No type info available for some library calls ... */
8355 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8357 /* The ABI says that record types with a single member are treated
8358 just like that member would be. */
8359 while (TREE_CODE (type
) == RECORD_TYPE
)
8361 tree field
, single
= NULL_TREE
;
8363 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8365 if (TREE_CODE (field
) != FIELD_DECL
)
8368 if (single
== NULL_TREE
)
8369 single
= TREE_TYPE (field
);
8374 if (single
== NULL_TREE
)
8380 return TREE_CODE (type
) == REAL_TYPE
;
8383 /* Return true if a function argument of type TYPE and mode MODE
8384 is to be passed in an integer register, or a pair of integer
8385 registers, if available. */
8388 s390_function_arg_integer (enum machine_mode mode
, tree type
)
8390 int size
= s390_function_arg_size (mode
, type
);
8394 /* No type info available for some library calls ... */
8396 return GET_MODE_CLASS (mode
) == MODE_INT
8397 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8399 /* We accept small integral (and similar) types. */
8400 if (INTEGRAL_TYPE_P (type
)
8401 || POINTER_TYPE_P (type
)
8402 || TREE_CODE (type
) == OFFSET_TYPE
8403 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8406 /* We also accept structs of size 1, 2, 4, 8 that are not
8407 passed in floating-point registers. */
8408 if (AGGREGATE_TYPE_P (type
)
8409 && exact_log2 (size
) >= 0
8410 && !s390_function_arg_float (mode
, type
))
8416 /* Return 1 if a function argument of type TYPE and mode MODE
8417 is to be passed by reference. The ABI specifies that only
8418 structures of size 1, 2, 4, or 8 bytes are passed by value,
8419 all other structures (and complex numbers) are passed by
8423 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
8424 enum machine_mode mode
, const_tree type
,
8425 bool named ATTRIBUTE_UNUSED
)
8427 int size
= s390_function_arg_size (mode
, type
);
8433 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8436 if (TREE_CODE (type
) == COMPLEX_TYPE
8437 || TREE_CODE (type
) == VECTOR_TYPE
)
8444 /* Update the data in CUM to advance over an argument of mode MODE and
8445 data type TYPE. (TYPE is null for libcalls where that information
8446 may not be available.). The boolean NAMED specifies whether the
8447 argument is a named argument (as opposed to an unnamed argument
8448 matching an ellipsis). */
8451 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8452 tree type
, int named ATTRIBUTE_UNUSED
)
8454 if (s390_function_arg_float (mode
, type
))
8458 else if (s390_function_arg_integer (mode
, type
))
8460 int size
= s390_function_arg_size (mode
, type
);
8461 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8467 /* Define where to put the arguments to a function.
8468 Value is zero to push the argument on the stack,
8469 or a hard register in which to store the argument.
8471 MODE is the argument's machine mode.
8472 TYPE is the data type of the argument (as a tree).
8473 This is null for libcalls where that information may
8475 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8476 the preceding args and about the function being called.
8477 NAMED is nonzero if this argument is a named parameter
8478 (otherwise it is an extra parameter matching an ellipsis).
8480 On S/390, we use general purpose registers 2 through 6 to
8481 pass integer, pointer, and certain structure arguments, and
8482 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8483 to pass floating point arguments. All remaining arguments
8484 are pushed to the stack. */
8487 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
8488 int named ATTRIBUTE_UNUSED
)
8490 if (s390_function_arg_float (mode
, type
))
8492 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8495 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8497 else if (s390_function_arg_integer (mode
, type
))
8499 int size
= s390_function_arg_size (mode
, type
);
8500 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8502 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8504 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8505 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8506 else if (n_gprs
== 2)
8508 rtvec p
= rtvec_alloc (2);
8511 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8514 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8517 return gen_rtx_PARALLEL (mode
, p
);
8521 /* After the real arguments, expand_call calls us once again
8522 with a void_type_node type. Whatever we return here is
8523 passed as operand 2 to the call expanders.
8525 We don't need this feature ... */
8526 else if (type
== void_type_node
)
8532 /* Return true if return values of type TYPE should be returned
8533 in a memory buffer whose address is passed by the caller as
8534 hidden first argument. */
8537 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8539 /* We accept small integral (and similar) types. */
8540 if (INTEGRAL_TYPE_P (type
)
8541 || POINTER_TYPE_P (type
)
8542 || TREE_CODE (type
) == OFFSET_TYPE
8543 || TREE_CODE (type
) == REAL_TYPE
)
8544 return int_size_in_bytes (type
) > 8;
8546 /* Aggregates and similar constructs are always returned
8548 if (AGGREGATE_TYPE_P (type
)
8549 || TREE_CODE (type
) == COMPLEX_TYPE
8550 || TREE_CODE (type
) == VECTOR_TYPE
)
8553 /* ??? We get called on all sorts of random stuff from
8554 aggregate_value_p. We can't abort, but it's not clear
8555 what's safe to return. Pretend it's a struct I guess. */
8559 /* Function arguments and return values are promoted to word size. */
8561 static enum machine_mode
8562 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8564 const_tree fntype ATTRIBUTE_UNUSED
,
8565 int for_return ATTRIBUTE_UNUSED
)
8567 if (INTEGRAL_MODE_P (mode
)
8568 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8570 if (POINTER_TYPE_P (type
))
8571 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8578 /* Define where to return a (scalar) value of type TYPE.
8579 If TYPE is null, define where to return a (scalar)
8580 value of mode MODE from a libcall. */
8583 s390_function_value (const_tree type
, const_tree fn
, enum machine_mode mode
)
8587 int unsignedp
= TYPE_UNSIGNED (type
);
8588 mode
= promote_function_mode (type
, TYPE_MODE (type
), &unsignedp
, fn
, 1);
8591 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8592 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8594 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8595 return gen_rtx_REG (mode
, 16);
8596 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8597 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8598 return gen_rtx_REG (mode
, 2);
8599 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8601 rtvec p
= rtvec_alloc (2);
8604 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8606 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8608 return gen_rtx_PARALLEL (mode
, p
);
8615 /* Create and return the va_list datatype.
8617 On S/390, va_list is an array type equivalent to
8619 typedef struct __va_list_tag
8623 void *__overflow_arg_area;
8624 void *__reg_save_area;
8627 where __gpr and __fpr hold the number of general purpose
8628 or floating point arguments used up to now, respectively,
8629 __overflow_arg_area points to the stack location of the
8630 next argument passed on the stack, and __reg_save_area
8631 always points to the start of the register area in the
8632 call frame of the current function. The function prologue
8633 saves all registers used for argument passing into this
8634 area if the function uses variable arguments. */
8637 s390_build_builtin_va_list (void)
8639 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8641 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8644 build_decl (BUILTINS_LOCATION
,
8645 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8647 f_gpr
= build_decl (BUILTINS_LOCATION
,
8648 FIELD_DECL
, get_identifier ("__gpr"),
8649 long_integer_type_node
);
8650 f_fpr
= build_decl (BUILTINS_LOCATION
,
8651 FIELD_DECL
, get_identifier ("__fpr"),
8652 long_integer_type_node
);
8653 f_ovf
= build_decl (BUILTINS_LOCATION
,
8654 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8656 f_sav
= build_decl (BUILTINS_LOCATION
,
8657 FIELD_DECL
, get_identifier ("__reg_save_area"),
8660 va_list_gpr_counter_field
= f_gpr
;
8661 va_list_fpr_counter_field
= f_fpr
;
8663 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8664 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8665 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8666 DECL_FIELD_CONTEXT (f_sav
) = record
;
8668 TREE_CHAIN (record
) = type_decl
;
8669 TYPE_NAME (record
) = type_decl
;
8670 TYPE_FIELDS (record
) = f_gpr
;
8671 DECL_CHAIN (f_gpr
) = f_fpr
;
8672 DECL_CHAIN (f_fpr
) = f_ovf
;
8673 DECL_CHAIN (f_ovf
) = f_sav
;
8675 layout_type (record
);
8677 /* The correct type is an array type of one element. */
8678 return build_array_type (record
, build_index_type (size_zero_node
));
8681 /* Implement va_start by filling the va_list structure VALIST.
8682 STDARG_P is always true, and ignored.
8683 NEXTARG points to the first anonymous stack argument.
8685 The following global variables are used to initialize
8686 the va_list structure:
8689 holds number of gprs and fprs used for named arguments.
8690 crtl->args.arg_offset_rtx:
8691 holds the offset of the first anonymous stack argument
8692 (relative to the virtual arg pointer). */
8695 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8697 HOST_WIDE_INT n_gpr
, n_fpr
;
8699 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8700 tree gpr
, fpr
, ovf
, sav
, t
;
8702 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8703 f_fpr
= DECL_CHAIN (f_gpr
);
8704 f_ovf
= DECL_CHAIN (f_fpr
);
8705 f_sav
= DECL_CHAIN (f_ovf
);
8707 valist
= build_va_arg_indirect_ref (valist
);
8708 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8709 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8710 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8711 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8713 /* Count number of gp and fp argument registers used. */
8715 n_gpr
= crtl
->args
.info
.gprs
;
8716 n_fpr
= crtl
->args
.info
.fprs
;
8718 if (cfun
->va_list_gpr_size
)
8720 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8721 build_int_cst (NULL_TREE
, n_gpr
));
8722 TREE_SIDE_EFFECTS (t
) = 1;
8723 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8726 if (cfun
->va_list_fpr_size
)
8728 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8729 build_int_cst (NULL_TREE
, n_fpr
));
8730 TREE_SIDE_EFFECTS (t
) = 1;
8731 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8734 /* Find the overflow area. */
8735 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8736 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8738 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8740 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8741 off
= off
< 0 ? 0 : off
;
8742 if (TARGET_DEBUG_ARG
)
8743 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8744 (int)n_gpr
, (int)n_fpr
, off
);
8746 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8748 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8749 TREE_SIDE_EFFECTS (t
) = 1;
8750 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8753 /* Find the register save area. */
8754 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8755 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8757 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8758 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
8759 size_int (-RETURN_REGNUM
* UNITS_PER_LONG
));
8761 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8762 TREE_SIDE_EFFECTS (t
) = 1;
8763 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8767 /* Implement va_arg by updating the va_list structure
8768 VALIST as required to retrieve an argument of type
8769 TYPE, and returning that argument.
8771 Generates code equivalent to:
8773 if (integral value) {
8774 if (size <= 4 && args.gpr < 5 ||
8775 size > 4 && args.gpr < 4 )
8776 ret = args.reg_save_area[args.gpr+8]
8778 ret = *args.overflow_arg_area++;
8779 } else if (float value) {
8781 ret = args.reg_save_area[args.fpr+64]
8783 ret = *args.overflow_arg_area++;
8784 } else if (aggregate value) {
8786 ret = *args.reg_save_area[args.gpr]
8788 ret = **args.overflow_arg_area++;
8792 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8793 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8795 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8796 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8797 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8798 tree lab_false
, lab_over
, addr
;
8800 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8801 f_fpr
= DECL_CHAIN (f_gpr
);
8802 f_ovf
= DECL_CHAIN (f_fpr
);
8803 f_sav
= DECL_CHAIN (f_ovf
);
8805 valist
= build_va_arg_indirect_ref (valist
);
8806 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8807 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8808 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8810 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8811 both appear on a lhs. */
8812 valist
= unshare_expr (valist
);
8813 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8815 size
= int_size_in_bytes (type
);
8817 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8819 if (TARGET_DEBUG_ARG
)
8821 fprintf (stderr
, "va_arg: aggregate type");
8825 /* Aggregates are passed by reference. */
8830 /* kernel stack layout on 31 bit: It is assumed here that no padding
8831 will be added by s390_frame_info because for va_args always an even
8832 number of gprs has to be saved r15-r2 = 14 regs. */
8833 sav_ofs
= 2 * UNITS_PER_LONG
;
8834 sav_scale
= UNITS_PER_LONG
;
8835 size
= UNITS_PER_LONG
;
8836 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8838 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8840 if (TARGET_DEBUG_ARG
)
8842 fprintf (stderr
, "va_arg: float type");
8846 /* FP args go in FP registers, if present. */
8850 sav_ofs
= 16 * UNITS_PER_LONG
;
8852 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8856 if (TARGET_DEBUG_ARG
)
8858 fprintf (stderr
, "va_arg: other type");
8862 /* Otherwise into GP registers. */
8865 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8867 /* kernel stack layout on 31 bit: It is assumed here that no padding
8868 will be added by s390_frame_info because for va_args always an even
8869 number of gprs has to be saved r15-r2 = 14 regs. */
8870 sav_ofs
= 2 * UNITS_PER_LONG
;
8872 if (size
< UNITS_PER_LONG
)
8873 sav_ofs
+= UNITS_PER_LONG
- size
;
8875 sav_scale
= UNITS_PER_LONG
;
8876 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8879 /* Pull the value out of the saved registers ... */
8881 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
8882 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
8883 addr
= create_tmp_var (ptr_type_node
, "addr");
8885 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
8886 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
8887 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
8888 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
8889 gimplify_and_add (t
, pre_p
);
8891 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
8892 size_int (sav_ofs
));
8893 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
8894 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
8895 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
8897 gimplify_assign (addr
, t
, pre_p
);
8899 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
8901 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
8904 /* ... Otherwise out of the overflow area. */
8907 if (size
< UNITS_PER_LONG
)
8908 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8909 size_int (UNITS_PER_LONG
- size
));
8911 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
8913 gimplify_assign (addr
, t
, pre_p
);
8915 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8917 gimplify_assign (ovf
, t
, pre_p
);
8919 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
8922 /* Increment register save count. */
8924 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
8925 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
8926 gimplify_and_add (u
, pre_p
);
8930 t
= build_pointer_type_for_mode (build_pointer_type (type
),
8932 addr
= fold_convert (t
, addr
);
8933 addr
= build_va_arg_indirect_ref (addr
);
8937 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
8938 addr
= fold_convert (t
, addr
);
8941 return build_va_arg_indirect_ref (addr
);
8949 S390_BUILTIN_THREAD_POINTER
,
8950 S390_BUILTIN_SET_THREAD_POINTER
,
8955 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
8960 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
8966 s390_init_builtins (void)
8970 ftype
= build_function_type (ptr_type_node
, void_list_node
);
8971 add_builtin_function ("__builtin_thread_pointer", ftype
,
8972 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
8975 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
8976 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
8977 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
8981 /* Expand an expression EXP that calls a built-in function,
8982 with result going to TARGET if that's convenient
8983 (and in mode MODE if that's convenient).
8984 SUBTARGET may be used as the target for computing one of EXP's operands.
8985 IGNORE is nonzero if the value is to be ignored. */
8988 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8989 enum machine_mode mode ATTRIBUTE_UNUSED
,
8990 int ignore ATTRIBUTE_UNUSED
)
8994 enum insn_code
const *code_for_builtin
=
8995 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
8997 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8998 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8999 enum insn_code icode
;
9000 rtx op
[MAX_ARGS
], pat
;
9004 call_expr_arg_iterator iter
;
9006 if (fcode
>= S390_BUILTIN_max
)
9007 internal_error ("bad builtin fcode");
9008 icode
= code_for_builtin
[fcode
];
9010 internal_error ("bad builtin fcode");
9012 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9015 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9017 const struct insn_operand_data
*insn_op
;
9019 if (arg
== error_mark_node
)
9021 if (arity
> MAX_ARGS
)
9024 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
9026 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
9028 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
9029 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
9035 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9037 || GET_MODE (target
) != tmode
9038 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9039 target
= gen_reg_rtx (tmode
);
9045 pat
= GEN_FCN (icode
) (target
);
9049 pat
= GEN_FCN (icode
) (target
, op
[0]);
9051 pat
= GEN_FCN (icode
) (op
[0]);
9054 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9070 /* Output assembly code for the trampoline template to
9073 On S/390, we use gpr 1 internally in the trampoline code;
9074 gpr 0 is used to hold the static chain. */
9077 s390_asm_trampoline_template (FILE *file
)
9080 op
[0] = gen_rtx_REG (Pmode
, 0);
9081 op
[1] = gen_rtx_REG (Pmode
, 1);
9085 output_asm_insn ("basr\t%1,0", op
);
9086 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
9087 output_asm_insn ("br\t%1", op
);
9088 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9092 output_asm_insn ("basr\t%1,0", op
);
9093 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
9094 output_asm_insn ("br\t%1", op
);
9095 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9099 /* Emit RTL insns to initialize the variable parts of a trampoline.
9100 FNADDR is an RTX for the address of the function's pure code.
9101 CXT is an RTX for the static chain value for the function. */
9104 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9106 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9109 emit_block_move (m_tramp
, assemble_trampoline_template (),
9110 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
9112 mem
= adjust_address (m_tramp
, Pmode
, 2*UNITS_PER_WORD
);
9113 emit_move_insn (mem
, cxt
);
9114 mem
= adjust_address (m_tramp
, Pmode
, 3*UNITS_PER_WORD
);
9115 emit_move_insn (mem
, fnaddr
);
9118 /* Output assembler code to FILE to increment profiler label # LABELNO
9119 for profiling a function entry. */
9122 s390_function_profiler (FILE *file
, int labelno
)
9127 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9129 fprintf (file
, "# function profiler \n");
9131 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9132 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9133 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_LONG
));
9135 op
[2] = gen_rtx_REG (Pmode
, 1);
9136 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9137 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9139 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9142 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9143 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9148 output_asm_insn ("stg\t%0,%1", op
);
9149 output_asm_insn ("larl\t%2,%3", op
);
9150 output_asm_insn ("brasl\t%0,%4", op
);
9151 output_asm_insn ("lg\t%0,%1", op
);
9155 op
[6] = gen_label_rtx ();
9157 output_asm_insn ("st\t%0,%1", op
);
9158 output_asm_insn ("bras\t%2,%l6", op
);
9159 output_asm_insn (".long\t%4", op
);
9160 output_asm_insn (".long\t%3", op
);
9161 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9162 output_asm_insn ("l\t%0,0(%2)", op
);
9163 output_asm_insn ("l\t%2,4(%2)", op
);
9164 output_asm_insn ("basr\t%0,%0", op
);
9165 output_asm_insn ("l\t%0,%1", op
);
9169 op
[5] = gen_label_rtx ();
9170 op
[6] = gen_label_rtx ();
9172 output_asm_insn ("st\t%0,%1", op
);
9173 output_asm_insn ("bras\t%2,%l6", op
);
9174 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9175 output_asm_insn (".long\t%4-%l5", op
);
9176 output_asm_insn (".long\t%3-%l5", op
);
9177 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9178 output_asm_insn ("lr\t%0,%2", op
);
9179 output_asm_insn ("a\t%0,0(%2)", op
);
9180 output_asm_insn ("a\t%2,4(%2)", op
);
9181 output_asm_insn ("basr\t%0,%0", op
);
9182 output_asm_insn ("l\t%0,%1", op
);
9186 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9187 into its SYMBOL_REF_FLAGS. */
9190 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9192 default_encode_section_info (decl
, rtl
, first
);
9194 if (TREE_CODE (decl
) == VAR_DECL
)
9196 /* If a variable has a forced alignment to < 2 bytes, mark it
9197 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9199 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9200 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9201 if (!DECL_SIZE (decl
)
9202 || !DECL_ALIGN (decl
)
9203 || !host_integerp (DECL_SIZE (decl
), 0)
9204 || (DECL_ALIGN (decl
) <= 64
9205 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9206 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9209 /* Literal pool references don't have a decl so they are handled
9210 differently here. We rely on the information in the MEM_ALIGN
9211 entry to decide upon natural alignment. */
9213 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9214 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9215 && (MEM_ALIGN (rtl
) == 0
9216 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9217 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9218 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9221 /* Output thunk to FILE that implements a C++ virtual function call (with
9222 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9223 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9224 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9225 relative to the resulting this pointer. */
9228 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9229 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9235 /* Make sure unwind info is emitted for the thunk if needed. */
9236 final_start_function (emit_barrier (), file
, 1);
9238 /* Operand 0 is the target function. */
9239 op
[0] = XEXP (DECL_RTL (function
), 0);
9240 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9243 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9244 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9245 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9248 /* Operand 1 is the 'this' pointer. */
9249 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9250 op
[1] = gen_rtx_REG (Pmode
, 3);
9252 op
[1] = gen_rtx_REG (Pmode
, 2);
9254 /* Operand 2 is the delta. */
9255 op
[2] = GEN_INT (delta
);
9257 /* Operand 3 is the vcall_offset. */
9258 op
[3] = GEN_INT (vcall_offset
);
9260 /* Operand 4 is the temporary register. */
9261 op
[4] = gen_rtx_REG (Pmode
, 1);
9263 /* Operands 5 to 8 can be used as labels. */
9269 /* Operand 9 can be used for temporary register. */
9272 /* Generate code. */
9275 /* Setup literal pool pointer if required. */
9276 if ((!DISP_IN_RANGE (delta
)
9277 && !CONST_OK_FOR_K (delta
)
9278 && !CONST_OK_FOR_Os (delta
))
9279 || (!DISP_IN_RANGE (vcall_offset
)
9280 && !CONST_OK_FOR_K (vcall_offset
)
9281 && !CONST_OK_FOR_Os (vcall_offset
)))
9283 op
[5] = gen_label_rtx ();
9284 output_asm_insn ("larl\t%4,%5", op
);
9287 /* Add DELTA to this pointer. */
9290 if (CONST_OK_FOR_J (delta
))
9291 output_asm_insn ("la\t%1,%2(%1)", op
);
9292 else if (DISP_IN_RANGE (delta
))
9293 output_asm_insn ("lay\t%1,%2(%1)", op
);
9294 else if (CONST_OK_FOR_K (delta
))
9295 output_asm_insn ("aghi\t%1,%2", op
);
9296 else if (CONST_OK_FOR_Os (delta
))
9297 output_asm_insn ("agfi\t%1,%2", op
);
9300 op
[6] = gen_label_rtx ();
9301 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9305 /* Perform vcall adjustment. */
9308 if (DISP_IN_RANGE (vcall_offset
))
9310 output_asm_insn ("lg\t%4,0(%1)", op
);
9311 output_asm_insn ("ag\t%1,%3(%4)", op
);
9313 else if (CONST_OK_FOR_K (vcall_offset
))
9315 output_asm_insn ("lghi\t%4,%3", op
);
9316 output_asm_insn ("ag\t%4,0(%1)", op
);
9317 output_asm_insn ("ag\t%1,0(%4)", op
);
9319 else if (CONST_OK_FOR_Os (vcall_offset
))
9321 output_asm_insn ("lgfi\t%4,%3", op
);
9322 output_asm_insn ("ag\t%4,0(%1)", op
);
9323 output_asm_insn ("ag\t%1,0(%4)", op
);
9327 op
[7] = gen_label_rtx ();
9328 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9329 output_asm_insn ("ag\t%4,0(%1)", op
);
9330 output_asm_insn ("ag\t%1,0(%4)", op
);
9334 /* Jump to target. */
9335 output_asm_insn ("jg\t%0", op
);
9337 /* Output literal pool if required. */
9340 output_asm_insn (".align\t4", op
);
9341 targetm
.asm_out
.internal_label (file
, "L",
9342 CODE_LABEL_NUMBER (op
[5]));
9346 targetm
.asm_out
.internal_label (file
, "L",
9347 CODE_LABEL_NUMBER (op
[6]));
9348 output_asm_insn (".long\t%2", op
);
9352 targetm
.asm_out
.internal_label (file
, "L",
9353 CODE_LABEL_NUMBER (op
[7]));
9354 output_asm_insn (".long\t%3", op
);
9359 /* Setup base pointer if required. */
9361 || (!DISP_IN_RANGE (delta
)
9362 && !CONST_OK_FOR_K (delta
)
9363 && !CONST_OK_FOR_Os (delta
))
9364 || (!DISP_IN_RANGE (delta
)
9365 && !CONST_OK_FOR_K (vcall_offset
)
9366 && !CONST_OK_FOR_Os (vcall_offset
)))
9368 op
[5] = gen_label_rtx ();
9369 output_asm_insn ("basr\t%4,0", op
);
9370 targetm
.asm_out
.internal_label (file
, "L",
9371 CODE_LABEL_NUMBER (op
[5]));
9374 /* Add DELTA to this pointer. */
9377 if (CONST_OK_FOR_J (delta
))
9378 output_asm_insn ("la\t%1,%2(%1)", op
);
9379 else if (DISP_IN_RANGE (delta
))
9380 output_asm_insn ("lay\t%1,%2(%1)", op
);
9381 else if (CONST_OK_FOR_K (delta
))
9382 output_asm_insn ("ahi\t%1,%2", op
);
9383 else if (CONST_OK_FOR_Os (delta
))
9384 output_asm_insn ("afi\t%1,%2", op
);
9387 op
[6] = gen_label_rtx ();
9388 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9392 /* Perform vcall adjustment. */
9395 if (CONST_OK_FOR_J (vcall_offset
))
9397 output_asm_insn ("l\t%4,0(%1)", op
);
9398 output_asm_insn ("a\t%1,%3(%4)", op
);
9400 else if (DISP_IN_RANGE (vcall_offset
))
9402 output_asm_insn ("l\t%4,0(%1)", op
);
9403 output_asm_insn ("ay\t%1,%3(%4)", op
);
9405 else if (CONST_OK_FOR_K (vcall_offset
))
9407 output_asm_insn ("lhi\t%4,%3", op
);
9408 output_asm_insn ("a\t%4,0(%1)", op
);
9409 output_asm_insn ("a\t%1,0(%4)", op
);
9411 else if (CONST_OK_FOR_Os (vcall_offset
))
9413 output_asm_insn ("iilf\t%4,%3", op
);
9414 output_asm_insn ("a\t%4,0(%1)", op
);
9415 output_asm_insn ("a\t%1,0(%4)", op
);
9419 op
[7] = gen_label_rtx ();
9420 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9421 output_asm_insn ("a\t%4,0(%1)", op
);
9422 output_asm_insn ("a\t%1,0(%4)", op
);
9425 /* We had to clobber the base pointer register.
9426 Re-setup the base pointer (with a different base). */
9427 op
[5] = gen_label_rtx ();
9428 output_asm_insn ("basr\t%4,0", op
);
9429 targetm
.asm_out
.internal_label (file
, "L",
9430 CODE_LABEL_NUMBER (op
[5]));
9433 /* Jump to target. */
9434 op
[8] = gen_label_rtx ();
9437 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9439 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9440 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9441 else if (flag_pic
== 1)
9443 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9444 output_asm_insn ("l\t%4,%0(%4)", op
);
9446 else if (flag_pic
== 2)
9448 op
[9] = gen_rtx_REG (Pmode
, 0);
9449 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9450 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9451 output_asm_insn ("ar\t%4,%9", op
);
9452 output_asm_insn ("l\t%4,0(%4)", op
);
9455 output_asm_insn ("br\t%4", op
);
9457 /* Output literal pool. */
9458 output_asm_insn (".align\t4", op
);
9460 if (nonlocal
&& flag_pic
== 2)
9461 output_asm_insn (".long\t%0", op
);
9464 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9465 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9468 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9470 output_asm_insn (".long\t%0", op
);
9472 output_asm_insn (".long\t%0-%5", op
);
9476 targetm
.asm_out
.internal_label (file
, "L",
9477 CODE_LABEL_NUMBER (op
[6]));
9478 output_asm_insn (".long\t%2", op
);
9482 targetm
.asm_out
.internal_label (file
, "L",
9483 CODE_LABEL_NUMBER (op
[7]));
9484 output_asm_insn (".long\t%3", op
);
9487 final_end_function ();
9491 s390_valid_pointer_mode (enum machine_mode mode
)
9493 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9496 /* Checks whether the given CALL_EXPR would use a caller
9497 saved register. This is used to decide whether sibling call
9498 optimization could be performed on the respective function
9502 s390_call_saved_register_used (tree call_expr
)
9504 CUMULATIVE_ARGS cum
;
9506 enum machine_mode mode
;
9511 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
9513 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9515 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9516 gcc_assert (parameter
);
9518 /* For an undeclared variable passed as parameter we will get
9519 an ERROR_MARK node here. */
9520 if (TREE_CODE (parameter
) == ERROR_MARK
)
9523 type
= TREE_TYPE (parameter
);
9526 mode
= TYPE_MODE (type
);
9529 if (pass_by_reference (&cum
, mode
, type
, true))
9532 type
= build_pointer_type (type
);
9535 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
9537 s390_function_arg_advance (&cum
, mode
, type
, 0);
9542 if (REG_P (parm_rtx
))
9545 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9547 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9551 if (GET_CODE (parm_rtx
) == PARALLEL
)
9555 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9557 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9559 gcc_assert (REG_P (r
));
9562 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9564 if (!call_used_regs
[reg
+ REGNO (r
)])
9573 /* Return true if the given call expression can be
9574 turned into a sibling call.
9575 DECL holds the declaration of the function to be called whereas
9576 EXP is the call expression itself. */
9579 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9581 /* The TPF epilogue uses register 1. */
9582 if (TARGET_TPF_PROFILING
)
9585 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9586 which would have to be restored before the sibcall. */
9587 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9590 /* Register 6 on s390 is available as an argument register but unfortunately
9591 "caller saved". This makes functions needing this register for arguments
9592 not suitable for sibcalls. */
9593 return !s390_call_saved_register_used (exp
);
9596 /* Return the fixed registers used for condition codes. */
9599 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9602 *p2
= INVALID_REGNUM
;
9607 /* This function is used by the call expanders of the machine description.
9608 It emits the call insn itself together with the necessary operations
9609 to adjust the target address and returns the emitted insn.
9610 ADDR_LOCATION is the target address rtx
9611 TLS_CALL the location of the thread-local symbol
9612 RESULT_REG the register where the result of the call should be stored
9613 RETADDR_REG the register where the return address should be stored
9614 If this parameter is NULL_RTX the call is considered
9615 to be a sibling call. */
9618 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9621 bool plt_call
= false;
9627 /* Direct function calls need special treatment. */
9628 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9630 /* When calling a global routine in PIC mode, we must
9631 replace the symbol itself with the PLT stub. */
9632 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9634 if (retaddr_reg
!= NULL_RTX
)
9636 addr_location
= gen_rtx_UNSPEC (Pmode
,
9637 gen_rtvec (1, addr_location
),
9639 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9643 /* For -fpic code the PLT entries might use r12 which is
9644 call-saved. Therefore we cannot do a sibcall when
9645 calling directly using a symbol ref. When reaching
9646 this point we decided (in s390_function_ok_for_sibcall)
9647 to do a sibcall for a function pointer but one of the
9648 optimizers was able to get rid of the function pointer
9649 by propagating the symbol ref into the call. This
9650 optimization is illegal for S/390 so we turn the direct
9651 call into a indirect call again. */
9652 addr_location
= force_reg (Pmode
, addr_location
);
9655 /* Unless we can use the bras(l) insn, force the
9656 routine address into a register. */
9657 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9660 addr_location
= legitimize_pic_address (addr_location
, 0);
9662 addr_location
= force_reg (Pmode
, addr_location
);
9666 /* If it is already an indirect call or the code above moved the
9667 SYMBOL_REF to somewhere else make sure the address can be found in
9669 if (retaddr_reg
== NULL_RTX
9670 && GET_CODE (addr_location
) != SYMBOL_REF
9673 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9674 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9677 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9678 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9680 if (result_reg
!= NULL_RTX
)
9681 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9683 if (retaddr_reg
!= NULL_RTX
)
9685 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9687 if (tls_call
!= NULL_RTX
)
9688 vec
= gen_rtvec (3, call
, clobber
,
9689 gen_rtx_USE (VOIDmode
, tls_call
));
9691 vec
= gen_rtvec (2, call
, clobber
);
9693 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9696 insn
= emit_call_insn (call
);
9698 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9699 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9701 /* s390_function_ok_for_sibcall should
9702 have denied sibcalls in this case. */
9703 gcc_assert (retaddr_reg
!= NULL_RTX
);
9705 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9710 /* Implement CONDITIONAL_REGISTER_USAGE. */
9713 s390_conditional_register_usage (void)
9719 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9720 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9722 if (TARGET_CPU_ZARCH
)
9724 fixed_regs
[BASE_REGNUM
] = 0;
9725 call_used_regs
[BASE_REGNUM
] = 0;
9726 fixed_regs
[RETURN_REGNUM
] = 0;
9727 call_used_regs
[RETURN_REGNUM
] = 0;
9731 for (i
= 24; i
< 32; i
++)
9732 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9736 for (i
= 18; i
< 20; i
++)
9737 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9740 if (TARGET_SOFT_FLOAT
)
9742 for (i
= 16; i
< 32; i
++)
9743 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9747 /* Corresponding function to eh_return expander. */
9749 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9751 s390_emit_tpf_eh_return (rtx target
)
9755 if (!s390_tpf_eh_return_symbol
)
9756 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9758 reg
= gen_rtx_REG (Pmode
, 2);
9760 emit_move_insn (reg
, target
);
9761 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9762 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9763 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9765 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9768 /* Rework the prologue/epilogue to avoid saving/restoring
9769 registers unnecessarily. */
9772 s390_optimize_prologue (void)
9774 rtx insn
, new_insn
, next_insn
;
9776 /* Do a final recompute of the frame-related data. */
9778 s390_update_frame_layout ();
9780 /* If all special registers are in fact used, there's nothing we
9781 can do, so no point in walking the insn list. */
9783 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9784 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9785 && (TARGET_CPU_ZARCH
9786 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9787 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9790 /* Search for prologue/epilogue insns and replace them. */
9792 for (insn
= get_insns (); insn
; insn
= next_insn
)
9794 int first
, last
, off
;
9795 rtx set
, base
, offset
;
9797 next_insn
= NEXT_INSN (insn
);
9799 if (GET_CODE (insn
) != INSN
)
9802 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9803 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9805 set
= XVECEXP (PATTERN (insn
), 0, 0);
9806 first
= REGNO (SET_SRC (set
));
9807 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9808 offset
= const0_rtx
;
9809 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9810 off
= INTVAL (offset
);
9812 if (GET_CODE (base
) != REG
|| off
< 0)
9814 if (cfun_frame_layout
.first_save_gpr
!= -1
9815 && (cfun_frame_layout
.first_save_gpr
< first
9816 || cfun_frame_layout
.last_save_gpr
> last
))
9818 if (REGNO (base
) != STACK_POINTER_REGNUM
9819 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9821 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9824 if (cfun_frame_layout
.first_save_gpr
!= -1)
9826 new_insn
= save_gprs (base
,
9827 off
+ (cfun_frame_layout
.first_save_gpr
9828 - first
) * UNITS_PER_LONG
,
9829 cfun_frame_layout
.first_save_gpr
,
9830 cfun_frame_layout
.last_save_gpr
);
9831 new_insn
= emit_insn_before (new_insn
, insn
);
9832 INSN_ADDRESSES_NEW (new_insn
, -1);
9839 if (cfun_frame_layout
.first_save_gpr
== -1
9840 && GET_CODE (PATTERN (insn
)) == SET
9841 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9842 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9843 || (!TARGET_CPU_ZARCH
9844 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9845 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9847 set
= PATTERN (insn
);
9848 first
= REGNO (SET_SRC (set
));
9849 offset
= const0_rtx
;
9850 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9851 off
= INTVAL (offset
);
9853 if (GET_CODE (base
) != REG
|| off
< 0)
9855 if (REGNO (base
) != STACK_POINTER_REGNUM
9856 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9863 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9864 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9866 set
= XVECEXP (PATTERN (insn
), 0, 0);
9867 first
= REGNO (SET_DEST (set
));
9868 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9869 offset
= const0_rtx
;
9870 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9871 off
= INTVAL (offset
);
9873 if (GET_CODE (base
) != REG
|| off
< 0)
9875 if (cfun_frame_layout
.first_restore_gpr
!= -1
9876 && (cfun_frame_layout
.first_restore_gpr
< first
9877 || cfun_frame_layout
.last_restore_gpr
> last
))
9879 if (REGNO (base
) != STACK_POINTER_REGNUM
9880 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9882 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9885 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9887 new_insn
= restore_gprs (base
,
9888 off
+ (cfun_frame_layout
.first_restore_gpr
9889 - first
) * UNITS_PER_LONG
,
9890 cfun_frame_layout
.first_restore_gpr
,
9891 cfun_frame_layout
.last_restore_gpr
);
9892 new_insn
= emit_insn_before (new_insn
, insn
);
9893 INSN_ADDRESSES_NEW (new_insn
, -1);
9900 if (cfun_frame_layout
.first_restore_gpr
== -1
9901 && GET_CODE (PATTERN (insn
)) == SET
9902 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
9903 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
9904 || (!TARGET_CPU_ZARCH
9905 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
9906 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
9908 set
= PATTERN (insn
);
9909 first
= REGNO (SET_DEST (set
));
9910 offset
= const0_rtx
;
9911 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9912 off
= INTVAL (offset
);
9914 if (GET_CODE (base
) != REG
|| off
< 0)
9916 if (REGNO (base
) != STACK_POINTER_REGNUM
9917 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9926 /* On z10 and later the dynamic branch prediction must see the
9927 backward jump within a certain windows. If not it falls back to
9928 the static prediction. This function rearranges the loop backward
9929 branch in a way which makes the static prediction always correct.
9930 The function returns true if it added an instruction. */
9932 s390_fix_long_loop_prediction (rtx insn
)
9934 rtx set
= single_set (insn
);
9935 rtx code_label
, label_ref
, new_label
;
9941 /* This will exclude branch on count and branch on index patterns
9942 since these are correctly statically predicted. */
9944 || SET_DEST (set
) != pc_rtx
9945 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
9948 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
9949 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
9951 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
9953 code_label
= XEXP (label_ref
, 0);
9955 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
9956 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
9957 || (INSN_ADDRESSES (INSN_UID (insn
))
9958 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
9961 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
9962 distance
< PREDICT_DISTANCE
- 6;
9963 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
9964 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
9967 new_label
= gen_label_rtx ();
9968 uncond_jump
= emit_jump_insn_after (
9969 gen_rtx_SET (VOIDmode
, pc_rtx
,
9970 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
9972 emit_label_after (new_label
, uncond_jump
);
9974 tmp
= XEXP (SET_SRC (set
), 1);
9975 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
9976 XEXP (SET_SRC (set
), 2) = tmp
;
9977 INSN_CODE (insn
) = -1;
9979 XEXP (label_ref
, 0) = new_label
;
9980 JUMP_LABEL (insn
) = new_label
;
9981 JUMP_LABEL (uncond_jump
) = code_label
;
9986 /* Returns 1 if INSN reads the value of REG for purposes not related
9987 to addressing of memory, and 0 otherwise. */
9989 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
9991 return reg_referenced_p (reg
, PATTERN (insn
))
9992 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
9995 /* Starting from INSN find_cond_jump looks downwards in the insn
9996 stream for a single jump insn which is the last user of the
9997 condition code set in INSN. */
9999 find_cond_jump (rtx insn
)
10001 for (; insn
; insn
= NEXT_INSN (insn
))
10005 if (LABEL_P (insn
))
10008 if (!JUMP_P (insn
))
10010 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10015 /* This will be triggered by a return. */
10016 if (GET_CODE (PATTERN (insn
)) != SET
)
10019 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10020 ite
= SET_SRC (PATTERN (insn
));
10022 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10025 cc
= XEXP (XEXP (ite
, 0), 0);
10026 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10029 if (find_reg_note (insn
, REG_DEAD
, cc
))
10037 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10038 the semantics does not change. If NULL_RTX is passed as COND the
10039 function tries to find the conditional jump starting with INSN. */
10041 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10045 if (cond
== NULL_RTX
)
10047 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10048 jump
= jump
? single_set (jump
) : NULL_RTX
;
10050 if (jump
== NULL_RTX
)
10053 cond
= XEXP (XEXP (jump
, 1), 0);
10058 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10061 /* On z10, instructions of the compare-and-branch family have the
10062 property to access the register occurring as second operand with
10063 its bits complemented. If such a compare is grouped with a second
10064 instruction that accesses the same register non-complemented, and
10065 if that register's value is delivered via a bypass, then the
10066 pipeline recycles, thereby causing significant performance decline.
10067 This function locates such situations and exchanges the two
10068 operands of the compare. The function return true whenever it
10071 s390_z10_optimize_cmp (rtx insn
)
10073 rtx prev_insn
, next_insn
;
10074 bool insn_added_p
= false;
10075 rtx cond
, *op0
, *op1
;
10077 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10079 /* Handle compare and branch and branch on count
10081 rtx pattern
= single_set (insn
);
10084 || SET_DEST (pattern
) != pc_rtx
10085 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10088 cond
= XEXP (SET_SRC (pattern
), 0);
10089 op0
= &XEXP (cond
, 0);
10090 op1
= &XEXP (cond
, 1);
10092 else if (GET_CODE (PATTERN (insn
)) == SET
)
10096 /* Handle normal compare instructions. */
10097 src
= SET_SRC (PATTERN (insn
));
10098 dest
= SET_DEST (PATTERN (insn
));
10101 || !CC_REGNO_P (REGNO (dest
))
10102 || GET_CODE (src
) != COMPARE
)
10105 /* s390_swap_cmp will try to find the conditional
10106 jump when passing NULL_RTX as condition. */
10108 op0
= &XEXP (src
, 0);
10109 op1
= &XEXP (src
, 1);
10114 if (!REG_P (*op0
) || !REG_P (*op1
))
10117 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10120 /* Swap the COMPARE arguments and its mask if there is a
10121 conflicting access in the previous insn. */
10122 prev_insn
= prev_active_insn (insn
);
10123 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10124 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10125 s390_swap_cmp (cond
, op0
, op1
, insn
);
10127 /* Check if there is a conflict with the next insn. If there
10128 was no conflict with the previous insn, then swap the
10129 COMPARE arguments and its mask. If we already swapped
10130 the operands, or if swapping them would cause a conflict
10131 with the previous insn, issue a NOP after the COMPARE in
10132 order to separate the two instuctions. */
10133 next_insn
= next_active_insn (insn
);
10134 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10135 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10137 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10138 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10140 if (REGNO (*op1
) == 0)
10141 emit_insn_after (gen_nop1 (), insn
);
10143 emit_insn_after (gen_nop (), insn
);
10144 insn_added_p
= true;
10147 s390_swap_cmp (cond
, op0
, op1
, insn
);
10149 return insn_added_p
;
10152 /* Perform machine-dependent processing. */
10157 bool pool_overflow
= false;
10159 /* Make sure all splits have been performed; splits after
10160 machine_dependent_reorg might confuse insn length counts. */
10161 split_all_insns_noflow ();
10163 /* Install the main literal pool and the associated base
10164 register load insns.
10166 In addition, there are two problematic situations we need
10169 - the literal pool might be > 4096 bytes in size, so that
10170 some of its elements cannot be directly accessed
10172 - a branch target might be > 64K away from the branch, so that
10173 it is not possible to use a PC-relative instruction.
10175 To fix those, we split the single literal pool into multiple
10176 pool chunks, reloading the pool base register at various
10177 points throughout the function to ensure it always points to
10178 the pool chunk the following code expects, and / or replace
10179 PC-relative branches by absolute branches.
10181 However, the two problems are interdependent: splitting the
10182 literal pool can move a branch further away from its target,
10183 causing the 64K limit to overflow, and on the other hand,
10184 replacing a PC-relative branch by an absolute branch means
10185 we need to put the branch target address into the literal
10186 pool, possibly causing it to overflow.
10188 So, we loop trying to fix up both problems until we manage
10189 to satisfy both conditions at the same time. Note that the
10190 loop is guaranteed to terminate as every pass of the loop
10191 strictly decreases the total number of PC-relative branches
10192 in the function. (This is not completely true as there
10193 might be branch-over-pool insns introduced by chunkify_start.
10194 Those never need to be split however.) */
10198 struct constant_pool
*pool
= NULL
;
10200 /* Collect the literal pool. */
10201 if (!pool_overflow
)
10203 pool
= s390_mainpool_start ();
10205 pool_overflow
= true;
10208 /* If literal pool overflowed, start to chunkify it. */
10210 pool
= s390_chunkify_start ();
10212 /* Split out-of-range branches. If this has created new
10213 literal pool entries, cancel current chunk list and
10214 recompute it. zSeries machines have large branch
10215 instructions, so we never need to split a branch. */
10216 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10219 s390_chunkify_cancel (pool
);
10221 s390_mainpool_cancel (pool
);
10226 /* If we made it up to here, both conditions are satisfied.
10227 Finish up literal pool related changes. */
10229 s390_chunkify_finish (pool
);
10231 s390_mainpool_finish (pool
);
10233 /* We're done splitting branches. */
10234 cfun
->machine
->split_branches_pending_p
= false;
10238 /* Generate out-of-pool execute target insns. */
10239 if (TARGET_CPU_ZARCH
)
10241 rtx insn
, label
, target
;
10243 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10245 label
= s390_execute_label (insn
);
10249 gcc_assert (label
!= const0_rtx
);
10251 target
= emit_label (XEXP (label
, 0));
10252 INSN_ADDRESSES_NEW (target
, -1);
10254 target
= emit_insn (s390_execute_target (insn
));
10255 INSN_ADDRESSES_NEW (target
, -1);
10259 /* Try to optimize prologue and epilogue further. */
10260 s390_optimize_prologue ();
10262 /* Walk over the insns and do some >=z10 specific changes. */
10263 if (s390_tune
== PROCESSOR_2097_Z10
10264 || s390_tune
== PROCESSOR_2817_Z196
)
10267 bool insn_added_p
= false;
10269 /* The insn lengths and addresses have to be up to date for the
10270 following manipulations. */
10271 shorten_branches (get_insns ());
10273 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10275 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10279 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10281 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10282 || GET_CODE (PATTERN (insn
)) == SET
)
10283 && s390_tune
== PROCESSOR_2097_Z10
)
10284 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10287 /* Adjust branches if we added new instructions. */
10289 shorten_branches (get_insns ());
10293 /* Return true if INSN is a fp load insn writing register REGNO. */
10295 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10298 enum attr_type flag
= s390_safe_attr_type (insn
);
10300 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10303 set
= single_set (insn
);
10305 if (set
== NULL_RTX
)
10308 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10311 if (REGNO (SET_DEST (set
)) != regno
)
10317 /* This value describes the distance to be avoided between an
10318 aritmetic fp instruction and an fp load writing the same register.
10319 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10320 fine but the exact value has to be avoided. Otherwise the FP
10321 pipeline will throw an exception causing a major penalty. */
10322 #define Z10_EARLYLOAD_DISTANCE 7
10324 /* Rearrange the ready list in order to avoid the situation described
10325 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10326 moved to the very end of the ready list. */
10328 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10330 unsigned int regno
;
10331 int nready
= *nready_p
;
10336 enum attr_type flag
;
10339 /* Skip DISTANCE - 1 active insns. */
10340 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10341 distance
> 0 && insn
!= NULL_RTX
;
10342 distance
--, insn
= prev_active_insn (insn
))
10343 if (CALL_P (insn
) || JUMP_P (insn
))
10346 if (insn
== NULL_RTX
)
10349 set
= single_set (insn
);
10351 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10352 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10355 flag
= s390_safe_attr_type (insn
);
10357 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10360 regno
= REGNO (SET_DEST (set
));
10363 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10370 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10374 /* This function is called via hook TARGET_SCHED_REORDER before
10375 issueing one insn from list READY which contains *NREADYP entries.
10376 For target z10 it reorders load instructions to avoid early load
10377 conflicts in the floating point pipeline */
10379 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10380 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10382 if (s390_tune
== PROCESSOR_2097_Z10
)
10383 if (reload_completed
&& *nreadyp
> 1)
10384 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10386 return s390_issue_rate ();
10389 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10390 the scheduler has issued INSN. It stores the last issued insn into
10391 last_scheduled_insn in order to make it available for
10392 s390_sched_reorder. */
10394 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10395 int verbose ATTRIBUTE_UNUSED
,
10396 rtx insn
, int more
)
10398 last_scheduled_insn
= insn
;
10400 if (GET_CODE (PATTERN (insn
)) != USE
10401 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10408 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10409 int verbose ATTRIBUTE_UNUSED
,
10410 int max_ready ATTRIBUTE_UNUSED
)
10412 last_scheduled_insn
= NULL_RTX
;
10415 /* This function checks the whole of insn X for memory references. The
10416 function always returns zero because the framework it is called
10417 from would stop recursively analyzing the insn upon a return value
10418 other than zero. The real result of this function is updating
10419 counter variable MEM_COUNT. */
10421 check_dpu (rtx
*x
, unsigned *mem_count
)
10423 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10428 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10429 a new number struct loop *loop should be unrolled if tuned for cpus with
10430 a built-in stride prefetcher.
10431 The loop is analyzed for memory accesses by calling check_dpu for
10432 each rtx of the loop. Depending on the loop_depth and the amount of
10433 memory accesses a new number <=nunroll is returned to improve the
10434 behaviour of the hardware prefetch unit. */
10436 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10441 unsigned mem_count
= 0;
10443 if (s390_tune
!= PROCESSOR_2097_Z10
&& s390_tune
!= PROCESSOR_2817_Z196
)
10446 /* Count the number of memory references within the loop body. */
10447 bbs
= get_loop_body (loop
);
10448 for (i
= 0; i
< loop
->num_nodes
; i
++)
10450 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10451 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10452 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10456 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10457 if (mem_count
== 0)
10460 switch (loop_depth(loop
))
10463 return MIN (nunroll
, 28 / mem_count
);
10465 return MIN (nunroll
, 22 / mem_count
);
10467 return MIN (nunroll
, 16 / mem_count
);
10471 /* Initialize GCC target structure. */
10473 #undef TARGET_ASM_ALIGNED_HI_OP
10474 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10475 #undef TARGET_ASM_ALIGNED_DI_OP
10476 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10477 #undef TARGET_ASM_INTEGER
10478 #define TARGET_ASM_INTEGER s390_assemble_integer
10480 #undef TARGET_ASM_OPEN_PAREN
10481 #define TARGET_ASM_OPEN_PAREN ""
10483 #undef TARGET_ASM_CLOSE_PAREN
10484 #define TARGET_ASM_CLOSE_PAREN ""
10486 #undef TARGET_DEFAULT_TARGET_FLAGS
10487 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10489 #undef TARGET_HANDLE_OPTION
10490 #define TARGET_HANDLE_OPTION s390_handle_option
10492 #undef TARGET_OPTION_OVERRIDE
10493 #define TARGET_OPTION_OVERRIDE s390_option_override
10495 #undef TARGET_OPTION_OPTIMIZATION
10496 #define TARGET_OPTION_OPTIMIZATION s390_option_optimization
10498 #undef TARGET_ENCODE_SECTION_INFO
10499 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10501 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10502 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10505 #undef TARGET_HAVE_TLS
10506 #define TARGET_HAVE_TLS true
10508 #undef TARGET_CANNOT_FORCE_CONST_MEM
10509 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10511 #undef TARGET_DELEGITIMIZE_ADDRESS
10512 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10514 #undef TARGET_LEGITIMIZE_ADDRESS
10515 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10517 #undef TARGET_RETURN_IN_MEMORY
10518 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10520 #undef TARGET_INIT_BUILTINS
10521 #define TARGET_INIT_BUILTINS s390_init_builtins
10522 #undef TARGET_EXPAND_BUILTIN
10523 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10525 #undef TARGET_ASM_OUTPUT_MI_THUNK
10526 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10527 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10528 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10530 #undef TARGET_SCHED_ADJUST_PRIORITY
10531 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10532 #undef TARGET_SCHED_ISSUE_RATE
10533 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10534 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10535 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10537 #undef TARGET_SCHED_VARIABLE_ISSUE
10538 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10539 #undef TARGET_SCHED_REORDER
10540 #define TARGET_SCHED_REORDER s390_sched_reorder
10541 #undef TARGET_SCHED_INIT
10542 #define TARGET_SCHED_INIT s390_sched_init
10544 #undef TARGET_CANNOT_COPY_INSN_P
10545 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10546 #undef TARGET_RTX_COSTS
10547 #define TARGET_RTX_COSTS s390_rtx_costs
10548 #undef TARGET_ADDRESS_COST
10549 #define TARGET_ADDRESS_COST s390_address_cost
10551 #undef TARGET_MACHINE_DEPENDENT_REORG
10552 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10554 #undef TARGET_VALID_POINTER_MODE
10555 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10557 #undef TARGET_BUILD_BUILTIN_VA_LIST
10558 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10559 #undef TARGET_EXPAND_BUILTIN_VA_START
10560 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10561 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10562 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10564 #undef TARGET_PROMOTE_FUNCTION_MODE
10565 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10566 #undef TARGET_PASS_BY_REFERENCE
10567 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10569 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10570 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10572 #undef TARGET_FIXED_CONDITION_CODE_REGS
10573 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10575 #undef TARGET_CC_MODES_COMPATIBLE
10576 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10578 #undef TARGET_INVALID_WITHIN_DOLOOP
10579 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10582 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10583 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10586 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10587 #undef TARGET_MANGLE_TYPE
10588 #define TARGET_MANGLE_TYPE s390_mangle_type
10591 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10592 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10594 #undef TARGET_SECONDARY_RELOAD
10595 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10597 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10598 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10600 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10601 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10603 #undef TARGET_LEGITIMATE_ADDRESS_P
10604 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10606 #undef TARGET_CAN_ELIMINATE
10607 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10609 #undef TARGET_LOOP_UNROLL_ADJUST
10610 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10612 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10613 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10614 #undef TARGET_TRAMPOLINE_INIT
10615 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10617 #undef TARGET_UNWIND_WORD_MODE
10618 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10620 struct gcc_target targetm
= TARGET_INITIALIZER
;
10622 #include "gt-s390.h"