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s390.c (s390_handle_arch_option): Set type and flags to defined values in case of...
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55 #include "params.h"
56 #include "cfgloop.h"
57
58
59 /* Define the specific costs for a given cpu. */
60
61 struct processor_costs
62 {
63 /* multiplication */
64 const int m; /* cost of an M instruction. */
65 const int mghi; /* cost of an MGHI instruction. */
66 const int mh; /* cost of an MH instruction. */
67 const int mhi; /* cost of an MHI instruction. */
68 const int ml; /* cost of an ML instruction. */
69 const int mr; /* cost of an MR instruction. */
70 const int ms; /* cost of an MS instruction. */
71 const int msg; /* cost of an MSG instruction. */
72 const int msgf; /* cost of an MSGF instruction. */
73 const int msgfr; /* cost of an MSGFR instruction. */
74 const int msgr; /* cost of an MSGR instruction. */
75 const int msr; /* cost of an MSR instruction. */
76 const int mult_df; /* cost of multiplication in DFmode. */
77 const int mxbr;
78 /* square root */
79 const int sqxbr; /* cost of square root in TFmode. */
80 const int sqdbr; /* cost of square root in DFmode. */
81 const int sqebr; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr; /* cost of multiply and add in DFmode. */
84 const int maebr; /* cost of multiply and add in SFmode. */
85 /* division */
86 const int dxbr;
87 const int ddbr;
88 const int debr;
89 const int dlgr;
90 const int dlr;
91 const int dr;
92 const int dsgfr;
93 const int dsgr;
94 };
95
96 const struct processor_costs *s390_cost;
97
98 static const
99 struct processor_costs z900_cost =
100 {
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
128 };
129
130 static const
131 struct processor_costs z990_cost =
132 {
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
160 };
161
162 static const
163 struct processor_costs z9_109_cost =
164 {
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
192 };
193
194 static const
195 struct processor_costs z10_cost =
196 {
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
224 };
225
226 static const
227 struct processor_costs z196_cost =
228 {
229 COSTS_N_INSNS (7), /* M */
230 COSTS_N_INSNS (5), /* MGHI */
231 COSTS_N_INSNS (5), /* MH */
232 COSTS_N_INSNS (5), /* MHI */
233 COSTS_N_INSNS (7), /* ML */
234 COSTS_N_INSNS (7), /* MR */
235 COSTS_N_INSNS (6), /* MS */
236 COSTS_N_INSNS (8), /* MSG */
237 COSTS_N_INSNS (6), /* MSGF */
238 COSTS_N_INSNS (6), /* MSGFR */
239 COSTS_N_INSNS (8), /* MSGR */
240 COSTS_N_INSNS (6), /* MSR */
241 COSTS_N_INSNS (1) , /* multiplication in DFmode */
242 COSTS_N_INSNS (40), /* MXBR B+40 */
243 COSTS_N_INSNS (100), /* SQXBR B+100 */
244 COSTS_N_INSNS (42), /* SQDBR B+42 */
245 COSTS_N_INSNS (28), /* SQEBR B+28 */
246 COSTS_N_INSNS (1), /* MADBR B */
247 COSTS_N_INSNS (1), /* MAEBR B */
248 COSTS_N_INSNS (101), /* DXBR B+101 */
249 COSTS_N_INSNS (29), /* DDBR */
250 COSTS_N_INSNS (22), /* DEBR */
251 COSTS_N_INSNS (160), /* DLGR cracked */
252 COSTS_N_INSNS (160), /* DLR cracked */
253 COSTS_N_INSNS (160), /* DR expanded */
254 COSTS_N_INSNS (160), /* DSGFR cracked */
255 COSTS_N_INSNS (160), /* DSGR cracked */
256 };
257
258 extern int reload_completed;
259
260 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
261 static rtx last_scheduled_insn;
262
263 /* Structure used to hold the components of a S/390 memory
264 address. A legitimate address on S/390 is of the general
265 form
266 base + index + displacement
267 where any of the components is optional.
268
269 base and index are registers of the class ADDR_REGS,
270 displacement is an unsigned 12-bit immediate constant. */
271
272 struct s390_address
273 {
274 rtx base;
275 rtx indx;
276 rtx disp;
277 bool pointer;
278 bool literal_pool;
279 };
280
281 /* Which cpu are we tuning for. */
282 enum processor_type s390_tune = PROCESSOR_max;
283 int s390_tune_flags;
284 /* Which instruction set architecture to use. */
285 enum processor_type s390_arch;
286 int s390_arch_flags;
287
288 HOST_WIDE_INT s390_warn_framesize = 0;
289 HOST_WIDE_INT s390_stack_size = 0;
290 HOST_WIDE_INT s390_stack_guard = 0;
291
292 /* The following structure is embedded in the machine
293 specific part of struct function. */
294
295 struct GTY (()) s390_frame_layout
296 {
297 /* Offset within stack frame. */
298 HOST_WIDE_INT gprs_offset;
299 HOST_WIDE_INT f0_offset;
300 HOST_WIDE_INT f4_offset;
301 HOST_WIDE_INT f8_offset;
302 HOST_WIDE_INT backchain_offset;
303
304 /* Number of first and last gpr where slots in the register
305 save area are reserved for. */
306 int first_save_gpr_slot;
307 int last_save_gpr_slot;
308
309 /* Number of first and last gpr to be saved, restored. */
310 int first_save_gpr;
311 int first_restore_gpr;
312 int last_save_gpr;
313 int last_restore_gpr;
314
315 /* Bits standing for floating point registers. Set, if the
316 respective register has to be saved. Starting with reg 16 (f0)
317 at the rightmost bit.
318 Bit 15 - 8 7 6 5 4 3 2 1 0
319 fpr 15 - 8 7 5 3 1 6 4 2 0
320 reg 31 - 24 23 22 21 20 19 18 17 16 */
321 unsigned int fpr_bitmap;
322
323 /* Number of floating point registers f8-f15 which must be saved. */
324 int high_fprs;
325
326 /* Set if return address needs to be saved.
327 This flag is set by s390_return_addr_rtx if it could not use
328 the initial value of r14 and therefore depends on r14 saved
329 to the stack. */
330 bool save_return_addr_p;
331
332 /* Size of stack frame. */
333 HOST_WIDE_INT frame_size;
334 };
335
336 /* Define the structure for the machine field in struct function. */
337
338 struct GTY(()) machine_function
339 {
340 struct s390_frame_layout frame_layout;
341
342 /* Literal pool base register. */
343 rtx base_reg;
344
345 /* True if we may need to perform branch splitting. */
346 bool split_branches_pending_p;
347
348 /* Some local-dynamic TLS symbol name. */
349 const char *some_ld_name;
350
351 bool has_landing_pad_p;
352 };
353
354 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
355
356 #define cfun_frame_layout (cfun->machine->frame_layout)
357 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
358 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
359 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
360 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
361 (1 << (BITNUM)))
362 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
363 (1 << (BITNUM))))
364
365 /* Number of GPRs and FPRs used for argument passing. */
366 #define GP_ARG_NUM_REG 5
367 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
368
369 /* A couple of shortcuts. */
370 #define CONST_OK_FOR_J(x) \
371 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
372 #define CONST_OK_FOR_K(x) \
373 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
374 #define CONST_OK_FOR_Os(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
376 #define CONST_OK_FOR_Op(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
378 #define CONST_OK_FOR_On(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
380
381 #define REGNO_PAIR_OK(REGNO, MODE) \
382 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
383
384 /* That's the read ahead of the dynamic branch prediction unit in
385 bytes on a z10 (or higher) CPU. */
386 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
387
388 static enum machine_mode
389 s390_libgcc_cmp_return_mode (void)
390 {
391 return TARGET_64BIT ? DImode : SImode;
392 }
393
394 static enum machine_mode
395 s390_libgcc_shift_count_mode (void)
396 {
397 return TARGET_64BIT ? DImode : SImode;
398 }
399
400 static enum machine_mode
401 s390_unwind_word_mode (void)
402 {
403 return TARGET_64BIT ? DImode : SImode;
404 }
405
406 /* Return true if the back end supports mode MODE. */
407 static bool
408 s390_scalar_mode_supported_p (enum machine_mode mode)
409 {
410 /* In contrast to the default implementation reject TImode constants on 31bit
411 TARGET_ZARCH for ABI compliance. */
412 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
413 return false;
414
415 if (DECIMAL_FLOAT_MODE_P (mode))
416 return default_decimal_float_supported_p ();
417
418 return default_scalar_mode_supported_p (mode);
419 }
420
421 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
422
423 void
424 s390_set_has_landing_pad_p (bool value)
425 {
426 cfun->machine->has_landing_pad_p = value;
427 }
428
429 /* If two condition code modes are compatible, return a condition code
430 mode which is compatible with both. Otherwise, return
431 VOIDmode. */
432
433 static enum machine_mode
434 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
435 {
436 if (m1 == m2)
437 return m1;
438
439 switch (m1)
440 {
441 case CCZmode:
442 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
443 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
444 return m2;
445 return VOIDmode;
446
447 case CCSmode:
448 case CCUmode:
449 case CCTmode:
450 case CCSRmode:
451 case CCURmode:
452 case CCZ1mode:
453 if (m2 == CCZmode)
454 return m1;
455
456 return VOIDmode;
457
458 default:
459 return VOIDmode;
460 }
461 return VOIDmode;
462 }
463
464 /* Return true if SET either doesn't set the CC register, or else
465 the source and destination have matching CC modes and that
466 CC mode is at least as constrained as REQ_MODE. */
467
468 static bool
469 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
470 {
471 enum machine_mode set_mode;
472
473 gcc_assert (GET_CODE (set) == SET);
474
475 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
476 return 1;
477
478 set_mode = GET_MODE (SET_DEST (set));
479 switch (set_mode)
480 {
481 case CCSmode:
482 case CCSRmode:
483 case CCUmode:
484 case CCURmode:
485 case CCLmode:
486 case CCL1mode:
487 case CCL2mode:
488 case CCL3mode:
489 case CCT1mode:
490 case CCT2mode:
491 case CCT3mode:
492 if (req_mode != set_mode)
493 return 0;
494 break;
495
496 case CCZmode:
497 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
498 && req_mode != CCSRmode && req_mode != CCURmode)
499 return 0;
500 break;
501
502 case CCAPmode:
503 case CCANmode:
504 if (req_mode != CCAmode)
505 return 0;
506 break;
507
508 default:
509 gcc_unreachable ();
510 }
511
512 return (GET_MODE (SET_SRC (set)) == set_mode);
513 }
514
515 /* Return true if every SET in INSN that sets the CC register
516 has source and destination with matching CC modes and that
517 CC mode is at least as constrained as REQ_MODE.
518 If REQ_MODE is VOIDmode, always return false. */
519
520 bool
521 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
522 {
523 int i;
524
525 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
526 if (req_mode == VOIDmode)
527 return false;
528
529 if (GET_CODE (PATTERN (insn)) == SET)
530 return s390_match_ccmode_set (PATTERN (insn), req_mode);
531
532 if (GET_CODE (PATTERN (insn)) == PARALLEL)
533 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
534 {
535 rtx set = XVECEXP (PATTERN (insn), 0, i);
536 if (GET_CODE (set) == SET)
537 if (!s390_match_ccmode_set (set, req_mode))
538 return false;
539 }
540
541 return true;
542 }
543
544 /* If a test-under-mask instruction can be used to implement
545 (compare (and ... OP1) OP2), return the CC mode required
546 to do that. Otherwise, return VOIDmode.
547 MIXED is true if the instruction can distinguish between
548 CC1 and CC2 for mixed selected bits (TMxx), it is false
549 if the instruction cannot (TM). */
550
551 enum machine_mode
552 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
553 {
554 int bit0, bit1;
555
556 /* ??? Fixme: should work on CONST_DOUBLE as well. */
557 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
558 return VOIDmode;
559
560 /* Selected bits all zero: CC0.
561 e.g.: int a; if ((a & (16 + 128)) == 0) */
562 if (INTVAL (op2) == 0)
563 return CCTmode;
564
565 /* Selected bits all one: CC3.
566 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
567 if (INTVAL (op2) == INTVAL (op1))
568 return CCT3mode;
569
570 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
571 int a;
572 if ((a & (16 + 128)) == 16) -> CCT1
573 if ((a & (16 + 128)) == 128) -> CCT2 */
574 if (mixed)
575 {
576 bit1 = exact_log2 (INTVAL (op2));
577 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
578 if (bit0 != -1 && bit1 != -1)
579 return bit0 > bit1 ? CCT1mode : CCT2mode;
580 }
581
582 return VOIDmode;
583 }
584
585 /* Given a comparison code OP (EQ, NE, etc.) and the operands
586 OP0 and OP1 of a COMPARE, return the mode to be used for the
587 comparison. */
588
589 enum machine_mode
590 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
591 {
592 switch (code)
593 {
594 case EQ:
595 case NE:
596 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
597 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
598 return CCAPmode;
599 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
600 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
601 return CCAPmode;
602 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
603 || GET_CODE (op1) == NEG)
604 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
605 return CCLmode;
606
607 if (GET_CODE (op0) == AND)
608 {
609 /* Check whether we can potentially do it via TM. */
610 enum machine_mode ccmode;
611 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
612 if (ccmode != VOIDmode)
613 {
614 /* Relax CCTmode to CCZmode to allow fall-back to AND
615 if that turns out to be beneficial. */
616 return ccmode == CCTmode ? CCZmode : ccmode;
617 }
618 }
619
620 if (register_operand (op0, HImode)
621 && GET_CODE (op1) == CONST_INT
622 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
623 return CCT3mode;
624 if (register_operand (op0, QImode)
625 && GET_CODE (op1) == CONST_INT
626 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
627 return CCT3mode;
628
629 return CCZmode;
630
631 case LE:
632 case LT:
633 case GE:
634 case GT:
635 /* The only overflow condition of NEG and ABS happens when
636 -INT_MAX is used as parameter, which stays negative. So
637 we have an overflow from a positive value to a negative.
638 Using CCAP mode the resulting cc can be used for comparisons. */
639 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
640 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
641 return CCAPmode;
642
643 /* If constants are involved in an add instruction it is possible to use
644 the resulting cc for comparisons with zero. Knowing the sign of the
645 constant the overflow behavior gets predictable. e.g.:
646 int a, b; if ((b = a + c) > 0)
647 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
648 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
649 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
650 {
651 if (INTVAL (XEXP((op0), 1)) < 0)
652 return CCANmode;
653 else
654 return CCAPmode;
655 }
656 /* Fall through. */
657 case UNORDERED:
658 case ORDERED:
659 case UNEQ:
660 case UNLE:
661 case UNLT:
662 case UNGE:
663 case UNGT:
664 case LTGT:
665 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
666 && GET_CODE (op1) != CONST_INT)
667 return CCSRmode;
668 return CCSmode;
669
670 case LTU:
671 case GEU:
672 if (GET_CODE (op0) == PLUS
673 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
674 return CCL1mode;
675
676 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
677 && GET_CODE (op1) != CONST_INT)
678 return CCURmode;
679 return CCUmode;
680
681 case LEU:
682 case GTU:
683 if (GET_CODE (op0) == MINUS
684 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
685 return CCL2mode;
686
687 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
688 && GET_CODE (op1) != CONST_INT)
689 return CCURmode;
690 return CCUmode;
691
692 default:
693 gcc_unreachable ();
694 }
695 }
696
697 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
698 that we can implement more efficiently. */
699
700 void
701 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
702 {
703 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
704 if ((*code == EQ || *code == NE)
705 && *op1 == const0_rtx
706 && GET_CODE (*op0) == ZERO_EXTRACT
707 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
708 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
709 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
710 {
711 rtx inner = XEXP (*op0, 0);
712 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
713 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
714 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
715
716 if (len > 0 && len < modesize
717 && pos >= 0 && pos + len <= modesize
718 && modesize <= HOST_BITS_PER_WIDE_INT)
719 {
720 unsigned HOST_WIDE_INT block;
721 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
722 block <<= modesize - pos - len;
723
724 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
725 gen_int_mode (block, GET_MODE (inner)));
726 }
727 }
728
729 /* Narrow AND of memory against immediate to enable TM. */
730 if ((*code == EQ || *code == NE)
731 && *op1 == const0_rtx
732 && GET_CODE (*op0) == AND
733 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
734 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
735 {
736 rtx inner = XEXP (*op0, 0);
737 rtx mask = XEXP (*op0, 1);
738
739 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
740 if (GET_CODE (inner) == SUBREG
741 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
742 && (GET_MODE_SIZE (GET_MODE (inner))
743 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
744 && ((INTVAL (mask)
745 & GET_MODE_MASK (GET_MODE (inner))
746 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
747 == 0))
748 inner = SUBREG_REG (inner);
749
750 /* Do not change volatile MEMs. */
751 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
752 {
753 int part = s390_single_part (XEXP (*op0, 1),
754 GET_MODE (inner), QImode, 0);
755 if (part >= 0)
756 {
757 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
758 inner = adjust_address_nv (inner, QImode, part);
759 *op0 = gen_rtx_AND (QImode, inner, mask);
760 }
761 }
762 }
763
764 /* Narrow comparisons against 0xffff to HImode if possible. */
765 if ((*code == EQ || *code == NE)
766 && GET_CODE (*op1) == CONST_INT
767 && INTVAL (*op1) == 0xffff
768 && SCALAR_INT_MODE_P (GET_MODE (*op0))
769 && (nonzero_bits (*op0, GET_MODE (*op0))
770 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
771 {
772 *op0 = gen_lowpart (HImode, *op0);
773 *op1 = constm1_rtx;
774 }
775
776 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
777 if (GET_CODE (*op0) == UNSPEC
778 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
779 && XVECLEN (*op0, 0) == 1
780 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
781 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
782 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
783 && *op1 == const0_rtx)
784 {
785 enum rtx_code new_code = UNKNOWN;
786 switch (*code)
787 {
788 case EQ: new_code = EQ; break;
789 case NE: new_code = NE; break;
790 case LT: new_code = GTU; break;
791 case GT: new_code = LTU; break;
792 case LE: new_code = GEU; break;
793 case GE: new_code = LEU; break;
794 default: break;
795 }
796
797 if (new_code != UNKNOWN)
798 {
799 *op0 = XVECEXP (*op0, 0, 0);
800 *code = new_code;
801 }
802 }
803
804 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
805 if (GET_CODE (*op0) == UNSPEC
806 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
807 && XVECLEN (*op0, 0) == 1
808 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
809 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
810 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
811 && *op1 == const0_rtx)
812 {
813 enum rtx_code new_code = UNKNOWN;
814 switch (*code)
815 {
816 case EQ: new_code = EQ; break;
817 case NE: new_code = NE; break;
818 default: break;
819 }
820
821 if (new_code != UNKNOWN)
822 {
823 *op0 = XVECEXP (*op0, 0, 0);
824 *code = new_code;
825 }
826 }
827
828 /* Simplify cascaded EQ, NE with const0_rtx. */
829 if ((*code == NE || *code == EQ)
830 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
831 && GET_MODE (*op0) == SImode
832 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
833 && REG_P (XEXP (*op0, 0))
834 && XEXP (*op0, 1) == const0_rtx
835 && *op1 == const0_rtx)
836 {
837 if ((*code == EQ && GET_CODE (*op0) == NE)
838 || (*code == NE && GET_CODE (*op0) == EQ))
839 *code = EQ;
840 else
841 *code = NE;
842 *op0 = XEXP (*op0, 0);
843 }
844
845 /* Prefer register over memory as first operand. */
846 if (MEM_P (*op0) && REG_P (*op1))
847 {
848 rtx tem = *op0; *op0 = *op1; *op1 = tem;
849 *code = swap_condition (*code);
850 }
851 }
852
853 /* Emit a compare instruction suitable to implement the comparison
854 OP0 CODE OP1. Return the correct condition RTL to be placed in
855 the IF_THEN_ELSE of the conditional branch testing the result. */
856
857 rtx
858 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
859 {
860 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
861 rtx cc;
862
863 /* Do not output a redundant compare instruction if a compare_and_swap
864 pattern already computed the result and the machine modes are compatible. */
865 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
866 {
867 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
868 == GET_MODE (op0));
869 cc = op0;
870 }
871 else
872 {
873 cc = gen_rtx_REG (mode, CC_REGNUM);
874 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
875 }
876
877 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
878 }
879
880 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
881 matches CMP.
882 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
883 conditional branch testing the result. */
884
885 static rtx
886 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
887 {
888 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
889 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
890 }
891
892 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
893 unconditional jump, else a conditional jump under condition COND. */
894
895 void
896 s390_emit_jump (rtx target, rtx cond)
897 {
898 rtx insn;
899
900 target = gen_rtx_LABEL_REF (VOIDmode, target);
901 if (cond)
902 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
903
904 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
905 emit_jump_insn (insn);
906 }
907
908 /* Return branch condition mask to implement a branch
909 specified by CODE. Return -1 for invalid comparisons. */
910
911 int
912 s390_branch_condition_mask (rtx code)
913 {
914 const int CC0 = 1 << 3;
915 const int CC1 = 1 << 2;
916 const int CC2 = 1 << 1;
917 const int CC3 = 1 << 0;
918
919 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
920 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
921 gcc_assert (XEXP (code, 1) == const0_rtx);
922
923 switch (GET_MODE (XEXP (code, 0)))
924 {
925 case CCZmode:
926 case CCZ1mode:
927 switch (GET_CODE (code))
928 {
929 case EQ: return CC0;
930 case NE: return CC1 | CC2 | CC3;
931 default: return -1;
932 }
933 break;
934
935 case CCT1mode:
936 switch (GET_CODE (code))
937 {
938 case EQ: return CC1;
939 case NE: return CC0 | CC2 | CC3;
940 default: return -1;
941 }
942 break;
943
944 case CCT2mode:
945 switch (GET_CODE (code))
946 {
947 case EQ: return CC2;
948 case NE: return CC0 | CC1 | CC3;
949 default: return -1;
950 }
951 break;
952
953 case CCT3mode:
954 switch (GET_CODE (code))
955 {
956 case EQ: return CC3;
957 case NE: return CC0 | CC1 | CC2;
958 default: return -1;
959 }
960 break;
961
962 case CCLmode:
963 switch (GET_CODE (code))
964 {
965 case EQ: return CC0 | CC2;
966 case NE: return CC1 | CC3;
967 default: return -1;
968 }
969 break;
970
971 case CCL1mode:
972 switch (GET_CODE (code))
973 {
974 case LTU: return CC2 | CC3; /* carry */
975 case GEU: return CC0 | CC1; /* no carry */
976 default: return -1;
977 }
978 break;
979
980 case CCL2mode:
981 switch (GET_CODE (code))
982 {
983 case GTU: return CC0 | CC1; /* borrow */
984 case LEU: return CC2 | CC3; /* no borrow */
985 default: return -1;
986 }
987 break;
988
989 case CCL3mode:
990 switch (GET_CODE (code))
991 {
992 case EQ: return CC0 | CC2;
993 case NE: return CC1 | CC3;
994 case LTU: return CC1;
995 case GTU: return CC3;
996 case LEU: return CC1 | CC2;
997 case GEU: return CC2 | CC3;
998 default: return -1;
999 }
1000
1001 case CCUmode:
1002 switch (GET_CODE (code))
1003 {
1004 case EQ: return CC0;
1005 case NE: return CC1 | CC2 | CC3;
1006 case LTU: return CC1;
1007 case GTU: return CC2;
1008 case LEU: return CC0 | CC1;
1009 case GEU: return CC0 | CC2;
1010 default: return -1;
1011 }
1012 break;
1013
1014 case CCURmode:
1015 switch (GET_CODE (code))
1016 {
1017 case EQ: return CC0;
1018 case NE: return CC2 | CC1 | CC3;
1019 case LTU: return CC2;
1020 case GTU: return CC1;
1021 case LEU: return CC0 | CC2;
1022 case GEU: return CC0 | CC1;
1023 default: return -1;
1024 }
1025 break;
1026
1027 case CCAPmode:
1028 switch (GET_CODE (code))
1029 {
1030 case EQ: return CC0;
1031 case NE: return CC1 | CC2 | CC3;
1032 case LT: return CC1 | CC3;
1033 case GT: return CC2;
1034 case LE: return CC0 | CC1 | CC3;
1035 case GE: return CC0 | CC2;
1036 default: return -1;
1037 }
1038 break;
1039
1040 case CCANmode:
1041 switch (GET_CODE (code))
1042 {
1043 case EQ: return CC0;
1044 case NE: return CC1 | CC2 | CC3;
1045 case LT: return CC1;
1046 case GT: return CC2 | CC3;
1047 case LE: return CC0 | CC1;
1048 case GE: return CC0 | CC2 | CC3;
1049 default: return -1;
1050 }
1051 break;
1052
1053 case CCSmode:
1054 switch (GET_CODE (code))
1055 {
1056 case EQ: return CC0;
1057 case NE: return CC1 | CC2 | CC3;
1058 case LT: return CC1;
1059 case GT: return CC2;
1060 case LE: return CC0 | CC1;
1061 case GE: return CC0 | CC2;
1062 case UNORDERED: return CC3;
1063 case ORDERED: return CC0 | CC1 | CC2;
1064 case UNEQ: return CC0 | CC3;
1065 case UNLT: return CC1 | CC3;
1066 case UNGT: return CC2 | CC3;
1067 case UNLE: return CC0 | CC1 | CC3;
1068 case UNGE: return CC0 | CC2 | CC3;
1069 case LTGT: return CC1 | CC2;
1070 default: return -1;
1071 }
1072 break;
1073
1074 case CCSRmode:
1075 switch (GET_CODE (code))
1076 {
1077 case EQ: return CC0;
1078 case NE: return CC2 | CC1 | CC3;
1079 case LT: return CC2;
1080 case GT: return CC1;
1081 case LE: return CC0 | CC2;
1082 case GE: return CC0 | CC1;
1083 case UNORDERED: return CC3;
1084 case ORDERED: return CC0 | CC2 | CC1;
1085 case UNEQ: return CC0 | CC3;
1086 case UNLT: return CC2 | CC3;
1087 case UNGT: return CC1 | CC3;
1088 case UNLE: return CC0 | CC2 | CC3;
1089 case UNGE: return CC0 | CC1 | CC3;
1090 case LTGT: return CC2 | CC1;
1091 default: return -1;
1092 }
1093 break;
1094
1095 default:
1096 return -1;
1097 }
1098 }
1099
1100
1101 /* Return branch condition mask to implement a compare and branch
1102 specified by CODE. Return -1 for invalid comparisons. */
1103
1104 int
1105 s390_compare_and_branch_condition_mask (rtx code)
1106 {
1107 const int CC0 = 1 << 3;
1108 const int CC1 = 1 << 2;
1109 const int CC2 = 1 << 1;
1110
1111 switch (GET_CODE (code))
1112 {
1113 case EQ:
1114 return CC0;
1115 case NE:
1116 return CC1 | CC2;
1117 case LT:
1118 case LTU:
1119 return CC1;
1120 case GT:
1121 case GTU:
1122 return CC2;
1123 case LE:
1124 case LEU:
1125 return CC0 | CC1;
1126 case GE:
1127 case GEU:
1128 return CC0 | CC2;
1129 default:
1130 gcc_unreachable ();
1131 }
1132 return -1;
1133 }
1134
1135 /* If INV is false, return assembler mnemonic string to implement
1136 a branch specified by CODE. If INV is true, return mnemonic
1137 for the corresponding inverted branch. */
1138
1139 static const char *
1140 s390_branch_condition_mnemonic (rtx code, int inv)
1141 {
1142 int mask;
1143
1144 static const char *const mnemonic[16] =
1145 {
1146 NULL, "o", "h", "nle",
1147 "l", "nhe", "lh", "ne",
1148 "e", "nlh", "he", "nl",
1149 "le", "nh", "no", NULL
1150 };
1151
1152 if (GET_CODE (XEXP (code, 0)) == REG
1153 && REGNO (XEXP (code, 0)) == CC_REGNUM
1154 && XEXP (code, 1) == const0_rtx)
1155 mask = s390_branch_condition_mask (code);
1156 else
1157 mask = s390_compare_and_branch_condition_mask (code);
1158
1159 gcc_assert (mask >= 0);
1160
1161 if (inv)
1162 mask ^= 15;
1163
1164 gcc_assert (mask >= 1 && mask <= 14);
1165
1166 return mnemonic[mask];
1167 }
1168
1169 /* Return the part of op which has a value different from def.
1170 The size of the part is determined by mode.
1171 Use this function only if you already know that op really
1172 contains such a part. */
1173
1174 unsigned HOST_WIDE_INT
1175 s390_extract_part (rtx op, enum machine_mode mode, int def)
1176 {
1177 unsigned HOST_WIDE_INT value = 0;
1178 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1179 int part_bits = GET_MODE_BITSIZE (mode);
1180 unsigned HOST_WIDE_INT part_mask
1181 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1182 int i;
1183
1184 for (i = 0; i < max_parts; i++)
1185 {
1186 if (i == 0)
1187 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1188 else
1189 value >>= part_bits;
1190
1191 if ((value & part_mask) != (def & part_mask))
1192 return value & part_mask;
1193 }
1194
1195 gcc_unreachable ();
1196 }
1197
1198 /* If OP is an integer constant of mode MODE with exactly one
1199 part of mode PART_MODE unequal to DEF, return the number of that
1200 part. Otherwise, return -1. */
1201
1202 int
1203 s390_single_part (rtx op,
1204 enum machine_mode mode,
1205 enum machine_mode part_mode,
1206 int def)
1207 {
1208 unsigned HOST_WIDE_INT value = 0;
1209 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1210 unsigned HOST_WIDE_INT part_mask
1211 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1212 int i, part = -1;
1213
1214 if (GET_CODE (op) != CONST_INT)
1215 return -1;
1216
1217 for (i = 0; i < n_parts; i++)
1218 {
1219 if (i == 0)
1220 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1221 else
1222 value >>= GET_MODE_BITSIZE (part_mode);
1223
1224 if ((value & part_mask) != (def & part_mask))
1225 {
1226 if (part != -1)
1227 return -1;
1228 else
1229 part = i;
1230 }
1231 }
1232 return part == -1 ? -1 : n_parts - 1 - part;
1233 }
1234
1235 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1236 bits and no other bits are set in IN. POS and LENGTH can be used
1237 to obtain the start position and the length of the bitfield.
1238
1239 POS gives the position of the first bit of the bitfield counting
1240 from the lowest order bit starting with zero. In order to use this
1241 value for S/390 instructions this has to be converted to "bits big
1242 endian" style. */
1243
1244 bool
1245 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1246 int *pos, int *length)
1247 {
1248 int tmp_pos = 0;
1249 int tmp_length = 0;
1250 int i;
1251 unsigned HOST_WIDE_INT mask = 1ULL;
1252 bool contiguous = false;
1253
1254 for (i = 0; i < size; mask <<= 1, i++)
1255 {
1256 if (contiguous)
1257 {
1258 if (mask & in)
1259 tmp_length++;
1260 else
1261 break;
1262 }
1263 else
1264 {
1265 if (mask & in)
1266 {
1267 contiguous = true;
1268 tmp_length++;
1269 }
1270 else
1271 tmp_pos++;
1272 }
1273 }
1274
1275 if (!tmp_length)
1276 return false;
1277
1278 /* Calculate a mask for all bits beyond the contiguous bits. */
1279 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1280
1281 if (mask & in)
1282 return false;
1283
1284 if (tmp_length + tmp_pos - 1 > size)
1285 return false;
1286
1287 if (length)
1288 *length = tmp_length;
1289
1290 if (pos)
1291 *pos = tmp_pos;
1292
1293 return true;
1294 }
1295
1296 /* Check whether we can (and want to) split a double-word
1297 move in mode MODE from SRC to DST into two single-word
1298 moves, moving the subword FIRST_SUBWORD first. */
1299
1300 bool
1301 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1302 {
1303 /* Floating point registers cannot be split. */
1304 if (FP_REG_P (src) || FP_REG_P (dst))
1305 return false;
1306
1307 /* We don't need to split if operands are directly accessible. */
1308 if (s_operand (src, mode) || s_operand (dst, mode))
1309 return false;
1310
1311 /* Non-offsettable memory references cannot be split. */
1312 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1313 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1314 return false;
1315
1316 /* Moving the first subword must not clobber a register
1317 needed to move the second subword. */
1318 if (register_operand (dst, mode))
1319 {
1320 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1321 if (reg_overlap_mentioned_p (subreg, src))
1322 return false;
1323 }
1324
1325 return true;
1326 }
1327
1328 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1329 and [MEM2, MEM2 + SIZE] do overlap and false
1330 otherwise. */
1331
1332 bool
1333 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1334 {
1335 rtx addr1, addr2, addr_delta;
1336 HOST_WIDE_INT delta;
1337
1338 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1339 return true;
1340
1341 if (size == 0)
1342 return false;
1343
1344 addr1 = XEXP (mem1, 0);
1345 addr2 = XEXP (mem2, 0);
1346
1347 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1348
1349 /* This overlapping check is used by peepholes merging memory block operations.
1350 Overlapping operations would otherwise be recognized by the S/390 hardware
1351 and would fall back to a slower implementation. Allowing overlapping
1352 operations would lead to slow code but not to wrong code. Therefore we are
1353 somewhat optimistic if we cannot prove that the memory blocks are
1354 overlapping.
1355 That's why we return false here although this may accept operations on
1356 overlapping memory areas. */
1357 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1358 return false;
1359
1360 delta = INTVAL (addr_delta);
1361
1362 if (delta == 0
1363 || (delta > 0 && delta < size)
1364 || (delta < 0 && -delta < size))
1365 return true;
1366
1367 return false;
1368 }
1369
1370 /* Check whether the address of memory reference MEM2 equals exactly
1371 the address of memory reference MEM1 plus DELTA. Return true if
1372 we can prove this to be the case, false otherwise. */
1373
1374 bool
1375 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1376 {
1377 rtx addr1, addr2, addr_delta;
1378
1379 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1380 return false;
1381
1382 addr1 = XEXP (mem1, 0);
1383 addr2 = XEXP (mem2, 0);
1384
1385 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1386 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1387 return false;
1388
1389 return true;
1390 }
1391
1392 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1393
1394 void
1395 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1396 rtx *operands)
1397 {
1398 enum machine_mode wmode = mode;
1399 rtx dst = operands[0];
1400 rtx src1 = operands[1];
1401 rtx src2 = operands[2];
1402 rtx op, clob, tem;
1403
1404 /* If we cannot handle the operation directly, use a temp register. */
1405 if (!s390_logical_operator_ok_p (operands))
1406 dst = gen_reg_rtx (mode);
1407
1408 /* QImode and HImode patterns make sense only if we have a destination
1409 in memory. Otherwise perform the operation in SImode. */
1410 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1411 wmode = SImode;
1412
1413 /* Widen operands if required. */
1414 if (mode != wmode)
1415 {
1416 if (GET_CODE (dst) == SUBREG
1417 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1418 dst = tem;
1419 else if (REG_P (dst))
1420 dst = gen_rtx_SUBREG (wmode, dst, 0);
1421 else
1422 dst = gen_reg_rtx (wmode);
1423
1424 if (GET_CODE (src1) == SUBREG
1425 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1426 src1 = tem;
1427 else if (GET_MODE (src1) != VOIDmode)
1428 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1429
1430 if (GET_CODE (src2) == SUBREG
1431 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1432 src2 = tem;
1433 else if (GET_MODE (src2) != VOIDmode)
1434 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1435 }
1436
1437 /* Emit the instruction. */
1438 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1439 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1440 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1441
1442 /* Fix up the destination if needed. */
1443 if (dst != operands[0])
1444 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1445 }
1446
1447 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1448
1449 bool
1450 s390_logical_operator_ok_p (rtx *operands)
1451 {
1452 /* If the destination operand is in memory, it needs to coincide
1453 with one of the source operands. After reload, it has to be
1454 the first source operand. */
1455 if (GET_CODE (operands[0]) == MEM)
1456 return rtx_equal_p (operands[0], operands[1])
1457 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1458
1459 return true;
1460 }
1461
1462 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1463 operand IMMOP to switch from SS to SI type instructions. */
1464
1465 void
1466 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1467 {
1468 int def = code == AND ? -1 : 0;
1469 HOST_WIDE_INT mask;
1470 int part;
1471
1472 gcc_assert (GET_CODE (*memop) == MEM);
1473 gcc_assert (!MEM_VOLATILE_P (*memop));
1474
1475 mask = s390_extract_part (*immop, QImode, def);
1476 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1477 gcc_assert (part >= 0);
1478
1479 *memop = adjust_address (*memop, QImode, part);
1480 *immop = gen_int_mode (mask, QImode);
1481 }
1482
1483
1484 /* How to allocate a 'struct machine_function'. */
1485
1486 static struct machine_function *
1487 s390_init_machine_status (void)
1488 {
1489 return ggc_alloc_cleared_machine_function ();
1490 }
1491
1492 /* Change optimizations to be performed, depending on the
1493 optimization level. */
1494
1495 static const struct default_options s390_option_optimization_table[] =
1496 {
1497 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
1498
1499 /* ??? There are apparently still problems with -fcaller-saves. */
1500 { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 },
1501
1502 /* Use MVCLE instructions to decrease code size if requested. */
1503 { OPT_LEVELS_SIZE, OPT_mmvcle, NULL, 1 },
1504
1505 { OPT_LEVELS_NONE, 0, NULL, 0 }
1506 };
1507
1508 /* Implement TARGET_OPTION_INIT_STRUCT. */
1509
1510 static void
1511 s390_option_init_struct (struct gcc_options *opts)
1512 {
1513 /* By default, always emit DWARF-2 unwind info. This allows debugging
1514 without maintaining a stack frame back-chain. */
1515 opts->x_flag_asynchronous_unwind_tables = 1;
1516 }
1517
1518 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1519 to the associated processor_type and processor_flags if so. */
1520
1521 static bool
1522 s390_handle_arch_option (const char *arg,
1523 enum processor_type *type,
1524 int *flags)
1525 {
1526 static struct pta
1527 {
1528 const char *const name; /* processor name or nickname. */
1529 const enum processor_type processor;
1530 const int flags; /* From enum processor_flags. */
1531 }
1532 const processor_alias_table[] =
1533 {
1534 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1535 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1536 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1537 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1538 | PF_LONG_DISPLACEMENT},
1539 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1540 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1541 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1542 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1543 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1544 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1545 {"z196", PROCESSOR_2817_Z196, PF_IEEE_FLOAT | PF_ZARCH
1546 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 },
1547 };
1548 size_t i;
1549
1550 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1551 if (strcmp (arg, processor_alias_table[i].name) == 0)
1552 {
1553 *type = processor_alias_table[i].processor;
1554 *flags = processor_alias_table[i].flags;
1555 return true;
1556 }
1557
1558 *type = PROCESSOR_max;
1559 *flags = 0;
1560 return false;
1561 }
1562
1563 /* Implement TARGET_HANDLE_OPTION. */
1564
1565 static bool
1566 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1567 {
1568 switch (code)
1569 {
1570 case OPT_march_:
1571 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1572
1573 case OPT_mstack_guard_:
1574 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1575 return false;
1576 if (exact_log2 (s390_stack_guard) == -1)
1577 error ("stack guard value must be an exact power of 2");
1578 return true;
1579
1580 case OPT_mstack_size_:
1581 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1582 return false;
1583 if (exact_log2 (s390_stack_size) == -1)
1584 error ("stack size must be an exact power of 2");
1585 return true;
1586
1587 case OPT_mtune_:
1588 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1589
1590 case OPT_mwarn_framesize_:
1591 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1592
1593 default:
1594 return true;
1595 }
1596 }
1597
1598 static void
1599 s390_option_override (void)
1600 {
1601 /* Set up function hooks. */
1602 init_machine_status = s390_init_machine_status;
1603
1604 /* Architecture mode defaults according to ABI. */
1605 if (!(target_flags_explicit & MASK_ZARCH))
1606 {
1607 if (TARGET_64BIT)
1608 target_flags |= MASK_ZARCH;
1609 else
1610 target_flags &= ~MASK_ZARCH;
1611 }
1612
1613 /* Determine processor architectural level. */
1614 if (!s390_arch_string)
1615 {
1616 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1617 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1618 }
1619
1620 /* This check is triggered when the user specified a wrong -march=
1621 string and prevents subsequent error messages from being
1622 issued. */
1623 if (s390_arch == PROCESSOR_max)
1624 return;
1625
1626 /* Determine processor to tune for. */
1627 if (s390_tune == PROCESSOR_max)
1628 {
1629 s390_tune = s390_arch;
1630 s390_tune_flags = s390_arch_flags;
1631 }
1632
1633 /* Sanity checks. */
1634 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1635 error ("z/Architecture mode not supported on %s", s390_arch_string);
1636 if (TARGET_64BIT && !TARGET_ZARCH)
1637 error ("64-bit ABI not supported in ESA/390 mode");
1638
1639 if (TARGET_HARD_DFP && !TARGET_DFP)
1640 {
1641 if (target_flags_explicit & MASK_HARD_DFP)
1642 {
1643 if (!TARGET_CPU_DFP)
1644 error ("Hardware decimal floating point instructions"
1645 " not available on %s", s390_arch_string);
1646 if (!TARGET_ZARCH)
1647 error ("Hardware decimal floating point instructions"
1648 " not available in ESA/390 mode");
1649 }
1650 else
1651 target_flags &= ~MASK_HARD_DFP;
1652 }
1653
1654 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1655 {
1656 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1657 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1658
1659 target_flags &= ~MASK_HARD_DFP;
1660 }
1661
1662 /* Set processor cost function. */
1663 switch (s390_tune)
1664 {
1665 case PROCESSOR_2084_Z990:
1666 s390_cost = &z990_cost;
1667 break;
1668 case PROCESSOR_2094_Z9_109:
1669 s390_cost = &z9_109_cost;
1670 break;
1671 case PROCESSOR_2097_Z10:
1672 s390_cost = &z10_cost;
1673 case PROCESSOR_2817_Z196:
1674 s390_cost = &z196_cost;
1675 break;
1676 default:
1677 s390_cost = &z900_cost;
1678 }
1679
1680 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1681 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1682 "in combination");
1683
1684 if (s390_stack_size)
1685 {
1686 if (s390_stack_guard >= s390_stack_size)
1687 error ("stack size must be greater than the stack guard value");
1688 else if (s390_stack_size > 1 << 16)
1689 error ("stack size must not be greater than 64k");
1690 }
1691 else if (s390_stack_guard)
1692 error ("-mstack-guard implies use of -mstack-size");
1693
1694 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1695 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1696 target_flags |= MASK_LONG_DOUBLE_128;
1697 #endif
1698
1699 if (s390_tune == PROCESSOR_2097_Z10
1700 || s390_tune == PROCESSOR_2817_Z196)
1701 {
1702 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1703 global_options.x_param_values,
1704 global_options_set.x_param_values);
1705 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1706 global_options.x_param_values,
1707 global_options_set.x_param_values);
1708 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1709 global_options.x_param_values,
1710 global_options_set.x_param_values);
1711 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1712 global_options.x_param_values,
1713 global_options_set.x_param_values);
1714 }
1715
1716 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1717 global_options.x_param_values,
1718 global_options_set.x_param_values);
1719 /* values for loop prefetching */
1720 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1721 global_options.x_param_values,
1722 global_options_set.x_param_values);
1723 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1724 global_options.x_param_values,
1725 global_options_set.x_param_values);
1726 /* s390 has more than 2 levels and the size is much larger. Since
1727 we are always running virtualized assume that we only get a small
1728 part of the caches above l1. */
1729 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1730 global_options.x_param_values,
1731 global_options_set.x_param_values);
1732 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1733 global_options.x_param_values,
1734 global_options_set.x_param_values);
1735 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1736 global_options.x_param_values,
1737 global_options_set.x_param_values);
1738
1739 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1740 requires the arch flags to be evaluated already. Since prefetching
1741 is beneficial on s390, we enable it if available. */
1742 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1743 flag_prefetch_loop_arrays = 1;
1744 }
1745
1746 /* Map for smallest class containing reg regno. */
1747
1748 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1749 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1750 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1751 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1752 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1753 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1754 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1755 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1756 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1757 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1758 ACCESS_REGS, ACCESS_REGS
1759 };
1760
1761 /* Return attribute type of insn. */
1762
1763 static enum attr_type
1764 s390_safe_attr_type (rtx insn)
1765 {
1766 if (recog_memoized (insn) >= 0)
1767 return get_attr_type (insn);
1768 else
1769 return TYPE_NONE;
1770 }
1771
1772 /* Return true if DISP is a valid short displacement. */
1773
1774 static bool
1775 s390_short_displacement (rtx disp)
1776 {
1777 /* No displacement is OK. */
1778 if (!disp)
1779 return true;
1780
1781 /* Without the long displacement facility we don't need to
1782 distingiush between long and short displacement. */
1783 if (!TARGET_LONG_DISPLACEMENT)
1784 return true;
1785
1786 /* Integer displacement in range. */
1787 if (GET_CODE (disp) == CONST_INT)
1788 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1789
1790 /* GOT offset is not OK, the GOT can be large. */
1791 if (GET_CODE (disp) == CONST
1792 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1793 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1794 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1795 return false;
1796
1797 /* All other symbolic constants are literal pool references,
1798 which are OK as the literal pool must be small. */
1799 if (GET_CODE (disp) == CONST)
1800 return true;
1801
1802 return false;
1803 }
1804
1805 /* Decompose a RTL expression ADDR for a memory address into
1806 its components, returned in OUT.
1807
1808 Returns false if ADDR is not a valid memory address, true
1809 otherwise. If OUT is NULL, don't return the components,
1810 but check for validity only.
1811
1812 Note: Only addresses in canonical form are recognized.
1813 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1814 canonical form so that they will be recognized. */
1815
1816 static int
1817 s390_decompose_address (rtx addr, struct s390_address *out)
1818 {
1819 HOST_WIDE_INT offset = 0;
1820 rtx base = NULL_RTX;
1821 rtx indx = NULL_RTX;
1822 rtx disp = NULL_RTX;
1823 rtx orig_disp;
1824 bool pointer = false;
1825 bool base_ptr = false;
1826 bool indx_ptr = false;
1827 bool literal_pool = false;
1828
1829 /* We may need to substitute the literal pool base register into the address
1830 below. However, at this point we do not know which register is going to
1831 be used as base, so we substitute the arg pointer register. This is going
1832 to be treated as holding a pointer below -- it shouldn't be used for any
1833 other purpose. */
1834 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1835
1836 /* Decompose address into base + index + displacement. */
1837
1838 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1839 base = addr;
1840
1841 else if (GET_CODE (addr) == PLUS)
1842 {
1843 rtx op0 = XEXP (addr, 0);
1844 rtx op1 = XEXP (addr, 1);
1845 enum rtx_code code0 = GET_CODE (op0);
1846 enum rtx_code code1 = GET_CODE (op1);
1847
1848 if (code0 == REG || code0 == UNSPEC)
1849 {
1850 if (code1 == REG || code1 == UNSPEC)
1851 {
1852 indx = op0; /* index + base */
1853 base = op1;
1854 }
1855
1856 else
1857 {
1858 base = op0; /* base + displacement */
1859 disp = op1;
1860 }
1861 }
1862
1863 else if (code0 == PLUS)
1864 {
1865 indx = XEXP (op0, 0); /* index + base + disp */
1866 base = XEXP (op0, 1);
1867 disp = op1;
1868 }
1869
1870 else
1871 {
1872 return false;
1873 }
1874 }
1875
1876 else
1877 disp = addr; /* displacement */
1878
1879 /* Extract integer part of displacement. */
1880 orig_disp = disp;
1881 if (disp)
1882 {
1883 if (GET_CODE (disp) == CONST_INT)
1884 {
1885 offset = INTVAL (disp);
1886 disp = NULL_RTX;
1887 }
1888 else if (GET_CODE (disp) == CONST
1889 && GET_CODE (XEXP (disp, 0)) == PLUS
1890 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1891 {
1892 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1893 disp = XEXP (XEXP (disp, 0), 0);
1894 }
1895 }
1896
1897 /* Strip off CONST here to avoid special case tests later. */
1898 if (disp && GET_CODE (disp) == CONST)
1899 disp = XEXP (disp, 0);
1900
1901 /* We can convert literal pool addresses to
1902 displacements by basing them off the base register. */
1903 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1904 {
1905 /* Either base or index must be free to hold the base register. */
1906 if (!base)
1907 base = fake_pool_base, literal_pool = true;
1908 else if (!indx)
1909 indx = fake_pool_base, literal_pool = true;
1910 else
1911 return false;
1912
1913 /* Mark up the displacement. */
1914 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1915 UNSPEC_LTREL_OFFSET);
1916 }
1917
1918 /* Validate base register. */
1919 if (base)
1920 {
1921 if (GET_CODE (base) == UNSPEC)
1922 switch (XINT (base, 1))
1923 {
1924 case UNSPEC_LTREF:
1925 if (!disp)
1926 disp = gen_rtx_UNSPEC (Pmode,
1927 gen_rtvec (1, XVECEXP (base, 0, 0)),
1928 UNSPEC_LTREL_OFFSET);
1929 else
1930 return false;
1931
1932 base = XVECEXP (base, 0, 1);
1933 break;
1934
1935 case UNSPEC_LTREL_BASE:
1936 if (XVECLEN (base, 0) == 1)
1937 base = fake_pool_base, literal_pool = true;
1938 else
1939 base = XVECEXP (base, 0, 1);
1940 break;
1941
1942 default:
1943 return false;
1944 }
1945
1946 if (!REG_P (base)
1947 || (GET_MODE (base) != SImode
1948 && GET_MODE (base) != Pmode))
1949 return false;
1950
1951 if (REGNO (base) == STACK_POINTER_REGNUM
1952 || REGNO (base) == FRAME_POINTER_REGNUM
1953 || ((reload_completed || reload_in_progress)
1954 && frame_pointer_needed
1955 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1956 || REGNO (base) == ARG_POINTER_REGNUM
1957 || (flag_pic
1958 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1959 pointer = base_ptr = true;
1960
1961 if ((reload_completed || reload_in_progress)
1962 && base == cfun->machine->base_reg)
1963 pointer = base_ptr = literal_pool = true;
1964 }
1965
1966 /* Validate index register. */
1967 if (indx)
1968 {
1969 if (GET_CODE (indx) == UNSPEC)
1970 switch (XINT (indx, 1))
1971 {
1972 case UNSPEC_LTREF:
1973 if (!disp)
1974 disp = gen_rtx_UNSPEC (Pmode,
1975 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1976 UNSPEC_LTREL_OFFSET);
1977 else
1978 return false;
1979
1980 indx = XVECEXP (indx, 0, 1);
1981 break;
1982
1983 case UNSPEC_LTREL_BASE:
1984 if (XVECLEN (indx, 0) == 1)
1985 indx = fake_pool_base, literal_pool = true;
1986 else
1987 indx = XVECEXP (indx, 0, 1);
1988 break;
1989
1990 default:
1991 return false;
1992 }
1993
1994 if (!REG_P (indx)
1995 || (GET_MODE (indx) != SImode
1996 && GET_MODE (indx) != Pmode))
1997 return false;
1998
1999 if (REGNO (indx) == STACK_POINTER_REGNUM
2000 || REGNO (indx) == FRAME_POINTER_REGNUM
2001 || ((reload_completed || reload_in_progress)
2002 && frame_pointer_needed
2003 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
2004 || REGNO (indx) == ARG_POINTER_REGNUM
2005 || (flag_pic
2006 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
2007 pointer = indx_ptr = true;
2008
2009 if ((reload_completed || reload_in_progress)
2010 && indx == cfun->machine->base_reg)
2011 pointer = indx_ptr = literal_pool = true;
2012 }
2013
2014 /* Prefer to use pointer as base, not index. */
2015 if (base && indx && !base_ptr
2016 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
2017 {
2018 rtx tmp = base;
2019 base = indx;
2020 indx = tmp;
2021 }
2022
2023 /* Validate displacement. */
2024 if (!disp)
2025 {
2026 /* If virtual registers are involved, the displacement will change later
2027 anyway as the virtual registers get eliminated. This could make a
2028 valid displacement invalid, but it is more likely to make an invalid
2029 displacement valid, because we sometimes access the register save area
2030 via negative offsets to one of those registers.
2031 Thus we don't check the displacement for validity here. If after
2032 elimination the displacement turns out to be invalid after all,
2033 this is fixed up by reload in any case. */
2034 if (base != arg_pointer_rtx
2035 && indx != arg_pointer_rtx
2036 && base != return_address_pointer_rtx
2037 && indx != return_address_pointer_rtx
2038 && base != frame_pointer_rtx
2039 && indx != frame_pointer_rtx
2040 && base != virtual_stack_vars_rtx
2041 && indx != virtual_stack_vars_rtx)
2042 if (!DISP_IN_RANGE (offset))
2043 return false;
2044 }
2045 else
2046 {
2047 /* All the special cases are pointers. */
2048 pointer = true;
2049
2050 /* In the small-PIC case, the linker converts @GOT
2051 and @GOTNTPOFF offsets to possible displacements. */
2052 if (GET_CODE (disp) == UNSPEC
2053 && (XINT (disp, 1) == UNSPEC_GOT
2054 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2055 && flag_pic == 1)
2056 {
2057 ;
2058 }
2059
2060 /* Accept pool label offsets. */
2061 else if (GET_CODE (disp) == UNSPEC
2062 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2063 ;
2064
2065 /* Accept literal pool references. */
2066 else if (GET_CODE (disp) == UNSPEC
2067 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2068 {
2069 orig_disp = gen_rtx_CONST (Pmode, disp);
2070 if (offset)
2071 {
2072 /* If we have an offset, make sure it does not
2073 exceed the size of the constant pool entry. */
2074 rtx sym = XVECEXP (disp, 0, 0);
2075 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2076 return false;
2077
2078 orig_disp = plus_constant (orig_disp, offset);
2079 }
2080 }
2081
2082 else
2083 return false;
2084 }
2085
2086 if (!base && !indx)
2087 pointer = true;
2088
2089 if (out)
2090 {
2091 out->base = base;
2092 out->indx = indx;
2093 out->disp = orig_disp;
2094 out->pointer = pointer;
2095 out->literal_pool = literal_pool;
2096 }
2097
2098 return true;
2099 }
2100
2101 /* Decompose a RTL expression OP for a shift count into its components,
2102 and return the base register in BASE and the offset in OFFSET.
2103
2104 Return true if OP is a valid shift count, false if not. */
2105
2106 bool
2107 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2108 {
2109 HOST_WIDE_INT off = 0;
2110
2111 /* We can have an integer constant, an address register,
2112 or a sum of the two. */
2113 if (GET_CODE (op) == CONST_INT)
2114 {
2115 off = INTVAL (op);
2116 op = NULL_RTX;
2117 }
2118 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2119 {
2120 off = INTVAL (XEXP (op, 1));
2121 op = XEXP (op, 0);
2122 }
2123 while (op && GET_CODE (op) == SUBREG)
2124 op = SUBREG_REG (op);
2125
2126 if (op && GET_CODE (op) != REG)
2127 return false;
2128
2129 if (offset)
2130 *offset = off;
2131 if (base)
2132 *base = op;
2133
2134 return true;
2135 }
2136
2137
2138 /* Return true if CODE is a valid address without index. */
2139
2140 bool
2141 s390_legitimate_address_without_index_p (rtx op)
2142 {
2143 struct s390_address addr;
2144
2145 if (!s390_decompose_address (XEXP (op, 0), &addr))
2146 return false;
2147 if (addr.indx)
2148 return false;
2149
2150 return true;
2151 }
2152
2153
2154 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2155 and return these parts in SYMREF and ADDEND. You can pass NULL in
2156 SYMREF and/or ADDEND if you are not interested in these values.
2157 Literal pool references are *not* considered symbol references. */
2158
2159 static bool
2160 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2161 {
2162 HOST_WIDE_INT tmpaddend = 0;
2163
2164 if (GET_CODE (addr) == CONST)
2165 addr = XEXP (addr, 0);
2166
2167 if (GET_CODE (addr) == PLUS)
2168 {
2169 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2170 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2171 && CONST_INT_P (XEXP (addr, 1)))
2172 {
2173 tmpaddend = INTVAL (XEXP (addr, 1));
2174 addr = XEXP (addr, 0);
2175 }
2176 else
2177 return false;
2178 }
2179 else
2180 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2181 return false;
2182
2183 if (symref)
2184 *symref = addr;
2185 if (addend)
2186 *addend = tmpaddend;
2187
2188 return true;
2189 }
2190
2191
2192 /* Return true if the address in OP is valid for constraint letter C
2193 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2194 pool MEMs should be accepted. Only the Q, R, S, T constraint
2195 letters are allowed for C. */
2196
2197 static int
2198 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2199 {
2200 struct s390_address addr;
2201 bool decomposed = false;
2202
2203 /* This check makes sure that no symbolic address (except literal
2204 pool references) are accepted by the R or T constraints. */
2205 if (s390_symref_operand_p (op, NULL, NULL))
2206 return 0;
2207
2208 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2209 if (!lit_pool_ok)
2210 {
2211 if (!s390_decompose_address (op, &addr))
2212 return 0;
2213 if (addr.literal_pool)
2214 return 0;
2215 decomposed = true;
2216 }
2217
2218 switch (c)
2219 {
2220 case 'Q': /* no index short displacement */
2221 if (!decomposed && !s390_decompose_address (op, &addr))
2222 return 0;
2223 if (addr.indx)
2224 return 0;
2225 if (!s390_short_displacement (addr.disp))
2226 return 0;
2227 break;
2228
2229 case 'R': /* with index short displacement */
2230 if (TARGET_LONG_DISPLACEMENT)
2231 {
2232 if (!decomposed && !s390_decompose_address (op, &addr))
2233 return 0;
2234 if (!s390_short_displacement (addr.disp))
2235 return 0;
2236 }
2237 /* Any invalid address here will be fixed up by reload,
2238 so accept it for the most generic constraint. */
2239 break;
2240
2241 case 'S': /* no index long displacement */
2242 if (!TARGET_LONG_DISPLACEMENT)
2243 return 0;
2244 if (!decomposed && !s390_decompose_address (op, &addr))
2245 return 0;
2246 if (addr.indx)
2247 return 0;
2248 if (s390_short_displacement (addr.disp))
2249 return 0;
2250 break;
2251
2252 case 'T': /* with index long displacement */
2253 if (!TARGET_LONG_DISPLACEMENT)
2254 return 0;
2255 /* Any invalid address here will be fixed up by reload,
2256 so accept it for the most generic constraint. */
2257 if ((decomposed || s390_decompose_address (op, &addr))
2258 && s390_short_displacement (addr.disp))
2259 return 0;
2260 break;
2261 default:
2262 return 0;
2263 }
2264 return 1;
2265 }
2266
2267
2268 /* Evaluates constraint strings described by the regular expression
2269 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2270 the constraint given in STR, or 0 else. */
2271
2272 int
2273 s390_mem_constraint (const char *str, rtx op)
2274 {
2275 char c = str[0];
2276
2277 switch (c)
2278 {
2279 case 'A':
2280 /* Check for offsettable variants of memory constraints. */
2281 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2282 return 0;
2283 if ((reload_completed || reload_in_progress)
2284 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2285 return 0;
2286 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2287 case 'B':
2288 /* Check for non-literal-pool variants of memory constraints. */
2289 if (!MEM_P (op))
2290 return 0;
2291 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2292 case 'Q':
2293 case 'R':
2294 case 'S':
2295 case 'T':
2296 if (GET_CODE (op) != MEM)
2297 return 0;
2298 return s390_check_qrst_address (c, XEXP (op, 0), true);
2299 case 'U':
2300 return (s390_check_qrst_address ('Q', op, true)
2301 || s390_check_qrst_address ('R', op, true));
2302 case 'W':
2303 return (s390_check_qrst_address ('S', op, true)
2304 || s390_check_qrst_address ('T', op, true));
2305 case 'Y':
2306 /* Simply check for the basic form of a shift count. Reload will
2307 take care of making sure we have a proper base register. */
2308 if (!s390_decompose_shift_count (op, NULL, NULL))
2309 return 0;
2310 break;
2311 case 'Z':
2312 return s390_check_qrst_address (str[1], op, true);
2313 default:
2314 return 0;
2315 }
2316 return 1;
2317 }
2318
2319
2320 /* Evaluates constraint strings starting with letter O. Input
2321 parameter C is the second letter following the "O" in the constraint
2322 string. Returns 1 if VALUE meets the respective constraint and 0
2323 otherwise. */
2324
2325 int
2326 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2327 {
2328 if (!TARGET_EXTIMM)
2329 return 0;
2330
2331 switch (c)
2332 {
2333 case 's':
2334 return trunc_int_for_mode (value, SImode) == value;
2335
2336 case 'p':
2337 return value == 0
2338 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2339
2340 case 'n':
2341 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2342
2343 default:
2344 gcc_unreachable ();
2345 }
2346 }
2347
2348
2349 /* Evaluates constraint strings starting with letter N. Parameter STR
2350 contains the letters following letter "N" in the constraint string.
2351 Returns true if VALUE matches the constraint. */
2352
2353 int
2354 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2355 {
2356 enum machine_mode mode, part_mode;
2357 int def;
2358 int part, part_goal;
2359
2360
2361 if (str[0] == 'x')
2362 part_goal = -1;
2363 else
2364 part_goal = str[0] - '0';
2365
2366 switch (str[1])
2367 {
2368 case 'Q':
2369 part_mode = QImode;
2370 break;
2371 case 'H':
2372 part_mode = HImode;
2373 break;
2374 case 'S':
2375 part_mode = SImode;
2376 break;
2377 default:
2378 return 0;
2379 }
2380
2381 switch (str[2])
2382 {
2383 case 'H':
2384 mode = HImode;
2385 break;
2386 case 'S':
2387 mode = SImode;
2388 break;
2389 case 'D':
2390 mode = DImode;
2391 break;
2392 default:
2393 return 0;
2394 }
2395
2396 switch (str[3])
2397 {
2398 case '0':
2399 def = 0;
2400 break;
2401 case 'F':
2402 def = -1;
2403 break;
2404 default:
2405 return 0;
2406 }
2407
2408 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2409 return 0;
2410
2411 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2412 if (part < 0)
2413 return 0;
2414 if (part_goal != -1 && part_goal != part)
2415 return 0;
2416
2417 return 1;
2418 }
2419
2420
2421 /* Returns true if the input parameter VALUE is a float zero. */
2422
2423 int
2424 s390_float_const_zero_p (rtx value)
2425 {
2426 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2427 && value == CONST0_RTX (GET_MODE (value)));
2428 }
2429
2430
2431 /* Compute a (partial) cost for rtx X. Return true if the complete
2432 cost has been computed, and false if subexpressions should be
2433 scanned. In either case, *TOTAL contains the cost result.
2434 CODE contains GET_CODE (x), OUTER_CODE contains the code
2435 of the superexpression of x. */
2436
2437 static bool
2438 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2439 bool speed ATTRIBUTE_UNUSED)
2440 {
2441 switch (code)
2442 {
2443 case CONST:
2444 case CONST_INT:
2445 case LABEL_REF:
2446 case SYMBOL_REF:
2447 case CONST_DOUBLE:
2448 case MEM:
2449 *total = 0;
2450 return true;
2451
2452 case ASHIFT:
2453 case ASHIFTRT:
2454 case LSHIFTRT:
2455 case ROTATE:
2456 case ROTATERT:
2457 case AND:
2458 case IOR:
2459 case XOR:
2460 case NEG:
2461 case NOT:
2462 *total = COSTS_N_INSNS (1);
2463 return false;
2464
2465 case PLUS:
2466 case MINUS:
2467 /* Check for multiply and add. */
2468 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2469 && GET_CODE (XEXP (x, 0)) == MULT
2470 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2471 {
2472 /* This is the multiply and add case. */
2473 if (GET_MODE (x) == DFmode)
2474 *total = s390_cost->madbr;
2475 else
2476 *total = s390_cost->maebr;
2477 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2478 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2479 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2480 return true; /* Do not do an additional recursive descent. */
2481 }
2482 *total = COSTS_N_INSNS (1);
2483 return false;
2484
2485 case MULT:
2486 switch (GET_MODE (x))
2487 {
2488 case SImode:
2489 {
2490 rtx left = XEXP (x, 0);
2491 rtx right = XEXP (x, 1);
2492 if (GET_CODE (right) == CONST_INT
2493 && CONST_OK_FOR_K (INTVAL (right)))
2494 *total = s390_cost->mhi;
2495 else if (GET_CODE (left) == SIGN_EXTEND)
2496 *total = s390_cost->mh;
2497 else
2498 *total = s390_cost->ms; /* msr, ms, msy */
2499 break;
2500 }
2501 case DImode:
2502 {
2503 rtx left = XEXP (x, 0);
2504 rtx right = XEXP (x, 1);
2505 if (TARGET_ZARCH)
2506 {
2507 if (GET_CODE (right) == CONST_INT
2508 && CONST_OK_FOR_K (INTVAL (right)))
2509 *total = s390_cost->mghi;
2510 else if (GET_CODE (left) == SIGN_EXTEND)
2511 *total = s390_cost->msgf;
2512 else
2513 *total = s390_cost->msg; /* msgr, msg */
2514 }
2515 else /* TARGET_31BIT */
2516 {
2517 if (GET_CODE (left) == SIGN_EXTEND
2518 && GET_CODE (right) == SIGN_EXTEND)
2519 /* mulsidi case: mr, m */
2520 *total = s390_cost->m;
2521 else if (GET_CODE (left) == ZERO_EXTEND
2522 && GET_CODE (right) == ZERO_EXTEND
2523 && TARGET_CPU_ZARCH)
2524 /* umulsidi case: ml, mlr */
2525 *total = s390_cost->ml;
2526 else
2527 /* Complex calculation is required. */
2528 *total = COSTS_N_INSNS (40);
2529 }
2530 break;
2531 }
2532 case SFmode:
2533 case DFmode:
2534 *total = s390_cost->mult_df;
2535 break;
2536 case TFmode:
2537 *total = s390_cost->mxbr;
2538 break;
2539 default:
2540 return false;
2541 }
2542 return false;
2543
2544 case UDIV:
2545 case UMOD:
2546 if (GET_MODE (x) == TImode) /* 128 bit division */
2547 *total = s390_cost->dlgr;
2548 else if (GET_MODE (x) == DImode)
2549 {
2550 rtx right = XEXP (x, 1);
2551 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2552 *total = s390_cost->dlr;
2553 else /* 64 by 64 bit division */
2554 *total = s390_cost->dlgr;
2555 }
2556 else if (GET_MODE (x) == SImode) /* 32 bit division */
2557 *total = s390_cost->dlr;
2558 return false;
2559
2560 case DIV:
2561 case MOD:
2562 if (GET_MODE (x) == DImode)
2563 {
2564 rtx right = XEXP (x, 1);
2565 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2566 if (TARGET_ZARCH)
2567 *total = s390_cost->dsgfr;
2568 else
2569 *total = s390_cost->dr;
2570 else /* 64 by 64 bit division */
2571 *total = s390_cost->dsgr;
2572 }
2573 else if (GET_MODE (x) == SImode) /* 32 bit division */
2574 *total = s390_cost->dlr;
2575 else if (GET_MODE (x) == SFmode)
2576 {
2577 *total = s390_cost->debr;
2578 }
2579 else if (GET_MODE (x) == DFmode)
2580 {
2581 *total = s390_cost->ddbr;
2582 }
2583 else if (GET_MODE (x) == TFmode)
2584 {
2585 *total = s390_cost->dxbr;
2586 }
2587 return false;
2588
2589 case SQRT:
2590 if (GET_MODE (x) == SFmode)
2591 *total = s390_cost->sqebr;
2592 else if (GET_MODE (x) == DFmode)
2593 *total = s390_cost->sqdbr;
2594 else /* TFmode */
2595 *total = s390_cost->sqxbr;
2596 return false;
2597
2598 case SIGN_EXTEND:
2599 case ZERO_EXTEND:
2600 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2601 || outer_code == PLUS || outer_code == MINUS
2602 || outer_code == COMPARE)
2603 *total = 0;
2604 return false;
2605
2606 case COMPARE:
2607 *total = COSTS_N_INSNS (1);
2608 if (GET_CODE (XEXP (x, 0)) == AND
2609 && GET_CODE (XEXP (x, 1)) == CONST_INT
2610 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2611 {
2612 rtx op0 = XEXP (XEXP (x, 0), 0);
2613 rtx op1 = XEXP (XEXP (x, 0), 1);
2614 rtx op2 = XEXP (x, 1);
2615
2616 if (memory_operand (op0, GET_MODE (op0))
2617 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2618 return true;
2619 if (register_operand (op0, GET_MODE (op0))
2620 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2621 return true;
2622 }
2623 return false;
2624
2625 default:
2626 return false;
2627 }
2628 }
2629
2630 /* Return the cost of an address rtx ADDR. */
2631
2632 static int
2633 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2634 {
2635 struct s390_address ad;
2636 if (!s390_decompose_address (addr, &ad))
2637 return 1000;
2638
2639 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2640 }
2641
2642 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2643 otherwise return 0. */
2644
2645 int
2646 tls_symbolic_operand (rtx op)
2647 {
2648 if (GET_CODE (op) != SYMBOL_REF)
2649 return 0;
2650 return SYMBOL_REF_TLS_MODEL (op);
2651 }
2652 \f
2653 /* Split DImode access register reference REG (on 64-bit) into its constituent
2654 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2655 gen_highpart cannot be used as they assume all registers are word-sized,
2656 while our access registers have only half that size. */
2657
2658 void
2659 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2660 {
2661 gcc_assert (TARGET_64BIT);
2662 gcc_assert (ACCESS_REG_P (reg));
2663 gcc_assert (GET_MODE (reg) == DImode);
2664 gcc_assert (!(REGNO (reg) & 1));
2665
2666 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2667 *hi = gen_rtx_REG (SImode, REGNO (reg));
2668 }
2669
2670 /* Return true if OP contains a symbol reference */
2671
2672 bool
2673 symbolic_reference_mentioned_p (rtx op)
2674 {
2675 const char *fmt;
2676 int i;
2677
2678 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2679 return 1;
2680
2681 fmt = GET_RTX_FORMAT (GET_CODE (op));
2682 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2683 {
2684 if (fmt[i] == 'E')
2685 {
2686 int j;
2687
2688 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2689 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2690 return 1;
2691 }
2692
2693 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2694 return 1;
2695 }
2696
2697 return 0;
2698 }
2699
2700 /* Return true if OP contains a reference to a thread-local symbol. */
2701
2702 bool
2703 tls_symbolic_reference_mentioned_p (rtx op)
2704 {
2705 const char *fmt;
2706 int i;
2707
2708 if (GET_CODE (op) == SYMBOL_REF)
2709 return tls_symbolic_operand (op);
2710
2711 fmt = GET_RTX_FORMAT (GET_CODE (op));
2712 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2713 {
2714 if (fmt[i] == 'E')
2715 {
2716 int j;
2717
2718 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2719 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2720 return true;
2721 }
2722
2723 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2724 return true;
2725 }
2726
2727 return false;
2728 }
2729
2730
2731 /* Return true if OP is a legitimate general operand when
2732 generating PIC code. It is given that flag_pic is on
2733 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2734
2735 int
2736 legitimate_pic_operand_p (rtx op)
2737 {
2738 /* Accept all non-symbolic constants. */
2739 if (!SYMBOLIC_CONST (op))
2740 return 1;
2741
2742 /* Reject everything else; must be handled
2743 via emit_symbolic_move. */
2744 return 0;
2745 }
2746
2747 /* Returns true if the constant value OP is a legitimate general operand.
2748 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2749
2750 int
2751 legitimate_constant_p (rtx op)
2752 {
2753 /* Accept all non-symbolic constants. */
2754 if (!SYMBOLIC_CONST (op))
2755 return 1;
2756
2757 /* Accept immediate LARL operands. */
2758 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2759 return 1;
2760
2761 /* Thread-local symbols are never legal constants. This is
2762 so that emit_call knows that computing such addresses
2763 might require a function call. */
2764 if (TLS_SYMBOLIC_CONST (op))
2765 return 0;
2766
2767 /* In the PIC case, symbolic constants must *not* be
2768 forced into the literal pool. We accept them here,
2769 so that they will be handled by emit_symbolic_move. */
2770 if (flag_pic)
2771 return 1;
2772
2773 /* All remaining non-PIC symbolic constants are
2774 forced into the literal pool. */
2775 return 0;
2776 }
2777
2778 /* Determine if it's legal to put X into the constant pool. This
2779 is not possible if X contains the address of a symbol that is
2780 not constant (TLS) or not known at final link time (PIC). */
2781
2782 static bool
2783 s390_cannot_force_const_mem (rtx x)
2784 {
2785 switch (GET_CODE (x))
2786 {
2787 case CONST_INT:
2788 case CONST_DOUBLE:
2789 /* Accept all non-symbolic constants. */
2790 return false;
2791
2792 case LABEL_REF:
2793 /* Labels are OK iff we are non-PIC. */
2794 return flag_pic != 0;
2795
2796 case SYMBOL_REF:
2797 /* 'Naked' TLS symbol references are never OK,
2798 non-TLS symbols are OK iff we are non-PIC. */
2799 if (tls_symbolic_operand (x))
2800 return true;
2801 else
2802 return flag_pic != 0;
2803
2804 case CONST:
2805 return s390_cannot_force_const_mem (XEXP (x, 0));
2806 case PLUS:
2807 case MINUS:
2808 return s390_cannot_force_const_mem (XEXP (x, 0))
2809 || s390_cannot_force_const_mem (XEXP (x, 1));
2810
2811 case UNSPEC:
2812 switch (XINT (x, 1))
2813 {
2814 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2815 case UNSPEC_LTREL_OFFSET:
2816 case UNSPEC_GOT:
2817 case UNSPEC_GOTOFF:
2818 case UNSPEC_PLTOFF:
2819 case UNSPEC_TLSGD:
2820 case UNSPEC_TLSLDM:
2821 case UNSPEC_NTPOFF:
2822 case UNSPEC_DTPOFF:
2823 case UNSPEC_GOTNTPOFF:
2824 case UNSPEC_INDNTPOFF:
2825 return false;
2826
2827 /* If the literal pool shares the code section, be put
2828 execute template placeholders into the pool as well. */
2829 case UNSPEC_INSN:
2830 return TARGET_CPU_ZARCH;
2831
2832 default:
2833 return true;
2834 }
2835 break;
2836
2837 default:
2838 gcc_unreachable ();
2839 }
2840 }
2841
2842 /* Returns true if the constant value OP is a legitimate general
2843 operand during and after reload. The difference to
2844 legitimate_constant_p is that this function will not accept
2845 a constant that would need to be forced to the literal pool
2846 before it can be used as operand.
2847 This function accepts all constants which can be loaded directly
2848 into a GPR. */
2849
2850 bool
2851 legitimate_reload_constant_p (rtx op)
2852 {
2853 /* Accept la(y) operands. */
2854 if (GET_CODE (op) == CONST_INT
2855 && DISP_IN_RANGE (INTVAL (op)))
2856 return true;
2857
2858 /* Accept l(g)hi/l(g)fi operands. */
2859 if (GET_CODE (op) == CONST_INT
2860 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2861 return true;
2862
2863 /* Accept lliXX operands. */
2864 if (TARGET_ZARCH
2865 && GET_CODE (op) == CONST_INT
2866 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2867 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2868 return true;
2869
2870 if (TARGET_EXTIMM
2871 && GET_CODE (op) == CONST_INT
2872 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2873 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2874 return true;
2875
2876 /* Accept larl operands. */
2877 if (TARGET_CPU_ZARCH
2878 && larl_operand (op, VOIDmode))
2879 return true;
2880
2881 /* Accept floating-point zero operands that fit into a single GPR. */
2882 if (GET_CODE (op) == CONST_DOUBLE
2883 && s390_float_const_zero_p (op)
2884 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2885 return true;
2886
2887 /* Accept double-word operands that can be split. */
2888 if (GET_CODE (op) == CONST_INT
2889 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2890 {
2891 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2892 rtx hi = operand_subword (op, 0, 0, dword_mode);
2893 rtx lo = operand_subword (op, 1, 0, dword_mode);
2894 return legitimate_reload_constant_p (hi)
2895 && legitimate_reload_constant_p (lo);
2896 }
2897
2898 /* Everything else cannot be handled without reload. */
2899 return false;
2900 }
2901
2902 /* Returns true if the constant value OP is a legitimate fp operand
2903 during and after reload.
2904 This function accepts all constants which can be loaded directly
2905 into an FPR. */
2906
2907 static bool
2908 legitimate_reload_fp_constant_p (rtx op)
2909 {
2910 /* Accept floating-point zero operands if the load zero instruction
2911 can be used. */
2912 if (TARGET_Z196
2913 && GET_CODE (op) == CONST_DOUBLE
2914 && s390_float_const_zero_p (op))
2915 return true;
2916
2917 return false;
2918 }
2919
2920 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2921 return the class of reg to actually use. */
2922
2923 enum reg_class
2924 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2925 {
2926 switch (GET_CODE (op))
2927 {
2928 /* Constants we cannot reload into general registers
2929 must be forced into the literal pool. */
2930 case CONST_DOUBLE:
2931 case CONST_INT:
2932 if (reg_class_subset_p (GENERAL_REGS, rclass)
2933 && legitimate_reload_constant_p (op))
2934 return GENERAL_REGS;
2935 else if (reg_class_subset_p (ADDR_REGS, rclass)
2936 && legitimate_reload_constant_p (op))
2937 return ADDR_REGS;
2938 else if (reg_class_subset_p (FP_REGS, rclass)
2939 && legitimate_reload_fp_constant_p (op))
2940 return FP_REGS;
2941 return NO_REGS;
2942
2943 /* If a symbolic constant or a PLUS is reloaded,
2944 it is most likely being used as an address, so
2945 prefer ADDR_REGS. If 'class' is not a superset
2946 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2947 case PLUS:
2948 case LABEL_REF:
2949 case SYMBOL_REF:
2950 case CONST:
2951 if (reg_class_subset_p (ADDR_REGS, rclass))
2952 return ADDR_REGS;
2953 else
2954 return NO_REGS;
2955
2956 default:
2957 break;
2958 }
2959
2960 return rclass;
2961 }
2962
2963 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2964 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2965 aligned. */
2966
2967 bool
2968 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2969 {
2970 HOST_WIDE_INT addend;
2971 rtx symref;
2972
2973 if (!s390_symref_operand_p (addr, &symref, &addend))
2974 return false;
2975
2976 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2977 && !(addend & (alignment - 1)));
2978 }
2979
2980 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2981 operand SCRATCH is used to reload the even part of the address and
2982 adding one. */
2983
2984 void
2985 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2986 {
2987 HOST_WIDE_INT addend;
2988 rtx symref;
2989
2990 if (!s390_symref_operand_p (addr, &symref, &addend))
2991 gcc_unreachable ();
2992
2993 if (!(addend & 1))
2994 /* Easy case. The addend is even so larl will do fine. */
2995 emit_move_insn (reg, addr);
2996 else
2997 {
2998 /* We can leave the scratch register untouched if the target
2999 register is a valid base register. */
3000 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3001 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3002 scratch = reg;
3003
3004 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3005 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3006
3007 if (addend != 1)
3008 emit_move_insn (scratch,
3009 gen_rtx_CONST (Pmode,
3010 gen_rtx_PLUS (Pmode, symref,
3011 GEN_INT (addend - 1))));
3012 else
3013 emit_move_insn (scratch, symref);
3014
3015 /* Increment the address using la in order to avoid clobbering cc. */
3016 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3017 }
3018 }
3019
3020 /* Generate what is necessary to move between REG and MEM using
3021 SCRATCH. The direction is given by TOMEM. */
3022
3023 void
3024 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3025 {
3026 /* Reload might have pulled a constant out of the literal pool.
3027 Force it back in. */
3028 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3029 || GET_CODE (mem) == CONST)
3030 mem = force_const_mem (GET_MODE (reg), mem);
3031
3032 gcc_assert (MEM_P (mem));
3033
3034 /* For a load from memory we can leave the scratch register
3035 untouched if the target register is a valid base register. */
3036 if (!tomem
3037 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3038 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3039 && GET_MODE (reg) == GET_MODE (scratch))
3040 scratch = reg;
3041
3042 /* Load address into scratch register. Since we can't have a
3043 secondary reload for a secondary reload we have to cover the case
3044 where larl would need a secondary reload here as well. */
3045 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3046
3047 /* Now we can use a standard load/store to do the move. */
3048 if (tomem)
3049 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3050 else
3051 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3052 }
3053
3054 /* Inform reload about cases where moving X with a mode MODE to a register in
3055 RCLASS requires an extra scratch or immediate register. Return the class
3056 needed for the immediate register. */
3057
3058 static reg_class_t
3059 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3060 enum machine_mode mode, secondary_reload_info *sri)
3061 {
3062 enum reg_class rclass = (enum reg_class) rclass_i;
3063
3064 /* Intermediate register needed. */
3065 if (reg_classes_intersect_p (CC_REGS, rclass))
3066 return GENERAL_REGS;
3067
3068 if (TARGET_Z10)
3069 {
3070 /* On z10 several optimizer steps may generate larl operands with
3071 an odd addend. */
3072 if (in_p
3073 && s390_symref_operand_p (x, NULL, NULL)
3074 && mode == Pmode
3075 && !s390_check_symref_alignment (x, 2))
3076 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3077 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3078
3079 /* On z10 we need a scratch register when moving QI, TI or floating
3080 point mode values from or to a memory location with a SYMBOL_REF
3081 or if the symref addend of a SI or DI move is not aligned to the
3082 width of the access. */
3083 if (MEM_P (x)
3084 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3085 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3086 || (!TARGET_ZARCH && mode == DImode)
3087 || ((mode == HImode || mode == SImode || mode == DImode)
3088 && (!s390_check_symref_alignment (XEXP (x, 0),
3089 GET_MODE_SIZE (mode))))))
3090 {
3091 #define __SECONDARY_RELOAD_CASE(M,m) \
3092 case M##mode: \
3093 if (TARGET_64BIT) \
3094 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3095 CODE_FOR_reload##m##di_tomem_z10; \
3096 else \
3097 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3098 CODE_FOR_reload##m##si_tomem_z10; \
3099 break;
3100
3101 switch (GET_MODE (x))
3102 {
3103 __SECONDARY_RELOAD_CASE (QI, qi);
3104 __SECONDARY_RELOAD_CASE (HI, hi);
3105 __SECONDARY_RELOAD_CASE (SI, si);
3106 __SECONDARY_RELOAD_CASE (DI, di);
3107 __SECONDARY_RELOAD_CASE (TI, ti);
3108 __SECONDARY_RELOAD_CASE (SF, sf);
3109 __SECONDARY_RELOAD_CASE (DF, df);
3110 __SECONDARY_RELOAD_CASE (TF, tf);
3111 __SECONDARY_RELOAD_CASE (SD, sd);
3112 __SECONDARY_RELOAD_CASE (DD, dd);
3113 __SECONDARY_RELOAD_CASE (TD, td);
3114
3115 default:
3116 gcc_unreachable ();
3117 }
3118 #undef __SECONDARY_RELOAD_CASE
3119 }
3120 }
3121
3122 /* We need a scratch register when loading a PLUS expression which
3123 is not a legitimate operand of the LOAD ADDRESS instruction. */
3124 if (in_p && s390_plus_operand (x, mode))
3125 sri->icode = (TARGET_64BIT ?
3126 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3127
3128 /* Performing a multiword move from or to memory we have to make sure the
3129 second chunk in memory is addressable without causing a displacement
3130 overflow. If that would be the case we calculate the address in
3131 a scratch register. */
3132 if (MEM_P (x)
3133 && GET_CODE (XEXP (x, 0)) == PLUS
3134 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3135 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3136 + GET_MODE_SIZE (mode) - 1))
3137 {
3138 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3139 in a s_operand address since we may fallback to lm/stm. So we only
3140 have to care about overflows in the b+i+d case. */
3141 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3142 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3143 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3144 /* For FP_REGS no lm/stm is available so this check is triggered
3145 for displacement overflows in b+i+d and b+d like addresses. */
3146 || (reg_classes_intersect_p (FP_REGS, rclass)
3147 && s390_class_max_nregs (FP_REGS, mode) > 1))
3148 {
3149 if (in_p)
3150 sri->icode = (TARGET_64BIT ?
3151 CODE_FOR_reloaddi_nonoffmem_in :
3152 CODE_FOR_reloadsi_nonoffmem_in);
3153 else
3154 sri->icode = (TARGET_64BIT ?
3155 CODE_FOR_reloaddi_nonoffmem_out :
3156 CODE_FOR_reloadsi_nonoffmem_out);
3157 }
3158 }
3159
3160 /* A scratch address register is needed when a symbolic constant is
3161 copied to r0 compiling with -fPIC. In other cases the target
3162 register might be used as temporary (see legitimize_pic_address). */
3163 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3164 sri->icode = (TARGET_64BIT ?
3165 CODE_FOR_reloaddi_PIC_addr :
3166 CODE_FOR_reloadsi_PIC_addr);
3167
3168 /* Either scratch or no register needed. */
3169 return NO_REGS;
3170 }
3171
3172 /* Generate code to load SRC, which is PLUS that is not a
3173 legitimate operand for the LA instruction, into TARGET.
3174 SCRATCH may be used as scratch register. */
3175
3176 void
3177 s390_expand_plus_operand (rtx target, rtx src,
3178 rtx scratch)
3179 {
3180 rtx sum1, sum2;
3181 struct s390_address ad;
3182
3183 /* src must be a PLUS; get its two operands. */
3184 gcc_assert (GET_CODE (src) == PLUS);
3185 gcc_assert (GET_MODE (src) == Pmode);
3186
3187 /* Check if any of the two operands is already scheduled
3188 for replacement by reload. This can happen e.g. when
3189 float registers occur in an address. */
3190 sum1 = find_replacement (&XEXP (src, 0));
3191 sum2 = find_replacement (&XEXP (src, 1));
3192 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3193
3194 /* If the address is already strictly valid, there's nothing to do. */
3195 if (!s390_decompose_address (src, &ad)
3196 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3197 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3198 {
3199 /* Otherwise, one of the operands cannot be an address register;
3200 we reload its value into the scratch register. */
3201 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3202 {
3203 emit_move_insn (scratch, sum1);
3204 sum1 = scratch;
3205 }
3206 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3207 {
3208 emit_move_insn (scratch, sum2);
3209 sum2 = scratch;
3210 }
3211
3212 /* According to the way these invalid addresses are generated
3213 in reload.c, it should never happen (at least on s390) that
3214 *neither* of the PLUS components, after find_replacements
3215 was applied, is an address register. */
3216 if (sum1 == scratch && sum2 == scratch)
3217 {
3218 debug_rtx (src);
3219 gcc_unreachable ();
3220 }
3221
3222 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3223 }
3224
3225 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3226 is only ever performed on addresses, so we can mark the
3227 sum as legitimate for LA in any case. */
3228 s390_load_address (target, src);
3229 }
3230
3231
3232 /* Return true if ADDR is a valid memory address.
3233 STRICT specifies whether strict register checking applies. */
3234
3235 static bool
3236 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3237 {
3238 struct s390_address ad;
3239
3240 if (TARGET_Z10
3241 && larl_operand (addr, VOIDmode)
3242 && (mode == VOIDmode
3243 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3244 return true;
3245
3246 if (!s390_decompose_address (addr, &ad))
3247 return false;
3248
3249 if (strict)
3250 {
3251 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3252 return false;
3253
3254 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3255 return false;
3256 }
3257 else
3258 {
3259 if (ad.base
3260 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3261 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3262 return false;
3263
3264 if (ad.indx
3265 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3266 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3267 return false;
3268 }
3269 return true;
3270 }
3271
3272 /* Return true if OP is a valid operand for the LA instruction.
3273 In 31-bit, we need to prove that the result is used as an
3274 address, as LA performs only a 31-bit addition. */
3275
3276 bool
3277 legitimate_la_operand_p (rtx op)
3278 {
3279 struct s390_address addr;
3280 if (!s390_decompose_address (op, &addr))
3281 return false;
3282
3283 return (TARGET_64BIT || addr.pointer);
3284 }
3285
3286 /* Return true if it is valid *and* preferable to use LA to
3287 compute the sum of OP1 and OP2. */
3288
3289 bool
3290 preferred_la_operand_p (rtx op1, rtx op2)
3291 {
3292 struct s390_address addr;
3293
3294 if (op2 != const0_rtx)
3295 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3296
3297 if (!s390_decompose_address (op1, &addr))
3298 return false;
3299 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3300 return false;
3301 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3302 return false;
3303
3304 /* Avoid LA instructions with index register on z196; it is
3305 preferable to use regular add instructions when possible. */
3306 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3307 return false;
3308
3309 if (!TARGET_64BIT && !addr.pointer)
3310 return false;
3311
3312 if (addr.pointer)
3313 return true;
3314
3315 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3316 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3317 return true;
3318
3319 return false;
3320 }
3321
3322 /* Emit a forced load-address operation to load SRC into DST.
3323 This will use the LOAD ADDRESS instruction even in situations
3324 where legitimate_la_operand_p (SRC) returns false. */
3325
3326 void
3327 s390_load_address (rtx dst, rtx src)
3328 {
3329 if (TARGET_64BIT)
3330 emit_move_insn (dst, src);
3331 else
3332 emit_insn (gen_force_la_31 (dst, src));
3333 }
3334
3335 /* Return a legitimate reference for ORIG (an address) using the
3336 register REG. If REG is 0, a new pseudo is generated.
3337
3338 There are two types of references that must be handled:
3339
3340 1. Global data references must load the address from the GOT, via
3341 the PIC reg. An insn is emitted to do this load, and the reg is
3342 returned.
3343
3344 2. Static data references, constant pool addresses, and code labels
3345 compute the address as an offset from the GOT, whose base is in
3346 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3347 differentiate them from global data objects. The returned
3348 address is the PIC reg + an unspec constant.
3349
3350 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3351 reg also appears in the address. */
3352
3353 rtx
3354 legitimize_pic_address (rtx orig, rtx reg)
3355 {
3356 rtx addr = orig;
3357 rtx new_rtx = orig;
3358 rtx base;
3359
3360 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3361
3362 if (GET_CODE (addr) == LABEL_REF
3363 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3364 {
3365 /* This is a local symbol. */
3366 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3367 {
3368 /* Access local symbols PC-relative via LARL.
3369 This is the same as in the non-PIC case, so it is
3370 handled automatically ... */
3371 }
3372 else
3373 {
3374 /* Access local symbols relative to the GOT. */
3375
3376 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3377
3378 if (reload_in_progress || reload_completed)
3379 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3380
3381 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3382 addr = gen_rtx_CONST (Pmode, addr);
3383 addr = force_const_mem (Pmode, addr);
3384 emit_move_insn (temp, addr);
3385
3386 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3387 if (reg != 0)
3388 {
3389 s390_load_address (reg, new_rtx);
3390 new_rtx = reg;
3391 }
3392 }
3393 }
3394 else if (GET_CODE (addr) == SYMBOL_REF)
3395 {
3396 if (reg == 0)
3397 reg = gen_reg_rtx (Pmode);
3398
3399 if (flag_pic == 1)
3400 {
3401 /* Assume GOT offset < 4k. This is handled the same way
3402 in both 31- and 64-bit code (@GOT). */
3403
3404 if (reload_in_progress || reload_completed)
3405 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3406
3407 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3408 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3409 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3410 new_rtx = gen_const_mem (Pmode, new_rtx);
3411 emit_move_insn (reg, new_rtx);
3412 new_rtx = reg;
3413 }
3414 else if (TARGET_CPU_ZARCH)
3415 {
3416 /* If the GOT offset might be >= 4k, we determine the position
3417 of the GOT entry via a PC-relative LARL (@GOTENT). */
3418
3419 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3420
3421 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3422 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3423
3424 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3425 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3426 emit_move_insn (temp, new_rtx);
3427
3428 new_rtx = gen_const_mem (Pmode, temp);
3429 emit_move_insn (reg, new_rtx);
3430 new_rtx = reg;
3431 }
3432 else
3433 {
3434 /* If the GOT offset might be >= 4k, we have to load it
3435 from the literal pool (@GOT). */
3436
3437 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3438
3439 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3440 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3441
3442 if (reload_in_progress || reload_completed)
3443 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3444
3445 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3446 addr = gen_rtx_CONST (Pmode, addr);
3447 addr = force_const_mem (Pmode, addr);
3448 emit_move_insn (temp, addr);
3449
3450 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3451 new_rtx = gen_const_mem (Pmode, new_rtx);
3452 emit_move_insn (reg, new_rtx);
3453 new_rtx = reg;
3454 }
3455 }
3456 else
3457 {
3458 if (GET_CODE (addr) == CONST)
3459 {
3460 addr = XEXP (addr, 0);
3461 if (GET_CODE (addr) == UNSPEC)
3462 {
3463 gcc_assert (XVECLEN (addr, 0) == 1);
3464 switch (XINT (addr, 1))
3465 {
3466 /* If someone moved a GOT-relative UNSPEC
3467 out of the literal pool, force them back in. */
3468 case UNSPEC_GOTOFF:
3469 case UNSPEC_PLTOFF:
3470 new_rtx = force_const_mem (Pmode, orig);
3471 break;
3472
3473 /* @GOT is OK as is if small. */
3474 case UNSPEC_GOT:
3475 if (flag_pic == 2)
3476 new_rtx = force_const_mem (Pmode, orig);
3477 break;
3478
3479 /* @GOTENT is OK as is. */
3480 case UNSPEC_GOTENT:
3481 break;
3482
3483 /* @PLT is OK as is on 64-bit, must be converted to
3484 GOT-relative @PLTOFF on 31-bit. */
3485 case UNSPEC_PLT:
3486 if (!TARGET_CPU_ZARCH)
3487 {
3488 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3489
3490 if (reload_in_progress || reload_completed)
3491 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3492
3493 addr = XVECEXP (addr, 0, 0);
3494 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3495 UNSPEC_PLTOFF);
3496 addr = gen_rtx_CONST (Pmode, addr);
3497 addr = force_const_mem (Pmode, addr);
3498 emit_move_insn (temp, addr);
3499
3500 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3501 if (reg != 0)
3502 {
3503 s390_load_address (reg, new_rtx);
3504 new_rtx = reg;
3505 }
3506 }
3507 break;
3508
3509 /* Everything else cannot happen. */
3510 default:
3511 gcc_unreachable ();
3512 }
3513 }
3514 else
3515 gcc_assert (GET_CODE (addr) == PLUS);
3516 }
3517 if (GET_CODE (addr) == PLUS)
3518 {
3519 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3520
3521 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3522 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3523
3524 /* Check first to see if this is a constant offset
3525 from a local symbol reference. */
3526 if ((GET_CODE (op0) == LABEL_REF
3527 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3528 && GET_CODE (op1) == CONST_INT)
3529 {
3530 if (TARGET_CPU_ZARCH
3531 && larl_operand (op0, VOIDmode)
3532 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3533 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3534 {
3535 if (INTVAL (op1) & 1)
3536 {
3537 /* LARL can't handle odd offsets, so emit a
3538 pair of LARL and LA. */
3539 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3540
3541 if (!DISP_IN_RANGE (INTVAL (op1)))
3542 {
3543 HOST_WIDE_INT even = INTVAL (op1) - 1;
3544 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3545 op0 = gen_rtx_CONST (Pmode, op0);
3546 op1 = const1_rtx;
3547 }
3548
3549 emit_move_insn (temp, op0);
3550 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3551
3552 if (reg != 0)
3553 {
3554 s390_load_address (reg, new_rtx);
3555 new_rtx = reg;
3556 }
3557 }
3558 else
3559 {
3560 /* If the offset is even, we can just use LARL.
3561 This will happen automatically. */
3562 }
3563 }
3564 else
3565 {
3566 /* Access local symbols relative to the GOT. */
3567
3568 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3569
3570 if (reload_in_progress || reload_completed)
3571 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3572
3573 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3574 UNSPEC_GOTOFF);
3575 addr = gen_rtx_PLUS (Pmode, addr, op1);
3576 addr = gen_rtx_CONST (Pmode, addr);
3577 addr = force_const_mem (Pmode, addr);
3578 emit_move_insn (temp, addr);
3579
3580 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3581 if (reg != 0)
3582 {
3583 s390_load_address (reg, new_rtx);
3584 new_rtx = reg;
3585 }
3586 }
3587 }
3588
3589 /* Now, check whether it is a GOT relative symbol plus offset
3590 that was pulled out of the literal pool. Force it back in. */
3591
3592 else if (GET_CODE (op0) == UNSPEC
3593 && GET_CODE (op1) == CONST_INT
3594 && XINT (op0, 1) == UNSPEC_GOTOFF)
3595 {
3596 gcc_assert (XVECLEN (op0, 0) == 1);
3597
3598 new_rtx = force_const_mem (Pmode, orig);
3599 }
3600
3601 /* Otherwise, compute the sum. */
3602 else
3603 {
3604 base = legitimize_pic_address (XEXP (addr, 0), reg);
3605 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3606 base == reg ? NULL_RTX : reg);
3607 if (GET_CODE (new_rtx) == CONST_INT)
3608 new_rtx = plus_constant (base, INTVAL (new_rtx));
3609 else
3610 {
3611 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3612 {
3613 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3614 new_rtx = XEXP (new_rtx, 1);
3615 }
3616 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3617 }
3618
3619 if (GET_CODE (new_rtx) == CONST)
3620 new_rtx = XEXP (new_rtx, 0);
3621 new_rtx = force_operand (new_rtx, 0);
3622 }
3623 }
3624 }
3625 return new_rtx;
3626 }
3627
3628 /* Load the thread pointer into a register. */
3629
3630 rtx
3631 s390_get_thread_pointer (void)
3632 {
3633 rtx tp = gen_reg_rtx (Pmode);
3634
3635 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3636 mark_reg_pointer (tp, BITS_PER_WORD);
3637
3638 return tp;
3639 }
3640
3641 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3642 in s390_tls_symbol which always refers to __tls_get_offset.
3643 The returned offset is written to RESULT_REG and an USE rtx is
3644 generated for TLS_CALL. */
3645
3646 static GTY(()) rtx s390_tls_symbol;
3647
3648 static void
3649 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3650 {
3651 rtx insn;
3652
3653 gcc_assert (flag_pic);
3654
3655 if (!s390_tls_symbol)
3656 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3657
3658 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3659 gen_rtx_REG (Pmode, RETURN_REGNUM));
3660
3661 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3662 RTL_CONST_CALL_P (insn) = 1;
3663 }
3664
3665 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3666 this (thread-local) address. REG may be used as temporary. */
3667
3668 static rtx
3669 legitimize_tls_address (rtx addr, rtx reg)
3670 {
3671 rtx new_rtx, tls_call, temp, base, r2, insn;
3672
3673 if (GET_CODE (addr) == SYMBOL_REF)
3674 switch (tls_symbolic_operand (addr))
3675 {
3676 case TLS_MODEL_GLOBAL_DYNAMIC:
3677 start_sequence ();
3678 r2 = gen_rtx_REG (Pmode, 2);
3679 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3680 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3681 new_rtx = force_const_mem (Pmode, new_rtx);
3682 emit_move_insn (r2, new_rtx);
3683 s390_emit_tls_call_insn (r2, tls_call);
3684 insn = get_insns ();
3685 end_sequence ();
3686
3687 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3688 temp = gen_reg_rtx (Pmode);
3689 emit_libcall_block (insn, temp, r2, new_rtx);
3690
3691 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3692 if (reg != 0)
3693 {
3694 s390_load_address (reg, new_rtx);
3695 new_rtx = reg;
3696 }
3697 break;
3698
3699 case TLS_MODEL_LOCAL_DYNAMIC:
3700 start_sequence ();
3701 r2 = gen_rtx_REG (Pmode, 2);
3702 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3703 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3704 new_rtx = force_const_mem (Pmode, new_rtx);
3705 emit_move_insn (r2, new_rtx);
3706 s390_emit_tls_call_insn (r2, tls_call);
3707 insn = get_insns ();
3708 end_sequence ();
3709
3710 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3711 temp = gen_reg_rtx (Pmode);
3712 emit_libcall_block (insn, temp, r2, new_rtx);
3713
3714 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3715 base = gen_reg_rtx (Pmode);
3716 s390_load_address (base, new_rtx);
3717
3718 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3719 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3720 new_rtx = force_const_mem (Pmode, new_rtx);
3721 temp = gen_reg_rtx (Pmode);
3722 emit_move_insn (temp, new_rtx);
3723
3724 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3725 if (reg != 0)
3726 {
3727 s390_load_address (reg, new_rtx);
3728 new_rtx = reg;
3729 }
3730 break;
3731
3732 case TLS_MODEL_INITIAL_EXEC:
3733 if (flag_pic == 1)
3734 {
3735 /* Assume GOT offset < 4k. This is handled the same way
3736 in both 31- and 64-bit code. */
3737
3738 if (reload_in_progress || reload_completed)
3739 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3740
3741 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3742 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3743 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3744 new_rtx = gen_const_mem (Pmode, new_rtx);
3745 temp = gen_reg_rtx (Pmode);
3746 emit_move_insn (temp, new_rtx);
3747 }
3748 else if (TARGET_CPU_ZARCH)
3749 {
3750 /* If the GOT offset might be >= 4k, we determine the position
3751 of the GOT entry via a PC-relative LARL. */
3752
3753 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3754 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3755 temp = gen_reg_rtx (Pmode);
3756 emit_move_insn (temp, new_rtx);
3757
3758 new_rtx = gen_const_mem (Pmode, temp);
3759 temp = gen_reg_rtx (Pmode);
3760 emit_move_insn (temp, new_rtx);
3761 }
3762 else if (flag_pic)
3763 {
3764 /* If the GOT offset might be >= 4k, we have to load it
3765 from the literal pool. */
3766
3767 if (reload_in_progress || reload_completed)
3768 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3769
3770 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3771 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3772 new_rtx = force_const_mem (Pmode, new_rtx);
3773 temp = gen_reg_rtx (Pmode);
3774 emit_move_insn (temp, new_rtx);
3775
3776 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3777 new_rtx = gen_const_mem (Pmode, new_rtx);
3778
3779 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3780 temp = gen_reg_rtx (Pmode);
3781 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3782 }
3783 else
3784 {
3785 /* In position-dependent code, load the absolute address of
3786 the GOT entry from the literal pool. */
3787
3788 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3789 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3790 new_rtx = force_const_mem (Pmode, new_rtx);
3791 temp = gen_reg_rtx (Pmode);
3792 emit_move_insn (temp, new_rtx);
3793
3794 new_rtx = temp;
3795 new_rtx = gen_const_mem (Pmode, new_rtx);
3796 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3797 temp = gen_reg_rtx (Pmode);
3798 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3799 }
3800
3801 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3802 if (reg != 0)
3803 {
3804 s390_load_address (reg, new_rtx);
3805 new_rtx = reg;
3806 }
3807 break;
3808
3809 case TLS_MODEL_LOCAL_EXEC:
3810 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3811 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3812 new_rtx = force_const_mem (Pmode, new_rtx);
3813 temp = gen_reg_rtx (Pmode);
3814 emit_move_insn (temp, new_rtx);
3815
3816 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3817 if (reg != 0)
3818 {
3819 s390_load_address (reg, new_rtx);
3820 new_rtx = reg;
3821 }
3822 break;
3823
3824 default:
3825 gcc_unreachable ();
3826 }
3827
3828 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3829 {
3830 switch (XINT (XEXP (addr, 0), 1))
3831 {
3832 case UNSPEC_INDNTPOFF:
3833 gcc_assert (TARGET_CPU_ZARCH);
3834 new_rtx = addr;
3835 break;
3836
3837 default:
3838 gcc_unreachable ();
3839 }
3840 }
3841
3842 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3843 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3844 {
3845 new_rtx = XEXP (XEXP (addr, 0), 0);
3846 if (GET_CODE (new_rtx) != SYMBOL_REF)
3847 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3848
3849 new_rtx = legitimize_tls_address (new_rtx, reg);
3850 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3851 new_rtx = force_operand (new_rtx, 0);
3852 }
3853
3854 else
3855 gcc_unreachable (); /* for now ... */
3856
3857 return new_rtx;
3858 }
3859
3860 /* Emit insns making the address in operands[1] valid for a standard
3861 move to operands[0]. operands[1] is replaced by an address which
3862 should be used instead of the former RTX to emit the move
3863 pattern. */
3864
3865 void
3866 emit_symbolic_move (rtx *operands)
3867 {
3868 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3869
3870 if (GET_CODE (operands[0]) == MEM)
3871 operands[1] = force_reg (Pmode, operands[1]);
3872 else if (TLS_SYMBOLIC_CONST (operands[1]))
3873 operands[1] = legitimize_tls_address (operands[1], temp);
3874 else if (flag_pic)
3875 operands[1] = legitimize_pic_address (operands[1], temp);
3876 }
3877
3878 /* Try machine-dependent ways of modifying an illegitimate address X
3879 to be legitimate. If we find one, return the new, valid address.
3880
3881 OLDX is the address as it was before break_out_memory_refs was called.
3882 In some cases it is useful to look at this to decide what needs to be done.
3883
3884 MODE is the mode of the operand pointed to by X.
3885
3886 When -fpic is used, special handling is needed for symbolic references.
3887 See comments by legitimize_pic_address for details. */
3888
3889 static rtx
3890 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3891 enum machine_mode mode ATTRIBUTE_UNUSED)
3892 {
3893 rtx constant_term = const0_rtx;
3894
3895 if (TLS_SYMBOLIC_CONST (x))
3896 {
3897 x = legitimize_tls_address (x, 0);
3898
3899 if (s390_legitimate_address_p (mode, x, FALSE))
3900 return x;
3901 }
3902 else if (GET_CODE (x) == PLUS
3903 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3904 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3905 {
3906 return x;
3907 }
3908 else if (flag_pic)
3909 {
3910 if (SYMBOLIC_CONST (x)
3911 || (GET_CODE (x) == PLUS
3912 && (SYMBOLIC_CONST (XEXP (x, 0))
3913 || SYMBOLIC_CONST (XEXP (x, 1)))))
3914 x = legitimize_pic_address (x, 0);
3915
3916 if (s390_legitimate_address_p (mode, x, FALSE))
3917 return x;
3918 }
3919
3920 x = eliminate_constant_term (x, &constant_term);
3921
3922 /* Optimize loading of large displacements by splitting them
3923 into the multiple of 4K and the rest; this allows the
3924 former to be CSE'd if possible.
3925
3926 Don't do this if the displacement is added to a register
3927 pointing into the stack frame, as the offsets will
3928 change later anyway. */
3929
3930 if (GET_CODE (constant_term) == CONST_INT
3931 && !TARGET_LONG_DISPLACEMENT
3932 && !DISP_IN_RANGE (INTVAL (constant_term))
3933 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3934 {
3935 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3936 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3937
3938 rtx temp = gen_reg_rtx (Pmode);
3939 rtx val = force_operand (GEN_INT (upper), temp);
3940 if (val != temp)
3941 emit_move_insn (temp, val);
3942
3943 x = gen_rtx_PLUS (Pmode, x, temp);
3944 constant_term = GEN_INT (lower);
3945 }
3946
3947 if (GET_CODE (x) == PLUS)
3948 {
3949 if (GET_CODE (XEXP (x, 0)) == REG)
3950 {
3951 rtx temp = gen_reg_rtx (Pmode);
3952 rtx val = force_operand (XEXP (x, 1), temp);
3953 if (val != temp)
3954 emit_move_insn (temp, val);
3955
3956 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3957 }
3958
3959 else if (GET_CODE (XEXP (x, 1)) == REG)
3960 {
3961 rtx temp = gen_reg_rtx (Pmode);
3962 rtx val = force_operand (XEXP (x, 0), temp);
3963 if (val != temp)
3964 emit_move_insn (temp, val);
3965
3966 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3967 }
3968 }
3969
3970 if (constant_term != const0_rtx)
3971 x = gen_rtx_PLUS (Pmode, x, constant_term);
3972
3973 return x;
3974 }
3975
3976 /* Try a machine-dependent way of reloading an illegitimate address AD
3977 operand. If we find one, push the reload and and return the new address.
3978
3979 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3980 and TYPE is the reload type of the current reload. */
3981
3982 rtx
3983 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3984 int opnum, int type)
3985 {
3986 if (!optimize || TARGET_LONG_DISPLACEMENT)
3987 return NULL_RTX;
3988
3989 if (GET_CODE (ad) == PLUS)
3990 {
3991 rtx tem = simplify_binary_operation (PLUS, Pmode,
3992 XEXP (ad, 0), XEXP (ad, 1));
3993 if (tem)
3994 ad = tem;
3995 }
3996
3997 if (GET_CODE (ad) == PLUS
3998 && GET_CODE (XEXP (ad, 0)) == REG
3999 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4000 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4001 {
4002 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4003 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4004 rtx cst, tem, new_rtx;
4005
4006 cst = GEN_INT (upper);
4007 if (!legitimate_reload_constant_p (cst))
4008 cst = force_const_mem (Pmode, cst);
4009
4010 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4011 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4012
4013 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4014 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4015 opnum, (enum reload_type) type);
4016 return new_rtx;
4017 }
4018
4019 return NULL_RTX;
4020 }
4021
4022 /* Emit code to move LEN bytes from DST to SRC. */
4023
4024 void
4025 s390_expand_movmem (rtx dst, rtx src, rtx len)
4026 {
4027 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4028 {
4029 if (INTVAL (len) > 0)
4030 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4031 }
4032
4033 else if (TARGET_MVCLE)
4034 {
4035 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4036 }
4037
4038 else
4039 {
4040 rtx dst_addr, src_addr, count, blocks, temp;
4041 rtx loop_start_label = gen_label_rtx ();
4042 rtx loop_end_label = gen_label_rtx ();
4043 rtx end_label = gen_label_rtx ();
4044 enum machine_mode mode;
4045
4046 mode = GET_MODE (len);
4047 if (mode == VOIDmode)
4048 mode = Pmode;
4049
4050 dst_addr = gen_reg_rtx (Pmode);
4051 src_addr = gen_reg_rtx (Pmode);
4052 count = gen_reg_rtx (mode);
4053 blocks = gen_reg_rtx (mode);
4054
4055 convert_move (count, len, 1);
4056 emit_cmp_and_jump_insns (count, const0_rtx,
4057 EQ, NULL_RTX, mode, 1, end_label);
4058
4059 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4060 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4061 dst = change_address (dst, VOIDmode, dst_addr);
4062 src = change_address (src, VOIDmode, src_addr);
4063
4064 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4065 OPTAB_DIRECT);
4066 if (temp != count)
4067 emit_move_insn (count, temp);
4068
4069 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4070 OPTAB_DIRECT);
4071 if (temp != blocks)
4072 emit_move_insn (blocks, temp);
4073
4074 emit_cmp_and_jump_insns (blocks, const0_rtx,
4075 EQ, NULL_RTX, mode, 1, loop_end_label);
4076
4077 emit_label (loop_start_label);
4078
4079 if (TARGET_Z10
4080 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4081 {
4082 rtx prefetch;
4083
4084 /* Issue a read prefetch for the +3 cache line. */
4085 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4086 const0_rtx, const0_rtx);
4087 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4088 emit_insn (prefetch);
4089
4090 /* Issue a write prefetch for the +3 cache line. */
4091 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4092 const1_rtx, const0_rtx);
4093 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4094 emit_insn (prefetch);
4095 }
4096
4097 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4098 s390_load_address (dst_addr,
4099 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4100 s390_load_address (src_addr,
4101 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4102
4103 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4104 OPTAB_DIRECT);
4105 if (temp != blocks)
4106 emit_move_insn (blocks, temp);
4107
4108 emit_cmp_and_jump_insns (blocks, const0_rtx,
4109 EQ, NULL_RTX, mode, 1, loop_end_label);
4110
4111 emit_jump (loop_start_label);
4112 emit_label (loop_end_label);
4113
4114 emit_insn (gen_movmem_short (dst, src,
4115 convert_to_mode (Pmode, count, 1)));
4116 emit_label (end_label);
4117 }
4118 }
4119
4120 /* Emit code to set LEN bytes at DST to VAL.
4121 Make use of clrmem if VAL is zero. */
4122
4123 void
4124 s390_expand_setmem (rtx dst, rtx len, rtx val)
4125 {
4126 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4127 return;
4128
4129 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4130
4131 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4132 {
4133 if (val == const0_rtx && INTVAL (len) <= 256)
4134 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4135 else
4136 {
4137 /* Initialize memory by storing the first byte. */
4138 emit_move_insn (adjust_address (dst, QImode, 0), val);
4139
4140 if (INTVAL (len) > 1)
4141 {
4142 /* Initiate 1 byte overlap move.
4143 The first byte of DST is propagated through DSTP1.
4144 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4145 DST is set to size 1 so the rest of the memory location
4146 does not count as source operand. */
4147 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4148 set_mem_size (dst, const1_rtx);
4149
4150 emit_insn (gen_movmem_short (dstp1, dst,
4151 GEN_INT (INTVAL (len) - 2)));
4152 }
4153 }
4154 }
4155
4156 else if (TARGET_MVCLE)
4157 {
4158 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4159 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4160 }
4161
4162 else
4163 {
4164 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4165 rtx loop_start_label = gen_label_rtx ();
4166 rtx loop_end_label = gen_label_rtx ();
4167 rtx end_label = gen_label_rtx ();
4168 enum machine_mode mode;
4169
4170 mode = GET_MODE (len);
4171 if (mode == VOIDmode)
4172 mode = Pmode;
4173
4174 dst_addr = gen_reg_rtx (Pmode);
4175 count = gen_reg_rtx (mode);
4176 blocks = gen_reg_rtx (mode);
4177
4178 convert_move (count, len, 1);
4179 emit_cmp_and_jump_insns (count, const0_rtx,
4180 EQ, NULL_RTX, mode, 1, end_label);
4181
4182 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4183 dst = change_address (dst, VOIDmode, dst_addr);
4184
4185 if (val == const0_rtx)
4186 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4187 OPTAB_DIRECT);
4188 else
4189 {
4190 dstp1 = adjust_address (dst, VOIDmode, 1);
4191 set_mem_size (dst, const1_rtx);
4192
4193 /* Initialize memory by storing the first byte. */
4194 emit_move_insn (adjust_address (dst, QImode, 0), val);
4195
4196 /* If count is 1 we are done. */
4197 emit_cmp_and_jump_insns (count, const1_rtx,
4198 EQ, NULL_RTX, mode, 1, end_label);
4199
4200 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4201 OPTAB_DIRECT);
4202 }
4203 if (temp != count)
4204 emit_move_insn (count, temp);
4205
4206 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4207 OPTAB_DIRECT);
4208 if (temp != blocks)
4209 emit_move_insn (blocks, temp);
4210
4211 emit_cmp_and_jump_insns (blocks, const0_rtx,
4212 EQ, NULL_RTX, mode, 1, loop_end_label);
4213
4214 emit_label (loop_start_label);
4215
4216 if (TARGET_Z10
4217 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4218 {
4219 /* Issue a write prefetch for the +4 cache line. */
4220 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4221 GEN_INT (1024)),
4222 const1_rtx, const0_rtx);
4223 emit_insn (prefetch);
4224 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4225 }
4226
4227 if (val == const0_rtx)
4228 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4229 else
4230 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4231 s390_load_address (dst_addr,
4232 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4233
4234 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4235 OPTAB_DIRECT);
4236 if (temp != blocks)
4237 emit_move_insn (blocks, temp);
4238
4239 emit_cmp_and_jump_insns (blocks, const0_rtx,
4240 EQ, NULL_RTX, mode, 1, loop_end_label);
4241
4242 emit_jump (loop_start_label);
4243 emit_label (loop_end_label);
4244
4245 if (val == const0_rtx)
4246 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4247 else
4248 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4249 emit_label (end_label);
4250 }
4251 }
4252
4253 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4254 and return the result in TARGET. */
4255
4256 void
4257 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4258 {
4259 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4260 rtx tmp;
4261
4262 /* As the result of CMPINT is inverted compared to what we need,
4263 we have to swap the operands. */
4264 tmp = op0; op0 = op1; op1 = tmp;
4265
4266 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4267 {
4268 if (INTVAL (len) > 0)
4269 {
4270 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4271 emit_insn (gen_cmpint (target, ccreg));
4272 }
4273 else
4274 emit_move_insn (target, const0_rtx);
4275 }
4276 else if (TARGET_MVCLE)
4277 {
4278 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4279 emit_insn (gen_cmpint (target, ccreg));
4280 }
4281 else
4282 {
4283 rtx addr0, addr1, count, blocks, temp;
4284 rtx loop_start_label = gen_label_rtx ();
4285 rtx loop_end_label = gen_label_rtx ();
4286 rtx end_label = gen_label_rtx ();
4287 enum machine_mode mode;
4288
4289 mode = GET_MODE (len);
4290 if (mode == VOIDmode)
4291 mode = Pmode;
4292
4293 addr0 = gen_reg_rtx (Pmode);
4294 addr1 = gen_reg_rtx (Pmode);
4295 count = gen_reg_rtx (mode);
4296 blocks = gen_reg_rtx (mode);
4297
4298 convert_move (count, len, 1);
4299 emit_cmp_and_jump_insns (count, const0_rtx,
4300 EQ, NULL_RTX, mode, 1, end_label);
4301
4302 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4303 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4304 op0 = change_address (op0, VOIDmode, addr0);
4305 op1 = change_address (op1, VOIDmode, addr1);
4306
4307 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4308 OPTAB_DIRECT);
4309 if (temp != count)
4310 emit_move_insn (count, temp);
4311
4312 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4313 OPTAB_DIRECT);
4314 if (temp != blocks)
4315 emit_move_insn (blocks, temp);
4316
4317 emit_cmp_and_jump_insns (blocks, const0_rtx,
4318 EQ, NULL_RTX, mode, 1, loop_end_label);
4319
4320 emit_label (loop_start_label);
4321
4322 if (TARGET_Z10
4323 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4324 {
4325 rtx prefetch;
4326
4327 /* Issue a read prefetch for the +2 cache line of operand 1. */
4328 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4329 const0_rtx, const0_rtx);
4330 emit_insn (prefetch);
4331 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4332
4333 /* Issue a read prefetch for the +2 cache line of operand 2. */
4334 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4335 const0_rtx, const0_rtx);
4336 emit_insn (prefetch);
4337 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4338 }
4339
4340 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4341 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4342 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4343 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4344 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4345 emit_jump_insn (temp);
4346
4347 s390_load_address (addr0,
4348 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4349 s390_load_address (addr1,
4350 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4351
4352 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4353 OPTAB_DIRECT);
4354 if (temp != blocks)
4355 emit_move_insn (blocks, temp);
4356
4357 emit_cmp_and_jump_insns (blocks, const0_rtx,
4358 EQ, NULL_RTX, mode, 1, loop_end_label);
4359
4360 emit_jump (loop_start_label);
4361 emit_label (loop_end_label);
4362
4363 emit_insn (gen_cmpmem_short (op0, op1,
4364 convert_to_mode (Pmode, count, 1)));
4365 emit_label (end_label);
4366
4367 emit_insn (gen_cmpint (target, ccreg));
4368 }
4369 }
4370
4371
4372 /* Expand conditional increment or decrement using alc/slb instructions.
4373 Should generate code setting DST to either SRC or SRC + INCREMENT,
4374 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4375 Returns true if successful, false otherwise.
4376
4377 That makes it possible to implement some if-constructs without jumps e.g.:
4378 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4379 unsigned int a, b, c;
4380 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4381 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4382 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4383 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4384
4385 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4386 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4387 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4388 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4389 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4390
4391 bool
4392 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4393 rtx dst, rtx src, rtx increment)
4394 {
4395 enum machine_mode cmp_mode;
4396 enum machine_mode cc_mode;
4397 rtx op_res;
4398 rtx insn;
4399 rtvec p;
4400 int ret;
4401
4402 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4403 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4404 cmp_mode = SImode;
4405 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4406 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4407 cmp_mode = DImode;
4408 else
4409 return false;
4410
4411 /* Try ADD LOGICAL WITH CARRY. */
4412 if (increment == const1_rtx)
4413 {
4414 /* Determine CC mode to use. */
4415 if (cmp_code == EQ || cmp_code == NE)
4416 {
4417 if (cmp_op1 != const0_rtx)
4418 {
4419 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4420 NULL_RTX, 0, OPTAB_WIDEN);
4421 cmp_op1 = const0_rtx;
4422 }
4423
4424 cmp_code = cmp_code == EQ ? LEU : GTU;
4425 }
4426
4427 if (cmp_code == LTU || cmp_code == LEU)
4428 {
4429 rtx tem = cmp_op0;
4430 cmp_op0 = cmp_op1;
4431 cmp_op1 = tem;
4432 cmp_code = swap_condition (cmp_code);
4433 }
4434
4435 switch (cmp_code)
4436 {
4437 case GTU:
4438 cc_mode = CCUmode;
4439 break;
4440
4441 case GEU:
4442 cc_mode = CCL3mode;
4443 break;
4444
4445 default:
4446 return false;
4447 }
4448
4449 /* Emit comparison instruction pattern. */
4450 if (!register_operand (cmp_op0, cmp_mode))
4451 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4452
4453 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4454 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4455 /* We use insn_invalid_p here to add clobbers if required. */
4456 ret = insn_invalid_p (emit_insn (insn));
4457 gcc_assert (!ret);
4458
4459 /* Emit ALC instruction pattern. */
4460 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4461 gen_rtx_REG (cc_mode, CC_REGNUM),
4462 const0_rtx);
4463
4464 if (src != const0_rtx)
4465 {
4466 if (!register_operand (src, GET_MODE (dst)))
4467 src = force_reg (GET_MODE (dst), src);
4468
4469 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4470 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4471 }
4472
4473 p = rtvec_alloc (2);
4474 RTVEC_ELT (p, 0) =
4475 gen_rtx_SET (VOIDmode, dst, op_res);
4476 RTVEC_ELT (p, 1) =
4477 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4478 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4479
4480 return true;
4481 }
4482
4483 /* Try SUBTRACT LOGICAL WITH BORROW. */
4484 if (increment == constm1_rtx)
4485 {
4486 /* Determine CC mode to use. */
4487 if (cmp_code == EQ || cmp_code == NE)
4488 {
4489 if (cmp_op1 != const0_rtx)
4490 {
4491 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4492 NULL_RTX, 0, OPTAB_WIDEN);
4493 cmp_op1 = const0_rtx;
4494 }
4495
4496 cmp_code = cmp_code == EQ ? LEU : GTU;
4497 }
4498
4499 if (cmp_code == GTU || cmp_code == GEU)
4500 {
4501 rtx tem = cmp_op0;
4502 cmp_op0 = cmp_op1;
4503 cmp_op1 = tem;
4504 cmp_code = swap_condition (cmp_code);
4505 }
4506
4507 switch (cmp_code)
4508 {
4509 case LEU:
4510 cc_mode = CCUmode;
4511 break;
4512
4513 case LTU:
4514 cc_mode = CCL3mode;
4515 break;
4516
4517 default:
4518 return false;
4519 }
4520
4521 /* Emit comparison instruction pattern. */
4522 if (!register_operand (cmp_op0, cmp_mode))
4523 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4524
4525 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4526 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4527 /* We use insn_invalid_p here to add clobbers if required. */
4528 ret = insn_invalid_p (emit_insn (insn));
4529 gcc_assert (!ret);
4530
4531 /* Emit SLB instruction pattern. */
4532 if (!register_operand (src, GET_MODE (dst)))
4533 src = force_reg (GET_MODE (dst), src);
4534
4535 op_res = gen_rtx_MINUS (GET_MODE (dst),
4536 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4537 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4538 gen_rtx_REG (cc_mode, CC_REGNUM),
4539 const0_rtx));
4540 p = rtvec_alloc (2);
4541 RTVEC_ELT (p, 0) =
4542 gen_rtx_SET (VOIDmode, dst, op_res);
4543 RTVEC_ELT (p, 1) =
4544 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4545 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4546
4547 return true;
4548 }
4549
4550 return false;
4551 }
4552
4553 /* Expand code for the insv template. Return true if successful. */
4554
4555 bool
4556 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4557 {
4558 int bitsize = INTVAL (op1);
4559 int bitpos = INTVAL (op2);
4560
4561 /* On z10 we can use the risbg instruction to implement insv. */
4562 if (TARGET_Z10
4563 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4564 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4565 {
4566 rtx op;
4567 rtx clobber;
4568
4569 op = gen_rtx_SET (GET_MODE(src),
4570 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4571 src);
4572 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4573 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4574
4575 return true;
4576 }
4577
4578 /* We need byte alignment. */
4579 if (bitsize % BITS_PER_UNIT)
4580 return false;
4581
4582 if (bitpos == 0
4583 && memory_operand (dest, VOIDmode)
4584 && (register_operand (src, word_mode)
4585 || const_int_operand (src, VOIDmode)))
4586 {
4587 /* Emit standard pattern if possible. */
4588 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4589 if (GET_MODE_BITSIZE (mode) == bitsize)
4590 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4591
4592 /* (set (ze (mem)) (const_int)). */
4593 else if (const_int_operand (src, VOIDmode))
4594 {
4595 int size = bitsize / BITS_PER_UNIT;
4596 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4597 GET_MODE_SIZE (word_mode) - size);
4598
4599 dest = adjust_address (dest, BLKmode, 0);
4600 set_mem_size (dest, GEN_INT (size));
4601 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4602 }
4603
4604 /* (set (ze (mem)) (reg)). */
4605 else if (register_operand (src, word_mode))
4606 {
4607 if (bitsize <= GET_MODE_BITSIZE (SImode))
4608 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4609 const0_rtx), src);
4610 else
4611 {
4612 /* Emit st,stcmh sequence. */
4613 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4614 int size = stcmh_width / BITS_PER_UNIT;
4615
4616 emit_move_insn (adjust_address (dest, SImode, size),
4617 gen_lowpart (SImode, src));
4618 set_mem_size (dest, GEN_INT (size));
4619 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4620 (stcmh_width), const0_rtx),
4621 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4622 (GET_MODE_BITSIZE (SImode))));
4623 }
4624 }
4625 else
4626 return false;
4627
4628 return true;
4629 }
4630
4631 /* (set (ze (reg)) (const_int)). */
4632 if (TARGET_ZARCH
4633 && register_operand (dest, word_mode)
4634 && (bitpos % 16) == 0
4635 && (bitsize % 16) == 0
4636 && const_int_operand (src, VOIDmode))
4637 {
4638 HOST_WIDE_INT val = INTVAL (src);
4639 int regpos = bitpos + bitsize;
4640
4641 while (regpos > bitpos)
4642 {
4643 enum machine_mode putmode;
4644 int putsize;
4645
4646 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4647 putmode = SImode;
4648 else
4649 putmode = HImode;
4650
4651 putsize = GET_MODE_BITSIZE (putmode);
4652 regpos -= putsize;
4653 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4654 GEN_INT (putsize),
4655 GEN_INT (regpos)),
4656 gen_int_mode (val, putmode));
4657 val >>= putsize;
4658 }
4659 gcc_assert (regpos == bitpos);
4660 return true;
4661 }
4662
4663 return false;
4664 }
4665
4666 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4667 register that holds VAL of mode MODE shifted by COUNT bits. */
4668
4669 static inline rtx
4670 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4671 {
4672 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4673 NULL_RTX, 1, OPTAB_DIRECT);
4674 return expand_simple_binop (SImode, ASHIFT, val, count,
4675 NULL_RTX, 1, OPTAB_DIRECT);
4676 }
4677
4678 /* Structure to hold the initial parameters for a compare_and_swap operation
4679 in HImode and QImode. */
4680
4681 struct alignment_context
4682 {
4683 rtx memsi; /* SI aligned memory location. */
4684 rtx shift; /* Bit offset with regard to lsb. */
4685 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4686 rtx modemaski; /* ~modemask */
4687 bool aligned; /* True if memory is aligned, false else. */
4688 };
4689
4690 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4691 structure AC for transparent simplifying, if the memory alignment is known
4692 to be at least 32bit. MEM is the memory location for the actual operation
4693 and MODE its mode. */
4694
4695 static void
4696 init_alignment_context (struct alignment_context *ac, rtx mem,
4697 enum machine_mode mode)
4698 {
4699 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4700 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4701
4702 if (ac->aligned)
4703 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4704 else
4705 {
4706 /* Alignment is unknown. */
4707 rtx byteoffset, addr, align;
4708
4709 /* Force the address into a register. */
4710 addr = force_reg (Pmode, XEXP (mem, 0));
4711
4712 /* Align it to SImode. */
4713 align = expand_simple_binop (Pmode, AND, addr,
4714 GEN_INT (-GET_MODE_SIZE (SImode)),
4715 NULL_RTX, 1, OPTAB_DIRECT);
4716 /* Generate MEM. */
4717 ac->memsi = gen_rtx_MEM (SImode, align);
4718 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4719 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4720 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4721
4722 /* Calculate shiftcount. */
4723 byteoffset = expand_simple_binop (Pmode, AND, addr,
4724 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4725 NULL_RTX, 1, OPTAB_DIRECT);
4726 /* As we already have some offset, evaluate the remaining distance. */
4727 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4728 NULL_RTX, 1, OPTAB_DIRECT);
4729
4730 }
4731 /* Shift is the byte count, but we need the bitcount. */
4732 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4733 NULL_RTX, 1, OPTAB_DIRECT);
4734 /* Calculate masks. */
4735 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4736 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4737 NULL_RTX, 1, OPTAB_DIRECT);
4738 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4739 }
4740
4741 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4742 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4743 to set if CMP == MEM.
4744 CMP is never in memory for compare_and_swap_cc because
4745 expand_bool_compare_and_swap puts it into a register for later compare. */
4746
4747 void
4748 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4749 {
4750 struct alignment_context ac;
4751 rtx cmpv, newv, val, resv, cc;
4752 rtx res = gen_reg_rtx (SImode);
4753 rtx csloop = gen_label_rtx ();
4754 rtx csend = gen_label_rtx ();
4755
4756 gcc_assert (register_operand (target, VOIDmode));
4757 gcc_assert (MEM_P (mem));
4758
4759 init_alignment_context (&ac, mem, mode);
4760
4761 /* Shift the values to the correct bit positions. */
4762 if (!(ac.aligned && MEM_P (cmp)))
4763 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4764 if (!(ac.aligned && MEM_P (new_rtx)))
4765 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4766
4767 /* Load full word. Subsequent loads are performed by CS. */
4768 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4769 NULL_RTX, 1, OPTAB_DIRECT);
4770
4771 /* Start CS loop. */
4772 emit_label (csloop);
4773 /* val = "<mem>00..0<mem>"
4774 * cmp = "00..0<cmp>00..0"
4775 * new = "00..0<new>00..0"
4776 */
4777
4778 /* Patch cmp and new with val at correct position. */
4779 if (ac.aligned && MEM_P (cmp))
4780 {
4781 cmpv = force_reg (SImode, val);
4782 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4783 }
4784 else
4785 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4786 NULL_RTX, 1, OPTAB_DIRECT));
4787 if (ac.aligned && MEM_P (new_rtx))
4788 {
4789 newv = force_reg (SImode, val);
4790 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4791 }
4792 else
4793 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4794 NULL_RTX, 1, OPTAB_DIRECT));
4795
4796 /* Jump to end if we're done (likely?). */
4797 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4798 cmpv, newv));
4799
4800 /* Check for changes outside mode. */
4801 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4802 NULL_RTX, 1, OPTAB_DIRECT);
4803 cc = s390_emit_compare (NE, resv, val);
4804 emit_move_insn (val, resv);
4805 /* Loop internal if so. */
4806 s390_emit_jump (csloop, cc);
4807
4808 emit_label (csend);
4809
4810 /* Return the correct part of the bitfield. */
4811 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4812 NULL_RTX, 1, OPTAB_DIRECT), 1);
4813 }
4814
4815 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4816 and VAL the value to play with. If AFTER is true then store the value
4817 MEM holds after the operation, if AFTER is false then store the value MEM
4818 holds before the operation. If TARGET is zero then discard that value, else
4819 store it to TARGET. */
4820
4821 void
4822 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4823 rtx target, rtx mem, rtx val, bool after)
4824 {
4825 struct alignment_context ac;
4826 rtx cmp;
4827 rtx new_rtx = gen_reg_rtx (SImode);
4828 rtx orig = gen_reg_rtx (SImode);
4829 rtx csloop = gen_label_rtx ();
4830
4831 gcc_assert (!target || register_operand (target, VOIDmode));
4832 gcc_assert (MEM_P (mem));
4833
4834 init_alignment_context (&ac, mem, mode);
4835
4836 /* Shift val to the correct bit positions.
4837 Preserve "icm", but prevent "ex icm". */
4838 if (!(ac.aligned && code == SET && MEM_P (val)))
4839 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4840
4841 /* Further preparation insns. */
4842 if (code == PLUS || code == MINUS)
4843 emit_move_insn (orig, val);
4844 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4845 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4846 NULL_RTX, 1, OPTAB_DIRECT);
4847
4848 /* Load full word. Subsequent loads are performed by CS. */
4849 cmp = force_reg (SImode, ac.memsi);
4850
4851 /* Start CS loop. */
4852 emit_label (csloop);
4853 emit_move_insn (new_rtx, cmp);
4854
4855 /* Patch new with val at correct position. */
4856 switch (code)
4857 {
4858 case PLUS:
4859 case MINUS:
4860 val = expand_simple_binop (SImode, code, new_rtx, orig,
4861 NULL_RTX, 1, OPTAB_DIRECT);
4862 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4863 NULL_RTX, 1, OPTAB_DIRECT);
4864 /* FALLTHRU */
4865 case SET:
4866 if (ac.aligned && MEM_P (val))
4867 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4868 else
4869 {
4870 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4871 NULL_RTX, 1, OPTAB_DIRECT);
4872 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4873 NULL_RTX, 1, OPTAB_DIRECT);
4874 }
4875 break;
4876 case AND:
4877 case IOR:
4878 case XOR:
4879 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4880 NULL_RTX, 1, OPTAB_DIRECT);
4881 break;
4882 case MULT: /* NAND */
4883 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4884 NULL_RTX, 1, OPTAB_DIRECT);
4885 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4886 NULL_RTX, 1, OPTAB_DIRECT);
4887 break;
4888 default:
4889 gcc_unreachable ();
4890 }
4891
4892 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4893 ac.memsi, cmp, new_rtx));
4894
4895 /* Return the correct part of the bitfield. */
4896 if (target)
4897 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4898 after ? new_rtx : cmp, ac.shift,
4899 NULL_RTX, 1, OPTAB_DIRECT), 1);
4900 }
4901
4902 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4903 We need to emit DTP-relative relocations. */
4904
4905 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4906
4907 static void
4908 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4909 {
4910 switch (size)
4911 {
4912 case 4:
4913 fputs ("\t.long\t", file);
4914 break;
4915 case 8:
4916 fputs ("\t.quad\t", file);
4917 break;
4918 default:
4919 gcc_unreachable ();
4920 }
4921 output_addr_const (file, x);
4922 fputs ("@DTPOFF", file);
4923 }
4924
4925 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4926 /* Implement TARGET_MANGLE_TYPE. */
4927
4928 static const char *
4929 s390_mangle_type (const_tree type)
4930 {
4931 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4932 && TARGET_LONG_DOUBLE_128)
4933 return "g";
4934
4935 /* For all other types, use normal C++ mangling. */
4936 return NULL;
4937 }
4938 #endif
4939
4940 /* In the name of slightly smaller debug output, and to cater to
4941 general assembler lossage, recognize various UNSPEC sequences
4942 and turn them back into a direct symbol reference. */
4943
4944 static rtx
4945 s390_delegitimize_address (rtx orig_x)
4946 {
4947 rtx x, y;
4948
4949 orig_x = delegitimize_mem_from_attrs (orig_x);
4950 x = orig_x;
4951 if (GET_CODE (x) != MEM)
4952 return orig_x;
4953
4954 x = XEXP (x, 0);
4955 if (GET_CODE (x) == PLUS
4956 && GET_CODE (XEXP (x, 1)) == CONST
4957 && GET_CODE (XEXP (x, 0)) == REG
4958 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4959 {
4960 y = XEXP (XEXP (x, 1), 0);
4961 if (GET_CODE (y) == UNSPEC
4962 && XINT (y, 1) == UNSPEC_GOT)
4963 return XVECEXP (y, 0, 0);
4964 return orig_x;
4965 }
4966
4967 if (GET_CODE (x) == CONST)
4968 {
4969 y = XEXP (x, 0);
4970 if (GET_CODE (y) == UNSPEC
4971 && XINT (y, 1) == UNSPEC_GOTENT)
4972 return XVECEXP (y, 0, 0);
4973 return orig_x;
4974 }
4975
4976 return orig_x;
4977 }
4978
4979 /* Output operand OP to stdio stream FILE.
4980 OP is an address (register + offset) which is not used to address data;
4981 instead the rightmost bits are interpreted as the value. */
4982
4983 static void
4984 print_shift_count_operand (FILE *file, rtx op)
4985 {
4986 HOST_WIDE_INT offset;
4987 rtx base;
4988
4989 /* Extract base register and offset. */
4990 if (!s390_decompose_shift_count (op, &base, &offset))
4991 gcc_unreachable ();
4992
4993 /* Sanity check. */
4994 if (base)
4995 {
4996 gcc_assert (GET_CODE (base) == REG);
4997 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4998 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4999 }
5000
5001 /* Offsets are constricted to twelve bits. */
5002 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5003 if (base)
5004 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5005 }
5006
5007 /* See 'get_some_local_dynamic_name'. */
5008
5009 static int
5010 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5011 {
5012 rtx x = *px;
5013
5014 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5015 {
5016 x = get_pool_constant (x);
5017 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5018 }
5019
5020 if (GET_CODE (x) == SYMBOL_REF
5021 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5022 {
5023 cfun->machine->some_ld_name = XSTR (x, 0);
5024 return 1;
5025 }
5026
5027 return 0;
5028 }
5029
5030 /* Locate some local-dynamic symbol still in use by this function
5031 so that we can print its name in local-dynamic base patterns. */
5032
5033 static const char *
5034 get_some_local_dynamic_name (void)
5035 {
5036 rtx insn;
5037
5038 if (cfun->machine->some_ld_name)
5039 return cfun->machine->some_ld_name;
5040
5041 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5042 if (INSN_P (insn)
5043 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5044 return cfun->machine->some_ld_name;
5045
5046 gcc_unreachable ();
5047 }
5048
5049 /* Output machine-dependent UNSPECs occurring in address constant X
5050 in assembler syntax to stdio stream FILE. Returns true if the
5051 constant X could be recognized, false otherwise. */
5052
5053 bool
5054 s390_output_addr_const_extra (FILE *file, rtx x)
5055 {
5056 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5057 switch (XINT (x, 1))
5058 {
5059 case UNSPEC_GOTENT:
5060 output_addr_const (file, XVECEXP (x, 0, 0));
5061 fprintf (file, "@GOTENT");
5062 return true;
5063 case UNSPEC_GOT:
5064 output_addr_const (file, XVECEXP (x, 0, 0));
5065 fprintf (file, "@GOT");
5066 return true;
5067 case UNSPEC_GOTOFF:
5068 output_addr_const (file, XVECEXP (x, 0, 0));
5069 fprintf (file, "@GOTOFF");
5070 return true;
5071 case UNSPEC_PLT:
5072 output_addr_const (file, XVECEXP (x, 0, 0));
5073 fprintf (file, "@PLT");
5074 return true;
5075 case UNSPEC_PLTOFF:
5076 output_addr_const (file, XVECEXP (x, 0, 0));
5077 fprintf (file, "@PLTOFF");
5078 return true;
5079 case UNSPEC_TLSGD:
5080 output_addr_const (file, XVECEXP (x, 0, 0));
5081 fprintf (file, "@TLSGD");
5082 return true;
5083 case UNSPEC_TLSLDM:
5084 assemble_name (file, get_some_local_dynamic_name ());
5085 fprintf (file, "@TLSLDM");
5086 return true;
5087 case UNSPEC_DTPOFF:
5088 output_addr_const (file, XVECEXP (x, 0, 0));
5089 fprintf (file, "@DTPOFF");
5090 return true;
5091 case UNSPEC_NTPOFF:
5092 output_addr_const (file, XVECEXP (x, 0, 0));
5093 fprintf (file, "@NTPOFF");
5094 return true;
5095 case UNSPEC_GOTNTPOFF:
5096 output_addr_const (file, XVECEXP (x, 0, 0));
5097 fprintf (file, "@GOTNTPOFF");
5098 return true;
5099 case UNSPEC_INDNTPOFF:
5100 output_addr_const (file, XVECEXP (x, 0, 0));
5101 fprintf (file, "@INDNTPOFF");
5102 return true;
5103 }
5104
5105 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5106 switch (XINT (x, 1))
5107 {
5108 case UNSPEC_POOL_OFFSET:
5109 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5110 output_addr_const (file, x);
5111 return true;
5112 }
5113 return false;
5114 }
5115
5116 /* Output address operand ADDR in assembler syntax to
5117 stdio stream FILE. */
5118
5119 void
5120 print_operand_address (FILE *file, rtx addr)
5121 {
5122 struct s390_address ad;
5123
5124 if (s390_symref_operand_p (addr, NULL, NULL))
5125 {
5126 gcc_assert (TARGET_Z10);
5127 output_addr_const (file, addr);
5128 return;
5129 }
5130
5131 if (!s390_decompose_address (addr, &ad)
5132 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5133 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5134 output_operand_lossage ("cannot decompose address");
5135
5136 if (ad.disp)
5137 output_addr_const (file, ad.disp);
5138 else
5139 fprintf (file, "0");
5140
5141 if (ad.base && ad.indx)
5142 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5143 reg_names[REGNO (ad.base)]);
5144 else if (ad.base)
5145 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5146 }
5147
5148 /* Output operand X in assembler syntax to stdio stream FILE.
5149 CODE specified the format flag. The following format flags
5150 are recognized:
5151
5152 'C': print opcode suffix for branch condition.
5153 'D': print opcode suffix for inverse branch condition.
5154 'E': print opcode suffix for branch on index instruction.
5155 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5156 'G': print the size of the operand in bytes.
5157 'O': print only the displacement of a memory reference.
5158 'R': print only the base register of a memory reference.
5159 'S': print S-type memory reference (base+displacement).
5160 'N': print the second word of a DImode operand.
5161 'M': print the second word of a TImode operand.
5162 'Y': print shift count operand.
5163
5164 'b': print integer X as if it's an unsigned byte.
5165 'c': print integer X as if it's an signed byte.
5166 'x': print integer X as if it's an unsigned halfword.
5167 'h': print integer X as if it's a signed halfword.
5168 'i': print the first nonzero HImode part of X.
5169 'j': print the first HImode part unequal to -1 of X.
5170 'k': print the first nonzero SImode part of X.
5171 'm': print the first SImode part unequal to -1 of X.
5172 'o': print integer X as if it's an unsigned 32bit word. */
5173
5174 void
5175 print_operand (FILE *file, rtx x, int code)
5176 {
5177 switch (code)
5178 {
5179 case 'C':
5180 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5181 return;
5182
5183 case 'D':
5184 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5185 return;
5186
5187 case 'E':
5188 if (GET_CODE (x) == LE)
5189 fprintf (file, "l");
5190 else if (GET_CODE (x) == GT)
5191 fprintf (file, "h");
5192 else
5193 gcc_unreachable ();
5194 return;
5195
5196 case 'J':
5197 if (GET_CODE (x) == SYMBOL_REF)
5198 {
5199 fprintf (file, "%s", ":tls_load:");
5200 output_addr_const (file, x);
5201 }
5202 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5203 {
5204 fprintf (file, "%s", ":tls_gdcall:");
5205 output_addr_const (file, XVECEXP (x, 0, 0));
5206 }
5207 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5208 {
5209 fprintf (file, "%s", ":tls_ldcall:");
5210 assemble_name (file, get_some_local_dynamic_name ());
5211 }
5212 else
5213 gcc_unreachable ();
5214 return;
5215
5216 case 'G':
5217 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5218 return;
5219
5220 case 'O':
5221 {
5222 struct s390_address ad;
5223 int ret;
5224
5225 gcc_assert (GET_CODE (x) == MEM);
5226 ret = s390_decompose_address (XEXP (x, 0), &ad);
5227 gcc_assert (ret);
5228 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5229 gcc_assert (!ad.indx);
5230
5231 if (ad.disp)
5232 output_addr_const (file, ad.disp);
5233 else
5234 fprintf (file, "0");
5235 }
5236 return;
5237
5238 case 'R':
5239 {
5240 struct s390_address ad;
5241 int ret;
5242
5243 gcc_assert (GET_CODE (x) == MEM);
5244 ret = s390_decompose_address (XEXP (x, 0), &ad);
5245 gcc_assert (ret);
5246 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5247 gcc_assert (!ad.indx);
5248
5249 if (ad.base)
5250 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5251 else
5252 fprintf (file, "0");
5253 }
5254 return;
5255
5256 case 'S':
5257 {
5258 struct s390_address ad;
5259 int ret;
5260
5261 gcc_assert (GET_CODE (x) == MEM);
5262 ret = s390_decompose_address (XEXP (x, 0), &ad);
5263 gcc_assert (ret);
5264 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5265 gcc_assert (!ad.indx);
5266
5267 if (ad.disp)
5268 output_addr_const (file, ad.disp);
5269 else
5270 fprintf (file, "0");
5271
5272 if (ad.base)
5273 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5274 }
5275 return;
5276
5277 case 'N':
5278 if (GET_CODE (x) == REG)
5279 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5280 else if (GET_CODE (x) == MEM)
5281 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5282 else
5283 gcc_unreachable ();
5284 break;
5285
5286 case 'M':
5287 if (GET_CODE (x) == REG)
5288 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5289 else if (GET_CODE (x) == MEM)
5290 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5291 else
5292 gcc_unreachable ();
5293 break;
5294
5295 case 'Y':
5296 print_shift_count_operand (file, x);
5297 return;
5298 }
5299
5300 switch (GET_CODE (x))
5301 {
5302 case REG:
5303 fprintf (file, "%s", reg_names[REGNO (x)]);
5304 break;
5305
5306 case MEM:
5307 output_address (XEXP (x, 0));
5308 break;
5309
5310 case CONST:
5311 case CODE_LABEL:
5312 case LABEL_REF:
5313 case SYMBOL_REF:
5314 output_addr_const (file, x);
5315 break;
5316
5317 case CONST_INT:
5318 if (code == 'b')
5319 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5320 else if (code == 'c')
5321 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5322 else if (code == 'x')
5323 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5324 else if (code == 'h')
5325 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5326 else if (code == 'i')
5327 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5328 s390_extract_part (x, HImode, 0));
5329 else if (code == 'j')
5330 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5331 s390_extract_part (x, HImode, -1));
5332 else if (code == 'k')
5333 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5334 s390_extract_part (x, SImode, 0));
5335 else if (code == 'm')
5336 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5337 s390_extract_part (x, SImode, -1));
5338 else if (code == 'o')
5339 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5340 else
5341 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5342 break;
5343
5344 case CONST_DOUBLE:
5345 gcc_assert (GET_MODE (x) == VOIDmode);
5346 if (code == 'b')
5347 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5348 else if (code == 'x')
5349 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5350 else if (code == 'h')
5351 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5352 else
5353 gcc_unreachable ();
5354 break;
5355
5356 default:
5357 fatal_insn ("UNKNOWN in print_operand !?", x);
5358 break;
5359 }
5360 }
5361
5362 /* Target hook for assembling integer objects. We need to define it
5363 here to work a round a bug in some versions of GAS, which couldn't
5364 handle values smaller than INT_MIN when printed in decimal. */
5365
5366 static bool
5367 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5368 {
5369 if (size == 8 && aligned_p
5370 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5371 {
5372 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5373 INTVAL (x));
5374 return true;
5375 }
5376 return default_assemble_integer (x, size, aligned_p);
5377 }
5378
5379 /* Returns true if register REGNO is used for forming
5380 a memory address in expression X. */
5381
5382 static bool
5383 reg_used_in_mem_p (int regno, rtx x)
5384 {
5385 enum rtx_code code = GET_CODE (x);
5386 int i, j;
5387 const char *fmt;
5388
5389 if (code == MEM)
5390 {
5391 if (refers_to_regno_p (regno, regno+1,
5392 XEXP (x, 0), 0))
5393 return true;
5394 }
5395 else if (code == SET
5396 && GET_CODE (SET_DEST (x)) == PC)
5397 {
5398 if (refers_to_regno_p (regno, regno+1,
5399 SET_SRC (x), 0))
5400 return true;
5401 }
5402
5403 fmt = GET_RTX_FORMAT (code);
5404 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5405 {
5406 if (fmt[i] == 'e'
5407 && reg_used_in_mem_p (regno, XEXP (x, i)))
5408 return true;
5409
5410 else if (fmt[i] == 'E')
5411 for (j = 0; j < XVECLEN (x, i); j++)
5412 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5413 return true;
5414 }
5415 return false;
5416 }
5417
5418 /* Returns true if expression DEP_RTX sets an address register
5419 used by instruction INSN to address memory. */
5420
5421 static bool
5422 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5423 {
5424 rtx target, pat;
5425
5426 if (GET_CODE (dep_rtx) == INSN)
5427 dep_rtx = PATTERN (dep_rtx);
5428
5429 if (GET_CODE (dep_rtx) == SET)
5430 {
5431 target = SET_DEST (dep_rtx);
5432 if (GET_CODE (target) == STRICT_LOW_PART)
5433 target = XEXP (target, 0);
5434 while (GET_CODE (target) == SUBREG)
5435 target = SUBREG_REG (target);
5436
5437 if (GET_CODE (target) == REG)
5438 {
5439 int regno = REGNO (target);
5440
5441 if (s390_safe_attr_type (insn) == TYPE_LA)
5442 {
5443 pat = PATTERN (insn);
5444 if (GET_CODE (pat) == PARALLEL)
5445 {
5446 gcc_assert (XVECLEN (pat, 0) == 2);
5447 pat = XVECEXP (pat, 0, 0);
5448 }
5449 gcc_assert (GET_CODE (pat) == SET);
5450 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5451 }
5452 else if (get_attr_atype (insn) == ATYPE_AGEN)
5453 return reg_used_in_mem_p (regno, PATTERN (insn));
5454 }
5455 }
5456 return false;
5457 }
5458
5459 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5460
5461 int
5462 s390_agen_dep_p (rtx dep_insn, rtx insn)
5463 {
5464 rtx dep_rtx = PATTERN (dep_insn);
5465 int i;
5466
5467 if (GET_CODE (dep_rtx) == SET
5468 && addr_generation_dependency_p (dep_rtx, insn))
5469 return 1;
5470 else if (GET_CODE (dep_rtx) == PARALLEL)
5471 {
5472 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5473 {
5474 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5475 return 1;
5476 }
5477 }
5478 return 0;
5479 }
5480
5481
5482 /* A C statement (sans semicolon) to update the integer scheduling priority
5483 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5484 reduce the priority to execute INSN later. Do not define this macro if
5485 you do not need to adjust the scheduling priorities of insns.
5486
5487 A STD instruction should be scheduled earlier,
5488 in order to use the bypass. */
5489 static int
5490 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5491 {
5492 if (! INSN_P (insn))
5493 return priority;
5494
5495 if (s390_tune != PROCESSOR_2084_Z990
5496 && s390_tune != PROCESSOR_2094_Z9_109
5497 && s390_tune != PROCESSOR_2097_Z10
5498 && s390_tune != PROCESSOR_2817_Z196)
5499 return priority;
5500
5501 switch (s390_safe_attr_type (insn))
5502 {
5503 case TYPE_FSTOREDF:
5504 case TYPE_FSTORESF:
5505 priority = priority << 3;
5506 break;
5507 case TYPE_STORE:
5508 case TYPE_STM:
5509 priority = priority << 1;
5510 break;
5511 default:
5512 break;
5513 }
5514 return priority;
5515 }
5516
5517
5518 /* The number of instructions that can be issued per cycle. */
5519
5520 static int
5521 s390_issue_rate (void)
5522 {
5523 switch (s390_tune)
5524 {
5525 case PROCESSOR_2084_Z990:
5526 case PROCESSOR_2094_Z9_109:
5527 case PROCESSOR_2817_Z196:
5528 return 3;
5529 case PROCESSOR_2097_Z10:
5530 return 2;
5531 default:
5532 return 1;
5533 }
5534 }
5535
5536 static int
5537 s390_first_cycle_multipass_dfa_lookahead (void)
5538 {
5539 return 4;
5540 }
5541
5542 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5543 Fix up MEMs as required. */
5544
5545 static void
5546 annotate_constant_pool_refs (rtx *x)
5547 {
5548 int i, j;
5549 const char *fmt;
5550
5551 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5552 || !CONSTANT_POOL_ADDRESS_P (*x));
5553
5554 /* Literal pool references can only occur inside a MEM ... */
5555 if (GET_CODE (*x) == MEM)
5556 {
5557 rtx memref = XEXP (*x, 0);
5558
5559 if (GET_CODE (memref) == SYMBOL_REF
5560 && CONSTANT_POOL_ADDRESS_P (memref))
5561 {
5562 rtx base = cfun->machine->base_reg;
5563 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5564 UNSPEC_LTREF);
5565
5566 *x = replace_equiv_address (*x, addr);
5567 return;
5568 }
5569
5570 if (GET_CODE (memref) == CONST
5571 && GET_CODE (XEXP (memref, 0)) == PLUS
5572 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5573 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5574 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5575 {
5576 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5577 rtx sym = XEXP (XEXP (memref, 0), 0);
5578 rtx base = cfun->machine->base_reg;
5579 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5580 UNSPEC_LTREF);
5581
5582 *x = replace_equiv_address (*x, plus_constant (addr, off));
5583 return;
5584 }
5585 }
5586
5587 /* ... or a load-address type pattern. */
5588 if (GET_CODE (*x) == SET)
5589 {
5590 rtx addrref = SET_SRC (*x);
5591
5592 if (GET_CODE (addrref) == SYMBOL_REF
5593 && CONSTANT_POOL_ADDRESS_P (addrref))
5594 {
5595 rtx base = cfun->machine->base_reg;
5596 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5597 UNSPEC_LTREF);
5598
5599 SET_SRC (*x) = addr;
5600 return;
5601 }
5602
5603 if (GET_CODE (addrref) == CONST
5604 && GET_CODE (XEXP (addrref, 0)) == PLUS
5605 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5606 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5607 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5608 {
5609 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5610 rtx sym = XEXP (XEXP (addrref, 0), 0);
5611 rtx base = cfun->machine->base_reg;
5612 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5613 UNSPEC_LTREF);
5614
5615 SET_SRC (*x) = plus_constant (addr, off);
5616 return;
5617 }
5618 }
5619
5620 /* Annotate LTREL_BASE as well. */
5621 if (GET_CODE (*x) == UNSPEC
5622 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5623 {
5624 rtx base = cfun->machine->base_reg;
5625 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5626 UNSPEC_LTREL_BASE);
5627 return;
5628 }
5629
5630 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5631 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5632 {
5633 if (fmt[i] == 'e')
5634 {
5635 annotate_constant_pool_refs (&XEXP (*x, i));
5636 }
5637 else if (fmt[i] == 'E')
5638 {
5639 for (j = 0; j < XVECLEN (*x, i); j++)
5640 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5641 }
5642 }
5643 }
5644
5645 /* Split all branches that exceed the maximum distance.
5646 Returns true if this created a new literal pool entry. */
5647
5648 static int
5649 s390_split_branches (void)
5650 {
5651 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5652 int new_literal = 0, ret;
5653 rtx insn, pat, tmp, target;
5654 rtx *label;
5655
5656 /* We need correct insn addresses. */
5657
5658 shorten_branches (get_insns ());
5659
5660 /* Find all branches that exceed 64KB, and split them. */
5661
5662 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5663 {
5664 if (GET_CODE (insn) != JUMP_INSN)
5665 continue;
5666
5667 pat = PATTERN (insn);
5668 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5669 pat = XVECEXP (pat, 0, 0);
5670 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5671 continue;
5672
5673 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5674 {
5675 label = &SET_SRC (pat);
5676 }
5677 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5678 {
5679 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5680 label = &XEXP (SET_SRC (pat), 1);
5681 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5682 label = &XEXP (SET_SRC (pat), 2);
5683 else
5684 continue;
5685 }
5686 else
5687 continue;
5688
5689 if (get_attr_length (insn) <= 4)
5690 continue;
5691
5692 /* We are going to use the return register as scratch register,
5693 make sure it will be saved/restored by the prologue/epilogue. */
5694 cfun_frame_layout.save_return_addr_p = 1;
5695
5696 if (!flag_pic)
5697 {
5698 new_literal = 1;
5699 tmp = force_const_mem (Pmode, *label);
5700 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5701 INSN_ADDRESSES_NEW (tmp, -1);
5702 annotate_constant_pool_refs (&PATTERN (tmp));
5703
5704 target = temp_reg;
5705 }
5706 else
5707 {
5708 new_literal = 1;
5709 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5710 UNSPEC_LTREL_OFFSET);
5711 target = gen_rtx_CONST (Pmode, target);
5712 target = force_const_mem (Pmode, target);
5713 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5714 INSN_ADDRESSES_NEW (tmp, -1);
5715 annotate_constant_pool_refs (&PATTERN (tmp));
5716
5717 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5718 cfun->machine->base_reg),
5719 UNSPEC_LTREL_BASE);
5720 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5721 }
5722
5723 ret = validate_change (insn, label, target, 0);
5724 gcc_assert (ret);
5725 }
5726
5727 return new_literal;
5728 }
5729
5730
5731 /* Find an annotated literal pool symbol referenced in RTX X,
5732 and store it at REF. Will abort if X contains references to
5733 more than one such pool symbol; multiple references to the same
5734 symbol are allowed, however.
5735
5736 The rtx pointed to by REF must be initialized to NULL_RTX
5737 by the caller before calling this routine. */
5738
5739 static void
5740 find_constant_pool_ref (rtx x, rtx *ref)
5741 {
5742 int i, j;
5743 const char *fmt;
5744
5745 /* Ignore LTREL_BASE references. */
5746 if (GET_CODE (x) == UNSPEC
5747 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5748 return;
5749 /* Likewise POOL_ENTRY insns. */
5750 if (GET_CODE (x) == UNSPEC_VOLATILE
5751 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5752 return;
5753
5754 gcc_assert (GET_CODE (x) != SYMBOL_REF
5755 || !CONSTANT_POOL_ADDRESS_P (x));
5756
5757 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5758 {
5759 rtx sym = XVECEXP (x, 0, 0);
5760 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5761 && CONSTANT_POOL_ADDRESS_P (sym));
5762
5763 if (*ref == NULL_RTX)
5764 *ref = sym;
5765 else
5766 gcc_assert (*ref == sym);
5767
5768 return;
5769 }
5770
5771 fmt = GET_RTX_FORMAT (GET_CODE (x));
5772 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5773 {
5774 if (fmt[i] == 'e')
5775 {
5776 find_constant_pool_ref (XEXP (x, i), ref);
5777 }
5778 else if (fmt[i] == 'E')
5779 {
5780 for (j = 0; j < XVECLEN (x, i); j++)
5781 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5782 }
5783 }
5784 }
5785
5786 /* Replace every reference to the annotated literal pool
5787 symbol REF in X by its base plus OFFSET. */
5788
5789 static void
5790 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5791 {
5792 int i, j;
5793 const char *fmt;
5794
5795 gcc_assert (*x != ref);
5796
5797 if (GET_CODE (*x) == UNSPEC
5798 && XINT (*x, 1) == UNSPEC_LTREF
5799 && XVECEXP (*x, 0, 0) == ref)
5800 {
5801 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5802 return;
5803 }
5804
5805 if (GET_CODE (*x) == PLUS
5806 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5807 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5808 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5809 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5810 {
5811 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5812 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5813 return;
5814 }
5815
5816 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5817 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5818 {
5819 if (fmt[i] == 'e')
5820 {
5821 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5822 }
5823 else if (fmt[i] == 'E')
5824 {
5825 for (j = 0; j < XVECLEN (*x, i); j++)
5826 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5827 }
5828 }
5829 }
5830
5831 /* Check whether X contains an UNSPEC_LTREL_BASE.
5832 Return its constant pool symbol if found, NULL_RTX otherwise. */
5833
5834 static rtx
5835 find_ltrel_base (rtx x)
5836 {
5837 int i, j;
5838 const char *fmt;
5839
5840 if (GET_CODE (x) == UNSPEC
5841 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5842 return XVECEXP (x, 0, 0);
5843
5844 fmt = GET_RTX_FORMAT (GET_CODE (x));
5845 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5846 {
5847 if (fmt[i] == 'e')
5848 {
5849 rtx fnd = find_ltrel_base (XEXP (x, i));
5850 if (fnd)
5851 return fnd;
5852 }
5853 else if (fmt[i] == 'E')
5854 {
5855 for (j = 0; j < XVECLEN (x, i); j++)
5856 {
5857 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5858 if (fnd)
5859 return fnd;
5860 }
5861 }
5862 }
5863
5864 return NULL_RTX;
5865 }
5866
5867 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5868
5869 static void
5870 replace_ltrel_base (rtx *x)
5871 {
5872 int i, j;
5873 const char *fmt;
5874
5875 if (GET_CODE (*x) == UNSPEC
5876 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5877 {
5878 *x = XVECEXP (*x, 0, 1);
5879 return;
5880 }
5881
5882 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5883 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5884 {
5885 if (fmt[i] == 'e')
5886 {
5887 replace_ltrel_base (&XEXP (*x, i));
5888 }
5889 else if (fmt[i] == 'E')
5890 {
5891 for (j = 0; j < XVECLEN (*x, i); j++)
5892 replace_ltrel_base (&XVECEXP (*x, i, j));
5893 }
5894 }
5895 }
5896
5897
5898 /* We keep a list of constants which we have to add to internal
5899 constant tables in the middle of large functions. */
5900
5901 #define NR_C_MODES 11
5902 enum machine_mode constant_modes[NR_C_MODES] =
5903 {
5904 TFmode, TImode, TDmode,
5905 DFmode, DImode, DDmode,
5906 SFmode, SImode, SDmode,
5907 HImode,
5908 QImode
5909 };
5910
5911 struct constant
5912 {
5913 struct constant *next;
5914 rtx value;
5915 rtx label;
5916 };
5917
5918 struct constant_pool
5919 {
5920 struct constant_pool *next;
5921 rtx first_insn;
5922 rtx pool_insn;
5923 bitmap insns;
5924 rtx emit_pool_after;
5925
5926 struct constant *constants[NR_C_MODES];
5927 struct constant *execute;
5928 rtx label;
5929 int size;
5930 };
5931
5932 /* Allocate new constant_pool structure. */
5933
5934 static struct constant_pool *
5935 s390_alloc_pool (void)
5936 {
5937 struct constant_pool *pool;
5938 int i;
5939
5940 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5941 pool->next = NULL;
5942 for (i = 0; i < NR_C_MODES; i++)
5943 pool->constants[i] = NULL;
5944
5945 pool->execute = NULL;
5946 pool->label = gen_label_rtx ();
5947 pool->first_insn = NULL_RTX;
5948 pool->pool_insn = NULL_RTX;
5949 pool->insns = BITMAP_ALLOC (NULL);
5950 pool->size = 0;
5951 pool->emit_pool_after = NULL_RTX;
5952
5953 return pool;
5954 }
5955
5956 /* Create new constant pool covering instructions starting at INSN
5957 and chain it to the end of POOL_LIST. */
5958
5959 static struct constant_pool *
5960 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5961 {
5962 struct constant_pool *pool, **prev;
5963
5964 pool = s390_alloc_pool ();
5965 pool->first_insn = insn;
5966
5967 for (prev = pool_list; *prev; prev = &(*prev)->next)
5968 ;
5969 *prev = pool;
5970
5971 return pool;
5972 }
5973
5974 /* End range of instructions covered by POOL at INSN and emit
5975 placeholder insn representing the pool. */
5976
5977 static void
5978 s390_end_pool (struct constant_pool *pool, rtx insn)
5979 {
5980 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5981
5982 if (!insn)
5983 insn = get_last_insn ();
5984
5985 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5986 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5987 }
5988
5989 /* Add INSN to the list of insns covered by POOL. */
5990
5991 static void
5992 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5993 {
5994 bitmap_set_bit (pool->insns, INSN_UID (insn));
5995 }
5996
5997 /* Return pool out of POOL_LIST that covers INSN. */
5998
5999 static struct constant_pool *
6000 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6001 {
6002 struct constant_pool *pool;
6003
6004 for (pool = pool_list; pool; pool = pool->next)
6005 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6006 break;
6007
6008 return pool;
6009 }
6010
6011 /* Add constant VAL of mode MODE to the constant pool POOL. */
6012
6013 static void
6014 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6015 {
6016 struct constant *c;
6017 int i;
6018
6019 for (i = 0; i < NR_C_MODES; i++)
6020 if (constant_modes[i] == mode)
6021 break;
6022 gcc_assert (i != NR_C_MODES);
6023
6024 for (c = pool->constants[i]; c != NULL; c = c->next)
6025 if (rtx_equal_p (val, c->value))
6026 break;
6027
6028 if (c == NULL)
6029 {
6030 c = (struct constant *) xmalloc (sizeof *c);
6031 c->value = val;
6032 c->label = gen_label_rtx ();
6033 c->next = pool->constants[i];
6034 pool->constants[i] = c;
6035 pool->size += GET_MODE_SIZE (mode);
6036 }
6037 }
6038
6039 /* Return an rtx that represents the offset of X from the start of
6040 pool POOL. */
6041
6042 static rtx
6043 s390_pool_offset (struct constant_pool *pool, rtx x)
6044 {
6045 rtx label;
6046
6047 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6048 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6049 UNSPEC_POOL_OFFSET);
6050 return gen_rtx_CONST (GET_MODE (x), x);
6051 }
6052
6053 /* Find constant VAL of mode MODE in the constant pool POOL.
6054 Return an RTX describing the distance from the start of
6055 the pool to the location of the new constant. */
6056
6057 static rtx
6058 s390_find_constant (struct constant_pool *pool, rtx val,
6059 enum machine_mode mode)
6060 {
6061 struct constant *c;
6062 int i;
6063
6064 for (i = 0; i < NR_C_MODES; i++)
6065 if (constant_modes[i] == mode)
6066 break;
6067 gcc_assert (i != NR_C_MODES);
6068
6069 for (c = pool->constants[i]; c != NULL; c = c->next)
6070 if (rtx_equal_p (val, c->value))
6071 break;
6072
6073 gcc_assert (c);
6074
6075 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6076 }
6077
6078 /* Check whether INSN is an execute. Return the label_ref to its
6079 execute target template if so, NULL_RTX otherwise. */
6080
6081 static rtx
6082 s390_execute_label (rtx insn)
6083 {
6084 if (GET_CODE (insn) == INSN
6085 && GET_CODE (PATTERN (insn)) == PARALLEL
6086 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6087 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6088 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6089
6090 return NULL_RTX;
6091 }
6092
6093 /* Add execute target for INSN to the constant pool POOL. */
6094
6095 static void
6096 s390_add_execute (struct constant_pool *pool, rtx insn)
6097 {
6098 struct constant *c;
6099
6100 for (c = pool->execute; c != NULL; c = c->next)
6101 if (INSN_UID (insn) == INSN_UID (c->value))
6102 break;
6103
6104 if (c == NULL)
6105 {
6106 c = (struct constant *) xmalloc (sizeof *c);
6107 c->value = insn;
6108 c->label = gen_label_rtx ();
6109 c->next = pool->execute;
6110 pool->execute = c;
6111 pool->size += 6;
6112 }
6113 }
6114
6115 /* Find execute target for INSN in the constant pool POOL.
6116 Return an RTX describing the distance from the start of
6117 the pool to the location of the execute target. */
6118
6119 static rtx
6120 s390_find_execute (struct constant_pool *pool, rtx insn)
6121 {
6122 struct constant *c;
6123
6124 for (c = pool->execute; c != NULL; c = c->next)
6125 if (INSN_UID (insn) == INSN_UID (c->value))
6126 break;
6127
6128 gcc_assert (c);
6129
6130 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6131 }
6132
6133 /* For an execute INSN, extract the execute target template. */
6134
6135 static rtx
6136 s390_execute_target (rtx insn)
6137 {
6138 rtx pattern = PATTERN (insn);
6139 gcc_assert (s390_execute_label (insn));
6140
6141 if (XVECLEN (pattern, 0) == 2)
6142 {
6143 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6144 }
6145 else
6146 {
6147 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6148 int i;
6149
6150 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6151 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6152
6153 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6154 }
6155
6156 return pattern;
6157 }
6158
6159 /* Indicate that INSN cannot be duplicated. This is the case for
6160 execute insns that carry a unique label. */
6161
6162 static bool
6163 s390_cannot_copy_insn_p (rtx insn)
6164 {
6165 rtx label = s390_execute_label (insn);
6166 return label && label != const0_rtx;
6167 }
6168
6169 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6170 do not emit the pool base label. */
6171
6172 static void
6173 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6174 {
6175 struct constant *c;
6176 rtx insn = pool->pool_insn;
6177 int i;
6178
6179 /* Switch to rodata section. */
6180 if (TARGET_CPU_ZARCH)
6181 {
6182 insn = emit_insn_after (gen_pool_section_start (), insn);
6183 INSN_ADDRESSES_NEW (insn, -1);
6184 }
6185
6186 /* Ensure minimum pool alignment. */
6187 if (TARGET_CPU_ZARCH)
6188 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6189 else
6190 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6191 INSN_ADDRESSES_NEW (insn, -1);
6192
6193 /* Emit pool base label. */
6194 if (!remote_label)
6195 {
6196 insn = emit_label_after (pool->label, insn);
6197 INSN_ADDRESSES_NEW (insn, -1);
6198 }
6199
6200 /* Dump constants in descending alignment requirement order,
6201 ensuring proper alignment for every constant. */
6202 for (i = 0; i < NR_C_MODES; i++)
6203 for (c = pool->constants[i]; c; c = c->next)
6204 {
6205 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6206 rtx value = copy_rtx (c->value);
6207 if (GET_CODE (value) == CONST
6208 && GET_CODE (XEXP (value, 0)) == UNSPEC
6209 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6210 && XVECLEN (XEXP (value, 0), 0) == 1)
6211 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6212
6213 insn = emit_label_after (c->label, insn);
6214 INSN_ADDRESSES_NEW (insn, -1);
6215
6216 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6217 gen_rtvec (1, value),
6218 UNSPECV_POOL_ENTRY);
6219 insn = emit_insn_after (value, insn);
6220 INSN_ADDRESSES_NEW (insn, -1);
6221 }
6222
6223 /* Ensure minimum alignment for instructions. */
6224 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6225 INSN_ADDRESSES_NEW (insn, -1);
6226
6227 /* Output in-pool execute template insns. */
6228 for (c = pool->execute; c; c = c->next)
6229 {
6230 insn = emit_label_after (c->label, insn);
6231 INSN_ADDRESSES_NEW (insn, -1);
6232
6233 insn = emit_insn_after (s390_execute_target (c->value), insn);
6234 INSN_ADDRESSES_NEW (insn, -1);
6235 }
6236
6237 /* Switch back to previous section. */
6238 if (TARGET_CPU_ZARCH)
6239 {
6240 insn = emit_insn_after (gen_pool_section_end (), insn);
6241 INSN_ADDRESSES_NEW (insn, -1);
6242 }
6243
6244 insn = emit_barrier_after (insn);
6245 INSN_ADDRESSES_NEW (insn, -1);
6246
6247 /* Remove placeholder insn. */
6248 remove_insn (pool->pool_insn);
6249 }
6250
6251 /* Free all memory used by POOL. */
6252
6253 static void
6254 s390_free_pool (struct constant_pool *pool)
6255 {
6256 struct constant *c, *next;
6257 int i;
6258
6259 for (i = 0; i < NR_C_MODES; i++)
6260 for (c = pool->constants[i]; c; c = next)
6261 {
6262 next = c->next;
6263 free (c);
6264 }
6265
6266 for (c = pool->execute; c; c = next)
6267 {
6268 next = c->next;
6269 free (c);
6270 }
6271
6272 BITMAP_FREE (pool->insns);
6273 free (pool);
6274 }
6275
6276
6277 /* Collect main literal pool. Return NULL on overflow. */
6278
6279 static struct constant_pool *
6280 s390_mainpool_start (void)
6281 {
6282 struct constant_pool *pool;
6283 rtx insn;
6284
6285 pool = s390_alloc_pool ();
6286
6287 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6288 {
6289 if (GET_CODE (insn) == INSN
6290 && GET_CODE (PATTERN (insn)) == SET
6291 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6292 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6293 {
6294 gcc_assert (!pool->pool_insn);
6295 pool->pool_insn = insn;
6296 }
6297
6298 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6299 {
6300 s390_add_execute (pool, insn);
6301 }
6302 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6303 {
6304 rtx pool_ref = NULL_RTX;
6305 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6306 if (pool_ref)
6307 {
6308 rtx constant = get_pool_constant (pool_ref);
6309 enum machine_mode mode = get_pool_mode (pool_ref);
6310 s390_add_constant (pool, constant, mode);
6311 }
6312 }
6313
6314 /* If hot/cold partitioning is enabled we have to make sure that
6315 the literal pool is emitted in the same section where the
6316 initialization of the literal pool base pointer takes place.
6317 emit_pool_after is only used in the non-overflow case on non
6318 Z cpus where we can emit the literal pool at the end of the
6319 function body within the text section. */
6320 if (NOTE_P (insn)
6321 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6322 && !pool->emit_pool_after)
6323 pool->emit_pool_after = PREV_INSN (insn);
6324 }
6325
6326 gcc_assert (pool->pool_insn || pool->size == 0);
6327
6328 if (pool->size >= 4096)
6329 {
6330 /* We're going to chunkify the pool, so remove the main
6331 pool placeholder insn. */
6332 remove_insn (pool->pool_insn);
6333
6334 s390_free_pool (pool);
6335 pool = NULL;
6336 }
6337
6338 /* If the functions ends with the section where the literal pool
6339 should be emitted set the marker to its end. */
6340 if (pool && !pool->emit_pool_after)
6341 pool->emit_pool_after = get_last_insn ();
6342
6343 return pool;
6344 }
6345
6346 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6347 Modify the current function to output the pool constants as well as
6348 the pool register setup instruction. */
6349
6350 static void
6351 s390_mainpool_finish (struct constant_pool *pool)
6352 {
6353 rtx base_reg = cfun->machine->base_reg;
6354 rtx insn;
6355
6356 /* If the pool is empty, we're done. */
6357 if (pool->size == 0)
6358 {
6359 /* We don't actually need a base register after all. */
6360 cfun->machine->base_reg = NULL_RTX;
6361
6362 if (pool->pool_insn)
6363 remove_insn (pool->pool_insn);
6364 s390_free_pool (pool);
6365 return;
6366 }
6367
6368 /* We need correct insn addresses. */
6369 shorten_branches (get_insns ());
6370
6371 /* On zSeries, we use a LARL to load the pool register. The pool is
6372 located in the .rodata section, so we emit it after the function. */
6373 if (TARGET_CPU_ZARCH)
6374 {
6375 insn = gen_main_base_64 (base_reg, pool->label);
6376 insn = emit_insn_after (insn, pool->pool_insn);
6377 INSN_ADDRESSES_NEW (insn, -1);
6378 remove_insn (pool->pool_insn);
6379
6380 insn = get_last_insn ();
6381 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6382 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6383
6384 s390_dump_pool (pool, 0);
6385 }
6386
6387 /* On S/390, if the total size of the function's code plus literal pool
6388 does not exceed 4096 bytes, we use BASR to set up a function base
6389 pointer, and emit the literal pool at the end of the function. */
6390 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6391 + pool->size + 8 /* alignment slop */ < 4096)
6392 {
6393 insn = gen_main_base_31_small (base_reg, pool->label);
6394 insn = emit_insn_after (insn, pool->pool_insn);
6395 INSN_ADDRESSES_NEW (insn, -1);
6396 remove_insn (pool->pool_insn);
6397
6398 insn = emit_label_after (pool->label, insn);
6399 INSN_ADDRESSES_NEW (insn, -1);
6400
6401 /* emit_pool_after will be set by s390_mainpool_start to the
6402 last insn of the section where the literal pool should be
6403 emitted. */
6404 insn = pool->emit_pool_after;
6405
6406 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6407 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6408
6409 s390_dump_pool (pool, 1);
6410 }
6411
6412 /* Otherwise, we emit an inline literal pool and use BASR to branch
6413 over it, setting up the pool register at the same time. */
6414 else
6415 {
6416 rtx pool_end = gen_label_rtx ();
6417
6418 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6419 insn = emit_insn_after (insn, pool->pool_insn);
6420 INSN_ADDRESSES_NEW (insn, -1);
6421 remove_insn (pool->pool_insn);
6422
6423 insn = emit_label_after (pool->label, insn);
6424 INSN_ADDRESSES_NEW (insn, -1);
6425
6426 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6427 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6428
6429 insn = emit_label_after (pool_end, pool->pool_insn);
6430 INSN_ADDRESSES_NEW (insn, -1);
6431
6432 s390_dump_pool (pool, 1);
6433 }
6434
6435
6436 /* Replace all literal pool references. */
6437
6438 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6439 {
6440 if (INSN_P (insn))
6441 replace_ltrel_base (&PATTERN (insn));
6442
6443 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6444 {
6445 rtx addr, pool_ref = NULL_RTX;
6446 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6447 if (pool_ref)
6448 {
6449 if (s390_execute_label (insn))
6450 addr = s390_find_execute (pool, insn);
6451 else
6452 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6453 get_pool_mode (pool_ref));
6454
6455 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6456 INSN_CODE (insn) = -1;
6457 }
6458 }
6459 }
6460
6461
6462 /* Free the pool. */
6463 s390_free_pool (pool);
6464 }
6465
6466 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6467 We have decided we cannot use this pool, so revert all changes
6468 to the current function that were done by s390_mainpool_start. */
6469 static void
6470 s390_mainpool_cancel (struct constant_pool *pool)
6471 {
6472 /* We didn't actually change the instruction stream, so simply
6473 free the pool memory. */
6474 s390_free_pool (pool);
6475 }
6476
6477
6478 /* Chunkify the literal pool. */
6479
6480 #define S390_POOL_CHUNK_MIN 0xc00
6481 #define S390_POOL_CHUNK_MAX 0xe00
6482
6483 static struct constant_pool *
6484 s390_chunkify_start (void)
6485 {
6486 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6487 int extra_size = 0;
6488 bitmap far_labels;
6489 rtx pending_ltrel = NULL_RTX;
6490 rtx insn;
6491
6492 rtx (*gen_reload_base) (rtx, rtx) =
6493 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6494
6495
6496 /* We need correct insn addresses. */
6497
6498 shorten_branches (get_insns ());
6499
6500 /* Scan all insns and move literals to pool chunks. */
6501
6502 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6503 {
6504 bool section_switch_p = false;
6505
6506 /* Check for pending LTREL_BASE. */
6507 if (INSN_P (insn))
6508 {
6509 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6510 if (ltrel_base)
6511 {
6512 gcc_assert (ltrel_base == pending_ltrel);
6513 pending_ltrel = NULL_RTX;
6514 }
6515 }
6516
6517 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6518 {
6519 if (!curr_pool)
6520 curr_pool = s390_start_pool (&pool_list, insn);
6521
6522 s390_add_execute (curr_pool, insn);
6523 s390_add_pool_insn (curr_pool, insn);
6524 }
6525 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6526 {
6527 rtx pool_ref = NULL_RTX;
6528 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6529 if (pool_ref)
6530 {
6531 rtx constant = get_pool_constant (pool_ref);
6532 enum machine_mode mode = get_pool_mode (pool_ref);
6533
6534 if (!curr_pool)
6535 curr_pool = s390_start_pool (&pool_list, insn);
6536
6537 s390_add_constant (curr_pool, constant, mode);
6538 s390_add_pool_insn (curr_pool, insn);
6539
6540 /* Don't split the pool chunk between a LTREL_OFFSET load
6541 and the corresponding LTREL_BASE. */
6542 if (GET_CODE (constant) == CONST
6543 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6544 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6545 {
6546 gcc_assert (!pending_ltrel);
6547 pending_ltrel = pool_ref;
6548 }
6549 }
6550 }
6551
6552 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6553 {
6554 if (curr_pool)
6555 s390_add_pool_insn (curr_pool, insn);
6556 /* An LTREL_BASE must follow within the same basic block. */
6557 gcc_assert (!pending_ltrel);
6558 }
6559
6560 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6561 section_switch_p = true;
6562
6563 if (!curr_pool
6564 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6565 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6566 continue;
6567
6568 if (TARGET_CPU_ZARCH)
6569 {
6570 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6571 continue;
6572
6573 s390_end_pool (curr_pool, NULL_RTX);
6574 curr_pool = NULL;
6575 }
6576 else
6577 {
6578 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6579 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6580 + extra_size;
6581
6582 /* We will later have to insert base register reload insns.
6583 Those will have an effect on code size, which we need to
6584 consider here. This calculation makes rather pessimistic
6585 worst-case assumptions. */
6586 if (GET_CODE (insn) == CODE_LABEL)
6587 extra_size += 6;
6588
6589 if (chunk_size < S390_POOL_CHUNK_MIN
6590 && curr_pool->size < S390_POOL_CHUNK_MIN
6591 && !section_switch_p)
6592 continue;
6593
6594 /* Pool chunks can only be inserted after BARRIERs ... */
6595 if (GET_CODE (insn) == BARRIER)
6596 {
6597 s390_end_pool (curr_pool, insn);
6598 curr_pool = NULL;
6599 extra_size = 0;
6600 }
6601
6602 /* ... so if we don't find one in time, create one. */
6603 else if (chunk_size > S390_POOL_CHUNK_MAX
6604 || curr_pool->size > S390_POOL_CHUNK_MAX
6605 || section_switch_p)
6606 {
6607 rtx label, jump, barrier;
6608
6609 if (!section_switch_p)
6610 {
6611 /* We can insert the barrier only after a 'real' insn. */
6612 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6613 continue;
6614 if (get_attr_length (insn) == 0)
6615 continue;
6616 /* Don't separate LTREL_BASE from the corresponding
6617 LTREL_OFFSET load. */
6618 if (pending_ltrel)
6619 continue;
6620 }
6621 else
6622 {
6623 gcc_assert (!pending_ltrel);
6624
6625 /* The old pool has to end before the section switch
6626 note in order to make it part of the current
6627 section. */
6628 insn = PREV_INSN (insn);
6629 }
6630
6631 label = gen_label_rtx ();
6632 jump = emit_jump_insn_after (gen_jump (label), insn);
6633 barrier = emit_barrier_after (jump);
6634 insn = emit_label_after (label, barrier);
6635 JUMP_LABEL (jump) = label;
6636 LABEL_NUSES (label) = 1;
6637
6638 INSN_ADDRESSES_NEW (jump, -1);
6639 INSN_ADDRESSES_NEW (barrier, -1);
6640 INSN_ADDRESSES_NEW (insn, -1);
6641
6642 s390_end_pool (curr_pool, barrier);
6643 curr_pool = NULL;
6644 extra_size = 0;
6645 }
6646 }
6647 }
6648
6649 if (curr_pool)
6650 s390_end_pool (curr_pool, NULL_RTX);
6651 gcc_assert (!pending_ltrel);
6652
6653 /* Find all labels that are branched into
6654 from an insn belonging to a different chunk. */
6655
6656 far_labels = BITMAP_ALLOC (NULL);
6657
6658 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6659 {
6660 /* Labels marked with LABEL_PRESERVE_P can be target
6661 of non-local jumps, so we have to mark them.
6662 The same holds for named labels.
6663
6664 Don't do that, however, if it is the label before
6665 a jump table. */
6666
6667 if (GET_CODE (insn) == CODE_LABEL
6668 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6669 {
6670 rtx vec_insn = next_real_insn (insn);
6671 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6672 PATTERN (vec_insn) : NULL_RTX;
6673 if (!vec_pat
6674 || !(GET_CODE (vec_pat) == ADDR_VEC
6675 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6676 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6677 }
6678
6679 /* If we have a direct jump (conditional or unconditional)
6680 or a casesi jump, check all potential targets. */
6681 else if (GET_CODE (insn) == JUMP_INSN)
6682 {
6683 rtx pat = PATTERN (insn);
6684 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6685 pat = XVECEXP (pat, 0, 0);
6686
6687 if (GET_CODE (pat) == SET)
6688 {
6689 rtx label = JUMP_LABEL (insn);
6690 if (label)
6691 {
6692 if (s390_find_pool (pool_list, label)
6693 != s390_find_pool (pool_list, insn))
6694 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6695 }
6696 }
6697 else if (GET_CODE (pat) == PARALLEL
6698 && XVECLEN (pat, 0) == 2
6699 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6700 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6701 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6702 {
6703 /* Find the jump table used by this casesi jump. */
6704 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6705 rtx vec_insn = next_real_insn (vec_label);
6706 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6707 PATTERN (vec_insn) : NULL_RTX;
6708 if (vec_pat
6709 && (GET_CODE (vec_pat) == ADDR_VEC
6710 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6711 {
6712 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6713
6714 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6715 {
6716 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6717
6718 if (s390_find_pool (pool_list, label)
6719 != s390_find_pool (pool_list, insn))
6720 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6721 }
6722 }
6723 }
6724 }
6725 }
6726
6727 /* Insert base register reload insns before every pool. */
6728
6729 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6730 {
6731 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6732 curr_pool->label);
6733 rtx insn = curr_pool->first_insn;
6734 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6735 }
6736
6737 /* Insert base register reload insns at every far label. */
6738
6739 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6740 if (GET_CODE (insn) == CODE_LABEL
6741 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6742 {
6743 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6744 if (pool)
6745 {
6746 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6747 pool->label);
6748 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6749 }
6750 }
6751
6752
6753 BITMAP_FREE (far_labels);
6754
6755
6756 /* Recompute insn addresses. */
6757
6758 init_insn_lengths ();
6759 shorten_branches (get_insns ());
6760
6761 return pool_list;
6762 }
6763
6764 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6765 After we have decided to use this list, finish implementing
6766 all changes to the current function as required. */
6767
6768 static void
6769 s390_chunkify_finish (struct constant_pool *pool_list)
6770 {
6771 struct constant_pool *curr_pool = NULL;
6772 rtx insn;
6773
6774
6775 /* Replace all literal pool references. */
6776
6777 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6778 {
6779 if (INSN_P (insn))
6780 replace_ltrel_base (&PATTERN (insn));
6781
6782 curr_pool = s390_find_pool (pool_list, insn);
6783 if (!curr_pool)
6784 continue;
6785
6786 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6787 {
6788 rtx addr, pool_ref = NULL_RTX;
6789 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6790 if (pool_ref)
6791 {
6792 if (s390_execute_label (insn))
6793 addr = s390_find_execute (curr_pool, insn);
6794 else
6795 addr = s390_find_constant (curr_pool,
6796 get_pool_constant (pool_ref),
6797 get_pool_mode (pool_ref));
6798
6799 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6800 INSN_CODE (insn) = -1;
6801 }
6802 }
6803 }
6804
6805 /* Dump out all literal pools. */
6806
6807 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6808 s390_dump_pool (curr_pool, 0);
6809
6810 /* Free pool list. */
6811
6812 while (pool_list)
6813 {
6814 struct constant_pool *next = pool_list->next;
6815 s390_free_pool (pool_list);
6816 pool_list = next;
6817 }
6818 }
6819
6820 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6821 We have decided we cannot use this list, so revert all changes
6822 to the current function that were done by s390_chunkify_start. */
6823
6824 static void
6825 s390_chunkify_cancel (struct constant_pool *pool_list)
6826 {
6827 struct constant_pool *curr_pool = NULL;
6828 rtx insn;
6829
6830 /* Remove all pool placeholder insns. */
6831
6832 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6833 {
6834 /* Did we insert an extra barrier? Remove it. */
6835 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6836 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6837 rtx label = NEXT_INSN (curr_pool->pool_insn);
6838
6839 if (jump && GET_CODE (jump) == JUMP_INSN
6840 && barrier && GET_CODE (barrier) == BARRIER
6841 && label && GET_CODE (label) == CODE_LABEL
6842 && GET_CODE (PATTERN (jump)) == SET
6843 && SET_DEST (PATTERN (jump)) == pc_rtx
6844 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6845 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6846 {
6847 remove_insn (jump);
6848 remove_insn (barrier);
6849 remove_insn (label);
6850 }
6851
6852 remove_insn (curr_pool->pool_insn);
6853 }
6854
6855 /* Remove all base register reload insns. */
6856
6857 for (insn = get_insns (); insn; )
6858 {
6859 rtx next_insn = NEXT_INSN (insn);
6860
6861 if (GET_CODE (insn) == INSN
6862 && GET_CODE (PATTERN (insn)) == SET
6863 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6864 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6865 remove_insn (insn);
6866
6867 insn = next_insn;
6868 }
6869
6870 /* Free pool list. */
6871
6872 while (pool_list)
6873 {
6874 struct constant_pool *next = pool_list->next;
6875 s390_free_pool (pool_list);
6876 pool_list = next;
6877 }
6878 }
6879
6880 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6881
6882 void
6883 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6884 {
6885 REAL_VALUE_TYPE r;
6886
6887 switch (GET_MODE_CLASS (mode))
6888 {
6889 case MODE_FLOAT:
6890 case MODE_DECIMAL_FLOAT:
6891 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6892
6893 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6894 assemble_real (r, mode, align);
6895 break;
6896
6897 case MODE_INT:
6898 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6899 mark_symbol_refs_as_used (exp);
6900 break;
6901
6902 default:
6903 gcc_unreachable ();
6904 }
6905 }
6906
6907
6908 /* Return an RTL expression representing the value of the return address
6909 for the frame COUNT steps up from the current frame. FRAME is the
6910 frame pointer of that frame. */
6911
6912 rtx
6913 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6914 {
6915 int offset;
6916 rtx addr;
6917
6918 /* Without backchain, we fail for all but the current frame. */
6919
6920 if (!TARGET_BACKCHAIN && count > 0)
6921 return NULL_RTX;
6922
6923 /* For the current frame, we need to make sure the initial
6924 value of RETURN_REGNUM is actually saved. */
6925
6926 if (count == 0)
6927 {
6928 /* On non-z architectures branch splitting could overwrite r14. */
6929 if (TARGET_CPU_ZARCH)
6930 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6931 else
6932 {
6933 cfun_frame_layout.save_return_addr_p = true;
6934 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6935 }
6936 }
6937
6938 if (TARGET_PACKED_STACK)
6939 offset = -2 * UNITS_PER_LONG;
6940 else
6941 offset = RETURN_REGNUM * UNITS_PER_LONG;
6942
6943 addr = plus_constant (frame, offset);
6944 addr = memory_address (Pmode, addr);
6945 return gen_rtx_MEM (Pmode, addr);
6946 }
6947
6948 /* Return an RTL expression representing the back chain stored in
6949 the current stack frame. */
6950
6951 rtx
6952 s390_back_chain_rtx (void)
6953 {
6954 rtx chain;
6955
6956 gcc_assert (TARGET_BACKCHAIN);
6957
6958 if (TARGET_PACKED_STACK)
6959 chain = plus_constant (stack_pointer_rtx,
6960 STACK_POINTER_OFFSET - UNITS_PER_LONG);
6961 else
6962 chain = stack_pointer_rtx;
6963
6964 chain = gen_rtx_MEM (Pmode, chain);
6965 return chain;
6966 }
6967
6968 /* Find first call clobbered register unused in a function.
6969 This could be used as base register in a leaf function
6970 or for holding the return address before epilogue. */
6971
6972 static int
6973 find_unused_clobbered_reg (void)
6974 {
6975 int i;
6976 for (i = 0; i < 6; i++)
6977 if (!df_regs_ever_live_p (i))
6978 return i;
6979 return 0;
6980 }
6981
6982
6983 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6984 clobbered hard regs in SETREG. */
6985
6986 static void
6987 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6988 {
6989 int *regs_ever_clobbered = (int *)data;
6990 unsigned int i, regno;
6991 enum machine_mode mode = GET_MODE (setreg);
6992
6993 if (GET_CODE (setreg) == SUBREG)
6994 {
6995 rtx inner = SUBREG_REG (setreg);
6996 if (!GENERAL_REG_P (inner))
6997 return;
6998 regno = subreg_regno (setreg);
6999 }
7000 else if (GENERAL_REG_P (setreg))
7001 regno = REGNO (setreg);
7002 else
7003 return;
7004
7005 for (i = regno;
7006 i < regno + HARD_REGNO_NREGS (regno, mode);
7007 i++)
7008 regs_ever_clobbered[i] = 1;
7009 }
7010
7011 /* Walks through all basic blocks of the current function looking
7012 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7013 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7014 each of those regs. */
7015
7016 static void
7017 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7018 {
7019 basic_block cur_bb;
7020 rtx cur_insn;
7021 unsigned int i;
7022
7023 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7024
7025 /* For non-leaf functions we have to consider all call clobbered regs to be
7026 clobbered. */
7027 if (!current_function_is_leaf)
7028 {
7029 for (i = 0; i < 16; i++)
7030 regs_ever_clobbered[i] = call_really_used_regs[i];
7031 }
7032
7033 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7034 this work is done by liveness analysis (mark_regs_live_at_end).
7035 Special care is needed for functions containing landing pads. Landing pads
7036 may use the eh registers, but the code which sets these registers is not
7037 contained in that function. Hence s390_regs_ever_clobbered is not able to
7038 deal with this automatically. */
7039 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7040 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7041 if (crtl->calls_eh_return
7042 || (cfun->machine->has_landing_pad_p
7043 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7044 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7045
7046 /* For nonlocal gotos all call-saved registers have to be saved.
7047 This flag is also set for the unwinding code in libgcc.
7048 See expand_builtin_unwind_init. For regs_ever_live this is done by
7049 reload. */
7050 if (cfun->has_nonlocal_label)
7051 for (i = 0; i < 16; i++)
7052 if (!call_really_used_regs[i])
7053 regs_ever_clobbered[i] = 1;
7054
7055 FOR_EACH_BB (cur_bb)
7056 {
7057 FOR_BB_INSNS (cur_bb, cur_insn)
7058 {
7059 if (INSN_P (cur_insn))
7060 note_stores (PATTERN (cur_insn),
7061 s390_reg_clobbered_rtx,
7062 regs_ever_clobbered);
7063 }
7064 }
7065 }
7066
7067 /* Determine the frame area which actually has to be accessed
7068 in the function epilogue. The values are stored at the
7069 given pointers AREA_BOTTOM (address of the lowest used stack
7070 address) and AREA_TOP (address of the first item which does
7071 not belong to the stack frame). */
7072
7073 static void
7074 s390_frame_area (int *area_bottom, int *area_top)
7075 {
7076 int b, t;
7077 int i;
7078
7079 b = INT_MAX;
7080 t = INT_MIN;
7081
7082 if (cfun_frame_layout.first_restore_gpr != -1)
7083 {
7084 b = (cfun_frame_layout.gprs_offset
7085 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7086 t = b + (cfun_frame_layout.last_restore_gpr
7087 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7088 }
7089
7090 if (TARGET_64BIT && cfun_save_high_fprs_p)
7091 {
7092 b = MIN (b, cfun_frame_layout.f8_offset);
7093 t = MAX (t, (cfun_frame_layout.f8_offset
7094 + cfun_frame_layout.high_fprs * 8));
7095 }
7096
7097 if (!TARGET_64BIT)
7098 for (i = 2; i < 4; i++)
7099 if (cfun_fpr_bit_p (i))
7100 {
7101 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7102 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7103 }
7104
7105 *area_bottom = b;
7106 *area_top = t;
7107 }
7108
7109 /* Fill cfun->machine with info about register usage of current function.
7110 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7111
7112 static void
7113 s390_register_info (int clobbered_regs[])
7114 {
7115 int i, j;
7116
7117 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7118 cfun_frame_layout.fpr_bitmap = 0;
7119 cfun_frame_layout.high_fprs = 0;
7120 if (TARGET_64BIT)
7121 for (i = 24; i < 32; i++)
7122 if (df_regs_ever_live_p (i) && !global_regs[i])
7123 {
7124 cfun_set_fpr_bit (i - 16);
7125 cfun_frame_layout.high_fprs++;
7126 }
7127
7128 /* Find first and last gpr to be saved. We trust regs_ever_live
7129 data, except that we don't save and restore global registers.
7130
7131 Also, all registers with special meaning to the compiler need
7132 to be handled extra. */
7133
7134 s390_regs_ever_clobbered (clobbered_regs);
7135
7136 for (i = 0; i < 16; i++)
7137 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7138
7139 if (frame_pointer_needed)
7140 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7141
7142 if (flag_pic)
7143 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7144 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7145
7146 clobbered_regs[BASE_REGNUM]
7147 |= (cfun->machine->base_reg
7148 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7149
7150 clobbered_regs[RETURN_REGNUM]
7151 |= (!current_function_is_leaf
7152 || TARGET_TPF_PROFILING
7153 || cfun->machine->split_branches_pending_p
7154 || cfun_frame_layout.save_return_addr_p
7155 || crtl->calls_eh_return
7156 || cfun->stdarg);
7157
7158 clobbered_regs[STACK_POINTER_REGNUM]
7159 |= (!current_function_is_leaf
7160 || TARGET_TPF_PROFILING
7161 || cfun_save_high_fprs_p
7162 || get_frame_size () > 0
7163 || cfun->calls_alloca
7164 || cfun->stdarg);
7165
7166 for (i = 6; i < 16; i++)
7167 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7168 break;
7169 for (j = 15; j > i; j--)
7170 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7171 break;
7172
7173 if (i == 16)
7174 {
7175 /* Nothing to save/restore. */
7176 cfun_frame_layout.first_save_gpr_slot = -1;
7177 cfun_frame_layout.last_save_gpr_slot = -1;
7178 cfun_frame_layout.first_save_gpr = -1;
7179 cfun_frame_layout.first_restore_gpr = -1;
7180 cfun_frame_layout.last_save_gpr = -1;
7181 cfun_frame_layout.last_restore_gpr = -1;
7182 }
7183 else
7184 {
7185 /* Save slots for gprs from i to j. */
7186 cfun_frame_layout.first_save_gpr_slot = i;
7187 cfun_frame_layout.last_save_gpr_slot = j;
7188
7189 for (i = cfun_frame_layout.first_save_gpr_slot;
7190 i < cfun_frame_layout.last_save_gpr_slot + 1;
7191 i++)
7192 if (clobbered_regs[i])
7193 break;
7194
7195 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7196 if (clobbered_regs[j])
7197 break;
7198
7199 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7200 {
7201 /* Nothing to save/restore. */
7202 cfun_frame_layout.first_save_gpr = -1;
7203 cfun_frame_layout.first_restore_gpr = -1;
7204 cfun_frame_layout.last_save_gpr = -1;
7205 cfun_frame_layout.last_restore_gpr = -1;
7206 }
7207 else
7208 {
7209 /* Save / Restore from gpr i to j. */
7210 cfun_frame_layout.first_save_gpr = i;
7211 cfun_frame_layout.first_restore_gpr = i;
7212 cfun_frame_layout.last_save_gpr = j;
7213 cfun_frame_layout.last_restore_gpr = j;
7214 }
7215 }
7216
7217 if (cfun->stdarg)
7218 {
7219 /* Varargs functions need to save gprs 2 to 6. */
7220 if (cfun->va_list_gpr_size
7221 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7222 {
7223 int min_gpr = crtl->args.info.gprs;
7224 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7225 if (max_gpr > GP_ARG_NUM_REG)
7226 max_gpr = GP_ARG_NUM_REG;
7227
7228 if (cfun_frame_layout.first_save_gpr == -1
7229 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7230 {
7231 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7232 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7233 }
7234
7235 if (cfun_frame_layout.last_save_gpr == -1
7236 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7237 {
7238 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7239 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7240 }
7241 }
7242
7243 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7244 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7245 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7246 {
7247 int min_fpr = crtl->args.info.fprs;
7248 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7249 if (max_fpr > FP_ARG_NUM_REG)
7250 max_fpr = FP_ARG_NUM_REG;
7251
7252 /* ??? This is currently required to ensure proper location
7253 of the fpr save slots within the va_list save area. */
7254 if (TARGET_PACKED_STACK)
7255 min_fpr = 0;
7256
7257 for (i = min_fpr; i < max_fpr; i++)
7258 cfun_set_fpr_bit (i);
7259 }
7260 }
7261
7262 if (!TARGET_64BIT)
7263 for (i = 2; i < 4; i++)
7264 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7265 cfun_set_fpr_bit (i);
7266 }
7267
7268 /* Fill cfun->machine with info about frame of current function. */
7269
7270 static void
7271 s390_frame_info (void)
7272 {
7273 int i;
7274
7275 cfun_frame_layout.frame_size = get_frame_size ();
7276 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7277 fatal_error ("total size of local variables exceeds architecture limit");
7278
7279 if (!TARGET_PACKED_STACK)
7280 {
7281 cfun_frame_layout.backchain_offset = 0;
7282 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7283 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7284 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7285 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7286 * UNITS_PER_LONG);
7287 }
7288 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7289 {
7290 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7291 - UNITS_PER_LONG);
7292 cfun_frame_layout.gprs_offset
7293 = (cfun_frame_layout.backchain_offset
7294 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7295 * UNITS_PER_LONG);
7296
7297 if (TARGET_64BIT)
7298 {
7299 cfun_frame_layout.f4_offset
7300 = (cfun_frame_layout.gprs_offset
7301 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7302
7303 cfun_frame_layout.f0_offset
7304 = (cfun_frame_layout.f4_offset
7305 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7306 }
7307 else
7308 {
7309 /* On 31 bit we have to care about alignment of the
7310 floating point regs to provide fastest access. */
7311 cfun_frame_layout.f0_offset
7312 = ((cfun_frame_layout.gprs_offset
7313 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7314 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7315
7316 cfun_frame_layout.f4_offset
7317 = (cfun_frame_layout.f0_offset
7318 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7319 }
7320 }
7321 else /* no backchain */
7322 {
7323 cfun_frame_layout.f4_offset
7324 = (STACK_POINTER_OFFSET
7325 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7326
7327 cfun_frame_layout.f0_offset
7328 = (cfun_frame_layout.f4_offset
7329 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7330
7331 cfun_frame_layout.gprs_offset
7332 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7333 }
7334
7335 if (current_function_is_leaf
7336 && !TARGET_TPF_PROFILING
7337 && cfun_frame_layout.frame_size == 0
7338 && !cfun_save_high_fprs_p
7339 && !cfun->calls_alloca
7340 && !cfun->stdarg)
7341 return;
7342
7343 if (!TARGET_PACKED_STACK)
7344 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7345 + crtl->outgoing_args_size
7346 + cfun_frame_layout.high_fprs * 8);
7347 else
7348 {
7349 if (TARGET_BACKCHAIN)
7350 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7351
7352 /* No alignment trouble here because f8-f15 are only saved under
7353 64 bit. */
7354 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7355 cfun_frame_layout.f4_offset),
7356 cfun_frame_layout.gprs_offset)
7357 - cfun_frame_layout.high_fprs * 8);
7358
7359 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7360
7361 for (i = 0; i < 8; i++)
7362 if (cfun_fpr_bit_p (i))
7363 cfun_frame_layout.frame_size += 8;
7364
7365 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7366
7367 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7368 the frame size to sustain 8 byte alignment of stack frames. */
7369 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7370 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7371 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7372
7373 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7374 }
7375 }
7376
7377 /* Generate frame layout. Fills in register and frame data for the current
7378 function in cfun->machine. This routine can be called multiple times;
7379 it will re-do the complete frame layout every time. */
7380
7381 static void
7382 s390_init_frame_layout (void)
7383 {
7384 HOST_WIDE_INT frame_size;
7385 int base_used;
7386 int clobbered_regs[16];
7387
7388 /* On S/390 machines, we may need to perform branch splitting, which
7389 will require both base and return address register. We have no
7390 choice but to assume we're going to need them until right at the
7391 end of the machine dependent reorg phase. */
7392 if (!TARGET_CPU_ZARCH)
7393 cfun->machine->split_branches_pending_p = true;
7394
7395 do
7396 {
7397 frame_size = cfun_frame_layout.frame_size;
7398
7399 /* Try to predict whether we'll need the base register. */
7400 base_used = cfun->machine->split_branches_pending_p
7401 || crtl->uses_const_pool
7402 || (!DISP_IN_RANGE (frame_size)
7403 && !CONST_OK_FOR_K (frame_size));
7404
7405 /* Decide which register to use as literal pool base. In small
7406 leaf functions, try to use an unused call-clobbered register
7407 as base register to avoid save/restore overhead. */
7408 if (!base_used)
7409 cfun->machine->base_reg = NULL_RTX;
7410 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7411 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7412 else
7413 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7414
7415 s390_register_info (clobbered_regs);
7416 s390_frame_info ();
7417 }
7418 while (frame_size != cfun_frame_layout.frame_size);
7419 }
7420
7421 /* Update frame layout. Recompute actual register save data based on
7422 current info and update regs_ever_live for the special registers.
7423 May be called multiple times, but may never cause *more* registers
7424 to be saved than s390_init_frame_layout allocated room for. */
7425
7426 static void
7427 s390_update_frame_layout (void)
7428 {
7429 int clobbered_regs[16];
7430
7431 s390_register_info (clobbered_regs);
7432
7433 df_set_regs_ever_live (BASE_REGNUM,
7434 clobbered_regs[BASE_REGNUM] ? true : false);
7435 df_set_regs_ever_live (RETURN_REGNUM,
7436 clobbered_regs[RETURN_REGNUM] ? true : false);
7437 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7438 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7439
7440 if (cfun->machine->base_reg)
7441 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7442 }
7443
7444 /* Return true if it is legal to put a value with MODE into REGNO. */
7445
7446 bool
7447 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7448 {
7449 switch (REGNO_REG_CLASS (regno))
7450 {
7451 case FP_REGS:
7452 if (REGNO_PAIR_OK (regno, mode))
7453 {
7454 if (mode == SImode || mode == DImode)
7455 return true;
7456
7457 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7458 return true;
7459 }
7460 break;
7461 case ADDR_REGS:
7462 if (FRAME_REGNO_P (regno) && mode == Pmode)
7463 return true;
7464
7465 /* fallthrough */
7466 case GENERAL_REGS:
7467 if (REGNO_PAIR_OK (regno, mode))
7468 {
7469 if (TARGET_ZARCH
7470 || (mode != TFmode && mode != TCmode && mode != TDmode))
7471 return true;
7472 }
7473 break;
7474 case CC_REGS:
7475 if (GET_MODE_CLASS (mode) == MODE_CC)
7476 return true;
7477 break;
7478 case ACCESS_REGS:
7479 if (REGNO_PAIR_OK (regno, mode))
7480 {
7481 if (mode == SImode || mode == Pmode)
7482 return true;
7483 }
7484 break;
7485 default:
7486 return false;
7487 }
7488
7489 return false;
7490 }
7491
7492 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7493
7494 bool
7495 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7496 {
7497 /* Once we've decided upon a register to use as base register, it must
7498 no longer be used for any other purpose. */
7499 if (cfun->machine->base_reg)
7500 if (REGNO (cfun->machine->base_reg) == old_reg
7501 || REGNO (cfun->machine->base_reg) == new_reg)
7502 return false;
7503
7504 return true;
7505 }
7506
7507 /* Maximum number of registers to represent a value of mode MODE
7508 in a register of class RCLASS. */
7509
7510 bool
7511 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7512 {
7513 switch (rclass)
7514 {
7515 case FP_REGS:
7516 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7517 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7518 else
7519 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7520 case ACCESS_REGS:
7521 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7522 default:
7523 break;
7524 }
7525 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7526 }
7527
7528 /* Return true if register FROM can be eliminated via register TO. */
7529
7530 static bool
7531 s390_can_eliminate (const int from, const int to)
7532 {
7533 /* On zSeries machines, we have not marked the base register as fixed.
7534 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7535 If a function requires the base register, we say here that this
7536 elimination cannot be performed. This will cause reload to free
7537 up the base register (as if it were fixed). On the other hand,
7538 if the current function does *not* require the base register, we
7539 say here the elimination succeeds, which in turn allows reload
7540 to allocate the base register for any other purpose. */
7541 if (from == BASE_REGNUM && to == BASE_REGNUM)
7542 {
7543 if (TARGET_CPU_ZARCH)
7544 {
7545 s390_init_frame_layout ();
7546 return cfun->machine->base_reg == NULL_RTX;
7547 }
7548
7549 return false;
7550 }
7551
7552 /* Everything else must point into the stack frame. */
7553 gcc_assert (to == STACK_POINTER_REGNUM
7554 || to == HARD_FRAME_POINTER_REGNUM);
7555
7556 gcc_assert (from == FRAME_POINTER_REGNUM
7557 || from == ARG_POINTER_REGNUM
7558 || from == RETURN_ADDRESS_POINTER_REGNUM);
7559
7560 /* Make sure we actually saved the return address. */
7561 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7562 if (!crtl->calls_eh_return
7563 && !cfun->stdarg
7564 && !cfun_frame_layout.save_return_addr_p)
7565 return false;
7566
7567 return true;
7568 }
7569
7570 /* Return offset between register FROM and TO initially after prolog. */
7571
7572 HOST_WIDE_INT
7573 s390_initial_elimination_offset (int from, int to)
7574 {
7575 HOST_WIDE_INT offset;
7576 int index;
7577
7578 /* ??? Why are we called for non-eliminable pairs? */
7579 if (!s390_can_eliminate (from, to))
7580 return 0;
7581
7582 switch (from)
7583 {
7584 case FRAME_POINTER_REGNUM:
7585 offset = (get_frame_size()
7586 + STACK_POINTER_OFFSET
7587 + crtl->outgoing_args_size);
7588 break;
7589
7590 case ARG_POINTER_REGNUM:
7591 s390_init_frame_layout ();
7592 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7593 break;
7594
7595 case RETURN_ADDRESS_POINTER_REGNUM:
7596 s390_init_frame_layout ();
7597 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7598 gcc_assert (index >= 0);
7599 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7600 offset += index * UNITS_PER_LONG;
7601 break;
7602
7603 case BASE_REGNUM:
7604 offset = 0;
7605 break;
7606
7607 default:
7608 gcc_unreachable ();
7609 }
7610
7611 return offset;
7612 }
7613
7614 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7615 to register BASE. Return generated insn. */
7616
7617 static rtx
7618 save_fpr (rtx base, int offset, int regnum)
7619 {
7620 rtx addr;
7621 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7622
7623 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7624 set_mem_alias_set (addr, get_varargs_alias_set ());
7625 else
7626 set_mem_alias_set (addr, get_frame_alias_set ());
7627
7628 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7629 }
7630
7631 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7632 to register BASE. Return generated insn. */
7633
7634 static rtx
7635 restore_fpr (rtx base, int offset, int regnum)
7636 {
7637 rtx addr;
7638 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7639 set_mem_alias_set (addr, get_frame_alias_set ());
7640
7641 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7642 }
7643
7644 /* Return true if REGNO is a global register, but not one
7645 of the special ones that need to be saved/restored in anyway. */
7646
7647 static inline bool
7648 global_not_special_regno_p (int regno)
7649 {
7650 return (global_regs[regno]
7651 /* These registers are special and need to be
7652 restored in any case. */
7653 && !(regno == STACK_POINTER_REGNUM
7654 || regno == RETURN_REGNUM
7655 || regno == BASE_REGNUM
7656 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7657 }
7658
7659 /* Generate insn to save registers FIRST to LAST into
7660 the register save area located at offset OFFSET
7661 relative to register BASE. */
7662
7663 static rtx
7664 save_gprs (rtx base, int offset, int first, int last)
7665 {
7666 rtx addr, insn, note;
7667 int i;
7668
7669 addr = plus_constant (base, offset);
7670 addr = gen_rtx_MEM (Pmode, addr);
7671
7672 set_mem_alias_set (addr, get_frame_alias_set ());
7673
7674 /* Special-case single register. */
7675 if (first == last)
7676 {
7677 if (TARGET_64BIT)
7678 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7679 else
7680 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7681
7682 if (!global_not_special_regno_p (first))
7683 RTX_FRAME_RELATED_P (insn) = 1;
7684 return insn;
7685 }
7686
7687
7688 insn = gen_store_multiple (addr,
7689 gen_rtx_REG (Pmode, first),
7690 GEN_INT (last - first + 1));
7691
7692 if (first <= 6 && cfun->stdarg)
7693 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7694 {
7695 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7696
7697 if (first + i <= 6)
7698 set_mem_alias_set (mem, get_varargs_alias_set ());
7699 }
7700
7701 /* We need to set the FRAME_RELATED flag on all SETs
7702 inside the store-multiple pattern.
7703
7704 However, we must not emit DWARF records for registers 2..5
7705 if they are stored for use by variable arguments ...
7706
7707 ??? Unfortunately, it is not enough to simply not the
7708 FRAME_RELATED flags for those SETs, because the first SET
7709 of the PARALLEL is always treated as if it had the flag
7710 set, even if it does not. Therefore we emit a new pattern
7711 without those registers as REG_FRAME_RELATED_EXPR note. */
7712
7713 if (first >= 6 && !global_not_special_regno_p (first))
7714 {
7715 rtx pat = PATTERN (insn);
7716
7717 for (i = 0; i < XVECLEN (pat, 0); i++)
7718 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7719 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7720 0, i)))))
7721 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7722
7723 RTX_FRAME_RELATED_P (insn) = 1;
7724 }
7725 else if (last >= 6)
7726 {
7727 int start;
7728
7729 for (start = first >= 6 ? first : 6; start <= last; start++)
7730 if (!global_not_special_regno_p (start))
7731 break;
7732
7733 if (start > last)
7734 return insn;
7735
7736 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7737 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7738 gen_rtx_REG (Pmode, start),
7739 GEN_INT (last - start + 1));
7740 note = PATTERN (note);
7741
7742 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7743
7744 for (i = 0; i < XVECLEN (note, 0); i++)
7745 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7746 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7747 0, i)))))
7748 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7749
7750 RTX_FRAME_RELATED_P (insn) = 1;
7751 }
7752
7753 return insn;
7754 }
7755
7756 /* Generate insn to restore registers FIRST to LAST from
7757 the register save area located at offset OFFSET
7758 relative to register BASE. */
7759
7760 static rtx
7761 restore_gprs (rtx base, int offset, int first, int last)
7762 {
7763 rtx addr, insn;
7764
7765 addr = plus_constant (base, offset);
7766 addr = gen_rtx_MEM (Pmode, addr);
7767 set_mem_alias_set (addr, get_frame_alias_set ());
7768
7769 /* Special-case single register. */
7770 if (first == last)
7771 {
7772 if (TARGET_64BIT)
7773 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7774 else
7775 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7776
7777 return insn;
7778 }
7779
7780 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7781 addr,
7782 GEN_INT (last - first + 1));
7783 return insn;
7784 }
7785
7786 /* Return insn sequence to load the GOT register. */
7787
7788 static GTY(()) rtx got_symbol;
7789 rtx
7790 s390_load_got (void)
7791 {
7792 rtx insns;
7793
7794 if (!got_symbol)
7795 {
7796 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7797 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7798 }
7799
7800 start_sequence ();
7801
7802 if (TARGET_CPU_ZARCH)
7803 {
7804 emit_move_insn (pic_offset_table_rtx, got_symbol);
7805 }
7806 else
7807 {
7808 rtx offset;
7809
7810 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7811 UNSPEC_LTREL_OFFSET);
7812 offset = gen_rtx_CONST (Pmode, offset);
7813 offset = force_const_mem (Pmode, offset);
7814
7815 emit_move_insn (pic_offset_table_rtx, offset);
7816
7817 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7818 UNSPEC_LTREL_BASE);
7819 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7820
7821 emit_move_insn (pic_offset_table_rtx, offset);
7822 }
7823
7824 insns = get_insns ();
7825 end_sequence ();
7826 return insns;
7827 }
7828
7829 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7830 and the change to the stack pointer. */
7831
7832 static void
7833 s390_emit_stack_tie (void)
7834 {
7835 rtx mem = gen_frame_mem (BLKmode,
7836 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7837
7838 emit_insn (gen_stack_tie (mem));
7839 }
7840
7841 /* Expand the prologue into a bunch of separate insns. */
7842
7843 void
7844 s390_emit_prologue (void)
7845 {
7846 rtx insn, addr;
7847 rtx temp_reg;
7848 int i;
7849 int offset;
7850 int next_fpr = 0;
7851
7852 /* Complete frame layout. */
7853
7854 s390_update_frame_layout ();
7855
7856 /* Annotate all constant pool references to let the scheduler know
7857 they implicitly use the base register. */
7858
7859 push_topmost_sequence ();
7860
7861 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7862 if (INSN_P (insn))
7863 {
7864 annotate_constant_pool_refs (&PATTERN (insn));
7865 df_insn_rescan (insn);
7866 }
7867
7868 pop_topmost_sequence ();
7869
7870 /* Choose best register to use for temp use within prologue.
7871 See below for why TPF must use the register 1. */
7872
7873 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7874 && !current_function_is_leaf
7875 && !TARGET_TPF_PROFILING)
7876 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7877 else
7878 temp_reg = gen_rtx_REG (Pmode, 1);
7879
7880 /* Save call saved gprs. */
7881 if (cfun_frame_layout.first_save_gpr != -1)
7882 {
7883 insn = save_gprs (stack_pointer_rtx,
7884 cfun_frame_layout.gprs_offset +
7885 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7886 - cfun_frame_layout.first_save_gpr_slot),
7887 cfun_frame_layout.first_save_gpr,
7888 cfun_frame_layout.last_save_gpr);
7889 emit_insn (insn);
7890 }
7891
7892 /* Dummy insn to mark literal pool slot. */
7893
7894 if (cfun->machine->base_reg)
7895 emit_insn (gen_main_pool (cfun->machine->base_reg));
7896
7897 offset = cfun_frame_layout.f0_offset;
7898
7899 /* Save f0 and f2. */
7900 for (i = 0; i < 2; i++)
7901 {
7902 if (cfun_fpr_bit_p (i))
7903 {
7904 save_fpr (stack_pointer_rtx, offset, i + 16);
7905 offset += 8;
7906 }
7907 else if (!TARGET_PACKED_STACK)
7908 offset += 8;
7909 }
7910
7911 /* Save f4 and f6. */
7912 offset = cfun_frame_layout.f4_offset;
7913 for (i = 2; i < 4; i++)
7914 {
7915 if (cfun_fpr_bit_p (i))
7916 {
7917 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7918 offset += 8;
7919
7920 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7921 therefore are not frame related. */
7922 if (!call_really_used_regs[i + 16])
7923 RTX_FRAME_RELATED_P (insn) = 1;
7924 }
7925 else if (!TARGET_PACKED_STACK)
7926 offset += 8;
7927 }
7928
7929 if (TARGET_PACKED_STACK
7930 && cfun_save_high_fprs_p
7931 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7932 {
7933 offset = (cfun_frame_layout.f8_offset
7934 + (cfun_frame_layout.high_fprs - 1) * 8);
7935
7936 for (i = 15; i > 7 && offset >= 0; i--)
7937 if (cfun_fpr_bit_p (i))
7938 {
7939 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7940
7941 RTX_FRAME_RELATED_P (insn) = 1;
7942 offset -= 8;
7943 }
7944 if (offset >= cfun_frame_layout.f8_offset)
7945 next_fpr = i + 16;
7946 }
7947
7948 if (!TARGET_PACKED_STACK)
7949 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7950
7951 /* Decrement stack pointer. */
7952
7953 if (cfun_frame_layout.frame_size > 0)
7954 {
7955 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7956 rtx real_frame_off;
7957
7958 if (s390_stack_size)
7959 {
7960 HOST_WIDE_INT stack_guard;
7961
7962 if (s390_stack_guard)
7963 stack_guard = s390_stack_guard;
7964 else
7965 {
7966 /* If no value for stack guard is provided the smallest power of 2
7967 larger than the current frame size is chosen. */
7968 stack_guard = 1;
7969 while (stack_guard < cfun_frame_layout.frame_size)
7970 stack_guard <<= 1;
7971 }
7972
7973 if (cfun_frame_layout.frame_size >= s390_stack_size)
7974 {
7975 warning (0, "frame size of function %qs is "
7976 HOST_WIDE_INT_PRINT_DEC
7977 " bytes exceeding user provided stack limit of "
7978 HOST_WIDE_INT_PRINT_DEC " bytes. "
7979 "An unconditional trap is added.",
7980 current_function_name(), cfun_frame_layout.frame_size,
7981 s390_stack_size);
7982 emit_insn (gen_trap ());
7983 }
7984 else
7985 {
7986 /* stack_guard has to be smaller than s390_stack_size.
7987 Otherwise we would emit an AND with zero which would
7988 not match the test under mask pattern. */
7989 if (stack_guard >= s390_stack_size)
7990 {
7991 warning (0, "frame size of function %qs is "
7992 HOST_WIDE_INT_PRINT_DEC
7993 " bytes which is more than half the stack size. "
7994 "The dynamic check would not be reliable. "
7995 "No check emitted for this function.",
7996 current_function_name(),
7997 cfun_frame_layout.frame_size);
7998 }
7999 else
8000 {
8001 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8002 & ~(stack_guard - 1));
8003
8004 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8005 GEN_INT (stack_check_mask));
8006 if (TARGET_64BIT)
8007 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8008 t, const0_rtx),
8009 t, const0_rtx, const0_rtx));
8010 else
8011 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8012 t, const0_rtx),
8013 t, const0_rtx, const0_rtx));
8014 }
8015 }
8016 }
8017
8018 if (s390_warn_framesize > 0
8019 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8020 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
8021 current_function_name (), cfun_frame_layout.frame_size);
8022
8023 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8024 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8025
8026 /* Save incoming stack pointer into temp reg. */
8027 if (TARGET_BACKCHAIN || next_fpr)
8028 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8029
8030 /* Subtract frame size from stack pointer. */
8031
8032 if (DISP_IN_RANGE (INTVAL (frame_off)))
8033 {
8034 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8035 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8036 frame_off));
8037 insn = emit_insn (insn);
8038 }
8039 else
8040 {
8041 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8042 frame_off = force_const_mem (Pmode, frame_off);
8043
8044 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8045 annotate_constant_pool_refs (&PATTERN (insn));
8046 }
8047
8048 RTX_FRAME_RELATED_P (insn) = 1;
8049 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8050 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8051 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8052 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8053 real_frame_off)));
8054
8055 /* Set backchain. */
8056
8057 if (TARGET_BACKCHAIN)
8058 {
8059 if (cfun_frame_layout.backchain_offset)
8060 addr = gen_rtx_MEM (Pmode,
8061 plus_constant (stack_pointer_rtx,
8062 cfun_frame_layout.backchain_offset));
8063 else
8064 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8065 set_mem_alias_set (addr, get_frame_alias_set ());
8066 insn = emit_insn (gen_move_insn (addr, temp_reg));
8067 }
8068
8069 /* If we support non-call exceptions (e.g. for Java),
8070 we need to make sure the backchain pointer is set up
8071 before any possibly trapping memory access. */
8072 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8073 {
8074 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8075 emit_clobber (addr);
8076 }
8077 }
8078
8079 /* Save fprs 8 - 15 (64 bit ABI). */
8080
8081 if (cfun_save_high_fprs_p && next_fpr)
8082 {
8083 /* If the stack might be accessed through a different register
8084 we have to make sure that the stack pointer decrement is not
8085 moved below the use of the stack slots. */
8086 s390_emit_stack_tie ();
8087
8088 insn = emit_insn (gen_add2_insn (temp_reg,
8089 GEN_INT (cfun_frame_layout.f8_offset)));
8090
8091 offset = 0;
8092
8093 for (i = 24; i <= next_fpr; i++)
8094 if (cfun_fpr_bit_p (i - 16))
8095 {
8096 rtx addr = plus_constant (stack_pointer_rtx,
8097 cfun_frame_layout.frame_size
8098 + cfun_frame_layout.f8_offset
8099 + offset);
8100
8101 insn = save_fpr (temp_reg, offset, i);
8102 offset += 8;
8103 RTX_FRAME_RELATED_P (insn) = 1;
8104 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8105 gen_rtx_SET (VOIDmode,
8106 gen_rtx_MEM (DFmode, addr),
8107 gen_rtx_REG (DFmode, i)));
8108 }
8109 }
8110
8111 /* Set frame pointer, if needed. */
8112
8113 if (frame_pointer_needed)
8114 {
8115 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8116 RTX_FRAME_RELATED_P (insn) = 1;
8117 }
8118
8119 /* Set up got pointer, if needed. */
8120
8121 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8122 {
8123 rtx insns = s390_load_got ();
8124
8125 for (insn = insns; insn; insn = NEXT_INSN (insn))
8126 annotate_constant_pool_refs (&PATTERN (insn));
8127
8128 emit_insn (insns);
8129 }
8130
8131 if (TARGET_TPF_PROFILING)
8132 {
8133 /* Generate a BAS instruction to serve as a function
8134 entry intercept to facilitate the use of tracing
8135 algorithms located at the branch target. */
8136 emit_insn (gen_prologue_tpf ());
8137
8138 /* Emit a blockage here so that all code
8139 lies between the profiling mechanisms. */
8140 emit_insn (gen_blockage ());
8141 }
8142 }
8143
8144 /* Expand the epilogue into a bunch of separate insns. */
8145
8146 void
8147 s390_emit_epilogue (bool sibcall)
8148 {
8149 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8150 int area_bottom, area_top, offset = 0;
8151 int next_offset;
8152 rtvec p;
8153 int i;
8154
8155 if (TARGET_TPF_PROFILING)
8156 {
8157
8158 /* Generate a BAS instruction to serve as a function
8159 entry intercept to facilitate the use of tracing
8160 algorithms located at the branch target. */
8161
8162 /* Emit a blockage here so that all code
8163 lies between the profiling mechanisms. */
8164 emit_insn (gen_blockage ());
8165
8166 emit_insn (gen_epilogue_tpf ());
8167 }
8168
8169 /* Check whether to use frame or stack pointer for restore. */
8170
8171 frame_pointer = (frame_pointer_needed
8172 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8173
8174 s390_frame_area (&area_bottom, &area_top);
8175
8176 /* Check whether we can access the register save area.
8177 If not, increment the frame pointer as required. */
8178
8179 if (area_top <= area_bottom)
8180 {
8181 /* Nothing to restore. */
8182 }
8183 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8184 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8185 {
8186 /* Area is in range. */
8187 offset = cfun_frame_layout.frame_size;
8188 }
8189 else
8190 {
8191 rtx insn, frame_off, cfa;
8192
8193 offset = area_bottom < 0 ? -area_bottom : 0;
8194 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8195
8196 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8197 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8198 if (DISP_IN_RANGE (INTVAL (frame_off)))
8199 {
8200 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8201 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8202 insn = emit_insn (insn);
8203 }
8204 else
8205 {
8206 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8207 frame_off = force_const_mem (Pmode, frame_off);
8208
8209 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8210 annotate_constant_pool_refs (&PATTERN (insn));
8211 }
8212 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8213 RTX_FRAME_RELATED_P (insn) = 1;
8214 }
8215
8216 /* Restore call saved fprs. */
8217
8218 if (TARGET_64BIT)
8219 {
8220 if (cfun_save_high_fprs_p)
8221 {
8222 next_offset = cfun_frame_layout.f8_offset;
8223 for (i = 24; i < 32; i++)
8224 {
8225 if (cfun_fpr_bit_p (i - 16))
8226 {
8227 restore_fpr (frame_pointer,
8228 offset + next_offset, i);
8229 cfa_restores
8230 = alloc_reg_note (REG_CFA_RESTORE,
8231 gen_rtx_REG (DFmode, i), cfa_restores);
8232 next_offset += 8;
8233 }
8234 }
8235 }
8236
8237 }
8238 else
8239 {
8240 next_offset = cfun_frame_layout.f4_offset;
8241 for (i = 18; i < 20; i++)
8242 {
8243 if (cfun_fpr_bit_p (i - 16))
8244 {
8245 restore_fpr (frame_pointer,
8246 offset + next_offset, i);
8247 cfa_restores
8248 = alloc_reg_note (REG_CFA_RESTORE,
8249 gen_rtx_REG (DFmode, i), cfa_restores);
8250 next_offset += 8;
8251 }
8252 else if (!TARGET_PACKED_STACK)
8253 next_offset += 8;
8254 }
8255
8256 }
8257
8258 /* Return register. */
8259
8260 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8261
8262 /* Restore call saved gprs. */
8263
8264 if (cfun_frame_layout.first_restore_gpr != -1)
8265 {
8266 rtx insn, addr;
8267 int i;
8268
8269 /* Check for global register and save them
8270 to stack location from where they get restored. */
8271
8272 for (i = cfun_frame_layout.first_restore_gpr;
8273 i <= cfun_frame_layout.last_restore_gpr;
8274 i++)
8275 {
8276 if (global_not_special_regno_p (i))
8277 {
8278 addr = plus_constant (frame_pointer,
8279 offset + cfun_frame_layout.gprs_offset
8280 + (i - cfun_frame_layout.first_save_gpr_slot)
8281 * UNITS_PER_LONG);
8282 addr = gen_rtx_MEM (Pmode, addr);
8283 set_mem_alias_set (addr, get_frame_alias_set ());
8284 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8285 }
8286 else
8287 cfa_restores
8288 = alloc_reg_note (REG_CFA_RESTORE,
8289 gen_rtx_REG (Pmode, i), cfa_restores);
8290 }
8291
8292 if (! sibcall)
8293 {
8294 /* Fetch return address from stack before load multiple,
8295 this will do good for scheduling. */
8296
8297 if (cfun_frame_layout.save_return_addr_p
8298 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8299 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8300 {
8301 int return_regnum = find_unused_clobbered_reg();
8302 if (!return_regnum)
8303 return_regnum = 4;
8304 return_reg = gen_rtx_REG (Pmode, return_regnum);
8305
8306 addr = plus_constant (frame_pointer,
8307 offset + cfun_frame_layout.gprs_offset
8308 + (RETURN_REGNUM
8309 - cfun_frame_layout.first_save_gpr_slot)
8310 * UNITS_PER_LONG);
8311 addr = gen_rtx_MEM (Pmode, addr);
8312 set_mem_alias_set (addr, get_frame_alias_set ());
8313 emit_move_insn (return_reg, addr);
8314 }
8315 }
8316
8317 insn = restore_gprs (frame_pointer,
8318 offset + cfun_frame_layout.gprs_offset
8319 + (cfun_frame_layout.first_restore_gpr
8320 - cfun_frame_layout.first_save_gpr_slot)
8321 * UNITS_PER_LONG,
8322 cfun_frame_layout.first_restore_gpr,
8323 cfun_frame_layout.last_restore_gpr);
8324 insn = emit_insn (insn);
8325 REG_NOTES (insn) = cfa_restores;
8326 add_reg_note (insn, REG_CFA_DEF_CFA,
8327 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8328 RTX_FRAME_RELATED_P (insn) = 1;
8329 }
8330
8331 if (! sibcall)
8332 {
8333
8334 /* Return to caller. */
8335
8336 p = rtvec_alloc (2);
8337
8338 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8339 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8340 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8341 }
8342 }
8343
8344
8345 /* Return the size in bytes of a function argument of
8346 type TYPE and/or mode MODE. At least one of TYPE or
8347 MODE must be specified. */
8348
8349 static int
8350 s390_function_arg_size (enum machine_mode mode, const_tree type)
8351 {
8352 if (type)
8353 return int_size_in_bytes (type);
8354
8355 /* No type info available for some library calls ... */
8356 if (mode != BLKmode)
8357 return GET_MODE_SIZE (mode);
8358
8359 /* If we have neither type nor mode, abort */
8360 gcc_unreachable ();
8361 }
8362
8363 /* Return true if a function argument of type TYPE and mode MODE
8364 is to be passed in a floating-point register, if available. */
8365
8366 static bool
8367 s390_function_arg_float (enum machine_mode mode, const_tree type)
8368 {
8369 int size = s390_function_arg_size (mode, type);
8370 if (size > 8)
8371 return false;
8372
8373 /* Soft-float changes the ABI: no floating-point registers are used. */
8374 if (TARGET_SOFT_FLOAT)
8375 return false;
8376
8377 /* No type info available for some library calls ... */
8378 if (!type)
8379 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8380
8381 /* The ABI says that record types with a single member are treated
8382 just like that member would be. */
8383 while (TREE_CODE (type) == RECORD_TYPE)
8384 {
8385 tree field, single = NULL_TREE;
8386
8387 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8388 {
8389 if (TREE_CODE (field) != FIELD_DECL)
8390 continue;
8391
8392 if (single == NULL_TREE)
8393 single = TREE_TYPE (field);
8394 else
8395 return false;
8396 }
8397
8398 if (single == NULL_TREE)
8399 return false;
8400 else
8401 type = single;
8402 }
8403
8404 return TREE_CODE (type) == REAL_TYPE;
8405 }
8406
8407 /* Return true if a function argument of type TYPE and mode MODE
8408 is to be passed in an integer register, or a pair of integer
8409 registers, if available. */
8410
8411 static bool
8412 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8413 {
8414 int size = s390_function_arg_size (mode, type);
8415 if (size > 8)
8416 return false;
8417
8418 /* No type info available for some library calls ... */
8419 if (!type)
8420 return GET_MODE_CLASS (mode) == MODE_INT
8421 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8422
8423 /* We accept small integral (and similar) types. */
8424 if (INTEGRAL_TYPE_P (type)
8425 || POINTER_TYPE_P (type)
8426 || TREE_CODE (type) == OFFSET_TYPE
8427 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8428 return true;
8429
8430 /* We also accept structs of size 1, 2, 4, 8 that are not
8431 passed in floating-point registers. */
8432 if (AGGREGATE_TYPE_P (type)
8433 && exact_log2 (size) >= 0
8434 && !s390_function_arg_float (mode, type))
8435 return true;
8436
8437 return false;
8438 }
8439
8440 /* Return 1 if a function argument of type TYPE and mode MODE
8441 is to be passed by reference. The ABI specifies that only
8442 structures of size 1, 2, 4, or 8 bytes are passed by value,
8443 all other structures (and complex numbers) are passed by
8444 reference. */
8445
8446 static bool
8447 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8448 enum machine_mode mode, const_tree type,
8449 bool named ATTRIBUTE_UNUSED)
8450 {
8451 int size = s390_function_arg_size (mode, type);
8452 if (size > 8)
8453 return true;
8454
8455 if (type)
8456 {
8457 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8458 return 1;
8459
8460 if (TREE_CODE (type) == COMPLEX_TYPE
8461 || TREE_CODE (type) == VECTOR_TYPE)
8462 return 1;
8463 }
8464
8465 return 0;
8466 }
8467
8468 /* Update the data in CUM to advance over an argument of mode MODE and
8469 data type TYPE. (TYPE is null for libcalls where that information
8470 may not be available.). The boolean NAMED specifies whether the
8471 argument is a named argument (as opposed to an unnamed argument
8472 matching an ellipsis). */
8473
8474 static void
8475 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8476 const_tree type, bool named ATTRIBUTE_UNUSED)
8477 {
8478 if (s390_function_arg_float (mode, type))
8479 {
8480 cum->fprs += 1;
8481 }
8482 else if (s390_function_arg_integer (mode, type))
8483 {
8484 int size = s390_function_arg_size (mode, type);
8485 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8486 }
8487 else
8488 gcc_unreachable ();
8489 }
8490
8491 /* Define where to put the arguments to a function.
8492 Value is zero to push the argument on the stack,
8493 or a hard register in which to store the argument.
8494
8495 MODE is the argument's machine mode.
8496 TYPE is the data type of the argument (as a tree).
8497 This is null for libcalls where that information may
8498 not be available.
8499 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8500 the preceding args and about the function being called.
8501 NAMED is nonzero if this argument is a named parameter
8502 (otherwise it is an extra parameter matching an ellipsis).
8503
8504 On S/390, we use general purpose registers 2 through 6 to
8505 pass integer, pointer, and certain structure arguments, and
8506 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8507 to pass floating point arguments. All remaining arguments
8508 are pushed to the stack. */
8509
8510 static rtx
8511 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8512 const_tree type, bool named ATTRIBUTE_UNUSED)
8513 {
8514 if (s390_function_arg_float (mode, type))
8515 {
8516 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8517 return 0;
8518 else
8519 return gen_rtx_REG (mode, cum->fprs + 16);
8520 }
8521 else if (s390_function_arg_integer (mode, type))
8522 {
8523 int size = s390_function_arg_size (mode, type);
8524 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8525
8526 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8527 return 0;
8528 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8529 return gen_rtx_REG (mode, cum->gprs + 2);
8530 else if (n_gprs == 2)
8531 {
8532 rtvec p = rtvec_alloc (2);
8533
8534 RTVEC_ELT (p, 0)
8535 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8536 const0_rtx);
8537 RTVEC_ELT (p, 1)
8538 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8539 GEN_INT (4));
8540
8541 return gen_rtx_PARALLEL (mode, p);
8542 }
8543 }
8544
8545 /* After the real arguments, expand_call calls us once again
8546 with a void_type_node type. Whatever we return here is
8547 passed as operand 2 to the call expanders.
8548
8549 We don't need this feature ... */
8550 else if (type == void_type_node)
8551 return const0_rtx;
8552
8553 gcc_unreachable ();
8554 }
8555
8556 /* Return true if return values of type TYPE should be returned
8557 in a memory buffer whose address is passed by the caller as
8558 hidden first argument. */
8559
8560 static bool
8561 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8562 {
8563 /* We accept small integral (and similar) types. */
8564 if (INTEGRAL_TYPE_P (type)
8565 || POINTER_TYPE_P (type)
8566 || TREE_CODE (type) == OFFSET_TYPE
8567 || TREE_CODE (type) == REAL_TYPE)
8568 return int_size_in_bytes (type) > 8;
8569
8570 /* Aggregates and similar constructs are always returned
8571 in memory. */
8572 if (AGGREGATE_TYPE_P (type)
8573 || TREE_CODE (type) == COMPLEX_TYPE
8574 || TREE_CODE (type) == VECTOR_TYPE)
8575 return true;
8576
8577 /* ??? We get called on all sorts of random stuff from
8578 aggregate_value_p. We can't abort, but it's not clear
8579 what's safe to return. Pretend it's a struct I guess. */
8580 return true;
8581 }
8582
8583 /* Function arguments and return values are promoted to word size. */
8584
8585 static enum machine_mode
8586 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8587 int *punsignedp,
8588 const_tree fntype ATTRIBUTE_UNUSED,
8589 int for_return ATTRIBUTE_UNUSED)
8590 {
8591 if (INTEGRAL_MODE_P (mode)
8592 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8593 {
8594 if (POINTER_TYPE_P (type))
8595 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8596 return Pmode;
8597 }
8598
8599 return mode;
8600 }
8601
8602 /* Define where to return a (scalar) value of type TYPE.
8603 If TYPE is null, define where to return a (scalar)
8604 value of mode MODE from a libcall. */
8605
8606 rtx
8607 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8608 {
8609 if (type)
8610 {
8611 int unsignedp = TYPE_UNSIGNED (type);
8612 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8613 }
8614
8615 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8616 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8617
8618 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8619 return gen_rtx_REG (mode, 16);
8620 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8621 || UNITS_PER_LONG == UNITS_PER_WORD)
8622 return gen_rtx_REG (mode, 2);
8623 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8624 {
8625 rtvec p = rtvec_alloc (2);
8626
8627 RTVEC_ELT (p, 0)
8628 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8629 RTVEC_ELT (p, 1)
8630 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8631
8632 return gen_rtx_PARALLEL (mode, p);
8633 }
8634
8635 gcc_unreachable ();
8636 }
8637
8638
8639 /* Create and return the va_list datatype.
8640
8641 On S/390, va_list is an array type equivalent to
8642
8643 typedef struct __va_list_tag
8644 {
8645 long __gpr;
8646 long __fpr;
8647 void *__overflow_arg_area;
8648 void *__reg_save_area;
8649 } va_list[1];
8650
8651 where __gpr and __fpr hold the number of general purpose
8652 or floating point arguments used up to now, respectively,
8653 __overflow_arg_area points to the stack location of the
8654 next argument passed on the stack, and __reg_save_area
8655 always points to the start of the register area in the
8656 call frame of the current function. The function prologue
8657 saves all registers used for argument passing into this
8658 area if the function uses variable arguments. */
8659
8660 static tree
8661 s390_build_builtin_va_list (void)
8662 {
8663 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8664
8665 record = lang_hooks.types.make_type (RECORD_TYPE);
8666
8667 type_decl =
8668 build_decl (BUILTINS_LOCATION,
8669 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8670
8671 f_gpr = build_decl (BUILTINS_LOCATION,
8672 FIELD_DECL, get_identifier ("__gpr"),
8673 long_integer_type_node);
8674 f_fpr = build_decl (BUILTINS_LOCATION,
8675 FIELD_DECL, get_identifier ("__fpr"),
8676 long_integer_type_node);
8677 f_ovf = build_decl (BUILTINS_LOCATION,
8678 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8679 ptr_type_node);
8680 f_sav = build_decl (BUILTINS_LOCATION,
8681 FIELD_DECL, get_identifier ("__reg_save_area"),
8682 ptr_type_node);
8683
8684 va_list_gpr_counter_field = f_gpr;
8685 va_list_fpr_counter_field = f_fpr;
8686
8687 DECL_FIELD_CONTEXT (f_gpr) = record;
8688 DECL_FIELD_CONTEXT (f_fpr) = record;
8689 DECL_FIELD_CONTEXT (f_ovf) = record;
8690 DECL_FIELD_CONTEXT (f_sav) = record;
8691
8692 TYPE_STUB_DECL (record) = type_decl;
8693 TYPE_NAME (record) = type_decl;
8694 TYPE_FIELDS (record) = f_gpr;
8695 DECL_CHAIN (f_gpr) = f_fpr;
8696 DECL_CHAIN (f_fpr) = f_ovf;
8697 DECL_CHAIN (f_ovf) = f_sav;
8698
8699 layout_type (record);
8700
8701 /* The correct type is an array type of one element. */
8702 return build_array_type (record, build_index_type (size_zero_node));
8703 }
8704
8705 /* Implement va_start by filling the va_list structure VALIST.
8706 STDARG_P is always true, and ignored.
8707 NEXTARG points to the first anonymous stack argument.
8708
8709 The following global variables are used to initialize
8710 the va_list structure:
8711
8712 crtl->args.info:
8713 holds number of gprs and fprs used for named arguments.
8714 crtl->args.arg_offset_rtx:
8715 holds the offset of the first anonymous stack argument
8716 (relative to the virtual arg pointer). */
8717
8718 static void
8719 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8720 {
8721 HOST_WIDE_INT n_gpr, n_fpr;
8722 int off;
8723 tree f_gpr, f_fpr, f_ovf, f_sav;
8724 tree gpr, fpr, ovf, sav, t;
8725
8726 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8727 f_fpr = DECL_CHAIN (f_gpr);
8728 f_ovf = DECL_CHAIN (f_fpr);
8729 f_sav = DECL_CHAIN (f_ovf);
8730
8731 valist = build_simple_mem_ref (valist);
8732 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8733 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8734 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8735 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8736
8737 /* Count number of gp and fp argument registers used. */
8738
8739 n_gpr = crtl->args.info.gprs;
8740 n_fpr = crtl->args.info.fprs;
8741
8742 if (cfun->va_list_gpr_size)
8743 {
8744 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8745 build_int_cst (NULL_TREE, n_gpr));
8746 TREE_SIDE_EFFECTS (t) = 1;
8747 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8748 }
8749
8750 if (cfun->va_list_fpr_size)
8751 {
8752 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8753 build_int_cst (NULL_TREE, n_fpr));
8754 TREE_SIDE_EFFECTS (t) = 1;
8755 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8756 }
8757
8758 /* Find the overflow area. */
8759 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8760 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8761 {
8762 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8763
8764 off = INTVAL (crtl->args.arg_offset_rtx);
8765 off = off < 0 ? 0 : off;
8766 if (TARGET_DEBUG_ARG)
8767 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8768 (int)n_gpr, (int)n_fpr, off);
8769
8770 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8771
8772 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8773 TREE_SIDE_EFFECTS (t) = 1;
8774 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8775 }
8776
8777 /* Find the register save area. */
8778 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8779 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8780 {
8781 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8782 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8783 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8784
8785 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8786 TREE_SIDE_EFFECTS (t) = 1;
8787 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8788 }
8789 }
8790
8791 /* Implement va_arg by updating the va_list structure
8792 VALIST as required to retrieve an argument of type
8793 TYPE, and returning that argument.
8794
8795 Generates code equivalent to:
8796
8797 if (integral value) {
8798 if (size <= 4 && args.gpr < 5 ||
8799 size > 4 && args.gpr < 4 )
8800 ret = args.reg_save_area[args.gpr+8]
8801 else
8802 ret = *args.overflow_arg_area++;
8803 } else if (float value) {
8804 if (args.fgpr < 2)
8805 ret = args.reg_save_area[args.fpr+64]
8806 else
8807 ret = *args.overflow_arg_area++;
8808 } else if (aggregate value) {
8809 if (args.gpr < 5)
8810 ret = *args.reg_save_area[args.gpr]
8811 else
8812 ret = **args.overflow_arg_area++;
8813 } */
8814
8815 static tree
8816 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8817 gimple_seq *post_p ATTRIBUTE_UNUSED)
8818 {
8819 tree f_gpr, f_fpr, f_ovf, f_sav;
8820 tree gpr, fpr, ovf, sav, reg, t, u;
8821 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8822 tree lab_false, lab_over, addr;
8823
8824 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8825 f_fpr = DECL_CHAIN (f_gpr);
8826 f_ovf = DECL_CHAIN (f_fpr);
8827 f_sav = DECL_CHAIN (f_ovf);
8828
8829 valist = build_va_arg_indirect_ref (valist);
8830 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8831 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8832 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8833
8834 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8835 both appear on a lhs. */
8836 valist = unshare_expr (valist);
8837 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8838
8839 size = int_size_in_bytes (type);
8840
8841 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8842 {
8843 if (TARGET_DEBUG_ARG)
8844 {
8845 fprintf (stderr, "va_arg: aggregate type");
8846 debug_tree (type);
8847 }
8848
8849 /* Aggregates are passed by reference. */
8850 indirect_p = 1;
8851 reg = gpr;
8852 n_reg = 1;
8853
8854 /* kernel stack layout on 31 bit: It is assumed here that no padding
8855 will be added by s390_frame_info because for va_args always an even
8856 number of gprs has to be saved r15-r2 = 14 regs. */
8857 sav_ofs = 2 * UNITS_PER_LONG;
8858 sav_scale = UNITS_PER_LONG;
8859 size = UNITS_PER_LONG;
8860 max_reg = GP_ARG_NUM_REG - n_reg;
8861 }
8862 else if (s390_function_arg_float (TYPE_MODE (type), type))
8863 {
8864 if (TARGET_DEBUG_ARG)
8865 {
8866 fprintf (stderr, "va_arg: float type");
8867 debug_tree (type);
8868 }
8869
8870 /* FP args go in FP registers, if present. */
8871 indirect_p = 0;
8872 reg = fpr;
8873 n_reg = 1;
8874 sav_ofs = 16 * UNITS_PER_LONG;
8875 sav_scale = 8;
8876 max_reg = FP_ARG_NUM_REG - n_reg;
8877 }
8878 else
8879 {
8880 if (TARGET_DEBUG_ARG)
8881 {
8882 fprintf (stderr, "va_arg: other type");
8883 debug_tree (type);
8884 }
8885
8886 /* Otherwise into GP registers. */
8887 indirect_p = 0;
8888 reg = gpr;
8889 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8890
8891 /* kernel stack layout on 31 bit: It is assumed here that no padding
8892 will be added by s390_frame_info because for va_args always an even
8893 number of gprs has to be saved r15-r2 = 14 regs. */
8894 sav_ofs = 2 * UNITS_PER_LONG;
8895
8896 if (size < UNITS_PER_LONG)
8897 sav_ofs += UNITS_PER_LONG - size;
8898
8899 sav_scale = UNITS_PER_LONG;
8900 max_reg = GP_ARG_NUM_REG - n_reg;
8901 }
8902
8903 /* Pull the value out of the saved registers ... */
8904
8905 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8906 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8907 addr = create_tmp_var (ptr_type_node, "addr");
8908
8909 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8910 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8911 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8912 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8913 gimplify_and_add (t, pre_p);
8914
8915 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8916 size_int (sav_ofs));
8917 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8918 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8919 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8920
8921 gimplify_assign (addr, t, pre_p);
8922
8923 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8924
8925 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8926
8927
8928 /* ... Otherwise out of the overflow area. */
8929
8930 t = ovf;
8931 if (size < UNITS_PER_LONG)
8932 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8933 size_int (UNITS_PER_LONG - size));
8934
8935 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8936
8937 gimplify_assign (addr, t, pre_p);
8938
8939 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8940 size_int (size));
8941 gimplify_assign (ovf, t, pre_p);
8942
8943 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8944
8945
8946 /* Increment register save count. */
8947
8948 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8949 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8950 gimplify_and_add (u, pre_p);
8951
8952 if (indirect_p)
8953 {
8954 t = build_pointer_type_for_mode (build_pointer_type (type),
8955 ptr_mode, true);
8956 addr = fold_convert (t, addr);
8957 addr = build_va_arg_indirect_ref (addr);
8958 }
8959 else
8960 {
8961 t = build_pointer_type_for_mode (type, ptr_mode, true);
8962 addr = fold_convert (t, addr);
8963 }
8964
8965 return build_va_arg_indirect_ref (addr);
8966 }
8967
8968
8969 /* Builtins. */
8970
8971 enum s390_builtin
8972 {
8973 S390_BUILTIN_THREAD_POINTER,
8974 S390_BUILTIN_SET_THREAD_POINTER,
8975
8976 S390_BUILTIN_max
8977 };
8978
8979 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8980 CODE_FOR_get_tp_64,
8981 CODE_FOR_set_tp_64
8982 };
8983
8984 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8985 CODE_FOR_get_tp_31,
8986 CODE_FOR_set_tp_31
8987 };
8988
8989 static void
8990 s390_init_builtins (void)
8991 {
8992 tree ftype;
8993
8994 ftype = build_function_type (ptr_type_node, void_list_node);
8995 add_builtin_function ("__builtin_thread_pointer", ftype,
8996 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8997 NULL, NULL_TREE);
8998
8999 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9000 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9001 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9002 NULL, NULL_TREE);
9003 }
9004
9005 /* Expand an expression EXP that calls a built-in function,
9006 with result going to TARGET if that's convenient
9007 (and in mode MODE if that's convenient).
9008 SUBTARGET may be used as the target for computing one of EXP's operands.
9009 IGNORE is nonzero if the value is to be ignored. */
9010
9011 static rtx
9012 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9013 enum machine_mode mode ATTRIBUTE_UNUSED,
9014 int ignore ATTRIBUTE_UNUSED)
9015 {
9016 #define MAX_ARGS 2
9017
9018 enum insn_code const *code_for_builtin =
9019 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9020
9021 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9022 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9023 enum insn_code icode;
9024 rtx op[MAX_ARGS], pat;
9025 int arity;
9026 bool nonvoid;
9027 tree arg;
9028 call_expr_arg_iterator iter;
9029
9030 if (fcode >= S390_BUILTIN_max)
9031 internal_error ("bad builtin fcode");
9032 icode = code_for_builtin[fcode];
9033 if (icode == 0)
9034 internal_error ("bad builtin fcode");
9035
9036 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9037
9038 arity = 0;
9039 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9040 {
9041 const struct insn_operand_data *insn_op;
9042
9043 if (arg == error_mark_node)
9044 return NULL_RTX;
9045 if (arity > MAX_ARGS)
9046 return NULL_RTX;
9047
9048 insn_op = &insn_data[icode].operand[arity + nonvoid];
9049
9050 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9051
9052 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9053 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9054 arity++;
9055 }
9056
9057 if (nonvoid)
9058 {
9059 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9060 if (!target
9061 || GET_MODE (target) != tmode
9062 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9063 target = gen_reg_rtx (tmode);
9064 }
9065
9066 switch (arity)
9067 {
9068 case 0:
9069 pat = GEN_FCN (icode) (target);
9070 break;
9071 case 1:
9072 if (nonvoid)
9073 pat = GEN_FCN (icode) (target, op[0]);
9074 else
9075 pat = GEN_FCN (icode) (op[0]);
9076 break;
9077 case 2:
9078 pat = GEN_FCN (icode) (target, op[0], op[1]);
9079 break;
9080 default:
9081 gcc_unreachable ();
9082 }
9083 if (!pat)
9084 return NULL_RTX;
9085 emit_insn (pat);
9086
9087 if (nonvoid)
9088 return target;
9089 else
9090 return const0_rtx;
9091 }
9092
9093
9094 /* Output assembly code for the trampoline template to
9095 stdio stream FILE.
9096
9097 On S/390, we use gpr 1 internally in the trampoline code;
9098 gpr 0 is used to hold the static chain. */
9099
9100 static void
9101 s390_asm_trampoline_template (FILE *file)
9102 {
9103 rtx op[2];
9104 op[0] = gen_rtx_REG (Pmode, 0);
9105 op[1] = gen_rtx_REG (Pmode, 1);
9106
9107 if (TARGET_64BIT)
9108 {
9109 output_asm_insn ("basr\t%1,0", op);
9110 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9111 output_asm_insn ("br\t%1", op);
9112 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9113 }
9114 else
9115 {
9116 output_asm_insn ("basr\t%1,0", op);
9117 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9118 output_asm_insn ("br\t%1", op);
9119 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9120 }
9121 }
9122
9123 /* Emit RTL insns to initialize the variable parts of a trampoline.
9124 FNADDR is an RTX for the address of the function's pure code.
9125 CXT is an RTX for the static chain value for the function. */
9126
9127 static void
9128 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9129 {
9130 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9131 rtx mem;
9132
9133 emit_block_move (m_tramp, assemble_trampoline_template (),
9134 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9135
9136 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9137 emit_move_insn (mem, cxt);
9138 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9139 emit_move_insn (mem, fnaddr);
9140 }
9141
9142 /* Output assembler code to FILE to increment profiler label # LABELNO
9143 for profiling a function entry. */
9144
9145 void
9146 s390_function_profiler (FILE *file, int labelno)
9147 {
9148 rtx op[7];
9149
9150 char label[128];
9151 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9152
9153 fprintf (file, "# function profiler \n");
9154
9155 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9156 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9157 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9158
9159 op[2] = gen_rtx_REG (Pmode, 1);
9160 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9161 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9162
9163 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9164 if (flag_pic)
9165 {
9166 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9167 op[4] = gen_rtx_CONST (Pmode, op[4]);
9168 }
9169
9170 if (TARGET_64BIT)
9171 {
9172 output_asm_insn ("stg\t%0,%1", op);
9173 output_asm_insn ("larl\t%2,%3", op);
9174 output_asm_insn ("brasl\t%0,%4", op);
9175 output_asm_insn ("lg\t%0,%1", op);
9176 }
9177 else if (!flag_pic)
9178 {
9179 op[6] = gen_label_rtx ();
9180
9181 output_asm_insn ("st\t%0,%1", op);
9182 output_asm_insn ("bras\t%2,%l6", op);
9183 output_asm_insn (".long\t%4", op);
9184 output_asm_insn (".long\t%3", op);
9185 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9186 output_asm_insn ("l\t%0,0(%2)", op);
9187 output_asm_insn ("l\t%2,4(%2)", op);
9188 output_asm_insn ("basr\t%0,%0", op);
9189 output_asm_insn ("l\t%0,%1", op);
9190 }
9191 else
9192 {
9193 op[5] = gen_label_rtx ();
9194 op[6] = gen_label_rtx ();
9195
9196 output_asm_insn ("st\t%0,%1", op);
9197 output_asm_insn ("bras\t%2,%l6", op);
9198 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9199 output_asm_insn (".long\t%4-%l5", op);
9200 output_asm_insn (".long\t%3-%l5", op);
9201 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9202 output_asm_insn ("lr\t%0,%2", op);
9203 output_asm_insn ("a\t%0,0(%2)", op);
9204 output_asm_insn ("a\t%2,4(%2)", op);
9205 output_asm_insn ("basr\t%0,%0", op);
9206 output_asm_insn ("l\t%0,%1", op);
9207 }
9208 }
9209
9210 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9211 into its SYMBOL_REF_FLAGS. */
9212
9213 static void
9214 s390_encode_section_info (tree decl, rtx rtl, int first)
9215 {
9216 default_encode_section_info (decl, rtl, first);
9217
9218 if (TREE_CODE (decl) == VAR_DECL)
9219 {
9220 /* If a variable has a forced alignment to < 2 bytes, mark it
9221 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9222 operand. */
9223 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9224 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9225 if (!DECL_SIZE (decl)
9226 || !DECL_ALIGN (decl)
9227 || !host_integerp (DECL_SIZE (decl), 0)
9228 || (DECL_ALIGN (decl) <= 64
9229 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9230 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9231 }
9232
9233 /* Literal pool references don't have a decl so they are handled
9234 differently here. We rely on the information in the MEM_ALIGN
9235 entry to decide upon natural alignment. */
9236 if (MEM_P (rtl)
9237 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9238 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9239 && (MEM_ALIGN (rtl) == 0
9240 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9241 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9242 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9243 }
9244
9245 /* Output thunk to FILE that implements a C++ virtual function call (with
9246 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9247 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9248 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9249 relative to the resulting this pointer. */
9250
9251 static void
9252 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9253 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9254 tree function)
9255 {
9256 rtx op[10];
9257 int nonlocal = 0;
9258
9259 /* Make sure unwind info is emitted for the thunk if needed. */
9260 final_start_function (emit_barrier (), file, 1);
9261
9262 /* Operand 0 is the target function. */
9263 op[0] = XEXP (DECL_RTL (function), 0);
9264 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9265 {
9266 nonlocal = 1;
9267 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9268 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9269 op[0] = gen_rtx_CONST (Pmode, op[0]);
9270 }
9271
9272 /* Operand 1 is the 'this' pointer. */
9273 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9274 op[1] = gen_rtx_REG (Pmode, 3);
9275 else
9276 op[1] = gen_rtx_REG (Pmode, 2);
9277
9278 /* Operand 2 is the delta. */
9279 op[2] = GEN_INT (delta);
9280
9281 /* Operand 3 is the vcall_offset. */
9282 op[3] = GEN_INT (vcall_offset);
9283
9284 /* Operand 4 is the temporary register. */
9285 op[4] = gen_rtx_REG (Pmode, 1);
9286
9287 /* Operands 5 to 8 can be used as labels. */
9288 op[5] = NULL_RTX;
9289 op[6] = NULL_RTX;
9290 op[7] = NULL_RTX;
9291 op[8] = NULL_RTX;
9292
9293 /* Operand 9 can be used for temporary register. */
9294 op[9] = NULL_RTX;
9295
9296 /* Generate code. */
9297 if (TARGET_64BIT)
9298 {
9299 /* Setup literal pool pointer if required. */
9300 if ((!DISP_IN_RANGE (delta)
9301 && !CONST_OK_FOR_K (delta)
9302 && !CONST_OK_FOR_Os (delta))
9303 || (!DISP_IN_RANGE (vcall_offset)
9304 && !CONST_OK_FOR_K (vcall_offset)
9305 && !CONST_OK_FOR_Os (vcall_offset)))
9306 {
9307 op[5] = gen_label_rtx ();
9308 output_asm_insn ("larl\t%4,%5", op);
9309 }
9310
9311 /* Add DELTA to this pointer. */
9312 if (delta)
9313 {
9314 if (CONST_OK_FOR_J (delta))
9315 output_asm_insn ("la\t%1,%2(%1)", op);
9316 else if (DISP_IN_RANGE (delta))
9317 output_asm_insn ("lay\t%1,%2(%1)", op);
9318 else if (CONST_OK_FOR_K (delta))
9319 output_asm_insn ("aghi\t%1,%2", op);
9320 else if (CONST_OK_FOR_Os (delta))
9321 output_asm_insn ("agfi\t%1,%2", op);
9322 else
9323 {
9324 op[6] = gen_label_rtx ();
9325 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9326 }
9327 }
9328
9329 /* Perform vcall adjustment. */
9330 if (vcall_offset)
9331 {
9332 if (DISP_IN_RANGE (vcall_offset))
9333 {
9334 output_asm_insn ("lg\t%4,0(%1)", op);
9335 output_asm_insn ("ag\t%1,%3(%4)", op);
9336 }
9337 else if (CONST_OK_FOR_K (vcall_offset))
9338 {
9339 output_asm_insn ("lghi\t%4,%3", op);
9340 output_asm_insn ("ag\t%4,0(%1)", op);
9341 output_asm_insn ("ag\t%1,0(%4)", op);
9342 }
9343 else if (CONST_OK_FOR_Os (vcall_offset))
9344 {
9345 output_asm_insn ("lgfi\t%4,%3", op);
9346 output_asm_insn ("ag\t%4,0(%1)", op);
9347 output_asm_insn ("ag\t%1,0(%4)", op);
9348 }
9349 else
9350 {
9351 op[7] = gen_label_rtx ();
9352 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9353 output_asm_insn ("ag\t%4,0(%1)", op);
9354 output_asm_insn ("ag\t%1,0(%4)", op);
9355 }
9356 }
9357
9358 /* Jump to target. */
9359 output_asm_insn ("jg\t%0", op);
9360
9361 /* Output literal pool if required. */
9362 if (op[5])
9363 {
9364 output_asm_insn (".align\t4", op);
9365 targetm.asm_out.internal_label (file, "L",
9366 CODE_LABEL_NUMBER (op[5]));
9367 }
9368 if (op[6])
9369 {
9370 targetm.asm_out.internal_label (file, "L",
9371 CODE_LABEL_NUMBER (op[6]));
9372 output_asm_insn (".long\t%2", op);
9373 }
9374 if (op[7])
9375 {
9376 targetm.asm_out.internal_label (file, "L",
9377 CODE_LABEL_NUMBER (op[7]));
9378 output_asm_insn (".long\t%3", op);
9379 }
9380 }
9381 else
9382 {
9383 /* Setup base pointer if required. */
9384 if (!vcall_offset
9385 || (!DISP_IN_RANGE (delta)
9386 && !CONST_OK_FOR_K (delta)
9387 && !CONST_OK_FOR_Os (delta))
9388 || (!DISP_IN_RANGE (delta)
9389 && !CONST_OK_FOR_K (vcall_offset)
9390 && !CONST_OK_FOR_Os (vcall_offset)))
9391 {
9392 op[5] = gen_label_rtx ();
9393 output_asm_insn ("basr\t%4,0", op);
9394 targetm.asm_out.internal_label (file, "L",
9395 CODE_LABEL_NUMBER (op[5]));
9396 }
9397
9398 /* Add DELTA to this pointer. */
9399 if (delta)
9400 {
9401 if (CONST_OK_FOR_J (delta))
9402 output_asm_insn ("la\t%1,%2(%1)", op);
9403 else if (DISP_IN_RANGE (delta))
9404 output_asm_insn ("lay\t%1,%2(%1)", op);
9405 else if (CONST_OK_FOR_K (delta))
9406 output_asm_insn ("ahi\t%1,%2", op);
9407 else if (CONST_OK_FOR_Os (delta))
9408 output_asm_insn ("afi\t%1,%2", op);
9409 else
9410 {
9411 op[6] = gen_label_rtx ();
9412 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9413 }
9414 }
9415
9416 /* Perform vcall adjustment. */
9417 if (vcall_offset)
9418 {
9419 if (CONST_OK_FOR_J (vcall_offset))
9420 {
9421 output_asm_insn ("l\t%4,0(%1)", op);
9422 output_asm_insn ("a\t%1,%3(%4)", op);
9423 }
9424 else if (DISP_IN_RANGE (vcall_offset))
9425 {
9426 output_asm_insn ("l\t%4,0(%1)", op);
9427 output_asm_insn ("ay\t%1,%3(%4)", op);
9428 }
9429 else if (CONST_OK_FOR_K (vcall_offset))
9430 {
9431 output_asm_insn ("lhi\t%4,%3", op);
9432 output_asm_insn ("a\t%4,0(%1)", op);
9433 output_asm_insn ("a\t%1,0(%4)", op);
9434 }
9435 else if (CONST_OK_FOR_Os (vcall_offset))
9436 {
9437 output_asm_insn ("iilf\t%4,%3", op);
9438 output_asm_insn ("a\t%4,0(%1)", op);
9439 output_asm_insn ("a\t%1,0(%4)", op);
9440 }
9441 else
9442 {
9443 op[7] = gen_label_rtx ();
9444 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9445 output_asm_insn ("a\t%4,0(%1)", op);
9446 output_asm_insn ("a\t%1,0(%4)", op);
9447 }
9448
9449 /* We had to clobber the base pointer register.
9450 Re-setup the base pointer (with a different base). */
9451 op[5] = gen_label_rtx ();
9452 output_asm_insn ("basr\t%4,0", op);
9453 targetm.asm_out.internal_label (file, "L",
9454 CODE_LABEL_NUMBER (op[5]));
9455 }
9456
9457 /* Jump to target. */
9458 op[8] = gen_label_rtx ();
9459
9460 if (!flag_pic)
9461 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9462 else if (!nonlocal)
9463 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9464 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9465 else if (flag_pic == 1)
9466 {
9467 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9468 output_asm_insn ("l\t%4,%0(%4)", op);
9469 }
9470 else if (flag_pic == 2)
9471 {
9472 op[9] = gen_rtx_REG (Pmode, 0);
9473 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9474 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9475 output_asm_insn ("ar\t%4,%9", op);
9476 output_asm_insn ("l\t%4,0(%4)", op);
9477 }
9478
9479 output_asm_insn ("br\t%4", op);
9480
9481 /* Output literal pool. */
9482 output_asm_insn (".align\t4", op);
9483
9484 if (nonlocal && flag_pic == 2)
9485 output_asm_insn (".long\t%0", op);
9486 if (nonlocal)
9487 {
9488 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9489 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9490 }
9491
9492 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9493 if (!flag_pic)
9494 output_asm_insn (".long\t%0", op);
9495 else
9496 output_asm_insn (".long\t%0-%5", op);
9497
9498 if (op[6])
9499 {
9500 targetm.asm_out.internal_label (file, "L",
9501 CODE_LABEL_NUMBER (op[6]));
9502 output_asm_insn (".long\t%2", op);
9503 }
9504 if (op[7])
9505 {
9506 targetm.asm_out.internal_label (file, "L",
9507 CODE_LABEL_NUMBER (op[7]));
9508 output_asm_insn (".long\t%3", op);
9509 }
9510 }
9511 final_end_function ();
9512 }
9513
9514 static bool
9515 s390_valid_pointer_mode (enum machine_mode mode)
9516 {
9517 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9518 }
9519
9520 /* Checks whether the given CALL_EXPR would use a caller
9521 saved register. This is used to decide whether sibling call
9522 optimization could be performed on the respective function
9523 call. */
9524
9525 static bool
9526 s390_call_saved_register_used (tree call_expr)
9527 {
9528 CUMULATIVE_ARGS cum;
9529 tree parameter;
9530 enum machine_mode mode;
9531 tree type;
9532 rtx parm_rtx;
9533 int reg, i;
9534
9535 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9536
9537 for (i = 0; i < call_expr_nargs (call_expr); i++)
9538 {
9539 parameter = CALL_EXPR_ARG (call_expr, i);
9540 gcc_assert (parameter);
9541
9542 /* For an undeclared variable passed as parameter we will get
9543 an ERROR_MARK node here. */
9544 if (TREE_CODE (parameter) == ERROR_MARK)
9545 return true;
9546
9547 type = TREE_TYPE (parameter);
9548 gcc_assert (type);
9549
9550 mode = TYPE_MODE (type);
9551 gcc_assert (mode);
9552
9553 if (pass_by_reference (&cum, mode, type, true))
9554 {
9555 mode = Pmode;
9556 type = build_pointer_type (type);
9557 }
9558
9559 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9560
9561 s390_function_arg_advance (&cum, mode, type, 0);
9562
9563 if (!parm_rtx)
9564 continue;
9565
9566 if (REG_P (parm_rtx))
9567 {
9568 for (reg = 0;
9569 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9570 reg++)
9571 if (!call_used_regs[reg + REGNO (parm_rtx)])
9572 return true;
9573 }
9574
9575 if (GET_CODE (parm_rtx) == PARALLEL)
9576 {
9577 int i;
9578
9579 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9580 {
9581 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9582
9583 gcc_assert (REG_P (r));
9584
9585 for (reg = 0;
9586 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9587 reg++)
9588 if (!call_used_regs[reg + REGNO (r)])
9589 return true;
9590 }
9591 }
9592
9593 }
9594 return false;
9595 }
9596
9597 /* Return true if the given call expression can be
9598 turned into a sibling call.
9599 DECL holds the declaration of the function to be called whereas
9600 EXP is the call expression itself. */
9601
9602 static bool
9603 s390_function_ok_for_sibcall (tree decl, tree exp)
9604 {
9605 /* The TPF epilogue uses register 1. */
9606 if (TARGET_TPF_PROFILING)
9607 return false;
9608
9609 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9610 which would have to be restored before the sibcall. */
9611 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9612 return false;
9613
9614 /* Register 6 on s390 is available as an argument register but unfortunately
9615 "caller saved". This makes functions needing this register for arguments
9616 not suitable for sibcalls. */
9617 return !s390_call_saved_register_used (exp);
9618 }
9619
9620 /* Return the fixed registers used for condition codes. */
9621
9622 static bool
9623 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9624 {
9625 *p1 = CC_REGNUM;
9626 *p2 = INVALID_REGNUM;
9627
9628 return true;
9629 }
9630
9631 /* This function is used by the call expanders of the machine description.
9632 It emits the call insn itself together with the necessary operations
9633 to adjust the target address and returns the emitted insn.
9634 ADDR_LOCATION is the target address rtx
9635 TLS_CALL the location of the thread-local symbol
9636 RESULT_REG the register where the result of the call should be stored
9637 RETADDR_REG the register where the return address should be stored
9638 If this parameter is NULL_RTX the call is considered
9639 to be a sibling call. */
9640
9641 rtx
9642 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9643 rtx retaddr_reg)
9644 {
9645 bool plt_call = false;
9646 rtx insn;
9647 rtx call;
9648 rtx clobber;
9649 rtvec vec;
9650
9651 /* Direct function calls need special treatment. */
9652 if (GET_CODE (addr_location) == SYMBOL_REF)
9653 {
9654 /* When calling a global routine in PIC mode, we must
9655 replace the symbol itself with the PLT stub. */
9656 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9657 {
9658 if (retaddr_reg != NULL_RTX)
9659 {
9660 addr_location = gen_rtx_UNSPEC (Pmode,
9661 gen_rtvec (1, addr_location),
9662 UNSPEC_PLT);
9663 addr_location = gen_rtx_CONST (Pmode, addr_location);
9664 plt_call = true;
9665 }
9666 else
9667 /* For -fpic code the PLT entries might use r12 which is
9668 call-saved. Therefore we cannot do a sibcall when
9669 calling directly using a symbol ref. When reaching
9670 this point we decided (in s390_function_ok_for_sibcall)
9671 to do a sibcall for a function pointer but one of the
9672 optimizers was able to get rid of the function pointer
9673 by propagating the symbol ref into the call. This
9674 optimization is illegal for S/390 so we turn the direct
9675 call into a indirect call again. */
9676 addr_location = force_reg (Pmode, addr_location);
9677 }
9678
9679 /* Unless we can use the bras(l) insn, force the
9680 routine address into a register. */
9681 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9682 {
9683 if (flag_pic)
9684 addr_location = legitimize_pic_address (addr_location, 0);
9685 else
9686 addr_location = force_reg (Pmode, addr_location);
9687 }
9688 }
9689
9690 /* If it is already an indirect call or the code above moved the
9691 SYMBOL_REF to somewhere else make sure the address can be found in
9692 register 1. */
9693 if (retaddr_reg == NULL_RTX
9694 && GET_CODE (addr_location) != SYMBOL_REF
9695 && !plt_call)
9696 {
9697 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9698 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9699 }
9700
9701 addr_location = gen_rtx_MEM (QImode, addr_location);
9702 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9703
9704 if (result_reg != NULL_RTX)
9705 call = gen_rtx_SET (VOIDmode, result_reg, call);
9706
9707 if (retaddr_reg != NULL_RTX)
9708 {
9709 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9710
9711 if (tls_call != NULL_RTX)
9712 vec = gen_rtvec (3, call, clobber,
9713 gen_rtx_USE (VOIDmode, tls_call));
9714 else
9715 vec = gen_rtvec (2, call, clobber);
9716
9717 call = gen_rtx_PARALLEL (VOIDmode, vec);
9718 }
9719
9720 insn = emit_call_insn (call);
9721
9722 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9723 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9724 {
9725 /* s390_function_ok_for_sibcall should
9726 have denied sibcalls in this case. */
9727 gcc_assert (retaddr_reg != NULL_RTX);
9728
9729 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9730 }
9731 return insn;
9732 }
9733
9734 /* Implement CONDITIONAL_REGISTER_USAGE. */
9735
9736 void
9737 s390_conditional_register_usage (void)
9738 {
9739 int i;
9740
9741 if (flag_pic)
9742 {
9743 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9744 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9745 }
9746 if (TARGET_CPU_ZARCH)
9747 {
9748 fixed_regs[BASE_REGNUM] = 0;
9749 call_used_regs[BASE_REGNUM] = 0;
9750 fixed_regs[RETURN_REGNUM] = 0;
9751 call_used_regs[RETURN_REGNUM] = 0;
9752 }
9753 if (TARGET_64BIT)
9754 {
9755 for (i = 24; i < 32; i++)
9756 call_used_regs[i] = call_really_used_regs[i] = 0;
9757 }
9758 else
9759 {
9760 for (i = 18; i < 20; i++)
9761 call_used_regs[i] = call_really_used_regs[i] = 0;
9762 }
9763
9764 if (TARGET_SOFT_FLOAT)
9765 {
9766 for (i = 16; i < 32; i++)
9767 call_used_regs[i] = fixed_regs[i] = 1;
9768 }
9769 }
9770
9771 /* Corresponding function to eh_return expander. */
9772
9773 static GTY(()) rtx s390_tpf_eh_return_symbol;
9774 void
9775 s390_emit_tpf_eh_return (rtx target)
9776 {
9777 rtx insn, reg;
9778
9779 if (!s390_tpf_eh_return_symbol)
9780 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9781
9782 reg = gen_rtx_REG (Pmode, 2);
9783
9784 emit_move_insn (reg, target);
9785 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9786 gen_rtx_REG (Pmode, RETURN_REGNUM));
9787 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9788
9789 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9790 }
9791
9792 /* Rework the prologue/epilogue to avoid saving/restoring
9793 registers unnecessarily. */
9794
9795 static void
9796 s390_optimize_prologue (void)
9797 {
9798 rtx insn, new_insn, next_insn;
9799
9800 /* Do a final recompute of the frame-related data. */
9801
9802 s390_update_frame_layout ();
9803
9804 /* If all special registers are in fact used, there's nothing we
9805 can do, so no point in walking the insn list. */
9806
9807 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9808 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9809 && (TARGET_CPU_ZARCH
9810 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9811 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9812 return;
9813
9814 /* Search for prologue/epilogue insns and replace them. */
9815
9816 for (insn = get_insns (); insn; insn = next_insn)
9817 {
9818 int first, last, off;
9819 rtx set, base, offset;
9820
9821 next_insn = NEXT_INSN (insn);
9822
9823 if (GET_CODE (insn) != INSN)
9824 continue;
9825
9826 if (GET_CODE (PATTERN (insn)) == PARALLEL
9827 && store_multiple_operation (PATTERN (insn), VOIDmode))
9828 {
9829 set = XVECEXP (PATTERN (insn), 0, 0);
9830 first = REGNO (SET_SRC (set));
9831 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9832 offset = const0_rtx;
9833 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9834 off = INTVAL (offset);
9835
9836 if (GET_CODE (base) != REG || off < 0)
9837 continue;
9838 if (cfun_frame_layout.first_save_gpr != -1
9839 && (cfun_frame_layout.first_save_gpr < first
9840 || cfun_frame_layout.last_save_gpr > last))
9841 continue;
9842 if (REGNO (base) != STACK_POINTER_REGNUM
9843 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9844 continue;
9845 if (first > BASE_REGNUM || last < BASE_REGNUM)
9846 continue;
9847
9848 if (cfun_frame_layout.first_save_gpr != -1)
9849 {
9850 new_insn = save_gprs (base,
9851 off + (cfun_frame_layout.first_save_gpr
9852 - first) * UNITS_PER_LONG,
9853 cfun_frame_layout.first_save_gpr,
9854 cfun_frame_layout.last_save_gpr);
9855 new_insn = emit_insn_before (new_insn, insn);
9856 INSN_ADDRESSES_NEW (new_insn, -1);
9857 }
9858
9859 remove_insn (insn);
9860 continue;
9861 }
9862
9863 if (cfun_frame_layout.first_save_gpr == -1
9864 && GET_CODE (PATTERN (insn)) == SET
9865 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9866 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9867 || (!TARGET_CPU_ZARCH
9868 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9869 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9870 {
9871 set = PATTERN (insn);
9872 first = REGNO (SET_SRC (set));
9873 offset = const0_rtx;
9874 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9875 off = INTVAL (offset);
9876
9877 if (GET_CODE (base) != REG || off < 0)
9878 continue;
9879 if (REGNO (base) != STACK_POINTER_REGNUM
9880 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9881 continue;
9882
9883 remove_insn (insn);
9884 continue;
9885 }
9886
9887 if (GET_CODE (PATTERN (insn)) == PARALLEL
9888 && load_multiple_operation (PATTERN (insn), VOIDmode))
9889 {
9890 set = XVECEXP (PATTERN (insn), 0, 0);
9891 first = REGNO (SET_DEST (set));
9892 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9893 offset = const0_rtx;
9894 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9895 off = INTVAL (offset);
9896
9897 if (GET_CODE (base) != REG || off < 0)
9898 continue;
9899 if (cfun_frame_layout.first_restore_gpr != -1
9900 && (cfun_frame_layout.first_restore_gpr < first
9901 || cfun_frame_layout.last_restore_gpr > last))
9902 continue;
9903 if (REGNO (base) != STACK_POINTER_REGNUM
9904 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9905 continue;
9906 if (first > BASE_REGNUM || last < BASE_REGNUM)
9907 continue;
9908
9909 if (cfun_frame_layout.first_restore_gpr != -1)
9910 {
9911 new_insn = restore_gprs (base,
9912 off + (cfun_frame_layout.first_restore_gpr
9913 - first) * UNITS_PER_LONG,
9914 cfun_frame_layout.first_restore_gpr,
9915 cfun_frame_layout.last_restore_gpr);
9916 new_insn = emit_insn_before (new_insn, insn);
9917 INSN_ADDRESSES_NEW (new_insn, -1);
9918 }
9919
9920 remove_insn (insn);
9921 continue;
9922 }
9923
9924 if (cfun_frame_layout.first_restore_gpr == -1
9925 && GET_CODE (PATTERN (insn)) == SET
9926 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9927 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9928 || (!TARGET_CPU_ZARCH
9929 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9930 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9931 {
9932 set = PATTERN (insn);
9933 first = REGNO (SET_DEST (set));
9934 offset = const0_rtx;
9935 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9936 off = INTVAL (offset);
9937
9938 if (GET_CODE (base) != REG || off < 0)
9939 continue;
9940 if (REGNO (base) != STACK_POINTER_REGNUM
9941 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9942 continue;
9943
9944 remove_insn (insn);
9945 continue;
9946 }
9947 }
9948 }
9949
9950 /* On z10 and later the dynamic branch prediction must see the
9951 backward jump within a certain windows. If not it falls back to
9952 the static prediction. This function rearranges the loop backward
9953 branch in a way which makes the static prediction always correct.
9954 The function returns true if it added an instruction. */
9955 static bool
9956 s390_fix_long_loop_prediction (rtx insn)
9957 {
9958 rtx set = single_set (insn);
9959 rtx code_label, label_ref, new_label;
9960 rtx uncond_jump;
9961 rtx cur_insn;
9962 rtx tmp;
9963 int distance;
9964
9965 /* This will exclude branch on count and branch on index patterns
9966 since these are correctly statically predicted. */
9967 if (!set
9968 || SET_DEST (set) != pc_rtx
9969 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9970 return false;
9971
9972 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9973 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9974
9975 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9976
9977 code_label = XEXP (label_ref, 0);
9978
9979 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9980 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9981 || (INSN_ADDRESSES (INSN_UID (insn))
9982 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
9983 return false;
9984
9985 for (distance = 0, cur_insn = PREV_INSN (insn);
9986 distance < PREDICT_DISTANCE - 6;
9987 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9988 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
9989 return false;
9990
9991 new_label = gen_label_rtx ();
9992 uncond_jump = emit_jump_insn_after (
9993 gen_rtx_SET (VOIDmode, pc_rtx,
9994 gen_rtx_LABEL_REF (VOIDmode, code_label)),
9995 insn);
9996 emit_label_after (new_label, uncond_jump);
9997
9998 tmp = XEXP (SET_SRC (set), 1);
9999 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10000 XEXP (SET_SRC (set), 2) = tmp;
10001 INSN_CODE (insn) = -1;
10002
10003 XEXP (label_ref, 0) = new_label;
10004 JUMP_LABEL (insn) = new_label;
10005 JUMP_LABEL (uncond_jump) = code_label;
10006
10007 return true;
10008 }
10009
10010 /* Returns 1 if INSN reads the value of REG for purposes not related
10011 to addressing of memory, and 0 otherwise. */
10012 static int
10013 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10014 {
10015 return reg_referenced_p (reg, PATTERN (insn))
10016 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10017 }
10018
10019 /* Starting from INSN find_cond_jump looks downwards in the insn
10020 stream for a single jump insn which is the last user of the
10021 condition code set in INSN. */
10022 static rtx
10023 find_cond_jump (rtx insn)
10024 {
10025 for (; insn; insn = NEXT_INSN (insn))
10026 {
10027 rtx ite, cc;
10028
10029 if (LABEL_P (insn))
10030 break;
10031
10032 if (!JUMP_P (insn))
10033 {
10034 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10035 break;
10036 continue;
10037 }
10038
10039 /* This will be triggered by a return. */
10040 if (GET_CODE (PATTERN (insn)) != SET)
10041 break;
10042
10043 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10044 ite = SET_SRC (PATTERN (insn));
10045
10046 if (GET_CODE (ite) != IF_THEN_ELSE)
10047 break;
10048
10049 cc = XEXP (XEXP (ite, 0), 0);
10050 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10051 break;
10052
10053 if (find_reg_note (insn, REG_DEAD, cc))
10054 return insn;
10055 break;
10056 }
10057
10058 return NULL_RTX;
10059 }
10060
10061 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10062 the semantics does not change. If NULL_RTX is passed as COND the
10063 function tries to find the conditional jump starting with INSN. */
10064 static void
10065 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10066 {
10067 rtx tmp = *op0;
10068
10069 if (cond == NULL_RTX)
10070 {
10071 rtx jump = find_cond_jump (NEXT_INSN (insn));
10072 jump = jump ? single_set (jump) : NULL_RTX;
10073
10074 if (jump == NULL_RTX)
10075 return;
10076
10077 cond = XEXP (XEXP (jump, 1), 0);
10078 }
10079
10080 *op0 = *op1;
10081 *op1 = tmp;
10082 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10083 }
10084
10085 /* On z10, instructions of the compare-and-branch family have the
10086 property to access the register occurring as second operand with
10087 its bits complemented. If such a compare is grouped with a second
10088 instruction that accesses the same register non-complemented, and
10089 if that register's value is delivered via a bypass, then the
10090 pipeline recycles, thereby causing significant performance decline.
10091 This function locates such situations and exchanges the two
10092 operands of the compare. The function return true whenever it
10093 added an insn. */
10094 static bool
10095 s390_z10_optimize_cmp (rtx insn)
10096 {
10097 rtx prev_insn, next_insn;
10098 bool insn_added_p = false;
10099 rtx cond, *op0, *op1;
10100
10101 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10102 {
10103 /* Handle compare and branch and branch on count
10104 instructions. */
10105 rtx pattern = single_set (insn);
10106
10107 if (!pattern
10108 || SET_DEST (pattern) != pc_rtx
10109 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10110 return false;
10111
10112 cond = XEXP (SET_SRC (pattern), 0);
10113 op0 = &XEXP (cond, 0);
10114 op1 = &XEXP (cond, 1);
10115 }
10116 else if (GET_CODE (PATTERN (insn)) == SET)
10117 {
10118 rtx src, dest;
10119
10120 /* Handle normal compare instructions. */
10121 src = SET_SRC (PATTERN (insn));
10122 dest = SET_DEST (PATTERN (insn));
10123
10124 if (!REG_P (dest)
10125 || !CC_REGNO_P (REGNO (dest))
10126 || GET_CODE (src) != COMPARE)
10127 return false;
10128
10129 /* s390_swap_cmp will try to find the conditional
10130 jump when passing NULL_RTX as condition. */
10131 cond = NULL_RTX;
10132 op0 = &XEXP (src, 0);
10133 op1 = &XEXP (src, 1);
10134 }
10135 else
10136 return false;
10137
10138 if (!REG_P (*op0) || !REG_P (*op1))
10139 return false;
10140
10141 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10142 return false;
10143
10144 /* Swap the COMPARE arguments and its mask if there is a
10145 conflicting access in the previous insn. */
10146 prev_insn = prev_active_insn (insn);
10147 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10148 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10149 s390_swap_cmp (cond, op0, op1, insn);
10150
10151 /* Check if there is a conflict with the next insn. If there
10152 was no conflict with the previous insn, then swap the
10153 COMPARE arguments and its mask. If we already swapped
10154 the operands, or if swapping them would cause a conflict
10155 with the previous insn, issue a NOP after the COMPARE in
10156 order to separate the two instuctions. */
10157 next_insn = next_active_insn (insn);
10158 if (next_insn != NULL_RTX && INSN_P (next_insn)
10159 && s390_non_addr_reg_read_p (*op1, next_insn))
10160 {
10161 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10162 && s390_non_addr_reg_read_p (*op0, prev_insn))
10163 {
10164 if (REGNO (*op1) == 0)
10165 emit_insn_after (gen_nop1 (), insn);
10166 else
10167 emit_insn_after (gen_nop (), insn);
10168 insn_added_p = true;
10169 }
10170 else
10171 s390_swap_cmp (cond, op0, op1, insn);
10172 }
10173 return insn_added_p;
10174 }
10175
10176 /* Perform machine-dependent processing. */
10177
10178 static void
10179 s390_reorg (void)
10180 {
10181 bool pool_overflow = false;
10182
10183 /* Make sure all splits have been performed; splits after
10184 machine_dependent_reorg might confuse insn length counts. */
10185 split_all_insns_noflow ();
10186
10187 /* Install the main literal pool and the associated base
10188 register load insns.
10189
10190 In addition, there are two problematic situations we need
10191 to correct:
10192
10193 - the literal pool might be > 4096 bytes in size, so that
10194 some of its elements cannot be directly accessed
10195
10196 - a branch target might be > 64K away from the branch, so that
10197 it is not possible to use a PC-relative instruction.
10198
10199 To fix those, we split the single literal pool into multiple
10200 pool chunks, reloading the pool base register at various
10201 points throughout the function to ensure it always points to
10202 the pool chunk the following code expects, and / or replace
10203 PC-relative branches by absolute branches.
10204
10205 However, the two problems are interdependent: splitting the
10206 literal pool can move a branch further away from its target,
10207 causing the 64K limit to overflow, and on the other hand,
10208 replacing a PC-relative branch by an absolute branch means
10209 we need to put the branch target address into the literal
10210 pool, possibly causing it to overflow.
10211
10212 So, we loop trying to fix up both problems until we manage
10213 to satisfy both conditions at the same time. Note that the
10214 loop is guaranteed to terminate as every pass of the loop
10215 strictly decreases the total number of PC-relative branches
10216 in the function. (This is not completely true as there
10217 might be branch-over-pool insns introduced by chunkify_start.
10218 Those never need to be split however.) */
10219
10220 for (;;)
10221 {
10222 struct constant_pool *pool = NULL;
10223
10224 /* Collect the literal pool. */
10225 if (!pool_overflow)
10226 {
10227 pool = s390_mainpool_start ();
10228 if (!pool)
10229 pool_overflow = true;
10230 }
10231
10232 /* If literal pool overflowed, start to chunkify it. */
10233 if (pool_overflow)
10234 pool = s390_chunkify_start ();
10235
10236 /* Split out-of-range branches. If this has created new
10237 literal pool entries, cancel current chunk list and
10238 recompute it. zSeries machines have large branch
10239 instructions, so we never need to split a branch. */
10240 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10241 {
10242 if (pool_overflow)
10243 s390_chunkify_cancel (pool);
10244 else
10245 s390_mainpool_cancel (pool);
10246
10247 continue;
10248 }
10249
10250 /* If we made it up to here, both conditions are satisfied.
10251 Finish up literal pool related changes. */
10252 if (pool_overflow)
10253 s390_chunkify_finish (pool);
10254 else
10255 s390_mainpool_finish (pool);
10256
10257 /* We're done splitting branches. */
10258 cfun->machine->split_branches_pending_p = false;
10259 break;
10260 }
10261
10262 /* Generate out-of-pool execute target insns. */
10263 if (TARGET_CPU_ZARCH)
10264 {
10265 rtx insn, label, target;
10266
10267 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10268 {
10269 label = s390_execute_label (insn);
10270 if (!label)
10271 continue;
10272
10273 gcc_assert (label != const0_rtx);
10274
10275 target = emit_label (XEXP (label, 0));
10276 INSN_ADDRESSES_NEW (target, -1);
10277
10278 target = emit_insn (s390_execute_target (insn));
10279 INSN_ADDRESSES_NEW (target, -1);
10280 }
10281 }
10282
10283 /* Try to optimize prologue and epilogue further. */
10284 s390_optimize_prologue ();
10285
10286 /* Walk over the insns and do some >=z10 specific changes. */
10287 if (s390_tune == PROCESSOR_2097_Z10
10288 || s390_tune == PROCESSOR_2817_Z196)
10289 {
10290 rtx insn;
10291 bool insn_added_p = false;
10292
10293 /* The insn lengths and addresses have to be up to date for the
10294 following manipulations. */
10295 shorten_branches (get_insns ());
10296
10297 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10298 {
10299 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10300 continue;
10301
10302 if (JUMP_P (insn))
10303 insn_added_p |= s390_fix_long_loop_prediction (insn);
10304
10305 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10306 || GET_CODE (PATTERN (insn)) == SET)
10307 && s390_tune == PROCESSOR_2097_Z10)
10308 insn_added_p |= s390_z10_optimize_cmp (insn);
10309 }
10310
10311 /* Adjust branches if we added new instructions. */
10312 if (insn_added_p)
10313 shorten_branches (get_insns ());
10314 }
10315 }
10316
10317 /* Return true if INSN is a fp load insn writing register REGNO. */
10318 static inline bool
10319 s390_fpload_toreg (rtx insn, unsigned int regno)
10320 {
10321 rtx set;
10322 enum attr_type flag = s390_safe_attr_type (insn);
10323
10324 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10325 return false;
10326
10327 set = single_set (insn);
10328
10329 if (set == NULL_RTX)
10330 return false;
10331
10332 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10333 return false;
10334
10335 if (REGNO (SET_DEST (set)) != regno)
10336 return false;
10337
10338 return true;
10339 }
10340
10341 /* This value describes the distance to be avoided between an
10342 aritmetic fp instruction and an fp load writing the same register.
10343 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10344 fine but the exact value has to be avoided. Otherwise the FP
10345 pipeline will throw an exception causing a major penalty. */
10346 #define Z10_EARLYLOAD_DISTANCE 7
10347
10348 /* Rearrange the ready list in order to avoid the situation described
10349 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10350 moved to the very end of the ready list. */
10351 static void
10352 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10353 {
10354 unsigned int regno;
10355 int nready = *nready_p;
10356 rtx tmp;
10357 int i;
10358 rtx insn;
10359 rtx set;
10360 enum attr_type flag;
10361 int distance;
10362
10363 /* Skip DISTANCE - 1 active insns. */
10364 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10365 distance > 0 && insn != NULL_RTX;
10366 distance--, insn = prev_active_insn (insn))
10367 if (CALL_P (insn) || JUMP_P (insn))
10368 return;
10369
10370 if (insn == NULL_RTX)
10371 return;
10372
10373 set = single_set (insn);
10374
10375 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10376 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10377 return;
10378
10379 flag = s390_safe_attr_type (insn);
10380
10381 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10382 return;
10383
10384 regno = REGNO (SET_DEST (set));
10385 i = nready - 1;
10386
10387 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10388 i--;
10389
10390 if (!i)
10391 return;
10392
10393 tmp = ready[i];
10394 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10395 ready[0] = tmp;
10396 }
10397
10398 /* This function is called via hook TARGET_SCHED_REORDER before
10399 issueing one insn from list READY which contains *NREADYP entries.
10400 For target z10 it reorders load instructions to avoid early load
10401 conflicts in the floating point pipeline */
10402 static int
10403 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10404 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10405 {
10406 if (s390_tune == PROCESSOR_2097_Z10)
10407 if (reload_completed && *nreadyp > 1)
10408 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10409
10410 return s390_issue_rate ();
10411 }
10412
10413 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10414 the scheduler has issued INSN. It stores the last issued insn into
10415 last_scheduled_insn in order to make it available for
10416 s390_sched_reorder. */
10417 static int
10418 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10419 int verbose ATTRIBUTE_UNUSED,
10420 rtx insn, int more)
10421 {
10422 last_scheduled_insn = insn;
10423
10424 if (GET_CODE (PATTERN (insn)) != USE
10425 && GET_CODE (PATTERN (insn)) != CLOBBER)
10426 return more - 1;
10427 else
10428 return more;
10429 }
10430
10431 static void
10432 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10433 int verbose ATTRIBUTE_UNUSED,
10434 int max_ready ATTRIBUTE_UNUSED)
10435 {
10436 last_scheduled_insn = NULL_RTX;
10437 }
10438
10439 /* This function checks the whole of insn X for memory references. The
10440 function always returns zero because the framework it is called
10441 from would stop recursively analyzing the insn upon a return value
10442 other than zero. The real result of this function is updating
10443 counter variable MEM_COUNT. */
10444 static int
10445 check_dpu (rtx *x, unsigned *mem_count)
10446 {
10447 if (*x != NULL_RTX && MEM_P (*x))
10448 (*mem_count)++;
10449 return 0;
10450 }
10451
10452 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10453 a new number struct loop *loop should be unrolled if tuned for cpus with
10454 a built-in stride prefetcher.
10455 The loop is analyzed for memory accesses by calling check_dpu for
10456 each rtx of the loop. Depending on the loop_depth and the amount of
10457 memory accesses a new number <=nunroll is returned to improve the
10458 behaviour of the hardware prefetch unit. */
10459 static unsigned
10460 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10461 {
10462 basic_block *bbs;
10463 rtx insn;
10464 unsigned i;
10465 unsigned mem_count = 0;
10466
10467 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10468 return nunroll;
10469
10470 /* Count the number of memory references within the loop body. */
10471 bbs = get_loop_body (loop);
10472 for (i = 0; i < loop->num_nodes; i++)
10473 {
10474 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10475 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10476 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10477 }
10478 free (bbs);
10479
10480 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10481 if (mem_count == 0)
10482 return nunroll;
10483
10484 switch (loop_depth(loop))
10485 {
10486 case 1:
10487 return MIN (nunroll, 28 / mem_count);
10488 case 2:
10489 return MIN (nunroll, 22 / mem_count);
10490 default:
10491 return MIN (nunroll, 16 / mem_count);
10492 }
10493 }
10494
10495 /* Initialize GCC target structure. */
10496
10497 #undef TARGET_ASM_ALIGNED_HI_OP
10498 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10499 #undef TARGET_ASM_ALIGNED_DI_OP
10500 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10501 #undef TARGET_ASM_INTEGER
10502 #define TARGET_ASM_INTEGER s390_assemble_integer
10503
10504 #undef TARGET_ASM_OPEN_PAREN
10505 #define TARGET_ASM_OPEN_PAREN ""
10506
10507 #undef TARGET_ASM_CLOSE_PAREN
10508 #define TARGET_ASM_CLOSE_PAREN ""
10509
10510 #undef TARGET_DEFAULT_TARGET_FLAGS
10511 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10512
10513 #undef TARGET_HANDLE_OPTION
10514 #define TARGET_HANDLE_OPTION s390_handle_option
10515
10516 #undef TARGET_OPTION_OVERRIDE
10517 #define TARGET_OPTION_OVERRIDE s390_option_override
10518
10519 #undef TARGET_OPTION_OPTIMIZATION_TABLE
10520 #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table
10521
10522 #undef TARGET_OPTION_INIT_STRUCT
10523 #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct
10524
10525 #undef TARGET_ENCODE_SECTION_INFO
10526 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10527
10528 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10529 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10530
10531 #ifdef HAVE_AS_TLS
10532 #undef TARGET_HAVE_TLS
10533 #define TARGET_HAVE_TLS true
10534 #endif
10535 #undef TARGET_CANNOT_FORCE_CONST_MEM
10536 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10537
10538 #undef TARGET_DELEGITIMIZE_ADDRESS
10539 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10540
10541 #undef TARGET_LEGITIMIZE_ADDRESS
10542 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10543
10544 #undef TARGET_RETURN_IN_MEMORY
10545 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10546
10547 #undef TARGET_INIT_BUILTINS
10548 #define TARGET_INIT_BUILTINS s390_init_builtins
10549 #undef TARGET_EXPAND_BUILTIN
10550 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10551
10552 #undef TARGET_ASM_OUTPUT_MI_THUNK
10553 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10554 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10555 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10556
10557 #undef TARGET_SCHED_ADJUST_PRIORITY
10558 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10559 #undef TARGET_SCHED_ISSUE_RATE
10560 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10561 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10562 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10563
10564 #undef TARGET_SCHED_VARIABLE_ISSUE
10565 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10566 #undef TARGET_SCHED_REORDER
10567 #define TARGET_SCHED_REORDER s390_sched_reorder
10568 #undef TARGET_SCHED_INIT
10569 #define TARGET_SCHED_INIT s390_sched_init
10570
10571 #undef TARGET_CANNOT_COPY_INSN_P
10572 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10573 #undef TARGET_RTX_COSTS
10574 #define TARGET_RTX_COSTS s390_rtx_costs
10575 #undef TARGET_ADDRESS_COST
10576 #define TARGET_ADDRESS_COST s390_address_cost
10577
10578 #undef TARGET_MACHINE_DEPENDENT_REORG
10579 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10580
10581 #undef TARGET_VALID_POINTER_MODE
10582 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10583
10584 #undef TARGET_BUILD_BUILTIN_VA_LIST
10585 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10586 #undef TARGET_EXPAND_BUILTIN_VA_START
10587 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10588 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10589 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10590
10591 #undef TARGET_PROMOTE_FUNCTION_MODE
10592 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10593 #undef TARGET_PASS_BY_REFERENCE
10594 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10595
10596 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10597 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10598 #undef TARGET_FUNCTION_ARG
10599 #define TARGET_FUNCTION_ARG s390_function_arg
10600 #undef TARGET_FUNCTION_ARG_ADVANCE
10601 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10602
10603 #undef TARGET_FIXED_CONDITION_CODE_REGS
10604 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10605
10606 #undef TARGET_CC_MODES_COMPATIBLE
10607 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10608
10609 #undef TARGET_INVALID_WITHIN_DOLOOP
10610 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10611
10612 #ifdef HAVE_AS_TLS
10613 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10614 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10615 #endif
10616
10617 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10618 #undef TARGET_MANGLE_TYPE
10619 #define TARGET_MANGLE_TYPE s390_mangle_type
10620 #endif
10621
10622 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10623 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10624
10625 #undef TARGET_SECONDARY_RELOAD
10626 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10627
10628 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10629 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10630
10631 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10632 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10633
10634 #undef TARGET_LEGITIMATE_ADDRESS_P
10635 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10636
10637 #undef TARGET_CAN_ELIMINATE
10638 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10639
10640 #undef TARGET_LOOP_UNROLL_ADJUST
10641 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10642
10643 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10644 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10645 #undef TARGET_TRAMPOLINE_INIT
10646 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10647
10648 #undef TARGET_UNWIND_WORD_MODE
10649 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10650
10651 struct gcc_target targetm = TARGET_INITIALIZER;
10652
10653 #include "gt-s390.h"