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function.h (struct function): Add can_throw_non_call_exceptions bit.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "toplev.h"
44 #include "basic-block.h"
45 #include "integrate.h"
46 #include "ggc.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "debug.h"
50 #include "langhooks.h"
51 #include "optabs.h"
52 #include "gimple.h"
53 #include "df.h"
54 #include "params.h"
55 #include "cfgloop.h"
56
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 extern int reload_completed;
226
227 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
228 static rtx last_scheduled_insn;
229
230 /* Structure used to hold the components of a S/390 memory
231 address. A legitimate address on S/390 is of the general
232 form
233 base + index + displacement
234 where any of the components is optional.
235
236 base and index are registers of the class ADDR_REGS,
237 displacement is an unsigned 12-bit immediate constant. */
238
239 struct s390_address
240 {
241 rtx base;
242 rtx indx;
243 rtx disp;
244 bool pointer;
245 bool literal_pool;
246 };
247
248 /* Which cpu are we tuning for. */
249 enum processor_type s390_tune = PROCESSOR_max;
250 int s390_tune_flags;
251 /* Which instruction set architecture to use. */
252 enum processor_type s390_arch;
253 int s390_arch_flags;
254
255 HOST_WIDE_INT s390_warn_framesize = 0;
256 HOST_WIDE_INT s390_stack_size = 0;
257 HOST_WIDE_INT s390_stack_guard = 0;
258
259 /* The following structure is embedded in the machine
260 specific part of struct function. */
261
262 struct GTY (()) s390_frame_layout
263 {
264 /* Offset within stack frame. */
265 HOST_WIDE_INT gprs_offset;
266 HOST_WIDE_INT f0_offset;
267 HOST_WIDE_INT f4_offset;
268 HOST_WIDE_INT f8_offset;
269 HOST_WIDE_INT backchain_offset;
270
271 /* Number of first and last gpr where slots in the register
272 save area are reserved for. */
273 int first_save_gpr_slot;
274 int last_save_gpr_slot;
275
276 /* Number of first and last gpr to be saved, restored. */
277 int first_save_gpr;
278 int first_restore_gpr;
279 int last_save_gpr;
280 int last_restore_gpr;
281
282 /* Bits standing for floating point registers. Set, if the
283 respective register has to be saved. Starting with reg 16 (f0)
284 at the rightmost bit.
285 Bit 15 - 8 7 6 5 4 3 2 1 0
286 fpr 15 - 8 7 5 3 1 6 4 2 0
287 reg 31 - 24 23 22 21 20 19 18 17 16 */
288 unsigned int fpr_bitmap;
289
290 /* Number of floating point registers f8-f15 which must be saved. */
291 int high_fprs;
292
293 /* Set if return address needs to be saved.
294 This flag is set by s390_return_addr_rtx if it could not use
295 the initial value of r14 and therefore depends on r14 saved
296 to the stack. */
297 bool save_return_addr_p;
298
299 /* Size of stack frame. */
300 HOST_WIDE_INT frame_size;
301 };
302
303 /* Define the structure for the machine field in struct function. */
304
305 struct GTY(()) machine_function
306 {
307 struct s390_frame_layout frame_layout;
308
309 /* Literal pool base register. */
310 rtx base_reg;
311
312 /* True if we may need to perform branch splitting. */
313 bool split_branches_pending_p;
314
315 /* Some local-dynamic TLS symbol name. */
316 const char *some_ld_name;
317
318 bool has_landing_pad_p;
319 };
320
321 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
322
323 #define cfun_frame_layout (cfun->machine->frame_layout)
324 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
325 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
326 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
327 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
328 (1 << (BITNUM)))
329 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
330 (1 << (BITNUM))))
331
332 /* Number of GPRs and FPRs used for argument passing. */
333 #define GP_ARG_NUM_REG 5
334 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
335
336 /* A couple of shortcuts. */
337 #define CONST_OK_FOR_J(x) \
338 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
339 #define CONST_OK_FOR_K(x) \
340 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
341 #define CONST_OK_FOR_Os(x) \
342 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
343 #define CONST_OK_FOR_Op(x) \
344 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
345 #define CONST_OK_FOR_On(x) \
346 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
347
348 #define REGNO_PAIR_OK(REGNO, MODE) \
349 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
350
351 /* That's the read ahead of the dynamic branch prediction unit in
352 bytes on a z10 CPU. */
353 #define Z10_PREDICT_DISTANCE 384
354
355 static enum machine_mode
356 s390_libgcc_cmp_return_mode (void)
357 {
358 return TARGET_64BIT ? DImode : SImode;
359 }
360
361 static enum machine_mode
362 s390_libgcc_shift_count_mode (void)
363 {
364 return TARGET_64BIT ? DImode : SImode;
365 }
366
367 static enum machine_mode
368 s390_unwind_word_mode (void)
369 {
370 return TARGET_64BIT ? DImode : SImode;
371 }
372
373 /* Return true if the back end supports mode MODE. */
374 static bool
375 s390_scalar_mode_supported_p (enum machine_mode mode)
376 {
377 /* In contrast to the default implementation reject TImode constants on 31bit
378 TARGET_ZARCH for ABI compliance. */
379 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
380 return false;
381
382 if (DECIMAL_FLOAT_MODE_P (mode))
383 return default_decimal_float_supported_p ();
384
385 return default_scalar_mode_supported_p (mode);
386 }
387
388 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
389
390 void
391 s390_set_has_landing_pad_p (bool value)
392 {
393 cfun->machine->has_landing_pad_p = value;
394 }
395
396 /* If two condition code modes are compatible, return a condition code
397 mode which is compatible with both. Otherwise, return
398 VOIDmode. */
399
400 static enum machine_mode
401 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
402 {
403 if (m1 == m2)
404 return m1;
405
406 switch (m1)
407 {
408 case CCZmode:
409 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
410 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
411 return m2;
412 return VOIDmode;
413
414 case CCSmode:
415 case CCUmode:
416 case CCTmode:
417 case CCSRmode:
418 case CCURmode:
419 case CCZ1mode:
420 if (m2 == CCZmode)
421 return m1;
422
423 return VOIDmode;
424
425 default:
426 return VOIDmode;
427 }
428 return VOIDmode;
429 }
430
431 /* Return true if SET either doesn't set the CC register, or else
432 the source and destination have matching CC modes and that
433 CC mode is at least as constrained as REQ_MODE. */
434
435 static bool
436 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
437 {
438 enum machine_mode set_mode;
439
440 gcc_assert (GET_CODE (set) == SET);
441
442 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
443 return 1;
444
445 set_mode = GET_MODE (SET_DEST (set));
446 switch (set_mode)
447 {
448 case CCSmode:
449 case CCSRmode:
450 case CCUmode:
451 case CCURmode:
452 case CCLmode:
453 case CCL1mode:
454 case CCL2mode:
455 case CCL3mode:
456 case CCT1mode:
457 case CCT2mode:
458 case CCT3mode:
459 if (req_mode != set_mode)
460 return 0;
461 break;
462
463 case CCZmode:
464 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
465 && req_mode != CCSRmode && req_mode != CCURmode)
466 return 0;
467 break;
468
469 case CCAPmode:
470 case CCANmode:
471 if (req_mode != CCAmode)
472 return 0;
473 break;
474
475 default:
476 gcc_unreachable ();
477 }
478
479 return (GET_MODE (SET_SRC (set)) == set_mode);
480 }
481
482 /* Return true if every SET in INSN that sets the CC register
483 has source and destination with matching CC modes and that
484 CC mode is at least as constrained as REQ_MODE.
485 If REQ_MODE is VOIDmode, always return false. */
486
487 bool
488 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
489 {
490 int i;
491
492 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
493 if (req_mode == VOIDmode)
494 return false;
495
496 if (GET_CODE (PATTERN (insn)) == SET)
497 return s390_match_ccmode_set (PATTERN (insn), req_mode);
498
499 if (GET_CODE (PATTERN (insn)) == PARALLEL)
500 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
501 {
502 rtx set = XVECEXP (PATTERN (insn), 0, i);
503 if (GET_CODE (set) == SET)
504 if (!s390_match_ccmode_set (set, req_mode))
505 return false;
506 }
507
508 return true;
509 }
510
511 /* If a test-under-mask instruction can be used to implement
512 (compare (and ... OP1) OP2), return the CC mode required
513 to do that. Otherwise, return VOIDmode.
514 MIXED is true if the instruction can distinguish between
515 CC1 and CC2 for mixed selected bits (TMxx), it is false
516 if the instruction cannot (TM). */
517
518 enum machine_mode
519 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
520 {
521 int bit0, bit1;
522
523 /* ??? Fixme: should work on CONST_DOUBLE as well. */
524 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
525 return VOIDmode;
526
527 /* Selected bits all zero: CC0.
528 e.g.: int a; if ((a & (16 + 128)) == 0) */
529 if (INTVAL (op2) == 0)
530 return CCTmode;
531
532 /* Selected bits all one: CC3.
533 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
534 if (INTVAL (op2) == INTVAL (op1))
535 return CCT3mode;
536
537 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
538 int a;
539 if ((a & (16 + 128)) == 16) -> CCT1
540 if ((a & (16 + 128)) == 128) -> CCT2 */
541 if (mixed)
542 {
543 bit1 = exact_log2 (INTVAL (op2));
544 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
545 if (bit0 != -1 && bit1 != -1)
546 return bit0 > bit1 ? CCT1mode : CCT2mode;
547 }
548
549 return VOIDmode;
550 }
551
552 /* Given a comparison code OP (EQ, NE, etc.) and the operands
553 OP0 and OP1 of a COMPARE, return the mode to be used for the
554 comparison. */
555
556 enum machine_mode
557 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
558 {
559 switch (code)
560 {
561 case EQ:
562 case NE:
563 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
564 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
565 return CCAPmode;
566 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
567 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
568 return CCAPmode;
569 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
570 || GET_CODE (op1) == NEG)
571 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
572 return CCLmode;
573
574 if (GET_CODE (op0) == AND)
575 {
576 /* Check whether we can potentially do it via TM. */
577 enum machine_mode ccmode;
578 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
579 if (ccmode != VOIDmode)
580 {
581 /* Relax CCTmode to CCZmode to allow fall-back to AND
582 if that turns out to be beneficial. */
583 return ccmode == CCTmode ? CCZmode : ccmode;
584 }
585 }
586
587 if (register_operand (op0, HImode)
588 && GET_CODE (op1) == CONST_INT
589 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
590 return CCT3mode;
591 if (register_operand (op0, QImode)
592 && GET_CODE (op1) == CONST_INT
593 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
594 return CCT3mode;
595
596 return CCZmode;
597
598 case LE:
599 case LT:
600 case GE:
601 case GT:
602 /* The only overflow condition of NEG and ABS happens when
603 -INT_MAX is used as parameter, which stays negative. So
604 we have an overflow from a positive value to a negative.
605 Using CCAP mode the resulting cc can be used for comparisons. */
606 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
607 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
608 return CCAPmode;
609
610 /* If constants are involved in an add instruction it is possible to use
611 the resulting cc for comparisons with zero. Knowing the sign of the
612 constant the overflow behavior gets predictable. e.g.:
613 int a, b; if ((b = a + c) > 0)
614 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
615 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
616 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
617 {
618 if (INTVAL (XEXP((op0), 1)) < 0)
619 return CCANmode;
620 else
621 return CCAPmode;
622 }
623 /* Fall through. */
624 case UNORDERED:
625 case ORDERED:
626 case UNEQ:
627 case UNLE:
628 case UNLT:
629 case UNGE:
630 case UNGT:
631 case LTGT:
632 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
633 && GET_CODE (op1) != CONST_INT)
634 return CCSRmode;
635 return CCSmode;
636
637 case LTU:
638 case GEU:
639 if (GET_CODE (op0) == PLUS
640 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
641 return CCL1mode;
642
643 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
644 && GET_CODE (op1) != CONST_INT)
645 return CCURmode;
646 return CCUmode;
647
648 case LEU:
649 case GTU:
650 if (GET_CODE (op0) == MINUS
651 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
652 return CCL2mode;
653
654 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
655 && GET_CODE (op1) != CONST_INT)
656 return CCURmode;
657 return CCUmode;
658
659 default:
660 gcc_unreachable ();
661 }
662 }
663
664 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
665 that we can implement more efficiently. */
666
667 void
668 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
669 {
670 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
671 if ((*code == EQ || *code == NE)
672 && *op1 == const0_rtx
673 && GET_CODE (*op0) == ZERO_EXTRACT
674 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
675 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
676 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
677 {
678 rtx inner = XEXP (*op0, 0);
679 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
680 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
681 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
682
683 if (len > 0 && len < modesize
684 && pos >= 0 && pos + len <= modesize
685 && modesize <= HOST_BITS_PER_WIDE_INT)
686 {
687 unsigned HOST_WIDE_INT block;
688 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
689 block <<= modesize - pos - len;
690
691 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
692 gen_int_mode (block, GET_MODE (inner)));
693 }
694 }
695
696 /* Narrow AND of memory against immediate to enable TM. */
697 if ((*code == EQ || *code == NE)
698 && *op1 == const0_rtx
699 && GET_CODE (*op0) == AND
700 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
701 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
702 {
703 rtx inner = XEXP (*op0, 0);
704 rtx mask = XEXP (*op0, 1);
705
706 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
707 if (GET_CODE (inner) == SUBREG
708 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
709 && (GET_MODE_SIZE (GET_MODE (inner))
710 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
711 && ((INTVAL (mask)
712 & GET_MODE_MASK (GET_MODE (inner))
713 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
714 == 0))
715 inner = SUBREG_REG (inner);
716
717 /* Do not change volatile MEMs. */
718 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
719 {
720 int part = s390_single_part (XEXP (*op0, 1),
721 GET_MODE (inner), QImode, 0);
722 if (part >= 0)
723 {
724 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
725 inner = adjust_address_nv (inner, QImode, part);
726 *op0 = gen_rtx_AND (QImode, inner, mask);
727 }
728 }
729 }
730
731 /* Narrow comparisons against 0xffff to HImode if possible. */
732 if ((*code == EQ || *code == NE)
733 && GET_CODE (*op1) == CONST_INT
734 && INTVAL (*op1) == 0xffff
735 && SCALAR_INT_MODE_P (GET_MODE (*op0))
736 && (nonzero_bits (*op0, GET_MODE (*op0))
737 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
738 {
739 *op0 = gen_lowpart (HImode, *op0);
740 *op1 = constm1_rtx;
741 }
742
743 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
744 if (GET_CODE (*op0) == UNSPEC
745 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
746 && XVECLEN (*op0, 0) == 1
747 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
748 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
749 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
750 && *op1 == const0_rtx)
751 {
752 enum rtx_code new_code = UNKNOWN;
753 switch (*code)
754 {
755 case EQ: new_code = EQ; break;
756 case NE: new_code = NE; break;
757 case LT: new_code = GTU; break;
758 case GT: new_code = LTU; break;
759 case LE: new_code = GEU; break;
760 case GE: new_code = LEU; break;
761 default: break;
762 }
763
764 if (new_code != UNKNOWN)
765 {
766 *op0 = XVECEXP (*op0, 0, 0);
767 *code = new_code;
768 }
769 }
770
771 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
772 if (GET_CODE (*op0) == UNSPEC
773 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
774 && XVECLEN (*op0, 0) == 1
775 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
776 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
777 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
778 && *op1 == const0_rtx)
779 {
780 enum rtx_code new_code = UNKNOWN;
781 switch (*code)
782 {
783 case EQ: new_code = EQ; break;
784 case NE: new_code = NE; break;
785 default: break;
786 }
787
788 if (new_code != UNKNOWN)
789 {
790 *op0 = XVECEXP (*op0, 0, 0);
791 *code = new_code;
792 }
793 }
794
795 /* Simplify cascaded EQ, NE with const0_rtx. */
796 if ((*code == NE || *code == EQ)
797 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
798 && GET_MODE (*op0) == SImode
799 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
800 && REG_P (XEXP (*op0, 0))
801 && XEXP (*op0, 1) == const0_rtx
802 && *op1 == const0_rtx)
803 {
804 if ((*code == EQ && GET_CODE (*op0) == NE)
805 || (*code == NE && GET_CODE (*op0) == EQ))
806 *code = EQ;
807 else
808 *code = NE;
809 *op0 = XEXP (*op0, 0);
810 }
811
812 /* Prefer register over memory as first operand. */
813 if (MEM_P (*op0) && REG_P (*op1))
814 {
815 rtx tem = *op0; *op0 = *op1; *op1 = tem;
816 *code = swap_condition (*code);
817 }
818 }
819
820 /* Emit a compare instruction suitable to implement the comparison
821 OP0 CODE OP1. Return the correct condition RTL to be placed in
822 the IF_THEN_ELSE of the conditional branch testing the result. */
823
824 rtx
825 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
826 {
827 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
828 rtx cc;
829
830 /* Do not output a redundant compare instruction if a compare_and_swap
831 pattern already computed the result and the machine modes are compatible. */
832 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
833 {
834 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
835 == GET_MODE (op0));
836 cc = op0;
837 }
838 else
839 {
840 cc = gen_rtx_REG (mode, CC_REGNUM);
841 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
842 }
843
844 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
845 }
846
847 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
848 matches CMP.
849 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
850 conditional branch testing the result. */
851
852 static rtx
853 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
854 {
855 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
856 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
857 }
858
859 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
860 unconditional jump, else a conditional jump under condition COND. */
861
862 void
863 s390_emit_jump (rtx target, rtx cond)
864 {
865 rtx insn;
866
867 target = gen_rtx_LABEL_REF (VOIDmode, target);
868 if (cond)
869 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
870
871 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
872 emit_jump_insn (insn);
873 }
874
875 /* Return branch condition mask to implement a branch
876 specified by CODE. Return -1 for invalid comparisons. */
877
878 int
879 s390_branch_condition_mask (rtx code)
880 {
881 const int CC0 = 1 << 3;
882 const int CC1 = 1 << 2;
883 const int CC2 = 1 << 1;
884 const int CC3 = 1 << 0;
885
886 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
887 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
888 gcc_assert (XEXP (code, 1) == const0_rtx);
889
890 switch (GET_MODE (XEXP (code, 0)))
891 {
892 case CCZmode:
893 case CCZ1mode:
894 switch (GET_CODE (code))
895 {
896 case EQ: return CC0;
897 case NE: return CC1 | CC2 | CC3;
898 default: return -1;
899 }
900 break;
901
902 case CCT1mode:
903 switch (GET_CODE (code))
904 {
905 case EQ: return CC1;
906 case NE: return CC0 | CC2 | CC3;
907 default: return -1;
908 }
909 break;
910
911 case CCT2mode:
912 switch (GET_CODE (code))
913 {
914 case EQ: return CC2;
915 case NE: return CC0 | CC1 | CC3;
916 default: return -1;
917 }
918 break;
919
920 case CCT3mode:
921 switch (GET_CODE (code))
922 {
923 case EQ: return CC3;
924 case NE: return CC0 | CC1 | CC2;
925 default: return -1;
926 }
927 break;
928
929 case CCLmode:
930 switch (GET_CODE (code))
931 {
932 case EQ: return CC0 | CC2;
933 case NE: return CC1 | CC3;
934 default: return -1;
935 }
936 break;
937
938 case CCL1mode:
939 switch (GET_CODE (code))
940 {
941 case LTU: return CC2 | CC3; /* carry */
942 case GEU: return CC0 | CC1; /* no carry */
943 default: return -1;
944 }
945 break;
946
947 case CCL2mode:
948 switch (GET_CODE (code))
949 {
950 case GTU: return CC0 | CC1; /* borrow */
951 case LEU: return CC2 | CC3; /* no borrow */
952 default: return -1;
953 }
954 break;
955
956 case CCL3mode:
957 switch (GET_CODE (code))
958 {
959 case EQ: return CC0 | CC2;
960 case NE: return CC1 | CC3;
961 case LTU: return CC1;
962 case GTU: return CC3;
963 case LEU: return CC1 | CC2;
964 case GEU: return CC2 | CC3;
965 default: return -1;
966 }
967
968 case CCUmode:
969 switch (GET_CODE (code))
970 {
971 case EQ: return CC0;
972 case NE: return CC1 | CC2 | CC3;
973 case LTU: return CC1;
974 case GTU: return CC2;
975 case LEU: return CC0 | CC1;
976 case GEU: return CC0 | CC2;
977 default: return -1;
978 }
979 break;
980
981 case CCURmode:
982 switch (GET_CODE (code))
983 {
984 case EQ: return CC0;
985 case NE: return CC2 | CC1 | CC3;
986 case LTU: return CC2;
987 case GTU: return CC1;
988 case LEU: return CC0 | CC2;
989 case GEU: return CC0 | CC1;
990 default: return -1;
991 }
992 break;
993
994 case CCAPmode:
995 switch (GET_CODE (code))
996 {
997 case EQ: return CC0;
998 case NE: return CC1 | CC2 | CC3;
999 case LT: return CC1 | CC3;
1000 case GT: return CC2;
1001 case LE: return CC0 | CC1 | CC3;
1002 case GE: return CC0 | CC2;
1003 default: return -1;
1004 }
1005 break;
1006
1007 case CCANmode:
1008 switch (GET_CODE (code))
1009 {
1010 case EQ: return CC0;
1011 case NE: return CC1 | CC2 | CC3;
1012 case LT: return CC1;
1013 case GT: return CC2 | CC3;
1014 case LE: return CC0 | CC1;
1015 case GE: return CC0 | CC2 | CC3;
1016 default: return -1;
1017 }
1018 break;
1019
1020 case CCSmode:
1021 switch (GET_CODE (code))
1022 {
1023 case EQ: return CC0;
1024 case NE: return CC1 | CC2 | CC3;
1025 case LT: return CC1;
1026 case GT: return CC2;
1027 case LE: return CC0 | CC1;
1028 case GE: return CC0 | CC2;
1029 case UNORDERED: return CC3;
1030 case ORDERED: return CC0 | CC1 | CC2;
1031 case UNEQ: return CC0 | CC3;
1032 case UNLT: return CC1 | CC3;
1033 case UNGT: return CC2 | CC3;
1034 case UNLE: return CC0 | CC1 | CC3;
1035 case UNGE: return CC0 | CC2 | CC3;
1036 case LTGT: return CC1 | CC2;
1037 default: return -1;
1038 }
1039 break;
1040
1041 case CCSRmode:
1042 switch (GET_CODE (code))
1043 {
1044 case EQ: return CC0;
1045 case NE: return CC2 | CC1 | CC3;
1046 case LT: return CC2;
1047 case GT: return CC1;
1048 case LE: return CC0 | CC2;
1049 case GE: return CC0 | CC1;
1050 case UNORDERED: return CC3;
1051 case ORDERED: return CC0 | CC2 | CC1;
1052 case UNEQ: return CC0 | CC3;
1053 case UNLT: return CC2 | CC3;
1054 case UNGT: return CC1 | CC3;
1055 case UNLE: return CC0 | CC2 | CC3;
1056 case UNGE: return CC0 | CC1 | CC3;
1057 case LTGT: return CC2 | CC1;
1058 default: return -1;
1059 }
1060 break;
1061
1062 default:
1063 return -1;
1064 }
1065 }
1066
1067
1068 /* Return branch condition mask to implement a compare and branch
1069 specified by CODE. Return -1 for invalid comparisons. */
1070
1071 int
1072 s390_compare_and_branch_condition_mask (rtx code)
1073 {
1074 const int CC0 = 1 << 3;
1075 const int CC1 = 1 << 2;
1076 const int CC2 = 1 << 1;
1077
1078 switch (GET_CODE (code))
1079 {
1080 case EQ:
1081 return CC0;
1082 case NE:
1083 return CC1 | CC2;
1084 case LT:
1085 case LTU:
1086 return CC1;
1087 case GT:
1088 case GTU:
1089 return CC2;
1090 case LE:
1091 case LEU:
1092 return CC0 | CC1;
1093 case GE:
1094 case GEU:
1095 return CC0 | CC2;
1096 default:
1097 gcc_unreachable ();
1098 }
1099 return -1;
1100 }
1101
1102 /* If INV is false, return assembler mnemonic string to implement
1103 a branch specified by CODE. If INV is true, return mnemonic
1104 for the corresponding inverted branch. */
1105
1106 static const char *
1107 s390_branch_condition_mnemonic (rtx code, int inv)
1108 {
1109 int mask;
1110
1111 static const char *const mnemonic[16] =
1112 {
1113 NULL, "o", "h", "nle",
1114 "l", "nhe", "lh", "ne",
1115 "e", "nlh", "he", "nl",
1116 "le", "nh", "no", NULL
1117 };
1118
1119 if (GET_CODE (XEXP (code, 0)) == REG
1120 && REGNO (XEXP (code, 0)) == CC_REGNUM
1121 && XEXP (code, 1) == const0_rtx)
1122 mask = s390_branch_condition_mask (code);
1123 else
1124 mask = s390_compare_and_branch_condition_mask (code);
1125
1126 gcc_assert (mask >= 0);
1127
1128 if (inv)
1129 mask ^= 15;
1130
1131 gcc_assert (mask >= 1 && mask <= 14);
1132
1133 return mnemonic[mask];
1134 }
1135
1136 /* Return the part of op which has a value different from def.
1137 The size of the part is determined by mode.
1138 Use this function only if you already know that op really
1139 contains such a part. */
1140
1141 unsigned HOST_WIDE_INT
1142 s390_extract_part (rtx op, enum machine_mode mode, int def)
1143 {
1144 unsigned HOST_WIDE_INT value = 0;
1145 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1146 int part_bits = GET_MODE_BITSIZE (mode);
1147 unsigned HOST_WIDE_INT part_mask
1148 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1149 int i;
1150
1151 for (i = 0; i < max_parts; i++)
1152 {
1153 if (i == 0)
1154 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1155 else
1156 value >>= part_bits;
1157
1158 if ((value & part_mask) != (def & part_mask))
1159 return value & part_mask;
1160 }
1161
1162 gcc_unreachable ();
1163 }
1164
1165 /* If OP is an integer constant of mode MODE with exactly one
1166 part of mode PART_MODE unequal to DEF, return the number of that
1167 part. Otherwise, return -1. */
1168
1169 int
1170 s390_single_part (rtx op,
1171 enum machine_mode mode,
1172 enum machine_mode part_mode,
1173 int def)
1174 {
1175 unsigned HOST_WIDE_INT value = 0;
1176 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1177 unsigned HOST_WIDE_INT part_mask
1178 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1179 int i, part = -1;
1180
1181 if (GET_CODE (op) != CONST_INT)
1182 return -1;
1183
1184 for (i = 0; i < n_parts; i++)
1185 {
1186 if (i == 0)
1187 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1188 else
1189 value >>= GET_MODE_BITSIZE (part_mode);
1190
1191 if ((value & part_mask) != (def & part_mask))
1192 {
1193 if (part != -1)
1194 return -1;
1195 else
1196 part = i;
1197 }
1198 }
1199 return part == -1 ? -1 : n_parts - 1 - part;
1200 }
1201
1202 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1203 bits and no other bits are set in IN. POS and LENGTH can be used
1204 to obtain the start position and the length of the bitfield.
1205
1206 POS gives the position of the first bit of the bitfield counting
1207 from the lowest order bit starting with zero. In order to use this
1208 value for S/390 instructions this has to be converted to "bits big
1209 endian" style. */
1210
1211 bool
1212 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1213 int *pos, int *length)
1214 {
1215 int tmp_pos = 0;
1216 int tmp_length = 0;
1217 int i;
1218 unsigned HOST_WIDE_INT mask = 1ULL;
1219 bool contiguous = false;
1220
1221 for (i = 0; i < size; mask <<= 1, i++)
1222 {
1223 if (contiguous)
1224 {
1225 if (mask & in)
1226 tmp_length++;
1227 else
1228 break;
1229 }
1230 else
1231 {
1232 if (mask & in)
1233 {
1234 contiguous = true;
1235 tmp_length++;
1236 }
1237 else
1238 tmp_pos++;
1239 }
1240 }
1241
1242 if (!tmp_length)
1243 return false;
1244
1245 /* Calculate a mask for all bits beyond the contiguous bits. */
1246 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1247
1248 if (mask & in)
1249 return false;
1250
1251 if (tmp_length + tmp_pos - 1 > size)
1252 return false;
1253
1254 if (length)
1255 *length = tmp_length;
1256
1257 if (pos)
1258 *pos = tmp_pos;
1259
1260 return true;
1261 }
1262
1263 /* Check whether we can (and want to) split a double-word
1264 move in mode MODE from SRC to DST into two single-word
1265 moves, moving the subword FIRST_SUBWORD first. */
1266
1267 bool
1268 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1269 {
1270 /* Floating point registers cannot be split. */
1271 if (FP_REG_P (src) || FP_REG_P (dst))
1272 return false;
1273
1274 /* We don't need to split if operands are directly accessible. */
1275 if (s_operand (src, mode) || s_operand (dst, mode))
1276 return false;
1277
1278 /* Non-offsettable memory references cannot be split. */
1279 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1280 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1281 return false;
1282
1283 /* Moving the first subword must not clobber a register
1284 needed to move the second subword. */
1285 if (register_operand (dst, mode))
1286 {
1287 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1288 if (reg_overlap_mentioned_p (subreg, src))
1289 return false;
1290 }
1291
1292 return true;
1293 }
1294
1295 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1296 and [MEM2, MEM2 + SIZE] do overlap and false
1297 otherwise. */
1298
1299 bool
1300 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1301 {
1302 rtx addr1, addr2, addr_delta;
1303 HOST_WIDE_INT delta;
1304
1305 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1306 return true;
1307
1308 if (size == 0)
1309 return false;
1310
1311 addr1 = XEXP (mem1, 0);
1312 addr2 = XEXP (mem2, 0);
1313
1314 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1315
1316 /* This overlapping check is used by peepholes merging memory block operations.
1317 Overlapping operations would otherwise be recognized by the S/390 hardware
1318 and would fall back to a slower implementation. Allowing overlapping
1319 operations would lead to slow code but not to wrong code. Therefore we are
1320 somewhat optimistic if we cannot prove that the memory blocks are
1321 overlapping.
1322 That's why we return false here although this may accept operations on
1323 overlapping memory areas. */
1324 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1325 return false;
1326
1327 delta = INTVAL (addr_delta);
1328
1329 if (delta == 0
1330 || (delta > 0 && delta < size)
1331 || (delta < 0 && -delta < size))
1332 return true;
1333
1334 return false;
1335 }
1336
1337 /* Check whether the address of memory reference MEM2 equals exactly
1338 the address of memory reference MEM1 plus DELTA. Return true if
1339 we can prove this to be the case, false otherwise. */
1340
1341 bool
1342 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1343 {
1344 rtx addr1, addr2, addr_delta;
1345
1346 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1347 return false;
1348
1349 addr1 = XEXP (mem1, 0);
1350 addr2 = XEXP (mem2, 0);
1351
1352 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1353 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1354 return false;
1355
1356 return true;
1357 }
1358
1359 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1360
1361 void
1362 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1363 rtx *operands)
1364 {
1365 enum machine_mode wmode = mode;
1366 rtx dst = operands[0];
1367 rtx src1 = operands[1];
1368 rtx src2 = operands[2];
1369 rtx op, clob, tem;
1370
1371 /* If we cannot handle the operation directly, use a temp register. */
1372 if (!s390_logical_operator_ok_p (operands))
1373 dst = gen_reg_rtx (mode);
1374
1375 /* QImode and HImode patterns make sense only if we have a destination
1376 in memory. Otherwise perform the operation in SImode. */
1377 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1378 wmode = SImode;
1379
1380 /* Widen operands if required. */
1381 if (mode != wmode)
1382 {
1383 if (GET_CODE (dst) == SUBREG
1384 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1385 dst = tem;
1386 else if (REG_P (dst))
1387 dst = gen_rtx_SUBREG (wmode, dst, 0);
1388 else
1389 dst = gen_reg_rtx (wmode);
1390
1391 if (GET_CODE (src1) == SUBREG
1392 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1393 src1 = tem;
1394 else if (GET_MODE (src1) != VOIDmode)
1395 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1396
1397 if (GET_CODE (src2) == SUBREG
1398 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1399 src2 = tem;
1400 else if (GET_MODE (src2) != VOIDmode)
1401 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1402 }
1403
1404 /* Emit the instruction. */
1405 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1406 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1407 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1408
1409 /* Fix up the destination if needed. */
1410 if (dst != operands[0])
1411 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1412 }
1413
1414 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1415
1416 bool
1417 s390_logical_operator_ok_p (rtx *operands)
1418 {
1419 /* If the destination operand is in memory, it needs to coincide
1420 with one of the source operands. After reload, it has to be
1421 the first source operand. */
1422 if (GET_CODE (operands[0]) == MEM)
1423 return rtx_equal_p (operands[0], operands[1])
1424 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1425
1426 return true;
1427 }
1428
1429 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1430 operand IMMOP to switch from SS to SI type instructions. */
1431
1432 void
1433 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1434 {
1435 int def = code == AND ? -1 : 0;
1436 HOST_WIDE_INT mask;
1437 int part;
1438
1439 gcc_assert (GET_CODE (*memop) == MEM);
1440 gcc_assert (!MEM_VOLATILE_P (*memop));
1441
1442 mask = s390_extract_part (*immop, QImode, def);
1443 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1444 gcc_assert (part >= 0);
1445
1446 *memop = adjust_address (*memop, QImode, part);
1447 *immop = gen_int_mode (mask, QImode);
1448 }
1449
1450
1451 /* How to allocate a 'struct machine_function'. */
1452
1453 static struct machine_function *
1454 s390_init_machine_status (void)
1455 {
1456 return GGC_CNEW (struct machine_function);
1457 }
1458
1459 /* Change optimizations to be performed, depending on the
1460 optimization level.
1461
1462 LEVEL is the optimization level specified; 2 if `-O2' is
1463 specified, 1 if `-O' is specified, and 0 if neither is specified.
1464
1465 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1466
1467 void
1468 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1469 {
1470 /* ??? There are apparently still problems with -fcaller-saves. */
1471 flag_caller_saves = 0;
1472
1473 /* By default, always emit DWARF-2 unwind info. This allows debugging
1474 without maintaining a stack frame back-chain. */
1475 flag_asynchronous_unwind_tables = 1;
1476
1477 /* Use MVCLE instructions to decrease code size if requested. */
1478 if (size != 0)
1479 target_flags |= MASK_MVCLE;
1480 }
1481
1482 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1483 to the associated processor_type and processor_flags if so. */
1484
1485 static bool
1486 s390_handle_arch_option (const char *arg,
1487 enum processor_type *type,
1488 int *flags)
1489 {
1490 static struct pta
1491 {
1492 const char *const name; /* processor name or nickname. */
1493 const enum processor_type processor;
1494 const int flags; /* From enum processor_flags. */
1495 }
1496 const processor_alias_table[] =
1497 {
1498 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1499 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1500 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1501 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1502 | PF_LONG_DISPLACEMENT},
1503 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1504 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1505 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1506 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1507 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1508 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1509 };
1510 size_t i;
1511
1512 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1513 if (strcmp (arg, processor_alias_table[i].name) == 0)
1514 {
1515 *type = processor_alias_table[i].processor;
1516 *flags = processor_alias_table[i].flags;
1517 return true;
1518 }
1519 return false;
1520 }
1521
1522 /* Implement TARGET_HANDLE_OPTION. */
1523
1524 static bool
1525 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1526 {
1527 switch (code)
1528 {
1529 case OPT_march_:
1530 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1531
1532 case OPT_mstack_guard_:
1533 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1534 return false;
1535 if (exact_log2 (s390_stack_guard) == -1)
1536 error ("stack guard value must be an exact power of 2");
1537 return true;
1538
1539 case OPT_mstack_size_:
1540 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1541 return false;
1542 if (exact_log2 (s390_stack_size) == -1)
1543 error ("stack size must be an exact power of 2");
1544 return true;
1545
1546 case OPT_mtune_:
1547 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1548
1549 case OPT_mwarn_framesize_:
1550 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1551
1552 default:
1553 return true;
1554 }
1555 }
1556
1557 void
1558 override_options (void)
1559 {
1560 /* Set up function hooks. */
1561 init_machine_status = s390_init_machine_status;
1562
1563 /* Architecture mode defaults according to ABI. */
1564 if (!(target_flags_explicit & MASK_ZARCH))
1565 {
1566 if (TARGET_64BIT)
1567 target_flags |= MASK_ZARCH;
1568 else
1569 target_flags &= ~MASK_ZARCH;
1570 }
1571
1572 /* Determine processor architectural level. */
1573 if (!s390_arch_string)
1574 {
1575 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1576 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1577 }
1578
1579 /* Determine processor to tune for. */
1580 if (s390_tune == PROCESSOR_max)
1581 {
1582 s390_tune = s390_arch;
1583 s390_tune_flags = s390_arch_flags;
1584 }
1585
1586 /* Sanity checks. */
1587 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1588 error ("z/Architecture mode not supported on %s", s390_arch_string);
1589 if (TARGET_64BIT && !TARGET_ZARCH)
1590 error ("64-bit ABI not supported in ESA/390 mode");
1591
1592 if (TARGET_HARD_DFP && !TARGET_DFP)
1593 {
1594 if (target_flags_explicit & MASK_HARD_DFP)
1595 {
1596 if (!TARGET_CPU_DFP)
1597 error ("Hardware decimal floating point instructions"
1598 " not available on %s", s390_arch_string);
1599 if (!TARGET_ZARCH)
1600 error ("Hardware decimal floating point instructions"
1601 " not available in ESA/390 mode");
1602 }
1603 else
1604 target_flags &= ~MASK_HARD_DFP;
1605 }
1606
1607 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1608 {
1609 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1610 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1611
1612 target_flags &= ~MASK_HARD_DFP;
1613 }
1614
1615 /* Set processor cost function. */
1616 switch (s390_tune)
1617 {
1618 case PROCESSOR_2084_Z990:
1619 s390_cost = &z990_cost;
1620 break;
1621 case PROCESSOR_2094_Z9_109:
1622 s390_cost = &z9_109_cost;
1623 break;
1624 case PROCESSOR_2097_Z10:
1625 s390_cost = &z10_cost;
1626 break;
1627 default:
1628 s390_cost = &z900_cost;
1629 }
1630
1631 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1632 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1633 "in combination");
1634
1635 if (s390_stack_size)
1636 {
1637 if (s390_stack_guard >= s390_stack_size)
1638 error ("stack size must be greater than the stack guard value");
1639 else if (s390_stack_size > 1 << 16)
1640 error ("stack size must not be greater than 64k");
1641 }
1642 else if (s390_stack_guard)
1643 error ("-mstack-guard implies use of -mstack-size");
1644
1645 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1646 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1647 target_flags |= MASK_LONG_DOUBLE_128;
1648 #endif
1649
1650 if (s390_tune == PROCESSOR_2097_Z10)
1651 {
1652 if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1653 set_param_value ("max-unrolled-insns", 100);
1654 if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES))
1655 set_param_value ("max-unroll-times", 32);
1656 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEELED_INSNS))
1657 set_param_value ("max-completely-peeled-insns", 2000);
1658 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEEL_TIMES))
1659 set_param_value ("max-completely-peel-times", 64);
1660 }
1661
1662 set_param_value ("max-pending-list-length", 256);
1663 /* values for loop prefetching */
1664 set_param_value ("l1-cache-line-size", 256);
1665 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1666 set_param_value ("l1-cache-size", 128);
1667 /* s390 has more than 2 levels and the size is much larger. Since
1668 we are always running virtualized assume that we only get a small
1669 part of the caches above l1. */
1670 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1671 set_param_value ("l2-cache-size", 1500);
1672 if (!PARAM_SET_P (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO))
1673 set_param_value ("prefetch-min-insn-to-mem-ratio", 2);
1674 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1675 set_param_value ("simultaneous-prefetches", 6);
1676
1677 /* This cannot reside in optimization_options since HAVE_prefetch
1678 requires the arch flags to be evaluated already. */
1679 if (HAVE_prefetch && optimize >= 3)
1680 flag_prefetch_loop_arrays = 1;
1681 }
1682
1683 /* Map for smallest class containing reg regno. */
1684
1685 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1686 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1687 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1688 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1689 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1690 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1691 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1692 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1693 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1694 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1695 ACCESS_REGS, ACCESS_REGS
1696 };
1697
1698 /* Return attribute type of insn. */
1699
1700 static enum attr_type
1701 s390_safe_attr_type (rtx insn)
1702 {
1703 if (recog_memoized (insn) >= 0)
1704 return get_attr_type (insn);
1705 else
1706 return TYPE_NONE;
1707 }
1708
1709 /* Return true if DISP is a valid short displacement. */
1710
1711 static bool
1712 s390_short_displacement (rtx disp)
1713 {
1714 /* No displacement is OK. */
1715 if (!disp)
1716 return true;
1717
1718 /* Without the long displacement facility we don't need to
1719 distingiush between long and short displacement. */
1720 if (!TARGET_LONG_DISPLACEMENT)
1721 return true;
1722
1723 /* Integer displacement in range. */
1724 if (GET_CODE (disp) == CONST_INT)
1725 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1726
1727 /* GOT offset is not OK, the GOT can be large. */
1728 if (GET_CODE (disp) == CONST
1729 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1730 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1731 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1732 return false;
1733
1734 /* All other symbolic constants are literal pool references,
1735 which are OK as the literal pool must be small. */
1736 if (GET_CODE (disp) == CONST)
1737 return true;
1738
1739 return false;
1740 }
1741
1742 /* Decompose a RTL expression ADDR for a memory address into
1743 its components, returned in OUT.
1744
1745 Returns false if ADDR is not a valid memory address, true
1746 otherwise. If OUT is NULL, don't return the components,
1747 but check for validity only.
1748
1749 Note: Only addresses in canonical form are recognized.
1750 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1751 canonical form so that they will be recognized. */
1752
1753 static int
1754 s390_decompose_address (rtx addr, struct s390_address *out)
1755 {
1756 HOST_WIDE_INT offset = 0;
1757 rtx base = NULL_RTX;
1758 rtx indx = NULL_RTX;
1759 rtx disp = NULL_RTX;
1760 rtx orig_disp;
1761 bool pointer = false;
1762 bool base_ptr = false;
1763 bool indx_ptr = false;
1764 bool literal_pool = false;
1765
1766 /* We may need to substitute the literal pool base register into the address
1767 below. However, at this point we do not know which register is going to
1768 be used as base, so we substitute the arg pointer register. This is going
1769 to be treated as holding a pointer below -- it shouldn't be used for any
1770 other purpose. */
1771 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1772
1773 /* Decompose address into base + index + displacement. */
1774
1775 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1776 base = addr;
1777
1778 else if (GET_CODE (addr) == PLUS)
1779 {
1780 rtx op0 = XEXP (addr, 0);
1781 rtx op1 = XEXP (addr, 1);
1782 enum rtx_code code0 = GET_CODE (op0);
1783 enum rtx_code code1 = GET_CODE (op1);
1784
1785 if (code0 == REG || code0 == UNSPEC)
1786 {
1787 if (code1 == REG || code1 == UNSPEC)
1788 {
1789 indx = op0; /* index + base */
1790 base = op1;
1791 }
1792
1793 else
1794 {
1795 base = op0; /* base + displacement */
1796 disp = op1;
1797 }
1798 }
1799
1800 else if (code0 == PLUS)
1801 {
1802 indx = XEXP (op0, 0); /* index + base + disp */
1803 base = XEXP (op0, 1);
1804 disp = op1;
1805 }
1806
1807 else
1808 {
1809 return false;
1810 }
1811 }
1812
1813 else
1814 disp = addr; /* displacement */
1815
1816 /* Extract integer part of displacement. */
1817 orig_disp = disp;
1818 if (disp)
1819 {
1820 if (GET_CODE (disp) == CONST_INT)
1821 {
1822 offset = INTVAL (disp);
1823 disp = NULL_RTX;
1824 }
1825 else if (GET_CODE (disp) == CONST
1826 && GET_CODE (XEXP (disp, 0)) == PLUS
1827 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1828 {
1829 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1830 disp = XEXP (XEXP (disp, 0), 0);
1831 }
1832 }
1833
1834 /* Strip off CONST here to avoid special case tests later. */
1835 if (disp && GET_CODE (disp) == CONST)
1836 disp = XEXP (disp, 0);
1837
1838 /* We can convert literal pool addresses to
1839 displacements by basing them off the base register. */
1840 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1841 {
1842 /* Either base or index must be free to hold the base register. */
1843 if (!base)
1844 base = fake_pool_base, literal_pool = true;
1845 else if (!indx)
1846 indx = fake_pool_base, literal_pool = true;
1847 else
1848 return false;
1849
1850 /* Mark up the displacement. */
1851 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1852 UNSPEC_LTREL_OFFSET);
1853 }
1854
1855 /* Validate base register. */
1856 if (base)
1857 {
1858 if (GET_CODE (base) == UNSPEC)
1859 switch (XINT (base, 1))
1860 {
1861 case UNSPEC_LTREF:
1862 if (!disp)
1863 disp = gen_rtx_UNSPEC (Pmode,
1864 gen_rtvec (1, XVECEXP (base, 0, 0)),
1865 UNSPEC_LTREL_OFFSET);
1866 else
1867 return false;
1868
1869 base = XVECEXP (base, 0, 1);
1870 break;
1871
1872 case UNSPEC_LTREL_BASE:
1873 if (XVECLEN (base, 0) == 1)
1874 base = fake_pool_base, literal_pool = true;
1875 else
1876 base = XVECEXP (base, 0, 1);
1877 break;
1878
1879 default:
1880 return false;
1881 }
1882
1883 if (!REG_P (base)
1884 || (GET_MODE (base) != SImode
1885 && GET_MODE (base) != Pmode))
1886 return false;
1887
1888 if (REGNO (base) == STACK_POINTER_REGNUM
1889 || REGNO (base) == FRAME_POINTER_REGNUM
1890 || ((reload_completed || reload_in_progress)
1891 && frame_pointer_needed
1892 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1893 || REGNO (base) == ARG_POINTER_REGNUM
1894 || (flag_pic
1895 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1896 pointer = base_ptr = true;
1897
1898 if ((reload_completed || reload_in_progress)
1899 && base == cfun->machine->base_reg)
1900 pointer = base_ptr = literal_pool = true;
1901 }
1902
1903 /* Validate index register. */
1904 if (indx)
1905 {
1906 if (GET_CODE (indx) == UNSPEC)
1907 switch (XINT (indx, 1))
1908 {
1909 case UNSPEC_LTREF:
1910 if (!disp)
1911 disp = gen_rtx_UNSPEC (Pmode,
1912 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1913 UNSPEC_LTREL_OFFSET);
1914 else
1915 return false;
1916
1917 indx = XVECEXP (indx, 0, 1);
1918 break;
1919
1920 case UNSPEC_LTREL_BASE:
1921 if (XVECLEN (indx, 0) == 1)
1922 indx = fake_pool_base, literal_pool = true;
1923 else
1924 indx = XVECEXP (indx, 0, 1);
1925 break;
1926
1927 default:
1928 return false;
1929 }
1930
1931 if (!REG_P (indx)
1932 || (GET_MODE (indx) != SImode
1933 && GET_MODE (indx) != Pmode))
1934 return false;
1935
1936 if (REGNO (indx) == STACK_POINTER_REGNUM
1937 || REGNO (indx) == FRAME_POINTER_REGNUM
1938 || ((reload_completed || reload_in_progress)
1939 && frame_pointer_needed
1940 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1941 || REGNO (indx) == ARG_POINTER_REGNUM
1942 || (flag_pic
1943 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1944 pointer = indx_ptr = true;
1945
1946 if ((reload_completed || reload_in_progress)
1947 && indx == cfun->machine->base_reg)
1948 pointer = indx_ptr = literal_pool = true;
1949 }
1950
1951 /* Prefer to use pointer as base, not index. */
1952 if (base && indx && !base_ptr
1953 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1954 {
1955 rtx tmp = base;
1956 base = indx;
1957 indx = tmp;
1958 }
1959
1960 /* Validate displacement. */
1961 if (!disp)
1962 {
1963 /* If virtual registers are involved, the displacement will change later
1964 anyway as the virtual registers get eliminated. This could make a
1965 valid displacement invalid, but it is more likely to make an invalid
1966 displacement valid, because we sometimes access the register save area
1967 via negative offsets to one of those registers.
1968 Thus we don't check the displacement for validity here. If after
1969 elimination the displacement turns out to be invalid after all,
1970 this is fixed up by reload in any case. */
1971 if (base != arg_pointer_rtx
1972 && indx != arg_pointer_rtx
1973 && base != return_address_pointer_rtx
1974 && indx != return_address_pointer_rtx
1975 && base != frame_pointer_rtx
1976 && indx != frame_pointer_rtx
1977 && base != virtual_stack_vars_rtx
1978 && indx != virtual_stack_vars_rtx)
1979 if (!DISP_IN_RANGE (offset))
1980 return false;
1981 }
1982 else
1983 {
1984 /* All the special cases are pointers. */
1985 pointer = true;
1986
1987 /* In the small-PIC case, the linker converts @GOT
1988 and @GOTNTPOFF offsets to possible displacements. */
1989 if (GET_CODE (disp) == UNSPEC
1990 && (XINT (disp, 1) == UNSPEC_GOT
1991 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1992 && flag_pic == 1)
1993 {
1994 ;
1995 }
1996
1997 /* Accept pool label offsets. */
1998 else if (GET_CODE (disp) == UNSPEC
1999 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2000 ;
2001
2002 /* Accept literal pool references. */
2003 else if (GET_CODE (disp) == UNSPEC
2004 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2005 {
2006 orig_disp = gen_rtx_CONST (Pmode, disp);
2007 if (offset)
2008 {
2009 /* If we have an offset, make sure it does not
2010 exceed the size of the constant pool entry. */
2011 rtx sym = XVECEXP (disp, 0, 0);
2012 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2013 return false;
2014
2015 orig_disp = plus_constant (orig_disp, offset);
2016 }
2017 }
2018
2019 else
2020 return false;
2021 }
2022
2023 if (!base && !indx)
2024 pointer = true;
2025
2026 if (out)
2027 {
2028 out->base = base;
2029 out->indx = indx;
2030 out->disp = orig_disp;
2031 out->pointer = pointer;
2032 out->literal_pool = literal_pool;
2033 }
2034
2035 return true;
2036 }
2037
2038 /* Decompose a RTL expression OP for a shift count into its components,
2039 and return the base register in BASE and the offset in OFFSET.
2040
2041 Return true if OP is a valid shift count, false if not. */
2042
2043 bool
2044 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2045 {
2046 HOST_WIDE_INT off = 0;
2047
2048 /* We can have an integer constant, an address register,
2049 or a sum of the two. */
2050 if (GET_CODE (op) == CONST_INT)
2051 {
2052 off = INTVAL (op);
2053 op = NULL_RTX;
2054 }
2055 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2056 {
2057 off = INTVAL (XEXP (op, 1));
2058 op = XEXP (op, 0);
2059 }
2060 while (op && GET_CODE (op) == SUBREG)
2061 op = SUBREG_REG (op);
2062
2063 if (op && GET_CODE (op) != REG)
2064 return false;
2065
2066 if (offset)
2067 *offset = off;
2068 if (base)
2069 *base = op;
2070
2071 return true;
2072 }
2073
2074
2075 /* Return true if CODE is a valid address without index. */
2076
2077 bool
2078 s390_legitimate_address_without_index_p (rtx op)
2079 {
2080 struct s390_address addr;
2081
2082 if (!s390_decompose_address (XEXP (op, 0), &addr))
2083 return false;
2084 if (addr.indx)
2085 return false;
2086
2087 return true;
2088 }
2089
2090
2091 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2092 and return these parts in SYMREF and ADDEND. You can pass NULL in
2093 SYMREF and/or ADDEND if you are not interested in these values. */
2094
2095 static bool
2096 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2097 {
2098 HOST_WIDE_INT tmpaddend = 0;
2099
2100 if (GET_CODE (addr) == CONST)
2101 addr = XEXP (addr, 0);
2102
2103 if (GET_CODE (addr) == PLUS)
2104 {
2105 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2106 && CONST_INT_P (XEXP (addr, 1)))
2107 {
2108 tmpaddend = INTVAL (XEXP (addr, 1));
2109 addr = XEXP (addr, 0);
2110 }
2111 else
2112 return false;
2113 }
2114 else
2115 if (GET_CODE (addr) != SYMBOL_REF)
2116 return false;
2117
2118 if (symref)
2119 *symref = addr;
2120 if (addend)
2121 *addend = tmpaddend;
2122
2123 return true;
2124 }
2125
2126
2127 /* Return true if the address in OP is valid for constraint letter C
2128 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2129 pool MEMs should be accepted. Only the Q, R, S, T constraint
2130 letters are allowed for C. */
2131
2132 static int
2133 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2134 {
2135 struct s390_address addr;
2136 bool decomposed = false;
2137
2138 /* This check makes sure that no symbolic address (except literal
2139 pool references) are accepted by the R or T constraints. */
2140 if (s390_symref_operand_p (op, NULL, NULL))
2141 {
2142 if (!lit_pool_ok)
2143 return 0;
2144 if (!s390_decompose_address (op, &addr))
2145 return 0;
2146 if (!addr.literal_pool)
2147 return 0;
2148 decomposed = true;
2149 }
2150
2151 switch (c)
2152 {
2153 case 'Q': /* no index short displacement */
2154 if (!decomposed && !s390_decompose_address (op, &addr))
2155 return 0;
2156 if (addr.indx)
2157 return 0;
2158 if (!s390_short_displacement (addr.disp))
2159 return 0;
2160 break;
2161
2162 case 'R': /* with index short displacement */
2163 if (TARGET_LONG_DISPLACEMENT)
2164 {
2165 if (!decomposed && !s390_decompose_address (op, &addr))
2166 return 0;
2167 if (!s390_short_displacement (addr.disp))
2168 return 0;
2169 }
2170 /* Any invalid address here will be fixed up by reload,
2171 so accept it for the most generic constraint. */
2172 break;
2173
2174 case 'S': /* no index long displacement */
2175 if (!TARGET_LONG_DISPLACEMENT)
2176 return 0;
2177 if (!decomposed && !s390_decompose_address (op, &addr))
2178 return 0;
2179 if (addr.indx)
2180 return 0;
2181 if (s390_short_displacement (addr.disp))
2182 return 0;
2183 break;
2184
2185 case 'T': /* with index long displacement */
2186 if (!TARGET_LONG_DISPLACEMENT)
2187 return 0;
2188 /* Any invalid address here will be fixed up by reload,
2189 so accept it for the most generic constraint. */
2190 if ((decomposed || s390_decompose_address (op, &addr))
2191 && s390_short_displacement (addr.disp))
2192 return 0;
2193 break;
2194 default:
2195 return 0;
2196 }
2197 return 1;
2198 }
2199
2200
2201 /* Evaluates constraint strings described by the regular expression
2202 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2203 the constraint given in STR, or 0 else. */
2204
2205 int
2206 s390_mem_constraint (const char *str, rtx op)
2207 {
2208 char c = str[0];
2209
2210 switch (c)
2211 {
2212 case 'A':
2213 /* Check for offsettable variants of memory constraints. */
2214 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2215 return 0;
2216 if ((reload_completed || reload_in_progress)
2217 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2218 return 0;
2219 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2220 case 'B':
2221 /* Check for non-literal-pool variants of memory constraints. */
2222 if (!MEM_P (op))
2223 return 0;
2224 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2225 case 'Q':
2226 case 'R':
2227 case 'S':
2228 case 'T':
2229 if (GET_CODE (op) != MEM)
2230 return 0;
2231 return s390_check_qrst_address (c, XEXP (op, 0), true);
2232 case 'U':
2233 return (s390_check_qrst_address ('Q', op, true)
2234 || s390_check_qrst_address ('R', op, true));
2235 case 'W':
2236 return (s390_check_qrst_address ('S', op, true)
2237 || s390_check_qrst_address ('T', op, true));
2238 case 'Y':
2239 /* Simply check for the basic form of a shift count. Reload will
2240 take care of making sure we have a proper base register. */
2241 if (!s390_decompose_shift_count (op, NULL, NULL))
2242 return 0;
2243 break;
2244 case 'Z':
2245 return s390_check_qrst_address (str[1], op, true);
2246 default:
2247 return 0;
2248 }
2249 return 1;
2250 }
2251
2252
2253 /* Evaluates constraint strings starting with letter O. Input
2254 parameter C is the second letter following the "O" in the constraint
2255 string. Returns 1 if VALUE meets the respective constraint and 0
2256 otherwise. */
2257
2258 int
2259 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2260 {
2261 if (!TARGET_EXTIMM)
2262 return 0;
2263
2264 switch (c)
2265 {
2266 case 's':
2267 return trunc_int_for_mode (value, SImode) == value;
2268
2269 case 'p':
2270 return value == 0
2271 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2272
2273 case 'n':
2274 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2275
2276 default:
2277 gcc_unreachable ();
2278 }
2279 }
2280
2281
2282 /* Evaluates constraint strings starting with letter N. Parameter STR
2283 contains the letters following letter "N" in the constraint string.
2284 Returns true if VALUE matches the constraint. */
2285
2286 int
2287 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2288 {
2289 enum machine_mode mode, part_mode;
2290 int def;
2291 int part, part_goal;
2292
2293
2294 if (str[0] == 'x')
2295 part_goal = -1;
2296 else
2297 part_goal = str[0] - '0';
2298
2299 switch (str[1])
2300 {
2301 case 'Q':
2302 part_mode = QImode;
2303 break;
2304 case 'H':
2305 part_mode = HImode;
2306 break;
2307 case 'S':
2308 part_mode = SImode;
2309 break;
2310 default:
2311 return 0;
2312 }
2313
2314 switch (str[2])
2315 {
2316 case 'H':
2317 mode = HImode;
2318 break;
2319 case 'S':
2320 mode = SImode;
2321 break;
2322 case 'D':
2323 mode = DImode;
2324 break;
2325 default:
2326 return 0;
2327 }
2328
2329 switch (str[3])
2330 {
2331 case '0':
2332 def = 0;
2333 break;
2334 case 'F':
2335 def = -1;
2336 break;
2337 default:
2338 return 0;
2339 }
2340
2341 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2342 return 0;
2343
2344 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2345 if (part < 0)
2346 return 0;
2347 if (part_goal != -1 && part_goal != part)
2348 return 0;
2349
2350 return 1;
2351 }
2352
2353
2354 /* Returns true if the input parameter VALUE is a float zero. */
2355
2356 int
2357 s390_float_const_zero_p (rtx value)
2358 {
2359 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2360 && value == CONST0_RTX (GET_MODE (value)));
2361 }
2362
2363
2364 /* Compute a (partial) cost for rtx X. Return true if the complete
2365 cost has been computed, and false if subexpressions should be
2366 scanned. In either case, *TOTAL contains the cost result.
2367 CODE contains GET_CODE (x), OUTER_CODE contains the code
2368 of the superexpression of x. */
2369
2370 static bool
2371 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2372 bool speed ATTRIBUTE_UNUSED)
2373 {
2374 switch (code)
2375 {
2376 case CONST:
2377 case CONST_INT:
2378 case LABEL_REF:
2379 case SYMBOL_REF:
2380 case CONST_DOUBLE:
2381 case MEM:
2382 *total = 0;
2383 return true;
2384
2385 case ASHIFT:
2386 case ASHIFTRT:
2387 case LSHIFTRT:
2388 case ROTATE:
2389 case ROTATERT:
2390 case AND:
2391 case IOR:
2392 case XOR:
2393 case NEG:
2394 case NOT:
2395 *total = COSTS_N_INSNS (1);
2396 return false;
2397
2398 case PLUS:
2399 case MINUS:
2400 /* Check for multiply and add. */
2401 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2402 && GET_CODE (XEXP (x, 0)) == MULT
2403 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2404 {
2405 /* This is the multiply and add case. */
2406 if (GET_MODE (x) == DFmode)
2407 *total = s390_cost->madbr;
2408 else
2409 *total = s390_cost->maebr;
2410 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2411 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2412 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2413 return true; /* Do not do an additional recursive descent. */
2414 }
2415 *total = COSTS_N_INSNS (1);
2416 return false;
2417
2418 case MULT:
2419 switch (GET_MODE (x))
2420 {
2421 case SImode:
2422 {
2423 rtx left = XEXP (x, 0);
2424 rtx right = XEXP (x, 1);
2425 if (GET_CODE (right) == CONST_INT
2426 && CONST_OK_FOR_K (INTVAL (right)))
2427 *total = s390_cost->mhi;
2428 else if (GET_CODE (left) == SIGN_EXTEND)
2429 *total = s390_cost->mh;
2430 else
2431 *total = s390_cost->ms; /* msr, ms, msy */
2432 break;
2433 }
2434 case DImode:
2435 {
2436 rtx left = XEXP (x, 0);
2437 rtx right = XEXP (x, 1);
2438 if (TARGET_ZARCH)
2439 {
2440 if (GET_CODE (right) == CONST_INT
2441 && CONST_OK_FOR_K (INTVAL (right)))
2442 *total = s390_cost->mghi;
2443 else if (GET_CODE (left) == SIGN_EXTEND)
2444 *total = s390_cost->msgf;
2445 else
2446 *total = s390_cost->msg; /* msgr, msg */
2447 }
2448 else /* TARGET_31BIT */
2449 {
2450 if (GET_CODE (left) == SIGN_EXTEND
2451 && GET_CODE (right) == SIGN_EXTEND)
2452 /* mulsidi case: mr, m */
2453 *total = s390_cost->m;
2454 else if (GET_CODE (left) == ZERO_EXTEND
2455 && GET_CODE (right) == ZERO_EXTEND
2456 && TARGET_CPU_ZARCH)
2457 /* umulsidi case: ml, mlr */
2458 *total = s390_cost->ml;
2459 else
2460 /* Complex calculation is required. */
2461 *total = COSTS_N_INSNS (40);
2462 }
2463 break;
2464 }
2465 case SFmode:
2466 case DFmode:
2467 *total = s390_cost->mult_df;
2468 break;
2469 case TFmode:
2470 *total = s390_cost->mxbr;
2471 break;
2472 default:
2473 return false;
2474 }
2475 return false;
2476
2477 case UDIV:
2478 case UMOD:
2479 if (GET_MODE (x) == TImode) /* 128 bit division */
2480 *total = s390_cost->dlgr;
2481 else if (GET_MODE (x) == DImode)
2482 {
2483 rtx right = XEXP (x, 1);
2484 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2485 *total = s390_cost->dlr;
2486 else /* 64 by 64 bit division */
2487 *total = s390_cost->dlgr;
2488 }
2489 else if (GET_MODE (x) == SImode) /* 32 bit division */
2490 *total = s390_cost->dlr;
2491 return false;
2492
2493 case DIV:
2494 case MOD:
2495 if (GET_MODE (x) == DImode)
2496 {
2497 rtx right = XEXP (x, 1);
2498 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2499 if (TARGET_ZARCH)
2500 *total = s390_cost->dsgfr;
2501 else
2502 *total = s390_cost->dr;
2503 else /* 64 by 64 bit division */
2504 *total = s390_cost->dsgr;
2505 }
2506 else if (GET_MODE (x) == SImode) /* 32 bit division */
2507 *total = s390_cost->dlr;
2508 else if (GET_MODE (x) == SFmode)
2509 {
2510 *total = s390_cost->debr;
2511 }
2512 else if (GET_MODE (x) == DFmode)
2513 {
2514 *total = s390_cost->ddbr;
2515 }
2516 else if (GET_MODE (x) == TFmode)
2517 {
2518 *total = s390_cost->dxbr;
2519 }
2520 return false;
2521
2522 case SQRT:
2523 if (GET_MODE (x) == SFmode)
2524 *total = s390_cost->sqebr;
2525 else if (GET_MODE (x) == DFmode)
2526 *total = s390_cost->sqdbr;
2527 else /* TFmode */
2528 *total = s390_cost->sqxbr;
2529 return false;
2530
2531 case SIGN_EXTEND:
2532 case ZERO_EXTEND:
2533 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2534 || outer_code == PLUS || outer_code == MINUS
2535 || outer_code == COMPARE)
2536 *total = 0;
2537 return false;
2538
2539 case COMPARE:
2540 *total = COSTS_N_INSNS (1);
2541 if (GET_CODE (XEXP (x, 0)) == AND
2542 && GET_CODE (XEXP (x, 1)) == CONST_INT
2543 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2544 {
2545 rtx op0 = XEXP (XEXP (x, 0), 0);
2546 rtx op1 = XEXP (XEXP (x, 0), 1);
2547 rtx op2 = XEXP (x, 1);
2548
2549 if (memory_operand (op0, GET_MODE (op0))
2550 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2551 return true;
2552 if (register_operand (op0, GET_MODE (op0))
2553 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2554 return true;
2555 }
2556 return false;
2557
2558 default:
2559 return false;
2560 }
2561 }
2562
2563 /* Return the cost of an address rtx ADDR. */
2564
2565 static int
2566 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2567 {
2568 struct s390_address ad;
2569 if (!s390_decompose_address (addr, &ad))
2570 return 1000;
2571
2572 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2573 }
2574
2575 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2576 otherwise return 0. */
2577
2578 int
2579 tls_symbolic_operand (rtx op)
2580 {
2581 if (GET_CODE (op) != SYMBOL_REF)
2582 return 0;
2583 return SYMBOL_REF_TLS_MODEL (op);
2584 }
2585 \f
2586 /* Split DImode access register reference REG (on 64-bit) into its constituent
2587 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2588 gen_highpart cannot be used as they assume all registers are word-sized,
2589 while our access registers have only half that size. */
2590
2591 void
2592 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2593 {
2594 gcc_assert (TARGET_64BIT);
2595 gcc_assert (ACCESS_REG_P (reg));
2596 gcc_assert (GET_MODE (reg) == DImode);
2597 gcc_assert (!(REGNO (reg) & 1));
2598
2599 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2600 *hi = gen_rtx_REG (SImode, REGNO (reg));
2601 }
2602
2603 /* Return true if OP contains a symbol reference */
2604
2605 bool
2606 symbolic_reference_mentioned_p (rtx op)
2607 {
2608 const char *fmt;
2609 int i;
2610
2611 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2612 return 1;
2613
2614 fmt = GET_RTX_FORMAT (GET_CODE (op));
2615 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2616 {
2617 if (fmt[i] == 'E')
2618 {
2619 int j;
2620
2621 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2622 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2623 return 1;
2624 }
2625
2626 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2627 return 1;
2628 }
2629
2630 return 0;
2631 }
2632
2633 /* Return true if OP contains a reference to a thread-local symbol. */
2634
2635 bool
2636 tls_symbolic_reference_mentioned_p (rtx op)
2637 {
2638 const char *fmt;
2639 int i;
2640
2641 if (GET_CODE (op) == SYMBOL_REF)
2642 return tls_symbolic_operand (op);
2643
2644 fmt = GET_RTX_FORMAT (GET_CODE (op));
2645 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2646 {
2647 if (fmt[i] == 'E')
2648 {
2649 int j;
2650
2651 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2652 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2653 return true;
2654 }
2655
2656 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2657 return true;
2658 }
2659
2660 return false;
2661 }
2662
2663
2664 /* Return true if OP is a legitimate general operand when
2665 generating PIC code. It is given that flag_pic is on
2666 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2667
2668 int
2669 legitimate_pic_operand_p (rtx op)
2670 {
2671 /* Accept all non-symbolic constants. */
2672 if (!SYMBOLIC_CONST (op))
2673 return 1;
2674
2675 /* Reject everything else; must be handled
2676 via emit_symbolic_move. */
2677 return 0;
2678 }
2679
2680 /* Returns true if the constant value OP is a legitimate general operand.
2681 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2682
2683 int
2684 legitimate_constant_p (rtx op)
2685 {
2686 /* Accept all non-symbolic constants. */
2687 if (!SYMBOLIC_CONST (op))
2688 return 1;
2689
2690 /* Accept immediate LARL operands. */
2691 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2692 return 1;
2693
2694 /* Thread-local symbols are never legal constants. This is
2695 so that emit_call knows that computing such addresses
2696 might require a function call. */
2697 if (TLS_SYMBOLIC_CONST (op))
2698 return 0;
2699
2700 /* In the PIC case, symbolic constants must *not* be
2701 forced into the literal pool. We accept them here,
2702 so that they will be handled by emit_symbolic_move. */
2703 if (flag_pic)
2704 return 1;
2705
2706 /* All remaining non-PIC symbolic constants are
2707 forced into the literal pool. */
2708 return 0;
2709 }
2710
2711 /* Determine if it's legal to put X into the constant pool. This
2712 is not possible if X contains the address of a symbol that is
2713 not constant (TLS) or not known at final link time (PIC). */
2714
2715 static bool
2716 s390_cannot_force_const_mem (rtx x)
2717 {
2718 switch (GET_CODE (x))
2719 {
2720 case CONST_INT:
2721 case CONST_DOUBLE:
2722 /* Accept all non-symbolic constants. */
2723 return false;
2724
2725 case LABEL_REF:
2726 /* Labels are OK iff we are non-PIC. */
2727 return flag_pic != 0;
2728
2729 case SYMBOL_REF:
2730 /* 'Naked' TLS symbol references are never OK,
2731 non-TLS symbols are OK iff we are non-PIC. */
2732 if (tls_symbolic_operand (x))
2733 return true;
2734 else
2735 return flag_pic != 0;
2736
2737 case CONST:
2738 return s390_cannot_force_const_mem (XEXP (x, 0));
2739 case PLUS:
2740 case MINUS:
2741 return s390_cannot_force_const_mem (XEXP (x, 0))
2742 || s390_cannot_force_const_mem (XEXP (x, 1));
2743
2744 case UNSPEC:
2745 switch (XINT (x, 1))
2746 {
2747 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2748 case UNSPEC_LTREL_OFFSET:
2749 case UNSPEC_GOT:
2750 case UNSPEC_GOTOFF:
2751 case UNSPEC_PLTOFF:
2752 case UNSPEC_TLSGD:
2753 case UNSPEC_TLSLDM:
2754 case UNSPEC_NTPOFF:
2755 case UNSPEC_DTPOFF:
2756 case UNSPEC_GOTNTPOFF:
2757 case UNSPEC_INDNTPOFF:
2758 return false;
2759
2760 /* If the literal pool shares the code section, be put
2761 execute template placeholders into the pool as well. */
2762 case UNSPEC_INSN:
2763 return TARGET_CPU_ZARCH;
2764
2765 default:
2766 return true;
2767 }
2768 break;
2769
2770 default:
2771 gcc_unreachable ();
2772 }
2773 }
2774
2775 /* Returns true if the constant value OP is a legitimate general
2776 operand during and after reload. The difference to
2777 legitimate_constant_p is that this function will not accept
2778 a constant that would need to be forced to the literal pool
2779 before it can be used as operand. */
2780
2781 bool
2782 legitimate_reload_constant_p (rtx op)
2783 {
2784 /* Accept la(y) operands. */
2785 if (GET_CODE (op) == CONST_INT
2786 && DISP_IN_RANGE (INTVAL (op)))
2787 return true;
2788
2789 /* Accept l(g)hi/l(g)fi operands. */
2790 if (GET_CODE (op) == CONST_INT
2791 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2792 return true;
2793
2794 /* Accept lliXX operands. */
2795 if (TARGET_ZARCH
2796 && GET_CODE (op) == CONST_INT
2797 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2798 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2799 return true;
2800
2801 if (TARGET_EXTIMM
2802 && GET_CODE (op) == CONST_INT
2803 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2804 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2805 return true;
2806
2807 /* Accept larl operands. */
2808 if (TARGET_CPU_ZARCH
2809 && larl_operand (op, VOIDmode))
2810 return true;
2811
2812 /* Accept lzXX operands. */
2813 if (GET_CODE (op) == CONST_DOUBLE
2814 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2815 return true;
2816
2817 /* Accept double-word operands that can be split. */
2818 if (GET_CODE (op) == CONST_INT
2819 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2820 {
2821 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2822 rtx hi = operand_subword (op, 0, 0, dword_mode);
2823 rtx lo = operand_subword (op, 1, 0, dword_mode);
2824 return legitimate_reload_constant_p (hi)
2825 && legitimate_reload_constant_p (lo);
2826 }
2827
2828 /* Everything else cannot be handled without reload. */
2829 return false;
2830 }
2831
2832 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2833 return the class of reg to actually use. */
2834
2835 enum reg_class
2836 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2837 {
2838 switch (GET_CODE (op))
2839 {
2840 /* Constants we cannot reload must be forced into the
2841 literal pool. */
2842
2843 case CONST_DOUBLE:
2844 case CONST_INT:
2845 if (legitimate_reload_constant_p (op))
2846 return rclass;
2847 else
2848 return NO_REGS;
2849
2850 /* If a symbolic constant or a PLUS is reloaded,
2851 it is most likely being used as an address, so
2852 prefer ADDR_REGS. If 'class' is not a superset
2853 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2854 case PLUS:
2855 case LABEL_REF:
2856 case SYMBOL_REF:
2857 case CONST:
2858 if (reg_class_subset_p (ADDR_REGS, rclass))
2859 return ADDR_REGS;
2860 else
2861 return NO_REGS;
2862
2863 default:
2864 break;
2865 }
2866
2867 return rclass;
2868 }
2869
2870 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2871 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2872 aligned. */
2873
2874 bool
2875 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2876 {
2877 HOST_WIDE_INT addend;
2878 rtx symref;
2879
2880 if (!s390_symref_operand_p (addr, &symref, &addend))
2881 return false;
2882
2883 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2884 && !(addend & (alignment - 1)));
2885 }
2886
2887 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2888 operand SCRATCH is used to reload the even part of the address and
2889 adding one. */
2890
2891 void
2892 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2893 {
2894 HOST_WIDE_INT addend;
2895 rtx symref;
2896
2897 if (!s390_symref_operand_p (addr, &symref, &addend))
2898 gcc_unreachable ();
2899
2900 if (!(addend & 1))
2901 /* Easy case. The addend is even so larl will do fine. */
2902 emit_move_insn (reg, addr);
2903 else
2904 {
2905 /* We can leave the scratch register untouched if the target
2906 register is a valid base register. */
2907 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2908 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2909 scratch = reg;
2910
2911 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2912 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2913
2914 if (addend != 1)
2915 emit_move_insn (scratch,
2916 gen_rtx_CONST (Pmode,
2917 gen_rtx_PLUS (Pmode, symref,
2918 GEN_INT (addend - 1))));
2919 else
2920 emit_move_insn (scratch, symref);
2921
2922 /* Increment the address using la in order to avoid clobbering cc. */
2923 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2924 }
2925 }
2926
2927 /* Generate what is necessary to move between REG and MEM using
2928 SCRATCH. The direction is given by TOMEM. */
2929
2930 void
2931 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2932 {
2933 /* Reload might have pulled a constant out of the literal pool.
2934 Force it back in. */
2935 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2936 || GET_CODE (mem) == CONST)
2937 mem = force_const_mem (GET_MODE (reg), mem);
2938
2939 gcc_assert (MEM_P (mem));
2940
2941 /* For a load from memory we can leave the scratch register
2942 untouched if the target register is a valid base register. */
2943 if (!tomem
2944 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2945 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2946 && GET_MODE (reg) == GET_MODE (scratch))
2947 scratch = reg;
2948
2949 /* Load address into scratch register. Since we can't have a
2950 secondary reload for a secondary reload we have to cover the case
2951 where larl would need a secondary reload here as well. */
2952 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2953
2954 /* Now we can use a standard load/store to do the move. */
2955 if (tomem)
2956 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2957 else
2958 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2959 }
2960
2961 /* Inform reload about cases where moving X with a mode MODE to a register in
2962 RCLASS requires an extra scratch or immediate register. Return the class
2963 needed for the immediate register. */
2964
2965 static enum reg_class
2966 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2967 enum machine_mode mode, secondary_reload_info *sri)
2968 {
2969 /* Intermediate register needed. */
2970 if (reg_classes_intersect_p (CC_REGS, rclass))
2971 return GENERAL_REGS;
2972
2973 if (TARGET_Z10)
2974 {
2975 /* On z10 several optimizer steps may generate larl operands with
2976 an odd addend. */
2977 if (in_p
2978 && s390_symref_operand_p (x, NULL, NULL)
2979 && mode == Pmode
2980 && !s390_check_symref_alignment (x, 2))
2981 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2982 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2983
2984 /* On z10 we need a scratch register when moving QI, TI or floating
2985 point mode values from or to a memory location with a SYMBOL_REF
2986 or if the symref addend of a SI or DI move is not aligned to the
2987 width of the access. */
2988 if (MEM_P (x)
2989 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2990 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2991 || (!TARGET_ZARCH && mode == DImode)
2992 || ((mode == HImode || mode == SImode || mode == DImode)
2993 && (!s390_check_symref_alignment (XEXP (x, 0),
2994 GET_MODE_SIZE (mode))))))
2995 {
2996 #define __SECONDARY_RELOAD_CASE(M,m) \
2997 case M##mode: \
2998 if (TARGET_64BIT) \
2999 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3000 CODE_FOR_reload##m##di_tomem_z10; \
3001 else \
3002 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3003 CODE_FOR_reload##m##si_tomem_z10; \
3004 break;
3005
3006 switch (GET_MODE (x))
3007 {
3008 __SECONDARY_RELOAD_CASE (QI, qi);
3009 __SECONDARY_RELOAD_CASE (HI, hi);
3010 __SECONDARY_RELOAD_CASE (SI, si);
3011 __SECONDARY_RELOAD_CASE (DI, di);
3012 __SECONDARY_RELOAD_CASE (TI, ti);
3013 __SECONDARY_RELOAD_CASE (SF, sf);
3014 __SECONDARY_RELOAD_CASE (DF, df);
3015 __SECONDARY_RELOAD_CASE (TF, tf);
3016 __SECONDARY_RELOAD_CASE (SD, sd);
3017 __SECONDARY_RELOAD_CASE (DD, dd);
3018 __SECONDARY_RELOAD_CASE (TD, td);
3019
3020 default:
3021 gcc_unreachable ();
3022 }
3023 #undef __SECONDARY_RELOAD_CASE
3024 }
3025 }
3026
3027 /* We need a scratch register when loading a PLUS expression which
3028 is not a legitimate operand of the LOAD ADDRESS instruction. */
3029 if (in_p && s390_plus_operand (x, mode))
3030 sri->icode = (TARGET_64BIT ?
3031 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3032
3033 /* Performing a multiword move from or to memory we have to make sure the
3034 second chunk in memory is addressable without causing a displacement
3035 overflow. If that would be the case we calculate the address in
3036 a scratch register. */
3037 if (MEM_P (x)
3038 && GET_CODE (XEXP (x, 0)) == PLUS
3039 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3040 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3041 + GET_MODE_SIZE (mode) - 1))
3042 {
3043 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3044 in a s_operand address since we may fallback to lm/stm. So we only
3045 have to care about overflows in the b+i+d case. */
3046 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3047 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3048 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3049 /* For FP_REGS no lm/stm is available so this check is triggered
3050 for displacement overflows in b+i+d and b+d like addresses. */
3051 || (reg_classes_intersect_p (FP_REGS, rclass)
3052 && s390_class_max_nregs (FP_REGS, mode) > 1))
3053 {
3054 if (in_p)
3055 sri->icode = (TARGET_64BIT ?
3056 CODE_FOR_reloaddi_nonoffmem_in :
3057 CODE_FOR_reloadsi_nonoffmem_in);
3058 else
3059 sri->icode = (TARGET_64BIT ?
3060 CODE_FOR_reloaddi_nonoffmem_out :
3061 CODE_FOR_reloadsi_nonoffmem_out);
3062 }
3063 }
3064
3065 /* A scratch address register is needed when a symbolic constant is
3066 copied to r0 compiling with -fPIC. In other cases the target
3067 register might be used as temporary (see legitimize_pic_address). */
3068 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3069 sri->icode = (TARGET_64BIT ?
3070 CODE_FOR_reloaddi_PIC_addr :
3071 CODE_FOR_reloadsi_PIC_addr);
3072
3073 /* Either scratch or no register needed. */
3074 return NO_REGS;
3075 }
3076
3077 /* Generate code to load SRC, which is PLUS that is not a
3078 legitimate operand for the LA instruction, into TARGET.
3079 SCRATCH may be used as scratch register. */
3080
3081 void
3082 s390_expand_plus_operand (rtx target, rtx src,
3083 rtx scratch)
3084 {
3085 rtx sum1, sum2;
3086 struct s390_address ad;
3087
3088 /* src must be a PLUS; get its two operands. */
3089 gcc_assert (GET_CODE (src) == PLUS);
3090 gcc_assert (GET_MODE (src) == Pmode);
3091
3092 /* Check if any of the two operands is already scheduled
3093 for replacement by reload. This can happen e.g. when
3094 float registers occur in an address. */
3095 sum1 = find_replacement (&XEXP (src, 0));
3096 sum2 = find_replacement (&XEXP (src, 1));
3097 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3098
3099 /* If the address is already strictly valid, there's nothing to do. */
3100 if (!s390_decompose_address (src, &ad)
3101 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3102 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3103 {
3104 /* Otherwise, one of the operands cannot be an address register;
3105 we reload its value into the scratch register. */
3106 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3107 {
3108 emit_move_insn (scratch, sum1);
3109 sum1 = scratch;
3110 }
3111 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3112 {
3113 emit_move_insn (scratch, sum2);
3114 sum2 = scratch;
3115 }
3116
3117 /* According to the way these invalid addresses are generated
3118 in reload.c, it should never happen (at least on s390) that
3119 *neither* of the PLUS components, after find_replacements
3120 was applied, is an address register. */
3121 if (sum1 == scratch && sum2 == scratch)
3122 {
3123 debug_rtx (src);
3124 gcc_unreachable ();
3125 }
3126
3127 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3128 }
3129
3130 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3131 is only ever performed on addresses, so we can mark the
3132 sum as legitimate for LA in any case. */
3133 s390_load_address (target, src);
3134 }
3135
3136
3137 /* Return true if ADDR is a valid memory address.
3138 STRICT specifies whether strict register checking applies. */
3139
3140 static bool
3141 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3142 {
3143 struct s390_address ad;
3144
3145 if (TARGET_Z10
3146 && larl_operand (addr, VOIDmode)
3147 && (mode == VOIDmode
3148 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3149 return true;
3150
3151 if (!s390_decompose_address (addr, &ad))
3152 return false;
3153
3154 if (strict)
3155 {
3156 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3157 return false;
3158
3159 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3160 return false;
3161 }
3162 else
3163 {
3164 if (ad.base
3165 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3166 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3167 return false;
3168
3169 if (ad.indx
3170 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3171 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3172 return false;
3173 }
3174 return true;
3175 }
3176
3177 /* Return true if OP is a valid operand for the LA instruction.
3178 In 31-bit, we need to prove that the result is used as an
3179 address, as LA performs only a 31-bit addition. */
3180
3181 bool
3182 legitimate_la_operand_p (rtx op)
3183 {
3184 struct s390_address addr;
3185 if (!s390_decompose_address (op, &addr))
3186 return false;
3187
3188 return (TARGET_64BIT || addr.pointer);
3189 }
3190
3191 /* Return true if it is valid *and* preferable to use LA to
3192 compute the sum of OP1 and OP2. */
3193
3194 bool
3195 preferred_la_operand_p (rtx op1, rtx op2)
3196 {
3197 struct s390_address addr;
3198
3199 if (op2 != const0_rtx)
3200 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3201
3202 if (!s390_decompose_address (op1, &addr))
3203 return false;
3204 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3205 return false;
3206 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3207 return false;
3208
3209 if (!TARGET_64BIT && !addr.pointer)
3210 return false;
3211
3212 if (addr.pointer)
3213 return true;
3214
3215 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3216 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3217 return true;
3218
3219 return false;
3220 }
3221
3222 /* Emit a forced load-address operation to load SRC into DST.
3223 This will use the LOAD ADDRESS instruction even in situations
3224 where legitimate_la_operand_p (SRC) returns false. */
3225
3226 void
3227 s390_load_address (rtx dst, rtx src)
3228 {
3229 if (TARGET_64BIT)
3230 emit_move_insn (dst, src);
3231 else
3232 emit_insn (gen_force_la_31 (dst, src));
3233 }
3234
3235 /* Return a legitimate reference for ORIG (an address) using the
3236 register REG. If REG is 0, a new pseudo is generated.
3237
3238 There are two types of references that must be handled:
3239
3240 1. Global data references must load the address from the GOT, via
3241 the PIC reg. An insn is emitted to do this load, and the reg is
3242 returned.
3243
3244 2. Static data references, constant pool addresses, and code labels
3245 compute the address as an offset from the GOT, whose base is in
3246 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3247 differentiate them from global data objects. The returned
3248 address is the PIC reg + an unspec constant.
3249
3250 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3251 reg also appears in the address. */
3252
3253 rtx
3254 legitimize_pic_address (rtx orig, rtx reg)
3255 {
3256 rtx addr = orig;
3257 rtx new_rtx = orig;
3258 rtx base;
3259
3260 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3261
3262 if (GET_CODE (addr) == LABEL_REF
3263 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3264 {
3265 /* This is a local symbol. */
3266 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3267 {
3268 /* Access local symbols PC-relative via LARL.
3269 This is the same as in the non-PIC case, so it is
3270 handled automatically ... */
3271 }
3272 else
3273 {
3274 /* Access local symbols relative to the GOT. */
3275
3276 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3277
3278 if (reload_in_progress || reload_completed)
3279 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3280
3281 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3282 addr = gen_rtx_CONST (Pmode, addr);
3283 addr = force_const_mem (Pmode, addr);
3284 emit_move_insn (temp, addr);
3285
3286 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3287 if (reg != 0)
3288 {
3289 s390_load_address (reg, new_rtx);
3290 new_rtx = reg;
3291 }
3292 }
3293 }
3294 else if (GET_CODE (addr) == SYMBOL_REF)
3295 {
3296 if (reg == 0)
3297 reg = gen_reg_rtx (Pmode);
3298
3299 if (flag_pic == 1)
3300 {
3301 /* Assume GOT offset < 4k. This is handled the same way
3302 in both 31- and 64-bit code (@GOT). */
3303
3304 if (reload_in_progress || reload_completed)
3305 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3306
3307 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3308 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3309 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3310 new_rtx = gen_const_mem (Pmode, new_rtx);
3311 emit_move_insn (reg, new_rtx);
3312 new_rtx = reg;
3313 }
3314 else if (TARGET_CPU_ZARCH)
3315 {
3316 /* If the GOT offset might be >= 4k, we determine the position
3317 of the GOT entry via a PC-relative LARL (@GOTENT). */
3318
3319 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3320
3321 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3322 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3323
3324 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3325 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3326 emit_move_insn (temp, new_rtx);
3327
3328 new_rtx = gen_const_mem (Pmode, temp);
3329 emit_move_insn (reg, new_rtx);
3330 new_rtx = reg;
3331 }
3332 else
3333 {
3334 /* If the GOT offset might be >= 4k, we have to load it
3335 from the literal pool (@GOT). */
3336
3337 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3338
3339 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3340 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3341
3342 if (reload_in_progress || reload_completed)
3343 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3344
3345 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3346 addr = gen_rtx_CONST (Pmode, addr);
3347 addr = force_const_mem (Pmode, addr);
3348 emit_move_insn (temp, addr);
3349
3350 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3351 new_rtx = gen_const_mem (Pmode, new_rtx);
3352 emit_move_insn (reg, new_rtx);
3353 new_rtx = reg;
3354 }
3355 }
3356 else
3357 {
3358 if (GET_CODE (addr) == CONST)
3359 {
3360 addr = XEXP (addr, 0);
3361 if (GET_CODE (addr) == UNSPEC)
3362 {
3363 gcc_assert (XVECLEN (addr, 0) == 1);
3364 switch (XINT (addr, 1))
3365 {
3366 /* If someone moved a GOT-relative UNSPEC
3367 out of the literal pool, force them back in. */
3368 case UNSPEC_GOTOFF:
3369 case UNSPEC_PLTOFF:
3370 new_rtx = force_const_mem (Pmode, orig);
3371 break;
3372
3373 /* @GOT is OK as is if small. */
3374 case UNSPEC_GOT:
3375 if (flag_pic == 2)
3376 new_rtx = force_const_mem (Pmode, orig);
3377 break;
3378
3379 /* @GOTENT is OK as is. */
3380 case UNSPEC_GOTENT:
3381 break;
3382
3383 /* @PLT is OK as is on 64-bit, must be converted to
3384 GOT-relative @PLTOFF on 31-bit. */
3385 case UNSPEC_PLT:
3386 if (!TARGET_CPU_ZARCH)
3387 {
3388 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3389
3390 if (reload_in_progress || reload_completed)
3391 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3392
3393 addr = XVECEXP (addr, 0, 0);
3394 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3395 UNSPEC_PLTOFF);
3396 addr = gen_rtx_CONST (Pmode, addr);
3397 addr = force_const_mem (Pmode, addr);
3398 emit_move_insn (temp, addr);
3399
3400 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3401 if (reg != 0)
3402 {
3403 s390_load_address (reg, new_rtx);
3404 new_rtx = reg;
3405 }
3406 }
3407 break;
3408
3409 /* Everything else cannot happen. */
3410 default:
3411 gcc_unreachable ();
3412 }
3413 }
3414 else
3415 gcc_assert (GET_CODE (addr) == PLUS);
3416 }
3417 if (GET_CODE (addr) == PLUS)
3418 {
3419 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3420
3421 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3422 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3423
3424 /* Check first to see if this is a constant offset
3425 from a local symbol reference. */
3426 if ((GET_CODE (op0) == LABEL_REF
3427 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3428 && GET_CODE (op1) == CONST_INT)
3429 {
3430 if (TARGET_CPU_ZARCH
3431 && larl_operand (op0, VOIDmode)
3432 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3433 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3434 {
3435 if (INTVAL (op1) & 1)
3436 {
3437 /* LARL can't handle odd offsets, so emit a
3438 pair of LARL and LA. */
3439 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3440
3441 if (!DISP_IN_RANGE (INTVAL (op1)))
3442 {
3443 HOST_WIDE_INT even = INTVAL (op1) - 1;
3444 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3445 op0 = gen_rtx_CONST (Pmode, op0);
3446 op1 = const1_rtx;
3447 }
3448
3449 emit_move_insn (temp, op0);
3450 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3451
3452 if (reg != 0)
3453 {
3454 s390_load_address (reg, new_rtx);
3455 new_rtx = reg;
3456 }
3457 }
3458 else
3459 {
3460 /* If the offset is even, we can just use LARL.
3461 This will happen automatically. */
3462 }
3463 }
3464 else
3465 {
3466 /* Access local symbols relative to the GOT. */
3467
3468 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3469
3470 if (reload_in_progress || reload_completed)
3471 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3472
3473 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3474 UNSPEC_GOTOFF);
3475 addr = gen_rtx_PLUS (Pmode, addr, op1);
3476 addr = gen_rtx_CONST (Pmode, addr);
3477 addr = force_const_mem (Pmode, addr);
3478 emit_move_insn (temp, addr);
3479
3480 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3481 if (reg != 0)
3482 {
3483 s390_load_address (reg, new_rtx);
3484 new_rtx = reg;
3485 }
3486 }
3487 }
3488
3489 /* Now, check whether it is a GOT relative symbol plus offset
3490 that was pulled out of the literal pool. Force it back in. */
3491
3492 else if (GET_CODE (op0) == UNSPEC
3493 && GET_CODE (op1) == CONST_INT
3494 && XINT (op0, 1) == UNSPEC_GOTOFF)
3495 {
3496 gcc_assert (XVECLEN (op0, 0) == 1);
3497
3498 new_rtx = force_const_mem (Pmode, orig);
3499 }
3500
3501 /* Otherwise, compute the sum. */
3502 else
3503 {
3504 base = legitimize_pic_address (XEXP (addr, 0), reg);
3505 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3506 base == reg ? NULL_RTX : reg);
3507 if (GET_CODE (new_rtx) == CONST_INT)
3508 new_rtx = plus_constant (base, INTVAL (new_rtx));
3509 else
3510 {
3511 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3512 {
3513 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3514 new_rtx = XEXP (new_rtx, 1);
3515 }
3516 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3517 }
3518
3519 if (GET_CODE (new_rtx) == CONST)
3520 new_rtx = XEXP (new_rtx, 0);
3521 new_rtx = force_operand (new_rtx, 0);
3522 }
3523 }
3524 }
3525 return new_rtx;
3526 }
3527
3528 /* Load the thread pointer into a register. */
3529
3530 rtx
3531 s390_get_thread_pointer (void)
3532 {
3533 rtx tp = gen_reg_rtx (Pmode);
3534
3535 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3536 mark_reg_pointer (tp, BITS_PER_WORD);
3537
3538 return tp;
3539 }
3540
3541 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3542 in s390_tls_symbol which always refers to __tls_get_offset.
3543 The returned offset is written to RESULT_REG and an USE rtx is
3544 generated for TLS_CALL. */
3545
3546 static GTY(()) rtx s390_tls_symbol;
3547
3548 static void
3549 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3550 {
3551 rtx insn;
3552
3553 gcc_assert (flag_pic);
3554
3555 if (!s390_tls_symbol)
3556 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3557
3558 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3559 gen_rtx_REG (Pmode, RETURN_REGNUM));
3560
3561 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3562 RTL_CONST_CALL_P (insn) = 1;
3563 }
3564
3565 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3566 this (thread-local) address. REG may be used as temporary. */
3567
3568 static rtx
3569 legitimize_tls_address (rtx addr, rtx reg)
3570 {
3571 rtx new_rtx, tls_call, temp, base, r2, insn;
3572
3573 if (GET_CODE (addr) == SYMBOL_REF)
3574 switch (tls_symbolic_operand (addr))
3575 {
3576 case TLS_MODEL_GLOBAL_DYNAMIC:
3577 start_sequence ();
3578 r2 = gen_rtx_REG (Pmode, 2);
3579 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3580 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3581 new_rtx = force_const_mem (Pmode, new_rtx);
3582 emit_move_insn (r2, new_rtx);
3583 s390_emit_tls_call_insn (r2, tls_call);
3584 insn = get_insns ();
3585 end_sequence ();
3586
3587 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3588 temp = gen_reg_rtx (Pmode);
3589 emit_libcall_block (insn, temp, r2, new_rtx);
3590
3591 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3592 if (reg != 0)
3593 {
3594 s390_load_address (reg, new_rtx);
3595 new_rtx = reg;
3596 }
3597 break;
3598
3599 case TLS_MODEL_LOCAL_DYNAMIC:
3600 start_sequence ();
3601 r2 = gen_rtx_REG (Pmode, 2);
3602 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3603 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3604 new_rtx = force_const_mem (Pmode, new_rtx);
3605 emit_move_insn (r2, new_rtx);
3606 s390_emit_tls_call_insn (r2, tls_call);
3607 insn = get_insns ();
3608 end_sequence ();
3609
3610 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3611 temp = gen_reg_rtx (Pmode);
3612 emit_libcall_block (insn, temp, r2, new_rtx);
3613
3614 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3615 base = gen_reg_rtx (Pmode);
3616 s390_load_address (base, new_rtx);
3617
3618 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3619 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3620 new_rtx = force_const_mem (Pmode, new_rtx);
3621 temp = gen_reg_rtx (Pmode);
3622 emit_move_insn (temp, new_rtx);
3623
3624 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3625 if (reg != 0)
3626 {
3627 s390_load_address (reg, new_rtx);
3628 new_rtx = reg;
3629 }
3630 break;
3631
3632 case TLS_MODEL_INITIAL_EXEC:
3633 if (flag_pic == 1)
3634 {
3635 /* Assume GOT offset < 4k. This is handled the same way
3636 in both 31- and 64-bit code. */
3637
3638 if (reload_in_progress || reload_completed)
3639 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3640
3641 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3642 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3643 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3644 new_rtx = gen_const_mem (Pmode, new_rtx);
3645 temp = gen_reg_rtx (Pmode);
3646 emit_move_insn (temp, new_rtx);
3647 }
3648 else if (TARGET_CPU_ZARCH)
3649 {
3650 /* If the GOT offset might be >= 4k, we determine the position
3651 of the GOT entry via a PC-relative LARL. */
3652
3653 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3654 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3655 temp = gen_reg_rtx (Pmode);
3656 emit_move_insn (temp, new_rtx);
3657
3658 new_rtx = gen_const_mem (Pmode, temp);
3659 temp = gen_reg_rtx (Pmode);
3660 emit_move_insn (temp, new_rtx);
3661 }
3662 else if (flag_pic)
3663 {
3664 /* If the GOT offset might be >= 4k, we have to load it
3665 from the literal pool. */
3666
3667 if (reload_in_progress || reload_completed)
3668 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3669
3670 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3671 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3672 new_rtx = force_const_mem (Pmode, new_rtx);
3673 temp = gen_reg_rtx (Pmode);
3674 emit_move_insn (temp, new_rtx);
3675
3676 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3677 new_rtx = gen_const_mem (Pmode, new_rtx);
3678
3679 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3680 temp = gen_reg_rtx (Pmode);
3681 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3682 }
3683 else
3684 {
3685 /* In position-dependent code, load the absolute address of
3686 the GOT entry from the literal pool. */
3687
3688 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3689 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3690 new_rtx = force_const_mem (Pmode, new_rtx);
3691 temp = gen_reg_rtx (Pmode);
3692 emit_move_insn (temp, new_rtx);
3693
3694 new_rtx = temp;
3695 new_rtx = gen_const_mem (Pmode, new_rtx);
3696 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3697 temp = gen_reg_rtx (Pmode);
3698 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3699 }
3700
3701 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3702 if (reg != 0)
3703 {
3704 s390_load_address (reg, new_rtx);
3705 new_rtx = reg;
3706 }
3707 break;
3708
3709 case TLS_MODEL_LOCAL_EXEC:
3710 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3711 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3712 new_rtx = force_const_mem (Pmode, new_rtx);
3713 temp = gen_reg_rtx (Pmode);
3714 emit_move_insn (temp, new_rtx);
3715
3716 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3717 if (reg != 0)
3718 {
3719 s390_load_address (reg, new_rtx);
3720 new_rtx = reg;
3721 }
3722 break;
3723
3724 default:
3725 gcc_unreachable ();
3726 }
3727
3728 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3729 {
3730 switch (XINT (XEXP (addr, 0), 1))
3731 {
3732 case UNSPEC_INDNTPOFF:
3733 gcc_assert (TARGET_CPU_ZARCH);
3734 new_rtx = addr;
3735 break;
3736
3737 default:
3738 gcc_unreachable ();
3739 }
3740 }
3741
3742 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3743 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3744 {
3745 new_rtx = XEXP (XEXP (addr, 0), 0);
3746 if (GET_CODE (new_rtx) != SYMBOL_REF)
3747 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3748
3749 new_rtx = legitimize_tls_address (new_rtx, reg);
3750 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3751 new_rtx = force_operand (new_rtx, 0);
3752 }
3753
3754 else
3755 gcc_unreachable (); /* for now ... */
3756
3757 return new_rtx;
3758 }
3759
3760 /* Emit insns making the address in operands[1] valid for a standard
3761 move to operands[0]. operands[1] is replaced by an address which
3762 should be used instead of the former RTX to emit the move
3763 pattern. */
3764
3765 void
3766 emit_symbolic_move (rtx *operands)
3767 {
3768 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3769
3770 if (GET_CODE (operands[0]) == MEM)
3771 operands[1] = force_reg (Pmode, operands[1]);
3772 else if (TLS_SYMBOLIC_CONST (operands[1]))
3773 operands[1] = legitimize_tls_address (operands[1], temp);
3774 else if (flag_pic)
3775 operands[1] = legitimize_pic_address (operands[1], temp);
3776 }
3777
3778 /* Try machine-dependent ways of modifying an illegitimate address X
3779 to be legitimate. If we find one, return the new, valid address.
3780
3781 OLDX is the address as it was before break_out_memory_refs was called.
3782 In some cases it is useful to look at this to decide what needs to be done.
3783
3784 MODE is the mode of the operand pointed to by X.
3785
3786 When -fpic is used, special handling is needed for symbolic references.
3787 See comments by legitimize_pic_address for details. */
3788
3789 static rtx
3790 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3791 enum machine_mode mode ATTRIBUTE_UNUSED)
3792 {
3793 rtx constant_term = const0_rtx;
3794
3795 if (TLS_SYMBOLIC_CONST (x))
3796 {
3797 x = legitimize_tls_address (x, 0);
3798
3799 if (s390_legitimate_address_p (mode, x, FALSE))
3800 return x;
3801 }
3802 else if (GET_CODE (x) == PLUS
3803 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3804 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3805 {
3806 return x;
3807 }
3808 else if (flag_pic)
3809 {
3810 if (SYMBOLIC_CONST (x)
3811 || (GET_CODE (x) == PLUS
3812 && (SYMBOLIC_CONST (XEXP (x, 0))
3813 || SYMBOLIC_CONST (XEXP (x, 1)))))
3814 x = legitimize_pic_address (x, 0);
3815
3816 if (s390_legitimate_address_p (mode, x, FALSE))
3817 return x;
3818 }
3819
3820 x = eliminate_constant_term (x, &constant_term);
3821
3822 /* Optimize loading of large displacements by splitting them
3823 into the multiple of 4K and the rest; this allows the
3824 former to be CSE'd if possible.
3825
3826 Don't do this if the displacement is added to a register
3827 pointing into the stack frame, as the offsets will
3828 change later anyway. */
3829
3830 if (GET_CODE (constant_term) == CONST_INT
3831 && !TARGET_LONG_DISPLACEMENT
3832 && !DISP_IN_RANGE (INTVAL (constant_term))
3833 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3834 {
3835 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3836 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3837
3838 rtx temp = gen_reg_rtx (Pmode);
3839 rtx val = force_operand (GEN_INT (upper), temp);
3840 if (val != temp)
3841 emit_move_insn (temp, val);
3842
3843 x = gen_rtx_PLUS (Pmode, x, temp);
3844 constant_term = GEN_INT (lower);
3845 }
3846
3847 if (GET_CODE (x) == PLUS)
3848 {
3849 if (GET_CODE (XEXP (x, 0)) == REG)
3850 {
3851 rtx temp = gen_reg_rtx (Pmode);
3852 rtx val = force_operand (XEXP (x, 1), temp);
3853 if (val != temp)
3854 emit_move_insn (temp, val);
3855
3856 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3857 }
3858
3859 else if (GET_CODE (XEXP (x, 1)) == REG)
3860 {
3861 rtx temp = gen_reg_rtx (Pmode);
3862 rtx val = force_operand (XEXP (x, 0), temp);
3863 if (val != temp)
3864 emit_move_insn (temp, val);
3865
3866 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3867 }
3868 }
3869
3870 if (constant_term != const0_rtx)
3871 x = gen_rtx_PLUS (Pmode, x, constant_term);
3872
3873 return x;
3874 }
3875
3876 /* Try a machine-dependent way of reloading an illegitimate address AD
3877 operand. If we find one, push the reload and and return the new address.
3878
3879 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3880 and TYPE is the reload type of the current reload. */
3881
3882 rtx
3883 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3884 int opnum, int type)
3885 {
3886 if (!optimize || TARGET_LONG_DISPLACEMENT)
3887 return NULL_RTX;
3888
3889 if (GET_CODE (ad) == PLUS)
3890 {
3891 rtx tem = simplify_binary_operation (PLUS, Pmode,
3892 XEXP (ad, 0), XEXP (ad, 1));
3893 if (tem)
3894 ad = tem;
3895 }
3896
3897 if (GET_CODE (ad) == PLUS
3898 && GET_CODE (XEXP (ad, 0)) == REG
3899 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3900 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3901 {
3902 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3903 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3904 rtx cst, tem, new_rtx;
3905
3906 cst = GEN_INT (upper);
3907 if (!legitimate_reload_constant_p (cst))
3908 cst = force_const_mem (Pmode, cst);
3909
3910 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3911 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3912
3913 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3914 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3915 opnum, (enum reload_type) type);
3916 return new_rtx;
3917 }
3918
3919 return NULL_RTX;
3920 }
3921
3922 /* Emit code to move LEN bytes from DST to SRC. */
3923
3924 void
3925 s390_expand_movmem (rtx dst, rtx src, rtx len)
3926 {
3927 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3928 {
3929 if (INTVAL (len) > 0)
3930 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3931 }
3932
3933 else if (TARGET_MVCLE)
3934 {
3935 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3936 }
3937
3938 else
3939 {
3940 rtx dst_addr, src_addr, count, blocks, temp;
3941 rtx loop_start_label = gen_label_rtx ();
3942 rtx loop_end_label = gen_label_rtx ();
3943 rtx end_label = gen_label_rtx ();
3944 enum machine_mode mode;
3945
3946 mode = GET_MODE (len);
3947 if (mode == VOIDmode)
3948 mode = Pmode;
3949
3950 dst_addr = gen_reg_rtx (Pmode);
3951 src_addr = gen_reg_rtx (Pmode);
3952 count = gen_reg_rtx (mode);
3953 blocks = gen_reg_rtx (mode);
3954
3955 convert_move (count, len, 1);
3956 emit_cmp_and_jump_insns (count, const0_rtx,
3957 EQ, NULL_RTX, mode, 1, end_label);
3958
3959 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3960 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3961 dst = change_address (dst, VOIDmode, dst_addr);
3962 src = change_address (src, VOIDmode, src_addr);
3963
3964 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3965 OPTAB_DIRECT);
3966 if (temp != count)
3967 emit_move_insn (count, temp);
3968
3969 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3970 OPTAB_DIRECT);
3971 if (temp != blocks)
3972 emit_move_insn (blocks, temp);
3973
3974 emit_cmp_and_jump_insns (blocks, const0_rtx,
3975 EQ, NULL_RTX, mode, 1, loop_end_label);
3976
3977 emit_label (loop_start_label);
3978
3979 if (TARGET_Z10
3980 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
3981 {
3982 rtx prefetch;
3983
3984 /* Issue a read prefetch for the +3 cache line. */
3985 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
3986 const0_rtx, const0_rtx);
3987 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3988 emit_insn (prefetch);
3989
3990 /* Issue a write prefetch for the +3 cache line. */
3991 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
3992 const1_rtx, const0_rtx);
3993 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3994 emit_insn (prefetch);
3995 }
3996
3997 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3998 s390_load_address (dst_addr,
3999 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4000 s390_load_address (src_addr,
4001 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4002
4003 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4004 OPTAB_DIRECT);
4005 if (temp != blocks)
4006 emit_move_insn (blocks, temp);
4007
4008 emit_cmp_and_jump_insns (blocks, const0_rtx,
4009 EQ, NULL_RTX, mode, 1, loop_end_label);
4010
4011 emit_jump (loop_start_label);
4012 emit_label (loop_end_label);
4013
4014 emit_insn (gen_movmem_short (dst, src,
4015 convert_to_mode (Pmode, count, 1)));
4016 emit_label (end_label);
4017 }
4018 }
4019
4020 /* Emit code to set LEN bytes at DST to VAL.
4021 Make use of clrmem if VAL is zero. */
4022
4023 void
4024 s390_expand_setmem (rtx dst, rtx len, rtx val)
4025 {
4026 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4027 return;
4028
4029 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4030
4031 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4032 {
4033 if (val == const0_rtx && INTVAL (len) <= 256)
4034 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4035 else
4036 {
4037 /* Initialize memory by storing the first byte. */
4038 emit_move_insn (adjust_address (dst, QImode, 0), val);
4039
4040 if (INTVAL (len) > 1)
4041 {
4042 /* Initiate 1 byte overlap move.
4043 The first byte of DST is propagated through DSTP1.
4044 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4045 DST is set to size 1 so the rest of the memory location
4046 does not count as source operand. */
4047 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4048 set_mem_size (dst, const1_rtx);
4049
4050 emit_insn (gen_movmem_short (dstp1, dst,
4051 GEN_INT (INTVAL (len) - 2)));
4052 }
4053 }
4054 }
4055
4056 else if (TARGET_MVCLE)
4057 {
4058 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4059 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4060 }
4061
4062 else
4063 {
4064 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4065 rtx loop_start_label = gen_label_rtx ();
4066 rtx loop_end_label = gen_label_rtx ();
4067 rtx end_label = gen_label_rtx ();
4068 enum machine_mode mode;
4069
4070 mode = GET_MODE (len);
4071 if (mode == VOIDmode)
4072 mode = Pmode;
4073
4074 dst_addr = gen_reg_rtx (Pmode);
4075 count = gen_reg_rtx (mode);
4076 blocks = gen_reg_rtx (mode);
4077
4078 convert_move (count, len, 1);
4079 emit_cmp_and_jump_insns (count, const0_rtx,
4080 EQ, NULL_RTX, mode, 1, end_label);
4081
4082 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4083 dst = change_address (dst, VOIDmode, dst_addr);
4084
4085 if (val == const0_rtx)
4086 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4087 OPTAB_DIRECT);
4088 else
4089 {
4090 dstp1 = adjust_address (dst, VOIDmode, 1);
4091 set_mem_size (dst, const1_rtx);
4092
4093 /* Initialize memory by storing the first byte. */
4094 emit_move_insn (adjust_address (dst, QImode, 0), val);
4095
4096 /* If count is 1 we are done. */
4097 emit_cmp_and_jump_insns (count, const1_rtx,
4098 EQ, NULL_RTX, mode, 1, end_label);
4099
4100 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4101 OPTAB_DIRECT);
4102 }
4103 if (temp != count)
4104 emit_move_insn (count, temp);
4105
4106 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4107 OPTAB_DIRECT);
4108 if (temp != blocks)
4109 emit_move_insn (blocks, temp);
4110
4111 emit_cmp_and_jump_insns (blocks, const0_rtx,
4112 EQ, NULL_RTX, mode, 1, loop_end_label);
4113
4114 emit_label (loop_start_label);
4115
4116 if (TARGET_Z10
4117 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4118 {
4119 /* Issue a write prefetch for the +4 cache line. */
4120 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4121 GEN_INT (1024)),
4122 const1_rtx, const0_rtx);
4123 emit_insn (prefetch);
4124 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4125 }
4126
4127 if (val == const0_rtx)
4128 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4129 else
4130 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4131 s390_load_address (dst_addr,
4132 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4133
4134 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4135 OPTAB_DIRECT);
4136 if (temp != blocks)
4137 emit_move_insn (blocks, temp);
4138
4139 emit_cmp_and_jump_insns (blocks, const0_rtx,
4140 EQ, NULL_RTX, mode, 1, loop_end_label);
4141
4142 emit_jump (loop_start_label);
4143 emit_label (loop_end_label);
4144
4145 if (val == const0_rtx)
4146 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4147 else
4148 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4149 emit_label (end_label);
4150 }
4151 }
4152
4153 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4154 and return the result in TARGET. */
4155
4156 void
4157 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4158 {
4159 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4160 rtx tmp;
4161
4162 /* As the result of CMPINT is inverted compared to what we need,
4163 we have to swap the operands. */
4164 tmp = op0; op0 = op1; op1 = tmp;
4165
4166 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4167 {
4168 if (INTVAL (len) > 0)
4169 {
4170 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4171 emit_insn (gen_cmpint (target, ccreg));
4172 }
4173 else
4174 emit_move_insn (target, const0_rtx);
4175 }
4176 else if (TARGET_MVCLE)
4177 {
4178 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4179 emit_insn (gen_cmpint (target, ccreg));
4180 }
4181 else
4182 {
4183 rtx addr0, addr1, count, blocks, temp;
4184 rtx loop_start_label = gen_label_rtx ();
4185 rtx loop_end_label = gen_label_rtx ();
4186 rtx end_label = gen_label_rtx ();
4187 enum machine_mode mode;
4188
4189 mode = GET_MODE (len);
4190 if (mode == VOIDmode)
4191 mode = Pmode;
4192
4193 addr0 = gen_reg_rtx (Pmode);
4194 addr1 = gen_reg_rtx (Pmode);
4195 count = gen_reg_rtx (mode);
4196 blocks = gen_reg_rtx (mode);
4197
4198 convert_move (count, len, 1);
4199 emit_cmp_and_jump_insns (count, const0_rtx,
4200 EQ, NULL_RTX, mode, 1, end_label);
4201
4202 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4203 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4204 op0 = change_address (op0, VOIDmode, addr0);
4205 op1 = change_address (op1, VOIDmode, addr1);
4206
4207 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4208 OPTAB_DIRECT);
4209 if (temp != count)
4210 emit_move_insn (count, temp);
4211
4212 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4213 OPTAB_DIRECT);
4214 if (temp != blocks)
4215 emit_move_insn (blocks, temp);
4216
4217 emit_cmp_and_jump_insns (blocks, const0_rtx,
4218 EQ, NULL_RTX, mode, 1, loop_end_label);
4219
4220 emit_label (loop_start_label);
4221
4222 if (TARGET_Z10
4223 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4224 {
4225 rtx prefetch;
4226
4227 /* Issue a read prefetch for the +2 cache line of operand 1. */
4228 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4229 const0_rtx, const0_rtx);
4230 emit_insn (prefetch);
4231 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4232
4233 /* Issue a read prefetch for the +2 cache line of operand 2. */
4234 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4235 const0_rtx, const0_rtx);
4236 emit_insn (prefetch);
4237 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4238 }
4239
4240 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4241 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4242 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4243 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4244 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4245 emit_jump_insn (temp);
4246
4247 s390_load_address (addr0,
4248 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4249 s390_load_address (addr1,
4250 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4251
4252 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4253 OPTAB_DIRECT);
4254 if (temp != blocks)
4255 emit_move_insn (blocks, temp);
4256
4257 emit_cmp_and_jump_insns (blocks, const0_rtx,
4258 EQ, NULL_RTX, mode, 1, loop_end_label);
4259
4260 emit_jump (loop_start_label);
4261 emit_label (loop_end_label);
4262
4263 emit_insn (gen_cmpmem_short (op0, op1,
4264 convert_to_mode (Pmode, count, 1)));
4265 emit_label (end_label);
4266
4267 emit_insn (gen_cmpint (target, ccreg));
4268 }
4269 }
4270
4271
4272 /* Expand conditional increment or decrement using alc/slb instructions.
4273 Should generate code setting DST to either SRC or SRC + INCREMENT,
4274 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4275 Returns true if successful, false otherwise.
4276
4277 That makes it possible to implement some if-constructs without jumps e.g.:
4278 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4279 unsigned int a, b, c;
4280 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4281 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4282 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4283 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4284
4285 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4286 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4287 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4288 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4289 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4290
4291 bool
4292 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4293 rtx dst, rtx src, rtx increment)
4294 {
4295 enum machine_mode cmp_mode;
4296 enum machine_mode cc_mode;
4297 rtx op_res;
4298 rtx insn;
4299 rtvec p;
4300 int ret;
4301
4302 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4303 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4304 cmp_mode = SImode;
4305 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4306 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4307 cmp_mode = DImode;
4308 else
4309 return false;
4310
4311 /* Try ADD LOGICAL WITH CARRY. */
4312 if (increment == const1_rtx)
4313 {
4314 /* Determine CC mode to use. */
4315 if (cmp_code == EQ || cmp_code == NE)
4316 {
4317 if (cmp_op1 != const0_rtx)
4318 {
4319 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4320 NULL_RTX, 0, OPTAB_WIDEN);
4321 cmp_op1 = const0_rtx;
4322 }
4323
4324 cmp_code = cmp_code == EQ ? LEU : GTU;
4325 }
4326
4327 if (cmp_code == LTU || cmp_code == LEU)
4328 {
4329 rtx tem = cmp_op0;
4330 cmp_op0 = cmp_op1;
4331 cmp_op1 = tem;
4332 cmp_code = swap_condition (cmp_code);
4333 }
4334
4335 switch (cmp_code)
4336 {
4337 case GTU:
4338 cc_mode = CCUmode;
4339 break;
4340
4341 case GEU:
4342 cc_mode = CCL3mode;
4343 break;
4344
4345 default:
4346 return false;
4347 }
4348
4349 /* Emit comparison instruction pattern. */
4350 if (!register_operand (cmp_op0, cmp_mode))
4351 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4352
4353 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4354 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4355 /* We use insn_invalid_p here to add clobbers if required. */
4356 ret = insn_invalid_p (emit_insn (insn));
4357 gcc_assert (!ret);
4358
4359 /* Emit ALC instruction pattern. */
4360 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4361 gen_rtx_REG (cc_mode, CC_REGNUM),
4362 const0_rtx);
4363
4364 if (src != const0_rtx)
4365 {
4366 if (!register_operand (src, GET_MODE (dst)))
4367 src = force_reg (GET_MODE (dst), src);
4368
4369 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4370 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4371 }
4372
4373 p = rtvec_alloc (2);
4374 RTVEC_ELT (p, 0) =
4375 gen_rtx_SET (VOIDmode, dst, op_res);
4376 RTVEC_ELT (p, 1) =
4377 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4378 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4379
4380 return true;
4381 }
4382
4383 /* Try SUBTRACT LOGICAL WITH BORROW. */
4384 if (increment == constm1_rtx)
4385 {
4386 /* Determine CC mode to use. */
4387 if (cmp_code == EQ || cmp_code == NE)
4388 {
4389 if (cmp_op1 != const0_rtx)
4390 {
4391 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4392 NULL_RTX, 0, OPTAB_WIDEN);
4393 cmp_op1 = const0_rtx;
4394 }
4395
4396 cmp_code = cmp_code == EQ ? LEU : GTU;
4397 }
4398
4399 if (cmp_code == GTU || cmp_code == GEU)
4400 {
4401 rtx tem = cmp_op0;
4402 cmp_op0 = cmp_op1;
4403 cmp_op1 = tem;
4404 cmp_code = swap_condition (cmp_code);
4405 }
4406
4407 switch (cmp_code)
4408 {
4409 case LEU:
4410 cc_mode = CCUmode;
4411 break;
4412
4413 case LTU:
4414 cc_mode = CCL3mode;
4415 break;
4416
4417 default:
4418 return false;
4419 }
4420
4421 /* Emit comparison instruction pattern. */
4422 if (!register_operand (cmp_op0, cmp_mode))
4423 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4424
4425 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4426 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4427 /* We use insn_invalid_p here to add clobbers if required. */
4428 ret = insn_invalid_p (emit_insn (insn));
4429 gcc_assert (!ret);
4430
4431 /* Emit SLB instruction pattern. */
4432 if (!register_operand (src, GET_MODE (dst)))
4433 src = force_reg (GET_MODE (dst), src);
4434
4435 op_res = gen_rtx_MINUS (GET_MODE (dst),
4436 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4437 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4438 gen_rtx_REG (cc_mode, CC_REGNUM),
4439 const0_rtx));
4440 p = rtvec_alloc (2);
4441 RTVEC_ELT (p, 0) =
4442 gen_rtx_SET (VOIDmode, dst, op_res);
4443 RTVEC_ELT (p, 1) =
4444 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4445 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4446
4447 return true;
4448 }
4449
4450 return false;
4451 }
4452
4453 /* Expand code for the insv template. Return true if successful. */
4454
4455 bool
4456 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4457 {
4458 int bitsize = INTVAL (op1);
4459 int bitpos = INTVAL (op2);
4460
4461 /* On z10 we can use the risbg instruction to implement insv. */
4462 if (TARGET_Z10
4463 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4464 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4465 {
4466 rtx op;
4467 rtx clobber;
4468
4469 op = gen_rtx_SET (GET_MODE(src),
4470 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4471 src);
4472 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4473 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4474
4475 return true;
4476 }
4477
4478 /* We need byte alignment. */
4479 if (bitsize % BITS_PER_UNIT)
4480 return false;
4481
4482 if (bitpos == 0
4483 && memory_operand (dest, VOIDmode)
4484 && (register_operand (src, word_mode)
4485 || const_int_operand (src, VOIDmode)))
4486 {
4487 /* Emit standard pattern if possible. */
4488 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4489 if (GET_MODE_BITSIZE (mode) == bitsize)
4490 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4491
4492 /* (set (ze (mem)) (const_int)). */
4493 else if (const_int_operand (src, VOIDmode))
4494 {
4495 int size = bitsize / BITS_PER_UNIT;
4496 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4497 GET_MODE_SIZE (word_mode) - size);
4498
4499 dest = adjust_address (dest, BLKmode, 0);
4500 set_mem_size (dest, GEN_INT (size));
4501 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4502 }
4503
4504 /* (set (ze (mem)) (reg)). */
4505 else if (register_operand (src, word_mode))
4506 {
4507 if (bitsize <= GET_MODE_BITSIZE (SImode))
4508 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4509 const0_rtx), src);
4510 else
4511 {
4512 /* Emit st,stcmh sequence. */
4513 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4514 int size = stcmh_width / BITS_PER_UNIT;
4515
4516 emit_move_insn (adjust_address (dest, SImode, size),
4517 gen_lowpart (SImode, src));
4518 set_mem_size (dest, GEN_INT (size));
4519 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4520 (stcmh_width), const0_rtx),
4521 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4522 (GET_MODE_BITSIZE (SImode))));
4523 }
4524 }
4525 else
4526 return false;
4527
4528 return true;
4529 }
4530
4531 /* (set (ze (reg)) (const_int)). */
4532 if (TARGET_ZARCH
4533 && register_operand (dest, word_mode)
4534 && (bitpos % 16) == 0
4535 && (bitsize % 16) == 0
4536 && const_int_operand (src, VOIDmode))
4537 {
4538 HOST_WIDE_INT val = INTVAL (src);
4539 int regpos = bitpos + bitsize;
4540
4541 while (regpos > bitpos)
4542 {
4543 enum machine_mode putmode;
4544 int putsize;
4545
4546 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4547 putmode = SImode;
4548 else
4549 putmode = HImode;
4550
4551 putsize = GET_MODE_BITSIZE (putmode);
4552 regpos -= putsize;
4553 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4554 GEN_INT (putsize),
4555 GEN_INT (regpos)),
4556 gen_int_mode (val, putmode));
4557 val >>= putsize;
4558 }
4559 gcc_assert (regpos == bitpos);
4560 return true;
4561 }
4562
4563 return false;
4564 }
4565
4566 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4567 register that holds VAL of mode MODE shifted by COUNT bits. */
4568
4569 static inline rtx
4570 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4571 {
4572 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4573 NULL_RTX, 1, OPTAB_DIRECT);
4574 return expand_simple_binop (SImode, ASHIFT, val, count,
4575 NULL_RTX, 1, OPTAB_DIRECT);
4576 }
4577
4578 /* Structure to hold the initial parameters for a compare_and_swap operation
4579 in HImode and QImode. */
4580
4581 struct alignment_context
4582 {
4583 rtx memsi; /* SI aligned memory location. */
4584 rtx shift; /* Bit offset with regard to lsb. */
4585 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4586 rtx modemaski; /* ~modemask */
4587 bool aligned; /* True if memory is aligned, false else. */
4588 };
4589
4590 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4591 structure AC for transparent simplifying, if the memory alignment is known
4592 to be at least 32bit. MEM is the memory location for the actual operation
4593 and MODE its mode. */
4594
4595 static void
4596 init_alignment_context (struct alignment_context *ac, rtx mem,
4597 enum machine_mode mode)
4598 {
4599 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4600 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4601
4602 if (ac->aligned)
4603 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4604 else
4605 {
4606 /* Alignment is unknown. */
4607 rtx byteoffset, addr, align;
4608
4609 /* Force the address into a register. */
4610 addr = force_reg (Pmode, XEXP (mem, 0));
4611
4612 /* Align it to SImode. */
4613 align = expand_simple_binop (Pmode, AND, addr,
4614 GEN_INT (-GET_MODE_SIZE (SImode)),
4615 NULL_RTX, 1, OPTAB_DIRECT);
4616 /* Generate MEM. */
4617 ac->memsi = gen_rtx_MEM (SImode, align);
4618 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4619 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4620 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4621
4622 /* Calculate shiftcount. */
4623 byteoffset = expand_simple_binop (Pmode, AND, addr,
4624 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4625 NULL_RTX, 1, OPTAB_DIRECT);
4626 /* As we already have some offset, evaluate the remaining distance. */
4627 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4628 NULL_RTX, 1, OPTAB_DIRECT);
4629
4630 }
4631 /* Shift is the byte count, but we need the bitcount. */
4632 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4633 NULL_RTX, 1, OPTAB_DIRECT);
4634 /* Calculate masks. */
4635 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4636 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4637 NULL_RTX, 1, OPTAB_DIRECT);
4638 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4639 }
4640
4641 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4642 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4643 to set if CMP == MEM.
4644 CMP is never in memory for compare_and_swap_cc because
4645 expand_bool_compare_and_swap puts it into a register for later compare. */
4646
4647 void
4648 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4649 {
4650 struct alignment_context ac;
4651 rtx cmpv, newv, val, resv, cc;
4652 rtx res = gen_reg_rtx (SImode);
4653 rtx csloop = gen_label_rtx ();
4654 rtx csend = gen_label_rtx ();
4655
4656 gcc_assert (register_operand (target, VOIDmode));
4657 gcc_assert (MEM_P (mem));
4658
4659 init_alignment_context (&ac, mem, mode);
4660
4661 /* Shift the values to the correct bit positions. */
4662 if (!(ac.aligned && MEM_P (cmp)))
4663 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4664 if (!(ac.aligned && MEM_P (new_rtx)))
4665 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4666
4667 /* Load full word. Subsequent loads are performed by CS. */
4668 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4669 NULL_RTX, 1, OPTAB_DIRECT);
4670
4671 /* Start CS loop. */
4672 emit_label (csloop);
4673 /* val = "<mem>00..0<mem>"
4674 * cmp = "00..0<cmp>00..0"
4675 * new = "00..0<new>00..0"
4676 */
4677
4678 /* Patch cmp and new with val at correct position. */
4679 if (ac.aligned && MEM_P (cmp))
4680 {
4681 cmpv = force_reg (SImode, val);
4682 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4683 }
4684 else
4685 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4686 NULL_RTX, 1, OPTAB_DIRECT));
4687 if (ac.aligned && MEM_P (new_rtx))
4688 {
4689 newv = force_reg (SImode, val);
4690 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4691 }
4692 else
4693 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4694 NULL_RTX, 1, OPTAB_DIRECT));
4695
4696 /* Jump to end if we're done (likely?). */
4697 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4698 cmpv, newv));
4699
4700 /* Check for changes outside mode. */
4701 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4702 NULL_RTX, 1, OPTAB_DIRECT);
4703 cc = s390_emit_compare (NE, resv, val);
4704 emit_move_insn (val, resv);
4705 /* Loop internal if so. */
4706 s390_emit_jump (csloop, cc);
4707
4708 emit_label (csend);
4709
4710 /* Return the correct part of the bitfield. */
4711 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4712 NULL_RTX, 1, OPTAB_DIRECT), 1);
4713 }
4714
4715 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4716 and VAL the value to play with. If AFTER is true then store the value
4717 MEM holds after the operation, if AFTER is false then store the value MEM
4718 holds before the operation. If TARGET is zero then discard that value, else
4719 store it to TARGET. */
4720
4721 void
4722 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4723 rtx target, rtx mem, rtx val, bool after)
4724 {
4725 struct alignment_context ac;
4726 rtx cmp;
4727 rtx new_rtx = gen_reg_rtx (SImode);
4728 rtx orig = gen_reg_rtx (SImode);
4729 rtx csloop = gen_label_rtx ();
4730
4731 gcc_assert (!target || register_operand (target, VOIDmode));
4732 gcc_assert (MEM_P (mem));
4733
4734 init_alignment_context (&ac, mem, mode);
4735
4736 /* Shift val to the correct bit positions.
4737 Preserve "icm", but prevent "ex icm". */
4738 if (!(ac.aligned && code == SET && MEM_P (val)))
4739 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4740
4741 /* Further preparation insns. */
4742 if (code == PLUS || code == MINUS)
4743 emit_move_insn (orig, val);
4744 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4745 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4746 NULL_RTX, 1, OPTAB_DIRECT);
4747
4748 /* Load full word. Subsequent loads are performed by CS. */
4749 cmp = force_reg (SImode, ac.memsi);
4750
4751 /* Start CS loop. */
4752 emit_label (csloop);
4753 emit_move_insn (new_rtx, cmp);
4754
4755 /* Patch new with val at correct position. */
4756 switch (code)
4757 {
4758 case PLUS:
4759 case MINUS:
4760 val = expand_simple_binop (SImode, code, new_rtx, orig,
4761 NULL_RTX, 1, OPTAB_DIRECT);
4762 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4763 NULL_RTX, 1, OPTAB_DIRECT);
4764 /* FALLTHRU */
4765 case SET:
4766 if (ac.aligned && MEM_P (val))
4767 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4768 else
4769 {
4770 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4771 NULL_RTX, 1, OPTAB_DIRECT);
4772 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4773 NULL_RTX, 1, OPTAB_DIRECT);
4774 }
4775 break;
4776 case AND:
4777 case IOR:
4778 case XOR:
4779 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4780 NULL_RTX, 1, OPTAB_DIRECT);
4781 break;
4782 case MULT: /* NAND */
4783 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4784 NULL_RTX, 1, OPTAB_DIRECT);
4785 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4786 NULL_RTX, 1, OPTAB_DIRECT);
4787 break;
4788 default:
4789 gcc_unreachable ();
4790 }
4791
4792 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4793 ac.memsi, cmp, new_rtx));
4794
4795 /* Return the correct part of the bitfield. */
4796 if (target)
4797 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4798 after ? new_rtx : cmp, ac.shift,
4799 NULL_RTX, 1, OPTAB_DIRECT), 1);
4800 }
4801
4802 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4803 We need to emit DTP-relative relocations. */
4804
4805 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4806
4807 static void
4808 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4809 {
4810 switch (size)
4811 {
4812 case 4:
4813 fputs ("\t.long\t", file);
4814 break;
4815 case 8:
4816 fputs ("\t.quad\t", file);
4817 break;
4818 default:
4819 gcc_unreachable ();
4820 }
4821 output_addr_const (file, x);
4822 fputs ("@DTPOFF", file);
4823 }
4824
4825 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4826 /* Implement TARGET_MANGLE_TYPE. */
4827
4828 static const char *
4829 s390_mangle_type (const_tree type)
4830 {
4831 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4832 && TARGET_LONG_DOUBLE_128)
4833 return "g";
4834
4835 /* For all other types, use normal C++ mangling. */
4836 return NULL;
4837 }
4838 #endif
4839
4840 /* In the name of slightly smaller debug output, and to cater to
4841 general assembler lossage, recognize various UNSPEC sequences
4842 and turn them back into a direct symbol reference. */
4843
4844 static rtx
4845 s390_delegitimize_address (rtx orig_x)
4846 {
4847 rtx x, y;
4848
4849 orig_x = delegitimize_mem_from_attrs (orig_x);
4850 x = orig_x;
4851 if (GET_CODE (x) != MEM)
4852 return orig_x;
4853
4854 x = XEXP (x, 0);
4855 if (GET_CODE (x) == PLUS
4856 && GET_CODE (XEXP (x, 1)) == CONST
4857 && GET_CODE (XEXP (x, 0)) == REG
4858 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4859 {
4860 y = XEXP (XEXP (x, 1), 0);
4861 if (GET_CODE (y) == UNSPEC
4862 && XINT (y, 1) == UNSPEC_GOT)
4863 return XVECEXP (y, 0, 0);
4864 return orig_x;
4865 }
4866
4867 if (GET_CODE (x) == CONST)
4868 {
4869 y = XEXP (x, 0);
4870 if (GET_CODE (y) == UNSPEC
4871 && XINT (y, 1) == UNSPEC_GOTENT)
4872 return XVECEXP (y, 0, 0);
4873 return orig_x;
4874 }
4875
4876 return orig_x;
4877 }
4878
4879 /* Output operand OP to stdio stream FILE.
4880 OP is an address (register + offset) which is not used to address data;
4881 instead the rightmost bits are interpreted as the value. */
4882
4883 static void
4884 print_shift_count_operand (FILE *file, rtx op)
4885 {
4886 HOST_WIDE_INT offset;
4887 rtx base;
4888
4889 /* Extract base register and offset. */
4890 if (!s390_decompose_shift_count (op, &base, &offset))
4891 gcc_unreachable ();
4892
4893 /* Sanity check. */
4894 if (base)
4895 {
4896 gcc_assert (GET_CODE (base) == REG);
4897 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4898 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4899 }
4900
4901 /* Offsets are constricted to twelve bits. */
4902 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4903 if (base)
4904 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4905 }
4906
4907 /* See 'get_some_local_dynamic_name'. */
4908
4909 static int
4910 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4911 {
4912 rtx x = *px;
4913
4914 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4915 {
4916 x = get_pool_constant (x);
4917 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4918 }
4919
4920 if (GET_CODE (x) == SYMBOL_REF
4921 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4922 {
4923 cfun->machine->some_ld_name = XSTR (x, 0);
4924 return 1;
4925 }
4926
4927 return 0;
4928 }
4929
4930 /* Locate some local-dynamic symbol still in use by this function
4931 so that we can print its name in local-dynamic base patterns. */
4932
4933 static const char *
4934 get_some_local_dynamic_name (void)
4935 {
4936 rtx insn;
4937
4938 if (cfun->machine->some_ld_name)
4939 return cfun->machine->some_ld_name;
4940
4941 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4942 if (INSN_P (insn)
4943 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4944 return cfun->machine->some_ld_name;
4945
4946 gcc_unreachable ();
4947 }
4948
4949 /* Output machine-dependent UNSPECs occurring in address constant X
4950 in assembler syntax to stdio stream FILE. Returns true if the
4951 constant X could be recognized, false otherwise. */
4952
4953 bool
4954 s390_output_addr_const_extra (FILE *file, rtx x)
4955 {
4956 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4957 switch (XINT (x, 1))
4958 {
4959 case UNSPEC_GOTENT:
4960 output_addr_const (file, XVECEXP (x, 0, 0));
4961 fprintf (file, "@GOTENT");
4962 return true;
4963 case UNSPEC_GOT:
4964 output_addr_const (file, XVECEXP (x, 0, 0));
4965 fprintf (file, "@GOT");
4966 return true;
4967 case UNSPEC_GOTOFF:
4968 output_addr_const (file, XVECEXP (x, 0, 0));
4969 fprintf (file, "@GOTOFF");
4970 return true;
4971 case UNSPEC_PLT:
4972 output_addr_const (file, XVECEXP (x, 0, 0));
4973 fprintf (file, "@PLT");
4974 return true;
4975 case UNSPEC_PLTOFF:
4976 output_addr_const (file, XVECEXP (x, 0, 0));
4977 fprintf (file, "@PLTOFF");
4978 return true;
4979 case UNSPEC_TLSGD:
4980 output_addr_const (file, XVECEXP (x, 0, 0));
4981 fprintf (file, "@TLSGD");
4982 return true;
4983 case UNSPEC_TLSLDM:
4984 assemble_name (file, get_some_local_dynamic_name ());
4985 fprintf (file, "@TLSLDM");
4986 return true;
4987 case UNSPEC_DTPOFF:
4988 output_addr_const (file, XVECEXP (x, 0, 0));
4989 fprintf (file, "@DTPOFF");
4990 return true;
4991 case UNSPEC_NTPOFF:
4992 output_addr_const (file, XVECEXP (x, 0, 0));
4993 fprintf (file, "@NTPOFF");
4994 return true;
4995 case UNSPEC_GOTNTPOFF:
4996 output_addr_const (file, XVECEXP (x, 0, 0));
4997 fprintf (file, "@GOTNTPOFF");
4998 return true;
4999 case UNSPEC_INDNTPOFF:
5000 output_addr_const (file, XVECEXP (x, 0, 0));
5001 fprintf (file, "@INDNTPOFF");
5002 return true;
5003 }
5004
5005 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5006 switch (XINT (x, 1))
5007 {
5008 case UNSPEC_POOL_OFFSET:
5009 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5010 output_addr_const (file, x);
5011 return true;
5012 }
5013 return false;
5014 }
5015
5016 /* Output address operand ADDR in assembler syntax to
5017 stdio stream FILE. */
5018
5019 void
5020 print_operand_address (FILE *file, rtx addr)
5021 {
5022 struct s390_address ad;
5023
5024 if (s390_symref_operand_p (addr, NULL, NULL))
5025 {
5026 gcc_assert (TARGET_Z10);
5027 output_addr_const (file, addr);
5028 return;
5029 }
5030
5031 if (!s390_decompose_address (addr, &ad)
5032 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5033 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5034 output_operand_lossage ("cannot decompose address");
5035
5036 if (ad.disp)
5037 output_addr_const (file, ad.disp);
5038 else
5039 fprintf (file, "0");
5040
5041 if (ad.base && ad.indx)
5042 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5043 reg_names[REGNO (ad.base)]);
5044 else if (ad.base)
5045 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5046 }
5047
5048 /* Output operand X in assembler syntax to stdio stream FILE.
5049 CODE specified the format flag. The following format flags
5050 are recognized:
5051
5052 'C': print opcode suffix for branch condition.
5053 'D': print opcode suffix for inverse branch condition.
5054 'E': print opcode suffix for branch on index instruction.
5055 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5056 'G': print the size of the operand in bytes.
5057 'O': print only the displacement of a memory reference.
5058 'R': print only the base register of a memory reference.
5059 'S': print S-type memory reference (base+displacement).
5060 'N': print the second word of a DImode operand.
5061 'M': print the second word of a TImode operand.
5062 'Y': print shift count operand.
5063
5064 'b': print integer X as if it's an unsigned byte.
5065 'c': print integer X as if it's an signed byte.
5066 'x': print integer X as if it's an unsigned halfword.
5067 'h': print integer X as if it's a signed halfword.
5068 'i': print the first nonzero HImode part of X.
5069 'j': print the first HImode part unequal to -1 of X.
5070 'k': print the first nonzero SImode part of X.
5071 'm': print the first SImode part unequal to -1 of X.
5072 'o': print integer X as if it's an unsigned 32bit word. */
5073
5074 void
5075 print_operand (FILE *file, rtx x, int code)
5076 {
5077 switch (code)
5078 {
5079 case 'C':
5080 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5081 return;
5082
5083 case 'D':
5084 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5085 return;
5086
5087 case 'E':
5088 if (GET_CODE (x) == LE)
5089 fprintf (file, "l");
5090 else if (GET_CODE (x) == GT)
5091 fprintf (file, "h");
5092 else
5093 gcc_unreachable ();
5094 return;
5095
5096 case 'J':
5097 if (GET_CODE (x) == SYMBOL_REF)
5098 {
5099 fprintf (file, "%s", ":tls_load:");
5100 output_addr_const (file, x);
5101 }
5102 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5103 {
5104 fprintf (file, "%s", ":tls_gdcall:");
5105 output_addr_const (file, XVECEXP (x, 0, 0));
5106 }
5107 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5108 {
5109 fprintf (file, "%s", ":tls_ldcall:");
5110 assemble_name (file, get_some_local_dynamic_name ());
5111 }
5112 else
5113 gcc_unreachable ();
5114 return;
5115
5116 case 'G':
5117 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5118 return;
5119
5120 case 'O':
5121 {
5122 struct s390_address ad;
5123 int ret;
5124
5125 gcc_assert (GET_CODE (x) == MEM);
5126 ret = s390_decompose_address (XEXP (x, 0), &ad);
5127 gcc_assert (ret);
5128 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5129 gcc_assert (!ad.indx);
5130
5131 if (ad.disp)
5132 output_addr_const (file, ad.disp);
5133 else
5134 fprintf (file, "0");
5135 }
5136 return;
5137
5138 case 'R':
5139 {
5140 struct s390_address ad;
5141 int ret;
5142
5143 gcc_assert (GET_CODE (x) == MEM);
5144 ret = s390_decompose_address (XEXP (x, 0), &ad);
5145 gcc_assert (ret);
5146 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5147 gcc_assert (!ad.indx);
5148
5149 if (ad.base)
5150 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5151 else
5152 fprintf (file, "0");
5153 }
5154 return;
5155
5156 case 'S':
5157 {
5158 struct s390_address ad;
5159 int ret;
5160
5161 gcc_assert (GET_CODE (x) == MEM);
5162 ret = s390_decompose_address (XEXP (x, 0), &ad);
5163 gcc_assert (ret);
5164 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5165 gcc_assert (!ad.indx);
5166
5167 if (ad.disp)
5168 output_addr_const (file, ad.disp);
5169 else
5170 fprintf (file, "0");
5171
5172 if (ad.base)
5173 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5174 }
5175 return;
5176
5177 case 'N':
5178 if (GET_CODE (x) == REG)
5179 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5180 else if (GET_CODE (x) == MEM)
5181 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5182 else
5183 gcc_unreachable ();
5184 break;
5185
5186 case 'M':
5187 if (GET_CODE (x) == REG)
5188 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5189 else if (GET_CODE (x) == MEM)
5190 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5191 else
5192 gcc_unreachable ();
5193 break;
5194
5195 case 'Y':
5196 print_shift_count_operand (file, x);
5197 return;
5198 }
5199
5200 switch (GET_CODE (x))
5201 {
5202 case REG:
5203 fprintf (file, "%s", reg_names[REGNO (x)]);
5204 break;
5205
5206 case MEM:
5207 output_address (XEXP (x, 0));
5208 break;
5209
5210 case CONST:
5211 case CODE_LABEL:
5212 case LABEL_REF:
5213 case SYMBOL_REF:
5214 output_addr_const (file, x);
5215 break;
5216
5217 case CONST_INT:
5218 if (code == 'b')
5219 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5220 else if (code == 'c')
5221 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5222 else if (code == 'x')
5223 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5224 else if (code == 'h')
5225 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5226 else if (code == 'i')
5227 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5228 s390_extract_part (x, HImode, 0));
5229 else if (code == 'j')
5230 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5231 s390_extract_part (x, HImode, -1));
5232 else if (code == 'k')
5233 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5234 s390_extract_part (x, SImode, 0));
5235 else if (code == 'm')
5236 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5237 s390_extract_part (x, SImode, -1));
5238 else if (code == 'o')
5239 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5240 else
5241 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5242 break;
5243
5244 case CONST_DOUBLE:
5245 gcc_assert (GET_MODE (x) == VOIDmode);
5246 if (code == 'b')
5247 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5248 else if (code == 'x')
5249 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5250 else if (code == 'h')
5251 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5252 else
5253 gcc_unreachable ();
5254 break;
5255
5256 default:
5257 fatal_insn ("UNKNOWN in print_operand !?", x);
5258 break;
5259 }
5260 }
5261
5262 /* Target hook for assembling integer objects. We need to define it
5263 here to work a round a bug in some versions of GAS, which couldn't
5264 handle values smaller than INT_MIN when printed in decimal. */
5265
5266 static bool
5267 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5268 {
5269 if (size == 8 && aligned_p
5270 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5271 {
5272 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5273 INTVAL (x));
5274 return true;
5275 }
5276 return default_assemble_integer (x, size, aligned_p);
5277 }
5278
5279 /* Returns true if register REGNO is used for forming
5280 a memory address in expression X. */
5281
5282 static bool
5283 reg_used_in_mem_p (int regno, rtx x)
5284 {
5285 enum rtx_code code = GET_CODE (x);
5286 int i, j;
5287 const char *fmt;
5288
5289 if (code == MEM)
5290 {
5291 if (refers_to_regno_p (regno, regno+1,
5292 XEXP (x, 0), 0))
5293 return true;
5294 }
5295 else if (code == SET
5296 && GET_CODE (SET_DEST (x)) == PC)
5297 {
5298 if (refers_to_regno_p (regno, regno+1,
5299 SET_SRC (x), 0))
5300 return true;
5301 }
5302
5303 fmt = GET_RTX_FORMAT (code);
5304 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5305 {
5306 if (fmt[i] == 'e'
5307 && reg_used_in_mem_p (regno, XEXP (x, i)))
5308 return true;
5309
5310 else if (fmt[i] == 'E')
5311 for (j = 0; j < XVECLEN (x, i); j++)
5312 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5313 return true;
5314 }
5315 return false;
5316 }
5317
5318 /* Returns true if expression DEP_RTX sets an address register
5319 used by instruction INSN to address memory. */
5320
5321 static bool
5322 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5323 {
5324 rtx target, pat;
5325
5326 if (GET_CODE (dep_rtx) == INSN)
5327 dep_rtx = PATTERN (dep_rtx);
5328
5329 if (GET_CODE (dep_rtx) == SET)
5330 {
5331 target = SET_DEST (dep_rtx);
5332 if (GET_CODE (target) == STRICT_LOW_PART)
5333 target = XEXP (target, 0);
5334 while (GET_CODE (target) == SUBREG)
5335 target = SUBREG_REG (target);
5336
5337 if (GET_CODE (target) == REG)
5338 {
5339 int regno = REGNO (target);
5340
5341 if (s390_safe_attr_type (insn) == TYPE_LA)
5342 {
5343 pat = PATTERN (insn);
5344 if (GET_CODE (pat) == PARALLEL)
5345 {
5346 gcc_assert (XVECLEN (pat, 0) == 2);
5347 pat = XVECEXP (pat, 0, 0);
5348 }
5349 gcc_assert (GET_CODE (pat) == SET);
5350 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5351 }
5352 else if (get_attr_atype (insn) == ATYPE_AGEN)
5353 return reg_used_in_mem_p (regno, PATTERN (insn));
5354 }
5355 }
5356 return false;
5357 }
5358
5359 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5360
5361 int
5362 s390_agen_dep_p (rtx dep_insn, rtx insn)
5363 {
5364 rtx dep_rtx = PATTERN (dep_insn);
5365 int i;
5366
5367 if (GET_CODE (dep_rtx) == SET
5368 && addr_generation_dependency_p (dep_rtx, insn))
5369 return 1;
5370 else if (GET_CODE (dep_rtx) == PARALLEL)
5371 {
5372 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5373 {
5374 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5375 return 1;
5376 }
5377 }
5378 return 0;
5379 }
5380
5381
5382 /* A C statement (sans semicolon) to update the integer scheduling priority
5383 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5384 reduce the priority to execute INSN later. Do not define this macro if
5385 you do not need to adjust the scheduling priorities of insns.
5386
5387 A STD instruction should be scheduled earlier,
5388 in order to use the bypass. */
5389
5390
5391 static int
5392 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5393 {
5394 if (! INSN_P (insn))
5395 return priority;
5396
5397 if (s390_tune != PROCESSOR_2084_Z990
5398 && s390_tune != PROCESSOR_2094_Z9_109
5399 && s390_tune != PROCESSOR_2097_Z10)
5400 return priority;
5401
5402 switch (s390_safe_attr_type (insn))
5403 {
5404 case TYPE_FSTOREDF:
5405 case TYPE_FSTORESF:
5406 priority = priority << 3;
5407 break;
5408 case TYPE_STORE:
5409 case TYPE_STM:
5410 priority = priority << 1;
5411 break;
5412 default:
5413 break;
5414 }
5415 return priority;
5416 }
5417
5418
5419 /* The number of instructions that can be issued per cycle. */
5420
5421 static int
5422 s390_issue_rate (void)
5423 {
5424 switch (s390_tune)
5425 {
5426 case PROCESSOR_2084_Z990:
5427 case PROCESSOR_2094_Z9_109:
5428 return 3;
5429 case PROCESSOR_2097_Z10:
5430 return 2;
5431 default:
5432 return 1;
5433 }
5434 }
5435
5436 static int
5437 s390_first_cycle_multipass_dfa_lookahead (void)
5438 {
5439 return 4;
5440 }
5441
5442 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5443 Fix up MEMs as required. */
5444
5445 static void
5446 annotate_constant_pool_refs (rtx *x)
5447 {
5448 int i, j;
5449 const char *fmt;
5450
5451 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5452 || !CONSTANT_POOL_ADDRESS_P (*x));
5453
5454 /* Literal pool references can only occur inside a MEM ... */
5455 if (GET_CODE (*x) == MEM)
5456 {
5457 rtx memref = XEXP (*x, 0);
5458
5459 if (GET_CODE (memref) == SYMBOL_REF
5460 && CONSTANT_POOL_ADDRESS_P (memref))
5461 {
5462 rtx base = cfun->machine->base_reg;
5463 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5464 UNSPEC_LTREF);
5465
5466 *x = replace_equiv_address (*x, addr);
5467 return;
5468 }
5469
5470 if (GET_CODE (memref) == CONST
5471 && GET_CODE (XEXP (memref, 0)) == PLUS
5472 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5473 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5474 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5475 {
5476 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5477 rtx sym = XEXP (XEXP (memref, 0), 0);
5478 rtx base = cfun->machine->base_reg;
5479 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5480 UNSPEC_LTREF);
5481
5482 *x = replace_equiv_address (*x, plus_constant (addr, off));
5483 return;
5484 }
5485 }
5486
5487 /* ... or a load-address type pattern. */
5488 if (GET_CODE (*x) == SET)
5489 {
5490 rtx addrref = SET_SRC (*x);
5491
5492 if (GET_CODE (addrref) == SYMBOL_REF
5493 && CONSTANT_POOL_ADDRESS_P (addrref))
5494 {
5495 rtx base = cfun->machine->base_reg;
5496 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5497 UNSPEC_LTREF);
5498
5499 SET_SRC (*x) = addr;
5500 return;
5501 }
5502
5503 if (GET_CODE (addrref) == CONST
5504 && GET_CODE (XEXP (addrref, 0)) == PLUS
5505 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5506 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5507 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5508 {
5509 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5510 rtx sym = XEXP (XEXP (addrref, 0), 0);
5511 rtx base = cfun->machine->base_reg;
5512 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5513 UNSPEC_LTREF);
5514
5515 SET_SRC (*x) = plus_constant (addr, off);
5516 return;
5517 }
5518 }
5519
5520 /* Annotate LTREL_BASE as well. */
5521 if (GET_CODE (*x) == UNSPEC
5522 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5523 {
5524 rtx base = cfun->machine->base_reg;
5525 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5526 UNSPEC_LTREL_BASE);
5527 return;
5528 }
5529
5530 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5531 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5532 {
5533 if (fmt[i] == 'e')
5534 {
5535 annotate_constant_pool_refs (&XEXP (*x, i));
5536 }
5537 else if (fmt[i] == 'E')
5538 {
5539 for (j = 0; j < XVECLEN (*x, i); j++)
5540 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5541 }
5542 }
5543 }
5544
5545 /* Split all branches that exceed the maximum distance.
5546 Returns true if this created a new literal pool entry. */
5547
5548 static int
5549 s390_split_branches (void)
5550 {
5551 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5552 int new_literal = 0, ret;
5553 rtx insn, pat, tmp, target;
5554 rtx *label;
5555
5556 /* We need correct insn addresses. */
5557
5558 shorten_branches (get_insns ());
5559
5560 /* Find all branches that exceed 64KB, and split them. */
5561
5562 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5563 {
5564 if (GET_CODE (insn) != JUMP_INSN)
5565 continue;
5566
5567 pat = PATTERN (insn);
5568 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5569 pat = XVECEXP (pat, 0, 0);
5570 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5571 continue;
5572
5573 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5574 {
5575 label = &SET_SRC (pat);
5576 }
5577 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5578 {
5579 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5580 label = &XEXP (SET_SRC (pat), 1);
5581 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5582 label = &XEXP (SET_SRC (pat), 2);
5583 else
5584 continue;
5585 }
5586 else
5587 continue;
5588
5589 if (get_attr_length (insn) <= 4)
5590 continue;
5591
5592 /* We are going to use the return register as scratch register,
5593 make sure it will be saved/restored by the prologue/epilogue. */
5594 cfun_frame_layout.save_return_addr_p = 1;
5595
5596 if (!flag_pic)
5597 {
5598 new_literal = 1;
5599 tmp = force_const_mem (Pmode, *label);
5600 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5601 INSN_ADDRESSES_NEW (tmp, -1);
5602 annotate_constant_pool_refs (&PATTERN (tmp));
5603
5604 target = temp_reg;
5605 }
5606 else
5607 {
5608 new_literal = 1;
5609 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5610 UNSPEC_LTREL_OFFSET);
5611 target = gen_rtx_CONST (Pmode, target);
5612 target = force_const_mem (Pmode, target);
5613 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5614 INSN_ADDRESSES_NEW (tmp, -1);
5615 annotate_constant_pool_refs (&PATTERN (tmp));
5616
5617 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5618 cfun->machine->base_reg),
5619 UNSPEC_LTREL_BASE);
5620 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5621 }
5622
5623 ret = validate_change (insn, label, target, 0);
5624 gcc_assert (ret);
5625 }
5626
5627 return new_literal;
5628 }
5629
5630
5631 /* Find an annotated literal pool symbol referenced in RTX X,
5632 and store it at REF. Will abort if X contains references to
5633 more than one such pool symbol; multiple references to the same
5634 symbol are allowed, however.
5635
5636 The rtx pointed to by REF must be initialized to NULL_RTX
5637 by the caller before calling this routine. */
5638
5639 static void
5640 find_constant_pool_ref (rtx x, rtx *ref)
5641 {
5642 int i, j;
5643 const char *fmt;
5644
5645 /* Ignore LTREL_BASE references. */
5646 if (GET_CODE (x) == UNSPEC
5647 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5648 return;
5649 /* Likewise POOL_ENTRY insns. */
5650 if (GET_CODE (x) == UNSPEC_VOLATILE
5651 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5652 return;
5653
5654 gcc_assert (GET_CODE (x) != SYMBOL_REF
5655 || !CONSTANT_POOL_ADDRESS_P (x));
5656
5657 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5658 {
5659 rtx sym = XVECEXP (x, 0, 0);
5660 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5661 && CONSTANT_POOL_ADDRESS_P (sym));
5662
5663 if (*ref == NULL_RTX)
5664 *ref = sym;
5665 else
5666 gcc_assert (*ref == sym);
5667
5668 return;
5669 }
5670
5671 fmt = GET_RTX_FORMAT (GET_CODE (x));
5672 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5673 {
5674 if (fmt[i] == 'e')
5675 {
5676 find_constant_pool_ref (XEXP (x, i), ref);
5677 }
5678 else if (fmt[i] == 'E')
5679 {
5680 for (j = 0; j < XVECLEN (x, i); j++)
5681 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5682 }
5683 }
5684 }
5685
5686 /* Replace every reference to the annotated literal pool
5687 symbol REF in X by its base plus OFFSET. */
5688
5689 static void
5690 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5691 {
5692 int i, j;
5693 const char *fmt;
5694
5695 gcc_assert (*x != ref);
5696
5697 if (GET_CODE (*x) == UNSPEC
5698 && XINT (*x, 1) == UNSPEC_LTREF
5699 && XVECEXP (*x, 0, 0) == ref)
5700 {
5701 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5702 return;
5703 }
5704
5705 if (GET_CODE (*x) == PLUS
5706 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5707 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5708 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5709 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5710 {
5711 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5712 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5713 return;
5714 }
5715
5716 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5717 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5718 {
5719 if (fmt[i] == 'e')
5720 {
5721 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5722 }
5723 else if (fmt[i] == 'E')
5724 {
5725 for (j = 0; j < XVECLEN (*x, i); j++)
5726 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5727 }
5728 }
5729 }
5730
5731 /* Check whether X contains an UNSPEC_LTREL_BASE.
5732 Return its constant pool symbol if found, NULL_RTX otherwise. */
5733
5734 static rtx
5735 find_ltrel_base (rtx x)
5736 {
5737 int i, j;
5738 const char *fmt;
5739
5740 if (GET_CODE (x) == UNSPEC
5741 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5742 return XVECEXP (x, 0, 0);
5743
5744 fmt = GET_RTX_FORMAT (GET_CODE (x));
5745 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5746 {
5747 if (fmt[i] == 'e')
5748 {
5749 rtx fnd = find_ltrel_base (XEXP (x, i));
5750 if (fnd)
5751 return fnd;
5752 }
5753 else if (fmt[i] == 'E')
5754 {
5755 for (j = 0; j < XVECLEN (x, i); j++)
5756 {
5757 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5758 if (fnd)
5759 return fnd;
5760 }
5761 }
5762 }
5763
5764 return NULL_RTX;
5765 }
5766
5767 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5768
5769 static void
5770 replace_ltrel_base (rtx *x)
5771 {
5772 int i, j;
5773 const char *fmt;
5774
5775 if (GET_CODE (*x) == UNSPEC
5776 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5777 {
5778 *x = XVECEXP (*x, 0, 1);
5779 return;
5780 }
5781
5782 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5783 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5784 {
5785 if (fmt[i] == 'e')
5786 {
5787 replace_ltrel_base (&XEXP (*x, i));
5788 }
5789 else if (fmt[i] == 'E')
5790 {
5791 for (j = 0; j < XVECLEN (*x, i); j++)
5792 replace_ltrel_base (&XVECEXP (*x, i, j));
5793 }
5794 }
5795 }
5796
5797
5798 /* We keep a list of constants which we have to add to internal
5799 constant tables in the middle of large functions. */
5800
5801 #define NR_C_MODES 11
5802 enum machine_mode constant_modes[NR_C_MODES] =
5803 {
5804 TFmode, TImode, TDmode,
5805 DFmode, DImode, DDmode,
5806 SFmode, SImode, SDmode,
5807 HImode,
5808 QImode
5809 };
5810
5811 struct constant
5812 {
5813 struct constant *next;
5814 rtx value;
5815 rtx label;
5816 };
5817
5818 struct constant_pool
5819 {
5820 struct constant_pool *next;
5821 rtx first_insn;
5822 rtx pool_insn;
5823 bitmap insns;
5824 rtx emit_pool_after;
5825
5826 struct constant *constants[NR_C_MODES];
5827 struct constant *execute;
5828 rtx label;
5829 int size;
5830 };
5831
5832 /* Allocate new constant_pool structure. */
5833
5834 static struct constant_pool *
5835 s390_alloc_pool (void)
5836 {
5837 struct constant_pool *pool;
5838 int i;
5839
5840 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5841 pool->next = NULL;
5842 for (i = 0; i < NR_C_MODES; i++)
5843 pool->constants[i] = NULL;
5844
5845 pool->execute = NULL;
5846 pool->label = gen_label_rtx ();
5847 pool->first_insn = NULL_RTX;
5848 pool->pool_insn = NULL_RTX;
5849 pool->insns = BITMAP_ALLOC (NULL);
5850 pool->size = 0;
5851 pool->emit_pool_after = NULL_RTX;
5852
5853 return pool;
5854 }
5855
5856 /* Create new constant pool covering instructions starting at INSN
5857 and chain it to the end of POOL_LIST. */
5858
5859 static struct constant_pool *
5860 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5861 {
5862 struct constant_pool *pool, **prev;
5863
5864 pool = s390_alloc_pool ();
5865 pool->first_insn = insn;
5866
5867 for (prev = pool_list; *prev; prev = &(*prev)->next)
5868 ;
5869 *prev = pool;
5870
5871 return pool;
5872 }
5873
5874 /* End range of instructions covered by POOL at INSN and emit
5875 placeholder insn representing the pool. */
5876
5877 static void
5878 s390_end_pool (struct constant_pool *pool, rtx insn)
5879 {
5880 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5881
5882 if (!insn)
5883 insn = get_last_insn ();
5884
5885 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5886 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5887 }
5888
5889 /* Add INSN to the list of insns covered by POOL. */
5890
5891 static void
5892 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5893 {
5894 bitmap_set_bit (pool->insns, INSN_UID (insn));
5895 }
5896
5897 /* Return pool out of POOL_LIST that covers INSN. */
5898
5899 static struct constant_pool *
5900 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5901 {
5902 struct constant_pool *pool;
5903
5904 for (pool = pool_list; pool; pool = pool->next)
5905 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5906 break;
5907
5908 return pool;
5909 }
5910
5911 /* Add constant VAL of mode MODE to the constant pool POOL. */
5912
5913 static void
5914 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5915 {
5916 struct constant *c;
5917 int i;
5918
5919 for (i = 0; i < NR_C_MODES; i++)
5920 if (constant_modes[i] == mode)
5921 break;
5922 gcc_assert (i != NR_C_MODES);
5923
5924 for (c = pool->constants[i]; c != NULL; c = c->next)
5925 if (rtx_equal_p (val, c->value))
5926 break;
5927
5928 if (c == NULL)
5929 {
5930 c = (struct constant *) xmalloc (sizeof *c);
5931 c->value = val;
5932 c->label = gen_label_rtx ();
5933 c->next = pool->constants[i];
5934 pool->constants[i] = c;
5935 pool->size += GET_MODE_SIZE (mode);
5936 }
5937 }
5938
5939 /* Return an rtx that represents the offset of X from the start of
5940 pool POOL. */
5941
5942 static rtx
5943 s390_pool_offset (struct constant_pool *pool, rtx x)
5944 {
5945 rtx label;
5946
5947 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5948 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5949 UNSPEC_POOL_OFFSET);
5950 return gen_rtx_CONST (GET_MODE (x), x);
5951 }
5952
5953 /* Find constant VAL of mode MODE in the constant pool POOL.
5954 Return an RTX describing the distance from the start of
5955 the pool to the location of the new constant. */
5956
5957 static rtx
5958 s390_find_constant (struct constant_pool *pool, rtx val,
5959 enum machine_mode mode)
5960 {
5961 struct constant *c;
5962 int i;
5963
5964 for (i = 0; i < NR_C_MODES; i++)
5965 if (constant_modes[i] == mode)
5966 break;
5967 gcc_assert (i != NR_C_MODES);
5968
5969 for (c = pool->constants[i]; c != NULL; c = c->next)
5970 if (rtx_equal_p (val, c->value))
5971 break;
5972
5973 gcc_assert (c);
5974
5975 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5976 }
5977
5978 /* Check whether INSN is an execute. Return the label_ref to its
5979 execute target template if so, NULL_RTX otherwise. */
5980
5981 static rtx
5982 s390_execute_label (rtx insn)
5983 {
5984 if (GET_CODE (insn) == INSN
5985 && GET_CODE (PATTERN (insn)) == PARALLEL
5986 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5987 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5988 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5989
5990 return NULL_RTX;
5991 }
5992
5993 /* Add execute target for INSN to the constant pool POOL. */
5994
5995 static void
5996 s390_add_execute (struct constant_pool *pool, rtx insn)
5997 {
5998 struct constant *c;
5999
6000 for (c = pool->execute; c != NULL; c = c->next)
6001 if (INSN_UID (insn) == INSN_UID (c->value))
6002 break;
6003
6004 if (c == NULL)
6005 {
6006 c = (struct constant *) xmalloc (sizeof *c);
6007 c->value = insn;
6008 c->label = gen_label_rtx ();
6009 c->next = pool->execute;
6010 pool->execute = c;
6011 pool->size += 6;
6012 }
6013 }
6014
6015 /* Find execute target for INSN in the constant pool POOL.
6016 Return an RTX describing the distance from the start of
6017 the pool to the location of the execute target. */
6018
6019 static rtx
6020 s390_find_execute (struct constant_pool *pool, rtx insn)
6021 {
6022 struct constant *c;
6023
6024 for (c = pool->execute; c != NULL; c = c->next)
6025 if (INSN_UID (insn) == INSN_UID (c->value))
6026 break;
6027
6028 gcc_assert (c);
6029
6030 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6031 }
6032
6033 /* For an execute INSN, extract the execute target template. */
6034
6035 static rtx
6036 s390_execute_target (rtx insn)
6037 {
6038 rtx pattern = PATTERN (insn);
6039 gcc_assert (s390_execute_label (insn));
6040
6041 if (XVECLEN (pattern, 0) == 2)
6042 {
6043 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6044 }
6045 else
6046 {
6047 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6048 int i;
6049
6050 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6051 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6052
6053 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6054 }
6055
6056 return pattern;
6057 }
6058
6059 /* Indicate that INSN cannot be duplicated. This is the case for
6060 execute insns that carry a unique label. */
6061
6062 static bool
6063 s390_cannot_copy_insn_p (rtx insn)
6064 {
6065 rtx label = s390_execute_label (insn);
6066 return label && label != const0_rtx;
6067 }
6068
6069 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6070 do not emit the pool base label. */
6071
6072 static void
6073 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6074 {
6075 struct constant *c;
6076 rtx insn = pool->pool_insn;
6077 int i;
6078
6079 /* Switch to rodata section. */
6080 if (TARGET_CPU_ZARCH)
6081 {
6082 insn = emit_insn_after (gen_pool_section_start (), insn);
6083 INSN_ADDRESSES_NEW (insn, -1);
6084 }
6085
6086 /* Ensure minimum pool alignment. */
6087 if (TARGET_CPU_ZARCH)
6088 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6089 else
6090 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6091 INSN_ADDRESSES_NEW (insn, -1);
6092
6093 /* Emit pool base label. */
6094 if (!remote_label)
6095 {
6096 insn = emit_label_after (pool->label, insn);
6097 INSN_ADDRESSES_NEW (insn, -1);
6098 }
6099
6100 /* Dump constants in descending alignment requirement order,
6101 ensuring proper alignment for every constant. */
6102 for (i = 0; i < NR_C_MODES; i++)
6103 for (c = pool->constants[i]; c; c = c->next)
6104 {
6105 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6106 rtx value = copy_rtx (c->value);
6107 if (GET_CODE (value) == CONST
6108 && GET_CODE (XEXP (value, 0)) == UNSPEC
6109 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6110 && XVECLEN (XEXP (value, 0), 0) == 1)
6111 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6112
6113 insn = emit_label_after (c->label, insn);
6114 INSN_ADDRESSES_NEW (insn, -1);
6115
6116 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6117 gen_rtvec (1, value),
6118 UNSPECV_POOL_ENTRY);
6119 insn = emit_insn_after (value, insn);
6120 INSN_ADDRESSES_NEW (insn, -1);
6121 }
6122
6123 /* Ensure minimum alignment for instructions. */
6124 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6125 INSN_ADDRESSES_NEW (insn, -1);
6126
6127 /* Output in-pool execute template insns. */
6128 for (c = pool->execute; c; c = c->next)
6129 {
6130 insn = emit_label_after (c->label, insn);
6131 INSN_ADDRESSES_NEW (insn, -1);
6132
6133 insn = emit_insn_after (s390_execute_target (c->value), insn);
6134 INSN_ADDRESSES_NEW (insn, -1);
6135 }
6136
6137 /* Switch back to previous section. */
6138 if (TARGET_CPU_ZARCH)
6139 {
6140 insn = emit_insn_after (gen_pool_section_end (), insn);
6141 INSN_ADDRESSES_NEW (insn, -1);
6142 }
6143
6144 insn = emit_barrier_after (insn);
6145 INSN_ADDRESSES_NEW (insn, -1);
6146
6147 /* Remove placeholder insn. */
6148 remove_insn (pool->pool_insn);
6149 }
6150
6151 /* Free all memory used by POOL. */
6152
6153 static void
6154 s390_free_pool (struct constant_pool *pool)
6155 {
6156 struct constant *c, *next;
6157 int i;
6158
6159 for (i = 0; i < NR_C_MODES; i++)
6160 for (c = pool->constants[i]; c; c = next)
6161 {
6162 next = c->next;
6163 free (c);
6164 }
6165
6166 for (c = pool->execute; c; c = next)
6167 {
6168 next = c->next;
6169 free (c);
6170 }
6171
6172 BITMAP_FREE (pool->insns);
6173 free (pool);
6174 }
6175
6176
6177 /* Collect main literal pool. Return NULL on overflow. */
6178
6179 static struct constant_pool *
6180 s390_mainpool_start (void)
6181 {
6182 struct constant_pool *pool;
6183 rtx insn;
6184
6185 pool = s390_alloc_pool ();
6186
6187 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6188 {
6189 if (GET_CODE (insn) == INSN
6190 && GET_CODE (PATTERN (insn)) == SET
6191 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6192 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6193 {
6194 gcc_assert (!pool->pool_insn);
6195 pool->pool_insn = insn;
6196 }
6197
6198 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6199 {
6200 s390_add_execute (pool, insn);
6201 }
6202 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6203 {
6204 rtx pool_ref = NULL_RTX;
6205 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6206 if (pool_ref)
6207 {
6208 rtx constant = get_pool_constant (pool_ref);
6209 enum machine_mode mode = get_pool_mode (pool_ref);
6210 s390_add_constant (pool, constant, mode);
6211 }
6212 }
6213
6214 /* If hot/cold partitioning is enabled we have to make sure that
6215 the literal pool is emitted in the same section where the
6216 initialization of the literal pool base pointer takes place.
6217 emit_pool_after is only used in the non-overflow case on non
6218 Z cpus where we can emit the literal pool at the end of the
6219 function body within the text section. */
6220 if (NOTE_P (insn)
6221 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6222 && !pool->emit_pool_after)
6223 pool->emit_pool_after = PREV_INSN (insn);
6224 }
6225
6226 gcc_assert (pool->pool_insn || pool->size == 0);
6227
6228 if (pool->size >= 4096)
6229 {
6230 /* We're going to chunkify the pool, so remove the main
6231 pool placeholder insn. */
6232 remove_insn (pool->pool_insn);
6233
6234 s390_free_pool (pool);
6235 pool = NULL;
6236 }
6237
6238 /* If the functions ends with the section where the literal pool
6239 should be emitted set the marker to its end. */
6240 if (pool && !pool->emit_pool_after)
6241 pool->emit_pool_after = get_last_insn ();
6242
6243 return pool;
6244 }
6245
6246 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6247 Modify the current function to output the pool constants as well as
6248 the pool register setup instruction. */
6249
6250 static void
6251 s390_mainpool_finish (struct constant_pool *pool)
6252 {
6253 rtx base_reg = cfun->machine->base_reg;
6254 rtx insn;
6255
6256 /* If the pool is empty, we're done. */
6257 if (pool->size == 0)
6258 {
6259 /* We don't actually need a base register after all. */
6260 cfun->machine->base_reg = NULL_RTX;
6261
6262 if (pool->pool_insn)
6263 remove_insn (pool->pool_insn);
6264 s390_free_pool (pool);
6265 return;
6266 }
6267
6268 /* We need correct insn addresses. */
6269 shorten_branches (get_insns ());
6270
6271 /* On zSeries, we use a LARL to load the pool register. The pool is
6272 located in the .rodata section, so we emit it after the function. */
6273 if (TARGET_CPU_ZARCH)
6274 {
6275 insn = gen_main_base_64 (base_reg, pool->label);
6276 insn = emit_insn_after (insn, pool->pool_insn);
6277 INSN_ADDRESSES_NEW (insn, -1);
6278 remove_insn (pool->pool_insn);
6279
6280 insn = get_last_insn ();
6281 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6282 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6283
6284 s390_dump_pool (pool, 0);
6285 }
6286
6287 /* On S/390, if the total size of the function's code plus literal pool
6288 does not exceed 4096 bytes, we use BASR to set up a function base
6289 pointer, and emit the literal pool at the end of the function. */
6290 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6291 + pool->size + 8 /* alignment slop */ < 4096)
6292 {
6293 insn = gen_main_base_31_small (base_reg, pool->label);
6294 insn = emit_insn_after (insn, pool->pool_insn);
6295 INSN_ADDRESSES_NEW (insn, -1);
6296 remove_insn (pool->pool_insn);
6297
6298 insn = emit_label_after (pool->label, insn);
6299 INSN_ADDRESSES_NEW (insn, -1);
6300
6301 /* emit_pool_after will be set by s390_mainpool_start to the
6302 last insn of the section where the literal pool should be
6303 emitted. */
6304 insn = pool->emit_pool_after;
6305
6306 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6307 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6308
6309 s390_dump_pool (pool, 1);
6310 }
6311
6312 /* Otherwise, we emit an inline literal pool and use BASR to branch
6313 over it, setting up the pool register at the same time. */
6314 else
6315 {
6316 rtx pool_end = gen_label_rtx ();
6317
6318 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6319 insn = emit_insn_after (insn, pool->pool_insn);
6320 INSN_ADDRESSES_NEW (insn, -1);
6321 remove_insn (pool->pool_insn);
6322
6323 insn = emit_label_after (pool->label, insn);
6324 INSN_ADDRESSES_NEW (insn, -1);
6325
6326 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6327 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6328
6329 insn = emit_label_after (pool_end, pool->pool_insn);
6330 INSN_ADDRESSES_NEW (insn, -1);
6331
6332 s390_dump_pool (pool, 1);
6333 }
6334
6335
6336 /* Replace all literal pool references. */
6337
6338 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6339 {
6340 if (INSN_P (insn))
6341 replace_ltrel_base (&PATTERN (insn));
6342
6343 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6344 {
6345 rtx addr, pool_ref = NULL_RTX;
6346 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6347 if (pool_ref)
6348 {
6349 if (s390_execute_label (insn))
6350 addr = s390_find_execute (pool, insn);
6351 else
6352 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6353 get_pool_mode (pool_ref));
6354
6355 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6356 INSN_CODE (insn) = -1;
6357 }
6358 }
6359 }
6360
6361
6362 /* Free the pool. */
6363 s390_free_pool (pool);
6364 }
6365
6366 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6367 We have decided we cannot use this pool, so revert all changes
6368 to the current function that were done by s390_mainpool_start. */
6369 static void
6370 s390_mainpool_cancel (struct constant_pool *pool)
6371 {
6372 /* We didn't actually change the instruction stream, so simply
6373 free the pool memory. */
6374 s390_free_pool (pool);
6375 }
6376
6377
6378 /* Chunkify the literal pool. */
6379
6380 #define S390_POOL_CHUNK_MIN 0xc00
6381 #define S390_POOL_CHUNK_MAX 0xe00
6382
6383 static struct constant_pool *
6384 s390_chunkify_start (void)
6385 {
6386 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6387 int extra_size = 0;
6388 bitmap far_labels;
6389 rtx pending_ltrel = NULL_RTX;
6390 rtx insn;
6391
6392 rtx (*gen_reload_base) (rtx, rtx) =
6393 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6394
6395
6396 /* We need correct insn addresses. */
6397
6398 shorten_branches (get_insns ());
6399
6400 /* Scan all insns and move literals to pool chunks. */
6401
6402 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6403 {
6404 bool section_switch_p = false;
6405
6406 /* Check for pending LTREL_BASE. */
6407 if (INSN_P (insn))
6408 {
6409 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6410 if (ltrel_base)
6411 {
6412 gcc_assert (ltrel_base == pending_ltrel);
6413 pending_ltrel = NULL_RTX;
6414 }
6415 }
6416
6417 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6418 {
6419 if (!curr_pool)
6420 curr_pool = s390_start_pool (&pool_list, insn);
6421
6422 s390_add_execute (curr_pool, insn);
6423 s390_add_pool_insn (curr_pool, insn);
6424 }
6425 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6426 {
6427 rtx pool_ref = NULL_RTX;
6428 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6429 if (pool_ref)
6430 {
6431 rtx constant = get_pool_constant (pool_ref);
6432 enum machine_mode mode = get_pool_mode (pool_ref);
6433
6434 if (!curr_pool)
6435 curr_pool = s390_start_pool (&pool_list, insn);
6436
6437 s390_add_constant (curr_pool, constant, mode);
6438 s390_add_pool_insn (curr_pool, insn);
6439
6440 /* Don't split the pool chunk between a LTREL_OFFSET load
6441 and the corresponding LTREL_BASE. */
6442 if (GET_CODE (constant) == CONST
6443 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6444 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6445 {
6446 gcc_assert (!pending_ltrel);
6447 pending_ltrel = pool_ref;
6448 }
6449 }
6450 }
6451
6452 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6453 {
6454 if (curr_pool)
6455 s390_add_pool_insn (curr_pool, insn);
6456 /* An LTREL_BASE must follow within the same basic block. */
6457 gcc_assert (!pending_ltrel);
6458 }
6459
6460 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6461 section_switch_p = true;
6462
6463 if (!curr_pool
6464 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6465 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6466 continue;
6467
6468 if (TARGET_CPU_ZARCH)
6469 {
6470 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6471 continue;
6472
6473 s390_end_pool (curr_pool, NULL_RTX);
6474 curr_pool = NULL;
6475 }
6476 else
6477 {
6478 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6479 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6480 + extra_size;
6481
6482 /* We will later have to insert base register reload insns.
6483 Those will have an effect on code size, which we need to
6484 consider here. This calculation makes rather pessimistic
6485 worst-case assumptions. */
6486 if (GET_CODE (insn) == CODE_LABEL)
6487 extra_size += 6;
6488
6489 if (chunk_size < S390_POOL_CHUNK_MIN
6490 && curr_pool->size < S390_POOL_CHUNK_MIN
6491 && !section_switch_p)
6492 continue;
6493
6494 /* Pool chunks can only be inserted after BARRIERs ... */
6495 if (GET_CODE (insn) == BARRIER)
6496 {
6497 s390_end_pool (curr_pool, insn);
6498 curr_pool = NULL;
6499 extra_size = 0;
6500 }
6501
6502 /* ... so if we don't find one in time, create one. */
6503 else if (chunk_size > S390_POOL_CHUNK_MAX
6504 || curr_pool->size > S390_POOL_CHUNK_MAX
6505 || section_switch_p)
6506 {
6507 rtx label, jump, barrier;
6508
6509 if (!section_switch_p)
6510 {
6511 /* We can insert the barrier only after a 'real' insn. */
6512 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6513 continue;
6514 if (get_attr_length (insn) == 0)
6515 continue;
6516 /* Don't separate LTREL_BASE from the corresponding
6517 LTREL_OFFSET load. */
6518 if (pending_ltrel)
6519 continue;
6520 }
6521 else
6522 {
6523 gcc_assert (!pending_ltrel);
6524
6525 /* The old pool has to end before the section switch
6526 note in order to make it part of the current
6527 section. */
6528 insn = PREV_INSN (insn);
6529 }
6530
6531 label = gen_label_rtx ();
6532 jump = emit_jump_insn_after (gen_jump (label), insn);
6533 barrier = emit_barrier_after (jump);
6534 insn = emit_label_after (label, barrier);
6535 JUMP_LABEL (jump) = label;
6536 LABEL_NUSES (label) = 1;
6537
6538 INSN_ADDRESSES_NEW (jump, -1);
6539 INSN_ADDRESSES_NEW (barrier, -1);
6540 INSN_ADDRESSES_NEW (insn, -1);
6541
6542 s390_end_pool (curr_pool, barrier);
6543 curr_pool = NULL;
6544 extra_size = 0;
6545 }
6546 }
6547 }
6548
6549 if (curr_pool)
6550 s390_end_pool (curr_pool, NULL_RTX);
6551 gcc_assert (!pending_ltrel);
6552
6553 /* Find all labels that are branched into
6554 from an insn belonging to a different chunk. */
6555
6556 far_labels = BITMAP_ALLOC (NULL);
6557
6558 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6559 {
6560 /* Labels marked with LABEL_PRESERVE_P can be target
6561 of non-local jumps, so we have to mark them.
6562 The same holds for named labels.
6563
6564 Don't do that, however, if it is the label before
6565 a jump table. */
6566
6567 if (GET_CODE (insn) == CODE_LABEL
6568 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6569 {
6570 rtx vec_insn = next_real_insn (insn);
6571 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6572 PATTERN (vec_insn) : NULL_RTX;
6573 if (!vec_pat
6574 || !(GET_CODE (vec_pat) == ADDR_VEC
6575 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6576 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6577 }
6578
6579 /* If we have a direct jump (conditional or unconditional)
6580 or a casesi jump, check all potential targets. */
6581 else if (GET_CODE (insn) == JUMP_INSN)
6582 {
6583 rtx pat = PATTERN (insn);
6584 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6585 pat = XVECEXP (pat, 0, 0);
6586
6587 if (GET_CODE (pat) == SET)
6588 {
6589 rtx label = JUMP_LABEL (insn);
6590 if (label)
6591 {
6592 if (s390_find_pool (pool_list, label)
6593 != s390_find_pool (pool_list, insn))
6594 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6595 }
6596 }
6597 else if (GET_CODE (pat) == PARALLEL
6598 && XVECLEN (pat, 0) == 2
6599 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6600 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6601 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6602 {
6603 /* Find the jump table used by this casesi jump. */
6604 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6605 rtx vec_insn = next_real_insn (vec_label);
6606 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6607 PATTERN (vec_insn) : NULL_RTX;
6608 if (vec_pat
6609 && (GET_CODE (vec_pat) == ADDR_VEC
6610 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6611 {
6612 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6613
6614 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6615 {
6616 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6617
6618 if (s390_find_pool (pool_list, label)
6619 != s390_find_pool (pool_list, insn))
6620 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6621 }
6622 }
6623 }
6624 }
6625 }
6626
6627 /* Insert base register reload insns before every pool. */
6628
6629 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6630 {
6631 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6632 curr_pool->label);
6633 rtx insn = curr_pool->first_insn;
6634 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6635 }
6636
6637 /* Insert base register reload insns at every far label. */
6638
6639 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6640 if (GET_CODE (insn) == CODE_LABEL
6641 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6642 {
6643 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6644 if (pool)
6645 {
6646 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6647 pool->label);
6648 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6649 }
6650 }
6651
6652
6653 BITMAP_FREE (far_labels);
6654
6655
6656 /* Recompute insn addresses. */
6657
6658 init_insn_lengths ();
6659 shorten_branches (get_insns ());
6660
6661 return pool_list;
6662 }
6663
6664 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6665 After we have decided to use this list, finish implementing
6666 all changes to the current function as required. */
6667
6668 static void
6669 s390_chunkify_finish (struct constant_pool *pool_list)
6670 {
6671 struct constant_pool *curr_pool = NULL;
6672 rtx insn;
6673
6674
6675 /* Replace all literal pool references. */
6676
6677 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6678 {
6679 if (INSN_P (insn))
6680 replace_ltrel_base (&PATTERN (insn));
6681
6682 curr_pool = s390_find_pool (pool_list, insn);
6683 if (!curr_pool)
6684 continue;
6685
6686 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6687 {
6688 rtx addr, pool_ref = NULL_RTX;
6689 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6690 if (pool_ref)
6691 {
6692 if (s390_execute_label (insn))
6693 addr = s390_find_execute (curr_pool, insn);
6694 else
6695 addr = s390_find_constant (curr_pool,
6696 get_pool_constant (pool_ref),
6697 get_pool_mode (pool_ref));
6698
6699 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6700 INSN_CODE (insn) = -1;
6701 }
6702 }
6703 }
6704
6705 /* Dump out all literal pools. */
6706
6707 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6708 s390_dump_pool (curr_pool, 0);
6709
6710 /* Free pool list. */
6711
6712 while (pool_list)
6713 {
6714 struct constant_pool *next = pool_list->next;
6715 s390_free_pool (pool_list);
6716 pool_list = next;
6717 }
6718 }
6719
6720 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6721 We have decided we cannot use this list, so revert all changes
6722 to the current function that were done by s390_chunkify_start. */
6723
6724 static void
6725 s390_chunkify_cancel (struct constant_pool *pool_list)
6726 {
6727 struct constant_pool *curr_pool = NULL;
6728 rtx insn;
6729
6730 /* Remove all pool placeholder insns. */
6731
6732 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6733 {
6734 /* Did we insert an extra barrier? Remove it. */
6735 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6736 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6737 rtx label = NEXT_INSN (curr_pool->pool_insn);
6738
6739 if (jump && GET_CODE (jump) == JUMP_INSN
6740 && barrier && GET_CODE (barrier) == BARRIER
6741 && label && GET_CODE (label) == CODE_LABEL
6742 && GET_CODE (PATTERN (jump)) == SET
6743 && SET_DEST (PATTERN (jump)) == pc_rtx
6744 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6745 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6746 {
6747 remove_insn (jump);
6748 remove_insn (barrier);
6749 remove_insn (label);
6750 }
6751
6752 remove_insn (curr_pool->pool_insn);
6753 }
6754
6755 /* Remove all base register reload insns. */
6756
6757 for (insn = get_insns (); insn; )
6758 {
6759 rtx next_insn = NEXT_INSN (insn);
6760
6761 if (GET_CODE (insn) == INSN
6762 && GET_CODE (PATTERN (insn)) == SET
6763 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6764 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6765 remove_insn (insn);
6766
6767 insn = next_insn;
6768 }
6769
6770 /* Free pool list. */
6771
6772 while (pool_list)
6773 {
6774 struct constant_pool *next = pool_list->next;
6775 s390_free_pool (pool_list);
6776 pool_list = next;
6777 }
6778 }
6779
6780 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6781
6782 void
6783 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6784 {
6785 REAL_VALUE_TYPE r;
6786
6787 switch (GET_MODE_CLASS (mode))
6788 {
6789 case MODE_FLOAT:
6790 case MODE_DECIMAL_FLOAT:
6791 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6792
6793 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6794 assemble_real (r, mode, align);
6795 break;
6796
6797 case MODE_INT:
6798 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6799 mark_symbol_refs_as_used (exp);
6800 break;
6801
6802 default:
6803 gcc_unreachable ();
6804 }
6805 }
6806
6807
6808 /* Return an RTL expression representing the value of the return address
6809 for the frame COUNT steps up from the current frame. FRAME is the
6810 frame pointer of that frame. */
6811
6812 rtx
6813 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6814 {
6815 int offset;
6816 rtx addr;
6817
6818 /* Without backchain, we fail for all but the current frame. */
6819
6820 if (!TARGET_BACKCHAIN && count > 0)
6821 return NULL_RTX;
6822
6823 /* For the current frame, we need to make sure the initial
6824 value of RETURN_REGNUM is actually saved. */
6825
6826 if (count == 0)
6827 {
6828 /* On non-z architectures branch splitting could overwrite r14. */
6829 if (TARGET_CPU_ZARCH)
6830 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6831 else
6832 {
6833 cfun_frame_layout.save_return_addr_p = true;
6834 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6835 }
6836 }
6837
6838 if (TARGET_PACKED_STACK)
6839 offset = -2 * UNITS_PER_LONG;
6840 else
6841 offset = RETURN_REGNUM * UNITS_PER_LONG;
6842
6843 addr = plus_constant (frame, offset);
6844 addr = memory_address (Pmode, addr);
6845 return gen_rtx_MEM (Pmode, addr);
6846 }
6847
6848 /* Return an RTL expression representing the back chain stored in
6849 the current stack frame. */
6850
6851 rtx
6852 s390_back_chain_rtx (void)
6853 {
6854 rtx chain;
6855
6856 gcc_assert (TARGET_BACKCHAIN);
6857
6858 if (TARGET_PACKED_STACK)
6859 chain = plus_constant (stack_pointer_rtx,
6860 STACK_POINTER_OFFSET - UNITS_PER_LONG);
6861 else
6862 chain = stack_pointer_rtx;
6863
6864 chain = gen_rtx_MEM (Pmode, chain);
6865 return chain;
6866 }
6867
6868 /* Find first call clobbered register unused in a function.
6869 This could be used as base register in a leaf function
6870 or for holding the return address before epilogue. */
6871
6872 static int
6873 find_unused_clobbered_reg (void)
6874 {
6875 int i;
6876 for (i = 0; i < 6; i++)
6877 if (!df_regs_ever_live_p (i))
6878 return i;
6879 return 0;
6880 }
6881
6882
6883 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6884 clobbered hard regs in SETREG. */
6885
6886 static void
6887 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6888 {
6889 int *regs_ever_clobbered = (int *)data;
6890 unsigned int i, regno;
6891 enum machine_mode mode = GET_MODE (setreg);
6892
6893 if (GET_CODE (setreg) == SUBREG)
6894 {
6895 rtx inner = SUBREG_REG (setreg);
6896 if (!GENERAL_REG_P (inner))
6897 return;
6898 regno = subreg_regno (setreg);
6899 }
6900 else if (GENERAL_REG_P (setreg))
6901 regno = REGNO (setreg);
6902 else
6903 return;
6904
6905 for (i = regno;
6906 i < regno + HARD_REGNO_NREGS (regno, mode);
6907 i++)
6908 regs_ever_clobbered[i] = 1;
6909 }
6910
6911 /* Walks through all basic blocks of the current function looking
6912 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6913 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6914 each of those regs. */
6915
6916 static void
6917 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6918 {
6919 basic_block cur_bb;
6920 rtx cur_insn;
6921 unsigned int i;
6922
6923 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6924
6925 /* For non-leaf functions we have to consider all call clobbered regs to be
6926 clobbered. */
6927 if (!current_function_is_leaf)
6928 {
6929 for (i = 0; i < 16; i++)
6930 regs_ever_clobbered[i] = call_really_used_regs[i];
6931 }
6932
6933 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6934 this work is done by liveness analysis (mark_regs_live_at_end).
6935 Special care is needed for functions containing landing pads. Landing pads
6936 may use the eh registers, but the code which sets these registers is not
6937 contained in that function. Hence s390_regs_ever_clobbered is not able to
6938 deal with this automatically. */
6939 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6940 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6941 if (crtl->calls_eh_return
6942 || (cfun->machine->has_landing_pad_p
6943 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6944 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6945
6946 /* For nonlocal gotos all call-saved registers have to be saved.
6947 This flag is also set for the unwinding code in libgcc.
6948 See expand_builtin_unwind_init. For regs_ever_live this is done by
6949 reload. */
6950 if (cfun->has_nonlocal_label)
6951 for (i = 0; i < 16; i++)
6952 if (!call_really_used_regs[i])
6953 regs_ever_clobbered[i] = 1;
6954
6955 FOR_EACH_BB (cur_bb)
6956 {
6957 FOR_BB_INSNS (cur_bb, cur_insn)
6958 {
6959 if (INSN_P (cur_insn))
6960 note_stores (PATTERN (cur_insn),
6961 s390_reg_clobbered_rtx,
6962 regs_ever_clobbered);
6963 }
6964 }
6965 }
6966
6967 /* Determine the frame area which actually has to be accessed
6968 in the function epilogue. The values are stored at the
6969 given pointers AREA_BOTTOM (address of the lowest used stack
6970 address) and AREA_TOP (address of the first item which does
6971 not belong to the stack frame). */
6972
6973 static void
6974 s390_frame_area (int *area_bottom, int *area_top)
6975 {
6976 int b, t;
6977 int i;
6978
6979 b = INT_MAX;
6980 t = INT_MIN;
6981
6982 if (cfun_frame_layout.first_restore_gpr != -1)
6983 {
6984 b = (cfun_frame_layout.gprs_offset
6985 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
6986 t = b + (cfun_frame_layout.last_restore_gpr
6987 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
6988 }
6989
6990 if (TARGET_64BIT && cfun_save_high_fprs_p)
6991 {
6992 b = MIN (b, cfun_frame_layout.f8_offset);
6993 t = MAX (t, (cfun_frame_layout.f8_offset
6994 + cfun_frame_layout.high_fprs * 8));
6995 }
6996
6997 if (!TARGET_64BIT)
6998 for (i = 2; i < 4; i++)
6999 if (cfun_fpr_bit_p (i))
7000 {
7001 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7002 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7003 }
7004
7005 *area_bottom = b;
7006 *area_top = t;
7007 }
7008
7009 /* Fill cfun->machine with info about register usage of current function.
7010 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7011
7012 static void
7013 s390_register_info (int clobbered_regs[])
7014 {
7015 int i, j;
7016
7017 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7018 cfun_frame_layout.fpr_bitmap = 0;
7019 cfun_frame_layout.high_fprs = 0;
7020 if (TARGET_64BIT)
7021 for (i = 24; i < 32; i++)
7022 if (df_regs_ever_live_p (i) && !global_regs[i])
7023 {
7024 cfun_set_fpr_bit (i - 16);
7025 cfun_frame_layout.high_fprs++;
7026 }
7027
7028 /* Find first and last gpr to be saved. We trust regs_ever_live
7029 data, except that we don't save and restore global registers.
7030
7031 Also, all registers with special meaning to the compiler need
7032 to be handled extra. */
7033
7034 s390_regs_ever_clobbered (clobbered_regs);
7035
7036 for (i = 0; i < 16; i++)
7037 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7038
7039 if (frame_pointer_needed)
7040 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7041
7042 if (flag_pic)
7043 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7044 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7045
7046 clobbered_regs[BASE_REGNUM]
7047 |= (cfun->machine->base_reg
7048 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7049
7050 clobbered_regs[RETURN_REGNUM]
7051 |= (!current_function_is_leaf
7052 || TARGET_TPF_PROFILING
7053 || cfun->machine->split_branches_pending_p
7054 || cfun_frame_layout.save_return_addr_p
7055 || crtl->calls_eh_return
7056 || cfun->stdarg);
7057
7058 clobbered_regs[STACK_POINTER_REGNUM]
7059 |= (!current_function_is_leaf
7060 || TARGET_TPF_PROFILING
7061 || cfun_save_high_fprs_p
7062 || get_frame_size () > 0
7063 || cfun->calls_alloca
7064 || cfun->stdarg);
7065
7066 for (i = 6; i < 16; i++)
7067 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7068 break;
7069 for (j = 15; j > i; j--)
7070 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7071 break;
7072
7073 if (i == 16)
7074 {
7075 /* Nothing to save/restore. */
7076 cfun_frame_layout.first_save_gpr_slot = -1;
7077 cfun_frame_layout.last_save_gpr_slot = -1;
7078 cfun_frame_layout.first_save_gpr = -1;
7079 cfun_frame_layout.first_restore_gpr = -1;
7080 cfun_frame_layout.last_save_gpr = -1;
7081 cfun_frame_layout.last_restore_gpr = -1;
7082 }
7083 else
7084 {
7085 /* Save slots for gprs from i to j. */
7086 cfun_frame_layout.first_save_gpr_slot = i;
7087 cfun_frame_layout.last_save_gpr_slot = j;
7088
7089 for (i = cfun_frame_layout.first_save_gpr_slot;
7090 i < cfun_frame_layout.last_save_gpr_slot + 1;
7091 i++)
7092 if (clobbered_regs[i])
7093 break;
7094
7095 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7096 if (clobbered_regs[j])
7097 break;
7098
7099 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7100 {
7101 /* Nothing to save/restore. */
7102 cfun_frame_layout.first_save_gpr = -1;
7103 cfun_frame_layout.first_restore_gpr = -1;
7104 cfun_frame_layout.last_save_gpr = -1;
7105 cfun_frame_layout.last_restore_gpr = -1;
7106 }
7107 else
7108 {
7109 /* Save / Restore from gpr i to j. */
7110 cfun_frame_layout.first_save_gpr = i;
7111 cfun_frame_layout.first_restore_gpr = i;
7112 cfun_frame_layout.last_save_gpr = j;
7113 cfun_frame_layout.last_restore_gpr = j;
7114 }
7115 }
7116
7117 if (cfun->stdarg)
7118 {
7119 /* Varargs functions need to save gprs 2 to 6. */
7120 if (cfun->va_list_gpr_size
7121 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7122 {
7123 int min_gpr = crtl->args.info.gprs;
7124 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7125 if (max_gpr > GP_ARG_NUM_REG)
7126 max_gpr = GP_ARG_NUM_REG;
7127
7128 if (cfun_frame_layout.first_save_gpr == -1
7129 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7130 {
7131 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7132 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7133 }
7134
7135 if (cfun_frame_layout.last_save_gpr == -1
7136 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7137 {
7138 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7139 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7140 }
7141 }
7142
7143 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7144 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7145 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7146 {
7147 int min_fpr = crtl->args.info.fprs;
7148 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7149 if (max_fpr > FP_ARG_NUM_REG)
7150 max_fpr = FP_ARG_NUM_REG;
7151
7152 /* ??? This is currently required to ensure proper location
7153 of the fpr save slots within the va_list save area. */
7154 if (TARGET_PACKED_STACK)
7155 min_fpr = 0;
7156
7157 for (i = min_fpr; i < max_fpr; i++)
7158 cfun_set_fpr_bit (i);
7159 }
7160 }
7161
7162 if (!TARGET_64BIT)
7163 for (i = 2; i < 4; i++)
7164 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7165 cfun_set_fpr_bit (i);
7166 }
7167
7168 /* Fill cfun->machine with info about frame of current function. */
7169
7170 static void
7171 s390_frame_info (void)
7172 {
7173 int i;
7174
7175 cfun_frame_layout.frame_size = get_frame_size ();
7176 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7177 fatal_error ("total size of local variables exceeds architecture limit");
7178
7179 if (!TARGET_PACKED_STACK)
7180 {
7181 cfun_frame_layout.backchain_offset = 0;
7182 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7183 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7184 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7185 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7186 * UNITS_PER_LONG);
7187 }
7188 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7189 {
7190 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7191 - UNITS_PER_LONG);
7192 cfun_frame_layout.gprs_offset
7193 = (cfun_frame_layout.backchain_offset
7194 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7195 * UNITS_PER_LONG);
7196
7197 if (TARGET_64BIT)
7198 {
7199 cfun_frame_layout.f4_offset
7200 = (cfun_frame_layout.gprs_offset
7201 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7202
7203 cfun_frame_layout.f0_offset
7204 = (cfun_frame_layout.f4_offset
7205 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7206 }
7207 else
7208 {
7209 /* On 31 bit we have to care about alignment of the
7210 floating point regs to provide fastest access. */
7211 cfun_frame_layout.f0_offset
7212 = ((cfun_frame_layout.gprs_offset
7213 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7214 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7215
7216 cfun_frame_layout.f4_offset
7217 = (cfun_frame_layout.f0_offset
7218 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7219 }
7220 }
7221 else /* no backchain */
7222 {
7223 cfun_frame_layout.f4_offset
7224 = (STACK_POINTER_OFFSET
7225 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7226
7227 cfun_frame_layout.f0_offset
7228 = (cfun_frame_layout.f4_offset
7229 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7230
7231 cfun_frame_layout.gprs_offset
7232 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7233 }
7234
7235 if (current_function_is_leaf
7236 && !TARGET_TPF_PROFILING
7237 && cfun_frame_layout.frame_size == 0
7238 && !cfun_save_high_fprs_p
7239 && !cfun->calls_alloca
7240 && !cfun->stdarg)
7241 return;
7242
7243 if (!TARGET_PACKED_STACK)
7244 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7245 + crtl->outgoing_args_size
7246 + cfun_frame_layout.high_fprs * 8);
7247 else
7248 {
7249 if (TARGET_BACKCHAIN)
7250 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7251
7252 /* No alignment trouble here because f8-f15 are only saved under
7253 64 bit. */
7254 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7255 cfun_frame_layout.f4_offset),
7256 cfun_frame_layout.gprs_offset)
7257 - cfun_frame_layout.high_fprs * 8);
7258
7259 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7260
7261 for (i = 0; i < 8; i++)
7262 if (cfun_fpr_bit_p (i))
7263 cfun_frame_layout.frame_size += 8;
7264
7265 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7266
7267 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7268 the frame size to sustain 8 byte alignment of stack frames. */
7269 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7270 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7271 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7272
7273 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7274 }
7275 }
7276
7277 /* Generate frame layout. Fills in register and frame data for the current
7278 function in cfun->machine. This routine can be called multiple times;
7279 it will re-do the complete frame layout every time. */
7280
7281 static void
7282 s390_init_frame_layout (void)
7283 {
7284 HOST_WIDE_INT frame_size;
7285 int base_used;
7286 int clobbered_regs[16];
7287
7288 /* On S/390 machines, we may need to perform branch splitting, which
7289 will require both base and return address register. We have no
7290 choice but to assume we're going to need them until right at the
7291 end of the machine dependent reorg phase. */
7292 if (!TARGET_CPU_ZARCH)
7293 cfun->machine->split_branches_pending_p = true;
7294
7295 do
7296 {
7297 frame_size = cfun_frame_layout.frame_size;
7298
7299 /* Try to predict whether we'll need the base register. */
7300 base_used = cfun->machine->split_branches_pending_p
7301 || crtl->uses_const_pool
7302 || (!DISP_IN_RANGE (frame_size)
7303 && !CONST_OK_FOR_K (frame_size));
7304
7305 /* Decide which register to use as literal pool base. In small
7306 leaf functions, try to use an unused call-clobbered register
7307 as base register to avoid save/restore overhead. */
7308 if (!base_used)
7309 cfun->machine->base_reg = NULL_RTX;
7310 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7311 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7312 else
7313 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7314
7315 s390_register_info (clobbered_regs);
7316 s390_frame_info ();
7317 }
7318 while (frame_size != cfun_frame_layout.frame_size);
7319 }
7320
7321 /* Update frame layout. Recompute actual register save data based on
7322 current info and update regs_ever_live for the special registers.
7323 May be called multiple times, but may never cause *more* registers
7324 to be saved than s390_init_frame_layout allocated room for. */
7325
7326 static void
7327 s390_update_frame_layout (void)
7328 {
7329 int clobbered_regs[16];
7330
7331 s390_register_info (clobbered_regs);
7332
7333 df_set_regs_ever_live (BASE_REGNUM,
7334 clobbered_regs[BASE_REGNUM] ? true : false);
7335 df_set_regs_ever_live (RETURN_REGNUM,
7336 clobbered_regs[RETURN_REGNUM] ? true : false);
7337 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7338 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7339
7340 if (cfun->machine->base_reg)
7341 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7342 }
7343
7344 /* Return true if it is legal to put a value with MODE into REGNO. */
7345
7346 bool
7347 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7348 {
7349 switch (REGNO_REG_CLASS (regno))
7350 {
7351 case FP_REGS:
7352 if (REGNO_PAIR_OK (regno, mode))
7353 {
7354 if (mode == SImode || mode == DImode)
7355 return true;
7356
7357 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7358 return true;
7359 }
7360 break;
7361 case ADDR_REGS:
7362 if (FRAME_REGNO_P (regno) && mode == Pmode)
7363 return true;
7364
7365 /* fallthrough */
7366 case GENERAL_REGS:
7367 if (REGNO_PAIR_OK (regno, mode))
7368 {
7369 if (TARGET_ZARCH
7370 || (mode != TFmode && mode != TCmode && mode != TDmode))
7371 return true;
7372 }
7373 break;
7374 case CC_REGS:
7375 if (GET_MODE_CLASS (mode) == MODE_CC)
7376 return true;
7377 break;
7378 case ACCESS_REGS:
7379 if (REGNO_PAIR_OK (regno, mode))
7380 {
7381 if (mode == SImode || mode == Pmode)
7382 return true;
7383 }
7384 break;
7385 default:
7386 return false;
7387 }
7388
7389 return false;
7390 }
7391
7392 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7393
7394 bool
7395 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7396 {
7397 /* Once we've decided upon a register to use as base register, it must
7398 no longer be used for any other purpose. */
7399 if (cfun->machine->base_reg)
7400 if (REGNO (cfun->machine->base_reg) == old_reg
7401 || REGNO (cfun->machine->base_reg) == new_reg)
7402 return false;
7403
7404 return true;
7405 }
7406
7407 /* Maximum number of registers to represent a value of mode MODE
7408 in a register of class RCLASS. */
7409
7410 bool
7411 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7412 {
7413 switch (rclass)
7414 {
7415 case FP_REGS:
7416 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7417 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7418 else
7419 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7420 case ACCESS_REGS:
7421 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7422 default:
7423 break;
7424 }
7425 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7426 }
7427
7428 /* Return true if register FROM can be eliminated via register TO. */
7429
7430 static bool
7431 s390_can_eliminate (const int from, const int to)
7432 {
7433 /* On zSeries machines, we have not marked the base register as fixed.
7434 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7435 If a function requires the base register, we say here that this
7436 elimination cannot be performed. This will cause reload to free
7437 up the base register (as if it were fixed). On the other hand,
7438 if the current function does *not* require the base register, we
7439 say here the elimination succeeds, which in turn allows reload
7440 to allocate the base register for any other purpose. */
7441 if (from == BASE_REGNUM && to == BASE_REGNUM)
7442 {
7443 if (TARGET_CPU_ZARCH)
7444 {
7445 s390_init_frame_layout ();
7446 return cfun->machine->base_reg == NULL_RTX;
7447 }
7448
7449 return false;
7450 }
7451
7452 /* Everything else must point into the stack frame. */
7453 gcc_assert (to == STACK_POINTER_REGNUM
7454 || to == HARD_FRAME_POINTER_REGNUM);
7455
7456 gcc_assert (from == FRAME_POINTER_REGNUM
7457 || from == ARG_POINTER_REGNUM
7458 || from == RETURN_ADDRESS_POINTER_REGNUM);
7459
7460 /* Make sure we actually saved the return address. */
7461 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7462 if (!crtl->calls_eh_return
7463 && !cfun->stdarg
7464 && !cfun_frame_layout.save_return_addr_p)
7465 return false;
7466
7467 return true;
7468 }
7469
7470 /* Return offset between register FROM and TO initially after prolog. */
7471
7472 HOST_WIDE_INT
7473 s390_initial_elimination_offset (int from, int to)
7474 {
7475 HOST_WIDE_INT offset;
7476 int index;
7477
7478 /* ??? Why are we called for non-eliminable pairs? */
7479 if (!s390_can_eliminate (from, to))
7480 return 0;
7481
7482 switch (from)
7483 {
7484 case FRAME_POINTER_REGNUM:
7485 offset = (get_frame_size()
7486 + STACK_POINTER_OFFSET
7487 + crtl->outgoing_args_size);
7488 break;
7489
7490 case ARG_POINTER_REGNUM:
7491 s390_init_frame_layout ();
7492 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7493 break;
7494
7495 case RETURN_ADDRESS_POINTER_REGNUM:
7496 s390_init_frame_layout ();
7497 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7498 gcc_assert (index >= 0);
7499 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7500 offset += index * UNITS_PER_LONG;
7501 break;
7502
7503 case BASE_REGNUM:
7504 offset = 0;
7505 break;
7506
7507 default:
7508 gcc_unreachable ();
7509 }
7510
7511 return offset;
7512 }
7513
7514 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7515 to register BASE. Return generated insn. */
7516
7517 static rtx
7518 save_fpr (rtx base, int offset, int regnum)
7519 {
7520 rtx addr;
7521 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7522
7523 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7524 set_mem_alias_set (addr, get_varargs_alias_set ());
7525 else
7526 set_mem_alias_set (addr, get_frame_alias_set ());
7527
7528 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7529 }
7530
7531 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7532 to register BASE. Return generated insn. */
7533
7534 static rtx
7535 restore_fpr (rtx base, int offset, int regnum)
7536 {
7537 rtx addr;
7538 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7539 set_mem_alias_set (addr, get_frame_alias_set ());
7540
7541 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7542 }
7543
7544 /* Return true if REGNO is a global register, but not one
7545 of the special ones that need to be saved/restored in anyway. */
7546
7547 static inline bool
7548 global_not_special_regno_p (int regno)
7549 {
7550 return (global_regs[regno]
7551 /* These registers are special and need to be
7552 restored in any case. */
7553 && !(regno == STACK_POINTER_REGNUM
7554 || regno == RETURN_REGNUM
7555 || regno == BASE_REGNUM
7556 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7557 }
7558
7559 /* Generate insn to save registers FIRST to LAST into
7560 the register save area located at offset OFFSET
7561 relative to register BASE. */
7562
7563 static rtx
7564 save_gprs (rtx base, int offset, int first, int last)
7565 {
7566 rtx addr, insn, note;
7567 int i;
7568
7569 addr = plus_constant (base, offset);
7570 addr = gen_rtx_MEM (Pmode, addr);
7571
7572 set_mem_alias_set (addr, get_frame_alias_set ());
7573
7574 /* Special-case single register. */
7575 if (first == last)
7576 {
7577 if (TARGET_64BIT)
7578 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7579 else
7580 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7581
7582 if (!global_not_special_regno_p (first))
7583 RTX_FRAME_RELATED_P (insn) = 1;
7584 return insn;
7585 }
7586
7587
7588 insn = gen_store_multiple (addr,
7589 gen_rtx_REG (Pmode, first),
7590 GEN_INT (last - first + 1));
7591
7592 if (first <= 6 && cfun->stdarg)
7593 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7594 {
7595 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7596
7597 if (first + i <= 6)
7598 set_mem_alias_set (mem, get_varargs_alias_set ());
7599 }
7600
7601 /* We need to set the FRAME_RELATED flag on all SETs
7602 inside the store-multiple pattern.
7603
7604 However, we must not emit DWARF records for registers 2..5
7605 if they are stored for use by variable arguments ...
7606
7607 ??? Unfortunately, it is not enough to simply not the
7608 FRAME_RELATED flags for those SETs, because the first SET
7609 of the PARALLEL is always treated as if it had the flag
7610 set, even if it does not. Therefore we emit a new pattern
7611 without those registers as REG_FRAME_RELATED_EXPR note. */
7612
7613 if (first >= 6 && !global_not_special_regno_p (first))
7614 {
7615 rtx pat = PATTERN (insn);
7616
7617 for (i = 0; i < XVECLEN (pat, 0); i++)
7618 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7619 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7620 0, i)))))
7621 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7622
7623 RTX_FRAME_RELATED_P (insn) = 1;
7624 }
7625 else if (last >= 6)
7626 {
7627 int start;
7628
7629 for (start = first >= 6 ? first : 6; start <= last; start++)
7630 if (!global_not_special_regno_p (start))
7631 break;
7632
7633 if (start > last)
7634 return insn;
7635
7636 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7637 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7638 gen_rtx_REG (Pmode, start),
7639 GEN_INT (last - start + 1));
7640 note = PATTERN (note);
7641
7642 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7643
7644 for (i = 0; i < XVECLEN (note, 0); i++)
7645 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7646 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7647 0, i)))))
7648 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7649
7650 RTX_FRAME_RELATED_P (insn) = 1;
7651 }
7652
7653 return insn;
7654 }
7655
7656 /* Generate insn to restore registers FIRST to LAST from
7657 the register save area located at offset OFFSET
7658 relative to register BASE. */
7659
7660 static rtx
7661 restore_gprs (rtx base, int offset, int first, int last)
7662 {
7663 rtx addr, insn;
7664
7665 addr = plus_constant (base, offset);
7666 addr = gen_rtx_MEM (Pmode, addr);
7667 set_mem_alias_set (addr, get_frame_alias_set ());
7668
7669 /* Special-case single register. */
7670 if (first == last)
7671 {
7672 if (TARGET_64BIT)
7673 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7674 else
7675 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7676
7677 return insn;
7678 }
7679
7680 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7681 addr,
7682 GEN_INT (last - first + 1));
7683 return insn;
7684 }
7685
7686 /* Return insn sequence to load the GOT register. */
7687
7688 static GTY(()) rtx got_symbol;
7689 rtx
7690 s390_load_got (void)
7691 {
7692 rtx insns;
7693
7694 if (!got_symbol)
7695 {
7696 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7697 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7698 }
7699
7700 start_sequence ();
7701
7702 if (TARGET_CPU_ZARCH)
7703 {
7704 emit_move_insn (pic_offset_table_rtx, got_symbol);
7705 }
7706 else
7707 {
7708 rtx offset;
7709
7710 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7711 UNSPEC_LTREL_OFFSET);
7712 offset = gen_rtx_CONST (Pmode, offset);
7713 offset = force_const_mem (Pmode, offset);
7714
7715 emit_move_insn (pic_offset_table_rtx, offset);
7716
7717 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7718 UNSPEC_LTREL_BASE);
7719 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7720
7721 emit_move_insn (pic_offset_table_rtx, offset);
7722 }
7723
7724 insns = get_insns ();
7725 end_sequence ();
7726 return insns;
7727 }
7728
7729 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7730 and the change to the stack pointer. */
7731
7732 static void
7733 s390_emit_stack_tie (void)
7734 {
7735 rtx mem = gen_frame_mem (BLKmode,
7736 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7737
7738 emit_insn (gen_stack_tie (mem));
7739 }
7740
7741 /* Expand the prologue into a bunch of separate insns. */
7742
7743 void
7744 s390_emit_prologue (void)
7745 {
7746 rtx insn, addr;
7747 rtx temp_reg;
7748 int i;
7749 int offset;
7750 int next_fpr = 0;
7751
7752 /* Complete frame layout. */
7753
7754 s390_update_frame_layout ();
7755
7756 /* Annotate all constant pool references to let the scheduler know
7757 they implicitly use the base register. */
7758
7759 push_topmost_sequence ();
7760
7761 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7762 if (INSN_P (insn))
7763 {
7764 annotate_constant_pool_refs (&PATTERN (insn));
7765 df_insn_rescan (insn);
7766 }
7767
7768 pop_topmost_sequence ();
7769
7770 /* Choose best register to use for temp use within prologue.
7771 See below for why TPF must use the register 1. */
7772
7773 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7774 && !current_function_is_leaf
7775 && !TARGET_TPF_PROFILING)
7776 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7777 else
7778 temp_reg = gen_rtx_REG (Pmode, 1);
7779
7780 /* Save call saved gprs. */
7781 if (cfun_frame_layout.first_save_gpr != -1)
7782 {
7783 insn = save_gprs (stack_pointer_rtx,
7784 cfun_frame_layout.gprs_offset +
7785 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7786 - cfun_frame_layout.first_save_gpr_slot),
7787 cfun_frame_layout.first_save_gpr,
7788 cfun_frame_layout.last_save_gpr);
7789 emit_insn (insn);
7790 }
7791
7792 /* Dummy insn to mark literal pool slot. */
7793
7794 if (cfun->machine->base_reg)
7795 emit_insn (gen_main_pool (cfun->machine->base_reg));
7796
7797 offset = cfun_frame_layout.f0_offset;
7798
7799 /* Save f0 and f2. */
7800 for (i = 0; i < 2; i++)
7801 {
7802 if (cfun_fpr_bit_p (i))
7803 {
7804 save_fpr (stack_pointer_rtx, offset, i + 16);
7805 offset += 8;
7806 }
7807 else if (!TARGET_PACKED_STACK)
7808 offset += 8;
7809 }
7810
7811 /* Save f4 and f6. */
7812 offset = cfun_frame_layout.f4_offset;
7813 for (i = 2; i < 4; i++)
7814 {
7815 if (cfun_fpr_bit_p (i))
7816 {
7817 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7818 offset += 8;
7819
7820 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7821 therefore are not frame related. */
7822 if (!call_really_used_regs[i + 16])
7823 RTX_FRAME_RELATED_P (insn) = 1;
7824 }
7825 else if (!TARGET_PACKED_STACK)
7826 offset += 8;
7827 }
7828
7829 if (TARGET_PACKED_STACK
7830 && cfun_save_high_fprs_p
7831 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7832 {
7833 offset = (cfun_frame_layout.f8_offset
7834 + (cfun_frame_layout.high_fprs - 1) * 8);
7835
7836 for (i = 15; i > 7 && offset >= 0; i--)
7837 if (cfun_fpr_bit_p (i))
7838 {
7839 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7840
7841 RTX_FRAME_RELATED_P (insn) = 1;
7842 offset -= 8;
7843 }
7844 if (offset >= cfun_frame_layout.f8_offset)
7845 next_fpr = i + 16;
7846 }
7847
7848 if (!TARGET_PACKED_STACK)
7849 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7850
7851 /* Decrement stack pointer. */
7852
7853 if (cfun_frame_layout.frame_size > 0)
7854 {
7855 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7856 rtx real_frame_off;
7857
7858 if (s390_stack_size)
7859 {
7860 HOST_WIDE_INT stack_guard;
7861
7862 if (s390_stack_guard)
7863 stack_guard = s390_stack_guard;
7864 else
7865 {
7866 /* If no value for stack guard is provided the smallest power of 2
7867 larger than the current frame size is chosen. */
7868 stack_guard = 1;
7869 while (stack_guard < cfun_frame_layout.frame_size)
7870 stack_guard <<= 1;
7871 }
7872
7873 if (cfun_frame_layout.frame_size >= s390_stack_size)
7874 {
7875 warning (0, "frame size of function %qs is "
7876 HOST_WIDE_INT_PRINT_DEC
7877 " bytes exceeding user provided stack limit of "
7878 HOST_WIDE_INT_PRINT_DEC " bytes. "
7879 "An unconditional trap is added.",
7880 current_function_name(), cfun_frame_layout.frame_size,
7881 s390_stack_size);
7882 emit_insn (gen_trap ());
7883 }
7884 else
7885 {
7886 /* stack_guard has to be smaller than s390_stack_size.
7887 Otherwise we would emit an AND with zero which would
7888 not match the test under mask pattern. */
7889 if (stack_guard >= s390_stack_size)
7890 {
7891 warning (0, "frame size of function %qs is "
7892 HOST_WIDE_INT_PRINT_DEC
7893 " bytes which is more than half the stack size. "
7894 "The dynamic check would not be reliable. "
7895 "No check emitted for this function.",
7896 current_function_name(),
7897 cfun_frame_layout.frame_size);
7898 }
7899 else
7900 {
7901 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7902 & ~(stack_guard - 1));
7903
7904 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7905 GEN_INT (stack_check_mask));
7906 if (TARGET_64BIT)
7907 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
7908 t, const0_rtx),
7909 t, const0_rtx, const0_rtx));
7910 else
7911 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
7912 t, const0_rtx),
7913 t, const0_rtx, const0_rtx));
7914 }
7915 }
7916 }
7917
7918 if (s390_warn_framesize > 0
7919 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7920 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7921 current_function_name (), cfun_frame_layout.frame_size);
7922
7923 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7924 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7925
7926 /* Save incoming stack pointer into temp reg. */
7927 if (TARGET_BACKCHAIN || next_fpr)
7928 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7929
7930 /* Subtract frame size from stack pointer. */
7931
7932 if (DISP_IN_RANGE (INTVAL (frame_off)))
7933 {
7934 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7935 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7936 frame_off));
7937 insn = emit_insn (insn);
7938 }
7939 else
7940 {
7941 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7942 frame_off = force_const_mem (Pmode, frame_off);
7943
7944 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7945 annotate_constant_pool_refs (&PATTERN (insn));
7946 }
7947
7948 RTX_FRAME_RELATED_P (insn) = 1;
7949 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7950 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7951 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7952 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7953 real_frame_off)));
7954
7955 /* Set backchain. */
7956
7957 if (TARGET_BACKCHAIN)
7958 {
7959 if (cfun_frame_layout.backchain_offset)
7960 addr = gen_rtx_MEM (Pmode,
7961 plus_constant (stack_pointer_rtx,
7962 cfun_frame_layout.backchain_offset));
7963 else
7964 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7965 set_mem_alias_set (addr, get_frame_alias_set ());
7966 insn = emit_insn (gen_move_insn (addr, temp_reg));
7967 }
7968
7969 /* If we support non-call exceptions (e.g. for Java),
7970 we need to make sure the backchain pointer is set up
7971 before any possibly trapping memory access. */
7972 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
7973 {
7974 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7975 emit_clobber (addr);
7976 }
7977 }
7978
7979 /* Save fprs 8 - 15 (64 bit ABI). */
7980
7981 if (cfun_save_high_fprs_p && next_fpr)
7982 {
7983 /* If the stack might be accessed through a different register
7984 we have to make sure that the stack pointer decrement is not
7985 moved below the use of the stack slots. */
7986 s390_emit_stack_tie ();
7987
7988 insn = emit_insn (gen_add2_insn (temp_reg,
7989 GEN_INT (cfun_frame_layout.f8_offset)));
7990
7991 offset = 0;
7992
7993 for (i = 24; i <= next_fpr; i++)
7994 if (cfun_fpr_bit_p (i - 16))
7995 {
7996 rtx addr = plus_constant (stack_pointer_rtx,
7997 cfun_frame_layout.frame_size
7998 + cfun_frame_layout.f8_offset
7999 + offset);
8000
8001 insn = save_fpr (temp_reg, offset, i);
8002 offset += 8;
8003 RTX_FRAME_RELATED_P (insn) = 1;
8004 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8005 gen_rtx_SET (VOIDmode,
8006 gen_rtx_MEM (DFmode, addr),
8007 gen_rtx_REG (DFmode, i)));
8008 }
8009 }
8010
8011 /* Set frame pointer, if needed. */
8012
8013 if (frame_pointer_needed)
8014 {
8015 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8016 RTX_FRAME_RELATED_P (insn) = 1;
8017 }
8018
8019 /* Set up got pointer, if needed. */
8020
8021 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8022 {
8023 rtx insns = s390_load_got ();
8024
8025 for (insn = insns; insn; insn = NEXT_INSN (insn))
8026 annotate_constant_pool_refs (&PATTERN (insn));
8027
8028 emit_insn (insns);
8029 }
8030
8031 if (TARGET_TPF_PROFILING)
8032 {
8033 /* Generate a BAS instruction to serve as a function
8034 entry intercept to facilitate the use of tracing
8035 algorithms located at the branch target. */
8036 emit_insn (gen_prologue_tpf ());
8037
8038 /* Emit a blockage here so that all code
8039 lies between the profiling mechanisms. */
8040 emit_insn (gen_blockage ());
8041 }
8042 }
8043
8044 /* Expand the epilogue into a bunch of separate insns. */
8045
8046 void
8047 s390_emit_epilogue (bool sibcall)
8048 {
8049 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8050 int area_bottom, area_top, offset = 0;
8051 int next_offset;
8052 rtvec p;
8053 int i;
8054
8055 if (TARGET_TPF_PROFILING)
8056 {
8057
8058 /* Generate a BAS instruction to serve as a function
8059 entry intercept to facilitate the use of tracing
8060 algorithms located at the branch target. */
8061
8062 /* Emit a blockage here so that all code
8063 lies between the profiling mechanisms. */
8064 emit_insn (gen_blockage ());
8065
8066 emit_insn (gen_epilogue_tpf ());
8067 }
8068
8069 /* Check whether to use frame or stack pointer for restore. */
8070
8071 frame_pointer = (frame_pointer_needed
8072 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8073
8074 s390_frame_area (&area_bottom, &area_top);
8075
8076 /* Check whether we can access the register save area.
8077 If not, increment the frame pointer as required. */
8078
8079 if (area_top <= area_bottom)
8080 {
8081 /* Nothing to restore. */
8082 }
8083 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8084 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8085 {
8086 /* Area is in range. */
8087 offset = cfun_frame_layout.frame_size;
8088 }
8089 else
8090 {
8091 rtx insn, frame_off, cfa;
8092
8093 offset = area_bottom < 0 ? -area_bottom : 0;
8094 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8095
8096 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8097 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8098 if (DISP_IN_RANGE (INTVAL (frame_off)))
8099 {
8100 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8101 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8102 insn = emit_insn (insn);
8103 }
8104 else
8105 {
8106 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8107 frame_off = force_const_mem (Pmode, frame_off);
8108
8109 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8110 annotate_constant_pool_refs (&PATTERN (insn));
8111 }
8112 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8113 RTX_FRAME_RELATED_P (insn) = 1;
8114 }
8115
8116 /* Restore call saved fprs. */
8117
8118 if (TARGET_64BIT)
8119 {
8120 if (cfun_save_high_fprs_p)
8121 {
8122 next_offset = cfun_frame_layout.f8_offset;
8123 for (i = 24; i < 32; i++)
8124 {
8125 if (cfun_fpr_bit_p (i - 16))
8126 {
8127 restore_fpr (frame_pointer,
8128 offset + next_offset, i);
8129 cfa_restores
8130 = alloc_reg_note (REG_CFA_RESTORE,
8131 gen_rtx_REG (DFmode, i), cfa_restores);
8132 next_offset += 8;
8133 }
8134 }
8135 }
8136
8137 }
8138 else
8139 {
8140 next_offset = cfun_frame_layout.f4_offset;
8141 for (i = 18; i < 20; i++)
8142 {
8143 if (cfun_fpr_bit_p (i - 16))
8144 {
8145 restore_fpr (frame_pointer,
8146 offset + next_offset, i);
8147 cfa_restores
8148 = alloc_reg_note (REG_CFA_RESTORE,
8149 gen_rtx_REG (DFmode, i), cfa_restores);
8150 next_offset += 8;
8151 }
8152 else if (!TARGET_PACKED_STACK)
8153 next_offset += 8;
8154 }
8155
8156 }
8157
8158 /* Return register. */
8159
8160 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8161
8162 /* Restore call saved gprs. */
8163
8164 if (cfun_frame_layout.first_restore_gpr != -1)
8165 {
8166 rtx insn, addr;
8167 int i;
8168
8169 /* Check for global register and save them
8170 to stack location from where they get restored. */
8171
8172 for (i = cfun_frame_layout.first_restore_gpr;
8173 i <= cfun_frame_layout.last_restore_gpr;
8174 i++)
8175 {
8176 if (global_not_special_regno_p (i))
8177 {
8178 addr = plus_constant (frame_pointer,
8179 offset + cfun_frame_layout.gprs_offset
8180 + (i - cfun_frame_layout.first_save_gpr_slot)
8181 * UNITS_PER_LONG);
8182 addr = gen_rtx_MEM (Pmode, addr);
8183 set_mem_alias_set (addr, get_frame_alias_set ());
8184 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8185 }
8186 else
8187 cfa_restores
8188 = alloc_reg_note (REG_CFA_RESTORE,
8189 gen_rtx_REG (Pmode, i), cfa_restores);
8190 }
8191
8192 if (! sibcall)
8193 {
8194 /* Fetch return address from stack before load multiple,
8195 this will do good for scheduling. */
8196
8197 if (cfun_frame_layout.save_return_addr_p
8198 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8199 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8200 {
8201 int return_regnum = find_unused_clobbered_reg();
8202 if (!return_regnum)
8203 return_regnum = 4;
8204 return_reg = gen_rtx_REG (Pmode, return_regnum);
8205
8206 addr = plus_constant (frame_pointer,
8207 offset + cfun_frame_layout.gprs_offset
8208 + (RETURN_REGNUM
8209 - cfun_frame_layout.first_save_gpr_slot)
8210 * UNITS_PER_LONG);
8211 addr = gen_rtx_MEM (Pmode, addr);
8212 set_mem_alias_set (addr, get_frame_alias_set ());
8213 emit_move_insn (return_reg, addr);
8214 }
8215 }
8216
8217 insn = restore_gprs (frame_pointer,
8218 offset + cfun_frame_layout.gprs_offset
8219 + (cfun_frame_layout.first_restore_gpr
8220 - cfun_frame_layout.first_save_gpr_slot)
8221 * UNITS_PER_LONG,
8222 cfun_frame_layout.first_restore_gpr,
8223 cfun_frame_layout.last_restore_gpr);
8224 insn = emit_insn (insn);
8225 REG_NOTES (insn) = cfa_restores;
8226 add_reg_note (insn, REG_CFA_DEF_CFA,
8227 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8228 RTX_FRAME_RELATED_P (insn) = 1;
8229 }
8230
8231 if (! sibcall)
8232 {
8233
8234 /* Return to caller. */
8235
8236 p = rtvec_alloc (2);
8237
8238 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8239 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8240 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8241 }
8242 }
8243
8244
8245 /* Return the size in bytes of a function argument of
8246 type TYPE and/or mode MODE. At least one of TYPE or
8247 MODE must be specified. */
8248
8249 static int
8250 s390_function_arg_size (enum machine_mode mode, const_tree type)
8251 {
8252 if (type)
8253 return int_size_in_bytes (type);
8254
8255 /* No type info available for some library calls ... */
8256 if (mode != BLKmode)
8257 return GET_MODE_SIZE (mode);
8258
8259 /* If we have neither type nor mode, abort */
8260 gcc_unreachable ();
8261 }
8262
8263 /* Return true if a function argument of type TYPE and mode MODE
8264 is to be passed in a floating-point register, if available. */
8265
8266 static bool
8267 s390_function_arg_float (enum machine_mode mode, tree type)
8268 {
8269 int size = s390_function_arg_size (mode, type);
8270 if (size > 8)
8271 return false;
8272
8273 /* Soft-float changes the ABI: no floating-point registers are used. */
8274 if (TARGET_SOFT_FLOAT)
8275 return false;
8276
8277 /* No type info available for some library calls ... */
8278 if (!type)
8279 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8280
8281 /* The ABI says that record types with a single member are treated
8282 just like that member would be. */
8283 while (TREE_CODE (type) == RECORD_TYPE)
8284 {
8285 tree field, single = NULL_TREE;
8286
8287 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8288 {
8289 if (TREE_CODE (field) != FIELD_DECL)
8290 continue;
8291
8292 if (single == NULL_TREE)
8293 single = TREE_TYPE (field);
8294 else
8295 return false;
8296 }
8297
8298 if (single == NULL_TREE)
8299 return false;
8300 else
8301 type = single;
8302 }
8303
8304 return TREE_CODE (type) == REAL_TYPE;
8305 }
8306
8307 /* Return true if a function argument of type TYPE and mode MODE
8308 is to be passed in an integer register, or a pair of integer
8309 registers, if available. */
8310
8311 static bool
8312 s390_function_arg_integer (enum machine_mode mode, tree type)
8313 {
8314 int size = s390_function_arg_size (mode, type);
8315 if (size > 8)
8316 return false;
8317
8318 /* No type info available for some library calls ... */
8319 if (!type)
8320 return GET_MODE_CLASS (mode) == MODE_INT
8321 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8322
8323 /* We accept small integral (and similar) types. */
8324 if (INTEGRAL_TYPE_P (type)
8325 || POINTER_TYPE_P (type)
8326 || TREE_CODE (type) == OFFSET_TYPE
8327 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8328 return true;
8329
8330 /* We also accept structs of size 1, 2, 4, 8 that are not
8331 passed in floating-point registers. */
8332 if (AGGREGATE_TYPE_P (type)
8333 && exact_log2 (size) >= 0
8334 && !s390_function_arg_float (mode, type))
8335 return true;
8336
8337 return false;
8338 }
8339
8340 /* Return 1 if a function argument of type TYPE and mode MODE
8341 is to be passed by reference. The ABI specifies that only
8342 structures of size 1, 2, 4, or 8 bytes are passed by value,
8343 all other structures (and complex numbers) are passed by
8344 reference. */
8345
8346 static bool
8347 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8348 enum machine_mode mode, const_tree type,
8349 bool named ATTRIBUTE_UNUSED)
8350 {
8351 int size = s390_function_arg_size (mode, type);
8352 if (size > 8)
8353 return true;
8354
8355 if (type)
8356 {
8357 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8358 return 1;
8359
8360 if (TREE_CODE (type) == COMPLEX_TYPE
8361 || TREE_CODE (type) == VECTOR_TYPE)
8362 return 1;
8363 }
8364
8365 return 0;
8366 }
8367
8368 /* Update the data in CUM to advance over an argument of mode MODE and
8369 data type TYPE. (TYPE is null for libcalls where that information
8370 may not be available.). The boolean NAMED specifies whether the
8371 argument is a named argument (as opposed to an unnamed argument
8372 matching an ellipsis). */
8373
8374 void
8375 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8376 tree type, int named ATTRIBUTE_UNUSED)
8377 {
8378 if (s390_function_arg_float (mode, type))
8379 {
8380 cum->fprs += 1;
8381 }
8382 else if (s390_function_arg_integer (mode, type))
8383 {
8384 int size = s390_function_arg_size (mode, type);
8385 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8386 }
8387 else
8388 gcc_unreachable ();
8389 }
8390
8391 /* Define where to put the arguments to a function.
8392 Value is zero to push the argument on the stack,
8393 or a hard register in which to store the argument.
8394
8395 MODE is the argument's machine mode.
8396 TYPE is the data type of the argument (as a tree).
8397 This is null for libcalls where that information may
8398 not be available.
8399 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8400 the preceding args and about the function being called.
8401 NAMED is nonzero if this argument is a named parameter
8402 (otherwise it is an extra parameter matching an ellipsis).
8403
8404 On S/390, we use general purpose registers 2 through 6 to
8405 pass integer, pointer, and certain structure arguments, and
8406 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8407 to pass floating point arguments. All remaining arguments
8408 are pushed to the stack. */
8409
8410 rtx
8411 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8412 int named ATTRIBUTE_UNUSED)
8413 {
8414 if (s390_function_arg_float (mode, type))
8415 {
8416 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8417 return 0;
8418 else
8419 return gen_rtx_REG (mode, cum->fprs + 16);
8420 }
8421 else if (s390_function_arg_integer (mode, type))
8422 {
8423 int size = s390_function_arg_size (mode, type);
8424 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8425
8426 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8427 return 0;
8428 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8429 return gen_rtx_REG (mode, cum->gprs + 2);
8430 else if (n_gprs == 2)
8431 {
8432 rtvec p = rtvec_alloc (2);
8433
8434 RTVEC_ELT (p, 0)
8435 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8436 const0_rtx);
8437 RTVEC_ELT (p, 1)
8438 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8439 GEN_INT (4));
8440
8441 return gen_rtx_PARALLEL (mode, p);
8442 }
8443 }
8444
8445 /* After the real arguments, expand_call calls us once again
8446 with a void_type_node type. Whatever we return here is
8447 passed as operand 2 to the call expanders.
8448
8449 We don't need this feature ... */
8450 else if (type == void_type_node)
8451 return const0_rtx;
8452
8453 gcc_unreachable ();
8454 }
8455
8456 /* Return true if return values of type TYPE should be returned
8457 in a memory buffer whose address is passed by the caller as
8458 hidden first argument. */
8459
8460 static bool
8461 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8462 {
8463 /* We accept small integral (and similar) types. */
8464 if (INTEGRAL_TYPE_P (type)
8465 || POINTER_TYPE_P (type)
8466 || TREE_CODE (type) == OFFSET_TYPE
8467 || TREE_CODE (type) == REAL_TYPE)
8468 return int_size_in_bytes (type) > 8;
8469
8470 /* Aggregates and similar constructs are always returned
8471 in memory. */
8472 if (AGGREGATE_TYPE_P (type)
8473 || TREE_CODE (type) == COMPLEX_TYPE
8474 || TREE_CODE (type) == VECTOR_TYPE)
8475 return true;
8476
8477 /* ??? We get called on all sorts of random stuff from
8478 aggregate_value_p. We can't abort, but it's not clear
8479 what's safe to return. Pretend it's a struct I guess. */
8480 return true;
8481 }
8482
8483 /* Function arguments and return values are promoted to word size. */
8484
8485 static enum machine_mode
8486 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8487 int *punsignedp,
8488 const_tree fntype ATTRIBUTE_UNUSED,
8489 int for_return ATTRIBUTE_UNUSED)
8490 {
8491 if (INTEGRAL_MODE_P (mode)
8492 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8493 {
8494 if (POINTER_TYPE_P (type))
8495 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8496 return Pmode;
8497 }
8498
8499 return mode;
8500 }
8501
8502 /* Define where to return a (scalar) value of type TYPE.
8503 If TYPE is null, define where to return a (scalar)
8504 value of mode MODE from a libcall. */
8505
8506 rtx
8507 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8508 {
8509 if (type)
8510 {
8511 int unsignedp = TYPE_UNSIGNED (type);
8512 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8513 }
8514
8515 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8516 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8517
8518 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8519 return gen_rtx_REG (mode, 16);
8520 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8521 || UNITS_PER_LONG == UNITS_PER_WORD)
8522 return gen_rtx_REG (mode, 2);
8523 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8524 {
8525 rtvec p = rtvec_alloc (2);
8526
8527 RTVEC_ELT (p, 0)
8528 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8529 RTVEC_ELT (p, 1)
8530 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8531
8532 return gen_rtx_PARALLEL (mode, p);
8533 }
8534
8535 gcc_unreachable ();
8536 }
8537
8538
8539 /* Create and return the va_list datatype.
8540
8541 On S/390, va_list is an array type equivalent to
8542
8543 typedef struct __va_list_tag
8544 {
8545 long __gpr;
8546 long __fpr;
8547 void *__overflow_arg_area;
8548 void *__reg_save_area;
8549 } va_list[1];
8550
8551 where __gpr and __fpr hold the number of general purpose
8552 or floating point arguments used up to now, respectively,
8553 __overflow_arg_area points to the stack location of the
8554 next argument passed on the stack, and __reg_save_area
8555 always points to the start of the register area in the
8556 call frame of the current function. The function prologue
8557 saves all registers used for argument passing into this
8558 area if the function uses variable arguments. */
8559
8560 static tree
8561 s390_build_builtin_va_list (void)
8562 {
8563 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8564
8565 record = lang_hooks.types.make_type (RECORD_TYPE);
8566
8567 type_decl =
8568 build_decl (BUILTINS_LOCATION,
8569 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8570
8571 f_gpr = build_decl (BUILTINS_LOCATION,
8572 FIELD_DECL, get_identifier ("__gpr"),
8573 long_integer_type_node);
8574 f_fpr = build_decl (BUILTINS_LOCATION,
8575 FIELD_DECL, get_identifier ("__fpr"),
8576 long_integer_type_node);
8577 f_ovf = build_decl (BUILTINS_LOCATION,
8578 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8579 ptr_type_node);
8580 f_sav = build_decl (BUILTINS_LOCATION,
8581 FIELD_DECL, get_identifier ("__reg_save_area"),
8582 ptr_type_node);
8583
8584 va_list_gpr_counter_field = f_gpr;
8585 va_list_fpr_counter_field = f_fpr;
8586
8587 DECL_FIELD_CONTEXT (f_gpr) = record;
8588 DECL_FIELD_CONTEXT (f_fpr) = record;
8589 DECL_FIELD_CONTEXT (f_ovf) = record;
8590 DECL_FIELD_CONTEXT (f_sav) = record;
8591
8592 TREE_CHAIN (record) = type_decl;
8593 TYPE_NAME (record) = type_decl;
8594 TYPE_FIELDS (record) = f_gpr;
8595 TREE_CHAIN (f_gpr) = f_fpr;
8596 TREE_CHAIN (f_fpr) = f_ovf;
8597 TREE_CHAIN (f_ovf) = f_sav;
8598
8599 layout_type (record);
8600
8601 /* The correct type is an array type of one element. */
8602 return build_array_type (record, build_index_type (size_zero_node));
8603 }
8604
8605 /* Implement va_start by filling the va_list structure VALIST.
8606 STDARG_P is always true, and ignored.
8607 NEXTARG points to the first anonymous stack argument.
8608
8609 The following global variables are used to initialize
8610 the va_list structure:
8611
8612 crtl->args.info:
8613 holds number of gprs and fprs used for named arguments.
8614 crtl->args.arg_offset_rtx:
8615 holds the offset of the first anonymous stack argument
8616 (relative to the virtual arg pointer). */
8617
8618 static void
8619 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8620 {
8621 HOST_WIDE_INT n_gpr, n_fpr;
8622 int off;
8623 tree f_gpr, f_fpr, f_ovf, f_sav;
8624 tree gpr, fpr, ovf, sav, t;
8625
8626 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8627 f_fpr = TREE_CHAIN (f_gpr);
8628 f_ovf = TREE_CHAIN (f_fpr);
8629 f_sav = TREE_CHAIN (f_ovf);
8630
8631 valist = build_va_arg_indirect_ref (valist);
8632 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8633 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8634 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8635 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8636
8637 /* Count number of gp and fp argument registers used. */
8638
8639 n_gpr = crtl->args.info.gprs;
8640 n_fpr = crtl->args.info.fprs;
8641
8642 if (cfun->va_list_gpr_size)
8643 {
8644 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8645 build_int_cst (NULL_TREE, n_gpr));
8646 TREE_SIDE_EFFECTS (t) = 1;
8647 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8648 }
8649
8650 if (cfun->va_list_fpr_size)
8651 {
8652 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8653 build_int_cst (NULL_TREE, n_fpr));
8654 TREE_SIDE_EFFECTS (t) = 1;
8655 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8656 }
8657
8658 /* Find the overflow area. */
8659 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8660 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8661 {
8662 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8663
8664 off = INTVAL (crtl->args.arg_offset_rtx);
8665 off = off < 0 ? 0 : off;
8666 if (TARGET_DEBUG_ARG)
8667 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8668 (int)n_gpr, (int)n_fpr, off);
8669
8670 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8671
8672 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8673 TREE_SIDE_EFFECTS (t) = 1;
8674 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8675 }
8676
8677 /* Find the register save area. */
8678 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8679 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8680 {
8681 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8682 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8683 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8684
8685 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8686 TREE_SIDE_EFFECTS (t) = 1;
8687 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8688 }
8689 }
8690
8691 /* Implement va_arg by updating the va_list structure
8692 VALIST as required to retrieve an argument of type
8693 TYPE, and returning that argument.
8694
8695 Generates code equivalent to:
8696
8697 if (integral value) {
8698 if (size <= 4 && args.gpr < 5 ||
8699 size > 4 && args.gpr < 4 )
8700 ret = args.reg_save_area[args.gpr+8]
8701 else
8702 ret = *args.overflow_arg_area++;
8703 } else if (float value) {
8704 if (args.fgpr < 2)
8705 ret = args.reg_save_area[args.fpr+64]
8706 else
8707 ret = *args.overflow_arg_area++;
8708 } else if (aggregate value) {
8709 if (args.gpr < 5)
8710 ret = *args.reg_save_area[args.gpr]
8711 else
8712 ret = **args.overflow_arg_area++;
8713 } */
8714
8715 static tree
8716 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8717 gimple_seq *post_p ATTRIBUTE_UNUSED)
8718 {
8719 tree f_gpr, f_fpr, f_ovf, f_sav;
8720 tree gpr, fpr, ovf, sav, reg, t, u;
8721 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8722 tree lab_false, lab_over, addr;
8723
8724 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8725 f_fpr = TREE_CHAIN (f_gpr);
8726 f_ovf = TREE_CHAIN (f_fpr);
8727 f_sav = TREE_CHAIN (f_ovf);
8728
8729 valist = build_va_arg_indirect_ref (valist);
8730 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8731 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8732 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8733
8734 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8735 both appear on a lhs. */
8736 valist = unshare_expr (valist);
8737 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8738
8739 size = int_size_in_bytes (type);
8740
8741 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8742 {
8743 if (TARGET_DEBUG_ARG)
8744 {
8745 fprintf (stderr, "va_arg: aggregate type");
8746 debug_tree (type);
8747 }
8748
8749 /* Aggregates are passed by reference. */
8750 indirect_p = 1;
8751 reg = gpr;
8752 n_reg = 1;
8753
8754 /* kernel stack layout on 31 bit: It is assumed here that no padding
8755 will be added by s390_frame_info because for va_args always an even
8756 number of gprs has to be saved r15-r2 = 14 regs. */
8757 sav_ofs = 2 * UNITS_PER_LONG;
8758 sav_scale = UNITS_PER_LONG;
8759 size = UNITS_PER_LONG;
8760 max_reg = GP_ARG_NUM_REG - n_reg;
8761 }
8762 else if (s390_function_arg_float (TYPE_MODE (type), type))
8763 {
8764 if (TARGET_DEBUG_ARG)
8765 {
8766 fprintf (stderr, "va_arg: float type");
8767 debug_tree (type);
8768 }
8769
8770 /* FP args go in FP registers, if present. */
8771 indirect_p = 0;
8772 reg = fpr;
8773 n_reg = 1;
8774 sav_ofs = 16 * UNITS_PER_LONG;
8775 sav_scale = 8;
8776 max_reg = FP_ARG_NUM_REG - n_reg;
8777 }
8778 else
8779 {
8780 if (TARGET_DEBUG_ARG)
8781 {
8782 fprintf (stderr, "va_arg: other type");
8783 debug_tree (type);
8784 }
8785
8786 /* Otherwise into GP registers. */
8787 indirect_p = 0;
8788 reg = gpr;
8789 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8790
8791 /* kernel stack layout on 31 bit: It is assumed here that no padding
8792 will be added by s390_frame_info because for va_args always an even
8793 number of gprs has to be saved r15-r2 = 14 regs. */
8794 sav_ofs = 2 * UNITS_PER_LONG;
8795
8796 if (size < UNITS_PER_LONG)
8797 sav_ofs += UNITS_PER_LONG - size;
8798
8799 sav_scale = UNITS_PER_LONG;
8800 max_reg = GP_ARG_NUM_REG - n_reg;
8801 }
8802
8803 /* Pull the value out of the saved registers ... */
8804
8805 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8806 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8807 addr = create_tmp_var (ptr_type_node, "addr");
8808
8809 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8810 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8811 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8812 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8813 gimplify_and_add (t, pre_p);
8814
8815 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8816 size_int (sav_ofs));
8817 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8818 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8819 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8820
8821 gimplify_assign (addr, t, pre_p);
8822
8823 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8824
8825 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8826
8827
8828 /* ... Otherwise out of the overflow area. */
8829
8830 t = ovf;
8831 if (size < UNITS_PER_LONG)
8832 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8833 size_int (UNITS_PER_LONG - size));
8834
8835 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8836
8837 gimplify_assign (addr, t, pre_p);
8838
8839 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8840 size_int (size));
8841 gimplify_assign (ovf, t, pre_p);
8842
8843 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8844
8845
8846 /* Increment register save count. */
8847
8848 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8849 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8850 gimplify_and_add (u, pre_p);
8851
8852 if (indirect_p)
8853 {
8854 t = build_pointer_type_for_mode (build_pointer_type (type),
8855 ptr_mode, true);
8856 addr = fold_convert (t, addr);
8857 addr = build_va_arg_indirect_ref (addr);
8858 }
8859 else
8860 {
8861 t = build_pointer_type_for_mode (type, ptr_mode, true);
8862 addr = fold_convert (t, addr);
8863 }
8864
8865 return build_va_arg_indirect_ref (addr);
8866 }
8867
8868
8869 /* Builtins. */
8870
8871 enum s390_builtin
8872 {
8873 S390_BUILTIN_THREAD_POINTER,
8874 S390_BUILTIN_SET_THREAD_POINTER,
8875
8876 S390_BUILTIN_max
8877 };
8878
8879 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8880 CODE_FOR_get_tp_64,
8881 CODE_FOR_set_tp_64
8882 };
8883
8884 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8885 CODE_FOR_get_tp_31,
8886 CODE_FOR_set_tp_31
8887 };
8888
8889 static void
8890 s390_init_builtins (void)
8891 {
8892 tree ftype;
8893
8894 ftype = build_function_type (ptr_type_node, void_list_node);
8895 add_builtin_function ("__builtin_thread_pointer", ftype,
8896 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8897 NULL, NULL_TREE);
8898
8899 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8900 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8901 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8902 NULL, NULL_TREE);
8903 }
8904
8905 /* Expand an expression EXP that calls a built-in function,
8906 with result going to TARGET if that's convenient
8907 (and in mode MODE if that's convenient).
8908 SUBTARGET may be used as the target for computing one of EXP's operands.
8909 IGNORE is nonzero if the value is to be ignored. */
8910
8911 static rtx
8912 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8913 enum machine_mode mode ATTRIBUTE_UNUSED,
8914 int ignore ATTRIBUTE_UNUSED)
8915 {
8916 #define MAX_ARGS 2
8917
8918 enum insn_code const *code_for_builtin =
8919 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8920
8921 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8922 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8923 enum insn_code icode;
8924 rtx op[MAX_ARGS], pat;
8925 int arity;
8926 bool nonvoid;
8927 tree arg;
8928 call_expr_arg_iterator iter;
8929
8930 if (fcode >= S390_BUILTIN_max)
8931 internal_error ("bad builtin fcode");
8932 icode = code_for_builtin[fcode];
8933 if (icode == 0)
8934 internal_error ("bad builtin fcode");
8935
8936 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8937
8938 arity = 0;
8939 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8940 {
8941 const struct insn_operand_data *insn_op;
8942
8943 if (arg == error_mark_node)
8944 return NULL_RTX;
8945 if (arity > MAX_ARGS)
8946 return NULL_RTX;
8947
8948 insn_op = &insn_data[icode].operand[arity + nonvoid];
8949
8950 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8951
8952 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8953 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8954 arity++;
8955 }
8956
8957 if (nonvoid)
8958 {
8959 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8960 if (!target
8961 || GET_MODE (target) != tmode
8962 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8963 target = gen_reg_rtx (tmode);
8964 }
8965
8966 switch (arity)
8967 {
8968 case 0:
8969 pat = GEN_FCN (icode) (target);
8970 break;
8971 case 1:
8972 if (nonvoid)
8973 pat = GEN_FCN (icode) (target, op[0]);
8974 else
8975 pat = GEN_FCN (icode) (op[0]);
8976 break;
8977 case 2:
8978 pat = GEN_FCN (icode) (target, op[0], op[1]);
8979 break;
8980 default:
8981 gcc_unreachable ();
8982 }
8983 if (!pat)
8984 return NULL_RTX;
8985 emit_insn (pat);
8986
8987 if (nonvoid)
8988 return target;
8989 else
8990 return const0_rtx;
8991 }
8992
8993
8994 /* Output assembly code for the trampoline template to
8995 stdio stream FILE.
8996
8997 On S/390, we use gpr 1 internally in the trampoline code;
8998 gpr 0 is used to hold the static chain. */
8999
9000 static void
9001 s390_asm_trampoline_template (FILE *file)
9002 {
9003 rtx op[2];
9004 op[0] = gen_rtx_REG (Pmode, 0);
9005 op[1] = gen_rtx_REG (Pmode, 1);
9006
9007 if (TARGET_64BIT)
9008 {
9009 output_asm_insn ("basr\t%1,0", op);
9010 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9011 output_asm_insn ("br\t%1", op);
9012 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9013 }
9014 else
9015 {
9016 output_asm_insn ("basr\t%1,0", op);
9017 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9018 output_asm_insn ("br\t%1", op);
9019 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9020 }
9021 }
9022
9023 /* Emit RTL insns to initialize the variable parts of a trampoline.
9024 FNADDR is an RTX for the address of the function's pure code.
9025 CXT is an RTX for the static chain value for the function. */
9026
9027 static void
9028 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9029 {
9030 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9031 rtx mem;
9032
9033 emit_block_move (m_tramp, assemble_trampoline_template (),
9034 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9035
9036 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9037 emit_move_insn (mem, cxt);
9038 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9039 emit_move_insn (mem, fnaddr);
9040 }
9041
9042 /* Output assembler code to FILE to increment profiler label # LABELNO
9043 for profiling a function entry. */
9044
9045 void
9046 s390_function_profiler (FILE *file, int labelno)
9047 {
9048 rtx op[7];
9049
9050 char label[128];
9051 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9052
9053 fprintf (file, "# function profiler \n");
9054
9055 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9056 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9057 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9058
9059 op[2] = gen_rtx_REG (Pmode, 1);
9060 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9061 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9062
9063 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9064 if (flag_pic)
9065 {
9066 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9067 op[4] = gen_rtx_CONST (Pmode, op[4]);
9068 }
9069
9070 if (TARGET_64BIT)
9071 {
9072 output_asm_insn ("stg\t%0,%1", op);
9073 output_asm_insn ("larl\t%2,%3", op);
9074 output_asm_insn ("brasl\t%0,%4", op);
9075 output_asm_insn ("lg\t%0,%1", op);
9076 }
9077 else if (!flag_pic)
9078 {
9079 op[6] = gen_label_rtx ();
9080
9081 output_asm_insn ("st\t%0,%1", op);
9082 output_asm_insn ("bras\t%2,%l6", op);
9083 output_asm_insn (".long\t%4", op);
9084 output_asm_insn (".long\t%3", op);
9085 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9086 output_asm_insn ("l\t%0,0(%2)", op);
9087 output_asm_insn ("l\t%2,4(%2)", op);
9088 output_asm_insn ("basr\t%0,%0", op);
9089 output_asm_insn ("l\t%0,%1", op);
9090 }
9091 else
9092 {
9093 op[5] = gen_label_rtx ();
9094 op[6] = gen_label_rtx ();
9095
9096 output_asm_insn ("st\t%0,%1", op);
9097 output_asm_insn ("bras\t%2,%l6", op);
9098 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9099 output_asm_insn (".long\t%4-%l5", op);
9100 output_asm_insn (".long\t%3-%l5", op);
9101 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9102 output_asm_insn ("lr\t%0,%2", op);
9103 output_asm_insn ("a\t%0,0(%2)", op);
9104 output_asm_insn ("a\t%2,4(%2)", op);
9105 output_asm_insn ("basr\t%0,%0", op);
9106 output_asm_insn ("l\t%0,%1", op);
9107 }
9108 }
9109
9110 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9111 into its SYMBOL_REF_FLAGS. */
9112
9113 static void
9114 s390_encode_section_info (tree decl, rtx rtl, int first)
9115 {
9116 default_encode_section_info (decl, rtl, first);
9117
9118 if (TREE_CODE (decl) == VAR_DECL)
9119 {
9120 /* If a variable has a forced alignment to < 2 bytes, mark it
9121 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9122 operand. */
9123 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9124 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9125 if (!DECL_SIZE (decl)
9126 || !DECL_ALIGN (decl)
9127 || !host_integerp (DECL_SIZE (decl), 0)
9128 || (DECL_ALIGN (decl) <= 64
9129 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9130 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9131 }
9132
9133 /* Literal pool references don't have a decl so they are handled
9134 differently here. We rely on the information in the MEM_ALIGN
9135 entry to decide upon natural alignment. */
9136 if (MEM_P (rtl)
9137 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9138 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9139 && (MEM_ALIGN (rtl) == 0
9140 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9141 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9142 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9143 }
9144
9145 /* Output thunk to FILE that implements a C++ virtual function call (with
9146 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9147 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9148 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9149 relative to the resulting this pointer. */
9150
9151 static void
9152 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9153 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9154 tree function)
9155 {
9156 rtx op[10];
9157 int nonlocal = 0;
9158
9159 /* Make sure unwind info is emitted for the thunk if needed. */
9160 final_start_function (emit_barrier (), file, 1);
9161
9162 /* Operand 0 is the target function. */
9163 op[0] = XEXP (DECL_RTL (function), 0);
9164 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9165 {
9166 nonlocal = 1;
9167 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9168 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9169 op[0] = gen_rtx_CONST (Pmode, op[0]);
9170 }
9171
9172 /* Operand 1 is the 'this' pointer. */
9173 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9174 op[1] = gen_rtx_REG (Pmode, 3);
9175 else
9176 op[1] = gen_rtx_REG (Pmode, 2);
9177
9178 /* Operand 2 is the delta. */
9179 op[2] = GEN_INT (delta);
9180
9181 /* Operand 3 is the vcall_offset. */
9182 op[3] = GEN_INT (vcall_offset);
9183
9184 /* Operand 4 is the temporary register. */
9185 op[4] = gen_rtx_REG (Pmode, 1);
9186
9187 /* Operands 5 to 8 can be used as labels. */
9188 op[5] = NULL_RTX;
9189 op[6] = NULL_RTX;
9190 op[7] = NULL_RTX;
9191 op[8] = NULL_RTX;
9192
9193 /* Operand 9 can be used for temporary register. */
9194 op[9] = NULL_RTX;
9195
9196 /* Generate code. */
9197 if (TARGET_64BIT)
9198 {
9199 /* Setup literal pool pointer if required. */
9200 if ((!DISP_IN_RANGE (delta)
9201 && !CONST_OK_FOR_K (delta)
9202 && !CONST_OK_FOR_Os (delta))
9203 || (!DISP_IN_RANGE (vcall_offset)
9204 && !CONST_OK_FOR_K (vcall_offset)
9205 && !CONST_OK_FOR_Os (vcall_offset)))
9206 {
9207 op[5] = gen_label_rtx ();
9208 output_asm_insn ("larl\t%4,%5", op);
9209 }
9210
9211 /* Add DELTA to this pointer. */
9212 if (delta)
9213 {
9214 if (CONST_OK_FOR_J (delta))
9215 output_asm_insn ("la\t%1,%2(%1)", op);
9216 else if (DISP_IN_RANGE (delta))
9217 output_asm_insn ("lay\t%1,%2(%1)", op);
9218 else if (CONST_OK_FOR_K (delta))
9219 output_asm_insn ("aghi\t%1,%2", op);
9220 else if (CONST_OK_FOR_Os (delta))
9221 output_asm_insn ("agfi\t%1,%2", op);
9222 else
9223 {
9224 op[6] = gen_label_rtx ();
9225 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9226 }
9227 }
9228
9229 /* Perform vcall adjustment. */
9230 if (vcall_offset)
9231 {
9232 if (DISP_IN_RANGE (vcall_offset))
9233 {
9234 output_asm_insn ("lg\t%4,0(%1)", op);
9235 output_asm_insn ("ag\t%1,%3(%4)", op);
9236 }
9237 else if (CONST_OK_FOR_K (vcall_offset))
9238 {
9239 output_asm_insn ("lghi\t%4,%3", op);
9240 output_asm_insn ("ag\t%4,0(%1)", op);
9241 output_asm_insn ("ag\t%1,0(%4)", op);
9242 }
9243 else if (CONST_OK_FOR_Os (vcall_offset))
9244 {
9245 output_asm_insn ("lgfi\t%4,%3", op);
9246 output_asm_insn ("ag\t%4,0(%1)", op);
9247 output_asm_insn ("ag\t%1,0(%4)", op);
9248 }
9249 else
9250 {
9251 op[7] = gen_label_rtx ();
9252 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9253 output_asm_insn ("ag\t%4,0(%1)", op);
9254 output_asm_insn ("ag\t%1,0(%4)", op);
9255 }
9256 }
9257
9258 /* Jump to target. */
9259 output_asm_insn ("jg\t%0", op);
9260
9261 /* Output literal pool if required. */
9262 if (op[5])
9263 {
9264 output_asm_insn (".align\t4", op);
9265 targetm.asm_out.internal_label (file, "L",
9266 CODE_LABEL_NUMBER (op[5]));
9267 }
9268 if (op[6])
9269 {
9270 targetm.asm_out.internal_label (file, "L",
9271 CODE_LABEL_NUMBER (op[6]));
9272 output_asm_insn (".long\t%2", op);
9273 }
9274 if (op[7])
9275 {
9276 targetm.asm_out.internal_label (file, "L",
9277 CODE_LABEL_NUMBER (op[7]));
9278 output_asm_insn (".long\t%3", op);
9279 }
9280 }
9281 else
9282 {
9283 /* Setup base pointer if required. */
9284 if (!vcall_offset
9285 || (!DISP_IN_RANGE (delta)
9286 && !CONST_OK_FOR_K (delta)
9287 && !CONST_OK_FOR_Os (delta))
9288 || (!DISP_IN_RANGE (delta)
9289 && !CONST_OK_FOR_K (vcall_offset)
9290 && !CONST_OK_FOR_Os (vcall_offset)))
9291 {
9292 op[5] = gen_label_rtx ();
9293 output_asm_insn ("basr\t%4,0", op);
9294 targetm.asm_out.internal_label (file, "L",
9295 CODE_LABEL_NUMBER (op[5]));
9296 }
9297
9298 /* Add DELTA to this pointer. */
9299 if (delta)
9300 {
9301 if (CONST_OK_FOR_J (delta))
9302 output_asm_insn ("la\t%1,%2(%1)", op);
9303 else if (DISP_IN_RANGE (delta))
9304 output_asm_insn ("lay\t%1,%2(%1)", op);
9305 else if (CONST_OK_FOR_K (delta))
9306 output_asm_insn ("ahi\t%1,%2", op);
9307 else if (CONST_OK_FOR_Os (delta))
9308 output_asm_insn ("afi\t%1,%2", op);
9309 else
9310 {
9311 op[6] = gen_label_rtx ();
9312 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9313 }
9314 }
9315
9316 /* Perform vcall adjustment. */
9317 if (vcall_offset)
9318 {
9319 if (CONST_OK_FOR_J (vcall_offset))
9320 {
9321 output_asm_insn ("l\t%4,0(%1)", op);
9322 output_asm_insn ("a\t%1,%3(%4)", op);
9323 }
9324 else if (DISP_IN_RANGE (vcall_offset))
9325 {
9326 output_asm_insn ("l\t%4,0(%1)", op);
9327 output_asm_insn ("ay\t%1,%3(%4)", op);
9328 }
9329 else if (CONST_OK_FOR_K (vcall_offset))
9330 {
9331 output_asm_insn ("lhi\t%4,%3", op);
9332 output_asm_insn ("a\t%4,0(%1)", op);
9333 output_asm_insn ("a\t%1,0(%4)", op);
9334 }
9335 else if (CONST_OK_FOR_Os (vcall_offset))
9336 {
9337 output_asm_insn ("iilf\t%4,%3", op);
9338 output_asm_insn ("a\t%4,0(%1)", op);
9339 output_asm_insn ("a\t%1,0(%4)", op);
9340 }
9341 else
9342 {
9343 op[7] = gen_label_rtx ();
9344 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9345 output_asm_insn ("a\t%4,0(%1)", op);
9346 output_asm_insn ("a\t%1,0(%4)", op);
9347 }
9348
9349 /* We had to clobber the base pointer register.
9350 Re-setup the base pointer (with a different base). */
9351 op[5] = gen_label_rtx ();
9352 output_asm_insn ("basr\t%4,0", op);
9353 targetm.asm_out.internal_label (file, "L",
9354 CODE_LABEL_NUMBER (op[5]));
9355 }
9356
9357 /* Jump to target. */
9358 op[8] = gen_label_rtx ();
9359
9360 if (!flag_pic)
9361 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9362 else if (!nonlocal)
9363 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9364 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9365 else if (flag_pic == 1)
9366 {
9367 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9368 output_asm_insn ("l\t%4,%0(%4)", op);
9369 }
9370 else if (flag_pic == 2)
9371 {
9372 op[9] = gen_rtx_REG (Pmode, 0);
9373 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9374 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9375 output_asm_insn ("ar\t%4,%9", op);
9376 output_asm_insn ("l\t%4,0(%4)", op);
9377 }
9378
9379 output_asm_insn ("br\t%4", op);
9380
9381 /* Output literal pool. */
9382 output_asm_insn (".align\t4", op);
9383
9384 if (nonlocal && flag_pic == 2)
9385 output_asm_insn (".long\t%0", op);
9386 if (nonlocal)
9387 {
9388 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9389 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9390 }
9391
9392 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9393 if (!flag_pic)
9394 output_asm_insn (".long\t%0", op);
9395 else
9396 output_asm_insn (".long\t%0-%5", op);
9397
9398 if (op[6])
9399 {
9400 targetm.asm_out.internal_label (file, "L",
9401 CODE_LABEL_NUMBER (op[6]));
9402 output_asm_insn (".long\t%2", op);
9403 }
9404 if (op[7])
9405 {
9406 targetm.asm_out.internal_label (file, "L",
9407 CODE_LABEL_NUMBER (op[7]));
9408 output_asm_insn (".long\t%3", op);
9409 }
9410 }
9411 final_end_function ();
9412 }
9413
9414 static bool
9415 s390_valid_pointer_mode (enum machine_mode mode)
9416 {
9417 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9418 }
9419
9420 /* Checks whether the given CALL_EXPR would use a caller
9421 saved register. This is used to decide whether sibling call
9422 optimization could be performed on the respective function
9423 call. */
9424
9425 static bool
9426 s390_call_saved_register_used (tree call_expr)
9427 {
9428 CUMULATIVE_ARGS cum;
9429 tree parameter;
9430 enum machine_mode mode;
9431 tree type;
9432 rtx parm_rtx;
9433 int reg, i;
9434
9435 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9436
9437 for (i = 0; i < call_expr_nargs (call_expr); i++)
9438 {
9439 parameter = CALL_EXPR_ARG (call_expr, i);
9440 gcc_assert (parameter);
9441
9442 /* For an undeclared variable passed as parameter we will get
9443 an ERROR_MARK node here. */
9444 if (TREE_CODE (parameter) == ERROR_MARK)
9445 return true;
9446
9447 type = TREE_TYPE (parameter);
9448 gcc_assert (type);
9449
9450 mode = TYPE_MODE (type);
9451 gcc_assert (mode);
9452
9453 if (pass_by_reference (&cum, mode, type, true))
9454 {
9455 mode = Pmode;
9456 type = build_pointer_type (type);
9457 }
9458
9459 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9460
9461 s390_function_arg_advance (&cum, mode, type, 0);
9462
9463 if (!parm_rtx)
9464 continue;
9465
9466 if (REG_P (parm_rtx))
9467 {
9468 for (reg = 0;
9469 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9470 reg++)
9471 if (!call_used_regs[reg + REGNO (parm_rtx)])
9472 return true;
9473 }
9474
9475 if (GET_CODE (parm_rtx) == PARALLEL)
9476 {
9477 int i;
9478
9479 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9480 {
9481 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9482
9483 gcc_assert (REG_P (r));
9484
9485 for (reg = 0;
9486 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9487 reg++)
9488 if (!call_used_regs[reg + REGNO (r)])
9489 return true;
9490 }
9491 }
9492
9493 }
9494 return false;
9495 }
9496
9497 /* Return true if the given call expression can be
9498 turned into a sibling call.
9499 DECL holds the declaration of the function to be called whereas
9500 EXP is the call expression itself. */
9501
9502 static bool
9503 s390_function_ok_for_sibcall (tree decl, tree exp)
9504 {
9505 /* The TPF epilogue uses register 1. */
9506 if (TARGET_TPF_PROFILING)
9507 return false;
9508
9509 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9510 which would have to be restored before the sibcall. */
9511 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9512 return false;
9513
9514 /* Register 6 on s390 is available as an argument register but unfortunately
9515 "caller saved". This makes functions needing this register for arguments
9516 not suitable for sibcalls. */
9517 return !s390_call_saved_register_used (exp);
9518 }
9519
9520 /* Return the fixed registers used for condition codes. */
9521
9522 static bool
9523 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9524 {
9525 *p1 = CC_REGNUM;
9526 *p2 = INVALID_REGNUM;
9527
9528 return true;
9529 }
9530
9531 /* This function is used by the call expanders of the machine description.
9532 It emits the call insn itself together with the necessary operations
9533 to adjust the target address and returns the emitted insn.
9534 ADDR_LOCATION is the target address rtx
9535 TLS_CALL the location of the thread-local symbol
9536 RESULT_REG the register where the result of the call should be stored
9537 RETADDR_REG the register where the return address should be stored
9538 If this parameter is NULL_RTX the call is considered
9539 to be a sibling call. */
9540
9541 rtx
9542 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9543 rtx retaddr_reg)
9544 {
9545 bool plt_call = false;
9546 rtx insn;
9547 rtx call;
9548 rtx clobber;
9549 rtvec vec;
9550
9551 /* Direct function calls need special treatment. */
9552 if (GET_CODE (addr_location) == SYMBOL_REF)
9553 {
9554 /* When calling a global routine in PIC mode, we must
9555 replace the symbol itself with the PLT stub. */
9556 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9557 {
9558 if (retaddr_reg != NULL_RTX)
9559 {
9560 addr_location = gen_rtx_UNSPEC (Pmode,
9561 gen_rtvec (1, addr_location),
9562 UNSPEC_PLT);
9563 addr_location = gen_rtx_CONST (Pmode, addr_location);
9564 plt_call = true;
9565 }
9566 else
9567 /* For -fpic code the PLT entries might use r12 which is
9568 call-saved. Therefore we cannot do a sibcall when
9569 calling directly using a symbol ref. When reaching
9570 this point we decided (in s390_function_ok_for_sibcall)
9571 to do a sibcall for a function pointer but one of the
9572 optimizers was able to get rid of the function pointer
9573 by propagating the symbol ref into the call. This
9574 optimization is illegal for S/390 so we turn the direct
9575 call into a indirect call again. */
9576 addr_location = force_reg (Pmode, addr_location);
9577 }
9578
9579 /* Unless we can use the bras(l) insn, force the
9580 routine address into a register. */
9581 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9582 {
9583 if (flag_pic)
9584 addr_location = legitimize_pic_address (addr_location, 0);
9585 else
9586 addr_location = force_reg (Pmode, addr_location);
9587 }
9588 }
9589
9590 /* If it is already an indirect call or the code above moved the
9591 SYMBOL_REF to somewhere else make sure the address can be found in
9592 register 1. */
9593 if (retaddr_reg == NULL_RTX
9594 && GET_CODE (addr_location) != SYMBOL_REF
9595 && !plt_call)
9596 {
9597 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9598 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9599 }
9600
9601 addr_location = gen_rtx_MEM (QImode, addr_location);
9602 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9603
9604 if (result_reg != NULL_RTX)
9605 call = gen_rtx_SET (VOIDmode, result_reg, call);
9606
9607 if (retaddr_reg != NULL_RTX)
9608 {
9609 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9610
9611 if (tls_call != NULL_RTX)
9612 vec = gen_rtvec (3, call, clobber,
9613 gen_rtx_USE (VOIDmode, tls_call));
9614 else
9615 vec = gen_rtvec (2, call, clobber);
9616
9617 call = gen_rtx_PARALLEL (VOIDmode, vec);
9618 }
9619
9620 insn = emit_call_insn (call);
9621
9622 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9623 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9624 {
9625 /* s390_function_ok_for_sibcall should
9626 have denied sibcalls in this case. */
9627 gcc_assert (retaddr_reg != NULL_RTX);
9628
9629 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9630 }
9631 return insn;
9632 }
9633
9634 /* Implement CONDITIONAL_REGISTER_USAGE. */
9635
9636 void
9637 s390_conditional_register_usage (void)
9638 {
9639 int i;
9640
9641 if (flag_pic)
9642 {
9643 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9644 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9645 }
9646 if (TARGET_CPU_ZARCH)
9647 {
9648 fixed_regs[BASE_REGNUM] = 0;
9649 call_used_regs[BASE_REGNUM] = 0;
9650 fixed_regs[RETURN_REGNUM] = 0;
9651 call_used_regs[RETURN_REGNUM] = 0;
9652 }
9653 if (TARGET_64BIT)
9654 {
9655 for (i = 24; i < 32; i++)
9656 call_used_regs[i] = call_really_used_regs[i] = 0;
9657 }
9658 else
9659 {
9660 for (i = 18; i < 20; i++)
9661 call_used_regs[i] = call_really_used_regs[i] = 0;
9662 }
9663
9664 if (TARGET_SOFT_FLOAT)
9665 {
9666 for (i = 16; i < 32; i++)
9667 call_used_regs[i] = fixed_regs[i] = 1;
9668 }
9669 }
9670
9671 /* Corresponding function to eh_return expander. */
9672
9673 static GTY(()) rtx s390_tpf_eh_return_symbol;
9674 void
9675 s390_emit_tpf_eh_return (rtx target)
9676 {
9677 rtx insn, reg;
9678
9679 if (!s390_tpf_eh_return_symbol)
9680 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9681
9682 reg = gen_rtx_REG (Pmode, 2);
9683
9684 emit_move_insn (reg, target);
9685 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9686 gen_rtx_REG (Pmode, RETURN_REGNUM));
9687 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9688
9689 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9690 }
9691
9692 /* Rework the prologue/epilogue to avoid saving/restoring
9693 registers unnecessarily. */
9694
9695 static void
9696 s390_optimize_prologue (void)
9697 {
9698 rtx insn, new_insn, next_insn;
9699
9700 /* Do a final recompute of the frame-related data. */
9701
9702 s390_update_frame_layout ();
9703
9704 /* If all special registers are in fact used, there's nothing we
9705 can do, so no point in walking the insn list. */
9706
9707 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9708 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9709 && (TARGET_CPU_ZARCH
9710 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9711 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9712 return;
9713
9714 /* Search for prologue/epilogue insns and replace them. */
9715
9716 for (insn = get_insns (); insn; insn = next_insn)
9717 {
9718 int first, last, off;
9719 rtx set, base, offset;
9720
9721 next_insn = NEXT_INSN (insn);
9722
9723 if (GET_CODE (insn) != INSN)
9724 continue;
9725
9726 if (GET_CODE (PATTERN (insn)) == PARALLEL
9727 && store_multiple_operation (PATTERN (insn), VOIDmode))
9728 {
9729 set = XVECEXP (PATTERN (insn), 0, 0);
9730 first = REGNO (SET_SRC (set));
9731 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9732 offset = const0_rtx;
9733 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9734 off = INTVAL (offset);
9735
9736 if (GET_CODE (base) != REG || off < 0)
9737 continue;
9738 if (cfun_frame_layout.first_save_gpr != -1
9739 && (cfun_frame_layout.first_save_gpr < first
9740 || cfun_frame_layout.last_save_gpr > last))
9741 continue;
9742 if (REGNO (base) != STACK_POINTER_REGNUM
9743 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9744 continue;
9745 if (first > BASE_REGNUM || last < BASE_REGNUM)
9746 continue;
9747
9748 if (cfun_frame_layout.first_save_gpr != -1)
9749 {
9750 new_insn = save_gprs (base,
9751 off + (cfun_frame_layout.first_save_gpr
9752 - first) * UNITS_PER_LONG,
9753 cfun_frame_layout.first_save_gpr,
9754 cfun_frame_layout.last_save_gpr);
9755 new_insn = emit_insn_before (new_insn, insn);
9756 INSN_ADDRESSES_NEW (new_insn, -1);
9757 }
9758
9759 remove_insn (insn);
9760 continue;
9761 }
9762
9763 if (cfun_frame_layout.first_save_gpr == -1
9764 && GET_CODE (PATTERN (insn)) == SET
9765 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9766 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9767 || (!TARGET_CPU_ZARCH
9768 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9769 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9770 {
9771 set = PATTERN (insn);
9772 first = REGNO (SET_SRC (set));
9773 offset = const0_rtx;
9774 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9775 off = INTVAL (offset);
9776
9777 if (GET_CODE (base) != REG || off < 0)
9778 continue;
9779 if (REGNO (base) != STACK_POINTER_REGNUM
9780 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9781 continue;
9782
9783 remove_insn (insn);
9784 continue;
9785 }
9786
9787 if (GET_CODE (PATTERN (insn)) == PARALLEL
9788 && load_multiple_operation (PATTERN (insn), VOIDmode))
9789 {
9790 set = XVECEXP (PATTERN (insn), 0, 0);
9791 first = REGNO (SET_DEST (set));
9792 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9793 offset = const0_rtx;
9794 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9795 off = INTVAL (offset);
9796
9797 if (GET_CODE (base) != REG || off < 0)
9798 continue;
9799 if (cfun_frame_layout.first_restore_gpr != -1
9800 && (cfun_frame_layout.first_restore_gpr < first
9801 || cfun_frame_layout.last_restore_gpr > last))
9802 continue;
9803 if (REGNO (base) != STACK_POINTER_REGNUM
9804 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9805 continue;
9806 if (first > BASE_REGNUM || last < BASE_REGNUM)
9807 continue;
9808
9809 if (cfun_frame_layout.first_restore_gpr != -1)
9810 {
9811 new_insn = restore_gprs (base,
9812 off + (cfun_frame_layout.first_restore_gpr
9813 - first) * UNITS_PER_LONG,
9814 cfun_frame_layout.first_restore_gpr,
9815 cfun_frame_layout.last_restore_gpr);
9816 new_insn = emit_insn_before (new_insn, insn);
9817 INSN_ADDRESSES_NEW (new_insn, -1);
9818 }
9819
9820 remove_insn (insn);
9821 continue;
9822 }
9823
9824 if (cfun_frame_layout.first_restore_gpr == -1
9825 && GET_CODE (PATTERN (insn)) == SET
9826 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9827 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9828 || (!TARGET_CPU_ZARCH
9829 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9830 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9831 {
9832 set = PATTERN (insn);
9833 first = REGNO (SET_DEST (set));
9834 offset = const0_rtx;
9835 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9836 off = INTVAL (offset);
9837
9838 if (GET_CODE (base) != REG || off < 0)
9839 continue;
9840 if (REGNO (base) != STACK_POINTER_REGNUM
9841 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9842 continue;
9843
9844 remove_insn (insn);
9845 continue;
9846 }
9847 }
9848 }
9849
9850 /* On z10 the dynamic branch prediction must see the backward jump in
9851 a window of 384 bytes. If not it falls back to the static
9852 prediction. This function rearranges the loop backward branch in a
9853 way which makes the static prediction always correct. The function
9854 returns true if it added an instruction. */
9855 static bool
9856 s390_z10_fix_long_loop_prediction (rtx insn)
9857 {
9858 rtx set = single_set (insn);
9859 rtx code_label, label_ref, new_label;
9860 rtx uncond_jump;
9861 rtx cur_insn;
9862 rtx tmp;
9863 int distance;
9864
9865 /* This will exclude branch on count and branch on index patterns
9866 since these are correctly statically predicted. */
9867 if (!set
9868 || SET_DEST (set) != pc_rtx
9869 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9870 return false;
9871
9872 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9873 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9874
9875 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9876
9877 code_label = XEXP (label_ref, 0);
9878
9879 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9880 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9881 || (INSN_ADDRESSES (INSN_UID (insn))
9882 - INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE))
9883 return false;
9884
9885 for (distance = 0, cur_insn = PREV_INSN (insn);
9886 distance < Z10_PREDICT_DISTANCE - 6;
9887 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9888 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
9889 return false;
9890
9891 new_label = gen_label_rtx ();
9892 uncond_jump = emit_jump_insn_after (
9893 gen_rtx_SET (VOIDmode, pc_rtx,
9894 gen_rtx_LABEL_REF (VOIDmode, code_label)),
9895 insn);
9896 emit_label_after (new_label, uncond_jump);
9897
9898 tmp = XEXP (SET_SRC (set), 1);
9899 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
9900 XEXP (SET_SRC (set), 2) = tmp;
9901 INSN_CODE (insn) = -1;
9902
9903 XEXP (label_ref, 0) = new_label;
9904 JUMP_LABEL (insn) = new_label;
9905 JUMP_LABEL (uncond_jump) = code_label;
9906
9907 return true;
9908 }
9909
9910 /* Returns 1 if INSN reads the value of REG for purposes not related
9911 to addressing of memory, and 0 otherwise. */
9912 static int
9913 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9914 {
9915 return reg_referenced_p (reg, PATTERN (insn))
9916 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9917 }
9918
9919 /* Starting from INSN find_cond_jump looks downwards in the insn
9920 stream for a single jump insn which is the last user of the
9921 condition code set in INSN. */
9922 static rtx
9923 find_cond_jump (rtx insn)
9924 {
9925 for (; insn; insn = NEXT_INSN (insn))
9926 {
9927 rtx ite, cc;
9928
9929 if (LABEL_P (insn))
9930 break;
9931
9932 if (!JUMP_P (insn))
9933 {
9934 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9935 break;
9936 continue;
9937 }
9938
9939 /* This will be triggered by a return. */
9940 if (GET_CODE (PATTERN (insn)) != SET)
9941 break;
9942
9943 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9944 ite = SET_SRC (PATTERN (insn));
9945
9946 if (GET_CODE (ite) != IF_THEN_ELSE)
9947 break;
9948
9949 cc = XEXP (XEXP (ite, 0), 0);
9950 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9951 break;
9952
9953 if (find_reg_note (insn, REG_DEAD, cc))
9954 return insn;
9955 break;
9956 }
9957
9958 return NULL_RTX;
9959 }
9960
9961 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9962 the semantics does not change. If NULL_RTX is passed as COND the
9963 function tries to find the conditional jump starting with INSN. */
9964 static void
9965 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9966 {
9967 rtx tmp = *op0;
9968
9969 if (cond == NULL_RTX)
9970 {
9971 rtx jump = find_cond_jump (NEXT_INSN (insn));
9972 jump = jump ? single_set (jump) : NULL_RTX;
9973
9974 if (jump == NULL_RTX)
9975 return;
9976
9977 cond = XEXP (XEXP (jump, 1), 0);
9978 }
9979
9980 *op0 = *op1;
9981 *op1 = tmp;
9982 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9983 }
9984
9985 /* On z10, instructions of the compare-and-branch family have the
9986 property to access the register occurring as second operand with
9987 its bits complemented. If such a compare is grouped with a second
9988 instruction that accesses the same register non-complemented, and
9989 if that register's value is delivered via a bypass, then the
9990 pipeline recycles, thereby causing significant performance decline.
9991 This function locates such situations and exchanges the two
9992 operands of the compare. The function return true whenever it
9993 added an insn. */
9994 static bool
9995 s390_z10_optimize_cmp (rtx insn)
9996 {
9997 rtx prev_insn, next_insn;
9998 bool insn_added_p = false;
9999 rtx cond, *op0, *op1;
10000
10001 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10002 {
10003 /* Handle compare and branch and branch on count
10004 instructions. */
10005 rtx pattern = single_set (insn);
10006
10007 if (!pattern
10008 || SET_DEST (pattern) != pc_rtx
10009 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10010 return false;
10011
10012 cond = XEXP (SET_SRC (pattern), 0);
10013 op0 = &XEXP (cond, 0);
10014 op1 = &XEXP (cond, 1);
10015 }
10016 else if (GET_CODE (PATTERN (insn)) == SET)
10017 {
10018 rtx src, dest;
10019
10020 /* Handle normal compare instructions. */
10021 src = SET_SRC (PATTERN (insn));
10022 dest = SET_DEST (PATTERN (insn));
10023
10024 if (!REG_P (dest)
10025 || !CC_REGNO_P (REGNO (dest))
10026 || GET_CODE (src) != COMPARE)
10027 return false;
10028
10029 /* s390_swap_cmp will try to find the conditional
10030 jump when passing NULL_RTX as condition. */
10031 cond = NULL_RTX;
10032 op0 = &XEXP (src, 0);
10033 op1 = &XEXP (src, 1);
10034 }
10035 else
10036 return false;
10037
10038 if (!REG_P (*op0) || !REG_P (*op1))
10039 return false;
10040
10041 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10042 return false;
10043
10044 /* Swap the COMPARE arguments and its mask if there is a
10045 conflicting access in the previous insn. */
10046 prev_insn = prev_active_insn (insn);
10047 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10048 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10049 s390_swap_cmp (cond, op0, op1, insn);
10050
10051 /* Check if there is a conflict with the next insn. If there
10052 was no conflict with the previous insn, then swap the
10053 COMPARE arguments and its mask. If we already swapped
10054 the operands, or if swapping them would cause a conflict
10055 with the previous insn, issue a NOP after the COMPARE in
10056 order to separate the two instuctions. */
10057 next_insn = next_active_insn (insn);
10058 if (next_insn != NULL_RTX && INSN_P (next_insn)
10059 && s390_non_addr_reg_read_p (*op1, next_insn))
10060 {
10061 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10062 && s390_non_addr_reg_read_p (*op0, prev_insn))
10063 {
10064 if (REGNO (*op1) == 0)
10065 emit_insn_after (gen_nop1 (), insn);
10066 else
10067 emit_insn_after (gen_nop (), insn);
10068 insn_added_p = true;
10069 }
10070 else
10071 s390_swap_cmp (cond, op0, op1, insn);
10072 }
10073 return insn_added_p;
10074 }
10075
10076 /* Perform machine-dependent processing. */
10077
10078 static void
10079 s390_reorg (void)
10080 {
10081 bool pool_overflow = false;
10082
10083 /* Make sure all splits have been performed; splits after
10084 machine_dependent_reorg might confuse insn length counts. */
10085 split_all_insns_noflow ();
10086
10087 /* Install the main literal pool and the associated base
10088 register load insns.
10089
10090 In addition, there are two problematic situations we need
10091 to correct:
10092
10093 - the literal pool might be > 4096 bytes in size, so that
10094 some of its elements cannot be directly accessed
10095
10096 - a branch target might be > 64K away from the branch, so that
10097 it is not possible to use a PC-relative instruction.
10098
10099 To fix those, we split the single literal pool into multiple
10100 pool chunks, reloading the pool base register at various
10101 points throughout the function to ensure it always points to
10102 the pool chunk the following code expects, and / or replace
10103 PC-relative branches by absolute branches.
10104
10105 However, the two problems are interdependent: splitting the
10106 literal pool can move a branch further away from its target,
10107 causing the 64K limit to overflow, and on the other hand,
10108 replacing a PC-relative branch by an absolute branch means
10109 we need to put the branch target address into the literal
10110 pool, possibly causing it to overflow.
10111
10112 So, we loop trying to fix up both problems until we manage
10113 to satisfy both conditions at the same time. Note that the
10114 loop is guaranteed to terminate as every pass of the loop
10115 strictly decreases the total number of PC-relative branches
10116 in the function. (This is not completely true as there
10117 might be branch-over-pool insns introduced by chunkify_start.
10118 Those never need to be split however.) */
10119
10120 for (;;)
10121 {
10122 struct constant_pool *pool = NULL;
10123
10124 /* Collect the literal pool. */
10125 if (!pool_overflow)
10126 {
10127 pool = s390_mainpool_start ();
10128 if (!pool)
10129 pool_overflow = true;
10130 }
10131
10132 /* If literal pool overflowed, start to chunkify it. */
10133 if (pool_overflow)
10134 pool = s390_chunkify_start ();
10135
10136 /* Split out-of-range branches. If this has created new
10137 literal pool entries, cancel current chunk list and
10138 recompute it. zSeries machines have large branch
10139 instructions, so we never need to split a branch. */
10140 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10141 {
10142 if (pool_overflow)
10143 s390_chunkify_cancel (pool);
10144 else
10145 s390_mainpool_cancel (pool);
10146
10147 continue;
10148 }
10149
10150 /* If we made it up to here, both conditions are satisfied.
10151 Finish up literal pool related changes. */
10152 if (pool_overflow)
10153 s390_chunkify_finish (pool);
10154 else
10155 s390_mainpool_finish (pool);
10156
10157 /* We're done splitting branches. */
10158 cfun->machine->split_branches_pending_p = false;
10159 break;
10160 }
10161
10162 /* Generate out-of-pool execute target insns. */
10163 if (TARGET_CPU_ZARCH)
10164 {
10165 rtx insn, label, target;
10166
10167 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10168 {
10169 label = s390_execute_label (insn);
10170 if (!label)
10171 continue;
10172
10173 gcc_assert (label != const0_rtx);
10174
10175 target = emit_label (XEXP (label, 0));
10176 INSN_ADDRESSES_NEW (target, -1);
10177
10178 target = emit_insn (s390_execute_target (insn));
10179 INSN_ADDRESSES_NEW (target, -1);
10180 }
10181 }
10182
10183 /* Try to optimize prologue and epilogue further. */
10184 s390_optimize_prologue ();
10185
10186 /* Walk over the insns and do some z10 specific changes. */
10187 if (s390_tune == PROCESSOR_2097_Z10)
10188 {
10189 rtx insn;
10190 bool insn_added_p = false;
10191
10192 /* The insn lengths and addresses have to be up to date for the
10193 following manipulations. */
10194 shorten_branches (get_insns ());
10195
10196 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10197 {
10198 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10199 continue;
10200
10201 if (JUMP_P (insn))
10202 insn_added_p |= s390_z10_fix_long_loop_prediction (insn);
10203
10204 if (GET_CODE (PATTERN (insn)) == PARALLEL
10205 || GET_CODE (PATTERN (insn)) == SET)
10206 insn_added_p |= s390_z10_optimize_cmp (insn);
10207 }
10208
10209 /* Adjust branches if we added new instructions. */
10210 if (insn_added_p)
10211 shorten_branches (get_insns ());
10212 }
10213 }
10214
10215 /* Return true if INSN is a fp load insn writing register REGNO. */
10216 static inline bool
10217 s390_fpload_toreg (rtx insn, unsigned int regno)
10218 {
10219 rtx set;
10220 enum attr_type flag = s390_safe_attr_type (insn);
10221
10222 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10223 return false;
10224
10225 set = single_set (insn);
10226
10227 if (set == NULL_RTX)
10228 return false;
10229
10230 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10231 return false;
10232
10233 if (REGNO (SET_DEST (set)) != regno)
10234 return false;
10235
10236 return true;
10237 }
10238
10239 /* This value describes the distance to be avoided between an
10240 aritmetic fp instruction and an fp load writing the same register.
10241 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10242 fine but the exact value has to be avoided. Otherwise the FP
10243 pipeline will throw an exception causing a major penalty. */
10244 #define Z10_EARLYLOAD_DISTANCE 7
10245
10246 /* Rearrange the ready list in order to avoid the situation described
10247 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10248 moved to the very end of the ready list. */
10249 static void
10250 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10251 {
10252 unsigned int regno;
10253 int nready = *nready_p;
10254 rtx tmp;
10255 int i;
10256 rtx insn;
10257 rtx set;
10258 enum attr_type flag;
10259 int distance;
10260
10261 /* Skip DISTANCE - 1 active insns. */
10262 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10263 distance > 0 && insn != NULL_RTX;
10264 distance--, insn = prev_active_insn (insn))
10265 if (CALL_P (insn) || JUMP_P (insn))
10266 return;
10267
10268 if (insn == NULL_RTX)
10269 return;
10270
10271 set = single_set (insn);
10272
10273 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10274 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10275 return;
10276
10277 flag = s390_safe_attr_type (insn);
10278
10279 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10280 return;
10281
10282 regno = REGNO (SET_DEST (set));
10283 i = nready - 1;
10284
10285 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10286 i--;
10287
10288 if (!i)
10289 return;
10290
10291 tmp = ready[i];
10292 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10293 ready[0] = tmp;
10294 }
10295
10296 /* This function is called via hook TARGET_SCHED_REORDER before
10297 issueing one insn from list READY which contains *NREADYP entries.
10298 For target z10 it reorders load instructions to avoid early load
10299 conflicts in the floating point pipeline */
10300 static int
10301 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10302 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10303 {
10304 if (s390_tune == PROCESSOR_2097_Z10)
10305 if (reload_completed && *nreadyp > 1)
10306 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10307
10308 return s390_issue_rate ();
10309 }
10310
10311 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10312 the scheduler has issued INSN. It stores the last issued insn into
10313 last_scheduled_insn in order to make it available for
10314 s390_sched_reorder. */
10315 static int
10316 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10317 int verbose ATTRIBUTE_UNUSED,
10318 rtx insn, int more)
10319 {
10320 last_scheduled_insn = insn;
10321
10322 if (GET_CODE (PATTERN (insn)) != USE
10323 && GET_CODE (PATTERN (insn)) != CLOBBER)
10324 return more - 1;
10325 else
10326 return more;
10327 }
10328
10329 static void
10330 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10331 int verbose ATTRIBUTE_UNUSED,
10332 int max_ready ATTRIBUTE_UNUSED)
10333 {
10334 last_scheduled_insn = NULL_RTX;
10335 }
10336
10337 /* This function checks the whole of insn X for memory references. The
10338 function always returns zero because the framework it is called
10339 from would stop recursively analyzing the insn upon a return value
10340 other than zero. The real result of this function is updating
10341 counter variable MEM_COUNT. */
10342 static int
10343 check_dpu (rtx *x, unsigned *mem_count)
10344 {
10345 if (*x != NULL_RTX && MEM_P (*x))
10346 (*mem_count)++;
10347 return 0;
10348 }
10349
10350 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10351 a new number struct loop *loop should be unrolled if tuned for the z10
10352 cpu. The loop is analyzed for memory accesses by calling check_dpu for
10353 each rtx of the loop. Depending on the loop_depth and the amount of
10354 memory accesses a new number <=nunroll is returned to improve the
10355 behaviour of the hardware prefetch unit. */
10356 static unsigned
10357 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10358 {
10359 basic_block *bbs;
10360 rtx insn;
10361 unsigned i;
10362 unsigned mem_count = 0;
10363
10364 /* Only z10 needs special handling. */
10365 if (s390_tune != PROCESSOR_2097_Z10)
10366 return nunroll;
10367
10368 /* Count the number of memory references within the loop body. */
10369 bbs = get_loop_body (loop);
10370 for (i = 0; i < loop->num_nodes; i++)
10371 {
10372 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10373 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10374 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10375 }
10376 free (bbs);
10377
10378 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10379 if (mem_count == 0)
10380 return nunroll;
10381
10382 switch (loop_depth(loop))
10383 {
10384 case 1:
10385 return MIN (nunroll, 28 / mem_count);
10386 case 2:
10387 return MIN (nunroll, 22 / mem_count);
10388 default:
10389 return MIN (nunroll, 16 / mem_count);
10390 }
10391 }
10392
10393 /* Initialize GCC target structure. */
10394
10395 #undef TARGET_ASM_ALIGNED_HI_OP
10396 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10397 #undef TARGET_ASM_ALIGNED_DI_OP
10398 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10399 #undef TARGET_ASM_INTEGER
10400 #define TARGET_ASM_INTEGER s390_assemble_integer
10401
10402 #undef TARGET_ASM_OPEN_PAREN
10403 #define TARGET_ASM_OPEN_PAREN ""
10404
10405 #undef TARGET_ASM_CLOSE_PAREN
10406 #define TARGET_ASM_CLOSE_PAREN ""
10407
10408 #undef TARGET_DEFAULT_TARGET_FLAGS
10409 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10410
10411 #undef TARGET_HANDLE_OPTION
10412 #define TARGET_HANDLE_OPTION s390_handle_option
10413
10414 #undef TARGET_ENCODE_SECTION_INFO
10415 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10416
10417 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10418 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10419
10420 #ifdef HAVE_AS_TLS
10421 #undef TARGET_HAVE_TLS
10422 #define TARGET_HAVE_TLS true
10423 #endif
10424 #undef TARGET_CANNOT_FORCE_CONST_MEM
10425 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10426
10427 #undef TARGET_DELEGITIMIZE_ADDRESS
10428 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10429
10430 #undef TARGET_LEGITIMIZE_ADDRESS
10431 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10432
10433 #undef TARGET_RETURN_IN_MEMORY
10434 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10435
10436 #undef TARGET_INIT_BUILTINS
10437 #define TARGET_INIT_BUILTINS s390_init_builtins
10438 #undef TARGET_EXPAND_BUILTIN
10439 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10440
10441 #undef TARGET_ASM_OUTPUT_MI_THUNK
10442 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10443 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10444 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10445
10446 #undef TARGET_SCHED_ADJUST_PRIORITY
10447 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10448 #undef TARGET_SCHED_ISSUE_RATE
10449 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10450 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10451 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10452
10453 #undef TARGET_SCHED_VARIABLE_ISSUE
10454 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10455 #undef TARGET_SCHED_REORDER
10456 #define TARGET_SCHED_REORDER s390_sched_reorder
10457 #undef TARGET_SCHED_INIT
10458 #define TARGET_SCHED_INIT s390_sched_init
10459
10460 #undef TARGET_CANNOT_COPY_INSN_P
10461 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10462 #undef TARGET_RTX_COSTS
10463 #define TARGET_RTX_COSTS s390_rtx_costs
10464 #undef TARGET_ADDRESS_COST
10465 #define TARGET_ADDRESS_COST s390_address_cost
10466
10467 #undef TARGET_MACHINE_DEPENDENT_REORG
10468 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10469
10470 #undef TARGET_VALID_POINTER_MODE
10471 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10472
10473 #undef TARGET_BUILD_BUILTIN_VA_LIST
10474 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10475 #undef TARGET_EXPAND_BUILTIN_VA_START
10476 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10477 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10478 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10479
10480 #undef TARGET_PROMOTE_FUNCTION_MODE
10481 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10482 #undef TARGET_PASS_BY_REFERENCE
10483 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10484
10485 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10486 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10487
10488 #undef TARGET_FIXED_CONDITION_CODE_REGS
10489 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10490
10491 #undef TARGET_CC_MODES_COMPATIBLE
10492 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10493
10494 #undef TARGET_INVALID_WITHIN_DOLOOP
10495 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10496
10497 #ifdef HAVE_AS_TLS
10498 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10499 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10500 #endif
10501
10502 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10503 #undef TARGET_MANGLE_TYPE
10504 #define TARGET_MANGLE_TYPE s390_mangle_type
10505 #endif
10506
10507 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10508 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10509
10510 #undef TARGET_SECONDARY_RELOAD
10511 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10512
10513 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10514 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10515
10516 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10517 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10518
10519 #undef TARGET_LEGITIMATE_ADDRESS_P
10520 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10521
10522 #undef TARGET_CAN_ELIMINATE
10523 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10524
10525 #undef TARGET_LOOP_UNROLL_ADJUST
10526 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10527
10528 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10529 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10530 #undef TARGET_TRAMPOLINE_INIT
10531 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10532
10533 #undef TARGET_UNWIND_WORD_MODE
10534 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10535
10536 struct gcc_target targetm = TARGET_INITIALIZER;
10537
10538 #include "gt-s390.h"