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tree.h (DECL_CHAIN): Define.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "gimple.h"
54 #include "df.h"
55 #include "params.h"
56 #include "cfgloop.h"
57
58
59 /* Define the specific costs for a given cpu. */
60
61 struct processor_costs
62 {
63 /* multiplication */
64 const int m; /* cost of an M instruction. */
65 const int mghi; /* cost of an MGHI instruction. */
66 const int mh; /* cost of an MH instruction. */
67 const int mhi; /* cost of an MHI instruction. */
68 const int ml; /* cost of an ML instruction. */
69 const int mr; /* cost of an MR instruction. */
70 const int ms; /* cost of an MS instruction. */
71 const int msg; /* cost of an MSG instruction. */
72 const int msgf; /* cost of an MSGF instruction. */
73 const int msgfr; /* cost of an MSGFR instruction. */
74 const int msgr; /* cost of an MSGR instruction. */
75 const int msr; /* cost of an MSR instruction. */
76 const int mult_df; /* cost of multiplication in DFmode. */
77 const int mxbr;
78 /* square root */
79 const int sqxbr; /* cost of square root in TFmode. */
80 const int sqdbr; /* cost of square root in DFmode. */
81 const int sqebr; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr; /* cost of multiply and add in DFmode. */
84 const int maebr; /* cost of multiply and add in SFmode. */
85 /* division */
86 const int dxbr;
87 const int ddbr;
88 const int debr;
89 const int dlgr;
90 const int dlr;
91 const int dr;
92 const int dsgfr;
93 const int dsgr;
94 };
95
96 const struct processor_costs *s390_cost;
97
98 static const
99 struct processor_costs z900_cost =
100 {
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
128 };
129
130 static const
131 struct processor_costs z990_cost =
132 {
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
160 };
161
162 static const
163 struct processor_costs z9_109_cost =
164 {
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
192 };
193
194 static const
195 struct processor_costs z10_cost =
196 {
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
224 };
225
226 extern int reload_completed;
227
228 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
229 static rtx last_scheduled_insn;
230
231 /* Structure used to hold the components of a S/390 memory
232 address. A legitimate address on S/390 is of the general
233 form
234 base + index + displacement
235 where any of the components is optional.
236
237 base and index are registers of the class ADDR_REGS,
238 displacement is an unsigned 12-bit immediate constant. */
239
240 struct s390_address
241 {
242 rtx base;
243 rtx indx;
244 rtx disp;
245 bool pointer;
246 bool literal_pool;
247 };
248
249 /* Which cpu are we tuning for. */
250 enum processor_type s390_tune = PROCESSOR_max;
251 int s390_tune_flags;
252 /* Which instruction set architecture to use. */
253 enum processor_type s390_arch;
254 int s390_arch_flags;
255
256 HOST_WIDE_INT s390_warn_framesize = 0;
257 HOST_WIDE_INT s390_stack_size = 0;
258 HOST_WIDE_INT s390_stack_guard = 0;
259
260 /* The following structure is embedded in the machine
261 specific part of struct function. */
262
263 struct GTY (()) s390_frame_layout
264 {
265 /* Offset within stack frame. */
266 HOST_WIDE_INT gprs_offset;
267 HOST_WIDE_INT f0_offset;
268 HOST_WIDE_INT f4_offset;
269 HOST_WIDE_INT f8_offset;
270 HOST_WIDE_INT backchain_offset;
271
272 /* Number of first and last gpr where slots in the register
273 save area are reserved for. */
274 int first_save_gpr_slot;
275 int last_save_gpr_slot;
276
277 /* Number of first and last gpr to be saved, restored. */
278 int first_save_gpr;
279 int first_restore_gpr;
280 int last_save_gpr;
281 int last_restore_gpr;
282
283 /* Bits standing for floating point registers. Set, if the
284 respective register has to be saved. Starting with reg 16 (f0)
285 at the rightmost bit.
286 Bit 15 - 8 7 6 5 4 3 2 1 0
287 fpr 15 - 8 7 5 3 1 6 4 2 0
288 reg 31 - 24 23 22 21 20 19 18 17 16 */
289 unsigned int fpr_bitmap;
290
291 /* Number of floating point registers f8-f15 which must be saved. */
292 int high_fprs;
293
294 /* Set if return address needs to be saved.
295 This flag is set by s390_return_addr_rtx if it could not use
296 the initial value of r14 and therefore depends on r14 saved
297 to the stack. */
298 bool save_return_addr_p;
299
300 /* Size of stack frame. */
301 HOST_WIDE_INT frame_size;
302 };
303
304 /* Define the structure for the machine field in struct function. */
305
306 struct GTY(()) machine_function
307 {
308 struct s390_frame_layout frame_layout;
309
310 /* Literal pool base register. */
311 rtx base_reg;
312
313 /* True if we may need to perform branch splitting. */
314 bool split_branches_pending_p;
315
316 /* Some local-dynamic TLS symbol name. */
317 const char *some_ld_name;
318
319 bool has_landing_pad_p;
320 };
321
322 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
323
324 #define cfun_frame_layout (cfun->machine->frame_layout)
325 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
326 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
327 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
328 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
329 (1 << (BITNUM)))
330 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
331 (1 << (BITNUM))))
332
333 /* Number of GPRs and FPRs used for argument passing. */
334 #define GP_ARG_NUM_REG 5
335 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
336
337 /* A couple of shortcuts. */
338 #define CONST_OK_FOR_J(x) \
339 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
340 #define CONST_OK_FOR_K(x) \
341 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
342 #define CONST_OK_FOR_Os(x) \
343 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
344 #define CONST_OK_FOR_Op(x) \
345 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
346 #define CONST_OK_FOR_On(x) \
347 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
348
349 #define REGNO_PAIR_OK(REGNO, MODE) \
350 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
351
352 /* That's the read ahead of the dynamic branch prediction unit in
353 bytes on a z10 CPU. */
354 #define Z10_PREDICT_DISTANCE 384
355
356 static enum machine_mode
357 s390_libgcc_cmp_return_mode (void)
358 {
359 return TARGET_64BIT ? DImode : SImode;
360 }
361
362 static enum machine_mode
363 s390_libgcc_shift_count_mode (void)
364 {
365 return TARGET_64BIT ? DImode : SImode;
366 }
367
368 static enum machine_mode
369 s390_unwind_word_mode (void)
370 {
371 return TARGET_64BIT ? DImode : SImode;
372 }
373
374 /* Return true if the back end supports mode MODE. */
375 static bool
376 s390_scalar_mode_supported_p (enum machine_mode mode)
377 {
378 /* In contrast to the default implementation reject TImode constants on 31bit
379 TARGET_ZARCH for ABI compliance. */
380 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
381 return false;
382
383 if (DECIMAL_FLOAT_MODE_P (mode))
384 return default_decimal_float_supported_p ();
385
386 return default_scalar_mode_supported_p (mode);
387 }
388
389 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
390
391 void
392 s390_set_has_landing_pad_p (bool value)
393 {
394 cfun->machine->has_landing_pad_p = value;
395 }
396
397 /* If two condition code modes are compatible, return a condition code
398 mode which is compatible with both. Otherwise, return
399 VOIDmode. */
400
401 static enum machine_mode
402 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
403 {
404 if (m1 == m2)
405 return m1;
406
407 switch (m1)
408 {
409 case CCZmode:
410 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
411 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
412 return m2;
413 return VOIDmode;
414
415 case CCSmode:
416 case CCUmode:
417 case CCTmode:
418 case CCSRmode:
419 case CCURmode:
420 case CCZ1mode:
421 if (m2 == CCZmode)
422 return m1;
423
424 return VOIDmode;
425
426 default:
427 return VOIDmode;
428 }
429 return VOIDmode;
430 }
431
432 /* Return true if SET either doesn't set the CC register, or else
433 the source and destination have matching CC modes and that
434 CC mode is at least as constrained as REQ_MODE. */
435
436 static bool
437 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
438 {
439 enum machine_mode set_mode;
440
441 gcc_assert (GET_CODE (set) == SET);
442
443 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
444 return 1;
445
446 set_mode = GET_MODE (SET_DEST (set));
447 switch (set_mode)
448 {
449 case CCSmode:
450 case CCSRmode:
451 case CCUmode:
452 case CCURmode:
453 case CCLmode:
454 case CCL1mode:
455 case CCL2mode:
456 case CCL3mode:
457 case CCT1mode:
458 case CCT2mode:
459 case CCT3mode:
460 if (req_mode != set_mode)
461 return 0;
462 break;
463
464 case CCZmode:
465 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
466 && req_mode != CCSRmode && req_mode != CCURmode)
467 return 0;
468 break;
469
470 case CCAPmode:
471 case CCANmode:
472 if (req_mode != CCAmode)
473 return 0;
474 break;
475
476 default:
477 gcc_unreachable ();
478 }
479
480 return (GET_MODE (SET_SRC (set)) == set_mode);
481 }
482
483 /* Return true if every SET in INSN that sets the CC register
484 has source and destination with matching CC modes and that
485 CC mode is at least as constrained as REQ_MODE.
486 If REQ_MODE is VOIDmode, always return false. */
487
488 bool
489 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
490 {
491 int i;
492
493 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
494 if (req_mode == VOIDmode)
495 return false;
496
497 if (GET_CODE (PATTERN (insn)) == SET)
498 return s390_match_ccmode_set (PATTERN (insn), req_mode);
499
500 if (GET_CODE (PATTERN (insn)) == PARALLEL)
501 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
502 {
503 rtx set = XVECEXP (PATTERN (insn), 0, i);
504 if (GET_CODE (set) == SET)
505 if (!s390_match_ccmode_set (set, req_mode))
506 return false;
507 }
508
509 return true;
510 }
511
512 /* If a test-under-mask instruction can be used to implement
513 (compare (and ... OP1) OP2), return the CC mode required
514 to do that. Otherwise, return VOIDmode.
515 MIXED is true if the instruction can distinguish between
516 CC1 and CC2 for mixed selected bits (TMxx), it is false
517 if the instruction cannot (TM). */
518
519 enum machine_mode
520 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
521 {
522 int bit0, bit1;
523
524 /* ??? Fixme: should work on CONST_DOUBLE as well. */
525 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
526 return VOIDmode;
527
528 /* Selected bits all zero: CC0.
529 e.g.: int a; if ((a & (16 + 128)) == 0) */
530 if (INTVAL (op2) == 0)
531 return CCTmode;
532
533 /* Selected bits all one: CC3.
534 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
535 if (INTVAL (op2) == INTVAL (op1))
536 return CCT3mode;
537
538 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
539 int a;
540 if ((a & (16 + 128)) == 16) -> CCT1
541 if ((a & (16 + 128)) == 128) -> CCT2 */
542 if (mixed)
543 {
544 bit1 = exact_log2 (INTVAL (op2));
545 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
546 if (bit0 != -1 && bit1 != -1)
547 return bit0 > bit1 ? CCT1mode : CCT2mode;
548 }
549
550 return VOIDmode;
551 }
552
553 /* Given a comparison code OP (EQ, NE, etc.) and the operands
554 OP0 and OP1 of a COMPARE, return the mode to be used for the
555 comparison. */
556
557 enum machine_mode
558 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
559 {
560 switch (code)
561 {
562 case EQ:
563 case NE:
564 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
565 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
566 return CCAPmode;
567 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
568 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
569 return CCAPmode;
570 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
571 || GET_CODE (op1) == NEG)
572 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
573 return CCLmode;
574
575 if (GET_CODE (op0) == AND)
576 {
577 /* Check whether we can potentially do it via TM. */
578 enum machine_mode ccmode;
579 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
580 if (ccmode != VOIDmode)
581 {
582 /* Relax CCTmode to CCZmode to allow fall-back to AND
583 if that turns out to be beneficial. */
584 return ccmode == CCTmode ? CCZmode : ccmode;
585 }
586 }
587
588 if (register_operand (op0, HImode)
589 && GET_CODE (op1) == CONST_INT
590 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
591 return CCT3mode;
592 if (register_operand (op0, QImode)
593 && GET_CODE (op1) == CONST_INT
594 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
595 return CCT3mode;
596
597 return CCZmode;
598
599 case LE:
600 case LT:
601 case GE:
602 case GT:
603 /* The only overflow condition of NEG and ABS happens when
604 -INT_MAX is used as parameter, which stays negative. So
605 we have an overflow from a positive value to a negative.
606 Using CCAP mode the resulting cc can be used for comparisons. */
607 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
608 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
609 return CCAPmode;
610
611 /* If constants are involved in an add instruction it is possible to use
612 the resulting cc for comparisons with zero. Knowing the sign of the
613 constant the overflow behavior gets predictable. e.g.:
614 int a, b; if ((b = a + c) > 0)
615 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
616 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
617 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
618 {
619 if (INTVAL (XEXP((op0), 1)) < 0)
620 return CCANmode;
621 else
622 return CCAPmode;
623 }
624 /* Fall through. */
625 case UNORDERED:
626 case ORDERED:
627 case UNEQ:
628 case UNLE:
629 case UNLT:
630 case UNGE:
631 case UNGT:
632 case LTGT:
633 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
634 && GET_CODE (op1) != CONST_INT)
635 return CCSRmode;
636 return CCSmode;
637
638 case LTU:
639 case GEU:
640 if (GET_CODE (op0) == PLUS
641 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
642 return CCL1mode;
643
644 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
645 && GET_CODE (op1) != CONST_INT)
646 return CCURmode;
647 return CCUmode;
648
649 case LEU:
650 case GTU:
651 if (GET_CODE (op0) == MINUS
652 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
653 return CCL2mode;
654
655 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
656 && GET_CODE (op1) != CONST_INT)
657 return CCURmode;
658 return CCUmode;
659
660 default:
661 gcc_unreachable ();
662 }
663 }
664
665 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
666 that we can implement more efficiently. */
667
668 void
669 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
670 {
671 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
672 if ((*code == EQ || *code == NE)
673 && *op1 == const0_rtx
674 && GET_CODE (*op0) == ZERO_EXTRACT
675 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
676 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
677 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
678 {
679 rtx inner = XEXP (*op0, 0);
680 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
681 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
682 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
683
684 if (len > 0 && len < modesize
685 && pos >= 0 && pos + len <= modesize
686 && modesize <= HOST_BITS_PER_WIDE_INT)
687 {
688 unsigned HOST_WIDE_INT block;
689 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
690 block <<= modesize - pos - len;
691
692 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
693 gen_int_mode (block, GET_MODE (inner)));
694 }
695 }
696
697 /* Narrow AND of memory against immediate to enable TM. */
698 if ((*code == EQ || *code == NE)
699 && *op1 == const0_rtx
700 && GET_CODE (*op0) == AND
701 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
702 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
703 {
704 rtx inner = XEXP (*op0, 0);
705 rtx mask = XEXP (*op0, 1);
706
707 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
708 if (GET_CODE (inner) == SUBREG
709 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
710 && (GET_MODE_SIZE (GET_MODE (inner))
711 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
712 && ((INTVAL (mask)
713 & GET_MODE_MASK (GET_MODE (inner))
714 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
715 == 0))
716 inner = SUBREG_REG (inner);
717
718 /* Do not change volatile MEMs. */
719 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
720 {
721 int part = s390_single_part (XEXP (*op0, 1),
722 GET_MODE (inner), QImode, 0);
723 if (part >= 0)
724 {
725 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
726 inner = adjust_address_nv (inner, QImode, part);
727 *op0 = gen_rtx_AND (QImode, inner, mask);
728 }
729 }
730 }
731
732 /* Narrow comparisons against 0xffff to HImode if possible. */
733 if ((*code == EQ || *code == NE)
734 && GET_CODE (*op1) == CONST_INT
735 && INTVAL (*op1) == 0xffff
736 && SCALAR_INT_MODE_P (GET_MODE (*op0))
737 && (nonzero_bits (*op0, GET_MODE (*op0))
738 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
739 {
740 *op0 = gen_lowpart (HImode, *op0);
741 *op1 = constm1_rtx;
742 }
743
744 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
745 if (GET_CODE (*op0) == UNSPEC
746 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
747 && XVECLEN (*op0, 0) == 1
748 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
749 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
750 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
751 && *op1 == const0_rtx)
752 {
753 enum rtx_code new_code = UNKNOWN;
754 switch (*code)
755 {
756 case EQ: new_code = EQ; break;
757 case NE: new_code = NE; break;
758 case LT: new_code = GTU; break;
759 case GT: new_code = LTU; break;
760 case LE: new_code = GEU; break;
761 case GE: new_code = LEU; break;
762 default: break;
763 }
764
765 if (new_code != UNKNOWN)
766 {
767 *op0 = XVECEXP (*op0, 0, 0);
768 *code = new_code;
769 }
770 }
771
772 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
773 if (GET_CODE (*op0) == UNSPEC
774 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
775 && XVECLEN (*op0, 0) == 1
776 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
777 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
778 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
779 && *op1 == const0_rtx)
780 {
781 enum rtx_code new_code = UNKNOWN;
782 switch (*code)
783 {
784 case EQ: new_code = EQ; break;
785 case NE: new_code = NE; break;
786 default: break;
787 }
788
789 if (new_code != UNKNOWN)
790 {
791 *op0 = XVECEXP (*op0, 0, 0);
792 *code = new_code;
793 }
794 }
795
796 /* Simplify cascaded EQ, NE with const0_rtx. */
797 if ((*code == NE || *code == EQ)
798 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
799 && GET_MODE (*op0) == SImode
800 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
801 && REG_P (XEXP (*op0, 0))
802 && XEXP (*op0, 1) == const0_rtx
803 && *op1 == const0_rtx)
804 {
805 if ((*code == EQ && GET_CODE (*op0) == NE)
806 || (*code == NE && GET_CODE (*op0) == EQ))
807 *code = EQ;
808 else
809 *code = NE;
810 *op0 = XEXP (*op0, 0);
811 }
812
813 /* Prefer register over memory as first operand. */
814 if (MEM_P (*op0) && REG_P (*op1))
815 {
816 rtx tem = *op0; *op0 = *op1; *op1 = tem;
817 *code = swap_condition (*code);
818 }
819 }
820
821 /* Emit a compare instruction suitable to implement the comparison
822 OP0 CODE OP1. Return the correct condition RTL to be placed in
823 the IF_THEN_ELSE of the conditional branch testing the result. */
824
825 rtx
826 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
827 {
828 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
829 rtx cc;
830
831 /* Do not output a redundant compare instruction if a compare_and_swap
832 pattern already computed the result and the machine modes are compatible. */
833 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
834 {
835 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
836 == GET_MODE (op0));
837 cc = op0;
838 }
839 else
840 {
841 cc = gen_rtx_REG (mode, CC_REGNUM);
842 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
843 }
844
845 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
846 }
847
848 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
849 matches CMP.
850 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
851 conditional branch testing the result. */
852
853 static rtx
854 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
855 {
856 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
857 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
858 }
859
860 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
861 unconditional jump, else a conditional jump under condition COND. */
862
863 void
864 s390_emit_jump (rtx target, rtx cond)
865 {
866 rtx insn;
867
868 target = gen_rtx_LABEL_REF (VOIDmode, target);
869 if (cond)
870 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
871
872 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
873 emit_jump_insn (insn);
874 }
875
876 /* Return branch condition mask to implement a branch
877 specified by CODE. Return -1 for invalid comparisons. */
878
879 int
880 s390_branch_condition_mask (rtx code)
881 {
882 const int CC0 = 1 << 3;
883 const int CC1 = 1 << 2;
884 const int CC2 = 1 << 1;
885 const int CC3 = 1 << 0;
886
887 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
888 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
889 gcc_assert (XEXP (code, 1) == const0_rtx);
890
891 switch (GET_MODE (XEXP (code, 0)))
892 {
893 case CCZmode:
894 case CCZ1mode:
895 switch (GET_CODE (code))
896 {
897 case EQ: return CC0;
898 case NE: return CC1 | CC2 | CC3;
899 default: return -1;
900 }
901 break;
902
903 case CCT1mode:
904 switch (GET_CODE (code))
905 {
906 case EQ: return CC1;
907 case NE: return CC0 | CC2 | CC3;
908 default: return -1;
909 }
910 break;
911
912 case CCT2mode:
913 switch (GET_CODE (code))
914 {
915 case EQ: return CC2;
916 case NE: return CC0 | CC1 | CC3;
917 default: return -1;
918 }
919 break;
920
921 case CCT3mode:
922 switch (GET_CODE (code))
923 {
924 case EQ: return CC3;
925 case NE: return CC0 | CC1 | CC2;
926 default: return -1;
927 }
928 break;
929
930 case CCLmode:
931 switch (GET_CODE (code))
932 {
933 case EQ: return CC0 | CC2;
934 case NE: return CC1 | CC3;
935 default: return -1;
936 }
937 break;
938
939 case CCL1mode:
940 switch (GET_CODE (code))
941 {
942 case LTU: return CC2 | CC3; /* carry */
943 case GEU: return CC0 | CC1; /* no carry */
944 default: return -1;
945 }
946 break;
947
948 case CCL2mode:
949 switch (GET_CODE (code))
950 {
951 case GTU: return CC0 | CC1; /* borrow */
952 case LEU: return CC2 | CC3; /* no borrow */
953 default: return -1;
954 }
955 break;
956
957 case CCL3mode:
958 switch (GET_CODE (code))
959 {
960 case EQ: return CC0 | CC2;
961 case NE: return CC1 | CC3;
962 case LTU: return CC1;
963 case GTU: return CC3;
964 case LEU: return CC1 | CC2;
965 case GEU: return CC2 | CC3;
966 default: return -1;
967 }
968
969 case CCUmode:
970 switch (GET_CODE (code))
971 {
972 case EQ: return CC0;
973 case NE: return CC1 | CC2 | CC3;
974 case LTU: return CC1;
975 case GTU: return CC2;
976 case LEU: return CC0 | CC1;
977 case GEU: return CC0 | CC2;
978 default: return -1;
979 }
980 break;
981
982 case CCURmode:
983 switch (GET_CODE (code))
984 {
985 case EQ: return CC0;
986 case NE: return CC2 | CC1 | CC3;
987 case LTU: return CC2;
988 case GTU: return CC1;
989 case LEU: return CC0 | CC2;
990 case GEU: return CC0 | CC1;
991 default: return -1;
992 }
993 break;
994
995 case CCAPmode:
996 switch (GET_CODE (code))
997 {
998 case EQ: return CC0;
999 case NE: return CC1 | CC2 | CC3;
1000 case LT: return CC1 | CC3;
1001 case GT: return CC2;
1002 case LE: return CC0 | CC1 | CC3;
1003 case GE: return CC0 | CC2;
1004 default: return -1;
1005 }
1006 break;
1007
1008 case CCANmode:
1009 switch (GET_CODE (code))
1010 {
1011 case EQ: return CC0;
1012 case NE: return CC1 | CC2 | CC3;
1013 case LT: return CC1;
1014 case GT: return CC2 | CC3;
1015 case LE: return CC0 | CC1;
1016 case GE: return CC0 | CC2 | CC3;
1017 default: return -1;
1018 }
1019 break;
1020
1021 case CCSmode:
1022 switch (GET_CODE (code))
1023 {
1024 case EQ: return CC0;
1025 case NE: return CC1 | CC2 | CC3;
1026 case LT: return CC1;
1027 case GT: return CC2;
1028 case LE: return CC0 | CC1;
1029 case GE: return CC0 | CC2;
1030 case UNORDERED: return CC3;
1031 case ORDERED: return CC0 | CC1 | CC2;
1032 case UNEQ: return CC0 | CC3;
1033 case UNLT: return CC1 | CC3;
1034 case UNGT: return CC2 | CC3;
1035 case UNLE: return CC0 | CC1 | CC3;
1036 case UNGE: return CC0 | CC2 | CC3;
1037 case LTGT: return CC1 | CC2;
1038 default: return -1;
1039 }
1040 break;
1041
1042 case CCSRmode:
1043 switch (GET_CODE (code))
1044 {
1045 case EQ: return CC0;
1046 case NE: return CC2 | CC1 | CC3;
1047 case LT: return CC2;
1048 case GT: return CC1;
1049 case LE: return CC0 | CC2;
1050 case GE: return CC0 | CC1;
1051 case UNORDERED: return CC3;
1052 case ORDERED: return CC0 | CC2 | CC1;
1053 case UNEQ: return CC0 | CC3;
1054 case UNLT: return CC2 | CC3;
1055 case UNGT: return CC1 | CC3;
1056 case UNLE: return CC0 | CC2 | CC3;
1057 case UNGE: return CC0 | CC1 | CC3;
1058 case LTGT: return CC2 | CC1;
1059 default: return -1;
1060 }
1061 break;
1062
1063 default:
1064 return -1;
1065 }
1066 }
1067
1068
1069 /* Return branch condition mask to implement a compare and branch
1070 specified by CODE. Return -1 for invalid comparisons. */
1071
1072 int
1073 s390_compare_and_branch_condition_mask (rtx code)
1074 {
1075 const int CC0 = 1 << 3;
1076 const int CC1 = 1 << 2;
1077 const int CC2 = 1 << 1;
1078
1079 switch (GET_CODE (code))
1080 {
1081 case EQ:
1082 return CC0;
1083 case NE:
1084 return CC1 | CC2;
1085 case LT:
1086 case LTU:
1087 return CC1;
1088 case GT:
1089 case GTU:
1090 return CC2;
1091 case LE:
1092 case LEU:
1093 return CC0 | CC1;
1094 case GE:
1095 case GEU:
1096 return CC0 | CC2;
1097 default:
1098 gcc_unreachable ();
1099 }
1100 return -1;
1101 }
1102
1103 /* If INV is false, return assembler mnemonic string to implement
1104 a branch specified by CODE. If INV is true, return mnemonic
1105 for the corresponding inverted branch. */
1106
1107 static const char *
1108 s390_branch_condition_mnemonic (rtx code, int inv)
1109 {
1110 int mask;
1111
1112 static const char *const mnemonic[16] =
1113 {
1114 NULL, "o", "h", "nle",
1115 "l", "nhe", "lh", "ne",
1116 "e", "nlh", "he", "nl",
1117 "le", "nh", "no", NULL
1118 };
1119
1120 if (GET_CODE (XEXP (code, 0)) == REG
1121 && REGNO (XEXP (code, 0)) == CC_REGNUM
1122 && XEXP (code, 1) == const0_rtx)
1123 mask = s390_branch_condition_mask (code);
1124 else
1125 mask = s390_compare_and_branch_condition_mask (code);
1126
1127 gcc_assert (mask >= 0);
1128
1129 if (inv)
1130 mask ^= 15;
1131
1132 gcc_assert (mask >= 1 && mask <= 14);
1133
1134 return mnemonic[mask];
1135 }
1136
1137 /* Return the part of op which has a value different from def.
1138 The size of the part is determined by mode.
1139 Use this function only if you already know that op really
1140 contains such a part. */
1141
1142 unsigned HOST_WIDE_INT
1143 s390_extract_part (rtx op, enum machine_mode mode, int def)
1144 {
1145 unsigned HOST_WIDE_INT value = 0;
1146 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1147 int part_bits = GET_MODE_BITSIZE (mode);
1148 unsigned HOST_WIDE_INT part_mask
1149 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1150 int i;
1151
1152 for (i = 0; i < max_parts; i++)
1153 {
1154 if (i == 0)
1155 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1156 else
1157 value >>= part_bits;
1158
1159 if ((value & part_mask) != (def & part_mask))
1160 return value & part_mask;
1161 }
1162
1163 gcc_unreachable ();
1164 }
1165
1166 /* If OP is an integer constant of mode MODE with exactly one
1167 part of mode PART_MODE unequal to DEF, return the number of that
1168 part. Otherwise, return -1. */
1169
1170 int
1171 s390_single_part (rtx op,
1172 enum machine_mode mode,
1173 enum machine_mode part_mode,
1174 int def)
1175 {
1176 unsigned HOST_WIDE_INT value = 0;
1177 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1178 unsigned HOST_WIDE_INT part_mask
1179 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1180 int i, part = -1;
1181
1182 if (GET_CODE (op) != CONST_INT)
1183 return -1;
1184
1185 for (i = 0; i < n_parts; i++)
1186 {
1187 if (i == 0)
1188 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1189 else
1190 value >>= GET_MODE_BITSIZE (part_mode);
1191
1192 if ((value & part_mask) != (def & part_mask))
1193 {
1194 if (part != -1)
1195 return -1;
1196 else
1197 part = i;
1198 }
1199 }
1200 return part == -1 ? -1 : n_parts - 1 - part;
1201 }
1202
1203 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1204 bits and no other bits are set in IN. POS and LENGTH can be used
1205 to obtain the start position and the length of the bitfield.
1206
1207 POS gives the position of the first bit of the bitfield counting
1208 from the lowest order bit starting with zero. In order to use this
1209 value for S/390 instructions this has to be converted to "bits big
1210 endian" style. */
1211
1212 bool
1213 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1214 int *pos, int *length)
1215 {
1216 int tmp_pos = 0;
1217 int tmp_length = 0;
1218 int i;
1219 unsigned HOST_WIDE_INT mask = 1ULL;
1220 bool contiguous = false;
1221
1222 for (i = 0; i < size; mask <<= 1, i++)
1223 {
1224 if (contiguous)
1225 {
1226 if (mask & in)
1227 tmp_length++;
1228 else
1229 break;
1230 }
1231 else
1232 {
1233 if (mask & in)
1234 {
1235 contiguous = true;
1236 tmp_length++;
1237 }
1238 else
1239 tmp_pos++;
1240 }
1241 }
1242
1243 if (!tmp_length)
1244 return false;
1245
1246 /* Calculate a mask for all bits beyond the contiguous bits. */
1247 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1248
1249 if (mask & in)
1250 return false;
1251
1252 if (tmp_length + tmp_pos - 1 > size)
1253 return false;
1254
1255 if (length)
1256 *length = tmp_length;
1257
1258 if (pos)
1259 *pos = tmp_pos;
1260
1261 return true;
1262 }
1263
1264 /* Check whether we can (and want to) split a double-word
1265 move in mode MODE from SRC to DST into two single-word
1266 moves, moving the subword FIRST_SUBWORD first. */
1267
1268 bool
1269 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1270 {
1271 /* Floating point registers cannot be split. */
1272 if (FP_REG_P (src) || FP_REG_P (dst))
1273 return false;
1274
1275 /* We don't need to split if operands are directly accessible. */
1276 if (s_operand (src, mode) || s_operand (dst, mode))
1277 return false;
1278
1279 /* Non-offsettable memory references cannot be split. */
1280 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1281 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1282 return false;
1283
1284 /* Moving the first subword must not clobber a register
1285 needed to move the second subword. */
1286 if (register_operand (dst, mode))
1287 {
1288 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1289 if (reg_overlap_mentioned_p (subreg, src))
1290 return false;
1291 }
1292
1293 return true;
1294 }
1295
1296 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1297 and [MEM2, MEM2 + SIZE] do overlap and false
1298 otherwise. */
1299
1300 bool
1301 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1302 {
1303 rtx addr1, addr2, addr_delta;
1304 HOST_WIDE_INT delta;
1305
1306 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1307 return true;
1308
1309 if (size == 0)
1310 return false;
1311
1312 addr1 = XEXP (mem1, 0);
1313 addr2 = XEXP (mem2, 0);
1314
1315 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1316
1317 /* This overlapping check is used by peepholes merging memory block operations.
1318 Overlapping operations would otherwise be recognized by the S/390 hardware
1319 and would fall back to a slower implementation. Allowing overlapping
1320 operations would lead to slow code but not to wrong code. Therefore we are
1321 somewhat optimistic if we cannot prove that the memory blocks are
1322 overlapping.
1323 That's why we return false here although this may accept operations on
1324 overlapping memory areas. */
1325 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1326 return false;
1327
1328 delta = INTVAL (addr_delta);
1329
1330 if (delta == 0
1331 || (delta > 0 && delta < size)
1332 || (delta < 0 && -delta < size))
1333 return true;
1334
1335 return false;
1336 }
1337
1338 /* Check whether the address of memory reference MEM2 equals exactly
1339 the address of memory reference MEM1 plus DELTA. Return true if
1340 we can prove this to be the case, false otherwise. */
1341
1342 bool
1343 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1344 {
1345 rtx addr1, addr2, addr_delta;
1346
1347 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1348 return false;
1349
1350 addr1 = XEXP (mem1, 0);
1351 addr2 = XEXP (mem2, 0);
1352
1353 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1354 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1355 return false;
1356
1357 return true;
1358 }
1359
1360 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1361
1362 void
1363 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1364 rtx *operands)
1365 {
1366 enum machine_mode wmode = mode;
1367 rtx dst = operands[0];
1368 rtx src1 = operands[1];
1369 rtx src2 = operands[2];
1370 rtx op, clob, tem;
1371
1372 /* If we cannot handle the operation directly, use a temp register. */
1373 if (!s390_logical_operator_ok_p (operands))
1374 dst = gen_reg_rtx (mode);
1375
1376 /* QImode and HImode patterns make sense only if we have a destination
1377 in memory. Otherwise perform the operation in SImode. */
1378 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1379 wmode = SImode;
1380
1381 /* Widen operands if required. */
1382 if (mode != wmode)
1383 {
1384 if (GET_CODE (dst) == SUBREG
1385 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1386 dst = tem;
1387 else if (REG_P (dst))
1388 dst = gen_rtx_SUBREG (wmode, dst, 0);
1389 else
1390 dst = gen_reg_rtx (wmode);
1391
1392 if (GET_CODE (src1) == SUBREG
1393 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1394 src1 = tem;
1395 else if (GET_MODE (src1) != VOIDmode)
1396 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1397
1398 if (GET_CODE (src2) == SUBREG
1399 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1400 src2 = tem;
1401 else if (GET_MODE (src2) != VOIDmode)
1402 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1403 }
1404
1405 /* Emit the instruction. */
1406 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1407 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1408 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1409
1410 /* Fix up the destination if needed. */
1411 if (dst != operands[0])
1412 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1413 }
1414
1415 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1416
1417 bool
1418 s390_logical_operator_ok_p (rtx *operands)
1419 {
1420 /* If the destination operand is in memory, it needs to coincide
1421 with one of the source operands. After reload, it has to be
1422 the first source operand. */
1423 if (GET_CODE (operands[0]) == MEM)
1424 return rtx_equal_p (operands[0], operands[1])
1425 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1426
1427 return true;
1428 }
1429
1430 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1431 operand IMMOP to switch from SS to SI type instructions. */
1432
1433 void
1434 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1435 {
1436 int def = code == AND ? -1 : 0;
1437 HOST_WIDE_INT mask;
1438 int part;
1439
1440 gcc_assert (GET_CODE (*memop) == MEM);
1441 gcc_assert (!MEM_VOLATILE_P (*memop));
1442
1443 mask = s390_extract_part (*immop, QImode, def);
1444 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1445 gcc_assert (part >= 0);
1446
1447 *memop = adjust_address (*memop, QImode, part);
1448 *immop = gen_int_mode (mask, QImode);
1449 }
1450
1451
1452 /* How to allocate a 'struct machine_function'. */
1453
1454 static struct machine_function *
1455 s390_init_machine_status (void)
1456 {
1457 return ggc_alloc_cleared_machine_function ();
1458 }
1459
1460 /* Change optimizations to be performed, depending on the
1461 optimization level.
1462
1463 LEVEL is the optimization level specified; 2 if `-O2' is
1464 specified, 1 if `-O' is specified, and 0 if neither is specified.
1465
1466 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1467
1468 void
1469 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1470 {
1471 /* ??? There are apparently still problems with -fcaller-saves. */
1472 flag_caller_saves = 0;
1473
1474 /* By default, always emit DWARF-2 unwind info. This allows debugging
1475 without maintaining a stack frame back-chain. */
1476 flag_asynchronous_unwind_tables = 1;
1477
1478 /* Use MVCLE instructions to decrease code size if requested. */
1479 if (size != 0)
1480 target_flags |= MASK_MVCLE;
1481 }
1482
1483 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1484 to the associated processor_type and processor_flags if so. */
1485
1486 static bool
1487 s390_handle_arch_option (const char *arg,
1488 enum processor_type *type,
1489 int *flags)
1490 {
1491 static struct pta
1492 {
1493 const char *const name; /* processor name or nickname. */
1494 const enum processor_type processor;
1495 const int flags; /* From enum processor_flags. */
1496 }
1497 const processor_alias_table[] =
1498 {
1499 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1500 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1501 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1502 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1503 | PF_LONG_DISPLACEMENT},
1504 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1505 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1506 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1507 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1508 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1509 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1510 };
1511 size_t i;
1512
1513 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1514 if (strcmp (arg, processor_alias_table[i].name) == 0)
1515 {
1516 *type = processor_alias_table[i].processor;
1517 *flags = processor_alias_table[i].flags;
1518 return true;
1519 }
1520 return false;
1521 }
1522
1523 /* Implement TARGET_HANDLE_OPTION. */
1524
1525 static bool
1526 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1527 {
1528 switch (code)
1529 {
1530 case OPT_march_:
1531 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1532
1533 case OPT_mstack_guard_:
1534 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1535 return false;
1536 if (exact_log2 (s390_stack_guard) == -1)
1537 error ("stack guard value must be an exact power of 2");
1538 return true;
1539
1540 case OPT_mstack_size_:
1541 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1542 return false;
1543 if (exact_log2 (s390_stack_size) == -1)
1544 error ("stack size must be an exact power of 2");
1545 return true;
1546
1547 case OPT_mtune_:
1548 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1549
1550 case OPT_mwarn_framesize_:
1551 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1552
1553 default:
1554 return true;
1555 }
1556 }
1557
1558 void
1559 override_options (void)
1560 {
1561 /* Set up function hooks. */
1562 init_machine_status = s390_init_machine_status;
1563
1564 /* Architecture mode defaults according to ABI. */
1565 if (!(target_flags_explicit & MASK_ZARCH))
1566 {
1567 if (TARGET_64BIT)
1568 target_flags |= MASK_ZARCH;
1569 else
1570 target_flags &= ~MASK_ZARCH;
1571 }
1572
1573 /* Determine processor architectural level. */
1574 if (!s390_arch_string)
1575 {
1576 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1577 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1578 }
1579
1580 /* Determine processor to tune for. */
1581 if (s390_tune == PROCESSOR_max)
1582 {
1583 s390_tune = s390_arch;
1584 s390_tune_flags = s390_arch_flags;
1585 }
1586
1587 /* Sanity checks. */
1588 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1589 error ("z/Architecture mode not supported on %s", s390_arch_string);
1590 if (TARGET_64BIT && !TARGET_ZARCH)
1591 error ("64-bit ABI not supported in ESA/390 mode");
1592
1593 if (TARGET_HARD_DFP && !TARGET_DFP)
1594 {
1595 if (target_flags_explicit & MASK_HARD_DFP)
1596 {
1597 if (!TARGET_CPU_DFP)
1598 error ("Hardware decimal floating point instructions"
1599 " not available on %s", s390_arch_string);
1600 if (!TARGET_ZARCH)
1601 error ("Hardware decimal floating point instructions"
1602 " not available in ESA/390 mode");
1603 }
1604 else
1605 target_flags &= ~MASK_HARD_DFP;
1606 }
1607
1608 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1609 {
1610 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1611 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1612
1613 target_flags &= ~MASK_HARD_DFP;
1614 }
1615
1616 /* Set processor cost function. */
1617 switch (s390_tune)
1618 {
1619 case PROCESSOR_2084_Z990:
1620 s390_cost = &z990_cost;
1621 break;
1622 case PROCESSOR_2094_Z9_109:
1623 s390_cost = &z9_109_cost;
1624 break;
1625 case PROCESSOR_2097_Z10:
1626 s390_cost = &z10_cost;
1627 break;
1628 default:
1629 s390_cost = &z900_cost;
1630 }
1631
1632 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1633 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1634 "in combination");
1635
1636 if (s390_stack_size)
1637 {
1638 if (s390_stack_guard >= s390_stack_size)
1639 error ("stack size must be greater than the stack guard value");
1640 else if (s390_stack_size > 1 << 16)
1641 error ("stack size must not be greater than 64k");
1642 }
1643 else if (s390_stack_guard)
1644 error ("-mstack-guard implies use of -mstack-size");
1645
1646 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1647 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1648 target_flags |= MASK_LONG_DOUBLE_128;
1649 #endif
1650
1651 if (s390_tune == PROCESSOR_2097_Z10)
1652 {
1653 if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1654 set_param_value ("max-unrolled-insns", 100);
1655 if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES))
1656 set_param_value ("max-unroll-times", 32);
1657 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEELED_INSNS))
1658 set_param_value ("max-completely-peeled-insns", 2000);
1659 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEEL_TIMES))
1660 set_param_value ("max-completely-peel-times", 64);
1661 }
1662
1663 set_param_value ("max-pending-list-length", 256);
1664 /* values for loop prefetching */
1665 set_param_value ("l1-cache-line-size", 256);
1666 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1667 set_param_value ("l1-cache-size", 128);
1668 /* s390 has more than 2 levels and the size is much larger. Since
1669 we are always running virtualized assume that we only get a small
1670 part of the caches above l1. */
1671 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1672 set_param_value ("l2-cache-size", 1500);
1673 if (!PARAM_SET_P (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO))
1674 set_param_value ("prefetch-min-insn-to-mem-ratio", 2);
1675 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1676 set_param_value ("simultaneous-prefetches", 6);
1677
1678 /* This cannot reside in optimization_options since HAVE_prefetch
1679 requires the arch flags to be evaluated already. Since prefetching
1680 is beneficial on s390, we enable it if available. */
1681 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1682 flag_prefetch_loop_arrays = 1;
1683 }
1684
1685 /* Map for smallest class containing reg regno. */
1686
1687 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1688 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1689 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1690 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1691 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1692 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1693 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1694 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1695 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1696 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1697 ACCESS_REGS, ACCESS_REGS
1698 };
1699
1700 /* Return attribute type of insn. */
1701
1702 static enum attr_type
1703 s390_safe_attr_type (rtx insn)
1704 {
1705 if (recog_memoized (insn) >= 0)
1706 return get_attr_type (insn);
1707 else
1708 return TYPE_NONE;
1709 }
1710
1711 /* Return true if DISP is a valid short displacement. */
1712
1713 static bool
1714 s390_short_displacement (rtx disp)
1715 {
1716 /* No displacement is OK. */
1717 if (!disp)
1718 return true;
1719
1720 /* Without the long displacement facility we don't need to
1721 distingiush between long and short displacement. */
1722 if (!TARGET_LONG_DISPLACEMENT)
1723 return true;
1724
1725 /* Integer displacement in range. */
1726 if (GET_CODE (disp) == CONST_INT)
1727 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1728
1729 /* GOT offset is not OK, the GOT can be large. */
1730 if (GET_CODE (disp) == CONST
1731 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1732 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1733 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1734 return false;
1735
1736 /* All other symbolic constants are literal pool references,
1737 which are OK as the literal pool must be small. */
1738 if (GET_CODE (disp) == CONST)
1739 return true;
1740
1741 return false;
1742 }
1743
1744 /* Decompose a RTL expression ADDR for a memory address into
1745 its components, returned in OUT.
1746
1747 Returns false if ADDR is not a valid memory address, true
1748 otherwise. If OUT is NULL, don't return the components,
1749 but check for validity only.
1750
1751 Note: Only addresses in canonical form are recognized.
1752 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1753 canonical form so that they will be recognized. */
1754
1755 static int
1756 s390_decompose_address (rtx addr, struct s390_address *out)
1757 {
1758 HOST_WIDE_INT offset = 0;
1759 rtx base = NULL_RTX;
1760 rtx indx = NULL_RTX;
1761 rtx disp = NULL_RTX;
1762 rtx orig_disp;
1763 bool pointer = false;
1764 bool base_ptr = false;
1765 bool indx_ptr = false;
1766 bool literal_pool = false;
1767
1768 /* We may need to substitute the literal pool base register into the address
1769 below. However, at this point we do not know which register is going to
1770 be used as base, so we substitute the arg pointer register. This is going
1771 to be treated as holding a pointer below -- it shouldn't be used for any
1772 other purpose. */
1773 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1774
1775 /* Decompose address into base + index + displacement. */
1776
1777 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1778 base = addr;
1779
1780 else if (GET_CODE (addr) == PLUS)
1781 {
1782 rtx op0 = XEXP (addr, 0);
1783 rtx op1 = XEXP (addr, 1);
1784 enum rtx_code code0 = GET_CODE (op0);
1785 enum rtx_code code1 = GET_CODE (op1);
1786
1787 if (code0 == REG || code0 == UNSPEC)
1788 {
1789 if (code1 == REG || code1 == UNSPEC)
1790 {
1791 indx = op0; /* index + base */
1792 base = op1;
1793 }
1794
1795 else
1796 {
1797 base = op0; /* base + displacement */
1798 disp = op1;
1799 }
1800 }
1801
1802 else if (code0 == PLUS)
1803 {
1804 indx = XEXP (op0, 0); /* index + base + disp */
1805 base = XEXP (op0, 1);
1806 disp = op1;
1807 }
1808
1809 else
1810 {
1811 return false;
1812 }
1813 }
1814
1815 else
1816 disp = addr; /* displacement */
1817
1818 /* Extract integer part of displacement. */
1819 orig_disp = disp;
1820 if (disp)
1821 {
1822 if (GET_CODE (disp) == CONST_INT)
1823 {
1824 offset = INTVAL (disp);
1825 disp = NULL_RTX;
1826 }
1827 else if (GET_CODE (disp) == CONST
1828 && GET_CODE (XEXP (disp, 0)) == PLUS
1829 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1830 {
1831 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1832 disp = XEXP (XEXP (disp, 0), 0);
1833 }
1834 }
1835
1836 /* Strip off CONST here to avoid special case tests later. */
1837 if (disp && GET_CODE (disp) == CONST)
1838 disp = XEXP (disp, 0);
1839
1840 /* We can convert literal pool addresses to
1841 displacements by basing them off the base register. */
1842 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1843 {
1844 /* Either base or index must be free to hold the base register. */
1845 if (!base)
1846 base = fake_pool_base, literal_pool = true;
1847 else if (!indx)
1848 indx = fake_pool_base, literal_pool = true;
1849 else
1850 return false;
1851
1852 /* Mark up the displacement. */
1853 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1854 UNSPEC_LTREL_OFFSET);
1855 }
1856
1857 /* Validate base register. */
1858 if (base)
1859 {
1860 if (GET_CODE (base) == UNSPEC)
1861 switch (XINT (base, 1))
1862 {
1863 case UNSPEC_LTREF:
1864 if (!disp)
1865 disp = gen_rtx_UNSPEC (Pmode,
1866 gen_rtvec (1, XVECEXP (base, 0, 0)),
1867 UNSPEC_LTREL_OFFSET);
1868 else
1869 return false;
1870
1871 base = XVECEXP (base, 0, 1);
1872 break;
1873
1874 case UNSPEC_LTREL_BASE:
1875 if (XVECLEN (base, 0) == 1)
1876 base = fake_pool_base, literal_pool = true;
1877 else
1878 base = XVECEXP (base, 0, 1);
1879 break;
1880
1881 default:
1882 return false;
1883 }
1884
1885 if (!REG_P (base)
1886 || (GET_MODE (base) != SImode
1887 && GET_MODE (base) != Pmode))
1888 return false;
1889
1890 if (REGNO (base) == STACK_POINTER_REGNUM
1891 || REGNO (base) == FRAME_POINTER_REGNUM
1892 || ((reload_completed || reload_in_progress)
1893 && frame_pointer_needed
1894 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1895 || REGNO (base) == ARG_POINTER_REGNUM
1896 || (flag_pic
1897 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1898 pointer = base_ptr = true;
1899
1900 if ((reload_completed || reload_in_progress)
1901 && base == cfun->machine->base_reg)
1902 pointer = base_ptr = literal_pool = true;
1903 }
1904
1905 /* Validate index register. */
1906 if (indx)
1907 {
1908 if (GET_CODE (indx) == UNSPEC)
1909 switch (XINT (indx, 1))
1910 {
1911 case UNSPEC_LTREF:
1912 if (!disp)
1913 disp = gen_rtx_UNSPEC (Pmode,
1914 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1915 UNSPEC_LTREL_OFFSET);
1916 else
1917 return false;
1918
1919 indx = XVECEXP (indx, 0, 1);
1920 break;
1921
1922 case UNSPEC_LTREL_BASE:
1923 if (XVECLEN (indx, 0) == 1)
1924 indx = fake_pool_base, literal_pool = true;
1925 else
1926 indx = XVECEXP (indx, 0, 1);
1927 break;
1928
1929 default:
1930 return false;
1931 }
1932
1933 if (!REG_P (indx)
1934 || (GET_MODE (indx) != SImode
1935 && GET_MODE (indx) != Pmode))
1936 return false;
1937
1938 if (REGNO (indx) == STACK_POINTER_REGNUM
1939 || REGNO (indx) == FRAME_POINTER_REGNUM
1940 || ((reload_completed || reload_in_progress)
1941 && frame_pointer_needed
1942 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1943 || REGNO (indx) == ARG_POINTER_REGNUM
1944 || (flag_pic
1945 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1946 pointer = indx_ptr = true;
1947
1948 if ((reload_completed || reload_in_progress)
1949 && indx == cfun->machine->base_reg)
1950 pointer = indx_ptr = literal_pool = true;
1951 }
1952
1953 /* Prefer to use pointer as base, not index. */
1954 if (base && indx && !base_ptr
1955 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1956 {
1957 rtx tmp = base;
1958 base = indx;
1959 indx = tmp;
1960 }
1961
1962 /* Validate displacement. */
1963 if (!disp)
1964 {
1965 /* If virtual registers are involved, the displacement will change later
1966 anyway as the virtual registers get eliminated. This could make a
1967 valid displacement invalid, but it is more likely to make an invalid
1968 displacement valid, because we sometimes access the register save area
1969 via negative offsets to one of those registers.
1970 Thus we don't check the displacement for validity here. If after
1971 elimination the displacement turns out to be invalid after all,
1972 this is fixed up by reload in any case. */
1973 if (base != arg_pointer_rtx
1974 && indx != arg_pointer_rtx
1975 && base != return_address_pointer_rtx
1976 && indx != return_address_pointer_rtx
1977 && base != frame_pointer_rtx
1978 && indx != frame_pointer_rtx
1979 && base != virtual_stack_vars_rtx
1980 && indx != virtual_stack_vars_rtx)
1981 if (!DISP_IN_RANGE (offset))
1982 return false;
1983 }
1984 else
1985 {
1986 /* All the special cases are pointers. */
1987 pointer = true;
1988
1989 /* In the small-PIC case, the linker converts @GOT
1990 and @GOTNTPOFF offsets to possible displacements. */
1991 if (GET_CODE (disp) == UNSPEC
1992 && (XINT (disp, 1) == UNSPEC_GOT
1993 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1994 && flag_pic == 1)
1995 {
1996 ;
1997 }
1998
1999 /* Accept pool label offsets. */
2000 else if (GET_CODE (disp) == UNSPEC
2001 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2002 ;
2003
2004 /* Accept literal pool references. */
2005 else if (GET_CODE (disp) == UNSPEC
2006 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2007 {
2008 orig_disp = gen_rtx_CONST (Pmode, disp);
2009 if (offset)
2010 {
2011 /* If we have an offset, make sure it does not
2012 exceed the size of the constant pool entry. */
2013 rtx sym = XVECEXP (disp, 0, 0);
2014 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2015 return false;
2016
2017 orig_disp = plus_constant (orig_disp, offset);
2018 }
2019 }
2020
2021 else
2022 return false;
2023 }
2024
2025 if (!base && !indx)
2026 pointer = true;
2027
2028 if (out)
2029 {
2030 out->base = base;
2031 out->indx = indx;
2032 out->disp = orig_disp;
2033 out->pointer = pointer;
2034 out->literal_pool = literal_pool;
2035 }
2036
2037 return true;
2038 }
2039
2040 /* Decompose a RTL expression OP for a shift count into its components,
2041 and return the base register in BASE and the offset in OFFSET.
2042
2043 Return true if OP is a valid shift count, false if not. */
2044
2045 bool
2046 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2047 {
2048 HOST_WIDE_INT off = 0;
2049
2050 /* We can have an integer constant, an address register,
2051 or a sum of the two. */
2052 if (GET_CODE (op) == CONST_INT)
2053 {
2054 off = INTVAL (op);
2055 op = NULL_RTX;
2056 }
2057 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2058 {
2059 off = INTVAL (XEXP (op, 1));
2060 op = XEXP (op, 0);
2061 }
2062 while (op && GET_CODE (op) == SUBREG)
2063 op = SUBREG_REG (op);
2064
2065 if (op && GET_CODE (op) != REG)
2066 return false;
2067
2068 if (offset)
2069 *offset = off;
2070 if (base)
2071 *base = op;
2072
2073 return true;
2074 }
2075
2076
2077 /* Return true if CODE is a valid address without index. */
2078
2079 bool
2080 s390_legitimate_address_without_index_p (rtx op)
2081 {
2082 struct s390_address addr;
2083
2084 if (!s390_decompose_address (XEXP (op, 0), &addr))
2085 return false;
2086 if (addr.indx)
2087 return false;
2088
2089 return true;
2090 }
2091
2092
2093 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2094 and return these parts in SYMREF and ADDEND. You can pass NULL in
2095 SYMREF and/or ADDEND if you are not interested in these values. */
2096
2097 static bool
2098 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2099 {
2100 HOST_WIDE_INT tmpaddend = 0;
2101
2102 if (GET_CODE (addr) == CONST)
2103 addr = XEXP (addr, 0);
2104
2105 if (GET_CODE (addr) == PLUS)
2106 {
2107 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2108 && CONST_INT_P (XEXP (addr, 1)))
2109 {
2110 tmpaddend = INTVAL (XEXP (addr, 1));
2111 addr = XEXP (addr, 0);
2112 }
2113 else
2114 return false;
2115 }
2116 else
2117 if (GET_CODE (addr) != SYMBOL_REF)
2118 return false;
2119
2120 if (symref)
2121 *symref = addr;
2122 if (addend)
2123 *addend = tmpaddend;
2124
2125 return true;
2126 }
2127
2128
2129 /* Return true if the address in OP is valid for constraint letter C
2130 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2131 pool MEMs should be accepted. Only the Q, R, S, T constraint
2132 letters are allowed for C. */
2133
2134 static int
2135 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2136 {
2137 struct s390_address addr;
2138 bool decomposed = false;
2139
2140 /* This check makes sure that no symbolic address (except literal
2141 pool references) are accepted by the R or T constraints. */
2142 if (s390_symref_operand_p (op, NULL, NULL))
2143 {
2144 if (!lit_pool_ok)
2145 return 0;
2146 if (!s390_decompose_address (op, &addr))
2147 return 0;
2148 if (!addr.literal_pool)
2149 return 0;
2150 decomposed = true;
2151 }
2152
2153 switch (c)
2154 {
2155 case 'Q': /* no index short displacement */
2156 if (!decomposed && !s390_decompose_address (op, &addr))
2157 return 0;
2158 if (addr.indx)
2159 return 0;
2160 if (!s390_short_displacement (addr.disp))
2161 return 0;
2162 break;
2163
2164 case 'R': /* with index short displacement */
2165 if (TARGET_LONG_DISPLACEMENT)
2166 {
2167 if (!decomposed && !s390_decompose_address (op, &addr))
2168 return 0;
2169 if (!s390_short_displacement (addr.disp))
2170 return 0;
2171 }
2172 /* Any invalid address here will be fixed up by reload,
2173 so accept it for the most generic constraint. */
2174 break;
2175
2176 case 'S': /* no index long displacement */
2177 if (!TARGET_LONG_DISPLACEMENT)
2178 return 0;
2179 if (!decomposed && !s390_decompose_address (op, &addr))
2180 return 0;
2181 if (addr.indx)
2182 return 0;
2183 if (s390_short_displacement (addr.disp))
2184 return 0;
2185 break;
2186
2187 case 'T': /* with index long displacement */
2188 if (!TARGET_LONG_DISPLACEMENT)
2189 return 0;
2190 /* Any invalid address here will be fixed up by reload,
2191 so accept it for the most generic constraint. */
2192 if ((decomposed || s390_decompose_address (op, &addr))
2193 && s390_short_displacement (addr.disp))
2194 return 0;
2195 break;
2196 default:
2197 return 0;
2198 }
2199 return 1;
2200 }
2201
2202
2203 /* Evaluates constraint strings described by the regular expression
2204 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2205 the constraint given in STR, or 0 else. */
2206
2207 int
2208 s390_mem_constraint (const char *str, rtx op)
2209 {
2210 char c = str[0];
2211
2212 switch (c)
2213 {
2214 case 'A':
2215 /* Check for offsettable variants of memory constraints. */
2216 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2217 return 0;
2218 if ((reload_completed || reload_in_progress)
2219 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2220 return 0;
2221 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2222 case 'B':
2223 /* Check for non-literal-pool variants of memory constraints. */
2224 if (!MEM_P (op))
2225 return 0;
2226 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2227 case 'Q':
2228 case 'R':
2229 case 'S':
2230 case 'T':
2231 if (GET_CODE (op) != MEM)
2232 return 0;
2233 return s390_check_qrst_address (c, XEXP (op, 0), true);
2234 case 'U':
2235 return (s390_check_qrst_address ('Q', op, true)
2236 || s390_check_qrst_address ('R', op, true));
2237 case 'W':
2238 return (s390_check_qrst_address ('S', op, true)
2239 || s390_check_qrst_address ('T', op, true));
2240 case 'Y':
2241 /* Simply check for the basic form of a shift count. Reload will
2242 take care of making sure we have a proper base register. */
2243 if (!s390_decompose_shift_count (op, NULL, NULL))
2244 return 0;
2245 break;
2246 case 'Z':
2247 return s390_check_qrst_address (str[1], op, true);
2248 default:
2249 return 0;
2250 }
2251 return 1;
2252 }
2253
2254
2255 /* Evaluates constraint strings starting with letter O. Input
2256 parameter C is the second letter following the "O" in the constraint
2257 string. Returns 1 if VALUE meets the respective constraint and 0
2258 otherwise. */
2259
2260 int
2261 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2262 {
2263 if (!TARGET_EXTIMM)
2264 return 0;
2265
2266 switch (c)
2267 {
2268 case 's':
2269 return trunc_int_for_mode (value, SImode) == value;
2270
2271 case 'p':
2272 return value == 0
2273 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2274
2275 case 'n':
2276 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2277
2278 default:
2279 gcc_unreachable ();
2280 }
2281 }
2282
2283
2284 /* Evaluates constraint strings starting with letter N. Parameter STR
2285 contains the letters following letter "N" in the constraint string.
2286 Returns true if VALUE matches the constraint. */
2287
2288 int
2289 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2290 {
2291 enum machine_mode mode, part_mode;
2292 int def;
2293 int part, part_goal;
2294
2295
2296 if (str[0] == 'x')
2297 part_goal = -1;
2298 else
2299 part_goal = str[0] - '0';
2300
2301 switch (str[1])
2302 {
2303 case 'Q':
2304 part_mode = QImode;
2305 break;
2306 case 'H':
2307 part_mode = HImode;
2308 break;
2309 case 'S':
2310 part_mode = SImode;
2311 break;
2312 default:
2313 return 0;
2314 }
2315
2316 switch (str[2])
2317 {
2318 case 'H':
2319 mode = HImode;
2320 break;
2321 case 'S':
2322 mode = SImode;
2323 break;
2324 case 'D':
2325 mode = DImode;
2326 break;
2327 default:
2328 return 0;
2329 }
2330
2331 switch (str[3])
2332 {
2333 case '0':
2334 def = 0;
2335 break;
2336 case 'F':
2337 def = -1;
2338 break;
2339 default:
2340 return 0;
2341 }
2342
2343 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2344 return 0;
2345
2346 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2347 if (part < 0)
2348 return 0;
2349 if (part_goal != -1 && part_goal != part)
2350 return 0;
2351
2352 return 1;
2353 }
2354
2355
2356 /* Returns true if the input parameter VALUE is a float zero. */
2357
2358 int
2359 s390_float_const_zero_p (rtx value)
2360 {
2361 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2362 && value == CONST0_RTX (GET_MODE (value)));
2363 }
2364
2365
2366 /* Compute a (partial) cost for rtx X. Return true if the complete
2367 cost has been computed, and false if subexpressions should be
2368 scanned. In either case, *TOTAL contains the cost result.
2369 CODE contains GET_CODE (x), OUTER_CODE contains the code
2370 of the superexpression of x. */
2371
2372 static bool
2373 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2374 bool speed ATTRIBUTE_UNUSED)
2375 {
2376 switch (code)
2377 {
2378 case CONST:
2379 case CONST_INT:
2380 case LABEL_REF:
2381 case SYMBOL_REF:
2382 case CONST_DOUBLE:
2383 case MEM:
2384 *total = 0;
2385 return true;
2386
2387 case ASHIFT:
2388 case ASHIFTRT:
2389 case LSHIFTRT:
2390 case ROTATE:
2391 case ROTATERT:
2392 case AND:
2393 case IOR:
2394 case XOR:
2395 case NEG:
2396 case NOT:
2397 *total = COSTS_N_INSNS (1);
2398 return false;
2399
2400 case PLUS:
2401 case MINUS:
2402 /* Check for multiply and add. */
2403 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2404 && GET_CODE (XEXP (x, 0)) == MULT
2405 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2406 {
2407 /* This is the multiply and add case. */
2408 if (GET_MODE (x) == DFmode)
2409 *total = s390_cost->madbr;
2410 else
2411 *total = s390_cost->maebr;
2412 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2413 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2414 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2415 return true; /* Do not do an additional recursive descent. */
2416 }
2417 *total = COSTS_N_INSNS (1);
2418 return false;
2419
2420 case MULT:
2421 switch (GET_MODE (x))
2422 {
2423 case SImode:
2424 {
2425 rtx left = XEXP (x, 0);
2426 rtx right = XEXP (x, 1);
2427 if (GET_CODE (right) == CONST_INT
2428 && CONST_OK_FOR_K (INTVAL (right)))
2429 *total = s390_cost->mhi;
2430 else if (GET_CODE (left) == SIGN_EXTEND)
2431 *total = s390_cost->mh;
2432 else
2433 *total = s390_cost->ms; /* msr, ms, msy */
2434 break;
2435 }
2436 case DImode:
2437 {
2438 rtx left = XEXP (x, 0);
2439 rtx right = XEXP (x, 1);
2440 if (TARGET_ZARCH)
2441 {
2442 if (GET_CODE (right) == CONST_INT
2443 && CONST_OK_FOR_K (INTVAL (right)))
2444 *total = s390_cost->mghi;
2445 else if (GET_CODE (left) == SIGN_EXTEND)
2446 *total = s390_cost->msgf;
2447 else
2448 *total = s390_cost->msg; /* msgr, msg */
2449 }
2450 else /* TARGET_31BIT */
2451 {
2452 if (GET_CODE (left) == SIGN_EXTEND
2453 && GET_CODE (right) == SIGN_EXTEND)
2454 /* mulsidi case: mr, m */
2455 *total = s390_cost->m;
2456 else if (GET_CODE (left) == ZERO_EXTEND
2457 && GET_CODE (right) == ZERO_EXTEND
2458 && TARGET_CPU_ZARCH)
2459 /* umulsidi case: ml, mlr */
2460 *total = s390_cost->ml;
2461 else
2462 /* Complex calculation is required. */
2463 *total = COSTS_N_INSNS (40);
2464 }
2465 break;
2466 }
2467 case SFmode:
2468 case DFmode:
2469 *total = s390_cost->mult_df;
2470 break;
2471 case TFmode:
2472 *total = s390_cost->mxbr;
2473 break;
2474 default:
2475 return false;
2476 }
2477 return false;
2478
2479 case UDIV:
2480 case UMOD:
2481 if (GET_MODE (x) == TImode) /* 128 bit division */
2482 *total = s390_cost->dlgr;
2483 else if (GET_MODE (x) == DImode)
2484 {
2485 rtx right = XEXP (x, 1);
2486 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2487 *total = s390_cost->dlr;
2488 else /* 64 by 64 bit division */
2489 *total = s390_cost->dlgr;
2490 }
2491 else if (GET_MODE (x) == SImode) /* 32 bit division */
2492 *total = s390_cost->dlr;
2493 return false;
2494
2495 case DIV:
2496 case MOD:
2497 if (GET_MODE (x) == DImode)
2498 {
2499 rtx right = XEXP (x, 1);
2500 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2501 if (TARGET_ZARCH)
2502 *total = s390_cost->dsgfr;
2503 else
2504 *total = s390_cost->dr;
2505 else /* 64 by 64 bit division */
2506 *total = s390_cost->dsgr;
2507 }
2508 else if (GET_MODE (x) == SImode) /* 32 bit division */
2509 *total = s390_cost->dlr;
2510 else if (GET_MODE (x) == SFmode)
2511 {
2512 *total = s390_cost->debr;
2513 }
2514 else if (GET_MODE (x) == DFmode)
2515 {
2516 *total = s390_cost->ddbr;
2517 }
2518 else if (GET_MODE (x) == TFmode)
2519 {
2520 *total = s390_cost->dxbr;
2521 }
2522 return false;
2523
2524 case SQRT:
2525 if (GET_MODE (x) == SFmode)
2526 *total = s390_cost->sqebr;
2527 else if (GET_MODE (x) == DFmode)
2528 *total = s390_cost->sqdbr;
2529 else /* TFmode */
2530 *total = s390_cost->sqxbr;
2531 return false;
2532
2533 case SIGN_EXTEND:
2534 case ZERO_EXTEND:
2535 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2536 || outer_code == PLUS || outer_code == MINUS
2537 || outer_code == COMPARE)
2538 *total = 0;
2539 return false;
2540
2541 case COMPARE:
2542 *total = COSTS_N_INSNS (1);
2543 if (GET_CODE (XEXP (x, 0)) == AND
2544 && GET_CODE (XEXP (x, 1)) == CONST_INT
2545 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2546 {
2547 rtx op0 = XEXP (XEXP (x, 0), 0);
2548 rtx op1 = XEXP (XEXP (x, 0), 1);
2549 rtx op2 = XEXP (x, 1);
2550
2551 if (memory_operand (op0, GET_MODE (op0))
2552 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2553 return true;
2554 if (register_operand (op0, GET_MODE (op0))
2555 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2556 return true;
2557 }
2558 return false;
2559
2560 default:
2561 return false;
2562 }
2563 }
2564
2565 /* Return the cost of an address rtx ADDR. */
2566
2567 static int
2568 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2569 {
2570 struct s390_address ad;
2571 if (!s390_decompose_address (addr, &ad))
2572 return 1000;
2573
2574 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2575 }
2576
2577 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2578 otherwise return 0. */
2579
2580 int
2581 tls_symbolic_operand (rtx op)
2582 {
2583 if (GET_CODE (op) != SYMBOL_REF)
2584 return 0;
2585 return SYMBOL_REF_TLS_MODEL (op);
2586 }
2587 \f
2588 /* Split DImode access register reference REG (on 64-bit) into its constituent
2589 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2590 gen_highpart cannot be used as they assume all registers are word-sized,
2591 while our access registers have only half that size. */
2592
2593 void
2594 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2595 {
2596 gcc_assert (TARGET_64BIT);
2597 gcc_assert (ACCESS_REG_P (reg));
2598 gcc_assert (GET_MODE (reg) == DImode);
2599 gcc_assert (!(REGNO (reg) & 1));
2600
2601 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2602 *hi = gen_rtx_REG (SImode, REGNO (reg));
2603 }
2604
2605 /* Return true if OP contains a symbol reference */
2606
2607 bool
2608 symbolic_reference_mentioned_p (rtx op)
2609 {
2610 const char *fmt;
2611 int i;
2612
2613 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2614 return 1;
2615
2616 fmt = GET_RTX_FORMAT (GET_CODE (op));
2617 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2618 {
2619 if (fmt[i] == 'E')
2620 {
2621 int j;
2622
2623 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2624 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2625 return 1;
2626 }
2627
2628 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2629 return 1;
2630 }
2631
2632 return 0;
2633 }
2634
2635 /* Return true if OP contains a reference to a thread-local symbol. */
2636
2637 bool
2638 tls_symbolic_reference_mentioned_p (rtx op)
2639 {
2640 const char *fmt;
2641 int i;
2642
2643 if (GET_CODE (op) == SYMBOL_REF)
2644 return tls_symbolic_operand (op);
2645
2646 fmt = GET_RTX_FORMAT (GET_CODE (op));
2647 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2648 {
2649 if (fmt[i] == 'E')
2650 {
2651 int j;
2652
2653 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2654 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2655 return true;
2656 }
2657
2658 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2659 return true;
2660 }
2661
2662 return false;
2663 }
2664
2665
2666 /* Return true if OP is a legitimate general operand when
2667 generating PIC code. It is given that flag_pic is on
2668 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2669
2670 int
2671 legitimate_pic_operand_p (rtx op)
2672 {
2673 /* Accept all non-symbolic constants. */
2674 if (!SYMBOLIC_CONST (op))
2675 return 1;
2676
2677 /* Reject everything else; must be handled
2678 via emit_symbolic_move. */
2679 return 0;
2680 }
2681
2682 /* Returns true if the constant value OP is a legitimate general operand.
2683 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2684
2685 int
2686 legitimate_constant_p (rtx op)
2687 {
2688 /* Accept all non-symbolic constants. */
2689 if (!SYMBOLIC_CONST (op))
2690 return 1;
2691
2692 /* Accept immediate LARL operands. */
2693 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2694 return 1;
2695
2696 /* Thread-local symbols are never legal constants. This is
2697 so that emit_call knows that computing such addresses
2698 might require a function call. */
2699 if (TLS_SYMBOLIC_CONST (op))
2700 return 0;
2701
2702 /* In the PIC case, symbolic constants must *not* be
2703 forced into the literal pool. We accept them here,
2704 so that they will be handled by emit_symbolic_move. */
2705 if (flag_pic)
2706 return 1;
2707
2708 /* All remaining non-PIC symbolic constants are
2709 forced into the literal pool. */
2710 return 0;
2711 }
2712
2713 /* Determine if it's legal to put X into the constant pool. This
2714 is not possible if X contains the address of a symbol that is
2715 not constant (TLS) or not known at final link time (PIC). */
2716
2717 static bool
2718 s390_cannot_force_const_mem (rtx x)
2719 {
2720 switch (GET_CODE (x))
2721 {
2722 case CONST_INT:
2723 case CONST_DOUBLE:
2724 /* Accept all non-symbolic constants. */
2725 return false;
2726
2727 case LABEL_REF:
2728 /* Labels are OK iff we are non-PIC. */
2729 return flag_pic != 0;
2730
2731 case SYMBOL_REF:
2732 /* 'Naked' TLS symbol references are never OK,
2733 non-TLS symbols are OK iff we are non-PIC. */
2734 if (tls_symbolic_operand (x))
2735 return true;
2736 else
2737 return flag_pic != 0;
2738
2739 case CONST:
2740 return s390_cannot_force_const_mem (XEXP (x, 0));
2741 case PLUS:
2742 case MINUS:
2743 return s390_cannot_force_const_mem (XEXP (x, 0))
2744 || s390_cannot_force_const_mem (XEXP (x, 1));
2745
2746 case UNSPEC:
2747 switch (XINT (x, 1))
2748 {
2749 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2750 case UNSPEC_LTREL_OFFSET:
2751 case UNSPEC_GOT:
2752 case UNSPEC_GOTOFF:
2753 case UNSPEC_PLTOFF:
2754 case UNSPEC_TLSGD:
2755 case UNSPEC_TLSLDM:
2756 case UNSPEC_NTPOFF:
2757 case UNSPEC_DTPOFF:
2758 case UNSPEC_GOTNTPOFF:
2759 case UNSPEC_INDNTPOFF:
2760 return false;
2761
2762 /* If the literal pool shares the code section, be put
2763 execute template placeholders into the pool as well. */
2764 case UNSPEC_INSN:
2765 return TARGET_CPU_ZARCH;
2766
2767 default:
2768 return true;
2769 }
2770 break;
2771
2772 default:
2773 gcc_unreachable ();
2774 }
2775 }
2776
2777 /* Returns true if the constant value OP is a legitimate general
2778 operand during and after reload. The difference to
2779 legitimate_constant_p is that this function will not accept
2780 a constant that would need to be forced to the literal pool
2781 before it can be used as operand. */
2782
2783 bool
2784 legitimate_reload_constant_p (rtx op)
2785 {
2786 /* Accept la(y) operands. */
2787 if (GET_CODE (op) == CONST_INT
2788 && DISP_IN_RANGE (INTVAL (op)))
2789 return true;
2790
2791 /* Accept l(g)hi/l(g)fi operands. */
2792 if (GET_CODE (op) == CONST_INT
2793 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2794 return true;
2795
2796 /* Accept lliXX operands. */
2797 if (TARGET_ZARCH
2798 && GET_CODE (op) == CONST_INT
2799 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2800 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2801 return true;
2802
2803 if (TARGET_EXTIMM
2804 && GET_CODE (op) == CONST_INT
2805 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2806 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2807 return true;
2808
2809 /* Accept larl operands. */
2810 if (TARGET_CPU_ZARCH
2811 && larl_operand (op, VOIDmode))
2812 return true;
2813
2814 /* Accept double-word operands that can be split. */
2815 if (GET_CODE (op) == CONST_INT
2816 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2817 {
2818 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2819 rtx hi = operand_subword (op, 0, 0, dword_mode);
2820 rtx lo = operand_subword (op, 1, 0, dword_mode);
2821 return legitimate_reload_constant_p (hi)
2822 && legitimate_reload_constant_p (lo);
2823 }
2824
2825 /* Everything else cannot be handled without reload. */
2826 return false;
2827 }
2828
2829 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2830 return the class of reg to actually use. */
2831
2832 enum reg_class
2833 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2834 {
2835 switch (GET_CODE (op))
2836 {
2837 /* Constants we cannot reload must be forced into the
2838 literal pool. */
2839
2840 case CONST_DOUBLE:
2841 case CONST_INT:
2842 if (legitimate_reload_constant_p (op))
2843 return rclass;
2844 else
2845 return NO_REGS;
2846
2847 /* If a symbolic constant or a PLUS is reloaded,
2848 it is most likely being used as an address, so
2849 prefer ADDR_REGS. If 'class' is not a superset
2850 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2851 case PLUS:
2852 case LABEL_REF:
2853 case SYMBOL_REF:
2854 case CONST:
2855 if (reg_class_subset_p (ADDR_REGS, rclass))
2856 return ADDR_REGS;
2857 else
2858 return NO_REGS;
2859
2860 default:
2861 break;
2862 }
2863
2864 return rclass;
2865 }
2866
2867 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2868 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2869 aligned. */
2870
2871 bool
2872 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2873 {
2874 HOST_WIDE_INT addend;
2875 rtx symref;
2876
2877 if (!s390_symref_operand_p (addr, &symref, &addend))
2878 return false;
2879
2880 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2881 && !(addend & (alignment - 1)));
2882 }
2883
2884 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2885 operand SCRATCH is used to reload the even part of the address and
2886 adding one. */
2887
2888 void
2889 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2890 {
2891 HOST_WIDE_INT addend;
2892 rtx symref;
2893
2894 if (!s390_symref_operand_p (addr, &symref, &addend))
2895 gcc_unreachable ();
2896
2897 if (!(addend & 1))
2898 /* Easy case. The addend is even so larl will do fine. */
2899 emit_move_insn (reg, addr);
2900 else
2901 {
2902 /* We can leave the scratch register untouched if the target
2903 register is a valid base register. */
2904 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2905 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2906 scratch = reg;
2907
2908 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2909 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2910
2911 if (addend != 1)
2912 emit_move_insn (scratch,
2913 gen_rtx_CONST (Pmode,
2914 gen_rtx_PLUS (Pmode, symref,
2915 GEN_INT (addend - 1))));
2916 else
2917 emit_move_insn (scratch, symref);
2918
2919 /* Increment the address using la in order to avoid clobbering cc. */
2920 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2921 }
2922 }
2923
2924 /* Generate what is necessary to move between REG and MEM using
2925 SCRATCH. The direction is given by TOMEM. */
2926
2927 void
2928 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2929 {
2930 /* Reload might have pulled a constant out of the literal pool.
2931 Force it back in. */
2932 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2933 || GET_CODE (mem) == CONST)
2934 mem = force_const_mem (GET_MODE (reg), mem);
2935
2936 gcc_assert (MEM_P (mem));
2937
2938 /* For a load from memory we can leave the scratch register
2939 untouched if the target register is a valid base register. */
2940 if (!tomem
2941 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2942 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2943 && GET_MODE (reg) == GET_MODE (scratch))
2944 scratch = reg;
2945
2946 /* Load address into scratch register. Since we can't have a
2947 secondary reload for a secondary reload we have to cover the case
2948 where larl would need a secondary reload here as well. */
2949 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2950
2951 /* Now we can use a standard load/store to do the move. */
2952 if (tomem)
2953 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2954 else
2955 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2956 }
2957
2958 /* Inform reload about cases where moving X with a mode MODE to a register in
2959 RCLASS requires an extra scratch or immediate register. Return the class
2960 needed for the immediate register. */
2961
2962 static reg_class_t
2963 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
2964 enum machine_mode mode, secondary_reload_info *sri)
2965 {
2966 enum reg_class rclass = (enum reg_class) rclass_i;
2967
2968 /* Intermediate register needed. */
2969 if (reg_classes_intersect_p (CC_REGS, rclass))
2970 return GENERAL_REGS;
2971
2972 if (TARGET_Z10)
2973 {
2974 /* On z10 several optimizer steps may generate larl operands with
2975 an odd addend. */
2976 if (in_p
2977 && s390_symref_operand_p (x, NULL, NULL)
2978 && mode == Pmode
2979 && !s390_check_symref_alignment (x, 2))
2980 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2981 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2982
2983 /* On z10 we need a scratch register when moving QI, TI or floating
2984 point mode values from or to a memory location with a SYMBOL_REF
2985 or if the symref addend of a SI or DI move is not aligned to the
2986 width of the access. */
2987 if (MEM_P (x)
2988 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2989 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2990 || (!TARGET_ZARCH && mode == DImode)
2991 || ((mode == HImode || mode == SImode || mode == DImode)
2992 && (!s390_check_symref_alignment (XEXP (x, 0),
2993 GET_MODE_SIZE (mode))))))
2994 {
2995 #define __SECONDARY_RELOAD_CASE(M,m) \
2996 case M##mode: \
2997 if (TARGET_64BIT) \
2998 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2999 CODE_FOR_reload##m##di_tomem_z10; \
3000 else \
3001 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3002 CODE_FOR_reload##m##si_tomem_z10; \
3003 break;
3004
3005 switch (GET_MODE (x))
3006 {
3007 __SECONDARY_RELOAD_CASE (QI, qi);
3008 __SECONDARY_RELOAD_CASE (HI, hi);
3009 __SECONDARY_RELOAD_CASE (SI, si);
3010 __SECONDARY_RELOAD_CASE (DI, di);
3011 __SECONDARY_RELOAD_CASE (TI, ti);
3012 __SECONDARY_RELOAD_CASE (SF, sf);
3013 __SECONDARY_RELOAD_CASE (DF, df);
3014 __SECONDARY_RELOAD_CASE (TF, tf);
3015 __SECONDARY_RELOAD_CASE (SD, sd);
3016 __SECONDARY_RELOAD_CASE (DD, dd);
3017 __SECONDARY_RELOAD_CASE (TD, td);
3018
3019 default:
3020 gcc_unreachable ();
3021 }
3022 #undef __SECONDARY_RELOAD_CASE
3023 }
3024 }
3025
3026 /* We need a scratch register when loading a PLUS expression which
3027 is not a legitimate operand of the LOAD ADDRESS instruction. */
3028 if (in_p && s390_plus_operand (x, mode))
3029 sri->icode = (TARGET_64BIT ?
3030 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3031
3032 /* Performing a multiword move from or to memory we have to make sure the
3033 second chunk in memory is addressable without causing a displacement
3034 overflow. If that would be the case we calculate the address in
3035 a scratch register. */
3036 if (MEM_P (x)
3037 && GET_CODE (XEXP (x, 0)) == PLUS
3038 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3039 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3040 + GET_MODE_SIZE (mode) - 1))
3041 {
3042 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3043 in a s_operand address since we may fallback to lm/stm. So we only
3044 have to care about overflows in the b+i+d case. */
3045 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3046 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3047 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3048 /* For FP_REGS no lm/stm is available so this check is triggered
3049 for displacement overflows in b+i+d and b+d like addresses. */
3050 || (reg_classes_intersect_p (FP_REGS, rclass)
3051 && s390_class_max_nregs (FP_REGS, mode) > 1))
3052 {
3053 if (in_p)
3054 sri->icode = (TARGET_64BIT ?
3055 CODE_FOR_reloaddi_nonoffmem_in :
3056 CODE_FOR_reloadsi_nonoffmem_in);
3057 else
3058 sri->icode = (TARGET_64BIT ?
3059 CODE_FOR_reloaddi_nonoffmem_out :
3060 CODE_FOR_reloadsi_nonoffmem_out);
3061 }
3062 }
3063
3064 /* A scratch address register is needed when a symbolic constant is
3065 copied to r0 compiling with -fPIC. In other cases the target
3066 register might be used as temporary (see legitimize_pic_address). */
3067 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3068 sri->icode = (TARGET_64BIT ?
3069 CODE_FOR_reloaddi_PIC_addr :
3070 CODE_FOR_reloadsi_PIC_addr);
3071
3072 /* Either scratch or no register needed. */
3073 return NO_REGS;
3074 }
3075
3076 /* Generate code to load SRC, which is PLUS that is not a
3077 legitimate operand for the LA instruction, into TARGET.
3078 SCRATCH may be used as scratch register. */
3079
3080 void
3081 s390_expand_plus_operand (rtx target, rtx src,
3082 rtx scratch)
3083 {
3084 rtx sum1, sum2;
3085 struct s390_address ad;
3086
3087 /* src must be a PLUS; get its two operands. */
3088 gcc_assert (GET_CODE (src) == PLUS);
3089 gcc_assert (GET_MODE (src) == Pmode);
3090
3091 /* Check if any of the two operands is already scheduled
3092 for replacement by reload. This can happen e.g. when
3093 float registers occur in an address. */
3094 sum1 = find_replacement (&XEXP (src, 0));
3095 sum2 = find_replacement (&XEXP (src, 1));
3096 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3097
3098 /* If the address is already strictly valid, there's nothing to do. */
3099 if (!s390_decompose_address (src, &ad)
3100 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3101 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3102 {
3103 /* Otherwise, one of the operands cannot be an address register;
3104 we reload its value into the scratch register. */
3105 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3106 {
3107 emit_move_insn (scratch, sum1);
3108 sum1 = scratch;
3109 }
3110 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3111 {
3112 emit_move_insn (scratch, sum2);
3113 sum2 = scratch;
3114 }
3115
3116 /* According to the way these invalid addresses are generated
3117 in reload.c, it should never happen (at least on s390) that
3118 *neither* of the PLUS components, after find_replacements
3119 was applied, is an address register. */
3120 if (sum1 == scratch && sum2 == scratch)
3121 {
3122 debug_rtx (src);
3123 gcc_unreachable ();
3124 }
3125
3126 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3127 }
3128
3129 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3130 is only ever performed on addresses, so we can mark the
3131 sum as legitimate for LA in any case. */
3132 s390_load_address (target, src);
3133 }
3134
3135
3136 /* Return true if ADDR is a valid memory address.
3137 STRICT specifies whether strict register checking applies. */
3138
3139 static bool
3140 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3141 {
3142 struct s390_address ad;
3143
3144 if (TARGET_Z10
3145 && larl_operand (addr, VOIDmode)
3146 && (mode == VOIDmode
3147 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3148 return true;
3149
3150 if (!s390_decompose_address (addr, &ad))
3151 return false;
3152
3153 if (strict)
3154 {
3155 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3156 return false;
3157
3158 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3159 return false;
3160 }
3161 else
3162 {
3163 if (ad.base
3164 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3165 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3166 return false;
3167
3168 if (ad.indx
3169 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3170 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3171 return false;
3172 }
3173 return true;
3174 }
3175
3176 /* Return true if OP is a valid operand for the LA instruction.
3177 In 31-bit, we need to prove that the result is used as an
3178 address, as LA performs only a 31-bit addition. */
3179
3180 bool
3181 legitimate_la_operand_p (rtx op)
3182 {
3183 struct s390_address addr;
3184 if (!s390_decompose_address (op, &addr))
3185 return false;
3186
3187 return (TARGET_64BIT || addr.pointer);
3188 }
3189
3190 /* Return true if it is valid *and* preferable to use LA to
3191 compute the sum of OP1 and OP2. */
3192
3193 bool
3194 preferred_la_operand_p (rtx op1, rtx op2)
3195 {
3196 struct s390_address addr;
3197
3198 if (op2 != const0_rtx)
3199 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3200
3201 if (!s390_decompose_address (op1, &addr))
3202 return false;
3203 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3204 return false;
3205 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3206 return false;
3207
3208 if (!TARGET_64BIT && !addr.pointer)
3209 return false;
3210
3211 if (addr.pointer)
3212 return true;
3213
3214 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3215 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3216 return true;
3217
3218 return false;
3219 }
3220
3221 /* Emit a forced load-address operation to load SRC into DST.
3222 This will use the LOAD ADDRESS instruction even in situations
3223 where legitimate_la_operand_p (SRC) returns false. */
3224
3225 void
3226 s390_load_address (rtx dst, rtx src)
3227 {
3228 if (TARGET_64BIT)
3229 emit_move_insn (dst, src);
3230 else
3231 emit_insn (gen_force_la_31 (dst, src));
3232 }
3233
3234 /* Return a legitimate reference for ORIG (an address) using the
3235 register REG. If REG is 0, a new pseudo is generated.
3236
3237 There are two types of references that must be handled:
3238
3239 1. Global data references must load the address from the GOT, via
3240 the PIC reg. An insn is emitted to do this load, and the reg is
3241 returned.
3242
3243 2. Static data references, constant pool addresses, and code labels
3244 compute the address as an offset from the GOT, whose base is in
3245 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3246 differentiate them from global data objects. The returned
3247 address is the PIC reg + an unspec constant.
3248
3249 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3250 reg also appears in the address. */
3251
3252 rtx
3253 legitimize_pic_address (rtx orig, rtx reg)
3254 {
3255 rtx addr = orig;
3256 rtx new_rtx = orig;
3257 rtx base;
3258
3259 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3260
3261 if (GET_CODE (addr) == LABEL_REF
3262 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3263 {
3264 /* This is a local symbol. */
3265 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3266 {
3267 /* Access local symbols PC-relative via LARL.
3268 This is the same as in the non-PIC case, so it is
3269 handled automatically ... */
3270 }
3271 else
3272 {
3273 /* Access local symbols relative to the GOT. */
3274
3275 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3276
3277 if (reload_in_progress || reload_completed)
3278 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3279
3280 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3281 addr = gen_rtx_CONST (Pmode, addr);
3282 addr = force_const_mem (Pmode, addr);
3283 emit_move_insn (temp, addr);
3284
3285 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3286 if (reg != 0)
3287 {
3288 s390_load_address (reg, new_rtx);
3289 new_rtx = reg;
3290 }
3291 }
3292 }
3293 else if (GET_CODE (addr) == SYMBOL_REF)
3294 {
3295 if (reg == 0)
3296 reg = gen_reg_rtx (Pmode);
3297
3298 if (flag_pic == 1)
3299 {
3300 /* Assume GOT offset < 4k. This is handled the same way
3301 in both 31- and 64-bit code (@GOT). */
3302
3303 if (reload_in_progress || reload_completed)
3304 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3305
3306 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3307 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3308 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3309 new_rtx = gen_const_mem (Pmode, new_rtx);
3310 emit_move_insn (reg, new_rtx);
3311 new_rtx = reg;
3312 }
3313 else if (TARGET_CPU_ZARCH)
3314 {
3315 /* If the GOT offset might be >= 4k, we determine the position
3316 of the GOT entry via a PC-relative LARL (@GOTENT). */
3317
3318 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3319
3320 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3321 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3322
3323 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3324 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3325 emit_move_insn (temp, new_rtx);
3326
3327 new_rtx = gen_const_mem (Pmode, temp);
3328 emit_move_insn (reg, new_rtx);
3329 new_rtx = reg;
3330 }
3331 else
3332 {
3333 /* If the GOT offset might be >= 4k, we have to load it
3334 from the literal pool (@GOT). */
3335
3336 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3337
3338 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3339 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3340
3341 if (reload_in_progress || reload_completed)
3342 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3343
3344 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3345 addr = gen_rtx_CONST (Pmode, addr);
3346 addr = force_const_mem (Pmode, addr);
3347 emit_move_insn (temp, addr);
3348
3349 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3350 new_rtx = gen_const_mem (Pmode, new_rtx);
3351 emit_move_insn (reg, new_rtx);
3352 new_rtx = reg;
3353 }
3354 }
3355 else
3356 {
3357 if (GET_CODE (addr) == CONST)
3358 {
3359 addr = XEXP (addr, 0);
3360 if (GET_CODE (addr) == UNSPEC)
3361 {
3362 gcc_assert (XVECLEN (addr, 0) == 1);
3363 switch (XINT (addr, 1))
3364 {
3365 /* If someone moved a GOT-relative UNSPEC
3366 out of the literal pool, force them back in. */
3367 case UNSPEC_GOTOFF:
3368 case UNSPEC_PLTOFF:
3369 new_rtx = force_const_mem (Pmode, orig);
3370 break;
3371
3372 /* @GOT is OK as is if small. */
3373 case UNSPEC_GOT:
3374 if (flag_pic == 2)
3375 new_rtx = force_const_mem (Pmode, orig);
3376 break;
3377
3378 /* @GOTENT is OK as is. */
3379 case UNSPEC_GOTENT:
3380 break;
3381
3382 /* @PLT is OK as is on 64-bit, must be converted to
3383 GOT-relative @PLTOFF on 31-bit. */
3384 case UNSPEC_PLT:
3385 if (!TARGET_CPU_ZARCH)
3386 {
3387 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3388
3389 if (reload_in_progress || reload_completed)
3390 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3391
3392 addr = XVECEXP (addr, 0, 0);
3393 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3394 UNSPEC_PLTOFF);
3395 addr = gen_rtx_CONST (Pmode, addr);
3396 addr = force_const_mem (Pmode, addr);
3397 emit_move_insn (temp, addr);
3398
3399 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3400 if (reg != 0)
3401 {
3402 s390_load_address (reg, new_rtx);
3403 new_rtx = reg;
3404 }
3405 }
3406 break;
3407
3408 /* Everything else cannot happen. */
3409 default:
3410 gcc_unreachable ();
3411 }
3412 }
3413 else
3414 gcc_assert (GET_CODE (addr) == PLUS);
3415 }
3416 if (GET_CODE (addr) == PLUS)
3417 {
3418 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3419
3420 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3421 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3422
3423 /* Check first to see if this is a constant offset
3424 from a local symbol reference. */
3425 if ((GET_CODE (op0) == LABEL_REF
3426 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3427 && GET_CODE (op1) == CONST_INT)
3428 {
3429 if (TARGET_CPU_ZARCH
3430 && larl_operand (op0, VOIDmode)
3431 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3432 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3433 {
3434 if (INTVAL (op1) & 1)
3435 {
3436 /* LARL can't handle odd offsets, so emit a
3437 pair of LARL and LA. */
3438 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3439
3440 if (!DISP_IN_RANGE (INTVAL (op1)))
3441 {
3442 HOST_WIDE_INT even = INTVAL (op1) - 1;
3443 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3444 op0 = gen_rtx_CONST (Pmode, op0);
3445 op1 = const1_rtx;
3446 }
3447
3448 emit_move_insn (temp, op0);
3449 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3450
3451 if (reg != 0)
3452 {
3453 s390_load_address (reg, new_rtx);
3454 new_rtx = reg;
3455 }
3456 }
3457 else
3458 {
3459 /* If the offset is even, we can just use LARL.
3460 This will happen automatically. */
3461 }
3462 }
3463 else
3464 {
3465 /* Access local symbols relative to the GOT. */
3466
3467 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3468
3469 if (reload_in_progress || reload_completed)
3470 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3471
3472 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3473 UNSPEC_GOTOFF);
3474 addr = gen_rtx_PLUS (Pmode, addr, op1);
3475 addr = gen_rtx_CONST (Pmode, addr);
3476 addr = force_const_mem (Pmode, addr);
3477 emit_move_insn (temp, addr);
3478
3479 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3480 if (reg != 0)
3481 {
3482 s390_load_address (reg, new_rtx);
3483 new_rtx = reg;
3484 }
3485 }
3486 }
3487
3488 /* Now, check whether it is a GOT relative symbol plus offset
3489 that was pulled out of the literal pool. Force it back in. */
3490
3491 else if (GET_CODE (op0) == UNSPEC
3492 && GET_CODE (op1) == CONST_INT
3493 && XINT (op0, 1) == UNSPEC_GOTOFF)
3494 {
3495 gcc_assert (XVECLEN (op0, 0) == 1);
3496
3497 new_rtx = force_const_mem (Pmode, orig);
3498 }
3499
3500 /* Otherwise, compute the sum. */
3501 else
3502 {
3503 base = legitimize_pic_address (XEXP (addr, 0), reg);
3504 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3505 base == reg ? NULL_RTX : reg);
3506 if (GET_CODE (new_rtx) == CONST_INT)
3507 new_rtx = plus_constant (base, INTVAL (new_rtx));
3508 else
3509 {
3510 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3511 {
3512 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3513 new_rtx = XEXP (new_rtx, 1);
3514 }
3515 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3516 }
3517
3518 if (GET_CODE (new_rtx) == CONST)
3519 new_rtx = XEXP (new_rtx, 0);
3520 new_rtx = force_operand (new_rtx, 0);
3521 }
3522 }
3523 }
3524 return new_rtx;
3525 }
3526
3527 /* Load the thread pointer into a register. */
3528
3529 rtx
3530 s390_get_thread_pointer (void)
3531 {
3532 rtx tp = gen_reg_rtx (Pmode);
3533
3534 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3535 mark_reg_pointer (tp, BITS_PER_WORD);
3536
3537 return tp;
3538 }
3539
3540 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3541 in s390_tls_symbol which always refers to __tls_get_offset.
3542 The returned offset is written to RESULT_REG and an USE rtx is
3543 generated for TLS_CALL. */
3544
3545 static GTY(()) rtx s390_tls_symbol;
3546
3547 static void
3548 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3549 {
3550 rtx insn;
3551
3552 gcc_assert (flag_pic);
3553
3554 if (!s390_tls_symbol)
3555 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3556
3557 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3558 gen_rtx_REG (Pmode, RETURN_REGNUM));
3559
3560 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3561 RTL_CONST_CALL_P (insn) = 1;
3562 }
3563
3564 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3565 this (thread-local) address. REG may be used as temporary. */
3566
3567 static rtx
3568 legitimize_tls_address (rtx addr, rtx reg)
3569 {
3570 rtx new_rtx, tls_call, temp, base, r2, insn;
3571
3572 if (GET_CODE (addr) == SYMBOL_REF)
3573 switch (tls_symbolic_operand (addr))
3574 {
3575 case TLS_MODEL_GLOBAL_DYNAMIC:
3576 start_sequence ();
3577 r2 = gen_rtx_REG (Pmode, 2);
3578 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3579 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3580 new_rtx = force_const_mem (Pmode, new_rtx);
3581 emit_move_insn (r2, new_rtx);
3582 s390_emit_tls_call_insn (r2, tls_call);
3583 insn = get_insns ();
3584 end_sequence ();
3585
3586 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3587 temp = gen_reg_rtx (Pmode);
3588 emit_libcall_block (insn, temp, r2, new_rtx);
3589
3590 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3591 if (reg != 0)
3592 {
3593 s390_load_address (reg, new_rtx);
3594 new_rtx = reg;
3595 }
3596 break;
3597
3598 case TLS_MODEL_LOCAL_DYNAMIC:
3599 start_sequence ();
3600 r2 = gen_rtx_REG (Pmode, 2);
3601 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3602 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3603 new_rtx = force_const_mem (Pmode, new_rtx);
3604 emit_move_insn (r2, new_rtx);
3605 s390_emit_tls_call_insn (r2, tls_call);
3606 insn = get_insns ();
3607 end_sequence ();
3608
3609 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3610 temp = gen_reg_rtx (Pmode);
3611 emit_libcall_block (insn, temp, r2, new_rtx);
3612
3613 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3614 base = gen_reg_rtx (Pmode);
3615 s390_load_address (base, new_rtx);
3616
3617 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3618 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3619 new_rtx = force_const_mem (Pmode, new_rtx);
3620 temp = gen_reg_rtx (Pmode);
3621 emit_move_insn (temp, new_rtx);
3622
3623 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3624 if (reg != 0)
3625 {
3626 s390_load_address (reg, new_rtx);
3627 new_rtx = reg;
3628 }
3629 break;
3630
3631 case TLS_MODEL_INITIAL_EXEC:
3632 if (flag_pic == 1)
3633 {
3634 /* Assume GOT offset < 4k. This is handled the same way
3635 in both 31- and 64-bit code. */
3636
3637 if (reload_in_progress || reload_completed)
3638 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3639
3640 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3641 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3642 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3643 new_rtx = gen_const_mem (Pmode, new_rtx);
3644 temp = gen_reg_rtx (Pmode);
3645 emit_move_insn (temp, new_rtx);
3646 }
3647 else if (TARGET_CPU_ZARCH)
3648 {
3649 /* If the GOT offset might be >= 4k, we determine the position
3650 of the GOT entry via a PC-relative LARL. */
3651
3652 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3653 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3654 temp = gen_reg_rtx (Pmode);
3655 emit_move_insn (temp, new_rtx);
3656
3657 new_rtx = gen_const_mem (Pmode, temp);
3658 temp = gen_reg_rtx (Pmode);
3659 emit_move_insn (temp, new_rtx);
3660 }
3661 else if (flag_pic)
3662 {
3663 /* If the GOT offset might be >= 4k, we have to load it
3664 from the literal pool. */
3665
3666 if (reload_in_progress || reload_completed)
3667 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3668
3669 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3670 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3671 new_rtx = force_const_mem (Pmode, new_rtx);
3672 temp = gen_reg_rtx (Pmode);
3673 emit_move_insn (temp, new_rtx);
3674
3675 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3676 new_rtx = gen_const_mem (Pmode, new_rtx);
3677
3678 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3679 temp = gen_reg_rtx (Pmode);
3680 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3681 }
3682 else
3683 {
3684 /* In position-dependent code, load the absolute address of
3685 the GOT entry from the literal pool. */
3686
3687 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3688 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3689 new_rtx = force_const_mem (Pmode, new_rtx);
3690 temp = gen_reg_rtx (Pmode);
3691 emit_move_insn (temp, new_rtx);
3692
3693 new_rtx = temp;
3694 new_rtx = gen_const_mem (Pmode, new_rtx);
3695 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3696 temp = gen_reg_rtx (Pmode);
3697 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3698 }
3699
3700 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3701 if (reg != 0)
3702 {
3703 s390_load_address (reg, new_rtx);
3704 new_rtx = reg;
3705 }
3706 break;
3707
3708 case TLS_MODEL_LOCAL_EXEC:
3709 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3710 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3711 new_rtx = force_const_mem (Pmode, new_rtx);
3712 temp = gen_reg_rtx (Pmode);
3713 emit_move_insn (temp, new_rtx);
3714
3715 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3716 if (reg != 0)
3717 {
3718 s390_load_address (reg, new_rtx);
3719 new_rtx = reg;
3720 }
3721 break;
3722
3723 default:
3724 gcc_unreachable ();
3725 }
3726
3727 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3728 {
3729 switch (XINT (XEXP (addr, 0), 1))
3730 {
3731 case UNSPEC_INDNTPOFF:
3732 gcc_assert (TARGET_CPU_ZARCH);
3733 new_rtx = addr;
3734 break;
3735
3736 default:
3737 gcc_unreachable ();
3738 }
3739 }
3740
3741 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3742 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3743 {
3744 new_rtx = XEXP (XEXP (addr, 0), 0);
3745 if (GET_CODE (new_rtx) != SYMBOL_REF)
3746 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3747
3748 new_rtx = legitimize_tls_address (new_rtx, reg);
3749 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3750 new_rtx = force_operand (new_rtx, 0);
3751 }
3752
3753 else
3754 gcc_unreachable (); /* for now ... */
3755
3756 return new_rtx;
3757 }
3758
3759 /* Emit insns making the address in operands[1] valid for a standard
3760 move to operands[0]. operands[1] is replaced by an address which
3761 should be used instead of the former RTX to emit the move
3762 pattern. */
3763
3764 void
3765 emit_symbolic_move (rtx *operands)
3766 {
3767 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3768
3769 if (GET_CODE (operands[0]) == MEM)
3770 operands[1] = force_reg (Pmode, operands[1]);
3771 else if (TLS_SYMBOLIC_CONST (operands[1]))
3772 operands[1] = legitimize_tls_address (operands[1], temp);
3773 else if (flag_pic)
3774 operands[1] = legitimize_pic_address (operands[1], temp);
3775 }
3776
3777 /* Try machine-dependent ways of modifying an illegitimate address X
3778 to be legitimate. If we find one, return the new, valid address.
3779
3780 OLDX is the address as it was before break_out_memory_refs was called.
3781 In some cases it is useful to look at this to decide what needs to be done.
3782
3783 MODE is the mode of the operand pointed to by X.
3784
3785 When -fpic is used, special handling is needed for symbolic references.
3786 See comments by legitimize_pic_address for details. */
3787
3788 static rtx
3789 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3790 enum machine_mode mode ATTRIBUTE_UNUSED)
3791 {
3792 rtx constant_term = const0_rtx;
3793
3794 if (TLS_SYMBOLIC_CONST (x))
3795 {
3796 x = legitimize_tls_address (x, 0);
3797
3798 if (s390_legitimate_address_p (mode, x, FALSE))
3799 return x;
3800 }
3801 else if (GET_CODE (x) == PLUS
3802 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3803 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3804 {
3805 return x;
3806 }
3807 else if (flag_pic)
3808 {
3809 if (SYMBOLIC_CONST (x)
3810 || (GET_CODE (x) == PLUS
3811 && (SYMBOLIC_CONST (XEXP (x, 0))
3812 || SYMBOLIC_CONST (XEXP (x, 1)))))
3813 x = legitimize_pic_address (x, 0);
3814
3815 if (s390_legitimate_address_p (mode, x, FALSE))
3816 return x;
3817 }
3818
3819 x = eliminate_constant_term (x, &constant_term);
3820
3821 /* Optimize loading of large displacements by splitting them
3822 into the multiple of 4K and the rest; this allows the
3823 former to be CSE'd if possible.
3824
3825 Don't do this if the displacement is added to a register
3826 pointing into the stack frame, as the offsets will
3827 change later anyway. */
3828
3829 if (GET_CODE (constant_term) == CONST_INT
3830 && !TARGET_LONG_DISPLACEMENT
3831 && !DISP_IN_RANGE (INTVAL (constant_term))
3832 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3833 {
3834 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3835 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3836
3837 rtx temp = gen_reg_rtx (Pmode);
3838 rtx val = force_operand (GEN_INT (upper), temp);
3839 if (val != temp)
3840 emit_move_insn (temp, val);
3841
3842 x = gen_rtx_PLUS (Pmode, x, temp);
3843 constant_term = GEN_INT (lower);
3844 }
3845
3846 if (GET_CODE (x) == PLUS)
3847 {
3848 if (GET_CODE (XEXP (x, 0)) == REG)
3849 {
3850 rtx temp = gen_reg_rtx (Pmode);
3851 rtx val = force_operand (XEXP (x, 1), temp);
3852 if (val != temp)
3853 emit_move_insn (temp, val);
3854
3855 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3856 }
3857
3858 else if (GET_CODE (XEXP (x, 1)) == REG)
3859 {
3860 rtx temp = gen_reg_rtx (Pmode);
3861 rtx val = force_operand (XEXP (x, 0), temp);
3862 if (val != temp)
3863 emit_move_insn (temp, val);
3864
3865 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3866 }
3867 }
3868
3869 if (constant_term != const0_rtx)
3870 x = gen_rtx_PLUS (Pmode, x, constant_term);
3871
3872 return x;
3873 }
3874
3875 /* Try a machine-dependent way of reloading an illegitimate address AD
3876 operand. If we find one, push the reload and and return the new address.
3877
3878 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3879 and TYPE is the reload type of the current reload. */
3880
3881 rtx
3882 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3883 int opnum, int type)
3884 {
3885 if (!optimize || TARGET_LONG_DISPLACEMENT)
3886 return NULL_RTX;
3887
3888 if (GET_CODE (ad) == PLUS)
3889 {
3890 rtx tem = simplify_binary_operation (PLUS, Pmode,
3891 XEXP (ad, 0), XEXP (ad, 1));
3892 if (tem)
3893 ad = tem;
3894 }
3895
3896 if (GET_CODE (ad) == PLUS
3897 && GET_CODE (XEXP (ad, 0)) == REG
3898 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3899 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3900 {
3901 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3902 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3903 rtx cst, tem, new_rtx;
3904
3905 cst = GEN_INT (upper);
3906 if (!legitimate_reload_constant_p (cst))
3907 cst = force_const_mem (Pmode, cst);
3908
3909 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3910 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3911
3912 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3913 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3914 opnum, (enum reload_type) type);
3915 return new_rtx;
3916 }
3917
3918 return NULL_RTX;
3919 }
3920
3921 /* Emit code to move LEN bytes from DST to SRC. */
3922
3923 void
3924 s390_expand_movmem (rtx dst, rtx src, rtx len)
3925 {
3926 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3927 {
3928 if (INTVAL (len) > 0)
3929 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3930 }
3931
3932 else if (TARGET_MVCLE)
3933 {
3934 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3935 }
3936
3937 else
3938 {
3939 rtx dst_addr, src_addr, count, blocks, temp;
3940 rtx loop_start_label = gen_label_rtx ();
3941 rtx loop_end_label = gen_label_rtx ();
3942 rtx end_label = gen_label_rtx ();
3943 enum machine_mode mode;
3944
3945 mode = GET_MODE (len);
3946 if (mode == VOIDmode)
3947 mode = Pmode;
3948
3949 dst_addr = gen_reg_rtx (Pmode);
3950 src_addr = gen_reg_rtx (Pmode);
3951 count = gen_reg_rtx (mode);
3952 blocks = gen_reg_rtx (mode);
3953
3954 convert_move (count, len, 1);
3955 emit_cmp_and_jump_insns (count, const0_rtx,
3956 EQ, NULL_RTX, mode, 1, end_label);
3957
3958 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3959 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3960 dst = change_address (dst, VOIDmode, dst_addr);
3961 src = change_address (src, VOIDmode, src_addr);
3962
3963 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3964 OPTAB_DIRECT);
3965 if (temp != count)
3966 emit_move_insn (count, temp);
3967
3968 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3969 OPTAB_DIRECT);
3970 if (temp != blocks)
3971 emit_move_insn (blocks, temp);
3972
3973 emit_cmp_and_jump_insns (blocks, const0_rtx,
3974 EQ, NULL_RTX, mode, 1, loop_end_label);
3975
3976 emit_label (loop_start_label);
3977
3978 if (TARGET_Z10
3979 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
3980 {
3981 rtx prefetch;
3982
3983 /* Issue a read prefetch for the +3 cache line. */
3984 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
3985 const0_rtx, const0_rtx);
3986 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3987 emit_insn (prefetch);
3988
3989 /* Issue a write prefetch for the +3 cache line. */
3990 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
3991 const1_rtx, const0_rtx);
3992 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3993 emit_insn (prefetch);
3994 }
3995
3996 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3997 s390_load_address (dst_addr,
3998 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3999 s390_load_address (src_addr,
4000 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4001
4002 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4003 OPTAB_DIRECT);
4004 if (temp != blocks)
4005 emit_move_insn (blocks, temp);
4006
4007 emit_cmp_and_jump_insns (blocks, const0_rtx,
4008 EQ, NULL_RTX, mode, 1, loop_end_label);
4009
4010 emit_jump (loop_start_label);
4011 emit_label (loop_end_label);
4012
4013 emit_insn (gen_movmem_short (dst, src,
4014 convert_to_mode (Pmode, count, 1)));
4015 emit_label (end_label);
4016 }
4017 }
4018
4019 /* Emit code to set LEN bytes at DST to VAL.
4020 Make use of clrmem if VAL is zero. */
4021
4022 void
4023 s390_expand_setmem (rtx dst, rtx len, rtx val)
4024 {
4025 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4026 return;
4027
4028 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4029
4030 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4031 {
4032 if (val == const0_rtx && INTVAL (len) <= 256)
4033 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4034 else
4035 {
4036 /* Initialize memory by storing the first byte. */
4037 emit_move_insn (adjust_address (dst, QImode, 0), val);
4038
4039 if (INTVAL (len) > 1)
4040 {
4041 /* Initiate 1 byte overlap move.
4042 The first byte of DST is propagated through DSTP1.
4043 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4044 DST is set to size 1 so the rest of the memory location
4045 does not count as source operand. */
4046 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4047 set_mem_size (dst, const1_rtx);
4048
4049 emit_insn (gen_movmem_short (dstp1, dst,
4050 GEN_INT (INTVAL (len) - 2)));
4051 }
4052 }
4053 }
4054
4055 else if (TARGET_MVCLE)
4056 {
4057 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4058 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4059 }
4060
4061 else
4062 {
4063 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4064 rtx loop_start_label = gen_label_rtx ();
4065 rtx loop_end_label = gen_label_rtx ();
4066 rtx end_label = gen_label_rtx ();
4067 enum machine_mode mode;
4068
4069 mode = GET_MODE (len);
4070 if (mode == VOIDmode)
4071 mode = Pmode;
4072
4073 dst_addr = gen_reg_rtx (Pmode);
4074 count = gen_reg_rtx (mode);
4075 blocks = gen_reg_rtx (mode);
4076
4077 convert_move (count, len, 1);
4078 emit_cmp_and_jump_insns (count, const0_rtx,
4079 EQ, NULL_RTX, mode, 1, end_label);
4080
4081 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4082 dst = change_address (dst, VOIDmode, dst_addr);
4083
4084 if (val == const0_rtx)
4085 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4086 OPTAB_DIRECT);
4087 else
4088 {
4089 dstp1 = adjust_address (dst, VOIDmode, 1);
4090 set_mem_size (dst, const1_rtx);
4091
4092 /* Initialize memory by storing the first byte. */
4093 emit_move_insn (adjust_address (dst, QImode, 0), val);
4094
4095 /* If count is 1 we are done. */
4096 emit_cmp_and_jump_insns (count, const1_rtx,
4097 EQ, NULL_RTX, mode, 1, end_label);
4098
4099 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4100 OPTAB_DIRECT);
4101 }
4102 if (temp != count)
4103 emit_move_insn (count, temp);
4104
4105 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4106 OPTAB_DIRECT);
4107 if (temp != blocks)
4108 emit_move_insn (blocks, temp);
4109
4110 emit_cmp_and_jump_insns (blocks, const0_rtx,
4111 EQ, NULL_RTX, mode, 1, loop_end_label);
4112
4113 emit_label (loop_start_label);
4114
4115 if (TARGET_Z10
4116 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4117 {
4118 /* Issue a write prefetch for the +4 cache line. */
4119 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4120 GEN_INT (1024)),
4121 const1_rtx, const0_rtx);
4122 emit_insn (prefetch);
4123 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4124 }
4125
4126 if (val == const0_rtx)
4127 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4128 else
4129 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4130 s390_load_address (dst_addr,
4131 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4132
4133 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4134 OPTAB_DIRECT);
4135 if (temp != blocks)
4136 emit_move_insn (blocks, temp);
4137
4138 emit_cmp_and_jump_insns (blocks, const0_rtx,
4139 EQ, NULL_RTX, mode, 1, loop_end_label);
4140
4141 emit_jump (loop_start_label);
4142 emit_label (loop_end_label);
4143
4144 if (val == const0_rtx)
4145 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4146 else
4147 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4148 emit_label (end_label);
4149 }
4150 }
4151
4152 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4153 and return the result in TARGET. */
4154
4155 void
4156 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4157 {
4158 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4159 rtx tmp;
4160
4161 /* As the result of CMPINT is inverted compared to what we need,
4162 we have to swap the operands. */
4163 tmp = op0; op0 = op1; op1 = tmp;
4164
4165 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4166 {
4167 if (INTVAL (len) > 0)
4168 {
4169 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4170 emit_insn (gen_cmpint (target, ccreg));
4171 }
4172 else
4173 emit_move_insn (target, const0_rtx);
4174 }
4175 else if (TARGET_MVCLE)
4176 {
4177 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4178 emit_insn (gen_cmpint (target, ccreg));
4179 }
4180 else
4181 {
4182 rtx addr0, addr1, count, blocks, temp;
4183 rtx loop_start_label = gen_label_rtx ();
4184 rtx loop_end_label = gen_label_rtx ();
4185 rtx end_label = gen_label_rtx ();
4186 enum machine_mode mode;
4187
4188 mode = GET_MODE (len);
4189 if (mode == VOIDmode)
4190 mode = Pmode;
4191
4192 addr0 = gen_reg_rtx (Pmode);
4193 addr1 = gen_reg_rtx (Pmode);
4194 count = gen_reg_rtx (mode);
4195 blocks = gen_reg_rtx (mode);
4196
4197 convert_move (count, len, 1);
4198 emit_cmp_and_jump_insns (count, const0_rtx,
4199 EQ, NULL_RTX, mode, 1, end_label);
4200
4201 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4202 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4203 op0 = change_address (op0, VOIDmode, addr0);
4204 op1 = change_address (op1, VOIDmode, addr1);
4205
4206 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4207 OPTAB_DIRECT);
4208 if (temp != count)
4209 emit_move_insn (count, temp);
4210
4211 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4212 OPTAB_DIRECT);
4213 if (temp != blocks)
4214 emit_move_insn (blocks, temp);
4215
4216 emit_cmp_and_jump_insns (blocks, const0_rtx,
4217 EQ, NULL_RTX, mode, 1, loop_end_label);
4218
4219 emit_label (loop_start_label);
4220
4221 if (TARGET_Z10
4222 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4223 {
4224 rtx prefetch;
4225
4226 /* Issue a read prefetch for the +2 cache line of operand 1. */
4227 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4228 const0_rtx, const0_rtx);
4229 emit_insn (prefetch);
4230 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4231
4232 /* Issue a read prefetch for the +2 cache line of operand 2. */
4233 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4234 const0_rtx, const0_rtx);
4235 emit_insn (prefetch);
4236 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4237 }
4238
4239 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4240 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4241 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4242 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4243 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4244 emit_jump_insn (temp);
4245
4246 s390_load_address (addr0,
4247 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4248 s390_load_address (addr1,
4249 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4250
4251 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4252 OPTAB_DIRECT);
4253 if (temp != blocks)
4254 emit_move_insn (blocks, temp);
4255
4256 emit_cmp_and_jump_insns (blocks, const0_rtx,
4257 EQ, NULL_RTX, mode, 1, loop_end_label);
4258
4259 emit_jump (loop_start_label);
4260 emit_label (loop_end_label);
4261
4262 emit_insn (gen_cmpmem_short (op0, op1,
4263 convert_to_mode (Pmode, count, 1)));
4264 emit_label (end_label);
4265
4266 emit_insn (gen_cmpint (target, ccreg));
4267 }
4268 }
4269
4270
4271 /* Expand conditional increment or decrement using alc/slb instructions.
4272 Should generate code setting DST to either SRC or SRC + INCREMENT,
4273 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4274 Returns true if successful, false otherwise.
4275
4276 That makes it possible to implement some if-constructs without jumps e.g.:
4277 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4278 unsigned int a, b, c;
4279 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4280 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4281 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4282 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4283
4284 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4285 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4286 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4287 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4288 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4289
4290 bool
4291 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4292 rtx dst, rtx src, rtx increment)
4293 {
4294 enum machine_mode cmp_mode;
4295 enum machine_mode cc_mode;
4296 rtx op_res;
4297 rtx insn;
4298 rtvec p;
4299 int ret;
4300
4301 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4302 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4303 cmp_mode = SImode;
4304 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4305 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4306 cmp_mode = DImode;
4307 else
4308 return false;
4309
4310 /* Try ADD LOGICAL WITH CARRY. */
4311 if (increment == const1_rtx)
4312 {
4313 /* Determine CC mode to use. */
4314 if (cmp_code == EQ || cmp_code == NE)
4315 {
4316 if (cmp_op1 != const0_rtx)
4317 {
4318 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4319 NULL_RTX, 0, OPTAB_WIDEN);
4320 cmp_op1 = const0_rtx;
4321 }
4322
4323 cmp_code = cmp_code == EQ ? LEU : GTU;
4324 }
4325
4326 if (cmp_code == LTU || cmp_code == LEU)
4327 {
4328 rtx tem = cmp_op0;
4329 cmp_op0 = cmp_op1;
4330 cmp_op1 = tem;
4331 cmp_code = swap_condition (cmp_code);
4332 }
4333
4334 switch (cmp_code)
4335 {
4336 case GTU:
4337 cc_mode = CCUmode;
4338 break;
4339
4340 case GEU:
4341 cc_mode = CCL3mode;
4342 break;
4343
4344 default:
4345 return false;
4346 }
4347
4348 /* Emit comparison instruction pattern. */
4349 if (!register_operand (cmp_op0, cmp_mode))
4350 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4351
4352 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4353 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4354 /* We use insn_invalid_p here to add clobbers if required. */
4355 ret = insn_invalid_p (emit_insn (insn));
4356 gcc_assert (!ret);
4357
4358 /* Emit ALC instruction pattern. */
4359 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4360 gen_rtx_REG (cc_mode, CC_REGNUM),
4361 const0_rtx);
4362
4363 if (src != const0_rtx)
4364 {
4365 if (!register_operand (src, GET_MODE (dst)))
4366 src = force_reg (GET_MODE (dst), src);
4367
4368 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4369 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4370 }
4371
4372 p = rtvec_alloc (2);
4373 RTVEC_ELT (p, 0) =
4374 gen_rtx_SET (VOIDmode, dst, op_res);
4375 RTVEC_ELT (p, 1) =
4376 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4377 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4378
4379 return true;
4380 }
4381
4382 /* Try SUBTRACT LOGICAL WITH BORROW. */
4383 if (increment == constm1_rtx)
4384 {
4385 /* Determine CC mode to use. */
4386 if (cmp_code == EQ || cmp_code == NE)
4387 {
4388 if (cmp_op1 != const0_rtx)
4389 {
4390 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4391 NULL_RTX, 0, OPTAB_WIDEN);
4392 cmp_op1 = const0_rtx;
4393 }
4394
4395 cmp_code = cmp_code == EQ ? LEU : GTU;
4396 }
4397
4398 if (cmp_code == GTU || cmp_code == GEU)
4399 {
4400 rtx tem = cmp_op0;
4401 cmp_op0 = cmp_op1;
4402 cmp_op1 = tem;
4403 cmp_code = swap_condition (cmp_code);
4404 }
4405
4406 switch (cmp_code)
4407 {
4408 case LEU:
4409 cc_mode = CCUmode;
4410 break;
4411
4412 case LTU:
4413 cc_mode = CCL3mode;
4414 break;
4415
4416 default:
4417 return false;
4418 }
4419
4420 /* Emit comparison instruction pattern. */
4421 if (!register_operand (cmp_op0, cmp_mode))
4422 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4423
4424 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4425 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4426 /* We use insn_invalid_p here to add clobbers if required. */
4427 ret = insn_invalid_p (emit_insn (insn));
4428 gcc_assert (!ret);
4429
4430 /* Emit SLB instruction pattern. */
4431 if (!register_operand (src, GET_MODE (dst)))
4432 src = force_reg (GET_MODE (dst), src);
4433
4434 op_res = gen_rtx_MINUS (GET_MODE (dst),
4435 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4436 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4437 gen_rtx_REG (cc_mode, CC_REGNUM),
4438 const0_rtx));
4439 p = rtvec_alloc (2);
4440 RTVEC_ELT (p, 0) =
4441 gen_rtx_SET (VOIDmode, dst, op_res);
4442 RTVEC_ELT (p, 1) =
4443 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4444 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4445
4446 return true;
4447 }
4448
4449 return false;
4450 }
4451
4452 /* Expand code for the insv template. Return true if successful. */
4453
4454 bool
4455 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4456 {
4457 int bitsize = INTVAL (op1);
4458 int bitpos = INTVAL (op2);
4459
4460 /* On z10 we can use the risbg instruction to implement insv. */
4461 if (TARGET_Z10
4462 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4463 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4464 {
4465 rtx op;
4466 rtx clobber;
4467
4468 op = gen_rtx_SET (GET_MODE(src),
4469 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4470 src);
4471 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4472 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4473
4474 return true;
4475 }
4476
4477 /* We need byte alignment. */
4478 if (bitsize % BITS_PER_UNIT)
4479 return false;
4480
4481 if (bitpos == 0
4482 && memory_operand (dest, VOIDmode)
4483 && (register_operand (src, word_mode)
4484 || const_int_operand (src, VOIDmode)))
4485 {
4486 /* Emit standard pattern if possible. */
4487 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4488 if (GET_MODE_BITSIZE (mode) == bitsize)
4489 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4490
4491 /* (set (ze (mem)) (const_int)). */
4492 else if (const_int_operand (src, VOIDmode))
4493 {
4494 int size = bitsize / BITS_PER_UNIT;
4495 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4496 GET_MODE_SIZE (word_mode) - size);
4497
4498 dest = adjust_address (dest, BLKmode, 0);
4499 set_mem_size (dest, GEN_INT (size));
4500 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4501 }
4502
4503 /* (set (ze (mem)) (reg)). */
4504 else if (register_operand (src, word_mode))
4505 {
4506 if (bitsize <= GET_MODE_BITSIZE (SImode))
4507 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4508 const0_rtx), src);
4509 else
4510 {
4511 /* Emit st,stcmh sequence. */
4512 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4513 int size = stcmh_width / BITS_PER_UNIT;
4514
4515 emit_move_insn (adjust_address (dest, SImode, size),
4516 gen_lowpart (SImode, src));
4517 set_mem_size (dest, GEN_INT (size));
4518 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4519 (stcmh_width), const0_rtx),
4520 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4521 (GET_MODE_BITSIZE (SImode))));
4522 }
4523 }
4524 else
4525 return false;
4526
4527 return true;
4528 }
4529
4530 /* (set (ze (reg)) (const_int)). */
4531 if (TARGET_ZARCH
4532 && register_operand (dest, word_mode)
4533 && (bitpos % 16) == 0
4534 && (bitsize % 16) == 0
4535 && const_int_operand (src, VOIDmode))
4536 {
4537 HOST_WIDE_INT val = INTVAL (src);
4538 int regpos = bitpos + bitsize;
4539
4540 while (regpos > bitpos)
4541 {
4542 enum machine_mode putmode;
4543 int putsize;
4544
4545 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4546 putmode = SImode;
4547 else
4548 putmode = HImode;
4549
4550 putsize = GET_MODE_BITSIZE (putmode);
4551 regpos -= putsize;
4552 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4553 GEN_INT (putsize),
4554 GEN_INT (regpos)),
4555 gen_int_mode (val, putmode));
4556 val >>= putsize;
4557 }
4558 gcc_assert (regpos == bitpos);
4559 return true;
4560 }
4561
4562 return false;
4563 }
4564
4565 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4566 register that holds VAL of mode MODE shifted by COUNT bits. */
4567
4568 static inline rtx
4569 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4570 {
4571 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4572 NULL_RTX, 1, OPTAB_DIRECT);
4573 return expand_simple_binop (SImode, ASHIFT, val, count,
4574 NULL_RTX, 1, OPTAB_DIRECT);
4575 }
4576
4577 /* Structure to hold the initial parameters for a compare_and_swap operation
4578 in HImode and QImode. */
4579
4580 struct alignment_context
4581 {
4582 rtx memsi; /* SI aligned memory location. */
4583 rtx shift; /* Bit offset with regard to lsb. */
4584 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4585 rtx modemaski; /* ~modemask */
4586 bool aligned; /* True if memory is aligned, false else. */
4587 };
4588
4589 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4590 structure AC for transparent simplifying, if the memory alignment is known
4591 to be at least 32bit. MEM is the memory location for the actual operation
4592 and MODE its mode. */
4593
4594 static void
4595 init_alignment_context (struct alignment_context *ac, rtx mem,
4596 enum machine_mode mode)
4597 {
4598 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4599 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4600
4601 if (ac->aligned)
4602 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4603 else
4604 {
4605 /* Alignment is unknown. */
4606 rtx byteoffset, addr, align;
4607
4608 /* Force the address into a register. */
4609 addr = force_reg (Pmode, XEXP (mem, 0));
4610
4611 /* Align it to SImode. */
4612 align = expand_simple_binop (Pmode, AND, addr,
4613 GEN_INT (-GET_MODE_SIZE (SImode)),
4614 NULL_RTX, 1, OPTAB_DIRECT);
4615 /* Generate MEM. */
4616 ac->memsi = gen_rtx_MEM (SImode, align);
4617 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4618 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4619 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4620
4621 /* Calculate shiftcount. */
4622 byteoffset = expand_simple_binop (Pmode, AND, addr,
4623 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4624 NULL_RTX, 1, OPTAB_DIRECT);
4625 /* As we already have some offset, evaluate the remaining distance. */
4626 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4627 NULL_RTX, 1, OPTAB_DIRECT);
4628
4629 }
4630 /* Shift is the byte count, but we need the bitcount. */
4631 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4632 NULL_RTX, 1, OPTAB_DIRECT);
4633 /* Calculate masks. */
4634 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4635 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4636 NULL_RTX, 1, OPTAB_DIRECT);
4637 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4638 }
4639
4640 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4641 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4642 to set if CMP == MEM.
4643 CMP is never in memory for compare_and_swap_cc because
4644 expand_bool_compare_and_swap puts it into a register for later compare. */
4645
4646 void
4647 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4648 {
4649 struct alignment_context ac;
4650 rtx cmpv, newv, val, resv, cc;
4651 rtx res = gen_reg_rtx (SImode);
4652 rtx csloop = gen_label_rtx ();
4653 rtx csend = gen_label_rtx ();
4654
4655 gcc_assert (register_operand (target, VOIDmode));
4656 gcc_assert (MEM_P (mem));
4657
4658 init_alignment_context (&ac, mem, mode);
4659
4660 /* Shift the values to the correct bit positions. */
4661 if (!(ac.aligned && MEM_P (cmp)))
4662 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4663 if (!(ac.aligned && MEM_P (new_rtx)))
4664 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4665
4666 /* Load full word. Subsequent loads are performed by CS. */
4667 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4668 NULL_RTX, 1, OPTAB_DIRECT);
4669
4670 /* Start CS loop. */
4671 emit_label (csloop);
4672 /* val = "<mem>00..0<mem>"
4673 * cmp = "00..0<cmp>00..0"
4674 * new = "00..0<new>00..0"
4675 */
4676
4677 /* Patch cmp and new with val at correct position. */
4678 if (ac.aligned && MEM_P (cmp))
4679 {
4680 cmpv = force_reg (SImode, val);
4681 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4682 }
4683 else
4684 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4685 NULL_RTX, 1, OPTAB_DIRECT));
4686 if (ac.aligned && MEM_P (new_rtx))
4687 {
4688 newv = force_reg (SImode, val);
4689 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4690 }
4691 else
4692 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4693 NULL_RTX, 1, OPTAB_DIRECT));
4694
4695 /* Jump to end if we're done (likely?). */
4696 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4697 cmpv, newv));
4698
4699 /* Check for changes outside mode. */
4700 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4701 NULL_RTX, 1, OPTAB_DIRECT);
4702 cc = s390_emit_compare (NE, resv, val);
4703 emit_move_insn (val, resv);
4704 /* Loop internal if so. */
4705 s390_emit_jump (csloop, cc);
4706
4707 emit_label (csend);
4708
4709 /* Return the correct part of the bitfield. */
4710 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4711 NULL_RTX, 1, OPTAB_DIRECT), 1);
4712 }
4713
4714 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4715 and VAL the value to play with. If AFTER is true then store the value
4716 MEM holds after the operation, if AFTER is false then store the value MEM
4717 holds before the operation. If TARGET is zero then discard that value, else
4718 store it to TARGET. */
4719
4720 void
4721 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4722 rtx target, rtx mem, rtx val, bool after)
4723 {
4724 struct alignment_context ac;
4725 rtx cmp;
4726 rtx new_rtx = gen_reg_rtx (SImode);
4727 rtx orig = gen_reg_rtx (SImode);
4728 rtx csloop = gen_label_rtx ();
4729
4730 gcc_assert (!target || register_operand (target, VOIDmode));
4731 gcc_assert (MEM_P (mem));
4732
4733 init_alignment_context (&ac, mem, mode);
4734
4735 /* Shift val to the correct bit positions.
4736 Preserve "icm", but prevent "ex icm". */
4737 if (!(ac.aligned && code == SET && MEM_P (val)))
4738 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4739
4740 /* Further preparation insns. */
4741 if (code == PLUS || code == MINUS)
4742 emit_move_insn (orig, val);
4743 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4744 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4745 NULL_RTX, 1, OPTAB_DIRECT);
4746
4747 /* Load full word. Subsequent loads are performed by CS. */
4748 cmp = force_reg (SImode, ac.memsi);
4749
4750 /* Start CS loop. */
4751 emit_label (csloop);
4752 emit_move_insn (new_rtx, cmp);
4753
4754 /* Patch new with val at correct position. */
4755 switch (code)
4756 {
4757 case PLUS:
4758 case MINUS:
4759 val = expand_simple_binop (SImode, code, new_rtx, orig,
4760 NULL_RTX, 1, OPTAB_DIRECT);
4761 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4762 NULL_RTX, 1, OPTAB_DIRECT);
4763 /* FALLTHRU */
4764 case SET:
4765 if (ac.aligned && MEM_P (val))
4766 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4767 else
4768 {
4769 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4770 NULL_RTX, 1, OPTAB_DIRECT);
4771 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4772 NULL_RTX, 1, OPTAB_DIRECT);
4773 }
4774 break;
4775 case AND:
4776 case IOR:
4777 case XOR:
4778 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4779 NULL_RTX, 1, OPTAB_DIRECT);
4780 break;
4781 case MULT: /* NAND */
4782 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4783 NULL_RTX, 1, OPTAB_DIRECT);
4784 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4785 NULL_RTX, 1, OPTAB_DIRECT);
4786 break;
4787 default:
4788 gcc_unreachable ();
4789 }
4790
4791 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4792 ac.memsi, cmp, new_rtx));
4793
4794 /* Return the correct part of the bitfield. */
4795 if (target)
4796 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4797 after ? new_rtx : cmp, ac.shift,
4798 NULL_RTX, 1, OPTAB_DIRECT), 1);
4799 }
4800
4801 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4802 We need to emit DTP-relative relocations. */
4803
4804 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4805
4806 static void
4807 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4808 {
4809 switch (size)
4810 {
4811 case 4:
4812 fputs ("\t.long\t", file);
4813 break;
4814 case 8:
4815 fputs ("\t.quad\t", file);
4816 break;
4817 default:
4818 gcc_unreachable ();
4819 }
4820 output_addr_const (file, x);
4821 fputs ("@DTPOFF", file);
4822 }
4823
4824 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4825 /* Implement TARGET_MANGLE_TYPE. */
4826
4827 static const char *
4828 s390_mangle_type (const_tree type)
4829 {
4830 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4831 && TARGET_LONG_DOUBLE_128)
4832 return "g";
4833
4834 /* For all other types, use normal C++ mangling. */
4835 return NULL;
4836 }
4837 #endif
4838
4839 /* In the name of slightly smaller debug output, and to cater to
4840 general assembler lossage, recognize various UNSPEC sequences
4841 and turn them back into a direct symbol reference. */
4842
4843 static rtx
4844 s390_delegitimize_address (rtx orig_x)
4845 {
4846 rtx x, y;
4847
4848 orig_x = delegitimize_mem_from_attrs (orig_x);
4849 x = orig_x;
4850 if (GET_CODE (x) != MEM)
4851 return orig_x;
4852
4853 x = XEXP (x, 0);
4854 if (GET_CODE (x) == PLUS
4855 && GET_CODE (XEXP (x, 1)) == CONST
4856 && GET_CODE (XEXP (x, 0)) == REG
4857 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4858 {
4859 y = XEXP (XEXP (x, 1), 0);
4860 if (GET_CODE (y) == UNSPEC
4861 && XINT (y, 1) == UNSPEC_GOT)
4862 return XVECEXP (y, 0, 0);
4863 return orig_x;
4864 }
4865
4866 if (GET_CODE (x) == CONST)
4867 {
4868 y = XEXP (x, 0);
4869 if (GET_CODE (y) == UNSPEC
4870 && XINT (y, 1) == UNSPEC_GOTENT)
4871 return XVECEXP (y, 0, 0);
4872 return orig_x;
4873 }
4874
4875 return orig_x;
4876 }
4877
4878 /* Output operand OP to stdio stream FILE.
4879 OP is an address (register + offset) which is not used to address data;
4880 instead the rightmost bits are interpreted as the value. */
4881
4882 static void
4883 print_shift_count_operand (FILE *file, rtx op)
4884 {
4885 HOST_WIDE_INT offset;
4886 rtx base;
4887
4888 /* Extract base register and offset. */
4889 if (!s390_decompose_shift_count (op, &base, &offset))
4890 gcc_unreachable ();
4891
4892 /* Sanity check. */
4893 if (base)
4894 {
4895 gcc_assert (GET_CODE (base) == REG);
4896 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4897 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4898 }
4899
4900 /* Offsets are constricted to twelve bits. */
4901 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4902 if (base)
4903 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4904 }
4905
4906 /* See 'get_some_local_dynamic_name'. */
4907
4908 static int
4909 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4910 {
4911 rtx x = *px;
4912
4913 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4914 {
4915 x = get_pool_constant (x);
4916 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4917 }
4918
4919 if (GET_CODE (x) == SYMBOL_REF
4920 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4921 {
4922 cfun->machine->some_ld_name = XSTR (x, 0);
4923 return 1;
4924 }
4925
4926 return 0;
4927 }
4928
4929 /* Locate some local-dynamic symbol still in use by this function
4930 so that we can print its name in local-dynamic base patterns. */
4931
4932 static const char *
4933 get_some_local_dynamic_name (void)
4934 {
4935 rtx insn;
4936
4937 if (cfun->machine->some_ld_name)
4938 return cfun->machine->some_ld_name;
4939
4940 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4941 if (INSN_P (insn)
4942 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4943 return cfun->machine->some_ld_name;
4944
4945 gcc_unreachable ();
4946 }
4947
4948 /* Output machine-dependent UNSPECs occurring in address constant X
4949 in assembler syntax to stdio stream FILE. Returns true if the
4950 constant X could be recognized, false otherwise. */
4951
4952 bool
4953 s390_output_addr_const_extra (FILE *file, rtx x)
4954 {
4955 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4956 switch (XINT (x, 1))
4957 {
4958 case UNSPEC_GOTENT:
4959 output_addr_const (file, XVECEXP (x, 0, 0));
4960 fprintf (file, "@GOTENT");
4961 return true;
4962 case UNSPEC_GOT:
4963 output_addr_const (file, XVECEXP (x, 0, 0));
4964 fprintf (file, "@GOT");
4965 return true;
4966 case UNSPEC_GOTOFF:
4967 output_addr_const (file, XVECEXP (x, 0, 0));
4968 fprintf (file, "@GOTOFF");
4969 return true;
4970 case UNSPEC_PLT:
4971 output_addr_const (file, XVECEXP (x, 0, 0));
4972 fprintf (file, "@PLT");
4973 return true;
4974 case UNSPEC_PLTOFF:
4975 output_addr_const (file, XVECEXP (x, 0, 0));
4976 fprintf (file, "@PLTOFF");
4977 return true;
4978 case UNSPEC_TLSGD:
4979 output_addr_const (file, XVECEXP (x, 0, 0));
4980 fprintf (file, "@TLSGD");
4981 return true;
4982 case UNSPEC_TLSLDM:
4983 assemble_name (file, get_some_local_dynamic_name ());
4984 fprintf (file, "@TLSLDM");
4985 return true;
4986 case UNSPEC_DTPOFF:
4987 output_addr_const (file, XVECEXP (x, 0, 0));
4988 fprintf (file, "@DTPOFF");
4989 return true;
4990 case UNSPEC_NTPOFF:
4991 output_addr_const (file, XVECEXP (x, 0, 0));
4992 fprintf (file, "@NTPOFF");
4993 return true;
4994 case UNSPEC_GOTNTPOFF:
4995 output_addr_const (file, XVECEXP (x, 0, 0));
4996 fprintf (file, "@GOTNTPOFF");
4997 return true;
4998 case UNSPEC_INDNTPOFF:
4999 output_addr_const (file, XVECEXP (x, 0, 0));
5000 fprintf (file, "@INDNTPOFF");
5001 return true;
5002 }
5003
5004 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5005 switch (XINT (x, 1))
5006 {
5007 case UNSPEC_POOL_OFFSET:
5008 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5009 output_addr_const (file, x);
5010 return true;
5011 }
5012 return false;
5013 }
5014
5015 /* Output address operand ADDR in assembler syntax to
5016 stdio stream FILE. */
5017
5018 void
5019 print_operand_address (FILE *file, rtx addr)
5020 {
5021 struct s390_address ad;
5022
5023 if (s390_symref_operand_p (addr, NULL, NULL))
5024 {
5025 gcc_assert (TARGET_Z10);
5026 output_addr_const (file, addr);
5027 return;
5028 }
5029
5030 if (!s390_decompose_address (addr, &ad)
5031 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5032 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5033 output_operand_lossage ("cannot decompose address");
5034
5035 if (ad.disp)
5036 output_addr_const (file, ad.disp);
5037 else
5038 fprintf (file, "0");
5039
5040 if (ad.base && ad.indx)
5041 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5042 reg_names[REGNO (ad.base)]);
5043 else if (ad.base)
5044 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5045 }
5046
5047 /* Output operand X in assembler syntax to stdio stream FILE.
5048 CODE specified the format flag. The following format flags
5049 are recognized:
5050
5051 'C': print opcode suffix for branch condition.
5052 'D': print opcode suffix for inverse branch condition.
5053 'E': print opcode suffix for branch on index instruction.
5054 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5055 'G': print the size of the operand in bytes.
5056 'O': print only the displacement of a memory reference.
5057 'R': print only the base register of a memory reference.
5058 'S': print S-type memory reference (base+displacement).
5059 'N': print the second word of a DImode operand.
5060 'M': print the second word of a TImode operand.
5061 'Y': print shift count operand.
5062
5063 'b': print integer X as if it's an unsigned byte.
5064 'c': print integer X as if it's an signed byte.
5065 'x': print integer X as if it's an unsigned halfword.
5066 'h': print integer X as if it's a signed halfword.
5067 'i': print the first nonzero HImode part of X.
5068 'j': print the first HImode part unequal to -1 of X.
5069 'k': print the first nonzero SImode part of X.
5070 'm': print the first SImode part unequal to -1 of X.
5071 'o': print integer X as if it's an unsigned 32bit word. */
5072
5073 void
5074 print_operand (FILE *file, rtx x, int code)
5075 {
5076 switch (code)
5077 {
5078 case 'C':
5079 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5080 return;
5081
5082 case 'D':
5083 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5084 return;
5085
5086 case 'E':
5087 if (GET_CODE (x) == LE)
5088 fprintf (file, "l");
5089 else if (GET_CODE (x) == GT)
5090 fprintf (file, "h");
5091 else
5092 gcc_unreachable ();
5093 return;
5094
5095 case 'J':
5096 if (GET_CODE (x) == SYMBOL_REF)
5097 {
5098 fprintf (file, "%s", ":tls_load:");
5099 output_addr_const (file, x);
5100 }
5101 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5102 {
5103 fprintf (file, "%s", ":tls_gdcall:");
5104 output_addr_const (file, XVECEXP (x, 0, 0));
5105 }
5106 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5107 {
5108 fprintf (file, "%s", ":tls_ldcall:");
5109 assemble_name (file, get_some_local_dynamic_name ());
5110 }
5111 else
5112 gcc_unreachable ();
5113 return;
5114
5115 case 'G':
5116 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5117 return;
5118
5119 case 'O':
5120 {
5121 struct s390_address ad;
5122 int ret;
5123
5124 gcc_assert (GET_CODE (x) == MEM);
5125 ret = s390_decompose_address (XEXP (x, 0), &ad);
5126 gcc_assert (ret);
5127 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5128 gcc_assert (!ad.indx);
5129
5130 if (ad.disp)
5131 output_addr_const (file, ad.disp);
5132 else
5133 fprintf (file, "0");
5134 }
5135 return;
5136
5137 case 'R':
5138 {
5139 struct s390_address ad;
5140 int ret;
5141
5142 gcc_assert (GET_CODE (x) == MEM);
5143 ret = s390_decompose_address (XEXP (x, 0), &ad);
5144 gcc_assert (ret);
5145 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5146 gcc_assert (!ad.indx);
5147
5148 if (ad.base)
5149 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5150 else
5151 fprintf (file, "0");
5152 }
5153 return;
5154
5155 case 'S':
5156 {
5157 struct s390_address ad;
5158 int ret;
5159
5160 gcc_assert (GET_CODE (x) == MEM);
5161 ret = s390_decompose_address (XEXP (x, 0), &ad);
5162 gcc_assert (ret);
5163 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5164 gcc_assert (!ad.indx);
5165
5166 if (ad.disp)
5167 output_addr_const (file, ad.disp);
5168 else
5169 fprintf (file, "0");
5170
5171 if (ad.base)
5172 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5173 }
5174 return;
5175
5176 case 'N':
5177 if (GET_CODE (x) == REG)
5178 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5179 else if (GET_CODE (x) == MEM)
5180 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5181 else
5182 gcc_unreachable ();
5183 break;
5184
5185 case 'M':
5186 if (GET_CODE (x) == REG)
5187 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5188 else if (GET_CODE (x) == MEM)
5189 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5190 else
5191 gcc_unreachable ();
5192 break;
5193
5194 case 'Y':
5195 print_shift_count_operand (file, x);
5196 return;
5197 }
5198
5199 switch (GET_CODE (x))
5200 {
5201 case REG:
5202 fprintf (file, "%s", reg_names[REGNO (x)]);
5203 break;
5204
5205 case MEM:
5206 output_address (XEXP (x, 0));
5207 break;
5208
5209 case CONST:
5210 case CODE_LABEL:
5211 case LABEL_REF:
5212 case SYMBOL_REF:
5213 output_addr_const (file, x);
5214 break;
5215
5216 case CONST_INT:
5217 if (code == 'b')
5218 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5219 else if (code == 'c')
5220 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5221 else if (code == 'x')
5222 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5223 else if (code == 'h')
5224 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5225 else if (code == 'i')
5226 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5227 s390_extract_part (x, HImode, 0));
5228 else if (code == 'j')
5229 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5230 s390_extract_part (x, HImode, -1));
5231 else if (code == 'k')
5232 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5233 s390_extract_part (x, SImode, 0));
5234 else if (code == 'm')
5235 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5236 s390_extract_part (x, SImode, -1));
5237 else if (code == 'o')
5238 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5239 else
5240 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5241 break;
5242
5243 case CONST_DOUBLE:
5244 gcc_assert (GET_MODE (x) == VOIDmode);
5245 if (code == 'b')
5246 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5247 else if (code == 'x')
5248 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5249 else if (code == 'h')
5250 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5251 else
5252 gcc_unreachable ();
5253 break;
5254
5255 default:
5256 fatal_insn ("UNKNOWN in print_operand !?", x);
5257 break;
5258 }
5259 }
5260
5261 /* Target hook for assembling integer objects. We need to define it
5262 here to work a round a bug in some versions of GAS, which couldn't
5263 handle values smaller than INT_MIN when printed in decimal. */
5264
5265 static bool
5266 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5267 {
5268 if (size == 8 && aligned_p
5269 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5270 {
5271 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5272 INTVAL (x));
5273 return true;
5274 }
5275 return default_assemble_integer (x, size, aligned_p);
5276 }
5277
5278 /* Returns true if register REGNO is used for forming
5279 a memory address in expression X. */
5280
5281 static bool
5282 reg_used_in_mem_p (int regno, rtx x)
5283 {
5284 enum rtx_code code = GET_CODE (x);
5285 int i, j;
5286 const char *fmt;
5287
5288 if (code == MEM)
5289 {
5290 if (refers_to_regno_p (regno, regno+1,
5291 XEXP (x, 0), 0))
5292 return true;
5293 }
5294 else if (code == SET
5295 && GET_CODE (SET_DEST (x)) == PC)
5296 {
5297 if (refers_to_regno_p (regno, regno+1,
5298 SET_SRC (x), 0))
5299 return true;
5300 }
5301
5302 fmt = GET_RTX_FORMAT (code);
5303 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5304 {
5305 if (fmt[i] == 'e'
5306 && reg_used_in_mem_p (regno, XEXP (x, i)))
5307 return true;
5308
5309 else if (fmt[i] == 'E')
5310 for (j = 0; j < XVECLEN (x, i); j++)
5311 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5312 return true;
5313 }
5314 return false;
5315 }
5316
5317 /* Returns true if expression DEP_RTX sets an address register
5318 used by instruction INSN to address memory. */
5319
5320 static bool
5321 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5322 {
5323 rtx target, pat;
5324
5325 if (GET_CODE (dep_rtx) == INSN)
5326 dep_rtx = PATTERN (dep_rtx);
5327
5328 if (GET_CODE (dep_rtx) == SET)
5329 {
5330 target = SET_DEST (dep_rtx);
5331 if (GET_CODE (target) == STRICT_LOW_PART)
5332 target = XEXP (target, 0);
5333 while (GET_CODE (target) == SUBREG)
5334 target = SUBREG_REG (target);
5335
5336 if (GET_CODE (target) == REG)
5337 {
5338 int regno = REGNO (target);
5339
5340 if (s390_safe_attr_type (insn) == TYPE_LA)
5341 {
5342 pat = PATTERN (insn);
5343 if (GET_CODE (pat) == PARALLEL)
5344 {
5345 gcc_assert (XVECLEN (pat, 0) == 2);
5346 pat = XVECEXP (pat, 0, 0);
5347 }
5348 gcc_assert (GET_CODE (pat) == SET);
5349 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5350 }
5351 else if (get_attr_atype (insn) == ATYPE_AGEN)
5352 return reg_used_in_mem_p (regno, PATTERN (insn));
5353 }
5354 }
5355 return false;
5356 }
5357
5358 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5359
5360 int
5361 s390_agen_dep_p (rtx dep_insn, rtx insn)
5362 {
5363 rtx dep_rtx = PATTERN (dep_insn);
5364 int i;
5365
5366 if (GET_CODE (dep_rtx) == SET
5367 && addr_generation_dependency_p (dep_rtx, insn))
5368 return 1;
5369 else if (GET_CODE (dep_rtx) == PARALLEL)
5370 {
5371 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5372 {
5373 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5374 return 1;
5375 }
5376 }
5377 return 0;
5378 }
5379
5380
5381 /* A C statement (sans semicolon) to update the integer scheduling priority
5382 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5383 reduce the priority to execute INSN later. Do not define this macro if
5384 you do not need to adjust the scheduling priorities of insns.
5385
5386 A STD instruction should be scheduled earlier,
5387 in order to use the bypass. */
5388
5389
5390 static int
5391 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5392 {
5393 if (! INSN_P (insn))
5394 return priority;
5395
5396 if (s390_tune != PROCESSOR_2084_Z990
5397 && s390_tune != PROCESSOR_2094_Z9_109
5398 && s390_tune != PROCESSOR_2097_Z10)
5399 return priority;
5400
5401 switch (s390_safe_attr_type (insn))
5402 {
5403 case TYPE_FSTOREDF:
5404 case TYPE_FSTORESF:
5405 priority = priority << 3;
5406 break;
5407 case TYPE_STORE:
5408 case TYPE_STM:
5409 priority = priority << 1;
5410 break;
5411 default:
5412 break;
5413 }
5414 return priority;
5415 }
5416
5417
5418 /* The number of instructions that can be issued per cycle. */
5419
5420 static int
5421 s390_issue_rate (void)
5422 {
5423 switch (s390_tune)
5424 {
5425 case PROCESSOR_2084_Z990:
5426 case PROCESSOR_2094_Z9_109:
5427 return 3;
5428 case PROCESSOR_2097_Z10:
5429 return 2;
5430 default:
5431 return 1;
5432 }
5433 }
5434
5435 static int
5436 s390_first_cycle_multipass_dfa_lookahead (void)
5437 {
5438 return 4;
5439 }
5440
5441 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5442 Fix up MEMs as required. */
5443
5444 static void
5445 annotate_constant_pool_refs (rtx *x)
5446 {
5447 int i, j;
5448 const char *fmt;
5449
5450 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5451 || !CONSTANT_POOL_ADDRESS_P (*x));
5452
5453 /* Literal pool references can only occur inside a MEM ... */
5454 if (GET_CODE (*x) == MEM)
5455 {
5456 rtx memref = XEXP (*x, 0);
5457
5458 if (GET_CODE (memref) == SYMBOL_REF
5459 && CONSTANT_POOL_ADDRESS_P (memref))
5460 {
5461 rtx base = cfun->machine->base_reg;
5462 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5463 UNSPEC_LTREF);
5464
5465 *x = replace_equiv_address (*x, addr);
5466 return;
5467 }
5468
5469 if (GET_CODE (memref) == CONST
5470 && GET_CODE (XEXP (memref, 0)) == PLUS
5471 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5472 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5473 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5474 {
5475 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5476 rtx sym = XEXP (XEXP (memref, 0), 0);
5477 rtx base = cfun->machine->base_reg;
5478 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5479 UNSPEC_LTREF);
5480
5481 *x = replace_equiv_address (*x, plus_constant (addr, off));
5482 return;
5483 }
5484 }
5485
5486 /* ... or a load-address type pattern. */
5487 if (GET_CODE (*x) == SET)
5488 {
5489 rtx addrref = SET_SRC (*x);
5490
5491 if (GET_CODE (addrref) == SYMBOL_REF
5492 && CONSTANT_POOL_ADDRESS_P (addrref))
5493 {
5494 rtx base = cfun->machine->base_reg;
5495 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5496 UNSPEC_LTREF);
5497
5498 SET_SRC (*x) = addr;
5499 return;
5500 }
5501
5502 if (GET_CODE (addrref) == CONST
5503 && GET_CODE (XEXP (addrref, 0)) == PLUS
5504 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5505 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5506 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5507 {
5508 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5509 rtx sym = XEXP (XEXP (addrref, 0), 0);
5510 rtx base = cfun->machine->base_reg;
5511 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5512 UNSPEC_LTREF);
5513
5514 SET_SRC (*x) = plus_constant (addr, off);
5515 return;
5516 }
5517 }
5518
5519 /* Annotate LTREL_BASE as well. */
5520 if (GET_CODE (*x) == UNSPEC
5521 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5522 {
5523 rtx base = cfun->machine->base_reg;
5524 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5525 UNSPEC_LTREL_BASE);
5526 return;
5527 }
5528
5529 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5530 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5531 {
5532 if (fmt[i] == 'e')
5533 {
5534 annotate_constant_pool_refs (&XEXP (*x, i));
5535 }
5536 else if (fmt[i] == 'E')
5537 {
5538 for (j = 0; j < XVECLEN (*x, i); j++)
5539 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5540 }
5541 }
5542 }
5543
5544 /* Split all branches that exceed the maximum distance.
5545 Returns true if this created a new literal pool entry. */
5546
5547 static int
5548 s390_split_branches (void)
5549 {
5550 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5551 int new_literal = 0, ret;
5552 rtx insn, pat, tmp, target;
5553 rtx *label;
5554
5555 /* We need correct insn addresses. */
5556
5557 shorten_branches (get_insns ());
5558
5559 /* Find all branches that exceed 64KB, and split them. */
5560
5561 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5562 {
5563 if (GET_CODE (insn) != JUMP_INSN)
5564 continue;
5565
5566 pat = PATTERN (insn);
5567 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5568 pat = XVECEXP (pat, 0, 0);
5569 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5570 continue;
5571
5572 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5573 {
5574 label = &SET_SRC (pat);
5575 }
5576 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5577 {
5578 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5579 label = &XEXP (SET_SRC (pat), 1);
5580 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5581 label = &XEXP (SET_SRC (pat), 2);
5582 else
5583 continue;
5584 }
5585 else
5586 continue;
5587
5588 if (get_attr_length (insn) <= 4)
5589 continue;
5590
5591 /* We are going to use the return register as scratch register,
5592 make sure it will be saved/restored by the prologue/epilogue. */
5593 cfun_frame_layout.save_return_addr_p = 1;
5594
5595 if (!flag_pic)
5596 {
5597 new_literal = 1;
5598 tmp = force_const_mem (Pmode, *label);
5599 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5600 INSN_ADDRESSES_NEW (tmp, -1);
5601 annotate_constant_pool_refs (&PATTERN (tmp));
5602
5603 target = temp_reg;
5604 }
5605 else
5606 {
5607 new_literal = 1;
5608 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5609 UNSPEC_LTREL_OFFSET);
5610 target = gen_rtx_CONST (Pmode, target);
5611 target = force_const_mem (Pmode, target);
5612 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5613 INSN_ADDRESSES_NEW (tmp, -1);
5614 annotate_constant_pool_refs (&PATTERN (tmp));
5615
5616 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5617 cfun->machine->base_reg),
5618 UNSPEC_LTREL_BASE);
5619 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5620 }
5621
5622 ret = validate_change (insn, label, target, 0);
5623 gcc_assert (ret);
5624 }
5625
5626 return new_literal;
5627 }
5628
5629
5630 /* Find an annotated literal pool symbol referenced in RTX X,
5631 and store it at REF. Will abort if X contains references to
5632 more than one such pool symbol; multiple references to the same
5633 symbol are allowed, however.
5634
5635 The rtx pointed to by REF must be initialized to NULL_RTX
5636 by the caller before calling this routine. */
5637
5638 static void
5639 find_constant_pool_ref (rtx x, rtx *ref)
5640 {
5641 int i, j;
5642 const char *fmt;
5643
5644 /* Ignore LTREL_BASE references. */
5645 if (GET_CODE (x) == UNSPEC
5646 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5647 return;
5648 /* Likewise POOL_ENTRY insns. */
5649 if (GET_CODE (x) == UNSPEC_VOLATILE
5650 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5651 return;
5652
5653 gcc_assert (GET_CODE (x) != SYMBOL_REF
5654 || !CONSTANT_POOL_ADDRESS_P (x));
5655
5656 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5657 {
5658 rtx sym = XVECEXP (x, 0, 0);
5659 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5660 && CONSTANT_POOL_ADDRESS_P (sym));
5661
5662 if (*ref == NULL_RTX)
5663 *ref = sym;
5664 else
5665 gcc_assert (*ref == sym);
5666
5667 return;
5668 }
5669
5670 fmt = GET_RTX_FORMAT (GET_CODE (x));
5671 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5672 {
5673 if (fmt[i] == 'e')
5674 {
5675 find_constant_pool_ref (XEXP (x, i), ref);
5676 }
5677 else if (fmt[i] == 'E')
5678 {
5679 for (j = 0; j < XVECLEN (x, i); j++)
5680 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5681 }
5682 }
5683 }
5684
5685 /* Replace every reference to the annotated literal pool
5686 symbol REF in X by its base plus OFFSET. */
5687
5688 static void
5689 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5690 {
5691 int i, j;
5692 const char *fmt;
5693
5694 gcc_assert (*x != ref);
5695
5696 if (GET_CODE (*x) == UNSPEC
5697 && XINT (*x, 1) == UNSPEC_LTREF
5698 && XVECEXP (*x, 0, 0) == ref)
5699 {
5700 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5701 return;
5702 }
5703
5704 if (GET_CODE (*x) == PLUS
5705 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5706 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5707 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5708 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5709 {
5710 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5711 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5712 return;
5713 }
5714
5715 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5716 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5717 {
5718 if (fmt[i] == 'e')
5719 {
5720 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5721 }
5722 else if (fmt[i] == 'E')
5723 {
5724 for (j = 0; j < XVECLEN (*x, i); j++)
5725 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5726 }
5727 }
5728 }
5729
5730 /* Check whether X contains an UNSPEC_LTREL_BASE.
5731 Return its constant pool symbol if found, NULL_RTX otherwise. */
5732
5733 static rtx
5734 find_ltrel_base (rtx x)
5735 {
5736 int i, j;
5737 const char *fmt;
5738
5739 if (GET_CODE (x) == UNSPEC
5740 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5741 return XVECEXP (x, 0, 0);
5742
5743 fmt = GET_RTX_FORMAT (GET_CODE (x));
5744 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5745 {
5746 if (fmt[i] == 'e')
5747 {
5748 rtx fnd = find_ltrel_base (XEXP (x, i));
5749 if (fnd)
5750 return fnd;
5751 }
5752 else if (fmt[i] == 'E')
5753 {
5754 for (j = 0; j < XVECLEN (x, i); j++)
5755 {
5756 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5757 if (fnd)
5758 return fnd;
5759 }
5760 }
5761 }
5762
5763 return NULL_RTX;
5764 }
5765
5766 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5767
5768 static void
5769 replace_ltrel_base (rtx *x)
5770 {
5771 int i, j;
5772 const char *fmt;
5773
5774 if (GET_CODE (*x) == UNSPEC
5775 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5776 {
5777 *x = XVECEXP (*x, 0, 1);
5778 return;
5779 }
5780
5781 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5782 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5783 {
5784 if (fmt[i] == 'e')
5785 {
5786 replace_ltrel_base (&XEXP (*x, i));
5787 }
5788 else if (fmt[i] == 'E')
5789 {
5790 for (j = 0; j < XVECLEN (*x, i); j++)
5791 replace_ltrel_base (&XVECEXP (*x, i, j));
5792 }
5793 }
5794 }
5795
5796
5797 /* We keep a list of constants which we have to add to internal
5798 constant tables in the middle of large functions. */
5799
5800 #define NR_C_MODES 11
5801 enum machine_mode constant_modes[NR_C_MODES] =
5802 {
5803 TFmode, TImode, TDmode,
5804 DFmode, DImode, DDmode,
5805 SFmode, SImode, SDmode,
5806 HImode,
5807 QImode
5808 };
5809
5810 struct constant
5811 {
5812 struct constant *next;
5813 rtx value;
5814 rtx label;
5815 };
5816
5817 struct constant_pool
5818 {
5819 struct constant_pool *next;
5820 rtx first_insn;
5821 rtx pool_insn;
5822 bitmap insns;
5823 rtx emit_pool_after;
5824
5825 struct constant *constants[NR_C_MODES];
5826 struct constant *execute;
5827 rtx label;
5828 int size;
5829 };
5830
5831 /* Allocate new constant_pool structure. */
5832
5833 static struct constant_pool *
5834 s390_alloc_pool (void)
5835 {
5836 struct constant_pool *pool;
5837 int i;
5838
5839 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5840 pool->next = NULL;
5841 for (i = 0; i < NR_C_MODES; i++)
5842 pool->constants[i] = NULL;
5843
5844 pool->execute = NULL;
5845 pool->label = gen_label_rtx ();
5846 pool->first_insn = NULL_RTX;
5847 pool->pool_insn = NULL_RTX;
5848 pool->insns = BITMAP_ALLOC (NULL);
5849 pool->size = 0;
5850 pool->emit_pool_after = NULL_RTX;
5851
5852 return pool;
5853 }
5854
5855 /* Create new constant pool covering instructions starting at INSN
5856 and chain it to the end of POOL_LIST. */
5857
5858 static struct constant_pool *
5859 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5860 {
5861 struct constant_pool *pool, **prev;
5862
5863 pool = s390_alloc_pool ();
5864 pool->first_insn = insn;
5865
5866 for (prev = pool_list; *prev; prev = &(*prev)->next)
5867 ;
5868 *prev = pool;
5869
5870 return pool;
5871 }
5872
5873 /* End range of instructions covered by POOL at INSN and emit
5874 placeholder insn representing the pool. */
5875
5876 static void
5877 s390_end_pool (struct constant_pool *pool, rtx insn)
5878 {
5879 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5880
5881 if (!insn)
5882 insn = get_last_insn ();
5883
5884 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5885 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5886 }
5887
5888 /* Add INSN to the list of insns covered by POOL. */
5889
5890 static void
5891 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5892 {
5893 bitmap_set_bit (pool->insns, INSN_UID (insn));
5894 }
5895
5896 /* Return pool out of POOL_LIST that covers INSN. */
5897
5898 static struct constant_pool *
5899 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5900 {
5901 struct constant_pool *pool;
5902
5903 for (pool = pool_list; pool; pool = pool->next)
5904 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5905 break;
5906
5907 return pool;
5908 }
5909
5910 /* Add constant VAL of mode MODE to the constant pool POOL. */
5911
5912 static void
5913 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5914 {
5915 struct constant *c;
5916 int i;
5917
5918 for (i = 0; i < NR_C_MODES; i++)
5919 if (constant_modes[i] == mode)
5920 break;
5921 gcc_assert (i != NR_C_MODES);
5922
5923 for (c = pool->constants[i]; c != NULL; c = c->next)
5924 if (rtx_equal_p (val, c->value))
5925 break;
5926
5927 if (c == NULL)
5928 {
5929 c = (struct constant *) xmalloc (sizeof *c);
5930 c->value = val;
5931 c->label = gen_label_rtx ();
5932 c->next = pool->constants[i];
5933 pool->constants[i] = c;
5934 pool->size += GET_MODE_SIZE (mode);
5935 }
5936 }
5937
5938 /* Return an rtx that represents the offset of X from the start of
5939 pool POOL. */
5940
5941 static rtx
5942 s390_pool_offset (struct constant_pool *pool, rtx x)
5943 {
5944 rtx label;
5945
5946 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5947 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5948 UNSPEC_POOL_OFFSET);
5949 return gen_rtx_CONST (GET_MODE (x), x);
5950 }
5951
5952 /* Find constant VAL of mode MODE in the constant pool POOL.
5953 Return an RTX describing the distance from the start of
5954 the pool to the location of the new constant. */
5955
5956 static rtx
5957 s390_find_constant (struct constant_pool *pool, rtx val,
5958 enum machine_mode mode)
5959 {
5960 struct constant *c;
5961 int i;
5962
5963 for (i = 0; i < NR_C_MODES; i++)
5964 if (constant_modes[i] == mode)
5965 break;
5966 gcc_assert (i != NR_C_MODES);
5967
5968 for (c = pool->constants[i]; c != NULL; c = c->next)
5969 if (rtx_equal_p (val, c->value))
5970 break;
5971
5972 gcc_assert (c);
5973
5974 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5975 }
5976
5977 /* Check whether INSN is an execute. Return the label_ref to its
5978 execute target template if so, NULL_RTX otherwise. */
5979
5980 static rtx
5981 s390_execute_label (rtx insn)
5982 {
5983 if (GET_CODE (insn) == INSN
5984 && GET_CODE (PATTERN (insn)) == PARALLEL
5985 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5986 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5987 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5988
5989 return NULL_RTX;
5990 }
5991
5992 /* Add execute target for INSN to the constant pool POOL. */
5993
5994 static void
5995 s390_add_execute (struct constant_pool *pool, rtx insn)
5996 {
5997 struct constant *c;
5998
5999 for (c = pool->execute; c != NULL; c = c->next)
6000 if (INSN_UID (insn) == INSN_UID (c->value))
6001 break;
6002
6003 if (c == NULL)
6004 {
6005 c = (struct constant *) xmalloc (sizeof *c);
6006 c->value = insn;
6007 c->label = gen_label_rtx ();
6008 c->next = pool->execute;
6009 pool->execute = c;
6010 pool->size += 6;
6011 }
6012 }
6013
6014 /* Find execute target for INSN in the constant pool POOL.
6015 Return an RTX describing the distance from the start of
6016 the pool to the location of the execute target. */
6017
6018 static rtx
6019 s390_find_execute (struct constant_pool *pool, rtx insn)
6020 {
6021 struct constant *c;
6022
6023 for (c = pool->execute; c != NULL; c = c->next)
6024 if (INSN_UID (insn) == INSN_UID (c->value))
6025 break;
6026
6027 gcc_assert (c);
6028
6029 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6030 }
6031
6032 /* For an execute INSN, extract the execute target template. */
6033
6034 static rtx
6035 s390_execute_target (rtx insn)
6036 {
6037 rtx pattern = PATTERN (insn);
6038 gcc_assert (s390_execute_label (insn));
6039
6040 if (XVECLEN (pattern, 0) == 2)
6041 {
6042 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6043 }
6044 else
6045 {
6046 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6047 int i;
6048
6049 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6050 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6051
6052 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6053 }
6054
6055 return pattern;
6056 }
6057
6058 /* Indicate that INSN cannot be duplicated. This is the case for
6059 execute insns that carry a unique label. */
6060
6061 static bool
6062 s390_cannot_copy_insn_p (rtx insn)
6063 {
6064 rtx label = s390_execute_label (insn);
6065 return label && label != const0_rtx;
6066 }
6067
6068 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6069 do not emit the pool base label. */
6070
6071 static void
6072 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6073 {
6074 struct constant *c;
6075 rtx insn = pool->pool_insn;
6076 int i;
6077
6078 /* Switch to rodata section. */
6079 if (TARGET_CPU_ZARCH)
6080 {
6081 insn = emit_insn_after (gen_pool_section_start (), insn);
6082 INSN_ADDRESSES_NEW (insn, -1);
6083 }
6084
6085 /* Ensure minimum pool alignment. */
6086 if (TARGET_CPU_ZARCH)
6087 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6088 else
6089 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6090 INSN_ADDRESSES_NEW (insn, -1);
6091
6092 /* Emit pool base label. */
6093 if (!remote_label)
6094 {
6095 insn = emit_label_after (pool->label, insn);
6096 INSN_ADDRESSES_NEW (insn, -1);
6097 }
6098
6099 /* Dump constants in descending alignment requirement order,
6100 ensuring proper alignment for every constant. */
6101 for (i = 0; i < NR_C_MODES; i++)
6102 for (c = pool->constants[i]; c; c = c->next)
6103 {
6104 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6105 rtx value = copy_rtx (c->value);
6106 if (GET_CODE (value) == CONST
6107 && GET_CODE (XEXP (value, 0)) == UNSPEC
6108 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6109 && XVECLEN (XEXP (value, 0), 0) == 1)
6110 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6111
6112 insn = emit_label_after (c->label, insn);
6113 INSN_ADDRESSES_NEW (insn, -1);
6114
6115 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6116 gen_rtvec (1, value),
6117 UNSPECV_POOL_ENTRY);
6118 insn = emit_insn_after (value, insn);
6119 INSN_ADDRESSES_NEW (insn, -1);
6120 }
6121
6122 /* Ensure minimum alignment for instructions. */
6123 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6124 INSN_ADDRESSES_NEW (insn, -1);
6125
6126 /* Output in-pool execute template insns. */
6127 for (c = pool->execute; c; c = c->next)
6128 {
6129 insn = emit_label_after (c->label, insn);
6130 INSN_ADDRESSES_NEW (insn, -1);
6131
6132 insn = emit_insn_after (s390_execute_target (c->value), insn);
6133 INSN_ADDRESSES_NEW (insn, -1);
6134 }
6135
6136 /* Switch back to previous section. */
6137 if (TARGET_CPU_ZARCH)
6138 {
6139 insn = emit_insn_after (gen_pool_section_end (), insn);
6140 INSN_ADDRESSES_NEW (insn, -1);
6141 }
6142
6143 insn = emit_barrier_after (insn);
6144 INSN_ADDRESSES_NEW (insn, -1);
6145
6146 /* Remove placeholder insn. */
6147 remove_insn (pool->pool_insn);
6148 }
6149
6150 /* Free all memory used by POOL. */
6151
6152 static void
6153 s390_free_pool (struct constant_pool *pool)
6154 {
6155 struct constant *c, *next;
6156 int i;
6157
6158 for (i = 0; i < NR_C_MODES; i++)
6159 for (c = pool->constants[i]; c; c = next)
6160 {
6161 next = c->next;
6162 free (c);
6163 }
6164
6165 for (c = pool->execute; c; c = next)
6166 {
6167 next = c->next;
6168 free (c);
6169 }
6170
6171 BITMAP_FREE (pool->insns);
6172 free (pool);
6173 }
6174
6175
6176 /* Collect main literal pool. Return NULL on overflow. */
6177
6178 static struct constant_pool *
6179 s390_mainpool_start (void)
6180 {
6181 struct constant_pool *pool;
6182 rtx insn;
6183
6184 pool = s390_alloc_pool ();
6185
6186 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6187 {
6188 if (GET_CODE (insn) == INSN
6189 && GET_CODE (PATTERN (insn)) == SET
6190 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6191 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6192 {
6193 gcc_assert (!pool->pool_insn);
6194 pool->pool_insn = insn;
6195 }
6196
6197 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6198 {
6199 s390_add_execute (pool, insn);
6200 }
6201 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6202 {
6203 rtx pool_ref = NULL_RTX;
6204 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6205 if (pool_ref)
6206 {
6207 rtx constant = get_pool_constant (pool_ref);
6208 enum machine_mode mode = get_pool_mode (pool_ref);
6209 s390_add_constant (pool, constant, mode);
6210 }
6211 }
6212
6213 /* If hot/cold partitioning is enabled we have to make sure that
6214 the literal pool is emitted in the same section where the
6215 initialization of the literal pool base pointer takes place.
6216 emit_pool_after is only used in the non-overflow case on non
6217 Z cpus where we can emit the literal pool at the end of the
6218 function body within the text section. */
6219 if (NOTE_P (insn)
6220 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6221 && !pool->emit_pool_after)
6222 pool->emit_pool_after = PREV_INSN (insn);
6223 }
6224
6225 gcc_assert (pool->pool_insn || pool->size == 0);
6226
6227 if (pool->size >= 4096)
6228 {
6229 /* We're going to chunkify the pool, so remove the main
6230 pool placeholder insn. */
6231 remove_insn (pool->pool_insn);
6232
6233 s390_free_pool (pool);
6234 pool = NULL;
6235 }
6236
6237 /* If the functions ends with the section where the literal pool
6238 should be emitted set the marker to its end. */
6239 if (pool && !pool->emit_pool_after)
6240 pool->emit_pool_after = get_last_insn ();
6241
6242 return pool;
6243 }
6244
6245 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6246 Modify the current function to output the pool constants as well as
6247 the pool register setup instruction. */
6248
6249 static void
6250 s390_mainpool_finish (struct constant_pool *pool)
6251 {
6252 rtx base_reg = cfun->machine->base_reg;
6253 rtx insn;
6254
6255 /* If the pool is empty, we're done. */
6256 if (pool->size == 0)
6257 {
6258 /* We don't actually need a base register after all. */
6259 cfun->machine->base_reg = NULL_RTX;
6260
6261 if (pool->pool_insn)
6262 remove_insn (pool->pool_insn);
6263 s390_free_pool (pool);
6264 return;
6265 }
6266
6267 /* We need correct insn addresses. */
6268 shorten_branches (get_insns ());
6269
6270 /* On zSeries, we use a LARL to load the pool register. The pool is
6271 located in the .rodata section, so we emit it after the function. */
6272 if (TARGET_CPU_ZARCH)
6273 {
6274 insn = gen_main_base_64 (base_reg, pool->label);
6275 insn = emit_insn_after (insn, pool->pool_insn);
6276 INSN_ADDRESSES_NEW (insn, -1);
6277 remove_insn (pool->pool_insn);
6278
6279 insn = get_last_insn ();
6280 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6281 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6282
6283 s390_dump_pool (pool, 0);
6284 }
6285
6286 /* On S/390, if the total size of the function's code plus literal pool
6287 does not exceed 4096 bytes, we use BASR to set up a function base
6288 pointer, and emit the literal pool at the end of the function. */
6289 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6290 + pool->size + 8 /* alignment slop */ < 4096)
6291 {
6292 insn = gen_main_base_31_small (base_reg, pool->label);
6293 insn = emit_insn_after (insn, pool->pool_insn);
6294 INSN_ADDRESSES_NEW (insn, -1);
6295 remove_insn (pool->pool_insn);
6296
6297 insn = emit_label_after (pool->label, insn);
6298 INSN_ADDRESSES_NEW (insn, -1);
6299
6300 /* emit_pool_after will be set by s390_mainpool_start to the
6301 last insn of the section where the literal pool should be
6302 emitted. */
6303 insn = pool->emit_pool_after;
6304
6305 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6306 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6307
6308 s390_dump_pool (pool, 1);
6309 }
6310
6311 /* Otherwise, we emit an inline literal pool and use BASR to branch
6312 over it, setting up the pool register at the same time. */
6313 else
6314 {
6315 rtx pool_end = gen_label_rtx ();
6316
6317 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6318 insn = emit_insn_after (insn, pool->pool_insn);
6319 INSN_ADDRESSES_NEW (insn, -1);
6320 remove_insn (pool->pool_insn);
6321
6322 insn = emit_label_after (pool->label, insn);
6323 INSN_ADDRESSES_NEW (insn, -1);
6324
6325 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6326 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6327
6328 insn = emit_label_after (pool_end, pool->pool_insn);
6329 INSN_ADDRESSES_NEW (insn, -1);
6330
6331 s390_dump_pool (pool, 1);
6332 }
6333
6334
6335 /* Replace all literal pool references. */
6336
6337 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6338 {
6339 if (INSN_P (insn))
6340 replace_ltrel_base (&PATTERN (insn));
6341
6342 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6343 {
6344 rtx addr, pool_ref = NULL_RTX;
6345 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6346 if (pool_ref)
6347 {
6348 if (s390_execute_label (insn))
6349 addr = s390_find_execute (pool, insn);
6350 else
6351 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6352 get_pool_mode (pool_ref));
6353
6354 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6355 INSN_CODE (insn) = -1;
6356 }
6357 }
6358 }
6359
6360
6361 /* Free the pool. */
6362 s390_free_pool (pool);
6363 }
6364
6365 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6366 We have decided we cannot use this pool, so revert all changes
6367 to the current function that were done by s390_mainpool_start. */
6368 static void
6369 s390_mainpool_cancel (struct constant_pool *pool)
6370 {
6371 /* We didn't actually change the instruction stream, so simply
6372 free the pool memory. */
6373 s390_free_pool (pool);
6374 }
6375
6376
6377 /* Chunkify the literal pool. */
6378
6379 #define S390_POOL_CHUNK_MIN 0xc00
6380 #define S390_POOL_CHUNK_MAX 0xe00
6381
6382 static struct constant_pool *
6383 s390_chunkify_start (void)
6384 {
6385 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6386 int extra_size = 0;
6387 bitmap far_labels;
6388 rtx pending_ltrel = NULL_RTX;
6389 rtx insn;
6390
6391 rtx (*gen_reload_base) (rtx, rtx) =
6392 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6393
6394
6395 /* We need correct insn addresses. */
6396
6397 shorten_branches (get_insns ());
6398
6399 /* Scan all insns and move literals to pool chunks. */
6400
6401 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6402 {
6403 bool section_switch_p = false;
6404
6405 /* Check for pending LTREL_BASE. */
6406 if (INSN_P (insn))
6407 {
6408 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6409 if (ltrel_base)
6410 {
6411 gcc_assert (ltrel_base == pending_ltrel);
6412 pending_ltrel = NULL_RTX;
6413 }
6414 }
6415
6416 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6417 {
6418 if (!curr_pool)
6419 curr_pool = s390_start_pool (&pool_list, insn);
6420
6421 s390_add_execute (curr_pool, insn);
6422 s390_add_pool_insn (curr_pool, insn);
6423 }
6424 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6425 {
6426 rtx pool_ref = NULL_RTX;
6427 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6428 if (pool_ref)
6429 {
6430 rtx constant = get_pool_constant (pool_ref);
6431 enum machine_mode mode = get_pool_mode (pool_ref);
6432
6433 if (!curr_pool)
6434 curr_pool = s390_start_pool (&pool_list, insn);
6435
6436 s390_add_constant (curr_pool, constant, mode);
6437 s390_add_pool_insn (curr_pool, insn);
6438
6439 /* Don't split the pool chunk between a LTREL_OFFSET load
6440 and the corresponding LTREL_BASE. */
6441 if (GET_CODE (constant) == CONST
6442 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6443 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6444 {
6445 gcc_assert (!pending_ltrel);
6446 pending_ltrel = pool_ref;
6447 }
6448 }
6449 }
6450
6451 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6452 {
6453 if (curr_pool)
6454 s390_add_pool_insn (curr_pool, insn);
6455 /* An LTREL_BASE must follow within the same basic block. */
6456 gcc_assert (!pending_ltrel);
6457 }
6458
6459 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6460 section_switch_p = true;
6461
6462 if (!curr_pool
6463 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6464 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6465 continue;
6466
6467 if (TARGET_CPU_ZARCH)
6468 {
6469 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6470 continue;
6471
6472 s390_end_pool (curr_pool, NULL_RTX);
6473 curr_pool = NULL;
6474 }
6475 else
6476 {
6477 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6478 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6479 + extra_size;
6480
6481 /* We will later have to insert base register reload insns.
6482 Those will have an effect on code size, which we need to
6483 consider here. This calculation makes rather pessimistic
6484 worst-case assumptions. */
6485 if (GET_CODE (insn) == CODE_LABEL)
6486 extra_size += 6;
6487
6488 if (chunk_size < S390_POOL_CHUNK_MIN
6489 && curr_pool->size < S390_POOL_CHUNK_MIN
6490 && !section_switch_p)
6491 continue;
6492
6493 /* Pool chunks can only be inserted after BARRIERs ... */
6494 if (GET_CODE (insn) == BARRIER)
6495 {
6496 s390_end_pool (curr_pool, insn);
6497 curr_pool = NULL;
6498 extra_size = 0;
6499 }
6500
6501 /* ... so if we don't find one in time, create one. */
6502 else if (chunk_size > S390_POOL_CHUNK_MAX
6503 || curr_pool->size > S390_POOL_CHUNK_MAX
6504 || section_switch_p)
6505 {
6506 rtx label, jump, barrier;
6507
6508 if (!section_switch_p)
6509 {
6510 /* We can insert the barrier only after a 'real' insn. */
6511 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6512 continue;
6513 if (get_attr_length (insn) == 0)
6514 continue;
6515 /* Don't separate LTREL_BASE from the corresponding
6516 LTREL_OFFSET load. */
6517 if (pending_ltrel)
6518 continue;
6519 }
6520 else
6521 {
6522 gcc_assert (!pending_ltrel);
6523
6524 /* The old pool has to end before the section switch
6525 note in order to make it part of the current
6526 section. */
6527 insn = PREV_INSN (insn);
6528 }
6529
6530 label = gen_label_rtx ();
6531 jump = emit_jump_insn_after (gen_jump (label), insn);
6532 barrier = emit_barrier_after (jump);
6533 insn = emit_label_after (label, barrier);
6534 JUMP_LABEL (jump) = label;
6535 LABEL_NUSES (label) = 1;
6536
6537 INSN_ADDRESSES_NEW (jump, -1);
6538 INSN_ADDRESSES_NEW (barrier, -1);
6539 INSN_ADDRESSES_NEW (insn, -1);
6540
6541 s390_end_pool (curr_pool, barrier);
6542 curr_pool = NULL;
6543 extra_size = 0;
6544 }
6545 }
6546 }
6547
6548 if (curr_pool)
6549 s390_end_pool (curr_pool, NULL_RTX);
6550 gcc_assert (!pending_ltrel);
6551
6552 /* Find all labels that are branched into
6553 from an insn belonging to a different chunk. */
6554
6555 far_labels = BITMAP_ALLOC (NULL);
6556
6557 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6558 {
6559 /* Labels marked with LABEL_PRESERVE_P can be target
6560 of non-local jumps, so we have to mark them.
6561 The same holds for named labels.
6562
6563 Don't do that, however, if it is the label before
6564 a jump table. */
6565
6566 if (GET_CODE (insn) == CODE_LABEL
6567 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6568 {
6569 rtx vec_insn = next_real_insn (insn);
6570 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6571 PATTERN (vec_insn) : NULL_RTX;
6572 if (!vec_pat
6573 || !(GET_CODE (vec_pat) == ADDR_VEC
6574 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6575 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6576 }
6577
6578 /* If we have a direct jump (conditional or unconditional)
6579 or a casesi jump, check all potential targets. */
6580 else if (GET_CODE (insn) == JUMP_INSN)
6581 {
6582 rtx pat = PATTERN (insn);
6583 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6584 pat = XVECEXP (pat, 0, 0);
6585
6586 if (GET_CODE (pat) == SET)
6587 {
6588 rtx label = JUMP_LABEL (insn);
6589 if (label)
6590 {
6591 if (s390_find_pool (pool_list, label)
6592 != s390_find_pool (pool_list, insn))
6593 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6594 }
6595 }
6596 else if (GET_CODE (pat) == PARALLEL
6597 && XVECLEN (pat, 0) == 2
6598 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6599 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6600 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6601 {
6602 /* Find the jump table used by this casesi jump. */
6603 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6604 rtx vec_insn = next_real_insn (vec_label);
6605 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6606 PATTERN (vec_insn) : NULL_RTX;
6607 if (vec_pat
6608 && (GET_CODE (vec_pat) == ADDR_VEC
6609 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6610 {
6611 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6612
6613 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6614 {
6615 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6616
6617 if (s390_find_pool (pool_list, label)
6618 != s390_find_pool (pool_list, insn))
6619 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6620 }
6621 }
6622 }
6623 }
6624 }
6625
6626 /* Insert base register reload insns before every pool. */
6627
6628 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6629 {
6630 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6631 curr_pool->label);
6632 rtx insn = curr_pool->first_insn;
6633 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6634 }
6635
6636 /* Insert base register reload insns at every far label. */
6637
6638 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6639 if (GET_CODE (insn) == CODE_LABEL
6640 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6641 {
6642 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6643 if (pool)
6644 {
6645 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6646 pool->label);
6647 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6648 }
6649 }
6650
6651
6652 BITMAP_FREE (far_labels);
6653
6654
6655 /* Recompute insn addresses. */
6656
6657 init_insn_lengths ();
6658 shorten_branches (get_insns ());
6659
6660 return pool_list;
6661 }
6662
6663 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6664 After we have decided to use this list, finish implementing
6665 all changes to the current function as required. */
6666
6667 static void
6668 s390_chunkify_finish (struct constant_pool *pool_list)
6669 {
6670 struct constant_pool *curr_pool = NULL;
6671 rtx insn;
6672
6673
6674 /* Replace all literal pool references. */
6675
6676 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6677 {
6678 if (INSN_P (insn))
6679 replace_ltrel_base (&PATTERN (insn));
6680
6681 curr_pool = s390_find_pool (pool_list, insn);
6682 if (!curr_pool)
6683 continue;
6684
6685 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6686 {
6687 rtx addr, pool_ref = NULL_RTX;
6688 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6689 if (pool_ref)
6690 {
6691 if (s390_execute_label (insn))
6692 addr = s390_find_execute (curr_pool, insn);
6693 else
6694 addr = s390_find_constant (curr_pool,
6695 get_pool_constant (pool_ref),
6696 get_pool_mode (pool_ref));
6697
6698 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6699 INSN_CODE (insn) = -1;
6700 }
6701 }
6702 }
6703
6704 /* Dump out all literal pools. */
6705
6706 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6707 s390_dump_pool (curr_pool, 0);
6708
6709 /* Free pool list. */
6710
6711 while (pool_list)
6712 {
6713 struct constant_pool *next = pool_list->next;
6714 s390_free_pool (pool_list);
6715 pool_list = next;
6716 }
6717 }
6718
6719 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6720 We have decided we cannot use this list, so revert all changes
6721 to the current function that were done by s390_chunkify_start. */
6722
6723 static void
6724 s390_chunkify_cancel (struct constant_pool *pool_list)
6725 {
6726 struct constant_pool *curr_pool = NULL;
6727 rtx insn;
6728
6729 /* Remove all pool placeholder insns. */
6730
6731 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6732 {
6733 /* Did we insert an extra barrier? Remove it. */
6734 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6735 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6736 rtx label = NEXT_INSN (curr_pool->pool_insn);
6737
6738 if (jump && GET_CODE (jump) == JUMP_INSN
6739 && barrier && GET_CODE (barrier) == BARRIER
6740 && label && GET_CODE (label) == CODE_LABEL
6741 && GET_CODE (PATTERN (jump)) == SET
6742 && SET_DEST (PATTERN (jump)) == pc_rtx
6743 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6744 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6745 {
6746 remove_insn (jump);
6747 remove_insn (barrier);
6748 remove_insn (label);
6749 }
6750
6751 remove_insn (curr_pool->pool_insn);
6752 }
6753
6754 /* Remove all base register reload insns. */
6755
6756 for (insn = get_insns (); insn; )
6757 {
6758 rtx next_insn = NEXT_INSN (insn);
6759
6760 if (GET_CODE (insn) == INSN
6761 && GET_CODE (PATTERN (insn)) == SET
6762 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6763 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6764 remove_insn (insn);
6765
6766 insn = next_insn;
6767 }
6768
6769 /* Free pool list. */
6770
6771 while (pool_list)
6772 {
6773 struct constant_pool *next = pool_list->next;
6774 s390_free_pool (pool_list);
6775 pool_list = next;
6776 }
6777 }
6778
6779 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6780
6781 void
6782 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6783 {
6784 REAL_VALUE_TYPE r;
6785
6786 switch (GET_MODE_CLASS (mode))
6787 {
6788 case MODE_FLOAT:
6789 case MODE_DECIMAL_FLOAT:
6790 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6791
6792 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6793 assemble_real (r, mode, align);
6794 break;
6795
6796 case MODE_INT:
6797 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6798 mark_symbol_refs_as_used (exp);
6799 break;
6800
6801 default:
6802 gcc_unreachable ();
6803 }
6804 }
6805
6806
6807 /* Return an RTL expression representing the value of the return address
6808 for the frame COUNT steps up from the current frame. FRAME is the
6809 frame pointer of that frame. */
6810
6811 rtx
6812 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6813 {
6814 int offset;
6815 rtx addr;
6816
6817 /* Without backchain, we fail for all but the current frame. */
6818
6819 if (!TARGET_BACKCHAIN && count > 0)
6820 return NULL_RTX;
6821
6822 /* For the current frame, we need to make sure the initial
6823 value of RETURN_REGNUM is actually saved. */
6824
6825 if (count == 0)
6826 {
6827 /* On non-z architectures branch splitting could overwrite r14. */
6828 if (TARGET_CPU_ZARCH)
6829 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6830 else
6831 {
6832 cfun_frame_layout.save_return_addr_p = true;
6833 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6834 }
6835 }
6836
6837 if (TARGET_PACKED_STACK)
6838 offset = -2 * UNITS_PER_LONG;
6839 else
6840 offset = RETURN_REGNUM * UNITS_PER_LONG;
6841
6842 addr = plus_constant (frame, offset);
6843 addr = memory_address (Pmode, addr);
6844 return gen_rtx_MEM (Pmode, addr);
6845 }
6846
6847 /* Return an RTL expression representing the back chain stored in
6848 the current stack frame. */
6849
6850 rtx
6851 s390_back_chain_rtx (void)
6852 {
6853 rtx chain;
6854
6855 gcc_assert (TARGET_BACKCHAIN);
6856
6857 if (TARGET_PACKED_STACK)
6858 chain = plus_constant (stack_pointer_rtx,
6859 STACK_POINTER_OFFSET - UNITS_PER_LONG);
6860 else
6861 chain = stack_pointer_rtx;
6862
6863 chain = gen_rtx_MEM (Pmode, chain);
6864 return chain;
6865 }
6866
6867 /* Find first call clobbered register unused in a function.
6868 This could be used as base register in a leaf function
6869 or for holding the return address before epilogue. */
6870
6871 static int
6872 find_unused_clobbered_reg (void)
6873 {
6874 int i;
6875 for (i = 0; i < 6; i++)
6876 if (!df_regs_ever_live_p (i))
6877 return i;
6878 return 0;
6879 }
6880
6881
6882 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6883 clobbered hard regs in SETREG. */
6884
6885 static void
6886 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6887 {
6888 int *regs_ever_clobbered = (int *)data;
6889 unsigned int i, regno;
6890 enum machine_mode mode = GET_MODE (setreg);
6891
6892 if (GET_CODE (setreg) == SUBREG)
6893 {
6894 rtx inner = SUBREG_REG (setreg);
6895 if (!GENERAL_REG_P (inner))
6896 return;
6897 regno = subreg_regno (setreg);
6898 }
6899 else if (GENERAL_REG_P (setreg))
6900 regno = REGNO (setreg);
6901 else
6902 return;
6903
6904 for (i = regno;
6905 i < regno + HARD_REGNO_NREGS (regno, mode);
6906 i++)
6907 regs_ever_clobbered[i] = 1;
6908 }
6909
6910 /* Walks through all basic blocks of the current function looking
6911 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6912 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6913 each of those regs. */
6914
6915 static void
6916 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6917 {
6918 basic_block cur_bb;
6919 rtx cur_insn;
6920 unsigned int i;
6921
6922 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6923
6924 /* For non-leaf functions we have to consider all call clobbered regs to be
6925 clobbered. */
6926 if (!current_function_is_leaf)
6927 {
6928 for (i = 0; i < 16; i++)
6929 regs_ever_clobbered[i] = call_really_used_regs[i];
6930 }
6931
6932 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6933 this work is done by liveness analysis (mark_regs_live_at_end).
6934 Special care is needed for functions containing landing pads. Landing pads
6935 may use the eh registers, but the code which sets these registers is not
6936 contained in that function. Hence s390_regs_ever_clobbered is not able to
6937 deal with this automatically. */
6938 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6939 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6940 if (crtl->calls_eh_return
6941 || (cfun->machine->has_landing_pad_p
6942 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6943 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6944
6945 /* For nonlocal gotos all call-saved registers have to be saved.
6946 This flag is also set for the unwinding code in libgcc.
6947 See expand_builtin_unwind_init. For regs_ever_live this is done by
6948 reload. */
6949 if (cfun->has_nonlocal_label)
6950 for (i = 0; i < 16; i++)
6951 if (!call_really_used_regs[i])
6952 regs_ever_clobbered[i] = 1;
6953
6954 FOR_EACH_BB (cur_bb)
6955 {
6956 FOR_BB_INSNS (cur_bb, cur_insn)
6957 {
6958 if (INSN_P (cur_insn))
6959 note_stores (PATTERN (cur_insn),
6960 s390_reg_clobbered_rtx,
6961 regs_ever_clobbered);
6962 }
6963 }
6964 }
6965
6966 /* Determine the frame area which actually has to be accessed
6967 in the function epilogue. The values are stored at the
6968 given pointers AREA_BOTTOM (address of the lowest used stack
6969 address) and AREA_TOP (address of the first item which does
6970 not belong to the stack frame). */
6971
6972 static void
6973 s390_frame_area (int *area_bottom, int *area_top)
6974 {
6975 int b, t;
6976 int i;
6977
6978 b = INT_MAX;
6979 t = INT_MIN;
6980
6981 if (cfun_frame_layout.first_restore_gpr != -1)
6982 {
6983 b = (cfun_frame_layout.gprs_offset
6984 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
6985 t = b + (cfun_frame_layout.last_restore_gpr
6986 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
6987 }
6988
6989 if (TARGET_64BIT && cfun_save_high_fprs_p)
6990 {
6991 b = MIN (b, cfun_frame_layout.f8_offset);
6992 t = MAX (t, (cfun_frame_layout.f8_offset
6993 + cfun_frame_layout.high_fprs * 8));
6994 }
6995
6996 if (!TARGET_64BIT)
6997 for (i = 2; i < 4; i++)
6998 if (cfun_fpr_bit_p (i))
6999 {
7000 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7001 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7002 }
7003
7004 *area_bottom = b;
7005 *area_top = t;
7006 }
7007
7008 /* Fill cfun->machine with info about register usage of current function.
7009 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7010
7011 static void
7012 s390_register_info (int clobbered_regs[])
7013 {
7014 int i, j;
7015
7016 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7017 cfun_frame_layout.fpr_bitmap = 0;
7018 cfun_frame_layout.high_fprs = 0;
7019 if (TARGET_64BIT)
7020 for (i = 24; i < 32; i++)
7021 if (df_regs_ever_live_p (i) && !global_regs[i])
7022 {
7023 cfun_set_fpr_bit (i - 16);
7024 cfun_frame_layout.high_fprs++;
7025 }
7026
7027 /* Find first and last gpr to be saved. We trust regs_ever_live
7028 data, except that we don't save and restore global registers.
7029
7030 Also, all registers with special meaning to the compiler need
7031 to be handled extra. */
7032
7033 s390_regs_ever_clobbered (clobbered_regs);
7034
7035 for (i = 0; i < 16; i++)
7036 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7037
7038 if (frame_pointer_needed)
7039 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7040
7041 if (flag_pic)
7042 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7043 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7044
7045 clobbered_regs[BASE_REGNUM]
7046 |= (cfun->machine->base_reg
7047 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7048
7049 clobbered_regs[RETURN_REGNUM]
7050 |= (!current_function_is_leaf
7051 || TARGET_TPF_PROFILING
7052 || cfun->machine->split_branches_pending_p
7053 || cfun_frame_layout.save_return_addr_p
7054 || crtl->calls_eh_return
7055 || cfun->stdarg);
7056
7057 clobbered_regs[STACK_POINTER_REGNUM]
7058 |= (!current_function_is_leaf
7059 || TARGET_TPF_PROFILING
7060 || cfun_save_high_fprs_p
7061 || get_frame_size () > 0
7062 || cfun->calls_alloca
7063 || cfun->stdarg);
7064
7065 for (i = 6; i < 16; i++)
7066 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7067 break;
7068 for (j = 15; j > i; j--)
7069 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7070 break;
7071
7072 if (i == 16)
7073 {
7074 /* Nothing to save/restore. */
7075 cfun_frame_layout.first_save_gpr_slot = -1;
7076 cfun_frame_layout.last_save_gpr_slot = -1;
7077 cfun_frame_layout.first_save_gpr = -1;
7078 cfun_frame_layout.first_restore_gpr = -1;
7079 cfun_frame_layout.last_save_gpr = -1;
7080 cfun_frame_layout.last_restore_gpr = -1;
7081 }
7082 else
7083 {
7084 /* Save slots for gprs from i to j. */
7085 cfun_frame_layout.first_save_gpr_slot = i;
7086 cfun_frame_layout.last_save_gpr_slot = j;
7087
7088 for (i = cfun_frame_layout.first_save_gpr_slot;
7089 i < cfun_frame_layout.last_save_gpr_slot + 1;
7090 i++)
7091 if (clobbered_regs[i])
7092 break;
7093
7094 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7095 if (clobbered_regs[j])
7096 break;
7097
7098 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7099 {
7100 /* Nothing to save/restore. */
7101 cfun_frame_layout.first_save_gpr = -1;
7102 cfun_frame_layout.first_restore_gpr = -1;
7103 cfun_frame_layout.last_save_gpr = -1;
7104 cfun_frame_layout.last_restore_gpr = -1;
7105 }
7106 else
7107 {
7108 /* Save / Restore from gpr i to j. */
7109 cfun_frame_layout.first_save_gpr = i;
7110 cfun_frame_layout.first_restore_gpr = i;
7111 cfun_frame_layout.last_save_gpr = j;
7112 cfun_frame_layout.last_restore_gpr = j;
7113 }
7114 }
7115
7116 if (cfun->stdarg)
7117 {
7118 /* Varargs functions need to save gprs 2 to 6. */
7119 if (cfun->va_list_gpr_size
7120 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7121 {
7122 int min_gpr = crtl->args.info.gprs;
7123 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7124 if (max_gpr > GP_ARG_NUM_REG)
7125 max_gpr = GP_ARG_NUM_REG;
7126
7127 if (cfun_frame_layout.first_save_gpr == -1
7128 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7129 {
7130 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7131 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7132 }
7133
7134 if (cfun_frame_layout.last_save_gpr == -1
7135 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7136 {
7137 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7138 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7139 }
7140 }
7141
7142 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7143 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7144 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7145 {
7146 int min_fpr = crtl->args.info.fprs;
7147 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7148 if (max_fpr > FP_ARG_NUM_REG)
7149 max_fpr = FP_ARG_NUM_REG;
7150
7151 /* ??? This is currently required to ensure proper location
7152 of the fpr save slots within the va_list save area. */
7153 if (TARGET_PACKED_STACK)
7154 min_fpr = 0;
7155
7156 for (i = min_fpr; i < max_fpr; i++)
7157 cfun_set_fpr_bit (i);
7158 }
7159 }
7160
7161 if (!TARGET_64BIT)
7162 for (i = 2; i < 4; i++)
7163 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7164 cfun_set_fpr_bit (i);
7165 }
7166
7167 /* Fill cfun->machine with info about frame of current function. */
7168
7169 static void
7170 s390_frame_info (void)
7171 {
7172 int i;
7173
7174 cfun_frame_layout.frame_size = get_frame_size ();
7175 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7176 fatal_error ("total size of local variables exceeds architecture limit");
7177
7178 if (!TARGET_PACKED_STACK)
7179 {
7180 cfun_frame_layout.backchain_offset = 0;
7181 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7182 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7183 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7184 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7185 * UNITS_PER_LONG);
7186 }
7187 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7188 {
7189 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7190 - UNITS_PER_LONG);
7191 cfun_frame_layout.gprs_offset
7192 = (cfun_frame_layout.backchain_offset
7193 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7194 * UNITS_PER_LONG);
7195
7196 if (TARGET_64BIT)
7197 {
7198 cfun_frame_layout.f4_offset
7199 = (cfun_frame_layout.gprs_offset
7200 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7201
7202 cfun_frame_layout.f0_offset
7203 = (cfun_frame_layout.f4_offset
7204 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7205 }
7206 else
7207 {
7208 /* On 31 bit we have to care about alignment of the
7209 floating point regs to provide fastest access. */
7210 cfun_frame_layout.f0_offset
7211 = ((cfun_frame_layout.gprs_offset
7212 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7213 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7214
7215 cfun_frame_layout.f4_offset
7216 = (cfun_frame_layout.f0_offset
7217 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7218 }
7219 }
7220 else /* no backchain */
7221 {
7222 cfun_frame_layout.f4_offset
7223 = (STACK_POINTER_OFFSET
7224 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7225
7226 cfun_frame_layout.f0_offset
7227 = (cfun_frame_layout.f4_offset
7228 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7229
7230 cfun_frame_layout.gprs_offset
7231 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7232 }
7233
7234 if (current_function_is_leaf
7235 && !TARGET_TPF_PROFILING
7236 && cfun_frame_layout.frame_size == 0
7237 && !cfun_save_high_fprs_p
7238 && !cfun->calls_alloca
7239 && !cfun->stdarg)
7240 return;
7241
7242 if (!TARGET_PACKED_STACK)
7243 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7244 + crtl->outgoing_args_size
7245 + cfun_frame_layout.high_fprs * 8);
7246 else
7247 {
7248 if (TARGET_BACKCHAIN)
7249 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7250
7251 /* No alignment trouble here because f8-f15 are only saved under
7252 64 bit. */
7253 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7254 cfun_frame_layout.f4_offset),
7255 cfun_frame_layout.gprs_offset)
7256 - cfun_frame_layout.high_fprs * 8);
7257
7258 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7259
7260 for (i = 0; i < 8; i++)
7261 if (cfun_fpr_bit_p (i))
7262 cfun_frame_layout.frame_size += 8;
7263
7264 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7265
7266 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7267 the frame size to sustain 8 byte alignment of stack frames. */
7268 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7269 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7270 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7271
7272 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7273 }
7274 }
7275
7276 /* Generate frame layout. Fills in register and frame data for the current
7277 function in cfun->machine. This routine can be called multiple times;
7278 it will re-do the complete frame layout every time. */
7279
7280 static void
7281 s390_init_frame_layout (void)
7282 {
7283 HOST_WIDE_INT frame_size;
7284 int base_used;
7285 int clobbered_regs[16];
7286
7287 /* On S/390 machines, we may need to perform branch splitting, which
7288 will require both base and return address register. We have no
7289 choice but to assume we're going to need them until right at the
7290 end of the machine dependent reorg phase. */
7291 if (!TARGET_CPU_ZARCH)
7292 cfun->machine->split_branches_pending_p = true;
7293
7294 do
7295 {
7296 frame_size = cfun_frame_layout.frame_size;
7297
7298 /* Try to predict whether we'll need the base register. */
7299 base_used = cfun->machine->split_branches_pending_p
7300 || crtl->uses_const_pool
7301 || (!DISP_IN_RANGE (frame_size)
7302 && !CONST_OK_FOR_K (frame_size));
7303
7304 /* Decide which register to use as literal pool base. In small
7305 leaf functions, try to use an unused call-clobbered register
7306 as base register to avoid save/restore overhead. */
7307 if (!base_used)
7308 cfun->machine->base_reg = NULL_RTX;
7309 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7310 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7311 else
7312 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7313
7314 s390_register_info (clobbered_regs);
7315 s390_frame_info ();
7316 }
7317 while (frame_size != cfun_frame_layout.frame_size);
7318 }
7319
7320 /* Update frame layout. Recompute actual register save data based on
7321 current info and update regs_ever_live for the special registers.
7322 May be called multiple times, but may never cause *more* registers
7323 to be saved than s390_init_frame_layout allocated room for. */
7324
7325 static void
7326 s390_update_frame_layout (void)
7327 {
7328 int clobbered_regs[16];
7329
7330 s390_register_info (clobbered_regs);
7331
7332 df_set_regs_ever_live (BASE_REGNUM,
7333 clobbered_regs[BASE_REGNUM] ? true : false);
7334 df_set_regs_ever_live (RETURN_REGNUM,
7335 clobbered_regs[RETURN_REGNUM] ? true : false);
7336 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7337 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7338
7339 if (cfun->machine->base_reg)
7340 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7341 }
7342
7343 /* Return true if it is legal to put a value with MODE into REGNO. */
7344
7345 bool
7346 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7347 {
7348 switch (REGNO_REG_CLASS (regno))
7349 {
7350 case FP_REGS:
7351 if (REGNO_PAIR_OK (regno, mode))
7352 {
7353 if (mode == SImode || mode == DImode)
7354 return true;
7355
7356 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7357 return true;
7358 }
7359 break;
7360 case ADDR_REGS:
7361 if (FRAME_REGNO_P (regno) && mode == Pmode)
7362 return true;
7363
7364 /* fallthrough */
7365 case GENERAL_REGS:
7366 if (REGNO_PAIR_OK (regno, mode))
7367 {
7368 if (TARGET_ZARCH
7369 || (mode != TFmode && mode != TCmode && mode != TDmode))
7370 return true;
7371 }
7372 break;
7373 case CC_REGS:
7374 if (GET_MODE_CLASS (mode) == MODE_CC)
7375 return true;
7376 break;
7377 case ACCESS_REGS:
7378 if (REGNO_PAIR_OK (regno, mode))
7379 {
7380 if (mode == SImode || mode == Pmode)
7381 return true;
7382 }
7383 break;
7384 default:
7385 return false;
7386 }
7387
7388 return false;
7389 }
7390
7391 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7392
7393 bool
7394 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7395 {
7396 /* Once we've decided upon a register to use as base register, it must
7397 no longer be used for any other purpose. */
7398 if (cfun->machine->base_reg)
7399 if (REGNO (cfun->machine->base_reg) == old_reg
7400 || REGNO (cfun->machine->base_reg) == new_reg)
7401 return false;
7402
7403 return true;
7404 }
7405
7406 /* Maximum number of registers to represent a value of mode MODE
7407 in a register of class RCLASS. */
7408
7409 bool
7410 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7411 {
7412 switch (rclass)
7413 {
7414 case FP_REGS:
7415 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7416 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7417 else
7418 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7419 case ACCESS_REGS:
7420 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7421 default:
7422 break;
7423 }
7424 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7425 }
7426
7427 /* Return true if register FROM can be eliminated via register TO. */
7428
7429 static bool
7430 s390_can_eliminate (const int from, const int to)
7431 {
7432 /* On zSeries machines, we have not marked the base register as fixed.
7433 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7434 If a function requires the base register, we say here that this
7435 elimination cannot be performed. This will cause reload to free
7436 up the base register (as if it were fixed). On the other hand,
7437 if the current function does *not* require the base register, we
7438 say here the elimination succeeds, which in turn allows reload
7439 to allocate the base register for any other purpose. */
7440 if (from == BASE_REGNUM && to == BASE_REGNUM)
7441 {
7442 if (TARGET_CPU_ZARCH)
7443 {
7444 s390_init_frame_layout ();
7445 return cfun->machine->base_reg == NULL_RTX;
7446 }
7447
7448 return false;
7449 }
7450
7451 /* Everything else must point into the stack frame. */
7452 gcc_assert (to == STACK_POINTER_REGNUM
7453 || to == HARD_FRAME_POINTER_REGNUM);
7454
7455 gcc_assert (from == FRAME_POINTER_REGNUM
7456 || from == ARG_POINTER_REGNUM
7457 || from == RETURN_ADDRESS_POINTER_REGNUM);
7458
7459 /* Make sure we actually saved the return address. */
7460 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7461 if (!crtl->calls_eh_return
7462 && !cfun->stdarg
7463 && !cfun_frame_layout.save_return_addr_p)
7464 return false;
7465
7466 return true;
7467 }
7468
7469 /* Return offset between register FROM and TO initially after prolog. */
7470
7471 HOST_WIDE_INT
7472 s390_initial_elimination_offset (int from, int to)
7473 {
7474 HOST_WIDE_INT offset;
7475 int index;
7476
7477 /* ??? Why are we called for non-eliminable pairs? */
7478 if (!s390_can_eliminate (from, to))
7479 return 0;
7480
7481 switch (from)
7482 {
7483 case FRAME_POINTER_REGNUM:
7484 offset = (get_frame_size()
7485 + STACK_POINTER_OFFSET
7486 + crtl->outgoing_args_size);
7487 break;
7488
7489 case ARG_POINTER_REGNUM:
7490 s390_init_frame_layout ();
7491 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7492 break;
7493
7494 case RETURN_ADDRESS_POINTER_REGNUM:
7495 s390_init_frame_layout ();
7496 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7497 gcc_assert (index >= 0);
7498 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7499 offset += index * UNITS_PER_LONG;
7500 break;
7501
7502 case BASE_REGNUM:
7503 offset = 0;
7504 break;
7505
7506 default:
7507 gcc_unreachable ();
7508 }
7509
7510 return offset;
7511 }
7512
7513 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7514 to register BASE. Return generated insn. */
7515
7516 static rtx
7517 save_fpr (rtx base, int offset, int regnum)
7518 {
7519 rtx addr;
7520 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7521
7522 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7523 set_mem_alias_set (addr, get_varargs_alias_set ());
7524 else
7525 set_mem_alias_set (addr, get_frame_alias_set ());
7526
7527 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7528 }
7529
7530 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7531 to register BASE. Return generated insn. */
7532
7533 static rtx
7534 restore_fpr (rtx base, int offset, int regnum)
7535 {
7536 rtx addr;
7537 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7538 set_mem_alias_set (addr, get_frame_alias_set ());
7539
7540 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7541 }
7542
7543 /* Return true if REGNO is a global register, but not one
7544 of the special ones that need to be saved/restored in anyway. */
7545
7546 static inline bool
7547 global_not_special_regno_p (int regno)
7548 {
7549 return (global_regs[regno]
7550 /* These registers are special and need to be
7551 restored in any case. */
7552 && !(regno == STACK_POINTER_REGNUM
7553 || regno == RETURN_REGNUM
7554 || regno == BASE_REGNUM
7555 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7556 }
7557
7558 /* Generate insn to save registers FIRST to LAST into
7559 the register save area located at offset OFFSET
7560 relative to register BASE. */
7561
7562 static rtx
7563 save_gprs (rtx base, int offset, int first, int last)
7564 {
7565 rtx addr, insn, note;
7566 int i;
7567
7568 addr = plus_constant (base, offset);
7569 addr = gen_rtx_MEM (Pmode, addr);
7570
7571 set_mem_alias_set (addr, get_frame_alias_set ());
7572
7573 /* Special-case single register. */
7574 if (first == last)
7575 {
7576 if (TARGET_64BIT)
7577 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7578 else
7579 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7580
7581 if (!global_not_special_regno_p (first))
7582 RTX_FRAME_RELATED_P (insn) = 1;
7583 return insn;
7584 }
7585
7586
7587 insn = gen_store_multiple (addr,
7588 gen_rtx_REG (Pmode, first),
7589 GEN_INT (last - first + 1));
7590
7591 if (first <= 6 && cfun->stdarg)
7592 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7593 {
7594 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7595
7596 if (first + i <= 6)
7597 set_mem_alias_set (mem, get_varargs_alias_set ());
7598 }
7599
7600 /* We need to set the FRAME_RELATED flag on all SETs
7601 inside the store-multiple pattern.
7602
7603 However, we must not emit DWARF records for registers 2..5
7604 if they are stored for use by variable arguments ...
7605
7606 ??? Unfortunately, it is not enough to simply not the
7607 FRAME_RELATED flags for those SETs, because the first SET
7608 of the PARALLEL is always treated as if it had the flag
7609 set, even if it does not. Therefore we emit a new pattern
7610 without those registers as REG_FRAME_RELATED_EXPR note. */
7611
7612 if (first >= 6 && !global_not_special_regno_p (first))
7613 {
7614 rtx pat = PATTERN (insn);
7615
7616 for (i = 0; i < XVECLEN (pat, 0); i++)
7617 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7618 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7619 0, i)))))
7620 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7621
7622 RTX_FRAME_RELATED_P (insn) = 1;
7623 }
7624 else if (last >= 6)
7625 {
7626 int start;
7627
7628 for (start = first >= 6 ? first : 6; start <= last; start++)
7629 if (!global_not_special_regno_p (start))
7630 break;
7631
7632 if (start > last)
7633 return insn;
7634
7635 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7636 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7637 gen_rtx_REG (Pmode, start),
7638 GEN_INT (last - start + 1));
7639 note = PATTERN (note);
7640
7641 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7642
7643 for (i = 0; i < XVECLEN (note, 0); i++)
7644 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7645 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7646 0, i)))))
7647 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7648
7649 RTX_FRAME_RELATED_P (insn) = 1;
7650 }
7651
7652 return insn;
7653 }
7654
7655 /* Generate insn to restore registers FIRST to LAST from
7656 the register save area located at offset OFFSET
7657 relative to register BASE. */
7658
7659 static rtx
7660 restore_gprs (rtx base, int offset, int first, int last)
7661 {
7662 rtx addr, insn;
7663
7664 addr = plus_constant (base, offset);
7665 addr = gen_rtx_MEM (Pmode, addr);
7666 set_mem_alias_set (addr, get_frame_alias_set ());
7667
7668 /* Special-case single register. */
7669 if (first == last)
7670 {
7671 if (TARGET_64BIT)
7672 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7673 else
7674 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7675
7676 return insn;
7677 }
7678
7679 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7680 addr,
7681 GEN_INT (last - first + 1));
7682 return insn;
7683 }
7684
7685 /* Return insn sequence to load the GOT register. */
7686
7687 static GTY(()) rtx got_symbol;
7688 rtx
7689 s390_load_got (void)
7690 {
7691 rtx insns;
7692
7693 if (!got_symbol)
7694 {
7695 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7696 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7697 }
7698
7699 start_sequence ();
7700
7701 if (TARGET_CPU_ZARCH)
7702 {
7703 emit_move_insn (pic_offset_table_rtx, got_symbol);
7704 }
7705 else
7706 {
7707 rtx offset;
7708
7709 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7710 UNSPEC_LTREL_OFFSET);
7711 offset = gen_rtx_CONST (Pmode, offset);
7712 offset = force_const_mem (Pmode, offset);
7713
7714 emit_move_insn (pic_offset_table_rtx, offset);
7715
7716 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7717 UNSPEC_LTREL_BASE);
7718 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7719
7720 emit_move_insn (pic_offset_table_rtx, offset);
7721 }
7722
7723 insns = get_insns ();
7724 end_sequence ();
7725 return insns;
7726 }
7727
7728 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7729 and the change to the stack pointer. */
7730
7731 static void
7732 s390_emit_stack_tie (void)
7733 {
7734 rtx mem = gen_frame_mem (BLKmode,
7735 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7736
7737 emit_insn (gen_stack_tie (mem));
7738 }
7739
7740 /* Expand the prologue into a bunch of separate insns. */
7741
7742 void
7743 s390_emit_prologue (void)
7744 {
7745 rtx insn, addr;
7746 rtx temp_reg;
7747 int i;
7748 int offset;
7749 int next_fpr = 0;
7750
7751 /* Complete frame layout. */
7752
7753 s390_update_frame_layout ();
7754
7755 /* Annotate all constant pool references to let the scheduler know
7756 they implicitly use the base register. */
7757
7758 push_topmost_sequence ();
7759
7760 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7761 if (INSN_P (insn))
7762 {
7763 annotate_constant_pool_refs (&PATTERN (insn));
7764 df_insn_rescan (insn);
7765 }
7766
7767 pop_topmost_sequence ();
7768
7769 /* Choose best register to use for temp use within prologue.
7770 See below for why TPF must use the register 1. */
7771
7772 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7773 && !current_function_is_leaf
7774 && !TARGET_TPF_PROFILING)
7775 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7776 else
7777 temp_reg = gen_rtx_REG (Pmode, 1);
7778
7779 /* Save call saved gprs. */
7780 if (cfun_frame_layout.first_save_gpr != -1)
7781 {
7782 insn = save_gprs (stack_pointer_rtx,
7783 cfun_frame_layout.gprs_offset +
7784 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7785 - cfun_frame_layout.first_save_gpr_slot),
7786 cfun_frame_layout.first_save_gpr,
7787 cfun_frame_layout.last_save_gpr);
7788 emit_insn (insn);
7789 }
7790
7791 /* Dummy insn to mark literal pool slot. */
7792
7793 if (cfun->machine->base_reg)
7794 emit_insn (gen_main_pool (cfun->machine->base_reg));
7795
7796 offset = cfun_frame_layout.f0_offset;
7797
7798 /* Save f0 and f2. */
7799 for (i = 0; i < 2; i++)
7800 {
7801 if (cfun_fpr_bit_p (i))
7802 {
7803 save_fpr (stack_pointer_rtx, offset, i + 16);
7804 offset += 8;
7805 }
7806 else if (!TARGET_PACKED_STACK)
7807 offset += 8;
7808 }
7809
7810 /* Save f4 and f6. */
7811 offset = cfun_frame_layout.f4_offset;
7812 for (i = 2; i < 4; i++)
7813 {
7814 if (cfun_fpr_bit_p (i))
7815 {
7816 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7817 offset += 8;
7818
7819 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7820 therefore are not frame related. */
7821 if (!call_really_used_regs[i + 16])
7822 RTX_FRAME_RELATED_P (insn) = 1;
7823 }
7824 else if (!TARGET_PACKED_STACK)
7825 offset += 8;
7826 }
7827
7828 if (TARGET_PACKED_STACK
7829 && cfun_save_high_fprs_p
7830 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7831 {
7832 offset = (cfun_frame_layout.f8_offset
7833 + (cfun_frame_layout.high_fprs - 1) * 8);
7834
7835 for (i = 15; i > 7 && offset >= 0; i--)
7836 if (cfun_fpr_bit_p (i))
7837 {
7838 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7839
7840 RTX_FRAME_RELATED_P (insn) = 1;
7841 offset -= 8;
7842 }
7843 if (offset >= cfun_frame_layout.f8_offset)
7844 next_fpr = i + 16;
7845 }
7846
7847 if (!TARGET_PACKED_STACK)
7848 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7849
7850 /* Decrement stack pointer. */
7851
7852 if (cfun_frame_layout.frame_size > 0)
7853 {
7854 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7855 rtx real_frame_off;
7856
7857 if (s390_stack_size)
7858 {
7859 HOST_WIDE_INT stack_guard;
7860
7861 if (s390_stack_guard)
7862 stack_guard = s390_stack_guard;
7863 else
7864 {
7865 /* If no value for stack guard is provided the smallest power of 2
7866 larger than the current frame size is chosen. */
7867 stack_guard = 1;
7868 while (stack_guard < cfun_frame_layout.frame_size)
7869 stack_guard <<= 1;
7870 }
7871
7872 if (cfun_frame_layout.frame_size >= s390_stack_size)
7873 {
7874 warning (0, "frame size of function %qs is "
7875 HOST_WIDE_INT_PRINT_DEC
7876 " bytes exceeding user provided stack limit of "
7877 HOST_WIDE_INT_PRINT_DEC " bytes. "
7878 "An unconditional trap is added.",
7879 current_function_name(), cfun_frame_layout.frame_size,
7880 s390_stack_size);
7881 emit_insn (gen_trap ());
7882 }
7883 else
7884 {
7885 /* stack_guard has to be smaller than s390_stack_size.
7886 Otherwise we would emit an AND with zero which would
7887 not match the test under mask pattern. */
7888 if (stack_guard >= s390_stack_size)
7889 {
7890 warning (0, "frame size of function %qs is "
7891 HOST_WIDE_INT_PRINT_DEC
7892 " bytes which is more than half the stack size. "
7893 "The dynamic check would not be reliable. "
7894 "No check emitted for this function.",
7895 current_function_name(),
7896 cfun_frame_layout.frame_size);
7897 }
7898 else
7899 {
7900 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7901 & ~(stack_guard - 1));
7902
7903 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7904 GEN_INT (stack_check_mask));
7905 if (TARGET_64BIT)
7906 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
7907 t, const0_rtx),
7908 t, const0_rtx, const0_rtx));
7909 else
7910 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
7911 t, const0_rtx),
7912 t, const0_rtx, const0_rtx));
7913 }
7914 }
7915 }
7916
7917 if (s390_warn_framesize > 0
7918 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7919 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7920 current_function_name (), cfun_frame_layout.frame_size);
7921
7922 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7923 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7924
7925 /* Save incoming stack pointer into temp reg. */
7926 if (TARGET_BACKCHAIN || next_fpr)
7927 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7928
7929 /* Subtract frame size from stack pointer. */
7930
7931 if (DISP_IN_RANGE (INTVAL (frame_off)))
7932 {
7933 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7934 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7935 frame_off));
7936 insn = emit_insn (insn);
7937 }
7938 else
7939 {
7940 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7941 frame_off = force_const_mem (Pmode, frame_off);
7942
7943 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7944 annotate_constant_pool_refs (&PATTERN (insn));
7945 }
7946
7947 RTX_FRAME_RELATED_P (insn) = 1;
7948 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7949 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7950 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7951 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7952 real_frame_off)));
7953
7954 /* Set backchain. */
7955
7956 if (TARGET_BACKCHAIN)
7957 {
7958 if (cfun_frame_layout.backchain_offset)
7959 addr = gen_rtx_MEM (Pmode,
7960 plus_constant (stack_pointer_rtx,
7961 cfun_frame_layout.backchain_offset));
7962 else
7963 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7964 set_mem_alias_set (addr, get_frame_alias_set ());
7965 insn = emit_insn (gen_move_insn (addr, temp_reg));
7966 }
7967
7968 /* If we support non-call exceptions (e.g. for Java),
7969 we need to make sure the backchain pointer is set up
7970 before any possibly trapping memory access. */
7971 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
7972 {
7973 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7974 emit_clobber (addr);
7975 }
7976 }
7977
7978 /* Save fprs 8 - 15 (64 bit ABI). */
7979
7980 if (cfun_save_high_fprs_p && next_fpr)
7981 {
7982 /* If the stack might be accessed through a different register
7983 we have to make sure that the stack pointer decrement is not
7984 moved below the use of the stack slots. */
7985 s390_emit_stack_tie ();
7986
7987 insn = emit_insn (gen_add2_insn (temp_reg,
7988 GEN_INT (cfun_frame_layout.f8_offset)));
7989
7990 offset = 0;
7991
7992 for (i = 24; i <= next_fpr; i++)
7993 if (cfun_fpr_bit_p (i - 16))
7994 {
7995 rtx addr = plus_constant (stack_pointer_rtx,
7996 cfun_frame_layout.frame_size
7997 + cfun_frame_layout.f8_offset
7998 + offset);
7999
8000 insn = save_fpr (temp_reg, offset, i);
8001 offset += 8;
8002 RTX_FRAME_RELATED_P (insn) = 1;
8003 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8004 gen_rtx_SET (VOIDmode,
8005 gen_rtx_MEM (DFmode, addr),
8006 gen_rtx_REG (DFmode, i)));
8007 }
8008 }
8009
8010 /* Set frame pointer, if needed. */
8011
8012 if (frame_pointer_needed)
8013 {
8014 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8015 RTX_FRAME_RELATED_P (insn) = 1;
8016 }
8017
8018 /* Set up got pointer, if needed. */
8019
8020 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8021 {
8022 rtx insns = s390_load_got ();
8023
8024 for (insn = insns; insn; insn = NEXT_INSN (insn))
8025 annotate_constant_pool_refs (&PATTERN (insn));
8026
8027 emit_insn (insns);
8028 }
8029
8030 if (TARGET_TPF_PROFILING)
8031 {
8032 /* Generate a BAS instruction to serve as a function
8033 entry intercept to facilitate the use of tracing
8034 algorithms located at the branch target. */
8035 emit_insn (gen_prologue_tpf ());
8036
8037 /* Emit a blockage here so that all code
8038 lies between the profiling mechanisms. */
8039 emit_insn (gen_blockage ());
8040 }
8041 }
8042
8043 /* Expand the epilogue into a bunch of separate insns. */
8044
8045 void
8046 s390_emit_epilogue (bool sibcall)
8047 {
8048 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8049 int area_bottom, area_top, offset = 0;
8050 int next_offset;
8051 rtvec p;
8052 int i;
8053
8054 if (TARGET_TPF_PROFILING)
8055 {
8056
8057 /* Generate a BAS instruction to serve as a function
8058 entry intercept to facilitate the use of tracing
8059 algorithms located at the branch target. */
8060
8061 /* Emit a blockage here so that all code
8062 lies between the profiling mechanisms. */
8063 emit_insn (gen_blockage ());
8064
8065 emit_insn (gen_epilogue_tpf ());
8066 }
8067
8068 /* Check whether to use frame or stack pointer for restore. */
8069
8070 frame_pointer = (frame_pointer_needed
8071 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8072
8073 s390_frame_area (&area_bottom, &area_top);
8074
8075 /* Check whether we can access the register save area.
8076 If not, increment the frame pointer as required. */
8077
8078 if (area_top <= area_bottom)
8079 {
8080 /* Nothing to restore. */
8081 }
8082 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8083 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8084 {
8085 /* Area is in range. */
8086 offset = cfun_frame_layout.frame_size;
8087 }
8088 else
8089 {
8090 rtx insn, frame_off, cfa;
8091
8092 offset = area_bottom < 0 ? -area_bottom : 0;
8093 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8094
8095 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8096 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8097 if (DISP_IN_RANGE (INTVAL (frame_off)))
8098 {
8099 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8100 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8101 insn = emit_insn (insn);
8102 }
8103 else
8104 {
8105 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8106 frame_off = force_const_mem (Pmode, frame_off);
8107
8108 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8109 annotate_constant_pool_refs (&PATTERN (insn));
8110 }
8111 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8112 RTX_FRAME_RELATED_P (insn) = 1;
8113 }
8114
8115 /* Restore call saved fprs. */
8116
8117 if (TARGET_64BIT)
8118 {
8119 if (cfun_save_high_fprs_p)
8120 {
8121 next_offset = cfun_frame_layout.f8_offset;
8122 for (i = 24; i < 32; i++)
8123 {
8124 if (cfun_fpr_bit_p (i - 16))
8125 {
8126 restore_fpr (frame_pointer,
8127 offset + next_offset, i);
8128 cfa_restores
8129 = alloc_reg_note (REG_CFA_RESTORE,
8130 gen_rtx_REG (DFmode, i), cfa_restores);
8131 next_offset += 8;
8132 }
8133 }
8134 }
8135
8136 }
8137 else
8138 {
8139 next_offset = cfun_frame_layout.f4_offset;
8140 for (i = 18; i < 20; i++)
8141 {
8142 if (cfun_fpr_bit_p (i - 16))
8143 {
8144 restore_fpr (frame_pointer,
8145 offset + next_offset, i);
8146 cfa_restores
8147 = alloc_reg_note (REG_CFA_RESTORE,
8148 gen_rtx_REG (DFmode, i), cfa_restores);
8149 next_offset += 8;
8150 }
8151 else if (!TARGET_PACKED_STACK)
8152 next_offset += 8;
8153 }
8154
8155 }
8156
8157 /* Return register. */
8158
8159 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8160
8161 /* Restore call saved gprs. */
8162
8163 if (cfun_frame_layout.first_restore_gpr != -1)
8164 {
8165 rtx insn, addr;
8166 int i;
8167
8168 /* Check for global register and save them
8169 to stack location from where they get restored. */
8170
8171 for (i = cfun_frame_layout.first_restore_gpr;
8172 i <= cfun_frame_layout.last_restore_gpr;
8173 i++)
8174 {
8175 if (global_not_special_regno_p (i))
8176 {
8177 addr = plus_constant (frame_pointer,
8178 offset + cfun_frame_layout.gprs_offset
8179 + (i - cfun_frame_layout.first_save_gpr_slot)
8180 * UNITS_PER_LONG);
8181 addr = gen_rtx_MEM (Pmode, addr);
8182 set_mem_alias_set (addr, get_frame_alias_set ());
8183 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8184 }
8185 else
8186 cfa_restores
8187 = alloc_reg_note (REG_CFA_RESTORE,
8188 gen_rtx_REG (Pmode, i), cfa_restores);
8189 }
8190
8191 if (! sibcall)
8192 {
8193 /* Fetch return address from stack before load multiple,
8194 this will do good for scheduling. */
8195
8196 if (cfun_frame_layout.save_return_addr_p
8197 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8198 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8199 {
8200 int return_regnum = find_unused_clobbered_reg();
8201 if (!return_regnum)
8202 return_regnum = 4;
8203 return_reg = gen_rtx_REG (Pmode, return_regnum);
8204
8205 addr = plus_constant (frame_pointer,
8206 offset + cfun_frame_layout.gprs_offset
8207 + (RETURN_REGNUM
8208 - cfun_frame_layout.first_save_gpr_slot)
8209 * UNITS_PER_LONG);
8210 addr = gen_rtx_MEM (Pmode, addr);
8211 set_mem_alias_set (addr, get_frame_alias_set ());
8212 emit_move_insn (return_reg, addr);
8213 }
8214 }
8215
8216 insn = restore_gprs (frame_pointer,
8217 offset + cfun_frame_layout.gprs_offset
8218 + (cfun_frame_layout.first_restore_gpr
8219 - cfun_frame_layout.first_save_gpr_slot)
8220 * UNITS_PER_LONG,
8221 cfun_frame_layout.first_restore_gpr,
8222 cfun_frame_layout.last_restore_gpr);
8223 insn = emit_insn (insn);
8224 REG_NOTES (insn) = cfa_restores;
8225 add_reg_note (insn, REG_CFA_DEF_CFA,
8226 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8227 RTX_FRAME_RELATED_P (insn) = 1;
8228 }
8229
8230 if (! sibcall)
8231 {
8232
8233 /* Return to caller. */
8234
8235 p = rtvec_alloc (2);
8236
8237 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8238 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8239 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8240 }
8241 }
8242
8243
8244 /* Return the size in bytes of a function argument of
8245 type TYPE and/or mode MODE. At least one of TYPE or
8246 MODE must be specified. */
8247
8248 static int
8249 s390_function_arg_size (enum machine_mode mode, const_tree type)
8250 {
8251 if (type)
8252 return int_size_in_bytes (type);
8253
8254 /* No type info available for some library calls ... */
8255 if (mode != BLKmode)
8256 return GET_MODE_SIZE (mode);
8257
8258 /* If we have neither type nor mode, abort */
8259 gcc_unreachable ();
8260 }
8261
8262 /* Return true if a function argument of type TYPE and mode MODE
8263 is to be passed in a floating-point register, if available. */
8264
8265 static bool
8266 s390_function_arg_float (enum machine_mode mode, tree type)
8267 {
8268 int size = s390_function_arg_size (mode, type);
8269 if (size > 8)
8270 return false;
8271
8272 /* Soft-float changes the ABI: no floating-point registers are used. */
8273 if (TARGET_SOFT_FLOAT)
8274 return false;
8275
8276 /* No type info available for some library calls ... */
8277 if (!type)
8278 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8279
8280 /* The ABI says that record types with a single member are treated
8281 just like that member would be. */
8282 while (TREE_CODE (type) == RECORD_TYPE)
8283 {
8284 tree field, single = NULL_TREE;
8285
8286 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8287 {
8288 if (TREE_CODE (field) != FIELD_DECL)
8289 continue;
8290
8291 if (single == NULL_TREE)
8292 single = TREE_TYPE (field);
8293 else
8294 return false;
8295 }
8296
8297 if (single == NULL_TREE)
8298 return false;
8299 else
8300 type = single;
8301 }
8302
8303 return TREE_CODE (type) == REAL_TYPE;
8304 }
8305
8306 /* Return true if a function argument of type TYPE and mode MODE
8307 is to be passed in an integer register, or a pair of integer
8308 registers, if available. */
8309
8310 static bool
8311 s390_function_arg_integer (enum machine_mode mode, tree type)
8312 {
8313 int size = s390_function_arg_size (mode, type);
8314 if (size > 8)
8315 return false;
8316
8317 /* No type info available for some library calls ... */
8318 if (!type)
8319 return GET_MODE_CLASS (mode) == MODE_INT
8320 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8321
8322 /* We accept small integral (and similar) types. */
8323 if (INTEGRAL_TYPE_P (type)
8324 || POINTER_TYPE_P (type)
8325 || TREE_CODE (type) == OFFSET_TYPE
8326 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8327 return true;
8328
8329 /* We also accept structs of size 1, 2, 4, 8 that are not
8330 passed in floating-point registers. */
8331 if (AGGREGATE_TYPE_P (type)
8332 && exact_log2 (size) >= 0
8333 && !s390_function_arg_float (mode, type))
8334 return true;
8335
8336 return false;
8337 }
8338
8339 /* Return 1 if a function argument of type TYPE and mode MODE
8340 is to be passed by reference. The ABI specifies that only
8341 structures of size 1, 2, 4, or 8 bytes are passed by value,
8342 all other structures (and complex numbers) are passed by
8343 reference. */
8344
8345 static bool
8346 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8347 enum machine_mode mode, const_tree type,
8348 bool named ATTRIBUTE_UNUSED)
8349 {
8350 int size = s390_function_arg_size (mode, type);
8351 if (size > 8)
8352 return true;
8353
8354 if (type)
8355 {
8356 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8357 return 1;
8358
8359 if (TREE_CODE (type) == COMPLEX_TYPE
8360 || TREE_CODE (type) == VECTOR_TYPE)
8361 return 1;
8362 }
8363
8364 return 0;
8365 }
8366
8367 /* Update the data in CUM to advance over an argument of mode MODE and
8368 data type TYPE. (TYPE is null for libcalls where that information
8369 may not be available.). The boolean NAMED specifies whether the
8370 argument is a named argument (as opposed to an unnamed argument
8371 matching an ellipsis). */
8372
8373 void
8374 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8375 tree type, int named ATTRIBUTE_UNUSED)
8376 {
8377 if (s390_function_arg_float (mode, type))
8378 {
8379 cum->fprs += 1;
8380 }
8381 else if (s390_function_arg_integer (mode, type))
8382 {
8383 int size = s390_function_arg_size (mode, type);
8384 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8385 }
8386 else
8387 gcc_unreachable ();
8388 }
8389
8390 /* Define where to put the arguments to a function.
8391 Value is zero to push the argument on the stack,
8392 or a hard register in which to store the argument.
8393
8394 MODE is the argument's machine mode.
8395 TYPE is the data type of the argument (as a tree).
8396 This is null for libcalls where that information may
8397 not be available.
8398 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8399 the preceding args and about the function being called.
8400 NAMED is nonzero if this argument is a named parameter
8401 (otherwise it is an extra parameter matching an ellipsis).
8402
8403 On S/390, we use general purpose registers 2 through 6 to
8404 pass integer, pointer, and certain structure arguments, and
8405 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8406 to pass floating point arguments. All remaining arguments
8407 are pushed to the stack. */
8408
8409 rtx
8410 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8411 int named ATTRIBUTE_UNUSED)
8412 {
8413 if (s390_function_arg_float (mode, type))
8414 {
8415 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8416 return 0;
8417 else
8418 return gen_rtx_REG (mode, cum->fprs + 16);
8419 }
8420 else if (s390_function_arg_integer (mode, type))
8421 {
8422 int size = s390_function_arg_size (mode, type);
8423 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8424
8425 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8426 return 0;
8427 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8428 return gen_rtx_REG (mode, cum->gprs + 2);
8429 else if (n_gprs == 2)
8430 {
8431 rtvec p = rtvec_alloc (2);
8432
8433 RTVEC_ELT (p, 0)
8434 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8435 const0_rtx);
8436 RTVEC_ELT (p, 1)
8437 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8438 GEN_INT (4));
8439
8440 return gen_rtx_PARALLEL (mode, p);
8441 }
8442 }
8443
8444 /* After the real arguments, expand_call calls us once again
8445 with a void_type_node type. Whatever we return here is
8446 passed as operand 2 to the call expanders.
8447
8448 We don't need this feature ... */
8449 else if (type == void_type_node)
8450 return const0_rtx;
8451
8452 gcc_unreachable ();
8453 }
8454
8455 /* Return true if return values of type TYPE should be returned
8456 in a memory buffer whose address is passed by the caller as
8457 hidden first argument. */
8458
8459 static bool
8460 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8461 {
8462 /* We accept small integral (and similar) types. */
8463 if (INTEGRAL_TYPE_P (type)
8464 || POINTER_TYPE_P (type)
8465 || TREE_CODE (type) == OFFSET_TYPE
8466 || TREE_CODE (type) == REAL_TYPE)
8467 return int_size_in_bytes (type) > 8;
8468
8469 /* Aggregates and similar constructs are always returned
8470 in memory. */
8471 if (AGGREGATE_TYPE_P (type)
8472 || TREE_CODE (type) == COMPLEX_TYPE
8473 || TREE_CODE (type) == VECTOR_TYPE)
8474 return true;
8475
8476 /* ??? We get called on all sorts of random stuff from
8477 aggregate_value_p. We can't abort, but it's not clear
8478 what's safe to return. Pretend it's a struct I guess. */
8479 return true;
8480 }
8481
8482 /* Function arguments and return values are promoted to word size. */
8483
8484 static enum machine_mode
8485 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8486 int *punsignedp,
8487 const_tree fntype ATTRIBUTE_UNUSED,
8488 int for_return ATTRIBUTE_UNUSED)
8489 {
8490 if (INTEGRAL_MODE_P (mode)
8491 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8492 {
8493 if (POINTER_TYPE_P (type))
8494 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8495 return Pmode;
8496 }
8497
8498 return mode;
8499 }
8500
8501 /* Define where to return a (scalar) value of type TYPE.
8502 If TYPE is null, define where to return a (scalar)
8503 value of mode MODE from a libcall. */
8504
8505 rtx
8506 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8507 {
8508 if (type)
8509 {
8510 int unsignedp = TYPE_UNSIGNED (type);
8511 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8512 }
8513
8514 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8515 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8516
8517 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8518 return gen_rtx_REG (mode, 16);
8519 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8520 || UNITS_PER_LONG == UNITS_PER_WORD)
8521 return gen_rtx_REG (mode, 2);
8522 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8523 {
8524 rtvec p = rtvec_alloc (2);
8525
8526 RTVEC_ELT (p, 0)
8527 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8528 RTVEC_ELT (p, 1)
8529 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8530
8531 return gen_rtx_PARALLEL (mode, p);
8532 }
8533
8534 gcc_unreachable ();
8535 }
8536
8537
8538 /* Create and return the va_list datatype.
8539
8540 On S/390, va_list is an array type equivalent to
8541
8542 typedef struct __va_list_tag
8543 {
8544 long __gpr;
8545 long __fpr;
8546 void *__overflow_arg_area;
8547 void *__reg_save_area;
8548 } va_list[1];
8549
8550 where __gpr and __fpr hold the number of general purpose
8551 or floating point arguments used up to now, respectively,
8552 __overflow_arg_area points to the stack location of the
8553 next argument passed on the stack, and __reg_save_area
8554 always points to the start of the register area in the
8555 call frame of the current function. The function prologue
8556 saves all registers used for argument passing into this
8557 area if the function uses variable arguments. */
8558
8559 static tree
8560 s390_build_builtin_va_list (void)
8561 {
8562 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8563
8564 record = lang_hooks.types.make_type (RECORD_TYPE);
8565
8566 type_decl =
8567 build_decl (BUILTINS_LOCATION,
8568 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8569
8570 f_gpr = build_decl (BUILTINS_LOCATION,
8571 FIELD_DECL, get_identifier ("__gpr"),
8572 long_integer_type_node);
8573 f_fpr = build_decl (BUILTINS_LOCATION,
8574 FIELD_DECL, get_identifier ("__fpr"),
8575 long_integer_type_node);
8576 f_ovf = build_decl (BUILTINS_LOCATION,
8577 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8578 ptr_type_node);
8579 f_sav = build_decl (BUILTINS_LOCATION,
8580 FIELD_DECL, get_identifier ("__reg_save_area"),
8581 ptr_type_node);
8582
8583 va_list_gpr_counter_field = f_gpr;
8584 va_list_fpr_counter_field = f_fpr;
8585
8586 DECL_FIELD_CONTEXT (f_gpr) = record;
8587 DECL_FIELD_CONTEXT (f_fpr) = record;
8588 DECL_FIELD_CONTEXT (f_ovf) = record;
8589 DECL_FIELD_CONTEXT (f_sav) = record;
8590
8591 TREE_CHAIN (record) = type_decl;
8592 TYPE_NAME (record) = type_decl;
8593 TYPE_FIELDS (record) = f_gpr;
8594 DECL_CHAIN (f_gpr) = f_fpr;
8595 DECL_CHAIN (f_fpr) = f_ovf;
8596 DECL_CHAIN (f_ovf) = f_sav;
8597
8598 layout_type (record);
8599
8600 /* The correct type is an array type of one element. */
8601 return build_array_type (record, build_index_type (size_zero_node));
8602 }
8603
8604 /* Implement va_start by filling the va_list structure VALIST.
8605 STDARG_P is always true, and ignored.
8606 NEXTARG points to the first anonymous stack argument.
8607
8608 The following global variables are used to initialize
8609 the va_list structure:
8610
8611 crtl->args.info:
8612 holds number of gprs and fprs used for named arguments.
8613 crtl->args.arg_offset_rtx:
8614 holds the offset of the first anonymous stack argument
8615 (relative to the virtual arg pointer). */
8616
8617 static void
8618 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8619 {
8620 HOST_WIDE_INT n_gpr, n_fpr;
8621 int off;
8622 tree f_gpr, f_fpr, f_ovf, f_sav;
8623 tree gpr, fpr, ovf, sav, t;
8624
8625 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8626 f_fpr = DECL_CHAIN (f_gpr);
8627 f_ovf = DECL_CHAIN (f_fpr);
8628 f_sav = DECL_CHAIN (f_ovf);
8629
8630 valist = build_va_arg_indirect_ref (valist);
8631 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8632 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8633 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8634 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8635
8636 /* Count number of gp and fp argument registers used. */
8637
8638 n_gpr = crtl->args.info.gprs;
8639 n_fpr = crtl->args.info.fprs;
8640
8641 if (cfun->va_list_gpr_size)
8642 {
8643 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8644 build_int_cst (NULL_TREE, n_gpr));
8645 TREE_SIDE_EFFECTS (t) = 1;
8646 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8647 }
8648
8649 if (cfun->va_list_fpr_size)
8650 {
8651 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8652 build_int_cst (NULL_TREE, n_fpr));
8653 TREE_SIDE_EFFECTS (t) = 1;
8654 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8655 }
8656
8657 /* Find the overflow area. */
8658 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8659 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8660 {
8661 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8662
8663 off = INTVAL (crtl->args.arg_offset_rtx);
8664 off = off < 0 ? 0 : off;
8665 if (TARGET_DEBUG_ARG)
8666 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8667 (int)n_gpr, (int)n_fpr, off);
8668
8669 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8670
8671 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8672 TREE_SIDE_EFFECTS (t) = 1;
8673 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8674 }
8675
8676 /* Find the register save area. */
8677 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8678 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8679 {
8680 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8681 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8682 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8683
8684 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8685 TREE_SIDE_EFFECTS (t) = 1;
8686 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8687 }
8688 }
8689
8690 /* Implement va_arg by updating the va_list structure
8691 VALIST as required to retrieve an argument of type
8692 TYPE, and returning that argument.
8693
8694 Generates code equivalent to:
8695
8696 if (integral value) {
8697 if (size <= 4 && args.gpr < 5 ||
8698 size > 4 && args.gpr < 4 )
8699 ret = args.reg_save_area[args.gpr+8]
8700 else
8701 ret = *args.overflow_arg_area++;
8702 } else if (float value) {
8703 if (args.fgpr < 2)
8704 ret = args.reg_save_area[args.fpr+64]
8705 else
8706 ret = *args.overflow_arg_area++;
8707 } else if (aggregate value) {
8708 if (args.gpr < 5)
8709 ret = *args.reg_save_area[args.gpr]
8710 else
8711 ret = **args.overflow_arg_area++;
8712 } */
8713
8714 static tree
8715 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8716 gimple_seq *post_p ATTRIBUTE_UNUSED)
8717 {
8718 tree f_gpr, f_fpr, f_ovf, f_sav;
8719 tree gpr, fpr, ovf, sav, reg, t, u;
8720 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8721 tree lab_false, lab_over, addr;
8722
8723 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8724 f_fpr = DECL_CHAIN (f_gpr);
8725 f_ovf = DECL_CHAIN (f_fpr);
8726 f_sav = DECL_CHAIN (f_ovf);
8727
8728 valist = build_va_arg_indirect_ref (valist);
8729 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8730 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8731 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8732
8733 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8734 both appear on a lhs. */
8735 valist = unshare_expr (valist);
8736 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8737
8738 size = int_size_in_bytes (type);
8739
8740 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8741 {
8742 if (TARGET_DEBUG_ARG)
8743 {
8744 fprintf (stderr, "va_arg: aggregate type");
8745 debug_tree (type);
8746 }
8747
8748 /* Aggregates are passed by reference. */
8749 indirect_p = 1;
8750 reg = gpr;
8751 n_reg = 1;
8752
8753 /* kernel stack layout on 31 bit: It is assumed here that no padding
8754 will be added by s390_frame_info because for va_args always an even
8755 number of gprs has to be saved r15-r2 = 14 regs. */
8756 sav_ofs = 2 * UNITS_PER_LONG;
8757 sav_scale = UNITS_PER_LONG;
8758 size = UNITS_PER_LONG;
8759 max_reg = GP_ARG_NUM_REG - n_reg;
8760 }
8761 else if (s390_function_arg_float (TYPE_MODE (type), type))
8762 {
8763 if (TARGET_DEBUG_ARG)
8764 {
8765 fprintf (stderr, "va_arg: float type");
8766 debug_tree (type);
8767 }
8768
8769 /* FP args go in FP registers, if present. */
8770 indirect_p = 0;
8771 reg = fpr;
8772 n_reg = 1;
8773 sav_ofs = 16 * UNITS_PER_LONG;
8774 sav_scale = 8;
8775 max_reg = FP_ARG_NUM_REG - n_reg;
8776 }
8777 else
8778 {
8779 if (TARGET_DEBUG_ARG)
8780 {
8781 fprintf (stderr, "va_arg: other type");
8782 debug_tree (type);
8783 }
8784
8785 /* Otherwise into GP registers. */
8786 indirect_p = 0;
8787 reg = gpr;
8788 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8789
8790 /* kernel stack layout on 31 bit: It is assumed here that no padding
8791 will be added by s390_frame_info because for va_args always an even
8792 number of gprs has to be saved r15-r2 = 14 regs. */
8793 sav_ofs = 2 * UNITS_PER_LONG;
8794
8795 if (size < UNITS_PER_LONG)
8796 sav_ofs += UNITS_PER_LONG - size;
8797
8798 sav_scale = UNITS_PER_LONG;
8799 max_reg = GP_ARG_NUM_REG - n_reg;
8800 }
8801
8802 /* Pull the value out of the saved registers ... */
8803
8804 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8805 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8806 addr = create_tmp_var (ptr_type_node, "addr");
8807
8808 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8809 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8810 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8811 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8812 gimplify_and_add (t, pre_p);
8813
8814 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8815 size_int (sav_ofs));
8816 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8817 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8818 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8819
8820 gimplify_assign (addr, t, pre_p);
8821
8822 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8823
8824 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8825
8826
8827 /* ... Otherwise out of the overflow area. */
8828
8829 t = ovf;
8830 if (size < UNITS_PER_LONG)
8831 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8832 size_int (UNITS_PER_LONG - size));
8833
8834 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8835
8836 gimplify_assign (addr, t, pre_p);
8837
8838 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8839 size_int (size));
8840 gimplify_assign (ovf, t, pre_p);
8841
8842 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8843
8844
8845 /* Increment register save count. */
8846
8847 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8848 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8849 gimplify_and_add (u, pre_p);
8850
8851 if (indirect_p)
8852 {
8853 t = build_pointer_type_for_mode (build_pointer_type (type),
8854 ptr_mode, true);
8855 addr = fold_convert (t, addr);
8856 addr = build_va_arg_indirect_ref (addr);
8857 }
8858 else
8859 {
8860 t = build_pointer_type_for_mode (type, ptr_mode, true);
8861 addr = fold_convert (t, addr);
8862 }
8863
8864 return build_va_arg_indirect_ref (addr);
8865 }
8866
8867
8868 /* Builtins. */
8869
8870 enum s390_builtin
8871 {
8872 S390_BUILTIN_THREAD_POINTER,
8873 S390_BUILTIN_SET_THREAD_POINTER,
8874
8875 S390_BUILTIN_max
8876 };
8877
8878 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8879 CODE_FOR_get_tp_64,
8880 CODE_FOR_set_tp_64
8881 };
8882
8883 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8884 CODE_FOR_get_tp_31,
8885 CODE_FOR_set_tp_31
8886 };
8887
8888 static void
8889 s390_init_builtins (void)
8890 {
8891 tree ftype;
8892
8893 ftype = build_function_type (ptr_type_node, void_list_node);
8894 add_builtin_function ("__builtin_thread_pointer", ftype,
8895 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8896 NULL, NULL_TREE);
8897
8898 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8899 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8900 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8901 NULL, NULL_TREE);
8902 }
8903
8904 /* Expand an expression EXP that calls a built-in function,
8905 with result going to TARGET if that's convenient
8906 (and in mode MODE if that's convenient).
8907 SUBTARGET may be used as the target for computing one of EXP's operands.
8908 IGNORE is nonzero if the value is to be ignored. */
8909
8910 static rtx
8911 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8912 enum machine_mode mode ATTRIBUTE_UNUSED,
8913 int ignore ATTRIBUTE_UNUSED)
8914 {
8915 #define MAX_ARGS 2
8916
8917 enum insn_code const *code_for_builtin =
8918 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8919
8920 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8921 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8922 enum insn_code icode;
8923 rtx op[MAX_ARGS], pat;
8924 int arity;
8925 bool nonvoid;
8926 tree arg;
8927 call_expr_arg_iterator iter;
8928
8929 if (fcode >= S390_BUILTIN_max)
8930 internal_error ("bad builtin fcode");
8931 icode = code_for_builtin[fcode];
8932 if (icode == 0)
8933 internal_error ("bad builtin fcode");
8934
8935 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8936
8937 arity = 0;
8938 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8939 {
8940 const struct insn_operand_data *insn_op;
8941
8942 if (arg == error_mark_node)
8943 return NULL_RTX;
8944 if (arity > MAX_ARGS)
8945 return NULL_RTX;
8946
8947 insn_op = &insn_data[icode].operand[arity + nonvoid];
8948
8949 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8950
8951 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8952 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8953 arity++;
8954 }
8955
8956 if (nonvoid)
8957 {
8958 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8959 if (!target
8960 || GET_MODE (target) != tmode
8961 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8962 target = gen_reg_rtx (tmode);
8963 }
8964
8965 switch (arity)
8966 {
8967 case 0:
8968 pat = GEN_FCN (icode) (target);
8969 break;
8970 case 1:
8971 if (nonvoid)
8972 pat = GEN_FCN (icode) (target, op[0]);
8973 else
8974 pat = GEN_FCN (icode) (op[0]);
8975 break;
8976 case 2:
8977 pat = GEN_FCN (icode) (target, op[0], op[1]);
8978 break;
8979 default:
8980 gcc_unreachable ();
8981 }
8982 if (!pat)
8983 return NULL_RTX;
8984 emit_insn (pat);
8985
8986 if (nonvoid)
8987 return target;
8988 else
8989 return const0_rtx;
8990 }
8991
8992
8993 /* Output assembly code for the trampoline template to
8994 stdio stream FILE.
8995
8996 On S/390, we use gpr 1 internally in the trampoline code;
8997 gpr 0 is used to hold the static chain. */
8998
8999 static void
9000 s390_asm_trampoline_template (FILE *file)
9001 {
9002 rtx op[2];
9003 op[0] = gen_rtx_REG (Pmode, 0);
9004 op[1] = gen_rtx_REG (Pmode, 1);
9005
9006 if (TARGET_64BIT)
9007 {
9008 output_asm_insn ("basr\t%1,0", op);
9009 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9010 output_asm_insn ("br\t%1", op);
9011 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9012 }
9013 else
9014 {
9015 output_asm_insn ("basr\t%1,0", op);
9016 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9017 output_asm_insn ("br\t%1", op);
9018 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9019 }
9020 }
9021
9022 /* Emit RTL insns to initialize the variable parts of a trampoline.
9023 FNADDR is an RTX for the address of the function's pure code.
9024 CXT is an RTX for the static chain value for the function. */
9025
9026 static void
9027 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9028 {
9029 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9030 rtx mem;
9031
9032 emit_block_move (m_tramp, assemble_trampoline_template (),
9033 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9034
9035 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9036 emit_move_insn (mem, cxt);
9037 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9038 emit_move_insn (mem, fnaddr);
9039 }
9040
9041 /* Output assembler code to FILE to increment profiler label # LABELNO
9042 for profiling a function entry. */
9043
9044 void
9045 s390_function_profiler (FILE *file, int labelno)
9046 {
9047 rtx op[7];
9048
9049 char label[128];
9050 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9051
9052 fprintf (file, "# function profiler \n");
9053
9054 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9055 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9056 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9057
9058 op[2] = gen_rtx_REG (Pmode, 1);
9059 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9060 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9061
9062 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9063 if (flag_pic)
9064 {
9065 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9066 op[4] = gen_rtx_CONST (Pmode, op[4]);
9067 }
9068
9069 if (TARGET_64BIT)
9070 {
9071 output_asm_insn ("stg\t%0,%1", op);
9072 output_asm_insn ("larl\t%2,%3", op);
9073 output_asm_insn ("brasl\t%0,%4", op);
9074 output_asm_insn ("lg\t%0,%1", op);
9075 }
9076 else if (!flag_pic)
9077 {
9078 op[6] = gen_label_rtx ();
9079
9080 output_asm_insn ("st\t%0,%1", op);
9081 output_asm_insn ("bras\t%2,%l6", op);
9082 output_asm_insn (".long\t%4", op);
9083 output_asm_insn (".long\t%3", op);
9084 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9085 output_asm_insn ("l\t%0,0(%2)", op);
9086 output_asm_insn ("l\t%2,4(%2)", op);
9087 output_asm_insn ("basr\t%0,%0", op);
9088 output_asm_insn ("l\t%0,%1", op);
9089 }
9090 else
9091 {
9092 op[5] = gen_label_rtx ();
9093 op[6] = gen_label_rtx ();
9094
9095 output_asm_insn ("st\t%0,%1", op);
9096 output_asm_insn ("bras\t%2,%l6", op);
9097 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9098 output_asm_insn (".long\t%4-%l5", op);
9099 output_asm_insn (".long\t%3-%l5", op);
9100 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9101 output_asm_insn ("lr\t%0,%2", op);
9102 output_asm_insn ("a\t%0,0(%2)", op);
9103 output_asm_insn ("a\t%2,4(%2)", op);
9104 output_asm_insn ("basr\t%0,%0", op);
9105 output_asm_insn ("l\t%0,%1", op);
9106 }
9107 }
9108
9109 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9110 into its SYMBOL_REF_FLAGS. */
9111
9112 static void
9113 s390_encode_section_info (tree decl, rtx rtl, int first)
9114 {
9115 default_encode_section_info (decl, rtl, first);
9116
9117 if (TREE_CODE (decl) == VAR_DECL)
9118 {
9119 /* If a variable has a forced alignment to < 2 bytes, mark it
9120 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9121 operand. */
9122 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9123 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9124 if (!DECL_SIZE (decl)
9125 || !DECL_ALIGN (decl)
9126 || !host_integerp (DECL_SIZE (decl), 0)
9127 || (DECL_ALIGN (decl) <= 64
9128 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9129 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9130 }
9131
9132 /* Literal pool references don't have a decl so they are handled
9133 differently here. We rely on the information in the MEM_ALIGN
9134 entry to decide upon natural alignment. */
9135 if (MEM_P (rtl)
9136 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9137 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9138 && (MEM_ALIGN (rtl) == 0
9139 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9140 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9141 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9142 }
9143
9144 /* Output thunk to FILE that implements a C++ virtual function call (with
9145 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9146 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9147 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9148 relative to the resulting this pointer. */
9149
9150 static void
9151 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9152 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9153 tree function)
9154 {
9155 rtx op[10];
9156 int nonlocal = 0;
9157
9158 /* Make sure unwind info is emitted for the thunk if needed. */
9159 final_start_function (emit_barrier (), file, 1);
9160
9161 /* Operand 0 is the target function. */
9162 op[0] = XEXP (DECL_RTL (function), 0);
9163 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9164 {
9165 nonlocal = 1;
9166 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9167 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9168 op[0] = gen_rtx_CONST (Pmode, op[0]);
9169 }
9170
9171 /* Operand 1 is the 'this' pointer. */
9172 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9173 op[1] = gen_rtx_REG (Pmode, 3);
9174 else
9175 op[1] = gen_rtx_REG (Pmode, 2);
9176
9177 /* Operand 2 is the delta. */
9178 op[2] = GEN_INT (delta);
9179
9180 /* Operand 3 is the vcall_offset. */
9181 op[3] = GEN_INT (vcall_offset);
9182
9183 /* Operand 4 is the temporary register. */
9184 op[4] = gen_rtx_REG (Pmode, 1);
9185
9186 /* Operands 5 to 8 can be used as labels. */
9187 op[5] = NULL_RTX;
9188 op[6] = NULL_RTX;
9189 op[7] = NULL_RTX;
9190 op[8] = NULL_RTX;
9191
9192 /* Operand 9 can be used for temporary register. */
9193 op[9] = NULL_RTX;
9194
9195 /* Generate code. */
9196 if (TARGET_64BIT)
9197 {
9198 /* Setup literal pool pointer if required. */
9199 if ((!DISP_IN_RANGE (delta)
9200 && !CONST_OK_FOR_K (delta)
9201 && !CONST_OK_FOR_Os (delta))
9202 || (!DISP_IN_RANGE (vcall_offset)
9203 && !CONST_OK_FOR_K (vcall_offset)
9204 && !CONST_OK_FOR_Os (vcall_offset)))
9205 {
9206 op[5] = gen_label_rtx ();
9207 output_asm_insn ("larl\t%4,%5", op);
9208 }
9209
9210 /* Add DELTA to this pointer. */
9211 if (delta)
9212 {
9213 if (CONST_OK_FOR_J (delta))
9214 output_asm_insn ("la\t%1,%2(%1)", op);
9215 else if (DISP_IN_RANGE (delta))
9216 output_asm_insn ("lay\t%1,%2(%1)", op);
9217 else if (CONST_OK_FOR_K (delta))
9218 output_asm_insn ("aghi\t%1,%2", op);
9219 else if (CONST_OK_FOR_Os (delta))
9220 output_asm_insn ("agfi\t%1,%2", op);
9221 else
9222 {
9223 op[6] = gen_label_rtx ();
9224 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9225 }
9226 }
9227
9228 /* Perform vcall adjustment. */
9229 if (vcall_offset)
9230 {
9231 if (DISP_IN_RANGE (vcall_offset))
9232 {
9233 output_asm_insn ("lg\t%4,0(%1)", op);
9234 output_asm_insn ("ag\t%1,%3(%4)", op);
9235 }
9236 else if (CONST_OK_FOR_K (vcall_offset))
9237 {
9238 output_asm_insn ("lghi\t%4,%3", op);
9239 output_asm_insn ("ag\t%4,0(%1)", op);
9240 output_asm_insn ("ag\t%1,0(%4)", op);
9241 }
9242 else if (CONST_OK_FOR_Os (vcall_offset))
9243 {
9244 output_asm_insn ("lgfi\t%4,%3", op);
9245 output_asm_insn ("ag\t%4,0(%1)", op);
9246 output_asm_insn ("ag\t%1,0(%4)", op);
9247 }
9248 else
9249 {
9250 op[7] = gen_label_rtx ();
9251 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9252 output_asm_insn ("ag\t%4,0(%1)", op);
9253 output_asm_insn ("ag\t%1,0(%4)", op);
9254 }
9255 }
9256
9257 /* Jump to target. */
9258 output_asm_insn ("jg\t%0", op);
9259
9260 /* Output literal pool if required. */
9261 if (op[5])
9262 {
9263 output_asm_insn (".align\t4", op);
9264 targetm.asm_out.internal_label (file, "L",
9265 CODE_LABEL_NUMBER (op[5]));
9266 }
9267 if (op[6])
9268 {
9269 targetm.asm_out.internal_label (file, "L",
9270 CODE_LABEL_NUMBER (op[6]));
9271 output_asm_insn (".long\t%2", op);
9272 }
9273 if (op[7])
9274 {
9275 targetm.asm_out.internal_label (file, "L",
9276 CODE_LABEL_NUMBER (op[7]));
9277 output_asm_insn (".long\t%3", op);
9278 }
9279 }
9280 else
9281 {
9282 /* Setup base pointer if required. */
9283 if (!vcall_offset
9284 || (!DISP_IN_RANGE (delta)
9285 && !CONST_OK_FOR_K (delta)
9286 && !CONST_OK_FOR_Os (delta))
9287 || (!DISP_IN_RANGE (delta)
9288 && !CONST_OK_FOR_K (vcall_offset)
9289 && !CONST_OK_FOR_Os (vcall_offset)))
9290 {
9291 op[5] = gen_label_rtx ();
9292 output_asm_insn ("basr\t%4,0", op);
9293 targetm.asm_out.internal_label (file, "L",
9294 CODE_LABEL_NUMBER (op[5]));
9295 }
9296
9297 /* Add DELTA to this pointer. */
9298 if (delta)
9299 {
9300 if (CONST_OK_FOR_J (delta))
9301 output_asm_insn ("la\t%1,%2(%1)", op);
9302 else if (DISP_IN_RANGE (delta))
9303 output_asm_insn ("lay\t%1,%2(%1)", op);
9304 else if (CONST_OK_FOR_K (delta))
9305 output_asm_insn ("ahi\t%1,%2", op);
9306 else if (CONST_OK_FOR_Os (delta))
9307 output_asm_insn ("afi\t%1,%2", op);
9308 else
9309 {
9310 op[6] = gen_label_rtx ();
9311 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9312 }
9313 }
9314
9315 /* Perform vcall adjustment. */
9316 if (vcall_offset)
9317 {
9318 if (CONST_OK_FOR_J (vcall_offset))
9319 {
9320 output_asm_insn ("l\t%4,0(%1)", op);
9321 output_asm_insn ("a\t%1,%3(%4)", op);
9322 }
9323 else if (DISP_IN_RANGE (vcall_offset))
9324 {
9325 output_asm_insn ("l\t%4,0(%1)", op);
9326 output_asm_insn ("ay\t%1,%3(%4)", op);
9327 }
9328 else if (CONST_OK_FOR_K (vcall_offset))
9329 {
9330 output_asm_insn ("lhi\t%4,%3", op);
9331 output_asm_insn ("a\t%4,0(%1)", op);
9332 output_asm_insn ("a\t%1,0(%4)", op);
9333 }
9334 else if (CONST_OK_FOR_Os (vcall_offset))
9335 {
9336 output_asm_insn ("iilf\t%4,%3", op);
9337 output_asm_insn ("a\t%4,0(%1)", op);
9338 output_asm_insn ("a\t%1,0(%4)", op);
9339 }
9340 else
9341 {
9342 op[7] = gen_label_rtx ();
9343 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9344 output_asm_insn ("a\t%4,0(%1)", op);
9345 output_asm_insn ("a\t%1,0(%4)", op);
9346 }
9347
9348 /* We had to clobber the base pointer register.
9349 Re-setup the base pointer (with a different base). */
9350 op[5] = gen_label_rtx ();
9351 output_asm_insn ("basr\t%4,0", op);
9352 targetm.asm_out.internal_label (file, "L",
9353 CODE_LABEL_NUMBER (op[5]));
9354 }
9355
9356 /* Jump to target. */
9357 op[8] = gen_label_rtx ();
9358
9359 if (!flag_pic)
9360 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9361 else if (!nonlocal)
9362 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9363 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9364 else if (flag_pic == 1)
9365 {
9366 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9367 output_asm_insn ("l\t%4,%0(%4)", op);
9368 }
9369 else if (flag_pic == 2)
9370 {
9371 op[9] = gen_rtx_REG (Pmode, 0);
9372 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9373 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9374 output_asm_insn ("ar\t%4,%9", op);
9375 output_asm_insn ("l\t%4,0(%4)", op);
9376 }
9377
9378 output_asm_insn ("br\t%4", op);
9379
9380 /* Output literal pool. */
9381 output_asm_insn (".align\t4", op);
9382
9383 if (nonlocal && flag_pic == 2)
9384 output_asm_insn (".long\t%0", op);
9385 if (nonlocal)
9386 {
9387 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9388 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9389 }
9390
9391 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9392 if (!flag_pic)
9393 output_asm_insn (".long\t%0", op);
9394 else
9395 output_asm_insn (".long\t%0-%5", op);
9396
9397 if (op[6])
9398 {
9399 targetm.asm_out.internal_label (file, "L",
9400 CODE_LABEL_NUMBER (op[6]));
9401 output_asm_insn (".long\t%2", op);
9402 }
9403 if (op[7])
9404 {
9405 targetm.asm_out.internal_label (file, "L",
9406 CODE_LABEL_NUMBER (op[7]));
9407 output_asm_insn (".long\t%3", op);
9408 }
9409 }
9410 final_end_function ();
9411 }
9412
9413 static bool
9414 s390_valid_pointer_mode (enum machine_mode mode)
9415 {
9416 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9417 }
9418
9419 /* Checks whether the given CALL_EXPR would use a caller
9420 saved register. This is used to decide whether sibling call
9421 optimization could be performed on the respective function
9422 call. */
9423
9424 static bool
9425 s390_call_saved_register_used (tree call_expr)
9426 {
9427 CUMULATIVE_ARGS cum;
9428 tree parameter;
9429 enum machine_mode mode;
9430 tree type;
9431 rtx parm_rtx;
9432 int reg, i;
9433
9434 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9435
9436 for (i = 0; i < call_expr_nargs (call_expr); i++)
9437 {
9438 parameter = CALL_EXPR_ARG (call_expr, i);
9439 gcc_assert (parameter);
9440
9441 /* For an undeclared variable passed as parameter we will get
9442 an ERROR_MARK node here. */
9443 if (TREE_CODE (parameter) == ERROR_MARK)
9444 return true;
9445
9446 type = TREE_TYPE (parameter);
9447 gcc_assert (type);
9448
9449 mode = TYPE_MODE (type);
9450 gcc_assert (mode);
9451
9452 if (pass_by_reference (&cum, mode, type, true))
9453 {
9454 mode = Pmode;
9455 type = build_pointer_type (type);
9456 }
9457
9458 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9459
9460 s390_function_arg_advance (&cum, mode, type, 0);
9461
9462 if (!parm_rtx)
9463 continue;
9464
9465 if (REG_P (parm_rtx))
9466 {
9467 for (reg = 0;
9468 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9469 reg++)
9470 if (!call_used_regs[reg + REGNO (parm_rtx)])
9471 return true;
9472 }
9473
9474 if (GET_CODE (parm_rtx) == PARALLEL)
9475 {
9476 int i;
9477
9478 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9479 {
9480 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9481
9482 gcc_assert (REG_P (r));
9483
9484 for (reg = 0;
9485 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9486 reg++)
9487 if (!call_used_regs[reg + REGNO (r)])
9488 return true;
9489 }
9490 }
9491
9492 }
9493 return false;
9494 }
9495
9496 /* Return true if the given call expression can be
9497 turned into a sibling call.
9498 DECL holds the declaration of the function to be called whereas
9499 EXP is the call expression itself. */
9500
9501 static bool
9502 s390_function_ok_for_sibcall (tree decl, tree exp)
9503 {
9504 /* The TPF epilogue uses register 1. */
9505 if (TARGET_TPF_PROFILING)
9506 return false;
9507
9508 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9509 which would have to be restored before the sibcall. */
9510 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9511 return false;
9512
9513 /* Register 6 on s390 is available as an argument register but unfortunately
9514 "caller saved". This makes functions needing this register for arguments
9515 not suitable for sibcalls. */
9516 return !s390_call_saved_register_used (exp);
9517 }
9518
9519 /* Return the fixed registers used for condition codes. */
9520
9521 static bool
9522 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9523 {
9524 *p1 = CC_REGNUM;
9525 *p2 = INVALID_REGNUM;
9526
9527 return true;
9528 }
9529
9530 /* This function is used by the call expanders of the machine description.
9531 It emits the call insn itself together with the necessary operations
9532 to adjust the target address and returns the emitted insn.
9533 ADDR_LOCATION is the target address rtx
9534 TLS_CALL the location of the thread-local symbol
9535 RESULT_REG the register where the result of the call should be stored
9536 RETADDR_REG the register where the return address should be stored
9537 If this parameter is NULL_RTX the call is considered
9538 to be a sibling call. */
9539
9540 rtx
9541 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9542 rtx retaddr_reg)
9543 {
9544 bool plt_call = false;
9545 rtx insn;
9546 rtx call;
9547 rtx clobber;
9548 rtvec vec;
9549
9550 /* Direct function calls need special treatment. */
9551 if (GET_CODE (addr_location) == SYMBOL_REF)
9552 {
9553 /* When calling a global routine in PIC mode, we must
9554 replace the symbol itself with the PLT stub. */
9555 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9556 {
9557 if (retaddr_reg != NULL_RTX)
9558 {
9559 addr_location = gen_rtx_UNSPEC (Pmode,
9560 gen_rtvec (1, addr_location),
9561 UNSPEC_PLT);
9562 addr_location = gen_rtx_CONST (Pmode, addr_location);
9563 plt_call = true;
9564 }
9565 else
9566 /* For -fpic code the PLT entries might use r12 which is
9567 call-saved. Therefore we cannot do a sibcall when
9568 calling directly using a symbol ref. When reaching
9569 this point we decided (in s390_function_ok_for_sibcall)
9570 to do a sibcall for a function pointer but one of the
9571 optimizers was able to get rid of the function pointer
9572 by propagating the symbol ref into the call. This
9573 optimization is illegal for S/390 so we turn the direct
9574 call into a indirect call again. */
9575 addr_location = force_reg (Pmode, addr_location);
9576 }
9577
9578 /* Unless we can use the bras(l) insn, force the
9579 routine address into a register. */
9580 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9581 {
9582 if (flag_pic)
9583 addr_location = legitimize_pic_address (addr_location, 0);
9584 else
9585 addr_location = force_reg (Pmode, addr_location);
9586 }
9587 }
9588
9589 /* If it is already an indirect call or the code above moved the
9590 SYMBOL_REF to somewhere else make sure the address can be found in
9591 register 1. */
9592 if (retaddr_reg == NULL_RTX
9593 && GET_CODE (addr_location) != SYMBOL_REF
9594 && !plt_call)
9595 {
9596 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9597 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9598 }
9599
9600 addr_location = gen_rtx_MEM (QImode, addr_location);
9601 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9602
9603 if (result_reg != NULL_RTX)
9604 call = gen_rtx_SET (VOIDmode, result_reg, call);
9605
9606 if (retaddr_reg != NULL_RTX)
9607 {
9608 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9609
9610 if (tls_call != NULL_RTX)
9611 vec = gen_rtvec (3, call, clobber,
9612 gen_rtx_USE (VOIDmode, tls_call));
9613 else
9614 vec = gen_rtvec (2, call, clobber);
9615
9616 call = gen_rtx_PARALLEL (VOIDmode, vec);
9617 }
9618
9619 insn = emit_call_insn (call);
9620
9621 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9622 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9623 {
9624 /* s390_function_ok_for_sibcall should
9625 have denied sibcalls in this case. */
9626 gcc_assert (retaddr_reg != NULL_RTX);
9627
9628 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9629 }
9630 return insn;
9631 }
9632
9633 /* Implement CONDITIONAL_REGISTER_USAGE. */
9634
9635 void
9636 s390_conditional_register_usage (void)
9637 {
9638 int i;
9639
9640 if (flag_pic)
9641 {
9642 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9643 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9644 }
9645 if (TARGET_CPU_ZARCH)
9646 {
9647 fixed_regs[BASE_REGNUM] = 0;
9648 call_used_regs[BASE_REGNUM] = 0;
9649 fixed_regs[RETURN_REGNUM] = 0;
9650 call_used_regs[RETURN_REGNUM] = 0;
9651 }
9652 if (TARGET_64BIT)
9653 {
9654 for (i = 24; i < 32; i++)
9655 call_used_regs[i] = call_really_used_regs[i] = 0;
9656 }
9657 else
9658 {
9659 for (i = 18; i < 20; i++)
9660 call_used_regs[i] = call_really_used_regs[i] = 0;
9661 }
9662
9663 if (TARGET_SOFT_FLOAT)
9664 {
9665 for (i = 16; i < 32; i++)
9666 call_used_regs[i] = fixed_regs[i] = 1;
9667 }
9668 }
9669
9670 /* Corresponding function to eh_return expander. */
9671
9672 static GTY(()) rtx s390_tpf_eh_return_symbol;
9673 void
9674 s390_emit_tpf_eh_return (rtx target)
9675 {
9676 rtx insn, reg;
9677
9678 if (!s390_tpf_eh_return_symbol)
9679 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9680
9681 reg = gen_rtx_REG (Pmode, 2);
9682
9683 emit_move_insn (reg, target);
9684 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9685 gen_rtx_REG (Pmode, RETURN_REGNUM));
9686 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9687
9688 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9689 }
9690
9691 /* Rework the prologue/epilogue to avoid saving/restoring
9692 registers unnecessarily. */
9693
9694 static void
9695 s390_optimize_prologue (void)
9696 {
9697 rtx insn, new_insn, next_insn;
9698
9699 /* Do a final recompute of the frame-related data. */
9700
9701 s390_update_frame_layout ();
9702
9703 /* If all special registers are in fact used, there's nothing we
9704 can do, so no point in walking the insn list. */
9705
9706 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9707 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9708 && (TARGET_CPU_ZARCH
9709 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9710 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9711 return;
9712
9713 /* Search for prologue/epilogue insns and replace them. */
9714
9715 for (insn = get_insns (); insn; insn = next_insn)
9716 {
9717 int first, last, off;
9718 rtx set, base, offset;
9719
9720 next_insn = NEXT_INSN (insn);
9721
9722 if (GET_CODE (insn) != INSN)
9723 continue;
9724
9725 if (GET_CODE (PATTERN (insn)) == PARALLEL
9726 && store_multiple_operation (PATTERN (insn), VOIDmode))
9727 {
9728 set = XVECEXP (PATTERN (insn), 0, 0);
9729 first = REGNO (SET_SRC (set));
9730 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9731 offset = const0_rtx;
9732 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9733 off = INTVAL (offset);
9734
9735 if (GET_CODE (base) != REG || off < 0)
9736 continue;
9737 if (cfun_frame_layout.first_save_gpr != -1
9738 && (cfun_frame_layout.first_save_gpr < first
9739 || cfun_frame_layout.last_save_gpr > last))
9740 continue;
9741 if (REGNO (base) != STACK_POINTER_REGNUM
9742 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9743 continue;
9744 if (first > BASE_REGNUM || last < BASE_REGNUM)
9745 continue;
9746
9747 if (cfun_frame_layout.first_save_gpr != -1)
9748 {
9749 new_insn = save_gprs (base,
9750 off + (cfun_frame_layout.first_save_gpr
9751 - first) * UNITS_PER_LONG,
9752 cfun_frame_layout.first_save_gpr,
9753 cfun_frame_layout.last_save_gpr);
9754 new_insn = emit_insn_before (new_insn, insn);
9755 INSN_ADDRESSES_NEW (new_insn, -1);
9756 }
9757
9758 remove_insn (insn);
9759 continue;
9760 }
9761
9762 if (cfun_frame_layout.first_save_gpr == -1
9763 && GET_CODE (PATTERN (insn)) == SET
9764 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9765 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9766 || (!TARGET_CPU_ZARCH
9767 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9768 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9769 {
9770 set = PATTERN (insn);
9771 first = REGNO (SET_SRC (set));
9772 offset = const0_rtx;
9773 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9774 off = INTVAL (offset);
9775
9776 if (GET_CODE (base) != REG || off < 0)
9777 continue;
9778 if (REGNO (base) != STACK_POINTER_REGNUM
9779 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9780 continue;
9781
9782 remove_insn (insn);
9783 continue;
9784 }
9785
9786 if (GET_CODE (PATTERN (insn)) == PARALLEL
9787 && load_multiple_operation (PATTERN (insn), VOIDmode))
9788 {
9789 set = XVECEXP (PATTERN (insn), 0, 0);
9790 first = REGNO (SET_DEST (set));
9791 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9792 offset = const0_rtx;
9793 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9794 off = INTVAL (offset);
9795
9796 if (GET_CODE (base) != REG || off < 0)
9797 continue;
9798 if (cfun_frame_layout.first_restore_gpr != -1
9799 && (cfun_frame_layout.first_restore_gpr < first
9800 || cfun_frame_layout.last_restore_gpr > last))
9801 continue;
9802 if (REGNO (base) != STACK_POINTER_REGNUM
9803 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9804 continue;
9805 if (first > BASE_REGNUM || last < BASE_REGNUM)
9806 continue;
9807
9808 if (cfun_frame_layout.first_restore_gpr != -1)
9809 {
9810 new_insn = restore_gprs (base,
9811 off + (cfun_frame_layout.first_restore_gpr
9812 - first) * UNITS_PER_LONG,
9813 cfun_frame_layout.first_restore_gpr,
9814 cfun_frame_layout.last_restore_gpr);
9815 new_insn = emit_insn_before (new_insn, insn);
9816 INSN_ADDRESSES_NEW (new_insn, -1);
9817 }
9818
9819 remove_insn (insn);
9820 continue;
9821 }
9822
9823 if (cfun_frame_layout.first_restore_gpr == -1
9824 && GET_CODE (PATTERN (insn)) == SET
9825 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9826 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9827 || (!TARGET_CPU_ZARCH
9828 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9829 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9830 {
9831 set = PATTERN (insn);
9832 first = REGNO (SET_DEST (set));
9833 offset = const0_rtx;
9834 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9835 off = INTVAL (offset);
9836
9837 if (GET_CODE (base) != REG || off < 0)
9838 continue;
9839 if (REGNO (base) != STACK_POINTER_REGNUM
9840 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9841 continue;
9842
9843 remove_insn (insn);
9844 continue;
9845 }
9846 }
9847 }
9848
9849 /* On z10 the dynamic branch prediction must see the backward jump in
9850 a window of 384 bytes. If not it falls back to the static
9851 prediction. This function rearranges the loop backward branch in a
9852 way which makes the static prediction always correct. The function
9853 returns true if it added an instruction. */
9854 static bool
9855 s390_z10_fix_long_loop_prediction (rtx insn)
9856 {
9857 rtx set = single_set (insn);
9858 rtx code_label, label_ref, new_label;
9859 rtx uncond_jump;
9860 rtx cur_insn;
9861 rtx tmp;
9862 int distance;
9863
9864 /* This will exclude branch on count and branch on index patterns
9865 since these are correctly statically predicted. */
9866 if (!set
9867 || SET_DEST (set) != pc_rtx
9868 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9869 return false;
9870
9871 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9872 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9873
9874 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9875
9876 code_label = XEXP (label_ref, 0);
9877
9878 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9879 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9880 || (INSN_ADDRESSES (INSN_UID (insn))
9881 - INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE))
9882 return false;
9883
9884 for (distance = 0, cur_insn = PREV_INSN (insn);
9885 distance < Z10_PREDICT_DISTANCE - 6;
9886 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9887 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
9888 return false;
9889
9890 new_label = gen_label_rtx ();
9891 uncond_jump = emit_jump_insn_after (
9892 gen_rtx_SET (VOIDmode, pc_rtx,
9893 gen_rtx_LABEL_REF (VOIDmode, code_label)),
9894 insn);
9895 emit_label_after (new_label, uncond_jump);
9896
9897 tmp = XEXP (SET_SRC (set), 1);
9898 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
9899 XEXP (SET_SRC (set), 2) = tmp;
9900 INSN_CODE (insn) = -1;
9901
9902 XEXP (label_ref, 0) = new_label;
9903 JUMP_LABEL (insn) = new_label;
9904 JUMP_LABEL (uncond_jump) = code_label;
9905
9906 return true;
9907 }
9908
9909 /* Returns 1 if INSN reads the value of REG for purposes not related
9910 to addressing of memory, and 0 otherwise. */
9911 static int
9912 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9913 {
9914 return reg_referenced_p (reg, PATTERN (insn))
9915 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9916 }
9917
9918 /* Starting from INSN find_cond_jump looks downwards in the insn
9919 stream for a single jump insn which is the last user of the
9920 condition code set in INSN. */
9921 static rtx
9922 find_cond_jump (rtx insn)
9923 {
9924 for (; insn; insn = NEXT_INSN (insn))
9925 {
9926 rtx ite, cc;
9927
9928 if (LABEL_P (insn))
9929 break;
9930
9931 if (!JUMP_P (insn))
9932 {
9933 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9934 break;
9935 continue;
9936 }
9937
9938 /* This will be triggered by a return. */
9939 if (GET_CODE (PATTERN (insn)) != SET)
9940 break;
9941
9942 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9943 ite = SET_SRC (PATTERN (insn));
9944
9945 if (GET_CODE (ite) != IF_THEN_ELSE)
9946 break;
9947
9948 cc = XEXP (XEXP (ite, 0), 0);
9949 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9950 break;
9951
9952 if (find_reg_note (insn, REG_DEAD, cc))
9953 return insn;
9954 break;
9955 }
9956
9957 return NULL_RTX;
9958 }
9959
9960 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9961 the semantics does not change. If NULL_RTX is passed as COND the
9962 function tries to find the conditional jump starting with INSN. */
9963 static void
9964 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9965 {
9966 rtx tmp = *op0;
9967
9968 if (cond == NULL_RTX)
9969 {
9970 rtx jump = find_cond_jump (NEXT_INSN (insn));
9971 jump = jump ? single_set (jump) : NULL_RTX;
9972
9973 if (jump == NULL_RTX)
9974 return;
9975
9976 cond = XEXP (XEXP (jump, 1), 0);
9977 }
9978
9979 *op0 = *op1;
9980 *op1 = tmp;
9981 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9982 }
9983
9984 /* On z10, instructions of the compare-and-branch family have the
9985 property to access the register occurring as second operand with
9986 its bits complemented. If such a compare is grouped with a second
9987 instruction that accesses the same register non-complemented, and
9988 if that register's value is delivered via a bypass, then the
9989 pipeline recycles, thereby causing significant performance decline.
9990 This function locates such situations and exchanges the two
9991 operands of the compare. The function return true whenever it
9992 added an insn. */
9993 static bool
9994 s390_z10_optimize_cmp (rtx insn)
9995 {
9996 rtx prev_insn, next_insn;
9997 bool insn_added_p = false;
9998 rtx cond, *op0, *op1;
9999
10000 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10001 {
10002 /* Handle compare and branch and branch on count
10003 instructions. */
10004 rtx pattern = single_set (insn);
10005
10006 if (!pattern
10007 || SET_DEST (pattern) != pc_rtx
10008 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10009 return false;
10010
10011 cond = XEXP (SET_SRC (pattern), 0);
10012 op0 = &XEXP (cond, 0);
10013 op1 = &XEXP (cond, 1);
10014 }
10015 else if (GET_CODE (PATTERN (insn)) == SET)
10016 {
10017 rtx src, dest;
10018
10019 /* Handle normal compare instructions. */
10020 src = SET_SRC (PATTERN (insn));
10021 dest = SET_DEST (PATTERN (insn));
10022
10023 if (!REG_P (dest)
10024 || !CC_REGNO_P (REGNO (dest))
10025 || GET_CODE (src) != COMPARE)
10026 return false;
10027
10028 /* s390_swap_cmp will try to find the conditional
10029 jump when passing NULL_RTX as condition. */
10030 cond = NULL_RTX;
10031 op0 = &XEXP (src, 0);
10032 op1 = &XEXP (src, 1);
10033 }
10034 else
10035 return false;
10036
10037 if (!REG_P (*op0) || !REG_P (*op1))
10038 return false;
10039
10040 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10041 return false;
10042
10043 /* Swap the COMPARE arguments and its mask if there is a
10044 conflicting access in the previous insn. */
10045 prev_insn = prev_active_insn (insn);
10046 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10047 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10048 s390_swap_cmp (cond, op0, op1, insn);
10049
10050 /* Check if there is a conflict with the next insn. If there
10051 was no conflict with the previous insn, then swap the
10052 COMPARE arguments and its mask. If we already swapped
10053 the operands, or if swapping them would cause a conflict
10054 with the previous insn, issue a NOP after the COMPARE in
10055 order to separate the two instuctions. */
10056 next_insn = next_active_insn (insn);
10057 if (next_insn != NULL_RTX && INSN_P (next_insn)
10058 && s390_non_addr_reg_read_p (*op1, next_insn))
10059 {
10060 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10061 && s390_non_addr_reg_read_p (*op0, prev_insn))
10062 {
10063 if (REGNO (*op1) == 0)
10064 emit_insn_after (gen_nop1 (), insn);
10065 else
10066 emit_insn_after (gen_nop (), insn);
10067 insn_added_p = true;
10068 }
10069 else
10070 s390_swap_cmp (cond, op0, op1, insn);
10071 }
10072 return insn_added_p;
10073 }
10074
10075 /* Perform machine-dependent processing. */
10076
10077 static void
10078 s390_reorg (void)
10079 {
10080 bool pool_overflow = false;
10081
10082 /* Make sure all splits have been performed; splits after
10083 machine_dependent_reorg might confuse insn length counts. */
10084 split_all_insns_noflow ();
10085
10086 /* Install the main literal pool and the associated base
10087 register load insns.
10088
10089 In addition, there are two problematic situations we need
10090 to correct:
10091
10092 - the literal pool might be > 4096 bytes in size, so that
10093 some of its elements cannot be directly accessed
10094
10095 - a branch target might be > 64K away from the branch, so that
10096 it is not possible to use a PC-relative instruction.
10097
10098 To fix those, we split the single literal pool into multiple
10099 pool chunks, reloading the pool base register at various
10100 points throughout the function to ensure it always points to
10101 the pool chunk the following code expects, and / or replace
10102 PC-relative branches by absolute branches.
10103
10104 However, the two problems are interdependent: splitting the
10105 literal pool can move a branch further away from its target,
10106 causing the 64K limit to overflow, and on the other hand,
10107 replacing a PC-relative branch by an absolute branch means
10108 we need to put the branch target address into the literal
10109 pool, possibly causing it to overflow.
10110
10111 So, we loop trying to fix up both problems until we manage
10112 to satisfy both conditions at the same time. Note that the
10113 loop is guaranteed to terminate as every pass of the loop
10114 strictly decreases the total number of PC-relative branches
10115 in the function. (This is not completely true as there
10116 might be branch-over-pool insns introduced by chunkify_start.
10117 Those never need to be split however.) */
10118
10119 for (;;)
10120 {
10121 struct constant_pool *pool = NULL;
10122
10123 /* Collect the literal pool. */
10124 if (!pool_overflow)
10125 {
10126 pool = s390_mainpool_start ();
10127 if (!pool)
10128 pool_overflow = true;
10129 }
10130
10131 /* If literal pool overflowed, start to chunkify it. */
10132 if (pool_overflow)
10133 pool = s390_chunkify_start ();
10134
10135 /* Split out-of-range branches. If this has created new
10136 literal pool entries, cancel current chunk list and
10137 recompute it. zSeries machines have large branch
10138 instructions, so we never need to split a branch. */
10139 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10140 {
10141 if (pool_overflow)
10142 s390_chunkify_cancel (pool);
10143 else
10144 s390_mainpool_cancel (pool);
10145
10146 continue;
10147 }
10148
10149 /* If we made it up to here, both conditions are satisfied.
10150 Finish up literal pool related changes. */
10151 if (pool_overflow)
10152 s390_chunkify_finish (pool);
10153 else
10154 s390_mainpool_finish (pool);
10155
10156 /* We're done splitting branches. */
10157 cfun->machine->split_branches_pending_p = false;
10158 break;
10159 }
10160
10161 /* Generate out-of-pool execute target insns. */
10162 if (TARGET_CPU_ZARCH)
10163 {
10164 rtx insn, label, target;
10165
10166 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10167 {
10168 label = s390_execute_label (insn);
10169 if (!label)
10170 continue;
10171
10172 gcc_assert (label != const0_rtx);
10173
10174 target = emit_label (XEXP (label, 0));
10175 INSN_ADDRESSES_NEW (target, -1);
10176
10177 target = emit_insn (s390_execute_target (insn));
10178 INSN_ADDRESSES_NEW (target, -1);
10179 }
10180 }
10181
10182 /* Try to optimize prologue and epilogue further. */
10183 s390_optimize_prologue ();
10184
10185 /* Walk over the insns and do some z10 specific changes. */
10186 if (s390_tune == PROCESSOR_2097_Z10)
10187 {
10188 rtx insn;
10189 bool insn_added_p = false;
10190
10191 /* The insn lengths and addresses have to be up to date for the
10192 following manipulations. */
10193 shorten_branches (get_insns ());
10194
10195 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10196 {
10197 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10198 continue;
10199
10200 if (JUMP_P (insn))
10201 insn_added_p |= s390_z10_fix_long_loop_prediction (insn);
10202
10203 if (GET_CODE (PATTERN (insn)) == PARALLEL
10204 || GET_CODE (PATTERN (insn)) == SET)
10205 insn_added_p |= s390_z10_optimize_cmp (insn);
10206 }
10207
10208 /* Adjust branches if we added new instructions. */
10209 if (insn_added_p)
10210 shorten_branches (get_insns ());
10211 }
10212 }
10213
10214 /* Return true if INSN is a fp load insn writing register REGNO. */
10215 static inline bool
10216 s390_fpload_toreg (rtx insn, unsigned int regno)
10217 {
10218 rtx set;
10219 enum attr_type flag = s390_safe_attr_type (insn);
10220
10221 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10222 return false;
10223
10224 set = single_set (insn);
10225
10226 if (set == NULL_RTX)
10227 return false;
10228
10229 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10230 return false;
10231
10232 if (REGNO (SET_DEST (set)) != regno)
10233 return false;
10234
10235 return true;
10236 }
10237
10238 /* This value describes the distance to be avoided between an
10239 aritmetic fp instruction and an fp load writing the same register.
10240 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10241 fine but the exact value has to be avoided. Otherwise the FP
10242 pipeline will throw an exception causing a major penalty. */
10243 #define Z10_EARLYLOAD_DISTANCE 7
10244
10245 /* Rearrange the ready list in order to avoid the situation described
10246 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10247 moved to the very end of the ready list. */
10248 static void
10249 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10250 {
10251 unsigned int regno;
10252 int nready = *nready_p;
10253 rtx tmp;
10254 int i;
10255 rtx insn;
10256 rtx set;
10257 enum attr_type flag;
10258 int distance;
10259
10260 /* Skip DISTANCE - 1 active insns. */
10261 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10262 distance > 0 && insn != NULL_RTX;
10263 distance--, insn = prev_active_insn (insn))
10264 if (CALL_P (insn) || JUMP_P (insn))
10265 return;
10266
10267 if (insn == NULL_RTX)
10268 return;
10269
10270 set = single_set (insn);
10271
10272 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10273 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10274 return;
10275
10276 flag = s390_safe_attr_type (insn);
10277
10278 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10279 return;
10280
10281 regno = REGNO (SET_DEST (set));
10282 i = nready - 1;
10283
10284 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10285 i--;
10286
10287 if (!i)
10288 return;
10289
10290 tmp = ready[i];
10291 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10292 ready[0] = tmp;
10293 }
10294
10295 /* This function is called via hook TARGET_SCHED_REORDER before
10296 issueing one insn from list READY which contains *NREADYP entries.
10297 For target z10 it reorders load instructions to avoid early load
10298 conflicts in the floating point pipeline */
10299 static int
10300 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10301 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10302 {
10303 if (s390_tune == PROCESSOR_2097_Z10)
10304 if (reload_completed && *nreadyp > 1)
10305 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10306
10307 return s390_issue_rate ();
10308 }
10309
10310 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10311 the scheduler has issued INSN. It stores the last issued insn into
10312 last_scheduled_insn in order to make it available for
10313 s390_sched_reorder. */
10314 static int
10315 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10316 int verbose ATTRIBUTE_UNUSED,
10317 rtx insn, int more)
10318 {
10319 last_scheduled_insn = insn;
10320
10321 if (GET_CODE (PATTERN (insn)) != USE
10322 && GET_CODE (PATTERN (insn)) != CLOBBER)
10323 return more - 1;
10324 else
10325 return more;
10326 }
10327
10328 static void
10329 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10330 int verbose ATTRIBUTE_UNUSED,
10331 int max_ready ATTRIBUTE_UNUSED)
10332 {
10333 last_scheduled_insn = NULL_RTX;
10334 }
10335
10336 /* This function checks the whole of insn X for memory references. The
10337 function always returns zero because the framework it is called
10338 from would stop recursively analyzing the insn upon a return value
10339 other than zero. The real result of this function is updating
10340 counter variable MEM_COUNT. */
10341 static int
10342 check_dpu (rtx *x, unsigned *mem_count)
10343 {
10344 if (*x != NULL_RTX && MEM_P (*x))
10345 (*mem_count)++;
10346 return 0;
10347 }
10348
10349 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10350 a new number struct loop *loop should be unrolled if tuned for the z10
10351 cpu. The loop is analyzed for memory accesses by calling check_dpu for
10352 each rtx of the loop. Depending on the loop_depth and the amount of
10353 memory accesses a new number <=nunroll is returned to improve the
10354 behaviour of the hardware prefetch unit. */
10355 static unsigned
10356 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10357 {
10358 basic_block *bbs;
10359 rtx insn;
10360 unsigned i;
10361 unsigned mem_count = 0;
10362
10363 /* Only z10 needs special handling. */
10364 if (s390_tune != PROCESSOR_2097_Z10)
10365 return nunroll;
10366
10367 /* Count the number of memory references within the loop body. */
10368 bbs = get_loop_body (loop);
10369 for (i = 0; i < loop->num_nodes; i++)
10370 {
10371 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10372 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10373 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10374 }
10375 free (bbs);
10376
10377 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10378 if (mem_count == 0)
10379 return nunroll;
10380
10381 switch (loop_depth(loop))
10382 {
10383 case 1:
10384 return MIN (nunroll, 28 / mem_count);
10385 case 2:
10386 return MIN (nunroll, 22 / mem_count);
10387 default:
10388 return MIN (nunroll, 16 / mem_count);
10389 }
10390 }
10391
10392 /* Initialize GCC target structure. */
10393
10394 #undef TARGET_ASM_ALIGNED_HI_OP
10395 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10396 #undef TARGET_ASM_ALIGNED_DI_OP
10397 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10398 #undef TARGET_ASM_INTEGER
10399 #define TARGET_ASM_INTEGER s390_assemble_integer
10400
10401 #undef TARGET_ASM_OPEN_PAREN
10402 #define TARGET_ASM_OPEN_PAREN ""
10403
10404 #undef TARGET_ASM_CLOSE_PAREN
10405 #define TARGET_ASM_CLOSE_PAREN ""
10406
10407 #undef TARGET_DEFAULT_TARGET_FLAGS
10408 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10409
10410 #undef TARGET_HANDLE_OPTION
10411 #define TARGET_HANDLE_OPTION s390_handle_option
10412
10413 #undef TARGET_ENCODE_SECTION_INFO
10414 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10415
10416 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10417 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10418
10419 #ifdef HAVE_AS_TLS
10420 #undef TARGET_HAVE_TLS
10421 #define TARGET_HAVE_TLS true
10422 #endif
10423 #undef TARGET_CANNOT_FORCE_CONST_MEM
10424 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10425
10426 #undef TARGET_DELEGITIMIZE_ADDRESS
10427 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10428
10429 #undef TARGET_LEGITIMIZE_ADDRESS
10430 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10431
10432 #undef TARGET_RETURN_IN_MEMORY
10433 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10434
10435 #undef TARGET_INIT_BUILTINS
10436 #define TARGET_INIT_BUILTINS s390_init_builtins
10437 #undef TARGET_EXPAND_BUILTIN
10438 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10439
10440 #undef TARGET_ASM_OUTPUT_MI_THUNK
10441 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10442 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10443 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10444
10445 #undef TARGET_SCHED_ADJUST_PRIORITY
10446 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10447 #undef TARGET_SCHED_ISSUE_RATE
10448 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10449 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10450 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10451
10452 #undef TARGET_SCHED_VARIABLE_ISSUE
10453 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10454 #undef TARGET_SCHED_REORDER
10455 #define TARGET_SCHED_REORDER s390_sched_reorder
10456 #undef TARGET_SCHED_INIT
10457 #define TARGET_SCHED_INIT s390_sched_init
10458
10459 #undef TARGET_CANNOT_COPY_INSN_P
10460 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10461 #undef TARGET_RTX_COSTS
10462 #define TARGET_RTX_COSTS s390_rtx_costs
10463 #undef TARGET_ADDRESS_COST
10464 #define TARGET_ADDRESS_COST s390_address_cost
10465
10466 #undef TARGET_MACHINE_DEPENDENT_REORG
10467 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10468
10469 #undef TARGET_VALID_POINTER_MODE
10470 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10471
10472 #undef TARGET_BUILD_BUILTIN_VA_LIST
10473 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10474 #undef TARGET_EXPAND_BUILTIN_VA_START
10475 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10476 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10477 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10478
10479 #undef TARGET_PROMOTE_FUNCTION_MODE
10480 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10481 #undef TARGET_PASS_BY_REFERENCE
10482 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10483
10484 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10485 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10486
10487 #undef TARGET_FIXED_CONDITION_CODE_REGS
10488 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10489
10490 #undef TARGET_CC_MODES_COMPATIBLE
10491 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10492
10493 #undef TARGET_INVALID_WITHIN_DOLOOP
10494 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10495
10496 #ifdef HAVE_AS_TLS
10497 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10498 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10499 #endif
10500
10501 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10502 #undef TARGET_MANGLE_TYPE
10503 #define TARGET_MANGLE_TYPE s390_mangle_type
10504 #endif
10505
10506 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10507 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10508
10509 #undef TARGET_SECONDARY_RELOAD
10510 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10511
10512 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10513 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10514
10515 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10516 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10517
10518 #undef TARGET_LEGITIMATE_ADDRESS_P
10519 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10520
10521 #undef TARGET_CAN_ELIMINATE
10522 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10523
10524 #undef TARGET_LOOP_UNROLL_ADJUST
10525 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10526
10527 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10528 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10529 #undef TARGET_TRAMPOLINE_INIT
10530 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10531
10532 #undef TARGET_UNWIND_WORD_MODE
10533 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10534
10535 struct gcc_target targetm = TARGET_INITIALIZER;
10536
10537 #include "gt-s390.h"