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rtl.h (assign_stack_temp, [...]): Remove 'keep' argument.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "integrate.h"
46 #include "ggc.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "debug.h"
50 #include "langhooks.h"
51 #include "optabs.h"
52 #include "gimple.h"
53 #include "df.h"
54 #include "params.h"
55 #include "cfgloop.h"
56 #include "opts.h"
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 static const
226 struct processor_costs z196_cost =
227 {
228 COSTS_N_INSNS (7), /* M */
229 COSTS_N_INSNS (5), /* MGHI */
230 COSTS_N_INSNS (5), /* MH */
231 COSTS_N_INSNS (5), /* MHI */
232 COSTS_N_INSNS (7), /* ML */
233 COSTS_N_INSNS (7), /* MR */
234 COSTS_N_INSNS (6), /* MS */
235 COSTS_N_INSNS (8), /* MSG */
236 COSTS_N_INSNS (6), /* MSGF */
237 COSTS_N_INSNS (6), /* MSGFR */
238 COSTS_N_INSNS (8), /* MSGR */
239 COSTS_N_INSNS (6), /* MSR */
240 COSTS_N_INSNS (1) , /* multiplication in DFmode */
241 COSTS_N_INSNS (40), /* MXBR B+40 */
242 COSTS_N_INSNS (100), /* SQXBR B+100 */
243 COSTS_N_INSNS (42), /* SQDBR B+42 */
244 COSTS_N_INSNS (28), /* SQEBR B+28 */
245 COSTS_N_INSNS (1), /* MADBR B */
246 COSTS_N_INSNS (1), /* MAEBR B */
247 COSTS_N_INSNS (101), /* DXBR B+101 */
248 COSTS_N_INSNS (29), /* DDBR */
249 COSTS_N_INSNS (22), /* DEBR */
250 COSTS_N_INSNS (160), /* DLGR cracked */
251 COSTS_N_INSNS (160), /* DLR cracked */
252 COSTS_N_INSNS (160), /* DR expanded */
253 COSTS_N_INSNS (160), /* DSGFR cracked */
254 COSTS_N_INSNS (160), /* DSGR cracked */
255 };
256
257 extern int reload_completed;
258
259 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
260 static rtx last_scheduled_insn;
261
262 /* Structure used to hold the components of a S/390 memory
263 address. A legitimate address on S/390 is of the general
264 form
265 base + index + displacement
266 where any of the components is optional.
267
268 base and index are registers of the class ADDR_REGS,
269 displacement is an unsigned 12-bit immediate constant. */
270
271 struct s390_address
272 {
273 rtx base;
274 rtx indx;
275 rtx disp;
276 bool pointer;
277 bool literal_pool;
278 };
279
280 /* The following structure is embedded in the machine
281 specific part of struct function. */
282
283 struct GTY (()) s390_frame_layout
284 {
285 /* Offset within stack frame. */
286 HOST_WIDE_INT gprs_offset;
287 HOST_WIDE_INT f0_offset;
288 HOST_WIDE_INT f4_offset;
289 HOST_WIDE_INT f8_offset;
290 HOST_WIDE_INT backchain_offset;
291
292 /* Number of first and last gpr where slots in the register
293 save area are reserved for. */
294 int first_save_gpr_slot;
295 int last_save_gpr_slot;
296
297 /* Number of first and last gpr to be saved, restored. */
298 int first_save_gpr;
299 int first_restore_gpr;
300 int last_save_gpr;
301 int last_restore_gpr;
302
303 /* Bits standing for floating point registers. Set, if the
304 respective register has to be saved. Starting with reg 16 (f0)
305 at the rightmost bit.
306 Bit 15 - 8 7 6 5 4 3 2 1 0
307 fpr 15 - 8 7 5 3 1 6 4 2 0
308 reg 31 - 24 23 22 21 20 19 18 17 16 */
309 unsigned int fpr_bitmap;
310
311 /* Number of floating point registers f8-f15 which must be saved. */
312 int high_fprs;
313
314 /* Set if return address needs to be saved.
315 This flag is set by s390_return_addr_rtx if it could not use
316 the initial value of r14 and therefore depends on r14 saved
317 to the stack. */
318 bool save_return_addr_p;
319
320 /* Size of stack frame. */
321 HOST_WIDE_INT frame_size;
322 };
323
324 /* Define the structure for the machine field in struct function. */
325
326 struct GTY(()) machine_function
327 {
328 struct s390_frame_layout frame_layout;
329
330 /* Literal pool base register. */
331 rtx base_reg;
332
333 /* True if we may need to perform branch splitting. */
334 bool split_branches_pending_p;
335
336 /* Some local-dynamic TLS symbol name. */
337 const char *some_ld_name;
338
339 bool has_landing_pad_p;
340 };
341
342 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
343
344 #define cfun_frame_layout (cfun->machine->frame_layout)
345 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
346 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
347 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
348 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
349 (1 << (BITNUM)))
350 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
351 (1 << (BITNUM))))
352
353 /* Number of GPRs and FPRs used for argument passing. */
354 #define GP_ARG_NUM_REG 5
355 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
356
357 /* A couple of shortcuts. */
358 #define CONST_OK_FOR_J(x) \
359 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
360 #define CONST_OK_FOR_K(x) \
361 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
362 #define CONST_OK_FOR_Os(x) \
363 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
364 #define CONST_OK_FOR_Op(x) \
365 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
366 #define CONST_OK_FOR_On(x) \
367 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
368
369 #define REGNO_PAIR_OK(REGNO, MODE) \
370 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
371
372 /* That's the read ahead of the dynamic branch prediction unit in
373 bytes on a z10 (or higher) CPU. */
374 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
375
376 /* Return the alignment for LABEL. We default to the -falign-labels
377 value except for the literal pool base label. */
378 int
379 s390_label_align (rtx label)
380 {
381 rtx prev_insn = prev_active_insn (label);
382
383 if (prev_insn == NULL_RTX)
384 goto old;
385
386 prev_insn = single_set (prev_insn);
387
388 if (prev_insn == NULL_RTX)
389 goto old;
390
391 prev_insn = SET_SRC (prev_insn);
392
393 /* Don't align literal pool base labels. */
394 if (GET_CODE (prev_insn) == UNSPEC
395 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
396 return 0;
397
398 old:
399 return align_labels_log;
400 }
401
402 static enum machine_mode
403 s390_libgcc_cmp_return_mode (void)
404 {
405 return TARGET_64BIT ? DImode : SImode;
406 }
407
408 static enum machine_mode
409 s390_libgcc_shift_count_mode (void)
410 {
411 return TARGET_64BIT ? DImode : SImode;
412 }
413
414 static enum machine_mode
415 s390_unwind_word_mode (void)
416 {
417 return TARGET_64BIT ? DImode : SImode;
418 }
419
420 /* Return true if the back end supports mode MODE. */
421 static bool
422 s390_scalar_mode_supported_p (enum machine_mode mode)
423 {
424 /* In contrast to the default implementation reject TImode constants on 31bit
425 TARGET_ZARCH for ABI compliance. */
426 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
427 return false;
428
429 if (DECIMAL_FLOAT_MODE_P (mode))
430 return default_decimal_float_supported_p ();
431
432 return default_scalar_mode_supported_p (mode);
433 }
434
435 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
436
437 void
438 s390_set_has_landing_pad_p (bool value)
439 {
440 cfun->machine->has_landing_pad_p = value;
441 }
442
443 /* If two condition code modes are compatible, return a condition code
444 mode which is compatible with both. Otherwise, return
445 VOIDmode. */
446
447 static enum machine_mode
448 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
449 {
450 if (m1 == m2)
451 return m1;
452
453 switch (m1)
454 {
455 case CCZmode:
456 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
457 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
458 return m2;
459 return VOIDmode;
460
461 case CCSmode:
462 case CCUmode:
463 case CCTmode:
464 case CCSRmode:
465 case CCURmode:
466 case CCZ1mode:
467 if (m2 == CCZmode)
468 return m1;
469
470 return VOIDmode;
471
472 default:
473 return VOIDmode;
474 }
475 return VOIDmode;
476 }
477
478 /* Return true if SET either doesn't set the CC register, or else
479 the source and destination have matching CC modes and that
480 CC mode is at least as constrained as REQ_MODE. */
481
482 static bool
483 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
484 {
485 enum machine_mode set_mode;
486
487 gcc_assert (GET_CODE (set) == SET);
488
489 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
490 return 1;
491
492 set_mode = GET_MODE (SET_DEST (set));
493 switch (set_mode)
494 {
495 case CCSmode:
496 case CCSRmode:
497 case CCUmode:
498 case CCURmode:
499 case CCLmode:
500 case CCL1mode:
501 case CCL2mode:
502 case CCL3mode:
503 case CCT1mode:
504 case CCT2mode:
505 case CCT3mode:
506 if (req_mode != set_mode)
507 return 0;
508 break;
509
510 case CCZmode:
511 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
512 && req_mode != CCSRmode && req_mode != CCURmode)
513 return 0;
514 break;
515
516 case CCAPmode:
517 case CCANmode:
518 if (req_mode != CCAmode)
519 return 0;
520 break;
521
522 default:
523 gcc_unreachable ();
524 }
525
526 return (GET_MODE (SET_SRC (set)) == set_mode);
527 }
528
529 /* Return true if every SET in INSN that sets the CC register
530 has source and destination with matching CC modes and that
531 CC mode is at least as constrained as REQ_MODE.
532 If REQ_MODE is VOIDmode, always return false. */
533
534 bool
535 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
536 {
537 int i;
538
539 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
540 if (req_mode == VOIDmode)
541 return false;
542
543 if (GET_CODE (PATTERN (insn)) == SET)
544 return s390_match_ccmode_set (PATTERN (insn), req_mode);
545
546 if (GET_CODE (PATTERN (insn)) == PARALLEL)
547 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
548 {
549 rtx set = XVECEXP (PATTERN (insn), 0, i);
550 if (GET_CODE (set) == SET)
551 if (!s390_match_ccmode_set (set, req_mode))
552 return false;
553 }
554
555 return true;
556 }
557
558 /* If a test-under-mask instruction can be used to implement
559 (compare (and ... OP1) OP2), return the CC mode required
560 to do that. Otherwise, return VOIDmode.
561 MIXED is true if the instruction can distinguish between
562 CC1 and CC2 for mixed selected bits (TMxx), it is false
563 if the instruction cannot (TM). */
564
565 enum machine_mode
566 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
567 {
568 int bit0, bit1;
569
570 /* ??? Fixme: should work on CONST_DOUBLE as well. */
571 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
572 return VOIDmode;
573
574 /* Selected bits all zero: CC0.
575 e.g.: int a; if ((a & (16 + 128)) == 0) */
576 if (INTVAL (op2) == 0)
577 return CCTmode;
578
579 /* Selected bits all one: CC3.
580 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
581 if (INTVAL (op2) == INTVAL (op1))
582 return CCT3mode;
583
584 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
585 int a;
586 if ((a & (16 + 128)) == 16) -> CCT1
587 if ((a & (16 + 128)) == 128) -> CCT2 */
588 if (mixed)
589 {
590 bit1 = exact_log2 (INTVAL (op2));
591 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
592 if (bit0 != -1 && bit1 != -1)
593 return bit0 > bit1 ? CCT1mode : CCT2mode;
594 }
595
596 return VOIDmode;
597 }
598
599 /* Given a comparison code OP (EQ, NE, etc.) and the operands
600 OP0 and OP1 of a COMPARE, return the mode to be used for the
601 comparison. */
602
603 enum machine_mode
604 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
605 {
606 switch (code)
607 {
608 case EQ:
609 case NE:
610 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
611 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
612 return CCAPmode;
613 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
614 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
615 return CCAPmode;
616 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
617 || GET_CODE (op1) == NEG)
618 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
619 return CCLmode;
620
621 if (GET_CODE (op0) == AND)
622 {
623 /* Check whether we can potentially do it via TM. */
624 enum machine_mode ccmode;
625 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
626 if (ccmode != VOIDmode)
627 {
628 /* Relax CCTmode to CCZmode to allow fall-back to AND
629 if that turns out to be beneficial. */
630 return ccmode == CCTmode ? CCZmode : ccmode;
631 }
632 }
633
634 if (register_operand (op0, HImode)
635 && GET_CODE (op1) == CONST_INT
636 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
637 return CCT3mode;
638 if (register_operand (op0, QImode)
639 && GET_CODE (op1) == CONST_INT
640 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
641 return CCT3mode;
642
643 return CCZmode;
644
645 case LE:
646 case LT:
647 case GE:
648 case GT:
649 /* The only overflow condition of NEG and ABS happens when
650 -INT_MAX is used as parameter, which stays negative. So
651 we have an overflow from a positive value to a negative.
652 Using CCAP mode the resulting cc can be used for comparisons. */
653 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
654 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
655 return CCAPmode;
656
657 /* If constants are involved in an add instruction it is possible to use
658 the resulting cc for comparisons with zero. Knowing the sign of the
659 constant the overflow behavior gets predictable. e.g.:
660 int a, b; if ((b = a + c) > 0)
661 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
662 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
663 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
664 {
665 if (INTVAL (XEXP((op0), 1)) < 0)
666 return CCANmode;
667 else
668 return CCAPmode;
669 }
670 /* Fall through. */
671 case UNORDERED:
672 case ORDERED:
673 case UNEQ:
674 case UNLE:
675 case UNLT:
676 case UNGE:
677 case UNGT:
678 case LTGT:
679 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
680 && GET_CODE (op1) != CONST_INT)
681 return CCSRmode;
682 return CCSmode;
683
684 case LTU:
685 case GEU:
686 if (GET_CODE (op0) == PLUS
687 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
688 return CCL1mode;
689
690 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
691 && GET_CODE (op1) != CONST_INT)
692 return CCURmode;
693 return CCUmode;
694
695 case LEU:
696 case GTU:
697 if (GET_CODE (op0) == MINUS
698 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
699 return CCL2mode;
700
701 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
702 && GET_CODE (op1) != CONST_INT)
703 return CCURmode;
704 return CCUmode;
705
706 default:
707 gcc_unreachable ();
708 }
709 }
710
711 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
712 that we can implement more efficiently. */
713
714 void
715 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
716 {
717 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
718 if ((*code == EQ || *code == NE)
719 && *op1 == const0_rtx
720 && GET_CODE (*op0) == ZERO_EXTRACT
721 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
722 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
723 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
724 {
725 rtx inner = XEXP (*op0, 0);
726 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
727 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
728 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
729
730 if (len > 0 && len < modesize
731 && pos >= 0 && pos + len <= modesize
732 && modesize <= HOST_BITS_PER_WIDE_INT)
733 {
734 unsigned HOST_WIDE_INT block;
735 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
736 block <<= modesize - pos - len;
737
738 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
739 gen_int_mode (block, GET_MODE (inner)));
740 }
741 }
742
743 /* Narrow AND of memory against immediate to enable TM. */
744 if ((*code == EQ || *code == NE)
745 && *op1 == const0_rtx
746 && GET_CODE (*op0) == AND
747 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
748 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
749 {
750 rtx inner = XEXP (*op0, 0);
751 rtx mask = XEXP (*op0, 1);
752
753 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
754 if (GET_CODE (inner) == SUBREG
755 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
756 && (GET_MODE_SIZE (GET_MODE (inner))
757 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
758 && ((INTVAL (mask)
759 & GET_MODE_MASK (GET_MODE (inner))
760 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
761 == 0))
762 inner = SUBREG_REG (inner);
763
764 /* Do not change volatile MEMs. */
765 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
766 {
767 int part = s390_single_part (XEXP (*op0, 1),
768 GET_MODE (inner), QImode, 0);
769 if (part >= 0)
770 {
771 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
772 inner = adjust_address_nv (inner, QImode, part);
773 *op0 = gen_rtx_AND (QImode, inner, mask);
774 }
775 }
776 }
777
778 /* Narrow comparisons against 0xffff to HImode if possible. */
779 if ((*code == EQ || *code == NE)
780 && GET_CODE (*op1) == CONST_INT
781 && INTVAL (*op1) == 0xffff
782 && SCALAR_INT_MODE_P (GET_MODE (*op0))
783 && (nonzero_bits (*op0, GET_MODE (*op0))
784 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
785 {
786 *op0 = gen_lowpart (HImode, *op0);
787 *op1 = constm1_rtx;
788 }
789
790 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
791 if (GET_CODE (*op0) == UNSPEC
792 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
793 && XVECLEN (*op0, 0) == 1
794 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
795 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
796 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
797 && *op1 == const0_rtx)
798 {
799 enum rtx_code new_code = UNKNOWN;
800 switch (*code)
801 {
802 case EQ: new_code = EQ; break;
803 case NE: new_code = NE; break;
804 case LT: new_code = GTU; break;
805 case GT: new_code = LTU; break;
806 case LE: new_code = GEU; break;
807 case GE: new_code = LEU; break;
808 default: break;
809 }
810
811 if (new_code != UNKNOWN)
812 {
813 *op0 = XVECEXP (*op0, 0, 0);
814 *code = new_code;
815 }
816 }
817
818 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
819 if (GET_CODE (*op0) == UNSPEC
820 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
821 && XVECLEN (*op0, 0) == 1
822 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
823 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
824 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
825 && *op1 == const0_rtx)
826 {
827 enum rtx_code new_code = UNKNOWN;
828 switch (*code)
829 {
830 case EQ: new_code = EQ; break;
831 case NE: new_code = NE; break;
832 default: break;
833 }
834
835 if (new_code != UNKNOWN)
836 {
837 *op0 = XVECEXP (*op0, 0, 0);
838 *code = new_code;
839 }
840 }
841
842 /* Simplify cascaded EQ, NE with const0_rtx. */
843 if ((*code == NE || *code == EQ)
844 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
845 && GET_MODE (*op0) == SImode
846 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
847 && REG_P (XEXP (*op0, 0))
848 && XEXP (*op0, 1) == const0_rtx
849 && *op1 == const0_rtx)
850 {
851 if ((*code == EQ && GET_CODE (*op0) == NE)
852 || (*code == NE && GET_CODE (*op0) == EQ))
853 *code = EQ;
854 else
855 *code = NE;
856 *op0 = XEXP (*op0, 0);
857 }
858
859 /* Prefer register over memory as first operand. */
860 if (MEM_P (*op0) && REG_P (*op1))
861 {
862 rtx tem = *op0; *op0 = *op1; *op1 = tem;
863 *code = swap_condition (*code);
864 }
865 }
866
867 /* Emit a compare instruction suitable to implement the comparison
868 OP0 CODE OP1. Return the correct condition RTL to be placed in
869 the IF_THEN_ELSE of the conditional branch testing the result. */
870
871 rtx
872 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
873 {
874 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
875 rtx cc;
876
877 /* Do not output a redundant compare instruction if a compare_and_swap
878 pattern already computed the result and the machine modes are compatible. */
879 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
880 {
881 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
882 == GET_MODE (op0));
883 cc = op0;
884 }
885 else
886 {
887 cc = gen_rtx_REG (mode, CC_REGNUM);
888 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
889 }
890
891 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
892 }
893
894 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
895 matches CMP.
896 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
897 conditional branch testing the result. */
898
899 static rtx
900 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
901 {
902 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
903 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
904 }
905
906 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
907 unconditional jump, else a conditional jump under condition COND. */
908
909 void
910 s390_emit_jump (rtx target, rtx cond)
911 {
912 rtx insn;
913
914 target = gen_rtx_LABEL_REF (VOIDmode, target);
915 if (cond)
916 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
917
918 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
919 emit_jump_insn (insn);
920 }
921
922 /* Return branch condition mask to implement a branch
923 specified by CODE. Return -1 for invalid comparisons. */
924
925 int
926 s390_branch_condition_mask (rtx code)
927 {
928 const int CC0 = 1 << 3;
929 const int CC1 = 1 << 2;
930 const int CC2 = 1 << 1;
931 const int CC3 = 1 << 0;
932
933 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
934 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
935 gcc_assert (XEXP (code, 1) == const0_rtx);
936
937 switch (GET_MODE (XEXP (code, 0)))
938 {
939 case CCZmode:
940 case CCZ1mode:
941 switch (GET_CODE (code))
942 {
943 case EQ: return CC0;
944 case NE: return CC1 | CC2 | CC3;
945 default: return -1;
946 }
947 break;
948
949 case CCT1mode:
950 switch (GET_CODE (code))
951 {
952 case EQ: return CC1;
953 case NE: return CC0 | CC2 | CC3;
954 default: return -1;
955 }
956 break;
957
958 case CCT2mode:
959 switch (GET_CODE (code))
960 {
961 case EQ: return CC2;
962 case NE: return CC0 | CC1 | CC3;
963 default: return -1;
964 }
965 break;
966
967 case CCT3mode:
968 switch (GET_CODE (code))
969 {
970 case EQ: return CC3;
971 case NE: return CC0 | CC1 | CC2;
972 default: return -1;
973 }
974 break;
975
976 case CCLmode:
977 switch (GET_CODE (code))
978 {
979 case EQ: return CC0 | CC2;
980 case NE: return CC1 | CC3;
981 default: return -1;
982 }
983 break;
984
985 case CCL1mode:
986 switch (GET_CODE (code))
987 {
988 case LTU: return CC2 | CC3; /* carry */
989 case GEU: return CC0 | CC1; /* no carry */
990 default: return -1;
991 }
992 break;
993
994 case CCL2mode:
995 switch (GET_CODE (code))
996 {
997 case GTU: return CC0 | CC1; /* borrow */
998 case LEU: return CC2 | CC3; /* no borrow */
999 default: return -1;
1000 }
1001 break;
1002
1003 case CCL3mode:
1004 switch (GET_CODE (code))
1005 {
1006 case EQ: return CC0 | CC2;
1007 case NE: return CC1 | CC3;
1008 case LTU: return CC1;
1009 case GTU: return CC3;
1010 case LEU: return CC1 | CC2;
1011 case GEU: return CC2 | CC3;
1012 default: return -1;
1013 }
1014
1015 case CCUmode:
1016 switch (GET_CODE (code))
1017 {
1018 case EQ: return CC0;
1019 case NE: return CC1 | CC2 | CC3;
1020 case LTU: return CC1;
1021 case GTU: return CC2;
1022 case LEU: return CC0 | CC1;
1023 case GEU: return CC0 | CC2;
1024 default: return -1;
1025 }
1026 break;
1027
1028 case CCURmode:
1029 switch (GET_CODE (code))
1030 {
1031 case EQ: return CC0;
1032 case NE: return CC2 | CC1 | CC3;
1033 case LTU: return CC2;
1034 case GTU: return CC1;
1035 case LEU: return CC0 | CC2;
1036 case GEU: return CC0 | CC1;
1037 default: return -1;
1038 }
1039 break;
1040
1041 case CCAPmode:
1042 switch (GET_CODE (code))
1043 {
1044 case EQ: return CC0;
1045 case NE: return CC1 | CC2 | CC3;
1046 case LT: return CC1 | CC3;
1047 case GT: return CC2;
1048 case LE: return CC0 | CC1 | CC3;
1049 case GE: return CC0 | CC2;
1050 default: return -1;
1051 }
1052 break;
1053
1054 case CCANmode:
1055 switch (GET_CODE (code))
1056 {
1057 case EQ: return CC0;
1058 case NE: return CC1 | CC2 | CC3;
1059 case LT: return CC1;
1060 case GT: return CC2 | CC3;
1061 case LE: return CC0 | CC1;
1062 case GE: return CC0 | CC2 | CC3;
1063 default: return -1;
1064 }
1065 break;
1066
1067 case CCSmode:
1068 switch (GET_CODE (code))
1069 {
1070 case EQ: return CC0;
1071 case NE: return CC1 | CC2 | CC3;
1072 case LT: return CC1;
1073 case GT: return CC2;
1074 case LE: return CC0 | CC1;
1075 case GE: return CC0 | CC2;
1076 case UNORDERED: return CC3;
1077 case ORDERED: return CC0 | CC1 | CC2;
1078 case UNEQ: return CC0 | CC3;
1079 case UNLT: return CC1 | CC3;
1080 case UNGT: return CC2 | CC3;
1081 case UNLE: return CC0 | CC1 | CC3;
1082 case UNGE: return CC0 | CC2 | CC3;
1083 case LTGT: return CC1 | CC2;
1084 default: return -1;
1085 }
1086 break;
1087
1088 case CCSRmode:
1089 switch (GET_CODE (code))
1090 {
1091 case EQ: return CC0;
1092 case NE: return CC2 | CC1 | CC3;
1093 case LT: return CC2;
1094 case GT: return CC1;
1095 case LE: return CC0 | CC2;
1096 case GE: return CC0 | CC1;
1097 case UNORDERED: return CC3;
1098 case ORDERED: return CC0 | CC2 | CC1;
1099 case UNEQ: return CC0 | CC3;
1100 case UNLT: return CC2 | CC3;
1101 case UNGT: return CC1 | CC3;
1102 case UNLE: return CC0 | CC2 | CC3;
1103 case UNGE: return CC0 | CC1 | CC3;
1104 case LTGT: return CC2 | CC1;
1105 default: return -1;
1106 }
1107 break;
1108
1109 default:
1110 return -1;
1111 }
1112 }
1113
1114
1115 /* Return branch condition mask to implement a compare and branch
1116 specified by CODE. Return -1 for invalid comparisons. */
1117
1118 int
1119 s390_compare_and_branch_condition_mask (rtx code)
1120 {
1121 const int CC0 = 1 << 3;
1122 const int CC1 = 1 << 2;
1123 const int CC2 = 1 << 1;
1124
1125 switch (GET_CODE (code))
1126 {
1127 case EQ:
1128 return CC0;
1129 case NE:
1130 return CC1 | CC2;
1131 case LT:
1132 case LTU:
1133 return CC1;
1134 case GT:
1135 case GTU:
1136 return CC2;
1137 case LE:
1138 case LEU:
1139 return CC0 | CC1;
1140 case GE:
1141 case GEU:
1142 return CC0 | CC2;
1143 default:
1144 gcc_unreachable ();
1145 }
1146 return -1;
1147 }
1148
1149 /* If INV is false, return assembler mnemonic string to implement
1150 a branch specified by CODE. If INV is true, return mnemonic
1151 for the corresponding inverted branch. */
1152
1153 static const char *
1154 s390_branch_condition_mnemonic (rtx code, int inv)
1155 {
1156 int mask;
1157
1158 static const char *const mnemonic[16] =
1159 {
1160 NULL, "o", "h", "nle",
1161 "l", "nhe", "lh", "ne",
1162 "e", "nlh", "he", "nl",
1163 "le", "nh", "no", NULL
1164 };
1165
1166 if (GET_CODE (XEXP (code, 0)) == REG
1167 && REGNO (XEXP (code, 0)) == CC_REGNUM
1168 && XEXP (code, 1) == const0_rtx)
1169 mask = s390_branch_condition_mask (code);
1170 else
1171 mask = s390_compare_and_branch_condition_mask (code);
1172
1173 gcc_assert (mask >= 0);
1174
1175 if (inv)
1176 mask ^= 15;
1177
1178 gcc_assert (mask >= 1 && mask <= 14);
1179
1180 return mnemonic[mask];
1181 }
1182
1183 /* Return the part of op which has a value different from def.
1184 The size of the part is determined by mode.
1185 Use this function only if you already know that op really
1186 contains such a part. */
1187
1188 unsigned HOST_WIDE_INT
1189 s390_extract_part (rtx op, enum machine_mode mode, int def)
1190 {
1191 unsigned HOST_WIDE_INT value = 0;
1192 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1193 int part_bits = GET_MODE_BITSIZE (mode);
1194 unsigned HOST_WIDE_INT part_mask
1195 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1196 int i;
1197
1198 for (i = 0; i < max_parts; i++)
1199 {
1200 if (i == 0)
1201 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1202 else
1203 value >>= part_bits;
1204
1205 if ((value & part_mask) != (def & part_mask))
1206 return value & part_mask;
1207 }
1208
1209 gcc_unreachable ();
1210 }
1211
1212 /* If OP is an integer constant of mode MODE with exactly one
1213 part of mode PART_MODE unequal to DEF, return the number of that
1214 part. Otherwise, return -1. */
1215
1216 int
1217 s390_single_part (rtx op,
1218 enum machine_mode mode,
1219 enum machine_mode part_mode,
1220 int def)
1221 {
1222 unsigned HOST_WIDE_INT value = 0;
1223 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1224 unsigned HOST_WIDE_INT part_mask
1225 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1226 int i, part = -1;
1227
1228 if (GET_CODE (op) != CONST_INT)
1229 return -1;
1230
1231 for (i = 0; i < n_parts; i++)
1232 {
1233 if (i == 0)
1234 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1235 else
1236 value >>= GET_MODE_BITSIZE (part_mode);
1237
1238 if ((value & part_mask) != (def & part_mask))
1239 {
1240 if (part != -1)
1241 return -1;
1242 else
1243 part = i;
1244 }
1245 }
1246 return part == -1 ? -1 : n_parts - 1 - part;
1247 }
1248
1249 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1250 bits and no other bits are set in IN. POS and LENGTH can be used
1251 to obtain the start position and the length of the bitfield.
1252
1253 POS gives the position of the first bit of the bitfield counting
1254 from the lowest order bit starting with zero. In order to use this
1255 value for S/390 instructions this has to be converted to "bits big
1256 endian" style. */
1257
1258 bool
1259 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1260 int *pos, int *length)
1261 {
1262 int tmp_pos = 0;
1263 int tmp_length = 0;
1264 int i;
1265 unsigned HOST_WIDE_INT mask = 1ULL;
1266 bool contiguous = false;
1267
1268 for (i = 0; i < size; mask <<= 1, i++)
1269 {
1270 if (contiguous)
1271 {
1272 if (mask & in)
1273 tmp_length++;
1274 else
1275 break;
1276 }
1277 else
1278 {
1279 if (mask & in)
1280 {
1281 contiguous = true;
1282 tmp_length++;
1283 }
1284 else
1285 tmp_pos++;
1286 }
1287 }
1288
1289 if (!tmp_length)
1290 return false;
1291
1292 /* Calculate a mask for all bits beyond the contiguous bits. */
1293 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1294
1295 if (mask & in)
1296 return false;
1297
1298 if (tmp_length + tmp_pos - 1 > size)
1299 return false;
1300
1301 if (length)
1302 *length = tmp_length;
1303
1304 if (pos)
1305 *pos = tmp_pos;
1306
1307 return true;
1308 }
1309
1310 /* Check whether we can (and want to) split a double-word
1311 move in mode MODE from SRC to DST into two single-word
1312 moves, moving the subword FIRST_SUBWORD first. */
1313
1314 bool
1315 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1316 {
1317 /* Floating point registers cannot be split. */
1318 if (FP_REG_P (src) || FP_REG_P (dst))
1319 return false;
1320
1321 /* We don't need to split if operands are directly accessible. */
1322 if (s_operand (src, mode) || s_operand (dst, mode))
1323 return false;
1324
1325 /* Non-offsettable memory references cannot be split. */
1326 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1327 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1328 return false;
1329
1330 /* Moving the first subword must not clobber a register
1331 needed to move the second subword. */
1332 if (register_operand (dst, mode))
1333 {
1334 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1335 if (reg_overlap_mentioned_p (subreg, src))
1336 return false;
1337 }
1338
1339 return true;
1340 }
1341
1342 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1343 and [MEM2, MEM2 + SIZE] do overlap and false
1344 otherwise. */
1345
1346 bool
1347 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1348 {
1349 rtx addr1, addr2, addr_delta;
1350 HOST_WIDE_INT delta;
1351
1352 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1353 return true;
1354
1355 if (size == 0)
1356 return false;
1357
1358 addr1 = XEXP (mem1, 0);
1359 addr2 = XEXP (mem2, 0);
1360
1361 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1362
1363 /* This overlapping check is used by peepholes merging memory block operations.
1364 Overlapping operations would otherwise be recognized by the S/390 hardware
1365 and would fall back to a slower implementation. Allowing overlapping
1366 operations would lead to slow code but not to wrong code. Therefore we are
1367 somewhat optimistic if we cannot prove that the memory blocks are
1368 overlapping.
1369 That's why we return false here although this may accept operations on
1370 overlapping memory areas. */
1371 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1372 return false;
1373
1374 delta = INTVAL (addr_delta);
1375
1376 if (delta == 0
1377 || (delta > 0 && delta < size)
1378 || (delta < 0 && -delta < size))
1379 return true;
1380
1381 return false;
1382 }
1383
1384 /* Check whether the address of memory reference MEM2 equals exactly
1385 the address of memory reference MEM1 plus DELTA. Return true if
1386 we can prove this to be the case, false otherwise. */
1387
1388 bool
1389 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1390 {
1391 rtx addr1, addr2, addr_delta;
1392
1393 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1394 return false;
1395
1396 addr1 = XEXP (mem1, 0);
1397 addr2 = XEXP (mem2, 0);
1398
1399 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1400 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1401 return false;
1402
1403 return true;
1404 }
1405
1406 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1407
1408 void
1409 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1410 rtx *operands)
1411 {
1412 enum machine_mode wmode = mode;
1413 rtx dst = operands[0];
1414 rtx src1 = operands[1];
1415 rtx src2 = operands[2];
1416 rtx op, clob, tem;
1417
1418 /* If we cannot handle the operation directly, use a temp register. */
1419 if (!s390_logical_operator_ok_p (operands))
1420 dst = gen_reg_rtx (mode);
1421
1422 /* QImode and HImode patterns make sense only if we have a destination
1423 in memory. Otherwise perform the operation in SImode. */
1424 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1425 wmode = SImode;
1426
1427 /* Widen operands if required. */
1428 if (mode != wmode)
1429 {
1430 if (GET_CODE (dst) == SUBREG
1431 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1432 dst = tem;
1433 else if (REG_P (dst))
1434 dst = gen_rtx_SUBREG (wmode, dst, 0);
1435 else
1436 dst = gen_reg_rtx (wmode);
1437
1438 if (GET_CODE (src1) == SUBREG
1439 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1440 src1 = tem;
1441 else if (GET_MODE (src1) != VOIDmode)
1442 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1443
1444 if (GET_CODE (src2) == SUBREG
1445 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1446 src2 = tem;
1447 else if (GET_MODE (src2) != VOIDmode)
1448 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1449 }
1450
1451 /* Emit the instruction. */
1452 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1453 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1454 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1455
1456 /* Fix up the destination if needed. */
1457 if (dst != operands[0])
1458 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1459 }
1460
1461 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1462
1463 bool
1464 s390_logical_operator_ok_p (rtx *operands)
1465 {
1466 /* If the destination operand is in memory, it needs to coincide
1467 with one of the source operands. After reload, it has to be
1468 the first source operand. */
1469 if (GET_CODE (operands[0]) == MEM)
1470 return rtx_equal_p (operands[0], operands[1])
1471 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1472
1473 return true;
1474 }
1475
1476 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1477 operand IMMOP to switch from SS to SI type instructions. */
1478
1479 void
1480 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1481 {
1482 int def = code == AND ? -1 : 0;
1483 HOST_WIDE_INT mask;
1484 int part;
1485
1486 gcc_assert (GET_CODE (*memop) == MEM);
1487 gcc_assert (!MEM_VOLATILE_P (*memop));
1488
1489 mask = s390_extract_part (*immop, QImode, def);
1490 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1491 gcc_assert (part >= 0);
1492
1493 *memop = adjust_address (*memop, QImode, part);
1494 *immop = gen_int_mode (mask, QImode);
1495 }
1496
1497
1498 /* How to allocate a 'struct machine_function'. */
1499
1500 static struct machine_function *
1501 s390_init_machine_status (void)
1502 {
1503 return ggc_alloc_cleared_machine_function ();
1504 }
1505
1506 static void
1507 s390_option_override (void)
1508 {
1509 /* Set up function hooks. */
1510 init_machine_status = s390_init_machine_status;
1511
1512 /* Architecture mode defaults according to ABI. */
1513 if (!(target_flags_explicit & MASK_ZARCH))
1514 {
1515 if (TARGET_64BIT)
1516 target_flags |= MASK_ZARCH;
1517 else
1518 target_flags &= ~MASK_ZARCH;
1519 }
1520
1521 /* Set the march default in case it hasn't been specified on
1522 cmdline. */
1523 if (s390_arch == PROCESSOR_max)
1524 {
1525 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1526 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1527 s390_arch_flags = processor_flags_table[(int)s390_arch];
1528 }
1529
1530 /* Determine processor to tune for. */
1531 if (s390_tune == PROCESSOR_max)
1532 {
1533 s390_tune = s390_arch;
1534 s390_tune_flags = s390_arch_flags;
1535 }
1536
1537 /* Sanity checks. */
1538 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1539 error ("z/Architecture mode not supported on %s", s390_arch_string);
1540 if (TARGET_64BIT && !TARGET_ZARCH)
1541 error ("64-bit ABI not supported in ESA/390 mode");
1542
1543 /* Use hardware DFP if available and not explicitly disabled by
1544 user. E.g. with -m31 -march=z10 -mzarch */
1545 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1546 target_flags |= MASK_HARD_DFP;
1547
1548 if (TARGET_HARD_DFP && !TARGET_DFP)
1549 {
1550 if (target_flags_explicit & MASK_HARD_DFP)
1551 {
1552 if (!TARGET_CPU_DFP)
1553 error ("hardware decimal floating point instructions"
1554 " not available on %s", s390_arch_string);
1555 if (!TARGET_ZARCH)
1556 error ("hardware decimal floating point instructions"
1557 " not available in ESA/390 mode");
1558 }
1559 else
1560 target_flags &= ~MASK_HARD_DFP;
1561 }
1562
1563 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1564 {
1565 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1566 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1567
1568 target_flags &= ~MASK_HARD_DFP;
1569 }
1570
1571 /* Set processor cost function. */
1572 switch (s390_tune)
1573 {
1574 case PROCESSOR_2084_Z990:
1575 s390_cost = &z990_cost;
1576 break;
1577 case PROCESSOR_2094_Z9_109:
1578 s390_cost = &z9_109_cost;
1579 break;
1580 case PROCESSOR_2097_Z10:
1581 s390_cost = &z10_cost;
1582 case PROCESSOR_2817_Z196:
1583 s390_cost = &z196_cost;
1584 break;
1585 default:
1586 s390_cost = &z900_cost;
1587 }
1588
1589 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1590 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1591 "in combination");
1592
1593 if (s390_stack_size)
1594 {
1595 if (s390_stack_guard >= s390_stack_size)
1596 error ("stack size must be greater than the stack guard value");
1597 else if (s390_stack_size > 1 << 16)
1598 error ("stack size must not be greater than 64k");
1599 }
1600 else if (s390_stack_guard)
1601 error ("-mstack-guard implies use of -mstack-size");
1602
1603 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1604 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1605 target_flags |= MASK_LONG_DOUBLE_128;
1606 #endif
1607
1608 if (s390_tune == PROCESSOR_2097_Z10
1609 || s390_tune == PROCESSOR_2817_Z196)
1610 {
1611 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1612 global_options.x_param_values,
1613 global_options_set.x_param_values);
1614 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1615 global_options.x_param_values,
1616 global_options_set.x_param_values);
1617 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1618 global_options.x_param_values,
1619 global_options_set.x_param_values);
1620 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1621 global_options.x_param_values,
1622 global_options_set.x_param_values);
1623 }
1624
1625 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1626 global_options.x_param_values,
1627 global_options_set.x_param_values);
1628 /* values for loop prefetching */
1629 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1630 global_options.x_param_values,
1631 global_options_set.x_param_values);
1632 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1633 global_options.x_param_values,
1634 global_options_set.x_param_values);
1635 /* s390 has more than 2 levels and the size is much larger. Since
1636 we are always running virtualized assume that we only get a small
1637 part of the caches above l1. */
1638 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1639 global_options.x_param_values,
1640 global_options_set.x_param_values);
1641 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1642 global_options.x_param_values,
1643 global_options_set.x_param_values);
1644 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1645 global_options.x_param_values,
1646 global_options_set.x_param_values);
1647
1648 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1649 requires the arch flags to be evaluated already. Since prefetching
1650 is beneficial on s390, we enable it if available. */
1651 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1652 flag_prefetch_loop_arrays = 1;
1653 }
1654
1655 /* Map for smallest class containing reg regno. */
1656
1657 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1658 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1659 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1660 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1661 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1662 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1663 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1664 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1665 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1666 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1667 ACCESS_REGS, ACCESS_REGS
1668 };
1669
1670 /* Return attribute type of insn. */
1671
1672 static enum attr_type
1673 s390_safe_attr_type (rtx insn)
1674 {
1675 if (recog_memoized (insn) >= 0)
1676 return get_attr_type (insn);
1677 else
1678 return TYPE_NONE;
1679 }
1680
1681 /* Return true if DISP is a valid short displacement. */
1682
1683 static bool
1684 s390_short_displacement (rtx disp)
1685 {
1686 /* No displacement is OK. */
1687 if (!disp)
1688 return true;
1689
1690 /* Without the long displacement facility we don't need to
1691 distingiush between long and short displacement. */
1692 if (!TARGET_LONG_DISPLACEMENT)
1693 return true;
1694
1695 /* Integer displacement in range. */
1696 if (GET_CODE (disp) == CONST_INT)
1697 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1698
1699 /* GOT offset is not OK, the GOT can be large. */
1700 if (GET_CODE (disp) == CONST
1701 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1702 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1703 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1704 return false;
1705
1706 /* All other symbolic constants are literal pool references,
1707 which are OK as the literal pool must be small. */
1708 if (GET_CODE (disp) == CONST)
1709 return true;
1710
1711 return false;
1712 }
1713
1714 /* Decompose a RTL expression ADDR for a memory address into
1715 its components, returned in OUT.
1716
1717 Returns false if ADDR is not a valid memory address, true
1718 otherwise. If OUT is NULL, don't return the components,
1719 but check for validity only.
1720
1721 Note: Only addresses in canonical form are recognized.
1722 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1723 canonical form so that they will be recognized. */
1724
1725 static int
1726 s390_decompose_address (rtx addr, struct s390_address *out)
1727 {
1728 HOST_WIDE_INT offset = 0;
1729 rtx base = NULL_RTX;
1730 rtx indx = NULL_RTX;
1731 rtx disp = NULL_RTX;
1732 rtx orig_disp;
1733 bool pointer = false;
1734 bool base_ptr = false;
1735 bool indx_ptr = false;
1736 bool literal_pool = false;
1737
1738 /* We may need to substitute the literal pool base register into the address
1739 below. However, at this point we do not know which register is going to
1740 be used as base, so we substitute the arg pointer register. This is going
1741 to be treated as holding a pointer below -- it shouldn't be used for any
1742 other purpose. */
1743 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1744
1745 /* Decompose address into base + index + displacement. */
1746
1747 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1748 base = addr;
1749
1750 else if (GET_CODE (addr) == PLUS)
1751 {
1752 rtx op0 = XEXP (addr, 0);
1753 rtx op1 = XEXP (addr, 1);
1754 enum rtx_code code0 = GET_CODE (op0);
1755 enum rtx_code code1 = GET_CODE (op1);
1756
1757 if (code0 == REG || code0 == UNSPEC)
1758 {
1759 if (code1 == REG || code1 == UNSPEC)
1760 {
1761 indx = op0; /* index + base */
1762 base = op1;
1763 }
1764
1765 else
1766 {
1767 base = op0; /* base + displacement */
1768 disp = op1;
1769 }
1770 }
1771
1772 else if (code0 == PLUS)
1773 {
1774 indx = XEXP (op0, 0); /* index + base + disp */
1775 base = XEXP (op0, 1);
1776 disp = op1;
1777 }
1778
1779 else
1780 {
1781 return false;
1782 }
1783 }
1784
1785 else
1786 disp = addr; /* displacement */
1787
1788 /* Extract integer part of displacement. */
1789 orig_disp = disp;
1790 if (disp)
1791 {
1792 if (GET_CODE (disp) == CONST_INT)
1793 {
1794 offset = INTVAL (disp);
1795 disp = NULL_RTX;
1796 }
1797 else if (GET_CODE (disp) == CONST
1798 && GET_CODE (XEXP (disp, 0)) == PLUS
1799 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1800 {
1801 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1802 disp = XEXP (XEXP (disp, 0), 0);
1803 }
1804 }
1805
1806 /* Strip off CONST here to avoid special case tests later. */
1807 if (disp && GET_CODE (disp) == CONST)
1808 disp = XEXP (disp, 0);
1809
1810 /* We can convert literal pool addresses to
1811 displacements by basing them off the base register. */
1812 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1813 {
1814 /* Either base or index must be free to hold the base register. */
1815 if (!base)
1816 base = fake_pool_base, literal_pool = true;
1817 else if (!indx)
1818 indx = fake_pool_base, literal_pool = true;
1819 else
1820 return false;
1821
1822 /* Mark up the displacement. */
1823 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1824 UNSPEC_LTREL_OFFSET);
1825 }
1826
1827 /* Validate base register. */
1828 if (base)
1829 {
1830 if (GET_CODE (base) == UNSPEC)
1831 switch (XINT (base, 1))
1832 {
1833 case UNSPEC_LTREF:
1834 if (!disp)
1835 disp = gen_rtx_UNSPEC (Pmode,
1836 gen_rtvec (1, XVECEXP (base, 0, 0)),
1837 UNSPEC_LTREL_OFFSET);
1838 else
1839 return false;
1840
1841 base = XVECEXP (base, 0, 1);
1842 break;
1843
1844 case UNSPEC_LTREL_BASE:
1845 if (XVECLEN (base, 0) == 1)
1846 base = fake_pool_base, literal_pool = true;
1847 else
1848 base = XVECEXP (base, 0, 1);
1849 break;
1850
1851 default:
1852 return false;
1853 }
1854
1855 if (!REG_P (base)
1856 || (GET_MODE (base) != SImode
1857 && GET_MODE (base) != Pmode))
1858 return false;
1859
1860 if (REGNO (base) == STACK_POINTER_REGNUM
1861 || REGNO (base) == FRAME_POINTER_REGNUM
1862 || ((reload_completed || reload_in_progress)
1863 && frame_pointer_needed
1864 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1865 || REGNO (base) == ARG_POINTER_REGNUM
1866 || (flag_pic
1867 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1868 pointer = base_ptr = true;
1869
1870 if ((reload_completed || reload_in_progress)
1871 && base == cfun->machine->base_reg)
1872 pointer = base_ptr = literal_pool = true;
1873 }
1874
1875 /* Validate index register. */
1876 if (indx)
1877 {
1878 if (GET_CODE (indx) == UNSPEC)
1879 switch (XINT (indx, 1))
1880 {
1881 case UNSPEC_LTREF:
1882 if (!disp)
1883 disp = gen_rtx_UNSPEC (Pmode,
1884 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1885 UNSPEC_LTREL_OFFSET);
1886 else
1887 return false;
1888
1889 indx = XVECEXP (indx, 0, 1);
1890 break;
1891
1892 case UNSPEC_LTREL_BASE:
1893 if (XVECLEN (indx, 0) == 1)
1894 indx = fake_pool_base, literal_pool = true;
1895 else
1896 indx = XVECEXP (indx, 0, 1);
1897 break;
1898
1899 default:
1900 return false;
1901 }
1902
1903 if (!REG_P (indx)
1904 || (GET_MODE (indx) != SImode
1905 && GET_MODE (indx) != Pmode))
1906 return false;
1907
1908 if (REGNO (indx) == STACK_POINTER_REGNUM
1909 || REGNO (indx) == FRAME_POINTER_REGNUM
1910 || ((reload_completed || reload_in_progress)
1911 && frame_pointer_needed
1912 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1913 || REGNO (indx) == ARG_POINTER_REGNUM
1914 || (flag_pic
1915 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1916 pointer = indx_ptr = true;
1917
1918 if ((reload_completed || reload_in_progress)
1919 && indx == cfun->machine->base_reg)
1920 pointer = indx_ptr = literal_pool = true;
1921 }
1922
1923 /* Prefer to use pointer as base, not index. */
1924 if (base && indx && !base_ptr
1925 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1926 {
1927 rtx tmp = base;
1928 base = indx;
1929 indx = tmp;
1930 }
1931
1932 /* Validate displacement. */
1933 if (!disp)
1934 {
1935 /* If virtual registers are involved, the displacement will change later
1936 anyway as the virtual registers get eliminated. This could make a
1937 valid displacement invalid, but it is more likely to make an invalid
1938 displacement valid, because we sometimes access the register save area
1939 via negative offsets to one of those registers.
1940 Thus we don't check the displacement for validity here. If after
1941 elimination the displacement turns out to be invalid after all,
1942 this is fixed up by reload in any case. */
1943 if (base != arg_pointer_rtx
1944 && indx != arg_pointer_rtx
1945 && base != return_address_pointer_rtx
1946 && indx != return_address_pointer_rtx
1947 && base != frame_pointer_rtx
1948 && indx != frame_pointer_rtx
1949 && base != virtual_stack_vars_rtx
1950 && indx != virtual_stack_vars_rtx)
1951 if (!DISP_IN_RANGE (offset))
1952 return false;
1953 }
1954 else
1955 {
1956 /* All the special cases are pointers. */
1957 pointer = true;
1958
1959 /* In the small-PIC case, the linker converts @GOT
1960 and @GOTNTPOFF offsets to possible displacements. */
1961 if (GET_CODE (disp) == UNSPEC
1962 && (XINT (disp, 1) == UNSPEC_GOT
1963 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1964 && flag_pic == 1)
1965 {
1966 ;
1967 }
1968
1969 /* Accept pool label offsets. */
1970 else if (GET_CODE (disp) == UNSPEC
1971 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1972 ;
1973
1974 /* Accept literal pool references. */
1975 else if (GET_CODE (disp) == UNSPEC
1976 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1977 {
1978 /* In case CSE pulled a non literal pool reference out of
1979 the pool we have to reject the address. This is
1980 especially important when loading the GOT pointer on non
1981 zarch CPUs. In this case the literal pool contains an lt
1982 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1983 will most likely exceed the displacement. */
1984 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
1985 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
1986 return false;
1987
1988 orig_disp = gen_rtx_CONST (Pmode, disp);
1989 if (offset)
1990 {
1991 /* If we have an offset, make sure it does not
1992 exceed the size of the constant pool entry. */
1993 rtx sym = XVECEXP (disp, 0, 0);
1994 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1995 return false;
1996
1997 orig_disp = plus_constant (Pmode, orig_disp, offset);
1998 }
1999 }
2000
2001 else
2002 return false;
2003 }
2004
2005 if (!base && !indx)
2006 pointer = true;
2007
2008 if (out)
2009 {
2010 out->base = base;
2011 out->indx = indx;
2012 out->disp = orig_disp;
2013 out->pointer = pointer;
2014 out->literal_pool = literal_pool;
2015 }
2016
2017 return true;
2018 }
2019
2020 /* Decompose a RTL expression OP for a shift count into its components,
2021 and return the base register in BASE and the offset in OFFSET.
2022
2023 Return true if OP is a valid shift count, false if not. */
2024
2025 bool
2026 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2027 {
2028 HOST_WIDE_INT off = 0;
2029
2030 /* We can have an integer constant, an address register,
2031 or a sum of the two. */
2032 if (GET_CODE (op) == CONST_INT)
2033 {
2034 off = INTVAL (op);
2035 op = NULL_RTX;
2036 }
2037 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2038 {
2039 off = INTVAL (XEXP (op, 1));
2040 op = XEXP (op, 0);
2041 }
2042 while (op && GET_CODE (op) == SUBREG)
2043 op = SUBREG_REG (op);
2044
2045 if (op && GET_CODE (op) != REG)
2046 return false;
2047
2048 if (offset)
2049 *offset = off;
2050 if (base)
2051 *base = op;
2052
2053 return true;
2054 }
2055
2056
2057 /* Return true if CODE is a valid address without index. */
2058
2059 bool
2060 s390_legitimate_address_without_index_p (rtx op)
2061 {
2062 struct s390_address addr;
2063
2064 if (!s390_decompose_address (XEXP (op, 0), &addr))
2065 return false;
2066 if (addr.indx)
2067 return false;
2068
2069 return true;
2070 }
2071
2072
2073 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2074 and return these parts in SYMREF and ADDEND. You can pass NULL in
2075 SYMREF and/or ADDEND if you are not interested in these values.
2076 Literal pool references are *not* considered symbol references. */
2077
2078 static bool
2079 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2080 {
2081 HOST_WIDE_INT tmpaddend = 0;
2082
2083 if (GET_CODE (addr) == CONST)
2084 addr = XEXP (addr, 0);
2085
2086 if (GET_CODE (addr) == PLUS)
2087 {
2088 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2089 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2090 && CONST_INT_P (XEXP (addr, 1)))
2091 {
2092 tmpaddend = INTVAL (XEXP (addr, 1));
2093 addr = XEXP (addr, 0);
2094 }
2095 else
2096 return false;
2097 }
2098 else
2099 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2100 return false;
2101
2102 if (symref)
2103 *symref = addr;
2104 if (addend)
2105 *addend = tmpaddend;
2106
2107 return true;
2108 }
2109
2110
2111 /* Return true if the address in OP is valid for constraint letter C
2112 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2113 pool MEMs should be accepted. Only the Q, R, S, T constraint
2114 letters are allowed for C. */
2115
2116 static int
2117 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2118 {
2119 struct s390_address addr;
2120 bool decomposed = false;
2121
2122 /* This check makes sure that no symbolic address (except literal
2123 pool references) are accepted by the R or T constraints. */
2124 if (s390_symref_operand_p (op, NULL, NULL))
2125 return 0;
2126
2127 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2128 if (!lit_pool_ok)
2129 {
2130 if (!s390_decompose_address (op, &addr))
2131 return 0;
2132 if (addr.literal_pool)
2133 return 0;
2134 decomposed = true;
2135 }
2136
2137 switch (c)
2138 {
2139 case 'Q': /* no index short displacement */
2140 if (!decomposed && !s390_decompose_address (op, &addr))
2141 return 0;
2142 if (addr.indx)
2143 return 0;
2144 if (!s390_short_displacement (addr.disp))
2145 return 0;
2146 break;
2147
2148 case 'R': /* with index short displacement */
2149 if (TARGET_LONG_DISPLACEMENT)
2150 {
2151 if (!decomposed && !s390_decompose_address (op, &addr))
2152 return 0;
2153 if (!s390_short_displacement (addr.disp))
2154 return 0;
2155 }
2156 /* Any invalid address here will be fixed up by reload,
2157 so accept it for the most generic constraint. */
2158 break;
2159
2160 case 'S': /* no index long displacement */
2161 if (!TARGET_LONG_DISPLACEMENT)
2162 return 0;
2163 if (!decomposed && !s390_decompose_address (op, &addr))
2164 return 0;
2165 if (addr.indx)
2166 return 0;
2167 if (s390_short_displacement (addr.disp))
2168 return 0;
2169 break;
2170
2171 case 'T': /* with index long displacement */
2172 if (!TARGET_LONG_DISPLACEMENT)
2173 return 0;
2174 /* Any invalid address here will be fixed up by reload,
2175 so accept it for the most generic constraint. */
2176 if ((decomposed || s390_decompose_address (op, &addr))
2177 && s390_short_displacement (addr.disp))
2178 return 0;
2179 break;
2180 default:
2181 return 0;
2182 }
2183 return 1;
2184 }
2185
2186
2187 /* Evaluates constraint strings described by the regular expression
2188 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2189 the constraint given in STR, or 0 else. */
2190
2191 int
2192 s390_mem_constraint (const char *str, rtx op)
2193 {
2194 char c = str[0];
2195
2196 switch (c)
2197 {
2198 case 'A':
2199 /* Check for offsettable variants of memory constraints. */
2200 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2201 return 0;
2202 if ((reload_completed || reload_in_progress)
2203 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2204 return 0;
2205 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2206 case 'B':
2207 /* Check for non-literal-pool variants of memory constraints. */
2208 if (!MEM_P (op))
2209 return 0;
2210 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2211 case 'Q':
2212 case 'R':
2213 case 'S':
2214 case 'T':
2215 if (GET_CODE (op) != MEM)
2216 return 0;
2217 return s390_check_qrst_address (c, XEXP (op, 0), true);
2218 case 'U':
2219 return (s390_check_qrst_address ('Q', op, true)
2220 || s390_check_qrst_address ('R', op, true));
2221 case 'W':
2222 return (s390_check_qrst_address ('S', op, true)
2223 || s390_check_qrst_address ('T', op, true));
2224 case 'Y':
2225 /* Simply check for the basic form of a shift count. Reload will
2226 take care of making sure we have a proper base register. */
2227 if (!s390_decompose_shift_count (op, NULL, NULL))
2228 return 0;
2229 break;
2230 case 'Z':
2231 return s390_check_qrst_address (str[1], op, true);
2232 default:
2233 return 0;
2234 }
2235 return 1;
2236 }
2237
2238
2239 /* Evaluates constraint strings starting with letter O. Input
2240 parameter C is the second letter following the "O" in the constraint
2241 string. Returns 1 if VALUE meets the respective constraint and 0
2242 otherwise. */
2243
2244 int
2245 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2246 {
2247 if (!TARGET_EXTIMM)
2248 return 0;
2249
2250 switch (c)
2251 {
2252 case 's':
2253 return trunc_int_for_mode (value, SImode) == value;
2254
2255 case 'p':
2256 return value == 0
2257 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2258
2259 case 'n':
2260 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2261
2262 default:
2263 gcc_unreachable ();
2264 }
2265 }
2266
2267
2268 /* Evaluates constraint strings starting with letter N. Parameter STR
2269 contains the letters following letter "N" in the constraint string.
2270 Returns true if VALUE matches the constraint. */
2271
2272 int
2273 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2274 {
2275 enum machine_mode mode, part_mode;
2276 int def;
2277 int part, part_goal;
2278
2279
2280 if (str[0] == 'x')
2281 part_goal = -1;
2282 else
2283 part_goal = str[0] - '0';
2284
2285 switch (str[1])
2286 {
2287 case 'Q':
2288 part_mode = QImode;
2289 break;
2290 case 'H':
2291 part_mode = HImode;
2292 break;
2293 case 'S':
2294 part_mode = SImode;
2295 break;
2296 default:
2297 return 0;
2298 }
2299
2300 switch (str[2])
2301 {
2302 case 'H':
2303 mode = HImode;
2304 break;
2305 case 'S':
2306 mode = SImode;
2307 break;
2308 case 'D':
2309 mode = DImode;
2310 break;
2311 default:
2312 return 0;
2313 }
2314
2315 switch (str[3])
2316 {
2317 case '0':
2318 def = 0;
2319 break;
2320 case 'F':
2321 def = -1;
2322 break;
2323 default:
2324 return 0;
2325 }
2326
2327 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2328 return 0;
2329
2330 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2331 if (part < 0)
2332 return 0;
2333 if (part_goal != -1 && part_goal != part)
2334 return 0;
2335
2336 return 1;
2337 }
2338
2339
2340 /* Returns true if the input parameter VALUE is a float zero. */
2341
2342 int
2343 s390_float_const_zero_p (rtx value)
2344 {
2345 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2346 && value == CONST0_RTX (GET_MODE (value)));
2347 }
2348
2349 /* Implement TARGET_REGISTER_MOVE_COST. */
2350
2351 static int
2352 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2353 reg_class_t from, reg_class_t to)
2354 {
2355 /* On s390, copy between fprs and gprs is expensive. */
2356 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2357 && reg_classes_intersect_p (to, FP_REGS))
2358 || (reg_classes_intersect_p (from, FP_REGS)
2359 && reg_classes_intersect_p (to, GENERAL_REGS)))
2360 return 10;
2361
2362 return 1;
2363 }
2364
2365 /* Implement TARGET_MEMORY_MOVE_COST. */
2366
2367 static int
2368 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2369 reg_class_t rclass ATTRIBUTE_UNUSED,
2370 bool in ATTRIBUTE_UNUSED)
2371 {
2372 return 1;
2373 }
2374
2375 /* Compute a (partial) cost for rtx X. Return true if the complete
2376 cost has been computed, and false if subexpressions should be
2377 scanned. In either case, *TOTAL contains the cost result.
2378 CODE contains GET_CODE (x), OUTER_CODE contains the code
2379 of the superexpression of x. */
2380
2381 static bool
2382 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2383 int *total, bool speed ATTRIBUTE_UNUSED)
2384 {
2385 switch (code)
2386 {
2387 case CONST:
2388 case CONST_INT:
2389 case LABEL_REF:
2390 case SYMBOL_REF:
2391 case CONST_DOUBLE:
2392 case MEM:
2393 *total = 0;
2394 return true;
2395
2396 case ASHIFT:
2397 case ASHIFTRT:
2398 case LSHIFTRT:
2399 case ROTATE:
2400 case ROTATERT:
2401 case AND:
2402 case IOR:
2403 case XOR:
2404 case NEG:
2405 case NOT:
2406 *total = COSTS_N_INSNS (1);
2407 return false;
2408
2409 case PLUS:
2410 case MINUS:
2411 *total = COSTS_N_INSNS (1);
2412 return false;
2413
2414 case MULT:
2415 switch (GET_MODE (x))
2416 {
2417 case SImode:
2418 {
2419 rtx left = XEXP (x, 0);
2420 rtx right = XEXP (x, 1);
2421 if (GET_CODE (right) == CONST_INT
2422 && CONST_OK_FOR_K (INTVAL (right)))
2423 *total = s390_cost->mhi;
2424 else if (GET_CODE (left) == SIGN_EXTEND)
2425 *total = s390_cost->mh;
2426 else
2427 *total = s390_cost->ms; /* msr, ms, msy */
2428 break;
2429 }
2430 case DImode:
2431 {
2432 rtx left = XEXP (x, 0);
2433 rtx right = XEXP (x, 1);
2434 if (TARGET_ZARCH)
2435 {
2436 if (GET_CODE (right) == CONST_INT
2437 && CONST_OK_FOR_K (INTVAL (right)))
2438 *total = s390_cost->mghi;
2439 else if (GET_CODE (left) == SIGN_EXTEND)
2440 *total = s390_cost->msgf;
2441 else
2442 *total = s390_cost->msg; /* msgr, msg */
2443 }
2444 else /* TARGET_31BIT */
2445 {
2446 if (GET_CODE (left) == SIGN_EXTEND
2447 && GET_CODE (right) == SIGN_EXTEND)
2448 /* mulsidi case: mr, m */
2449 *total = s390_cost->m;
2450 else if (GET_CODE (left) == ZERO_EXTEND
2451 && GET_CODE (right) == ZERO_EXTEND
2452 && TARGET_CPU_ZARCH)
2453 /* umulsidi case: ml, mlr */
2454 *total = s390_cost->ml;
2455 else
2456 /* Complex calculation is required. */
2457 *total = COSTS_N_INSNS (40);
2458 }
2459 break;
2460 }
2461 case SFmode:
2462 case DFmode:
2463 *total = s390_cost->mult_df;
2464 break;
2465 case TFmode:
2466 *total = s390_cost->mxbr;
2467 break;
2468 default:
2469 return false;
2470 }
2471 return false;
2472
2473 case FMA:
2474 switch (GET_MODE (x))
2475 {
2476 case DFmode:
2477 *total = s390_cost->madbr;
2478 break;
2479 case SFmode:
2480 *total = s390_cost->maebr;
2481 break;
2482 default:
2483 return false;
2484 }
2485 /* Negate in the third argument is free: FMSUB. */
2486 if (GET_CODE (XEXP (x, 2)) == NEG)
2487 {
2488 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2489 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2490 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2491 return true;
2492 }
2493 return false;
2494
2495 case UDIV:
2496 case UMOD:
2497 if (GET_MODE (x) == TImode) /* 128 bit division */
2498 *total = s390_cost->dlgr;
2499 else if (GET_MODE (x) == DImode)
2500 {
2501 rtx right = XEXP (x, 1);
2502 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2503 *total = s390_cost->dlr;
2504 else /* 64 by 64 bit division */
2505 *total = s390_cost->dlgr;
2506 }
2507 else if (GET_MODE (x) == SImode) /* 32 bit division */
2508 *total = s390_cost->dlr;
2509 return false;
2510
2511 case DIV:
2512 case MOD:
2513 if (GET_MODE (x) == DImode)
2514 {
2515 rtx right = XEXP (x, 1);
2516 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2517 if (TARGET_ZARCH)
2518 *total = s390_cost->dsgfr;
2519 else
2520 *total = s390_cost->dr;
2521 else /* 64 by 64 bit division */
2522 *total = s390_cost->dsgr;
2523 }
2524 else if (GET_MODE (x) == SImode) /* 32 bit division */
2525 *total = s390_cost->dlr;
2526 else if (GET_MODE (x) == SFmode)
2527 {
2528 *total = s390_cost->debr;
2529 }
2530 else if (GET_MODE (x) == DFmode)
2531 {
2532 *total = s390_cost->ddbr;
2533 }
2534 else if (GET_MODE (x) == TFmode)
2535 {
2536 *total = s390_cost->dxbr;
2537 }
2538 return false;
2539
2540 case SQRT:
2541 if (GET_MODE (x) == SFmode)
2542 *total = s390_cost->sqebr;
2543 else if (GET_MODE (x) == DFmode)
2544 *total = s390_cost->sqdbr;
2545 else /* TFmode */
2546 *total = s390_cost->sqxbr;
2547 return false;
2548
2549 case SIGN_EXTEND:
2550 case ZERO_EXTEND:
2551 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2552 || outer_code == PLUS || outer_code == MINUS
2553 || outer_code == COMPARE)
2554 *total = 0;
2555 return false;
2556
2557 case COMPARE:
2558 *total = COSTS_N_INSNS (1);
2559 if (GET_CODE (XEXP (x, 0)) == AND
2560 && GET_CODE (XEXP (x, 1)) == CONST_INT
2561 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2562 {
2563 rtx op0 = XEXP (XEXP (x, 0), 0);
2564 rtx op1 = XEXP (XEXP (x, 0), 1);
2565 rtx op2 = XEXP (x, 1);
2566
2567 if (memory_operand (op0, GET_MODE (op0))
2568 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2569 return true;
2570 if (register_operand (op0, GET_MODE (op0))
2571 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2572 return true;
2573 }
2574 return false;
2575
2576 default:
2577 return false;
2578 }
2579 }
2580
2581 /* Return the cost of an address rtx ADDR. */
2582
2583 static int
2584 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2585 {
2586 struct s390_address ad;
2587 if (!s390_decompose_address (addr, &ad))
2588 return 1000;
2589
2590 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2591 }
2592
2593 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2594 otherwise return 0. */
2595
2596 int
2597 tls_symbolic_operand (rtx op)
2598 {
2599 if (GET_CODE (op) != SYMBOL_REF)
2600 return 0;
2601 return SYMBOL_REF_TLS_MODEL (op);
2602 }
2603 \f
2604 /* Split DImode access register reference REG (on 64-bit) into its constituent
2605 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2606 gen_highpart cannot be used as they assume all registers are word-sized,
2607 while our access registers have only half that size. */
2608
2609 void
2610 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2611 {
2612 gcc_assert (TARGET_64BIT);
2613 gcc_assert (ACCESS_REG_P (reg));
2614 gcc_assert (GET_MODE (reg) == DImode);
2615 gcc_assert (!(REGNO (reg) & 1));
2616
2617 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2618 *hi = gen_rtx_REG (SImode, REGNO (reg));
2619 }
2620
2621 /* Return true if OP contains a symbol reference */
2622
2623 bool
2624 symbolic_reference_mentioned_p (rtx op)
2625 {
2626 const char *fmt;
2627 int i;
2628
2629 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2630 return 1;
2631
2632 fmt = GET_RTX_FORMAT (GET_CODE (op));
2633 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2634 {
2635 if (fmt[i] == 'E')
2636 {
2637 int j;
2638
2639 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2640 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2641 return 1;
2642 }
2643
2644 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2645 return 1;
2646 }
2647
2648 return 0;
2649 }
2650
2651 /* Return true if OP contains a reference to a thread-local symbol. */
2652
2653 bool
2654 tls_symbolic_reference_mentioned_p (rtx op)
2655 {
2656 const char *fmt;
2657 int i;
2658
2659 if (GET_CODE (op) == SYMBOL_REF)
2660 return tls_symbolic_operand (op);
2661
2662 fmt = GET_RTX_FORMAT (GET_CODE (op));
2663 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2664 {
2665 if (fmt[i] == 'E')
2666 {
2667 int j;
2668
2669 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2670 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2671 return true;
2672 }
2673
2674 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2675 return true;
2676 }
2677
2678 return false;
2679 }
2680
2681
2682 /* Return true if OP is a legitimate general operand when
2683 generating PIC code. It is given that flag_pic is on
2684 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2685
2686 int
2687 legitimate_pic_operand_p (rtx op)
2688 {
2689 /* Accept all non-symbolic constants. */
2690 if (!SYMBOLIC_CONST (op))
2691 return 1;
2692
2693 /* Reject everything else; must be handled
2694 via emit_symbolic_move. */
2695 return 0;
2696 }
2697
2698 /* Returns true if the constant value OP is a legitimate general operand.
2699 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2700
2701 static bool
2702 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2703 {
2704 /* Accept all non-symbolic constants. */
2705 if (!SYMBOLIC_CONST (op))
2706 return 1;
2707
2708 /* Accept immediate LARL operands. */
2709 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2710 return 1;
2711
2712 /* Thread-local symbols are never legal constants. This is
2713 so that emit_call knows that computing such addresses
2714 might require a function call. */
2715 if (TLS_SYMBOLIC_CONST (op))
2716 return 0;
2717
2718 /* In the PIC case, symbolic constants must *not* be
2719 forced into the literal pool. We accept them here,
2720 so that they will be handled by emit_symbolic_move. */
2721 if (flag_pic)
2722 return 1;
2723
2724 /* All remaining non-PIC symbolic constants are
2725 forced into the literal pool. */
2726 return 0;
2727 }
2728
2729 /* Determine if it's legal to put X into the constant pool. This
2730 is not possible if X contains the address of a symbol that is
2731 not constant (TLS) or not known at final link time (PIC). */
2732
2733 static bool
2734 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2735 {
2736 switch (GET_CODE (x))
2737 {
2738 case CONST_INT:
2739 case CONST_DOUBLE:
2740 /* Accept all non-symbolic constants. */
2741 return false;
2742
2743 case LABEL_REF:
2744 /* Labels are OK iff we are non-PIC. */
2745 return flag_pic != 0;
2746
2747 case SYMBOL_REF:
2748 /* 'Naked' TLS symbol references are never OK,
2749 non-TLS symbols are OK iff we are non-PIC. */
2750 if (tls_symbolic_operand (x))
2751 return true;
2752 else
2753 return flag_pic != 0;
2754
2755 case CONST:
2756 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2757 case PLUS:
2758 case MINUS:
2759 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2760 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2761
2762 case UNSPEC:
2763 switch (XINT (x, 1))
2764 {
2765 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2766 case UNSPEC_LTREL_OFFSET:
2767 case UNSPEC_GOT:
2768 case UNSPEC_GOTOFF:
2769 case UNSPEC_PLTOFF:
2770 case UNSPEC_TLSGD:
2771 case UNSPEC_TLSLDM:
2772 case UNSPEC_NTPOFF:
2773 case UNSPEC_DTPOFF:
2774 case UNSPEC_GOTNTPOFF:
2775 case UNSPEC_INDNTPOFF:
2776 return false;
2777
2778 /* If the literal pool shares the code section, be put
2779 execute template placeholders into the pool as well. */
2780 case UNSPEC_INSN:
2781 return TARGET_CPU_ZARCH;
2782
2783 default:
2784 return true;
2785 }
2786 break;
2787
2788 default:
2789 gcc_unreachable ();
2790 }
2791 }
2792
2793 /* Returns true if the constant value OP is a legitimate general
2794 operand during and after reload. The difference to
2795 legitimate_constant_p is that this function will not accept
2796 a constant that would need to be forced to the literal pool
2797 before it can be used as operand.
2798 This function accepts all constants which can be loaded directly
2799 into a GPR. */
2800
2801 bool
2802 legitimate_reload_constant_p (rtx op)
2803 {
2804 /* Accept la(y) operands. */
2805 if (GET_CODE (op) == CONST_INT
2806 && DISP_IN_RANGE (INTVAL (op)))
2807 return true;
2808
2809 /* Accept l(g)hi/l(g)fi operands. */
2810 if (GET_CODE (op) == CONST_INT
2811 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2812 return true;
2813
2814 /* Accept lliXX operands. */
2815 if (TARGET_ZARCH
2816 && GET_CODE (op) == CONST_INT
2817 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2818 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2819 return true;
2820
2821 if (TARGET_EXTIMM
2822 && GET_CODE (op) == CONST_INT
2823 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2824 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2825 return true;
2826
2827 /* Accept larl operands. */
2828 if (TARGET_CPU_ZARCH
2829 && larl_operand (op, VOIDmode))
2830 return true;
2831
2832 /* Accept floating-point zero operands that fit into a single GPR. */
2833 if (GET_CODE (op) == CONST_DOUBLE
2834 && s390_float_const_zero_p (op)
2835 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2836 return true;
2837
2838 /* Accept double-word operands that can be split. */
2839 if (GET_CODE (op) == CONST_INT
2840 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2841 {
2842 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2843 rtx hi = operand_subword (op, 0, 0, dword_mode);
2844 rtx lo = operand_subword (op, 1, 0, dword_mode);
2845 return legitimate_reload_constant_p (hi)
2846 && legitimate_reload_constant_p (lo);
2847 }
2848
2849 /* Everything else cannot be handled without reload. */
2850 return false;
2851 }
2852
2853 /* Returns true if the constant value OP is a legitimate fp operand
2854 during and after reload.
2855 This function accepts all constants which can be loaded directly
2856 into an FPR. */
2857
2858 static bool
2859 legitimate_reload_fp_constant_p (rtx op)
2860 {
2861 /* Accept floating-point zero operands if the load zero instruction
2862 can be used. */
2863 if (TARGET_Z196
2864 && GET_CODE (op) == CONST_DOUBLE
2865 && s390_float_const_zero_p (op))
2866 return true;
2867
2868 return false;
2869 }
2870
2871 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2872 return the class of reg to actually use. */
2873
2874 static reg_class_t
2875 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2876 {
2877 switch (GET_CODE (op))
2878 {
2879 /* Constants we cannot reload into general registers
2880 must be forced into the literal pool. */
2881 case CONST_DOUBLE:
2882 case CONST_INT:
2883 if (reg_class_subset_p (GENERAL_REGS, rclass)
2884 && legitimate_reload_constant_p (op))
2885 return GENERAL_REGS;
2886 else if (reg_class_subset_p (ADDR_REGS, rclass)
2887 && legitimate_reload_constant_p (op))
2888 return ADDR_REGS;
2889 else if (reg_class_subset_p (FP_REGS, rclass)
2890 && legitimate_reload_fp_constant_p (op))
2891 return FP_REGS;
2892 return NO_REGS;
2893
2894 /* If a symbolic constant or a PLUS is reloaded,
2895 it is most likely being used as an address, so
2896 prefer ADDR_REGS. If 'class' is not a superset
2897 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2898 case LABEL_REF:
2899 case SYMBOL_REF:
2900 case CONST:
2901 if (!legitimate_reload_constant_p (op))
2902 return NO_REGS;
2903 /* fallthrough */
2904 case PLUS:
2905 /* load address will be used. */
2906 if (reg_class_subset_p (ADDR_REGS, rclass))
2907 return ADDR_REGS;
2908 else
2909 return NO_REGS;
2910
2911 default:
2912 break;
2913 }
2914
2915 return rclass;
2916 }
2917
2918 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2919 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2920 aligned. */
2921
2922 bool
2923 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2924 {
2925 HOST_WIDE_INT addend;
2926 rtx symref;
2927
2928 if (!s390_symref_operand_p (addr, &symref, &addend))
2929 return false;
2930
2931 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2932 && !(addend & (alignment - 1)));
2933 }
2934
2935 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2936 operand SCRATCH is used to reload the even part of the address and
2937 adding one. */
2938
2939 void
2940 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2941 {
2942 HOST_WIDE_INT addend;
2943 rtx symref;
2944
2945 if (!s390_symref_operand_p (addr, &symref, &addend))
2946 gcc_unreachable ();
2947
2948 if (!(addend & 1))
2949 /* Easy case. The addend is even so larl will do fine. */
2950 emit_move_insn (reg, addr);
2951 else
2952 {
2953 /* We can leave the scratch register untouched if the target
2954 register is a valid base register. */
2955 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2956 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2957 scratch = reg;
2958
2959 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2960 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2961
2962 if (addend != 1)
2963 emit_move_insn (scratch,
2964 gen_rtx_CONST (Pmode,
2965 gen_rtx_PLUS (Pmode, symref,
2966 GEN_INT (addend - 1))));
2967 else
2968 emit_move_insn (scratch, symref);
2969
2970 /* Increment the address using la in order to avoid clobbering cc. */
2971 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2972 }
2973 }
2974
2975 /* Generate what is necessary to move between REG and MEM using
2976 SCRATCH. The direction is given by TOMEM. */
2977
2978 void
2979 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2980 {
2981 /* Reload might have pulled a constant out of the literal pool.
2982 Force it back in. */
2983 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2984 || GET_CODE (mem) == CONST)
2985 mem = force_const_mem (GET_MODE (reg), mem);
2986
2987 gcc_assert (MEM_P (mem));
2988
2989 /* For a load from memory we can leave the scratch register
2990 untouched if the target register is a valid base register. */
2991 if (!tomem
2992 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2993 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2994 && GET_MODE (reg) == GET_MODE (scratch))
2995 scratch = reg;
2996
2997 /* Load address into scratch register. Since we can't have a
2998 secondary reload for a secondary reload we have to cover the case
2999 where larl would need a secondary reload here as well. */
3000 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3001
3002 /* Now we can use a standard load/store to do the move. */
3003 if (tomem)
3004 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3005 else
3006 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3007 }
3008
3009 /* Inform reload about cases where moving X with a mode MODE to a register in
3010 RCLASS requires an extra scratch or immediate register. Return the class
3011 needed for the immediate register. */
3012
3013 static reg_class_t
3014 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3015 enum machine_mode mode, secondary_reload_info *sri)
3016 {
3017 enum reg_class rclass = (enum reg_class) rclass_i;
3018
3019 /* Intermediate register needed. */
3020 if (reg_classes_intersect_p (CC_REGS, rclass))
3021 return GENERAL_REGS;
3022
3023 if (TARGET_Z10)
3024 {
3025 HOST_WIDE_INT offset;
3026 rtx symref;
3027
3028 /* On z10 several optimizer steps may generate larl operands with
3029 an odd addend. */
3030 if (in_p
3031 && s390_symref_operand_p (x, &symref, &offset)
3032 && mode == Pmode
3033 && !SYMBOL_REF_ALIGN1_P (symref)
3034 && (offset & 1) == 1)
3035 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3036 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3037
3038 /* On z10 we need a scratch register when moving QI, TI or floating
3039 point mode values from or to a memory location with a SYMBOL_REF
3040 or if the symref addend of a SI or DI move is not aligned to the
3041 width of the access. */
3042 if (MEM_P (x)
3043 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3044 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3045 || (!TARGET_ZARCH && mode == DImode)
3046 || ((mode == HImode || mode == SImode || mode == DImode)
3047 && (!s390_check_symref_alignment (XEXP (x, 0),
3048 GET_MODE_SIZE (mode))))))
3049 {
3050 #define __SECONDARY_RELOAD_CASE(M,m) \
3051 case M##mode: \
3052 if (TARGET_64BIT) \
3053 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3054 CODE_FOR_reload##m##di_tomem_z10; \
3055 else \
3056 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3057 CODE_FOR_reload##m##si_tomem_z10; \
3058 break;
3059
3060 switch (GET_MODE (x))
3061 {
3062 __SECONDARY_RELOAD_CASE (QI, qi);
3063 __SECONDARY_RELOAD_CASE (HI, hi);
3064 __SECONDARY_RELOAD_CASE (SI, si);
3065 __SECONDARY_RELOAD_CASE (DI, di);
3066 __SECONDARY_RELOAD_CASE (TI, ti);
3067 __SECONDARY_RELOAD_CASE (SF, sf);
3068 __SECONDARY_RELOAD_CASE (DF, df);
3069 __SECONDARY_RELOAD_CASE (TF, tf);
3070 __SECONDARY_RELOAD_CASE (SD, sd);
3071 __SECONDARY_RELOAD_CASE (DD, dd);
3072 __SECONDARY_RELOAD_CASE (TD, td);
3073
3074 default:
3075 gcc_unreachable ();
3076 }
3077 #undef __SECONDARY_RELOAD_CASE
3078 }
3079 }
3080
3081 /* We need a scratch register when loading a PLUS expression which
3082 is not a legitimate operand of the LOAD ADDRESS instruction. */
3083 if (in_p && s390_plus_operand (x, mode))
3084 sri->icode = (TARGET_64BIT ?
3085 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3086
3087 /* Performing a multiword move from or to memory we have to make sure the
3088 second chunk in memory is addressable without causing a displacement
3089 overflow. If that would be the case we calculate the address in
3090 a scratch register. */
3091 if (MEM_P (x)
3092 && GET_CODE (XEXP (x, 0)) == PLUS
3093 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3094 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3095 + GET_MODE_SIZE (mode) - 1))
3096 {
3097 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3098 in a s_operand address since we may fallback to lm/stm. So we only
3099 have to care about overflows in the b+i+d case. */
3100 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3101 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3102 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3103 /* For FP_REGS no lm/stm is available so this check is triggered
3104 for displacement overflows in b+i+d and b+d like addresses. */
3105 || (reg_classes_intersect_p (FP_REGS, rclass)
3106 && s390_class_max_nregs (FP_REGS, mode) > 1))
3107 {
3108 if (in_p)
3109 sri->icode = (TARGET_64BIT ?
3110 CODE_FOR_reloaddi_nonoffmem_in :
3111 CODE_FOR_reloadsi_nonoffmem_in);
3112 else
3113 sri->icode = (TARGET_64BIT ?
3114 CODE_FOR_reloaddi_nonoffmem_out :
3115 CODE_FOR_reloadsi_nonoffmem_out);
3116 }
3117 }
3118
3119 /* A scratch address register is needed when a symbolic constant is
3120 copied to r0 compiling with -fPIC. In other cases the target
3121 register might be used as temporary (see legitimize_pic_address). */
3122 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3123 sri->icode = (TARGET_64BIT ?
3124 CODE_FOR_reloaddi_PIC_addr :
3125 CODE_FOR_reloadsi_PIC_addr);
3126
3127 /* Either scratch or no register needed. */
3128 return NO_REGS;
3129 }
3130
3131 /* Generate code to load SRC, which is PLUS that is not a
3132 legitimate operand for the LA instruction, into TARGET.
3133 SCRATCH may be used as scratch register. */
3134
3135 void
3136 s390_expand_plus_operand (rtx target, rtx src,
3137 rtx scratch)
3138 {
3139 rtx sum1, sum2;
3140 struct s390_address ad;
3141
3142 /* src must be a PLUS; get its two operands. */
3143 gcc_assert (GET_CODE (src) == PLUS);
3144 gcc_assert (GET_MODE (src) == Pmode);
3145
3146 /* Check if any of the two operands is already scheduled
3147 for replacement by reload. This can happen e.g. when
3148 float registers occur in an address. */
3149 sum1 = find_replacement (&XEXP (src, 0));
3150 sum2 = find_replacement (&XEXP (src, 1));
3151 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3152
3153 /* If the address is already strictly valid, there's nothing to do. */
3154 if (!s390_decompose_address (src, &ad)
3155 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3156 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3157 {
3158 /* Otherwise, one of the operands cannot be an address register;
3159 we reload its value into the scratch register. */
3160 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3161 {
3162 emit_move_insn (scratch, sum1);
3163 sum1 = scratch;
3164 }
3165 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3166 {
3167 emit_move_insn (scratch, sum2);
3168 sum2 = scratch;
3169 }
3170
3171 /* According to the way these invalid addresses are generated
3172 in reload.c, it should never happen (at least on s390) that
3173 *neither* of the PLUS components, after find_replacements
3174 was applied, is an address register. */
3175 if (sum1 == scratch && sum2 == scratch)
3176 {
3177 debug_rtx (src);
3178 gcc_unreachable ();
3179 }
3180
3181 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3182 }
3183
3184 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3185 is only ever performed on addresses, so we can mark the
3186 sum as legitimate for LA in any case. */
3187 s390_load_address (target, src);
3188 }
3189
3190
3191 /* Return true if ADDR is a valid memory address.
3192 STRICT specifies whether strict register checking applies. */
3193
3194 static bool
3195 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3196 {
3197 struct s390_address ad;
3198
3199 if (TARGET_Z10
3200 && larl_operand (addr, VOIDmode)
3201 && (mode == VOIDmode
3202 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3203 return true;
3204
3205 if (!s390_decompose_address (addr, &ad))
3206 return false;
3207
3208 if (strict)
3209 {
3210 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3211 return false;
3212
3213 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3214 return false;
3215 }
3216 else
3217 {
3218 if (ad.base
3219 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3220 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3221 return false;
3222
3223 if (ad.indx
3224 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3225 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3226 return false;
3227 }
3228 return true;
3229 }
3230
3231 /* Return true if OP is a valid operand for the LA instruction.
3232 In 31-bit, we need to prove that the result is used as an
3233 address, as LA performs only a 31-bit addition. */
3234
3235 bool
3236 legitimate_la_operand_p (rtx op)
3237 {
3238 struct s390_address addr;
3239 if (!s390_decompose_address (op, &addr))
3240 return false;
3241
3242 return (TARGET_64BIT || addr.pointer);
3243 }
3244
3245 /* Return true if it is valid *and* preferable to use LA to
3246 compute the sum of OP1 and OP2. */
3247
3248 bool
3249 preferred_la_operand_p (rtx op1, rtx op2)
3250 {
3251 struct s390_address addr;
3252
3253 if (op2 != const0_rtx)
3254 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3255
3256 if (!s390_decompose_address (op1, &addr))
3257 return false;
3258 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3259 return false;
3260 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3261 return false;
3262
3263 /* Avoid LA instructions with index register on z196; it is
3264 preferable to use regular add instructions when possible. */
3265 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3266 return false;
3267
3268 if (!TARGET_64BIT && !addr.pointer)
3269 return false;
3270
3271 if (addr.pointer)
3272 return true;
3273
3274 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3275 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3276 return true;
3277
3278 return false;
3279 }
3280
3281 /* Emit a forced load-address operation to load SRC into DST.
3282 This will use the LOAD ADDRESS instruction even in situations
3283 where legitimate_la_operand_p (SRC) returns false. */
3284
3285 void
3286 s390_load_address (rtx dst, rtx src)
3287 {
3288 if (TARGET_64BIT)
3289 emit_move_insn (dst, src);
3290 else
3291 emit_insn (gen_force_la_31 (dst, src));
3292 }
3293
3294 /* Return a legitimate reference for ORIG (an address) using the
3295 register REG. If REG is 0, a new pseudo is generated.
3296
3297 There are two types of references that must be handled:
3298
3299 1. Global data references must load the address from the GOT, via
3300 the PIC reg. An insn is emitted to do this load, and the reg is
3301 returned.
3302
3303 2. Static data references, constant pool addresses, and code labels
3304 compute the address as an offset from the GOT, whose base is in
3305 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3306 differentiate them from global data objects. The returned
3307 address is the PIC reg + an unspec constant.
3308
3309 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3310 reg also appears in the address. */
3311
3312 rtx
3313 legitimize_pic_address (rtx orig, rtx reg)
3314 {
3315 rtx addr = orig;
3316 rtx new_rtx = orig;
3317 rtx base;
3318
3319 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3320
3321 if (GET_CODE (addr) == LABEL_REF
3322 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3323 {
3324 /* This is a local symbol. */
3325 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3326 {
3327 /* Access local symbols PC-relative via LARL.
3328 This is the same as in the non-PIC case, so it is
3329 handled automatically ... */
3330 }
3331 else
3332 {
3333 /* Access local symbols relative to the GOT. */
3334
3335 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3336
3337 if (reload_in_progress || reload_completed)
3338 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3339
3340 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3341 addr = gen_rtx_CONST (Pmode, addr);
3342 addr = force_const_mem (Pmode, addr);
3343 emit_move_insn (temp, addr);
3344
3345 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3346 if (reg != 0)
3347 {
3348 s390_load_address (reg, new_rtx);
3349 new_rtx = reg;
3350 }
3351 }
3352 }
3353 else if (GET_CODE (addr) == SYMBOL_REF)
3354 {
3355 if (reg == 0)
3356 reg = gen_reg_rtx (Pmode);
3357
3358 if (flag_pic == 1)
3359 {
3360 /* Assume GOT offset < 4k. This is handled the same way
3361 in both 31- and 64-bit code (@GOT). */
3362
3363 if (reload_in_progress || reload_completed)
3364 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3365
3366 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3367 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3368 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3369 new_rtx = gen_const_mem (Pmode, new_rtx);
3370 emit_move_insn (reg, new_rtx);
3371 new_rtx = reg;
3372 }
3373 else if (TARGET_CPU_ZARCH)
3374 {
3375 /* If the GOT offset might be >= 4k, we determine the position
3376 of the GOT entry via a PC-relative LARL (@GOTENT). */
3377
3378 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3379
3380 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3381 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3382
3383 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3384 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3385 emit_move_insn (temp, new_rtx);
3386
3387 new_rtx = gen_const_mem (Pmode, temp);
3388 emit_move_insn (reg, new_rtx);
3389 new_rtx = reg;
3390 }
3391 else
3392 {
3393 /* If the GOT offset might be >= 4k, we have to load it
3394 from the literal pool (@GOT). */
3395
3396 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3397
3398 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3399 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3400
3401 if (reload_in_progress || reload_completed)
3402 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3403
3404 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3405 addr = gen_rtx_CONST (Pmode, addr);
3406 addr = force_const_mem (Pmode, addr);
3407 emit_move_insn (temp, addr);
3408
3409 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3410 new_rtx = gen_const_mem (Pmode, new_rtx);
3411 emit_move_insn (reg, new_rtx);
3412 new_rtx = reg;
3413 }
3414 }
3415 else
3416 {
3417 if (GET_CODE (addr) == CONST)
3418 {
3419 addr = XEXP (addr, 0);
3420 if (GET_CODE (addr) == UNSPEC)
3421 {
3422 gcc_assert (XVECLEN (addr, 0) == 1);
3423 switch (XINT (addr, 1))
3424 {
3425 /* If someone moved a GOT-relative UNSPEC
3426 out of the literal pool, force them back in. */
3427 case UNSPEC_GOTOFF:
3428 case UNSPEC_PLTOFF:
3429 new_rtx = force_const_mem (Pmode, orig);
3430 break;
3431
3432 /* @GOT is OK as is if small. */
3433 case UNSPEC_GOT:
3434 if (flag_pic == 2)
3435 new_rtx = force_const_mem (Pmode, orig);
3436 break;
3437
3438 /* @GOTENT is OK as is. */
3439 case UNSPEC_GOTENT:
3440 break;
3441
3442 /* @PLT is OK as is on 64-bit, must be converted to
3443 GOT-relative @PLTOFF on 31-bit. */
3444 case UNSPEC_PLT:
3445 if (!TARGET_CPU_ZARCH)
3446 {
3447 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3448
3449 if (reload_in_progress || reload_completed)
3450 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3451
3452 addr = XVECEXP (addr, 0, 0);
3453 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3454 UNSPEC_PLTOFF);
3455 addr = gen_rtx_CONST (Pmode, addr);
3456 addr = force_const_mem (Pmode, addr);
3457 emit_move_insn (temp, addr);
3458
3459 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3460 if (reg != 0)
3461 {
3462 s390_load_address (reg, new_rtx);
3463 new_rtx = reg;
3464 }
3465 }
3466 break;
3467
3468 /* Everything else cannot happen. */
3469 default:
3470 gcc_unreachable ();
3471 }
3472 }
3473 else
3474 gcc_assert (GET_CODE (addr) == PLUS);
3475 }
3476 if (GET_CODE (addr) == PLUS)
3477 {
3478 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3479
3480 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3481 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3482
3483 /* Check first to see if this is a constant offset
3484 from a local symbol reference. */
3485 if ((GET_CODE (op0) == LABEL_REF
3486 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3487 && GET_CODE (op1) == CONST_INT)
3488 {
3489 if (TARGET_CPU_ZARCH
3490 && larl_operand (op0, VOIDmode)
3491 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3492 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3493 {
3494 if (INTVAL (op1) & 1)
3495 {
3496 /* LARL can't handle odd offsets, so emit a
3497 pair of LARL and LA. */
3498 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3499
3500 if (!DISP_IN_RANGE (INTVAL (op1)))
3501 {
3502 HOST_WIDE_INT even = INTVAL (op1) - 1;
3503 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3504 op0 = gen_rtx_CONST (Pmode, op0);
3505 op1 = const1_rtx;
3506 }
3507
3508 emit_move_insn (temp, op0);
3509 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3510
3511 if (reg != 0)
3512 {
3513 s390_load_address (reg, new_rtx);
3514 new_rtx = reg;
3515 }
3516 }
3517 else
3518 {
3519 /* If the offset is even, we can just use LARL.
3520 This will happen automatically. */
3521 }
3522 }
3523 else
3524 {
3525 /* Access local symbols relative to the GOT. */
3526
3527 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3528
3529 if (reload_in_progress || reload_completed)
3530 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3531
3532 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3533 UNSPEC_GOTOFF);
3534 addr = gen_rtx_PLUS (Pmode, addr, op1);
3535 addr = gen_rtx_CONST (Pmode, addr);
3536 addr = force_const_mem (Pmode, addr);
3537 emit_move_insn (temp, addr);
3538
3539 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3540 if (reg != 0)
3541 {
3542 s390_load_address (reg, new_rtx);
3543 new_rtx = reg;
3544 }
3545 }
3546 }
3547
3548 /* Now, check whether it is a GOT relative symbol plus offset
3549 that was pulled out of the literal pool. Force it back in. */
3550
3551 else if (GET_CODE (op0) == UNSPEC
3552 && GET_CODE (op1) == CONST_INT
3553 && XINT (op0, 1) == UNSPEC_GOTOFF)
3554 {
3555 gcc_assert (XVECLEN (op0, 0) == 1);
3556
3557 new_rtx = force_const_mem (Pmode, orig);
3558 }
3559
3560 /* Otherwise, compute the sum. */
3561 else
3562 {
3563 base = legitimize_pic_address (XEXP (addr, 0), reg);
3564 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3565 base == reg ? NULL_RTX : reg);
3566 if (GET_CODE (new_rtx) == CONST_INT)
3567 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3568 else
3569 {
3570 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3571 {
3572 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3573 new_rtx = XEXP (new_rtx, 1);
3574 }
3575 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3576 }
3577
3578 if (GET_CODE (new_rtx) == CONST)
3579 new_rtx = XEXP (new_rtx, 0);
3580 new_rtx = force_operand (new_rtx, 0);
3581 }
3582 }
3583 }
3584 return new_rtx;
3585 }
3586
3587 /* Load the thread pointer into a register. */
3588
3589 rtx
3590 s390_get_thread_pointer (void)
3591 {
3592 rtx tp = gen_reg_rtx (Pmode);
3593
3594 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3595 mark_reg_pointer (tp, BITS_PER_WORD);
3596
3597 return tp;
3598 }
3599
3600 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3601 in s390_tls_symbol which always refers to __tls_get_offset.
3602 The returned offset is written to RESULT_REG and an USE rtx is
3603 generated for TLS_CALL. */
3604
3605 static GTY(()) rtx s390_tls_symbol;
3606
3607 static void
3608 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3609 {
3610 rtx insn;
3611
3612 if (!flag_pic)
3613 emit_insn (s390_load_got ());
3614
3615 if (!s390_tls_symbol)
3616 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3617
3618 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3619 gen_rtx_REG (Pmode, RETURN_REGNUM));
3620
3621 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3622 RTL_CONST_CALL_P (insn) = 1;
3623 }
3624
3625 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3626 this (thread-local) address. REG may be used as temporary. */
3627
3628 static rtx
3629 legitimize_tls_address (rtx addr, rtx reg)
3630 {
3631 rtx new_rtx, tls_call, temp, base, r2, insn;
3632
3633 if (GET_CODE (addr) == SYMBOL_REF)
3634 switch (tls_symbolic_operand (addr))
3635 {
3636 case TLS_MODEL_GLOBAL_DYNAMIC:
3637 start_sequence ();
3638 r2 = gen_rtx_REG (Pmode, 2);
3639 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3640 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3641 new_rtx = force_const_mem (Pmode, new_rtx);
3642 emit_move_insn (r2, new_rtx);
3643 s390_emit_tls_call_insn (r2, tls_call);
3644 insn = get_insns ();
3645 end_sequence ();
3646
3647 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3648 temp = gen_reg_rtx (Pmode);
3649 emit_libcall_block (insn, temp, r2, new_rtx);
3650
3651 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3652 if (reg != 0)
3653 {
3654 s390_load_address (reg, new_rtx);
3655 new_rtx = reg;
3656 }
3657 break;
3658
3659 case TLS_MODEL_LOCAL_DYNAMIC:
3660 start_sequence ();
3661 r2 = gen_rtx_REG (Pmode, 2);
3662 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3663 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3664 new_rtx = force_const_mem (Pmode, new_rtx);
3665 emit_move_insn (r2, new_rtx);
3666 s390_emit_tls_call_insn (r2, tls_call);
3667 insn = get_insns ();
3668 end_sequence ();
3669
3670 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3671 temp = gen_reg_rtx (Pmode);
3672 emit_libcall_block (insn, temp, r2, new_rtx);
3673
3674 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3675 base = gen_reg_rtx (Pmode);
3676 s390_load_address (base, new_rtx);
3677
3678 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3679 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3680 new_rtx = force_const_mem (Pmode, new_rtx);
3681 temp = gen_reg_rtx (Pmode);
3682 emit_move_insn (temp, new_rtx);
3683
3684 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3685 if (reg != 0)
3686 {
3687 s390_load_address (reg, new_rtx);
3688 new_rtx = reg;
3689 }
3690 break;
3691
3692 case TLS_MODEL_INITIAL_EXEC:
3693 if (flag_pic == 1)
3694 {
3695 /* Assume GOT offset < 4k. This is handled the same way
3696 in both 31- and 64-bit code. */
3697
3698 if (reload_in_progress || reload_completed)
3699 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3700
3701 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3702 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3703 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3704 new_rtx = gen_const_mem (Pmode, new_rtx);
3705 temp = gen_reg_rtx (Pmode);
3706 emit_move_insn (temp, new_rtx);
3707 }
3708 else if (TARGET_CPU_ZARCH)
3709 {
3710 /* If the GOT offset might be >= 4k, we determine the position
3711 of the GOT entry via a PC-relative LARL. */
3712
3713 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3714 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3715 temp = gen_reg_rtx (Pmode);
3716 emit_move_insn (temp, new_rtx);
3717
3718 new_rtx = gen_const_mem (Pmode, temp);
3719 temp = gen_reg_rtx (Pmode);
3720 emit_move_insn (temp, new_rtx);
3721 }
3722 else if (flag_pic)
3723 {
3724 /* If the GOT offset might be >= 4k, we have to load it
3725 from the literal pool. */
3726
3727 if (reload_in_progress || reload_completed)
3728 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3729
3730 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3731 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3732 new_rtx = force_const_mem (Pmode, new_rtx);
3733 temp = gen_reg_rtx (Pmode);
3734 emit_move_insn (temp, new_rtx);
3735
3736 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3737 new_rtx = gen_const_mem (Pmode, new_rtx);
3738
3739 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3740 temp = gen_reg_rtx (Pmode);
3741 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3742 }
3743 else
3744 {
3745 /* In position-dependent code, load the absolute address of
3746 the GOT entry from the literal pool. */
3747
3748 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3749 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3750 new_rtx = force_const_mem (Pmode, new_rtx);
3751 temp = gen_reg_rtx (Pmode);
3752 emit_move_insn (temp, new_rtx);
3753
3754 new_rtx = temp;
3755 new_rtx = gen_const_mem (Pmode, new_rtx);
3756 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3757 temp = gen_reg_rtx (Pmode);
3758 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3759 }
3760
3761 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3762 if (reg != 0)
3763 {
3764 s390_load_address (reg, new_rtx);
3765 new_rtx = reg;
3766 }
3767 break;
3768
3769 case TLS_MODEL_LOCAL_EXEC:
3770 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3771 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3772 new_rtx = force_const_mem (Pmode, new_rtx);
3773 temp = gen_reg_rtx (Pmode);
3774 emit_move_insn (temp, new_rtx);
3775
3776 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3777 if (reg != 0)
3778 {
3779 s390_load_address (reg, new_rtx);
3780 new_rtx = reg;
3781 }
3782 break;
3783
3784 default:
3785 gcc_unreachable ();
3786 }
3787
3788 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3789 {
3790 switch (XINT (XEXP (addr, 0), 1))
3791 {
3792 case UNSPEC_INDNTPOFF:
3793 gcc_assert (TARGET_CPU_ZARCH);
3794 new_rtx = addr;
3795 break;
3796
3797 default:
3798 gcc_unreachable ();
3799 }
3800 }
3801
3802 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3803 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3804 {
3805 new_rtx = XEXP (XEXP (addr, 0), 0);
3806 if (GET_CODE (new_rtx) != SYMBOL_REF)
3807 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3808
3809 new_rtx = legitimize_tls_address (new_rtx, reg);
3810 new_rtx = plus_constant (Pmode, new_rtx,
3811 INTVAL (XEXP (XEXP (addr, 0), 1)));
3812 new_rtx = force_operand (new_rtx, 0);
3813 }
3814
3815 else
3816 gcc_unreachable (); /* for now ... */
3817
3818 return new_rtx;
3819 }
3820
3821 /* Emit insns making the address in operands[1] valid for a standard
3822 move to operands[0]. operands[1] is replaced by an address which
3823 should be used instead of the former RTX to emit the move
3824 pattern. */
3825
3826 void
3827 emit_symbolic_move (rtx *operands)
3828 {
3829 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3830
3831 if (GET_CODE (operands[0]) == MEM)
3832 operands[1] = force_reg (Pmode, operands[1]);
3833 else if (TLS_SYMBOLIC_CONST (operands[1]))
3834 operands[1] = legitimize_tls_address (operands[1], temp);
3835 else if (flag_pic)
3836 operands[1] = legitimize_pic_address (operands[1], temp);
3837 }
3838
3839 /* Try machine-dependent ways of modifying an illegitimate address X
3840 to be legitimate. If we find one, return the new, valid address.
3841
3842 OLDX is the address as it was before break_out_memory_refs was called.
3843 In some cases it is useful to look at this to decide what needs to be done.
3844
3845 MODE is the mode of the operand pointed to by X.
3846
3847 When -fpic is used, special handling is needed for symbolic references.
3848 See comments by legitimize_pic_address for details. */
3849
3850 static rtx
3851 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3852 enum machine_mode mode ATTRIBUTE_UNUSED)
3853 {
3854 rtx constant_term = const0_rtx;
3855
3856 if (TLS_SYMBOLIC_CONST (x))
3857 {
3858 x = legitimize_tls_address (x, 0);
3859
3860 if (s390_legitimate_address_p (mode, x, FALSE))
3861 return x;
3862 }
3863 else if (GET_CODE (x) == PLUS
3864 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3865 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3866 {
3867 return x;
3868 }
3869 else if (flag_pic)
3870 {
3871 if (SYMBOLIC_CONST (x)
3872 || (GET_CODE (x) == PLUS
3873 && (SYMBOLIC_CONST (XEXP (x, 0))
3874 || SYMBOLIC_CONST (XEXP (x, 1)))))
3875 x = legitimize_pic_address (x, 0);
3876
3877 if (s390_legitimate_address_p (mode, x, FALSE))
3878 return x;
3879 }
3880
3881 x = eliminate_constant_term (x, &constant_term);
3882
3883 /* Optimize loading of large displacements by splitting them
3884 into the multiple of 4K and the rest; this allows the
3885 former to be CSE'd if possible.
3886
3887 Don't do this if the displacement is added to a register
3888 pointing into the stack frame, as the offsets will
3889 change later anyway. */
3890
3891 if (GET_CODE (constant_term) == CONST_INT
3892 && !TARGET_LONG_DISPLACEMENT
3893 && !DISP_IN_RANGE (INTVAL (constant_term))
3894 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3895 {
3896 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3897 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3898
3899 rtx temp = gen_reg_rtx (Pmode);
3900 rtx val = force_operand (GEN_INT (upper), temp);
3901 if (val != temp)
3902 emit_move_insn (temp, val);
3903
3904 x = gen_rtx_PLUS (Pmode, x, temp);
3905 constant_term = GEN_INT (lower);
3906 }
3907
3908 if (GET_CODE (x) == PLUS)
3909 {
3910 if (GET_CODE (XEXP (x, 0)) == REG)
3911 {
3912 rtx temp = gen_reg_rtx (Pmode);
3913 rtx val = force_operand (XEXP (x, 1), temp);
3914 if (val != temp)
3915 emit_move_insn (temp, val);
3916
3917 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3918 }
3919
3920 else if (GET_CODE (XEXP (x, 1)) == REG)
3921 {
3922 rtx temp = gen_reg_rtx (Pmode);
3923 rtx val = force_operand (XEXP (x, 0), temp);
3924 if (val != temp)
3925 emit_move_insn (temp, val);
3926
3927 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3928 }
3929 }
3930
3931 if (constant_term != const0_rtx)
3932 x = gen_rtx_PLUS (Pmode, x, constant_term);
3933
3934 return x;
3935 }
3936
3937 /* Try a machine-dependent way of reloading an illegitimate address AD
3938 operand. If we find one, push the reload and return the new address.
3939
3940 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3941 and TYPE is the reload type of the current reload. */
3942
3943 rtx
3944 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3945 int opnum, int type)
3946 {
3947 if (!optimize || TARGET_LONG_DISPLACEMENT)
3948 return NULL_RTX;
3949
3950 if (GET_CODE (ad) == PLUS)
3951 {
3952 rtx tem = simplify_binary_operation (PLUS, Pmode,
3953 XEXP (ad, 0), XEXP (ad, 1));
3954 if (tem)
3955 ad = tem;
3956 }
3957
3958 if (GET_CODE (ad) == PLUS
3959 && GET_CODE (XEXP (ad, 0)) == REG
3960 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3961 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3962 {
3963 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3964 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3965 rtx cst, tem, new_rtx;
3966
3967 cst = GEN_INT (upper);
3968 if (!legitimate_reload_constant_p (cst))
3969 cst = force_const_mem (Pmode, cst);
3970
3971 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3972 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3973
3974 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3975 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3976 opnum, (enum reload_type) type);
3977 return new_rtx;
3978 }
3979
3980 return NULL_RTX;
3981 }
3982
3983 /* Emit code to move LEN bytes from DST to SRC. */
3984
3985 void
3986 s390_expand_movmem (rtx dst, rtx src, rtx len)
3987 {
3988 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3989 {
3990 if (INTVAL (len) > 0)
3991 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3992 }
3993
3994 else if (TARGET_MVCLE)
3995 {
3996 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3997 }
3998
3999 else
4000 {
4001 rtx dst_addr, src_addr, count, blocks, temp;
4002 rtx loop_start_label = gen_label_rtx ();
4003 rtx loop_end_label = gen_label_rtx ();
4004 rtx end_label = gen_label_rtx ();
4005 enum machine_mode mode;
4006
4007 mode = GET_MODE (len);
4008 if (mode == VOIDmode)
4009 mode = Pmode;
4010
4011 dst_addr = gen_reg_rtx (Pmode);
4012 src_addr = gen_reg_rtx (Pmode);
4013 count = gen_reg_rtx (mode);
4014 blocks = gen_reg_rtx (mode);
4015
4016 convert_move (count, len, 1);
4017 emit_cmp_and_jump_insns (count, const0_rtx,
4018 EQ, NULL_RTX, mode, 1, end_label);
4019
4020 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4021 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4022 dst = change_address (dst, VOIDmode, dst_addr);
4023 src = change_address (src, VOIDmode, src_addr);
4024
4025 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4026 OPTAB_DIRECT);
4027 if (temp != count)
4028 emit_move_insn (count, temp);
4029
4030 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4031 OPTAB_DIRECT);
4032 if (temp != blocks)
4033 emit_move_insn (blocks, temp);
4034
4035 emit_cmp_and_jump_insns (blocks, const0_rtx,
4036 EQ, NULL_RTX, mode, 1, loop_end_label);
4037
4038 emit_label (loop_start_label);
4039
4040 if (TARGET_Z10
4041 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4042 {
4043 rtx prefetch;
4044
4045 /* Issue a read prefetch for the +3 cache line. */
4046 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4047 const0_rtx, const0_rtx);
4048 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4049 emit_insn (prefetch);
4050
4051 /* Issue a write prefetch for the +3 cache line. */
4052 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4053 const1_rtx, const0_rtx);
4054 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4055 emit_insn (prefetch);
4056 }
4057
4058 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4059 s390_load_address (dst_addr,
4060 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4061 s390_load_address (src_addr,
4062 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4063
4064 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4065 OPTAB_DIRECT);
4066 if (temp != blocks)
4067 emit_move_insn (blocks, temp);
4068
4069 emit_cmp_and_jump_insns (blocks, const0_rtx,
4070 EQ, NULL_RTX, mode, 1, loop_end_label);
4071
4072 emit_jump (loop_start_label);
4073 emit_label (loop_end_label);
4074
4075 emit_insn (gen_movmem_short (dst, src,
4076 convert_to_mode (Pmode, count, 1)));
4077 emit_label (end_label);
4078 }
4079 }
4080
4081 /* Emit code to set LEN bytes at DST to VAL.
4082 Make use of clrmem if VAL is zero. */
4083
4084 void
4085 s390_expand_setmem (rtx dst, rtx len, rtx val)
4086 {
4087 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4088 return;
4089
4090 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4091
4092 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4093 {
4094 if (val == const0_rtx && INTVAL (len) <= 256)
4095 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4096 else
4097 {
4098 /* Initialize memory by storing the first byte. */
4099 emit_move_insn (adjust_address (dst, QImode, 0), val);
4100
4101 if (INTVAL (len) > 1)
4102 {
4103 /* Initiate 1 byte overlap move.
4104 The first byte of DST is propagated through DSTP1.
4105 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4106 DST is set to size 1 so the rest of the memory location
4107 does not count as source operand. */
4108 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4109 set_mem_size (dst, 1);
4110
4111 emit_insn (gen_movmem_short (dstp1, dst,
4112 GEN_INT (INTVAL (len) - 2)));
4113 }
4114 }
4115 }
4116
4117 else if (TARGET_MVCLE)
4118 {
4119 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4120 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4121 }
4122
4123 else
4124 {
4125 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4126 rtx loop_start_label = gen_label_rtx ();
4127 rtx loop_end_label = gen_label_rtx ();
4128 rtx end_label = gen_label_rtx ();
4129 enum machine_mode mode;
4130
4131 mode = GET_MODE (len);
4132 if (mode == VOIDmode)
4133 mode = Pmode;
4134
4135 dst_addr = gen_reg_rtx (Pmode);
4136 count = gen_reg_rtx (mode);
4137 blocks = gen_reg_rtx (mode);
4138
4139 convert_move (count, len, 1);
4140 emit_cmp_and_jump_insns (count, const0_rtx,
4141 EQ, NULL_RTX, mode, 1, end_label);
4142
4143 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4144 dst = change_address (dst, VOIDmode, dst_addr);
4145
4146 if (val == const0_rtx)
4147 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4148 OPTAB_DIRECT);
4149 else
4150 {
4151 dstp1 = adjust_address (dst, VOIDmode, 1);
4152 set_mem_size (dst, 1);
4153
4154 /* Initialize memory by storing the first byte. */
4155 emit_move_insn (adjust_address (dst, QImode, 0), val);
4156
4157 /* If count is 1 we are done. */
4158 emit_cmp_and_jump_insns (count, const1_rtx,
4159 EQ, NULL_RTX, mode, 1, end_label);
4160
4161 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4162 OPTAB_DIRECT);
4163 }
4164 if (temp != count)
4165 emit_move_insn (count, temp);
4166
4167 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4168 OPTAB_DIRECT);
4169 if (temp != blocks)
4170 emit_move_insn (blocks, temp);
4171
4172 emit_cmp_and_jump_insns (blocks, const0_rtx,
4173 EQ, NULL_RTX, mode, 1, loop_end_label);
4174
4175 emit_label (loop_start_label);
4176
4177 if (TARGET_Z10
4178 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4179 {
4180 /* Issue a write prefetch for the +4 cache line. */
4181 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4182 GEN_INT (1024)),
4183 const1_rtx, const0_rtx);
4184 emit_insn (prefetch);
4185 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4186 }
4187
4188 if (val == const0_rtx)
4189 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4190 else
4191 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4192 s390_load_address (dst_addr,
4193 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4194
4195 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4196 OPTAB_DIRECT);
4197 if (temp != blocks)
4198 emit_move_insn (blocks, temp);
4199
4200 emit_cmp_and_jump_insns (blocks, const0_rtx,
4201 EQ, NULL_RTX, mode, 1, loop_end_label);
4202
4203 emit_jump (loop_start_label);
4204 emit_label (loop_end_label);
4205
4206 if (val == const0_rtx)
4207 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4208 else
4209 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4210 emit_label (end_label);
4211 }
4212 }
4213
4214 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4215 and return the result in TARGET. */
4216
4217 void
4218 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4219 {
4220 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4221 rtx tmp;
4222
4223 /* As the result of CMPINT is inverted compared to what we need,
4224 we have to swap the operands. */
4225 tmp = op0; op0 = op1; op1 = tmp;
4226
4227 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4228 {
4229 if (INTVAL (len) > 0)
4230 {
4231 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4232 emit_insn (gen_cmpint (target, ccreg));
4233 }
4234 else
4235 emit_move_insn (target, const0_rtx);
4236 }
4237 else if (TARGET_MVCLE)
4238 {
4239 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4240 emit_insn (gen_cmpint (target, ccreg));
4241 }
4242 else
4243 {
4244 rtx addr0, addr1, count, blocks, temp;
4245 rtx loop_start_label = gen_label_rtx ();
4246 rtx loop_end_label = gen_label_rtx ();
4247 rtx end_label = gen_label_rtx ();
4248 enum machine_mode mode;
4249
4250 mode = GET_MODE (len);
4251 if (mode == VOIDmode)
4252 mode = Pmode;
4253
4254 addr0 = gen_reg_rtx (Pmode);
4255 addr1 = gen_reg_rtx (Pmode);
4256 count = gen_reg_rtx (mode);
4257 blocks = gen_reg_rtx (mode);
4258
4259 convert_move (count, len, 1);
4260 emit_cmp_and_jump_insns (count, const0_rtx,
4261 EQ, NULL_RTX, mode, 1, end_label);
4262
4263 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4264 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4265 op0 = change_address (op0, VOIDmode, addr0);
4266 op1 = change_address (op1, VOIDmode, addr1);
4267
4268 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4269 OPTAB_DIRECT);
4270 if (temp != count)
4271 emit_move_insn (count, temp);
4272
4273 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4274 OPTAB_DIRECT);
4275 if (temp != blocks)
4276 emit_move_insn (blocks, temp);
4277
4278 emit_cmp_and_jump_insns (blocks, const0_rtx,
4279 EQ, NULL_RTX, mode, 1, loop_end_label);
4280
4281 emit_label (loop_start_label);
4282
4283 if (TARGET_Z10
4284 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4285 {
4286 rtx prefetch;
4287
4288 /* Issue a read prefetch for the +2 cache line of operand 1. */
4289 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4290 const0_rtx, const0_rtx);
4291 emit_insn (prefetch);
4292 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4293
4294 /* Issue a read prefetch for the +2 cache line of operand 2. */
4295 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4296 const0_rtx, const0_rtx);
4297 emit_insn (prefetch);
4298 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4299 }
4300
4301 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4302 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4303 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4304 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4305 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4306 emit_jump_insn (temp);
4307
4308 s390_load_address (addr0,
4309 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4310 s390_load_address (addr1,
4311 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4312
4313 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4314 OPTAB_DIRECT);
4315 if (temp != blocks)
4316 emit_move_insn (blocks, temp);
4317
4318 emit_cmp_and_jump_insns (blocks, const0_rtx,
4319 EQ, NULL_RTX, mode, 1, loop_end_label);
4320
4321 emit_jump (loop_start_label);
4322 emit_label (loop_end_label);
4323
4324 emit_insn (gen_cmpmem_short (op0, op1,
4325 convert_to_mode (Pmode, count, 1)));
4326 emit_label (end_label);
4327
4328 emit_insn (gen_cmpint (target, ccreg));
4329 }
4330 }
4331
4332
4333 /* Expand conditional increment or decrement using alc/slb instructions.
4334 Should generate code setting DST to either SRC or SRC + INCREMENT,
4335 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4336 Returns true if successful, false otherwise.
4337
4338 That makes it possible to implement some if-constructs without jumps e.g.:
4339 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4340 unsigned int a, b, c;
4341 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4342 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4343 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4344 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4345
4346 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4347 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4348 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4349 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4350 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4351
4352 bool
4353 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4354 rtx dst, rtx src, rtx increment)
4355 {
4356 enum machine_mode cmp_mode;
4357 enum machine_mode cc_mode;
4358 rtx op_res;
4359 rtx insn;
4360 rtvec p;
4361 int ret;
4362
4363 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4364 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4365 cmp_mode = SImode;
4366 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4367 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4368 cmp_mode = DImode;
4369 else
4370 return false;
4371
4372 /* Try ADD LOGICAL WITH CARRY. */
4373 if (increment == const1_rtx)
4374 {
4375 /* Determine CC mode to use. */
4376 if (cmp_code == EQ || cmp_code == NE)
4377 {
4378 if (cmp_op1 != const0_rtx)
4379 {
4380 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4381 NULL_RTX, 0, OPTAB_WIDEN);
4382 cmp_op1 = const0_rtx;
4383 }
4384
4385 cmp_code = cmp_code == EQ ? LEU : GTU;
4386 }
4387
4388 if (cmp_code == LTU || cmp_code == LEU)
4389 {
4390 rtx tem = cmp_op0;
4391 cmp_op0 = cmp_op1;
4392 cmp_op1 = tem;
4393 cmp_code = swap_condition (cmp_code);
4394 }
4395
4396 switch (cmp_code)
4397 {
4398 case GTU:
4399 cc_mode = CCUmode;
4400 break;
4401
4402 case GEU:
4403 cc_mode = CCL3mode;
4404 break;
4405
4406 default:
4407 return false;
4408 }
4409
4410 /* Emit comparison instruction pattern. */
4411 if (!register_operand (cmp_op0, cmp_mode))
4412 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4413
4414 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4415 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4416 /* We use insn_invalid_p here to add clobbers if required. */
4417 ret = insn_invalid_p (emit_insn (insn), false);
4418 gcc_assert (!ret);
4419
4420 /* Emit ALC instruction pattern. */
4421 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4422 gen_rtx_REG (cc_mode, CC_REGNUM),
4423 const0_rtx);
4424
4425 if (src != const0_rtx)
4426 {
4427 if (!register_operand (src, GET_MODE (dst)))
4428 src = force_reg (GET_MODE (dst), src);
4429
4430 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4431 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4432 }
4433
4434 p = rtvec_alloc (2);
4435 RTVEC_ELT (p, 0) =
4436 gen_rtx_SET (VOIDmode, dst, op_res);
4437 RTVEC_ELT (p, 1) =
4438 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4439 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4440
4441 return true;
4442 }
4443
4444 /* Try SUBTRACT LOGICAL WITH BORROW. */
4445 if (increment == constm1_rtx)
4446 {
4447 /* Determine CC mode to use. */
4448 if (cmp_code == EQ || cmp_code == NE)
4449 {
4450 if (cmp_op1 != const0_rtx)
4451 {
4452 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4453 NULL_RTX, 0, OPTAB_WIDEN);
4454 cmp_op1 = const0_rtx;
4455 }
4456
4457 cmp_code = cmp_code == EQ ? LEU : GTU;
4458 }
4459
4460 if (cmp_code == GTU || cmp_code == GEU)
4461 {
4462 rtx tem = cmp_op0;
4463 cmp_op0 = cmp_op1;
4464 cmp_op1 = tem;
4465 cmp_code = swap_condition (cmp_code);
4466 }
4467
4468 switch (cmp_code)
4469 {
4470 case LEU:
4471 cc_mode = CCUmode;
4472 break;
4473
4474 case LTU:
4475 cc_mode = CCL3mode;
4476 break;
4477
4478 default:
4479 return false;
4480 }
4481
4482 /* Emit comparison instruction pattern. */
4483 if (!register_operand (cmp_op0, cmp_mode))
4484 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4485
4486 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4487 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4488 /* We use insn_invalid_p here to add clobbers if required. */
4489 ret = insn_invalid_p (emit_insn (insn), false);
4490 gcc_assert (!ret);
4491
4492 /* Emit SLB instruction pattern. */
4493 if (!register_operand (src, GET_MODE (dst)))
4494 src = force_reg (GET_MODE (dst), src);
4495
4496 op_res = gen_rtx_MINUS (GET_MODE (dst),
4497 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4498 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4499 gen_rtx_REG (cc_mode, CC_REGNUM),
4500 const0_rtx));
4501 p = rtvec_alloc (2);
4502 RTVEC_ELT (p, 0) =
4503 gen_rtx_SET (VOIDmode, dst, op_res);
4504 RTVEC_ELT (p, 1) =
4505 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4506 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4507
4508 return true;
4509 }
4510
4511 return false;
4512 }
4513
4514 /* Expand code for the insv template. Return true if successful. */
4515
4516 bool
4517 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4518 {
4519 int bitsize = INTVAL (op1);
4520 int bitpos = INTVAL (op2);
4521
4522 /* On z10 we can use the risbg instruction to implement insv. */
4523 if (TARGET_Z10
4524 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4525 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4526 {
4527 rtx op;
4528 rtx clobber;
4529
4530 op = gen_rtx_SET (GET_MODE(src),
4531 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4532 src);
4533 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4534 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4535
4536 return true;
4537 }
4538
4539 /* We need byte alignment. */
4540 if (bitsize % BITS_PER_UNIT)
4541 return false;
4542
4543 if (bitpos == 0
4544 && memory_operand (dest, VOIDmode)
4545 && (register_operand (src, word_mode)
4546 || const_int_operand (src, VOIDmode)))
4547 {
4548 /* Emit standard pattern if possible. */
4549 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4550 if (GET_MODE_BITSIZE (mode) == bitsize)
4551 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4552
4553 /* (set (ze (mem)) (const_int)). */
4554 else if (const_int_operand (src, VOIDmode))
4555 {
4556 int size = bitsize / BITS_PER_UNIT;
4557 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4558 GET_MODE_SIZE (word_mode) - size);
4559
4560 dest = adjust_address (dest, BLKmode, 0);
4561 set_mem_size (dest, size);
4562 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4563 }
4564
4565 /* (set (ze (mem)) (reg)). */
4566 else if (register_operand (src, word_mode))
4567 {
4568 if (bitsize <= GET_MODE_BITSIZE (SImode))
4569 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4570 const0_rtx), src);
4571 else
4572 {
4573 /* Emit st,stcmh sequence. */
4574 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4575 int size = stcmh_width / BITS_PER_UNIT;
4576
4577 emit_move_insn (adjust_address (dest, SImode, size),
4578 gen_lowpart (SImode, src));
4579 set_mem_size (dest, size);
4580 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4581 (stcmh_width), const0_rtx),
4582 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4583 (GET_MODE_BITSIZE (SImode))));
4584 }
4585 }
4586 else
4587 return false;
4588
4589 return true;
4590 }
4591
4592 /* (set (ze (reg)) (const_int)). */
4593 if (TARGET_ZARCH
4594 && register_operand (dest, word_mode)
4595 && (bitpos % 16) == 0
4596 && (bitsize % 16) == 0
4597 && const_int_operand (src, VOIDmode))
4598 {
4599 HOST_WIDE_INT val = INTVAL (src);
4600 int regpos = bitpos + bitsize;
4601
4602 while (regpos > bitpos)
4603 {
4604 enum machine_mode putmode;
4605 int putsize;
4606
4607 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4608 putmode = SImode;
4609 else
4610 putmode = HImode;
4611
4612 putsize = GET_MODE_BITSIZE (putmode);
4613 regpos -= putsize;
4614 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4615 GEN_INT (putsize),
4616 GEN_INT (regpos)),
4617 gen_int_mode (val, putmode));
4618 val >>= putsize;
4619 }
4620 gcc_assert (regpos == bitpos);
4621 return true;
4622 }
4623
4624 return false;
4625 }
4626
4627 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4628 register that holds VAL of mode MODE shifted by COUNT bits. */
4629
4630 static inline rtx
4631 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4632 {
4633 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4634 NULL_RTX, 1, OPTAB_DIRECT);
4635 return expand_simple_binop (SImode, ASHIFT, val, count,
4636 NULL_RTX, 1, OPTAB_DIRECT);
4637 }
4638
4639 /* Structure to hold the initial parameters for a compare_and_swap operation
4640 in HImode and QImode. */
4641
4642 struct alignment_context
4643 {
4644 rtx memsi; /* SI aligned memory location. */
4645 rtx shift; /* Bit offset with regard to lsb. */
4646 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4647 rtx modemaski; /* ~modemask */
4648 bool aligned; /* True if memory is aligned, false else. */
4649 };
4650
4651 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4652 structure AC for transparent simplifying, if the memory alignment is known
4653 to be at least 32bit. MEM is the memory location for the actual operation
4654 and MODE its mode. */
4655
4656 static void
4657 init_alignment_context (struct alignment_context *ac, rtx mem,
4658 enum machine_mode mode)
4659 {
4660 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4661 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4662
4663 if (ac->aligned)
4664 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4665 else
4666 {
4667 /* Alignment is unknown. */
4668 rtx byteoffset, addr, align;
4669
4670 /* Force the address into a register. */
4671 addr = force_reg (Pmode, XEXP (mem, 0));
4672
4673 /* Align it to SImode. */
4674 align = expand_simple_binop (Pmode, AND, addr,
4675 GEN_INT (-GET_MODE_SIZE (SImode)),
4676 NULL_RTX, 1, OPTAB_DIRECT);
4677 /* Generate MEM. */
4678 ac->memsi = gen_rtx_MEM (SImode, align);
4679 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4680 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4681 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4682
4683 /* Calculate shiftcount. */
4684 byteoffset = expand_simple_binop (Pmode, AND, addr,
4685 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4686 NULL_RTX, 1, OPTAB_DIRECT);
4687 /* As we already have some offset, evaluate the remaining distance. */
4688 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4689 NULL_RTX, 1, OPTAB_DIRECT);
4690
4691 }
4692 /* Shift is the byte count, but we need the bitcount. */
4693 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4694 NULL_RTX, 1, OPTAB_DIRECT);
4695 /* Calculate masks. */
4696 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4697 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4698 NULL_RTX, 1, OPTAB_DIRECT);
4699 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4700 }
4701
4702 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4703 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4704 to set if CMP == MEM.
4705 CMP is never in memory for compare_and_swap_cc because
4706 expand_bool_compare_and_swap puts it into a register for later compare. */
4707
4708 void
4709 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4710 {
4711 struct alignment_context ac;
4712 rtx cmpv, newv, val, resv, cc;
4713 rtx res = gen_reg_rtx (SImode);
4714 rtx csloop = gen_label_rtx ();
4715 rtx csend = gen_label_rtx ();
4716
4717 gcc_assert (register_operand (target, VOIDmode));
4718 gcc_assert (MEM_P (mem));
4719
4720 init_alignment_context (&ac, mem, mode);
4721
4722 /* Shift the values to the correct bit positions. */
4723 if (!(ac.aligned && MEM_P (cmp)))
4724 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4725 if (!(ac.aligned && MEM_P (new_rtx)))
4726 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4727
4728 /* Load full word. Subsequent loads are performed by CS. */
4729 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4730 NULL_RTX, 1, OPTAB_DIRECT);
4731
4732 /* Start CS loop. */
4733 emit_label (csloop);
4734 /* val = "<mem>00..0<mem>"
4735 * cmp = "00..0<cmp>00..0"
4736 * new = "00..0<new>00..0"
4737 */
4738
4739 /* Patch cmp and new with val at correct position. */
4740 if (ac.aligned && MEM_P (cmp))
4741 {
4742 cmpv = force_reg (SImode, val);
4743 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0,
4744 0, 0, SImode, cmp);
4745 }
4746 else
4747 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4748 NULL_RTX, 1, OPTAB_DIRECT));
4749 if (ac.aligned && MEM_P (new_rtx))
4750 {
4751 newv = force_reg (SImode, val);
4752 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0,
4753 0, 0, SImode, new_rtx);
4754 }
4755 else
4756 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4757 NULL_RTX, 1, OPTAB_DIRECT));
4758
4759 /* Jump to end if we're done (likely?). */
4760 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4761 cmpv, newv));
4762
4763 /* Check for changes outside mode. */
4764 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4765 NULL_RTX, 1, OPTAB_DIRECT);
4766 cc = s390_emit_compare (NE, resv, val);
4767 emit_move_insn (val, resv);
4768 /* Loop internal if so. */
4769 s390_emit_jump (csloop, cc);
4770
4771 emit_label (csend);
4772
4773 /* Return the correct part of the bitfield. */
4774 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4775 NULL_RTX, 1, OPTAB_DIRECT), 1);
4776 }
4777
4778 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4779 and VAL the value to play with. If AFTER is true then store the value
4780 MEM holds after the operation, if AFTER is false then store the value MEM
4781 holds before the operation. If TARGET is zero then discard that value, else
4782 store it to TARGET. */
4783
4784 void
4785 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4786 rtx target, rtx mem, rtx val, bool after)
4787 {
4788 struct alignment_context ac;
4789 rtx cmp;
4790 rtx new_rtx = gen_reg_rtx (SImode);
4791 rtx orig = gen_reg_rtx (SImode);
4792 rtx csloop = gen_label_rtx ();
4793
4794 gcc_assert (!target || register_operand (target, VOIDmode));
4795 gcc_assert (MEM_P (mem));
4796
4797 init_alignment_context (&ac, mem, mode);
4798
4799 /* Shift val to the correct bit positions.
4800 Preserve "icm", but prevent "ex icm". */
4801 if (!(ac.aligned && code == SET && MEM_P (val)))
4802 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4803
4804 /* Further preparation insns. */
4805 if (code == PLUS || code == MINUS)
4806 emit_move_insn (orig, val);
4807 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4808 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4809 NULL_RTX, 1, OPTAB_DIRECT);
4810
4811 /* Load full word. Subsequent loads are performed by CS. */
4812 cmp = force_reg (SImode, ac.memsi);
4813
4814 /* Start CS loop. */
4815 emit_label (csloop);
4816 emit_move_insn (new_rtx, cmp);
4817
4818 /* Patch new with val at correct position. */
4819 switch (code)
4820 {
4821 case PLUS:
4822 case MINUS:
4823 val = expand_simple_binop (SImode, code, new_rtx, orig,
4824 NULL_RTX, 1, OPTAB_DIRECT);
4825 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4826 NULL_RTX, 1, OPTAB_DIRECT);
4827 /* FALLTHRU */
4828 case SET:
4829 if (ac.aligned && MEM_P (val))
4830 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
4831 0, 0, SImode, val);
4832 else
4833 {
4834 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4835 NULL_RTX, 1, OPTAB_DIRECT);
4836 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4837 NULL_RTX, 1, OPTAB_DIRECT);
4838 }
4839 break;
4840 case AND:
4841 case IOR:
4842 case XOR:
4843 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4844 NULL_RTX, 1, OPTAB_DIRECT);
4845 break;
4846 case MULT: /* NAND */
4847 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4848 NULL_RTX, 1, OPTAB_DIRECT);
4849 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4850 NULL_RTX, 1, OPTAB_DIRECT);
4851 break;
4852 default:
4853 gcc_unreachable ();
4854 }
4855
4856 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4857 ac.memsi, cmp, new_rtx));
4858
4859 /* Return the correct part of the bitfield. */
4860 if (target)
4861 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4862 after ? new_rtx : cmp, ac.shift,
4863 NULL_RTX, 1, OPTAB_DIRECT), 1);
4864 }
4865
4866 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4867 We need to emit DTP-relative relocations. */
4868
4869 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4870
4871 static void
4872 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4873 {
4874 switch (size)
4875 {
4876 case 4:
4877 fputs ("\t.long\t", file);
4878 break;
4879 case 8:
4880 fputs ("\t.quad\t", file);
4881 break;
4882 default:
4883 gcc_unreachable ();
4884 }
4885 output_addr_const (file, x);
4886 fputs ("@DTPOFF", file);
4887 }
4888
4889 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4890 /* Implement TARGET_MANGLE_TYPE. */
4891
4892 static const char *
4893 s390_mangle_type (const_tree type)
4894 {
4895 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4896 && TARGET_LONG_DOUBLE_128)
4897 return "g";
4898
4899 /* For all other types, use normal C++ mangling. */
4900 return NULL;
4901 }
4902 #endif
4903
4904 /* In the name of slightly smaller debug output, and to cater to
4905 general assembler lossage, recognize various UNSPEC sequences
4906 and turn them back into a direct symbol reference. */
4907
4908 static rtx
4909 s390_delegitimize_address (rtx orig_x)
4910 {
4911 rtx x, y;
4912
4913 orig_x = delegitimize_mem_from_attrs (orig_x);
4914 x = orig_x;
4915
4916 /* Extract the symbol ref from:
4917 (plus:SI (reg:SI 12 %r12)
4918 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4919 UNSPEC_GOTOFF/PLTOFF)))
4920 and
4921 (plus:SI (reg:SI 12 %r12)
4922 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4923 UNSPEC_GOTOFF/PLTOFF)
4924 (const_int 4 [0x4])))) */
4925 if (GET_CODE (x) == PLUS
4926 && REG_P (XEXP (x, 0))
4927 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4928 && GET_CODE (XEXP (x, 1)) == CONST)
4929 {
4930 HOST_WIDE_INT offset = 0;
4931
4932 /* The const operand. */
4933 y = XEXP (XEXP (x, 1), 0);
4934
4935 if (GET_CODE (y) == PLUS
4936 && GET_CODE (XEXP (y, 1)) == CONST_INT)
4937 {
4938 offset = INTVAL (XEXP (y, 1));
4939 y = XEXP (y, 0);
4940 }
4941
4942 if (GET_CODE (y) == UNSPEC
4943 && (XINT (y, 1) == UNSPEC_GOTOFF
4944 || XINT (y, 1) == UNSPEC_PLTOFF))
4945 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
4946 }
4947
4948 if (GET_CODE (x) != MEM)
4949 return orig_x;
4950
4951 x = XEXP (x, 0);
4952 if (GET_CODE (x) == PLUS
4953 && GET_CODE (XEXP (x, 1)) == CONST
4954 && GET_CODE (XEXP (x, 0)) == REG
4955 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4956 {
4957 y = XEXP (XEXP (x, 1), 0);
4958 if (GET_CODE (y) == UNSPEC
4959 && XINT (y, 1) == UNSPEC_GOT)
4960 y = XVECEXP (y, 0, 0);
4961 else
4962 return orig_x;
4963 }
4964 else if (GET_CODE (x) == CONST)
4965 {
4966 /* Extract the symbol ref from:
4967 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
4968 UNSPEC_PLT/GOTENT))) */
4969
4970 y = XEXP (x, 0);
4971 if (GET_CODE (y) == UNSPEC
4972 && (XINT (y, 1) == UNSPEC_GOTENT
4973 || XINT (y, 1) == UNSPEC_PLT))
4974 y = XVECEXP (y, 0, 0);
4975 else
4976 return orig_x;
4977 }
4978 else
4979 return orig_x;
4980
4981 if (GET_MODE (orig_x) != Pmode)
4982 {
4983 if (GET_MODE (orig_x) == BLKmode)
4984 return orig_x;
4985 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
4986 if (y == NULL_RTX)
4987 return orig_x;
4988 }
4989 return y;
4990 }
4991
4992 /* Output operand OP to stdio stream FILE.
4993 OP is an address (register + offset) which is not used to address data;
4994 instead the rightmost bits are interpreted as the value. */
4995
4996 static void
4997 print_shift_count_operand (FILE *file, rtx op)
4998 {
4999 HOST_WIDE_INT offset;
5000 rtx base;
5001
5002 /* Extract base register and offset. */
5003 if (!s390_decompose_shift_count (op, &base, &offset))
5004 gcc_unreachable ();
5005
5006 /* Sanity check. */
5007 if (base)
5008 {
5009 gcc_assert (GET_CODE (base) == REG);
5010 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5011 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5012 }
5013
5014 /* Offsets are constricted to twelve bits. */
5015 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5016 if (base)
5017 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5018 }
5019
5020 /* See 'get_some_local_dynamic_name'. */
5021
5022 static int
5023 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5024 {
5025 rtx x = *px;
5026
5027 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5028 {
5029 x = get_pool_constant (x);
5030 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5031 }
5032
5033 if (GET_CODE (x) == SYMBOL_REF
5034 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5035 {
5036 cfun->machine->some_ld_name = XSTR (x, 0);
5037 return 1;
5038 }
5039
5040 return 0;
5041 }
5042
5043 /* Locate some local-dynamic symbol still in use by this function
5044 so that we can print its name in local-dynamic base patterns. */
5045
5046 static const char *
5047 get_some_local_dynamic_name (void)
5048 {
5049 rtx insn;
5050
5051 if (cfun->machine->some_ld_name)
5052 return cfun->machine->some_ld_name;
5053
5054 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5055 if (INSN_P (insn)
5056 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5057 return cfun->machine->some_ld_name;
5058
5059 gcc_unreachable ();
5060 }
5061
5062 /* Output machine-dependent UNSPECs occurring in address constant X
5063 in assembler syntax to stdio stream FILE. Returns true if the
5064 constant X could be recognized, false otherwise. */
5065
5066 static bool
5067 s390_output_addr_const_extra (FILE *file, rtx x)
5068 {
5069 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5070 switch (XINT (x, 1))
5071 {
5072 case UNSPEC_GOTENT:
5073 output_addr_const (file, XVECEXP (x, 0, 0));
5074 fprintf (file, "@GOTENT");
5075 return true;
5076 case UNSPEC_GOT:
5077 output_addr_const (file, XVECEXP (x, 0, 0));
5078 fprintf (file, "@GOT");
5079 return true;
5080 case UNSPEC_GOTOFF:
5081 output_addr_const (file, XVECEXP (x, 0, 0));
5082 fprintf (file, "@GOTOFF");
5083 return true;
5084 case UNSPEC_PLT:
5085 output_addr_const (file, XVECEXP (x, 0, 0));
5086 fprintf (file, "@PLT");
5087 return true;
5088 case UNSPEC_PLTOFF:
5089 output_addr_const (file, XVECEXP (x, 0, 0));
5090 fprintf (file, "@PLTOFF");
5091 return true;
5092 case UNSPEC_TLSGD:
5093 output_addr_const (file, XVECEXP (x, 0, 0));
5094 fprintf (file, "@TLSGD");
5095 return true;
5096 case UNSPEC_TLSLDM:
5097 assemble_name (file, get_some_local_dynamic_name ());
5098 fprintf (file, "@TLSLDM");
5099 return true;
5100 case UNSPEC_DTPOFF:
5101 output_addr_const (file, XVECEXP (x, 0, 0));
5102 fprintf (file, "@DTPOFF");
5103 return true;
5104 case UNSPEC_NTPOFF:
5105 output_addr_const (file, XVECEXP (x, 0, 0));
5106 fprintf (file, "@NTPOFF");
5107 return true;
5108 case UNSPEC_GOTNTPOFF:
5109 output_addr_const (file, XVECEXP (x, 0, 0));
5110 fprintf (file, "@GOTNTPOFF");
5111 return true;
5112 case UNSPEC_INDNTPOFF:
5113 output_addr_const (file, XVECEXP (x, 0, 0));
5114 fprintf (file, "@INDNTPOFF");
5115 return true;
5116 }
5117
5118 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5119 switch (XINT (x, 1))
5120 {
5121 case UNSPEC_POOL_OFFSET:
5122 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5123 output_addr_const (file, x);
5124 return true;
5125 }
5126 return false;
5127 }
5128
5129 /* Output address operand ADDR in assembler syntax to
5130 stdio stream FILE. */
5131
5132 void
5133 print_operand_address (FILE *file, rtx addr)
5134 {
5135 struct s390_address ad;
5136
5137 if (s390_symref_operand_p (addr, NULL, NULL))
5138 {
5139 if (!TARGET_Z10)
5140 {
5141 output_operand_lossage ("symbolic memory references are "
5142 "only supported on z10 or later");
5143 return;
5144 }
5145 output_addr_const (file, addr);
5146 return;
5147 }
5148
5149 if (!s390_decompose_address (addr, &ad)
5150 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5151 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5152 output_operand_lossage ("cannot decompose address");
5153
5154 if (ad.disp)
5155 output_addr_const (file, ad.disp);
5156 else
5157 fprintf (file, "0");
5158
5159 if (ad.base && ad.indx)
5160 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5161 reg_names[REGNO (ad.base)]);
5162 else if (ad.base)
5163 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5164 }
5165
5166 /* Output operand X in assembler syntax to stdio stream FILE.
5167 CODE specified the format flag. The following format flags
5168 are recognized:
5169
5170 'C': print opcode suffix for branch condition.
5171 'D': print opcode suffix for inverse branch condition.
5172 'E': print opcode suffix for branch on index instruction.
5173 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5174 'G': print the size of the operand in bytes.
5175 'O': print only the displacement of a memory reference.
5176 'R': print only the base register of a memory reference.
5177 'S': print S-type memory reference (base+displacement).
5178 'N': print the second word of a DImode operand.
5179 'M': print the second word of a TImode operand.
5180 'Y': print shift count operand.
5181
5182 'b': print integer X as if it's an unsigned byte.
5183 'c': print integer X as if it's an signed byte.
5184 'x': print integer X as if it's an unsigned halfword.
5185 'h': print integer X as if it's a signed halfword.
5186 'i': print the first nonzero HImode part of X.
5187 'j': print the first HImode part unequal to -1 of X.
5188 'k': print the first nonzero SImode part of X.
5189 'm': print the first SImode part unequal to -1 of X.
5190 'o': print integer X as if it's an unsigned 32bit word. */
5191
5192 void
5193 print_operand (FILE *file, rtx x, int code)
5194 {
5195 switch (code)
5196 {
5197 case 'C':
5198 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5199 return;
5200
5201 case 'D':
5202 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5203 return;
5204
5205 case 'E':
5206 if (GET_CODE (x) == LE)
5207 fprintf (file, "l");
5208 else if (GET_CODE (x) == GT)
5209 fprintf (file, "h");
5210 else
5211 output_operand_lossage ("invalid comparison operator "
5212 "for 'E' output modifier");
5213 return;
5214
5215 case 'J':
5216 if (GET_CODE (x) == SYMBOL_REF)
5217 {
5218 fprintf (file, "%s", ":tls_load:");
5219 output_addr_const (file, x);
5220 }
5221 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5222 {
5223 fprintf (file, "%s", ":tls_gdcall:");
5224 output_addr_const (file, XVECEXP (x, 0, 0));
5225 }
5226 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5227 {
5228 fprintf (file, "%s", ":tls_ldcall:");
5229 assemble_name (file, get_some_local_dynamic_name ());
5230 }
5231 else
5232 output_operand_lossage ("invalid reference for 'J' output modifier");
5233 return;
5234
5235 case 'G':
5236 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5237 return;
5238
5239 case 'O':
5240 {
5241 struct s390_address ad;
5242 int ret;
5243
5244 if (!MEM_P (x))
5245 {
5246 output_operand_lossage ("memory reference expected for "
5247 "'O' output modifier");
5248 return;
5249 }
5250
5251 ret = s390_decompose_address (XEXP (x, 0), &ad);
5252
5253 if (!ret
5254 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5255 || ad.indx)
5256 {
5257 output_operand_lossage ("invalid address for 'O' output modifier");
5258 return;
5259 }
5260
5261 if (ad.disp)
5262 output_addr_const (file, ad.disp);
5263 else
5264 fprintf (file, "0");
5265 }
5266 return;
5267
5268 case 'R':
5269 {
5270 struct s390_address ad;
5271 int ret;
5272
5273 if (!MEM_P (x))
5274 {
5275 output_operand_lossage ("memory reference expected for "
5276 "'R' output modifier");
5277 return;
5278 }
5279
5280 ret = s390_decompose_address (XEXP (x, 0), &ad);
5281
5282 if (!ret
5283 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5284 || ad.indx)
5285 {
5286 output_operand_lossage ("invalid address for 'R' output modifier");
5287 return;
5288 }
5289
5290 if (ad.base)
5291 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5292 else
5293 fprintf (file, "0");
5294 }
5295 return;
5296
5297 case 'S':
5298 {
5299 struct s390_address ad;
5300 int ret;
5301
5302 if (!MEM_P (x))
5303 {
5304 output_operand_lossage ("memory reference expected for "
5305 "'S' output modifier");
5306 return;
5307 }
5308 ret = s390_decompose_address (XEXP (x, 0), &ad);
5309
5310 if (!ret
5311 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5312 || ad.indx)
5313 {
5314 output_operand_lossage ("invalid address for 'S' output modifier");
5315 return;
5316 }
5317
5318 if (ad.disp)
5319 output_addr_const (file, ad.disp);
5320 else
5321 fprintf (file, "0");
5322
5323 if (ad.base)
5324 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5325 }
5326 return;
5327
5328 case 'N':
5329 if (GET_CODE (x) == REG)
5330 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5331 else if (GET_CODE (x) == MEM)
5332 x = change_address (x, VOIDmode,
5333 plus_constant (Pmode, XEXP (x, 0), 4));
5334 else
5335 output_operand_lossage ("register or memory expression expected "
5336 "for 'N' output modifier");
5337 break;
5338
5339 case 'M':
5340 if (GET_CODE (x) == REG)
5341 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5342 else if (GET_CODE (x) == MEM)
5343 x = change_address (x, VOIDmode,
5344 plus_constant (Pmode, XEXP (x, 0), 8));
5345 else
5346 output_operand_lossage ("register or memory expression expected "
5347 "for 'M' output modifier");
5348 break;
5349
5350 case 'Y':
5351 print_shift_count_operand (file, x);
5352 return;
5353 }
5354
5355 switch (GET_CODE (x))
5356 {
5357 case REG:
5358 fprintf (file, "%s", reg_names[REGNO (x)]);
5359 break;
5360
5361 case MEM:
5362 output_address (XEXP (x, 0));
5363 break;
5364
5365 case CONST:
5366 case CODE_LABEL:
5367 case LABEL_REF:
5368 case SYMBOL_REF:
5369 output_addr_const (file, x);
5370 break;
5371
5372 case CONST_INT:
5373 if (code == 'b')
5374 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5375 else if (code == 'c')
5376 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5377 else if (code == 'x')
5378 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5379 else if (code == 'h')
5380 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5381 else if (code == 'i')
5382 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5383 s390_extract_part (x, HImode, 0));
5384 else if (code == 'j')
5385 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5386 s390_extract_part (x, HImode, -1));
5387 else if (code == 'k')
5388 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5389 s390_extract_part (x, SImode, 0));
5390 else if (code == 'm')
5391 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5392 s390_extract_part (x, SImode, -1));
5393 else if (code == 'o')
5394 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5395 else
5396 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5397 break;
5398
5399 case CONST_DOUBLE:
5400 gcc_assert (GET_MODE (x) == VOIDmode);
5401 if (code == 'b')
5402 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5403 else if (code == 'x')
5404 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5405 else if (code == 'h')
5406 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5407 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5408 else
5409 {
5410 if (code == 0)
5411 output_operand_lossage ("invalid constant - try using "
5412 "an output modifier");
5413 else
5414 output_operand_lossage ("invalid constant for output modifier '%c'",
5415 code);
5416 }
5417 break;
5418
5419 default:
5420 if (code == 0)
5421 output_operand_lossage ("invalid expression - try using "
5422 "an output modifier");
5423 else
5424 output_operand_lossage ("invalid expression for output "
5425 "modifier '%c'", code);
5426 break;
5427 }
5428 }
5429
5430 /* Target hook for assembling integer objects. We need to define it
5431 here to work a round a bug in some versions of GAS, which couldn't
5432 handle values smaller than INT_MIN when printed in decimal. */
5433
5434 static bool
5435 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5436 {
5437 if (size == 8 && aligned_p
5438 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5439 {
5440 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5441 INTVAL (x));
5442 return true;
5443 }
5444 return default_assemble_integer (x, size, aligned_p);
5445 }
5446
5447 /* Returns true if register REGNO is used for forming
5448 a memory address in expression X. */
5449
5450 static bool
5451 reg_used_in_mem_p (int regno, rtx x)
5452 {
5453 enum rtx_code code = GET_CODE (x);
5454 int i, j;
5455 const char *fmt;
5456
5457 if (code == MEM)
5458 {
5459 if (refers_to_regno_p (regno, regno+1,
5460 XEXP (x, 0), 0))
5461 return true;
5462 }
5463 else if (code == SET
5464 && GET_CODE (SET_DEST (x)) == PC)
5465 {
5466 if (refers_to_regno_p (regno, regno+1,
5467 SET_SRC (x), 0))
5468 return true;
5469 }
5470
5471 fmt = GET_RTX_FORMAT (code);
5472 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5473 {
5474 if (fmt[i] == 'e'
5475 && reg_used_in_mem_p (regno, XEXP (x, i)))
5476 return true;
5477
5478 else if (fmt[i] == 'E')
5479 for (j = 0; j < XVECLEN (x, i); j++)
5480 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5481 return true;
5482 }
5483 return false;
5484 }
5485
5486 /* Returns true if expression DEP_RTX sets an address register
5487 used by instruction INSN to address memory. */
5488
5489 static bool
5490 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5491 {
5492 rtx target, pat;
5493
5494 if (GET_CODE (dep_rtx) == INSN)
5495 dep_rtx = PATTERN (dep_rtx);
5496
5497 if (GET_CODE (dep_rtx) == SET)
5498 {
5499 target = SET_DEST (dep_rtx);
5500 if (GET_CODE (target) == STRICT_LOW_PART)
5501 target = XEXP (target, 0);
5502 while (GET_CODE (target) == SUBREG)
5503 target = SUBREG_REG (target);
5504
5505 if (GET_CODE (target) == REG)
5506 {
5507 int regno = REGNO (target);
5508
5509 if (s390_safe_attr_type (insn) == TYPE_LA)
5510 {
5511 pat = PATTERN (insn);
5512 if (GET_CODE (pat) == PARALLEL)
5513 {
5514 gcc_assert (XVECLEN (pat, 0) == 2);
5515 pat = XVECEXP (pat, 0, 0);
5516 }
5517 gcc_assert (GET_CODE (pat) == SET);
5518 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5519 }
5520 else if (get_attr_atype (insn) == ATYPE_AGEN)
5521 return reg_used_in_mem_p (regno, PATTERN (insn));
5522 }
5523 }
5524 return false;
5525 }
5526
5527 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5528
5529 int
5530 s390_agen_dep_p (rtx dep_insn, rtx insn)
5531 {
5532 rtx dep_rtx = PATTERN (dep_insn);
5533 int i;
5534
5535 if (GET_CODE (dep_rtx) == SET
5536 && addr_generation_dependency_p (dep_rtx, insn))
5537 return 1;
5538 else if (GET_CODE (dep_rtx) == PARALLEL)
5539 {
5540 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5541 {
5542 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5543 return 1;
5544 }
5545 }
5546 return 0;
5547 }
5548
5549
5550 /* A C statement (sans semicolon) to update the integer scheduling priority
5551 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5552 reduce the priority to execute INSN later. Do not define this macro if
5553 you do not need to adjust the scheduling priorities of insns.
5554
5555 A STD instruction should be scheduled earlier,
5556 in order to use the bypass. */
5557 static int
5558 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5559 {
5560 if (! INSN_P (insn))
5561 return priority;
5562
5563 if (s390_tune != PROCESSOR_2084_Z990
5564 && s390_tune != PROCESSOR_2094_Z9_109
5565 && s390_tune != PROCESSOR_2097_Z10
5566 && s390_tune != PROCESSOR_2817_Z196)
5567 return priority;
5568
5569 switch (s390_safe_attr_type (insn))
5570 {
5571 case TYPE_FSTOREDF:
5572 case TYPE_FSTORESF:
5573 priority = priority << 3;
5574 break;
5575 case TYPE_STORE:
5576 case TYPE_STM:
5577 priority = priority << 1;
5578 break;
5579 default:
5580 break;
5581 }
5582 return priority;
5583 }
5584
5585
5586 /* The number of instructions that can be issued per cycle. */
5587
5588 static int
5589 s390_issue_rate (void)
5590 {
5591 switch (s390_tune)
5592 {
5593 case PROCESSOR_2084_Z990:
5594 case PROCESSOR_2094_Z9_109:
5595 case PROCESSOR_2817_Z196:
5596 return 3;
5597 case PROCESSOR_2097_Z10:
5598 return 2;
5599 default:
5600 return 1;
5601 }
5602 }
5603
5604 static int
5605 s390_first_cycle_multipass_dfa_lookahead (void)
5606 {
5607 return 4;
5608 }
5609
5610 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5611 Fix up MEMs as required. */
5612
5613 static void
5614 annotate_constant_pool_refs (rtx *x)
5615 {
5616 int i, j;
5617 const char *fmt;
5618
5619 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5620 || !CONSTANT_POOL_ADDRESS_P (*x));
5621
5622 /* Literal pool references can only occur inside a MEM ... */
5623 if (GET_CODE (*x) == MEM)
5624 {
5625 rtx memref = XEXP (*x, 0);
5626
5627 if (GET_CODE (memref) == SYMBOL_REF
5628 && CONSTANT_POOL_ADDRESS_P (memref))
5629 {
5630 rtx base = cfun->machine->base_reg;
5631 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5632 UNSPEC_LTREF);
5633
5634 *x = replace_equiv_address (*x, addr);
5635 return;
5636 }
5637
5638 if (GET_CODE (memref) == CONST
5639 && GET_CODE (XEXP (memref, 0)) == PLUS
5640 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5641 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5642 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5643 {
5644 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5645 rtx sym = XEXP (XEXP (memref, 0), 0);
5646 rtx base = cfun->machine->base_reg;
5647 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5648 UNSPEC_LTREF);
5649
5650 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5651 return;
5652 }
5653 }
5654
5655 /* ... or a load-address type pattern. */
5656 if (GET_CODE (*x) == SET)
5657 {
5658 rtx addrref = SET_SRC (*x);
5659
5660 if (GET_CODE (addrref) == SYMBOL_REF
5661 && CONSTANT_POOL_ADDRESS_P (addrref))
5662 {
5663 rtx base = cfun->machine->base_reg;
5664 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5665 UNSPEC_LTREF);
5666
5667 SET_SRC (*x) = addr;
5668 return;
5669 }
5670
5671 if (GET_CODE (addrref) == CONST
5672 && GET_CODE (XEXP (addrref, 0)) == PLUS
5673 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5674 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5675 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5676 {
5677 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5678 rtx sym = XEXP (XEXP (addrref, 0), 0);
5679 rtx base = cfun->machine->base_reg;
5680 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5681 UNSPEC_LTREF);
5682
5683 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5684 return;
5685 }
5686 }
5687
5688 /* Annotate LTREL_BASE as well. */
5689 if (GET_CODE (*x) == UNSPEC
5690 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5691 {
5692 rtx base = cfun->machine->base_reg;
5693 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5694 UNSPEC_LTREL_BASE);
5695 return;
5696 }
5697
5698 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5699 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5700 {
5701 if (fmt[i] == 'e')
5702 {
5703 annotate_constant_pool_refs (&XEXP (*x, i));
5704 }
5705 else if (fmt[i] == 'E')
5706 {
5707 for (j = 0; j < XVECLEN (*x, i); j++)
5708 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5709 }
5710 }
5711 }
5712
5713 /* Split all branches that exceed the maximum distance.
5714 Returns true if this created a new literal pool entry. */
5715
5716 static int
5717 s390_split_branches (void)
5718 {
5719 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5720 int new_literal = 0, ret;
5721 rtx insn, pat, tmp, target;
5722 rtx *label;
5723
5724 /* We need correct insn addresses. */
5725
5726 shorten_branches (get_insns ());
5727
5728 /* Find all branches that exceed 64KB, and split them. */
5729
5730 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5731 {
5732 if (GET_CODE (insn) != JUMP_INSN)
5733 continue;
5734
5735 pat = PATTERN (insn);
5736 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5737 pat = XVECEXP (pat, 0, 0);
5738 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5739 continue;
5740
5741 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5742 {
5743 label = &SET_SRC (pat);
5744 }
5745 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5746 {
5747 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5748 label = &XEXP (SET_SRC (pat), 1);
5749 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5750 label = &XEXP (SET_SRC (pat), 2);
5751 else
5752 continue;
5753 }
5754 else
5755 continue;
5756
5757 if (get_attr_length (insn) <= 4)
5758 continue;
5759
5760 /* We are going to use the return register as scratch register,
5761 make sure it will be saved/restored by the prologue/epilogue. */
5762 cfun_frame_layout.save_return_addr_p = 1;
5763
5764 if (!flag_pic)
5765 {
5766 new_literal = 1;
5767 tmp = force_const_mem (Pmode, *label);
5768 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5769 INSN_ADDRESSES_NEW (tmp, -1);
5770 annotate_constant_pool_refs (&PATTERN (tmp));
5771
5772 target = temp_reg;
5773 }
5774 else
5775 {
5776 new_literal = 1;
5777 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5778 UNSPEC_LTREL_OFFSET);
5779 target = gen_rtx_CONST (Pmode, target);
5780 target = force_const_mem (Pmode, target);
5781 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5782 INSN_ADDRESSES_NEW (tmp, -1);
5783 annotate_constant_pool_refs (&PATTERN (tmp));
5784
5785 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5786 cfun->machine->base_reg),
5787 UNSPEC_LTREL_BASE);
5788 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5789 }
5790
5791 ret = validate_change (insn, label, target, 0);
5792 gcc_assert (ret);
5793 }
5794
5795 return new_literal;
5796 }
5797
5798
5799 /* Find an annotated literal pool symbol referenced in RTX X,
5800 and store it at REF. Will abort if X contains references to
5801 more than one such pool symbol; multiple references to the same
5802 symbol are allowed, however.
5803
5804 The rtx pointed to by REF must be initialized to NULL_RTX
5805 by the caller before calling this routine. */
5806
5807 static void
5808 find_constant_pool_ref (rtx x, rtx *ref)
5809 {
5810 int i, j;
5811 const char *fmt;
5812
5813 /* Ignore LTREL_BASE references. */
5814 if (GET_CODE (x) == UNSPEC
5815 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5816 return;
5817 /* Likewise POOL_ENTRY insns. */
5818 if (GET_CODE (x) == UNSPEC_VOLATILE
5819 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5820 return;
5821
5822 gcc_assert (GET_CODE (x) != SYMBOL_REF
5823 || !CONSTANT_POOL_ADDRESS_P (x));
5824
5825 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5826 {
5827 rtx sym = XVECEXP (x, 0, 0);
5828 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5829 && CONSTANT_POOL_ADDRESS_P (sym));
5830
5831 if (*ref == NULL_RTX)
5832 *ref = sym;
5833 else
5834 gcc_assert (*ref == sym);
5835
5836 return;
5837 }
5838
5839 fmt = GET_RTX_FORMAT (GET_CODE (x));
5840 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5841 {
5842 if (fmt[i] == 'e')
5843 {
5844 find_constant_pool_ref (XEXP (x, i), ref);
5845 }
5846 else if (fmt[i] == 'E')
5847 {
5848 for (j = 0; j < XVECLEN (x, i); j++)
5849 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5850 }
5851 }
5852 }
5853
5854 /* Replace every reference to the annotated literal pool
5855 symbol REF in X by its base plus OFFSET. */
5856
5857 static void
5858 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5859 {
5860 int i, j;
5861 const char *fmt;
5862
5863 gcc_assert (*x != ref);
5864
5865 if (GET_CODE (*x) == UNSPEC
5866 && XINT (*x, 1) == UNSPEC_LTREF
5867 && XVECEXP (*x, 0, 0) == ref)
5868 {
5869 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5870 return;
5871 }
5872
5873 if (GET_CODE (*x) == PLUS
5874 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5875 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5876 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5877 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5878 {
5879 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5880 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
5881 return;
5882 }
5883
5884 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5885 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5886 {
5887 if (fmt[i] == 'e')
5888 {
5889 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5890 }
5891 else if (fmt[i] == 'E')
5892 {
5893 for (j = 0; j < XVECLEN (*x, i); j++)
5894 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5895 }
5896 }
5897 }
5898
5899 /* Check whether X contains an UNSPEC_LTREL_BASE.
5900 Return its constant pool symbol if found, NULL_RTX otherwise. */
5901
5902 static rtx
5903 find_ltrel_base (rtx x)
5904 {
5905 int i, j;
5906 const char *fmt;
5907
5908 if (GET_CODE (x) == UNSPEC
5909 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5910 return XVECEXP (x, 0, 0);
5911
5912 fmt = GET_RTX_FORMAT (GET_CODE (x));
5913 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5914 {
5915 if (fmt[i] == 'e')
5916 {
5917 rtx fnd = find_ltrel_base (XEXP (x, i));
5918 if (fnd)
5919 return fnd;
5920 }
5921 else if (fmt[i] == 'E')
5922 {
5923 for (j = 0; j < XVECLEN (x, i); j++)
5924 {
5925 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5926 if (fnd)
5927 return fnd;
5928 }
5929 }
5930 }
5931
5932 return NULL_RTX;
5933 }
5934
5935 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5936
5937 static void
5938 replace_ltrel_base (rtx *x)
5939 {
5940 int i, j;
5941 const char *fmt;
5942
5943 if (GET_CODE (*x) == UNSPEC
5944 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5945 {
5946 *x = XVECEXP (*x, 0, 1);
5947 return;
5948 }
5949
5950 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5951 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5952 {
5953 if (fmt[i] == 'e')
5954 {
5955 replace_ltrel_base (&XEXP (*x, i));
5956 }
5957 else if (fmt[i] == 'E')
5958 {
5959 for (j = 0; j < XVECLEN (*x, i); j++)
5960 replace_ltrel_base (&XVECEXP (*x, i, j));
5961 }
5962 }
5963 }
5964
5965
5966 /* We keep a list of constants which we have to add to internal
5967 constant tables in the middle of large functions. */
5968
5969 #define NR_C_MODES 11
5970 enum machine_mode constant_modes[NR_C_MODES] =
5971 {
5972 TFmode, TImode, TDmode,
5973 DFmode, DImode, DDmode,
5974 SFmode, SImode, SDmode,
5975 HImode,
5976 QImode
5977 };
5978
5979 struct constant
5980 {
5981 struct constant *next;
5982 rtx value;
5983 rtx label;
5984 };
5985
5986 struct constant_pool
5987 {
5988 struct constant_pool *next;
5989 rtx first_insn;
5990 rtx pool_insn;
5991 bitmap insns;
5992 rtx emit_pool_after;
5993
5994 struct constant *constants[NR_C_MODES];
5995 struct constant *execute;
5996 rtx label;
5997 int size;
5998 };
5999
6000 /* Allocate new constant_pool structure. */
6001
6002 static struct constant_pool *
6003 s390_alloc_pool (void)
6004 {
6005 struct constant_pool *pool;
6006 int i;
6007
6008 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6009 pool->next = NULL;
6010 for (i = 0; i < NR_C_MODES; i++)
6011 pool->constants[i] = NULL;
6012
6013 pool->execute = NULL;
6014 pool->label = gen_label_rtx ();
6015 pool->first_insn = NULL_RTX;
6016 pool->pool_insn = NULL_RTX;
6017 pool->insns = BITMAP_ALLOC (NULL);
6018 pool->size = 0;
6019 pool->emit_pool_after = NULL_RTX;
6020
6021 return pool;
6022 }
6023
6024 /* Create new constant pool covering instructions starting at INSN
6025 and chain it to the end of POOL_LIST. */
6026
6027 static struct constant_pool *
6028 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6029 {
6030 struct constant_pool *pool, **prev;
6031
6032 pool = s390_alloc_pool ();
6033 pool->first_insn = insn;
6034
6035 for (prev = pool_list; *prev; prev = &(*prev)->next)
6036 ;
6037 *prev = pool;
6038
6039 return pool;
6040 }
6041
6042 /* End range of instructions covered by POOL at INSN and emit
6043 placeholder insn representing the pool. */
6044
6045 static void
6046 s390_end_pool (struct constant_pool *pool, rtx insn)
6047 {
6048 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6049
6050 if (!insn)
6051 insn = get_last_insn ();
6052
6053 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6054 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6055 }
6056
6057 /* Add INSN to the list of insns covered by POOL. */
6058
6059 static void
6060 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6061 {
6062 bitmap_set_bit (pool->insns, INSN_UID (insn));
6063 }
6064
6065 /* Return pool out of POOL_LIST that covers INSN. */
6066
6067 static struct constant_pool *
6068 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6069 {
6070 struct constant_pool *pool;
6071
6072 for (pool = pool_list; pool; pool = pool->next)
6073 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6074 break;
6075
6076 return pool;
6077 }
6078
6079 /* Add constant VAL of mode MODE to the constant pool POOL. */
6080
6081 static void
6082 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6083 {
6084 struct constant *c;
6085 int i;
6086
6087 for (i = 0; i < NR_C_MODES; i++)
6088 if (constant_modes[i] == mode)
6089 break;
6090 gcc_assert (i != NR_C_MODES);
6091
6092 for (c = pool->constants[i]; c != NULL; c = c->next)
6093 if (rtx_equal_p (val, c->value))
6094 break;
6095
6096 if (c == NULL)
6097 {
6098 c = (struct constant *) xmalloc (sizeof *c);
6099 c->value = val;
6100 c->label = gen_label_rtx ();
6101 c->next = pool->constants[i];
6102 pool->constants[i] = c;
6103 pool->size += GET_MODE_SIZE (mode);
6104 }
6105 }
6106
6107 /* Return an rtx that represents the offset of X from the start of
6108 pool POOL. */
6109
6110 static rtx
6111 s390_pool_offset (struct constant_pool *pool, rtx x)
6112 {
6113 rtx label;
6114
6115 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6116 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6117 UNSPEC_POOL_OFFSET);
6118 return gen_rtx_CONST (GET_MODE (x), x);
6119 }
6120
6121 /* Find constant VAL of mode MODE in the constant pool POOL.
6122 Return an RTX describing the distance from the start of
6123 the pool to the location of the new constant. */
6124
6125 static rtx
6126 s390_find_constant (struct constant_pool *pool, rtx val,
6127 enum machine_mode mode)
6128 {
6129 struct constant *c;
6130 int i;
6131
6132 for (i = 0; i < NR_C_MODES; i++)
6133 if (constant_modes[i] == mode)
6134 break;
6135 gcc_assert (i != NR_C_MODES);
6136
6137 for (c = pool->constants[i]; c != NULL; c = c->next)
6138 if (rtx_equal_p (val, c->value))
6139 break;
6140
6141 gcc_assert (c);
6142
6143 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6144 }
6145
6146 /* Check whether INSN is an execute. Return the label_ref to its
6147 execute target template if so, NULL_RTX otherwise. */
6148
6149 static rtx
6150 s390_execute_label (rtx insn)
6151 {
6152 if (GET_CODE (insn) == INSN
6153 && GET_CODE (PATTERN (insn)) == PARALLEL
6154 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6155 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6156 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6157
6158 return NULL_RTX;
6159 }
6160
6161 /* Add execute target for INSN to the constant pool POOL. */
6162
6163 static void
6164 s390_add_execute (struct constant_pool *pool, rtx insn)
6165 {
6166 struct constant *c;
6167
6168 for (c = pool->execute; c != NULL; c = c->next)
6169 if (INSN_UID (insn) == INSN_UID (c->value))
6170 break;
6171
6172 if (c == NULL)
6173 {
6174 c = (struct constant *) xmalloc (sizeof *c);
6175 c->value = insn;
6176 c->label = gen_label_rtx ();
6177 c->next = pool->execute;
6178 pool->execute = c;
6179 pool->size += 6;
6180 }
6181 }
6182
6183 /* Find execute target for INSN in the constant pool POOL.
6184 Return an RTX describing the distance from the start of
6185 the pool to the location of the execute target. */
6186
6187 static rtx
6188 s390_find_execute (struct constant_pool *pool, rtx insn)
6189 {
6190 struct constant *c;
6191
6192 for (c = pool->execute; c != NULL; c = c->next)
6193 if (INSN_UID (insn) == INSN_UID (c->value))
6194 break;
6195
6196 gcc_assert (c);
6197
6198 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6199 }
6200
6201 /* For an execute INSN, extract the execute target template. */
6202
6203 static rtx
6204 s390_execute_target (rtx insn)
6205 {
6206 rtx pattern = PATTERN (insn);
6207 gcc_assert (s390_execute_label (insn));
6208
6209 if (XVECLEN (pattern, 0) == 2)
6210 {
6211 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6212 }
6213 else
6214 {
6215 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6216 int i;
6217
6218 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6219 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6220
6221 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6222 }
6223
6224 return pattern;
6225 }
6226
6227 /* Indicate that INSN cannot be duplicated. This is the case for
6228 execute insns that carry a unique label. */
6229
6230 static bool
6231 s390_cannot_copy_insn_p (rtx insn)
6232 {
6233 rtx label = s390_execute_label (insn);
6234 return label && label != const0_rtx;
6235 }
6236
6237 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6238 do not emit the pool base label. */
6239
6240 static void
6241 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6242 {
6243 struct constant *c;
6244 rtx insn = pool->pool_insn;
6245 int i;
6246
6247 /* Switch to rodata section. */
6248 if (TARGET_CPU_ZARCH)
6249 {
6250 insn = emit_insn_after (gen_pool_section_start (), insn);
6251 INSN_ADDRESSES_NEW (insn, -1);
6252 }
6253
6254 /* Ensure minimum pool alignment. */
6255 if (TARGET_CPU_ZARCH)
6256 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6257 else
6258 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6259 INSN_ADDRESSES_NEW (insn, -1);
6260
6261 /* Emit pool base label. */
6262 if (!remote_label)
6263 {
6264 insn = emit_label_after (pool->label, insn);
6265 INSN_ADDRESSES_NEW (insn, -1);
6266 }
6267
6268 /* Dump constants in descending alignment requirement order,
6269 ensuring proper alignment for every constant. */
6270 for (i = 0; i < NR_C_MODES; i++)
6271 for (c = pool->constants[i]; c; c = c->next)
6272 {
6273 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6274 rtx value = copy_rtx (c->value);
6275 if (GET_CODE (value) == CONST
6276 && GET_CODE (XEXP (value, 0)) == UNSPEC
6277 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6278 && XVECLEN (XEXP (value, 0), 0) == 1)
6279 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6280
6281 insn = emit_label_after (c->label, insn);
6282 INSN_ADDRESSES_NEW (insn, -1);
6283
6284 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6285 gen_rtvec (1, value),
6286 UNSPECV_POOL_ENTRY);
6287 insn = emit_insn_after (value, insn);
6288 INSN_ADDRESSES_NEW (insn, -1);
6289 }
6290
6291 /* Ensure minimum alignment for instructions. */
6292 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6293 INSN_ADDRESSES_NEW (insn, -1);
6294
6295 /* Output in-pool execute template insns. */
6296 for (c = pool->execute; c; c = c->next)
6297 {
6298 insn = emit_label_after (c->label, insn);
6299 INSN_ADDRESSES_NEW (insn, -1);
6300
6301 insn = emit_insn_after (s390_execute_target (c->value), insn);
6302 INSN_ADDRESSES_NEW (insn, -1);
6303 }
6304
6305 /* Switch back to previous section. */
6306 if (TARGET_CPU_ZARCH)
6307 {
6308 insn = emit_insn_after (gen_pool_section_end (), insn);
6309 INSN_ADDRESSES_NEW (insn, -1);
6310 }
6311
6312 insn = emit_barrier_after (insn);
6313 INSN_ADDRESSES_NEW (insn, -1);
6314
6315 /* Remove placeholder insn. */
6316 remove_insn (pool->pool_insn);
6317 }
6318
6319 /* Free all memory used by POOL. */
6320
6321 static void
6322 s390_free_pool (struct constant_pool *pool)
6323 {
6324 struct constant *c, *next;
6325 int i;
6326
6327 for (i = 0; i < NR_C_MODES; i++)
6328 for (c = pool->constants[i]; c; c = next)
6329 {
6330 next = c->next;
6331 free (c);
6332 }
6333
6334 for (c = pool->execute; c; c = next)
6335 {
6336 next = c->next;
6337 free (c);
6338 }
6339
6340 BITMAP_FREE (pool->insns);
6341 free (pool);
6342 }
6343
6344
6345 /* Collect main literal pool. Return NULL on overflow. */
6346
6347 static struct constant_pool *
6348 s390_mainpool_start (void)
6349 {
6350 struct constant_pool *pool;
6351 rtx insn;
6352
6353 pool = s390_alloc_pool ();
6354
6355 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6356 {
6357 if (GET_CODE (insn) == INSN
6358 && GET_CODE (PATTERN (insn)) == SET
6359 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6360 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6361 {
6362 gcc_assert (!pool->pool_insn);
6363 pool->pool_insn = insn;
6364 }
6365
6366 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6367 {
6368 s390_add_execute (pool, insn);
6369 }
6370 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6371 {
6372 rtx pool_ref = NULL_RTX;
6373 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6374 if (pool_ref)
6375 {
6376 rtx constant = get_pool_constant (pool_ref);
6377 enum machine_mode mode = get_pool_mode (pool_ref);
6378 s390_add_constant (pool, constant, mode);
6379 }
6380 }
6381
6382 /* If hot/cold partitioning is enabled we have to make sure that
6383 the literal pool is emitted in the same section where the
6384 initialization of the literal pool base pointer takes place.
6385 emit_pool_after is only used in the non-overflow case on non
6386 Z cpus where we can emit the literal pool at the end of the
6387 function body within the text section. */
6388 if (NOTE_P (insn)
6389 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6390 && !pool->emit_pool_after)
6391 pool->emit_pool_after = PREV_INSN (insn);
6392 }
6393
6394 gcc_assert (pool->pool_insn || pool->size == 0);
6395
6396 if (pool->size >= 4096)
6397 {
6398 /* We're going to chunkify the pool, so remove the main
6399 pool placeholder insn. */
6400 remove_insn (pool->pool_insn);
6401
6402 s390_free_pool (pool);
6403 pool = NULL;
6404 }
6405
6406 /* If the functions ends with the section where the literal pool
6407 should be emitted set the marker to its end. */
6408 if (pool && !pool->emit_pool_after)
6409 pool->emit_pool_after = get_last_insn ();
6410
6411 return pool;
6412 }
6413
6414 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6415 Modify the current function to output the pool constants as well as
6416 the pool register setup instruction. */
6417
6418 static void
6419 s390_mainpool_finish (struct constant_pool *pool)
6420 {
6421 rtx base_reg = cfun->machine->base_reg;
6422 rtx insn;
6423
6424 /* If the pool is empty, we're done. */
6425 if (pool->size == 0)
6426 {
6427 /* We don't actually need a base register after all. */
6428 cfun->machine->base_reg = NULL_RTX;
6429
6430 if (pool->pool_insn)
6431 remove_insn (pool->pool_insn);
6432 s390_free_pool (pool);
6433 return;
6434 }
6435
6436 /* We need correct insn addresses. */
6437 shorten_branches (get_insns ());
6438
6439 /* On zSeries, we use a LARL to load the pool register. The pool is
6440 located in the .rodata section, so we emit it after the function. */
6441 if (TARGET_CPU_ZARCH)
6442 {
6443 insn = gen_main_base_64 (base_reg, pool->label);
6444 insn = emit_insn_after (insn, pool->pool_insn);
6445 INSN_ADDRESSES_NEW (insn, -1);
6446 remove_insn (pool->pool_insn);
6447
6448 insn = get_last_insn ();
6449 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6450 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6451
6452 s390_dump_pool (pool, 0);
6453 }
6454
6455 /* On S/390, if the total size of the function's code plus literal pool
6456 does not exceed 4096 bytes, we use BASR to set up a function base
6457 pointer, and emit the literal pool at the end of the function. */
6458 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6459 + pool->size + 8 /* alignment slop */ < 4096)
6460 {
6461 insn = gen_main_base_31_small (base_reg, pool->label);
6462 insn = emit_insn_after (insn, pool->pool_insn);
6463 INSN_ADDRESSES_NEW (insn, -1);
6464 remove_insn (pool->pool_insn);
6465
6466 insn = emit_label_after (pool->label, insn);
6467 INSN_ADDRESSES_NEW (insn, -1);
6468
6469 /* emit_pool_after will be set by s390_mainpool_start to the
6470 last insn of the section where the literal pool should be
6471 emitted. */
6472 insn = pool->emit_pool_after;
6473
6474 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6475 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6476
6477 s390_dump_pool (pool, 1);
6478 }
6479
6480 /* Otherwise, we emit an inline literal pool and use BASR to branch
6481 over it, setting up the pool register at the same time. */
6482 else
6483 {
6484 rtx pool_end = gen_label_rtx ();
6485
6486 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6487 insn = emit_jump_insn_after (insn, pool->pool_insn);
6488 JUMP_LABEL (insn) = pool_end;
6489 INSN_ADDRESSES_NEW (insn, -1);
6490 remove_insn (pool->pool_insn);
6491
6492 insn = emit_label_after (pool->label, insn);
6493 INSN_ADDRESSES_NEW (insn, -1);
6494
6495 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6496 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6497
6498 insn = emit_label_after (pool_end, pool->pool_insn);
6499 INSN_ADDRESSES_NEW (insn, -1);
6500
6501 s390_dump_pool (pool, 1);
6502 }
6503
6504
6505 /* Replace all literal pool references. */
6506
6507 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6508 {
6509 if (INSN_P (insn))
6510 replace_ltrel_base (&PATTERN (insn));
6511
6512 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6513 {
6514 rtx addr, pool_ref = NULL_RTX;
6515 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6516 if (pool_ref)
6517 {
6518 if (s390_execute_label (insn))
6519 addr = s390_find_execute (pool, insn);
6520 else
6521 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6522 get_pool_mode (pool_ref));
6523
6524 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6525 INSN_CODE (insn) = -1;
6526 }
6527 }
6528 }
6529
6530
6531 /* Free the pool. */
6532 s390_free_pool (pool);
6533 }
6534
6535 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6536 We have decided we cannot use this pool, so revert all changes
6537 to the current function that were done by s390_mainpool_start. */
6538 static void
6539 s390_mainpool_cancel (struct constant_pool *pool)
6540 {
6541 /* We didn't actually change the instruction stream, so simply
6542 free the pool memory. */
6543 s390_free_pool (pool);
6544 }
6545
6546
6547 /* Chunkify the literal pool. */
6548
6549 #define S390_POOL_CHUNK_MIN 0xc00
6550 #define S390_POOL_CHUNK_MAX 0xe00
6551
6552 static struct constant_pool *
6553 s390_chunkify_start (void)
6554 {
6555 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6556 int extra_size = 0;
6557 bitmap far_labels;
6558 rtx pending_ltrel = NULL_RTX;
6559 rtx insn;
6560
6561 rtx (*gen_reload_base) (rtx, rtx) =
6562 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6563
6564
6565 /* We need correct insn addresses. */
6566
6567 shorten_branches (get_insns ());
6568
6569 /* Scan all insns and move literals to pool chunks. */
6570
6571 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6572 {
6573 bool section_switch_p = false;
6574
6575 /* Check for pending LTREL_BASE. */
6576 if (INSN_P (insn))
6577 {
6578 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6579 if (ltrel_base)
6580 {
6581 gcc_assert (ltrel_base == pending_ltrel);
6582 pending_ltrel = NULL_RTX;
6583 }
6584 }
6585
6586 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6587 {
6588 if (!curr_pool)
6589 curr_pool = s390_start_pool (&pool_list, insn);
6590
6591 s390_add_execute (curr_pool, insn);
6592 s390_add_pool_insn (curr_pool, insn);
6593 }
6594 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6595 {
6596 rtx pool_ref = NULL_RTX;
6597 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6598 if (pool_ref)
6599 {
6600 rtx constant = get_pool_constant (pool_ref);
6601 enum machine_mode mode = get_pool_mode (pool_ref);
6602
6603 if (!curr_pool)
6604 curr_pool = s390_start_pool (&pool_list, insn);
6605
6606 s390_add_constant (curr_pool, constant, mode);
6607 s390_add_pool_insn (curr_pool, insn);
6608
6609 /* Don't split the pool chunk between a LTREL_OFFSET load
6610 and the corresponding LTREL_BASE. */
6611 if (GET_CODE (constant) == CONST
6612 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6613 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6614 {
6615 gcc_assert (!pending_ltrel);
6616 pending_ltrel = pool_ref;
6617 }
6618 }
6619 }
6620
6621 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6622 {
6623 if (curr_pool)
6624 s390_add_pool_insn (curr_pool, insn);
6625 /* An LTREL_BASE must follow within the same basic block. */
6626 gcc_assert (!pending_ltrel);
6627 }
6628
6629 if (NOTE_P (insn))
6630 switch (NOTE_KIND (insn))
6631 {
6632 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6633 section_switch_p = true;
6634 break;
6635 case NOTE_INSN_VAR_LOCATION:
6636 case NOTE_INSN_CALL_ARG_LOCATION:
6637 continue;
6638 default:
6639 break;
6640 }
6641
6642 if (!curr_pool
6643 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6644 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6645 continue;
6646
6647 if (TARGET_CPU_ZARCH)
6648 {
6649 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6650 continue;
6651
6652 s390_end_pool (curr_pool, NULL_RTX);
6653 curr_pool = NULL;
6654 }
6655 else
6656 {
6657 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6658 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6659 + extra_size;
6660
6661 /* We will later have to insert base register reload insns.
6662 Those will have an effect on code size, which we need to
6663 consider here. This calculation makes rather pessimistic
6664 worst-case assumptions. */
6665 if (GET_CODE (insn) == CODE_LABEL)
6666 extra_size += 6;
6667
6668 if (chunk_size < S390_POOL_CHUNK_MIN
6669 && curr_pool->size < S390_POOL_CHUNK_MIN
6670 && !section_switch_p)
6671 continue;
6672
6673 /* Pool chunks can only be inserted after BARRIERs ... */
6674 if (GET_CODE (insn) == BARRIER)
6675 {
6676 s390_end_pool (curr_pool, insn);
6677 curr_pool = NULL;
6678 extra_size = 0;
6679 }
6680
6681 /* ... so if we don't find one in time, create one. */
6682 else if (chunk_size > S390_POOL_CHUNK_MAX
6683 || curr_pool->size > S390_POOL_CHUNK_MAX
6684 || section_switch_p)
6685 {
6686 rtx label, jump, barrier, next, prev;
6687
6688 if (!section_switch_p)
6689 {
6690 /* We can insert the barrier only after a 'real' insn. */
6691 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6692 continue;
6693 if (get_attr_length (insn) == 0)
6694 continue;
6695 /* Don't separate LTREL_BASE from the corresponding
6696 LTREL_OFFSET load. */
6697 if (pending_ltrel)
6698 continue;
6699 next = insn;
6700 do
6701 {
6702 insn = next;
6703 next = NEXT_INSN (insn);
6704 }
6705 while (next
6706 && NOTE_P (next)
6707 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6708 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6709 }
6710 else
6711 {
6712 gcc_assert (!pending_ltrel);
6713
6714 /* The old pool has to end before the section switch
6715 note in order to make it part of the current
6716 section. */
6717 insn = PREV_INSN (insn);
6718 }
6719
6720 label = gen_label_rtx ();
6721 prev = insn;
6722 if (prev && NOTE_P (prev))
6723 prev = prev_nonnote_insn (prev);
6724 if (prev)
6725 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6726 INSN_LOCATOR (prev));
6727 else
6728 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6729 barrier = emit_barrier_after (jump);
6730 insn = emit_label_after (label, barrier);
6731 JUMP_LABEL (jump) = label;
6732 LABEL_NUSES (label) = 1;
6733
6734 INSN_ADDRESSES_NEW (jump, -1);
6735 INSN_ADDRESSES_NEW (barrier, -1);
6736 INSN_ADDRESSES_NEW (insn, -1);
6737
6738 s390_end_pool (curr_pool, barrier);
6739 curr_pool = NULL;
6740 extra_size = 0;
6741 }
6742 }
6743 }
6744
6745 if (curr_pool)
6746 s390_end_pool (curr_pool, NULL_RTX);
6747 gcc_assert (!pending_ltrel);
6748
6749 /* Find all labels that are branched into
6750 from an insn belonging to a different chunk. */
6751
6752 far_labels = BITMAP_ALLOC (NULL);
6753
6754 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6755 {
6756 /* Labels marked with LABEL_PRESERVE_P can be target
6757 of non-local jumps, so we have to mark them.
6758 The same holds for named labels.
6759
6760 Don't do that, however, if it is the label before
6761 a jump table. */
6762
6763 if (GET_CODE (insn) == CODE_LABEL
6764 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6765 {
6766 rtx vec_insn = next_real_insn (insn);
6767 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6768 PATTERN (vec_insn) : NULL_RTX;
6769 if (!vec_pat
6770 || !(GET_CODE (vec_pat) == ADDR_VEC
6771 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6772 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6773 }
6774
6775 /* If we have a direct jump (conditional or unconditional)
6776 or a casesi jump, check all potential targets. */
6777 else if (GET_CODE (insn) == JUMP_INSN)
6778 {
6779 rtx pat = PATTERN (insn);
6780 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6781 pat = XVECEXP (pat, 0, 0);
6782
6783 if (GET_CODE (pat) == SET)
6784 {
6785 rtx label = JUMP_LABEL (insn);
6786 if (label)
6787 {
6788 if (s390_find_pool (pool_list, label)
6789 != s390_find_pool (pool_list, insn))
6790 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6791 }
6792 }
6793 else if (GET_CODE (pat) == PARALLEL
6794 && XVECLEN (pat, 0) == 2
6795 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6796 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6797 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6798 {
6799 /* Find the jump table used by this casesi jump. */
6800 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6801 rtx vec_insn = next_real_insn (vec_label);
6802 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6803 PATTERN (vec_insn) : NULL_RTX;
6804 if (vec_pat
6805 && (GET_CODE (vec_pat) == ADDR_VEC
6806 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6807 {
6808 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6809
6810 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6811 {
6812 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6813
6814 if (s390_find_pool (pool_list, label)
6815 != s390_find_pool (pool_list, insn))
6816 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6817 }
6818 }
6819 }
6820 }
6821 }
6822
6823 /* Insert base register reload insns before every pool. */
6824
6825 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6826 {
6827 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6828 curr_pool->label);
6829 rtx insn = curr_pool->first_insn;
6830 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6831 }
6832
6833 /* Insert base register reload insns at every far label. */
6834
6835 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6836 if (GET_CODE (insn) == CODE_LABEL
6837 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6838 {
6839 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6840 if (pool)
6841 {
6842 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6843 pool->label);
6844 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6845 }
6846 }
6847
6848
6849 BITMAP_FREE (far_labels);
6850
6851
6852 /* Recompute insn addresses. */
6853
6854 init_insn_lengths ();
6855 shorten_branches (get_insns ());
6856
6857 return pool_list;
6858 }
6859
6860 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6861 After we have decided to use this list, finish implementing
6862 all changes to the current function as required. */
6863
6864 static void
6865 s390_chunkify_finish (struct constant_pool *pool_list)
6866 {
6867 struct constant_pool *curr_pool = NULL;
6868 rtx insn;
6869
6870
6871 /* Replace all literal pool references. */
6872
6873 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6874 {
6875 if (INSN_P (insn))
6876 replace_ltrel_base (&PATTERN (insn));
6877
6878 curr_pool = s390_find_pool (pool_list, insn);
6879 if (!curr_pool)
6880 continue;
6881
6882 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6883 {
6884 rtx addr, pool_ref = NULL_RTX;
6885 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6886 if (pool_ref)
6887 {
6888 if (s390_execute_label (insn))
6889 addr = s390_find_execute (curr_pool, insn);
6890 else
6891 addr = s390_find_constant (curr_pool,
6892 get_pool_constant (pool_ref),
6893 get_pool_mode (pool_ref));
6894
6895 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6896 INSN_CODE (insn) = -1;
6897 }
6898 }
6899 }
6900
6901 /* Dump out all literal pools. */
6902
6903 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6904 s390_dump_pool (curr_pool, 0);
6905
6906 /* Free pool list. */
6907
6908 while (pool_list)
6909 {
6910 struct constant_pool *next = pool_list->next;
6911 s390_free_pool (pool_list);
6912 pool_list = next;
6913 }
6914 }
6915
6916 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6917 We have decided we cannot use this list, so revert all changes
6918 to the current function that were done by s390_chunkify_start. */
6919
6920 static void
6921 s390_chunkify_cancel (struct constant_pool *pool_list)
6922 {
6923 struct constant_pool *curr_pool = NULL;
6924 rtx insn;
6925
6926 /* Remove all pool placeholder insns. */
6927
6928 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6929 {
6930 /* Did we insert an extra barrier? Remove it. */
6931 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6932 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6933 rtx label = NEXT_INSN (curr_pool->pool_insn);
6934
6935 if (jump && GET_CODE (jump) == JUMP_INSN
6936 && barrier && GET_CODE (barrier) == BARRIER
6937 && label && GET_CODE (label) == CODE_LABEL
6938 && GET_CODE (PATTERN (jump)) == SET
6939 && SET_DEST (PATTERN (jump)) == pc_rtx
6940 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6941 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6942 {
6943 remove_insn (jump);
6944 remove_insn (barrier);
6945 remove_insn (label);
6946 }
6947
6948 remove_insn (curr_pool->pool_insn);
6949 }
6950
6951 /* Remove all base register reload insns. */
6952
6953 for (insn = get_insns (); insn; )
6954 {
6955 rtx next_insn = NEXT_INSN (insn);
6956
6957 if (GET_CODE (insn) == INSN
6958 && GET_CODE (PATTERN (insn)) == SET
6959 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6960 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6961 remove_insn (insn);
6962
6963 insn = next_insn;
6964 }
6965
6966 /* Free pool list. */
6967
6968 while (pool_list)
6969 {
6970 struct constant_pool *next = pool_list->next;
6971 s390_free_pool (pool_list);
6972 pool_list = next;
6973 }
6974 }
6975
6976 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6977
6978 void
6979 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6980 {
6981 REAL_VALUE_TYPE r;
6982
6983 switch (GET_MODE_CLASS (mode))
6984 {
6985 case MODE_FLOAT:
6986 case MODE_DECIMAL_FLOAT:
6987 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6988
6989 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6990 assemble_real (r, mode, align);
6991 break;
6992
6993 case MODE_INT:
6994 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6995 mark_symbol_refs_as_used (exp);
6996 break;
6997
6998 default:
6999 gcc_unreachable ();
7000 }
7001 }
7002
7003
7004 /* Return an RTL expression representing the value of the return address
7005 for the frame COUNT steps up from the current frame. FRAME is the
7006 frame pointer of that frame. */
7007
7008 rtx
7009 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7010 {
7011 int offset;
7012 rtx addr;
7013
7014 /* Without backchain, we fail for all but the current frame. */
7015
7016 if (!TARGET_BACKCHAIN && count > 0)
7017 return NULL_RTX;
7018
7019 /* For the current frame, we need to make sure the initial
7020 value of RETURN_REGNUM is actually saved. */
7021
7022 if (count == 0)
7023 {
7024 /* On non-z architectures branch splitting could overwrite r14. */
7025 if (TARGET_CPU_ZARCH)
7026 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7027 else
7028 {
7029 cfun_frame_layout.save_return_addr_p = true;
7030 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7031 }
7032 }
7033
7034 if (TARGET_PACKED_STACK)
7035 offset = -2 * UNITS_PER_LONG;
7036 else
7037 offset = RETURN_REGNUM * UNITS_PER_LONG;
7038
7039 addr = plus_constant (Pmode, frame, offset);
7040 addr = memory_address (Pmode, addr);
7041 return gen_rtx_MEM (Pmode, addr);
7042 }
7043
7044 /* Return an RTL expression representing the back chain stored in
7045 the current stack frame. */
7046
7047 rtx
7048 s390_back_chain_rtx (void)
7049 {
7050 rtx chain;
7051
7052 gcc_assert (TARGET_BACKCHAIN);
7053
7054 if (TARGET_PACKED_STACK)
7055 chain = plus_constant (Pmode, stack_pointer_rtx,
7056 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7057 else
7058 chain = stack_pointer_rtx;
7059
7060 chain = gen_rtx_MEM (Pmode, chain);
7061 return chain;
7062 }
7063
7064 /* Find first call clobbered register unused in a function.
7065 This could be used as base register in a leaf function
7066 or for holding the return address before epilogue. */
7067
7068 static int
7069 find_unused_clobbered_reg (void)
7070 {
7071 int i;
7072 for (i = 0; i < 6; i++)
7073 if (!df_regs_ever_live_p (i))
7074 return i;
7075 return 0;
7076 }
7077
7078
7079 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7080 clobbered hard regs in SETREG. */
7081
7082 static void
7083 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7084 {
7085 int *regs_ever_clobbered = (int *)data;
7086 unsigned int i, regno;
7087 enum machine_mode mode = GET_MODE (setreg);
7088
7089 if (GET_CODE (setreg) == SUBREG)
7090 {
7091 rtx inner = SUBREG_REG (setreg);
7092 if (!GENERAL_REG_P (inner))
7093 return;
7094 regno = subreg_regno (setreg);
7095 }
7096 else if (GENERAL_REG_P (setreg))
7097 regno = REGNO (setreg);
7098 else
7099 return;
7100
7101 for (i = regno;
7102 i < regno + HARD_REGNO_NREGS (regno, mode);
7103 i++)
7104 regs_ever_clobbered[i] = 1;
7105 }
7106
7107 /* Walks through all basic blocks of the current function looking
7108 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7109 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7110 each of those regs. */
7111
7112 static void
7113 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7114 {
7115 basic_block cur_bb;
7116 rtx cur_insn;
7117 unsigned int i;
7118
7119 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7120
7121 /* For non-leaf functions we have to consider all call clobbered regs to be
7122 clobbered. */
7123 if (!current_function_is_leaf)
7124 {
7125 for (i = 0; i < 16; i++)
7126 regs_ever_clobbered[i] = call_really_used_regs[i];
7127 }
7128
7129 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7130 this work is done by liveness analysis (mark_regs_live_at_end).
7131 Special care is needed for functions containing landing pads. Landing pads
7132 may use the eh registers, but the code which sets these registers is not
7133 contained in that function. Hence s390_regs_ever_clobbered is not able to
7134 deal with this automatically. */
7135 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7136 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7137 if (crtl->calls_eh_return
7138 || (cfun->machine->has_landing_pad_p
7139 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7140 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7141
7142 /* For nonlocal gotos all call-saved registers have to be saved.
7143 This flag is also set for the unwinding code in libgcc.
7144 See expand_builtin_unwind_init. For regs_ever_live this is done by
7145 reload. */
7146 if (cfun->has_nonlocal_label)
7147 for (i = 0; i < 16; i++)
7148 if (!call_really_used_regs[i])
7149 regs_ever_clobbered[i] = 1;
7150
7151 FOR_EACH_BB (cur_bb)
7152 {
7153 FOR_BB_INSNS (cur_bb, cur_insn)
7154 {
7155 if (INSN_P (cur_insn))
7156 note_stores (PATTERN (cur_insn),
7157 s390_reg_clobbered_rtx,
7158 regs_ever_clobbered);
7159 }
7160 }
7161 }
7162
7163 /* Determine the frame area which actually has to be accessed
7164 in the function epilogue. The values are stored at the
7165 given pointers AREA_BOTTOM (address of the lowest used stack
7166 address) and AREA_TOP (address of the first item which does
7167 not belong to the stack frame). */
7168
7169 static void
7170 s390_frame_area (int *area_bottom, int *area_top)
7171 {
7172 int b, t;
7173 int i;
7174
7175 b = INT_MAX;
7176 t = INT_MIN;
7177
7178 if (cfun_frame_layout.first_restore_gpr != -1)
7179 {
7180 b = (cfun_frame_layout.gprs_offset
7181 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7182 t = b + (cfun_frame_layout.last_restore_gpr
7183 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7184 }
7185
7186 if (TARGET_64BIT && cfun_save_high_fprs_p)
7187 {
7188 b = MIN (b, cfun_frame_layout.f8_offset);
7189 t = MAX (t, (cfun_frame_layout.f8_offset
7190 + cfun_frame_layout.high_fprs * 8));
7191 }
7192
7193 if (!TARGET_64BIT)
7194 for (i = 2; i < 4; i++)
7195 if (cfun_fpr_bit_p (i))
7196 {
7197 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7198 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7199 }
7200
7201 *area_bottom = b;
7202 *area_top = t;
7203 }
7204
7205 /* Fill cfun->machine with info about register usage of current function.
7206 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7207
7208 static void
7209 s390_register_info (int clobbered_regs[])
7210 {
7211 int i, j;
7212
7213 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7214 cfun_frame_layout.fpr_bitmap = 0;
7215 cfun_frame_layout.high_fprs = 0;
7216 if (TARGET_64BIT)
7217 for (i = 24; i < 32; i++)
7218 if (df_regs_ever_live_p (i) && !global_regs[i])
7219 {
7220 cfun_set_fpr_bit (i - 16);
7221 cfun_frame_layout.high_fprs++;
7222 }
7223
7224 /* Find first and last gpr to be saved. We trust regs_ever_live
7225 data, except that we don't save and restore global registers.
7226
7227 Also, all registers with special meaning to the compiler need
7228 to be handled extra. */
7229
7230 s390_regs_ever_clobbered (clobbered_regs);
7231
7232 for (i = 0; i < 16; i++)
7233 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7234
7235 if (frame_pointer_needed)
7236 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7237
7238 if (flag_pic)
7239 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7240 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7241
7242 clobbered_regs[BASE_REGNUM]
7243 |= (cfun->machine->base_reg
7244 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7245
7246 clobbered_regs[RETURN_REGNUM]
7247 |= (!current_function_is_leaf
7248 || TARGET_TPF_PROFILING
7249 || cfun->machine->split_branches_pending_p
7250 || cfun_frame_layout.save_return_addr_p
7251 || crtl->calls_eh_return
7252 || cfun->stdarg);
7253
7254 clobbered_regs[STACK_POINTER_REGNUM]
7255 |= (!current_function_is_leaf
7256 || TARGET_TPF_PROFILING
7257 || cfun_save_high_fprs_p
7258 || get_frame_size () > 0
7259 || cfun->calls_alloca
7260 || cfun->stdarg);
7261
7262 for (i = 6; i < 16; i++)
7263 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7264 break;
7265 for (j = 15; j > i; j--)
7266 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7267 break;
7268
7269 if (i == 16)
7270 {
7271 /* Nothing to save/restore. */
7272 cfun_frame_layout.first_save_gpr_slot = -1;
7273 cfun_frame_layout.last_save_gpr_slot = -1;
7274 cfun_frame_layout.first_save_gpr = -1;
7275 cfun_frame_layout.first_restore_gpr = -1;
7276 cfun_frame_layout.last_save_gpr = -1;
7277 cfun_frame_layout.last_restore_gpr = -1;
7278 }
7279 else
7280 {
7281 /* Save slots for gprs from i to j. */
7282 cfun_frame_layout.first_save_gpr_slot = i;
7283 cfun_frame_layout.last_save_gpr_slot = j;
7284
7285 for (i = cfun_frame_layout.first_save_gpr_slot;
7286 i < cfun_frame_layout.last_save_gpr_slot + 1;
7287 i++)
7288 if (clobbered_regs[i])
7289 break;
7290
7291 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7292 if (clobbered_regs[j])
7293 break;
7294
7295 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7296 {
7297 /* Nothing to save/restore. */
7298 cfun_frame_layout.first_save_gpr = -1;
7299 cfun_frame_layout.first_restore_gpr = -1;
7300 cfun_frame_layout.last_save_gpr = -1;
7301 cfun_frame_layout.last_restore_gpr = -1;
7302 }
7303 else
7304 {
7305 /* Save / Restore from gpr i to j. */
7306 cfun_frame_layout.first_save_gpr = i;
7307 cfun_frame_layout.first_restore_gpr = i;
7308 cfun_frame_layout.last_save_gpr = j;
7309 cfun_frame_layout.last_restore_gpr = j;
7310 }
7311 }
7312
7313 if (cfun->stdarg)
7314 {
7315 /* Varargs functions need to save gprs 2 to 6. */
7316 if (cfun->va_list_gpr_size
7317 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7318 {
7319 int min_gpr = crtl->args.info.gprs;
7320 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7321 if (max_gpr > GP_ARG_NUM_REG)
7322 max_gpr = GP_ARG_NUM_REG;
7323
7324 if (cfun_frame_layout.first_save_gpr == -1
7325 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7326 {
7327 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7328 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7329 }
7330
7331 if (cfun_frame_layout.last_save_gpr == -1
7332 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7333 {
7334 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7335 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7336 }
7337 }
7338
7339 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7340 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7341 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7342 {
7343 int min_fpr = crtl->args.info.fprs;
7344 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7345 if (max_fpr > FP_ARG_NUM_REG)
7346 max_fpr = FP_ARG_NUM_REG;
7347
7348 /* ??? This is currently required to ensure proper location
7349 of the fpr save slots within the va_list save area. */
7350 if (TARGET_PACKED_STACK)
7351 min_fpr = 0;
7352
7353 for (i = min_fpr; i < max_fpr; i++)
7354 cfun_set_fpr_bit (i);
7355 }
7356 }
7357
7358 if (!TARGET_64BIT)
7359 for (i = 2; i < 4; i++)
7360 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7361 cfun_set_fpr_bit (i);
7362 }
7363
7364 /* Fill cfun->machine with info about frame of current function. */
7365
7366 static void
7367 s390_frame_info (void)
7368 {
7369 int i;
7370
7371 cfun_frame_layout.frame_size = get_frame_size ();
7372 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7373 fatal_error ("total size of local variables exceeds architecture limit");
7374
7375 if (!TARGET_PACKED_STACK)
7376 {
7377 cfun_frame_layout.backchain_offset = 0;
7378 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7379 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7380 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7381 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7382 * UNITS_PER_LONG);
7383 }
7384 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7385 {
7386 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7387 - UNITS_PER_LONG);
7388 cfun_frame_layout.gprs_offset
7389 = (cfun_frame_layout.backchain_offset
7390 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7391 * UNITS_PER_LONG);
7392
7393 if (TARGET_64BIT)
7394 {
7395 cfun_frame_layout.f4_offset
7396 = (cfun_frame_layout.gprs_offset
7397 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7398
7399 cfun_frame_layout.f0_offset
7400 = (cfun_frame_layout.f4_offset
7401 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7402 }
7403 else
7404 {
7405 /* On 31 bit we have to care about alignment of the
7406 floating point regs to provide fastest access. */
7407 cfun_frame_layout.f0_offset
7408 = ((cfun_frame_layout.gprs_offset
7409 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7410 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7411
7412 cfun_frame_layout.f4_offset
7413 = (cfun_frame_layout.f0_offset
7414 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7415 }
7416 }
7417 else /* no backchain */
7418 {
7419 cfun_frame_layout.f4_offset
7420 = (STACK_POINTER_OFFSET
7421 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7422
7423 cfun_frame_layout.f0_offset
7424 = (cfun_frame_layout.f4_offset
7425 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7426
7427 cfun_frame_layout.gprs_offset
7428 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7429 }
7430
7431 if (current_function_is_leaf
7432 && !TARGET_TPF_PROFILING
7433 && cfun_frame_layout.frame_size == 0
7434 && !cfun_save_high_fprs_p
7435 && !cfun->calls_alloca
7436 && !cfun->stdarg)
7437 return;
7438
7439 if (!TARGET_PACKED_STACK)
7440 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7441 + crtl->outgoing_args_size
7442 + cfun_frame_layout.high_fprs * 8);
7443 else
7444 {
7445 if (TARGET_BACKCHAIN)
7446 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7447
7448 /* No alignment trouble here because f8-f15 are only saved under
7449 64 bit. */
7450 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7451 cfun_frame_layout.f4_offset),
7452 cfun_frame_layout.gprs_offset)
7453 - cfun_frame_layout.high_fprs * 8);
7454
7455 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7456
7457 for (i = 0; i < 8; i++)
7458 if (cfun_fpr_bit_p (i))
7459 cfun_frame_layout.frame_size += 8;
7460
7461 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7462
7463 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7464 the frame size to sustain 8 byte alignment of stack frames. */
7465 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7466 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7467 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7468
7469 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7470 }
7471 }
7472
7473 /* Generate frame layout. Fills in register and frame data for the current
7474 function in cfun->machine. This routine can be called multiple times;
7475 it will re-do the complete frame layout every time. */
7476
7477 static void
7478 s390_init_frame_layout (void)
7479 {
7480 HOST_WIDE_INT frame_size;
7481 int base_used;
7482 int clobbered_regs[16];
7483
7484 /* On S/390 machines, we may need to perform branch splitting, which
7485 will require both base and return address register. We have no
7486 choice but to assume we're going to need them until right at the
7487 end of the machine dependent reorg phase. */
7488 if (!TARGET_CPU_ZARCH)
7489 cfun->machine->split_branches_pending_p = true;
7490
7491 do
7492 {
7493 frame_size = cfun_frame_layout.frame_size;
7494
7495 /* Try to predict whether we'll need the base register. */
7496 base_used = cfun->machine->split_branches_pending_p
7497 || crtl->uses_const_pool
7498 || (!DISP_IN_RANGE (frame_size)
7499 && !CONST_OK_FOR_K (frame_size));
7500
7501 /* Decide which register to use as literal pool base. In small
7502 leaf functions, try to use an unused call-clobbered register
7503 as base register to avoid save/restore overhead. */
7504 if (!base_used)
7505 cfun->machine->base_reg = NULL_RTX;
7506 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7507 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7508 else
7509 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7510
7511 s390_register_info (clobbered_regs);
7512 s390_frame_info ();
7513 }
7514 while (frame_size != cfun_frame_layout.frame_size);
7515 }
7516
7517 /* Update frame layout. Recompute actual register save data based on
7518 current info and update regs_ever_live for the special registers.
7519 May be called multiple times, but may never cause *more* registers
7520 to be saved than s390_init_frame_layout allocated room for. */
7521
7522 static void
7523 s390_update_frame_layout (void)
7524 {
7525 int clobbered_regs[16];
7526
7527 s390_register_info (clobbered_regs);
7528
7529 df_set_regs_ever_live (BASE_REGNUM,
7530 clobbered_regs[BASE_REGNUM] ? true : false);
7531 df_set_regs_ever_live (RETURN_REGNUM,
7532 clobbered_regs[RETURN_REGNUM] ? true : false);
7533 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7534 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7535
7536 if (cfun->machine->base_reg)
7537 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7538 }
7539
7540 /* Return true if it is legal to put a value with MODE into REGNO. */
7541
7542 bool
7543 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7544 {
7545 switch (REGNO_REG_CLASS (regno))
7546 {
7547 case FP_REGS:
7548 if (REGNO_PAIR_OK (regno, mode))
7549 {
7550 if (mode == SImode || mode == DImode)
7551 return true;
7552
7553 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7554 return true;
7555 }
7556 break;
7557 case ADDR_REGS:
7558 if (FRAME_REGNO_P (regno) && mode == Pmode)
7559 return true;
7560
7561 /* fallthrough */
7562 case GENERAL_REGS:
7563 if (REGNO_PAIR_OK (regno, mode))
7564 {
7565 if (TARGET_ZARCH
7566 || (mode != TFmode && mode != TCmode && mode != TDmode))
7567 return true;
7568 }
7569 break;
7570 case CC_REGS:
7571 if (GET_MODE_CLASS (mode) == MODE_CC)
7572 return true;
7573 break;
7574 case ACCESS_REGS:
7575 if (REGNO_PAIR_OK (regno, mode))
7576 {
7577 if (mode == SImode || mode == Pmode)
7578 return true;
7579 }
7580 break;
7581 default:
7582 return false;
7583 }
7584
7585 return false;
7586 }
7587
7588 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7589
7590 bool
7591 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7592 {
7593 /* Once we've decided upon a register to use as base register, it must
7594 no longer be used for any other purpose. */
7595 if (cfun->machine->base_reg)
7596 if (REGNO (cfun->machine->base_reg) == old_reg
7597 || REGNO (cfun->machine->base_reg) == new_reg)
7598 return false;
7599
7600 return true;
7601 }
7602
7603 /* Maximum number of registers to represent a value of mode MODE
7604 in a register of class RCLASS. */
7605
7606 int
7607 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7608 {
7609 switch (rclass)
7610 {
7611 case FP_REGS:
7612 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7613 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7614 else
7615 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7616 case ACCESS_REGS:
7617 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7618 default:
7619 break;
7620 }
7621 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7622 }
7623
7624 /* Return true if register FROM can be eliminated via register TO. */
7625
7626 static bool
7627 s390_can_eliminate (const int from, const int to)
7628 {
7629 /* On zSeries machines, we have not marked the base register as fixed.
7630 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7631 If a function requires the base register, we say here that this
7632 elimination cannot be performed. This will cause reload to free
7633 up the base register (as if it were fixed). On the other hand,
7634 if the current function does *not* require the base register, we
7635 say here the elimination succeeds, which in turn allows reload
7636 to allocate the base register for any other purpose. */
7637 if (from == BASE_REGNUM && to == BASE_REGNUM)
7638 {
7639 if (TARGET_CPU_ZARCH)
7640 {
7641 s390_init_frame_layout ();
7642 return cfun->machine->base_reg == NULL_RTX;
7643 }
7644
7645 return false;
7646 }
7647
7648 /* Everything else must point into the stack frame. */
7649 gcc_assert (to == STACK_POINTER_REGNUM
7650 || to == HARD_FRAME_POINTER_REGNUM);
7651
7652 gcc_assert (from == FRAME_POINTER_REGNUM
7653 || from == ARG_POINTER_REGNUM
7654 || from == RETURN_ADDRESS_POINTER_REGNUM);
7655
7656 /* Make sure we actually saved the return address. */
7657 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7658 if (!crtl->calls_eh_return
7659 && !cfun->stdarg
7660 && !cfun_frame_layout.save_return_addr_p)
7661 return false;
7662
7663 return true;
7664 }
7665
7666 /* Return offset between register FROM and TO initially after prolog. */
7667
7668 HOST_WIDE_INT
7669 s390_initial_elimination_offset (int from, int to)
7670 {
7671 HOST_WIDE_INT offset;
7672 int index;
7673
7674 /* ??? Why are we called for non-eliminable pairs? */
7675 if (!s390_can_eliminate (from, to))
7676 return 0;
7677
7678 switch (from)
7679 {
7680 case FRAME_POINTER_REGNUM:
7681 offset = (get_frame_size()
7682 + STACK_POINTER_OFFSET
7683 + crtl->outgoing_args_size);
7684 break;
7685
7686 case ARG_POINTER_REGNUM:
7687 s390_init_frame_layout ();
7688 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7689 break;
7690
7691 case RETURN_ADDRESS_POINTER_REGNUM:
7692 s390_init_frame_layout ();
7693 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7694 gcc_assert (index >= 0);
7695 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7696 offset += index * UNITS_PER_LONG;
7697 break;
7698
7699 case BASE_REGNUM:
7700 offset = 0;
7701 break;
7702
7703 default:
7704 gcc_unreachable ();
7705 }
7706
7707 return offset;
7708 }
7709
7710 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7711 to register BASE. Return generated insn. */
7712
7713 static rtx
7714 save_fpr (rtx base, int offset, int regnum)
7715 {
7716 rtx addr;
7717 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7718
7719 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7720 set_mem_alias_set (addr, get_varargs_alias_set ());
7721 else
7722 set_mem_alias_set (addr, get_frame_alias_set ());
7723
7724 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7725 }
7726
7727 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7728 to register BASE. Return generated insn. */
7729
7730 static rtx
7731 restore_fpr (rtx base, int offset, int regnum)
7732 {
7733 rtx addr;
7734 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7735 set_mem_alias_set (addr, get_frame_alias_set ());
7736
7737 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7738 }
7739
7740 /* Return true if REGNO is a global register, but not one
7741 of the special ones that need to be saved/restored in anyway. */
7742
7743 static inline bool
7744 global_not_special_regno_p (int regno)
7745 {
7746 return (global_regs[regno]
7747 /* These registers are special and need to be
7748 restored in any case. */
7749 && !(regno == STACK_POINTER_REGNUM
7750 || regno == RETURN_REGNUM
7751 || regno == BASE_REGNUM
7752 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7753 }
7754
7755 /* Generate insn to save registers FIRST to LAST into
7756 the register save area located at offset OFFSET
7757 relative to register BASE. */
7758
7759 static rtx
7760 save_gprs (rtx base, int offset, int first, int last)
7761 {
7762 rtx addr, insn, note;
7763 int i;
7764
7765 addr = plus_constant (Pmode, base, offset);
7766 addr = gen_rtx_MEM (Pmode, addr);
7767
7768 set_mem_alias_set (addr, get_frame_alias_set ());
7769
7770 /* Special-case single register. */
7771 if (first == last)
7772 {
7773 if (TARGET_64BIT)
7774 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7775 else
7776 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7777
7778 if (!global_not_special_regno_p (first))
7779 RTX_FRAME_RELATED_P (insn) = 1;
7780 return insn;
7781 }
7782
7783
7784 insn = gen_store_multiple (addr,
7785 gen_rtx_REG (Pmode, first),
7786 GEN_INT (last - first + 1));
7787
7788 if (first <= 6 && cfun->stdarg)
7789 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7790 {
7791 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7792
7793 if (first + i <= 6)
7794 set_mem_alias_set (mem, get_varargs_alias_set ());
7795 }
7796
7797 /* We need to set the FRAME_RELATED flag on all SETs
7798 inside the store-multiple pattern.
7799
7800 However, we must not emit DWARF records for registers 2..5
7801 if they are stored for use by variable arguments ...
7802
7803 ??? Unfortunately, it is not enough to simply not the
7804 FRAME_RELATED flags for those SETs, because the first SET
7805 of the PARALLEL is always treated as if it had the flag
7806 set, even if it does not. Therefore we emit a new pattern
7807 without those registers as REG_FRAME_RELATED_EXPR note. */
7808
7809 if (first >= 6 && !global_not_special_regno_p (first))
7810 {
7811 rtx pat = PATTERN (insn);
7812
7813 for (i = 0; i < XVECLEN (pat, 0); i++)
7814 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7815 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7816 0, i)))))
7817 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7818
7819 RTX_FRAME_RELATED_P (insn) = 1;
7820 }
7821 else if (last >= 6)
7822 {
7823 int start;
7824
7825 for (start = first >= 6 ? first : 6; start <= last; start++)
7826 if (!global_not_special_regno_p (start))
7827 break;
7828
7829 if (start > last)
7830 return insn;
7831
7832 addr = plus_constant (Pmode, base,
7833 offset + (start - first) * UNITS_PER_LONG);
7834 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7835 gen_rtx_REG (Pmode, start),
7836 GEN_INT (last - start + 1));
7837 note = PATTERN (note);
7838
7839 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7840
7841 for (i = 0; i < XVECLEN (note, 0); i++)
7842 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7843 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7844 0, i)))))
7845 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7846
7847 RTX_FRAME_RELATED_P (insn) = 1;
7848 }
7849
7850 return insn;
7851 }
7852
7853 /* Generate insn to restore registers FIRST to LAST from
7854 the register save area located at offset OFFSET
7855 relative to register BASE. */
7856
7857 static rtx
7858 restore_gprs (rtx base, int offset, int first, int last)
7859 {
7860 rtx addr, insn;
7861
7862 addr = plus_constant (Pmode, base, offset);
7863 addr = gen_rtx_MEM (Pmode, addr);
7864 set_mem_alias_set (addr, get_frame_alias_set ());
7865
7866 /* Special-case single register. */
7867 if (first == last)
7868 {
7869 if (TARGET_64BIT)
7870 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7871 else
7872 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7873
7874 return insn;
7875 }
7876
7877 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7878 addr,
7879 GEN_INT (last - first + 1));
7880 return insn;
7881 }
7882
7883 /* Return insn sequence to load the GOT register. */
7884
7885 static GTY(()) rtx got_symbol;
7886 rtx
7887 s390_load_got (void)
7888 {
7889 rtx insns;
7890
7891 /* We cannot use pic_offset_table_rtx here since we use this
7892 function also for non-pic if __tls_get_offset is called and in
7893 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
7894 aren't usable. */
7895 rtx got_rtx = gen_rtx_REG (Pmode, 12);
7896
7897 if (!got_symbol)
7898 {
7899 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7900 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7901 }
7902
7903 start_sequence ();
7904
7905 if (TARGET_CPU_ZARCH)
7906 {
7907 emit_move_insn (got_rtx, got_symbol);
7908 }
7909 else
7910 {
7911 rtx offset;
7912
7913 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7914 UNSPEC_LTREL_OFFSET);
7915 offset = gen_rtx_CONST (Pmode, offset);
7916 offset = force_const_mem (Pmode, offset);
7917
7918 emit_move_insn (got_rtx, offset);
7919
7920 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7921 UNSPEC_LTREL_BASE);
7922 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
7923
7924 emit_move_insn (got_rtx, offset);
7925 }
7926
7927 insns = get_insns ();
7928 end_sequence ();
7929 return insns;
7930 }
7931
7932 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7933 and the change to the stack pointer. */
7934
7935 static void
7936 s390_emit_stack_tie (void)
7937 {
7938 rtx mem = gen_frame_mem (BLKmode,
7939 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7940
7941 emit_insn (gen_stack_tie (mem));
7942 }
7943
7944 /* Expand the prologue into a bunch of separate insns. */
7945
7946 void
7947 s390_emit_prologue (void)
7948 {
7949 rtx insn, addr;
7950 rtx temp_reg;
7951 int i;
7952 int offset;
7953 int next_fpr = 0;
7954
7955 /* Complete frame layout. */
7956
7957 s390_update_frame_layout ();
7958
7959 /* Annotate all constant pool references to let the scheduler know
7960 they implicitly use the base register. */
7961
7962 push_topmost_sequence ();
7963
7964 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7965 if (INSN_P (insn))
7966 {
7967 annotate_constant_pool_refs (&PATTERN (insn));
7968 df_insn_rescan (insn);
7969 }
7970
7971 pop_topmost_sequence ();
7972
7973 /* Choose best register to use for temp use within prologue.
7974 See below for why TPF must use the register 1. */
7975
7976 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7977 && !current_function_is_leaf
7978 && !TARGET_TPF_PROFILING)
7979 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7980 else
7981 temp_reg = gen_rtx_REG (Pmode, 1);
7982
7983 /* Save call saved gprs. */
7984 if (cfun_frame_layout.first_save_gpr != -1)
7985 {
7986 insn = save_gprs (stack_pointer_rtx,
7987 cfun_frame_layout.gprs_offset +
7988 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7989 - cfun_frame_layout.first_save_gpr_slot),
7990 cfun_frame_layout.first_save_gpr,
7991 cfun_frame_layout.last_save_gpr);
7992 emit_insn (insn);
7993 }
7994
7995 /* Dummy insn to mark literal pool slot. */
7996
7997 if (cfun->machine->base_reg)
7998 emit_insn (gen_main_pool (cfun->machine->base_reg));
7999
8000 offset = cfun_frame_layout.f0_offset;
8001
8002 /* Save f0 and f2. */
8003 for (i = 0; i < 2; i++)
8004 {
8005 if (cfun_fpr_bit_p (i))
8006 {
8007 save_fpr (stack_pointer_rtx, offset, i + 16);
8008 offset += 8;
8009 }
8010 else if (!TARGET_PACKED_STACK)
8011 offset += 8;
8012 }
8013
8014 /* Save f4 and f6. */
8015 offset = cfun_frame_layout.f4_offset;
8016 for (i = 2; i < 4; i++)
8017 {
8018 if (cfun_fpr_bit_p (i))
8019 {
8020 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8021 offset += 8;
8022
8023 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8024 therefore are not frame related. */
8025 if (!call_really_used_regs[i + 16])
8026 RTX_FRAME_RELATED_P (insn) = 1;
8027 }
8028 else if (!TARGET_PACKED_STACK)
8029 offset += 8;
8030 }
8031
8032 if (TARGET_PACKED_STACK
8033 && cfun_save_high_fprs_p
8034 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8035 {
8036 offset = (cfun_frame_layout.f8_offset
8037 + (cfun_frame_layout.high_fprs - 1) * 8);
8038
8039 for (i = 15; i > 7 && offset >= 0; i--)
8040 if (cfun_fpr_bit_p (i))
8041 {
8042 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8043
8044 RTX_FRAME_RELATED_P (insn) = 1;
8045 offset -= 8;
8046 }
8047 if (offset >= cfun_frame_layout.f8_offset)
8048 next_fpr = i + 16;
8049 }
8050
8051 if (!TARGET_PACKED_STACK)
8052 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8053
8054 if (flag_stack_usage_info)
8055 current_function_static_stack_size = cfun_frame_layout.frame_size;
8056
8057 /* Decrement stack pointer. */
8058
8059 if (cfun_frame_layout.frame_size > 0)
8060 {
8061 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8062 rtx real_frame_off;
8063
8064 if (s390_stack_size)
8065 {
8066 HOST_WIDE_INT stack_guard;
8067
8068 if (s390_stack_guard)
8069 stack_guard = s390_stack_guard;
8070 else
8071 {
8072 /* If no value for stack guard is provided the smallest power of 2
8073 larger than the current frame size is chosen. */
8074 stack_guard = 1;
8075 while (stack_guard < cfun_frame_layout.frame_size)
8076 stack_guard <<= 1;
8077 }
8078
8079 if (cfun_frame_layout.frame_size >= s390_stack_size)
8080 {
8081 warning (0, "frame size of function %qs is %wd"
8082 " bytes exceeding user provided stack limit of "
8083 "%d bytes. "
8084 "An unconditional trap is added.",
8085 current_function_name(), cfun_frame_layout.frame_size,
8086 s390_stack_size);
8087 emit_insn (gen_trap ());
8088 }
8089 else
8090 {
8091 /* stack_guard has to be smaller than s390_stack_size.
8092 Otherwise we would emit an AND with zero which would
8093 not match the test under mask pattern. */
8094 if (stack_guard >= s390_stack_size)
8095 {
8096 warning (0, "frame size of function %qs is %wd"
8097 " bytes which is more than half the stack size. "
8098 "The dynamic check would not be reliable. "
8099 "No check emitted for this function.",
8100 current_function_name(),
8101 cfun_frame_layout.frame_size);
8102 }
8103 else
8104 {
8105 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8106 & ~(stack_guard - 1));
8107
8108 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8109 GEN_INT (stack_check_mask));
8110 if (TARGET_64BIT)
8111 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8112 t, const0_rtx),
8113 t, const0_rtx, const0_rtx));
8114 else
8115 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8116 t, const0_rtx),
8117 t, const0_rtx, const0_rtx));
8118 }
8119 }
8120 }
8121
8122 if (s390_warn_framesize > 0
8123 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8124 warning (0, "frame size of %qs is %wd bytes",
8125 current_function_name (), cfun_frame_layout.frame_size);
8126
8127 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8128 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8129
8130 /* Save incoming stack pointer into temp reg. */
8131 if (TARGET_BACKCHAIN || next_fpr)
8132 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8133
8134 /* Subtract frame size from stack pointer. */
8135
8136 if (DISP_IN_RANGE (INTVAL (frame_off)))
8137 {
8138 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8139 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8140 frame_off));
8141 insn = emit_insn (insn);
8142 }
8143 else
8144 {
8145 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8146 frame_off = force_const_mem (Pmode, frame_off);
8147
8148 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8149 annotate_constant_pool_refs (&PATTERN (insn));
8150 }
8151
8152 RTX_FRAME_RELATED_P (insn) = 1;
8153 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8154 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8155 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8156 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8157 real_frame_off)));
8158
8159 /* Set backchain. */
8160
8161 if (TARGET_BACKCHAIN)
8162 {
8163 if (cfun_frame_layout.backchain_offset)
8164 addr = gen_rtx_MEM (Pmode,
8165 plus_constant (Pmode, stack_pointer_rtx,
8166 cfun_frame_layout.backchain_offset));
8167 else
8168 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8169 set_mem_alias_set (addr, get_frame_alias_set ());
8170 insn = emit_insn (gen_move_insn (addr, temp_reg));
8171 }
8172
8173 /* If we support non-call exceptions (e.g. for Java),
8174 we need to make sure the backchain pointer is set up
8175 before any possibly trapping memory access. */
8176 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8177 {
8178 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8179 emit_clobber (addr);
8180 }
8181 }
8182
8183 /* Save fprs 8 - 15 (64 bit ABI). */
8184
8185 if (cfun_save_high_fprs_p && next_fpr)
8186 {
8187 /* If the stack might be accessed through a different register
8188 we have to make sure that the stack pointer decrement is not
8189 moved below the use of the stack slots. */
8190 s390_emit_stack_tie ();
8191
8192 insn = emit_insn (gen_add2_insn (temp_reg,
8193 GEN_INT (cfun_frame_layout.f8_offset)));
8194
8195 offset = 0;
8196
8197 for (i = 24; i <= next_fpr; i++)
8198 if (cfun_fpr_bit_p (i - 16))
8199 {
8200 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8201 cfun_frame_layout.frame_size
8202 + cfun_frame_layout.f8_offset
8203 + offset);
8204
8205 insn = save_fpr (temp_reg, offset, i);
8206 offset += 8;
8207 RTX_FRAME_RELATED_P (insn) = 1;
8208 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8209 gen_rtx_SET (VOIDmode,
8210 gen_rtx_MEM (DFmode, addr),
8211 gen_rtx_REG (DFmode, i)));
8212 }
8213 }
8214
8215 /* Set frame pointer, if needed. */
8216
8217 if (frame_pointer_needed)
8218 {
8219 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8220 RTX_FRAME_RELATED_P (insn) = 1;
8221 }
8222
8223 /* Set up got pointer, if needed. */
8224
8225 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8226 {
8227 rtx insns = s390_load_got ();
8228
8229 for (insn = insns; insn; insn = NEXT_INSN (insn))
8230 annotate_constant_pool_refs (&PATTERN (insn));
8231
8232 emit_insn (insns);
8233 }
8234
8235 if (TARGET_TPF_PROFILING)
8236 {
8237 /* Generate a BAS instruction to serve as a function
8238 entry intercept to facilitate the use of tracing
8239 algorithms located at the branch target. */
8240 emit_insn (gen_prologue_tpf ());
8241
8242 /* Emit a blockage here so that all code
8243 lies between the profiling mechanisms. */
8244 emit_insn (gen_blockage ());
8245 }
8246 }
8247
8248 /* Expand the epilogue into a bunch of separate insns. */
8249
8250 void
8251 s390_emit_epilogue (bool sibcall)
8252 {
8253 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8254 int area_bottom, area_top, offset = 0;
8255 int next_offset;
8256 rtvec p;
8257 int i;
8258
8259 if (TARGET_TPF_PROFILING)
8260 {
8261
8262 /* Generate a BAS instruction to serve as a function
8263 entry intercept to facilitate the use of tracing
8264 algorithms located at the branch target. */
8265
8266 /* Emit a blockage here so that all code
8267 lies between the profiling mechanisms. */
8268 emit_insn (gen_blockage ());
8269
8270 emit_insn (gen_epilogue_tpf ());
8271 }
8272
8273 /* Check whether to use frame or stack pointer for restore. */
8274
8275 frame_pointer = (frame_pointer_needed
8276 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8277
8278 s390_frame_area (&area_bottom, &area_top);
8279
8280 /* Check whether we can access the register save area.
8281 If not, increment the frame pointer as required. */
8282
8283 if (area_top <= area_bottom)
8284 {
8285 /* Nothing to restore. */
8286 }
8287 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8288 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8289 {
8290 /* Area is in range. */
8291 offset = cfun_frame_layout.frame_size;
8292 }
8293 else
8294 {
8295 rtx insn, frame_off, cfa;
8296
8297 offset = area_bottom < 0 ? -area_bottom : 0;
8298 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8299
8300 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8301 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8302 if (DISP_IN_RANGE (INTVAL (frame_off)))
8303 {
8304 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8305 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8306 insn = emit_insn (insn);
8307 }
8308 else
8309 {
8310 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8311 frame_off = force_const_mem (Pmode, frame_off);
8312
8313 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8314 annotate_constant_pool_refs (&PATTERN (insn));
8315 }
8316 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8317 RTX_FRAME_RELATED_P (insn) = 1;
8318 }
8319
8320 /* Restore call saved fprs. */
8321
8322 if (TARGET_64BIT)
8323 {
8324 if (cfun_save_high_fprs_p)
8325 {
8326 next_offset = cfun_frame_layout.f8_offset;
8327 for (i = 24; i < 32; i++)
8328 {
8329 if (cfun_fpr_bit_p (i - 16))
8330 {
8331 restore_fpr (frame_pointer,
8332 offset + next_offset, i);
8333 cfa_restores
8334 = alloc_reg_note (REG_CFA_RESTORE,
8335 gen_rtx_REG (DFmode, i), cfa_restores);
8336 next_offset += 8;
8337 }
8338 }
8339 }
8340
8341 }
8342 else
8343 {
8344 next_offset = cfun_frame_layout.f4_offset;
8345 for (i = 18; i < 20; i++)
8346 {
8347 if (cfun_fpr_bit_p (i - 16))
8348 {
8349 restore_fpr (frame_pointer,
8350 offset + next_offset, i);
8351 cfa_restores
8352 = alloc_reg_note (REG_CFA_RESTORE,
8353 gen_rtx_REG (DFmode, i), cfa_restores);
8354 next_offset += 8;
8355 }
8356 else if (!TARGET_PACKED_STACK)
8357 next_offset += 8;
8358 }
8359
8360 }
8361
8362 /* Return register. */
8363
8364 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8365
8366 /* Restore call saved gprs. */
8367
8368 if (cfun_frame_layout.first_restore_gpr != -1)
8369 {
8370 rtx insn, addr;
8371 int i;
8372
8373 /* Check for global register and save them
8374 to stack location from where they get restored. */
8375
8376 for (i = cfun_frame_layout.first_restore_gpr;
8377 i <= cfun_frame_layout.last_restore_gpr;
8378 i++)
8379 {
8380 if (global_not_special_regno_p (i))
8381 {
8382 addr = plus_constant (Pmode, frame_pointer,
8383 offset + cfun_frame_layout.gprs_offset
8384 + (i - cfun_frame_layout.first_save_gpr_slot)
8385 * UNITS_PER_LONG);
8386 addr = gen_rtx_MEM (Pmode, addr);
8387 set_mem_alias_set (addr, get_frame_alias_set ());
8388 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8389 }
8390 else
8391 cfa_restores
8392 = alloc_reg_note (REG_CFA_RESTORE,
8393 gen_rtx_REG (Pmode, i), cfa_restores);
8394 }
8395
8396 if (! sibcall)
8397 {
8398 /* Fetch return address from stack before load multiple,
8399 this will do good for scheduling. */
8400
8401 if (cfun_frame_layout.save_return_addr_p
8402 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8403 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8404 {
8405 int return_regnum = find_unused_clobbered_reg();
8406 if (!return_regnum)
8407 return_regnum = 4;
8408 return_reg = gen_rtx_REG (Pmode, return_regnum);
8409
8410 addr = plus_constant (Pmode, frame_pointer,
8411 offset + cfun_frame_layout.gprs_offset
8412 + (RETURN_REGNUM
8413 - cfun_frame_layout.first_save_gpr_slot)
8414 * UNITS_PER_LONG);
8415 addr = gen_rtx_MEM (Pmode, addr);
8416 set_mem_alias_set (addr, get_frame_alias_set ());
8417 emit_move_insn (return_reg, addr);
8418 }
8419 }
8420
8421 insn = restore_gprs (frame_pointer,
8422 offset + cfun_frame_layout.gprs_offset
8423 + (cfun_frame_layout.first_restore_gpr
8424 - cfun_frame_layout.first_save_gpr_slot)
8425 * UNITS_PER_LONG,
8426 cfun_frame_layout.first_restore_gpr,
8427 cfun_frame_layout.last_restore_gpr);
8428 insn = emit_insn (insn);
8429 REG_NOTES (insn) = cfa_restores;
8430 add_reg_note (insn, REG_CFA_DEF_CFA,
8431 plus_constant (Pmode, stack_pointer_rtx,
8432 STACK_POINTER_OFFSET));
8433 RTX_FRAME_RELATED_P (insn) = 1;
8434 }
8435
8436 if (! sibcall)
8437 {
8438
8439 /* Return to caller. */
8440
8441 p = rtvec_alloc (2);
8442
8443 RTVEC_ELT (p, 0) = ret_rtx;
8444 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8445 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8446 }
8447 }
8448
8449
8450 /* Return the size in bytes of a function argument of
8451 type TYPE and/or mode MODE. At least one of TYPE or
8452 MODE must be specified. */
8453
8454 static int
8455 s390_function_arg_size (enum machine_mode mode, const_tree type)
8456 {
8457 if (type)
8458 return int_size_in_bytes (type);
8459
8460 /* No type info available for some library calls ... */
8461 if (mode != BLKmode)
8462 return GET_MODE_SIZE (mode);
8463
8464 /* If we have neither type nor mode, abort */
8465 gcc_unreachable ();
8466 }
8467
8468 /* Return true if a function argument of type TYPE and mode MODE
8469 is to be passed in a floating-point register, if available. */
8470
8471 static bool
8472 s390_function_arg_float (enum machine_mode mode, const_tree type)
8473 {
8474 int size = s390_function_arg_size (mode, type);
8475 if (size > 8)
8476 return false;
8477
8478 /* Soft-float changes the ABI: no floating-point registers are used. */
8479 if (TARGET_SOFT_FLOAT)
8480 return false;
8481
8482 /* No type info available for some library calls ... */
8483 if (!type)
8484 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8485
8486 /* The ABI says that record types with a single member are treated
8487 just like that member would be. */
8488 while (TREE_CODE (type) == RECORD_TYPE)
8489 {
8490 tree field, single = NULL_TREE;
8491
8492 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8493 {
8494 if (TREE_CODE (field) != FIELD_DECL)
8495 continue;
8496
8497 if (single == NULL_TREE)
8498 single = TREE_TYPE (field);
8499 else
8500 return false;
8501 }
8502
8503 if (single == NULL_TREE)
8504 return false;
8505 else
8506 type = single;
8507 }
8508
8509 return TREE_CODE (type) == REAL_TYPE;
8510 }
8511
8512 /* Return true if a function argument of type TYPE and mode MODE
8513 is to be passed in an integer register, or a pair of integer
8514 registers, if available. */
8515
8516 static bool
8517 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8518 {
8519 int size = s390_function_arg_size (mode, type);
8520 if (size > 8)
8521 return false;
8522
8523 /* No type info available for some library calls ... */
8524 if (!type)
8525 return GET_MODE_CLASS (mode) == MODE_INT
8526 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8527
8528 /* We accept small integral (and similar) types. */
8529 if (INTEGRAL_TYPE_P (type)
8530 || POINTER_TYPE_P (type)
8531 || TREE_CODE (type) == NULLPTR_TYPE
8532 || TREE_CODE (type) == OFFSET_TYPE
8533 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8534 return true;
8535
8536 /* We also accept structs of size 1, 2, 4, 8 that are not
8537 passed in floating-point registers. */
8538 if (AGGREGATE_TYPE_P (type)
8539 && exact_log2 (size) >= 0
8540 && !s390_function_arg_float (mode, type))
8541 return true;
8542
8543 return false;
8544 }
8545
8546 /* Return 1 if a function argument of type TYPE and mode MODE
8547 is to be passed by reference. The ABI specifies that only
8548 structures of size 1, 2, 4, or 8 bytes are passed by value,
8549 all other structures (and complex numbers) are passed by
8550 reference. */
8551
8552 static bool
8553 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8554 enum machine_mode mode, const_tree type,
8555 bool named ATTRIBUTE_UNUSED)
8556 {
8557 int size = s390_function_arg_size (mode, type);
8558 if (size > 8)
8559 return true;
8560
8561 if (type)
8562 {
8563 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8564 return 1;
8565
8566 if (TREE_CODE (type) == COMPLEX_TYPE
8567 || TREE_CODE (type) == VECTOR_TYPE)
8568 return 1;
8569 }
8570
8571 return 0;
8572 }
8573
8574 /* Update the data in CUM to advance over an argument of mode MODE and
8575 data type TYPE. (TYPE is null for libcalls where that information
8576 may not be available.). The boolean NAMED specifies whether the
8577 argument is a named argument (as opposed to an unnamed argument
8578 matching an ellipsis). */
8579
8580 static void
8581 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8582 const_tree type, bool named ATTRIBUTE_UNUSED)
8583 {
8584 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8585
8586 if (s390_function_arg_float (mode, type))
8587 {
8588 cum->fprs += 1;
8589 }
8590 else if (s390_function_arg_integer (mode, type))
8591 {
8592 int size = s390_function_arg_size (mode, type);
8593 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8594 }
8595 else
8596 gcc_unreachable ();
8597 }
8598
8599 /* Define where to put the arguments to a function.
8600 Value is zero to push the argument on the stack,
8601 or a hard register in which to store the argument.
8602
8603 MODE is the argument's machine mode.
8604 TYPE is the data type of the argument (as a tree).
8605 This is null for libcalls where that information may
8606 not be available.
8607 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8608 the preceding args and about the function being called.
8609 NAMED is nonzero if this argument is a named parameter
8610 (otherwise it is an extra parameter matching an ellipsis).
8611
8612 On S/390, we use general purpose registers 2 through 6 to
8613 pass integer, pointer, and certain structure arguments, and
8614 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8615 to pass floating point arguments. All remaining arguments
8616 are pushed to the stack. */
8617
8618 static rtx
8619 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8620 const_tree type, bool named ATTRIBUTE_UNUSED)
8621 {
8622 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8623
8624 if (s390_function_arg_float (mode, type))
8625 {
8626 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8627 return 0;
8628 else
8629 return gen_rtx_REG (mode, cum->fprs + 16);
8630 }
8631 else if (s390_function_arg_integer (mode, type))
8632 {
8633 int size = s390_function_arg_size (mode, type);
8634 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8635
8636 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8637 return 0;
8638 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8639 return gen_rtx_REG (mode, cum->gprs + 2);
8640 else if (n_gprs == 2)
8641 {
8642 rtvec p = rtvec_alloc (2);
8643
8644 RTVEC_ELT (p, 0)
8645 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8646 const0_rtx);
8647 RTVEC_ELT (p, 1)
8648 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8649 GEN_INT (4));
8650
8651 return gen_rtx_PARALLEL (mode, p);
8652 }
8653 }
8654
8655 /* After the real arguments, expand_call calls us once again
8656 with a void_type_node type. Whatever we return here is
8657 passed as operand 2 to the call expanders.
8658
8659 We don't need this feature ... */
8660 else if (type == void_type_node)
8661 return const0_rtx;
8662
8663 gcc_unreachable ();
8664 }
8665
8666 /* Return true if return values of type TYPE should be returned
8667 in a memory buffer whose address is passed by the caller as
8668 hidden first argument. */
8669
8670 static bool
8671 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8672 {
8673 /* We accept small integral (and similar) types. */
8674 if (INTEGRAL_TYPE_P (type)
8675 || POINTER_TYPE_P (type)
8676 || TREE_CODE (type) == OFFSET_TYPE
8677 || TREE_CODE (type) == REAL_TYPE)
8678 return int_size_in_bytes (type) > 8;
8679
8680 /* Aggregates and similar constructs are always returned
8681 in memory. */
8682 if (AGGREGATE_TYPE_P (type)
8683 || TREE_CODE (type) == COMPLEX_TYPE
8684 || TREE_CODE (type) == VECTOR_TYPE)
8685 return true;
8686
8687 /* ??? We get called on all sorts of random stuff from
8688 aggregate_value_p. We can't abort, but it's not clear
8689 what's safe to return. Pretend it's a struct I guess. */
8690 return true;
8691 }
8692
8693 /* Function arguments and return values are promoted to word size. */
8694
8695 static enum machine_mode
8696 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8697 int *punsignedp,
8698 const_tree fntype ATTRIBUTE_UNUSED,
8699 int for_return ATTRIBUTE_UNUSED)
8700 {
8701 if (INTEGRAL_MODE_P (mode)
8702 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8703 {
8704 if (type != NULL_TREE && POINTER_TYPE_P (type))
8705 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8706 return Pmode;
8707 }
8708
8709 return mode;
8710 }
8711
8712 /* Define where to return a (scalar) value of type RET_TYPE.
8713 If RET_TYPE is null, define where to return a (scalar)
8714 value of mode MODE from a libcall. */
8715
8716 static rtx
8717 s390_function_and_libcall_value (enum machine_mode mode,
8718 const_tree ret_type,
8719 const_tree fntype_or_decl,
8720 bool outgoing ATTRIBUTE_UNUSED)
8721 {
8722 /* For normal functions perform the promotion as
8723 promote_function_mode would do. */
8724 if (ret_type)
8725 {
8726 int unsignedp = TYPE_UNSIGNED (ret_type);
8727 mode = promote_function_mode (ret_type, mode, &unsignedp,
8728 fntype_or_decl, 1);
8729 }
8730
8731 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8732 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8733
8734 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8735 return gen_rtx_REG (mode, 16);
8736 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8737 || UNITS_PER_LONG == UNITS_PER_WORD)
8738 return gen_rtx_REG (mode, 2);
8739 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8740 {
8741 /* This case is triggered when returning a 64 bit value with
8742 -m31 -mzarch. Although the value would fit into a single
8743 register it has to be forced into a 32 bit register pair in
8744 order to match the ABI. */
8745 rtvec p = rtvec_alloc (2);
8746
8747 RTVEC_ELT (p, 0)
8748 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8749 RTVEC_ELT (p, 1)
8750 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8751
8752 return gen_rtx_PARALLEL (mode, p);
8753 }
8754
8755 gcc_unreachable ();
8756 }
8757
8758 /* Define where to return a scalar return value of type RET_TYPE. */
8759
8760 static rtx
8761 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8762 bool outgoing)
8763 {
8764 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8765 fn_decl_or_type, outgoing);
8766 }
8767
8768 /* Define where to return a scalar libcall return value of mode
8769 MODE. */
8770
8771 static rtx
8772 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8773 {
8774 return s390_function_and_libcall_value (mode, NULL_TREE,
8775 NULL_TREE, true);
8776 }
8777
8778
8779 /* Create and return the va_list datatype.
8780
8781 On S/390, va_list is an array type equivalent to
8782
8783 typedef struct __va_list_tag
8784 {
8785 long __gpr;
8786 long __fpr;
8787 void *__overflow_arg_area;
8788 void *__reg_save_area;
8789 } va_list[1];
8790
8791 where __gpr and __fpr hold the number of general purpose
8792 or floating point arguments used up to now, respectively,
8793 __overflow_arg_area points to the stack location of the
8794 next argument passed on the stack, and __reg_save_area
8795 always points to the start of the register area in the
8796 call frame of the current function. The function prologue
8797 saves all registers used for argument passing into this
8798 area if the function uses variable arguments. */
8799
8800 static tree
8801 s390_build_builtin_va_list (void)
8802 {
8803 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8804
8805 record = lang_hooks.types.make_type (RECORD_TYPE);
8806
8807 type_decl =
8808 build_decl (BUILTINS_LOCATION,
8809 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8810
8811 f_gpr = build_decl (BUILTINS_LOCATION,
8812 FIELD_DECL, get_identifier ("__gpr"),
8813 long_integer_type_node);
8814 f_fpr = build_decl (BUILTINS_LOCATION,
8815 FIELD_DECL, get_identifier ("__fpr"),
8816 long_integer_type_node);
8817 f_ovf = build_decl (BUILTINS_LOCATION,
8818 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8819 ptr_type_node);
8820 f_sav = build_decl (BUILTINS_LOCATION,
8821 FIELD_DECL, get_identifier ("__reg_save_area"),
8822 ptr_type_node);
8823
8824 va_list_gpr_counter_field = f_gpr;
8825 va_list_fpr_counter_field = f_fpr;
8826
8827 DECL_FIELD_CONTEXT (f_gpr) = record;
8828 DECL_FIELD_CONTEXT (f_fpr) = record;
8829 DECL_FIELD_CONTEXT (f_ovf) = record;
8830 DECL_FIELD_CONTEXT (f_sav) = record;
8831
8832 TYPE_STUB_DECL (record) = type_decl;
8833 TYPE_NAME (record) = type_decl;
8834 TYPE_FIELDS (record) = f_gpr;
8835 DECL_CHAIN (f_gpr) = f_fpr;
8836 DECL_CHAIN (f_fpr) = f_ovf;
8837 DECL_CHAIN (f_ovf) = f_sav;
8838
8839 layout_type (record);
8840
8841 /* The correct type is an array type of one element. */
8842 return build_array_type (record, build_index_type (size_zero_node));
8843 }
8844
8845 /* Implement va_start by filling the va_list structure VALIST.
8846 STDARG_P is always true, and ignored.
8847 NEXTARG points to the first anonymous stack argument.
8848
8849 The following global variables are used to initialize
8850 the va_list structure:
8851
8852 crtl->args.info:
8853 holds number of gprs and fprs used for named arguments.
8854 crtl->args.arg_offset_rtx:
8855 holds the offset of the first anonymous stack argument
8856 (relative to the virtual arg pointer). */
8857
8858 static void
8859 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8860 {
8861 HOST_WIDE_INT n_gpr, n_fpr;
8862 int off;
8863 tree f_gpr, f_fpr, f_ovf, f_sav;
8864 tree gpr, fpr, ovf, sav, t;
8865
8866 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8867 f_fpr = DECL_CHAIN (f_gpr);
8868 f_ovf = DECL_CHAIN (f_fpr);
8869 f_sav = DECL_CHAIN (f_ovf);
8870
8871 valist = build_simple_mem_ref (valist);
8872 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8873 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8874 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8875 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8876
8877 /* Count number of gp and fp argument registers used. */
8878
8879 n_gpr = crtl->args.info.gprs;
8880 n_fpr = crtl->args.info.fprs;
8881
8882 if (cfun->va_list_gpr_size)
8883 {
8884 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8885 build_int_cst (NULL_TREE, n_gpr));
8886 TREE_SIDE_EFFECTS (t) = 1;
8887 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8888 }
8889
8890 if (cfun->va_list_fpr_size)
8891 {
8892 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8893 build_int_cst (NULL_TREE, n_fpr));
8894 TREE_SIDE_EFFECTS (t) = 1;
8895 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8896 }
8897
8898 /* Find the overflow area. */
8899 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8900 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8901 {
8902 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8903
8904 off = INTVAL (crtl->args.arg_offset_rtx);
8905 off = off < 0 ? 0 : off;
8906 if (TARGET_DEBUG_ARG)
8907 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8908 (int)n_gpr, (int)n_fpr, off);
8909
8910 t = fold_build_pointer_plus_hwi (t, off);
8911
8912 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8913 TREE_SIDE_EFFECTS (t) = 1;
8914 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8915 }
8916
8917 /* Find the register save area. */
8918 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8919 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8920 {
8921 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8922 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
8923
8924 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8925 TREE_SIDE_EFFECTS (t) = 1;
8926 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8927 }
8928 }
8929
8930 /* Implement va_arg by updating the va_list structure
8931 VALIST as required to retrieve an argument of type
8932 TYPE, and returning that argument.
8933
8934 Generates code equivalent to:
8935
8936 if (integral value) {
8937 if (size <= 4 && args.gpr < 5 ||
8938 size > 4 && args.gpr < 4 )
8939 ret = args.reg_save_area[args.gpr+8]
8940 else
8941 ret = *args.overflow_arg_area++;
8942 } else if (float value) {
8943 if (args.fgpr < 2)
8944 ret = args.reg_save_area[args.fpr+64]
8945 else
8946 ret = *args.overflow_arg_area++;
8947 } else if (aggregate value) {
8948 if (args.gpr < 5)
8949 ret = *args.reg_save_area[args.gpr]
8950 else
8951 ret = **args.overflow_arg_area++;
8952 } */
8953
8954 static tree
8955 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8956 gimple_seq *post_p ATTRIBUTE_UNUSED)
8957 {
8958 tree f_gpr, f_fpr, f_ovf, f_sav;
8959 tree gpr, fpr, ovf, sav, reg, t, u;
8960 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8961 tree lab_false, lab_over, addr;
8962
8963 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8964 f_fpr = DECL_CHAIN (f_gpr);
8965 f_ovf = DECL_CHAIN (f_fpr);
8966 f_sav = DECL_CHAIN (f_ovf);
8967
8968 valist = build_va_arg_indirect_ref (valist);
8969 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8970 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8971 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8972
8973 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8974 both appear on a lhs. */
8975 valist = unshare_expr (valist);
8976 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8977
8978 size = int_size_in_bytes (type);
8979
8980 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8981 {
8982 if (TARGET_DEBUG_ARG)
8983 {
8984 fprintf (stderr, "va_arg: aggregate type");
8985 debug_tree (type);
8986 }
8987
8988 /* Aggregates are passed by reference. */
8989 indirect_p = 1;
8990 reg = gpr;
8991 n_reg = 1;
8992
8993 /* kernel stack layout on 31 bit: It is assumed here that no padding
8994 will be added by s390_frame_info because for va_args always an even
8995 number of gprs has to be saved r15-r2 = 14 regs. */
8996 sav_ofs = 2 * UNITS_PER_LONG;
8997 sav_scale = UNITS_PER_LONG;
8998 size = UNITS_PER_LONG;
8999 max_reg = GP_ARG_NUM_REG - n_reg;
9000 }
9001 else if (s390_function_arg_float (TYPE_MODE (type), type))
9002 {
9003 if (TARGET_DEBUG_ARG)
9004 {
9005 fprintf (stderr, "va_arg: float type");
9006 debug_tree (type);
9007 }
9008
9009 /* FP args go in FP registers, if present. */
9010 indirect_p = 0;
9011 reg = fpr;
9012 n_reg = 1;
9013 sav_ofs = 16 * UNITS_PER_LONG;
9014 sav_scale = 8;
9015 max_reg = FP_ARG_NUM_REG - n_reg;
9016 }
9017 else
9018 {
9019 if (TARGET_DEBUG_ARG)
9020 {
9021 fprintf (stderr, "va_arg: other type");
9022 debug_tree (type);
9023 }
9024
9025 /* Otherwise into GP registers. */
9026 indirect_p = 0;
9027 reg = gpr;
9028 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9029
9030 /* kernel stack layout on 31 bit: It is assumed here that no padding
9031 will be added by s390_frame_info because for va_args always an even
9032 number of gprs has to be saved r15-r2 = 14 regs. */
9033 sav_ofs = 2 * UNITS_PER_LONG;
9034
9035 if (size < UNITS_PER_LONG)
9036 sav_ofs += UNITS_PER_LONG - size;
9037
9038 sav_scale = UNITS_PER_LONG;
9039 max_reg = GP_ARG_NUM_REG - n_reg;
9040 }
9041
9042 /* Pull the value out of the saved registers ... */
9043
9044 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9045 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9046 addr = create_tmp_var (ptr_type_node, "addr");
9047 mark_sym_for_renaming (addr);
9048
9049 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9050 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9051 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9052 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9053 gimplify_and_add (t, pre_p);
9054
9055 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9056 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9057 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9058 t = fold_build_pointer_plus (t, u);
9059
9060 gimplify_assign (addr, t, pre_p);
9061
9062 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9063
9064 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9065
9066
9067 /* ... Otherwise out of the overflow area. */
9068
9069 t = ovf;
9070 if (size < UNITS_PER_LONG)
9071 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9072
9073 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9074
9075 gimplify_assign (addr, t, pre_p);
9076
9077 t = fold_build_pointer_plus_hwi (t, size);
9078 gimplify_assign (ovf, t, pre_p);
9079
9080 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9081
9082
9083 /* Increment register save count. */
9084
9085 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9086 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9087 gimplify_and_add (u, pre_p);
9088
9089 if (indirect_p)
9090 {
9091 t = build_pointer_type_for_mode (build_pointer_type (type),
9092 ptr_mode, true);
9093 addr = fold_convert (t, addr);
9094 addr = build_va_arg_indirect_ref (addr);
9095 }
9096 else
9097 {
9098 t = build_pointer_type_for_mode (type, ptr_mode, true);
9099 addr = fold_convert (t, addr);
9100 }
9101
9102 return build_va_arg_indirect_ref (addr);
9103 }
9104
9105
9106 /* Builtins. */
9107
9108 enum s390_builtin
9109 {
9110 S390_BUILTIN_THREAD_POINTER,
9111 S390_BUILTIN_SET_THREAD_POINTER,
9112
9113 S390_BUILTIN_max
9114 };
9115
9116 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9117 CODE_FOR_get_tp_64,
9118 CODE_FOR_set_tp_64
9119 };
9120
9121 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9122 CODE_FOR_get_tp_31,
9123 CODE_FOR_set_tp_31
9124 };
9125
9126 static void
9127 s390_init_builtins (void)
9128 {
9129 tree ftype;
9130
9131 ftype = build_function_type_list (ptr_type_node, NULL_TREE);
9132 add_builtin_function ("__builtin_thread_pointer", ftype,
9133 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9134 NULL, NULL_TREE);
9135
9136 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9137 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9138 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9139 NULL, NULL_TREE);
9140 }
9141
9142 /* Expand an expression EXP that calls a built-in function,
9143 with result going to TARGET if that's convenient
9144 (and in mode MODE if that's convenient).
9145 SUBTARGET may be used as the target for computing one of EXP's operands.
9146 IGNORE is nonzero if the value is to be ignored. */
9147
9148 static rtx
9149 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9150 enum machine_mode mode ATTRIBUTE_UNUSED,
9151 int ignore ATTRIBUTE_UNUSED)
9152 {
9153 #define MAX_ARGS 2
9154
9155 enum insn_code const *code_for_builtin =
9156 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9157
9158 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9159 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9160 enum insn_code icode;
9161 rtx op[MAX_ARGS], pat;
9162 int arity;
9163 bool nonvoid;
9164 tree arg;
9165 call_expr_arg_iterator iter;
9166
9167 if (fcode >= S390_BUILTIN_max)
9168 internal_error ("bad builtin fcode");
9169 icode = code_for_builtin[fcode];
9170 if (icode == 0)
9171 internal_error ("bad builtin fcode");
9172
9173 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9174
9175 arity = 0;
9176 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9177 {
9178 const struct insn_operand_data *insn_op;
9179
9180 if (arg == error_mark_node)
9181 return NULL_RTX;
9182 if (arity > MAX_ARGS)
9183 return NULL_RTX;
9184
9185 insn_op = &insn_data[icode].operand[arity + nonvoid];
9186
9187 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9188
9189 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9190 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9191 arity++;
9192 }
9193
9194 if (nonvoid)
9195 {
9196 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9197 if (!target
9198 || GET_MODE (target) != tmode
9199 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9200 target = gen_reg_rtx (tmode);
9201 }
9202
9203 switch (arity)
9204 {
9205 case 0:
9206 pat = GEN_FCN (icode) (target);
9207 break;
9208 case 1:
9209 if (nonvoid)
9210 pat = GEN_FCN (icode) (target, op[0]);
9211 else
9212 pat = GEN_FCN (icode) (op[0]);
9213 break;
9214 case 2:
9215 pat = GEN_FCN (icode) (target, op[0], op[1]);
9216 break;
9217 default:
9218 gcc_unreachable ();
9219 }
9220 if (!pat)
9221 return NULL_RTX;
9222 emit_insn (pat);
9223
9224 if (nonvoid)
9225 return target;
9226 else
9227 return const0_rtx;
9228 }
9229
9230
9231 /* Output assembly code for the trampoline template to
9232 stdio stream FILE.
9233
9234 On S/390, we use gpr 1 internally in the trampoline code;
9235 gpr 0 is used to hold the static chain. */
9236
9237 static void
9238 s390_asm_trampoline_template (FILE *file)
9239 {
9240 rtx op[2];
9241 op[0] = gen_rtx_REG (Pmode, 0);
9242 op[1] = gen_rtx_REG (Pmode, 1);
9243
9244 if (TARGET_64BIT)
9245 {
9246 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9247 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9248 output_asm_insn ("br\t%1", op); /* 2 byte */
9249 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9250 }
9251 else
9252 {
9253 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9254 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9255 output_asm_insn ("br\t%1", op); /* 2 byte */
9256 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9257 }
9258 }
9259
9260 /* Emit RTL insns to initialize the variable parts of a trampoline.
9261 FNADDR is an RTX for the address of the function's pure code.
9262 CXT is an RTX for the static chain value for the function. */
9263
9264 static void
9265 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9266 {
9267 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9268 rtx mem;
9269
9270 emit_block_move (m_tramp, assemble_trampoline_template (),
9271 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9272
9273 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9274 emit_move_insn (mem, cxt);
9275 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9276 emit_move_insn (mem, fnaddr);
9277 }
9278
9279 /* Output assembler code to FILE to increment profiler label # LABELNO
9280 for profiling a function entry. */
9281
9282 void
9283 s390_function_profiler (FILE *file, int labelno)
9284 {
9285 rtx op[7];
9286
9287 char label[128];
9288 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9289
9290 fprintf (file, "# function profiler \n");
9291
9292 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9293 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9294 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9295
9296 op[2] = gen_rtx_REG (Pmode, 1);
9297 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9298 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9299
9300 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9301 if (flag_pic)
9302 {
9303 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9304 op[4] = gen_rtx_CONST (Pmode, op[4]);
9305 }
9306
9307 if (TARGET_64BIT)
9308 {
9309 output_asm_insn ("stg\t%0,%1", op);
9310 output_asm_insn ("larl\t%2,%3", op);
9311 output_asm_insn ("brasl\t%0,%4", op);
9312 output_asm_insn ("lg\t%0,%1", op);
9313 }
9314 else if (!flag_pic)
9315 {
9316 op[6] = gen_label_rtx ();
9317
9318 output_asm_insn ("st\t%0,%1", op);
9319 output_asm_insn ("bras\t%2,%l6", op);
9320 output_asm_insn (".long\t%4", op);
9321 output_asm_insn (".long\t%3", op);
9322 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9323 output_asm_insn ("l\t%0,0(%2)", op);
9324 output_asm_insn ("l\t%2,4(%2)", op);
9325 output_asm_insn ("basr\t%0,%0", op);
9326 output_asm_insn ("l\t%0,%1", op);
9327 }
9328 else
9329 {
9330 op[5] = gen_label_rtx ();
9331 op[6] = gen_label_rtx ();
9332
9333 output_asm_insn ("st\t%0,%1", op);
9334 output_asm_insn ("bras\t%2,%l6", op);
9335 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9336 output_asm_insn (".long\t%4-%l5", op);
9337 output_asm_insn (".long\t%3-%l5", op);
9338 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9339 output_asm_insn ("lr\t%0,%2", op);
9340 output_asm_insn ("a\t%0,0(%2)", op);
9341 output_asm_insn ("a\t%2,4(%2)", op);
9342 output_asm_insn ("basr\t%0,%0", op);
9343 output_asm_insn ("l\t%0,%1", op);
9344 }
9345 }
9346
9347 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9348 into its SYMBOL_REF_FLAGS. */
9349
9350 static void
9351 s390_encode_section_info (tree decl, rtx rtl, int first)
9352 {
9353 default_encode_section_info (decl, rtl, first);
9354
9355 if (TREE_CODE (decl) == VAR_DECL)
9356 {
9357 /* If a variable has a forced alignment to < 2 bytes, mark it
9358 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9359 operand. */
9360 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9361 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9362 if (!DECL_SIZE (decl)
9363 || !DECL_ALIGN (decl)
9364 || !host_integerp (DECL_SIZE (decl), 0)
9365 || (DECL_ALIGN (decl) <= 64
9366 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9367 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9368 }
9369
9370 /* Literal pool references don't have a decl so they are handled
9371 differently here. We rely on the information in the MEM_ALIGN
9372 entry to decide upon natural alignment. */
9373 if (MEM_P (rtl)
9374 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9375 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9376 && (MEM_ALIGN (rtl) == 0
9377 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9378 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9379 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9380 }
9381
9382 /* Output thunk to FILE that implements a C++ virtual function call (with
9383 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9384 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9385 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9386 relative to the resulting this pointer. */
9387
9388 static void
9389 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9390 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9391 tree function)
9392 {
9393 rtx op[10];
9394 int nonlocal = 0;
9395
9396 /* Make sure unwind info is emitted for the thunk if needed. */
9397 final_start_function (emit_barrier (), file, 1);
9398
9399 /* Operand 0 is the target function. */
9400 op[0] = XEXP (DECL_RTL (function), 0);
9401 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9402 {
9403 nonlocal = 1;
9404 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9405 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9406 op[0] = gen_rtx_CONST (Pmode, op[0]);
9407 }
9408
9409 /* Operand 1 is the 'this' pointer. */
9410 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9411 op[1] = gen_rtx_REG (Pmode, 3);
9412 else
9413 op[1] = gen_rtx_REG (Pmode, 2);
9414
9415 /* Operand 2 is the delta. */
9416 op[2] = GEN_INT (delta);
9417
9418 /* Operand 3 is the vcall_offset. */
9419 op[3] = GEN_INT (vcall_offset);
9420
9421 /* Operand 4 is the temporary register. */
9422 op[4] = gen_rtx_REG (Pmode, 1);
9423
9424 /* Operands 5 to 8 can be used as labels. */
9425 op[5] = NULL_RTX;
9426 op[6] = NULL_RTX;
9427 op[7] = NULL_RTX;
9428 op[8] = NULL_RTX;
9429
9430 /* Operand 9 can be used for temporary register. */
9431 op[9] = NULL_RTX;
9432
9433 /* Generate code. */
9434 if (TARGET_64BIT)
9435 {
9436 /* Setup literal pool pointer if required. */
9437 if ((!DISP_IN_RANGE (delta)
9438 && !CONST_OK_FOR_K (delta)
9439 && !CONST_OK_FOR_Os (delta))
9440 || (!DISP_IN_RANGE (vcall_offset)
9441 && !CONST_OK_FOR_K (vcall_offset)
9442 && !CONST_OK_FOR_Os (vcall_offset)))
9443 {
9444 op[5] = gen_label_rtx ();
9445 output_asm_insn ("larl\t%4,%5", op);
9446 }
9447
9448 /* Add DELTA to this pointer. */
9449 if (delta)
9450 {
9451 if (CONST_OK_FOR_J (delta))
9452 output_asm_insn ("la\t%1,%2(%1)", op);
9453 else if (DISP_IN_RANGE (delta))
9454 output_asm_insn ("lay\t%1,%2(%1)", op);
9455 else if (CONST_OK_FOR_K (delta))
9456 output_asm_insn ("aghi\t%1,%2", op);
9457 else if (CONST_OK_FOR_Os (delta))
9458 output_asm_insn ("agfi\t%1,%2", op);
9459 else
9460 {
9461 op[6] = gen_label_rtx ();
9462 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9463 }
9464 }
9465
9466 /* Perform vcall adjustment. */
9467 if (vcall_offset)
9468 {
9469 if (DISP_IN_RANGE (vcall_offset))
9470 {
9471 output_asm_insn ("lg\t%4,0(%1)", op);
9472 output_asm_insn ("ag\t%1,%3(%4)", op);
9473 }
9474 else if (CONST_OK_FOR_K (vcall_offset))
9475 {
9476 output_asm_insn ("lghi\t%4,%3", op);
9477 output_asm_insn ("ag\t%4,0(%1)", op);
9478 output_asm_insn ("ag\t%1,0(%4)", op);
9479 }
9480 else if (CONST_OK_FOR_Os (vcall_offset))
9481 {
9482 output_asm_insn ("lgfi\t%4,%3", op);
9483 output_asm_insn ("ag\t%4,0(%1)", op);
9484 output_asm_insn ("ag\t%1,0(%4)", op);
9485 }
9486 else
9487 {
9488 op[7] = gen_label_rtx ();
9489 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9490 output_asm_insn ("ag\t%4,0(%1)", op);
9491 output_asm_insn ("ag\t%1,0(%4)", op);
9492 }
9493 }
9494
9495 /* Jump to target. */
9496 output_asm_insn ("jg\t%0", op);
9497
9498 /* Output literal pool if required. */
9499 if (op[5])
9500 {
9501 output_asm_insn (".align\t4", op);
9502 targetm.asm_out.internal_label (file, "L",
9503 CODE_LABEL_NUMBER (op[5]));
9504 }
9505 if (op[6])
9506 {
9507 targetm.asm_out.internal_label (file, "L",
9508 CODE_LABEL_NUMBER (op[6]));
9509 output_asm_insn (".long\t%2", op);
9510 }
9511 if (op[7])
9512 {
9513 targetm.asm_out.internal_label (file, "L",
9514 CODE_LABEL_NUMBER (op[7]));
9515 output_asm_insn (".long\t%3", op);
9516 }
9517 }
9518 else
9519 {
9520 /* Setup base pointer if required. */
9521 if (!vcall_offset
9522 || (!DISP_IN_RANGE (delta)
9523 && !CONST_OK_FOR_K (delta)
9524 && !CONST_OK_FOR_Os (delta))
9525 || (!DISP_IN_RANGE (delta)
9526 && !CONST_OK_FOR_K (vcall_offset)
9527 && !CONST_OK_FOR_Os (vcall_offset)))
9528 {
9529 op[5] = gen_label_rtx ();
9530 output_asm_insn ("basr\t%4,0", op);
9531 targetm.asm_out.internal_label (file, "L",
9532 CODE_LABEL_NUMBER (op[5]));
9533 }
9534
9535 /* Add DELTA to this pointer. */
9536 if (delta)
9537 {
9538 if (CONST_OK_FOR_J (delta))
9539 output_asm_insn ("la\t%1,%2(%1)", op);
9540 else if (DISP_IN_RANGE (delta))
9541 output_asm_insn ("lay\t%1,%2(%1)", op);
9542 else if (CONST_OK_FOR_K (delta))
9543 output_asm_insn ("ahi\t%1,%2", op);
9544 else if (CONST_OK_FOR_Os (delta))
9545 output_asm_insn ("afi\t%1,%2", op);
9546 else
9547 {
9548 op[6] = gen_label_rtx ();
9549 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9550 }
9551 }
9552
9553 /* Perform vcall adjustment. */
9554 if (vcall_offset)
9555 {
9556 if (CONST_OK_FOR_J (vcall_offset))
9557 {
9558 output_asm_insn ("l\t%4,0(%1)", op);
9559 output_asm_insn ("a\t%1,%3(%4)", op);
9560 }
9561 else if (DISP_IN_RANGE (vcall_offset))
9562 {
9563 output_asm_insn ("l\t%4,0(%1)", op);
9564 output_asm_insn ("ay\t%1,%3(%4)", op);
9565 }
9566 else if (CONST_OK_FOR_K (vcall_offset))
9567 {
9568 output_asm_insn ("lhi\t%4,%3", op);
9569 output_asm_insn ("a\t%4,0(%1)", op);
9570 output_asm_insn ("a\t%1,0(%4)", op);
9571 }
9572 else if (CONST_OK_FOR_Os (vcall_offset))
9573 {
9574 output_asm_insn ("iilf\t%4,%3", op);
9575 output_asm_insn ("a\t%4,0(%1)", op);
9576 output_asm_insn ("a\t%1,0(%4)", op);
9577 }
9578 else
9579 {
9580 op[7] = gen_label_rtx ();
9581 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9582 output_asm_insn ("a\t%4,0(%1)", op);
9583 output_asm_insn ("a\t%1,0(%4)", op);
9584 }
9585
9586 /* We had to clobber the base pointer register.
9587 Re-setup the base pointer (with a different base). */
9588 op[5] = gen_label_rtx ();
9589 output_asm_insn ("basr\t%4,0", op);
9590 targetm.asm_out.internal_label (file, "L",
9591 CODE_LABEL_NUMBER (op[5]));
9592 }
9593
9594 /* Jump to target. */
9595 op[8] = gen_label_rtx ();
9596
9597 if (!flag_pic)
9598 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9599 else if (!nonlocal)
9600 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9601 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9602 else if (flag_pic == 1)
9603 {
9604 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9605 output_asm_insn ("l\t%4,%0(%4)", op);
9606 }
9607 else if (flag_pic == 2)
9608 {
9609 op[9] = gen_rtx_REG (Pmode, 0);
9610 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9611 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9612 output_asm_insn ("ar\t%4,%9", op);
9613 output_asm_insn ("l\t%4,0(%4)", op);
9614 }
9615
9616 output_asm_insn ("br\t%4", op);
9617
9618 /* Output literal pool. */
9619 output_asm_insn (".align\t4", op);
9620
9621 if (nonlocal && flag_pic == 2)
9622 output_asm_insn (".long\t%0", op);
9623 if (nonlocal)
9624 {
9625 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9626 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9627 }
9628
9629 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9630 if (!flag_pic)
9631 output_asm_insn (".long\t%0", op);
9632 else
9633 output_asm_insn (".long\t%0-%5", op);
9634
9635 if (op[6])
9636 {
9637 targetm.asm_out.internal_label (file, "L",
9638 CODE_LABEL_NUMBER (op[6]));
9639 output_asm_insn (".long\t%2", op);
9640 }
9641 if (op[7])
9642 {
9643 targetm.asm_out.internal_label (file, "L",
9644 CODE_LABEL_NUMBER (op[7]));
9645 output_asm_insn (".long\t%3", op);
9646 }
9647 }
9648 final_end_function ();
9649 }
9650
9651 static bool
9652 s390_valid_pointer_mode (enum machine_mode mode)
9653 {
9654 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9655 }
9656
9657 /* Checks whether the given CALL_EXPR would use a caller
9658 saved register. This is used to decide whether sibling call
9659 optimization could be performed on the respective function
9660 call. */
9661
9662 static bool
9663 s390_call_saved_register_used (tree call_expr)
9664 {
9665 CUMULATIVE_ARGS cum_v;
9666 cumulative_args_t cum;
9667 tree parameter;
9668 enum machine_mode mode;
9669 tree type;
9670 rtx parm_rtx;
9671 int reg, i;
9672
9673 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9674 cum = pack_cumulative_args (&cum_v);
9675
9676 for (i = 0; i < call_expr_nargs (call_expr); i++)
9677 {
9678 parameter = CALL_EXPR_ARG (call_expr, i);
9679 gcc_assert (parameter);
9680
9681 /* For an undeclared variable passed as parameter we will get
9682 an ERROR_MARK node here. */
9683 if (TREE_CODE (parameter) == ERROR_MARK)
9684 return true;
9685
9686 type = TREE_TYPE (parameter);
9687 gcc_assert (type);
9688
9689 mode = TYPE_MODE (type);
9690 gcc_assert (mode);
9691
9692 if (pass_by_reference (&cum_v, mode, type, true))
9693 {
9694 mode = Pmode;
9695 type = build_pointer_type (type);
9696 }
9697
9698 parm_rtx = s390_function_arg (cum, mode, type, 0);
9699
9700 s390_function_arg_advance (cum, mode, type, 0);
9701
9702 if (!parm_rtx)
9703 continue;
9704
9705 if (REG_P (parm_rtx))
9706 {
9707 for (reg = 0;
9708 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9709 reg++)
9710 if (!call_used_regs[reg + REGNO (parm_rtx)])
9711 return true;
9712 }
9713
9714 if (GET_CODE (parm_rtx) == PARALLEL)
9715 {
9716 int i;
9717
9718 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9719 {
9720 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9721
9722 gcc_assert (REG_P (r));
9723
9724 for (reg = 0;
9725 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9726 reg++)
9727 if (!call_used_regs[reg + REGNO (r)])
9728 return true;
9729 }
9730 }
9731
9732 }
9733 return false;
9734 }
9735
9736 /* Return true if the given call expression can be
9737 turned into a sibling call.
9738 DECL holds the declaration of the function to be called whereas
9739 EXP is the call expression itself. */
9740
9741 static bool
9742 s390_function_ok_for_sibcall (tree decl, tree exp)
9743 {
9744 /* The TPF epilogue uses register 1. */
9745 if (TARGET_TPF_PROFILING)
9746 return false;
9747
9748 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9749 which would have to be restored before the sibcall. */
9750 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9751 return false;
9752
9753 /* Register 6 on s390 is available as an argument register but unfortunately
9754 "caller saved". This makes functions needing this register for arguments
9755 not suitable for sibcalls. */
9756 return !s390_call_saved_register_used (exp);
9757 }
9758
9759 /* Return the fixed registers used for condition codes. */
9760
9761 static bool
9762 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9763 {
9764 *p1 = CC_REGNUM;
9765 *p2 = INVALID_REGNUM;
9766
9767 return true;
9768 }
9769
9770 /* This function is used by the call expanders of the machine description.
9771 It emits the call insn itself together with the necessary operations
9772 to adjust the target address and returns the emitted insn.
9773 ADDR_LOCATION is the target address rtx
9774 TLS_CALL the location of the thread-local symbol
9775 RESULT_REG the register where the result of the call should be stored
9776 RETADDR_REG the register where the return address should be stored
9777 If this parameter is NULL_RTX the call is considered
9778 to be a sibling call. */
9779
9780 rtx
9781 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9782 rtx retaddr_reg)
9783 {
9784 bool plt_call = false;
9785 rtx insn;
9786 rtx call;
9787 rtx clobber;
9788 rtvec vec;
9789
9790 /* Direct function calls need special treatment. */
9791 if (GET_CODE (addr_location) == SYMBOL_REF)
9792 {
9793 /* When calling a global routine in PIC mode, we must
9794 replace the symbol itself with the PLT stub. */
9795 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9796 {
9797 if (retaddr_reg != NULL_RTX)
9798 {
9799 addr_location = gen_rtx_UNSPEC (Pmode,
9800 gen_rtvec (1, addr_location),
9801 UNSPEC_PLT);
9802 addr_location = gen_rtx_CONST (Pmode, addr_location);
9803 plt_call = true;
9804 }
9805 else
9806 /* For -fpic code the PLT entries might use r12 which is
9807 call-saved. Therefore we cannot do a sibcall when
9808 calling directly using a symbol ref. When reaching
9809 this point we decided (in s390_function_ok_for_sibcall)
9810 to do a sibcall for a function pointer but one of the
9811 optimizers was able to get rid of the function pointer
9812 by propagating the symbol ref into the call. This
9813 optimization is illegal for S/390 so we turn the direct
9814 call into a indirect call again. */
9815 addr_location = force_reg (Pmode, addr_location);
9816 }
9817
9818 /* Unless we can use the bras(l) insn, force the
9819 routine address into a register. */
9820 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9821 {
9822 if (flag_pic)
9823 addr_location = legitimize_pic_address (addr_location, 0);
9824 else
9825 addr_location = force_reg (Pmode, addr_location);
9826 }
9827 }
9828
9829 /* If it is already an indirect call or the code above moved the
9830 SYMBOL_REF to somewhere else make sure the address can be found in
9831 register 1. */
9832 if (retaddr_reg == NULL_RTX
9833 && GET_CODE (addr_location) != SYMBOL_REF
9834 && !plt_call)
9835 {
9836 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9837 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9838 }
9839
9840 addr_location = gen_rtx_MEM (QImode, addr_location);
9841 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9842
9843 if (result_reg != NULL_RTX)
9844 call = gen_rtx_SET (VOIDmode, result_reg, call);
9845
9846 if (retaddr_reg != NULL_RTX)
9847 {
9848 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9849
9850 if (tls_call != NULL_RTX)
9851 vec = gen_rtvec (3, call, clobber,
9852 gen_rtx_USE (VOIDmode, tls_call));
9853 else
9854 vec = gen_rtvec (2, call, clobber);
9855
9856 call = gen_rtx_PARALLEL (VOIDmode, vec);
9857 }
9858
9859 insn = emit_call_insn (call);
9860
9861 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9862 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9863 {
9864 /* s390_function_ok_for_sibcall should
9865 have denied sibcalls in this case. */
9866 gcc_assert (retaddr_reg != NULL_RTX);
9867 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
9868 }
9869 return insn;
9870 }
9871
9872 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9873
9874 static void
9875 s390_conditional_register_usage (void)
9876 {
9877 int i;
9878
9879 if (flag_pic)
9880 {
9881 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9882 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9883 }
9884 if (TARGET_CPU_ZARCH)
9885 {
9886 fixed_regs[BASE_REGNUM] = 0;
9887 call_used_regs[BASE_REGNUM] = 0;
9888 fixed_regs[RETURN_REGNUM] = 0;
9889 call_used_regs[RETURN_REGNUM] = 0;
9890 }
9891 if (TARGET_64BIT)
9892 {
9893 for (i = 24; i < 32; i++)
9894 call_used_regs[i] = call_really_used_regs[i] = 0;
9895 }
9896 else
9897 {
9898 for (i = 18; i < 20; i++)
9899 call_used_regs[i] = call_really_used_regs[i] = 0;
9900 }
9901
9902 if (TARGET_SOFT_FLOAT)
9903 {
9904 for (i = 16; i < 32; i++)
9905 call_used_regs[i] = fixed_regs[i] = 1;
9906 }
9907 }
9908
9909 /* Corresponding function to eh_return expander. */
9910
9911 static GTY(()) rtx s390_tpf_eh_return_symbol;
9912 void
9913 s390_emit_tpf_eh_return (rtx target)
9914 {
9915 rtx insn, reg;
9916
9917 if (!s390_tpf_eh_return_symbol)
9918 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9919
9920 reg = gen_rtx_REG (Pmode, 2);
9921
9922 emit_move_insn (reg, target);
9923 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9924 gen_rtx_REG (Pmode, RETURN_REGNUM));
9925 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9926
9927 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9928 }
9929
9930 /* Rework the prologue/epilogue to avoid saving/restoring
9931 registers unnecessarily. */
9932
9933 static void
9934 s390_optimize_prologue (void)
9935 {
9936 rtx insn, new_insn, next_insn;
9937
9938 /* Do a final recompute of the frame-related data. */
9939
9940 s390_update_frame_layout ();
9941
9942 /* If all special registers are in fact used, there's nothing we
9943 can do, so no point in walking the insn list. */
9944
9945 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9946 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9947 && (TARGET_CPU_ZARCH
9948 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9949 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9950 return;
9951
9952 /* Search for prologue/epilogue insns and replace them. */
9953
9954 for (insn = get_insns (); insn; insn = next_insn)
9955 {
9956 int first, last, off;
9957 rtx set, base, offset;
9958
9959 next_insn = NEXT_INSN (insn);
9960
9961 if (GET_CODE (insn) != INSN)
9962 continue;
9963
9964 if (GET_CODE (PATTERN (insn)) == PARALLEL
9965 && store_multiple_operation (PATTERN (insn), VOIDmode))
9966 {
9967 set = XVECEXP (PATTERN (insn), 0, 0);
9968 first = REGNO (SET_SRC (set));
9969 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9970 offset = const0_rtx;
9971 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9972 off = INTVAL (offset);
9973
9974 if (GET_CODE (base) != REG || off < 0)
9975 continue;
9976 if (cfun_frame_layout.first_save_gpr != -1
9977 && (cfun_frame_layout.first_save_gpr < first
9978 || cfun_frame_layout.last_save_gpr > last))
9979 continue;
9980 if (REGNO (base) != STACK_POINTER_REGNUM
9981 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9982 continue;
9983 if (first > BASE_REGNUM || last < BASE_REGNUM)
9984 continue;
9985
9986 if (cfun_frame_layout.first_save_gpr != -1)
9987 {
9988 new_insn = save_gprs (base,
9989 off + (cfun_frame_layout.first_save_gpr
9990 - first) * UNITS_PER_LONG,
9991 cfun_frame_layout.first_save_gpr,
9992 cfun_frame_layout.last_save_gpr);
9993 new_insn = emit_insn_before (new_insn, insn);
9994 INSN_ADDRESSES_NEW (new_insn, -1);
9995 }
9996
9997 remove_insn (insn);
9998 continue;
9999 }
10000
10001 if (cfun_frame_layout.first_save_gpr == -1
10002 && GET_CODE (PATTERN (insn)) == SET
10003 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10004 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10005 || (!TARGET_CPU_ZARCH
10006 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10007 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10008 {
10009 set = PATTERN (insn);
10010 first = REGNO (SET_SRC (set));
10011 offset = const0_rtx;
10012 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10013 off = INTVAL (offset);
10014
10015 if (GET_CODE (base) != REG || off < 0)
10016 continue;
10017 if (REGNO (base) != STACK_POINTER_REGNUM
10018 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10019 continue;
10020
10021 remove_insn (insn);
10022 continue;
10023 }
10024
10025 if (GET_CODE (PATTERN (insn)) == PARALLEL
10026 && load_multiple_operation (PATTERN (insn), VOIDmode))
10027 {
10028 set = XVECEXP (PATTERN (insn), 0, 0);
10029 first = REGNO (SET_DEST (set));
10030 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10031 offset = const0_rtx;
10032 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10033 off = INTVAL (offset);
10034
10035 if (GET_CODE (base) != REG || off < 0)
10036 continue;
10037 if (cfun_frame_layout.first_restore_gpr != -1
10038 && (cfun_frame_layout.first_restore_gpr < first
10039 || cfun_frame_layout.last_restore_gpr > last))
10040 continue;
10041 if (REGNO (base) != STACK_POINTER_REGNUM
10042 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10043 continue;
10044 if (first > BASE_REGNUM || last < BASE_REGNUM)
10045 continue;
10046
10047 if (cfun_frame_layout.first_restore_gpr != -1)
10048 {
10049 new_insn = restore_gprs (base,
10050 off + (cfun_frame_layout.first_restore_gpr
10051 - first) * UNITS_PER_LONG,
10052 cfun_frame_layout.first_restore_gpr,
10053 cfun_frame_layout.last_restore_gpr);
10054 new_insn = emit_insn_before (new_insn, insn);
10055 INSN_ADDRESSES_NEW (new_insn, -1);
10056 }
10057
10058 remove_insn (insn);
10059 continue;
10060 }
10061
10062 if (cfun_frame_layout.first_restore_gpr == -1
10063 && GET_CODE (PATTERN (insn)) == SET
10064 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10065 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10066 || (!TARGET_CPU_ZARCH
10067 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10068 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10069 {
10070 set = PATTERN (insn);
10071 first = REGNO (SET_DEST (set));
10072 offset = const0_rtx;
10073 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10074 off = INTVAL (offset);
10075
10076 if (GET_CODE (base) != REG || off < 0)
10077 continue;
10078 if (REGNO (base) != STACK_POINTER_REGNUM
10079 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10080 continue;
10081
10082 remove_insn (insn);
10083 continue;
10084 }
10085 }
10086 }
10087
10088 /* On z10 and later the dynamic branch prediction must see the
10089 backward jump within a certain windows. If not it falls back to
10090 the static prediction. This function rearranges the loop backward
10091 branch in a way which makes the static prediction always correct.
10092 The function returns true if it added an instruction. */
10093 static bool
10094 s390_fix_long_loop_prediction (rtx insn)
10095 {
10096 rtx set = single_set (insn);
10097 rtx code_label, label_ref, new_label;
10098 rtx uncond_jump;
10099 rtx cur_insn;
10100 rtx tmp;
10101 int distance;
10102
10103 /* This will exclude branch on count and branch on index patterns
10104 since these are correctly statically predicted. */
10105 if (!set
10106 || SET_DEST (set) != pc_rtx
10107 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10108 return false;
10109
10110 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10111 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10112
10113 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10114
10115 code_label = XEXP (label_ref, 0);
10116
10117 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10118 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10119 || (INSN_ADDRESSES (INSN_UID (insn))
10120 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10121 return false;
10122
10123 for (distance = 0, cur_insn = PREV_INSN (insn);
10124 distance < PREDICT_DISTANCE - 6;
10125 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10126 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10127 return false;
10128
10129 new_label = gen_label_rtx ();
10130 uncond_jump = emit_jump_insn_after (
10131 gen_rtx_SET (VOIDmode, pc_rtx,
10132 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10133 insn);
10134 emit_label_after (new_label, uncond_jump);
10135
10136 tmp = XEXP (SET_SRC (set), 1);
10137 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10138 XEXP (SET_SRC (set), 2) = tmp;
10139 INSN_CODE (insn) = -1;
10140
10141 XEXP (label_ref, 0) = new_label;
10142 JUMP_LABEL (insn) = new_label;
10143 JUMP_LABEL (uncond_jump) = code_label;
10144
10145 return true;
10146 }
10147
10148 /* Returns 1 if INSN reads the value of REG for purposes not related
10149 to addressing of memory, and 0 otherwise. */
10150 static int
10151 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10152 {
10153 return reg_referenced_p (reg, PATTERN (insn))
10154 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10155 }
10156
10157 /* Starting from INSN find_cond_jump looks downwards in the insn
10158 stream for a single jump insn which is the last user of the
10159 condition code set in INSN. */
10160 static rtx
10161 find_cond_jump (rtx insn)
10162 {
10163 for (; insn; insn = NEXT_INSN (insn))
10164 {
10165 rtx ite, cc;
10166
10167 if (LABEL_P (insn))
10168 break;
10169
10170 if (!JUMP_P (insn))
10171 {
10172 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10173 break;
10174 continue;
10175 }
10176
10177 /* This will be triggered by a return. */
10178 if (GET_CODE (PATTERN (insn)) != SET)
10179 break;
10180
10181 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10182 ite = SET_SRC (PATTERN (insn));
10183
10184 if (GET_CODE (ite) != IF_THEN_ELSE)
10185 break;
10186
10187 cc = XEXP (XEXP (ite, 0), 0);
10188 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10189 break;
10190
10191 if (find_reg_note (insn, REG_DEAD, cc))
10192 return insn;
10193 break;
10194 }
10195
10196 return NULL_RTX;
10197 }
10198
10199 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10200 the semantics does not change. If NULL_RTX is passed as COND the
10201 function tries to find the conditional jump starting with INSN. */
10202 static void
10203 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10204 {
10205 rtx tmp = *op0;
10206
10207 if (cond == NULL_RTX)
10208 {
10209 rtx jump = find_cond_jump (NEXT_INSN (insn));
10210 jump = jump ? single_set (jump) : NULL_RTX;
10211
10212 if (jump == NULL_RTX)
10213 return;
10214
10215 cond = XEXP (XEXP (jump, 1), 0);
10216 }
10217
10218 *op0 = *op1;
10219 *op1 = tmp;
10220 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10221 }
10222
10223 /* On z10, instructions of the compare-and-branch family have the
10224 property to access the register occurring as second operand with
10225 its bits complemented. If such a compare is grouped with a second
10226 instruction that accesses the same register non-complemented, and
10227 if that register's value is delivered via a bypass, then the
10228 pipeline recycles, thereby causing significant performance decline.
10229 This function locates such situations and exchanges the two
10230 operands of the compare. The function return true whenever it
10231 added an insn. */
10232 static bool
10233 s390_z10_optimize_cmp (rtx insn)
10234 {
10235 rtx prev_insn, next_insn;
10236 bool insn_added_p = false;
10237 rtx cond, *op0, *op1;
10238
10239 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10240 {
10241 /* Handle compare and branch and branch on count
10242 instructions. */
10243 rtx pattern = single_set (insn);
10244
10245 if (!pattern
10246 || SET_DEST (pattern) != pc_rtx
10247 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10248 return false;
10249
10250 cond = XEXP (SET_SRC (pattern), 0);
10251 op0 = &XEXP (cond, 0);
10252 op1 = &XEXP (cond, 1);
10253 }
10254 else if (GET_CODE (PATTERN (insn)) == SET)
10255 {
10256 rtx src, dest;
10257
10258 /* Handle normal compare instructions. */
10259 src = SET_SRC (PATTERN (insn));
10260 dest = SET_DEST (PATTERN (insn));
10261
10262 if (!REG_P (dest)
10263 || !CC_REGNO_P (REGNO (dest))
10264 || GET_CODE (src) != COMPARE)
10265 return false;
10266
10267 /* s390_swap_cmp will try to find the conditional
10268 jump when passing NULL_RTX as condition. */
10269 cond = NULL_RTX;
10270 op0 = &XEXP (src, 0);
10271 op1 = &XEXP (src, 1);
10272 }
10273 else
10274 return false;
10275
10276 if (!REG_P (*op0) || !REG_P (*op1))
10277 return false;
10278
10279 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10280 return false;
10281
10282 /* Swap the COMPARE arguments and its mask if there is a
10283 conflicting access in the previous insn. */
10284 prev_insn = prev_active_insn (insn);
10285 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10286 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10287 s390_swap_cmp (cond, op0, op1, insn);
10288
10289 /* Check if there is a conflict with the next insn. If there
10290 was no conflict with the previous insn, then swap the
10291 COMPARE arguments and its mask. If we already swapped
10292 the operands, or if swapping them would cause a conflict
10293 with the previous insn, issue a NOP after the COMPARE in
10294 order to separate the two instuctions. */
10295 next_insn = next_active_insn (insn);
10296 if (next_insn != NULL_RTX && INSN_P (next_insn)
10297 && s390_non_addr_reg_read_p (*op1, next_insn))
10298 {
10299 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10300 && s390_non_addr_reg_read_p (*op0, prev_insn))
10301 {
10302 if (REGNO (*op1) == 0)
10303 emit_insn_after (gen_nop1 (), insn);
10304 else
10305 emit_insn_after (gen_nop (), insn);
10306 insn_added_p = true;
10307 }
10308 else
10309 s390_swap_cmp (cond, op0, op1, insn);
10310 }
10311 return insn_added_p;
10312 }
10313
10314 /* Perform machine-dependent processing. */
10315
10316 static void
10317 s390_reorg (void)
10318 {
10319 bool pool_overflow = false;
10320
10321 /* Make sure all splits have been performed; splits after
10322 machine_dependent_reorg might confuse insn length counts. */
10323 split_all_insns_noflow ();
10324
10325 /* Install the main literal pool and the associated base
10326 register load insns.
10327
10328 In addition, there are two problematic situations we need
10329 to correct:
10330
10331 - the literal pool might be > 4096 bytes in size, so that
10332 some of its elements cannot be directly accessed
10333
10334 - a branch target might be > 64K away from the branch, so that
10335 it is not possible to use a PC-relative instruction.
10336
10337 To fix those, we split the single literal pool into multiple
10338 pool chunks, reloading the pool base register at various
10339 points throughout the function to ensure it always points to
10340 the pool chunk the following code expects, and / or replace
10341 PC-relative branches by absolute branches.
10342
10343 However, the two problems are interdependent: splitting the
10344 literal pool can move a branch further away from its target,
10345 causing the 64K limit to overflow, and on the other hand,
10346 replacing a PC-relative branch by an absolute branch means
10347 we need to put the branch target address into the literal
10348 pool, possibly causing it to overflow.
10349
10350 So, we loop trying to fix up both problems until we manage
10351 to satisfy both conditions at the same time. Note that the
10352 loop is guaranteed to terminate as every pass of the loop
10353 strictly decreases the total number of PC-relative branches
10354 in the function. (This is not completely true as there
10355 might be branch-over-pool insns introduced by chunkify_start.
10356 Those never need to be split however.) */
10357
10358 for (;;)
10359 {
10360 struct constant_pool *pool = NULL;
10361
10362 /* Collect the literal pool. */
10363 if (!pool_overflow)
10364 {
10365 pool = s390_mainpool_start ();
10366 if (!pool)
10367 pool_overflow = true;
10368 }
10369
10370 /* If literal pool overflowed, start to chunkify it. */
10371 if (pool_overflow)
10372 pool = s390_chunkify_start ();
10373
10374 /* Split out-of-range branches. If this has created new
10375 literal pool entries, cancel current chunk list and
10376 recompute it. zSeries machines have large branch
10377 instructions, so we never need to split a branch. */
10378 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10379 {
10380 if (pool_overflow)
10381 s390_chunkify_cancel (pool);
10382 else
10383 s390_mainpool_cancel (pool);
10384
10385 continue;
10386 }
10387
10388 /* If we made it up to here, both conditions are satisfied.
10389 Finish up literal pool related changes. */
10390 if (pool_overflow)
10391 s390_chunkify_finish (pool);
10392 else
10393 s390_mainpool_finish (pool);
10394
10395 /* We're done splitting branches. */
10396 cfun->machine->split_branches_pending_p = false;
10397 break;
10398 }
10399
10400 /* Generate out-of-pool execute target insns. */
10401 if (TARGET_CPU_ZARCH)
10402 {
10403 rtx insn, label, target;
10404
10405 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10406 {
10407 label = s390_execute_label (insn);
10408 if (!label)
10409 continue;
10410
10411 gcc_assert (label != const0_rtx);
10412
10413 target = emit_label (XEXP (label, 0));
10414 INSN_ADDRESSES_NEW (target, -1);
10415
10416 target = emit_insn (s390_execute_target (insn));
10417 INSN_ADDRESSES_NEW (target, -1);
10418 }
10419 }
10420
10421 /* Try to optimize prologue and epilogue further. */
10422 s390_optimize_prologue ();
10423
10424 /* Walk over the insns and do some >=z10 specific changes. */
10425 if (s390_tune == PROCESSOR_2097_Z10
10426 || s390_tune == PROCESSOR_2817_Z196)
10427 {
10428 rtx insn;
10429 bool insn_added_p = false;
10430
10431 /* The insn lengths and addresses have to be up to date for the
10432 following manipulations. */
10433 shorten_branches (get_insns ());
10434
10435 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10436 {
10437 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10438 continue;
10439
10440 if (JUMP_P (insn))
10441 insn_added_p |= s390_fix_long_loop_prediction (insn);
10442
10443 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10444 || GET_CODE (PATTERN (insn)) == SET)
10445 && s390_tune == PROCESSOR_2097_Z10)
10446 insn_added_p |= s390_z10_optimize_cmp (insn);
10447 }
10448
10449 /* Adjust branches if we added new instructions. */
10450 if (insn_added_p)
10451 shorten_branches (get_insns ());
10452 }
10453 }
10454
10455 /* Return true if INSN is a fp load insn writing register REGNO. */
10456 static inline bool
10457 s390_fpload_toreg (rtx insn, unsigned int regno)
10458 {
10459 rtx set;
10460 enum attr_type flag = s390_safe_attr_type (insn);
10461
10462 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10463 return false;
10464
10465 set = single_set (insn);
10466
10467 if (set == NULL_RTX)
10468 return false;
10469
10470 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10471 return false;
10472
10473 if (REGNO (SET_DEST (set)) != regno)
10474 return false;
10475
10476 return true;
10477 }
10478
10479 /* This value describes the distance to be avoided between an
10480 aritmetic fp instruction and an fp load writing the same register.
10481 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10482 fine but the exact value has to be avoided. Otherwise the FP
10483 pipeline will throw an exception causing a major penalty. */
10484 #define Z10_EARLYLOAD_DISTANCE 7
10485
10486 /* Rearrange the ready list in order to avoid the situation described
10487 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10488 moved to the very end of the ready list. */
10489 static void
10490 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10491 {
10492 unsigned int regno;
10493 int nready = *nready_p;
10494 rtx tmp;
10495 int i;
10496 rtx insn;
10497 rtx set;
10498 enum attr_type flag;
10499 int distance;
10500
10501 /* Skip DISTANCE - 1 active insns. */
10502 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10503 distance > 0 && insn != NULL_RTX;
10504 distance--, insn = prev_active_insn (insn))
10505 if (CALL_P (insn) || JUMP_P (insn))
10506 return;
10507
10508 if (insn == NULL_RTX)
10509 return;
10510
10511 set = single_set (insn);
10512
10513 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10514 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10515 return;
10516
10517 flag = s390_safe_attr_type (insn);
10518
10519 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10520 return;
10521
10522 regno = REGNO (SET_DEST (set));
10523 i = nready - 1;
10524
10525 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10526 i--;
10527
10528 if (!i)
10529 return;
10530
10531 tmp = ready[i];
10532 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10533 ready[0] = tmp;
10534 }
10535
10536 /* This function is called via hook TARGET_SCHED_REORDER before
10537 issuing one insn from list READY which contains *NREADYP entries.
10538 For target z10 it reorders load instructions to avoid early load
10539 conflicts in the floating point pipeline */
10540 static int
10541 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10542 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10543 {
10544 if (s390_tune == PROCESSOR_2097_Z10)
10545 if (reload_completed && *nreadyp > 1)
10546 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10547
10548 return s390_issue_rate ();
10549 }
10550
10551 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10552 the scheduler has issued INSN. It stores the last issued insn into
10553 last_scheduled_insn in order to make it available for
10554 s390_sched_reorder. */
10555 static int
10556 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10557 int verbose ATTRIBUTE_UNUSED,
10558 rtx insn, int more)
10559 {
10560 last_scheduled_insn = insn;
10561
10562 if (GET_CODE (PATTERN (insn)) != USE
10563 && GET_CODE (PATTERN (insn)) != CLOBBER)
10564 return more - 1;
10565 else
10566 return more;
10567 }
10568
10569 static void
10570 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10571 int verbose ATTRIBUTE_UNUSED,
10572 int max_ready ATTRIBUTE_UNUSED)
10573 {
10574 last_scheduled_insn = NULL_RTX;
10575 }
10576
10577 /* This function checks the whole of insn X for memory references. The
10578 function always returns zero because the framework it is called
10579 from would stop recursively analyzing the insn upon a return value
10580 other than zero. The real result of this function is updating
10581 counter variable MEM_COUNT. */
10582 static int
10583 check_dpu (rtx *x, unsigned *mem_count)
10584 {
10585 if (*x != NULL_RTX && MEM_P (*x))
10586 (*mem_count)++;
10587 return 0;
10588 }
10589
10590 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10591 a new number struct loop *loop should be unrolled if tuned for cpus with
10592 a built-in stride prefetcher.
10593 The loop is analyzed for memory accesses by calling check_dpu for
10594 each rtx of the loop. Depending on the loop_depth and the amount of
10595 memory accesses a new number <=nunroll is returned to improve the
10596 behaviour of the hardware prefetch unit. */
10597 static unsigned
10598 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10599 {
10600 basic_block *bbs;
10601 rtx insn;
10602 unsigned i;
10603 unsigned mem_count = 0;
10604
10605 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10606 return nunroll;
10607
10608 /* Count the number of memory references within the loop body. */
10609 bbs = get_loop_body (loop);
10610 for (i = 0; i < loop->num_nodes; i++)
10611 {
10612 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10613 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10614 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10615 }
10616 free (bbs);
10617
10618 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10619 if (mem_count == 0)
10620 return nunroll;
10621
10622 switch (loop_depth(loop))
10623 {
10624 case 1:
10625 return MIN (nunroll, 28 / mem_count);
10626 case 2:
10627 return MIN (nunroll, 22 / mem_count);
10628 default:
10629 return MIN (nunroll, 16 / mem_count);
10630 }
10631 }
10632
10633 /* Initialize GCC target structure. */
10634
10635 #undef TARGET_ASM_ALIGNED_HI_OP
10636 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10637 #undef TARGET_ASM_ALIGNED_DI_OP
10638 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10639 #undef TARGET_ASM_INTEGER
10640 #define TARGET_ASM_INTEGER s390_assemble_integer
10641
10642 #undef TARGET_ASM_OPEN_PAREN
10643 #define TARGET_ASM_OPEN_PAREN ""
10644
10645 #undef TARGET_ASM_CLOSE_PAREN
10646 #define TARGET_ASM_CLOSE_PAREN ""
10647
10648 #undef TARGET_OPTION_OVERRIDE
10649 #define TARGET_OPTION_OVERRIDE s390_option_override
10650
10651 #undef TARGET_ENCODE_SECTION_INFO
10652 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10653
10654 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10655 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10656
10657 #ifdef HAVE_AS_TLS
10658 #undef TARGET_HAVE_TLS
10659 #define TARGET_HAVE_TLS true
10660 #endif
10661 #undef TARGET_CANNOT_FORCE_CONST_MEM
10662 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10663
10664 #undef TARGET_DELEGITIMIZE_ADDRESS
10665 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10666
10667 #undef TARGET_LEGITIMIZE_ADDRESS
10668 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10669
10670 #undef TARGET_RETURN_IN_MEMORY
10671 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10672
10673 #undef TARGET_INIT_BUILTINS
10674 #define TARGET_INIT_BUILTINS s390_init_builtins
10675 #undef TARGET_EXPAND_BUILTIN
10676 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10677
10678 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10679 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10680
10681 #undef TARGET_ASM_OUTPUT_MI_THUNK
10682 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10683 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10684 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10685
10686 #undef TARGET_SCHED_ADJUST_PRIORITY
10687 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10688 #undef TARGET_SCHED_ISSUE_RATE
10689 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10690 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10691 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10692
10693 #undef TARGET_SCHED_VARIABLE_ISSUE
10694 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10695 #undef TARGET_SCHED_REORDER
10696 #define TARGET_SCHED_REORDER s390_sched_reorder
10697 #undef TARGET_SCHED_INIT
10698 #define TARGET_SCHED_INIT s390_sched_init
10699
10700 #undef TARGET_CANNOT_COPY_INSN_P
10701 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10702 #undef TARGET_RTX_COSTS
10703 #define TARGET_RTX_COSTS s390_rtx_costs
10704 #undef TARGET_ADDRESS_COST
10705 #define TARGET_ADDRESS_COST s390_address_cost
10706 #undef TARGET_REGISTER_MOVE_COST
10707 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10708 #undef TARGET_MEMORY_MOVE_COST
10709 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10710
10711 #undef TARGET_MACHINE_DEPENDENT_REORG
10712 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10713
10714 #undef TARGET_VALID_POINTER_MODE
10715 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10716
10717 #undef TARGET_BUILD_BUILTIN_VA_LIST
10718 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10719 #undef TARGET_EXPAND_BUILTIN_VA_START
10720 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10721 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10722 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10723
10724 #undef TARGET_PROMOTE_FUNCTION_MODE
10725 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10726 #undef TARGET_PASS_BY_REFERENCE
10727 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10728
10729 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10730 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10731 #undef TARGET_FUNCTION_ARG
10732 #define TARGET_FUNCTION_ARG s390_function_arg
10733 #undef TARGET_FUNCTION_ARG_ADVANCE
10734 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10735 #undef TARGET_FUNCTION_VALUE
10736 #define TARGET_FUNCTION_VALUE s390_function_value
10737 #undef TARGET_LIBCALL_VALUE
10738 #define TARGET_LIBCALL_VALUE s390_libcall_value
10739
10740 #undef TARGET_FIXED_CONDITION_CODE_REGS
10741 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10742
10743 #undef TARGET_CC_MODES_COMPATIBLE
10744 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10745
10746 #undef TARGET_INVALID_WITHIN_DOLOOP
10747 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10748
10749 #ifdef HAVE_AS_TLS
10750 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10751 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10752 #endif
10753
10754 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10755 #undef TARGET_MANGLE_TYPE
10756 #define TARGET_MANGLE_TYPE s390_mangle_type
10757 #endif
10758
10759 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10760 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10761
10762 #undef TARGET_PREFERRED_RELOAD_CLASS
10763 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10764
10765 #undef TARGET_SECONDARY_RELOAD
10766 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10767
10768 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10769 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10770
10771 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10772 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10773
10774 #undef TARGET_LEGITIMATE_ADDRESS_P
10775 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10776
10777 #undef TARGET_LEGITIMATE_CONSTANT_P
10778 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10779
10780 #undef TARGET_CAN_ELIMINATE
10781 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10782
10783 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10784 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10785
10786 #undef TARGET_LOOP_UNROLL_ADJUST
10787 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10788
10789 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10790 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10791 #undef TARGET_TRAMPOLINE_INIT
10792 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10793
10794 #undef TARGET_UNWIND_WORD_MODE
10795 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10796
10797 struct gcc_target targetm = TARGET_INITIALIZER;
10798
10799 #include "gt-s390.h"