1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
59 /* Define the specific costs for a given cpu. */
61 struct processor_costs
64 const int m
; /* cost of an M instruction. */
65 const int mghi
; /* cost of an MGHI instruction. */
66 const int mh
; /* cost of an MH instruction. */
67 const int mhi
; /* cost of an MHI instruction. */
68 const int ml
; /* cost of an ML instruction. */
69 const int mr
; /* cost of an MR instruction. */
70 const int ms
; /* cost of an MS instruction. */
71 const int msg
; /* cost of an MSG instruction. */
72 const int msgf
; /* cost of an MSGF instruction. */
73 const int msgfr
; /* cost of an MSGFR instruction. */
74 const int msgr
; /* cost of an MSGR instruction. */
75 const int msr
; /* cost of an MSR instruction. */
76 const int mult_df
; /* cost of multiplication in DFmode. */
79 const int sqxbr
; /* cost of square root in TFmode. */
80 const int sqdbr
; /* cost of square root in DFmode. */
81 const int sqebr
; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr
; /* cost of multiply and add in DFmode. */
84 const int maebr
; /* cost of multiply and add in SFmode. */
96 const struct processor_costs
*s390_cost
;
99 struct processor_costs z900_cost
=
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
131 struct processor_costs z990_cost
=
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
163 struct processor_costs z9_109_cost
=
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
195 struct processor_costs z10_cost
=
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
227 struct processor_costs z196_cost
=
229 COSTS_N_INSNS (7), /* M */
230 COSTS_N_INSNS (5), /* MGHI */
231 COSTS_N_INSNS (5), /* MH */
232 COSTS_N_INSNS (5), /* MHI */
233 COSTS_N_INSNS (7), /* ML */
234 COSTS_N_INSNS (7), /* MR */
235 COSTS_N_INSNS (6), /* MS */
236 COSTS_N_INSNS (8), /* MSG */
237 COSTS_N_INSNS (6), /* MSGF */
238 COSTS_N_INSNS (6), /* MSGFR */
239 COSTS_N_INSNS (8), /* MSGR */
240 COSTS_N_INSNS (6), /* MSR */
241 COSTS_N_INSNS (1) , /* multiplication in DFmode */
242 COSTS_N_INSNS (40), /* MXBR B+40 */
243 COSTS_N_INSNS (100), /* SQXBR B+100 */
244 COSTS_N_INSNS (42), /* SQDBR B+42 */
245 COSTS_N_INSNS (28), /* SQEBR B+28 */
246 COSTS_N_INSNS (1), /* MADBR B */
247 COSTS_N_INSNS (1), /* MAEBR B */
248 COSTS_N_INSNS (101), /* DXBR B+101 */
249 COSTS_N_INSNS (29), /* DDBR */
250 COSTS_N_INSNS (22), /* DEBR */
251 COSTS_N_INSNS (160), /* DLGR cracked */
252 COSTS_N_INSNS (160), /* DLR cracked */
253 COSTS_N_INSNS (160), /* DR expanded */
254 COSTS_N_INSNS (160), /* DSGFR cracked */
255 COSTS_N_INSNS (160), /* DSGR cracked */
258 extern int reload_completed
;
260 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
261 static rtx last_scheduled_insn
;
263 /* Structure used to hold the components of a S/390 memory
264 address. A legitimate address on S/390 is of the general
266 base + index + displacement
267 where any of the components is optional.
269 base and index are registers of the class ADDR_REGS,
270 displacement is an unsigned 12-bit immediate constant. */
281 /* Which cpu are we tuning for. */
282 enum processor_type s390_tune
= PROCESSOR_max
;
284 /* Which instruction set architecture to use. */
285 enum processor_type s390_arch
;
288 HOST_WIDE_INT s390_warn_framesize
= 0;
289 HOST_WIDE_INT s390_stack_size
= 0;
290 HOST_WIDE_INT s390_stack_guard
= 0;
292 /* The following structure is embedded in the machine
293 specific part of struct function. */
295 struct GTY (()) s390_frame_layout
297 /* Offset within stack frame. */
298 HOST_WIDE_INT gprs_offset
;
299 HOST_WIDE_INT f0_offset
;
300 HOST_WIDE_INT f4_offset
;
301 HOST_WIDE_INT f8_offset
;
302 HOST_WIDE_INT backchain_offset
;
304 /* Number of first and last gpr where slots in the register
305 save area are reserved for. */
306 int first_save_gpr_slot
;
307 int last_save_gpr_slot
;
309 /* Number of first and last gpr to be saved, restored. */
311 int first_restore_gpr
;
313 int last_restore_gpr
;
315 /* Bits standing for floating point registers. Set, if the
316 respective register has to be saved. Starting with reg 16 (f0)
317 at the rightmost bit.
318 Bit 15 - 8 7 6 5 4 3 2 1 0
319 fpr 15 - 8 7 5 3 1 6 4 2 0
320 reg 31 - 24 23 22 21 20 19 18 17 16 */
321 unsigned int fpr_bitmap
;
323 /* Number of floating point registers f8-f15 which must be saved. */
326 /* Set if return address needs to be saved.
327 This flag is set by s390_return_addr_rtx if it could not use
328 the initial value of r14 and therefore depends on r14 saved
330 bool save_return_addr_p
;
332 /* Size of stack frame. */
333 HOST_WIDE_INT frame_size
;
336 /* Define the structure for the machine field in struct function. */
338 struct GTY(()) machine_function
340 struct s390_frame_layout frame_layout
;
342 /* Literal pool base register. */
345 /* True if we may need to perform branch splitting. */
346 bool split_branches_pending_p
;
348 /* Some local-dynamic TLS symbol name. */
349 const char *some_ld_name
;
351 bool has_landing_pad_p
;
354 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
356 #define cfun_frame_layout (cfun->machine->frame_layout)
357 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
358 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
359 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
360 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
362 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
365 /* Number of GPRs and FPRs used for argument passing. */
366 #define GP_ARG_NUM_REG 5
367 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
369 /* A couple of shortcuts. */
370 #define CONST_OK_FOR_J(x) \
371 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
372 #define CONST_OK_FOR_K(x) \
373 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
374 #define CONST_OK_FOR_Os(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
376 #define CONST_OK_FOR_Op(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
378 #define CONST_OK_FOR_On(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
381 #define REGNO_PAIR_OK(REGNO, MODE) \
382 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
384 /* That's the read ahead of the dynamic branch prediction unit in
385 bytes on a z10 (or higher) CPU. */
386 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
388 /* Return the alignment for LABEL. We default to the -falign-labels
389 value except for the literal pool base label. */
391 s390_label_align (rtx label
)
393 rtx prev_insn
= prev_active_insn (label
);
395 if (prev_insn
== NULL_RTX
)
398 prev_insn
= single_set (prev_insn
);
400 if (prev_insn
== NULL_RTX
)
403 prev_insn
= SET_SRC (prev_insn
);
405 /* Don't align literal pool base labels. */
406 if (GET_CODE (prev_insn
) == UNSPEC
407 && XINT (prev_insn
, 1) == UNSPEC_MAIN_BASE
)
411 return align_labels_log
;
414 static enum machine_mode
415 s390_libgcc_cmp_return_mode (void)
417 return TARGET_64BIT
? DImode
: SImode
;
420 static enum machine_mode
421 s390_libgcc_shift_count_mode (void)
423 return TARGET_64BIT
? DImode
: SImode
;
426 static enum machine_mode
427 s390_unwind_word_mode (void)
429 return TARGET_64BIT
? DImode
: SImode
;
432 /* Return true if the back end supports mode MODE. */
434 s390_scalar_mode_supported_p (enum machine_mode mode
)
436 /* In contrast to the default implementation reject TImode constants on 31bit
437 TARGET_ZARCH for ABI compliance. */
438 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
441 if (DECIMAL_FLOAT_MODE_P (mode
))
442 return default_decimal_float_supported_p ();
444 return default_scalar_mode_supported_p (mode
);
447 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
450 s390_set_has_landing_pad_p (bool value
)
452 cfun
->machine
->has_landing_pad_p
= value
;
455 /* If two condition code modes are compatible, return a condition code
456 mode which is compatible with both. Otherwise, return
459 static enum machine_mode
460 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
468 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
469 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
490 /* Return true if SET either doesn't set the CC register, or else
491 the source and destination have matching CC modes and that
492 CC mode is at least as constrained as REQ_MODE. */
495 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
497 enum machine_mode set_mode
;
499 gcc_assert (GET_CODE (set
) == SET
);
501 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
504 set_mode
= GET_MODE (SET_DEST (set
));
518 if (req_mode
!= set_mode
)
523 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
524 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
530 if (req_mode
!= CCAmode
)
538 return (GET_MODE (SET_SRC (set
)) == set_mode
);
541 /* Return true if every SET in INSN that sets the CC register
542 has source and destination with matching CC modes and that
543 CC mode is at least as constrained as REQ_MODE.
544 If REQ_MODE is VOIDmode, always return false. */
547 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
551 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
552 if (req_mode
== VOIDmode
)
555 if (GET_CODE (PATTERN (insn
)) == SET
)
556 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
558 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
559 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
561 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
562 if (GET_CODE (set
) == SET
)
563 if (!s390_match_ccmode_set (set
, req_mode
))
570 /* If a test-under-mask instruction can be used to implement
571 (compare (and ... OP1) OP2), return the CC mode required
572 to do that. Otherwise, return VOIDmode.
573 MIXED is true if the instruction can distinguish between
574 CC1 and CC2 for mixed selected bits (TMxx), it is false
575 if the instruction cannot (TM). */
578 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
582 /* ??? Fixme: should work on CONST_DOUBLE as well. */
583 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
586 /* Selected bits all zero: CC0.
587 e.g.: int a; if ((a & (16 + 128)) == 0) */
588 if (INTVAL (op2
) == 0)
591 /* Selected bits all one: CC3.
592 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
593 if (INTVAL (op2
) == INTVAL (op1
))
596 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
598 if ((a & (16 + 128)) == 16) -> CCT1
599 if ((a & (16 + 128)) == 128) -> CCT2 */
602 bit1
= exact_log2 (INTVAL (op2
));
603 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
604 if (bit0
!= -1 && bit1
!= -1)
605 return bit0
> bit1
? CCT1mode
: CCT2mode
;
611 /* Given a comparison code OP (EQ, NE, etc.) and the operands
612 OP0 and OP1 of a COMPARE, return the mode to be used for the
616 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
622 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
623 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
625 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
626 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
628 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
629 || GET_CODE (op1
) == NEG
)
630 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
633 if (GET_CODE (op0
) == AND
)
635 /* Check whether we can potentially do it via TM. */
636 enum machine_mode ccmode
;
637 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
638 if (ccmode
!= VOIDmode
)
640 /* Relax CCTmode to CCZmode to allow fall-back to AND
641 if that turns out to be beneficial. */
642 return ccmode
== CCTmode
? CCZmode
: ccmode
;
646 if (register_operand (op0
, HImode
)
647 && GET_CODE (op1
) == CONST_INT
648 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
650 if (register_operand (op0
, QImode
)
651 && GET_CODE (op1
) == CONST_INT
652 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
661 /* The only overflow condition of NEG and ABS happens when
662 -INT_MAX is used as parameter, which stays negative. So
663 we have an overflow from a positive value to a negative.
664 Using CCAP mode the resulting cc can be used for comparisons. */
665 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
666 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
669 /* If constants are involved in an add instruction it is possible to use
670 the resulting cc for comparisons with zero. Knowing the sign of the
671 constant the overflow behavior gets predictable. e.g.:
672 int a, b; if ((b = a + c) > 0)
673 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
674 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
675 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
677 if (INTVAL (XEXP((op0
), 1)) < 0)
691 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
692 && GET_CODE (op1
) != CONST_INT
)
698 if (GET_CODE (op0
) == PLUS
699 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
702 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
703 && GET_CODE (op1
) != CONST_INT
)
709 if (GET_CODE (op0
) == MINUS
710 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
713 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
714 && GET_CODE (op1
) != CONST_INT
)
723 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
724 that we can implement more efficiently. */
727 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
729 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
730 if ((*code
== EQ
|| *code
== NE
)
731 && *op1
== const0_rtx
732 && GET_CODE (*op0
) == ZERO_EXTRACT
733 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
734 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
735 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
737 rtx inner
= XEXP (*op0
, 0);
738 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
739 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
740 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
742 if (len
> 0 && len
< modesize
743 && pos
>= 0 && pos
+ len
<= modesize
744 && modesize
<= HOST_BITS_PER_WIDE_INT
)
746 unsigned HOST_WIDE_INT block
;
747 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
748 block
<<= modesize
- pos
- len
;
750 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
751 gen_int_mode (block
, GET_MODE (inner
)));
755 /* Narrow AND of memory against immediate to enable TM. */
756 if ((*code
== EQ
|| *code
== NE
)
757 && *op1
== const0_rtx
758 && GET_CODE (*op0
) == AND
759 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
760 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
762 rtx inner
= XEXP (*op0
, 0);
763 rtx mask
= XEXP (*op0
, 1);
765 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
766 if (GET_CODE (inner
) == SUBREG
767 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
768 && (GET_MODE_SIZE (GET_MODE (inner
))
769 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
771 & GET_MODE_MASK (GET_MODE (inner
))
772 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
774 inner
= SUBREG_REG (inner
);
776 /* Do not change volatile MEMs. */
777 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
779 int part
= s390_single_part (XEXP (*op0
, 1),
780 GET_MODE (inner
), QImode
, 0);
783 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
784 inner
= adjust_address_nv (inner
, QImode
, part
);
785 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
790 /* Narrow comparisons against 0xffff to HImode if possible. */
791 if ((*code
== EQ
|| *code
== NE
)
792 && GET_CODE (*op1
) == CONST_INT
793 && INTVAL (*op1
) == 0xffff
794 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
795 && (nonzero_bits (*op0
, GET_MODE (*op0
))
796 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
798 *op0
= gen_lowpart (HImode
, *op0
);
802 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
803 if (GET_CODE (*op0
) == UNSPEC
804 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
805 && XVECLEN (*op0
, 0) == 1
806 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
807 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
808 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
809 && *op1
== const0_rtx
)
811 enum rtx_code new_code
= UNKNOWN
;
814 case EQ
: new_code
= EQ
; break;
815 case NE
: new_code
= NE
; break;
816 case LT
: new_code
= GTU
; break;
817 case GT
: new_code
= LTU
; break;
818 case LE
: new_code
= GEU
; break;
819 case GE
: new_code
= LEU
; break;
823 if (new_code
!= UNKNOWN
)
825 *op0
= XVECEXP (*op0
, 0, 0);
830 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
831 if (GET_CODE (*op0
) == UNSPEC
832 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
833 && XVECLEN (*op0
, 0) == 1
834 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
835 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
836 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
837 && *op1
== const0_rtx
)
839 enum rtx_code new_code
= UNKNOWN
;
842 case EQ
: new_code
= EQ
; break;
843 case NE
: new_code
= NE
; break;
847 if (new_code
!= UNKNOWN
)
849 *op0
= XVECEXP (*op0
, 0, 0);
854 /* Simplify cascaded EQ, NE with const0_rtx. */
855 if ((*code
== NE
|| *code
== EQ
)
856 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
857 && GET_MODE (*op0
) == SImode
858 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
859 && REG_P (XEXP (*op0
, 0))
860 && XEXP (*op0
, 1) == const0_rtx
861 && *op1
== const0_rtx
)
863 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
864 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
868 *op0
= XEXP (*op0
, 0);
871 /* Prefer register over memory as first operand. */
872 if (MEM_P (*op0
) && REG_P (*op1
))
874 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
875 *code
= swap_condition (*code
);
879 /* Emit a compare instruction suitable to implement the comparison
880 OP0 CODE OP1. Return the correct condition RTL to be placed in
881 the IF_THEN_ELSE of the conditional branch testing the result. */
884 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
886 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
889 /* Do not output a redundant compare instruction if a compare_and_swap
890 pattern already computed the result and the machine modes are compatible. */
891 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
893 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
899 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
900 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
903 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
906 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
908 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
909 conditional branch testing the result. */
912 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
914 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
915 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
918 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
919 unconditional jump, else a conditional jump under condition COND. */
922 s390_emit_jump (rtx target
, rtx cond
)
926 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
928 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
930 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
931 emit_jump_insn (insn
);
934 /* Return branch condition mask to implement a branch
935 specified by CODE. Return -1 for invalid comparisons. */
938 s390_branch_condition_mask (rtx code
)
940 const int CC0
= 1 << 3;
941 const int CC1
= 1 << 2;
942 const int CC2
= 1 << 1;
943 const int CC3
= 1 << 0;
945 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
946 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
947 gcc_assert (XEXP (code
, 1) == const0_rtx
);
949 switch (GET_MODE (XEXP (code
, 0)))
953 switch (GET_CODE (code
))
956 case NE
: return CC1
| CC2
| CC3
;
962 switch (GET_CODE (code
))
965 case NE
: return CC0
| CC2
| CC3
;
971 switch (GET_CODE (code
))
974 case NE
: return CC0
| CC1
| CC3
;
980 switch (GET_CODE (code
))
983 case NE
: return CC0
| CC1
| CC2
;
989 switch (GET_CODE (code
))
991 case EQ
: return CC0
| CC2
;
992 case NE
: return CC1
| CC3
;
998 switch (GET_CODE (code
))
1000 case LTU
: return CC2
| CC3
; /* carry */
1001 case GEU
: return CC0
| CC1
; /* no carry */
1007 switch (GET_CODE (code
))
1009 case GTU
: return CC0
| CC1
; /* borrow */
1010 case LEU
: return CC2
| CC3
; /* no borrow */
1016 switch (GET_CODE (code
))
1018 case EQ
: return CC0
| CC2
;
1019 case NE
: return CC1
| CC3
;
1020 case LTU
: return CC1
;
1021 case GTU
: return CC3
;
1022 case LEU
: return CC1
| CC2
;
1023 case GEU
: return CC2
| CC3
;
1028 switch (GET_CODE (code
))
1030 case EQ
: return CC0
;
1031 case NE
: return CC1
| CC2
| CC3
;
1032 case LTU
: return CC1
;
1033 case GTU
: return CC2
;
1034 case LEU
: return CC0
| CC1
;
1035 case GEU
: return CC0
| CC2
;
1041 switch (GET_CODE (code
))
1043 case EQ
: return CC0
;
1044 case NE
: return CC2
| CC1
| CC3
;
1045 case LTU
: return CC2
;
1046 case GTU
: return CC1
;
1047 case LEU
: return CC0
| CC2
;
1048 case GEU
: return CC0
| CC1
;
1054 switch (GET_CODE (code
))
1056 case EQ
: return CC0
;
1057 case NE
: return CC1
| CC2
| CC3
;
1058 case LT
: return CC1
| CC3
;
1059 case GT
: return CC2
;
1060 case LE
: return CC0
| CC1
| CC3
;
1061 case GE
: return CC0
| CC2
;
1067 switch (GET_CODE (code
))
1069 case EQ
: return CC0
;
1070 case NE
: return CC1
| CC2
| CC3
;
1071 case LT
: return CC1
;
1072 case GT
: return CC2
| CC3
;
1073 case LE
: return CC0
| CC1
;
1074 case GE
: return CC0
| CC2
| CC3
;
1080 switch (GET_CODE (code
))
1082 case EQ
: return CC0
;
1083 case NE
: return CC1
| CC2
| CC3
;
1084 case LT
: return CC1
;
1085 case GT
: return CC2
;
1086 case LE
: return CC0
| CC1
;
1087 case GE
: return CC0
| CC2
;
1088 case UNORDERED
: return CC3
;
1089 case ORDERED
: return CC0
| CC1
| CC2
;
1090 case UNEQ
: return CC0
| CC3
;
1091 case UNLT
: return CC1
| CC3
;
1092 case UNGT
: return CC2
| CC3
;
1093 case UNLE
: return CC0
| CC1
| CC3
;
1094 case UNGE
: return CC0
| CC2
| CC3
;
1095 case LTGT
: return CC1
| CC2
;
1101 switch (GET_CODE (code
))
1103 case EQ
: return CC0
;
1104 case NE
: return CC2
| CC1
| CC3
;
1105 case LT
: return CC2
;
1106 case GT
: return CC1
;
1107 case LE
: return CC0
| CC2
;
1108 case GE
: return CC0
| CC1
;
1109 case UNORDERED
: return CC3
;
1110 case ORDERED
: return CC0
| CC2
| CC1
;
1111 case UNEQ
: return CC0
| CC3
;
1112 case UNLT
: return CC2
| CC3
;
1113 case UNGT
: return CC1
| CC3
;
1114 case UNLE
: return CC0
| CC2
| CC3
;
1115 case UNGE
: return CC0
| CC1
| CC3
;
1116 case LTGT
: return CC2
| CC1
;
1127 /* Return branch condition mask to implement a compare and branch
1128 specified by CODE. Return -1 for invalid comparisons. */
1131 s390_compare_and_branch_condition_mask (rtx code
)
1133 const int CC0
= 1 << 3;
1134 const int CC1
= 1 << 2;
1135 const int CC2
= 1 << 1;
1137 switch (GET_CODE (code
))
1161 /* If INV is false, return assembler mnemonic string to implement
1162 a branch specified by CODE. If INV is true, return mnemonic
1163 for the corresponding inverted branch. */
1166 s390_branch_condition_mnemonic (rtx code
, int inv
)
1170 static const char *const mnemonic
[16] =
1172 NULL
, "o", "h", "nle",
1173 "l", "nhe", "lh", "ne",
1174 "e", "nlh", "he", "nl",
1175 "le", "nh", "no", NULL
1178 if (GET_CODE (XEXP (code
, 0)) == REG
1179 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1180 && XEXP (code
, 1) == const0_rtx
)
1181 mask
= s390_branch_condition_mask (code
);
1183 mask
= s390_compare_and_branch_condition_mask (code
);
1185 gcc_assert (mask
>= 0);
1190 gcc_assert (mask
>= 1 && mask
<= 14);
1192 return mnemonic
[mask
];
1195 /* Return the part of op which has a value different from def.
1196 The size of the part is determined by mode.
1197 Use this function only if you already know that op really
1198 contains such a part. */
1200 unsigned HOST_WIDE_INT
1201 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1203 unsigned HOST_WIDE_INT value
= 0;
1204 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1205 int part_bits
= GET_MODE_BITSIZE (mode
);
1206 unsigned HOST_WIDE_INT part_mask
1207 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1210 for (i
= 0; i
< max_parts
; i
++)
1213 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1215 value
>>= part_bits
;
1217 if ((value
& part_mask
) != (def
& part_mask
))
1218 return value
& part_mask
;
1224 /* If OP is an integer constant of mode MODE with exactly one
1225 part of mode PART_MODE unequal to DEF, return the number of that
1226 part. Otherwise, return -1. */
1229 s390_single_part (rtx op
,
1230 enum machine_mode mode
,
1231 enum machine_mode part_mode
,
1234 unsigned HOST_WIDE_INT value
= 0;
1235 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1236 unsigned HOST_WIDE_INT part_mask
1237 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1240 if (GET_CODE (op
) != CONST_INT
)
1243 for (i
= 0; i
< n_parts
; i
++)
1246 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1248 value
>>= GET_MODE_BITSIZE (part_mode
);
1250 if ((value
& part_mask
) != (def
& part_mask
))
1258 return part
== -1 ? -1 : n_parts
- 1 - part
;
1261 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1262 bits and no other bits are set in IN. POS and LENGTH can be used
1263 to obtain the start position and the length of the bitfield.
1265 POS gives the position of the first bit of the bitfield counting
1266 from the lowest order bit starting with zero. In order to use this
1267 value for S/390 instructions this has to be converted to "bits big
1271 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1272 int *pos
, int *length
)
1277 unsigned HOST_WIDE_INT mask
= 1ULL;
1278 bool contiguous
= false;
1280 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1304 /* Calculate a mask for all bits beyond the contiguous bits. */
1305 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1310 if (tmp_length
+ tmp_pos
- 1 > size
)
1314 *length
= tmp_length
;
1322 /* Check whether we can (and want to) split a double-word
1323 move in mode MODE from SRC to DST into two single-word
1324 moves, moving the subword FIRST_SUBWORD first. */
1327 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1329 /* Floating point registers cannot be split. */
1330 if (FP_REG_P (src
) || FP_REG_P (dst
))
1333 /* We don't need to split if operands are directly accessible. */
1334 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1337 /* Non-offsettable memory references cannot be split. */
1338 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1339 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1342 /* Moving the first subword must not clobber a register
1343 needed to move the second subword. */
1344 if (register_operand (dst
, mode
))
1346 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1347 if (reg_overlap_mentioned_p (subreg
, src
))
1354 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1355 and [MEM2, MEM2 + SIZE] do overlap and false
1359 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1361 rtx addr1
, addr2
, addr_delta
;
1362 HOST_WIDE_INT delta
;
1364 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1370 addr1
= XEXP (mem1
, 0);
1371 addr2
= XEXP (mem2
, 0);
1373 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1375 /* This overlapping check is used by peepholes merging memory block operations.
1376 Overlapping operations would otherwise be recognized by the S/390 hardware
1377 and would fall back to a slower implementation. Allowing overlapping
1378 operations would lead to slow code but not to wrong code. Therefore we are
1379 somewhat optimistic if we cannot prove that the memory blocks are
1381 That's why we return false here although this may accept operations on
1382 overlapping memory areas. */
1383 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1386 delta
= INTVAL (addr_delta
);
1389 || (delta
> 0 && delta
< size
)
1390 || (delta
< 0 && -delta
< size
))
1396 /* Check whether the address of memory reference MEM2 equals exactly
1397 the address of memory reference MEM1 plus DELTA. Return true if
1398 we can prove this to be the case, false otherwise. */
1401 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1403 rtx addr1
, addr2
, addr_delta
;
1405 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1408 addr1
= XEXP (mem1
, 0);
1409 addr2
= XEXP (mem2
, 0);
1411 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1412 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1418 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1421 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1424 enum machine_mode wmode
= mode
;
1425 rtx dst
= operands
[0];
1426 rtx src1
= operands
[1];
1427 rtx src2
= operands
[2];
1430 /* If we cannot handle the operation directly, use a temp register. */
1431 if (!s390_logical_operator_ok_p (operands
))
1432 dst
= gen_reg_rtx (mode
);
1434 /* QImode and HImode patterns make sense only if we have a destination
1435 in memory. Otherwise perform the operation in SImode. */
1436 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1439 /* Widen operands if required. */
1442 if (GET_CODE (dst
) == SUBREG
1443 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1445 else if (REG_P (dst
))
1446 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1448 dst
= gen_reg_rtx (wmode
);
1450 if (GET_CODE (src1
) == SUBREG
1451 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1453 else if (GET_MODE (src1
) != VOIDmode
)
1454 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1456 if (GET_CODE (src2
) == SUBREG
1457 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1459 else if (GET_MODE (src2
) != VOIDmode
)
1460 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1463 /* Emit the instruction. */
1464 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1465 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1466 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1468 /* Fix up the destination if needed. */
1469 if (dst
!= operands
[0])
1470 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1473 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1476 s390_logical_operator_ok_p (rtx
*operands
)
1478 /* If the destination operand is in memory, it needs to coincide
1479 with one of the source operands. After reload, it has to be
1480 the first source operand. */
1481 if (GET_CODE (operands
[0]) == MEM
)
1482 return rtx_equal_p (operands
[0], operands
[1])
1483 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1488 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1489 operand IMMOP to switch from SS to SI type instructions. */
1492 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1494 int def
= code
== AND
? -1 : 0;
1498 gcc_assert (GET_CODE (*memop
) == MEM
);
1499 gcc_assert (!MEM_VOLATILE_P (*memop
));
1501 mask
= s390_extract_part (*immop
, QImode
, def
);
1502 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1503 gcc_assert (part
>= 0);
1505 *memop
= adjust_address (*memop
, QImode
, part
);
1506 *immop
= gen_int_mode (mask
, QImode
);
1510 /* How to allocate a 'struct machine_function'. */
1512 static struct machine_function
*
1513 s390_init_machine_status (void)
1515 return ggc_alloc_cleared_machine_function ();
1518 /* Change optimizations to be performed, depending on the
1519 optimization level. */
1521 static const struct default_options s390_option_optimization_table
[] =
1523 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
1525 /* ??? There are apparently still problems with -fcaller-saves. */
1526 { OPT_LEVELS_ALL
, OPT_fcaller_saves
, NULL
, 0 },
1528 /* Use MVCLE instructions to decrease code size if requested. */
1529 { OPT_LEVELS_SIZE
, OPT_mmvcle
, NULL
, 1 },
1531 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
1534 /* Implement TARGET_OPTION_INIT_STRUCT. */
1537 s390_option_init_struct (struct gcc_options
*opts
)
1539 /* By default, always emit DWARF-2 unwind info. This allows debugging
1540 without maintaining a stack frame back-chain. */
1541 opts
->x_flag_asynchronous_unwind_tables
= 1;
1544 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1545 to the associated processor_type and processor_flags if so. */
1548 s390_handle_arch_option (const char *arg
,
1549 enum processor_type
*type
,
1554 const char *const name
; /* processor name or nickname. */
1555 const enum processor_type processor
;
1556 const int flags
; /* From enum processor_flags. */
1558 const processor_alias_table
[] =
1560 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1561 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1562 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1563 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1564 | PF_LONG_DISPLACEMENT
},
1565 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1566 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1567 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1568 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1569 {"z10", PROCESSOR_2097_Z10
, PF_IEEE_FLOAT
| PF_ZARCH
1570 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
},
1571 {"z196", PROCESSOR_2817_Z196
, PF_IEEE_FLOAT
| PF_ZARCH
1572 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
| PF_Z196
},
1576 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1577 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1579 *type
= processor_alias_table
[i
].processor
;
1580 *flags
= processor_alias_table
[i
].flags
;
1584 *type
= PROCESSOR_max
;
1589 /* Implement TARGET_HANDLE_OPTION. */
1592 s390_handle_option (struct gcc_options
*opts
, struct gcc_options
*opts_set
,
1593 const struct cl_decoded_option
*decoded
,
1594 location_t loc ATTRIBUTE_UNUSED
)
1596 size_t code
= decoded
->opt_index
;
1597 const char *arg
= decoded
->arg
;
1599 gcc_assert (opts
== &global_options
);
1600 gcc_assert (opts_set
== &global_options_set
);
1605 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1607 case OPT_mstack_guard_
:
1608 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1610 if (exact_log2 (s390_stack_guard
) == -1)
1611 error ("stack guard value must be an exact power of 2");
1614 case OPT_mstack_size_
:
1615 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1617 if (exact_log2 (s390_stack_size
) == -1)
1618 error ("stack size must be an exact power of 2");
1622 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1624 case OPT_mwarn_framesize_
:
1625 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1633 s390_option_override (void)
1635 /* Set up function hooks. */
1636 init_machine_status
= s390_init_machine_status
;
1638 /* Architecture mode defaults according to ABI. */
1639 if (!(target_flags_explicit
& MASK_ZARCH
))
1642 target_flags
|= MASK_ZARCH
;
1644 target_flags
&= ~MASK_ZARCH
;
1647 /* Determine processor architectural level. */
1648 if (!s390_arch_string
)
1650 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1651 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1654 /* This check is triggered when the user specified a wrong -march=
1655 string and prevents subsequent error messages from being
1657 if (s390_arch
== PROCESSOR_max
)
1660 /* Determine processor to tune for. */
1661 if (s390_tune
== PROCESSOR_max
)
1663 s390_tune
= s390_arch
;
1664 s390_tune_flags
= s390_arch_flags
;
1667 /* Sanity checks. */
1668 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1669 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1670 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1671 error ("64-bit ABI not supported in ESA/390 mode");
1673 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1675 if (target_flags_explicit
& MASK_HARD_DFP
)
1677 if (!TARGET_CPU_DFP
)
1678 error ("hardware decimal floating point instructions"
1679 " not available on %s", s390_arch_string
);
1681 error ("hardware decimal floating point instructions"
1682 " not available in ESA/390 mode");
1685 target_flags
&= ~MASK_HARD_DFP
;
1688 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1690 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1691 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1693 target_flags
&= ~MASK_HARD_DFP
;
1696 /* Set processor cost function. */
1699 case PROCESSOR_2084_Z990
:
1700 s390_cost
= &z990_cost
;
1702 case PROCESSOR_2094_Z9_109
:
1703 s390_cost
= &z9_109_cost
;
1705 case PROCESSOR_2097_Z10
:
1706 s390_cost
= &z10_cost
;
1707 case PROCESSOR_2817_Z196
:
1708 s390_cost
= &z196_cost
;
1711 s390_cost
= &z900_cost
;
1714 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1715 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1718 if (s390_stack_size
)
1720 if (s390_stack_guard
>= s390_stack_size
)
1721 error ("stack size must be greater than the stack guard value");
1722 else if (s390_stack_size
> 1 << 16)
1723 error ("stack size must not be greater than 64k");
1725 else if (s390_stack_guard
)
1726 error ("-mstack-guard implies use of -mstack-size");
1728 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1729 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1730 target_flags
|= MASK_LONG_DOUBLE_128
;
1733 if (s390_tune
== PROCESSOR_2097_Z10
1734 || s390_tune
== PROCESSOR_2817_Z196
)
1736 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
1737 global_options
.x_param_values
,
1738 global_options_set
.x_param_values
);
1739 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
1740 global_options
.x_param_values
,
1741 global_options_set
.x_param_values
);
1742 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
1743 global_options
.x_param_values
,
1744 global_options_set
.x_param_values
);
1745 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
1746 global_options
.x_param_values
,
1747 global_options_set
.x_param_values
);
1750 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
1751 global_options
.x_param_values
,
1752 global_options_set
.x_param_values
);
1753 /* values for loop prefetching */
1754 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
1755 global_options
.x_param_values
,
1756 global_options_set
.x_param_values
);
1757 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
1758 global_options
.x_param_values
,
1759 global_options_set
.x_param_values
);
1760 /* s390 has more than 2 levels and the size is much larger. Since
1761 we are always running virtualized assume that we only get a small
1762 part of the caches above l1. */
1763 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
1764 global_options
.x_param_values
,
1765 global_options_set
.x_param_values
);
1766 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
1767 global_options
.x_param_values
,
1768 global_options_set
.x_param_values
);
1769 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
1770 global_options
.x_param_values
,
1771 global_options_set
.x_param_values
);
1773 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1774 requires the arch flags to be evaluated already. Since prefetching
1775 is beneficial on s390, we enable it if available. */
1776 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1777 flag_prefetch_loop_arrays
= 1;
1780 /* Map for smallest class containing reg regno. */
1782 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1783 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1784 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1785 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1786 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1787 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1788 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1789 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1790 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1791 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1792 ACCESS_REGS
, ACCESS_REGS
1795 /* Return attribute type of insn. */
1797 static enum attr_type
1798 s390_safe_attr_type (rtx insn
)
1800 if (recog_memoized (insn
) >= 0)
1801 return get_attr_type (insn
);
1806 /* Return true if DISP is a valid short displacement. */
1809 s390_short_displacement (rtx disp
)
1811 /* No displacement is OK. */
1815 /* Without the long displacement facility we don't need to
1816 distingiush between long and short displacement. */
1817 if (!TARGET_LONG_DISPLACEMENT
)
1820 /* Integer displacement in range. */
1821 if (GET_CODE (disp
) == CONST_INT
)
1822 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1824 /* GOT offset is not OK, the GOT can be large. */
1825 if (GET_CODE (disp
) == CONST
1826 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1827 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1828 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1831 /* All other symbolic constants are literal pool references,
1832 which are OK as the literal pool must be small. */
1833 if (GET_CODE (disp
) == CONST
)
1839 /* Decompose a RTL expression ADDR for a memory address into
1840 its components, returned in OUT.
1842 Returns false if ADDR is not a valid memory address, true
1843 otherwise. If OUT is NULL, don't return the components,
1844 but check for validity only.
1846 Note: Only addresses in canonical form are recognized.
1847 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1848 canonical form so that they will be recognized. */
1851 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1853 HOST_WIDE_INT offset
= 0;
1854 rtx base
= NULL_RTX
;
1855 rtx indx
= NULL_RTX
;
1856 rtx disp
= NULL_RTX
;
1858 bool pointer
= false;
1859 bool base_ptr
= false;
1860 bool indx_ptr
= false;
1861 bool literal_pool
= false;
1863 /* We may need to substitute the literal pool base register into the address
1864 below. However, at this point we do not know which register is going to
1865 be used as base, so we substitute the arg pointer register. This is going
1866 to be treated as holding a pointer below -- it shouldn't be used for any
1868 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1870 /* Decompose address into base + index + displacement. */
1872 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1875 else if (GET_CODE (addr
) == PLUS
)
1877 rtx op0
= XEXP (addr
, 0);
1878 rtx op1
= XEXP (addr
, 1);
1879 enum rtx_code code0
= GET_CODE (op0
);
1880 enum rtx_code code1
= GET_CODE (op1
);
1882 if (code0
== REG
|| code0
== UNSPEC
)
1884 if (code1
== REG
|| code1
== UNSPEC
)
1886 indx
= op0
; /* index + base */
1892 base
= op0
; /* base + displacement */
1897 else if (code0
== PLUS
)
1899 indx
= XEXP (op0
, 0); /* index + base + disp */
1900 base
= XEXP (op0
, 1);
1911 disp
= addr
; /* displacement */
1913 /* Extract integer part of displacement. */
1917 if (GET_CODE (disp
) == CONST_INT
)
1919 offset
= INTVAL (disp
);
1922 else if (GET_CODE (disp
) == CONST
1923 && GET_CODE (XEXP (disp
, 0)) == PLUS
1924 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1926 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1927 disp
= XEXP (XEXP (disp
, 0), 0);
1931 /* Strip off CONST here to avoid special case tests later. */
1932 if (disp
&& GET_CODE (disp
) == CONST
)
1933 disp
= XEXP (disp
, 0);
1935 /* We can convert literal pool addresses to
1936 displacements by basing them off the base register. */
1937 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1939 /* Either base or index must be free to hold the base register. */
1941 base
= fake_pool_base
, literal_pool
= true;
1943 indx
= fake_pool_base
, literal_pool
= true;
1947 /* Mark up the displacement. */
1948 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1949 UNSPEC_LTREL_OFFSET
);
1952 /* Validate base register. */
1955 if (GET_CODE (base
) == UNSPEC
)
1956 switch (XINT (base
, 1))
1960 disp
= gen_rtx_UNSPEC (Pmode
,
1961 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1962 UNSPEC_LTREL_OFFSET
);
1966 base
= XVECEXP (base
, 0, 1);
1969 case UNSPEC_LTREL_BASE
:
1970 if (XVECLEN (base
, 0) == 1)
1971 base
= fake_pool_base
, literal_pool
= true;
1973 base
= XVECEXP (base
, 0, 1);
1981 || (GET_MODE (base
) != SImode
1982 && GET_MODE (base
) != Pmode
))
1985 if (REGNO (base
) == STACK_POINTER_REGNUM
1986 || REGNO (base
) == FRAME_POINTER_REGNUM
1987 || ((reload_completed
|| reload_in_progress
)
1988 && frame_pointer_needed
1989 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1990 || REGNO (base
) == ARG_POINTER_REGNUM
1992 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1993 pointer
= base_ptr
= true;
1995 if ((reload_completed
|| reload_in_progress
)
1996 && base
== cfun
->machine
->base_reg
)
1997 pointer
= base_ptr
= literal_pool
= true;
2000 /* Validate index register. */
2003 if (GET_CODE (indx
) == UNSPEC
)
2004 switch (XINT (indx
, 1))
2008 disp
= gen_rtx_UNSPEC (Pmode
,
2009 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
2010 UNSPEC_LTREL_OFFSET
);
2014 indx
= XVECEXP (indx
, 0, 1);
2017 case UNSPEC_LTREL_BASE
:
2018 if (XVECLEN (indx
, 0) == 1)
2019 indx
= fake_pool_base
, literal_pool
= true;
2021 indx
= XVECEXP (indx
, 0, 1);
2029 || (GET_MODE (indx
) != SImode
2030 && GET_MODE (indx
) != Pmode
))
2033 if (REGNO (indx
) == STACK_POINTER_REGNUM
2034 || REGNO (indx
) == FRAME_POINTER_REGNUM
2035 || ((reload_completed
|| reload_in_progress
)
2036 && frame_pointer_needed
2037 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
2038 || REGNO (indx
) == ARG_POINTER_REGNUM
2040 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
2041 pointer
= indx_ptr
= true;
2043 if ((reload_completed
|| reload_in_progress
)
2044 && indx
== cfun
->machine
->base_reg
)
2045 pointer
= indx_ptr
= literal_pool
= true;
2048 /* Prefer to use pointer as base, not index. */
2049 if (base
&& indx
&& !base_ptr
2050 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
2057 /* Validate displacement. */
2060 /* If virtual registers are involved, the displacement will change later
2061 anyway as the virtual registers get eliminated. This could make a
2062 valid displacement invalid, but it is more likely to make an invalid
2063 displacement valid, because we sometimes access the register save area
2064 via negative offsets to one of those registers.
2065 Thus we don't check the displacement for validity here. If after
2066 elimination the displacement turns out to be invalid after all,
2067 this is fixed up by reload in any case. */
2068 if (base
!= arg_pointer_rtx
2069 && indx
!= arg_pointer_rtx
2070 && base
!= return_address_pointer_rtx
2071 && indx
!= return_address_pointer_rtx
2072 && base
!= frame_pointer_rtx
2073 && indx
!= frame_pointer_rtx
2074 && base
!= virtual_stack_vars_rtx
2075 && indx
!= virtual_stack_vars_rtx
)
2076 if (!DISP_IN_RANGE (offset
))
2081 /* All the special cases are pointers. */
2084 /* In the small-PIC case, the linker converts @GOT
2085 and @GOTNTPOFF offsets to possible displacements. */
2086 if (GET_CODE (disp
) == UNSPEC
2087 && (XINT (disp
, 1) == UNSPEC_GOT
2088 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2094 /* Accept pool label offsets. */
2095 else if (GET_CODE (disp
) == UNSPEC
2096 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2099 /* Accept literal pool references. */
2100 else if (GET_CODE (disp
) == UNSPEC
2101 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2103 /* In case CSE pulled a non literal pool reference out of
2104 the pool we have to reject the address. This is
2105 especially important when loading the GOT pointer on non
2106 zarch CPUs. In this case the literal pool contains an lt
2107 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2108 will most likely exceed the displacement. */
2109 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2110 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
2113 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2116 /* If we have an offset, make sure it does not
2117 exceed the size of the constant pool entry. */
2118 rtx sym
= XVECEXP (disp
, 0, 0);
2119 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2122 orig_disp
= plus_constant (orig_disp
, offset
);
2137 out
->disp
= orig_disp
;
2138 out
->pointer
= pointer
;
2139 out
->literal_pool
= literal_pool
;
2145 /* Decompose a RTL expression OP for a shift count into its components,
2146 and return the base register in BASE and the offset in OFFSET.
2148 Return true if OP is a valid shift count, false if not. */
2151 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2153 HOST_WIDE_INT off
= 0;
2155 /* We can have an integer constant, an address register,
2156 or a sum of the two. */
2157 if (GET_CODE (op
) == CONST_INT
)
2162 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2164 off
= INTVAL (XEXP (op
, 1));
2167 while (op
&& GET_CODE (op
) == SUBREG
)
2168 op
= SUBREG_REG (op
);
2170 if (op
&& GET_CODE (op
) != REG
)
2182 /* Return true if CODE is a valid address without index. */
2185 s390_legitimate_address_without_index_p (rtx op
)
2187 struct s390_address addr
;
2189 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2198 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2199 and return these parts in SYMREF and ADDEND. You can pass NULL in
2200 SYMREF and/or ADDEND if you are not interested in these values.
2201 Literal pool references are *not* considered symbol references. */
2204 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2206 HOST_WIDE_INT tmpaddend
= 0;
2208 if (GET_CODE (addr
) == CONST
)
2209 addr
= XEXP (addr
, 0);
2211 if (GET_CODE (addr
) == PLUS
)
2213 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2214 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2215 && CONST_INT_P (XEXP (addr
, 1)))
2217 tmpaddend
= INTVAL (XEXP (addr
, 1));
2218 addr
= XEXP (addr
, 0);
2224 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2230 *addend
= tmpaddend
;
2236 /* Return true if the address in OP is valid for constraint letter C
2237 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2238 pool MEMs should be accepted. Only the Q, R, S, T constraint
2239 letters are allowed for C. */
2242 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2244 struct s390_address addr
;
2245 bool decomposed
= false;
2247 /* This check makes sure that no symbolic address (except literal
2248 pool references) are accepted by the R or T constraints. */
2249 if (s390_symref_operand_p (op
, NULL
, NULL
))
2252 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2255 if (!s390_decompose_address (op
, &addr
))
2257 if (addr
.literal_pool
)
2264 case 'Q': /* no index short displacement */
2265 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2269 if (!s390_short_displacement (addr
.disp
))
2273 case 'R': /* with index short displacement */
2274 if (TARGET_LONG_DISPLACEMENT
)
2276 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2278 if (!s390_short_displacement (addr
.disp
))
2281 /* Any invalid address here will be fixed up by reload,
2282 so accept it for the most generic constraint. */
2285 case 'S': /* no index long displacement */
2286 if (!TARGET_LONG_DISPLACEMENT
)
2288 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2292 if (s390_short_displacement (addr
.disp
))
2296 case 'T': /* with index long displacement */
2297 if (!TARGET_LONG_DISPLACEMENT
)
2299 /* Any invalid address here will be fixed up by reload,
2300 so accept it for the most generic constraint. */
2301 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2302 && s390_short_displacement (addr
.disp
))
2312 /* Evaluates constraint strings described by the regular expression
2313 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2314 the constraint given in STR, or 0 else. */
2317 s390_mem_constraint (const char *str
, rtx op
)
2324 /* Check for offsettable variants of memory constraints. */
2325 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2327 if ((reload_completed
|| reload_in_progress
)
2328 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2330 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2332 /* Check for non-literal-pool variants of memory constraints. */
2335 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2340 if (GET_CODE (op
) != MEM
)
2342 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2344 return (s390_check_qrst_address ('Q', op
, true)
2345 || s390_check_qrst_address ('R', op
, true));
2347 return (s390_check_qrst_address ('S', op
, true)
2348 || s390_check_qrst_address ('T', op
, true));
2350 /* Simply check for the basic form of a shift count. Reload will
2351 take care of making sure we have a proper base register. */
2352 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2356 return s390_check_qrst_address (str
[1], op
, true);
2364 /* Evaluates constraint strings starting with letter O. Input
2365 parameter C is the second letter following the "O" in the constraint
2366 string. Returns 1 if VALUE meets the respective constraint and 0
2370 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2378 return trunc_int_for_mode (value
, SImode
) == value
;
2382 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2385 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2393 /* Evaluates constraint strings starting with letter N. Parameter STR
2394 contains the letters following letter "N" in the constraint string.
2395 Returns true if VALUE matches the constraint. */
2398 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2400 enum machine_mode mode
, part_mode
;
2402 int part
, part_goal
;
2408 part_goal
= str
[0] - '0';
2452 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2455 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2458 if (part_goal
!= -1 && part_goal
!= part
)
2465 /* Returns true if the input parameter VALUE is a float zero. */
2468 s390_float_const_zero_p (rtx value
)
2470 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2471 && value
== CONST0_RTX (GET_MODE (value
)));
2474 /* Implement TARGET_REGISTER_MOVE_COST. */
2477 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2478 reg_class_t from
, reg_class_t to
)
2480 /* On s390, copy between fprs and gprs is expensive. */
2481 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
2482 && reg_classes_intersect_p (to
, FP_REGS
))
2483 || (reg_classes_intersect_p (from
, FP_REGS
)
2484 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
2490 /* Implement TARGET_MEMORY_MOVE_COST. */
2493 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2494 reg_class_t rclass ATTRIBUTE_UNUSED
,
2495 bool in ATTRIBUTE_UNUSED
)
2500 /* Compute a (partial) cost for rtx X. Return true if the complete
2501 cost has been computed, and false if subexpressions should be
2502 scanned. In either case, *TOTAL contains the cost result.
2503 CODE contains GET_CODE (x), OUTER_CODE contains the code
2504 of the superexpression of x. */
2507 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2508 bool speed ATTRIBUTE_UNUSED
)
2531 *total
= COSTS_N_INSNS (1);
2536 *total
= COSTS_N_INSNS (1);
2540 switch (GET_MODE (x
))
2544 rtx left
= XEXP (x
, 0);
2545 rtx right
= XEXP (x
, 1);
2546 if (GET_CODE (right
) == CONST_INT
2547 && CONST_OK_FOR_K (INTVAL (right
)))
2548 *total
= s390_cost
->mhi
;
2549 else if (GET_CODE (left
) == SIGN_EXTEND
)
2550 *total
= s390_cost
->mh
;
2552 *total
= s390_cost
->ms
; /* msr, ms, msy */
2557 rtx left
= XEXP (x
, 0);
2558 rtx right
= XEXP (x
, 1);
2561 if (GET_CODE (right
) == CONST_INT
2562 && CONST_OK_FOR_K (INTVAL (right
)))
2563 *total
= s390_cost
->mghi
;
2564 else if (GET_CODE (left
) == SIGN_EXTEND
)
2565 *total
= s390_cost
->msgf
;
2567 *total
= s390_cost
->msg
; /* msgr, msg */
2569 else /* TARGET_31BIT */
2571 if (GET_CODE (left
) == SIGN_EXTEND
2572 && GET_CODE (right
) == SIGN_EXTEND
)
2573 /* mulsidi case: mr, m */
2574 *total
= s390_cost
->m
;
2575 else if (GET_CODE (left
) == ZERO_EXTEND
2576 && GET_CODE (right
) == ZERO_EXTEND
2577 && TARGET_CPU_ZARCH
)
2578 /* umulsidi case: ml, mlr */
2579 *total
= s390_cost
->ml
;
2581 /* Complex calculation is required. */
2582 *total
= COSTS_N_INSNS (40);
2588 *total
= s390_cost
->mult_df
;
2591 *total
= s390_cost
->mxbr
;
2599 switch (GET_MODE (x
))
2602 *total
= s390_cost
->madbr
;
2605 *total
= s390_cost
->maebr
;
2610 /* Negate in the third argument is free: FMSUB. */
2611 if (GET_CODE (XEXP (x
, 2)) == NEG
)
2613 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, speed
)
2614 + rtx_cost (XEXP (x
, 1), FMA
, speed
)
2615 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, speed
));
2622 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2623 *total
= s390_cost
->dlgr
;
2624 else if (GET_MODE (x
) == DImode
)
2626 rtx right
= XEXP (x
, 1);
2627 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2628 *total
= s390_cost
->dlr
;
2629 else /* 64 by 64 bit division */
2630 *total
= s390_cost
->dlgr
;
2632 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2633 *total
= s390_cost
->dlr
;
2638 if (GET_MODE (x
) == DImode
)
2640 rtx right
= XEXP (x
, 1);
2641 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2643 *total
= s390_cost
->dsgfr
;
2645 *total
= s390_cost
->dr
;
2646 else /* 64 by 64 bit division */
2647 *total
= s390_cost
->dsgr
;
2649 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2650 *total
= s390_cost
->dlr
;
2651 else if (GET_MODE (x
) == SFmode
)
2653 *total
= s390_cost
->debr
;
2655 else if (GET_MODE (x
) == DFmode
)
2657 *total
= s390_cost
->ddbr
;
2659 else if (GET_MODE (x
) == TFmode
)
2661 *total
= s390_cost
->dxbr
;
2666 if (GET_MODE (x
) == SFmode
)
2667 *total
= s390_cost
->sqebr
;
2668 else if (GET_MODE (x
) == DFmode
)
2669 *total
= s390_cost
->sqdbr
;
2671 *total
= s390_cost
->sqxbr
;
2676 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2677 || outer_code
== PLUS
|| outer_code
== MINUS
2678 || outer_code
== COMPARE
)
2683 *total
= COSTS_N_INSNS (1);
2684 if (GET_CODE (XEXP (x
, 0)) == AND
2685 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2686 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2688 rtx op0
= XEXP (XEXP (x
, 0), 0);
2689 rtx op1
= XEXP (XEXP (x
, 0), 1);
2690 rtx op2
= XEXP (x
, 1);
2692 if (memory_operand (op0
, GET_MODE (op0
))
2693 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2695 if (register_operand (op0
, GET_MODE (op0
))
2696 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2706 /* Return the cost of an address rtx ADDR. */
2709 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2711 struct s390_address ad
;
2712 if (!s390_decompose_address (addr
, &ad
))
2715 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2718 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2719 otherwise return 0. */
2722 tls_symbolic_operand (rtx op
)
2724 if (GET_CODE (op
) != SYMBOL_REF
)
2726 return SYMBOL_REF_TLS_MODEL (op
);
2729 /* Split DImode access register reference REG (on 64-bit) into its constituent
2730 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2731 gen_highpart cannot be used as they assume all registers are word-sized,
2732 while our access registers have only half that size. */
2735 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2737 gcc_assert (TARGET_64BIT
);
2738 gcc_assert (ACCESS_REG_P (reg
));
2739 gcc_assert (GET_MODE (reg
) == DImode
);
2740 gcc_assert (!(REGNO (reg
) & 1));
2742 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2743 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2746 /* Return true if OP contains a symbol reference */
2749 symbolic_reference_mentioned_p (rtx op
)
2754 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2757 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2758 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2764 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2765 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2769 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2776 /* Return true if OP contains a reference to a thread-local symbol. */
2779 tls_symbolic_reference_mentioned_p (rtx op
)
2784 if (GET_CODE (op
) == SYMBOL_REF
)
2785 return tls_symbolic_operand (op
);
2787 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2788 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2794 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2795 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2799 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2807 /* Return true if OP is a legitimate general operand when
2808 generating PIC code. It is given that flag_pic is on
2809 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2812 legitimate_pic_operand_p (rtx op
)
2814 /* Accept all non-symbolic constants. */
2815 if (!SYMBOLIC_CONST (op
))
2818 /* Reject everything else; must be handled
2819 via emit_symbolic_move. */
2823 /* Returns true if the constant value OP is a legitimate general operand.
2824 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2827 legitimate_constant_p (rtx op
)
2829 /* Accept all non-symbolic constants. */
2830 if (!SYMBOLIC_CONST (op
))
2833 /* Accept immediate LARL operands. */
2834 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2837 /* Thread-local symbols are never legal constants. This is
2838 so that emit_call knows that computing such addresses
2839 might require a function call. */
2840 if (TLS_SYMBOLIC_CONST (op
))
2843 /* In the PIC case, symbolic constants must *not* be
2844 forced into the literal pool. We accept them here,
2845 so that they will be handled by emit_symbolic_move. */
2849 /* All remaining non-PIC symbolic constants are
2850 forced into the literal pool. */
2854 /* Determine if it's legal to put X into the constant pool. This
2855 is not possible if X contains the address of a symbol that is
2856 not constant (TLS) or not known at final link time (PIC). */
2859 s390_cannot_force_const_mem (rtx x
)
2861 switch (GET_CODE (x
))
2865 /* Accept all non-symbolic constants. */
2869 /* Labels are OK iff we are non-PIC. */
2870 return flag_pic
!= 0;
2873 /* 'Naked' TLS symbol references are never OK,
2874 non-TLS symbols are OK iff we are non-PIC. */
2875 if (tls_symbolic_operand (x
))
2878 return flag_pic
!= 0;
2881 return s390_cannot_force_const_mem (XEXP (x
, 0));
2884 return s390_cannot_force_const_mem (XEXP (x
, 0))
2885 || s390_cannot_force_const_mem (XEXP (x
, 1));
2888 switch (XINT (x
, 1))
2890 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2891 case UNSPEC_LTREL_OFFSET
:
2899 case UNSPEC_GOTNTPOFF
:
2900 case UNSPEC_INDNTPOFF
:
2903 /* If the literal pool shares the code section, be put
2904 execute template placeholders into the pool as well. */
2906 return TARGET_CPU_ZARCH
;
2918 /* Returns true if the constant value OP is a legitimate general
2919 operand during and after reload. The difference to
2920 legitimate_constant_p is that this function will not accept
2921 a constant that would need to be forced to the literal pool
2922 before it can be used as operand.
2923 This function accepts all constants which can be loaded directly
2927 legitimate_reload_constant_p (rtx op
)
2929 /* Accept la(y) operands. */
2930 if (GET_CODE (op
) == CONST_INT
2931 && DISP_IN_RANGE (INTVAL (op
)))
2934 /* Accept l(g)hi/l(g)fi operands. */
2935 if (GET_CODE (op
) == CONST_INT
2936 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2939 /* Accept lliXX operands. */
2941 && GET_CODE (op
) == CONST_INT
2942 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2943 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2947 && GET_CODE (op
) == CONST_INT
2948 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2949 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2952 /* Accept larl operands. */
2953 if (TARGET_CPU_ZARCH
2954 && larl_operand (op
, VOIDmode
))
2957 /* Accept floating-point zero operands that fit into a single GPR. */
2958 if (GET_CODE (op
) == CONST_DOUBLE
2959 && s390_float_const_zero_p (op
)
2960 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2963 /* Accept double-word operands that can be split. */
2964 if (GET_CODE (op
) == CONST_INT
2965 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2967 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2968 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2969 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2970 return legitimate_reload_constant_p (hi
)
2971 && legitimate_reload_constant_p (lo
);
2974 /* Everything else cannot be handled without reload. */
2978 /* Returns true if the constant value OP is a legitimate fp operand
2979 during and after reload.
2980 This function accepts all constants which can be loaded directly
2984 legitimate_reload_fp_constant_p (rtx op
)
2986 /* Accept floating-point zero operands if the load zero instruction
2989 && GET_CODE (op
) == CONST_DOUBLE
2990 && s390_float_const_zero_p (op
))
2996 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2997 return the class of reg to actually use. */
3000 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
3002 switch (GET_CODE (op
))
3004 /* Constants we cannot reload into general registers
3005 must be forced into the literal pool. */
3008 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
3009 && legitimate_reload_constant_p (op
))
3010 return GENERAL_REGS
;
3011 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
3012 && legitimate_reload_constant_p (op
))
3014 else if (reg_class_subset_p (FP_REGS
, rclass
)
3015 && legitimate_reload_fp_constant_p (op
))
3019 /* If a symbolic constant or a PLUS is reloaded,
3020 it is most likely being used as an address, so
3021 prefer ADDR_REGS. If 'class' is not a superset
3022 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
3027 if (reg_class_subset_p (ADDR_REGS
, rclass
))
3039 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
3040 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3044 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
3046 HOST_WIDE_INT addend
;
3049 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
3052 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
3053 && !(addend
& (alignment
- 1)));
3056 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3057 operand SCRATCH is used to reload the even part of the address and
3061 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
3063 HOST_WIDE_INT addend
;
3066 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
3070 /* Easy case. The addend is even so larl will do fine. */
3071 emit_move_insn (reg
, addr
);
3074 /* We can leave the scratch register untouched if the target
3075 register is a valid base register. */
3076 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
3077 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
3080 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
3081 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
3084 emit_move_insn (scratch
,
3085 gen_rtx_CONST (Pmode
,
3086 gen_rtx_PLUS (Pmode
, symref
,
3087 GEN_INT (addend
- 1))));
3089 emit_move_insn (scratch
, symref
);
3091 /* Increment the address using la in order to avoid clobbering cc. */
3092 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
3096 /* Generate what is necessary to move between REG and MEM using
3097 SCRATCH. The direction is given by TOMEM. */
3100 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3102 /* Reload might have pulled a constant out of the literal pool.
3103 Force it back in. */
3104 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3105 || GET_CODE (mem
) == CONST
)
3106 mem
= force_const_mem (GET_MODE (reg
), mem
);
3108 gcc_assert (MEM_P (mem
));
3110 /* For a load from memory we can leave the scratch register
3111 untouched if the target register is a valid base register. */
3113 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3114 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3115 && GET_MODE (reg
) == GET_MODE (scratch
))
3118 /* Load address into scratch register. Since we can't have a
3119 secondary reload for a secondary reload we have to cover the case
3120 where larl would need a secondary reload here as well. */
3121 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3123 /* Now we can use a standard load/store to do the move. */
3125 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3127 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3130 /* Inform reload about cases where moving X with a mode MODE to a register in
3131 RCLASS requires an extra scratch or immediate register. Return the class
3132 needed for the immediate register. */
3135 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3136 enum machine_mode mode
, secondary_reload_info
*sri
)
3138 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3140 /* Intermediate register needed. */
3141 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3142 return GENERAL_REGS
;
3146 /* On z10 several optimizer steps may generate larl operands with
3149 && s390_symref_operand_p (x
, NULL
, NULL
)
3151 && !s390_check_symref_alignment (x
, 2))
3152 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3153 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3155 /* On z10 we need a scratch register when moving QI, TI or floating
3156 point mode values from or to a memory location with a SYMBOL_REF
3157 or if the symref addend of a SI or DI move is not aligned to the
3158 width of the access. */
3160 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3161 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3162 || (!TARGET_ZARCH
&& mode
== DImode
)
3163 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3164 && (!s390_check_symref_alignment (XEXP (x
, 0),
3165 GET_MODE_SIZE (mode
))))))
3167 #define __SECONDARY_RELOAD_CASE(M,m) \
3170 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3171 CODE_FOR_reload##m##di_tomem_z10; \
3173 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3174 CODE_FOR_reload##m##si_tomem_z10; \
3177 switch (GET_MODE (x
))
3179 __SECONDARY_RELOAD_CASE (QI
, qi
);
3180 __SECONDARY_RELOAD_CASE (HI
, hi
);
3181 __SECONDARY_RELOAD_CASE (SI
, si
);
3182 __SECONDARY_RELOAD_CASE (DI
, di
);
3183 __SECONDARY_RELOAD_CASE (TI
, ti
);
3184 __SECONDARY_RELOAD_CASE (SF
, sf
);
3185 __SECONDARY_RELOAD_CASE (DF
, df
);
3186 __SECONDARY_RELOAD_CASE (TF
, tf
);
3187 __SECONDARY_RELOAD_CASE (SD
, sd
);
3188 __SECONDARY_RELOAD_CASE (DD
, dd
);
3189 __SECONDARY_RELOAD_CASE (TD
, td
);
3194 #undef __SECONDARY_RELOAD_CASE
3198 /* We need a scratch register when loading a PLUS expression which
3199 is not a legitimate operand of the LOAD ADDRESS instruction. */
3200 if (in_p
&& s390_plus_operand (x
, mode
))
3201 sri
->icode
= (TARGET_64BIT
?
3202 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3204 /* Performing a multiword move from or to memory we have to make sure the
3205 second chunk in memory is addressable without causing a displacement
3206 overflow. If that would be the case we calculate the address in
3207 a scratch register. */
3209 && GET_CODE (XEXP (x
, 0)) == PLUS
3210 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3211 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3212 + GET_MODE_SIZE (mode
) - 1))
3214 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3215 in a s_operand address since we may fallback to lm/stm. So we only
3216 have to care about overflows in the b+i+d case. */
3217 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3218 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3219 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3220 /* For FP_REGS no lm/stm is available so this check is triggered
3221 for displacement overflows in b+i+d and b+d like addresses. */
3222 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3223 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3226 sri
->icode
= (TARGET_64BIT
?
3227 CODE_FOR_reloaddi_nonoffmem_in
:
3228 CODE_FOR_reloadsi_nonoffmem_in
);
3230 sri
->icode
= (TARGET_64BIT
?
3231 CODE_FOR_reloaddi_nonoffmem_out
:
3232 CODE_FOR_reloadsi_nonoffmem_out
);
3236 /* A scratch address register is needed when a symbolic constant is
3237 copied to r0 compiling with -fPIC. In other cases the target
3238 register might be used as temporary (see legitimize_pic_address). */
3239 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3240 sri
->icode
= (TARGET_64BIT
?
3241 CODE_FOR_reloaddi_PIC_addr
:
3242 CODE_FOR_reloadsi_PIC_addr
);
3244 /* Either scratch or no register needed. */
3248 /* Generate code to load SRC, which is PLUS that is not a
3249 legitimate operand for the LA instruction, into TARGET.
3250 SCRATCH may be used as scratch register. */
3253 s390_expand_plus_operand (rtx target
, rtx src
,
3257 struct s390_address ad
;
3259 /* src must be a PLUS; get its two operands. */
3260 gcc_assert (GET_CODE (src
) == PLUS
);
3261 gcc_assert (GET_MODE (src
) == Pmode
);
3263 /* Check if any of the two operands is already scheduled
3264 for replacement by reload. This can happen e.g. when
3265 float registers occur in an address. */
3266 sum1
= find_replacement (&XEXP (src
, 0));
3267 sum2
= find_replacement (&XEXP (src
, 1));
3268 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3270 /* If the address is already strictly valid, there's nothing to do. */
3271 if (!s390_decompose_address (src
, &ad
)
3272 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3273 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3275 /* Otherwise, one of the operands cannot be an address register;
3276 we reload its value into the scratch register. */
3277 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3279 emit_move_insn (scratch
, sum1
);
3282 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3284 emit_move_insn (scratch
, sum2
);
3288 /* According to the way these invalid addresses are generated
3289 in reload.c, it should never happen (at least on s390) that
3290 *neither* of the PLUS components, after find_replacements
3291 was applied, is an address register. */
3292 if (sum1
== scratch
&& sum2
== scratch
)
3298 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3301 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3302 is only ever performed on addresses, so we can mark the
3303 sum as legitimate for LA in any case. */
3304 s390_load_address (target
, src
);
3308 /* Return true if ADDR is a valid memory address.
3309 STRICT specifies whether strict register checking applies. */
3312 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3314 struct s390_address ad
;
3317 && larl_operand (addr
, VOIDmode
)
3318 && (mode
== VOIDmode
3319 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3322 if (!s390_decompose_address (addr
, &ad
))
3327 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3330 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3336 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3337 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3341 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3342 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3348 /* Return true if OP is a valid operand for the LA instruction.
3349 In 31-bit, we need to prove that the result is used as an
3350 address, as LA performs only a 31-bit addition. */
3353 legitimate_la_operand_p (rtx op
)
3355 struct s390_address addr
;
3356 if (!s390_decompose_address (op
, &addr
))
3359 return (TARGET_64BIT
|| addr
.pointer
);
3362 /* Return true if it is valid *and* preferable to use LA to
3363 compute the sum of OP1 and OP2. */
3366 preferred_la_operand_p (rtx op1
, rtx op2
)
3368 struct s390_address addr
;
3370 if (op2
!= const0_rtx
)
3371 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3373 if (!s390_decompose_address (op1
, &addr
))
3375 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3377 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3380 /* Avoid LA instructions with index register on z196; it is
3381 preferable to use regular add instructions when possible. */
3382 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3385 if (!TARGET_64BIT
&& !addr
.pointer
)
3391 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3392 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3398 /* Emit a forced load-address operation to load SRC into DST.
3399 This will use the LOAD ADDRESS instruction even in situations
3400 where legitimate_la_operand_p (SRC) returns false. */
3403 s390_load_address (rtx dst
, rtx src
)
3406 emit_move_insn (dst
, src
);
3408 emit_insn (gen_force_la_31 (dst
, src
));
3411 /* Return a legitimate reference for ORIG (an address) using the
3412 register REG. If REG is 0, a new pseudo is generated.
3414 There are two types of references that must be handled:
3416 1. Global data references must load the address from the GOT, via
3417 the PIC reg. An insn is emitted to do this load, and the reg is
3420 2. Static data references, constant pool addresses, and code labels
3421 compute the address as an offset from the GOT, whose base is in
3422 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3423 differentiate them from global data objects. The returned
3424 address is the PIC reg + an unspec constant.
3426 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3427 reg also appears in the address. */
3430 legitimize_pic_address (rtx orig
, rtx reg
)
3436 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3438 if (GET_CODE (addr
) == LABEL_REF
3439 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3441 /* This is a local symbol. */
3442 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3444 /* Access local symbols PC-relative via LARL.
3445 This is the same as in the non-PIC case, so it is
3446 handled automatically ... */
3450 /* Access local symbols relative to the GOT. */
3452 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3454 if (reload_in_progress
|| reload_completed
)
3455 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3457 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3458 addr
= gen_rtx_CONST (Pmode
, addr
);
3459 addr
= force_const_mem (Pmode
, addr
);
3460 emit_move_insn (temp
, addr
);
3462 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3465 s390_load_address (reg
, new_rtx
);
3470 else if (GET_CODE (addr
) == SYMBOL_REF
)
3473 reg
= gen_reg_rtx (Pmode
);
3477 /* Assume GOT offset < 4k. This is handled the same way
3478 in both 31- and 64-bit code (@GOT). */
3480 if (reload_in_progress
|| reload_completed
)
3481 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3483 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3484 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3485 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3486 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3487 emit_move_insn (reg
, new_rtx
);
3490 else if (TARGET_CPU_ZARCH
)
3492 /* If the GOT offset might be >= 4k, we determine the position
3493 of the GOT entry via a PC-relative LARL (@GOTENT). */
3495 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3497 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3498 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3500 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3501 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3502 emit_move_insn (temp
, new_rtx
);
3504 new_rtx
= gen_const_mem (Pmode
, temp
);
3505 emit_move_insn (reg
, new_rtx
);
3510 /* If the GOT offset might be >= 4k, we have to load it
3511 from the literal pool (@GOT). */
3513 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3515 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3516 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3518 if (reload_in_progress
|| reload_completed
)
3519 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3521 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3522 addr
= gen_rtx_CONST (Pmode
, addr
);
3523 addr
= force_const_mem (Pmode
, addr
);
3524 emit_move_insn (temp
, addr
);
3526 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3527 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3528 emit_move_insn (reg
, new_rtx
);
3534 if (GET_CODE (addr
) == CONST
)
3536 addr
= XEXP (addr
, 0);
3537 if (GET_CODE (addr
) == UNSPEC
)
3539 gcc_assert (XVECLEN (addr
, 0) == 1);
3540 switch (XINT (addr
, 1))
3542 /* If someone moved a GOT-relative UNSPEC
3543 out of the literal pool, force them back in. */
3546 new_rtx
= force_const_mem (Pmode
, orig
);
3549 /* @GOT is OK as is if small. */
3552 new_rtx
= force_const_mem (Pmode
, orig
);
3555 /* @GOTENT is OK as is. */
3559 /* @PLT is OK as is on 64-bit, must be converted to
3560 GOT-relative @PLTOFF on 31-bit. */
3562 if (!TARGET_CPU_ZARCH
)
3564 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3566 if (reload_in_progress
|| reload_completed
)
3567 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3569 addr
= XVECEXP (addr
, 0, 0);
3570 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3572 addr
= gen_rtx_CONST (Pmode
, addr
);
3573 addr
= force_const_mem (Pmode
, addr
);
3574 emit_move_insn (temp
, addr
);
3576 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3579 s390_load_address (reg
, new_rtx
);
3585 /* Everything else cannot happen. */
3591 gcc_assert (GET_CODE (addr
) == PLUS
);
3593 if (GET_CODE (addr
) == PLUS
)
3595 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3597 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3598 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3600 /* Check first to see if this is a constant offset
3601 from a local symbol reference. */
3602 if ((GET_CODE (op0
) == LABEL_REF
3603 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3604 && GET_CODE (op1
) == CONST_INT
)
3606 if (TARGET_CPU_ZARCH
3607 && larl_operand (op0
, VOIDmode
)
3608 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3609 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3611 if (INTVAL (op1
) & 1)
3613 /* LARL can't handle odd offsets, so emit a
3614 pair of LARL and LA. */
3615 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3617 if (!DISP_IN_RANGE (INTVAL (op1
)))
3619 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3620 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3621 op0
= gen_rtx_CONST (Pmode
, op0
);
3625 emit_move_insn (temp
, op0
);
3626 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3630 s390_load_address (reg
, new_rtx
);
3636 /* If the offset is even, we can just use LARL.
3637 This will happen automatically. */
3642 /* Access local symbols relative to the GOT. */
3644 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3646 if (reload_in_progress
|| reload_completed
)
3647 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3649 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3651 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3652 addr
= gen_rtx_CONST (Pmode
, addr
);
3653 addr
= force_const_mem (Pmode
, addr
);
3654 emit_move_insn (temp
, addr
);
3656 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3659 s390_load_address (reg
, new_rtx
);
3665 /* Now, check whether it is a GOT relative symbol plus offset
3666 that was pulled out of the literal pool. Force it back in. */
3668 else if (GET_CODE (op0
) == UNSPEC
3669 && GET_CODE (op1
) == CONST_INT
3670 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3672 gcc_assert (XVECLEN (op0
, 0) == 1);
3674 new_rtx
= force_const_mem (Pmode
, orig
);
3677 /* Otherwise, compute the sum. */
3680 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3681 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3682 base
== reg
? NULL_RTX
: reg
);
3683 if (GET_CODE (new_rtx
) == CONST_INT
)
3684 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3687 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3689 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3690 new_rtx
= XEXP (new_rtx
, 1);
3692 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3695 if (GET_CODE (new_rtx
) == CONST
)
3696 new_rtx
= XEXP (new_rtx
, 0);
3697 new_rtx
= force_operand (new_rtx
, 0);
3704 /* Load the thread pointer into a register. */
3707 s390_get_thread_pointer (void)
3709 rtx tp
= gen_reg_rtx (Pmode
);
3711 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3712 mark_reg_pointer (tp
, BITS_PER_WORD
);
3717 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3718 in s390_tls_symbol which always refers to __tls_get_offset.
3719 The returned offset is written to RESULT_REG and an USE rtx is
3720 generated for TLS_CALL. */
3722 static GTY(()) rtx s390_tls_symbol
;
3725 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3729 gcc_assert (flag_pic
);
3731 if (!s390_tls_symbol
)
3732 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3734 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3735 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3737 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3738 RTL_CONST_CALL_P (insn
) = 1;
3741 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3742 this (thread-local) address. REG may be used as temporary. */
3745 legitimize_tls_address (rtx addr
, rtx reg
)
3747 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3749 if (GET_CODE (addr
) == SYMBOL_REF
)
3750 switch (tls_symbolic_operand (addr
))
3752 case TLS_MODEL_GLOBAL_DYNAMIC
:
3754 r2
= gen_rtx_REG (Pmode
, 2);
3755 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3756 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3757 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3758 emit_move_insn (r2
, new_rtx
);
3759 s390_emit_tls_call_insn (r2
, tls_call
);
3760 insn
= get_insns ();
3763 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3764 temp
= gen_reg_rtx (Pmode
);
3765 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3767 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3770 s390_load_address (reg
, new_rtx
);
3775 case TLS_MODEL_LOCAL_DYNAMIC
:
3777 r2
= gen_rtx_REG (Pmode
, 2);
3778 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3779 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3780 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3781 emit_move_insn (r2
, new_rtx
);
3782 s390_emit_tls_call_insn (r2
, tls_call
);
3783 insn
= get_insns ();
3786 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3787 temp
= gen_reg_rtx (Pmode
);
3788 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3790 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3791 base
= gen_reg_rtx (Pmode
);
3792 s390_load_address (base
, new_rtx
);
3794 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3795 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3796 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3797 temp
= gen_reg_rtx (Pmode
);
3798 emit_move_insn (temp
, new_rtx
);
3800 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3803 s390_load_address (reg
, new_rtx
);
3808 case TLS_MODEL_INITIAL_EXEC
:
3811 /* Assume GOT offset < 4k. This is handled the same way
3812 in both 31- and 64-bit code. */
3814 if (reload_in_progress
|| reload_completed
)
3815 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3817 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3818 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3819 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3820 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3821 temp
= gen_reg_rtx (Pmode
);
3822 emit_move_insn (temp
, new_rtx
);
3824 else if (TARGET_CPU_ZARCH
)
3826 /* If the GOT offset might be >= 4k, we determine the position
3827 of the GOT entry via a PC-relative LARL. */
3829 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3830 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3831 temp
= gen_reg_rtx (Pmode
);
3832 emit_move_insn (temp
, new_rtx
);
3834 new_rtx
= gen_const_mem (Pmode
, temp
);
3835 temp
= gen_reg_rtx (Pmode
);
3836 emit_move_insn (temp
, new_rtx
);
3840 /* If the GOT offset might be >= 4k, we have to load it
3841 from the literal pool. */
3843 if (reload_in_progress
|| reload_completed
)
3844 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3846 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3847 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3848 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3849 temp
= gen_reg_rtx (Pmode
);
3850 emit_move_insn (temp
, new_rtx
);
3852 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3853 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3855 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3856 temp
= gen_reg_rtx (Pmode
);
3857 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3861 /* In position-dependent code, load the absolute address of
3862 the GOT entry from the literal pool. */
3864 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3865 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3866 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3867 temp
= gen_reg_rtx (Pmode
);
3868 emit_move_insn (temp
, new_rtx
);
3871 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3872 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3873 temp
= gen_reg_rtx (Pmode
);
3874 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3877 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3880 s390_load_address (reg
, new_rtx
);
3885 case TLS_MODEL_LOCAL_EXEC
:
3886 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3887 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3888 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3889 temp
= gen_reg_rtx (Pmode
);
3890 emit_move_insn (temp
, new_rtx
);
3892 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3895 s390_load_address (reg
, new_rtx
);
3904 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3906 switch (XINT (XEXP (addr
, 0), 1))
3908 case UNSPEC_INDNTPOFF
:
3909 gcc_assert (TARGET_CPU_ZARCH
);
3918 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3919 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3921 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3922 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3923 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3925 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3926 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3927 new_rtx
= force_operand (new_rtx
, 0);
3931 gcc_unreachable (); /* for now ... */
3936 /* Emit insns making the address in operands[1] valid for a standard
3937 move to operands[0]. operands[1] is replaced by an address which
3938 should be used instead of the former RTX to emit the move
3942 emit_symbolic_move (rtx
*operands
)
3944 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3946 if (GET_CODE (operands
[0]) == MEM
)
3947 operands
[1] = force_reg (Pmode
, operands
[1]);
3948 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3949 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3951 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3954 /* Try machine-dependent ways of modifying an illegitimate address X
3955 to be legitimate. If we find one, return the new, valid address.
3957 OLDX is the address as it was before break_out_memory_refs was called.
3958 In some cases it is useful to look at this to decide what needs to be done.
3960 MODE is the mode of the operand pointed to by X.
3962 When -fpic is used, special handling is needed for symbolic references.
3963 See comments by legitimize_pic_address for details. */
3966 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3967 enum machine_mode mode ATTRIBUTE_UNUSED
)
3969 rtx constant_term
= const0_rtx
;
3971 if (TLS_SYMBOLIC_CONST (x
))
3973 x
= legitimize_tls_address (x
, 0);
3975 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3978 else if (GET_CODE (x
) == PLUS
3979 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3980 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3986 if (SYMBOLIC_CONST (x
)
3987 || (GET_CODE (x
) == PLUS
3988 && (SYMBOLIC_CONST (XEXP (x
, 0))
3989 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3990 x
= legitimize_pic_address (x
, 0);
3992 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3996 x
= eliminate_constant_term (x
, &constant_term
);
3998 /* Optimize loading of large displacements by splitting them
3999 into the multiple of 4K and the rest; this allows the
4000 former to be CSE'd if possible.
4002 Don't do this if the displacement is added to a register
4003 pointing into the stack frame, as the offsets will
4004 change later anyway. */
4006 if (GET_CODE (constant_term
) == CONST_INT
4007 && !TARGET_LONG_DISPLACEMENT
4008 && !DISP_IN_RANGE (INTVAL (constant_term
))
4009 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
4011 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
4012 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
4014 rtx temp
= gen_reg_rtx (Pmode
);
4015 rtx val
= force_operand (GEN_INT (upper
), temp
);
4017 emit_move_insn (temp
, val
);
4019 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
4020 constant_term
= GEN_INT (lower
);
4023 if (GET_CODE (x
) == PLUS
)
4025 if (GET_CODE (XEXP (x
, 0)) == REG
)
4027 rtx temp
= gen_reg_rtx (Pmode
);
4028 rtx val
= force_operand (XEXP (x
, 1), temp
);
4030 emit_move_insn (temp
, val
);
4032 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
4035 else if (GET_CODE (XEXP (x
, 1)) == REG
)
4037 rtx temp
= gen_reg_rtx (Pmode
);
4038 rtx val
= force_operand (XEXP (x
, 0), temp
);
4040 emit_move_insn (temp
, val
);
4042 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
4046 if (constant_term
!= const0_rtx
)
4047 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
4052 /* Try a machine-dependent way of reloading an illegitimate address AD
4053 operand. If we find one, push the reload and and return the new address.
4055 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4056 and TYPE is the reload type of the current reload. */
4059 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
4060 int opnum
, int type
)
4062 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
4065 if (GET_CODE (ad
) == PLUS
)
4067 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
4068 XEXP (ad
, 0), XEXP (ad
, 1));
4073 if (GET_CODE (ad
) == PLUS
4074 && GET_CODE (XEXP (ad
, 0)) == REG
4075 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
4076 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
4078 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
4079 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
4080 rtx cst
, tem
, new_rtx
;
4082 cst
= GEN_INT (upper
);
4083 if (!legitimate_reload_constant_p (cst
))
4084 cst
= force_const_mem (Pmode
, cst
);
4086 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
4087 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
4089 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
4090 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4091 opnum
, (enum reload_type
) type
);
4098 /* Emit code to move LEN bytes from DST to SRC. */
4101 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
4103 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4105 if (INTVAL (len
) > 0)
4106 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4109 else if (TARGET_MVCLE
)
4111 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4116 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4117 rtx loop_start_label
= gen_label_rtx ();
4118 rtx loop_end_label
= gen_label_rtx ();
4119 rtx end_label
= gen_label_rtx ();
4120 enum machine_mode mode
;
4122 mode
= GET_MODE (len
);
4123 if (mode
== VOIDmode
)
4126 dst_addr
= gen_reg_rtx (Pmode
);
4127 src_addr
= gen_reg_rtx (Pmode
);
4128 count
= gen_reg_rtx (mode
);
4129 blocks
= gen_reg_rtx (mode
);
4131 convert_move (count
, len
, 1);
4132 emit_cmp_and_jump_insns (count
, const0_rtx
,
4133 EQ
, NULL_RTX
, mode
, 1, end_label
);
4135 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4136 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4137 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4138 src
= change_address (src
, VOIDmode
, src_addr
);
4140 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4143 emit_move_insn (count
, temp
);
4145 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4148 emit_move_insn (blocks
, temp
);
4150 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4151 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4153 emit_label (loop_start_label
);
4156 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4160 /* Issue a read prefetch for the +3 cache line. */
4161 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4162 const0_rtx
, const0_rtx
);
4163 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4164 emit_insn (prefetch
);
4166 /* Issue a write prefetch for the +3 cache line. */
4167 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4168 const1_rtx
, const0_rtx
);
4169 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4170 emit_insn (prefetch
);
4173 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4174 s390_load_address (dst_addr
,
4175 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4176 s390_load_address (src_addr
,
4177 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4179 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4182 emit_move_insn (blocks
, temp
);
4184 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4185 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4187 emit_jump (loop_start_label
);
4188 emit_label (loop_end_label
);
4190 emit_insn (gen_movmem_short (dst
, src
,
4191 convert_to_mode (Pmode
, count
, 1)));
4192 emit_label (end_label
);
4196 /* Emit code to set LEN bytes at DST to VAL.
4197 Make use of clrmem if VAL is zero. */
4200 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4202 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4205 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4207 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4209 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4210 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4213 /* Initialize memory by storing the first byte. */
4214 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4216 if (INTVAL (len
) > 1)
4218 /* Initiate 1 byte overlap move.
4219 The first byte of DST is propagated through DSTP1.
4220 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4221 DST is set to size 1 so the rest of the memory location
4222 does not count as source operand. */
4223 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4224 set_mem_size (dst
, const1_rtx
);
4226 emit_insn (gen_movmem_short (dstp1
, dst
,
4227 GEN_INT (INTVAL (len
) - 2)));
4232 else if (TARGET_MVCLE
)
4234 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4235 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4240 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4241 rtx loop_start_label
= gen_label_rtx ();
4242 rtx loop_end_label
= gen_label_rtx ();
4243 rtx end_label
= gen_label_rtx ();
4244 enum machine_mode mode
;
4246 mode
= GET_MODE (len
);
4247 if (mode
== VOIDmode
)
4250 dst_addr
= gen_reg_rtx (Pmode
);
4251 count
= gen_reg_rtx (mode
);
4252 blocks
= gen_reg_rtx (mode
);
4254 convert_move (count
, len
, 1);
4255 emit_cmp_and_jump_insns (count
, const0_rtx
,
4256 EQ
, NULL_RTX
, mode
, 1, end_label
);
4258 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4259 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4261 if (val
== const0_rtx
)
4262 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4266 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4267 set_mem_size (dst
, const1_rtx
);
4269 /* Initialize memory by storing the first byte. */
4270 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4272 /* If count is 1 we are done. */
4273 emit_cmp_and_jump_insns (count
, const1_rtx
,
4274 EQ
, NULL_RTX
, mode
, 1, end_label
);
4276 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4280 emit_move_insn (count
, temp
);
4282 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4285 emit_move_insn (blocks
, temp
);
4287 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4288 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4290 emit_label (loop_start_label
);
4293 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4295 /* Issue a write prefetch for the +4 cache line. */
4296 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4298 const1_rtx
, const0_rtx
);
4299 emit_insn (prefetch
);
4300 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4303 if (val
== const0_rtx
)
4304 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4306 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4307 s390_load_address (dst_addr
,
4308 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4310 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4313 emit_move_insn (blocks
, temp
);
4315 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4316 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4318 emit_jump (loop_start_label
);
4319 emit_label (loop_end_label
);
4321 if (val
== const0_rtx
)
4322 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4324 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4325 emit_label (end_label
);
4329 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4330 and return the result in TARGET. */
4333 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4335 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4338 /* As the result of CMPINT is inverted compared to what we need,
4339 we have to swap the operands. */
4340 tmp
= op0
; op0
= op1
; op1
= tmp
;
4342 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4344 if (INTVAL (len
) > 0)
4346 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4347 emit_insn (gen_cmpint (target
, ccreg
));
4350 emit_move_insn (target
, const0_rtx
);
4352 else if (TARGET_MVCLE
)
4354 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4355 emit_insn (gen_cmpint (target
, ccreg
));
4359 rtx addr0
, addr1
, count
, blocks
, temp
;
4360 rtx loop_start_label
= gen_label_rtx ();
4361 rtx loop_end_label
= gen_label_rtx ();
4362 rtx end_label
= gen_label_rtx ();
4363 enum machine_mode mode
;
4365 mode
= GET_MODE (len
);
4366 if (mode
== VOIDmode
)
4369 addr0
= gen_reg_rtx (Pmode
);
4370 addr1
= gen_reg_rtx (Pmode
);
4371 count
= gen_reg_rtx (mode
);
4372 blocks
= gen_reg_rtx (mode
);
4374 convert_move (count
, len
, 1);
4375 emit_cmp_and_jump_insns (count
, const0_rtx
,
4376 EQ
, NULL_RTX
, mode
, 1, end_label
);
4378 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4379 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4380 op0
= change_address (op0
, VOIDmode
, addr0
);
4381 op1
= change_address (op1
, VOIDmode
, addr1
);
4383 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4386 emit_move_insn (count
, temp
);
4388 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4391 emit_move_insn (blocks
, temp
);
4393 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4394 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4396 emit_label (loop_start_label
);
4399 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4403 /* Issue a read prefetch for the +2 cache line of operand 1. */
4404 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4405 const0_rtx
, const0_rtx
);
4406 emit_insn (prefetch
);
4407 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4409 /* Issue a read prefetch for the +2 cache line of operand 2. */
4410 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4411 const0_rtx
, const0_rtx
);
4412 emit_insn (prefetch
);
4413 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4416 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4417 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4418 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4419 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4420 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4421 emit_jump_insn (temp
);
4423 s390_load_address (addr0
,
4424 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4425 s390_load_address (addr1
,
4426 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4428 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4431 emit_move_insn (blocks
, temp
);
4433 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4434 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4436 emit_jump (loop_start_label
);
4437 emit_label (loop_end_label
);
4439 emit_insn (gen_cmpmem_short (op0
, op1
,
4440 convert_to_mode (Pmode
, count
, 1)));
4441 emit_label (end_label
);
4443 emit_insn (gen_cmpint (target
, ccreg
));
4448 /* Expand conditional increment or decrement using alc/slb instructions.
4449 Should generate code setting DST to either SRC or SRC + INCREMENT,
4450 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4451 Returns true if successful, false otherwise.
4453 That makes it possible to implement some if-constructs without jumps e.g.:
4454 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4455 unsigned int a, b, c;
4456 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4457 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4458 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4459 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4461 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4462 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4463 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4464 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4465 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4468 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4469 rtx dst
, rtx src
, rtx increment
)
4471 enum machine_mode cmp_mode
;
4472 enum machine_mode cc_mode
;
4478 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4479 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4481 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4482 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4487 /* Try ADD LOGICAL WITH CARRY. */
4488 if (increment
== const1_rtx
)
4490 /* Determine CC mode to use. */
4491 if (cmp_code
== EQ
|| cmp_code
== NE
)
4493 if (cmp_op1
!= const0_rtx
)
4495 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4496 NULL_RTX
, 0, OPTAB_WIDEN
);
4497 cmp_op1
= const0_rtx
;
4500 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4503 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4508 cmp_code
= swap_condition (cmp_code
);
4525 /* Emit comparison instruction pattern. */
4526 if (!register_operand (cmp_op0
, cmp_mode
))
4527 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4529 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4530 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4531 /* We use insn_invalid_p here to add clobbers if required. */
4532 ret
= insn_invalid_p (emit_insn (insn
));
4535 /* Emit ALC instruction pattern. */
4536 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4537 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4540 if (src
!= const0_rtx
)
4542 if (!register_operand (src
, GET_MODE (dst
)))
4543 src
= force_reg (GET_MODE (dst
), src
);
4545 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4546 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4549 p
= rtvec_alloc (2);
4551 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4553 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4554 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4559 /* Try SUBTRACT LOGICAL WITH BORROW. */
4560 if (increment
== constm1_rtx
)
4562 /* Determine CC mode to use. */
4563 if (cmp_code
== EQ
|| cmp_code
== NE
)
4565 if (cmp_op1
!= const0_rtx
)
4567 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4568 NULL_RTX
, 0, OPTAB_WIDEN
);
4569 cmp_op1
= const0_rtx
;
4572 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4575 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4580 cmp_code
= swap_condition (cmp_code
);
4597 /* Emit comparison instruction pattern. */
4598 if (!register_operand (cmp_op0
, cmp_mode
))
4599 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4601 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4602 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4603 /* We use insn_invalid_p here to add clobbers if required. */
4604 ret
= insn_invalid_p (emit_insn (insn
));
4607 /* Emit SLB instruction pattern. */
4608 if (!register_operand (src
, GET_MODE (dst
)))
4609 src
= force_reg (GET_MODE (dst
), src
);
4611 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4612 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4613 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4614 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4616 p
= rtvec_alloc (2);
4618 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4620 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4621 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4629 /* Expand code for the insv template. Return true if successful. */
4632 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4634 int bitsize
= INTVAL (op1
);
4635 int bitpos
= INTVAL (op2
);
4637 /* On z10 we can use the risbg instruction to implement insv. */
4639 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4640 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4645 op
= gen_rtx_SET (GET_MODE(src
),
4646 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4648 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4649 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4654 /* We need byte alignment. */
4655 if (bitsize
% BITS_PER_UNIT
)
4659 && memory_operand (dest
, VOIDmode
)
4660 && (register_operand (src
, word_mode
)
4661 || const_int_operand (src
, VOIDmode
)))
4663 /* Emit standard pattern if possible. */
4664 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4665 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4666 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4668 /* (set (ze (mem)) (const_int)). */
4669 else if (const_int_operand (src
, VOIDmode
))
4671 int size
= bitsize
/ BITS_PER_UNIT
;
4672 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4673 GET_MODE_SIZE (word_mode
) - size
);
4675 dest
= adjust_address (dest
, BLKmode
, 0);
4676 set_mem_size (dest
, GEN_INT (size
));
4677 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4680 /* (set (ze (mem)) (reg)). */
4681 else if (register_operand (src
, word_mode
))
4683 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4684 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4688 /* Emit st,stcmh sequence. */
4689 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4690 int size
= stcmh_width
/ BITS_PER_UNIT
;
4692 emit_move_insn (adjust_address (dest
, SImode
, size
),
4693 gen_lowpart (SImode
, src
));
4694 set_mem_size (dest
, GEN_INT (size
));
4695 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4696 (stcmh_width
), const0_rtx
),
4697 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4698 (GET_MODE_BITSIZE (SImode
))));
4707 /* (set (ze (reg)) (const_int)). */
4709 && register_operand (dest
, word_mode
)
4710 && (bitpos
% 16) == 0
4711 && (bitsize
% 16) == 0
4712 && const_int_operand (src
, VOIDmode
))
4714 HOST_WIDE_INT val
= INTVAL (src
);
4715 int regpos
= bitpos
+ bitsize
;
4717 while (regpos
> bitpos
)
4719 enum machine_mode putmode
;
4722 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4727 putsize
= GET_MODE_BITSIZE (putmode
);
4729 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4732 gen_int_mode (val
, putmode
));
4735 gcc_assert (regpos
== bitpos
);
4742 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4743 register that holds VAL of mode MODE shifted by COUNT bits. */
4746 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4748 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4749 NULL_RTX
, 1, OPTAB_DIRECT
);
4750 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4751 NULL_RTX
, 1, OPTAB_DIRECT
);
4754 /* Structure to hold the initial parameters for a compare_and_swap operation
4755 in HImode and QImode. */
4757 struct alignment_context
4759 rtx memsi
; /* SI aligned memory location. */
4760 rtx shift
; /* Bit offset with regard to lsb. */
4761 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4762 rtx modemaski
; /* ~modemask */
4763 bool aligned
; /* True if memory is aligned, false else. */
4766 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4767 structure AC for transparent simplifying, if the memory alignment is known
4768 to be at least 32bit. MEM is the memory location for the actual operation
4769 and MODE its mode. */
4772 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4773 enum machine_mode mode
)
4775 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4776 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4779 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4782 /* Alignment is unknown. */
4783 rtx byteoffset
, addr
, align
;
4785 /* Force the address into a register. */
4786 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4788 /* Align it to SImode. */
4789 align
= expand_simple_binop (Pmode
, AND
, addr
,
4790 GEN_INT (-GET_MODE_SIZE (SImode
)),
4791 NULL_RTX
, 1, OPTAB_DIRECT
);
4793 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4794 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4795 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4796 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4798 /* Calculate shiftcount. */
4799 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4800 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4801 NULL_RTX
, 1, OPTAB_DIRECT
);
4802 /* As we already have some offset, evaluate the remaining distance. */
4803 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4804 NULL_RTX
, 1, OPTAB_DIRECT
);
4807 /* Shift is the byte count, but we need the bitcount. */
4808 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4809 NULL_RTX
, 1, OPTAB_DIRECT
);
4810 /* Calculate masks. */
4811 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4812 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4813 NULL_RTX
, 1, OPTAB_DIRECT
);
4814 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4817 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4818 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4819 to set if CMP == MEM.
4820 CMP is never in memory for compare_and_swap_cc because
4821 expand_bool_compare_and_swap puts it into a register for later compare. */
4824 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4826 struct alignment_context ac
;
4827 rtx cmpv
, newv
, val
, resv
, cc
;
4828 rtx res
= gen_reg_rtx (SImode
);
4829 rtx csloop
= gen_label_rtx ();
4830 rtx csend
= gen_label_rtx ();
4832 gcc_assert (register_operand (target
, VOIDmode
));
4833 gcc_assert (MEM_P (mem
));
4835 init_alignment_context (&ac
, mem
, mode
);
4837 /* Shift the values to the correct bit positions. */
4838 if (!(ac
.aligned
&& MEM_P (cmp
)))
4839 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4840 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4841 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4843 /* Load full word. Subsequent loads are performed by CS. */
4844 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4845 NULL_RTX
, 1, OPTAB_DIRECT
);
4847 /* Start CS loop. */
4848 emit_label (csloop
);
4849 /* val = "<mem>00..0<mem>"
4850 * cmp = "00..0<cmp>00..0"
4851 * new = "00..0<new>00..0"
4854 /* Patch cmp and new with val at correct position. */
4855 if (ac
.aligned
&& MEM_P (cmp
))
4857 cmpv
= force_reg (SImode
, val
);
4858 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4861 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4862 NULL_RTX
, 1, OPTAB_DIRECT
));
4863 if (ac
.aligned
&& MEM_P (new_rtx
))
4865 newv
= force_reg (SImode
, val
);
4866 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new_rtx
);
4869 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4870 NULL_RTX
, 1, OPTAB_DIRECT
));
4872 /* Jump to end if we're done (likely?). */
4873 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4876 /* Check for changes outside mode. */
4877 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4878 NULL_RTX
, 1, OPTAB_DIRECT
);
4879 cc
= s390_emit_compare (NE
, resv
, val
);
4880 emit_move_insn (val
, resv
);
4881 /* Loop internal if so. */
4882 s390_emit_jump (csloop
, cc
);
4886 /* Return the correct part of the bitfield. */
4887 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4888 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4891 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4892 and VAL the value to play with. If AFTER is true then store the value
4893 MEM holds after the operation, if AFTER is false then store the value MEM
4894 holds before the operation. If TARGET is zero then discard that value, else
4895 store it to TARGET. */
4898 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4899 rtx target
, rtx mem
, rtx val
, bool after
)
4901 struct alignment_context ac
;
4903 rtx new_rtx
= gen_reg_rtx (SImode
);
4904 rtx orig
= gen_reg_rtx (SImode
);
4905 rtx csloop
= gen_label_rtx ();
4907 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4908 gcc_assert (MEM_P (mem
));
4910 init_alignment_context (&ac
, mem
, mode
);
4912 /* Shift val to the correct bit positions.
4913 Preserve "icm", but prevent "ex icm". */
4914 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4915 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4917 /* Further preparation insns. */
4918 if (code
== PLUS
|| code
== MINUS
)
4919 emit_move_insn (orig
, val
);
4920 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4921 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4922 NULL_RTX
, 1, OPTAB_DIRECT
);
4924 /* Load full word. Subsequent loads are performed by CS. */
4925 cmp
= force_reg (SImode
, ac
.memsi
);
4927 /* Start CS loop. */
4928 emit_label (csloop
);
4929 emit_move_insn (new_rtx
, cmp
);
4931 /* Patch new with val at correct position. */
4936 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4937 NULL_RTX
, 1, OPTAB_DIRECT
);
4938 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4939 NULL_RTX
, 1, OPTAB_DIRECT
);
4942 if (ac
.aligned
&& MEM_P (val
))
4943 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4946 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4947 NULL_RTX
, 1, OPTAB_DIRECT
);
4948 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4949 NULL_RTX
, 1, OPTAB_DIRECT
);
4955 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4956 NULL_RTX
, 1, OPTAB_DIRECT
);
4958 case MULT
: /* NAND */
4959 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4960 NULL_RTX
, 1, OPTAB_DIRECT
);
4961 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4962 NULL_RTX
, 1, OPTAB_DIRECT
);
4968 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4969 ac
.memsi
, cmp
, new_rtx
));
4971 /* Return the correct part of the bitfield. */
4973 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4974 after
? new_rtx
: cmp
, ac
.shift
,
4975 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4978 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4979 We need to emit DTP-relative relocations. */
4981 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4984 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4989 fputs ("\t.long\t", file
);
4992 fputs ("\t.quad\t", file
);
4997 output_addr_const (file
, x
);
4998 fputs ("@DTPOFF", file
);
5001 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5002 /* Implement TARGET_MANGLE_TYPE. */
5005 s390_mangle_type (const_tree type
)
5007 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
5008 && TARGET_LONG_DOUBLE_128
)
5011 /* For all other types, use normal C++ mangling. */
5016 /* In the name of slightly smaller debug output, and to cater to
5017 general assembler lossage, recognize various UNSPEC sequences
5018 and turn them back into a direct symbol reference. */
5021 s390_delegitimize_address (rtx orig_x
)
5025 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5028 /* Extract the symbol ref from:
5029 (plus:SI (reg:SI 12 %r12)
5030 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5031 UNSPEC_GOTOFF/PLTOFF)))
5033 (plus:SI (reg:SI 12 %r12)
5034 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5035 UNSPEC_GOTOFF/PLTOFF)
5036 (const_int 4 [0x4])))) */
5037 if (GET_CODE (x
) == PLUS
5038 && REG_P (XEXP (x
, 0))
5039 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
5040 && GET_CODE (XEXP (x
, 1)) == CONST
)
5042 HOST_WIDE_INT offset
= 0;
5044 /* The const operand. */
5045 y
= XEXP (XEXP (x
, 1), 0);
5047 if (GET_CODE (y
) == PLUS
5048 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
5050 offset
= INTVAL (XEXP (y
, 1));
5054 if (GET_CODE (y
) == UNSPEC
5055 && (XINT (y
, 1) == UNSPEC_GOTOFF
5056 || XINT (y
, 1) == UNSPEC_PLTOFF
))
5057 return plus_constant (XVECEXP (y
, 0, 0), offset
);
5060 if (GET_CODE (x
) != MEM
)
5064 if (GET_CODE (x
) == PLUS
5065 && GET_CODE (XEXP (x
, 1)) == CONST
5066 && GET_CODE (XEXP (x
, 0)) == REG
5067 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5069 y
= XEXP (XEXP (x
, 1), 0);
5070 if (GET_CODE (y
) == UNSPEC
5071 && XINT (y
, 1) == UNSPEC_GOT
)
5072 y
= XVECEXP (y
, 0, 0);
5076 else if (GET_CODE (x
) == CONST
)
5078 /* Extract the symbol ref from:
5079 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5080 UNSPEC_PLT/GOTENT))) */
5083 if (GET_CODE (y
) == UNSPEC
5084 && (XINT (y
, 1) == UNSPEC_GOTENT
5085 || XINT (y
, 1) == UNSPEC_PLT
))
5086 y
= XVECEXP (y
, 0, 0);
5093 if (GET_MODE (orig_x
) != Pmode
)
5095 if (GET_MODE (orig_x
) == BLKmode
)
5097 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
5104 /* Output operand OP to stdio stream FILE.
5105 OP is an address (register + offset) which is not used to address data;
5106 instead the rightmost bits are interpreted as the value. */
5109 print_shift_count_operand (FILE *file
, rtx op
)
5111 HOST_WIDE_INT offset
;
5114 /* Extract base register and offset. */
5115 if (!s390_decompose_shift_count (op
, &base
, &offset
))
5121 gcc_assert (GET_CODE (base
) == REG
);
5122 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
5123 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5126 /* Offsets are constricted to twelve bits. */
5127 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5129 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5132 /* See 'get_some_local_dynamic_name'. */
5135 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5139 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
5141 x
= get_pool_constant (x
);
5142 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
5145 if (GET_CODE (x
) == SYMBOL_REF
5146 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5148 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5155 /* Locate some local-dynamic symbol still in use by this function
5156 so that we can print its name in local-dynamic base patterns. */
5159 get_some_local_dynamic_name (void)
5163 if (cfun
->machine
->some_ld_name
)
5164 return cfun
->machine
->some_ld_name
;
5166 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5168 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5169 return cfun
->machine
->some_ld_name
;
5174 /* Output machine-dependent UNSPECs occurring in address constant X
5175 in assembler syntax to stdio stream FILE. Returns true if the
5176 constant X could be recognized, false otherwise. */
5179 s390_output_addr_const_extra (FILE *file
, rtx x
)
5181 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5182 switch (XINT (x
, 1))
5185 output_addr_const (file
, XVECEXP (x
, 0, 0));
5186 fprintf (file
, "@GOTENT");
5189 output_addr_const (file
, XVECEXP (x
, 0, 0));
5190 fprintf (file
, "@GOT");
5193 output_addr_const (file
, XVECEXP (x
, 0, 0));
5194 fprintf (file
, "@GOTOFF");
5197 output_addr_const (file
, XVECEXP (x
, 0, 0));
5198 fprintf (file
, "@PLT");
5201 output_addr_const (file
, XVECEXP (x
, 0, 0));
5202 fprintf (file
, "@PLTOFF");
5205 output_addr_const (file
, XVECEXP (x
, 0, 0));
5206 fprintf (file
, "@TLSGD");
5209 assemble_name (file
, get_some_local_dynamic_name ());
5210 fprintf (file
, "@TLSLDM");
5213 output_addr_const (file
, XVECEXP (x
, 0, 0));
5214 fprintf (file
, "@DTPOFF");
5217 output_addr_const (file
, XVECEXP (x
, 0, 0));
5218 fprintf (file
, "@NTPOFF");
5220 case UNSPEC_GOTNTPOFF
:
5221 output_addr_const (file
, XVECEXP (x
, 0, 0));
5222 fprintf (file
, "@GOTNTPOFF");
5224 case UNSPEC_INDNTPOFF
:
5225 output_addr_const (file
, XVECEXP (x
, 0, 0));
5226 fprintf (file
, "@INDNTPOFF");
5230 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5231 switch (XINT (x
, 1))
5233 case UNSPEC_POOL_OFFSET
:
5234 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5235 output_addr_const (file
, x
);
5241 /* Output address operand ADDR in assembler syntax to
5242 stdio stream FILE. */
5245 print_operand_address (FILE *file
, rtx addr
)
5247 struct s390_address ad
;
5249 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5253 output_operand_lossage ("symbolic memory references are "
5254 "only supported on z10 or later");
5257 output_addr_const (file
, addr
);
5261 if (!s390_decompose_address (addr
, &ad
)
5262 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5263 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5264 output_operand_lossage ("cannot decompose address");
5267 output_addr_const (file
, ad
.disp
);
5269 fprintf (file
, "0");
5271 if (ad
.base
&& ad
.indx
)
5272 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5273 reg_names
[REGNO (ad
.base
)]);
5275 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5278 /* Output operand X in assembler syntax to stdio stream FILE.
5279 CODE specified the format flag. The following format flags
5282 'C': print opcode suffix for branch condition.
5283 'D': print opcode suffix for inverse branch condition.
5284 'E': print opcode suffix for branch on index instruction.
5285 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5286 'G': print the size of the operand in bytes.
5287 'O': print only the displacement of a memory reference.
5288 'R': print only the base register of a memory reference.
5289 'S': print S-type memory reference (base+displacement).
5290 'N': print the second word of a DImode operand.
5291 'M': print the second word of a TImode operand.
5292 'Y': print shift count operand.
5294 'b': print integer X as if it's an unsigned byte.
5295 'c': print integer X as if it's an signed byte.
5296 'x': print integer X as if it's an unsigned halfword.
5297 'h': print integer X as if it's a signed halfword.
5298 'i': print the first nonzero HImode part of X.
5299 'j': print the first HImode part unequal to -1 of X.
5300 'k': print the first nonzero SImode part of X.
5301 'm': print the first SImode part unequal to -1 of X.
5302 'o': print integer X as if it's an unsigned 32bit word. */
5305 print_operand (FILE *file
, rtx x
, int code
)
5310 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5314 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5318 if (GET_CODE (x
) == LE
)
5319 fprintf (file
, "l");
5320 else if (GET_CODE (x
) == GT
)
5321 fprintf (file
, "h");
5323 output_operand_lossage ("invalid comparison operator "
5324 "for 'E' output modifier");
5328 if (GET_CODE (x
) == SYMBOL_REF
)
5330 fprintf (file
, "%s", ":tls_load:");
5331 output_addr_const (file
, x
);
5333 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5335 fprintf (file
, "%s", ":tls_gdcall:");
5336 output_addr_const (file
, XVECEXP (x
, 0, 0));
5338 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5340 fprintf (file
, "%s", ":tls_ldcall:");
5341 assemble_name (file
, get_some_local_dynamic_name ());
5344 output_operand_lossage ("invalid reference for 'J' output modifier");
5348 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5353 struct s390_address ad
;
5358 output_operand_lossage ("memory reference expected for "
5359 "'O' output modifier");
5363 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5366 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5369 output_operand_lossage ("invalid address for 'O' output modifier");
5374 output_addr_const (file
, ad
.disp
);
5376 fprintf (file
, "0");
5382 struct s390_address ad
;
5387 output_operand_lossage ("memory reference expected for "
5388 "'R' output modifier");
5392 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5395 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5398 output_operand_lossage ("invalid address for 'R' output modifier");
5403 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5405 fprintf (file
, "0");
5411 struct s390_address ad
;
5416 output_operand_lossage ("memory reference expected for "
5417 "'S' output modifier");
5420 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5423 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5426 output_operand_lossage ("invalid address for 'S' output modifier");
5431 output_addr_const (file
, ad
.disp
);
5433 fprintf (file
, "0");
5436 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5441 if (GET_CODE (x
) == REG
)
5442 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5443 else if (GET_CODE (x
) == MEM
)
5444 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5446 output_operand_lossage ("register or memory expression expected "
5447 "for 'N' output modifier");
5451 if (GET_CODE (x
) == REG
)
5452 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5453 else if (GET_CODE (x
) == MEM
)
5454 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5456 output_operand_lossage ("register or memory expression expected "
5457 "for 'M' output modifier");
5461 print_shift_count_operand (file
, x
);
5465 switch (GET_CODE (x
))
5468 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5472 output_address (XEXP (x
, 0));
5479 output_addr_const (file
, x
);
5484 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5485 else if (code
== 'c')
5486 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5487 else if (code
== 'x')
5488 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5489 else if (code
== 'h')
5490 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5491 else if (code
== 'i')
5492 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5493 s390_extract_part (x
, HImode
, 0));
5494 else if (code
== 'j')
5495 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5496 s390_extract_part (x
, HImode
, -1));
5497 else if (code
== 'k')
5498 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5499 s390_extract_part (x
, SImode
, 0));
5500 else if (code
== 'm')
5501 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5502 s390_extract_part (x
, SImode
, -1));
5503 else if (code
== 'o')
5504 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5506 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5510 gcc_assert (GET_MODE (x
) == VOIDmode
);
5512 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5513 else if (code
== 'x')
5514 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5515 else if (code
== 'h')
5516 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5517 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5521 output_operand_lossage ("invalid constant - try using "
5522 "an output modifier");
5524 output_operand_lossage ("invalid constant for output modifier '%c'",
5531 output_operand_lossage ("invalid expression - try using "
5532 "an output modifier");
5534 output_operand_lossage ("invalid expression for output "
5535 "modifier '%c'", code
);
5540 /* Target hook for assembling integer objects. We need to define it
5541 here to work a round a bug in some versions of GAS, which couldn't
5542 handle values smaller than INT_MIN when printed in decimal. */
5545 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5547 if (size
== 8 && aligned_p
5548 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5550 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5554 return default_assemble_integer (x
, size
, aligned_p
);
5557 /* Returns true if register REGNO is used for forming
5558 a memory address in expression X. */
5561 reg_used_in_mem_p (int regno
, rtx x
)
5563 enum rtx_code code
= GET_CODE (x
);
5569 if (refers_to_regno_p (regno
, regno
+1,
5573 else if (code
== SET
5574 && GET_CODE (SET_DEST (x
)) == PC
)
5576 if (refers_to_regno_p (regno
, regno
+1,
5581 fmt
= GET_RTX_FORMAT (code
);
5582 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5585 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5588 else if (fmt
[i
] == 'E')
5589 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5590 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5596 /* Returns true if expression DEP_RTX sets an address register
5597 used by instruction INSN to address memory. */
5600 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5604 if (GET_CODE (dep_rtx
) == INSN
)
5605 dep_rtx
= PATTERN (dep_rtx
);
5607 if (GET_CODE (dep_rtx
) == SET
)
5609 target
= SET_DEST (dep_rtx
);
5610 if (GET_CODE (target
) == STRICT_LOW_PART
)
5611 target
= XEXP (target
, 0);
5612 while (GET_CODE (target
) == SUBREG
)
5613 target
= SUBREG_REG (target
);
5615 if (GET_CODE (target
) == REG
)
5617 int regno
= REGNO (target
);
5619 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5621 pat
= PATTERN (insn
);
5622 if (GET_CODE (pat
) == PARALLEL
)
5624 gcc_assert (XVECLEN (pat
, 0) == 2);
5625 pat
= XVECEXP (pat
, 0, 0);
5627 gcc_assert (GET_CODE (pat
) == SET
);
5628 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5630 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5631 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5637 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5640 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5642 rtx dep_rtx
= PATTERN (dep_insn
);
5645 if (GET_CODE (dep_rtx
) == SET
5646 && addr_generation_dependency_p (dep_rtx
, insn
))
5648 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5650 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5652 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5660 /* A C statement (sans semicolon) to update the integer scheduling priority
5661 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5662 reduce the priority to execute INSN later. Do not define this macro if
5663 you do not need to adjust the scheduling priorities of insns.
5665 A STD instruction should be scheduled earlier,
5666 in order to use the bypass. */
5668 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5670 if (! INSN_P (insn
))
5673 if (s390_tune
!= PROCESSOR_2084_Z990
5674 && s390_tune
!= PROCESSOR_2094_Z9_109
5675 && s390_tune
!= PROCESSOR_2097_Z10
5676 && s390_tune
!= PROCESSOR_2817_Z196
)
5679 switch (s390_safe_attr_type (insn
))
5683 priority
= priority
<< 3;
5687 priority
= priority
<< 1;
5696 /* The number of instructions that can be issued per cycle. */
5699 s390_issue_rate (void)
5703 case PROCESSOR_2084_Z990
:
5704 case PROCESSOR_2094_Z9_109
:
5705 case PROCESSOR_2817_Z196
:
5707 case PROCESSOR_2097_Z10
:
5715 s390_first_cycle_multipass_dfa_lookahead (void)
5720 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5721 Fix up MEMs as required. */
5724 annotate_constant_pool_refs (rtx
*x
)
5729 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5730 || !CONSTANT_POOL_ADDRESS_P (*x
));
5732 /* Literal pool references can only occur inside a MEM ... */
5733 if (GET_CODE (*x
) == MEM
)
5735 rtx memref
= XEXP (*x
, 0);
5737 if (GET_CODE (memref
) == SYMBOL_REF
5738 && CONSTANT_POOL_ADDRESS_P (memref
))
5740 rtx base
= cfun
->machine
->base_reg
;
5741 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5744 *x
= replace_equiv_address (*x
, addr
);
5748 if (GET_CODE (memref
) == CONST
5749 && GET_CODE (XEXP (memref
, 0)) == PLUS
5750 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5751 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5752 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5754 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5755 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5756 rtx base
= cfun
->machine
->base_reg
;
5757 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5760 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5765 /* ... or a load-address type pattern. */
5766 if (GET_CODE (*x
) == SET
)
5768 rtx addrref
= SET_SRC (*x
);
5770 if (GET_CODE (addrref
) == SYMBOL_REF
5771 && CONSTANT_POOL_ADDRESS_P (addrref
))
5773 rtx base
= cfun
->machine
->base_reg
;
5774 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5777 SET_SRC (*x
) = addr
;
5781 if (GET_CODE (addrref
) == CONST
5782 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5783 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5784 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5785 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5787 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5788 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5789 rtx base
= cfun
->machine
->base_reg
;
5790 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5793 SET_SRC (*x
) = plus_constant (addr
, off
);
5798 /* Annotate LTREL_BASE as well. */
5799 if (GET_CODE (*x
) == UNSPEC
5800 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5802 rtx base
= cfun
->machine
->base_reg
;
5803 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5808 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5809 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5813 annotate_constant_pool_refs (&XEXP (*x
, i
));
5815 else if (fmt
[i
] == 'E')
5817 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5818 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5823 /* Split all branches that exceed the maximum distance.
5824 Returns true if this created a new literal pool entry. */
5827 s390_split_branches (void)
5829 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5830 int new_literal
= 0, ret
;
5831 rtx insn
, pat
, tmp
, target
;
5834 /* We need correct insn addresses. */
5836 shorten_branches (get_insns ());
5838 /* Find all branches that exceed 64KB, and split them. */
5840 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5842 if (GET_CODE (insn
) != JUMP_INSN
)
5845 pat
= PATTERN (insn
);
5846 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5847 pat
= XVECEXP (pat
, 0, 0);
5848 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5851 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5853 label
= &SET_SRC (pat
);
5855 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5857 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5858 label
= &XEXP (SET_SRC (pat
), 1);
5859 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5860 label
= &XEXP (SET_SRC (pat
), 2);
5867 if (get_attr_length (insn
) <= 4)
5870 /* We are going to use the return register as scratch register,
5871 make sure it will be saved/restored by the prologue/epilogue. */
5872 cfun_frame_layout
.save_return_addr_p
= 1;
5877 tmp
= force_const_mem (Pmode
, *label
);
5878 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5879 INSN_ADDRESSES_NEW (tmp
, -1);
5880 annotate_constant_pool_refs (&PATTERN (tmp
));
5887 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5888 UNSPEC_LTREL_OFFSET
);
5889 target
= gen_rtx_CONST (Pmode
, target
);
5890 target
= force_const_mem (Pmode
, target
);
5891 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5892 INSN_ADDRESSES_NEW (tmp
, -1);
5893 annotate_constant_pool_refs (&PATTERN (tmp
));
5895 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5896 cfun
->machine
->base_reg
),
5898 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5901 ret
= validate_change (insn
, label
, target
, 0);
5909 /* Find an annotated literal pool symbol referenced in RTX X,
5910 and store it at REF. Will abort if X contains references to
5911 more than one such pool symbol; multiple references to the same
5912 symbol are allowed, however.
5914 The rtx pointed to by REF must be initialized to NULL_RTX
5915 by the caller before calling this routine. */
5918 find_constant_pool_ref (rtx x
, rtx
*ref
)
5923 /* Ignore LTREL_BASE references. */
5924 if (GET_CODE (x
) == UNSPEC
5925 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5927 /* Likewise POOL_ENTRY insns. */
5928 if (GET_CODE (x
) == UNSPEC_VOLATILE
5929 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5932 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5933 || !CONSTANT_POOL_ADDRESS_P (x
));
5935 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5937 rtx sym
= XVECEXP (x
, 0, 0);
5938 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5939 && CONSTANT_POOL_ADDRESS_P (sym
));
5941 if (*ref
== NULL_RTX
)
5944 gcc_assert (*ref
== sym
);
5949 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5950 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5954 find_constant_pool_ref (XEXP (x
, i
), ref
);
5956 else if (fmt
[i
] == 'E')
5958 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5959 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5964 /* Replace every reference to the annotated literal pool
5965 symbol REF in X by its base plus OFFSET. */
5968 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5973 gcc_assert (*x
!= ref
);
5975 if (GET_CODE (*x
) == UNSPEC
5976 && XINT (*x
, 1) == UNSPEC_LTREF
5977 && XVECEXP (*x
, 0, 0) == ref
)
5979 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5983 if (GET_CODE (*x
) == PLUS
5984 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5985 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5986 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5987 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5989 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5990 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5994 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5995 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5999 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
6001 else if (fmt
[i
] == 'E')
6003 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6004 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
6009 /* Check whether X contains an UNSPEC_LTREL_BASE.
6010 Return its constant pool symbol if found, NULL_RTX otherwise. */
6013 find_ltrel_base (rtx x
)
6018 if (GET_CODE (x
) == UNSPEC
6019 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
6020 return XVECEXP (x
, 0, 0);
6022 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6023 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6027 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
6031 else if (fmt
[i
] == 'E')
6033 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6035 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
6045 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6048 replace_ltrel_base (rtx
*x
)
6053 if (GET_CODE (*x
) == UNSPEC
6054 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
6056 *x
= XVECEXP (*x
, 0, 1);
6060 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6061 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6065 replace_ltrel_base (&XEXP (*x
, i
));
6067 else if (fmt
[i
] == 'E')
6069 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6070 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
6076 /* We keep a list of constants which we have to add to internal
6077 constant tables in the middle of large functions. */
6079 #define NR_C_MODES 11
6080 enum machine_mode constant_modes
[NR_C_MODES
] =
6082 TFmode
, TImode
, TDmode
,
6083 DFmode
, DImode
, DDmode
,
6084 SFmode
, SImode
, SDmode
,
6091 struct constant
*next
;
6096 struct constant_pool
6098 struct constant_pool
*next
;
6102 rtx emit_pool_after
;
6104 struct constant
*constants
[NR_C_MODES
];
6105 struct constant
*execute
;
6110 /* Allocate new constant_pool structure. */
6112 static struct constant_pool
*
6113 s390_alloc_pool (void)
6115 struct constant_pool
*pool
;
6118 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
6120 for (i
= 0; i
< NR_C_MODES
; i
++)
6121 pool
->constants
[i
] = NULL
;
6123 pool
->execute
= NULL
;
6124 pool
->label
= gen_label_rtx ();
6125 pool
->first_insn
= NULL_RTX
;
6126 pool
->pool_insn
= NULL_RTX
;
6127 pool
->insns
= BITMAP_ALLOC (NULL
);
6129 pool
->emit_pool_after
= NULL_RTX
;
6134 /* Create new constant pool covering instructions starting at INSN
6135 and chain it to the end of POOL_LIST. */
6137 static struct constant_pool
*
6138 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
6140 struct constant_pool
*pool
, **prev
;
6142 pool
= s390_alloc_pool ();
6143 pool
->first_insn
= insn
;
6145 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
6152 /* End range of instructions covered by POOL at INSN and emit
6153 placeholder insn representing the pool. */
6156 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
6158 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
6161 insn
= get_last_insn ();
6163 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
6164 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6167 /* Add INSN to the list of insns covered by POOL. */
6170 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
6172 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
6175 /* Return pool out of POOL_LIST that covers INSN. */
6177 static struct constant_pool
*
6178 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6180 struct constant_pool
*pool
;
6182 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6183 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6189 /* Add constant VAL of mode MODE to the constant pool POOL. */
6192 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
6197 for (i
= 0; i
< NR_C_MODES
; i
++)
6198 if (constant_modes
[i
] == mode
)
6200 gcc_assert (i
!= NR_C_MODES
);
6202 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6203 if (rtx_equal_p (val
, c
->value
))
6208 c
= (struct constant
*) xmalloc (sizeof *c
);
6210 c
->label
= gen_label_rtx ();
6211 c
->next
= pool
->constants
[i
];
6212 pool
->constants
[i
] = c
;
6213 pool
->size
+= GET_MODE_SIZE (mode
);
6217 /* Return an rtx that represents the offset of X from the start of
6221 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6225 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6226 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6227 UNSPEC_POOL_OFFSET
);
6228 return gen_rtx_CONST (GET_MODE (x
), x
);
6231 /* Find constant VAL of mode MODE in the constant pool POOL.
6232 Return an RTX describing the distance from the start of
6233 the pool to the location of the new constant. */
6236 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6237 enum machine_mode mode
)
6242 for (i
= 0; i
< NR_C_MODES
; i
++)
6243 if (constant_modes
[i
] == mode
)
6245 gcc_assert (i
!= NR_C_MODES
);
6247 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6248 if (rtx_equal_p (val
, c
->value
))
6253 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6256 /* Check whether INSN is an execute. Return the label_ref to its
6257 execute target template if so, NULL_RTX otherwise. */
6260 s390_execute_label (rtx insn
)
6262 if (GET_CODE (insn
) == INSN
6263 && GET_CODE (PATTERN (insn
)) == PARALLEL
6264 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6265 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6266 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6271 /* Add execute target for INSN to the constant pool POOL. */
6274 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6278 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6279 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6284 c
= (struct constant
*) xmalloc (sizeof *c
);
6286 c
->label
= gen_label_rtx ();
6287 c
->next
= pool
->execute
;
6293 /* Find execute target for INSN in the constant pool POOL.
6294 Return an RTX describing the distance from the start of
6295 the pool to the location of the execute target. */
6298 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6302 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6303 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6308 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6311 /* For an execute INSN, extract the execute target template. */
6314 s390_execute_target (rtx insn
)
6316 rtx pattern
= PATTERN (insn
);
6317 gcc_assert (s390_execute_label (insn
));
6319 if (XVECLEN (pattern
, 0) == 2)
6321 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6325 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6328 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6329 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6331 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6337 /* Indicate that INSN cannot be duplicated. This is the case for
6338 execute insns that carry a unique label. */
6341 s390_cannot_copy_insn_p (rtx insn
)
6343 rtx label
= s390_execute_label (insn
);
6344 return label
&& label
!= const0_rtx
;
6347 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6348 do not emit the pool base label. */
6351 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6354 rtx insn
= pool
->pool_insn
;
6357 /* Switch to rodata section. */
6358 if (TARGET_CPU_ZARCH
)
6360 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6361 INSN_ADDRESSES_NEW (insn
, -1);
6364 /* Ensure minimum pool alignment. */
6365 if (TARGET_CPU_ZARCH
)
6366 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6368 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6369 INSN_ADDRESSES_NEW (insn
, -1);
6371 /* Emit pool base label. */
6374 insn
= emit_label_after (pool
->label
, insn
);
6375 INSN_ADDRESSES_NEW (insn
, -1);
6378 /* Dump constants in descending alignment requirement order,
6379 ensuring proper alignment for every constant. */
6380 for (i
= 0; i
< NR_C_MODES
; i
++)
6381 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6383 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6384 rtx value
= copy_rtx (c
->value
);
6385 if (GET_CODE (value
) == CONST
6386 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6387 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6388 && XVECLEN (XEXP (value
, 0), 0) == 1)
6389 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6391 insn
= emit_label_after (c
->label
, insn
);
6392 INSN_ADDRESSES_NEW (insn
, -1);
6394 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6395 gen_rtvec (1, value
),
6396 UNSPECV_POOL_ENTRY
);
6397 insn
= emit_insn_after (value
, insn
);
6398 INSN_ADDRESSES_NEW (insn
, -1);
6401 /* Ensure minimum alignment for instructions. */
6402 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6403 INSN_ADDRESSES_NEW (insn
, -1);
6405 /* Output in-pool execute template insns. */
6406 for (c
= pool
->execute
; c
; c
= c
->next
)
6408 insn
= emit_label_after (c
->label
, insn
);
6409 INSN_ADDRESSES_NEW (insn
, -1);
6411 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6412 INSN_ADDRESSES_NEW (insn
, -1);
6415 /* Switch back to previous section. */
6416 if (TARGET_CPU_ZARCH
)
6418 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6419 INSN_ADDRESSES_NEW (insn
, -1);
6422 insn
= emit_barrier_after (insn
);
6423 INSN_ADDRESSES_NEW (insn
, -1);
6425 /* Remove placeholder insn. */
6426 remove_insn (pool
->pool_insn
);
6429 /* Free all memory used by POOL. */
6432 s390_free_pool (struct constant_pool
*pool
)
6434 struct constant
*c
, *next
;
6437 for (i
= 0; i
< NR_C_MODES
; i
++)
6438 for (c
= pool
->constants
[i
]; c
; c
= next
)
6444 for (c
= pool
->execute
; c
; c
= next
)
6450 BITMAP_FREE (pool
->insns
);
6455 /* Collect main literal pool. Return NULL on overflow. */
6457 static struct constant_pool
*
6458 s390_mainpool_start (void)
6460 struct constant_pool
*pool
;
6463 pool
= s390_alloc_pool ();
6465 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6467 if (GET_CODE (insn
) == INSN
6468 && GET_CODE (PATTERN (insn
)) == SET
6469 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6470 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6472 gcc_assert (!pool
->pool_insn
);
6473 pool
->pool_insn
= insn
;
6476 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6478 s390_add_execute (pool
, insn
);
6480 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6482 rtx pool_ref
= NULL_RTX
;
6483 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6486 rtx constant
= get_pool_constant (pool_ref
);
6487 enum machine_mode mode
= get_pool_mode (pool_ref
);
6488 s390_add_constant (pool
, constant
, mode
);
6492 /* If hot/cold partitioning is enabled we have to make sure that
6493 the literal pool is emitted in the same section where the
6494 initialization of the literal pool base pointer takes place.
6495 emit_pool_after is only used in the non-overflow case on non
6496 Z cpus where we can emit the literal pool at the end of the
6497 function body within the text section. */
6499 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6500 && !pool
->emit_pool_after
)
6501 pool
->emit_pool_after
= PREV_INSN (insn
);
6504 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6506 if (pool
->size
>= 4096)
6508 /* We're going to chunkify the pool, so remove the main
6509 pool placeholder insn. */
6510 remove_insn (pool
->pool_insn
);
6512 s390_free_pool (pool
);
6516 /* If the functions ends with the section where the literal pool
6517 should be emitted set the marker to its end. */
6518 if (pool
&& !pool
->emit_pool_after
)
6519 pool
->emit_pool_after
= get_last_insn ();
6524 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6525 Modify the current function to output the pool constants as well as
6526 the pool register setup instruction. */
6529 s390_mainpool_finish (struct constant_pool
*pool
)
6531 rtx base_reg
= cfun
->machine
->base_reg
;
6534 /* If the pool is empty, we're done. */
6535 if (pool
->size
== 0)
6537 /* We don't actually need a base register after all. */
6538 cfun
->machine
->base_reg
= NULL_RTX
;
6540 if (pool
->pool_insn
)
6541 remove_insn (pool
->pool_insn
);
6542 s390_free_pool (pool
);
6546 /* We need correct insn addresses. */
6547 shorten_branches (get_insns ());
6549 /* On zSeries, we use a LARL to load the pool register. The pool is
6550 located in the .rodata section, so we emit it after the function. */
6551 if (TARGET_CPU_ZARCH
)
6553 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6554 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6555 INSN_ADDRESSES_NEW (insn
, -1);
6556 remove_insn (pool
->pool_insn
);
6558 insn
= get_last_insn ();
6559 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6560 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6562 s390_dump_pool (pool
, 0);
6565 /* On S/390, if the total size of the function's code plus literal pool
6566 does not exceed 4096 bytes, we use BASR to set up a function base
6567 pointer, and emit the literal pool at the end of the function. */
6568 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6569 + pool
->size
+ 8 /* alignment slop */ < 4096)
6571 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6572 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6573 INSN_ADDRESSES_NEW (insn
, -1);
6574 remove_insn (pool
->pool_insn
);
6576 insn
= emit_label_after (pool
->label
, insn
);
6577 INSN_ADDRESSES_NEW (insn
, -1);
6579 /* emit_pool_after will be set by s390_mainpool_start to the
6580 last insn of the section where the literal pool should be
6582 insn
= pool
->emit_pool_after
;
6584 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6585 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6587 s390_dump_pool (pool
, 1);
6590 /* Otherwise, we emit an inline literal pool and use BASR to branch
6591 over it, setting up the pool register at the same time. */
6594 rtx pool_end
= gen_label_rtx ();
6596 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6597 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6598 INSN_ADDRESSES_NEW (insn
, -1);
6599 remove_insn (pool
->pool_insn
);
6601 insn
= emit_label_after (pool
->label
, insn
);
6602 INSN_ADDRESSES_NEW (insn
, -1);
6604 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6605 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6607 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6608 INSN_ADDRESSES_NEW (insn
, -1);
6610 s390_dump_pool (pool
, 1);
6614 /* Replace all literal pool references. */
6616 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6619 replace_ltrel_base (&PATTERN (insn
));
6621 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6623 rtx addr
, pool_ref
= NULL_RTX
;
6624 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6627 if (s390_execute_label (insn
))
6628 addr
= s390_find_execute (pool
, insn
);
6630 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6631 get_pool_mode (pool_ref
));
6633 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6634 INSN_CODE (insn
) = -1;
6640 /* Free the pool. */
6641 s390_free_pool (pool
);
6644 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6645 We have decided we cannot use this pool, so revert all changes
6646 to the current function that were done by s390_mainpool_start. */
6648 s390_mainpool_cancel (struct constant_pool
*pool
)
6650 /* We didn't actually change the instruction stream, so simply
6651 free the pool memory. */
6652 s390_free_pool (pool
);
6656 /* Chunkify the literal pool. */
6658 #define S390_POOL_CHUNK_MIN 0xc00
6659 #define S390_POOL_CHUNK_MAX 0xe00
6661 static struct constant_pool
*
6662 s390_chunkify_start (void)
6664 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6667 rtx pending_ltrel
= NULL_RTX
;
6670 rtx (*gen_reload_base
) (rtx
, rtx
) =
6671 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6674 /* We need correct insn addresses. */
6676 shorten_branches (get_insns ());
6678 /* Scan all insns and move literals to pool chunks. */
6680 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6682 bool section_switch_p
= false;
6684 /* Check for pending LTREL_BASE. */
6687 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6690 gcc_assert (ltrel_base
== pending_ltrel
);
6691 pending_ltrel
= NULL_RTX
;
6695 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6698 curr_pool
= s390_start_pool (&pool_list
, insn
);
6700 s390_add_execute (curr_pool
, insn
);
6701 s390_add_pool_insn (curr_pool
, insn
);
6703 else if (GET_CODE (insn
) == INSN
|| CALL_P (insn
))
6705 rtx pool_ref
= NULL_RTX
;
6706 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6709 rtx constant
= get_pool_constant (pool_ref
);
6710 enum machine_mode mode
= get_pool_mode (pool_ref
);
6713 curr_pool
= s390_start_pool (&pool_list
, insn
);
6715 s390_add_constant (curr_pool
, constant
, mode
);
6716 s390_add_pool_insn (curr_pool
, insn
);
6718 /* Don't split the pool chunk between a LTREL_OFFSET load
6719 and the corresponding LTREL_BASE. */
6720 if (GET_CODE (constant
) == CONST
6721 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6722 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6724 gcc_assert (!pending_ltrel
);
6725 pending_ltrel
= pool_ref
;
6728 /* Make sure we do not split between a call and its
6729 corresponding CALL_ARG_LOCATION note. */
6732 rtx next
= NEXT_INSN (insn
);
6733 if (next
&& NOTE_P (next
)
6734 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
6739 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6742 s390_add_pool_insn (curr_pool
, insn
);
6743 /* An LTREL_BASE must follow within the same basic block. */
6744 gcc_assert (!pending_ltrel
);
6747 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6748 section_switch_p
= true;
6751 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6752 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6755 if (TARGET_CPU_ZARCH
)
6757 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6760 s390_end_pool (curr_pool
, NULL_RTX
);
6765 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6766 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6769 /* We will later have to insert base register reload insns.
6770 Those will have an effect on code size, which we need to
6771 consider here. This calculation makes rather pessimistic
6772 worst-case assumptions. */
6773 if (GET_CODE (insn
) == CODE_LABEL
)
6776 if (chunk_size
< S390_POOL_CHUNK_MIN
6777 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6778 && !section_switch_p
)
6781 /* Pool chunks can only be inserted after BARRIERs ... */
6782 if (GET_CODE (insn
) == BARRIER
)
6784 s390_end_pool (curr_pool
, insn
);
6789 /* ... so if we don't find one in time, create one. */
6790 else if (chunk_size
> S390_POOL_CHUNK_MAX
6791 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6792 || section_switch_p
)
6794 rtx label
, jump
, barrier
;
6796 if (!section_switch_p
)
6798 /* We can insert the barrier only after a 'real' insn. */
6799 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6801 if (get_attr_length (insn
) == 0)
6803 /* Don't separate LTREL_BASE from the corresponding
6804 LTREL_OFFSET load. */
6810 gcc_assert (!pending_ltrel
);
6812 /* The old pool has to end before the section switch
6813 note in order to make it part of the current
6815 insn
= PREV_INSN (insn
);
6818 label
= gen_label_rtx ();
6819 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6820 barrier
= emit_barrier_after (jump
);
6821 insn
= emit_label_after (label
, barrier
);
6822 JUMP_LABEL (jump
) = label
;
6823 LABEL_NUSES (label
) = 1;
6825 INSN_ADDRESSES_NEW (jump
, -1);
6826 INSN_ADDRESSES_NEW (barrier
, -1);
6827 INSN_ADDRESSES_NEW (insn
, -1);
6829 s390_end_pool (curr_pool
, barrier
);
6837 s390_end_pool (curr_pool
, NULL_RTX
);
6838 gcc_assert (!pending_ltrel
);
6840 /* Find all labels that are branched into
6841 from an insn belonging to a different chunk. */
6843 far_labels
= BITMAP_ALLOC (NULL
);
6845 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6847 /* Labels marked with LABEL_PRESERVE_P can be target
6848 of non-local jumps, so we have to mark them.
6849 The same holds for named labels.
6851 Don't do that, however, if it is the label before
6854 if (GET_CODE (insn
) == CODE_LABEL
6855 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6857 rtx vec_insn
= next_real_insn (insn
);
6858 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6859 PATTERN (vec_insn
) : NULL_RTX
;
6861 || !(GET_CODE (vec_pat
) == ADDR_VEC
6862 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6863 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6866 /* If we have a direct jump (conditional or unconditional)
6867 or a casesi jump, check all potential targets. */
6868 else if (GET_CODE (insn
) == JUMP_INSN
)
6870 rtx pat
= PATTERN (insn
);
6871 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6872 pat
= XVECEXP (pat
, 0, 0);
6874 if (GET_CODE (pat
) == SET
)
6876 rtx label
= JUMP_LABEL (insn
);
6879 if (s390_find_pool (pool_list
, label
)
6880 != s390_find_pool (pool_list
, insn
))
6881 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6884 else if (GET_CODE (pat
) == PARALLEL
6885 && XVECLEN (pat
, 0) == 2
6886 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6887 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6888 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6890 /* Find the jump table used by this casesi jump. */
6891 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6892 rtx vec_insn
= next_real_insn (vec_label
);
6893 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6894 PATTERN (vec_insn
) : NULL_RTX
;
6896 && (GET_CODE (vec_pat
) == ADDR_VEC
6897 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6899 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6901 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6903 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6905 if (s390_find_pool (pool_list
, label
)
6906 != s390_find_pool (pool_list
, insn
))
6907 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6914 /* Insert base register reload insns before every pool. */
6916 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6918 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6920 rtx insn
= curr_pool
->first_insn
;
6921 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6924 /* Insert base register reload insns at every far label. */
6926 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6927 if (GET_CODE (insn
) == CODE_LABEL
6928 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6930 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6933 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6935 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6940 BITMAP_FREE (far_labels
);
6943 /* Recompute insn addresses. */
6945 init_insn_lengths ();
6946 shorten_branches (get_insns ());
6951 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6952 After we have decided to use this list, finish implementing
6953 all changes to the current function as required. */
6956 s390_chunkify_finish (struct constant_pool
*pool_list
)
6958 struct constant_pool
*curr_pool
= NULL
;
6962 /* Replace all literal pool references. */
6964 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6967 replace_ltrel_base (&PATTERN (insn
));
6969 curr_pool
= s390_find_pool (pool_list
, insn
);
6973 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6975 rtx addr
, pool_ref
= NULL_RTX
;
6976 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6979 if (s390_execute_label (insn
))
6980 addr
= s390_find_execute (curr_pool
, insn
);
6982 addr
= s390_find_constant (curr_pool
,
6983 get_pool_constant (pool_ref
),
6984 get_pool_mode (pool_ref
));
6986 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6987 INSN_CODE (insn
) = -1;
6992 /* Dump out all literal pools. */
6994 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6995 s390_dump_pool (curr_pool
, 0);
6997 /* Free pool list. */
7001 struct constant_pool
*next
= pool_list
->next
;
7002 s390_free_pool (pool_list
);
7007 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7008 We have decided we cannot use this list, so revert all changes
7009 to the current function that were done by s390_chunkify_start. */
7012 s390_chunkify_cancel (struct constant_pool
*pool_list
)
7014 struct constant_pool
*curr_pool
= NULL
;
7017 /* Remove all pool placeholder insns. */
7019 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
7021 /* Did we insert an extra barrier? Remove it. */
7022 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
7023 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
7024 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
7026 if (jump
&& GET_CODE (jump
) == JUMP_INSN
7027 && barrier
&& GET_CODE (barrier
) == BARRIER
7028 && label
&& GET_CODE (label
) == CODE_LABEL
7029 && GET_CODE (PATTERN (jump
)) == SET
7030 && SET_DEST (PATTERN (jump
)) == pc_rtx
7031 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
7032 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
7035 remove_insn (barrier
);
7036 remove_insn (label
);
7039 remove_insn (curr_pool
->pool_insn
);
7042 /* Remove all base register reload insns. */
7044 for (insn
= get_insns (); insn
; )
7046 rtx next_insn
= NEXT_INSN (insn
);
7048 if (GET_CODE (insn
) == INSN
7049 && GET_CODE (PATTERN (insn
)) == SET
7050 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
7051 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
7057 /* Free pool list. */
7061 struct constant_pool
*next
= pool_list
->next
;
7062 s390_free_pool (pool_list
);
7067 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7070 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
7074 switch (GET_MODE_CLASS (mode
))
7077 case MODE_DECIMAL_FLOAT
:
7078 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
7080 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
7081 assemble_real (r
, mode
, align
);
7085 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
7086 mark_symbol_refs_as_used (exp
);
7095 /* Return an RTL expression representing the value of the return address
7096 for the frame COUNT steps up from the current frame. FRAME is the
7097 frame pointer of that frame. */
7100 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
7105 /* Without backchain, we fail for all but the current frame. */
7107 if (!TARGET_BACKCHAIN
&& count
> 0)
7110 /* For the current frame, we need to make sure the initial
7111 value of RETURN_REGNUM is actually saved. */
7115 /* On non-z architectures branch splitting could overwrite r14. */
7116 if (TARGET_CPU_ZARCH
)
7117 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
7120 cfun_frame_layout
.save_return_addr_p
= true;
7121 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
7125 if (TARGET_PACKED_STACK
)
7126 offset
= -2 * UNITS_PER_LONG
;
7128 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
7130 addr
= plus_constant (frame
, offset
);
7131 addr
= memory_address (Pmode
, addr
);
7132 return gen_rtx_MEM (Pmode
, addr
);
7135 /* Return an RTL expression representing the back chain stored in
7136 the current stack frame. */
7139 s390_back_chain_rtx (void)
7143 gcc_assert (TARGET_BACKCHAIN
);
7145 if (TARGET_PACKED_STACK
)
7146 chain
= plus_constant (stack_pointer_rtx
,
7147 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
7149 chain
= stack_pointer_rtx
;
7151 chain
= gen_rtx_MEM (Pmode
, chain
);
7155 /* Find first call clobbered register unused in a function.
7156 This could be used as base register in a leaf function
7157 or for holding the return address before epilogue. */
7160 find_unused_clobbered_reg (void)
7163 for (i
= 0; i
< 6; i
++)
7164 if (!df_regs_ever_live_p (i
))
7170 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7171 clobbered hard regs in SETREG. */
7174 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
7176 int *regs_ever_clobbered
= (int *)data
;
7177 unsigned int i
, regno
;
7178 enum machine_mode mode
= GET_MODE (setreg
);
7180 if (GET_CODE (setreg
) == SUBREG
)
7182 rtx inner
= SUBREG_REG (setreg
);
7183 if (!GENERAL_REG_P (inner
))
7185 regno
= subreg_regno (setreg
);
7187 else if (GENERAL_REG_P (setreg
))
7188 regno
= REGNO (setreg
);
7193 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7195 regs_ever_clobbered
[i
] = 1;
7198 /* Walks through all basic blocks of the current function looking
7199 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7200 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7201 each of those regs. */
7204 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
7210 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
7212 /* For non-leaf functions we have to consider all call clobbered regs to be
7214 if (!current_function_is_leaf
)
7216 for (i
= 0; i
< 16; i
++)
7217 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7220 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7221 this work is done by liveness analysis (mark_regs_live_at_end).
7222 Special care is needed for functions containing landing pads. Landing pads
7223 may use the eh registers, but the code which sets these registers is not
7224 contained in that function. Hence s390_regs_ever_clobbered is not able to
7225 deal with this automatically. */
7226 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7227 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7228 if (crtl
->calls_eh_return
7229 || (cfun
->machine
->has_landing_pad_p
7230 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7231 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7233 /* For nonlocal gotos all call-saved registers have to be saved.
7234 This flag is also set for the unwinding code in libgcc.
7235 See expand_builtin_unwind_init. For regs_ever_live this is done by
7237 if (cfun
->has_nonlocal_label
)
7238 for (i
= 0; i
< 16; i
++)
7239 if (!call_really_used_regs
[i
])
7240 regs_ever_clobbered
[i
] = 1;
7242 FOR_EACH_BB (cur_bb
)
7244 FOR_BB_INSNS (cur_bb
, cur_insn
)
7246 if (INSN_P (cur_insn
))
7247 note_stores (PATTERN (cur_insn
),
7248 s390_reg_clobbered_rtx
,
7249 regs_ever_clobbered
);
7254 /* Determine the frame area which actually has to be accessed
7255 in the function epilogue. The values are stored at the
7256 given pointers AREA_BOTTOM (address of the lowest used stack
7257 address) and AREA_TOP (address of the first item which does
7258 not belong to the stack frame). */
7261 s390_frame_area (int *area_bottom
, int *area_top
)
7269 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7271 b
= (cfun_frame_layout
.gprs_offset
7272 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7273 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7274 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7277 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7279 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7280 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7281 + cfun_frame_layout
.high_fprs
* 8));
7285 for (i
= 2; i
< 4; i
++)
7286 if (cfun_fpr_bit_p (i
))
7288 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7289 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7296 /* Fill cfun->machine with info about register usage of current function.
7297 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7300 s390_register_info (int clobbered_regs
[])
7304 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7305 cfun_frame_layout
.fpr_bitmap
= 0;
7306 cfun_frame_layout
.high_fprs
= 0;
7308 for (i
= 24; i
< 32; i
++)
7309 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7311 cfun_set_fpr_bit (i
- 16);
7312 cfun_frame_layout
.high_fprs
++;
7315 /* Find first and last gpr to be saved. We trust regs_ever_live
7316 data, except that we don't save and restore global registers.
7318 Also, all registers with special meaning to the compiler need
7319 to be handled extra. */
7321 s390_regs_ever_clobbered (clobbered_regs
);
7323 for (i
= 0; i
< 16; i
++)
7324 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7326 if (frame_pointer_needed
)
7327 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7330 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7331 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7333 clobbered_regs
[BASE_REGNUM
]
7334 |= (cfun
->machine
->base_reg
7335 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7337 clobbered_regs
[RETURN_REGNUM
]
7338 |= (!current_function_is_leaf
7339 || TARGET_TPF_PROFILING
7340 || cfun
->machine
->split_branches_pending_p
7341 || cfun_frame_layout
.save_return_addr_p
7342 || crtl
->calls_eh_return
7345 clobbered_regs
[STACK_POINTER_REGNUM
]
7346 |= (!current_function_is_leaf
7347 || TARGET_TPF_PROFILING
7348 || cfun_save_high_fprs_p
7349 || get_frame_size () > 0
7350 || cfun
->calls_alloca
7353 for (i
= 6; i
< 16; i
++)
7354 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7356 for (j
= 15; j
> i
; j
--)
7357 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7362 /* Nothing to save/restore. */
7363 cfun_frame_layout
.first_save_gpr_slot
= -1;
7364 cfun_frame_layout
.last_save_gpr_slot
= -1;
7365 cfun_frame_layout
.first_save_gpr
= -1;
7366 cfun_frame_layout
.first_restore_gpr
= -1;
7367 cfun_frame_layout
.last_save_gpr
= -1;
7368 cfun_frame_layout
.last_restore_gpr
= -1;
7372 /* Save slots for gprs from i to j. */
7373 cfun_frame_layout
.first_save_gpr_slot
= i
;
7374 cfun_frame_layout
.last_save_gpr_slot
= j
;
7376 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7377 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7379 if (clobbered_regs
[i
])
7382 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7383 if (clobbered_regs
[j
])
7386 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7388 /* Nothing to save/restore. */
7389 cfun_frame_layout
.first_save_gpr
= -1;
7390 cfun_frame_layout
.first_restore_gpr
= -1;
7391 cfun_frame_layout
.last_save_gpr
= -1;
7392 cfun_frame_layout
.last_restore_gpr
= -1;
7396 /* Save / Restore from gpr i to j. */
7397 cfun_frame_layout
.first_save_gpr
= i
;
7398 cfun_frame_layout
.first_restore_gpr
= i
;
7399 cfun_frame_layout
.last_save_gpr
= j
;
7400 cfun_frame_layout
.last_restore_gpr
= j
;
7406 /* Varargs functions need to save gprs 2 to 6. */
7407 if (cfun
->va_list_gpr_size
7408 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7410 int min_gpr
= crtl
->args
.info
.gprs
;
7411 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7412 if (max_gpr
> GP_ARG_NUM_REG
)
7413 max_gpr
= GP_ARG_NUM_REG
;
7415 if (cfun_frame_layout
.first_save_gpr
== -1
7416 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7418 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7419 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7422 if (cfun_frame_layout
.last_save_gpr
== -1
7423 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7425 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7426 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7430 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7431 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7432 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7434 int min_fpr
= crtl
->args
.info
.fprs
;
7435 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7436 if (max_fpr
> FP_ARG_NUM_REG
)
7437 max_fpr
= FP_ARG_NUM_REG
;
7439 /* ??? This is currently required to ensure proper location
7440 of the fpr save slots within the va_list save area. */
7441 if (TARGET_PACKED_STACK
)
7444 for (i
= min_fpr
; i
< max_fpr
; i
++)
7445 cfun_set_fpr_bit (i
);
7450 for (i
= 2; i
< 4; i
++)
7451 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7452 cfun_set_fpr_bit (i
);
7455 /* Fill cfun->machine with info about frame of current function. */
7458 s390_frame_info (void)
7462 cfun_frame_layout
.frame_size
= get_frame_size ();
7463 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7464 fatal_error ("total size of local variables exceeds architecture limit");
7466 if (!TARGET_PACKED_STACK
)
7468 cfun_frame_layout
.backchain_offset
= 0;
7469 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7470 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7471 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7472 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7475 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7477 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7479 cfun_frame_layout
.gprs_offset
7480 = (cfun_frame_layout
.backchain_offset
7481 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7486 cfun_frame_layout
.f4_offset
7487 = (cfun_frame_layout
.gprs_offset
7488 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7490 cfun_frame_layout
.f0_offset
7491 = (cfun_frame_layout
.f4_offset
7492 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7496 /* On 31 bit we have to care about alignment of the
7497 floating point regs to provide fastest access. */
7498 cfun_frame_layout
.f0_offset
7499 = ((cfun_frame_layout
.gprs_offset
7500 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7501 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7503 cfun_frame_layout
.f4_offset
7504 = (cfun_frame_layout
.f0_offset
7505 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7508 else /* no backchain */
7510 cfun_frame_layout
.f4_offset
7511 = (STACK_POINTER_OFFSET
7512 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7514 cfun_frame_layout
.f0_offset
7515 = (cfun_frame_layout
.f4_offset
7516 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7518 cfun_frame_layout
.gprs_offset
7519 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7522 if (current_function_is_leaf
7523 && !TARGET_TPF_PROFILING
7524 && cfun_frame_layout
.frame_size
== 0
7525 && !cfun_save_high_fprs_p
7526 && !cfun
->calls_alloca
7530 if (!TARGET_PACKED_STACK
)
7531 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7532 + crtl
->outgoing_args_size
7533 + cfun_frame_layout
.high_fprs
* 8);
7536 if (TARGET_BACKCHAIN
)
7537 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7539 /* No alignment trouble here because f8-f15 are only saved under
7541 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7542 cfun_frame_layout
.f4_offset
),
7543 cfun_frame_layout
.gprs_offset
)
7544 - cfun_frame_layout
.high_fprs
* 8);
7546 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7548 for (i
= 0; i
< 8; i
++)
7549 if (cfun_fpr_bit_p (i
))
7550 cfun_frame_layout
.frame_size
+= 8;
7552 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7554 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7555 the frame size to sustain 8 byte alignment of stack frames. */
7556 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7557 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7558 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7560 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7564 /* Generate frame layout. Fills in register and frame data for the current
7565 function in cfun->machine. This routine can be called multiple times;
7566 it will re-do the complete frame layout every time. */
7569 s390_init_frame_layout (void)
7571 HOST_WIDE_INT frame_size
;
7573 int clobbered_regs
[16];
7575 /* On S/390 machines, we may need to perform branch splitting, which
7576 will require both base and return address register. We have no
7577 choice but to assume we're going to need them until right at the
7578 end of the machine dependent reorg phase. */
7579 if (!TARGET_CPU_ZARCH
)
7580 cfun
->machine
->split_branches_pending_p
= true;
7584 frame_size
= cfun_frame_layout
.frame_size
;
7586 /* Try to predict whether we'll need the base register. */
7587 base_used
= cfun
->machine
->split_branches_pending_p
7588 || crtl
->uses_const_pool
7589 || (!DISP_IN_RANGE (frame_size
)
7590 && !CONST_OK_FOR_K (frame_size
));
7592 /* Decide which register to use as literal pool base. In small
7593 leaf functions, try to use an unused call-clobbered register
7594 as base register to avoid save/restore overhead. */
7596 cfun
->machine
->base_reg
= NULL_RTX
;
7597 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7598 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7600 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7602 s390_register_info (clobbered_regs
);
7605 while (frame_size
!= cfun_frame_layout
.frame_size
);
7608 /* Update frame layout. Recompute actual register save data based on
7609 current info and update regs_ever_live for the special registers.
7610 May be called multiple times, but may never cause *more* registers
7611 to be saved than s390_init_frame_layout allocated room for. */
7614 s390_update_frame_layout (void)
7616 int clobbered_regs
[16];
7618 s390_register_info (clobbered_regs
);
7620 df_set_regs_ever_live (BASE_REGNUM
,
7621 clobbered_regs
[BASE_REGNUM
] ? true : false);
7622 df_set_regs_ever_live (RETURN_REGNUM
,
7623 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7624 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7625 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7627 if (cfun
->machine
->base_reg
)
7628 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7631 /* Return true if it is legal to put a value with MODE into REGNO. */
7634 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7636 switch (REGNO_REG_CLASS (regno
))
7639 if (REGNO_PAIR_OK (regno
, mode
))
7641 if (mode
== SImode
|| mode
== DImode
)
7644 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7649 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7654 if (REGNO_PAIR_OK (regno
, mode
))
7657 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7662 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7666 if (REGNO_PAIR_OK (regno
, mode
))
7668 if (mode
== SImode
|| mode
== Pmode
)
7679 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7682 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7684 /* Once we've decided upon a register to use as base register, it must
7685 no longer be used for any other purpose. */
7686 if (cfun
->machine
->base_reg
)
7687 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7688 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7694 /* Maximum number of registers to represent a value of mode MODE
7695 in a register of class RCLASS. */
7698 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7703 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7704 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7706 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7708 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7712 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7715 /* Return true if register FROM can be eliminated via register TO. */
7718 s390_can_eliminate (const int from
, const int to
)
7720 /* On zSeries machines, we have not marked the base register as fixed.
7721 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7722 If a function requires the base register, we say here that this
7723 elimination cannot be performed. This will cause reload to free
7724 up the base register (as if it were fixed). On the other hand,
7725 if the current function does *not* require the base register, we
7726 say here the elimination succeeds, which in turn allows reload
7727 to allocate the base register for any other purpose. */
7728 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7730 if (TARGET_CPU_ZARCH
)
7732 s390_init_frame_layout ();
7733 return cfun
->machine
->base_reg
== NULL_RTX
;
7739 /* Everything else must point into the stack frame. */
7740 gcc_assert (to
== STACK_POINTER_REGNUM
7741 || to
== HARD_FRAME_POINTER_REGNUM
);
7743 gcc_assert (from
== FRAME_POINTER_REGNUM
7744 || from
== ARG_POINTER_REGNUM
7745 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7747 /* Make sure we actually saved the return address. */
7748 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7749 if (!crtl
->calls_eh_return
7751 && !cfun_frame_layout
.save_return_addr_p
)
7757 /* Return offset between register FROM and TO initially after prolog. */
7760 s390_initial_elimination_offset (int from
, int to
)
7762 HOST_WIDE_INT offset
;
7765 /* ??? Why are we called for non-eliminable pairs? */
7766 if (!s390_can_eliminate (from
, to
))
7771 case FRAME_POINTER_REGNUM
:
7772 offset
= (get_frame_size()
7773 + STACK_POINTER_OFFSET
7774 + crtl
->outgoing_args_size
);
7777 case ARG_POINTER_REGNUM
:
7778 s390_init_frame_layout ();
7779 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7782 case RETURN_ADDRESS_POINTER_REGNUM
:
7783 s390_init_frame_layout ();
7784 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7785 gcc_assert (index
>= 0);
7786 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7787 offset
+= index
* UNITS_PER_LONG
;
7801 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7802 to register BASE. Return generated insn. */
7805 save_fpr (rtx base
, int offset
, int regnum
)
7808 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7810 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7811 set_mem_alias_set (addr
, get_varargs_alias_set ());
7813 set_mem_alias_set (addr
, get_frame_alias_set ());
7815 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7818 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7819 to register BASE. Return generated insn. */
7822 restore_fpr (rtx base
, int offset
, int regnum
)
7825 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7826 set_mem_alias_set (addr
, get_frame_alias_set ());
7828 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7831 /* Return true if REGNO is a global register, but not one
7832 of the special ones that need to be saved/restored in anyway. */
7835 global_not_special_regno_p (int regno
)
7837 return (global_regs
[regno
]
7838 /* These registers are special and need to be
7839 restored in any case. */
7840 && !(regno
== STACK_POINTER_REGNUM
7841 || regno
== RETURN_REGNUM
7842 || regno
== BASE_REGNUM
7843 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7846 /* Generate insn to save registers FIRST to LAST into
7847 the register save area located at offset OFFSET
7848 relative to register BASE. */
7851 save_gprs (rtx base
, int offset
, int first
, int last
)
7853 rtx addr
, insn
, note
;
7856 addr
= plus_constant (base
, offset
);
7857 addr
= gen_rtx_MEM (Pmode
, addr
);
7859 set_mem_alias_set (addr
, get_frame_alias_set ());
7861 /* Special-case single register. */
7865 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7867 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7869 if (!global_not_special_regno_p (first
))
7870 RTX_FRAME_RELATED_P (insn
) = 1;
7875 insn
= gen_store_multiple (addr
,
7876 gen_rtx_REG (Pmode
, first
),
7877 GEN_INT (last
- first
+ 1));
7879 if (first
<= 6 && cfun
->stdarg
)
7880 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7882 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7885 set_mem_alias_set (mem
, get_varargs_alias_set ());
7888 /* We need to set the FRAME_RELATED flag on all SETs
7889 inside the store-multiple pattern.
7891 However, we must not emit DWARF records for registers 2..5
7892 if they are stored for use by variable arguments ...
7894 ??? Unfortunately, it is not enough to simply not the
7895 FRAME_RELATED flags for those SETs, because the first SET
7896 of the PARALLEL is always treated as if it had the flag
7897 set, even if it does not. Therefore we emit a new pattern
7898 without those registers as REG_FRAME_RELATED_EXPR note. */
7900 if (first
>= 6 && !global_not_special_regno_p (first
))
7902 rtx pat
= PATTERN (insn
);
7904 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7905 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7906 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7908 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7910 RTX_FRAME_RELATED_P (insn
) = 1;
7916 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7917 if (!global_not_special_regno_p (start
))
7923 addr
= plus_constant (base
, offset
+ (start
- first
) * UNITS_PER_LONG
);
7924 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7925 gen_rtx_REG (Pmode
, start
),
7926 GEN_INT (last
- start
+ 1));
7927 note
= PATTERN (note
);
7929 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7931 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7932 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7933 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7935 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7937 RTX_FRAME_RELATED_P (insn
) = 1;
7943 /* Generate insn to restore registers FIRST to LAST from
7944 the register save area located at offset OFFSET
7945 relative to register BASE. */
7948 restore_gprs (rtx base
, int offset
, int first
, int last
)
7952 addr
= plus_constant (base
, offset
);
7953 addr
= gen_rtx_MEM (Pmode
, addr
);
7954 set_mem_alias_set (addr
, get_frame_alias_set ());
7956 /* Special-case single register. */
7960 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7962 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7967 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7969 GEN_INT (last
- first
+ 1));
7973 /* Return insn sequence to load the GOT register. */
7975 static GTY(()) rtx got_symbol
;
7977 s390_load_got (void)
7983 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7984 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7989 if (TARGET_CPU_ZARCH
)
7991 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7997 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7998 UNSPEC_LTREL_OFFSET
);
7999 offset
= gen_rtx_CONST (Pmode
, offset
);
8000 offset
= force_const_mem (Pmode
, offset
);
8002 emit_move_insn (pic_offset_table_rtx
, offset
);
8004 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
8006 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
8008 emit_move_insn (pic_offset_table_rtx
, offset
);
8011 insns
= get_insns ();
8016 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8017 and the change to the stack pointer. */
8020 s390_emit_stack_tie (void)
8022 rtx mem
= gen_frame_mem (BLKmode
,
8023 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
8025 emit_insn (gen_stack_tie (mem
));
8028 /* Expand the prologue into a bunch of separate insns. */
8031 s390_emit_prologue (void)
8039 /* Complete frame layout. */
8041 s390_update_frame_layout ();
8043 /* Annotate all constant pool references to let the scheduler know
8044 they implicitly use the base register. */
8046 push_topmost_sequence ();
8048 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8051 annotate_constant_pool_refs (&PATTERN (insn
));
8052 df_insn_rescan (insn
);
8055 pop_topmost_sequence ();
8057 /* Choose best register to use for temp use within prologue.
8058 See below for why TPF must use the register 1. */
8060 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
8061 && !current_function_is_leaf
8062 && !TARGET_TPF_PROFILING
)
8063 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8065 temp_reg
= gen_rtx_REG (Pmode
, 1);
8067 /* Save call saved gprs. */
8068 if (cfun_frame_layout
.first_save_gpr
!= -1)
8070 insn
= save_gprs (stack_pointer_rtx
,
8071 cfun_frame_layout
.gprs_offset
+
8072 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
8073 - cfun_frame_layout
.first_save_gpr_slot
),
8074 cfun_frame_layout
.first_save_gpr
,
8075 cfun_frame_layout
.last_save_gpr
);
8079 /* Dummy insn to mark literal pool slot. */
8081 if (cfun
->machine
->base_reg
)
8082 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
8084 offset
= cfun_frame_layout
.f0_offset
;
8086 /* Save f0 and f2. */
8087 for (i
= 0; i
< 2; i
++)
8089 if (cfun_fpr_bit_p (i
))
8091 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8094 else if (!TARGET_PACKED_STACK
)
8098 /* Save f4 and f6. */
8099 offset
= cfun_frame_layout
.f4_offset
;
8100 for (i
= 2; i
< 4; i
++)
8102 if (cfun_fpr_bit_p (i
))
8104 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8107 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8108 therefore are not frame related. */
8109 if (!call_really_used_regs
[i
+ 16])
8110 RTX_FRAME_RELATED_P (insn
) = 1;
8112 else if (!TARGET_PACKED_STACK
)
8116 if (TARGET_PACKED_STACK
8117 && cfun_save_high_fprs_p
8118 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
8120 offset
= (cfun_frame_layout
.f8_offset
8121 + (cfun_frame_layout
.high_fprs
- 1) * 8);
8123 for (i
= 15; i
> 7 && offset
>= 0; i
--)
8124 if (cfun_fpr_bit_p (i
))
8126 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8128 RTX_FRAME_RELATED_P (insn
) = 1;
8131 if (offset
>= cfun_frame_layout
.f8_offset
)
8135 if (!TARGET_PACKED_STACK
)
8136 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
8138 if (flag_stack_usage
)
8139 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
8141 /* Decrement stack pointer. */
8143 if (cfun_frame_layout
.frame_size
> 0)
8145 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8148 if (s390_stack_size
)
8150 HOST_WIDE_INT stack_guard
;
8152 if (s390_stack_guard
)
8153 stack_guard
= s390_stack_guard
;
8156 /* If no value for stack guard is provided the smallest power of 2
8157 larger than the current frame size is chosen. */
8159 while (stack_guard
< cfun_frame_layout
.frame_size
)
8163 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
8165 warning (0, "frame size of function %qs is "
8166 HOST_WIDE_INT_PRINT_DEC
8167 " bytes exceeding user provided stack limit of "
8168 HOST_WIDE_INT_PRINT_DEC
" bytes. "
8169 "An unconditional trap is added.",
8170 current_function_name(), cfun_frame_layout
.frame_size
,
8172 emit_insn (gen_trap ());
8176 /* stack_guard has to be smaller than s390_stack_size.
8177 Otherwise we would emit an AND with zero which would
8178 not match the test under mask pattern. */
8179 if (stack_guard
>= s390_stack_size
)
8181 warning (0, "frame size of function %qs is "
8182 HOST_WIDE_INT_PRINT_DEC
8183 " bytes which is more than half the stack size. "
8184 "The dynamic check would not be reliable. "
8185 "No check emitted for this function.",
8186 current_function_name(),
8187 cfun_frame_layout
.frame_size
);
8191 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8192 & ~(stack_guard
- 1));
8194 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8195 GEN_INT (stack_check_mask
));
8197 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8199 t
, const0_rtx
, const0_rtx
));
8201 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8203 t
, const0_rtx
, const0_rtx
));
8208 if (s390_warn_framesize
> 0
8209 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8210 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
8211 current_function_name (), cfun_frame_layout
.frame_size
);
8213 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8214 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8216 /* Save incoming stack pointer into temp reg. */
8217 if (TARGET_BACKCHAIN
|| next_fpr
)
8218 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8220 /* Subtract frame size from stack pointer. */
8222 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8224 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8225 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8227 insn
= emit_insn (insn
);
8231 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8232 frame_off
= force_const_mem (Pmode
, frame_off
);
8234 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8235 annotate_constant_pool_refs (&PATTERN (insn
));
8238 RTX_FRAME_RELATED_P (insn
) = 1;
8239 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8240 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8241 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8242 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8245 /* Set backchain. */
8247 if (TARGET_BACKCHAIN
)
8249 if (cfun_frame_layout
.backchain_offset
)
8250 addr
= gen_rtx_MEM (Pmode
,
8251 plus_constant (stack_pointer_rtx
,
8252 cfun_frame_layout
.backchain_offset
));
8254 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8255 set_mem_alias_set (addr
, get_frame_alias_set ());
8256 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8259 /* If we support non-call exceptions (e.g. for Java),
8260 we need to make sure the backchain pointer is set up
8261 before any possibly trapping memory access. */
8262 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8264 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8265 emit_clobber (addr
);
8269 /* Save fprs 8 - 15 (64 bit ABI). */
8271 if (cfun_save_high_fprs_p
&& next_fpr
)
8273 /* If the stack might be accessed through a different register
8274 we have to make sure that the stack pointer decrement is not
8275 moved below the use of the stack slots. */
8276 s390_emit_stack_tie ();
8278 insn
= emit_insn (gen_add2_insn (temp_reg
,
8279 GEN_INT (cfun_frame_layout
.f8_offset
)));
8283 for (i
= 24; i
<= next_fpr
; i
++)
8284 if (cfun_fpr_bit_p (i
- 16))
8286 rtx addr
= plus_constant (stack_pointer_rtx
,
8287 cfun_frame_layout
.frame_size
8288 + cfun_frame_layout
.f8_offset
8291 insn
= save_fpr (temp_reg
, offset
, i
);
8293 RTX_FRAME_RELATED_P (insn
) = 1;
8294 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8295 gen_rtx_SET (VOIDmode
,
8296 gen_rtx_MEM (DFmode
, addr
),
8297 gen_rtx_REG (DFmode
, i
)));
8301 /* Set frame pointer, if needed. */
8303 if (frame_pointer_needed
)
8305 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8306 RTX_FRAME_RELATED_P (insn
) = 1;
8309 /* Set up got pointer, if needed. */
8311 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8313 rtx insns
= s390_load_got ();
8315 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8316 annotate_constant_pool_refs (&PATTERN (insn
));
8321 if (TARGET_TPF_PROFILING
)
8323 /* Generate a BAS instruction to serve as a function
8324 entry intercept to facilitate the use of tracing
8325 algorithms located at the branch target. */
8326 emit_insn (gen_prologue_tpf ());
8328 /* Emit a blockage here so that all code
8329 lies between the profiling mechanisms. */
8330 emit_insn (gen_blockage ());
8334 /* Expand the epilogue into a bunch of separate insns. */
8337 s390_emit_epilogue (bool sibcall
)
8339 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8340 int area_bottom
, area_top
, offset
= 0;
8345 if (TARGET_TPF_PROFILING
)
8348 /* Generate a BAS instruction to serve as a function
8349 entry intercept to facilitate the use of tracing
8350 algorithms located at the branch target. */
8352 /* Emit a blockage here so that all code
8353 lies between the profiling mechanisms. */
8354 emit_insn (gen_blockage ());
8356 emit_insn (gen_epilogue_tpf ());
8359 /* Check whether to use frame or stack pointer for restore. */
8361 frame_pointer
= (frame_pointer_needed
8362 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8364 s390_frame_area (&area_bottom
, &area_top
);
8366 /* Check whether we can access the register save area.
8367 If not, increment the frame pointer as required. */
8369 if (area_top
<= area_bottom
)
8371 /* Nothing to restore. */
8373 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8374 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8376 /* Area is in range. */
8377 offset
= cfun_frame_layout
.frame_size
;
8381 rtx insn
, frame_off
, cfa
;
8383 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8384 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8386 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8387 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8388 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8390 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8391 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8392 insn
= emit_insn (insn
);
8396 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8397 frame_off
= force_const_mem (Pmode
, frame_off
);
8399 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8400 annotate_constant_pool_refs (&PATTERN (insn
));
8402 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8403 RTX_FRAME_RELATED_P (insn
) = 1;
8406 /* Restore call saved fprs. */
8410 if (cfun_save_high_fprs_p
)
8412 next_offset
= cfun_frame_layout
.f8_offset
;
8413 for (i
= 24; i
< 32; i
++)
8415 if (cfun_fpr_bit_p (i
- 16))
8417 restore_fpr (frame_pointer
,
8418 offset
+ next_offset
, i
);
8420 = alloc_reg_note (REG_CFA_RESTORE
,
8421 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8430 next_offset
= cfun_frame_layout
.f4_offset
;
8431 for (i
= 18; i
< 20; i
++)
8433 if (cfun_fpr_bit_p (i
- 16))
8435 restore_fpr (frame_pointer
,
8436 offset
+ next_offset
, i
);
8438 = alloc_reg_note (REG_CFA_RESTORE
,
8439 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8442 else if (!TARGET_PACKED_STACK
)
8448 /* Return register. */
8450 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8452 /* Restore call saved gprs. */
8454 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8459 /* Check for global register and save them
8460 to stack location from where they get restored. */
8462 for (i
= cfun_frame_layout
.first_restore_gpr
;
8463 i
<= cfun_frame_layout
.last_restore_gpr
;
8466 if (global_not_special_regno_p (i
))
8468 addr
= plus_constant (frame_pointer
,
8469 offset
+ cfun_frame_layout
.gprs_offset
8470 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8472 addr
= gen_rtx_MEM (Pmode
, addr
);
8473 set_mem_alias_set (addr
, get_frame_alias_set ());
8474 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8478 = alloc_reg_note (REG_CFA_RESTORE
,
8479 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8484 /* Fetch return address from stack before load multiple,
8485 this will do good for scheduling. */
8487 if (cfun_frame_layout
.save_return_addr_p
8488 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8489 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8491 int return_regnum
= find_unused_clobbered_reg();
8494 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8496 addr
= plus_constant (frame_pointer
,
8497 offset
+ cfun_frame_layout
.gprs_offset
8499 - cfun_frame_layout
.first_save_gpr_slot
)
8501 addr
= gen_rtx_MEM (Pmode
, addr
);
8502 set_mem_alias_set (addr
, get_frame_alias_set ());
8503 emit_move_insn (return_reg
, addr
);
8507 insn
= restore_gprs (frame_pointer
,
8508 offset
+ cfun_frame_layout
.gprs_offset
8509 + (cfun_frame_layout
.first_restore_gpr
8510 - cfun_frame_layout
.first_save_gpr_slot
)
8512 cfun_frame_layout
.first_restore_gpr
,
8513 cfun_frame_layout
.last_restore_gpr
);
8514 insn
= emit_insn (insn
);
8515 REG_NOTES (insn
) = cfa_restores
;
8516 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8517 plus_constant (stack_pointer_rtx
, STACK_POINTER_OFFSET
));
8518 RTX_FRAME_RELATED_P (insn
) = 1;
8524 /* Return to caller. */
8526 p
= rtvec_alloc (2);
8528 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
8529 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8530 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8535 /* Return the size in bytes of a function argument of
8536 type TYPE and/or mode MODE. At least one of TYPE or
8537 MODE must be specified. */
8540 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8543 return int_size_in_bytes (type
);
8545 /* No type info available for some library calls ... */
8546 if (mode
!= BLKmode
)
8547 return GET_MODE_SIZE (mode
);
8549 /* If we have neither type nor mode, abort */
8553 /* Return true if a function argument of type TYPE and mode MODE
8554 is to be passed in a floating-point register, if available. */
8557 s390_function_arg_float (enum machine_mode mode
, const_tree type
)
8559 int size
= s390_function_arg_size (mode
, type
);
8563 /* Soft-float changes the ABI: no floating-point registers are used. */
8564 if (TARGET_SOFT_FLOAT
)
8567 /* No type info available for some library calls ... */
8569 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8571 /* The ABI says that record types with a single member are treated
8572 just like that member would be. */
8573 while (TREE_CODE (type
) == RECORD_TYPE
)
8575 tree field
, single
= NULL_TREE
;
8577 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8579 if (TREE_CODE (field
) != FIELD_DECL
)
8582 if (single
== NULL_TREE
)
8583 single
= TREE_TYPE (field
);
8588 if (single
== NULL_TREE
)
8594 return TREE_CODE (type
) == REAL_TYPE
;
8597 /* Return true if a function argument of type TYPE and mode MODE
8598 is to be passed in an integer register, or a pair of integer
8599 registers, if available. */
8602 s390_function_arg_integer (enum machine_mode mode
, const_tree type
)
8604 int size
= s390_function_arg_size (mode
, type
);
8608 /* No type info available for some library calls ... */
8610 return GET_MODE_CLASS (mode
) == MODE_INT
8611 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8613 /* We accept small integral (and similar) types. */
8614 if (INTEGRAL_TYPE_P (type
)
8615 || POINTER_TYPE_P (type
)
8616 || TREE_CODE (type
) == NULLPTR_TYPE
8617 || TREE_CODE (type
) == OFFSET_TYPE
8618 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8621 /* We also accept structs of size 1, 2, 4, 8 that are not
8622 passed in floating-point registers. */
8623 if (AGGREGATE_TYPE_P (type
)
8624 && exact_log2 (size
) >= 0
8625 && !s390_function_arg_float (mode
, type
))
8631 /* Return 1 if a function argument of type TYPE and mode MODE
8632 is to be passed by reference. The ABI specifies that only
8633 structures of size 1, 2, 4, or 8 bytes are passed by value,
8634 all other structures (and complex numbers) are passed by
8638 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
8639 enum machine_mode mode
, const_tree type
,
8640 bool named ATTRIBUTE_UNUSED
)
8642 int size
= s390_function_arg_size (mode
, type
);
8648 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8651 if (TREE_CODE (type
) == COMPLEX_TYPE
8652 || TREE_CODE (type
) == VECTOR_TYPE
)
8659 /* Update the data in CUM to advance over an argument of mode MODE and
8660 data type TYPE. (TYPE is null for libcalls where that information
8661 may not be available.). The boolean NAMED specifies whether the
8662 argument is a named argument (as opposed to an unnamed argument
8663 matching an ellipsis). */
8666 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8667 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8669 if (s390_function_arg_float (mode
, type
))
8673 else if (s390_function_arg_integer (mode
, type
))
8675 int size
= s390_function_arg_size (mode
, type
);
8676 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8682 /* Define where to put the arguments to a function.
8683 Value is zero to push the argument on the stack,
8684 or a hard register in which to store the argument.
8686 MODE is the argument's machine mode.
8687 TYPE is the data type of the argument (as a tree).
8688 This is null for libcalls where that information may
8690 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8691 the preceding args and about the function being called.
8692 NAMED is nonzero if this argument is a named parameter
8693 (otherwise it is an extra parameter matching an ellipsis).
8695 On S/390, we use general purpose registers 2 through 6 to
8696 pass integer, pointer, and certain structure arguments, and
8697 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8698 to pass floating point arguments. All remaining arguments
8699 are pushed to the stack. */
8702 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8703 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8705 if (s390_function_arg_float (mode
, type
))
8707 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8710 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8712 else if (s390_function_arg_integer (mode
, type
))
8714 int size
= s390_function_arg_size (mode
, type
);
8715 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8717 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8719 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8720 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8721 else if (n_gprs
== 2)
8723 rtvec p
= rtvec_alloc (2);
8726 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8729 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8732 return gen_rtx_PARALLEL (mode
, p
);
8736 /* After the real arguments, expand_call calls us once again
8737 with a void_type_node type. Whatever we return here is
8738 passed as operand 2 to the call expanders.
8740 We don't need this feature ... */
8741 else if (type
== void_type_node
)
8747 /* Return true if return values of type TYPE should be returned
8748 in a memory buffer whose address is passed by the caller as
8749 hidden first argument. */
8752 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8754 /* We accept small integral (and similar) types. */
8755 if (INTEGRAL_TYPE_P (type
)
8756 || POINTER_TYPE_P (type
)
8757 || TREE_CODE (type
) == OFFSET_TYPE
8758 || TREE_CODE (type
) == REAL_TYPE
)
8759 return int_size_in_bytes (type
) > 8;
8761 /* Aggregates and similar constructs are always returned
8763 if (AGGREGATE_TYPE_P (type
)
8764 || TREE_CODE (type
) == COMPLEX_TYPE
8765 || TREE_CODE (type
) == VECTOR_TYPE
)
8768 /* ??? We get called on all sorts of random stuff from
8769 aggregate_value_p. We can't abort, but it's not clear
8770 what's safe to return. Pretend it's a struct I guess. */
8774 /* Function arguments and return values are promoted to word size. */
8776 static enum machine_mode
8777 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8779 const_tree fntype ATTRIBUTE_UNUSED
,
8780 int for_return ATTRIBUTE_UNUSED
)
8782 if (INTEGRAL_MODE_P (mode
)
8783 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8785 if (POINTER_TYPE_P (type
))
8786 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8793 /* Define where to return a (scalar) value of type RET_TYPE.
8794 If RET_TYPE is null, define where to return a (scalar)
8795 value of mode MODE from a libcall. */
8798 s390_function_and_libcall_value (enum machine_mode mode
,
8799 const_tree ret_type
,
8800 const_tree fntype_or_decl
,
8801 bool outgoing ATTRIBUTE_UNUSED
)
8803 /* For normal functions perform the promotion as
8804 promote_function_mode would do. */
8807 int unsignedp
= TYPE_UNSIGNED (ret_type
);
8808 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
8812 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8813 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8815 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8816 return gen_rtx_REG (mode
, 16);
8817 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8818 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8819 return gen_rtx_REG (mode
, 2);
8820 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8822 /* This case is triggered when returning a 64 bit value with
8823 -m31 -mzarch. Although the value would fit into a single
8824 register it has to be forced into a 32 bit register pair in
8825 order to match the ABI. */
8826 rtvec p
= rtvec_alloc (2);
8829 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8831 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8833 return gen_rtx_PARALLEL (mode
, p
);
8839 /* Define where to return a scalar return value of type RET_TYPE. */
8842 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
8845 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
8846 fn_decl_or_type
, outgoing
);
8849 /* Define where to return a scalar libcall return value of mode
8853 s390_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
8855 return s390_function_and_libcall_value (mode
, NULL_TREE
,
8860 /* Create and return the va_list datatype.
8862 On S/390, va_list is an array type equivalent to
8864 typedef struct __va_list_tag
8868 void *__overflow_arg_area;
8869 void *__reg_save_area;
8872 where __gpr and __fpr hold the number of general purpose
8873 or floating point arguments used up to now, respectively,
8874 __overflow_arg_area points to the stack location of the
8875 next argument passed on the stack, and __reg_save_area
8876 always points to the start of the register area in the
8877 call frame of the current function. The function prologue
8878 saves all registers used for argument passing into this
8879 area if the function uses variable arguments. */
8882 s390_build_builtin_va_list (void)
8884 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8886 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8889 build_decl (BUILTINS_LOCATION
,
8890 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8892 f_gpr
= build_decl (BUILTINS_LOCATION
,
8893 FIELD_DECL
, get_identifier ("__gpr"),
8894 long_integer_type_node
);
8895 f_fpr
= build_decl (BUILTINS_LOCATION
,
8896 FIELD_DECL
, get_identifier ("__fpr"),
8897 long_integer_type_node
);
8898 f_ovf
= build_decl (BUILTINS_LOCATION
,
8899 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8901 f_sav
= build_decl (BUILTINS_LOCATION
,
8902 FIELD_DECL
, get_identifier ("__reg_save_area"),
8905 va_list_gpr_counter_field
= f_gpr
;
8906 va_list_fpr_counter_field
= f_fpr
;
8908 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8909 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8910 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8911 DECL_FIELD_CONTEXT (f_sav
) = record
;
8913 TYPE_STUB_DECL (record
) = type_decl
;
8914 TYPE_NAME (record
) = type_decl
;
8915 TYPE_FIELDS (record
) = f_gpr
;
8916 DECL_CHAIN (f_gpr
) = f_fpr
;
8917 DECL_CHAIN (f_fpr
) = f_ovf
;
8918 DECL_CHAIN (f_ovf
) = f_sav
;
8920 layout_type (record
);
8922 /* The correct type is an array type of one element. */
8923 return build_array_type (record
, build_index_type (size_zero_node
));
8926 /* Implement va_start by filling the va_list structure VALIST.
8927 STDARG_P is always true, and ignored.
8928 NEXTARG points to the first anonymous stack argument.
8930 The following global variables are used to initialize
8931 the va_list structure:
8934 holds number of gprs and fprs used for named arguments.
8935 crtl->args.arg_offset_rtx:
8936 holds the offset of the first anonymous stack argument
8937 (relative to the virtual arg pointer). */
8940 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8942 HOST_WIDE_INT n_gpr
, n_fpr
;
8944 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8945 tree gpr
, fpr
, ovf
, sav
, t
;
8947 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8948 f_fpr
= DECL_CHAIN (f_gpr
);
8949 f_ovf
= DECL_CHAIN (f_fpr
);
8950 f_sav
= DECL_CHAIN (f_ovf
);
8952 valist
= build_simple_mem_ref (valist
);
8953 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8954 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8955 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8956 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8958 /* Count number of gp and fp argument registers used. */
8960 n_gpr
= crtl
->args
.info
.gprs
;
8961 n_fpr
= crtl
->args
.info
.fprs
;
8963 if (cfun
->va_list_gpr_size
)
8965 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8966 build_int_cst (NULL_TREE
, n_gpr
));
8967 TREE_SIDE_EFFECTS (t
) = 1;
8968 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8971 if (cfun
->va_list_fpr_size
)
8973 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8974 build_int_cst (NULL_TREE
, n_fpr
));
8975 TREE_SIDE_EFFECTS (t
) = 1;
8976 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8979 /* Find the overflow area. */
8980 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8981 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8983 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8985 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8986 off
= off
< 0 ? 0 : off
;
8987 if (TARGET_DEBUG_ARG
)
8988 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8989 (int)n_gpr
, (int)n_fpr
, off
);
8991 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8993 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8994 TREE_SIDE_EFFECTS (t
) = 1;
8995 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8998 /* Find the register save area. */
8999 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
9000 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
9002 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
9003 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
9004 size_int (-RETURN_REGNUM
* UNITS_PER_LONG
));
9006 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9007 TREE_SIDE_EFFECTS (t
) = 1;
9008 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9012 /* Implement va_arg by updating the va_list structure
9013 VALIST as required to retrieve an argument of type
9014 TYPE, and returning that argument.
9016 Generates code equivalent to:
9018 if (integral value) {
9019 if (size <= 4 && args.gpr < 5 ||
9020 size > 4 && args.gpr < 4 )
9021 ret = args.reg_save_area[args.gpr+8]
9023 ret = *args.overflow_arg_area++;
9024 } else if (float value) {
9026 ret = args.reg_save_area[args.fpr+64]
9028 ret = *args.overflow_arg_area++;
9029 } else if (aggregate value) {
9031 ret = *args.reg_save_area[args.gpr]
9033 ret = **args.overflow_arg_area++;
9037 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9038 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
9040 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9041 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9042 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
9043 tree lab_false
, lab_over
, addr
;
9045 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9046 f_fpr
= DECL_CHAIN (f_gpr
);
9047 f_ovf
= DECL_CHAIN (f_fpr
);
9048 f_sav
= DECL_CHAIN (f_ovf
);
9050 valist
= build_va_arg_indirect_ref (valist
);
9051 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9052 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9053 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9055 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9056 both appear on a lhs. */
9057 valist
= unshare_expr (valist
);
9058 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9060 size
= int_size_in_bytes (type
);
9062 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9064 if (TARGET_DEBUG_ARG
)
9066 fprintf (stderr
, "va_arg: aggregate type");
9070 /* Aggregates are passed by reference. */
9075 /* kernel stack layout on 31 bit: It is assumed here that no padding
9076 will be added by s390_frame_info because for va_args always an even
9077 number of gprs has to be saved r15-r2 = 14 regs. */
9078 sav_ofs
= 2 * UNITS_PER_LONG
;
9079 sav_scale
= UNITS_PER_LONG
;
9080 size
= UNITS_PER_LONG
;
9081 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9083 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
9085 if (TARGET_DEBUG_ARG
)
9087 fprintf (stderr
, "va_arg: float type");
9091 /* FP args go in FP registers, if present. */
9095 sav_ofs
= 16 * UNITS_PER_LONG
;
9097 max_reg
= FP_ARG_NUM_REG
- n_reg
;
9101 if (TARGET_DEBUG_ARG
)
9103 fprintf (stderr
, "va_arg: other type");
9107 /* Otherwise into GP registers. */
9110 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9112 /* kernel stack layout on 31 bit: It is assumed here that no padding
9113 will be added by s390_frame_info because for va_args always an even
9114 number of gprs has to be saved r15-r2 = 14 regs. */
9115 sav_ofs
= 2 * UNITS_PER_LONG
;
9117 if (size
< UNITS_PER_LONG
)
9118 sav_ofs
+= UNITS_PER_LONG
- size
;
9120 sav_scale
= UNITS_PER_LONG
;
9121 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9124 /* Pull the value out of the saved registers ... */
9126 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
9127 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
9128 addr
= create_tmp_var (ptr_type_node
, "addr");
9130 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
9131 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
9132 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9133 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9134 gimplify_and_add (t
, pre_p
);
9136 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
9137 size_int (sav_ofs
));
9138 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
9139 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
9140 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
9142 gimplify_assign (addr
, t
, pre_p
);
9144 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9146 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
9149 /* ... Otherwise out of the overflow area. */
9152 if (size
< UNITS_PER_LONG
)
9153 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
9154 size_int (UNITS_PER_LONG
- size
));
9156 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9158 gimplify_assign (addr
, t
, pre_p
);
9160 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
9162 gimplify_assign (ovf
, t
, pre_p
);
9164 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
9167 /* Increment register save count. */
9169 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
9170 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
9171 gimplify_and_add (u
, pre_p
);
9175 t
= build_pointer_type_for_mode (build_pointer_type (type
),
9177 addr
= fold_convert (t
, addr
);
9178 addr
= build_va_arg_indirect_ref (addr
);
9182 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9183 addr
= fold_convert (t
, addr
);
9186 return build_va_arg_indirect_ref (addr
);
9194 S390_BUILTIN_THREAD_POINTER
,
9195 S390_BUILTIN_SET_THREAD_POINTER
,
9200 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
9205 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
9211 s390_init_builtins (void)
9215 ftype
= build_function_type (ptr_type_node
, void_list_node
);
9216 add_builtin_function ("__builtin_thread_pointer", ftype
,
9217 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
9220 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
9221 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
9222 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
9226 /* Expand an expression EXP that calls a built-in function,
9227 with result going to TARGET if that's convenient
9228 (and in mode MODE if that's convenient).
9229 SUBTARGET may be used as the target for computing one of EXP's operands.
9230 IGNORE is nonzero if the value is to be ignored. */
9233 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9234 enum machine_mode mode ATTRIBUTE_UNUSED
,
9235 int ignore ATTRIBUTE_UNUSED
)
9239 enum insn_code
const *code_for_builtin
=
9240 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
9242 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9243 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9244 enum insn_code icode
;
9245 rtx op
[MAX_ARGS
], pat
;
9249 call_expr_arg_iterator iter
;
9251 if (fcode
>= S390_BUILTIN_max
)
9252 internal_error ("bad builtin fcode");
9253 icode
= code_for_builtin
[fcode
];
9255 internal_error ("bad builtin fcode");
9257 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9260 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9262 const struct insn_operand_data
*insn_op
;
9264 if (arg
== error_mark_node
)
9266 if (arity
> MAX_ARGS
)
9269 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
9271 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
9273 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
9274 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
9280 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9282 || GET_MODE (target
) != tmode
9283 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9284 target
= gen_reg_rtx (tmode
);
9290 pat
= GEN_FCN (icode
) (target
);
9294 pat
= GEN_FCN (icode
) (target
, op
[0]);
9296 pat
= GEN_FCN (icode
) (op
[0]);
9299 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9315 /* Output assembly code for the trampoline template to
9318 On S/390, we use gpr 1 internally in the trampoline code;
9319 gpr 0 is used to hold the static chain. */
9322 s390_asm_trampoline_template (FILE *file
)
9325 op
[0] = gen_rtx_REG (Pmode
, 0);
9326 op
[1] = gen_rtx_REG (Pmode
, 1);
9330 output_asm_insn ("basr\t%1,0", op
);
9331 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
9332 output_asm_insn ("br\t%1", op
);
9333 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9337 output_asm_insn ("basr\t%1,0", op
);
9338 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
9339 output_asm_insn ("br\t%1", op
);
9340 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9344 /* Emit RTL insns to initialize the variable parts of a trampoline.
9345 FNADDR is an RTX for the address of the function's pure code.
9346 CXT is an RTX for the static chain value for the function. */
9349 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9351 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9354 emit_block_move (m_tramp
, assemble_trampoline_template (),
9355 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
9357 mem
= adjust_address (m_tramp
, Pmode
, 2*UNITS_PER_WORD
);
9358 emit_move_insn (mem
, cxt
);
9359 mem
= adjust_address (m_tramp
, Pmode
, 3*UNITS_PER_WORD
);
9360 emit_move_insn (mem
, fnaddr
);
9363 /* Output assembler code to FILE to increment profiler label # LABELNO
9364 for profiling a function entry. */
9367 s390_function_profiler (FILE *file
, int labelno
)
9372 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9374 fprintf (file
, "# function profiler \n");
9376 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9377 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9378 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_LONG
));
9380 op
[2] = gen_rtx_REG (Pmode
, 1);
9381 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9382 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9384 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9387 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9388 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9393 output_asm_insn ("stg\t%0,%1", op
);
9394 output_asm_insn ("larl\t%2,%3", op
);
9395 output_asm_insn ("brasl\t%0,%4", op
);
9396 output_asm_insn ("lg\t%0,%1", op
);
9400 op
[6] = gen_label_rtx ();
9402 output_asm_insn ("st\t%0,%1", op
);
9403 output_asm_insn ("bras\t%2,%l6", op
);
9404 output_asm_insn (".long\t%4", op
);
9405 output_asm_insn (".long\t%3", op
);
9406 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9407 output_asm_insn ("l\t%0,0(%2)", op
);
9408 output_asm_insn ("l\t%2,4(%2)", op
);
9409 output_asm_insn ("basr\t%0,%0", op
);
9410 output_asm_insn ("l\t%0,%1", op
);
9414 op
[5] = gen_label_rtx ();
9415 op
[6] = gen_label_rtx ();
9417 output_asm_insn ("st\t%0,%1", op
);
9418 output_asm_insn ("bras\t%2,%l6", op
);
9419 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9420 output_asm_insn (".long\t%4-%l5", op
);
9421 output_asm_insn (".long\t%3-%l5", op
);
9422 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9423 output_asm_insn ("lr\t%0,%2", op
);
9424 output_asm_insn ("a\t%0,0(%2)", op
);
9425 output_asm_insn ("a\t%2,4(%2)", op
);
9426 output_asm_insn ("basr\t%0,%0", op
);
9427 output_asm_insn ("l\t%0,%1", op
);
9431 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9432 into its SYMBOL_REF_FLAGS. */
9435 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9437 default_encode_section_info (decl
, rtl
, first
);
9439 if (TREE_CODE (decl
) == VAR_DECL
)
9441 /* If a variable has a forced alignment to < 2 bytes, mark it
9442 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9444 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9445 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9446 if (!DECL_SIZE (decl
)
9447 || !DECL_ALIGN (decl
)
9448 || !host_integerp (DECL_SIZE (decl
), 0)
9449 || (DECL_ALIGN (decl
) <= 64
9450 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9451 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9454 /* Literal pool references don't have a decl so they are handled
9455 differently here. We rely on the information in the MEM_ALIGN
9456 entry to decide upon natural alignment. */
9458 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9459 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9460 && (MEM_ALIGN (rtl
) == 0
9461 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9462 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9463 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9466 /* Output thunk to FILE that implements a C++ virtual function call (with
9467 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9468 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9469 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9470 relative to the resulting this pointer. */
9473 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9474 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9480 /* Make sure unwind info is emitted for the thunk if needed. */
9481 final_start_function (emit_barrier (), file
, 1);
9483 /* Operand 0 is the target function. */
9484 op
[0] = XEXP (DECL_RTL (function
), 0);
9485 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9488 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9489 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9490 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9493 /* Operand 1 is the 'this' pointer. */
9494 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9495 op
[1] = gen_rtx_REG (Pmode
, 3);
9497 op
[1] = gen_rtx_REG (Pmode
, 2);
9499 /* Operand 2 is the delta. */
9500 op
[2] = GEN_INT (delta
);
9502 /* Operand 3 is the vcall_offset. */
9503 op
[3] = GEN_INT (vcall_offset
);
9505 /* Operand 4 is the temporary register. */
9506 op
[4] = gen_rtx_REG (Pmode
, 1);
9508 /* Operands 5 to 8 can be used as labels. */
9514 /* Operand 9 can be used for temporary register. */
9517 /* Generate code. */
9520 /* Setup literal pool pointer if required. */
9521 if ((!DISP_IN_RANGE (delta
)
9522 && !CONST_OK_FOR_K (delta
)
9523 && !CONST_OK_FOR_Os (delta
))
9524 || (!DISP_IN_RANGE (vcall_offset
)
9525 && !CONST_OK_FOR_K (vcall_offset
)
9526 && !CONST_OK_FOR_Os (vcall_offset
)))
9528 op
[5] = gen_label_rtx ();
9529 output_asm_insn ("larl\t%4,%5", op
);
9532 /* Add DELTA to this pointer. */
9535 if (CONST_OK_FOR_J (delta
))
9536 output_asm_insn ("la\t%1,%2(%1)", op
);
9537 else if (DISP_IN_RANGE (delta
))
9538 output_asm_insn ("lay\t%1,%2(%1)", op
);
9539 else if (CONST_OK_FOR_K (delta
))
9540 output_asm_insn ("aghi\t%1,%2", op
);
9541 else if (CONST_OK_FOR_Os (delta
))
9542 output_asm_insn ("agfi\t%1,%2", op
);
9545 op
[6] = gen_label_rtx ();
9546 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9550 /* Perform vcall adjustment. */
9553 if (DISP_IN_RANGE (vcall_offset
))
9555 output_asm_insn ("lg\t%4,0(%1)", op
);
9556 output_asm_insn ("ag\t%1,%3(%4)", op
);
9558 else if (CONST_OK_FOR_K (vcall_offset
))
9560 output_asm_insn ("lghi\t%4,%3", op
);
9561 output_asm_insn ("ag\t%4,0(%1)", op
);
9562 output_asm_insn ("ag\t%1,0(%4)", op
);
9564 else if (CONST_OK_FOR_Os (vcall_offset
))
9566 output_asm_insn ("lgfi\t%4,%3", op
);
9567 output_asm_insn ("ag\t%4,0(%1)", op
);
9568 output_asm_insn ("ag\t%1,0(%4)", op
);
9572 op
[7] = gen_label_rtx ();
9573 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9574 output_asm_insn ("ag\t%4,0(%1)", op
);
9575 output_asm_insn ("ag\t%1,0(%4)", op
);
9579 /* Jump to target. */
9580 output_asm_insn ("jg\t%0", op
);
9582 /* Output literal pool if required. */
9585 output_asm_insn (".align\t4", op
);
9586 targetm
.asm_out
.internal_label (file
, "L",
9587 CODE_LABEL_NUMBER (op
[5]));
9591 targetm
.asm_out
.internal_label (file
, "L",
9592 CODE_LABEL_NUMBER (op
[6]));
9593 output_asm_insn (".long\t%2", op
);
9597 targetm
.asm_out
.internal_label (file
, "L",
9598 CODE_LABEL_NUMBER (op
[7]));
9599 output_asm_insn (".long\t%3", op
);
9604 /* Setup base pointer if required. */
9606 || (!DISP_IN_RANGE (delta
)
9607 && !CONST_OK_FOR_K (delta
)
9608 && !CONST_OK_FOR_Os (delta
))
9609 || (!DISP_IN_RANGE (delta
)
9610 && !CONST_OK_FOR_K (vcall_offset
)
9611 && !CONST_OK_FOR_Os (vcall_offset
)))
9613 op
[5] = gen_label_rtx ();
9614 output_asm_insn ("basr\t%4,0", op
);
9615 targetm
.asm_out
.internal_label (file
, "L",
9616 CODE_LABEL_NUMBER (op
[5]));
9619 /* Add DELTA to this pointer. */
9622 if (CONST_OK_FOR_J (delta
))
9623 output_asm_insn ("la\t%1,%2(%1)", op
);
9624 else if (DISP_IN_RANGE (delta
))
9625 output_asm_insn ("lay\t%1,%2(%1)", op
);
9626 else if (CONST_OK_FOR_K (delta
))
9627 output_asm_insn ("ahi\t%1,%2", op
);
9628 else if (CONST_OK_FOR_Os (delta
))
9629 output_asm_insn ("afi\t%1,%2", op
);
9632 op
[6] = gen_label_rtx ();
9633 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9637 /* Perform vcall adjustment. */
9640 if (CONST_OK_FOR_J (vcall_offset
))
9642 output_asm_insn ("l\t%4,0(%1)", op
);
9643 output_asm_insn ("a\t%1,%3(%4)", op
);
9645 else if (DISP_IN_RANGE (vcall_offset
))
9647 output_asm_insn ("l\t%4,0(%1)", op
);
9648 output_asm_insn ("ay\t%1,%3(%4)", op
);
9650 else if (CONST_OK_FOR_K (vcall_offset
))
9652 output_asm_insn ("lhi\t%4,%3", op
);
9653 output_asm_insn ("a\t%4,0(%1)", op
);
9654 output_asm_insn ("a\t%1,0(%4)", op
);
9656 else if (CONST_OK_FOR_Os (vcall_offset
))
9658 output_asm_insn ("iilf\t%4,%3", op
);
9659 output_asm_insn ("a\t%4,0(%1)", op
);
9660 output_asm_insn ("a\t%1,0(%4)", op
);
9664 op
[7] = gen_label_rtx ();
9665 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9666 output_asm_insn ("a\t%4,0(%1)", op
);
9667 output_asm_insn ("a\t%1,0(%4)", op
);
9670 /* We had to clobber the base pointer register.
9671 Re-setup the base pointer (with a different base). */
9672 op
[5] = gen_label_rtx ();
9673 output_asm_insn ("basr\t%4,0", op
);
9674 targetm
.asm_out
.internal_label (file
, "L",
9675 CODE_LABEL_NUMBER (op
[5]));
9678 /* Jump to target. */
9679 op
[8] = gen_label_rtx ();
9682 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9684 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9685 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9686 else if (flag_pic
== 1)
9688 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9689 output_asm_insn ("l\t%4,%0(%4)", op
);
9691 else if (flag_pic
== 2)
9693 op
[9] = gen_rtx_REG (Pmode
, 0);
9694 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9695 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9696 output_asm_insn ("ar\t%4,%9", op
);
9697 output_asm_insn ("l\t%4,0(%4)", op
);
9700 output_asm_insn ("br\t%4", op
);
9702 /* Output literal pool. */
9703 output_asm_insn (".align\t4", op
);
9705 if (nonlocal
&& flag_pic
== 2)
9706 output_asm_insn (".long\t%0", op
);
9709 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9710 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9713 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9715 output_asm_insn (".long\t%0", op
);
9717 output_asm_insn (".long\t%0-%5", op
);
9721 targetm
.asm_out
.internal_label (file
, "L",
9722 CODE_LABEL_NUMBER (op
[6]));
9723 output_asm_insn (".long\t%2", op
);
9727 targetm
.asm_out
.internal_label (file
, "L",
9728 CODE_LABEL_NUMBER (op
[7]));
9729 output_asm_insn (".long\t%3", op
);
9732 final_end_function ();
9736 s390_valid_pointer_mode (enum machine_mode mode
)
9738 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9741 /* Checks whether the given CALL_EXPR would use a caller
9742 saved register. This is used to decide whether sibling call
9743 optimization could be performed on the respective function
9747 s390_call_saved_register_used (tree call_expr
)
9749 CUMULATIVE_ARGS cum
;
9751 enum machine_mode mode
;
9756 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
9758 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9760 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9761 gcc_assert (parameter
);
9763 /* For an undeclared variable passed as parameter we will get
9764 an ERROR_MARK node here. */
9765 if (TREE_CODE (parameter
) == ERROR_MARK
)
9768 type
= TREE_TYPE (parameter
);
9771 mode
= TYPE_MODE (type
);
9774 if (pass_by_reference (&cum
, mode
, type
, true))
9777 type
= build_pointer_type (type
);
9780 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
9782 s390_function_arg_advance (&cum
, mode
, type
, 0);
9787 if (REG_P (parm_rtx
))
9790 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9792 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9796 if (GET_CODE (parm_rtx
) == PARALLEL
)
9800 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9802 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9804 gcc_assert (REG_P (r
));
9807 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9809 if (!call_used_regs
[reg
+ REGNO (r
)])
9818 /* Return true if the given call expression can be
9819 turned into a sibling call.
9820 DECL holds the declaration of the function to be called whereas
9821 EXP is the call expression itself. */
9824 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9826 /* The TPF epilogue uses register 1. */
9827 if (TARGET_TPF_PROFILING
)
9830 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9831 which would have to be restored before the sibcall. */
9832 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9835 /* Register 6 on s390 is available as an argument register but unfortunately
9836 "caller saved". This makes functions needing this register for arguments
9837 not suitable for sibcalls. */
9838 return !s390_call_saved_register_used (exp
);
9841 /* Return the fixed registers used for condition codes. */
9844 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9847 *p2
= INVALID_REGNUM
;
9852 /* This function is used by the call expanders of the machine description.
9853 It emits the call insn itself together with the necessary operations
9854 to adjust the target address and returns the emitted insn.
9855 ADDR_LOCATION is the target address rtx
9856 TLS_CALL the location of the thread-local symbol
9857 RESULT_REG the register where the result of the call should be stored
9858 RETADDR_REG the register where the return address should be stored
9859 If this parameter is NULL_RTX the call is considered
9860 to be a sibling call. */
9863 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9866 bool plt_call
= false;
9872 /* Direct function calls need special treatment. */
9873 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9875 /* When calling a global routine in PIC mode, we must
9876 replace the symbol itself with the PLT stub. */
9877 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9879 if (retaddr_reg
!= NULL_RTX
)
9881 addr_location
= gen_rtx_UNSPEC (Pmode
,
9882 gen_rtvec (1, addr_location
),
9884 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9888 /* For -fpic code the PLT entries might use r12 which is
9889 call-saved. Therefore we cannot do a sibcall when
9890 calling directly using a symbol ref. When reaching
9891 this point we decided (in s390_function_ok_for_sibcall)
9892 to do a sibcall for a function pointer but one of the
9893 optimizers was able to get rid of the function pointer
9894 by propagating the symbol ref into the call. This
9895 optimization is illegal for S/390 so we turn the direct
9896 call into a indirect call again. */
9897 addr_location
= force_reg (Pmode
, addr_location
);
9900 /* Unless we can use the bras(l) insn, force the
9901 routine address into a register. */
9902 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9905 addr_location
= legitimize_pic_address (addr_location
, 0);
9907 addr_location
= force_reg (Pmode
, addr_location
);
9911 /* If it is already an indirect call or the code above moved the
9912 SYMBOL_REF to somewhere else make sure the address can be found in
9914 if (retaddr_reg
== NULL_RTX
9915 && GET_CODE (addr_location
) != SYMBOL_REF
9918 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9919 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9922 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9923 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9925 if (result_reg
!= NULL_RTX
)
9926 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9928 if (retaddr_reg
!= NULL_RTX
)
9930 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9932 if (tls_call
!= NULL_RTX
)
9933 vec
= gen_rtvec (3, call
, clobber
,
9934 gen_rtx_USE (VOIDmode
, tls_call
));
9936 vec
= gen_rtvec (2, call
, clobber
);
9938 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9941 insn
= emit_call_insn (call
);
9943 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9944 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9946 /* s390_function_ok_for_sibcall should
9947 have denied sibcalls in this case. */
9948 gcc_assert (retaddr_reg
!= NULL_RTX
);
9950 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9955 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9958 s390_conditional_register_usage (void)
9964 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9965 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9967 if (TARGET_CPU_ZARCH
)
9969 fixed_regs
[BASE_REGNUM
] = 0;
9970 call_used_regs
[BASE_REGNUM
] = 0;
9971 fixed_regs
[RETURN_REGNUM
] = 0;
9972 call_used_regs
[RETURN_REGNUM
] = 0;
9976 for (i
= 24; i
< 32; i
++)
9977 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9981 for (i
= 18; i
< 20; i
++)
9982 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9985 if (TARGET_SOFT_FLOAT
)
9987 for (i
= 16; i
< 32; i
++)
9988 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9992 /* Corresponding function to eh_return expander. */
9994 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9996 s390_emit_tpf_eh_return (rtx target
)
10000 if (!s390_tpf_eh_return_symbol
)
10001 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
10003 reg
= gen_rtx_REG (Pmode
, 2);
10005 emit_move_insn (reg
, target
);
10006 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
10007 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
10008 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
10010 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
10013 /* Rework the prologue/epilogue to avoid saving/restoring
10014 registers unnecessarily. */
10017 s390_optimize_prologue (void)
10019 rtx insn
, new_insn
, next_insn
;
10021 /* Do a final recompute of the frame-related data. */
10023 s390_update_frame_layout ();
10025 /* If all special registers are in fact used, there's nothing we
10026 can do, so no point in walking the insn list. */
10028 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
10029 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
10030 && (TARGET_CPU_ZARCH
10031 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
10032 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
10035 /* Search for prologue/epilogue insns and replace them. */
10037 for (insn
= get_insns (); insn
; insn
= next_insn
)
10039 int first
, last
, off
;
10040 rtx set
, base
, offset
;
10042 next_insn
= NEXT_INSN (insn
);
10044 if (GET_CODE (insn
) != INSN
)
10047 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10048 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
10050 set
= XVECEXP (PATTERN (insn
), 0, 0);
10051 first
= REGNO (SET_SRC (set
));
10052 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
10053 offset
= const0_rtx
;
10054 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10055 off
= INTVAL (offset
);
10057 if (GET_CODE (base
) != REG
|| off
< 0)
10059 if (cfun_frame_layout
.first_save_gpr
!= -1
10060 && (cfun_frame_layout
.first_save_gpr
< first
10061 || cfun_frame_layout
.last_save_gpr
> last
))
10063 if (REGNO (base
) != STACK_POINTER_REGNUM
10064 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10066 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10069 if (cfun_frame_layout
.first_save_gpr
!= -1)
10071 new_insn
= save_gprs (base
,
10072 off
+ (cfun_frame_layout
.first_save_gpr
10073 - first
) * UNITS_PER_LONG
,
10074 cfun_frame_layout
.first_save_gpr
,
10075 cfun_frame_layout
.last_save_gpr
);
10076 new_insn
= emit_insn_before (new_insn
, insn
);
10077 INSN_ADDRESSES_NEW (new_insn
, -1);
10080 remove_insn (insn
);
10084 if (cfun_frame_layout
.first_save_gpr
== -1
10085 && GET_CODE (PATTERN (insn
)) == SET
10086 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
10087 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
10088 || (!TARGET_CPU_ZARCH
10089 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
10090 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
10092 set
= PATTERN (insn
);
10093 first
= REGNO (SET_SRC (set
));
10094 offset
= const0_rtx
;
10095 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10096 off
= INTVAL (offset
);
10098 if (GET_CODE (base
) != REG
|| off
< 0)
10100 if (REGNO (base
) != STACK_POINTER_REGNUM
10101 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10104 remove_insn (insn
);
10108 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10109 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
10111 set
= XVECEXP (PATTERN (insn
), 0, 0);
10112 first
= REGNO (SET_DEST (set
));
10113 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
10114 offset
= const0_rtx
;
10115 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10116 off
= INTVAL (offset
);
10118 if (GET_CODE (base
) != REG
|| off
< 0)
10120 if (cfun_frame_layout
.first_restore_gpr
!= -1
10121 && (cfun_frame_layout
.first_restore_gpr
< first
10122 || cfun_frame_layout
.last_restore_gpr
> last
))
10124 if (REGNO (base
) != STACK_POINTER_REGNUM
10125 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10127 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10130 if (cfun_frame_layout
.first_restore_gpr
!= -1)
10132 new_insn
= restore_gprs (base
,
10133 off
+ (cfun_frame_layout
.first_restore_gpr
10134 - first
) * UNITS_PER_LONG
,
10135 cfun_frame_layout
.first_restore_gpr
,
10136 cfun_frame_layout
.last_restore_gpr
);
10137 new_insn
= emit_insn_before (new_insn
, insn
);
10138 INSN_ADDRESSES_NEW (new_insn
, -1);
10141 remove_insn (insn
);
10145 if (cfun_frame_layout
.first_restore_gpr
== -1
10146 && GET_CODE (PATTERN (insn
)) == SET
10147 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
10148 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
10149 || (!TARGET_CPU_ZARCH
10150 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
10151 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
10153 set
= PATTERN (insn
);
10154 first
= REGNO (SET_DEST (set
));
10155 offset
= const0_rtx
;
10156 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10157 off
= INTVAL (offset
);
10159 if (GET_CODE (base
) != REG
|| off
< 0)
10161 if (REGNO (base
) != STACK_POINTER_REGNUM
10162 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10165 remove_insn (insn
);
10171 /* On z10 and later the dynamic branch prediction must see the
10172 backward jump within a certain windows. If not it falls back to
10173 the static prediction. This function rearranges the loop backward
10174 branch in a way which makes the static prediction always correct.
10175 The function returns true if it added an instruction. */
10177 s390_fix_long_loop_prediction (rtx insn
)
10179 rtx set
= single_set (insn
);
10180 rtx code_label
, label_ref
, new_label
;
10186 /* This will exclude branch on count and branch on index patterns
10187 since these are correctly statically predicted. */
10189 || SET_DEST (set
) != pc_rtx
10190 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
10193 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
10194 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
10196 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
10198 code_label
= XEXP (label_ref
, 0);
10200 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
10201 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
10202 || (INSN_ADDRESSES (INSN_UID (insn
))
10203 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
10206 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
10207 distance
< PREDICT_DISTANCE
- 6;
10208 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
10209 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
10212 new_label
= gen_label_rtx ();
10213 uncond_jump
= emit_jump_insn_after (
10214 gen_rtx_SET (VOIDmode
, pc_rtx
,
10215 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
10217 emit_label_after (new_label
, uncond_jump
);
10219 tmp
= XEXP (SET_SRC (set
), 1);
10220 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
10221 XEXP (SET_SRC (set
), 2) = tmp
;
10222 INSN_CODE (insn
) = -1;
10224 XEXP (label_ref
, 0) = new_label
;
10225 JUMP_LABEL (insn
) = new_label
;
10226 JUMP_LABEL (uncond_jump
) = code_label
;
10231 /* Returns 1 if INSN reads the value of REG for purposes not related
10232 to addressing of memory, and 0 otherwise. */
10234 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
10236 return reg_referenced_p (reg
, PATTERN (insn
))
10237 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
10240 /* Starting from INSN find_cond_jump looks downwards in the insn
10241 stream for a single jump insn which is the last user of the
10242 condition code set in INSN. */
10244 find_cond_jump (rtx insn
)
10246 for (; insn
; insn
= NEXT_INSN (insn
))
10250 if (LABEL_P (insn
))
10253 if (!JUMP_P (insn
))
10255 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10260 /* This will be triggered by a return. */
10261 if (GET_CODE (PATTERN (insn
)) != SET
)
10264 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10265 ite
= SET_SRC (PATTERN (insn
));
10267 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10270 cc
= XEXP (XEXP (ite
, 0), 0);
10271 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10274 if (find_reg_note (insn
, REG_DEAD
, cc
))
10282 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10283 the semantics does not change. If NULL_RTX is passed as COND the
10284 function tries to find the conditional jump starting with INSN. */
10286 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10290 if (cond
== NULL_RTX
)
10292 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10293 jump
= jump
? single_set (jump
) : NULL_RTX
;
10295 if (jump
== NULL_RTX
)
10298 cond
= XEXP (XEXP (jump
, 1), 0);
10303 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10306 /* On z10, instructions of the compare-and-branch family have the
10307 property to access the register occurring as second operand with
10308 its bits complemented. If such a compare is grouped with a second
10309 instruction that accesses the same register non-complemented, and
10310 if that register's value is delivered via a bypass, then the
10311 pipeline recycles, thereby causing significant performance decline.
10312 This function locates such situations and exchanges the two
10313 operands of the compare. The function return true whenever it
10316 s390_z10_optimize_cmp (rtx insn
)
10318 rtx prev_insn
, next_insn
;
10319 bool insn_added_p
= false;
10320 rtx cond
, *op0
, *op1
;
10322 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10324 /* Handle compare and branch and branch on count
10326 rtx pattern
= single_set (insn
);
10329 || SET_DEST (pattern
) != pc_rtx
10330 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10333 cond
= XEXP (SET_SRC (pattern
), 0);
10334 op0
= &XEXP (cond
, 0);
10335 op1
= &XEXP (cond
, 1);
10337 else if (GET_CODE (PATTERN (insn
)) == SET
)
10341 /* Handle normal compare instructions. */
10342 src
= SET_SRC (PATTERN (insn
));
10343 dest
= SET_DEST (PATTERN (insn
));
10346 || !CC_REGNO_P (REGNO (dest
))
10347 || GET_CODE (src
) != COMPARE
)
10350 /* s390_swap_cmp will try to find the conditional
10351 jump when passing NULL_RTX as condition. */
10353 op0
= &XEXP (src
, 0);
10354 op1
= &XEXP (src
, 1);
10359 if (!REG_P (*op0
) || !REG_P (*op1
))
10362 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10365 /* Swap the COMPARE arguments and its mask if there is a
10366 conflicting access in the previous insn. */
10367 prev_insn
= prev_active_insn (insn
);
10368 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10369 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10370 s390_swap_cmp (cond
, op0
, op1
, insn
);
10372 /* Check if there is a conflict with the next insn. If there
10373 was no conflict with the previous insn, then swap the
10374 COMPARE arguments and its mask. If we already swapped
10375 the operands, or if swapping them would cause a conflict
10376 with the previous insn, issue a NOP after the COMPARE in
10377 order to separate the two instuctions. */
10378 next_insn
= next_active_insn (insn
);
10379 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10380 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10382 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10383 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10385 if (REGNO (*op1
) == 0)
10386 emit_insn_after (gen_nop1 (), insn
);
10388 emit_insn_after (gen_nop (), insn
);
10389 insn_added_p
= true;
10392 s390_swap_cmp (cond
, op0
, op1
, insn
);
10394 return insn_added_p
;
10397 /* Perform machine-dependent processing. */
10402 bool pool_overflow
= false;
10404 /* Make sure all splits have been performed; splits after
10405 machine_dependent_reorg might confuse insn length counts. */
10406 split_all_insns_noflow ();
10408 /* Install the main literal pool and the associated base
10409 register load insns.
10411 In addition, there are two problematic situations we need
10414 - the literal pool might be > 4096 bytes in size, so that
10415 some of its elements cannot be directly accessed
10417 - a branch target might be > 64K away from the branch, so that
10418 it is not possible to use a PC-relative instruction.
10420 To fix those, we split the single literal pool into multiple
10421 pool chunks, reloading the pool base register at various
10422 points throughout the function to ensure it always points to
10423 the pool chunk the following code expects, and / or replace
10424 PC-relative branches by absolute branches.
10426 However, the two problems are interdependent: splitting the
10427 literal pool can move a branch further away from its target,
10428 causing the 64K limit to overflow, and on the other hand,
10429 replacing a PC-relative branch by an absolute branch means
10430 we need to put the branch target address into the literal
10431 pool, possibly causing it to overflow.
10433 So, we loop trying to fix up both problems until we manage
10434 to satisfy both conditions at the same time. Note that the
10435 loop is guaranteed to terminate as every pass of the loop
10436 strictly decreases the total number of PC-relative branches
10437 in the function. (This is not completely true as there
10438 might be branch-over-pool insns introduced by chunkify_start.
10439 Those never need to be split however.) */
10443 struct constant_pool
*pool
= NULL
;
10445 /* Collect the literal pool. */
10446 if (!pool_overflow
)
10448 pool
= s390_mainpool_start ();
10450 pool_overflow
= true;
10453 /* If literal pool overflowed, start to chunkify it. */
10455 pool
= s390_chunkify_start ();
10457 /* Split out-of-range branches. If this has created new
10458 literal pool entries, cancel current chunk list and
10459 recompute it. zSeries machines have large branch
10460 instructions, so we never need to split a branch. */
10461 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10464 s390_chunkify_cancel (pool
);
10466 s390_mainpool_cancel (pool
);
10471 /* If we made it up to here, both conditions are satisfied.
10472 Finish up literal pool related changes. */
10474 s390_chunkify_finish (pool
);
10476 s390_mainpool_finish (pool
);
10478 /* We're done splitting branches. */
10479 cfun
->machine
->split_branches_pending_p
= false;
10483 /* Generate out-of-pool execute target insns. */
10484 if (TARGET_CPU_ZARCH
)
10486 rtx insn
, label
, target
;
10488 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10490 label
= s390_execute_label (insn
);
10494 gcc_assert (label
!= const0_rtx
);
10496 target
= emit_label (XEXP (label
, 0));
10497 INSN_ADDRESSES_NEW (target
, -1);
10499 target
= emit_insn (s390_execute_target (insn
));
10500 INSN_ADDRESSES_NEW (target
, -1);
10504 /* Try to optimize prologue and epilogue further. */
10505 s390_optimize_prologue ();
10507 /* Walk over the insns and do some >=z10 specific changes. */
10508 if (s390_tune
== PROCESSOR_2097_Z10
10509 || s390_tune
== PROCESSOR_2817_Z196
)
10512 bool insn_added_p
= false;
10514 /* The insn lengths and addresses have to be up to date for the
10515 following manipulations. */
10516 shorten_branches (get_insns ());
10518 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10520 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10524 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10526 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10527 || GET_CODE (PATTERN (insn
)) == SET
)
10528 && s390_tune
== PROCESSOR_2097_Z10
)
10529 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10532 /* Adjust branches if we added new instructions. */
10534 shorten_branches (get_insns ());
10538 /* Return true if INSN is a fp load insn writing register REGNO. */
10540 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10543 enum attr_type flag
= s390_safe_attr_type (insn
);
10545 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10548 set
= single_set (insn
);
10550 if (set
== NULL_RTX
)
10553 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10556 if (REGNO (SET_DEST (set
)) != regno
)
10562 /* This value describes the distance to be avoided between an
10563 aritmetic fp instruction and an fp load writing the same register.
10564 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10565 fine but the exact value has to be avoided. Otherwise the FP
10566 pipeline will throw an exception causing a major penalty. */
10567 #define Z10_EARLYLOAD_DISTANCE 7
10569 /* Rearrange the ready list in order to avoid the situation described
10570 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10571 moved to the very end of the ready list. */
10573 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10575 unsigned int regno
;
10576 int nready
= *nready_p
;
10581 enum attr_type flag
;
10584 /* Skip DISTANCE - 1 active insns. */
10585 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10586 distance
> 0 && insn
!= NULL_RTX
;
10587 distance
--, insn
= prev_active_insn (insn
))
10588 if (CALL_P (insn
) || JUMP_P (insn
))
10591 if (insn
== NULL_RTX
)
10594 set
= single_set (insn
);
10596 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10597 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10600 flag
= s390_safe_attr_type (insn
);
10602 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10605 regno
= REGNO (SET_DEST (set
));
10608 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10615 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10619 /* This function is called via hook TARGET_SCHED_REORDER before
10620 issueing one insn from list READY which contains *NREADYP entries.
10621 For target z10 it reorders load instructions to avoid early load
10622 conflicts in the floating point pipeline */
10624 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10625 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10627 if (s390_tune
== PROCESSOR_2097_Z10
)
10628 if (reload_completed
&& *nreadyp
> 1)
10629 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10631 return s390_issue_rate ();
10634 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10635 the scheduler has issued INSN. It stores the last issued insn into
10636 last_scheduled_insn in order to make it available for
10637 s390_sched_reorder. */
10639 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10640 int verbose ATTRIBUTE_UNUSED
,
10641 rtx insn
, int more
)
10643 last_scheduled_insn
= insn
;
10645 if (GET_CODE (PATTERN (insn
)) != USE
10646 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10653 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10654 int verbose ATTRIBUTE_UNUSED
,
10655 int max_ready ATTRIBUTE_UNUSED
)
10657 last_scheduled_insn
= NULL_RTX
;
10660 /* This function checks the whole of insn X for memory references. The
10661 function always returns zero because the framework it is called
10662 from would stop recursively analyzing the insn upon a return value
10663 other than zero. The real result of this function is updating
10664 counter variable MEM_COUNT. */
10666 check_dpu (rtx
*x
, unsigned *mem_count
)
10668 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10673 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10674 a new number struct loop *loop should be unrolled if tuned for cpus with
10675 a built-in stride prefetcher.
10676 The loop is analyzed for memory accesses by calling check_dpu for
10677 each rtx of the loop. Depending on the loop_depth and the amount of
10678 memory accesses a new number <=nunroll is returned to improve the
10679 behaviour of the hardware prefetch unit. */
10681 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10686 unsigned mem_count
= 0;
10688 if (s390_tune
!= PROCESSOR_2097_Z10
&& s390_tune
!= PROCESSOR_2817_Z196
)
10691 /* Count the number of memory references within the loop body. */
10692 bbs
= get_loop_body (loop
);
10693 for (i
= 0; i
< loop
->num_nodes
; i
++)
10695 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10696 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10697 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10701 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10702 if (mem_count
== 0)
10705 switch (loop_depth(loop
))
10708 return MIN (nunroll
, 28 / mem_count
);
10710 return MIN (nunroll
, 22 / mem_count
);
10712 return MIN (nunroll
, 16 / mem_count
);
10716 /* Initialize GCC target structure. */
10718 #undef TARGET_ASM_ALIGNED_HI_OP
10719 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10720 #undef TARGET_ASM_ALIGNED_DI_OP
10721 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10722 #undef TARGET_ASM_INTEGER
10723 #define TARGET_ASM_INTEGER s390_assemble_integer
10725 #undef TARGET_ASM_OPEN_PAREN
10726 #define TARGET_ASM_OPEN_PAREN ""
10728 #undef TARGET_ASM_CLOSE_PAREN
10729 #define TARGET_ASM_CLOSE_PAREN ""
10731 #undef TARGET_DEFAULT_TARGET_FLAGS
10732 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
10734 #undef TARGET_HANDLE_OPTION
10735 #define TARGET_HANDLE_OPTION s390_handle_option
10737 #undef TARGET_OPTION_OVERRIDE
10738 #define TARGET_OPTION_OVERRIDE s390_option_override
10740 #undef TARGET_OPTION_OPTIMIZATION_TABLE
10741 #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table
10743 #undef TARGET_OPTION_INIT_STRUCT
10744 #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct
10746 #undef TARGET_ENCODE_SECTION_INFO
10747 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10749 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10750 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10753 #undef TARGET_HAVE_TLS
10754 #define TARGET_HAVE_TLS true
10756 #undef TARGET_CANNOT_FORCE_CONST_MEM
10757 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10759 #undef TARGET_DELEGITIMIZE_ADDRESS
10760 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10762 #undef TARGET_LEGITIMIZE_ADDRESS
10763 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10765 #undef TARGET_RETURN_IN_MEMORY
10766 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10768 #undef TARGET_INIT_BUILTINS
10769 #define TARGET_INIT_BUILTINS s390_init_builtins
10770 #undef TARGET_EXPAND_BUILTIN
10771 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10773 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10774 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10776 #undef TARGET_ASM_OUTPUT_MI_THUNK
10777 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10778 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10779 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10781 #undef TARGET_SCHED_ADJUST_PRIORITY
10782 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10783 #undef TARGET_SCHED_ISSUE_RATE
10784 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10785 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10786 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10788 #undef TARGET_SCHED_VARIABLE_ISSUE
10789 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10790 #undef TARGET_SCHED_REORDER
10791 #define TARGET_SCHED_REORDER s390_sched_reorder
10792 #undef TARGET_SCHED_INIT
10793 #define TARGET_SCHED_INIT s390_sched_init
10795 #undef TARGET_CANNOT_COPY_INSN_P
10796 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10797 #undef TARGET_RTX_COSTS
10798 #define TARGET_RTX_COSTS s390_rtx_costs
10799 #undef TARGET_ADDRESS_COST
10800 #define TARGET_ADDRESS_COST s390_address_cost
10801 #undef TARGET_REGISTER_MOVE_COST
10802 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10803 #undef TARGET_MEMORY_MOVE_COST
10804 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10806 #undef TARGET_MACHINE_DEPENDENT_REORG
10807 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10809 #undef TARGET_VALID_POINTER_MODE
10810 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10812 #undef TARGET_BUILD_BUILTIN_VA_LIST
10813 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10814 #undef TARGET_EXPAND_BUILTIN_VA_START
10815 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10816 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10817 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10819 #undef TARGET_PROMOTE_FUNCTION_MODE
10820 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10821 #undef TARGET_PASS_BY_REFERENCE
10822 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10824 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10825 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10826 #undef TARGET_FUNCTION_ARG
10827 #define TARGET_FUNCTION_ARG s390_function_arg
10828 #undef TARGET_FUNCTION_ARG_ADVANCE
10829 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10830 #undef TARGET_FUNCTION_VALUE
10831 #define TARGET_FUNCTION_VALUE s390_function_value
10832 #undef TARGET_LIBCALL_VALUE
10833 #define TARGET_LIBCALL_VALUE s390_libcall_value
10835 #undef TARGET_FIXED_CONDITION_CODE_REGS
10836 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10838 #undef TARGET_CC_MODES_COMPATIBLE
10839 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10841 #undef TARGET_INVALID_WITHIN_DOLOOP
10842 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10845 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10846 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10849 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10850 #undef TARGET_MANGLE_TYPE
10851 #define TARGET_MANGLE_TYPE s390_mangle_type
10854 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10855 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10857 #undef TARGET_PREFERRED_RELOAD_CLASS
10858 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10860 #undef TARGET_SECONDARY_RELOAD
10861 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10863 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10864 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10866 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10867 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10869 #undef TARGET_LEGITIMATE_ADDRESS_P
10870 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10872 #undef TARGET_CAN_ELIMINATE
10873 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10875 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10876 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10878 #undef TARGET_LOOP_UNROLL_ADJUST
10879 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10881 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10882 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10883 #undef TARGET_TRAMPOLINE_INIT
10884 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10886 #undef TARGET_UNWIND_WORD_MODE
10887 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10889 struct gcc_target targetm
= TARGET_INITIALIZER
;
10891 #include "gt-s390.h"