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s390.c (s390_chunkify_start): Replacing INSN_LOCATOR.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48 #include "debug.h"
49 #include "langhooks.h"
50 #include "optabs.h"
51 #include "gimple.h"
52 #include "df.h"
53 #include "params.h"
54 #include "cfgloop.h"
55 #include "opts.h"
56
57 /* Define the specific costs for a given cpu. */
58
59 struct processor_costs
60 {
61 /* multiplication */
62 const int m; /* cost of an M instruction. */
63 const int mghi; /* cost of an MGHI instruction. */
64 const int mh; /* cost of an MH instruction. */
65 const int mhi; /* cost of an MHI instruction. */
66 const int ml; /* cost of an ML instruction. */
67 const int mr; /* cost of an MR instruction. */
68 const int ms; /* cost of an MS instruction. */
69 const int msg; /* cost of an MSG instruction. */
70 const int msgf; /* cost of an MSGF instruction. */
71 const int msgfr; /* cost of an MSGFR instruction. */
72 const int msgr; /* cost of an MSGR instruction. */
73 const int msr; /* cost of an MSR instruction. */
74 const int mult_df; /* cost of multiplication in DFmode. */
75 const int mxbr;
76 /* square root */
77 const int sqxbr; /* cost of square root in TFmode. */
78 const int sqdbr; /* cost of square root in DFmode. */
79 const int sqebr; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr; /* cost of multiply and add in DFmode. */
82 const int maebr; /* cost of multiply and add in SFmode. */
83 /* division */
84 const int dxbr;
85 const int ddbr;
86 const int debr;
87 const int dlgr;
88 const int dlr;
89 const int dr;
90 const int dsgfr;
91 const int dsgr;
92 };
93
94 const struct processor_costs *s390_cost;
95
96 static const
97 struct processor_costs z900_cost =
98 {
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
126 };
127
128 static const
129 struct processor_costs z990_cost =
130 {
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
158 };
159
160 static const
161 struct processor_costs z9_109_cost =
162 {
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
190 };
191
192 static const
193 struct processor_costs z10_cost =
194 {
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (1) , /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (1), /* MADBR */
213 COSTS_N_INSNS (1), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
222 };
223
224 static const
225 struct processor_costs z196_cost =
226 {
227 COSTS_N_INSNS (7), /* M */
228 COSTS_N_INSNS (5), /* MGHI */
229 COSTS_N_INSNS (5), /* MH */
230 COSTS_N_INSNS (5), /* MHI */
231 COSTS_N_INSNS (7), /* ML */
232 COSTS_N_INSNS (7), /* MR */
233 COSTS_N_INSNS (6), /* MS */
234 COSTS_N_INSNS (8), /* MSG */
235 COSTS_N_INSNS (6), /* MSGF */
236 COSTS_N_INSNS (6), /* MSGFR */
237 COSTS_N_INSNS (8), /* MSGR */
238 COSTS_N_INSNS (6), /* MSR */
239 COSTS_N_INSNS (1) , /* multiplication in DFmode */
240 COSTS_N_INSNS (40), /* MXBR B+40 */
241 COSTS_N_INSNS (100), /* SQXBR B+100 */
242 COSTS_N_INSNS (42), /* SQDBR B+42 */
243 COSTS_N_INSNS (28), /* SQEBR B+28 */
244 COSTS_N_INSNS (1), /* MADBR B */
245 COSTS_N_INSNS (1), /* MAEBR B */
246 COSTS_N_INSNS (101), /* DXBR B+101 */
247 COSTS_N_INSNS (29), /* DDBR */
248 COSTS_N_INSNS (22), /* DEBR */
249 COSTS_N_INSNS (160), /* DLGR cracked */
250 COSTS_N_INSNS (160), /* DLR cracked */
251 COSTS_N_INSNS (160), /* DR expanded */
252 COSTS_N_INSNS (160), /* DSGFR cracked */
253 COSTS_N_INSNS (160), /* DSGR cracked */
254 };
255
256 extern int reload_completed;
257
258 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
259 static rtx last_scheduled_insn;
260
261 /* Structure used to hold the components of a S/390 memory
262 address. A legitimate address on S/390 is of the general
263 form
264 base + index + displacement
265 where any of the components is optional.
266
267 base and index are registers of the class ADDR_REGS,
268 displacement is an unsigned 12-bit immediate constant. */
269
270 struct s390_address
271 {
272 rtx base;
273 rtx indx;
274 rtx disp;
275 bool pointer;
276 bool literal_pool;
277 };
278
279 /* The following structure is embedded in the machine
280 specific part of struct function. */
281
282 struct GTY (()) s390_frame_layout
283 {
284 /* Offset within stack frame. */
285 HOST_WIDE_INT gprs_offset;
286 HOST_WIDE_INT f0_offset;
287 HOST_WIDE_INT f4_offset;
288 HOST_WIDE_INT f8_offset;
289 HOST_WIDE_INT backchain_offset;
290
291 /* Number of first and last gpr where slots in the register
292 save area are reserved for. */
293 int first_save_gpr_slot;
294 int last_save_gpr_slot;
295
296 /* Number of first and last gpr to be saved, restored. */
297 int first_save_gpr;
298 int first_restore_gpr;
299 int last_save_gpr;
300 int last_restore_gpr;
301
302 /* Bits standing for floating point registers. Set, if the
303 respective register has to be saved. Starting with reg 16 (f0)
304 at the rightmost bit.
305 Bit 15 - 8 7 6 5 4 3 2 1 0
306 fpr 15 - 8 7 5 3 1 6 4 2 0
307 reg 31 - 24 23 22 21 20 19 18 17 16 */
308 unsigned int fpr_bitmap;
309
310 /* Number of floating point registers f8-f15 which must be saved. */
311 int high_fprs;
312
313 /* Set if return address needs to be saved.
314 This flag is set by s390_return_addr_rtx if it could not use
315 the initial value of r14 and therefore depends on r14 saved
316 to the stack. */
317 bool save_return_addr_p;
318
319 /* Size of stack frame. */
320 HOST_WIDE_INT frame_size;
321 };
322
323 /* Define the structure for the machine field in struct function. */
324
325 struct GTY(()) machine_function
326 {
327 struct s390_frame_layout frame_layout;
328
329 /* Literal pool base register. */
330 rtx base_reg;
331
332 /* True if we may need to perform branch splitting. */
333 bool split_branches_pending_p;
334
335 /* Some local-dynamic TLS symbol name. */
336 const char *some_ld_name;
337
338 bool has_landing_pad_p;
339 };
340
341 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
342
343 #define cfun_frame_layout (cfun->machine->frame_layout)
344 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
345 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
346 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
347 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
348 (1 << (BITNUM)))
349 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
350 (1 << (BITNUM))))
351
352 /* Number of GPRs and FPRs used for argument passing. */
353 #define GP_ARG_NUM_REG 5
354 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
355
356 /* A couple of shortcuts. */
357 #define CONST_OK_FOR_J(x) \
358 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
359 #define CONST_OK_FOR_K(x) \
360 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
361 #define CONST_OK_FOR_Os(x) \
362 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
363 #define CONST_OK_FOR_Op(x) \
364 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
365 #define CONST_OK_FOR_On(x) \
366 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
367
368 #define REGNO_PAIR_OK(REGNO, MODE) \
369 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
370
371 /* That's the read ahead of the dynamic branch prediction unit in
372 bytes on a z10 (or higher) CPU. */
373 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
374
375 /* Return the alignment for LABEL. We default to the -falign-labels
376 value except for the literal pool base label. */
377 int
378 s390_label_align (rtx label)
379 {
380 rtx prev_insn = prev_active_insn (label);
381
382 if (prev_insn == NULL_RTX)
383 goto old;
384
385 prev_insn = single_set (prev_insn);
386
387 if (prev_insn == NULL_RTX)
388 goto old;
389
390 prev_insn = SET_SRC (prev_insn);
391
392 /* Don't align literal pool base labels. */
393 if (GET_CODE (prev_insn) == UNSPEC
394 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
395 return 0;
396
397 old:
398 return align_labels_log;
399 }
400
401 static enum machine_mode
402 s390_libgcc_cmp_return_mode (void)
403 {
404 return TARGET_64BIT ? DImode : SImode;
405 }
406
407 static enum machine_mode
408 s390_libgcc_shift_count_mode (void)
409 {
410 return TARGET_64BIT ? DImode : SImode;
411 }
412
413 static enum machine_mode
414 s390_unwind_word_mode (void)
415 {
416 return TARGET_64BIT ? DImode : SImode;
417 }
418
419 /* Return true if the back end supports mode MODE. */
420 static bool
421 s390_scalar_mode_supported_p (enum machine_mode mode)
422 {
423 /* In contrast to the default implementation reject TImode constants on 31bit
424 TARGET_ZARCH for ABI compliance. */
425 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
426 return false;
427
428 if (DECIMAL_FLOAT_MODE_P (mode))
429 return default_decimal_float_supported_p ();
430
431 return default_scalar_mode_supported_p (mode);
432 }
433
434 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
435
436 void
437 s390_set_has_landing_pad_p (bool value)
438 {
439 cfun->machine->has_landing_pad_p = value;
440 }
441
442 /* If two condition code modes are compatible, return a condition code
443 mode which is compatible with both. Otherwise, return
444 VOIDmode. */
445
446 static enum machine_mode
447 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
448 {
449 if (m1 == m2)
450 return m1;
451
452 switch (m1)
453 {
454 case CCZmode:
455 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
456 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
457 return m2;
458 return VOIDmode;
459
460 case CCSmode:
461 case CCUmode:
462 case CCTmode:
463 case CCSRmode:
464 case CCURmode:
465 case CCZ1mode:
466 if (m2 == CCZmode)
467 return m1;
468
469 return VOIDmode;
470
471 default:
472 return VOIDmode;
473 }
474 return VOIDmode;
475 }
476
477 /* Return true if SET either doesn't set the CC register, or else
478 the source and destination have matching CC modes and that
479 CC mode is at least as constrained as REQ_MODE. */
480
481 static bool
482 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
483 {
484 enum machine_mode set_mode;
485
486 gcc_assert (GET_CODE (set) == SET);
487
488 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
489 return 1;
490
491 set_mode = GET_MODE (SET_DEST (set));
492 switch (set_mode)
493 {
494 case CCSmode:
495 case CCSRmode:
496 case CCUmode:
497 case CCURmode:
498 case CCLmode:
499 case CCL1mode:
500 case CCL2mode:
501 case CCL3mode:
502 case CCT1mode:
503 case CCT2mode:
504 case CCT3mode:
505 if (req_mode != set_mode)
506 return 0;
507 break;
508
509 case CCZmode:
510 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
511 && req_mode != CCSRmode && req_mode != CCURmode)
512 return 0;
513 break;
514
515 case CCAPmode:
516 case CCANmode:
517 if (req_mode != CCAmode)
518 return 0;
519 break;
520
521 default:
522 gcc_unreachable ();
523 }
524
525 return (GET_MODE (SET_SRC (set)) == set_mode);
526 }
527
528 /* Return true if every SET in INSN that sets the CC register
529 has source and destination with matching CC modes and that
530 CC mode is at least as constrained as REQ_MODE.
531 If REQ_MODE is VOIDmode, always return false. */
532
533 bool
534 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
535 {
536 int i;
537
538 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
539 if (req_mode == VOIDmode)
540 return false;
541
542 if (GET_CODE (PATTERN (insn)) == SET)
543 return s390_match_ccmode_set (PATTERN (insn), req_mode);
544
545 if (GET_CODE (PATTERN (insn)) == PARALLEL)
546 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
547 {
548 rtx set = XVECEXP (PATTERN (insn), 0, i);
549 if (GET_CODE (set) == SET)
550 if (!s390_match_ccmode_set (set, req_mode))
551 return false;
552 }
553
554 return true;
555 }
556
557 /* If a test-under-mask instruction can be used to implement
558 (compare (and ... OP1) OP2), return the CC mode required
559 to do that. Otherwise, return VOIDmode.
560 MIXED is true if the instruction can distinguish between
561 CC1 and CC2 for mixed selected bits (TMxx), it is false
562 if the instruction cannot (TM). */
563
564 enum machine_mode
565 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
566 {
567 int bit0, bit1;
568
569 /* ??? Fixme: should work on CONST_DOUBLE as well. */
570 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
571 return VOIDmode;
572
573 /* Selected bits all zero: CC0.
574 e.g.: int a; if ((a & (16 + 128)) == 0) */
575 if (INTVAL (op2) == 0)
576 return CCTmode;
577
578 /* Selected bits all one: CC3.
579 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
580 if (INTVAL (op2) == INTVAL (op1))
581 return CCT3mode;
582
583 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
584 int a;
585 if ((a & (16 + 128)) == 16) -> CCT1
586 if ((a & (16 + 128)) == 128) -> CCT2 */
587 if (mixed)
588 {
589 bit1 = exact_log2 (INTVAL (op2));
590 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
591 if (bit0 != -1 && bit1 != -1)
592 return bit0 > bit1 ? CCT1mode : CCT2mode;
593 }
594
595 return VOIDmode;
596 }
597
598 /* Given a comparison code OP (EQ, NE, etc.) and the operands
599 OP0 and OP1 of a COMPARE, return the mode to be used for the
600 comparison. */
601
602 enum machine_mode
603 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
604 {
605 switch (code)
606 {
607 case EQ:
608 case NE:
609 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
610 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
611 return CCAPmode;
612 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
613 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
614 return CCAPmode;
615 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
616 || GET_CODE (op1) == NEG)
617 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
618 return CCLmode;
619
620 if (GET_CODE (op0) == AND)
621 {
622 /* Check whether we can potentially do it via TM. */
623 enum machine_mode ccmode;
624 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
625 if (ccmode != VOIDmode)
626 {
627 /* Relax CCTmode to CCZmode to allow fall-back to AND
628 if that turns out to be beneficial. */
629 return ccmode == CCTmode ? CCZmode : ccmode;
630 }
631 }
632
633 if (register_operand (op0, HImode)
634 && GET_CODE (op1) == CONST_INT
635 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
636 return CCT3mode;
637 if (register_operand (op0, QImode)
638 && GET_CODE (op1) == CONST_INT
639 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
640 return CCT3mode;
641
642 return CCZmode;
643
644 case LE:
645 case LT:
646 case GE:
647 case GT:
648 /* The only overflow condition of NEG and ABS happens when
649 -INT_MAX is used as parameter, which stays negative. So
650 we have an overflow from a positive value to a negative.
651 Using CCAP mode the resulting cc can be used for comparisons. */
652 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
653 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
654 return CCAPmode;
655
656 /* If constants are involved in an add instruction it is possible to use
657 the resulting cc for comparisons with zero. Knowing the sign of the
658 constant the overflow behavior gets predictable. e.g.:
659 int a, b; if ((b = a + c) > 0)
660 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
661 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
662 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
663 {
664 if (INTVAL (XEXP((op0), 1)) < 0)
665 return CCANmode;
666 else
667 return CCAPmode;
668 }
669 /* Fall through. */
670 case UNORDERED:
671 case ORDERED:
672 case UNEQ:
673 case UNLE:
674 case UNLT:
675 case UNGE:
676 case UNGT:
677 case LTGT:
678 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
679 && GET_CODE (op1) != CONST_INT)
680 return CCSRmode;
681 return CCSmode;
682
683 case LTU:
684 case GEU:
685 if (GET_CODE (op0) == PLUS
686 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
687 return CCL1mode;
688
689 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
690 && GET_CODE (op1) != CONST_INT)
691 return CCURmode;
692 return CCUmode;
693
694 case LEU:
695 case GTU:
696 if (GET_CODE (op0) == MINUS
697 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
698 return CCL2mode;
699
700 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
701 && GET_CODE (op1) != CONST_INT)
702 return CCURmode;
703 return CCUmode;
704
705 default:
706 gcc_unreachable ();
707 }
708 }
709
710 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
711 that we can implement more efficiently. */
712
713 void
714 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
715 {
716 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
717 if ((*code == EQ || *code == NE)
718 && *op1 == const0_rtx
719 && GET_CODE (*op0) == ZERO_EXTRACT
720 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
721 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
722 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
723 {
724 rtx inner = XEXP (*op0, 0);
725 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
726 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
727 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
728
729 if (len > 0 && len < modesize
730 && pos >= 0 && pos + len <= modesize
731 && modesize <= HOST_BITS_PER_WIDE_INT)
732 {
733 unsigned HOST_WIDE_INT block;
734 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
735 block <<= modesize - pos - len;
736
737 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
738 gen_int_mode (block, GET_MODE (inner)));
739 }
740 }
741
742 /* Narrow AND of memory against immediate to enable TM. */
743 if ((*code == EQ || *code == NE)
744 && *op1 == const0_rtx
745 && GET_CODE (*op0) == AND
746 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
747 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
748 {
749 rtx inner = XEXP (*op0, 0);
750 rtx mask = XEXP (*op0, 1);
751
752 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
753 if (GET_CODE (inner) == SUBREG
754 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
755 && (GET_MODE_SIZE (GET_MODE (inner))
756 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
757 && ((INTVAL (mask)
758 & GET_MODE_MASK (GET_MODE (inner))
759 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
760 == 0))
761 inner = SUBREG_REG (inner);
762
763 /* Do not change volatile MEMs. */
764 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
765 {
766 int part = s390_single_part (XEXP (*op0, 1),
767 GET_MODE (inner), QImode, 0);
768 if (part >= 0)
769 {
770 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
771 inner = adjust_address_nv (inner, QImode, part);
772 *op0 = gen_rtx_AND (QImode, inner, mask);
773 }
774 }
775 }
776
777 /* Narrow comparisons against 0xffff to HImode if possible. */
778 if ((*code == EQ || *code == NE)
779 && GET_CODE (*op1) == CONST_INT
780 && INTVAL (*op1) == 0xffff
781 && SCALAR_INT_MODE_P (GET_MODE (*op0))
782 && (nonzero_bits (*op0, GET_MODE (*op0))
783 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
784 {
785 *op0 = gen_lowpart (HImode, *op0);
786 *op1 = constm1_rtx;
787 }
788
789 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
790 if (GET_CODE (*op0) == UNSPEC
791 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
792 && XVECLEN (*op0, 0) == 1
793 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
794 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
795 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
796 && *op1 == const0_rtx)
797 {
798 enum rtx_code new_code = UNKNOWN;
799 switch (*code)
800 {
801 case EQ: new_code = EQ; break;
802 case NE: new_code = NE; break;
803 case LT: new_code = GTU; break;
804 case GT: new_code = LTU; break;
805 case LE: new_code = GEU; break;
806 case GE: new_code = LEU; break;
807 default: break;
808 }
809
810 if (new_code != UNKNOWN)
811 {
812 *op0 = XVECEXP (*op0, 0, 0);
813 *code = new_code;
814 }
815 }
816
817 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
818 if (GET_CODE (*op0) == UNSPEC
819 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
820 && XVECLEN (*op0, 0) == 1
821 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
822 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
823 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
824 && *op1 == const0_rtx)
825 {
826 enum rtx_code new_code = UNKNOWN;
827 switch (*code)
828 {
829 case EQ: new_code = EQ; break;
830 case NE: new_code = NE; break;
831 default: break;
832 }
833
834 if (new_code != UNKNOWN)
835 {
836 *op0 = XVECEXP (*op0, 0, 0);
837 *code = new_code;
838 }
839 }
840
841 /* Simplify cascaded EQ, NE with const0_rtx. */
842 if ((*code == NE || *code == EQ)
843 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
844 && GET_MODE (*op0) == SImode
845 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
846 && REG_P (XEXP (*op0, 0))
847 && XEXP (*op0, 1) == const0_rtx
848 && *op1 == const0_rtx)
849 {
850 if ((*code == EQ && GET_CODE (*op0) == NE)
851 || (*code == NE && GET_CODE (*op0) == EQ))
852 *code = EQ;
853 else
854 *code = NE;
855 *op0 = XEXP (*op0, 0);
856 }
857
858 /* Prefer register over memory as first operand. */
859 if (MEM_P (*op0) && REG_P (*op1))
860 {
861 rtx tem = *op0; *op0 = *op1; *op1 = tem;
862 *code = swap_condition (*code);
863 }
864 }
865
866 /* Emit a compare instruction suitable to implement the comparison
867 OP0 CODE OP1. Return the correct condition RTL to be placed in
868 the IF_THEN_ELSE of the conditional branch testing the result. */
869
870 rtx
871 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
872 {
873 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
874 rtx cc;
875
876 /* Do not output a redundant compare instruction if a compare_and_swap
877 pattern already computed the result and the machine modes are compatible. */
878 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
879 {
880 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
881 == GET_MODE (op0));
882 cc = op0;
883 }
884 else
885 {
886 cc = gen_rtx_REG (mode, CC_REGNUM);
887 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
888 }
889
890 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
891 }
892
893 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
894 matches CMP.
895 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
896 conditional branch testing the result. */
897
898 static rtx
899 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
900 rtx cmp, rtx new_rtx)
901 {
902 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
903 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
904 const0_rtx);
905 }
906
907 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
908 unconditional jump, else a conditional jump under condition COND. */
909
910 void
911 s390_emit_jump (rtx target, rtx cond)
912 {
913 rtx insn;
914
915 target = gen_rtx_LABEL_REF (VOIDmode, target);
916 if (cond)
917 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
918
919 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
920 emit_jump_insn (insn);
921 }
922
923 /* Return branch condition mask to implement a branch
924 specified by CODE. Return -1 for invalid comparisons. */
925
926 int
927 s390_branch_condition_mask (rtx code)
928 {
929 const int CC0 = 1 << 3;
930 const int CC1 = 1 << 2;
931 const int CC2 = 1 << 1;
932 const int CC3 = 1 << 0;
933
934 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
935 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
936 gcc_assert (XEXP (code, 1) == const0_rtx);
937
938 switch (GET_MODE (XEXP (code, 0)))
939 {
940 case CCZmode:
941 case CCZ1mode:
942 switch (GET_CODE (code))
943 {
944 case EQ: return CC0;
945 case NE: return CC1 | CC2 | CC3;
946 default: return -1;
947 }
948 break;
949
950 case CCT1mode:
951 switch (GET_CODE (code))
952 {
953 case EQ: return CC1;
954 case NE: return CC0 | CC2 | CC3;
955 default: return -1;
956 }
957 break;
958
959 case CCT2mode:
960 switch (GET_CODE (code))
961 {
962 case EQ: return CC2;
963 case NE: return CC0 | CC1 | CC3;
964 default: return -1;
965 }
966 break;
967
968 case CCT3mode:
969 switch (GET_CODE (code))
970 {
971 case EQ: return CC3;
972 case NE: return CC0 | CC1 | CC2;
973 default: return -1;
974 }
975 break;
976
977 case CCLmode:
978 switch (GET_CODE (code))
979 {
980 case EQ: return CC0 | CC2;
981 case NE: return CC1 | CC3;
982 default: return -1;
983 }
984 break;
985
986 case CCL1mode:
987 switch (GET_CODE (code))
988 {
989 case LTU: return CC2 | CC3; /* carry */
990 case GEU: return CC0 | CC1; /* no carry */
991 default: return -1;
992 }
993 break;
994
995 case CCL2mode:
996 switch (GET_CODE (code))
997 {
998 case GTU: return CC0 | CC1; /* borrow */
999 case LEU: return CC2 | CC3; /* no borrow */
1000 default: return -1;
1001 }
1002 break;
1003
1004 case CCL3mode:
1005 switch (GET_CODE (code))
1006 {
1007 case EQ: return CC0 | CC2;
1008 case NE: return CC1 | CC3;
1009 case LTU: return CC1;
1010 case GTU: return CC3;
1011 case LEU: return CC1 | CC2;
1012 case GEU: return CC2 | CC3;
1013 default: return -1;
1014 }
1015
1016 case CCUmode:
1017 switch (GET_CODE (code))
1018 {
1019 case EQ: return CC0;
1020 case NE: return CC1 | CC2 | CC3;
1021 case LTU: return CC1;
1022 case GTU: return CC2;
1023 case LEU: return CC0 | CC1;
1024 case GEU: return CC0 | CC2;
1025 default: return -1;
1026 }
1027 break;
1028
1029 case CCURmode:
1030 switch (GET_CODE (code))
1031 {
1032 case EQ: return CC0;
1033 case NE: return CC2 | CC1 | CC3;
1034 case LTU: return CC2;
1035 case GTU: return CC1;
1036 case LEU: return CC0 | CC2;
1037 case GEU: return CC0 | CC1;
1038 default: return -1;
1039 }
1040 break;
1041
1042 case CCAPmode:
1043 switch (GET_CODE (code))
1044 {
1045 case EQ: return CC0;
1046 case NE: return CC1 | CC2 | CC3;
1047 case LT: return CC1 | CC3;
1048 case GT: return CC2;
1049 case LE: return CC0 | CC1 | CC3;
1050 case GE: return CC0 | CC2;
1051 default: return -1;
1052 }
1053 break;
1054
1055 case CCANmode:
1056 switch (GET_CODE (code))
1057 {
1058 case EQ: return CC0;
1059 case NE: return CC1 | CC2 | CC3;
1060 case LT: return CC1;
1061 case GT: return CC2 | CC3;
1062 case LE: return CC0 | CC1;
1063 case GE: return CC0 | CC2 | CC3;
1064 default: return -1;
1065 }
1066 break;
1067
1068 case CCSmode:
1069 switch (GET_CODE (code))
1070 {
1071 case EQ: return CC0;
1072 case NE: return CC1 | CC2 | CC3;
1073 case LT: return CC1;
1074 case GT: return CC2;
1075 case LE: return CC0 | CC1;
1076 case GE: return CC0 | CC2;
1077 case UNORDERED: return CC3;
1078 case ORDERED: return CC0 | CC1 | CC2;
1079 case UNEQ: return CC0 | CC3;
1080 case UNLT: return CC1 | CC3;
1081 case UNGT: return CC2 | CC3;
1082 case UNLE: return CC0 | CC1 | CC3;
1083 case UNGE: return CC0 | CC2 | CC3;
1084 case LTGT: return CC1 | CC2;
1085 default: return -1;
1086 }
1087 break;
1088
1089 case CCSRmode:
1090 switch (GET_CODE (code))
1091 {
1092 case EQ: return CC0;
1093 case NE: return CC2 | CC1 | CC3;
1094 case LT: return CC2;
1095 case GT: return CC1;
1096 case LE: return CC0 | CC2;
1097 case GE: return CC0 | CC1;
1098 case UNORDERED: return CC3;
1099 case ORDERED: return CC0 | CC2 | CC1;
1100 case UNEQ: return CC0 | CC3;
1101 case UNLT: return CC2 | CC3;
1102 case UNGT: return CC1 | CC3;
1103 case UNLE: return CC0 | CC2 | CC3;
1104 case UNGE: return CC0 | CC1 | CC3;
1105 case LTGT: return CC2 | CC1;
1106 default: return -1;
1107 }
1108 break;
1109
1110 default:
1111 return -1;
1112 }
1113 }
1114
1115
1116 /* Return branch condition mask to implement a compare and branch
1117 specified by CODE. Return -1 for invalid comparisons. */
1118
1119 int
1120 s390_compare_and_branch_condition_mask (rtx code)
1121 {
1122 const int CC0 = 1 << 3;
1123 const int CC1 = 1 << 2;
1124 const int CC2 = 1 << 1;
1125
1126 switch (GET_CODE (code))
1127 {
1128 case EQ:
1129 return CC0;
1130 case NE:
1131 return CC1 | CC2;
1132 case LT:
1133 case LTU:
1134 return CC1;
1135 case GT:
1136 case GTU:
1137 return CC2;
1138 case LE:
1139 case LEU:
1140 return CC0 | CC1;
1141 case GE:
1142 case GEU:
1143 return CC0 | CC2;
1144 default:
1145 gcc_unreachable ();
1146 }
1147 return -1;
1148 }
1149
1150 /* If INV is false, return assembler mnemonic string to implement
1151 a branch specified by CODE. If INV is true, return mnemonic
1152 for the corresponding inverted branch. */
1153
1154 static const char *
1155 s390_branch_condition_mnemonic (rtx code, int inv)
1156 {
1157 int mask;
1158
1159 static const char *const mnemonic[16] =
1160 {
1161 NULL, "o", "h", "nle",
1162 "l", "nhe", "lh", "ne",
1163 "e", "nlh", "he", "nl",
1164 "le", "nh", "no", NULL
1165 };
1166
1167 if (GET_CODE (XEXP (code, 0)) == REG
1168 && REGNO (XEXP (code, 0)) == CC_REGNUM
1169 && XEXP (code, 1) == const0_rtx)
1170 mask = s390_branch_condition_mask (code);
1171 else
1172 mask = s390_compare_and_branch_condition_mask (code);
1173
1174 gcc_assert (mask >= 0);
1175
1176 if (inv)
1177 mask ^= 15;
1178
1179 gcc_assert (mask >= 1 && mask <= 14);
1180
1181 return mnemonic[mask];
1182 }
1183
1184 /* Return the part of op which has a value different from def.
1185 The size of the part is determined by mode.
1186 Use this function only if you already know that op really
1187 contains such a part. */
1188
1189 unsigned HOST_WIDE_INT
1190 s390_extract_part (rtx op, enum machine_mode mode, int def)
1191 {
1192 unsigned HOST_WIDE_INT value = 0;
1193 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1194 int part_bits = GET_MODE_BITSIZE (mode);
1195 unsigned HOST_WIDE_INT part_mask
1196 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1197 int i;
1198
1199 for (i = 0; i < max_parts; i++)
1200 {
1201 if (i == 0)
1202 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1203 else
1204 value >>= part_bits;
1205
1206 if ((value & part_mask) != (def & part_mask))
1207 return value & part_mask;
1208 }
1209
1210 gcc_unreachable ();
1211 }
1212
1213 /* If OP is an integer constant of mode MODE with exactly one
1214 part of mode PART_MODE unequal to DEF, return the number of that
1215 part. Otherwise, return -1. */
1216
1217 int
1218 s390_single_part (rtx op,
1219 enum machine_mode mode,
1220 enum machine_mode part_mode,
1221 int def)
1222 {
1223 unsigned HOST_WIDE_INT value = 0;
1224 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1225 unsigned HOST_WIDE_INT part_mask
1226 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1227 int i, part = -1;
1228
1229 if (GET_CODE (op) != CONST_INT)
1230 return -1;
1231
1232 for (i = 0; i < n_parts; i++)
1233 {
1234 if (i == 0)
1235 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1236 else
1237 value >>= GET_MODE_BITSIZE (part_mode);
1238
1239 if ((value & part_mask) != (def & part_mask))
1240 {
1241 if (part != -1)
1242 return -1;
1243 else
1244 part = i;
1245 }
1246 }
1247 return part == -1 ? -1 : n_parts - 1 - part;
1248 }
1249
1250 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1251 bits and no other bits are set in IN. POS and LENGTH can be used
1252 to obtain the start position and the length of the bitfield.
1253
1254 POS gives the position of the first bit of the bitfield counting
1255 from the lowest order bit starting with zero. In order to use this
1256 value for S/390 instructions this has to be converted to "bits big
1257 endian" style. */
1258
1259 bool
1260 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1261 int *pos, int *length)
1262 {
1263 int tmp_pos = 0;
1264 int tmp_length = 0;
1265 int i;
1266 unsigned HOST_WIDE_INT mask = 1ULL;
1267 bool contiguous = false;
1268
1269 for (i = 0; i < size; mask <<= 1, i++)
1270 {
1271 if (contiguous)
1272 {
1273 if (mask & in)
1274 tmp_length++;
1275 else
1276 break;
1277 }
1278 else
1279 {
1280 if (mask & in)
1281 {
1282 contiguous = true;
1283 tmp_length++;
1284 }
1285 else
1286 tmp_pos++;
1287 }
1288 }
1289
1290 if (!tmp_length)
1291 return false;
1292
1293 /* Calculate a mask for all bits beyond the contiguous bits. */
1294 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1295
1296 if (mask & in)
1297 return false;
1298
1299 if (tmp_length + tmp_pos - 1 > size)
1300 return false;
1301
1302 if (length)
1303 *length = tmp_length;
1304
1305 if (pos)
1306 *pos = tmp_pos;
1307
1308 return true;
1309 }
1310
1311 /* Check whether we can (and want to) split a double-word
1312 move in mode MODE from SRC to DST into two single-word
1313 moves, moving the subword FIRST_SUBWORD first. */
1314
1315 bool
1316 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1317 {
1318 /* Floating point registers cannot be split. */
1319 if (FP_REG_P (src) || FP_REG_P (dst))
1320 return false;
1321
1322 /* We don't need to split if operands are directly accessible. */
1323 if (s_operand (src, mode) || s_operand (dst, mode))
1324 return false;
1325
1326 /* Non-offsettable memory references cannot be split. */
1327 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1328 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1329 return false;
1330
1331 /* Moving the first subword must not clobber a register
1332 needed to move the second subword. */
1333 if (register_operand (dst, mode))
1334 {
1335 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1336 if (reg_overlap_mentioned_p (subreg, src))
1337 return false;
1338 }
1339
1340 return true;
1341 }
1342
1343 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1344 and [MEM2, MEM2 + SIZE] do overlap and false
1345 otherwise. */
1346
1347 bool
1348 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1349 {
1350 rtx addr1, addr2, addr_delta;
1351 HOST_WIDE_INT delta;
1352
1353 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1354 return true;
1355
1356 if (size == 0)
1357 return false;
1358
1359 addr1 = XEXP (mem1, 0);
1360 addr2 = XEXP (mem2, 0);
1361
1362 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1363
1364 /* This overlapping check is used by peepholes merging memory block operations.
1365 Overlapping operations would otherwise be recognized by the S/390 hardware
1366 and would fall back to a slower implementation. Allowing overlapping
1367 operations would lead to slow code but not to wrong code. Therefore we are
1368 somewhat optimistic if we cannot prove that the memory blocks are
1369 overlapping.
1370 That's why we return false here although this may accept operations on
1371 overlapping memory areas. */
1372 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1373 return false;
1374
1375 delta = INTVAL (addr_delta);
1376
1377 if (delta == 0
1378 || (delta > 0 && delta < size)
1379 || (delta < 0 && -delta < size))
1380 return true;
1381
1382 return false;
1383 }
1384
1385 /* Check whether the address of memory reference MEM2 equals exactly
1386 the address of memory reference MEM1 plus DELTA. Return true if
1387 we can prove this to be the case, false otherwise. */
1388
1389 bool
1390 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1391 {
1392 rtx addr1, addr2, addr_delta;
1393
1394 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1395 return false;
1396
1397 addr1 = XEXP (mem1, 0);
1398 addr2 = XEXP (mem2, 0);
1399
1400 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1401 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1402 return false;
1403
1404 return true;
1405 }
1406
1407 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1408
1409 void
1410 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1411 rtx *operands)
1412 {
1413 enum machine_mode wmode = mode;
1414 rtx dst = operands[0];
1415 rtx src1 = operands[1];
1416 rtx src2 = operands[2];
1417 rtx op, clob, tem;
1418
1419 /* If we cannot handle the operation directly, use a temp register. */
1420 if (!s390_logical_operator_ok_p (operands))
1421 dst = gen_reg_rtx (mode);
1422
1423 /* QImode and HImode patterns make sense only if we have a destination
1424 in memory. Otherwise perform the operation in SImode. */
1425 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1426 wmode = SImode;
1427
1428 /* Widen operands if required. */
1429 if (mode != wmode)
1430 {
1431 if (GET_CODE (dst) == SUBREG
1432 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1433 dst = tem;
1434 else if (REG_P (dst))
1435 dst = gen_rtx_SUBREG (wmode, dst, 0);
1436 else
1437 dst = gen_reg_rtx (wmode);
1438
1439 if (GET_CODE (src1) == SUBREG
1440 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1441 src1 = tem;
1442 else if (GET_MODE (src1) != VOIDmode)
1443 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1444
1445 if (GET_CODE (src2) == SUBREG
1446 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1447 src2 = tem;
1448 else if (GET_MODE (src2) != VOIDmode)
1449 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1450 }
1451
1452 /* Emit the instruction. */
1453 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1454 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1455 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1456
1457 /* Fix up the destination if needed. */
1458 if (dst != operands[0])
1459 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1460 }
1461
1462 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1463
1464 bool
1465 s390_logical_operator_ok_p (rtx *operands)
1466 {
1467 /* If the destination operand is in memory, it needs to coincide
1468 with one of the source operands. After reload, it has to be
1469 the first source operand. */
1470 if (GET_CODE (operands[0]) == MEM)
1471 return rtx_equal_p (operands[0], operands[1])
1472 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1473
1474 return true;
1475 }
1476
1477 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1478 operand IMMOP to switch from SS to SI type instructions. */
1479
1480 void
1481 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1482 {
1483 int def = code == AND ? -1 : 0;
1484 HOST_WIDE_INT mask;
1485 int part;
1486
1487 gcc_assert (GET_CODE (*memop) == MEM);
1488 gcc_assert (!MEM_VOLATILE_P (*memop));
1489
1490 mask = s390_extract_part (*immop, QImode, def);
1491 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1492 gcc_assert (part >= 0);
1493
1494 *memop = adjust_address (*memop, QImode, part);
1495 *immop = gen_int_mode (mask, QImode);
1496 }
1497
1498
1499 /* How to allocate a 'struct machine_function'. */
1500
1501 static struct machine_function *
1502 s390_init_machine_status (void)
1503 {
1504 return ggc_alloc_cleared_machine_function ();
1505 }
1506
1507 static void
1508 s390_option_override (void)
1509 {
1510 /* Set up function hooks. */
1511 init_machine_status = s390_init_machine_status;
1512
1513 /* Architecture mode defaults according to ABI. */
1514 if (!(target_flags_explicit & MASK_ZARCH))
1515 {
1516 if (TARGET_64BIT)
1517 target_flags |= MASK_ZARCH;
1518 else
1519 target_flags &= ~MASK_ZARCH;
1520 }
1521
1522 /* Set the march default in case it hasn't been specified on
1523 cmdline. */
1524 if (s390_arch == PROCESSOR_max)
1525 {
1526 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1527 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1528 s390_arch_flags = processor_flags_table[(int)s390_arch];
1529 }
1530
1531 /* Determine processor to tune for. */
1532 if (s390_tune == PROCESSOR_max)
1533 {
1534 s390_tune = s390_arch;
1535 s390_tune_flags = s390_arch_flags;
1536 }
1537
1538 /* Sanity checks. */
1539 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1540 error ("z/Architecture mode not supported on %s", s390_arch_string);
1541 if (TARGET_64BIT && !TARGET_ZARCH)
1542 error ("64-bit ABI not supported in ESA/390 mode");
1543
1544 /* Use hardware DFP if available and not explicitly disabled by
1545 user. E.g. with -m31 -march=z10 -mzarch */
1546 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1547 target_flags |= MASK_HARD_DFP;
1548
1549 if (TARGET_HARD_DFP && !TARGET_DFP)
1550 {
1551 if (target_flags_explicit & MASK_HARD_DFP)
1552 {
1553 if (!TARGET_CPU_DFP)
1554 error ("hardware decimal floating point instructions"
1555 " not available on %s", s390_arch_string);
1556 if (!TARGET_ZARCH)
1557 error ("hardware decimal floating point instructions"
1558 " not available in ESA/390 mode");
1559 }
1560 else
1561 target_flags &= ~MASK_HARD_DFP;
1562 }
1563
1564 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1565 {
1566 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1567 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1568
1569 target_flags &= ~MASK_HARD_DFP;
1570 }
1571
1572 /* Set processor cost function. */
1573 switch (s390_tune)
1574 {
1575 case PROCESSOR_2084_Z990:
1576 s390_cost = &z990_cost;
1577 break;
1578 case PROCESSOR_2094_Z9_109:
1579 s390_cost = &z9_109_cost;
1580 break;
1581 case PROCESSOR_2097_Z10:
1582 s390_cost = &z10_cost;
1583 case PROCESSOR_2817_Z196:
1584 s390_cost = &z196_cost;
1585 break;
1586 default:
1587 s390_cost = &z900_cost;
1588 }
1589
1590 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1591 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1592 "in combination");
1593
1594 if (s390_stack_size)
1595 {
1596 if (s390_stack_guard >= s390_stack_size)
1597 error ("stack size must be greater than the stack guard value");
1598 else if (s390_stack_size > 1 << 16)
1599 error ("stack size must not be greater than 64k");
1600 }
1601 else if (s390_stack_guard)
1602 error ("-mstack-guard implies use of -mstack-size");
1603
1604 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1605 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1606 target_flags |= MASK_LONG_DOUBLE_128;
1607 #endif
1608
1609 if (s390_tune == PROCESSOR_2097_Z10
1610 || s390_tune == PROCESSOR_2817_Z196)
1611 {
1612 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1613 global_options.x_param_values,
1614 global_options_set.x_param_values);
1615 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1616 global_options.x_param_values,
1617 global_options_set.x_param_values);
1618 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1619 global_options.x_param_values,
1620 global_options_set.x_param_values);
1621 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1622 global_options.x_param_values,
1623 global_options_set.x_param_values);
1624 }
1625
1626 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1627 global_options.x_param_values,
1628 global_options_set.x_param_values);
1629 /* values for loop prefetching */
1630 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1631 global_options.x_param_values,
1632 global_options_set.x_param_values);
1633 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1634 global_options.x_param_values,
1635 global_options_set.x_param_values);
1636 /* s390 has more than 2 levels and the size is much larger. Since
1637 we are always running virtualized assume that we only get a small
1638 part of the caches above l1. */
1639 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1640 global_options.x_param_values,
1641 global_options_set.x_param_values);
1642 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1643 global_options.x_param_values,
1644 global_options_set.x_param_values);
1645 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1646 global_options.x_param_values,
1647 global_options_set.x_param_values);
1648
1649 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1650 requires the arch flags to be evaluated already. Since prefetching
1651 is beneficial on s390, we enable it if available. */
1652 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1653 flag_prefetch_loop_arrays = 1;
1654
1655 /* Use the alternative scheduling-pressure algorithm by default. */
1656 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
1657 global_options.x_param_values,
1658 global_options_set.x_param_values);
1659
1660 if (TARGET_TPF)
1661 {
1662 /* Don't emit DWARF3/4 unless specifically selected. The TPF
1663 debuggers do not yet support DWARF 3/4. */
1664 if (!global_options_set.x_dwarf_strict)
1665 dwarf_strict = 1;
1666 if (!global_options_set.x_dwarf_version)
1667 dwarf_version = 2;
1668 }
1669 }
1670
1671 /* Map for smallest class containing reg regno. */
1672
1673 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1674 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1675 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1676 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1677 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1678 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1679 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1680 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1681 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1682 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1683 ACCESS_REGS, ACCESS_REGS
1684 };
1685
1686 /* Return attribute type of insn. */
1687
1688 static enum attr_type
1689 s390_safe_attr_type (rtx insn)
1690 {
1691 if (recog_memoized (insn) >= 0)
1692 return get_attr_type (insn);
1693 else
1694 return TYPE_NONE;
1695 }
1696
1697 /* Return true if DISP is a valid short displacement. */
1698
1699 static bool
1700 s390_short_displacement (rtx disp)
1701 {
1702 /* No displacement is OK. */
1703 if (!disp)
1704 return true;
1705
1706 /* Without the long displacement facility we don't need to
1707 distingiush between long and short displacement. */
1708 if (!TARGET_LONG_DISPLACEMENT)
1709 return true;
1710
1711 /* Integer displacement in range. */
1712 if (GET_CODE (disp) == CONST_INT)
1713 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1714
1715 /* GOT offset is not OK, the GOT can be large. */
1716 if (GET_CODE (disp) == CONST
1717 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1718 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1719 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1720 return false;
1721
1722 /* All other symbolic constants are literal pool references,
1723 which are OK as the literal pool must be small. */
1724 if (GET_CODE (disp) == CONST)
1725 return true;
1726
1727 return false;
1728 }
1729
1730 /* Decompose a RTL expression ADDR for a memory address into
1731 its components, returned in OUT.
1732
1733 Returns false if ADDR is not a valid memory address, true
1734 otherwise. If OUT is NULL, don't return the components,
1735 but check for validity only.
1736
1737 Note: Only addresses in canonical form are recognized.
1738 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1739 canonical form so that they will be recognized. */
1740
1741 static int
1742 s390_decompose_address (rtx addr, struct s390_address *out)
1743 {
1744 HOST_WIDE_INT offset = 0;
1745 rtx base = NULL_RTX;
1746 rtx indx = NULL_RTX;
1747 rtx disp = NULL_RTX;
1748 rtx orig_disp;
1749 bool pointer = false;
1750 bool base_ptr = false;
1751 bool indx_ptr = false;
1752 bool literal_pool = false;
1753
1754 /* We may need to substitute the literal pool base register into the address
1755 below. However, at this point we do not know which register is going to
1756 be used as base, so we substitute the arg pointer register. This is going
1757 to be treated as holding a pointer below -- it shouldn't be used for any
1758 other purpose. */
1759 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1760
1761 /* Decompose address into base + index + displacement. */
1762
1763 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1764 base = addr;
1765
1766 else if (GET_CODE (addr) == PLUS)
1767 {
1768 rtx op0 = XEXP (addr, 0);
1769 rtx op1 = XEXP (addr, 1);
1770 enum rtx_code code0 = GET_CODE (op0);
1771 enum rtx_code code1 = GET_CODE (op1);
1772
1773 if (code0 == REG || code0 == UNSPEC)
1774 {
1775 if (code1 == REG || code1 == UNSPEC)
1776 {
1777 indx = op0; /* index + base */
1778 base = op1;
1779 }
1780
1781 else
1782 {
1783 base = op0; /* base + displacement */
1784 disp = op1;
1785 }
1786 }
1787
1788 else if (code0 == PLUS)
1789 {
1790 indx = XEXP (op0, 0); /* index + base + disp */
1791 base = XEXP (op0, 1);
1792 disp = op1;
1793 }
1794
1795 else
1796 {
1797 return false;
1798 }
1799 }
1800
1801 else
1802 disp = addr; /* displacement */
1803
1804 /* Extract integer part of displacement. */
1805 orig_disp = disp;
1806 if (disp)
1807 {
1808 if (GET_CODE (disp) == CONST_INT)
1809 {
1810 offset = INTVAL (disp);
1811 disp = NULL_RTX;
1812 }
1813 else if (GET_CODE (disp) == CONST
1814 && GET_CODE (XEXP (disp, 0)) == PLUS
1815 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1816 {
1817 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1818 disp = XEXP (XEXP (disp, 0), 0);
1819 }
1820 }
1821
1822 /* Strip off CONST here to avoid special case tests later. */
1823 if (disp && GET_CODE (disp) == CONST)
1824 disp = XEXP (disp, 0);
1825
1826 /* We can convert literal pool addresses to
1827 displacements by basing them off the base register. */
1828 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1829 {
1830 /* Either base or index must be free to hold the base register. */
1831 if (!base)
1832 base = fake_pool_base, literal_pool = true;
1833 else if (!indx)
1834 indx = fake_pool_base, literal_pool = true;
1835 else
1836 return false;
1837
1838 /* Mark up the displacement. */
1839 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1840 UNSPEC_LTREL_OFFSET);
1841 }
1842
1843 /* Validate base register. */
1844 if (base)
1845 {
1846 if (GET_CODE (base) == UNSPEC)
1847 switch (XINT (base, 1))
1848 {
1849 case UNSPEC_LTREF:
1850 if (!disp)
1851 disp = gen_rtx_UNSPEC (Pmode,
1852 gen_rtvec (1, XVECEXP (base, 0, 0)),
1853 UNSPEC_LTREL_OFFSET);
1854 else
1855 return false;
1856
1857 base = XVECEXP (base, 0, 1);
1858 break;
1859
1860 case UNSPEC_LTREL_BASE:
1861 if (XVECLEN (base, 0) == 1)
1862 base = fake_pool_base, literal_pool = true;
1863 else
1864 base = XVECEXP (base, 0, 1);
1865 break;
1866
1867 default:
1868 return false;
1869 }
1870
1871 if (!REG_P (base)
1872 || (GET_MODE (base) != SImode
1873 && GET_MODE (base) != Pmode))
1874 return false;
1875
1876 if (REGNO (base) == STACK_POINTER_REGNUM
1877 || REGNO (base) == FRAME_POINTER_REGNUM
1878 || ((reload_completed || reload_in_progress)
1879 && frame_pointer_needed
1880 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1881 || REGNO (base) == ARG_POINTER_REGNUM
1882 || (flag_pic
1883 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1884 pointer = base_ptr = true;
1885
1886 if ((reload_completed || reload_in_progress)
1887 && base == cfun->machine->base_reg)
1888 pointer = base_ptr = literal_pool = true;
1889 }
1890
1891 /* Validate index register. */
1892 if (indx)
1893 {
1894 if (GET_CODE (indx) == UNSPEC)
1895 switch (XINT (indx, 1))
1896 {
1897 case UNSPEC_LTREF:
1898 if (!disp)
1899 disp = gen_rtx_UNSPEC (Pmode,
1900 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1901 UNSPEC_LTREL_OFFSET);
1902 else
1903 return false;
1904
1905 indx = XVECEXP (indx, 0, 1);
1906 break;
1907
1908 case UNSPEC_LTREL_BASE:
1909 if (XVECLEN (indx, 0) == 1)
1910 indx = fake_pool_base, literal_pool = true;
1911 else
1912 indx = XVECEXP (indx, 0, 1);
1913 break;
1914
1915 default:
1916 return false;
1917 }
1918
1919 if (!REG_P (indx)
1920 || (GET_MODE (indx) != SImode
1921 && GET_MODE (indx) != Pmode))
1922 return false;
1923
1924 if (REGNO (indx) == STACK_POINTER_REGNUM
1925 || REGNO (indx) == FRAME_POINTER_REGNUM
1926 || ((reload_completed || reload_in_progress)
1927 && frame_pointer_needed
1928 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1929 || REGNO (indx) == ARG_POINTER_REGNUM
1930 || (flag_pic
1931 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1932 pointer = indx_ptr = true;
1933
1934 if ((reload_completed || reload_in_progress)
1935 && indx == cfun->machine->base_reg)
1936 pointer = indx_ptr = literal_pool = true;
1937 }
1938
1939 /* Prefer to use pointer as base, not index. */
1940 if (base && indx && !base_ptr
1941 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1942 {
1943 rtx tmp = base;
1944 base = indx;
1945 indx = tmp;
1946 }
1947
1948 /* Validate displacement. */
1949 if (!disp)
1950 {
1951 /* If virtual registers are involved, the displacement will change later
1952 anyway as the virtual registers get eliminated. This could make a
1953 valid displacement invalid, but it is more likely to make an invalid
1954 displacement valid, because we sometimes access the register save area
1955 via negative offsets to one of those registers.
1956 Thus we don't check the displacement for validity here. If after
1957 elimination the displacement turns out to be invalid after all,
1958 this is fixed up by reload in any case. */
1959 if (base != arg_pointer_rtx
1960 && indx != arg_pointer_rtx
1961 && base != return_address_pointer_rtx
1962 && indx != return_address_pointer_rtx
1963 && base != frame_pointer_rtx
1964 && indx != frame_pointer_rtx
1965 && base != virtual_stack_vars_rtx
1966 && indx != virtual_stack_vars_rtx)
1967 if (!DISP_IN_RANGE (offset))
1968 return false;
1969 }
1970 else
1971 {
1972 /* All the special cases are pointers. */
1973 pointer = true;
1974
1975 /* In the small-PIC case, the linker converts @GOT
1976 and @GOTNTPOFF offsets to possible displacements. */
1977 if (GET_CODE (disp) == UNSPEC
1978 && (XINT (disp, 1) == UNSPEC_GOT
1979 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1980 && flag_pic == 1)
1981 {
1982 ;
1983 }
1984
1985 /* Accept pool label offsets. */
1986 else if (GET_CODE (disp) == UNSPEC
1987 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1988 ;
1989
1990 /* Accept literal pool references. */
1991 else if (GET_CODE (disp) == UNSPEC
1992 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1993 {
1994 /* In case CSE pulled a non literal pool reference out of
1995 the pool we have to reject the address. This is
1996 especially important when loading the GOT pointer on non
1997 zarch CPUs. In this case the literal pool contains an lt
1998 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1999 will most likely exceed the displacement. */
2000 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2001 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2002 return false;
2003
2004 orig_disp = gen_rtx_CONST (Pmode, disp);
2005 if (offset)
2006 {
2007 /* If we have an offset, make sure it does not
2008 exceed the size of the constant pool entry. */
2009 rtx sym = XVECEXP (disp, 0, 0);
2010 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2011 return false;
2012
2013 orig_disp = plus_constant (Pmode, orig_disp, offset);
2014 }
2015 }
2016
2017 else
2018 return false;
2019 }
2020
2021 if (!base && !indx)
2022 pointer = true;
2023
2024 if (out)
2025 {
2026 out->base = base;
2027 out->indx = indx;
2028 out->disp = orig_disp;
2029 out->pointer = pointer;
2030 out->literal_pool = literal_pool;
2031 }
2032
2033 return true;
2034 }
2035
2036 /* Decompose a RTL expression OP for a shift count into its components,
2037 and return the base register in BASE and the offset in OFFSET.
2038
2039 Return true if OP is a valid shift count, false if not. */
2040
2041 bool
2042 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2043 {
2044 HOST_WIDE_INT off = 0;
2045
2046 /* We can have an integer constant, an address register,
2047 or a sum of the two. */
2048 if (GET_CODE (op) == CONST_INT)
2049 {
2050 off = INTVAL (op);
2051 op = NULL_RTX;
2052 }
2053 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2054 {
2055 off = INTVAL (XEXP (op, 1));
2056 op = XEXP (op, 0);
2057 }
2058 while (op && GET_CODE (op) == SUBREG)
2059 op = SUBREG_REG (op);
2060
2061 if (op && GET_CODE (op) != REG)
2062 return false;
2063
2064 if (offset)
2065 *offset = off;
2066 if (base)
2067 *base = op;
2068
2069 return true;
2070 }
2071
2072
2073 /* Return true if CODE is a valid address without index. */
2074
2075 bool
2076 s390_legitimate_address_without_index_p (rtx op)
2077 {
2078 struct s390_address addr;
2079
2080 if (!s390_decompose_address (XEXP (op, 0), &addr))
2081 return false;
2082 if (addr.indx)
2083 return false;
2084
2085 return true;
2086 }
2087
2088
2089 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2090 and return these parts in SYMREF and ADDEND. You can pass NULL in
2091 SYMREF and/or ADDEND if you are not interested in these values.
2092 Literal pool references are *not* considered symbol references. */
2093
2094 static bool
2095 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2096 {
2097 HOST_WIDE_INT tmpaddend = 0;
2098
2099 if (GET_CODE (addr) == CONST)
2100 addr = XEXP (addr, 0);
2101
2102 if (GET_CODE (addr) == PLUS)
2103 {
2104 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2105 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2106 && CONST_INT_P (XEXP (addr, 1)))
2107 {
2108 tmpaddend = INTVAL (XEXP (addr, 1));
2109 addr = XEXP (addr, 0);
2110 }
2111 else
2112 return false;
2113 }
2114 else
2115 if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2116 return false;
2117
2118 if (symref)
2119 *symref = addr;
2120 if (addend)
2121 *addend = tmpaddend;
2122
2123 return true;
2124 }
2125
2126 /* Return TRUE if ADDR is an operand valid for a load/store relative
2127 instructions. Be aware that the alignment of the operand needs to
2128 be checked separately. */
2129 static bool
2130 s390_loadrelative_operand_p (rtx addr)
2131 {
2132 if (GET_CODE (addr) == CONST)
2133 addr = XEXP (addr, 0);
2134
2135 /* Enable load relative for symbol@GOTENT. */
2136 if (GET_CODE (addr) == UNSPEC
2137 && XINT (addr, 1) == UNSPEC_GOTENT)
2138 return true;
2139
2140 return s390_symref_operand_p (addr, NULL, NULL);
2141 }
2142
2143 /* Return true if the address in OP is valid for constraint letter C
2144 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2145 pool MEMs should be accepted. Only the Q, R, S, T constraint
2146 letters are allowed for C. */
2147
2148 static int
2149 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2150 {
2151 struct s390_address addr;
2152 bool decomposed = false;
2153
2154 /* This check makes sure that no symbolic address (except literal
2155 pool references) are accepted by the R or T constraints. */
2156 if (s390_loadrelative_operand_p (op))
2157 return 0;
2158
2159 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2160 if (!lit_pool_ok)
2161 {
2162 if (!s390_decompose_address (op, &addr))
2163 return 0;
2164 if (addr.literal_pool)
2165 return 0;
2166 decomposed = true;
2167 }
2168
2169 switch (c)
2170 {
2171 case 'Q': /* no index short displacement */
2172 if (!decomposed && !s390_decompose_address (op, &addr))
2173 return 0;
2174 if (addr.indx)
2175 return 0;
2176 if (!s390_short_displacement (addr.disp))
2177 return 0;
2178 break;
2179
2180 case 'R': /* with index short displacement */
2181 if (TARGET_LONG_DISPLACEMENT)
2182 {
2183 if (!decomposed && !s390_decompose_address (op, &addr))
2184 return 0;
2185 if (!s390_short_displacement (addr.disp))
2186 return 0;
2187 }
2188 /* Any invalid address here will be fixed up by reload,
2189 so accept it for the most generic constraint. */
2190 break;
2191
2192 case 'S': /* no index long displacement */
2193 if (!TARGET_LONG_DISPLACEMENT)
2194 return 0;
2195 if (!decomposed && !s390_decompose_address (op, &addr))
2196 return 0;
2197 if (addr.indx)
2198 return 0;
2199 if (s390_short_displacement (addr.disp))
2200 return 0;
2201 break;
2202
2203 case 'T': /* with index long displacement */
2204 if (!TARGET_LONG_DISPLACEMENT)
2205 return 0;
2206 /* Any invalid address here will be fixed up by reload,
2207 so accept it for the most generic constraint. */
2208 if ((decomposed || s390_decompose_address (op, &addr))
2209 && s390_short_displacement (addr.disp))
2210 return 0;
2211 break;
2212 default:
2213 return 0;
2214 }
2215 return 1;
2216 }
2217
2218
2219 /* Evaluates constraint strings described by the regular expression
2220 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2221 the constraint given in STR, or 0 else. */
2222
2223 int
2224 s390_mem_constraint (const char *str, rtx op)
2225 {
2226 char c = str[0];
2227
2228 switch (c)
2229 {
2230 case 'A':
2231 /* Check for offsettable variants of memory constraints. */
2232 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2233 return 0;
2234 if ((reload_completed || reload_in_progress)
2235 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2236 return 0;
2237 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2238 case 'B':
2239 /* Check for non-literal-pool variants of memory constraints. */
2240 if (!MEM_P (op))
2241 return 0;
2242 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2243 case 'Q':
2244 case 'R':
2245 case 'S':
2246 case 'T':
2247 if (GET_CODE (op) != MEM)
2248 return 0;
2249 return s390_check_qrst_address (c, XEXP (op, 0), true);
2250 case 'U':
2251 return (s390_check_qrst_address ('Q', op, true)
2252 || s390_check_qrst_address ('R', op, true));
2253 case 'W':
2254 return (s390_check_qrst_address ('S', op, true)
2255 || s390_check_qrst_address ('T', op, true));
2256 case 'Y':
2257 /* Simply check for the basic form of a shift count. Reload will
2258 take care of making sure we have a proper base register. */
2259 if (!s390_decompose_shift_count (op, NULL, NULL))
2260 return 0;
2261 break;
2262 case 'Z':
2263 return s390_check_qrst_address (str[1], op, true);
2264 default:
2265 return 0;
2266 }
2267 return 1;
2268 }
2269
2270
2271 /* Evaluates constraint strings starting with letter O. Input
2272 parameter C is the second letter following the "O" in the constraint
2273 string. Returns 1 if VALUE meets the respective constraint and 0
2274 otherwise. */
2275
2276 int
2277 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2278 {
2279 if (!TARGET_EXTIMM)
2280 return 0;
2281
2282 switch (c)
2283 {
2284 case 's':
2285 return trunc_int_for_mode (value, SImode) == value;
2286
2287 case 'p':
2288 return value == 0
2289 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2290
2291 case 'n':
2292 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2293
2294 default:
2295 gcc_unreachable ();
2296 }
2297 }
2298
2299
2300 /* Evaluates constraint strings starting with letter N. Parameter STR
2301 contains the letters following letter "N" in the constraint string.
2302 Returns true if VALUE matches the constraint. */
2303
2304 int
2305 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2306 {
2307 enum machine_mode mode, part_mode;
2308 int def;
2309 int part, part_goal;
2310
2311
2312 if (str[0] == 'x')
2313 part_goal = -1;
2314 else
2315 part_goal = str[0] - '0';
2316
2317 switch (str[1])
2318 {
2319 case 'Q':
2320 part_mode = QImode;
2321 break;
2322 case 'H':
2323 part_mode = HImode;
2324 break;
2325 case 'S':
2326 part_mode = SImode;
2327 break;
2328 default:
2329 return 0;
2330 }
2331
2332 switch (str[2])
2333 {
2334 case 'H':
2335 mode = HImode;
2336 break;
2337 case 'S':
2338 mode = SImode;
2339 break;
2340 case 'D':
2341 mode = DImode;
2342 break;
2343 default:
2344 return 0;
2345 }
2346
2347 switch (str[3])
2348 {
2349 case '0':
2350 def = 0;
2351 break;
2352 case 'F':
2353 def = -1;
2354 break;
2355 default:
2356 return 0;
2357 }
2358
2359 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2360 return 0;
2361
2362 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2363 if (part < 0)
2364 return 0;
2365 if (part_goal != -1 && part_goal != part)
2366 return 0;
2367
2368 return 1;
2369 }
2370
2371
2372 /* Returns true if the input parameter VALUE is a float zero. */
2373
2374 int
2375 s390_float_const_zero_p (rtx value)
2376 {
2377 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2378 && value == CONST0_RTX (GET_MODE (value)));
2379 }
2380
2381 /* Implement TARGET_REGISTER_MOVE_COST. */
2382
2383 static int
2384 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2385 reg_class_t from, reg_class_t to)
2386 {
2387 /* On s390, copy between fprs and gprs is expensive. */
2388 if ((reg_classes_intersect_p (from, GENERAL_REGS)
2389 && reg_classes_intersect_p (to, FP_REGS))
2390 || (reg_classes_intersect_p (from, FP_REGS)
2391 && reg_classes_intersect_p (to, GENERAL_REGS)))
2392 return 10;
2393
2394 return 1;
2395 }
2396
2397 /* Implement TARGET_MEMORY_MOVE_COST. */
2398
2399 static int
2400 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2401 reg_class_t rclass ATTRIBUTE_UNUSED,
2402 bool in ATTRIBUTE_UNUSED)
2403 {
2404 return 1;
2405 }
2406
2407 /* Compute a (partial) cost for rtx X. Return true if the complete
2408 cost has been computed, and false if subexpressions should be
2409 scanned. In either case, *TOTAL contains the cost result.
2410 CODE contains GET_CODE (x), OUTER_CODE contains the code
2411 of the superexpression of x. */
2412
2413 static bool
2414 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2415 int *total, bool speed ATTRIBUTE_UNUSED)
2416 {
2417 switch (code)
2418 {
2419 case CONST:
2420 case CONST_INT:
2421 case LABEL_REF:
2422 case SYMBOL_REF:
2423 case CONST_DOUBLE:
2424 case MEM:
2425 *total = 0;
2426 return true;
2427
2428 case ASHIFT:
2429 case ASHIFTRT:
2430 case LSHIFTRT:
2431 case ROTATE:
2432 case ROTATERT:
2433 case AND:
2434 case IOR:
2435 case XOR:
2436 case NEG:
2437 case NOT:
2438 *total = COSTS_N_INSNS (1);
2439 return false;
2440
2441 case PLUS:
2442 case MINUS:
2443 *total = COSTS_N_INSNS (1);
2444 return false;
2445
2446 case MULT:
2447 switch (GET_MODE (x))
2448 {
2449 case SImode:
2450 {
2451 rtx left = XEXP (x, 0);
2452 rtx right = XEXP (x, 1);
2453 if (GET_CODE (right) == CONST_INT
2454 && CONST_OK_FOR_K (INTVAL (right)))
2455 *total = s390_cost->mhi;
2456 else if (GET_CODE (left) == SIGN_EXTEND)
2457 *total = s390_cost->mh;
2458 else
2459 *total = s390_cost->ms; /* msr, ms, msy */
2460 break;
2461 }
2462 case DImode:
2463 {
2464 rtx left = XEXP (x, 0);
2465 rtx right = XEXP (x, 1);
2466 if (TARGET_ZARCH)
2467 {
2468 if (GET_CODE (right) == CONST_INT
2469 && CONST_OK_FOR_K (INTVAL (right)))
2470 *total = s390_cost->mghi;
2471 else if (GET_CODE (left) == SIGN_EXTEND)
2472 *total = s390_cost->msgf;
2473 else
2474 *total = s390_cost->msg; /* msgr, msg */
2475 }
2476 else /* TARGET_31BIT */
2477 {
2478 if (GET_CODE (left) == SIGN_EXTEND
2479 && GET_CODE (right) == SIGN_EXTEND)
2480 /* mulsidi case: mr, m */
2481 *total = s390_cost->m;
2482 else if (GET_CODE (left) == ZERO_EXTEND
2483 && GET_CODE (right) == ZERO_EXTEND
2484 && TARGET_CPU_ZARCH)
2485 /* umulsidi case: ml, mlr */
2486 *total = s390_cost->ml;
2487 else
2488 /* Complex calculation is required. */
2489 *total = COSTS_N_INSNS (40);
2490 }
2491 break;
2492 }
2493 case SFmode:
2494 case DFmode:
2495 *total = s390_cost->mult_df;
2496 break;
2497 case TFmode:
2498 *total = s390_cost->mxbr;
2499 break;
2500 default:
2501 return false;
2502 }
2503 return false;
2504
2505 case FMA:
2506 switch (GET_MODE (x))
2507 {
2508 case DFmode:
2509 *total = s390_cost->madbr;
2510 break;
2511 case SFmode:
2512 *total = s390_cost->maebr;
2513 break;
2514 default:
2515 return false;
2516 }
2517 /* Negate in the third argument is free: FMSUB. */
2518 if (GET_CODE (XEXP (x, 2)) == NEG)
2519 {
2520 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2521 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2522 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2523 return true;
2524 }
2525 return false;
2526
2527 case UDIV:
2528 case UMOD:
2529 if (GET_MODE (x) == TImode) /* 128 bit division */
2530 *total = s390_cost->dlgr;
2531 else if (GET_MODE (x) == DImode)
2532 {
2533 rtx right = XEXP (x, 1);
2534 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2535 *total = s390_cost->dlr;
2536 else /* 64 by 64 bit division */
2537 *total = s390_cost->dlgr;
2538 }
2539 else if (GET_MODE (x) == SImode) /* 32 bit division */
2540 *total = s390_cost->dlr;
2541 return false;
2542
2543 case DIV:
2544 case MOD:
2545 if (GET_MODE (x) == DImode)
2546 {
2547 rtx right = XEXP (x, 1);
2548 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2549 if (TARGET_ZARCH)
2550 *total = s390_cost->dsgfr;
2551 else
2552 *total = s390_cost->dr;
2553 else /* 64 by 64 bit division */
2554 *total = s390_cost->dsgr;
2555 }
2556 else if (GET_MODE (x) == SImode) /* 32 bit division */
2557 *total = s390_cost->dlr;
2558 else if (GET_MODE (x) == SFmode)
2559 {
2560 *total = s390_cost->debr;
2561 }
2562 else if (GET_MODE (x) == DFmode)
2563 {
2564 *total = s390_cost->ddbr;
2565 }
2566 else if (GET_MODE (x) == TFmode)
2567 {
2568 *total = s390_cost->dxbr;
2569 }
2570 return false;
2571
2572 case SQRT:
2573 if (GET_MODE (x) == SFmode)
2574 *total = s390_cost->sqebr;
2575 else if (GET_MODE (x) == DFmode)
2576 *total = s390_cost->sqdbr;
2577 else /* TFmode */
2578 *total = s390_cost->sqxbr;
2579 return false;
2580
2581 case SIGN_EXTEND:
2582 case ZERO_EXTEND:
2583 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2584 || outer_code == PLUS || outer_code == MINUS
2585 || outer_code == COMPARE)
2586 *total = 0;
2587 return false;
2588
2589 case COMPARE:
2590 *total = COSTS_N_INSNS (1);
2591 if (GET_CODE (XEXP (x, 0)) == AND
2592 && GET_CODE (XEXP (x, 1)) == CONST_INT
2593 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2594 {
2595 rtx op0 = XEXP (XEXP (x, 0), 0);
2596 rtx op1 = XEXP (XEXP (x, 0), 1);
2597 rtx op2 = XEXP (x, 1);
2598
2599 if (memory_operand (op0, GET_MODE (op0))
2600 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2601 return true;
2602 if (register_operand (op0, GET_MODE (op0))
2603 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2604 return true;
2605 }
2606 return false;
2607
2608 default:
2609 return false;
2610 }
2611 }
2612
2613 /* Return the cost of an address rtx ADDR. */
2614
2615 static int
2616 s390_address_cost (rtx addr, enum machine_mode mode ATTRIBUTE_UNUSED,
2617 addr_space_t as ATTRIBUTE_UNUSED,
2618 bool speed ATTRIBUTE_UNUSED)
2619 {
2620 struct s390_address ad;
2621 if (!s390_decompose_address (addr, &ad))
2622 return 1000;
2623
2624 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2625 }
2626
2627 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2628 otherwise return 0. */
2629
2630 int
2631 tls_symbolic_operand (rtx op)
2632 {
2633 if (GET_CODE (op) != SYMBOL_REF)
2634 return 0;
2635 return SYMBOL_REF_TLS_MODEL (op);
2636 }
2637 \f
2638 /* Split DImode access register reference REG (on 64-bit) into its constituent
2639 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2640 gen_highpart cannot be used as they assume all registers are word-sized,
2641 while our access registers have only half that size. */
2642
2643 void
2644 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2645 {
2646 gcc_assert (TARGET_64BIT);
2647 gcc_assert (ACCESS_REG_P (reg));
2648 gcc_assert (GET_MODE (reg) == DImode);
2649 gcc_assert (!(REGNO (reg) & 1));
2650
2651 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2652 *hi = gen_rtx_REG (SImode, REGNO (reg));
2653 }
2654
2655 /* Return true if OP contains a symbol reference */
2656
2657 bool
2658 symbolic_reference_mentioned_p (rtx op)
2659 {
2660 const char *fmt;
2661 int i;
2662
2663 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2664 return 1;
2665
2666 fmt = GET_RTX_FORMAT (GET_CODE (op));
2667 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2668 {
2669 if (fmt[i] == 'E')
2670 {
2671 int j;
2672
2673 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2674 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2675 return 1;
2676 }
2677
2678 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2679 return 1;
2680 }
2681
2682 return 0;
2683 }
2684
2685 /* Return true if OP contains a reference to a thread-local symbol. */
2686
2687 bool
2688 tls_symbolic_reference_mentioned_p (rtx op)
2689 {
2690 const char *fmt;
2691 int i;
2692
2693 if (GET_CODE (op) == SYMBOL_REF)
2694 return tls_symbolic_operand (op);
2695
2696 fmt = GET_RTX_FORMAT (GET_CODE (op));
2697 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2698 {
2699 if (fmt[i] == 'E')
2700 {
2701 int j;
2702
2703 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2704 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2705 return true;
2706 }
2707
2708 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2709 return true;
2710 }
2711
2712 return false;
2713 }
2714
2715
2716 /* Return true if OP is a legitimate general operand when
2717 generating PIC code. It is given that flag_pic is on
2718 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2719
2720 int
2721 legitimate_pic_operand_p (rtx op)
2722 {
2723 /* Accept all non-symbolic constants. */
2724 if (!SYMBOLIC_CONST (op))
2725 return 1;
2726
2727 /* Reject everything else; must be handled
2728 via emit_symbolic_move. */
2729 return 0;
2730 }
2731
2732 /* Returns true if the constant value OP is a legitimate general operand.
2733 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2734
2735 static bool
2736 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2737 {
2738 /* Accept all non-symbolic constants. */
2739 if (!SYMBOLIC_CONST (op))
2740 return 1;
2741
2742 /* Accept immediate LARL operands. */
2743 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2744 return 1;
2745
2746 /* Thread-local symbols are never legal constants. This is
2747 so that emit_call knows that computing such addresses
2748 might require a function call. */
2749 if (TLS_SYMBOLIC_CONST (op))
2750 return 0;
2751
2752 /* In the PIC case, symbolic constants must *not* be
2753 forced into the literal pool. We accept them here,
2754 so that they will be handled by emit_symbolic_move. */
2755 if (flag_pic)
2756 return 1;
2757
2758 /* All remaining non-PIC symbolic constants are
2759 forced into the literal pool. */
2760 return 0;
2761 }
2762
2763 /* Determine if it's legal to put X into the constant pool. This
2764 is not possible if X contains the address of a symbol that is
2765 not constant (TLS) or not known at final link time (PIC). */
2766
2767 static bool
2768 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2769 {
2770 switch (GET_CODE (x))
2771 {
2772 case CONST_INT:
2773 case CONST_DOUBLE:
2774 /* Accept all non-symbolic constants. */
2775 return false;
2776
2777 case LABEL_REF:
2778 /* Labels are OK iff we are non-PIC. */
2779 return flag_pic != 0;
2780
2781 case SYMBOL_REF:
2782 /* 'Naked' TLS symbol references are never OK,
2783 non-TLS symbols are OK iff we are non-PIC. */
2784 if (tls_symbolic_operand (x))
2785 return true;
2786 else
2787 return flag_pic != 0;
2788
2789 case CONST:
2790 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2791 case PLUS:
2792 case MINUS:
2793 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2794 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2795
2796 case UNSPEC:
2797 switch (XINT (x, 1))
2798 {
2799 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2800 case UNSPEC_LTREL_OFFSET:
2801 case UNSPEC_GOT:
2802 case UNSPEC_GOTOFF:
2803 case UNSPEC_PLTOFF:
2804 case UNSPEC_TLSGD:
2805 case UNSPEC_TLSLDM:
2806 case UNSPEC_NTPOFF:
2807 case UNSPEC_DTPOFF:
2808 case UNSPEC_GOTNTPOFF:
2809 case UNSPEC_INDNTPOFF:
2810 return false;
2811
2812 /* If the literal pool shares the code section, be put
2813 execute template placeholders into the pool as well. */
2814 case UNSPEC_INSN:
2815 return TARGET_CPU_ZARCH;
2816
2817 default:
2818 return true;
2819 }
2820 break;
2821
2822 default:
2823 gcc_unreachable ();
2824 }
2825 }
2826
2827 /* Returns true if the constant value OP is a legitimate general
2828 operand during and after reload. The difference to
2829 legitimate_constant_p is that this function will not accept
2830 a constant that would need to be forced to the literal pool
2831 before it can be used as operand.
2832 This function accepts all constants which can be loaded directly
2833 into a GPR. */
2834
2835 bool
2836 legitimate_reload_constant_p (rtx op)
2837 {
2838 /* Accept la(y) operands. */
2839 if (GET_CODE (op) == CONST_INT
2840 && DISP_IN_RANGE (INTVAL (op)))
2841 return true;
2842
2843 /* Accept l(g)hi/l(g)fi operands. */
2844 if (GET_CODE (op) == CONST_INT
2845 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2846 return true;
2847
2848 /* Accept lliXX operands. */
2849 if (TARGET_ZARCH
2850 && GET_CODE (op) == CONST_INT
2851 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2852 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2853 return true;
2854
2855 if (TARGET_EXTIMM
2856 && GET_CODE (op) == CONST_INT
2857 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2858 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2859 return true;
2860
2861 /* Accept larl operands. */
2862 if (TARGET_CPU_ZARCH
2863 && larl_operand (op, VOIDmode))
2864 return true;
2865
2866 /* Accept floating-point zero operands that fit into a single GPR. */
2867 if (GET_CODE (op) == CONST_DOUBLE
2868 && s390_float_const_zero_p (op)
2869 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2870 return true;
2871
2872 /* Accept double-word operands that can be split. */
2873 if (GET_CODE (op) == CONST_INT
2874 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2875 {
2876 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2877 rtx hi = operand_subword (op, 0, 0, dword_mode);
2878 rtx lo = operand_subword (op, 1, 0, dword_mode);
2879 return legitimate_reload_constant_p (hi)
2880 && legitimate_reload_constant_p (lo);
2881 }
2882
2883 /* Everything else cannot be handled without reload. */
2884 return false;
2885 }
2886
2887 /* Returns true if the constant value OP is a legitimate fp operand
2888 during and after reload.
2889 This function accepts all constants which can be loaded directly
2890 into an FPR. */
2891
2892 static bool
2893 legitimate_reload_fp_constant_p (rtx op)
2894 {
2895 /* Accept floating-point zero operands if the load zero instruction
2896 can be used. */
2897 if (TARGET_Z196
2898 && GET_CODE (op) == CONST_DOUBLE
2899 && s390_float_const_zero_p (op))
2900 return true;
2901
2902 return false;
2903 }
2904
2905 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2906 return the class of reg to actually use. */
2907
2908 static reg_class_t
2909 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2910 {
2911 switch (GET_CODE (op))
2912 {
2913 /* Constants we cannot reload into general registers
2914 must be forced into the literal pool. */
2915 case CONST_DOUBLE:
2916 case CONST_INT:
2917 if (reg_class_subset_p (GENERAL_REGS, rclass)
2918 && legitimate_reload_constant_p (op))
2919 return GENERAL_REGS;
2920 else if (reg_class_subset_p (ADDR_REGS, rclass)
2921 && legitimate_reload_constant_p (op))
2922 return ADDR_REGS;
2923 else if (reg_class_subset_p (FP_REGS, rclass)
2924 && legitimate_reload_fp_constant_p (op))
2925 return FP_REGS;
2926 return NO_REGS;
2927
2928 /* If a symbolic constant or a PLUS is reloaded,
2929 it is most likely being used as an address, so
2930 prefer ADDR_REGS. If 'class' is not a superset
2931 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2932 case LABEL_REF:
2933 case SYMBOL_REF:
2934 case CONST:
2935 if (!legitimate_reload_constant_p (op))
2936 return NO_REGS;
2937 /* fallthrough */
2938 case PLUS:
2939 /* load address will be used. */
2940 if (reg_class_subset_p (ADDR_REGS, rclass))
2941 return ADDR_REGS;
2942 else
2943 return NO_REGS;
2944
2945 default:
2946 break;
2947 }
2948
2949 return rclass;
2950 }
2951
2952 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2953 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2954 aligned. */
2955
2956 bool
2957 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2958 {
2959 HOST_WIDE_INT addend;
2960 rtx symref;
2961
2962 /* Accept symbol@GOTENT with pointer size alignment. */
2963 if (GET_CODE (addr) == CONST
2964 && GET_CODE (XEXP (addr, 0)) == UNSPEC
2965 && XINT (XEXP (addr, 0), 1) == UNSPEC_GOTENT
2966 && alignment <= UNITS_PER_LONG)
2967 return true;
2968
2969 if (!s390_symref_operand_p (addr, &symref, &addend))
2970 return false;
2971
2972 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2973 && !(addend & (alignment - 1)));
2974 }
2975
2976 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2977 operand SCRATCH is used to reload the even part of the address and
2978 adding one. */
2979
2980 void
2981 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2982 {
2983 HOST_WIDE_INT addend;
2984 rtx symref;
2985
2986 if (!s390_symref_operand_p (addr, &symref, &addend))
2987 gcc_unreachable ();
2988
2989 if (!(addend & 1))
2990 /* Easy case. The addend is even so larl will do fine. */
2991 emit_move_insn (reg, addr);
2992 else
2993 {
2994 /* We can leave the scratch register untouched if the target
2995 register is a valid base register. */
2996 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2997 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2998 scratch = reg;
2999
3000 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3001 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3002
3003 if (addend != 1)
3004 emit_move_insn (scratch,
3005 gen_rtx_CONST (Pmode,
3006 gen_rtx_PLUS (Pmode, symref,
3007 GEN_INT (addend - 1))));
3008 else
3009 emit_move_insn (scratch, symref);
3010
3011 /* Increment the address using la in order to avoid clobbering cc. */
3012 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3013 }
3014 }
3015
3016 /* Generate what is necessary to move between REG and MEM using
3017 SCRATCH. The direction is given by TOMEM. */
3018
3019 void
3020 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3021 {
3022 /* Reload might have pulled a constant out of the literal pool.
3023 Force it back in. */
3024 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3025 || GET_CODE (mem) == CONST)
3026 mem = force_const_mem (GET_MODE (reg), mem);
3027
3028 gcc_assert (MEM_P (mem));
3029
3030 /* For a load from memory we can leave the scratch register
3031 untouched if the target register is a valid base register. */
3032 if (!tomem
3033 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3034 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3035 && GET_MODE (reg) == GET_MODE (scratch))
3036 scratch = reg;
3037
3038 /* Load address into scratch register. Since we can't have a
3039 secondary reload for a secondary reload we have to cover the case
3040 where larl would need a secondary reload here as well. */
3041 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3042
3043 /* Now we can use a standard load/store to do the move. */
3044 if (tomem)
3045 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3046 else
3047 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3048 }
3049
3050 /* Inform reload about cases where moving X with a mode MODE to a register in
3051 RCLASS requires an extra scratch or immediate register. Return the class
3052 needed for the immediate register. */
3053
3054 static reg_class_t
3055 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3056 enum machine_mode mode, secondary_reload_info *sri)
3057 {
3058 enum reg_class rclass = (enum reg_class) rclass_i;
3059
3060 /* Intermediate register needed. */
3061 if (reg_classes_intersect_p (CC_REGS, rclass))
3062 return GENERAL_REGS;
3063
3064 if (TARGET_Z10)
3065 {
3066 HOST_WIDE_INT offset;
3067 rtx symref;
3068
3069 /* On z10 several optimizer steps may generate larl operands with
3070 an odd addend. */
3071 if (in_p
3072 && s390_symref_operand_p (x, &symref, &offset)
3073 && mode == Pmode
3074 && !SYMBOL_REF_ALIGN1_P (symref)
3075 && (offset & 1) == 1)
3076 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3077 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3078
3079 /* On z10 we need a scratch register when moving QI, TI or floating
3080 point mode values from or to a memory location with a SYMBOL_REF
3081 or if the symref addend of a SI or DI move is not aligned to the
3082 width of the access. */
3083 if (MEM_P (x)
3084 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3085 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3086 || (!TARGET_ZARCH && mode == DImode)
3087 || ((mode == HImode || mode == SImode || mode == DImode)
3088 && (!s390_check_symref_alignment (XEXP (x, 0),
3089 GET_MODE_SIZE (mode))))))
3090 {
3091 #define __SECONDARY_RELOAD_CASE(M,m) \
3092 case M##mode: \
3093 if (TARGET_64BIT) \
3094 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3095 CODE_FOR_reload##m##di_tomem_z10; \
3096 else \
3097 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3098 CODE_FOR_reload##m##si_tomem_z10; \
3099 break;
3100
3101 switch (GET_MODE (x))
3102 {
3103 __SECONDARY_RELOAD_CASE (QI, qi);
3104 __SECONDARY_RELOAD_CASE (HI, hi);
3105 __SECONDARY_RELOAD_CASE (SI, si);
3106 __SECONDARY_RELOAD_CASE (DI, di);
3107 __SECONDARY_RELOAD_CASE (TI, ti);
3108 __SECONDARY_RELOAD_CASE (SF, sf);
3109 __SECONDARY_RELOAD_CASE (DF, df);
3110 __SECONDARY_RELOAD_CASE (TF, tf);
3111 __SECONDARY_RELOAD_CASE (SD, sd);
3112 __SECONDARY_RELOAD_CASE (DD, dd);
3113 __SECONDARY_RELOAD_CASE (TD, td);
3114
3115 default:
3116 gcc_unreachable ();
3117 }
3118 #undef __SECONDARY_RELOAD_CASE
3119 }
3120 }
3121
3122 /* We need a scratch register when loading a PLUS expression which
3123 is not a legitimate operand of the LOAD ADDRESS instruction. */
3124 if (in_p && s390_plus_operand (x, mode))
3125 sri->icode = (TARGET_64BIT ?
3126 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3127
3128 /* Performing a multiword move from or to memory we have to make sure the
3129 second chunk in memory is addressable without causing a displacement
3130 overflow. If that would be the case we calculate the address in
3131 a scratch register. */
3132 if (MEM_P (x)
3133 && GET_CODE (XEXP (x, 0)) == PLUS
3134 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3135 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3136 + GET_MODE_SIZE (mode) - 1))
3137 {
3138 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3139 in a s_operand address since we may fallback to lm/stm. So we only
3140 have to care about overflows in the b+i+d case. */
3141 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3142 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3143 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3144 /* For FP_REGS no lm/stm is available so this check is triggered
3145 for displacement overflows in b+i+d and b+d like addresses. */
3146 || (reg_classes_intersect_p (FP_REGS, rclass)
3147 && s390_class_max_nregs (FP_REGS, mode) > 1))
3148 {
3149 if (in_p)
3150 sri->icode = (TARGET_64BIT ?
3151 CODE_FOR_reloaddi_nonoffmem_in :
3152 CODE_FOR_reloadsi_nonoffmem_in);
3153 else
3154 sri->icode = (TARGET_64BIT ?
3155 CODE_FOR_reloaddi_nonoffmem_out :
3156 CODE_FOR_reloadsi_nonoffmem_out);
3157 }
3158 }
3159
3160 /* A scratch address register is needed when a symbolic constant is
3161 copied to r0 compiling with -fPIC. In other cases the target
3162 register might be used as temporary (see legitimize_pic_address). */
3163 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3164 sri->icode = (TARGET_64BIT ?
3165 CODE_FOR_reloaddi_PIC_addr :
3166 CODE_FOR_reloadsi_PIC_addr);
3167
3168 /* Either scratch or no register needed. */
3169 return NO_REGS;
3170 }
3171
3172 /* Generate code to load SRC, which is PLUS that is not a
3173 legitimate operand for the LA instruction, into TARGET.
3174 SCRATCH may be used as scratch register. */
3175
3176 void
3177 s390_expand_plus_operand (rtx target, rtx src,
3178 rtx scratch)
3179 {
3180 rtx sum1, sum2;
3181 struct s390_address ad;
3182
3183 /* src must be a PLUS; get its two operands. */
3184 gcc_assert (GET_CODE (src) == PLUS);
3185 gcc_assert (GET_MODE (src) == Pmode);
3186
3187 /* Check if any of the two operands is already scheduled
3188 for replacement by reload. This can happen e.g. when
3189 float registers occur in an address. */
3190 sum1 = find_replacement (&XEXP (src, 0));
3191 sum2 = find_replacement (&XEXP (src, 1));
3192 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3193
3194 /* If the address is already strictly valid, there's nothing to do. */
3195 if (!s390_decompose_address (src, &ad)
3196 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3197 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3198 {
3199 /* Otherwise, one of the operands cannot be an address register;
3200 we reload its value into the scratch register. */
3201 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3202 {
3203 emit_move_insn (scratch, sum1);
3204 sum1 = scratch;
3205 }
3206 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3207 {
3208 emit_move_insn (scratch, sum2);
3209 sum2 = scratch;
3210 }
3211
3212 /* According to the way these invalid addresses are generated
3213 in reload.c, it should never happen (at least on s390) that
3214 *neither* of the PLUS components, after find_replacements
3215 was applied, is an address register. */
3216 if (sum1 == scratch && sum2 == scratch)
3217 {
3218 debug_rtx (src);
3219 gcc_unreachable ();
3220 }
3221
3222 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3223 }
3224
3225 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3226 is only ever performed on addresses, so we can mark the
3227 sum as legitimate for LA in any case. */
3228 s390_load_address (target, src);
3229 }
3230
3231
3232 /* Return true if ADDR is a valid memory address.
3233 STRICT specifies whether strict register checking applies. */
3234
3235 static bool
3236 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3237 {
3238 struct s390_address ad;
3239
3240 if (TARGET_Z10
3241 && larl_operand (addr, VOIDmode)
3242 && (mode == VOIDmode
3243 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3244 return true;
3245
3246 if (!s390_decompose_address (addr, &ad))
3247 return false;
3248
3249 if (strict)
3250 {
3251 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3252 return false;
3253
3254 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3255 return false;
3256 }
3257 else
3258 {
3259 if (ad.base
3260 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3261 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3262 return false;
3263
3264 if (ad.indx
3265 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3266 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3267 return false;
3268 }
3269 return true;
3270 }
3271
3272 /* Return true if OP is a valid operand for the LA instruction.
3273 In 31-bit, we need to prove that the result is used as an
3274 address, as LA performs only a 31-bit addition. */
3275
3276 bool
3277 legitimate_la_operand_p (rtx op)
3278 {
3279 struct s390_address addr;
3280 if (!s390_decompose_address (op, &addr))
3281 return false;
3282
3283 return (TARGET_64BIT || addr.pointer);
3284 }
3285
3286 /* Return true if it is valid *and* preferable to use LA to
3287 compute the sum of OP1 and OP2. */
3288
3289 bool
3290 preferred_la_operand_p (rtx op1, rtx op2)
3291 {
3292 struct s390_address addr;
3293
3294 if (op2 != const0_rtx)
3295 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3296
3297 if (!s390_decompose_address (op1, &addr))
3298 return false;
3299 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3300 return false;
3301 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3302 return false;
3303
3304 /* Avoid LA instructions with index register on z196; it is
3305 preferable to use regular add instructions when possible. */
3306 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3307 return false;
3308
3309 if (!TARGET_64BIT && !addr.pointer)
3310 return false;
3311
3312 if (addr.pointer)
3313 return true;
3314
3315 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3316 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3317 return true;
3318
3319 return false;
3320 }
3321
3322 /* Emit a forced load-address operation to load SRC into DST.
3323 This will use the LOAD ADDRESS instruction even in situations
3324 where legitimate_la_operand_p (SRC) returns false. */
3325
3326 void
3327 s390_load_address (rtx dst, rtx src)
3328 {
3329 if (TARGET_64BIT)
3330 emit_move_insn (dst, src);
3331 else
3332 emit_insn (gen_force_la_31 (dst, src));
3333 }
3334
3335 /* Return a legitimate reference for ORIG (an address) using the
3336 register REG. If REG is 0, a new pseudo is generated.
3337
3338 There are two types of references that must be handled:
3339
3340 1. Global data references must load the address from the GOT, via
3341 the PIC reg. An insn is emitted to do this load, and the reg is
3342 returned.
3343
3344 2. Static data references, constant pool addresses, and code labels
3345 compute the address as an offset from the GOT, whose base is in
3346 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3347 differentiate them from global data objects. The returned
3348 address is the PIC reg + an unspec constant.
3349
3350 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3351 reg also appears in the address. */
3352
3353 rtx
3354 legitimize_pic_address (rtx orig, rtx reg)
3355 {
3356 rtx addr = orig;
3357 rtx new_rtx = orig;
3358 rtx base;
3359
3360 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3361
3362 if (GET_CODE (addr) == LABEL_REF
3363 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3364 {
3365 /* This is a local symbol. */
3366 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3367 {
3368 /* Access local symbols PC-relative via LARL.
3369 This is the same as in the non-PIC case, so it is
3370 handled automatically ... */
3371 }
3372 else
3373 {
3374 /* Access local symbols relative to the GOT. */
3375
3376 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3377
3378 if (reload_in_progress || reload_completed)
3379 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3380
3381 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3382 addr = gen_rtx_CONST (Pmode, addr);
3383 addr = force_const_mem (Pmode, addr);
3384 emit_move_insn (temp, addr);
3385
3386 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3387 if (reg != 0)
3388 {
3389 s390_load_address (reg, new_rtx);
3390 new_rtx = reg;
3391 }
3392 }
3393 }
3394 else if (GET_CODE (addr) == SYMBOL_REF)
3395 {
3396 if (reg == 0)
3397 reg = gen_reg_rtx (Pmode);
3398
3399 if (flag_pic == 1)
3400 {
3401 /* Assume GOT offset < 4k. This is handled the same way
3402 in both 31- and 64-bit code (@GOT). */
3403
3404 if (reload_in_progress || reload_completed)
3405 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3406
3407 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3408 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3409 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3410 new_rtx = gen_const_mem (Pmode, new_rtx);
3411 emit_move_insn (reg, new_rtx);
3412 new_rtx = reg;
3413 }
3414 else if (TARGET_CPU_ZARCH)
3415 {
3416 /* If the GOT offset might be >= 4k, we determine the position
3417 of the GOT entry via a PC-relative LARL (@GOTENT). */
3418
3419 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3420
3421 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3422 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3423
3424 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3425 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3426
3427 if (!TARGET_Z10)
3428 {
3429 emit_move_insn (temp, new_rtx);
3430 new_rtx = gen_const_mem (Pmode, temp);
3431 }
3432 else
3433 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3434 emit_move_insn (reg, new_rtx);
3435 new_rtx = reg;
3436 }
3437 else
3438 {
3439 /* If the GOT offset might be >= 4k, we have to load it
3440 from the literal pool (@GOT). */
3441
3442 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3443
3444 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3445 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3446
3447 if (reload_in_progress || reload_completed)
3448 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3449
3450 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3451 addr = gen_rtx_CONST (Pmode, addr);
3452 addr = force_const_mem (Pmode, addr);
3453 emit_move_insn (temp, addr);
3454
3455 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3456 new_rtx = gen_const_mem (Pmode, new_rtx);
3457 emit_move_insn (reg, new_rtx);
3458 new_rtx = reg;
3459 }
3460 }
3461 else
3462 {
3463 if (GET_CODE (addr) == CONST)
3464 {
3465 addr = XEXP (addr, 0);
3466 if (GET_CODE (addr) == UNSPEC)
3467 {
3468 gcc_assert (XVECLEN (addr, 0) == 1);
3469 switch (XINT (addr, 1))
3470 {
3471 /* If someone moved a GOT-relative UNSPEC
3472 out of the literal pool, force them back in. */
3473 case UNSPEC_GOTOFF:
3474 case UNSPEC_PLTOFF:
3475 new_rtx = force_const_mem (Pmode, orig);
3476 break;
3477
3478 /* @GOT is OK as is if small. */
3479 case UNSPEC_GOT:
3480 if (flag_pic == 2)
3481 new_rtx = force_const_mem (Pmode, orig);
3482 break;
3483
3484 /* @GOTENT is OK as is. */
3485 case UNSPEC_GOTENT:
3486 break;
3487
3488 /* @PLT is OK as is on 64-bit, must be converted to
3489 GOT-relative @PLTOFF on 31-bit. */
3490 case UNSPEC_PLT:
3491 if (!TARGET_CPU_ZARCH)
3492 {
3493 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3494
3495 if (reload_in_progress || reload_completed)
3496 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3497
3498 addr = XVECEXP (addr, 0, 0);
3499 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3500 UNSPEC_PLTOFF);
3501 addr = gen_rtx_CONST (Pmode, addr);
3502 addr = force_const_mem (Pmode, addr);
3503 emit_move_insn (temp, addr);
3504
3505 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3506 if (reg != 0)
3507 {
3508 s390_load_address (reg, new_rtx);
3509 new_rtx = reg;
3510 }
3511 }
3512 break;
3513
3514 /* Everything else cannot happen. */
3515 default:
3516 gcc_unreachable ();
3517 }
3518 }
3519 else
3520 gcc_assert (GET_CODE (addr) == PLUS);
3521 }
3522 if (GET_CODE (addr) == PLUS)
3523 {
3524 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3525
3526 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3527 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3528
3529 /* Check first to see if this is a constant offset
3530 from a local symbol reference. */
3531 if ((GET_CODE (op0) == LABEL_REF
3532 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3533 && GET_CODE (op1) == CONST_INT)
3534 {
3535 if (TARGET_CPU_ZARCH
3536 && larl_operand (op0, VOIDmode)
3537 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3538 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3539 {
3540 if (INTVAL (op1) & 1)
3541 {
3542 /* LARL can't handle odd offsets, so emit a
3543 pair of LARL and LA. */
3544 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3545
3546 if (!DISP_IN_RANGE (INTVAL (op1)))
3547 {
3548 HOST_WIDE_INT even = INTVAL (op1) - 1;
3549 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3550 op0 = gen_rtx_CONST (Pmode, op0);
3551 op1 = const1_rtx;
3552 }
3553
3554 emit_move_insn (temp, op0);
3555 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3556
3557 if (reg != 0)
3558 {
3559 s390_load_address (reg, new_rtx);
3560 new_rtx = reg;
3561 }
3562 }
3563 else
3564 {
3565 /* If the offset is even, we can just use LARL.
3566 This will happen automatically. */
3567 }
3568 }
3569 else
3570 {
3571 /* Access local symbols relative to the GOT. */
3572
3573 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3574
3575 if (reload_in_progress || reload_completed)
3576 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3577
3578 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3579 UNSPEC_GOTOFF);
3580 addr = gen_rtx_PLUS (Pmode, addr, op1);
3581 addr = gen_rtx_CONST (Pmode, addr);
3582 addr = force_const_mem (Pmode, addr);
3583 emit_move_insn (temp, addr);
3584
3585 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3586 if (reg != 0)
3587 {
3588 s390_load_address (reg, new_rtx);
3589 new_rtx = reg;
3590 }
3591 }
3592 }
3593
3594 /* Now, check whether it is a GOT relative symbol plus offset
3595 that was pulled out of the literal pool. Force it back in. */
3596
3597 else if (GET_CODE (op0) == UNSPEC
3598 && GET_CODE (op1) == CONST_INT
3599 && XINT (op0, 1) == UNSPEC_GOTOFF)
3600 {
3601 gcc_assert (XVECLEN (op0, 0) == 1);
3602
3603 new_rtx = force_const_mem (Pmode, orig);
3604 }
3605
3606 /* Otherwise, compute the sum. */
3607 else
3608 {
3609 base = legitimize_pic_address (XEXP (addr, 0), reg);
3610 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3611 base == reg ? NULL_RTX : reg);
3612 if (GET_CODE (new_rtx) == CONST_INT)
3613 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3614 else
3615 {
3616 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3617 {
3618 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3619 new_rtx = XEXP (new_rtx, 1);
3620 }
3621 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3622 }
3623
3624 if (GET_CODE (new_rtx) == CONST)
3625 new_rtx = XEXP (new_rtx, 0);
3626 new_rtx = force_operand (new_rtx, 0);
3627 }
3628 }
3629 }
3630 return new_rtx;
3631 }
3632
3633 /* Load the thread pointer into a register. */
3634
3635 rtx
3636 s390_get_thread_pointer (void)
3637 {
3638 rtx tp = gen_reg_rtx (Pmode);
3639
3640 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3641 mark_reg_pointer (tp, BITS_PER_WORD);
3642
3643 return tp;
3644 }
3645
3646 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3647 in s390_tls_symbol which always refers to __tls_get_offset.
3648 The returned offset is written to RESULT_REG and an USE rtx is
3649 generated for TLS_CALL. */
3650
3651 static GTY(()) rtx s390_tls_symbol;
3652
3653 static void
3654 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3655 {
3656 rtx insn;
3657
3658 if (!flag_pic)
3659 emit_insn (s390_load_got ());
3660
3661 if (!s390_tls_symbol)
3662 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3663
3664 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3665 gen_rtx_REG (Pmode, RETURN_REGNUM));
3666
3667 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3668 RTL_CONST_CALL_P (insn) = 1;
3669 }
3670
3671 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3672 this (thread-local) address. REG may be used as temporary. */
3673
3674 static rtx
3675 legitimize_tls_address (rtx addr, rtx reg)
3676 {
3677 rtx new_rtx, tls_call, temp, base, r2, insn;
3678
3679 if (GET_CODE (addr) == SYMBOL_REF)
3680 switch (tls_symbolic_operand (addr))
3681 {
3682 case TLS_MODEL_GLOBAL_DYNAMIC:
3683 start_sequence ();
3684 r2 = gen_rtx_REG (Pmode, 2);
3685 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3686 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3687 new_rtx = force_const_mem (Pmode, new_rtx);
3688 emit_move_insn (r2, new_rtx);
3689 s390_emit_tls_call_insn (r2, tls_call);
3690 insn = get_insns ();
3691 end_sequence ();
3692
3693 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3694 temp = gen_reg_rtx (Pmode);
3695 emit_libcall_block (insn, temp, r2, new_rtx);
3696
3697 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3698 if (reg != 0)
3699 {
3700 s390_load_address (reg, new_rtx);
3701 new_rtx = reg;
3702 }
3703 break;
3704
3705 case TLS_MODEL_LOCAL_DYNAMIC:
3706 start_sequence ();
3707 r2 = gen_rtx_REG (Pmode, 2);
3708 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3709 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3710 new_rtx = force_const_mem (Pmode, new_rtx);
3711 emit_move_insn (r2, new_rtx);
3712 s390_emit_tls_call_insn (r2, tls_call);
3713 insn = get_insns ();
3714 end_sequence ();
3715
3716 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3717 temp = gen_reg_rtx (Pmode);
3718 emit_libcall_block (insn, temp, r2, new_rtx);
3719
3720 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3721 base = gen_reg_rtx (Pmode);
3722 s390_load_address (base, new_rtx);
3723
3724 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3725 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3726 new_rtx = force_const_mem (Pmode, new_rtx);
3727 temp = gen_reg_rtx (Pmode);
3728 emit_move_insn (temp, new_rtx);
3729
3730 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3731 if (reg != 0)
3732 {
3733 s390_load_address (reg, new_rtx);
3734 new_rtx = reg;
3735 }
3736 break;
3737
3738 case TLS_MODEL_INITIAL_EXEC:
3739 if (flag_pic == 1)
3740 {
3741 /* Assume GOT offset < 4k. This is handled the same way
3742 in both 31- and 64-bit code. */
3743
3744 if (reload_in_progress || reload_completed)
3745 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3746
3747 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3748 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3749 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3750 new_rtx = gen_const_mem (Pmode, new_rtx);
3751 temp = gen_reg_rtx (Pmode);
3752 emit_move_insn (temp, new_rtx);
3753 }
3754 else if (TARGET_CPU_ZARCH)
3755 {
3756 /* If the GOT offset might be >= 4k, we determine the position
3757 of the GOT entry via a PC-relative LARL. */
3758
3759 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3760 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3761 temp = gen_reg_rtx (Pmode);
3762 emit_move_insn (temp, new_rtx);
3763
3764 new_rtx = gen_const_mem (Pmode, temp);
3765 temp = gen_reg_rtx (Pmode);
3766 emit_move_insn (temp, new_rtx);
3767 }
3768 else if (flag_pic)
3769 {
3770 /* If the GOT offset might be >= 4k, we have to load it
3771 from the literal pool. */
3772
3773 if (reload_in_progress || reload_completed)
3774 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3775
3776 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3777 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3778 new_rtx = force_const_mem (Pmode, new_rtx);
3779 temp = gen_reg_rtx (Pmode);
3780 emit_move_insn (temp, new_rtx);
3781
3782 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3783 new_rtx = gen_const_mem (Pmode, new_rtx);
3784
3785 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3786 temp = gen_reg_rtx (Pmode);
3787 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3788 }
3789 else
3790 {
3791 /* In position-dependent code, load the absolute address of
3792 the GOT entry from the literal pool. */
3793
3794 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3795 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3796 new_rtx = force_const_mem (Pmode, new_rtx);
3797 temp = gen_reg_rtx (Pmode);
3798 emit_move_insn (temp, new_rtx);
3799
3800 new_rtx = temp;
3801 new_rtx = gen_const_mem (Pmode, new_rtx);
3802 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3803 temp = gen_reg_rtx (Pmode);
3804 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3805 }
3806
3807 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3808 if (reg != 0)
3809 {
3810 s390_load_address (reg, new_rtx);
3811 new_rtx = reg;
3812 }
3813 break;
3814
3815 case TLS_MODEL_LOCAL_EXEC:
3816 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3817 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3818 new_rtx = force_const_mem (Pmode, new_rtx);
3819 temp = gen_reg_rtx (Pmode);
3820 emit_move_insn (temp, new_rtx);
3821
3822 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3823 if (reg != 0)
3824 {
3825 s390_load_address (reg, new_rtx);
3826 new_rtx = reg;
3827 }
3828 break;
3829
3830 default:
3831 gcc_unreachable ();
3832 }
3833
3834 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3835 {
3836 switch (XINT (XEXP (addr, 0), 1))
3837 {
3838 case UNSPEC_INDNTPOFF:
3839 gcc_assert (TARGET_CPU_ZARCH);
3840 new_rtx = addr;
3841 break;
3842
3843 default:
3844 gcc_unreachable ();
3845 }
3846 }
3847
3848 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3849 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3850 {
3851 new_rtx = XEXP (XEXP (addr, 0), 0);
3852 if (GET_CODE (new_rtx) != SYMBOL_REF)
3853 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3854
3855 new_rtx = legitimize_tls_address (new_rtx, reg);
3856 new_rtx = plus_constant (Pmode, new_rtx,
3857 INTVAL (XEXP (XEXP (addr, 0), 1)));
3858 new_rtx = force_operand (new_rtx, 0);
3859 }
3860
3861 else
3862 gcc_unreachable (); /* for now ... */
3863
3864 return new_rtx;
3865 }
3866
3867 /* Emit insns making the address in operands[1] valid for a standard
3868 move to operands[0]. operands[1] is replaced by an address which
3869 should be used instead of the former RTX to emit the move
3870 pattern. */
3871
3872 void
3873 emit_symbolic_move (rtx *operands)
3874 {
3875 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3876
3877 if (GET_CODE (operands[0]) == MEM)
3878 operands[1] = force_reg (Pmode, operands[1]);
3879 else if (TLS_SYMBOLIC_CONST (operands[1]))
3880 operands[1] = legitimize_tls_address (operands[1], temp);
3881 else if (flag_pic)
3882 operands[1] = legitimize_pic_address (operands[1], temp);
3883 }
3884
3885 /* Try machine-dependent ways of modifying an illegitimate address X
3886 to be legitimate. If we find one, return the new, valid address.
3887
3888 OLDX is the address as it was before break_out_memory_refs was called.
3889 In some cases it is useful to look at this to decide what needs to be done.
3890
3891 MODE is the mode of the operand pointed to by X.
3892
3893 When -fpic is used, special handling is needed for symbolic references.
3894 See comments by legitimize_pic_address for details. */
3895
3896 static rtx
3897 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3898 enum machine_mode mode ATTRIBUTE_UNUSED)
3899 {
3900 rtx constant_term = const0_rtx;
3901
3902 if (TLS_SYMBOLIC_CONST (x))
3903 {
3904 x = legitimize_tls_address (x, 0);
3905
3906 if (s390_legitimate_address_p (mode, x, FALSE))
3907 return x;
3908 }
3909 else if (GET_CODE (x) == PLUS
3910 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3911 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3912 {
3913 return x;
3914 }
3915 else if (flag_pic)
3916 {
3917 if (SYMBOLIC_CONST (x)
3918 || (GET_CODE (x) == PLUS
3919 && (SYMBOLIC_CONST (XEXP (x, 0))
3920 || SYMBOLIC_CONST (XEXP (x, 1)))))
3921 x = legitimize_pic_address (x, 0);
3922
3923 if (s390_legitimate_address_p (mode, x, FALSE))
3924 return x;
3925 }
3926
3927 x = eliminate_constant_term (x, &constant_term);
3928
3929 /* Optimize loading of large displacements by splitting them
3930 into the multiple of 4K and the rest; this allows the
3931 former to be CSE'd if possible.
3932
3933 Don't do this if the displacement is added to a register
3934 pointing into the stack frame, as the offsets will
3935 change later anyway. */
3936
3937 if (GET_CODE (constant_term) == CONST_INT
3938 && !TARGET_LONG_DISPLACEMENT
3939 && !DISP_IN_RANGE (INTVAL (constant_term))
3940 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3941 {
3942 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3943 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3944
3945 rtx temp = gen_reg_rtx (Pmode);
3946 rtx val = force_operand (GEN_INT (upper), temp);
3947 if (val != temp)
3948 emit_move_insn (temp, val);
3949
3950 x = gen_rtx_PLUS (Pmode, x, temp);
3951 constant_term = GEN_INT (lower);
3952 }
3953
3954 if (GET_CODE (x) == PLUS)
3955 {
3956 if (GET_CODE (XEXP (x, 0)) == REG)
3957 {
3958 rtx temp = gen_reg_rtx (Pmode);
3959 rtx val = force_operand (XEXP (x, 1), temp);
3960 if (val != temp)
3961 emit_move_insn (temp, val);
3962
3963 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3964 }
3965
3966 else if (GET_CODE (XEXP (x, 1)) == REG)
3967 {
3968 rtx temp = gen_reg_rtx (Pmode);
3969 rtx val = force_operand (XEXP (x, 0), temp);
3970 if (val != temp)
3971 emit_move_insn (temp, val);
3972
3973 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3974 }
3975 }
3976
3977 if (constant_term != const0_rtx)
3978 x = gen_rtx_PLUS (Pmode, x, constant_term);
3979
3980 return x;
3981 }
3982
3983 /* Try a machine-dependent way of reloading an illegitimate address AD
3984 operand. If we find one, push the reload and return the new address.
3985
3986 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3987 and TYPE is the reload type of the current reload. */
3988
3989 rtx
3990 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3991 int opnum, int type)
3992 {
3993 if (!optimize || TARGET_LONG_DISPLACEMENT)
3994 return NULL_RTX;
3995
3996 if (GET_CODE (ad) == PLUS)
3997 {
3998 rtx tem = simplify_binary_operation (PLUS, Pmode,
3999 XEXP (ad, 0), XEXP (ad, 1));
4000 if (tem)
4001 ad = tem;
4002 }
4003
4004 if (GET_CODE (ad) == PLUS
4005 && GET_CODE (XEXP (ad, 0)) == REG
4006 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4007 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4008 {
4009 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4010 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4011 rtx cst, tem, new_rtx;
4012
4013 cst = GEN_INT (upper);
4014 if (!legitimate_reload_constant_p (cst))
4015 cst = force_const_mem (Pmode, cst);
4016
4017 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4018 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4019
4020 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4021 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4022 opnum, (enum reload_type) type);
4023 return new_rtx;
4024 }
4025
4026 return NULL_RTX;
4027 }
4028
4029 /* Emit code to move LEN bytes from DST to SRC. */
4030
4031 bool
4032 s390_expand_movmem (rtx dst, rtx src, rtx len)
4033 {
4034 /* When tuning for z10 or higher we rely on the Glibc functions to
4035 do the right thing. Only for constant lengths below 64k we will
4036 generate inline code. */
4037 if (s390_tune >= PROCESSOR_2097_Z10
4038 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4039 return false;
4040
4041 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4042 {
4043 if (INTVAL (len) > 0)
4044 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4045 }
4046
4047 else if (TARGET_MVCLE)
4048 {
4049 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4050 }
4051
4052 else
4053 {
4054 rtx dst_addr, src_addr, count, blocks, temp;
4055 rtx loop_start_label = gen_label_rtx ();
4056 rtx loop_end_label = gen_label_rtx ();
4057 rtx end_label = gen_label_rtx ();
4058 enum machine_mode mode;
4059
4060 mode = GET_MODE (len);
4061 if (mode == VOIDmode)
4062 mode = Pmode;
4063
4064 dst_addr = gen_reg_rtx (Pmode);
4065 src_addr = gen_reg_rtx (Pmode);
4066 count = gen_reg_rtx (mode);
4067 blocks = gen_reg_rtx (mode);
4068
4069 convert_move (count, len, 1);
4070 emit_cmp_and_jump_insns (count, const0_rtx,
4071 EQ, NULL_RTX, mode, 1, end_label);
4072
4073 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4074 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4075 dst = change_address (dst, VOIDmode, dst_addr);
4076 src = change_address (src, VOIDmode, src_addr);
4077
4078 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4079 OPTAB_DIRECT);
4080 if (temp != count)
4081 emit_move_insn (count, temp);
4082
4083 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4084 OPTAB_DIRECT);
4085 if (temp != blocks)
4086 emit_move_insn (blocks, temp);
4087
4088 emit_cmp_and_jump_insns (blocks, const0_rtx,
4089 EQ, NULL_RTX, mode, 1, loop_end_label);
4090
4091 emit_label (loop_start_label);
4092
4093 if (TARGET_Z10
4094 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4095 {
4096 rtx prefetch;
4097
4098 /* Issue a read prefetch for the +3 cache line. */
4099 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4100 const0_rtx, const0_rtx);
4101 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4102 emit_insn (prefetch);
4103
4104 /* Issue a write prefetch for the +3 cache line. */
4105 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4106 const1_rtx, const0_rtx);
4107 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4108 emit_insn (prefetch);
4109 }
4110
4111 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4112 s390_load_address (dst_addr,
4113 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4114 s390_load_address (src_addr,
4115 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4116
4117 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4118 OPTAB_DIRECT);
4119 if (temp != blocks)
4120 emit_move_insn (blocks, temp);
4121
4122 emit_cmp_and_jump_insns (blocks, const0_rtx,
4123 EQ, NULL_RTX, mode, 1, loop_end_label);
4124
4125 emit_jump (loop_start_label);
4126 emit_label (loop_end_label);
4127
4128 emit_insn (gen_movmem_short (dst, src,
4129 convert_to_mode (Pmode, count, 1)));
4130 emit_label (end_label);
4131 }
4132 return true;
4133 }
4134
4135 /* Emit code to set LEN bytes at DST to VAL.
4136 Make use of clrmem if VAL is zero. */
4137
4138 void
4139 s390_expand_setmem (rtx dst, rtx len, rtx val)
4140 {
4141 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4142 return;
4143
4144 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4145
4146 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4147 {
4148 if (val == const0_rtx && INTVAL (len) <= 256)
4149 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4150 else
4151 {
4152 /* Initialize memory by storing the first byte. */
4153 emit_move_insn (adjust_address (dst, QImode, 0), val);
4154
4155 if (INTVAL (len) > 1)
4156 {
4157 /* Initiate 1 byte overlap move.
4158 The first byte of DST is propagated through DSTP1.
4159 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4160 DST is set to size 1 so the rest of the memory location
4161 does not count as source operand. */
4162 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4163 set_mem_size (dst, 1);
4164
4165 emit_insn (gen_movmem_short (dstp1, dst,
4166 GEN_INT (INTVAL (len) - 2)));
4167 }
4168 }
4169 }
4170
4171 else if (TARGET_MVCLE)
4172 {
4173 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4174 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4175 }
4176
4177 else
4178 {
4179 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4180 rtx loop_start_label = gen_label_rtx ();
4181 rtx loop_end_label = gen_label_rtx ();
4182 rtx end_label = gen_label_rtx ();
4183 enum machine_mode mode;
4184
4185 mode = GET_MODE (len);
4186 if (mode == VOIDmode)
4187 mode = Pmode;
4188
4189 dst_addr = gen_reg_rtx (Pmode);
4190 count = gen_reg_rtx (mode);
4191 blocks = gen_reg_rtx (mode);
4192
4193 convert_move (count, len, 1);
4194 emit_cmp_and_jump_insns (count, const0_rtx,
4195 EQ, NULL_RTX, mode, 1, end_label);
4196
4197 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4198 dst = change_address (dst, VOIDmode, dst_addr);
4199
4200 if (val == const0_rtx)
4201 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4202 OPTAB_DIRECT);
4203 else
4204 {
4205 dstp1 = adjust_address (dst, VOIDmode, 1);
4206 set_mem_size (dst, 1);
4207
4208 /* Initialize memory by storing the first byte. */
4209 emit_move_insn (adjust_address (dst, QImode, 0), val);
4210
4211 /* If count is 1 we are done. */
4212 emit_cmp_and_jump_insns (count, const1_rtx,
4213 EQ, NULL_RTX, mode, 1, end_label);
4214
4215 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4216 OPTAB_DIRECT);
4217 }
4218 if (temp != count)
4219 emit_move_insn (count, temp);
4220
4221 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4222 OPTAB_DIRECT);
4223 if (temp != blocks)
4224 emit_move_insn (blocks, temp);
4225
4226 emit_cmp_and_jump_insns (blocks, const0_rtx,
4227 EQ, NULL_RTX, mode, 1, loop_end_label);
4228
4229 emit_label (loop_start_label);
4230
4231 if (TARGET_Z10
4232 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4233 {
4234 /* Issue a write prefetch for the +4 cache line. */
4235 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4236 GEN_INT (1024)),
4237 const1_rtx, const0_rtx);
4238 emit_insn (prefetch);
4239 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4240 }
4241
4242 if (val == const0_rtx)
4243 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4244 else
4245 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4246 s390_load_address (dst_addr,
4247 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4248
4249 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4250 OPTAB_DIRECT);
4251 if (temp != blocks)
4252 emit_move_insn (blocks, temp);
4253
4254 emit_cmp_and_jump_insns (blocks, const0_rtx,
4255 EQ, NULL_RTX, mode, 1, loop_end_label);
4256
4257 emit_jump (loop_start_label);
4258 emit_label (loop_end_label);
4259
4260 if (val == const0_rtx)
4261 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4262 else
4263 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4264 emit_label (end_label);
4265 }
4266 }
4267
4268 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4269 and return the result in TARGET. */
4270
4271 bool
4272 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4273 {
4274 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4275 rtx tmp;
4276
4277 /* When tuning for z10 or higher we rely on the Glibc functions to
4278 do the right thing. Only for constant lengths below 64k we will
4279 generate inline code. */
4280 if (s390_tune >= PROCESSOR_2097_Z10
4281 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4282 return false;
4283
4284 /* As the result of CMPINT is inverted compared to what we need,
4285 we have to swap the operands. */
4286 tmp = op0; op0 = op1; op1 = tmp;
4287
4288 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4289 {
4290 if (INTVAL (len) > 0)
4291 {
4292 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4293 emit_insn (gen_cmpint (target, ccreg));
4294 }
4295 else
4296 emit_move_insn (target, const0_rtx);
4297 }
4298 else if (TARGET_MVCLE)
4299 {
4300 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4301 emit_insn (gen_cmpint (target, ccreg));
4302 }
4303 else
4304 {
4305 rtx addr0, addr1, count, blocks, temp;
4306 rtx loop_start_label = gen_label_rtx ();
4307 rtx loop_end_label = gen_label_rtx ();
4308 rtx end_label = gen_label_rtx ();
4309 enum machine_mode mode;
4310
4311 mode = GET_MODE (len);
4312 if (mode == VOIDmode)
4313 mode = Pmode;
4314
4315 addr0 = gen_reg_rtx (Pmode);
4316 addr1 = gen_reg_rtx (Pmode);
4317 count = gen_reg_rtx (mode);
4318 blocks = gen_reg_rtx (mode);
4319
4320 convert_move (count, len, 1);
4321 emit_cmp_and_jump_insns (count, const0_rtx,
4322 EQ, NULL_RTX, mode, 1, end_label);
4323
4324 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4325 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4326 op0 = change_address (op0, VOIDmode, addr0);
4327 op1 = change_address (op1, VOIDmode, addr1);
4328
4329 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4330 OPTAB_DIRECT);
4331 if (temp != count)
4332 emit_move_insn (count, temp);
4333
4334 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4335 OPTAB_DIRECT);
4336 if (temp != blocks)
4337 emit_move_insn (blocks, temp);
4338
4339 emit_cmp_and_jump_insns (blocks, const0_rtx,
4340 EQ, NULL_RTX, mode, 1, loop_end_label);
4341
4342 emit_label (loop_start_label);
4343
4344 if (TARGET_Z10
4345 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4346 {
4347 rtx prefetch;
4348
4349 /* Issue a read prefetch for the +2 cache line of operand 1. */
4350 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4351 const0_rtx, const0_rtx);
4352 emit_insn (prefetch);
4353 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4354
4355 /* Issue a read prefetch for the +2 cache line of operand 2. */
4356 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4357 const0_rtx, const0_rtx);
4358 emit_insn (prefetch);
4359 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4360 }
4361
4362 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4363 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4364 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4365 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4366 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4367 emit_jump_insn (temp);
4368
4369 s390_load_address (addr0,
4370 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4371 s390_load_address (addr1,
4372 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4373
4374 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4375 OPTAB_DIRECT);
4376 if (temp != blocks)
4377 emit_move_insn (blocks, temp);
4378
4379 emit_cmp_and_jump_insns (blocks, const0_rtx,
4380 EQ, NULL_RTX, mode, 1, loop_end_label);
4381
4382 emit_jump (loop_start_label);
4383 emit_label (loop_end_label);
4384
4385 emit_insn (gen_cmpmem_short (op0, op1,
4386 convert_to_mode (Pmode, count, 1)));
4387 emit_label (end_label);
4388
4389 emit_insn (gen_cmpint (target, ccreg));
4390 }
4391 return true;
4392 }
4393
4394
4395 /* Expand conditional increment or decrement using alc/slb instructions.
4396 Should generate code setting DST to either SRC or SRC + INCREMENT,
4397 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4398 Returns true if successful, false otherwise.
4399
4400 That makes it possible to implement some if-constructs without jumps e.g.:
4401 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4402 unsigned int a, b, c;
4403 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4404 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4405 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4406 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4407
4408 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4409 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4410 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4411 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4412 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4413
4414 bool
4415 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4416 rtx dst, rtx src, rtx increment)
4417 {
4418 enum machine_mode cmp_mode;
4419 enum machine_mode cc_mode;
4420 rtx op_res;
4421 rtx insn;
4422 rtvec p;
4423 int ret;
4424
4425 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4426 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4427 cmp_mode = SImode;
4428 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4429 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4430 cmp_mode = DImode;
4431 else
4432 return false;
4433
4434 /* Try ADD LOGICAL WITH CARRY. */
4435 if (increment == const1_rtx)
4436 {
4437 /* Determine CC mode to use. */
4438 if (cmp_code == EQ || cmp_code == NE)
4439 {
4440 if (cmp_op1 != const0_rtx)
4441 {
4442 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4443 NULL_RTX, 0, OPTAB_WIDEN);
4444 cmp_op1 = const0_rtx;
4445 }
4446
4447 cmp_code = cmp_code == EQ ? LEU : GTU;
4448 }
4449
4450 if (cmp_code == LTU || cmp_code == LEU)
4451 {
4452 rtx tem = cmp_op0;
4453 cmp_op0 = cmp_op1;
4454 cmp_op1 = tem;
4455 cmp_code = swap_condition (cmp_code);
4456 }
4457
4458 switch (cmp_code)
4459 {
4460 case GTU:
4461 cc_mode = CCUmode;
4462 break;
4463
4464 case GEU:
4465 cc_mode = CCL3mode;
4466 break;
4467
4468 default:
4469 return false;
4470 }
4471
4472 /* Emit comparison instruction pattern. */
4473 if (!register_operand (cmp_op0, cmp_mode))
4474 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4475
4476 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4477 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4478 /* We use insn_invalid_p here to add clobbers if required. */
4479 ret = insn_invalid_p (emit_insn (insn), false);
4480 gcc_assert (!ret);
4481
4482 /* Emit ALC instruction pattern. */
4483 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4484 gen_rtx_REG (cc_mode, CC_REGNUM),
4485 const0_rtx);
4486
4487 if (src != const0_rtx)
4488 {
4489 if (!register_operand (src, GET_MODE (dst)))
4490 src = force_reg (GET_MODE (dst), src);
4491
4492 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4493 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4494 }
4495
4496 p = rtvec_alloc (2);
4497 RTVEC_ELT (p, 0) =
4498 gen_rtx_SET (VOIDmode, dst, op_res);
4499 RTVEC_ELT (p, 1) =
4500 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4501 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4502
4503 return true;
4504 }
4505
4506 /* Try SUBTRACT LOGICAL WITH BORROW. */
4507 if (increment == constm1_rtx)
4508 {
4509 /* Determine CC mode to use. */
4510 if (cmp_code == EQ || cmp_code == NE)
4511 {
4512 if (cmp_op1 != const0_rtx)
4513 {
4514 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4515 NULL_RTX, 0, OPTAB_WIDEN);
4516 cmp_op1 = const0_rtx;
4517 }
4518
4519 cmp_code = cmp_code == EQ ? LEU : GTU;
4520 }
4521
4522 if (cmp_code == GTU || cmp_code == GEU)
4523 {
4524 rtx tem = cmp_op0;
4525 cmp_op0 = cmp_op1;
4526 cmp_op1 = tem;
4527 cmp_code = swap_condition (cmp_code);
4528 }
4529
4530 switch (cmp_code)
4531 {
4532 case LEU:
4533 cc_mode = CCUmode;
4534 break;
4535
4536 case LTU:
4537 cc_mode = CCL3mode;
4538 break;
4539
4540 default:
4541 return false;
4542 }
4543
4544 /* Emit comparison instruction pattern. */
4545 if (!register_operand (cmp_op0, cmp_mode))
4546 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4547
4548 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4549 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4550 /* We use insn_invalid_p here to add clobbers if required. */
4551 ret = insn_invalid_p (emit_insn (insn), false);
4552 gcc_assert (!ret);
4553
4554 /* Emit SLB instruction pattern. */
4555 if (!register_operand (src, GET_MODE (dst)))
4556 src = force_reg (GET_MODE (dst), src);
4557
4558 op_res = gen_rtx_MINUS (GET_MODE (dst),
4559 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4560 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4561 gen_rtx_REG (cc_mode, CC_REGNUM),
4562 const0_rtx));
4563 p = rtvec_alloc (2);
4564 RTVEC_ELT (p, 0) =
4565 gen_rtx_SET (VOIDmode, dst, op_res);
4566 RTVEC_ELT (p, 1) =
4567 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4568 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4569
4570 return true;
4571 }
4572
4573 return false;
4574 }
4575
4576 /* Expand code for the insv template. Return true if successful. */
4577
4578 bool
4579 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4580 {
4581 int bitsize = INTVAL (op1);
4582 int bitpos = INTVAL (op2);
4583 enum machine_mode mode = GET_MODE (dest);
4584 enum machine_mode smode;
4585 int smode_bsize, mode_bsize;
4586 rtx op, clobber;
4587
4588 /* Generate INSERT IMMEDIATE (IILL et al). */
4589 /* (set (ze (reg)) (const_int)). */
4590 if (TARGET_ZARCH
4591 && register_operand (dest, word_mode)
4592 && (bitpos % 16) == 0
4593 && (bitsize % 16) == 0
4594 && const_int_operand (src, VOIDmode))
4595 {
4596 HOST_WIDE_INT val = INTVAL (src);
4597 int regpos = bitpos + bitsize;
4598
4599 while (regpos > bitpos)
4600 {
4601 enum machine_mode putmode;
4602 int putsize;
4603
4604 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4605 putmode = SImode;
4606 else
4607 putmode = HImode;
4608
4609 putsize = GET_MODE_BITSIZE (putmode);
4610 regpos -= putsize;
4611 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4612 GEN_INT (putsize),
4613 GEN_INT (regpos)),
4614 gen_int_mode (val, putmode));
4615 val >>= putsize;
4616 }
4617 gcc_assert (regpos == bitpos);
4618 return true;
4619 }
4620
4621 smode = smallest_mode_for_size (bitsize, MODE_INT);
4622 smode_bsize = GET_MODE_BITSIZE (smode);
4623 mode_bsize = GET_MODE_BITSIZE (mode);
4624
4625 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4626 if (bitpos == 0
4627 && (bitsize % BITS_PER_UNIT) == 0
4628 && MEM_P (dest)
4629 && (register_operand (src, word_mode)
4630 || const_int_operand (src, VOIDmode)))
4631 {
4632 /* Emit standard pattern if possible. */
4633 if (smode_bsize == bitsize)
4634 {
4635 emit_move_insn (adjust_address (dest, smode, 0),
4636 gen_lowpart (smode, src));
4637 return true;
4638 }
4639
4640 /* (set (ze (mem)) (const_int)). */
4641 else if (const_int_operand (src, VOIDmode))
4642 {
4643 int size = bitsize / BITS_PER_UNIT;
4644 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4645 BLKmode,
4646 UNITS_PER_WORD - size);
4647
4648 dest = adjust_address (dest, BLKmode, 0);
4649 set_mem_size (dest, size);
4650 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4651 return true;
4652 }
4653
4654 /* (set (ze (mem)) (reg)). */
4655 else if (register_operand (src, word_mode))
4656 {
4657 if (bitsize <= 32)
4658 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4659 const0_rtx), src);
4660 else
4661 {
4662 /* Emit st,stcmh sequence. */
4663 int stcmh_width = bitsize - 32;
4664 int size = stcmh_width / BITS_PER_UNIT;
4665
4666 emit_move_insn (adjust_address (dest, SImode, size),
4667 gen_lowpart (SImode, src));
4668 set_mem_size (dest, size);
4669 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4670 GEN_INT (stcmh_width),
4671 const0_rtx),
4672 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
4673 }
4674 return true;
4675 }
4676 }
4677
4678 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4679 if ((bitpos % BITS_PER_UNIT) == 0
4680 && (bitsize % BITS_PER_UNIT) == 0
4681 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4682 && MEM_P (src)
4683 && (mode == DImode || mode == SImode)
4684 && register_operand (dest, mode))
4685 {
4686 /* Emit a strict_low_part pattern if possible. */
4687 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4688 {
4689 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4690 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4691 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4692 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4693 return true;
4694 }
4695
4696 /* ??? There are more powerful versions of ICM that are not
4697 completely represented in the md file. */
4698 }
4699
4700 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4701 if (TARGET_Z10 && (mode == DImode || mode == SImode))
4702 {
4703 enum machine_mode mode_s = GET_MODE (src);
4704
4705 if (mode_s == VOIDmode)
4706 {
4707 /* Assume const_int etc already in the proper mode. */
4708 src = force_reg (mode, src);
4709 }
4710 else if (mode_s != mode)
4711 {
4712 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4713 src = force_reg (mode_s, src);
4714 src = gen_lowpart (mode, src);
4715 }
4716
4717 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4718 op = gen_rtx_SET (VOIDmode, op, src);
4719 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4720 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4721
4722 return true;
4723 }
4724
4725 return false;
4726 }
4727
4728 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4729 register that holds VAL of mode MODE shifted by COUNT bits. */
4730
4731 static inline rtx
4732 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4733 {
4734 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4735 NULL_RTX, 1, OPTAB_DIRECT);
4736 return expand_simple_binop (SImode, ASHIFT, val, count,
4737 NULL_RTX, 1, OPTAB_DIRECT);
4738 }
4739
4740 /* Structure to hold the initial parameters for a compare_and_swap operation
4741 in HImode and QImode. */
4742
4743 struct alignment_context
4744 {
4745 rtx memsi; /* SI aligned memory location. */
4746 rtx shift; /* Bit offset with regard to lsb. */
4747 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4748 rtx modemaski; /* ~modemask */
4749 bool aligned; /* True if memory is aligned, false else. */
4750 };
4751
4752 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4753 structure AC for transparent simplifying, if the memory alignment is known
4754 to be at least 32bit. MEM is the memory location for the actual operation
4755 and MODE its mode. */
4756
4757 static void
4758 init_alignment_context (struct alignment_context *ac, rtx mem,
4759 enum machine_mode mode)
4760 {
4761 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4762 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4763
4764 if (ac->aligned)
4765 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4766 else
4767 {
4768 /* Alignment is unknown. */
4769 rtx byteoffset, addr, align;
4770
4771 /* Force the address into a register. */
4772 addr = force_reg (Pmode, XEXP (mem, 0));
4773
4774 /* Align it to SImode. */
4775 align = expand_simple_binop (Pmode, AND, addr,
4776 GEN_INT (-GET_MODE_SIZE (SImode)),
4777 NULL_RTX, 1, OPTAB_DIRECT);
4778 /* Generate MEM. */
4779 ac->memsi = gen_rtx_MEM (SImode, align);
4780 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4781 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4782 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4783
4784 /* Calculate shiftcount. */
4785 byteoffset = expand_simple_binop (Pmode, AND, addr,
4786 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4787 NULL_RTX, 1, OPTAB_DIRECT);
4788 /* As we already have some offset, evaluate the remaining distance. */
4789 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4790 NULL_RTX, 1, OPTAB_DIRECT);
4791 }
4792
4793 /* Shift is the byte count, but we need the bitcount. */
4794 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4795 NULL_RTX, 1, OPTAB_DIRECT);
4796
4797 /* Calculate masks. */
4798 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4799 GEN_INT (GET_MODE_MASK (mode)),
4800 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4801 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4802 NULL_RTX, 1);
4803 }
4804
4805 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4806 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4807 perform the merge in SEQ2. */
4808
4809 static rtx
4810 s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4811 enum machine_mode mode, rtx val, rtx ins)
4812 {
4813 rtx tmp;
4814
4815 if (ac->aligned)
4816 {
4817 start_sequence ();
4818 tmp = copy_to_mode_reg (SImode, val);
4819 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4820 const0_rtx, ins))
4821 {
4822 *seq1 = NULL;
4823 *seq2 = get_insns ();
4824 end_sequence ();
4825 return tmp;
4826 }
4827 end_sequence ();
4828 }
4829
4830 /* Failed to use insv. Generate a two part shift and mask. */
4831 start_sequence ();
4832 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4833 *seq1 = get_insns ();
4834 end_sequence ();
4835
4836 start_sequence ();
4837 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4838 *seq2 = get_insns ();
4839 end_sequence ();
4840
4841 return tmp;
4842 }
4843
4844 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4845 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4846 value to set if CMP == MEM. */
4847
4848 void
4849 s390_expand_cs_hqi (enum machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4850 rtx cmp, rtx new_rtx, bool is_weak)
4851 {
4852 struct alignment_context ac;
4853 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
4854 rtx res = gen_reg_rtx (SImode);
4855 rtx csloop = NULL, csend = NULL;
4856
4857 gcc_assert (MEM_P (mem));
4858
4859 init_alignment_context (&ac, mem, mode);
4860
4861 /* Load full word. Subsequent loads are performed by CS. */
4862 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4863 NULL_RTX, 1, OPTAB_DIRECT);
4864
4865 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4866 possible, we try to use insv to make this happen efficiently. If
4867 that fails we'll generate code both inside and outside the loop. */
4868 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4869 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4870
4871 if (seq0)
4872 emit_insn (seq0);
4873 if (seq1)
4874 emit_insn (seq1);
4875
4876 /* Start CS loop. */
4877 if (!is_weak)
4878 {
4879 /* Begin assuming success. */
4880 emit_move_insn (btarget, const1_rtx);
4881
4882 csloop = gen_label_rtx ();
4883 csend = gen_label_rtx ();
4884 emit_label (csloop);
4885 }
4886
4887 /* val = "<mem>00..0<mem>"
4888 * cmp = "00..0<cmp>00..0"
4889 * new = "00..0<new>00..0"
4890 */
4891
4892 emit_insn (seq2);
4893 emit_insn (seq3);
4894
4895 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4896 if (is_weak)
4897 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
4898 else
4899 {
4900 rtx tmp;
4901
4902 /* Jump to end if we're done (likely?). */
4903 s390_emit_jump (csend, cc);
4904
4905 /* Check for changes outside mode, and loop internal if so.
4906 Arrange the moves so that the compare is adjacent to the
4907 branch so that we can generate CRJ. */
4908 tmp = copy_to_reg (val);
4909 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4910 1, OPTAB_DIRECT);
4911 cc = s390_emit_compare (NE, val, tmp);
4912 s390_emit_jump (csloop, cc);
4913
4914 /* Failed. */
4915 emit_move_insn (btarget, const0_rtx);
4916 emit_label (csend);
4917 }
4918
4919 /* Return the correct part of the bitfield. */
4920 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4921 NULL_RTX, 1, OPTAB_DIRECT), 1);
4922 }
4923
4924 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4925 and VAL the value to play with. If AFTER is true then store the value
4926 MEM holds after the operation, if AFTER is false then store the value MEM
4927 holds before the operation. If TARGET is zero then discard that value, else
4928 store it to TARGET. */
4929
4930 void
4931 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4932 rtx target, rtx mem, rtx val, bool after)
4933 {
4934 struct alignment_context ac;
4935 rtx cmp;
4936 rtx new_rtx = gen_reg_rtx (SImode);
4937 rtx orig = gen_reg_rtx (SImode);
4938 rtx csloop = gen_label_rtx ();
4939
4940 gcc_assert (!target || register_operand (target, VOIDmode));
4941 gcc_assert (MEM_P (mem));
4942
4943 init_alignment_context (&ac, mem, mode);
4944
4945 /* Shift val to the correct bit positions.
4946 Preserve "icm", but prevent "ex icm". */
4947 if (!(ac.aligned && code == SET && MEM_P (val)))
4948 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4949
4950 /* Further preparation insns. */
4951 if (code == PLUS || code == MINUS)
4952 emit_move_insn (orig, val);
4953 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4954 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4955 NULL_RTX, 1, OPTAB_DIRECT);
4956
4957 /* Load full word. Subsequent loads are performed by CS. */
4958 cmp = force_reg (SImode, ac.memsi);
4959
4960 /* Start CS loop. */
4961 emit_label (csloop);
4962 emit_move_insn (new_rtx, cmp);
4963
4964 /* Patch new with val at correct position. */
4965 switch (code)
4966 {
4967 case PLUS:
4968 case MINUS:
4969 val = expand_simple_binop (SImode, code, new_rtx, orig,
4970 NULL_RTX, 1, OPTAB_DIRECT);
4971 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4972 NULL_RTX, 1, OPTAB_DIRECT);
4973 /* FALLTHRU */
4974 case SET:
4975 if (ac.aligned && MEM_P (val))
4976 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
4977 0, 0, SImode, val);
4978 else
4979 {
4980 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4981 NULL_RTX, 1, OPTAB_DIRECT);
4982 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4983 NULL_RTX, 1, OPTAB_DIRECT);
4984 }
4985 break;
4986 case AND:
4987 case IOR:
4988 case XOR:
4989 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4990 NULL_RTX, 1, OPTAB_DIRECT);
4991 break;
4992 case MULT: /* NAND */
4993 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4994 NULL_RTX, 1, OPTAB_DIRECT);
4995 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4996 NULL_RTX, 1, OPTAB_DIRECT);
4997 break;
4998 default:
4999 gcc_unreachable ();
5000 }
5001
5002 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
5003 ac.memsi, cmp, new_rtx));
5004
5005 /* Return the correct part of the bitfield. */
5006 if (target)
5007 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
5008 after ? new_rtx : cmp, ac.shift,
5009 NULL_RTX, 1, OPTAB_DIRECT), 1);
5010 }
5011
5012 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5013 We need to emit DTP-relative relocations. */
5014
5015 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5016
5017 static void
5018 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
5019 {
5020 switch (size)
5021 {
5022 case 4:
5023 fputs ("\t.long\t", file);
5024 break;
5025 case 8:
5026 fputs ("\t.quad\t", file);
5027 break;
5028 default:
5029 gcc_unreachable ();
5030 }
5031 output_addr_const (file, x);
5032 fputs ("@DTPOFF", file);
5033 }
5034
5035 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5036 /* Implement TARGET_MANGLE_TYPE. */
5037
5038 static const char *
5039 s390_mangle_type (const_tree type)
5040 {
5041 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5042 && TARGET_LONG_DOUBLE_128)
5043 return "g";
5044
5045 /* For all other types, use normal C++ mangling. */
5046 return NULL;
5047 }
5048 #endif
5049
5050 /* In the name of slightly smaller debug output, and to cater to
5051 general assembler lossage, recognize various UNSPEC sequences
5052 and turn them back into a direct symbol reference. */
5053
5054 static rtx
5055 s390_delegitimize_address (rtx orig_x)
5056 {
5057 rtx x, y;
5058
5059 orig_x = delegitimize_mem_from_attrs (orig_x);
5060 x = orig_x;
5061
5062 /* Extract the symbol ref from:
5063 (plus:SI (reg:SI 12 %r12)
5064 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5065 UNSPEC_GOTOFF/PLTOFF)))
5066 and
5067 (plus:SI (reg:SI 12 %r12)
5068 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5069 UNSPEC_GOTOFF/PLTOFF)
5070 (const_int 4 [0x4])))) */
5071 if (GET_CODE (x) == PLUS
5072 && REG_P (XEXP (x, 0))
5073 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5074 && GET_CODE (XEXP (x, 1)) == CONST)
5075 {
5076 HOST_WIDE_INT offset = 0;
5077
5078 /* The const operand. */
5079 y = XEXP (XEXP (x, 1), 0);
5080
5081 if (GET_CODE (y) == PLUS
5082 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5083 {
5084 offset = INTVAL (XEXP (y, 1));
5085 y = XEXP (y, 0);
5086 }
5087
5088 if (GET_CODE (y) == UNSPEC
5089 && (XINT (y, 1) == UNSPEC_GOTOFF
5090 || XINT (y, 1) == UNSPEC_PLTOFF))
5091 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
5092 }
5093
5094 if (GET_CODE (x) != MEM)
5095 return orig_x;
5096
5097 x = XEXP (x, 0);
5098 if (GET_CODE (x) == PLUS
5099 && GET_CODE (XEXP (x, 1)) == CONST
5100 && GET_CODE (XEXP (x, 0)) == REG
5101 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5102 {
5103 y = XEXP (XEXP (x, 1), 0);
5104 if (GET_CODE (y) == UNSPEC
5105 && XINT (y, 1) == UNSPEC_GOT)
5106 y = XVECEXP (y, 0, 0);
5107 else
5108 return orig_x;
5109 }
5110 else if (GET_CODE (x) == CONST)
5111 {
5112 /* Extract the symbol ref from:
5113 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5114 UNSPEC_PLT/GOTENT))) */
5115
5116 y = XEXP (x, 0);
5117 if (GET_CODE (y) == UNSPEC
5118 && (XINT (y, 1) == UNSPEC_GOTENT
5119 || XINT (y, 1) == UNSPEC_PLT))
5120 y = XVECEXP (y, 0, 0);
5121 else
5122 return orig_x;
5123 }
5124 else
5125 return orig_x;
5126
5127 if (GET_MODE (orig_x) != Pmode)
5128 {
5129 if (GET_MODE (orig_x) == BLKmode)
5130 return orig_x;
5131 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5132 if (y == NULL_RTX)
5133 return orig_x;
5134 }
5135 return y;
5136 }
5137
5138 /* Output operand OP to stdio stream FILE.
5139 OP is an address (register + offset) which is not used to address data;
5140 instead the rightmost bits are interpreted as the value. */
5141
5142 static void
5143 print_shift_count_operand (FILE *file, rtx op)
5144 {
5145 HOST_WIDE_INT offset;
5146 rtx base;
5147
5148 /* Extract base register and offset. */
5149 if (!s390_decompose_shift_count (op, &base, &offset))
5150 gcc_unreachable ();
5151
5152 /* Sanity check. */
5153 if (base)
5154 {
5155 gcc_assert (GET_CODE (base) == REG);
5156 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5157 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5158 }
5159
5160 /* Offsets are constricted to twelve bits. */
5161 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5162 if (base)
5163 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5164 }
5165
5166 /* See 'get_some_local_dynamic_name'. */
5167
5168 static int
5169 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5170 {
5171 rtx x = *px;
5172
5173 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5174 {
5175 x = get_pool_constant (x);
5176 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5177 }
5178
5179 if (GET_CODE (x) == SYMBOL_REF
5180 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5181 {
5182 cfun->machine->some_ld_name = XSTR (x, 0);
5183 return 1;
5184 }
5185
5186 return 0;
5187 }
5188
5189 /* Locate some local-dynamic symbol still in use by this function
5190 so that we can print its name in local-dynamic base patterns. */
5191
5192 static const char *
5193 get_some_local_dynamic_name (void)
5194 {
5195 rtx insn;
5196
5197 if (cfun->machine->some_ld_name)
5198 return cfun->machine->some_ld_name;
5199
5200 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5201 if (INSN_P (insn)
5202 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5203 return cfun->machine->some_ld_name;
5204
5205 gcc_unreachable ();
5206 }
5207
5208 /* Output machine-dependent UNSPECs occurring in address constant X
5209 in assembler syntax to stdio stream FILE. Returns true if the
5210 constant X could be recognized, false otherwise. */
5211
5212 static bool
5213 s390_output_addr_const_extra (FILE *file, rtx x)
5214 {
5215 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5216 switch (XINT (x, 1))
5217 {
5218 case UNSPEC_GOTENT:
5219 output_addr_const (file, XVECEXP (x, 0, 0));
5220 fprintf (file, "@GOTENT");
5221 return true;
5222 case UNSPEC_GOT:
5223 output_addr_const (file, XVECEXP (x, 0, 0));
5224 fprintf (file, "@GOT");
5225 return true;
5226 case UNSPEC_GOTOFF:
5227 output_addr_const (file, XVECEXP (x, 0, 0));
5228 fprintf (file, "@GOTOFF");
5229 return true;
5230 case UNSPEC_PLT:
5231 output_addr_const (file, XVECEXP (x, 0, 0));
5232 fprintf (file, "@PLT");
5233 return true;
5234 case UNSPEC_PLTOFF:
5235 output_addr_const (file, XVECEXP (x, 0, 0));
5236 fprintf (file, "@PLTOFF");
5237 return true;
5238 case UNSPEC_TLSGD:
5239 output_addr_const (file, XVECEXP (x, 0, 0));
5240 fprintf (file, "@TLSGD");
5241 return true;
5242 case UNSPEC_TLSLDM:
5243 assemble_name (file, get_some_local_dynamic_name ());
5244 fprintf (file, "@TLSLDM");
5245 return true;
5246 case UNSPEC_DTPOFF:
5247 output_addr_const (file, XVECEXP (x, 0, 0));
5248 fprintf (file, "@DTPOFF");
5249 return true;
5250 case UNSPEC_NTPOFF:
5251 output_addr_const (file, XVECEXP (x, 0, 0));
5252 fprintf (file, "@NTPOFF");
5253 return true;
5254 case UNSPEC_GOTNTPOFF:
5255 output_addr_const (file, XVECEXP (x, 0, 0));
5256 fprintf (file, "@GOTNTPOFF");
5257 return true;
5258 case UNSPEC_INDNTPOFF:
5259 output_addr_const (file, XVECEXP (x, 0, 0));
5260 fprintf (file, "@INDNTPOFF");
5261 return true;
5262 }
5263
5264 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5265 switch (XINT (x, 1))
5266 {
5267 case UNSPEC_POOL_OFFSET:
5268 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5269 output_addr_const (file, x);
5270 return true;
5271 }
5272 return false;
5273 }
5274
5275 /* Output address operand ADDR in assembler syntax to
5276 stdio stream FILE. */
5277
5278 void
5279 print_operand_address (FILE *file, rtx addr)
5280 {
5281 struct s390_address ad;
5282
5283 if (s390_loadrelative_operand_p (addr))
5284 {
5285 if (!TARGET_Z10)
5286 {
5287 output_operand_lossage ("symbolic memory references are "
5288 "only supported on z10 or later");
5289 return;
5290 }
5291 output_addr_const (file, addr);
5292 return;
5293 }
5294
5295 if (!s390_decompose_address (addr, &ad)
5296 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5297 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5298 output_operand_lossage ("cannot decompose address");
5299
5300 if (ad.disp)
5301 output_addr_const (file, ad.disp);
5302 else
5303 fprintf (file, "0");
5304
5305 if (ad.base && ad.indx)
5306 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5307 reg_names[REGNO (ad.base)]);
5308 else if (ad.base)
5309 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5310 }
5311
5312 /* Output operand X in assembler syntax to stdio stream FILE.
5313 CODE specified the format flag. The following format flags
5314 are recognized:
5315
5316 'C': print opcode suffix for branch condition.
5317 'D': print opcode suffix for inverse branch condition.
5318 'E': print opcode suffix for branch on index instruction.
5319 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5320 'G': print the size of the operand in bytes.
5321 'O': print only the displacement of a memory reference.
5322 'R': print only the base register of a memory reference.
5323 'S': print S-type memory reference (base+displacement).
5324 'N': print the second word of a DImode operand.
5325 'M': print the second word of a TImode operand.
5326 'Y': print shift count operand.
5327
5328 'b': print integer X as if it's an unsigned byte.
5329 'c': print integer X as if it's an signed byte.
5330 'x': print integer X as if it's an unsigned halfword.
5331 'h': print integer X as if it's a signed halfword.
5332 'i': print the first nonzero HImode part of X.
5333 'j': print the first HImode part unequal to -1 of X.
5334 'k': print the first nonzero SImode part of X.
5335 'm': print the first SImode part unequal to -1 of X.
5336 'o': print integer X as if it's an unsigned 32bit word. */
5337
5338 void
5339 print_operand (FILE *file, rtx x, int code)
5340 {
5341 switch (code)
5342 {
5343 case 'C':
5344 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5345 return;
5346
5347 case 'D':
5348 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5349 return;
5350
5351 case 'E':
5352 if (GET_CODE (x) == LE)
5353 fprintf (file, "l");
5354 else if (GET_CODE (x) == GT)
5355 fprintf (file, "h");
5356 else
5357 output_operand_lossage ("invalid comparison operator "
5358 "for 'E' output modifier");
5359 return;
5360
5361 case 'J':
5362 if (GET_CODE (x) == SYMBOL_REF)
5363 {
5364 fprintf (file, "%s", ":tls_load:");
5365 output_addr_const (file, x);
5366 }
5367 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5368 {
5369 fprintf (file, "%s", ":tls_gdcall:");
5370 output_addr_const (file, XVECEXP (x, 0, 0));
5371 }
5372 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5373 {
5374 fprintf (file, "%s", ":tls_ldcall:");
5375 assemble_name (file, get_some_local_dynamic_name ());
5376 }
5377 else
5378 output_operand_lossage ("invalid reference for 'J' output modifier");
5379 return;
5380
5381 case 'G':
5382 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5383 return;
5384
5385 case 'O':
5386 {
5387 struct s390_address ad;
5388 int ret;
5389
5390 if (!MEM_P (x))
5391 {
5392 output_operand_lossage ("memory reference expected for "
5393 "'O' output modifier");
5394 return;
5395 }
5396
5397 ret = s390_decompose_address (XEXP (x, 0), &ad);
5398
5399 if (!ret
5400 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5401 || ad.indx)
5402 {
5403 output_operand_lossage ("invalid address for 'O' output modifier");
5404 return;
5405 }
5406
5407 if (ad.disp)
5408 output_addr_const (file, ad.disp);
5409 else
5410 fprintf (file, "0");
5411 }
5412 return;
5413
5414 case 'R':
5415 {
5416 struct s390_address ad;
5417 int ret;
5418
5419 if (!MEM_P (x))
5420 {
5421 output_operand_lossage ("memory reference expected for "
5422 "'R' output modifier");
5423 return;
5424 }
5425
5426 ret = s390_decompose_address (XEXP (x, 0), &ad);
5427
5428 if (!ret
5429 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5430 || ad.indx)
5431 {
5432 output_operand_lossage ("invalid address for 'R' output modifier");
5433 return;
5434 }
5435
5436 if (ad.base)
5437 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5438 else
5439 fprintf (file, "0");
5440 }
5441 return;
5442
5443 case 'S':
5444 {
5445 struct s390_address ad;
5446 int ret;
5447
5448 if (!MEM_P (x))
5449 {
5450 output_operand_lossage ("memory reference expected for "
5451 "'S' output modifier");
5452 return;
5453 }
5454 ret = s390_decompose_address (XEXP (x, 0), &ad);
5455
5456 if (!ret
5457 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5458 || ad.indx)
5459 {
5460 output_operand_lossage ("invalid address for 'S' output modifier");
5461 return;
5462 }
5463
5464 if (ad.disp)
5465 output_addr_const (file, ad.disp);
5466 else
5467 fprintf (file, "0");
5468
5469 if (ad.base)
5470 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5471 }
5472 return;
5473
5474 case 'N':
5475 if (GET_CODE (x) == REG)
5476 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5477 else if (GET_CODE (x) == MEM)
5478 x = change_address (x, VOIDmode,
5479 plus_constant (Pmode, XEXP (x, 0), 4));
5480 else
5481 output_operand_lossage ("register or memory expression expected "
5482 "for 'N' output modifier");
5483 break;
5484
5485 case 'M':
5486 if (GET_CODE (x) == REG)
5487 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5488 else if (GET_CODE (x) == MEM)
5489 x = change_address (x, VOIDmode,
5490 plus_constant (Pmode, XEXP (x, 0), 8));
5491 else
5492 output_operand_lossage ("register or memory expression expected "
5493 "for 'M' output modifier");
5494 break;
5495
5496 case 'Y':
5497 print_shift_count_operand (file, x);
5498 return;
5499 }
5500
5501 switch (GET_CODE (x))
5502 {
5503 case REG:
5504 fprintf (file, "%s", reg_names[REGNO (x)]);
5505 break;
5506
5507 case MEM:
5508 output_address (XEXP (x, 0));
5509 break;
5510
5511 case CONST:
5512 case CODE_LABEL:
5513 case LABEL_REF:
5514 case SYMBOL_REF:
5515 output_addr_const (file, x);
5516 break;
5517
5518 case CONST_INT:
5519 if (code == 'b')
5520 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5521 else if (code == 'c')
5522 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5523 else if (code == 'x')
5524 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5525 else if (code == 'h')
5526 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5527 else if (code == 'i')
5528 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5529 s390_extract_part (x, HImode, 0));
5530 else if (code == 'j')
5531 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5532 s390_extract_part (x, HImode, -1));
5533 else if (code == 'k')
5534 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5535 s390_extract_part (x, SImode, 0));
5536 else if (code == 'm')
5537 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5538 s390_extract_part (x, SImode, -1));
5539 else if (code == 'o')
5540 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5541 else
5542 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5543 break;
5544
5545 case CONST_DOUBLE:
5546 gcc_assert (GET_MODE (x) == VOIDmode);
5547 if (code == 'b')
5548 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5549 else if (code == 'x')
5550 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5551 else if (code == 'h')
5552 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5553 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5554 else
5555 {
5556 if (code == 0)
5557 output_operand_lossage ("invalid constant - try using "
5558 "an output modifier");
5559 else
5560 output_operand_lossage ("invalid constant for output modifier '%c'",
5561 code);
5562 }
5563 break;
5564
5565 default:
5566 if (code == 0)
5567 output_operand_lossage ("invalid expression - try using "
5568 "an output modifier");
5569 else
5570 output_operand_lossage ("invalid expression for output "
5571 "modifier '%c'", code);
5572 break;
5573 }
5574 }
5575
5576 /* Target hook for assembling integer objects. We need to define it
5577 here to work a round a bug in some versions of GAS, which couldn't
5578 handle values smaller than INT_MIN when printed in decimal. */
5579
5580 static bool
5581 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5582 {
5583 if (size == 8 && aligned_p
5584 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5585 {
5586 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5587 INTVAL (x));
5588 return true;
5589 }
5590 return default_assemble_integer (x, size, aligned_p);
5591 }
5592
5593 /* Returns true if register REGNO is used for forming
5594 a memory address in expression X. */
5595
5596 static bool
5597 reg_used_in_mem_p (int regno, rtx x)
5598 {
5599 enum rtx_code code = GET_CODE (x);
5600 int i, j;
5601 const char *fmt;
5602
5603 if (code == MEM)
5604 {
5605 if (refers_to_regno_p (regno, regno+1,
5606 XEXP (x, 0), 0))
5607 return true;
5608 }
5609 else if (code == SET
5610 && GET_CODE (SET_DEST (x)) == PC)
5611 {
5612 if (refers_to_regno_p (regno, regno+1,
5613 SET_SRC (x), 0))
5614 return true;
5615 }
5616
5617 fmt = GET_RTX_FORMAT (code);
5618 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5619 {
5620 if (fmt[i] == 'e'
5621 && reg_used_in_mem_p (regno, XEXP (x, i)))
5622 return true;
5623
5624 else if (fmt[i] == 'E')
5625 for (j = 0; j < XVECLEN (x, i); j++)
5626 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5627 return true;
5628 }
5629 return false;
5630 }
5631
5632 /* Returns true if expression DEP_RTX sets an address register
5633 used by instruction INSN to address memory. */
5634
5635 static bool
5636 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5637 {
5638 rtx target, pat;
5639
5640 if (GET_CODE (dep_rtx) == INSN)
5641 dep_rtx = PATTERN (dep_rtx);
5642
5643 if (GET_CODE (dep_rtx) == SET)
5644 {
5645 target = SET_DEST (dep_rtx);
5646 if (GET_CODE (target) == STRICT_LOW_PART)
5647 target = XEXP (target, 0);
5648 while (GET_CODE (target) == SUBREG)
5649 target = SUBREG_REG (target);
5650
5651 if (GET_CODE (target) == REG)
5652 {
5653 int regno = REGNO (target);
5654
5655 if (s390_safe_attr_type (insn) == TYPE_LA)
5656 {
5657 pat = PATTERN (insn);
5658 if (GET_CODE (pat) == PARALLEL)
5659 {
5660 gcc_assert (XVECLEN (pat, 0) == 2);
5661 pat = XVECEXP (pat, 0, 0);
5662 }
5663 gcc_assert (GET_CODE (pat) == SET);
5664 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5665 }
5666 else if (get_attr_atype (insn) == ATYPE_AGEN)
5667 return reg_used_in_mem_p (regno, PATTERN (insn));
5668 }
5669 }
5670 return false;
5671 }
5672
5673 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5674
5675 int
5676 s390_agen_dep_p (rtx dep_insn, rtx insn)
5677 {
5678 rtx dep_rtx = PATTERN (dep_insn);
5679 int i;
5680
5681 if (GET_CODE (dep_rtx) == SET
5682 && addr_generation_dependency_p (dep_rtx, insn))
5683 return 1;
5684 else if (GET_CODE (dep_rtx) == PARALLEL)
5685 {
5686 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5687 {
5688 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5689 return 1;
5690 }
5691 }
5692 return 0;
5693 }
5694
5695
5696 /* A C statement (sans semicolon) to update the integer scheduling priority
5697 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5698 reduce the priority to execute INSN later. Do not define this macro if
5699 you do not need to adjust the scheduling priorities of insns.
5700
5701 A STD instruction should be scheduled earlier,
5702 in order to use the bypass. */
5703 static int
5704 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5705 {
5706 if (! INSN_P (insn))
5707 return priority;
5708
5709 if (s390_tune != PROCESSOR_2084_Z990
5710 && s390_tune != PROCESSOR_2094_Z9_109
5711 && s390_tune != PROCESSOR_2097_Z10
5712 && s390_tune != PROCESSOR_2817_Z196)
5713 return priority;
5714
5715 switch (s390_safe_attr_type (insn))
5716 {
5717 case TYPE_FSTOREDF:
5718 case TYPE_FSTORESF:
5719 priority = priority << 3;
5720 break;
5721 case TYPE_STORE:
5722 case TYPE_STM:
5723 priority = priority << 1;
5724 break;
5725 default:
5726 break;
5727 }
5728 return priority;
5729 }
5730
5731
5732 /* The number of instructions that can be issued per cycle. */
5733
5734 static int
5735 s390_issue_rate (void)
5736 {
5737 switch (s390_tune)
5738 {
5739 case PROCESSOR_2084_Z990:
5740 case PROCESSOR_2094_Z9_109:
5741 case PROCESSOR_2817_Z196:
5742 return 3;
5743 case PROCESSOR_2097_Z10:
5744 return 2;
5745 default:
5746 return 1;
5747 }
5748 }
5749
5750 static int
5751 s390_first_cycle_multipass_dfa_lookahead (void)
5752 {
5753 return 4;
5754 }
5755
5756 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5757 Fix up MEMs as required. */
5758
5759 static void
5760 annotate_constant_pool_refs (rtx *x)
5761 {
5762 int i, j;
5763 const char *fmt;
5764
5765 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5766 || !CONSTANT_POOL_ADDRESS_P (*x));
5767
5768 /* Literal pool references can only occur inside a MEM ... */
5769 if (GET_CODE (*x) == MEM)
5770 {
5771 rtx memref = XEXP (*x, 0);
5772
5773 if (GET_CODE (memref) == SYMBOL_REF
5774 && CONSTANT_POOL_ADDRESS_P (memref))
5775 {
5776 rtx base = cfun->machine->base_reg;
5777 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5778 UNSPEC_LTREF);
5779
5780 *x = replace_equiv_address (*x, addr);
5781 return;
5782 }
5783
5784 if (GET_CODE (memref) == CONST
5785 && GET_CODE (XEXP (memref, 0)) == PLUS
5786 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5787 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5788 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5789 {
5790 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5791 rtx sym = XEXP (XEXP (memref, 0), 0);
5792 rtx base = cfun->machine->base_reg;
5793 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5794 UNSPEC_LTREF);
5795
5796 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5797 return;
5798 }
5799 }
5800
5801 /* ... or a load-address type pattern. */
5802 if (GET_CODE (*x) == SET)
5803 {
5804 rtx addrref = SET_SRC (*x);
5805
5806 if (GET_CODE (addrref) == SYMBOL_REF
5807 && CONSTANT_POOL_ADDRESS_P (addrref))
5808 {
5809 rtx base = cfun->machine->base_reg;
5810 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5811 UNSPEC_LTREF);
5812
5813 SET_SRC (*x) = addr;
5814 return;
5815 }
5816
5817 if (GET_CODE (addrref) == CONST
5818 && GET_CODE (XEXP (addrref, 0)) == PLUS
5819 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5820 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5821 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5822 {
5823 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5824 rtx sym = XEXP (XEXP (addrref, 0), 0);
5825 rtx base = cfun->machine->base_reg;
5826 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5827 UNSPEC_LTREF);
5828
5829 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5830 return;
5831 }
5832 }
5833
5834 /* Annotate LTREL_BASE as well. */
5835 if (GET_CODE (*x) == UNSPEC
5836 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5837 {
5838 rtx base = cfun->machine->base_reg;
5839 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5840 UNSPEC_LTREL_BASE);
5841 return;
5842 }
5843
5844 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5845 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5846 {
5847 if (fmt[i] == 'e')
5848 {
5849 annotate_constant_pool_refs (&XEXP (*x, i));
5850 }
5851 else if (fmt[i] == 'E')
5852 {
5853 for (j = 0; j < XVECLEN (*x, i); j++)
5854 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5855 }
5856 }
5857 }
5858
5859 /* Split all branches that exceed the maximum distance.
5860 Returns true if this created a new literal pool entry. */
5861
5862 static int
5863 s390_split_branches (void)
5864 {
5865 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5866 int new_literal = 0, ret;
5867 rtx insn, pat, tmp, target;
5868 rtx *label;
5869
5870 /* We need correct insn addresses. */
5871
5872 shorten_branches (get_insns ());
5873
5874 /* Find all branches that exceed 64KB, and split them. */
5875
5876 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5877 {
5878 if (GET_CODE (insn) != JUMP_INSN)
5879 continue;
5880
5881 pat = PATTERN (insn);
5882 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5883 pat = XVECEXP (pat, 0, 0);
5884 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5885 continue;
5886
5887 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5888 {
5889 label = &SET_SRC (pat);
5890 }
5891 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5892 {
5893 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5894 label = &XEXP (SET_SRC (pat), 1);
5895 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5896 label = &XEXP (SET_SRC (pat), 2);
5897 else
5898 continue;
5899 }
5900 else
5901 continue;
5902
5903 if (get_attr_length (insn) <= 4)
5904 continue;
5905
5906 /* We are going to use the return register as scratch register,
5907 make sure it will be saved/restored by the prologue/epilogue. */
5908 cfun_frame_layout.save_return_addr_p = 1;
5909
5910 if (!flag_pic)
5911 {
5912 new_literal = 1;
5913 tmp = force_const_mem (Pmode, *label);
5914 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5915 INSN_ADDRESSES_NEW (tmp, -1);
5916 annotate_constant_pool_refs (&PATTERN (tmp));
5917
5918 target = temp_reg;
5919 }
5920 else
5921 {
5922 new_literal = 1;
5923 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5924 UNSPEC_LTREL_OFFSET);
5925 target = gen_rtx_CONST (Pmode, target);
5926 target = force_const_mem (Pmode, target);
5927 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5928 INSN_ADDRESSES_NEW (tmp, -1);
5929 annotate_constant_pool_refs (&PATTERN (tmp));
5930
5931 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5932 cfun->machine->base_reg),
5933 UNSPEC_LTREL_BASE);
5934 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5935 }
5936
5937 ret = validate_change (insn, label, target, 0);
5938 gcc_assert (ret);
5939 }
5940
5941 return new_literal;
5942 }
5943
5944
5945 /* Find an annotated literal pool symbol referenced in RTX X,
5946 and store it at REF. Will abort if X contains references to
5947 more than one such pool symbol; multiple references to the same
5948 symbol are allowed, however.
5949
5950 The rtx pointed to by REF must be initialized to NULL_RTX
5951 by the caller before calling this routine. */
5952
5953 static void
5954 find_constant_pool_ref (rtx x, rtx *ref)
5955 {
5956 int i, j;
5957 const char *fmt;
5958
5959 /* Ignore LTREL_BASE references. */
5960 if (GET_CODE (x) == UNSPEC
5961 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5962 return;
5963 /* Likewise POOL_ENTRY insns. */
5964 if (GET_CODE (x) == UNSPEC_VOLATILE
5965 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5966 return;
5967
5968 gcc_assert (GET_CODE (x) != SYMBOL_REF
5969 || !CONSTANT_POOL_ADDRESS_P (x));
5970
5971 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5972 {
5973 rtx sym = XVECEXP (x, 0, 0);
5974 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5975 && CONSTANT_POOL_ADDRESS_P (sym));
5976
5977 if (*ref == NULL_RTX)
5978 *ref = sym;
5979 else
5980 gcc_assert (*ref == sym);
5981
5982 return;
5983 }
5984
5985 fmt = GET_RTX_FORMAT (GET_CODE (x));
5986 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5987 {
5988 if (fmt[i] == 'e')
5989 {
5990 find_constant_pool_ref (XEXP (x, i), ref);
5991 }
5992 else if (fmt[i] == 'E')
5993 {
5994 for (j = 0; j < XVECLEN (x, i); j++)
5995 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5996 }
5997 }
5998 }
5999
6000 /* Replace every reference to the annotated literal pool
6001 symbol REF in X by its base plus OFFSET. */
6002
6003 static void
6004 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
6005 {
6006 int i, j;
6007 const char *fmt;
6008
6009 gcc_assert (*x != ref);
6010
6011 if (GET_CODE (*x) == UNSPEC
6012 && XINT (*x, 1) == UNSPEC_LTREF
6013 && XVECEXP (*x, 0, 0) == ref)
6014 {
6015 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6016 return;
6017 }
6018
6019 if (GET_CODE (*x) == PLUS
6020 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6021 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6022 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6023 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
6024 {
6025 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
6026 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
6027 return;
6028 }
6029
6030 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6031 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6032 {
6033 if (fmt[i] == 'e')
6034 {
6035 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
6036 }
6037 else if (fmt[i] == 'E')
6038 {
6039 for (j = 0; j < XVECLEN (*x, i); j++)
6040 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
6041 }
6042 }
6043 }
6044
6045 /* Check whether X contains an UNSPEC_LTREL_BASE.
6046 Return its constant pool symbol if found, NULL_RTX otherwise. */
6047
6048 static rtx
6049 find_ltrel_base (rtx x)
6050 {
6051 int i, j;
6052 const char *fmt;
6053
6054 if (GET_CODE (x) == UNSPEC
6055 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6056 return XVECEXP (x, 0, 0);
6057
6058 fmt = GET_RTX_FORMAT (GET_CODE (x));
6059 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6060 {
6061 if (fmt[i] == 'e')
6062 {
6063 rtx fnd = find_ltrel_base (XEXP (x, i));
6064 if (fnd)
6065 return fnd;
6066 }
6067 else if (fmt[i] == 'E')
6068 {
6069 for (j = 0; j < XVECLEN (x, i); j++)
6070 {
6071 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6072 if (fnd)
6073 return fnd;
6074 }
6075 }
6076 }
6077
6078 return NULL_RTX;
6079 }
6080
6081 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6082
6083 static void
6084 replace_ltrel_base (rtx *x)
6085 {
6086 int i, j;
6087 const char *fmt;
6088
6089 if (GET_CODE (*x) == UNSPEC
6090 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6091 {
6092 *x = XVECEXP (*x, 0, 1);
6093 return;
6094 }
6095
6096 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6097 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6098 {
6099 if (fmt[i] == 'e')
6100 {
6101 replace_ltrel_base (&XEXP (*x, i));
6102 }
6103 else if (fmt[i] == 'E')
6104 {
6105 for (j = 0; j < XVECLEN (*x, i); j++)
6106 replace_ltrel_base (&XVECEXP (*x, i, j));
6107 }
6108 }
6109 }
6110
6111
6112 /* We keep a list of constants which we have to add to internal
6113 constant tables in the middle of large functions. */
6114
6115 #define NR_C_MODES 11
6116 enum machine_mode constant_modes[NR_C_MODES] =
6117 {
6118 TFmode, TImode, TDmode,
6119 DFmode, DImode, DDmode,
6120 SFmode, SImode, SDmode,
6121 HImode,
6122 QImode
6123 };
6124
6125 struct constant
6126 {
6127 struct constant *next;
6128 rtx value;
6129 rtx label;
6130 };
6131
6132 struct constant_pool
6133 {
6134 struct constant_pool *next;
6135 rtx first_insn;
6136 rtx pool_insn;
6137 bitmap insns;
6138 rtx emit_pool_after;
6139
6140 struct constant *constants[NR_C_MODES];
6141 struct constant *execute;
6142 rtx label;
6143 int size;
6144 };
6145
6146 /* Allocate new constant_pool structure. */
6147
6148 static struct constant_pool *
6149 s390_alloc_pool (void)
6150 {
6151 struct constant_pool *pool;
6152 int i;
6153
6154 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6155 pool->next = NULL;
6156 for (i = 0; i < NR_C_MODES; i++)
6157 pool->constants[i] = NULL;
6158
6159 pool->execute = NULL;
6160 pool->label = gen_label_rtx ();
6161 pool->first_insn = NULL_RTX;
6162 pool->pool_insn = NULL_RTX;
6163 pool->insns = BITMAP_ALLOC (NULL);
6164 pool->size = 0;
6165 pool->emit_pool_after = NULL_RTX;
6166
6167 return pool;
6168 }
6169
6170 /* Create new constant pool covering instructions starting at INSN
6171 and chain it to the end of POOL_LIST. */
6172
6173 static struct constant_pool *
6174 s390_start_pool (struct constant_pool **pool_list, rtx insn)
6175 {
6176 struct constant_pool *pool, **prev;
6177
6178 pool = s390_alloc_pool ();
6179 pool->first_insn = insn;
6180
6181 for (prev = pool_list; *prev; prev = &(*prev)->next)
6182 ;
6183 *prev = pool;
6184
6185 return pool;
6186 }
6187
6188 /* End range of instructions covered by POOL at INSN and emit
6189 placeholder insn representing the pool. */
6190
6191 static void
6192 s390_end_pool (struct constant_pool *pool, rtx insn)
6193 {
6194 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6195
6196 if (!insn)
6197 insn = get_last_insn ();
6198
6199 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6200 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6201 }
6202
6203 /* Add INSN to the list of insns covered by POOL. */
6204
6205 static void
6206 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6207 {
6208 bitmap_set_bit (pool->insns, INSN_UID (insn));
6209 }
6210
6211 /* Return pool out of POOL_LIST that covers INSN. */
6212
6213 static struct constant_pool *
6214 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6215 {
6216 struct constant_pool *pool;
6217
6218 for (pool = pool_list; pool; pool = pool->next)
6219 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6220 break;
6221
6222 return pool;
6223 }
6224
6225 /* Add constant VAL of mode MODE to the constant pool POOL. */
6226
6227 static void
6228 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6229 {
6230 struct constant *c;
6231 int i;
6232
6233 for (i = 0; i < NR_C_MODES; i++)
6234 if (constant_modes[i] == mode)
6235 break;
6236 gcc_assert (i != NR_C_MODES);
6237
6238 for (c = pool->constants[i]; c != NULL; c = c->next)
6239 if (rtx_equal_p (val, c->value))
6240 break;
6241
6242 if (c == NULL)
6243 {
6244 c = (struct constant *) xmalloc (sizeof *c);
6245 c->value = val;
6246 c->label = gen_label_rtx ();
6247 c->next = pool->constants[i];
6248 pool->constants[i] = c;
6249 pool->size += GET_MODE_SIZE (mode);
6250 }
6251 }
6252
6253 /* Return an rtx that represents the offset of X from the start of
6254 pool POOL. */
6255
6256 static rtx
6257 s390_pool_offset (struct constant_pool *pool, rtx x)
6258 {
6259 rtx label;
6260
6261 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6262 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6263 UNSPEC_POOL_OFFSET);
6264 return gen_rtx_CONST (GET_MODE (x), x);
6265 }
6266
6267 /* Find constant VAL of mode MODE in the constant pool POOL.
6268 Return an RTX describing the distance from the start of
6269 the pool to the location of the new constant. */
6270
6271 static rtx
6272 s390_find_constant (struct constant_pool *pool, rtx val,
6273 enum machine_mode mode)
6274 {
6275 struct constant *c;
6276 int i;
6277
6278 for (i = 0; i < NR_C_MODES; i++)
6279 if (constant_modes[i] == mode)
6280 break;
6281 gcc_assert (i != NR_C_MODES);
6282
6283 for (c = pool->constants[i]; c != NULL; c = c->next)
6284 if (rtx_equal_p (val, c->value))
6285 break;
6286
6287 gcc_assert (c);
6288
6289 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6290 }
6291
6292 /* Check whether INSN is an execute. Return the label_ref to its
6293 execute target template if so, NULL_RTX otherwise. */
6294
6295 static rtx
6296 s390_execute_label (rtx insn)
6297 {
6298 if (GET_CODE (insn) == INSN
6299 && GET_CODE (PATTERN (insn)) == PARALLEL
6300 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6301 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6302 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6303
6304 return NULL_RTX;
6305 }
6306
6307 /* Add execute target for INSN to the constant pool POOL. */
6308
6309 static void
6310 s390_add_execute (struct constant_pool *pool, rtx insn)
6311 {
6312 struct constant *c;
6313
6314 for (c = pool->execute; c != NULL; c = c->next)
6315 if (INSN_UID (insn) == INSN_UID (c->value))
6316 break;
6317
6318 if (c == NULL)
6319 {
6320 c = (struct constant *) xmalloc (sizeof *c);
6321 c->value = insn;
6322 c->label = gen_label_rtx ();
6323 c->next = pool->execute;
6324 pool->execute = c;
6325 pool->size += 6;
6326 }
6327 }
6328
6329 /* Find execute target for INSN in the constant pool POOL.
6330 Return an RTX describing the distance from the start of
6331 the pool to the location of the execute target. */
6332
6333 static rtx
6334 s390_find_execute (struct constant_pool *pool, rtx insn)
6335 {
6336 struct constant *c;
6337
6338 for (c = pool->execute; c != NULL; c = c->next)
6339 if (INSN_UID (insn) == INSN_UID (c->value))
6340 break;
6341
6342 gcc_assert (c);
6343
6344 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6345 }
6346
6347 /* For an execute INSN, extract the execute target template. */
6348
6349 static rtx
6350 s390_execute_target (rtx insn)
6351 {
6352 rtx pattern = PATTERN (insn);
6353 gcc_assert (s390_execute_label (insn));
6354
6355 if (XVECLEN (pattern, 0) == 2)
6356 {
6357 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6358 }
6359 else
6360 {
6361 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6362 int i;
6363
6364 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6365 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6366
6367 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6368 }
6369
6370 return pattern;
6371 }
6372
6373 /* Indicate that INSN cannot be duplicated. This is the case for
6374 execute insns that carry a unique label. */
6375
6376 static bool
6377 s390_cannot_copy_insn_p (rtx insn)
6378 {
6379 rtx label = s390_execute_label (insn);
6380 return label && label != const0_rtx;
6381 }
6382
6383 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6384 do not emit the pool base label. */
6385
6386 static void
6387 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6388 {
6389 struct constant *c;
6390 rtx insn = pool->pool_insn;
6391 int i;
6392
6393 /* Switch to rodata section. */
6394 if (TARGET_CPU_ZARCH)
6395 {
6396 insn = emit_insn_after (gen_pool_section_start (), insn);
6397 INSN_ADDRESSES_NEW (insn, -1);
6398 }
6399
6400 /* Ensure minimum pool alignment. */
6401 if (TARGET_CPU_ZARCH)
6402 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6403 else
6404 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6405 INSN_ADDRESSES_NEW (insn, -1);
6406
6407 /* Emit pool base label. */
6408 if (!remote_label)
6409 {
6410 insn = emit_label_after (pool->label, insn);
6411 INSN_ADDRESSES_NEW (insn, -1);
6412 }
6413
6414 /* Dump constants in descending alignment requirement order,
6415 ensuring proper alignment for every constant. */
6416 for (i = 0; i < NR_C_MODES; i++)
6417 for (c = pool->constants[i]; c; c = c->next)
6418 {
6419 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6420 rtx value = copy_rtx (c->value);
6421 if (GET_CODE (value) == CONST
6422 && GET_CODE (XEXP (value, 0)) == UNSPEC
6423 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6424 && XVECLEN (XEXP (value, 0), 0) == 1)
6425 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6426
6427 insn = emit_label_after (c->label, insn);
6428 INSN_ADDRESSES_NEW (insn, -1);
6429
6430 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6431 gen_rtvec (1, value),
6432 UNSPECV_POOL_ENTRY);
6433 insn = emit_insn_after (value, insn);
6434 INSN_ADDRESSES_NEW (insn, -1);
6435 }
6436
6437 /* Ensure minimum alignment for instructions. */
6438 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6439 INSN_ADDRESSES_NEW (insn, -1);
6440
6441 /* Output in-pool execute template insns. */
6442 for (c = pool->execute; c; c = c->next)
6443 {
6444 insn = emit_label_after (c->label, insn);
6445 INSN_ADDRESSES_NEW (insn, -1);
6446
6447 insn = emit_insn_after (s390_execute_target (c->value), insn);
6448 INSN_ADDRESSES_NEW (insn, -1);
6449 }
6450
6451 /* Switch back to previous section. */
6452 if (TARGET_CPU_ZARCH)
6453 {
6454 insn = emit_insn_after (gen_pool_section_end (), insn);
6455 INSN_ADDRESSES_NEW (insn, -1);
6456 }
6457
6458 insn = emit_barrier_after (insn);
6459 INSN_ADDRESSES_NEW (insn, -1);
6460
6461 /* Remove placeholder insn. */
6462 remove_insn (pool->pool_insn);
6463 }
6464
6465 /* Free all memory used by POOL. */
6466
6467 static void
6468 s390_free_pool (struct constant_pool *pool)
6469 {
6470 struct constant *c, *next;
6471 int i;
6472
6473 for (i = 0; i < NR_C_MODES; i++)
6474 for (c = pool->constants[i]; c; c = next)
6475 {
6476 next = c->next;
6477 free (c);
6478 }
6479
6480 for (c = pool->execute; c; c = next)
6481 {
6482 next = c->next;
6483 free (c);
6484 }
6485
6486 BITMAP_FREE (pool->insns);
6487 free (pool);
6488 }
6489
6490
6491 /* Collect main literal pool. Return NULL on overflow. */
6492
6493 static struct constant_pool *
6494 s390_mainpool_start (void)
6495 {
6496 struct constant_pool *pool;
6497 rtx insn;
6498
6499 pool = s390_alloc_pool ();
6500
6501 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6502 {
6503 if (GET_CODE (insn) == INSN
6504 && GET_CODE (PATTERN (insn)) == SET
6505 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6506 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6507 {
6508 gcc_assert (!pool->pool_insn);
6509 pool->pool_insn = insn;
6510 }
6511
6512 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6513 {
6514 s390_add_execute (pool, insn);
6515 }
6516 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6517 {
6518 rtx pool_ref = NULL_RTX;
6519 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6520 if (pool_ref)
6521 {
6522 rtx constant = get_pool_constant (pool_ref);
6523 enum machine_mode mode = get_pool_mode (pool_ref);
6524 s390_add_constant (pool, constant, mode);
6525 }
6526 }
6527
6528 /* If hot/cold partitioning is enabled we have to make sure that
6529 the literal pool is emitted in the same section where the
6530 initialization of the literal pool base pointer takes place.
6531 emit_pool_after is only used in the non-overflow case on non
6532 Z cpus where we can emit the literal pool at the end of the
6533 function body within the text section. */
6534 if (NOTE_P (insn)
6535 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6536 && !pool->emit_pool_after)
6537 pool->emit_pool_after = PREV_INSN (insn);
6538 }
6539
6540 gcc_assert (pool->pool_insn || pool->size == 0);
6541
6542 if (pool->size >= 4096)
6543 {
6544 /* We're going to chunkify the pool, so remove the main
6545 pool placeholder insn. */
6546 remove_insn (pool->pool_insn);
6547
6548 s390_free_pool (pool);
6549 pool = NULL;
6550 }
6551
6552 /* If the functions ends with the section where the literal pool
6553 should be emitted set the marker to its end. */
6554 if (pool && !pool->emit_pool_after)
6555 pool->emit_pool_after = get_last_insn ();
6556
6557 return pool;
6558 }
6559
6560 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6561 Modify the current function to output the pool constants as well as
6562 the pool register setup instruction. */
6563
6564 static void
6565 s390_mainpool_finish (struct constant_pool *pool)
6566 {
6567 rtx base_reg = cfun->machine->base_reg;
6568 rtx insn;
6569
6570 /* If the pool is empty, we're done. */
6571 if (pool->size == 0)
6572 {
6573 /* We don't actually need a base register after all. */
6574 cfun->machine->base_reg = NULL_RTX;
6575
6576 if (pool->pool_insn)
6577 remove_insn (pool->pool_insn);
6578 s390_free_pool (pool);
6579 return;
6580 }
6581
6582 /* We need correct insn addresses. */
6583 shorten_branches (get_insns ());
6584
6585 /* On zSeries, we use a LARL to load the pool register. The pool is
6586 located in the .rodata section, so we emit it after the function. */
6587 if (TARGET_CPU_ZARCH)
6588 {
6589 insn = gen_main_base_64 (base_reg, pool->label);
6590 insn = emit_insn_after (insn, pool->pool_insn);
6591 INSN_ADDRESSES_NEW (insn, -1);
6592 remove_insn (pool->pool_insn);
6593
6594 insn = get_last_insn ();
6595 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6596 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6597
6598 s390_dump_pool (pool, 0);
6599 }
6600
6601 /* On S/390, if the total size of the function's code plus literal pool
6602 does not exceed 4096 bytes, we use BASR to set up a function base
6603 pointer, and emit the literal pool at the end of the function. */
6604 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6605 + pool->size + 8 /* alignment slop */ < 4096)
6606 {
6607 insn = gen_main_base_31_small (base_reg, pool->label);
6608 insn = emit_insn_after (insn, pool->pool_insn);
6609 INSN_ADDRESSES_NEW (insn, -1);
6610 remove_insn (pool->pool_insn);
6611
6612 insn = emit_label_after (pool->label, insn);
6613 INSN_ADDRESSES_NEW (insn, -1);
6614
6615 /* emit_pool_after will be set by s390_mainpool_start to the
6616 last insn of the section where the literal pool should be
6617 emitted. */
6618 insn = pool->emit_pool_after;
6619
6620 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6621 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6622
6623 s390_dump_pool (pool, 1);
6624 }
6625
6626 /* Otherwise, we emit an inline literal pool and use BASR to branch
6627 over it, setting up the pool register at the same time. */
6628 else
6629 {
6630 rtx pool_end = gen_label_rtx ();
6631
6632 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6633 insn = emit_jump_insn_after (insn, pool->pool_insn);
6634 JUMP_LABEL (insn) = pool_end;
6635 INSN_ADDRESSES_NEW (insn, -1);
6636 remove_insn (pool->pool_insn);
6637
6638 insn = emit_label_after (pool->label, insn);
6639 INSN_ADDRESSES_NEW (insn, -1);
6640
6641 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6642 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6643
6644 insn = emit_label_after (pool_end, pool->pool_insn);
6645 INSN_ADDRESSES_NEW (insn, -1);
6646
6647 s390_dump_pool (pool, 1);
6648 }
6649
6650
6651 /* Replace all literal pool references. */
6652
6653 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6654 {
6655 if (INSN_P (insn))
6656 replace_ltrel_base (&PATTERN (insn));
6657
6658 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6659 {
6660 rtx addr, pool_ref = NULL_RTX;
6661 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6662 if (pool_ref)
6663 {
6664 if (s390_execute_label (insn))
6665 addr = s390_find_execute (pool, insn);
6666 else
6667 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6668 get_pool_mode (pool_ref));
6669
6670 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6671 INSN_CODE (insn) = -1;
6672 }
6673 }
6674 }
6675
6676
6677 /* Free the pool. */
6678 s390_free_pool (pool);
6679 }
6680
6681 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6682 We have decided we cannot use this pool, so revert all changes
6683 to the current function that were done by s390_mainpool_start. */
6684 static void
6685 s390_mainpool_cancel (struct constant_pool *pool)
6686 {
6687 /* We didn't actually change the instruction stream, so simply
6688 free the pool memory. */
6689 s390_free_pool (pool);
6690 }
6691
6692
6693 /* Chunkify the literal pool. */
6694
6695 #define S390_POOL_CHUNK_MIN 0xc00
6696 #define S390_POOL_CHUNK_MAX 0xe00
6697
6698 static struct constant_pool *
6699 s390_chunkify_start (void)
6700 {
6701 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6702 int extra_size = 0;
6703 bitmap far_labels;
6704 rtx pending_ltrel = NULL_RTX;
6705 rtx insn;
6706
6707 rtx (*gen_reload_base) (rtx, rtx) =
6708 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6709
6710
6711 /* We need correct insn addresses. */
6712
6713 shorten_branches (get_insns ());
6714
6715 /* Scan all insns and move literals to pool chunks. */
6716
6717 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6718 {
6719 bool section_switch_p = false;
6720
6721 /* Check for pending LTREL_BASE. */
6722 if (INSN_P (insn))
6723 {
6724 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6725 if (ltrel_base)
6726 {
6727 gcc_assert (ltrel_base == pending_ltrel);
6728 pending_ltrel = NULL_RTX;
6729 }
6730 }
6731
6732 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6733 {
6734 if (!curr_pool)
6735 curr_pool = s390_start_pool (&pool_list, insn);
6736
6737 s390_add_execute (curr_pool, insn);
6738 s390_add_pool_insn (curr_pool, insn);
6739 }
6740 else if (GET_CODE (insn) == INSN || CALL_P (insn))
6741 {
6742 rtx pool_ref = NULL_RTX;
6743 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6744 if (pool_ref)
6745 {
6746 rtx constant = get_pool_constant (pool_ref);
6747 enum machine_mode mode = get_pool_mode (pool_ref);
6748
6749 if (!curr_pool)
6750 curr_pool = s390_start_pool (&pool_list, insn);
6751
6752 s390_add_constant (curr_pool, constant, mode);
6753 s390_add_pool_insn (curr_pool, insn);
6754
6755 /* Don't split the pool chunk between a LTREL_OFFSET load
6756 and the corresponding LTREL_BASE. */
6757 if (GET_CODE (constant) == CONST
6758 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6759 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6760 {
6761 gcc_assert (!pending_ltrel);
6762 pending_ltrel = pool_ref;
6763 }
6764 }
6765 }
6766
6767 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6768 {
6769 if (curr_pool)
6770 s390_add_pool_insn (curr_pool, insn);
6771 /* An LTREL_BASE must follow within the same basic block. */
6772 gcc_assert (!pending_ltrel);
6773 }
6774
6775 if (NOTE_P (insn))
6776 switch (NOTE_KIND (insn))
6777 {
6778 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6779 section_switch_p = true;
6780 break;
6781 case NOTE_INSN_VAR_LOCATION:
6782 case NOTE_INSN_CALL_ARG_LOCATION:
6783 continue;
6784 default:
6785 break;
6786 }
6787
6788 if (!curr_pool
6789 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6790 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6791 continue;
6792
6793 if (TARGET_CPU_ZARCH)
6794 {
6795 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6796 continue;
6797
6798 s390_end_pool (curr_pool, NULL_RTX);
6799 curr_pool = NULL;
6800 }
6801 else
6802 {
6803 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6804 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6805 + extra_size;
6806
6807 /* We will later have to insert base register reload insns.
6808 Those will have an effect on code size, which we need to
6809 consider here. This calculation makes rather pessimistic
6810 worst-case assumptions. */
6811 if (GET_CODE (insn) == CODE_LABEL)
6812 extra_size += 6;
6813
6814 if (chunk_size < S390_POOL_CHUNK_MIN
6815 && curr_pool->size < S390_POOL_CHUNK_MIN
6816 && !section_switch_p)
6817 continue;
6818
6819 /* Pool chunks can only be inserted after BARRIERs ... */
6820 if (GET_CODE (insn) == BARRIER)
6821 {
6822 s390_end_pool (curr_pool, insn);
6823 curr_pool = NULL;
6824 extra_size = 0;
6825 }
6826
6827 /* ... so if we don't find one in time, create one. */
6828 else if (chunk_size > S390_POOL_CHUNK_MAX
6829 || curr_pool->size > S390_POOL_CHUNK_MAX
6830 || section_switch_p)
6831 {
6832 rtx label, jump, barrier, next, prev;
6833
6834 if (!section_switch_p)
6835 {
6836 /* We can insert the barrier only after a 'real' insn. */
6837 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6838 continue;
6839 if (get_attr_length (insn) == 0)
6840 continue;
6841 /* Don't separate LTREL_BASE from the corresponding
6842 LTREL_OFFSET load. */
6843 if (pending_ltrel)
6844 continue;
6845 next = insn;
6846 do
6847 {
6848 insn = next;
6849 next = NEXT_INSN (insn);
6850 }
6851 while (next
6852 && NOTE_P (next)
6853 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6854 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6855 }
6856 else
6857 {
6858 gcc_assert (!pending_ltrel);
6859
6860 /* The old pool has to end before the section switch
6861 note in order to make it part of the current
6862 section. */
6863 insn = PREV_INSN (insn);
6864 }
6865
6866 label = gen_label_rtx ();
6867 prev = insn;
6868 if (prev && NOTE_P (prev))
6869 prev = prev_nonnote_insn (prev);
6870 if (prev)
6871 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6872 INSN_LOCATION (prev));
6873 else
6874 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6875 barrier = emit_barrier_after (jump);
6876 insn = emit_label_after (label, barrier);
6877 JUMP_LABEL (jump) = label;
6878 LABEL_NUSES (label) = 1;
6879
6880 INSN_ADDRESSES_NEW (jump, -1);
6881 INSN_ADDRESSES_NEW (barrier, -1);
6882 INSN_ADDRESSES_NEW (insn, -1);
6883
6884 s390_end_pool (curr_pool, barrier);
6885 curr_pool = NULL;
6886 extra_size = 0;
6887 }
6888 }
6889 }
6890
6891 if (curr_pool)
6892 s390_end_pool (curr_pool, NULL_RTX);
6893 gcc_assert (!pending_ltrel);
6894
6895 /* Find all labels that are branched into
6896 from an insn belonging to a different chunk. */
6897
6898 far_labels = BITMAP_ALLOC (NULL);
6899
6900 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6901 {
6902 /* Labels marked with LABEL_PRESERVE_P can be target
6903 of non-local jumps, so we have to mark them.
6904 The same holds for named labels.
6905
6906 Don't do that, however, if it is the label before
6907 a jump table. */
6908
6909 if (GET_CODE (insn) == CODE_LABEL
6910 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6911 {
6912 rtx vec_insn = next_real_insn (insn);
6913 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6914 PATTERN (vec_insn) : NULL_RTX;
6915 if (!vec_pat
6916 || !(GET_CODE (vec_pat) == ADDR_VEC
6917 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6918 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6919 }
6920
6921 /* If we have a direct jump (conditional or unconditional)
6922 or a casesi jump, check all potential targets. */
6923 else if (GET_CODE (insn) == JUMP_INSN)
6924 {
6925 rtx pat = PATTERN (insn);
6926 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6927 pat = XVECEXP (pat, 0, 0);
6928
6929 if (GET_CODE (pat) == SET)
6930 {
6931 rtx label = JUMP_LABEL (insn);
6932 if (label)
6933 {
6934 if (s390_find_pool (pool_list, label)
6935 != s390_find_pool (pool_list, insn))
6936 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6937 }
6938 }
6939 else if (GET_CODE (pat) == PARALLEL
6940 && XVECLEN (pat, 0) == 2
6941 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6942 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6943 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6944 {
6945 /* Find the jump table used by this casesi jump. */
6946 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6947 rtx vec_insn = next_real_insn (vec_label);
6948 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6949 PATTERN (vec_insn) : NULL_RTX;
6950 if (vec_pat
6951 && (GET_CODE (vec_pat) == ADDR_VEC
6952 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6953 {
6954 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6955
6956 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6957 {
6958 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6959
6960 if (s390_find_pool (pool_list, label)
6961 != s390_find_pool (pool_list, insn))
6962 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6963 }
6964 }
6965 }
6966 }
6967 }
6968
6969 /* Insert base register reload insns before every pool. */
6970
6971 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6972 {
6973 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6974 curr_pool->label);
6975 rtx insn = curr_pool->first_insn;
6976 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6977 }
6978
6979 /* Insert base register reload insns at every far label. */
6980
6981 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6982 if (GET_CODE (insn) == CODE_LABEL
6983 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6984 {
6985 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6986 if (pool)
6987 {
6988 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6989 pool->label);
6990 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6991 }
6992 }
6993
6994
6995 BITMAP_FREE (far_labels);
6996
6997
6998 /* Recompute insn addresses. */
6999
7000 init_insn_lengths ();
7001 shorten_branches (get_insns ());
7002
7003 return pool_list;
7004 }
7005
7006 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7007 After we have decided to use this list, finish implementing
7008 all changes to the current function as required. */
7009
7010 static void
7011 s390_chunkify_finish (struct constant_pool *pool_list)
7012 {
7013 struct constant_pool *curr_pool = NULL;
7014 rtx insn;
7015
7016
7017 /* Replace all literal pool references. */
7018
7019 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7020 {
7021 if (INSN_P (insn))
7022 replace_ltrel_base (&PATTERN (insn));
7023
7024 curr_pool = s390_find_pool (pool_list, insn);
7025 if (!curr_pool)
7026 continue;
7027
7028 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
7029 {
7030 rtx addr, pool_ref = NULL_RTX;
7031 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7032 if (pool_ref)
7033 {
7034 if (s390_execute_label (insn))
7035 addr = s390_find_execute (curr_pool, insn);
7036 else
7037 addr = s390_find_constant (curr_pool,
7038 get_pool_constant (pool_ref),
7039 get_pool_mode (pool_ref));
7040
7041 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7042 INSN_CODE (insn) = -1;
7043 }
7044 }
7045 }
7046
7047 /* Dump out all literal pools. */
7048
7049 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7050 s390_dump_pool (curr_pool, 0);
7051
7052 /* Free pool list. */
7053
7054 while (pool_list)
7055 {
7056 struct constant_pool *next = pool_list->next;
7057 s390_free_pool (pool_list);
7058 pool_list = next;
7059 }
7060 }
7061
7062 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7063 We have decided we cannot use this list, so revert all changes
7064 to the current function that were done by s390_chunkify_start. */
7065
7066 static void
7067 s390_chunkify_cancel (struct constant_pool *pool_list)
7068 {
7069 struct constant_pool *curr_pool = NULL;
7070 rtx insn;
7071
7072 /* Remove all pool placeholder insns. */
7073
7074 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7075 {
7076 /* Did we insert an extra barrier? Remove it. */
7077 rtx barrier = PREV_INSN (curr_pool->pool_insn);
7078 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
7079 rtx label = NEXT_INSN (curr_pool->pool_insn);
7080
7081 if (jump && GET_CODE (jump) == JUMP_INSN
7082 && barrier && GET_CODE (barrier) == BARRIER
7083 && label && GET_CODE (label) == CODE_LABEL
7084 && GET_CODE (PATTERN (jump)) == SET
7085 && SET_DEST (PATTERN (jump)) == pc_rtx
7086 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7087 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7088 {
7089 remove_insn (jump);
7090 remove_insn (barrier);
7091 remove_insn (label);
7092 }
7093
7094 remove_insn (curr_pool->pool_insn);
7095 }
7096
7097 /* Remove all base register reload insns. */
7098
7099 for (insn = get_insns (); insn; )
7100 {
7101 rtx next_insn = NEXT_INSN (insn);
7102
7103 if (GET_CODE (insn) == INSN
7104 && GET_CODE (PATTERN (insn)) == SET
7105 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7106 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7107 remove_insn (insn);
7108
7109 insn = next_insn;
7110 }
7111
7112 /* Free pool list. */
7113
7114 while (pool_list)
7115 {
7116 struct constant_pool *next = pool_list->next;
7117 s390_free_pool (pool_list);
7118 pool_list = next;
7119 }
7120 }
7121
7122 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7123
7124 void
7125 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
7126 {
7127 REAL_VALUE_TYPE r;
7128
7129 switch (GET_MODE_CLASS (mode))
7130 {
7131 case MODE_FLOAT:
7132 case MODE_DECIMAL_FLOAT:
7133 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7134
7135 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7136 assemble_real (r, mode, align);
7137 break;
7138
7139 case MODE_INT:
7140 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7141 mark_symbol_refs_as_used (exp);
7142 break;
7143
7144 default:
7145 gcc_unreachable ();
7146 }
7147 }
7148
7149
7150 /* Return an RTL expression representing the value of the return address
7151 for the frame COUNT steps up from the current frame. FRAME is the
7152 frame pointer of that frame. */
7153
7154 rtx
7155 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7156 {
7157 int offset;
7158 rtx addr;
7159
7160 /* Without backchain, we fail for all but the current frame. */
7161
7162 if (!TARGET_BACKCHAIN && count > 0)
7163 return NULL_RTX;
7164
7165 /* For the current frame, we need to make sure the initial
7166 value of RETURN_REGNUM is actually saved. */
7167
7168 if (count == 0)
7169 {
7170 /* On non-z architectures branch splitting could overwrite r14. */
7171 if (TARGET_CPU_ZARCH)
7172 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7173 else
7174 {
7175 cfun_frame_layout.save_return_addr_p = true;
7176 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7177 }
7178 }
7179
7180 if (TARGET_PACKED_STACK)
7181 offset = -2 * UNITS_PER_LONG;
7182 else
7183 offset = RETURN_REGNUM * UNITS_PER_LONG;
7184
7185 addr = plus_constant (Pmode, frame, offset);
7186 addr = memory_address (Pmode, addr);
7187 return gen_rtx_MEM (Pmode, addr);
7188 }
7189
7190 /* Return an RTL expression representing the back chain stored in
7191 the current stack frame. */
7192
7193 rtx
7194 s390_back_chain_rtx (void)
7195 {
7196 rtx chain;
7197
7198 gcc_assert (TARGET_BACKCHAIN);
7199
7200 if (TARGET_PACKED_STACK)
7201 chain = plus_constant (Pmode, stack_pointer_rtx,
7202 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7203 else
7204 chain = stack_pointer_rtx;
7205
7206 chain = gen_rtx_MEM (Pmode, chain);
7207 return chain;
7208 }
7209
7210 /* Find first call clobbered register unused in a function.
7211 This could be used as base register in a leaf function
7212 or for holding the return address before epilogue. */
7213
7214 static int
7215 find_unused_clobbered_reg (void)
7216 {
7217 int i;
7218 for (i = 0; i < 6; i++)
7219 if (!df_regs_ever_live_p (i))
7220 return i;
7221 return 0;
7222 }
7223
7224
7225 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7226 clobbered hard regs in SETREG. */
7227
7228 static void
7229 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7230 {
7231 int *regs_ever_clobbered = (int *)data;
7232 unsigned int i, regno;
7233 enum machine_mode mode = GET_MODE (setreg);
7234
7235 if (GET_CODE (setreg) == SUBREG)
7236 {
7237 rtx inner = SUBREG_REG (setreg);
7238 if (!GENERAL_REG_P (inner))
7239 return;
7240 regno = subreg_regno (setreg);
7241 }
7242 else if (GENERAL_REG_P (setreg))
7243 regno = REGNO (setreg);
7244 else
7245 return;
7246
7247 for (i = regno;
7248 i < regno + HARD_REGNO_NREGS (regno, mode);
7249 i++)
7250 regs_ever_clobbered[i] = 1;
7251 }
7252
7253 /* Walks through all basic blocks of the current function looking
7254 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7255 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7256 each of those regs. */
7257
7258 static void
7259 s390_regs_ever_clobbered (int *regs_ever_clobbered)
7260 {
7261 basic_block cur_bb;
7262 rtx cur_insn;
7263 unsigned int i;
7264
7265 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7266
7267 /* For non-leaf functions we have to consider all call clobbered regs to be
7268 clobbered. */
7269 if (!crtl->is_leaf)
7270 {
7271 for (i = 0; i < 16; i++)
7272 regs_ever_clobbered[i] = call_really_used_regs[i];
7273 }
7274
7275 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7276 this work is done by liveness analysis (mark_regs_live_at_end).
7277 Special care is needed for functions containing landing pads. Landing pads
7278 may use the eh registers, but the code which sets these registers is not
7279 contained in that function. Hence s390_regs_ever_clobbered is not able to
7280 deal with this automatically. */
7281 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7282 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7283 if (crtl->calls_eh_return
7284 || (cfun->machine->has_landing_pad_p
7285 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7286 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7287
7288 /* For nonlocal gotos all call-saved registers have to be saved.
7289 This flag is also set for the unwinding code in libgcc.
7290 See expand_builtin_unwind_init. For regs_ever_live this is done by
7291 reload. */
7292 if (cfun->has_nonlocal_label)
7293 for (i = 0; i < 16; i++)
7294 if (!call_really_used_regs[i])
7295 regs_ever_clobbered[i] = 1;
7296
7297 FOR_EACH_BB (cur_bb)
7298 {
7299 FOR_BB_INSNS (cur_bb, cur_insn)
7300 {
7301 if (INSN_P (cur_insn))
7302 note_stores (PATTERN (cur_insn),
7303 s390_reg_clobbered_rtx,
7304 regs_ever_clobbered);
7305 }
7306 }
7307 }
7308
7309 /* Determine the frame area which actually has to be accessed
7310 in the function epilogue. The values are stored at the
7311 given pointers AREA_BOTTOM (address of the lowest used stack
7312 address) and AREA_TOP (address of the first item which does
7313 not belong to the stack frame). */
7314
7315 static void
7316 s390_frame_area (int *area_bottom, int *area_top)
7317 {
7318 int b, t;
7319 int i;
7320
7321 b = INT_MAX;
7322 t = INT_MIN;
7323
7324 if (cfun_frame_layout.first_restore_gpr != -1)
7325 {
7326 b = (cfun_frame_layout.gprs_offset
7327 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7328 t = b + (cfun_frame_layout.last_restore_gpr
7329 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7330 }
7331
7332 if (TARGET_64BIT && cfun_save_high_fprs_p)
7333 {
7334 b = MIN (b, cfun_frame_layout.f8_offset);
7335 t = MAX (t, (cfun_frame_layout.f8_offset
7336 + cfun_frame_layout.high_fprs * 8));
7337 }
7338
7339 if (!TARGET_64BIT)
7340 for (i = 2; i < 4; i++)
7341 if (cfun_fpr_bit_p (i))
7342 {
7343 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7344 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7345 }
7346
7347 *area_bottom = b;
7348 *area_top = t;
7349 }
7350
7351 /* Fill cfun->machine with info about register usage of current function.
7352 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7353
7354 static void
7355 s390_register_info (int clobbered_regs[])
7356 {
7357 int i, j;
7358
7359 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7360 cfun_frame_layout.fpr_bitmap = 0;
7361 cfun_frame_layout.high_fprs = 0;
7362 if (TARGET_64BIT)
7363 for (i = 24; i < 32; i++)
7364 if (df_regs_ever_live_p (i) && !global_regs[i])
7365 {
7366 cfun_set_fpr_bit (i - 16);
7367 cfun_frame_layout.high_fprs++;
7368 }
7369
7370 /* Find first and last gpr to be saved. We trust regs_ever_live
7371 data, except that we don't save and restore global registers.
7372
7373 Also, all registers with special meaning to the compiler need
7374 to be handled extra. */
7375
7376 s390_regs_ever_clobbered (clobbered_regs);
7377
7378 for (i = 0; i < 16; i++)
7379 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7380
7381 if (frame_pointer_needed)
7382 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7383
7384 if (flag_pic)
7385 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7386 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7387
7388 clobbered_regs[BASE_REGNUM]
7389 |= (cfun->machine->base_reg
7390 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7391
7392 clobbered_regs[RETURN_REGNUM]
7393 |= (!crtl->is_leaf
7394 || TARGET_TPF_PROFILING
7395 || cfun->machine->split_branches_pending_p
7396 || cfun_frame_layout.save_return_addr_p
7397 || crtl->calls_eh_return
7398 || cfun->stdarg);
7399
7400 clobbered_regs[STACK_POINTER_REGNUM]
7401 |= (!crtl->is_leaf
7402 || TARGET_TPF_PROFILING
7403 || cfun_save_high_fprs_p
7404 || get_frame_size () > 0
7405 || cfun->calls_alloca
7406 || cfun->stdarg);
7407
7408 for (i = 6; i < 16; i++)
7409 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7410 break;
7411 for (j = 15; j > i; j--)
7412 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7413 break;
7414
7415 if (i == 16)
7416 {
7417 /* Nothing to save/restore. */
7418 cfun_frame_layout.first_save_gpr_slot = -1;
7419 cfun_frame_layout.last_save_gpr_slot = -1;
7420 cfun_frame_layout.first_save_gpr = -1;
7421 cfun_frame_layout.first_restore_gpr = -1;
7422 cfun_frame_layout.last_save_gpr = -1;
7423 cfun_frame_layout.last_restore_gpr = -1;
7424 }
7425 else
7426 {
7427 /* Save slots for gprs from i to j. */
7428 cfun_frame_layout.first_save_gpr_slot = i;
7429 cfun_frame_layout.last_save_gpr_slot = j;
7430
7431 for (i = cfun_frame_layout.first_save_gpr_slot;
7432 i < cfun_frame_layout.last_save_gpr_slot + 1;
7433 i++)
7434 if (clobbered_regs[i])
7435 break;
7436
7437 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7438 if (clobbered_regs[j])
7439 break;
7440
7441 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7442 {
7443 /* Nothing to save/restore. */
7444 cfun_frame_layout.first_save_gpr = -1;
7445 cfun_frame_layout.first_restore_gpr = -1;
7446 cfun_frame_layout.last_save_gpr = -1;
7447 cfun_frame_layout.last_restore_gpr = -1;
7448 }
7449 else
7450 {
7451 /* Save / Restore from gpr i to j. */
7452 cfun_frame_layout.first_save_gpr = i;
7453 cfun_frame_layout.first_restore_gpr = i;
7454 cfun_frame_layout.last_save_gpr = j;
7455 cfun_frame_layout.last_restore_gpr = j;
7456 }
7457 }
7458
7459 if (cfun->stdarg)
7460 {
7461 /* Varargs functions need to save gprs 2 to 6. */
7462 if (cfun->va_list_gpr_size
7463 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7464 {
7465 int min_gpr = crtl->args.info.gprs;
7466 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7467 if (max_gpr > GP_ARG_NUM_REG)
7468 max_gpr = GP_ARG_NUM_REG;
7469
7470 if (cfun_frame_layout.first_save_gpr == -1
7471 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7472 {
7473 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7474 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7475 }
7476
7477 if (cfun_frame_layout.last_save_gpr == -1
7478 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7479 {
7480 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7481 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7482 }
7483 }
7484
7485 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7486 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7487 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7488 {
7489 int min_fpr = crtl->args.info.fprs;
7490 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7491 if (max_fpr > FP_ARG_NUM_REG)
7492 max_fpr = FP_ARG_NUM_REG;
7493
7494 /* ??? This is currently required to ensure proper location
7495 of the fpr save slots within the va_list save area. */
7496 if (TARGET_PACKED_STACK)
7497 min_fpr = 0;
7498
7499 for (i = min_fpr; i < max_fpr; i++)
7500 cfun_set_fpr_bit (i);
7501 }
7502 }
7503
7504 if (!TARGET_64BIT)
7505 for (i = 2; i < 4; i++)
7506 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7507 cfun_set_fpr_bit (i);
7508 }
7509
7510 /* Fill cfun->machine with info about frame of current function. */
7511
7512 static void
7513 s390_frame_info (void)
7514 {
7515 int i;
7516
7517 cfun_frame_layout.frame_size = get_frame_size ();
7518 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7519 fatal_error ("total size of local variables exceeds architecture limit");
7520
7521 if (!TARGET_PACKED_STACK)
7522 {
7523 cfun_frame_layout.backchain_offset = 0;
7524 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7525 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7526 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7527 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7528 * UNITS_PER_LONG);
7529 }
7530 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7531 {
7532 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7533 - UNITS_PER_LONG);
7534 cfun_frame_layout.gprs_offset
7535 = (cfun_frame_layout.backchain_offset
7536 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7537 * UNITS_PER_LONG);
7538
7539 if (TARGET_64BIT)
7540 {
7541 cfun_frame_layout.f4_offset
7542 = (cfun_frame_layout.gprs_offset
7543 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7544
7545 cfun_frame_layout.f0_offset
7546 = (cfun_frame_layout.f4_offset
7547 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7548 }
7549 else
7550 {
7551 /* On 31 bit we have to care about alignment of the
7552 floating point regs to provide fastest access. */
7553 cfun_frame_layout.f0_offset
7554 = ((cfun_frame_layout.gprs_offset
7555 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7556 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7557
7558 cfun_frame_layout.f4_offset
7559 = (cfun_frame_layout.f0_offset
7560 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7561 }
7562 }
7563 else /* no backchain */
7564 {
7565 cfun_frame_layout.f4_offset
7566 = (STACK_POINTER_OFFSET
7567 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7568
7569 cfun_frame_layout.f0_offset
7570 = (cfun_frame_layout.f4_offset
7571 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7572
7573 cfun_frame_layout.gprs_offset
7574 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7575 }
7576
7577 if (crtl->is_leaf
7578 && !TARGET_TPF_PROFILING
7579 && cfun_frame_layout.frame_size == 0
7580 && !cfun_save_high_fprs_p
7581 && !cfun->calls_alloca
7582 && !cfun->stdarg)
7583 return;
7584
7585 if (!TARGET_PACKED_STACK)
7586 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7587 + crtl->outgoing_args_size
7588 + cfun_frame_layout.high_fprs * 8);
7589 else
7590 {
7591 if (TARGET_BACKCHAIN)
7592 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7593
7594 /* No alignment trouble here because f8-f15 are only saved under
7595 64 bit. */
7596 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7597 cfun_frame_layout.f4_offset),
7598 cfun_frame_layout.gprs_offset)
7599 - cfun_frame_layout.high_fprs * 8);
7600
7601 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7602
7603 for (i = 0; i < 8; i++)
7604 if (cfun_fpr_bit_p (i))
7605 cfun_frame_layout.frame_size += 8;
7606
7607 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7608
7609 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7610 the frame size to sustain 8 byte alignment of stack frames. */
7611 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7612 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7613 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7614
7615 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7616 }
7617 }
7618
7619 /* Generate frame layout. Fills in register and frame data for the current
7620 function in cfun->machine. This routine can be called multiple times;
7621 it will re-do the complete frame layout every time. */
7622
7623 static void
7624 s390_init_frame_layout (void)
7625 {
7626 HOST_WIDE_INT frame_size;
7627 int base_used;
7628 int clobbered_regs[16];
7629
7630 /* On S/390 machines, we may need to perform branch splitting, which
7631 will require both base and return address register. We have no
7632 choice but to assume we're going to need them until right at the
7633 end of the machine dependent reorg phase. */
7634 if (!TARGET_CPU_ZARCH)
7635 cfun->machine->split_branches_pending_p = true;
7636
7637 do
7638 {
7639 frame_size = cfun_frame_layout.frame_size;
7640
7641 /* Try to predict whether we'll need the base register. */
7642 base_used = cfun->machine->split_branches_pending_p
7643 || crtl->uses_const_pool
7644 || (!DISP_IN_RANGE (frame_size)
7645 && !CONST_OK_FOR_K (frame_size));
7646
7647 /* Decide which register to use as literal pool base. In small
7648 leaf functions, try to use an unused call-clobbered register
7649 as base register to avoid save/restore overhead. */
7650 if (!base_used)
7651 cfun->machine->base_reg = NULL_RTX;
7652 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7653 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7654 else
7655 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7656
7657 s390_register_info (clobbered_regs);
7658 s390_frame_info ();
7659 }
7660 while (frame_size != cfun_frame_layout.frame_size);
7661 }
7662
7663 /* Update frame layout. Recompute actual register save data based on
7664 current info and update regs_ever_live for the special registers.
7665 May be called multiple times, but may never cause *more* registers
7666 to be saved than s390_init_frame_layout allocated room for. */
7667
7668 static void
7669 s390_update_frame_layout (void)
7670 {
7671 int clobbered_regs[16];
7672
7673 s390_register_info (clobbered_regs);
7674
7675 df_set_regs_ever_live (BASE_REGNUM,
7676 clobbered_regs[BASE_REGNUM] ? true : false);
7677 df_set_regs_ever_live (RETURN_REGNUM,
7678 clobbered_regs[RETURN_REGNUM] ? true : false);
7679 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7680 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7681
7682 if (cfun->machine->base_reg)
7683 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7684 }
7685
7686 /* Return true if it is legal to put a value with MODE into REGNO. */
7687
7688 bool
7689 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7690 {
7691 switch (REGNO_REG_CLASS (regno))
7692 {
7693 case FP_REGS:
7694 if (REGNO_PAIR_OK (regno, mode))
7695 {
7696 if (mode == SImode || mode == DImode)
7697 return true;
7698
7699 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7700 return true;
7701 }
7702 break;
7703 case ADDR_REGS:
7704 if (FRAME_REGNO_P (regno) && mode == Pmode)
7705 return true;
7706
7707 /* fallthrough */
7708 case GENERAL_REGS:
7709 if (REGNO_PAIR_OK (regno, mode))
7710 {
7711 if (TARGET_ZARCH
7712 || (mode != TFmode && mode != TCmode && mode != TDmode))
7713 return true;
7714 }
7715 break;
7716 case CC_REGS:
7717 if (GET_MODE_CLASS (mode) == MODE_CC)
7718 return true;
7719 break;
7720 case ACCESS_REGS:
7721 if (REGNO_PAIR_OK (regno, mode))
7722 {
7723 if (mode == SImode || mode == Pmode)
7724 return true;
7725 }
7726 break;
7727 default:
7728 return false;
7729 }
7730
7731 return false;
7732 }
7733
7734 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7735
7736 bool
7737 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7738 {
7739 /* Once we've decided upon a register to use as base register, it must
7740 no longer be used for any other purpose. */
7741 if (cfun->machine->base_reg)
7742 if (REGNO (cfun->machine->base_reg) == old_reg
7743 || REGNO (cfun->machine->base_reg) == new_reg)
7744 return false;
7745
7746 return true;
7747 }
7748
7749 /* Maximum number of registers to represent a value of mode MODE
7750 in a register of class RCLASS. */
7751
7752 int
7753 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7754 {
7755 switch (rclass)
7756 {
7757 case FP_REGS:
7758 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7759 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7760 else
7761 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7762 case ACCESS_REGS:
7763 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7764 default:
7765 break;
7766 }
7767 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7768 }
7769
7770 /* Return true if register FROM can be eliminated via register TO. */
7771
7772 static bool
7773 s390_can_eliminate (const int from, const int to)
7774 {
7775 /* On zSeries machines, we have not marked the base register as fixed.
7776 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7777 If a function requires the base register, we say here that this
7778 elimination cannot be performed. This will cause reload to free
7779 up the base register (as if it were fixed). On the other hand,
7780 if the current function does *not* require the base register, we
7781 say here the elimination succeeds, which in turn allows reload
7782 to allocate the base register for any other purpose. */
7783 if (from == BASE_REGNUM && to == BASE_REGNUM)
7784 {
7785 if (TARGET_CPU_ZARCH)
7786 {
7787 s390_init_frame_layout ();
7788 return cfun->machine->base_reg == NULL_RTX;
7789 }
7790
7791 return false;
7792 }
7793
7794 /* Everything else must point into the stack frame. */
7795 gcc_assert (to == STACK_POINTER_REGNUM
7796 || to == HARD_FRAME_POINTER_REGNUM);
7797
7798 gcc_assert (from == FRAME_POINTER_REGNUM
7799 || from == ARG_POINTER_REGNUM
7800 || from == RETURN_ADDRESS_POINTER_REGNUM);
7801
7802 /* Make sure we actually saved the return address. */
7803 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7804 if (!crtl->calls_eh_return
7805 && !cfun->stdarg
7806 && !cfun_frame_layout.save_return_addr_p)
7807 return false;
7808
7809 return true;
7810 }
7811
7812 /* Return offset between register FROM and TO initially after prolog. */
7813
7814 HOST_WIDE_INT
7815 s390_initial_elimination_offset (int from, int to)
7816 {
7817 HOST_WIDE_INT offset;
7818 int index;
7819
7820 /* ??? Why are we called for non-eliminable pairs? */
7821 if (!s390_can_eliminate (from, to))
7822 return 0;
7823
7824 switch (from)
7825 {
7826 case FRAME_POINTER_REGNUM:
7827 offset = (get_frame_size()
7828 + STACK_POINTER_OFFSET
7829 + crtl->outgoing_args_size);
7830 break;
7831
7832 case ARG_POINTER_REGNUM:
7833 s390_init_frame_layout ();
7834 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7835 break;
7836
7837 case RETURN_ADDRESS_POINTER_REGNUM:
7838 s390_init_frame_layout ();
7839 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7840 gcc_assert (index >= 0);
7841 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7842 offset += index * UNITS_PER_LONG;
7843 break;
7844
7845 case BASE_REGNUM:
7846 offset = 0;
7847 break;
7848
7849 default:
7850 gcc_unreachable ();
7851 }
7852
7853 return offset;
7854 }
7855
7856 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7857 to register BASE. Return generated insn. */
7858
7859 static rtx
7860 save_fpr (rtx base, int offset, int regnum)
7861 {
7862 rtx addr;
7863 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7864
7865 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7866 set_mem_alias_set (addr, get_varargs_alias_set ());
7867 else
7868 set_mem_alias_set (addr, get_frame_alias_set ());
7869
7870 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7871 }
7872
7873 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7874 to register BASE. Return generated insn. */
7875
7876 static rtx
7877 restore_fpr (rtx base, int offset, int regnum)
7878 {
7879 rtx addr;
7880 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
7881 set_mem_alias_set (addr, get_frame_alias_set ());
7882
7883 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7884 }
7885
7886 /* Return true if REGNO is a global register, but not one
7887 of the special ones that need to be saved/restored in anyway. */
7888
7889 static inline bool
7890 global_not_special_regno_p (int regno)
7891 {
7892 return (global_regs[regno]
7893 /* These registers are special and need to be
7894 restored in any case. */
7895 && !(regno == STACK_POINTER_REGNUM
7896 || regno == RETURN_REGNUM
7897 || regno == BASE_REGNUM
7898 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7899 }
7900
7901 /* Generate insn to save registers FIRST to LAST into
7902 the register save area located at offset OFFSET
7903 relative to register BASE. */
7904
7905 static rtx
7906 save_gprs (rtx base, int offset, int first, int last)
7907 {
7908 rtx addr, insn, note;
7909 int i;
7910
7911 addr = plus_constant (Pmode, base, offset);
7912 addr = gen_rtx_MEM (Pmode, addr);
7913
7914 set_mem_alias_set (addr, get_frame_alias_set ());
7915
7916 /* Special-case single register. */
7917 if (first == last)
7918 {
7919 if (TARGET_64BIT)
7920 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7921 else
7922 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7923
7924 if (!global_not_special_regno_p (first))
7925 RTX_FRAME_RELATED_P (insn) = 1;
7926 return insn;
7927 }
7928
7929
7930 insn = gen_store_multiple (addr,
7931 gen_rtx_REG (Pmode, first),
7932 GEN_INT (last - first + 1));
7933
7934 if (first <= 6 && cfun->stdarg)
7935 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7936 {
7937 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7938
7939 if (first + i <= 6)
7940 set_mem_alias_set (mem, get_varargs_alias_set ());
7941 }
7942
7943 /* We need to set the FRAME_RELATED flag on all SETs
7944 inside the store-multiple pattern.
7945
7946 However, we must not emit DWARF records for registers 2..5
7947 if they are stored for use by variable arguments ...
7948
7949 ??? Unfortunately, it is not enough to simply not the
7950 FRAME_RELATED flags for those SETs, because the first SET
7951 of the PARALLEL is always treated as if it had the flag
7952 set, even if it does not. Therefore we emit a new pattern
7953 without those registers as REG_FRAME_RELATED_EXPR note. */
7954
7955 if (first >= 6 && !global_not_special_regno_p (first))
7956 {
7957 rtx pat = PATTERN (insn);
7958
7959 for (i = 0; i < XVECLEN (pat, 0); i++)
7960 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7961 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7962 0, i)))))
7963 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7964
7965 RTX_FRAME_RELATED_P (insn) = 1;
7966 }
7967 else if (last >= 6)
7968 {
7969 int start;
7970
7971 for (start = first >= 6 ? first : 6; start <= last; start++)
7972 if (!global_not_special_regno_p (start))
7973 break;
7974
7975 if (start > last)
7976 return insn;
7977
7978 addr = plus_constant (Pmode, base,
7979 offset + (start - first) * UNITS_PER_LONG);
7980 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7981 gen_rtx_REG (Pmode, start),
7982 GEN_INT (last - start + 1));
7983 note = PATTERN (note);
7984
7985 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7986
7987 for (i = 0; i < XVECLEN (note, 0); i++)
7988 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7989 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7990 0, i)))))
7991 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7992
7993 RTX_FRAME_RELATED_P (insn) = 1;
7994 }
7995
7996 return insn;
7997 }
7998
7999 /* Generate insn to restore registers FIRST to LAST from
8000 the register save area located at offset OFFSET
8001 relative to register BASE. */
8002
8003 static rtx
8004 restore_gprs (rtx base, int offset, int first, int last)
8005 {
8006 rtx addr, insn;
8007
8008 addr = plus_constant (Pmode, base, offset);
8009 addr = gen_rtx_MEM (Pmode, addr);
8010 set_mem_alias_set (addr, get_frame_alias_set ());
8011
8012 /* Special-case single register. */
8013 if (first == last)
8014 {
8015 if (TARGET_64BIT)
8016 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8017 else
8018 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8019
8020 return insn;
8021 }
8022
8023 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8024 addr,
8025 GEN_INT (last - first + 1));
8026 return insn;
8027 }
8028
8029 /* Return insn sequence to load the GOT register. */
8030
8031 static GTY(()) rtx got_symbol;
8032 rtx
8033 s390_load_got (void)
8034 {
8035 rtx insns;
8036
8037 /* We cannot use pic_offset_table_rtx here since we use this
8038 function also for non-pic if __tls_get_offset is called and in
8039 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8040 aren't usable. */
8041 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8042
8043 if (!got_symbol)
8044 {
8045 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8046 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8047 }
8048
8049 start_sequence ();
8050
8051 if (TARGET_CPU_ZARCH)
8052 {
8053 emit_move_insn (got_rtx, got_symbol);
8054 }
8055 else
8056 {
8057 rtx offset;
8058
8059 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
8060 UNSPEC_LTREL_OFFSET);
8061 offset = gen_rtx_CONST (Pmode, offset);
8062 offset = force_const_mem (Pmode, offset);
8063
8064 emit_move_insn (got_rtx, offset);
8065
8066 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
8067 UNSPEC_LTREL_BASE);
8068 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
8069
8070 emit_move_insn (got_rtx, offset);
8071 }
8072
8073 insns = get_insns ();
8074 end_sequence ();
8075 return insns;
8076 }
8077
8078 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8079 and the change to the stack pointer. */
8080
8081 static void
8082 s390_emit_stack_tie (void)
8083 {
8084 rtx mem = gen_frame_mem (BLKmode,
8085 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8086
8087 emit_insn (gen_stack_tie (mem));
8088 }
8089
8090 /* Expand the prologue into a bunch of separate insns. */
8091
8092 void
8093 s390_emit_prologue (void)
8094 {
8095 rtx insn, addr;
8096 rtx temp_reg;
8097 int i;
8098 int offset;
8099 int next_fpr = 0;
8100
8101 /* Complete frame layout. */
8102
8103 s390_update_frame_layout ();
8104
8105 /* Annotate all constant pool references to let the scheduler know
8106 they implicitly use the base register. */
8107
8108 push_topmost_sequence ();
8109
8110 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8111 if (INSN_P (insn))
8112 {
8113 annotate_constant_pool_refs (&PATTERN (insn));
8114 df_insn_rescan (insn);
8115 }
8116
8117 pop_topmost_sequence ();
8118
8119 /* Choose best register to use for temp use within prologue.
8120 See below for why TPF must use the register 1. */
8121
8122 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8123 && !crtl->is_leaf
8124 && !TARGET_TPF_PROFILING)
8125 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8126 else
8127 temp_reg = gen_rtx_REG (Pmode, 1);
8128
8129 /* Save call saved gprs. */
8130 if (cfun_frame_layout.first_save_gpr != -1)
8131 {
8132 insn = save_gprs (stack_pointer_rtx,
8133 cfun_frame_layout.gprs_offset +
8134 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8135 - cfun_frame_layout.first_save_gpr_slot),
8136 cfun_frame_layout.first_save_gpr,
8137 cfun_frame_layout.last_save_gpr);
8138 emit_insn (insn);
8139 }
8140
8141 /* Dummy insn to mark literal pool slot. */
8142
8143 if (cfun->machine->base_reg)
8144 emit_insn (gen_main_pool (cfun->machine->base_reg));
8145
8146 offset = cfun_frame_layout.f0_offset;
8147
8148 /* Save f0 and f2. */
8149 for (i = 0; i < 2; i++)
8150 {
8151 if (cfun_fpr_bit_p (i))
8152 {
8153 save_fpr (stack_pointer_rtx, offset, i + 16);
8154 offset += 8;
8155 }
8156 else if (!TARGET_PACKED_STACK)
8157 offset += 8;
8158 }
8159
8160 /* Save f4 and f6. */
8161 offset = cfun_frame_layout.f4_offset;
8162 for (i = 2; i < 4; i++)
8163 {
8164 if (cfun_fpr_bit_p (i))
8165 {
8166 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8167 offset += 8;
8168
8169 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8170 therefore are not frame related. */
8171 if (!call_really_used_regs[i + 16])
8172 RTX_FRAME_RELATED_P (insn) = 1;
8173 }
8174 else if (!TARGET_PACKED_STACK)
8175 offset += 8;
8176 }
8177
8178 if (TARGET_PACKED_STACK
8179 && cfun_save_high_fprs_p
8180 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8181 {
8182 offset = (cfun_frame_layout.f8_offset
8183 + (cfun_frame_layout.high_fprs - 1) * 8);
8184
8185 for (i = 15; i > 7 && offset >= 0; i--)
8186 if (cfun_fpr_bit_p (i))
8187 {
8188 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8189
8190 RTX_FRAME_RELATED_P (insn) = 1;
8191 offset -= 8;
8192 }
8193 if (offset >= cfun_frame_layout.f8_offset)
8194 next_fpr = i + 16;
8195 }
8196
8197 if (!TARGET_PACKED_STACK)
8198 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8199
8200 if (flag_stack_usage_info)
8201 current_function_static_stack_size = cfun_frame_layout.frame_size;
8202
8203 /* Decrement stack pointer. */
8204
8205 if (cfun_frame_layout.frame_size > 0)
8206 {
8207 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8208 rtx real_frame_off;
8209
8210 if (s390_stack_size)
8211 {
8212 HOST_WIDE_INT stack_guard;
8213
8214 if (s390_stack_guard)
8215 stack_guard = s390_stack_guard;
8216 else
8217 {
8218 /* If no value for stack guard is provided the smallest power of 2
8219 larger than the current frame size is chosen. */
8220 stack_guard = 1;
8221 while (stack_guard < cfun_frame_layout.frame_size)
8222 stack_guard <<= 1;
8223 }
8224
8225 if (cfun_frame_layout.frame_size >= s390_stack_size)
8226 {
8227 warning (0, "frame size of function %qs is %wd"
8228 " bytes exceeding user provided stack limit of "
8229 "%d bytes. "
8230 "An unconditional trap is added.",
8231 current_function_name(), cfun_frame_layout.frame_size,
8232 s390_stack_size);
8233 emit_insn (gen_trap ());
8234 }
8235 else
8236 {
8237 /* stack_guard has to be smaller than s390_stack_size.
8238 Otherwise we would emit an AND with zero which would
8239 not match the test under mask pattern. */
8240 if (stack_guard >= s390_stack_size)
8241 {
8242 warning (0, "frame size of function %qs is %wd"
8243 " bytes which is more than half the stack size. "
8244 "The dynamic check would not be reliable. "
8245 "No check emitted for this function.",
8246 current_function_name(),
8247 cfun_frame_layout.frame_size);
8248 }
8249 else
8250 {
8251 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8252 & ~(stack_guard - 1));
8253
8254 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8255 GEN_INT (stack_check_mask));
8256 if (TARGET_64BIT)
8257 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8258 t, const0_rtx),
8259 t, const0_rtx, const0_rtx));
8260 else
8261 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8262 t, const0_rtx),
8263 t, const0_rtx, const0_rtx));
8264 }
8265 }
8266 }
8267
8268 if (s390_warn_framesize > 0
8269 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8270 warning (0, "frame size of %qs is %wd bytes",
8271 current_function_name (), cfun_frame_layout.frame_size);
8272
8273 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8274 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8275
8276 /* Save incoming stack pointer into temp reg. */
8277 if (TARGET_BACKCHAIN || next_fpr)
8278 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8279
8280 /* Subtract frame size from stack pointer. */
8281
8282 if (DISP_IN_RANGE (INTVAL (frame_off)))
8283 {
8284 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8285 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8286 frame_off));
8287 insn = emit_insn (insn);
8288 }
8289 else
8290 {
8291 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8292 frame_off = force_const_mem (Pmode, frame_off);
8293
8294 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8295 annotate_constant_pool_refs (&PATTERN (insn));
8296 }
8297
8298 RTX_FRAME_RELATED_P (insn) = 1;
8299 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8300 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8301 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8302 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8303 real_frame_off)));
8304
8305 /* Set backchain. */
8306
8307 if (TARGET_BACKCHAIN)
8308 {
8309 if (cfun_frame_layout.backchain_offset)
8310 addr = gen_rtx_MEM (Pmode,
8311 plus_constant (Pmode, stack_pointer_rtx,
8312 cfun_frame_layout.backchain_offset));
8313 else
8314 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8315 set_mem_alias_set (addr, get_frame_alias_set ());
8316 insn = emit_insn (gen_move_insn (addr, temp_reg));
8317 }
8318
8319 /* If we support non-call exceptions (e.g. for Java),
8320 we need to make sure the backchain pointer is set up
8321 before any possibly trapping memory access. */
8322 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8323 {
8324 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8325 emit_clobber (addr);
8326 }
8327 }
8328
8329 /* Save fprs 8 - 15 (64 bit ABI). */
8330
8331 if (cfun_save_high_fprs_p && next_fpr)
8332 {
8333 /* If the stack might be accessed through a different register
8334 we have to make sure that the stack pointer decrement is not
8335 moved below the use of the stack slots. */
8336 s390_emit_stack_tie ();
8337
8338 insn = emit_insn (gen_add2_insn (temp_reg,
8339 GEN_INT (cfun_frame_layout.f8_offset)));
8340
8341 offset = 0;
8342
8343 for (i = 24; i <= next_fpr; i++)
8344 if (cfun_fpr_bit_p (i - 16))
8345 {
8346 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8347 cfun_frame_layout.frame_size
8348 + cfun_frame_layout.f8_offset
8349 + offset);
8350
8351 insn = save_fpr (temp_reg, offset, i);
8352 offset += 8;
8353 RTX_FRAME_RELATED_P (insn) = 1;
8354 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8355 gen_rtx_SET (VOIDmode,
8356 gen_rtx_MEM (DFmode, addr),
8357 gen_rtx_REG (DFmode, i)));
8358 }
8359 }
8360
8361 /* Set frame pointer, if needed. */
8362
8363 if (frame_pointer_needed)
8364 {
8365 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8366 RTX_FRAME_RELATED_P (insn) = 1;
8367 }
8368
8369 /* Set up got pointer, if needed. */
8370
8371 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8372 {
8373 rtx insns = s390_load_got ();
8374
8375 for (insn = insns; insn; insn = NEXT_INSN (insn))
8376 annotate_constant_pool_refs (&PATTERN (insn));
8377
8378 emit_insn (insns);
8379 }
8380
8381 if (TARGET_TPF_PROFILING)
8382 {
8383 /* Generate a BAS instruction to serve as a function
8384 entry intercept to facilitate the use of tracing
8385 algorithms located at the branch target. */
8386 emit_insn (gen_prologue_tpf ());
8387
8388 /* Emit a blockage here so that all code
8389 lies between the profiling mechanisms. */
8390 emit_insn (gen_blockage ());
8391 }
8392 }
8393
8394 /* Expand the epilogue into a bunch of separate insns. */
8395
8396 void
8397 s390_emit_epilogue (bool sibcall)
8398 {
8399 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8400 int area_bottom, area_top, offset = 0;
8401 int next_offset;
8402 rtvec p;
8403 int i;
8404
8405 if (TARGET_TPF_PROFILING)
8406 {
8407
8408 /* Generate a BAS instruction to serve as a function
8409 entry intercept to facilitate the use of tracing
8410 algorithms located at the branch target. */
8411
8412 /* Emit a blockage here so that all code
8413 lies between the profiling mechanisms. */
8414 emit_insn (gen_blockage ());
8415
8416 emit_insn (gen_epilogue_tpf ());
8417 }
8418
8419 /* Check whether to use frame or stack pointer for restore. */
8420
8421 frame_pointer = (frame_pointer_needed
8422 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8423
8424 s390_frame_area (&area_bottom, &area_top);
8425
8426 /* Check whether we can access the register save area.
8427 If not, increment the frame pointer as required. */
8428
8429 if (area_top <= area_bottom)
8430 {
8431 /* Nothing to restore. */
8432 }
8433 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8434 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8435 {
8436 /* Area is in range. */
8437 offset = cfun_frame_layout.frame_size;
8438 }
8439 else
8440 {
8441 rtx insn, frame_off, cfa;
8442
8443 offset = area_bottom < 0 ? -area_bottom : 0;
8444 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8445
8446 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8447 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8448 if (DISP_IN_RANGE (INTVAL (frame_off)))
8449 {
8450 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8451 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8452 insn = emit_insn (insn);
8453 }
8454 else
8455 {
8456 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8457 frame_off = force_const_mem (Pmode, frame_off);
8458
8459 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8460 annotate_constant_pool_refs (&PATTERN (insn));
8461 }
8462 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8463 RTX_FRAME_RELATED_P (insn) = 1;
8464 }
8465
8466 /* Restore call saved fprs. */
8467
8468 if (TARGET_64BIT)
8469 {
8470 if (cfun_save_high_fprs_p)
8471 {
8472 next_offset = cfun_frame_layout.f8_offset;
8473 for (i = 24; i < 32; i++)
8474 {
8475 if (cfun_fpr_bit_p (i - 16))
8476 {
8477 restore_fpr (frame_pointer,
8478 offset + next_offset, i);
8479 cfa_restores
8480 = alloc_reg_note (REG_CFA_RESTORE,
8481 gen_rtx_REG (DFmode, i), cfa_restores);
8482 next_offset += 8;
8483 }
8484 }
8485 }
8486
8487 }
8488 else
8489 {
8490 next_offset = cfun_frame_layout.f4_offset;
8491 for (i = 18; i < 20; i++)
8492 {
8493 if (cfun_fpr_bit_p (i - 16))
8494 {
8495 restore_fpr (frame_pointer,
8496 offset + next_offset, i);
8497 cfa_restores
8498 = alloc_reg_note (REG_CFA_RESTORE,
8499 gen_rtx_REG (DFmode, i), cfa_restores);
8500 next_offset += 8;
8501 }
8502 else if (!TARGET_PACKED_STACK)
8503 next_offset += 8;
8504 }
8505
8506 }
8507
8508 /* Return register. */
8509
8510 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8511
8512 /* Restore call saved gprs. */
8513
8514 if (cfun_frame_layout.first_restore_gpr != -1)
8515 {
8516 rtx insn, addr;
8517 int i;
8518
8519 /* Check for global register and save them
8520 to stack location from where they get restored. */
8521
8522 for (i = cfun_frame_layout.first_restore_gpr;
8523 i <= cfun_frame_layout.last_restore_gpr;
8524 i++)
8525 {
8526 if (global_not_special_regno_p (i))
8527 {
8528 addr = plus_constant (Pmode, frame_pointer,
8529 offset + cfun_frame_layout.gprs_offset
8530 + (i - cfun_frame_layout.first_save_gpr_slot)
8531 * UNITS_PER_LONG);
8532 addr = gen_rtx_MEM (Pmode, addr);
8533 set_mem_alias_set (addr, get_frame_alias_set ());
8534 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8535 }
8536 else
8537 cfa_restores
8538 = alloc_reg_note (REG_CFA_RESTORE,
8539 gen_rtx_REG (Pmode, i), cfa_restores);
8540 }
8541
8542 if (! sibcall)
8543 {
8544 /* Fetch return address from stack before load multiple,
8545 this will do good for scheduling. */
8546
8547 if (cfun_frame_layout.save_return_addr_p
8548 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8549 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8550 {
8551 int return_regnum = find_unused_clobbered_reg();
8552 if (!return_regnum)
8553 return_regnum = 4;
8554 return_reg = gen_rtx_REG (Pmode, return_regnum);
8555
8556 addr = plus_constant (Pmode, frame_pointer,
8557 offset + cfun_frame_layout.gprs_offset
8558 + (RETURN_REGNUM
8559 - cfun_frame_layout.first_save_gpr_slot)
8560 * UNITS_PER_LONG);
8561 addr = gen_rtx_MEM (Pmode, addr);
8562 set_mem_alias_set (addr, get_frame_alias_set ());
8563 emit_move_insn (return_reg, addr);
8564 }
8565 }
8566
8567 insn = restore_gprs (frame_pointer,
8568 offset + cfun_frame_layout.gprs_offset
8569 + (cfun_frame_layout.first_restore_gpr
8570 - cfun_frame_layout.first_save_gpr_slot)
8571 * UNITS_PER_LONG,
8572 cfun_frame_layout.first_restore_gpr,
8573 cfun_frame_layout.last_restore_gpr);
8574 insn = emit_insn (insn);
8575 REG_NOTES (insn) = cfa_restores;
8576 add_reg_note (insn, REG_CFA_DEF_CFA,
8577 plus_constant (Pmode, stack_pointer_rtx,
8578 STACK_POINTER_OFFSET));
8579 RTX_FRAME_RELATED_P (insn) = 1;
8580 }
8581
8582 if (! sibcall)
8583 {
8584
8585 /* Return to caller. */
8586
8587 p = rtvec_alloc (2);
8588
8589 RTVEC_ELT (p, 0) = ret_rtx;
8590 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8591 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8592 }
8593 }
8594
8595
8596 /* Return the size in bytes of a function argument of
8597 type TYPE and/or mode MODE. At least one of TYPE or
8598 MODE must be specified. */
8599
8600 static int
8601 s390_function_arg_size (enum machine_mode mode, const_tree type)
8602 {
8603 if (type)
8604 return int_size_in_bytes (type);
8605
8606 /* No type info available for some library calls ... */
8607 if (mode != BLKmode)
8608 return GET_MODE_SIZE (mode);
8609
8610 /* If we have neither type nor mode, abort */
8611 gcc_unreachable ();
8612 }
8613
8614 /* Return true if a function argument of type TYPE and mode MODE
8615 is to be passed in a floating-point register, if available. */
8616
8617 static bool
8618 s390_function_arg_float (enum machine_mode mode, const_tree type)
8619 {
8620 int size = s390_function_arg_size (mode, type);
8621 if (size > 8)
8622 return false;
8623
8624 /* Soft-float changes the ABI: no floating-point registers are used. */
8625 if (TARGET_SOFT_FLOAT)
8626 return false;
8627
8628 /* No type info available for some library calls ... */
8629 if (!type)
8630 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8631
8632 /* The ABI says that record types with a single member are treated
8633 just like that member would be. */
8634 while (TREE_CODE (type) == RECORD_TYPE)
8635 {
8636 tree field, single = NULL_TREE;
8637
8638 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8639 {
8640 if (TREE_CODE (field) != FIELD_DECL)
8641 continue;
8642
8643 if (single == NULL_TREE)
8644 single = TREE_TYPE (field);
8645 else
8646 return false;
8647 }
8648
8649 if (single == NULL_TREE)
8650 return false;
8651 else
8652 type = single;
8653 }
8654
8655 return TREE_CODE (type) == REAL_TYPE;
8656 }
8657
8658 /* Return true if a function argument of type TYPE and mode MODE
8659 is to be passed in an integer register, or a pair of integer
8660 registers, if available. */
8661
8662 static bool
8663 s390_function_arg_integer (enum machine_mode mode, const_tree type)
8664 {
8665 int size = s390_function_arg_size (mode, type);
8666 if (size > 8)
8667 return false;
8668
8669 /* No type info available for some library calls ... */
8670 if (!type)
8671 return GET_MODE_CLASS (mode) == MODE_INT
8672 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8673
8674 /* We accept small integral (and similar) types. */
8675 if (INTEGRAL_TYPE_P (type)
8676 || POINTER_TYPE_P (type)
8677 || TREE_CODE (type) == NULLPTR_TYPE
8678 || TREE_CODE (type) == OFFSET_TYPE
8679 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8680 return true;
8681
8682 /* We also accept structs of size 1, 2, 4, 8 that are not
8683 passed in floating-point registers. */
8684 if (AGGREGATE_TYPE_P (type)
8685 && exact_log2 (size) >= 0
8686 && !s390_function_arg_float (mode, type))
8687 return true;
8688
8689 return false;
8690 }
8691
8692 /* Return 1 if a function argument of type TYPE and mode MODE
8693 is to be passed by reference. The ABI specifies that only
8694 structures of size 1, 2, 4, or 8 bytes are passed by value,
8695 all other structures (and complex numbers) are passed by
8696 reference. */
8697
8698 static bool
8699 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8700 enum machine_mode mode, const_tree type,
8701 bool named ATTRIBUTE_UNUSED)
8702 {
8703 int size = s390_function_arg_size (mode, type);
8704 if (size > 8)
8705 return true;
8706
8707 if (type)
8708 {
8709 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8710 return 1;
8711
8712 if (TREE_CODE (type) == COMPLEX_TYPE
8713 || TREE_CODE (type) == VECTOR_TYPE)
8714 return 1;
8715 }
8716
8717 return 0;
8718 }
8719
8720 /* Update the data in CUM to advance over an argument of mode MODE and
8721 data type TYPE. (TYPE is null for libcalls where that information
8722 may not be available.). The boolean NAMED specifies whether the
8723 argument is a named argument (as opposed to an unnamed argument
8724 matching an ellipsis). */
8725
8726 static void
8727 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8728 const_tree type, bool named ATTRIBUTE_UNUSED)
8729 {
8730 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8731
8732 if (s390_function_arg_float (mode, type))
8733 {
8734 cum->fprs += 1;
8735 }
8736 else if (s390_function_arg_integer (mode, type))
8737 {
8738 int size = s390_function_arg_size (mode, type);
8739 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8740 }
8741 else
8742 gcc_unreachable ();
8743 }
8744
8745 /* Define where to put the arguments to a function.
8746 Value is zero to push the argument on the stack,
8747 or a hard register in which to store the argument.
8748
8749 MODE is the argument's machine mode.
8750 TYPE is the data type of the argument (as a tree).
8751 This is null for libcalls where that information may
8752 not be available.
8753 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8754 the preceding args and about the function being called.
8755 NAMED is nonzero if this argument is a named parameter
8756 (otherwise it is an extra parameter matching an ellipsis).
8757
8758 On S/390, we use general purpose registers 2 through 6 to
8759 pass integer, pointer, and certain structure arguments, and
8760 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8761 to pass floating point arguments. All remaining arguments
8762 are pushed to the stack. */
8763
8764 static rtx
8765 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8766 const_tree type, bool named ATTRIBUTE_UNUSED)
8767 {
8768 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8769
8770 if (s390_function_arg_float (mode, type))
8771 {
8772 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8773 return 0;
8774 else
8775 return gen_rtx_REG (mode, cum->fprs + 16);
8776 }
8777 else if (s390_function_arg_integer (mode, type))
8778 {
8779 int size = s390_function_arg_size (mode, type);
8780 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8781
8782 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8783 return 0;
8784 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8785 return gen_rtx_REG (mode, cum->gprs + 2);
8786 else if (n_gprs == 2)
8787 {
8788 rtvec p = rtvec_alloc (2);
8789
8790 RTVEC_ELT (p, 0)
8791 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8792 const0_rtx);
8793 RTVEC_ELT (p, 1)
8794 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8795 GEN_INT (4));
8796
8797 return gen_rtx_PARALLEL (mode, p);
8798 }
8799 }
8800
8801 /* After the real arguments, expand_call calls us once again
8802 with a void_type_node type. Whatever we return here is
8803 passed as operand 2 to the call expanders.
8804
8805 We don't need this feature ... */
8806 else if (type == void_type_node)
8807 return const0_rtx;
8808
8809 gcc_unreachable ();
8810 }
8811
8812 /* Return true if return values of type TYPE should be returned
8813 in a memory buffer whose address is passed by the caller as
8814 hidden first argument. */
8815
8816 static bool
8817 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8818 {
8819 /* We accept small integral (and similar) types. */
8820 if (INTEGRAL_TYPE_P (type)
8821 || POINTER_TYPE_P (type)
8822 || TREE_CODE (type) == OFFSET_TYPE
8823 || TREE_CODE (type) == REAL_TYPE)
8824 return int_size_in_bytes (type) > 8;
8825
8826 /* Aggregates and similar constructs are always returned
8827 in memory. */
8828 if (AGGREGATE_TYPE_P (type)
8829 || TREE_CODE (type) == COMPLEX_TYPE
8830 || TREE_CODE (type) == VECTOR_TYPE)
8831 return true;
8832
8833 /* ??? We get called on all sorts of random stuff from
8834 aggregate_value_p. We can't abort, but it's not clear
8835 what's safe to return. Pretend it's a struct I guess. */
8836 return true;
8837 }
8838
8839 /* Function arguments and return values are promoted to word size. */
8840
8841 static enum machine_mode
8842 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8843 int *punsignedp,
8844 const_tree fntype ATTRIBUTE_UNUSED,
8845 int for_return ATTRIBUTE_UNUSED)
8846 {
8847 if (INTEGRAL_MODE_P (mode)
8848 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8849 {
8850 if (type != NULL_TREE && POINTER_TYPE_P (type))
8851 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8852 return Pmode;
8853 }
8854
8855 return mode;
8856 }
8857
8858 /* Define where to return a (scalar) value of type RET_TYPE.
8859 If RET_TYPE is null, define where to return a (scalar)
8860 value of mode MODE from a libcall. */
8861
8862 static rtx
8863 s390_function_and_libcall_value (enum machine_mode mode,
8864 const_tree ret_type,
8865 const_tree fntype_or_decl,
8866 bool outgoing ATTRIBUTE_UNUSED)
8867 {
8868 /* For normal functions perform the promotion as
8869 promote_function_mode would do. */
8870 if (ret_type)
8871 {
8872 int unsignedp = TYPE_UNSIGNED (ret_type);
8873 mode = promote_function_mode (ret_type, mode, &unsignedp,
8874 fntype_or_decl, 1);
8875 }
8876
8877 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8878 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8879
8880 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8881 return gen_rtx_REG (mode, 16);
8882 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8883 || UNITS_PER_LONG == UNITS_PER_WORD)
8884 return gen_rtx_REG (mode, 2);
8885 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8886 {
8887 /* This case is triggered when returning a 64 bit value with
8888 -m31 -mzarch. Although the value would fit into a single
8889 register it has to be forced into a 32 bit register pair in
8890 order to match the ABI. */
8891 rtvec p = rtvec_alloc (2);
8892
8893 RTVEC_ELT (p, 0)
8894 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8895 RTVEC_ELT (p, 1)
8896 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8897
8898 return gen_rtx_PARALLEL (mode, p);
8899 }
8900
8901 gcc_unreachable ();
8902 }
8903
8904 /* Define where to return a scalar return value of type RET_TYPE. */
8905
8906 static rtx
8907 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8908 bool outgoing)
8909 {
8910 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8911 fn_decl_or_type, outgoing);
8912 }
8913
8914 /* Define where to return a scalar libcall return value of mode
8915 MODE. */
8916
8917 static rtx
8918 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8919 {
8920 return s390_function_and_libcall_value (mode, NULL_TREE,
8921 NULL_TREE, true);
8922 }
8923
8924
8925 /* Create and return the va_list datatype.
8926
8927 On S/390, va_list is an array type equivalent to
8928
8929 typedef struct __va_list_tag
8930 {
8931 long __gpr;
8932 long __fpr;
8933 void *__overflow_arg_area;
8934 void *__reg_save_area;
8935 } va_list[1];
8936
8937 where __gpr and __fpr hold the number of general purpose
8938 or floating point arguments used up to now, respectively,
8939 __overflow_arg_area points to the stack location of the
8940 next argument passed on the stack, and __reg_save_area
8941 always points to the start of the register area in the
8942 call frame of the current function. The function prologue
8943 saves all registers used for argument passing into this
8944 area if the function uses variable arguments. */
8945
8946 static tree
8947 s390_build_builtin_va_list (void)
8948 {
8949 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8950
8951 record = lang_hooks.types.make_type (RECORD_TYPE);
8952
8953 type_decl =
8954 build_decl (BUILTINS_LOCATION,
8955 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8956
8957 f_gpr = build_decl (BUILTINS_LOCATION,
8958 FIELD_DECL, get_identifier ("__gpr"),
8959 long_integer_type_node);
8960 f_fpr = build_decl (BUILTINS_LOCATION,
8961 FIELD_DECL, get_identifier ("__fpr"),
8962 long_integer_type_node);
8963 f_ovf = build_decl (BUILTINS_LOCATION,
8964 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8965 ptr_type_node);
8966 f_sav = build_decl (BUILTINS_LOCATION,
8967 FIELD_DECL, get_identifier ("__reg_save_area"),
8968 ptr_type_node);
8969
8970 va_list_gpr_counter_field = f_gpr;
8971 va_list_fpr_counter_field = f_fpr;
8972
8973 DECL_FIELD_CONTEXT (f_gpr) = record;
8974 DECL_FIELD_CONTEXT (f_fpr) = record;
8975 DECL_FIELD_CONTEXT (f_ovf) = record;
8976 DECL_FIELD_CONTEXT (f_sav) = record;
8977
8978 TYPE_STUB_DECL (record) = type_decl;
8979 TYPE_NAME (record) = type_decl;
8980 TYPE_FIELDS (record) = f_gpr;
8981 DECL_CHAIN (f_gpr) = f_fpr;
8982 DECL_CHAIN (f_fpr) = f_ovf;
8983 DECL_CHAIN (f_ovf) = f_sav;
8984
8985 layout_type (record);
8986
8987 /* The correct type is an array type of one element. */
8988 return build_array_type (record, build_index_type (size_zero_node));
8989 }
8990
8991 /* Implement va_start by filling the va_list structure VALIST.
8992 STDARG_P is always true, and ignored.
8993 NEXTARG points to the first anonymous stack argument.
8994
8995 The following global variables are used to initialize
8996 the va_list structure:
8997
8998 crtl->args.info:
8999 holds number of gprs and fprs used for named arguments.
9000 crtl->args.arg_offset_rtx:
9001 holds the offset of the first anonymous stack argument
9002 (relative to the virtual arg pointer). */
9003
9004 static void
9005 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9006 {
9007 HOST_WIDE_INT n_gpr, n_fpr;
9008 int off;
9009 tree f_gpr, f_fpr, f_ovf, f_sav;
9010 tree gpr, fpr, ovf, sav, t;
9011
9012 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9013 f_fpr = DECL_CHAIN (f_gpr);
9014 f_ovf = DECL_CHAIN (f_fpr);
9015 f_sav = DECL_CHAIN (f_ovf);
9016
9017 valist = build_simple_mem_ref (valist);
9018 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9019 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9020 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9021 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9022
9023 /* Count number of gp and fp argument registers used. */
9024
9025 n_gpr = crtl->args.info.gprs;
9026 n_fpr = crtl->args.info.fprs;
9027
9028 if (cfun->va_list_gpr_size)
9029 {
9030 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9031 build_int_cst (NULL_TREE, n_gpr));
9032 TREE_SIDE_EFFECTS (t) = 1;
9033 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9034 }
9035
9036 if (cfun->va_list_fpr_size)
9037 {
9038 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9039 build_int_cst (NULL_TREE, n_fpr));
9040 TREE_SIDE_EFFECTS (t) = 1;
9041 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9042 }
9043
9044 /* Find the overflow area. */
9045 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9046 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9047 {
9048 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9049
9050 off = INTVAL (crtl->args.arg_offset_rtx);
9051 off = off < 0 ? 0 : off;
9052 if (TARGET_DEBUG_ARG)
9053 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9054 (int)n_gpr, (int)n_fpr, off);
9055
9056 t = fold_build_pointer_plus_hwi (t, off);
9057
9058 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9059 TREE_SIDE_EFFECTS (t) = 1;
9060 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9061 }
9062
9063 /* Find the register save area. */
9064 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9065 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9066 {
9067 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
9068 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
9069
9070 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9071 TREE_SIDE_EFFECTS (t) = 1;
9072 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9073 }
9074 }
9075
9076 /* Implement va_arg by updating the va_list structure
9077 VALIST as required to retrieve an argument of type
9078 TYPE, and returning that argument.
9079
9080 Generates code equivalent to:
9081
9082 if (integral value) {
9083 if (size <= 4 && args.gpr < 5 ||
9084 size > 4 && args.gpr < 4 )
9085 ret = args.reg_save_area[args.gpr+8]
9086 else
9087 ret = *args.overflow_arg_area++;
9088 } else if (float value) {
9089 if (args.fgpr < 2)
9090 ret = args.reg_save_area[args.fpr+64]
9091 else
9092 ret = *args.overflow_arg_area++;
9093 } else if (aggregate value) {
9094 if (args.gpr < 5)
9095 ret = *args.reg_save_area[args.gpr]
9096 else
9097 ret = **args.overflow_arg_area++;
9098 } */
9099
9100 static tree
9101 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9102 gimple_seq *post_p ATTRIBUTE_UNUSED)
9103 {
9104 tree f_gpr, f_fpr, f_ovf, f_sav;
9105 tree gpr, fpr, ovf, sav, reg, t, u;
9106 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
9107 tree lab_false, lab_over, addr;
9108
9109 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9110 f_fpr = DECL_CHAIN (f_gpr);
9111 f_ovf = DECL_CHAIN (f_fpr);
9112 f_sav = DECL_CHAIN (f_ovf);
9113
9114 valist = build_va_arg_indirect_ref (valist);
9115 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9116 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9117 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9118
9119 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9120 both appear on a lhs. */
9121 valist = unshare_expr (valist);
9122 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9123
9124 size = int_size_in_bytes (type);
9125
9126 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9127 {
9128 if (TARGET_DEBUG_ARG)
9129 {
9130 fprintf (stderr, "va_arg: aggregate type");
9131 debug_tree (type);
9132 }
9133
9134 /* Aggregates are passed by reference. */
9135 indirect_p = 1;
9136 reg = gpr;
9137 n_reg = 1;
9138
9139 /* kernel stack layout on 31 bit: It is assumed here that no padding
9140 will be added by s390_frame_info because for va_args always an even
9141 number of gprs has to be saved r15-r2 = 14 regs. */
9142 sav_ofs = 2 * UNITS_PER_LONG;
9143 sav_scale = UNITS_PER_LONG;
9144 size = UNITS_PER_LONG;
9145 max_reg = GP_ARG_NUM_REG - n_reg;
9146 }
9147 else if (s390_function_arg_float (TYPE_MODE (type), type))
9148 {
9149 if (TARGET_DEBUG_ARG)
9150 {
9151 fprintf (stderr, "va_arg: float type");
9152 debug_tree (type);
9153 }
9154
9155 /* FP args go in FP registers, if present. */
9156 indirect_p = 0;
9157 reg = fpr;
9158 n_reg = 1;
9159 sav_ofs = 16 * UNITS_PER_LONG;
9160 sav_scale = 8;
9161 max_reg = FP_ARG_NUM_REG - n_reg;
9162 }
9163 else
9164 {
9165 if (TARGET_DEBUG_ARG)
9166 {
9167 fprintf (stderr, "va_arg: other type");
9168 debug_tree (type);
9169 }
9170
9171 /* Otherwise into GP registers. */
9172 indirect_p = 0;
9173 reg = gpr;
9174 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9175
9176 /* kernel stack layout on 31 bit: It is assumed here that no padding
9177 will be added by s390_frame_info because for va_args always an even
9178 number of gprs has to be saved r15-r2 = 14 regs. */
9179 sav_ofs = 2 * UNITS_PER_LONG;
9180
9181 if (size < UNITS_PER_LONG)
9182 sav_ofs += UNITS_PER_LONG - size;
9183
9184 sav_scale = UNITS_PER_LONG;
9185 max_reg = GP_ARG_NUM_REG - n_reg;
9186 }
9187
9188 /* Pull the value out of the saved registers ... */
9189
9190 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9191 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9192 addr = create_tmp_var (ptr_type_node, "addr");
9193
9194 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9195 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9196 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9197 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9198 gimplify_and_add (t, pre_p);
9199
9200 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9201 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9202 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9203 t = fold_build_pointer_plus (t, u);
9204
9205 gimplify_assign (addr, t, pre_p);
9206
9207 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9208
9209 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9210
9211
9212 /* ... Otherwise out of the overflow area. */
9213
9214 t = ovf;
9215 if (size < UNITS_PER_LONG)
9216 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9217
9218 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9219
9220 gimplify_assign (addr, t, pre_p);
9221
9222 t = fold_build_pointer_plus_hwi (t, size);
9223 gimplify_assign (ovf, t, pre_p);
9224
9225 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9226
9227
9228 /* Increment register save count. */
9229
9230 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9231 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9232 gimplify_and_add (u, pre_p);
9233
9234 if (indirect_p)
9235 {
9236 t = build_pointer_type_for_mode (build_pointer_type (type),
9237 ptr_mode, true);
9238 addr = fold_convert (t, addr);
9239 addr = build_va_arg_indirect_ref (addr);
9240 }
9241 else
9242 {
9243 t = build_pointer_type_for_mode (type, ptr_mode, true);
9244 addr = fold_convert (t, addr);
9245 }
9246
9247 return build_va_arg_indirect_ref (addr);
9248 }
9249
9250
9251 /* Builtins. */
9252
9253 enum s390_builtin
9254 {
9255 S390_BUILTIN_THREAD_POINTER,
9256 S390_BUILTIN_SET_THREAD_POINTER,
9257
9258 S390_BUILTIN_max
9259 };
9260
9261 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9262 CODE_FOR_get_tp_64,
9263 CODE_FOR_set_tp_64
9264 };
9265
9266 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9267 CODE_FOR_get_tp_31,
9268 CODE_FOR_set_tp_31
9269 };
9270
9271 static void
9272 s390_init_builtins (void)
9273 {
9274 tree ftype;
9275
9276 ftype = build_function_type_list (ptr_type_node, NULL_TREE);
9277 add_builtin_function ("__builtin_thread_pointer", ftype,
9278 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9279 NULL, NULL_TREE);
9280
9281 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9282 add_builtin_function ("__builtin_set_thread_pointer", ftype,
9283 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9284 NULL, NULL_TREE);
9285 }
9286
9287 /* Expand an expression EXP that calls a built-in function,
9288 with result going to TARGET if that's convenient
9289 (and in mode MODE if that's convenient).
9290 SUBTARGET may be used as the target for computing one of EXP's operands.
9291 IGNORE is nonzero if the value is to be ignored. */
9292
9293 static rtx
9294 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9295 enum machine_mode mode ATTRIBUTE_UNUSED,
9296 int ignore ATTRIBUTE_UNUSED)
9297 {
9298 #define MAX_ARGS 2
9299
9300 enum insn_code const *code_for_builtin =
9301 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9302
9303 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9304 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9305 enum insn_code icode;
9306 rtx op[MAX_ARGS], pat;
9307 int arity;
9308 bool nonvoid;
9309 tree arg;
9310 call_expr_arg_iterator iter;
9311
9312 if (fcode >= S390_BUILTIN_max)
9313 internal_error ("bad builtin fcode");
9314 icode = code_for_builtin[fcode];
9315 if (icode == 0)
9316 internal_error ("bad builtin fcode");
9317
9318 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9319
9320 arity = 0;
9321 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9322 {
9323 const struct insn_operand_data *insn_op;
9324
9325 if (arg == error_mark_node)
9326 return NULL_RTX;
9327 if (arity > MAX_ARGS)
9328 return NULL_RTX;
9329
9330 insn_op = &insn_data[icode].operand[arity + nonvoid];
9331
9332 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9333
9334 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9335 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9336 arity++;
9337 }
9338
9339 if (nonvoid)
9340 {
9341 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9342 if (!target
9343 || GET_MODE (target) != tmode
9344 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9345 target = gen_reg_rtx (tmode);
9346 }
9347
9348 switch (arity)
9349 {
9350 case 0:
9351 pat = GEN_FCN (icode) (target);
9352 break;
9353 case 1:
9354 if (nonvoid)
9355 pat = GEN_FCN (icode) (target, op[0]);
9356 else
9357 pat = GEN_FCN (icode) (op[0]);
9358 break;
9359 case 2:
9360 pat = GEN_FCN (icode) (target, op[0], op[1]);
9361 break;
9362 default:
9363 gcc_unreachable ();
9364 }
9365 if (!pat)
9366 return NULL_RTX;
9367 emit_insn (pat);
9368
9369 if (nonvoid)
9370 return target;
9371 else
9372 return const0_rtx;
9373 }
9374
9375
9376 /* Output assembly code for the trampoline template to
9377 stdio stream FILE.
9378
9379 On S/390, we use gpr 1 internally in the trampoline code;
9380 gpr 0 is used to hold the static chain. */
9381
9382 static void
9383 s390_asm_trampoline_template (FILE *file)
9384 {
9385 rtx op[2];
9386 op[0] = gen_rtx_REG (Pmode, 0);
9387 op[1] = gen_rtx_REG (Pmode, 1);
9388
9389 if (TARGET_64BIT)
9390 {
9391 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9392 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
9393 output_asm_insn ("br\t%1", op); /* 2 byte */
9394 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9395 }
9396 else
9397 {
9398 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
9399 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
9400 output_asm_insn ("br\t%1", op); /* 2 byte */
9401 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9402 }
9403 }
9404
9405 /* Emit RTL insns to initialize the variable parts of a trampoline.
9406 FNADDR is an RTX for the address of the function's pure code.
9407 CXT is an RTX for the static chain value for the function. */
9408
9409 static void
9410 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9411 {
9412 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9413 rtx mem;
9414
9415 emit_block_move (m_tramp, assemble_trampoline_template (),
9416 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9417
9418 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9419 emit_move_insn (mem, cxt);
9420 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9421 emit_move_insn (mem, fnaddr);
9422 }
9423
9424 /* Output assembler code to FILE to increment profiler label # LABELNO
9425 for profiling a function entry. */
9426
9427 void
9428 s390_function_profiler (FILE *file, int labelno)
9429 {
9430 rtx op[7];
9431
9432 char label[128];
9433 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9434
9435 fprintf (file, "# function profiler \n");
9436
9437 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9438 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9439 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
9440
9441 op[2] = gen_rtx_REG (Pmode, 1);
9442 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9443 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9444
9445 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9446 if (flag_pic)
9447 {
9448 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9449 op[4] = gen_rtx_CONST (Pmode, op[4]);
9450 }
9451
9452 if (TARGET_64BIT)
9453 {
9454 output_asm_insn ("stg\t%0,%1", op);
9455 output_asm_insn ("larl\t%2,%3", op);
9456 output_asm_insn ("brasl\t%0,%4", op);
9457 output_asm_insn ("lg\t%0,%1", op);
9458 }
9459 else if (!flag_pic)
9460 {
9461 op[6] = gen_label_rtx ();
9462
9463 output_asm_insn ("st\t%0,%1", op);
9464 output_asm_insn ("bras\t%2,%l6", op);
9465 output_asm_insn (".long\t%4", op);
9466 output_asm_insn (".long\t%3", op);
9467 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9468 output_asm_insn ("l\t%0,0(%2)", op);
9469 output_asm_insn ("l\t%2,4(%2)", op);
9470 output_asm_insn ("basr\t%0,%0", op);
9471 output_asm_insn ("l\t%0,%1", op);
9472 }
9473 else
9474 {
9475 op[5] = gen_label_rtx ();
9476 op[6] = gen_label_rtx ();
9477
9478 output_asm_insn ("st\t%0,%1", op);
9479 output_asm_insn ("bras\t%2,%l6", op);
9480 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9481 output_asm_insn (".long\t%4-%l5", op);
9482 output_asm_insn (".long\t%3-%l5", op);
9483 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9484 output_asm_insn ("lr\t%0,%2", op);
9485 output_asm_insn ("a\t%0,0(%2)", op);
9486 output_asm_insn ("a\t%2,4(%2)", op);
9487 output_asm_insn ("basr\t%0,%0", op);
9488 output_asm_insn ("l\t%0,%1", op);
9489 }
9490 }
9491
9492 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9493 into its SYMBOL_REF_FLAGS. */
9494
9495 static void
9496 s390_encode_section_info (tree decl, rtx rtl, int first)
9497 {
9498 default_encode_section_info (decl, rtl, first);
9499
9500 if (TREE_CODE (decl) == VAR_DECL)
9501 {
9502 /* If a variable has a forced alignment to < 2 bytes, mark it
9503 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9504 operand. */
9505 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9506 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9507 if (!DECL_SIZE (decl)
9508 || !DECL_ALIGN (decl)
9509 || !host_integerp (DECL_SIZE (decl), 0)
9510 || (DECL_ALIGN (decl) <= 64
9511 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9512 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9513 }
9514
9515 /* Literal pool references don't have a decl so they are handled
9516 differently here. We rely on the information in the MEM_ALIGN
9517 entry to decide upon natural alignment. */
9518 if (MEM_P (rtl)
9519 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9520 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9521 && (MEM_ALIGN (rtl) == 0
9522 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9523 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9524 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9525 }
9526
9527 /* Output thunk to FILE that implements a C++ virtual function call (with
9528 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9529 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9530 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9531 relative to the resulting this pointer. */
9532
9533 static void
9534 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9535 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9536 tree function)
9537 {
9538 rtx op[10];
9539 int nonlocal = 0;
9540
9541 /* Make sure unwind info is emitted for the thunk if needed. */
9542 final_start_function (emit_barrier (), file, 1);
9543
9544 /* Operand 0 is the target function. */
9545 op[0] = XEXP (DECL_RTL (function), 0);
9546 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9547 {
9548 nonlocal = 1;
9549 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9550 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9551 op[0] = gen_rtx_CONST (Pmode, op[0]);
9552 }
9553
9554 /* Operand 1 is the 'this' pointer. */
9555 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9556 op[1] = gen_rtx_REG (Pmode, 3);
9557 else
9558 op[1] = gen_rtx_REG (Pmode, 2);
9559
9560 /* Operand 2 is the delta. */
9561 op[2] = GEN_INT (delta);
9562
9563 /* Operand 3 is the vcall_offset. */
9564 op[3] = GEN_INT (vcall_offset);
9565
9566 /* Operand 4 is the temporary register. */
9567 op[4] = gen_rtx_REG (Pmode, 1);
9568
9569 /* Operands 5 to 8 can be used as labels. */
9570 op[5] = NULL_RTX;
9571 op[6] = NULL_RTX;
9572 op[7] = NULL_RTX;
9573 op[8] = NULL_RTX;
9574
9575 /* Operand 9 can be used for temporary register. */
9576 op[9] = NULL_RTX;
9577
9578 /* Generate code. */
9579 if (TARGET_64BIT)
9580 {
9581 /* Setup literal pool pointer if required. */
9582 if ((!DISP_IN_RANGE (delta)
9583 && !CONST_OK_FOR_K (delta)
9584 && !CONST_OK_FOR_Os (delta))
9585 || (!DISP_IN_RANGE (vcall_offset)
9586 && !CONST_OK_FOR_K (vcall_offset)
9587 && !CONST_OK_FOR_Os (vcall_offset)))
9588 {
9589 op[5] = gen_label_rtx ();
9590 output_asm_insn ("larl\t%4,%5", op);
9591 }
9592
9593 /* Add DELTA to this pointer. */
9594 if (delta)
9595 {
9596 if (CONST_OK_FOR_J (delta))
9597 output_asm_insn ("la\t%1,%2(%1)", op);
9598 else if (DISP_IN_RANGE (delta))
9599 output_asm_insn ("lay\t%1,%2(%1)", op);
9600 else if (CONST_OK_FOR_K (delta))
9601 output_asm_insn ("aghi\t%1,%2", op);
9602 else if (CONST_OK_FOR_Os (delta))
9603 output_asm_insn ("agfi\t%1,%2", op);
9604 else
9605 {
9606 op[6] = gen_label_rtx ();
9607 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9608 }
9609 }
9610
9611 /* Perform vcall adjustment. */
9612 if (vcall_offset)
9613 {
9614 if (DISP_IN_RANGE (vcall_offset))
9615 {
9616 output_asm_insn ("lg\t%4,0(%1)", op);
9617 output_asm_insn ("ag\t%1,%3(%4)", op);
9618 }
9619 else if (CONST_OK_FOR_K (vcall_offset))
9620 {
9621 output_asm_insn ("lghi\t%4,%3", op);
9622 output_asm_insn ("ag\t%4,0(%1)", op);
9623 output_asm_insn ("ag\t%1,0(%4)", op);
9624 }
9625 else if (CONST_OK_FOR_Os (vcall_offset))
9626 {
9627 output_asm_insn ("lgfi\t%4,%3", op);
9628 output_asm_insn ("ag\t%4,0(%1)", op);
9629 output_asm_insn ("ag\t%1,0(%4)", op);
9630 }
9631 else
9632 {
9633 op[7] = gen_label_rtx ();
9634 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9635 output_asm_insn ("ag\t%4,0(%1)", op);
9636 output_asm_insn ("ag\t%1,0(%4)", op);
9637 }
9638 }
9639
9640 /* Jump to target. */
9641 output_asm_insn ("jg\t%0", op);
9642
9643 /* Output literal pool if required. */
9644 if (op[5])
9645 {
9646 output_asm_insn (".align\t4", op);
9647 targetm.asm_out.internal_label (file, "L",
9648 CODE_LABEL_NUMBER (op[5]));
9649 }
9650 if (op[6])
9651 {
9652 targetm.asm_out.internal_label (file, "L",
9653 CODE_LABEL_NUMBER (op[6]));
9654 output_asm_insn (".long\t%2", op);
9655 }
9656 if (op[7])
9657 {
9658 targetm.asm_out.internal_label (file, "L",
9659 CODE_LABEL_NUMBER (op[7]));
9660 output_asm_insn (".long\t%3", op);
9661 }
9662 }
9663 else
9664 {
9665 /* Setup base pointer if required. */
9666 if (!vcall_offset
9667 || (!DISP_IN_RANGE (delta)
9668 && !CONST_OK_FOR_K (delta)
9669 && !CONST_OK_FOR_Os (delta))
9670 || (!DISP_IN_RANGE (delta)
9671 && !CONST_OK_FOR_K (vcall_offset)
9672 && !CONST_OK_FOR_Os (vcall_offset)))
9673 {
9674 op[5] = gen_label_rtx ();
9675 output_asm_insn ("basr\t%4,0", op);
9676 targetm.asm_out.internal_label (file, "L",
9677 CODE_LABEL_NUMBER (op[5]));
9678 }
9679
9680 /* Add DELTA to this pointer. */
9681 if (delta)
9682 {
9683 if (CONST_OK_FOR_J (delta))
9684 output_asm_insn ("la\t%1,%2(%1)", op);
9685 else if (DISP_IN_RANGE (delta))
9686 output_asm_insn ("lay\t%1,%2(%1)", op);
9687 else if (CONST_OK_FOR_K (delta))
9688 output_asm_insn ("ahi\t%1,%2", op);
9689 else if (CONST_OK_FOR_Os (delta))
9690 output_asm_insn ("afi\t%1,%2", op);
9691 else
9692 {
9693 op[6] = gen_label_rtx ();
9694 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9695 }
9696 }
9697
9698 /* Perform vcall adjustment. */
9699 if (vcall_offset)
9700 {
9701 if (CONST_OK_FOR_J (vcall_offset))
9702 {
9703 output_asm_insn ("l\t%4,0(%1)", op);
9704 output_asm_insn ("a\t%1,%3(%4)", op);
9705 }
9706 else if (DISP_IN_RANGE (vcall_offset))
9707 {
9708 output_asm_insn ("l\t%4,0(%1)", op);
9709 output_asm_insn ("ay\t%1,%3(%4)", op);
9710 }
9711 else if (CONST_OK_FOR_K (vcall_offset))
9712 {
9713 output_asm_insn ("lhi\t%4,%3", op);
9714 output_asm_insn ("a\t%4,0(%1)", op);
9715 output_asm_insn ("a\t%1,0(%4)", op);
9716 }
9717 else if (CONST_OK_FOR_Os (vcall_offset))
9718 {
9719 output_asm_insn ("iilf\t%4,%3", op);
9720 output_asm_insn ("a\t%4,0(%1)", op);
9721 output_asm_insn ("a\t%1,0(%4)", op);
9722 }
9723 else
9724 {
9725 op[7] = gen_label_rtx ();
9726 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9727 output_asm_insn ("a\t%4,0(%1)", op);
9728 output_asm_insn ("a\t%1,0(%4)", op);
9729 }
9730
9731 /* We had to clobber the base pointer register.
9732 Re-setup the base pointer (with a different base). */
9733 op[5] = gen_label_rtx ();
9734 output_asm_insn ("basr\t%4,0", op);
9735 targetm.asm_out.internal_label (file, "L",
9736 CODE_LABEL_NUMBER (op[5]));
9737 }
9738
9739 /* Jump to target. */
9740 op[8] = gen_label_rtx ();
9741
9742 if (!flag_pic)
9743 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9744 else if (!nonlocal)
9745 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9746 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9747 else if (flag_pic == 1)
9748 {
9749 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9750 output_asm_insn ("l\t%4,%0(%4)", op);
9751 }
9752 else if (flag_pic == 2)
9753 {
9754 op[9] = gen_rtx_REG (Pmode, 0);
9755 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9756 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9757 output_asm_insn ("ar\t%4,%9", op);
9758 output_asm_insn ("l\t%4,0(%4)", op);
9759 }
9760
9761 output_asm_insn ("br\t%4", op);
9762
9763 /* Output literal pool. */
9764 output_asm_insn (".align\t4", op);
9765
9766 if (nonlocal && flag_pic == 2)
9767 output_asm_insn (".long\t%0", op);
9768 if (nonlocal)
9769 {
9770 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9771 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9772 }
9773
9774 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9775 if (!flag_pic)
9776 output_asm_insn (".long\t%0", op);
9777 else
9778 output_asm_insn (".long\t%0-%5", op);
9779
9780 if (op[6])
9781 {
9782 targetm.asm_out.internal_label (file, "L",
9783 CODE_LABEL_NUMBER (op[6]));
9784 output_asm_insn (".long\t%2", op);
9785 }
9786 if (op[7])
9787 {
9788 targetm.asm_out.internal_label (file, "L",
9789 CODE_LABEL_NUMBER (op[7]));
9790 output_asm_insn (".long\t%3", op);
9791 }
9792 }
9793 final_end_function ();
9794 }
9795
9796 static bool
9797 s390_valid_pointer_mode (enum machine_mode mode)
9798 {
9799 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9800 }
9801
9802 /* Checks whether the given CALL_EXPR would use a caller
9803 saved register. This is used to decide whether sibling call
9804 optimization could be performed on the respective function
9805 call. */
9806
9807 static bool
9808 s390_call_saved_register_used (tree call_expr)
9809 {
9810 CUMULATIVE_ARGS cum_v;
9811 cumulative_args_t cum;
9812 tree parameter;
9813 enum machine_mode mode;
9814 tree type;
9815 rtx parm_rtx;
9816 int reg, i;
9817
9818 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9819 cum = pack_cumulative_args (&cum_v);
9820
9821 for (i = 0; i < call_expr_nargs (call_expr); i++)
9822 {
9823 parameter = CALL_EXPR_ARG (call_expr, i);
9824 gcc_assert (parameter);
9825
9826 /* For an undeclared variable passed as parameter we will get
9827 an ERROR_MARK node here. */
9828 if (TREE_CODE (parameter) == ERROR_MARK)
9829 return true;
9830
9831 type = TREE_TYPE (parameter);
9832 gcc_assert (type);
9833
9834 mode = TYPE_MODE (type);
9835 gcc_assert (mode);
9836
9837 if (pass_by_reference (&cum_v, mode, type, true))
9838 {
9839 mode = Pmode;
9840 type = build_pointer_type (type);
9841 }
9842
9843 parm_rtx = s390_function_arg (cum, mode, type, 0);
9844
9845 s390_function_arg_advance (cum, mode, type, 0);
9846
9847 if (!parm_rtx)
9848 continue;
9849
9850 if (REG_P (parm_rtx))
9851 {
9852 for (reg = 0;
9853 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9854 reg++)
9855 if (!call_used_regs[reg + REGNO (parm_rtx)])
9856 return true;
9857 }
9858
9859 if (GET_CODE (parm_rtx) == PARALLEL)
9860 {
9861 int i;
9862
9863 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9864 {
9865 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9866
9867 gcc_assert (REG_P (r));
9868
9869 for (reg = 0;
9870 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9871 reg++)
9872 if (!call_used_regs[reg + REGNO (r)])
9873 return true;
9874 }
9875 }
9876
9877 }
9878 return false;
9879 }
9880
9881 /* Return true if the given call expression can be
9882 turned into a sibling call.
9883 DECL holds the declaration of the function to be called whereas
9884 EXP is the call expression itself. */
9885
9886 static bool
9887 s390_function_ok_for_sibcall (tree decl, tree exp)
9888 {
9889 /* The TPF epilogue uses register 1. */
9890 if (TARGET_TPF_PROFILING)
9891 return false;
9892
9893 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9894 which would have to be restored before the sibcall. */
9895 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9896 return false;
9897
9898 /* Register 6 on s390 is available as an argument register but unfortunately
9899 "caller saved". This makes functions needing this register for arguments
9900 not suitable for sibcalls. */
9901 return !s390_call_saved_register_used (exp);
9902 }
9903
9904 /* Return the fixed registers used for condition codes. */
9905
9906 static bool
9907 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9908 {
9909 *p1 = CC_REGNUM;
9910 *p2 = INVALID_REGNUM;
9911
9912 return true;
9913 }
9914
9915 /* This function is used by the call expanders of the machine description.
9916 It emits the call insn itself together with the necessary operations
9917 to adjust the target address and returns the emitted insn.
9918 ADDR_LOCATION is the target address rtx
9919 TLS_CALL the location of the thread-local symbol
9920 RESULT_REG the register where the result of the call should be stored
9921 RETADDR_REG the register where the return address should be stored
9922 If this parameter is NULL_RTX the call is considered
9923 to be a sibling call. */
9924
9925 rtx
9926 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9927 rtx retaddr_reg)
9928 {
9929 bool plt_call = false;
9930 rtx insn;
9931 rtx call;
9932 rtx clobber;
9933 rtvec vec;
9934
9935 /* Direct function calls need special treatment. */
9936 if (GET_CODE (addr_location) == SYMBOL_REF)
9937 {
9938 /* When calling a global routine in PIC mode, we must
9939 replace the symbol itself with the PLT stub. */
9940 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9941 {
9942 if (retaddr_reg != NULL_RTX)
9943 {
9944 addr_location = gen_rtx_UNSPEC (Pmode,
9945 gen_rtvec (1, addr_location),
9946 UNSPEC_PLT);
9947 addr_location = gen_rtx_CONST (Pmode, addr_location);
9948 plt_call = true;
9949 }
9950 else
9951 /* For -fpic code the PLT entries might use r12 which is
9952 call-saved. Therefore we cannot do a sibcall when
9953 calling directly using a symbol ref. When reaching
9954 this point we decided (in s390_function_ok_for_sibcall)
9955 to do a sibcall for a function pointer but one of the
9956 optimizers was able to get rid of the function pointer
9957 by propagating the symbol ref into the call. This
9958 optimization is illegal for S/390 so we turn the direct
9959 call into a indirect call again. */
9960 addr_location = force_reg (Pmode, addr_location);
9961 }
9962
9963 /* Unless we can use the bras(l) insn, force the
9964 routine address into a register. */
9965 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9966 {
9967 if (flag_pic)
9968 addr_location = legitimize_pic_address (addr_location, 0);
9969 else
9970 addr_location = force_reg (Pmode, addr_location);
9971 }
9972 }
9973
9974 /* If it is already an indirect call or the code above moved the
9975 SYMBOL_REF to somewhere else make sure the address can be found in
9976 register 1. */
9977 if (retaddr_reg == NULL_RTX
9978 && GET_CODE (addr_location) != SYMBOL_REF
9979 && !plt_call)
9980 {
9981 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9982 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9983 }
9984
9985 addr_location = gen_rtx_MEM (QImode, addr_location);
9986 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9987
9988 if (result_reg != NULL_RTX)
9989 call = gen_rtx_SET (VOIDmode, result_reg, call);
9990
9991 if (retaddr_reg != NULL_RTX)
9992 {
9993 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9994
9995 if (tls_call != NULL_RTX)
9996 vec = gen_rtvec (3, call, clobber,
9997 gen_rtx_USE (VOIDmode, tls_call));
9998 else
9999 vec = gen_rtvec (2, call, clobber);
10000
10001 call = gen_rtx_PARALLEL (VOIDmode, vec);
10002 }
10003
10004 insn = emit_call_insn (call);
10005
10006 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10007 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10008 {
10009 /* s390_function_ok_for_sibcall should
10010 have denied sibcalls in this case. */
10011 gcc_assert (retaddr_reg != NULL_RTX);
10012 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
10013 }
10014 return insn;
10015 }
10016
10017 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10018
10019 static void
10020 s390_conditional_register_usage (void)
10021 {
10022 int i;
10023
10024 if (flag_pic)
10025 {
10026 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10027 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10028 }
10029 if (TARGET_CPU_ZARCH)
10030 {
10031 fixed_regs[BASE_REGNUM] = 0;
10032 call_used_regs[BASE_REGNUM] = 0;
10033 fixed_regs[RETURN_REGNUM] = 0;
10034 call_used_regs[RETURN_REGNUM] = 0;
10035 }
10036 if (TARGET_64BIT)
10037 {
10038 for (i = 24; i < 32; i++)
10039 call_used_regs[i] = call_really_used_regs[i] = 0;
10040 }
10041 else
10042 {
10043 for (i = 18; i < 20; i++)
10044 call_used_regs[i] = call_really_used_regs[i] = 0;
10045 }
10046
10047 if (TARGET_SOFT_FLOAT)
10048 {
10049 for (i = 16; i < 32; i++)
10050 call_used_regs[i] = fixed_regs[i] = 1;
10051 }
10052 }
10053
10054 /* Corresponding function to eh_return expander. */
10055
10056 static GTY(()) rtx s390_tpf_eh_return_symbol;
10057 void
10058 s390_emit_tpf_eh_return (rtx target)
10059 {
10060 rtx insn, reg;
10061
10062 if (!s390_tpf_eh_return_symbol)
10063 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10064
10065 reg = gen_rtx_REG (Pmode, 2);
10066
10067 emit_move_insn (reg, target);
10068 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10069 gen_rtx_REG (Pmode, RETURN_REGNUM));
10070 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
10071
10072 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
10073 }
10074
10075 /* Rework the prologue/epilogue to avoid saving/restoring
10076 registers unnecessarily. */
10077
10078 static void
10079 s390_optimize_prologue (void)
10080 {
10081 rtx insn, new_insn, next_insn;
10082
10083 /* Do a final recompute of the frame-related data. */
10084
10085 s390_update_frame_layout ();
10086
10087 /* If all special registers are in fact used, there's nothing we
10088 can do, so no point in walking the insn list. */
10089
10090 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
10091 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
10092 && (TARGET_CPU_ZARCH
10093 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
10094 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10095 return;
10096
10097 /* Search for prologue/epilogue insns and replace them. */
10098
10099 for (insn = get_insns (); insn; insn = next_insn)
10100 {
10101 int first, last, off;
10102 rtx set, base, offset;
10103
10104 next_insn = NEXT_INSN (insn);
10105
10106 if (GET_CODE (insn) != INSN)
10107 continue;
10108
10109 if (GET_CODE (PATTERN (insn)) == PARALLEL
10110 && store_multiple_operation (PATTERN (insn), VOIDmode))
10111 {
10112 set = XVECEXP (PATTERN (insn), 0, 0);
10113 first = REGNO (SET_SRC (set));
10114 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10115 offset = const0_rtx;
10116 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10117 off = INTVAL (offset);
10118
10119 if (GET_CODE (base) != REG || off < 0)
10120 continue;
10121 if (cfun_frame_layout.first_save_gpr != -1
10122 && (cfun_frame_layout.first_save_gpr < first
10123 || cfun_frame_layout.last_save_gpr > last))
10124 continue;
10125 if (REGNO (base) != STACK_POINTER_REGNUM
10126 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10127 continue;
10128 if (first > BASE_REGNUM || last < BASE_REGNUM)
10129 continue;
10130
10131 if (cfun_frame_layout.first_save_gpr != -1)
10132 {
10133 new_insn = save_gprs (base,
10134 off + (cfun_frame_layout.first_save_gpr
10135 - first) * UNITS_PER_LONG,
10136 cfun_frame_layout.first_save_gpr,
10137 cfun_frame_layout.last_save_gpr);
10138 new_insn = emit_insn_before (new_insn, insn);
10139 INSN_ADDRESSES_NEW (new_insn, -1);
10140 }
10141
10142 remove_insn (insn);
10143 continue;
10144 }
10145
10146 if (cfun_frame_layout.first_save_gpr == -1
10147 && GET_CODE (PATTERN (insn)) == SET
10148 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
10149 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
10150 || (!TARGET_CPU_ZARCH
10151 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10152 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10153 {
10154 set = PATTERN (insn);
10155 first = REGNO (SET_SRC (set));
10156 offset = const0_rtx;
10157 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10158 off = INTVAL (offset);
10159
10160 if (GET_CODE (base) != REG || off < 0)
10161 continue;
10162 if (REGNO (base) != STACK_POINTER_REGNUM
10163 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10164 continue;
10165
10166 remove_insn (insn);
10167 continue;
10168 }
10169
10170 if (GET_CODE (PATTERN (insn)) == PARALLEL
10171 && load_multiple_operation (PATTERN (insn), VOIDmode))
10172 {
10173 set = XVECEXP (PATTERN (insn), 0, 0);
10174 first = REGNO (SET_DEST (set));
10175 last = first + XVECLEN (PATTERN (insn), 0) - 1;
10176 offset = const0_rtx;
10177 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10178 off = INTVAL (offset);
10179
10180 if (GET_CODE (base) != REG || off < 0)
10181 continue;
10182 if (cfun_frame_layout.first_restore_gpr != -1
10183 && (cfun_frame_layout.first_restore_gpr < first
10184 || cfun_frame_layout.last_restore_gpr > last))
10185 continue;
10186 if (REGNO (base) != STACK_POINTER_REGNUM
10187 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10188 continue;
10189 if (first > BASE_REGNUM || last < BASE_REGNUM)
10190 continue;
10191
10192 if (cfun_frame_layout.first_restore_gpr != -1)
10193 {
10194 new_insn = restore_gprs (base,
10195 off + (cfun_frame_layout.first_restore_gpr
10196 - first) * UNITS_PER_LONG,
10197 cfun_frame_layout.first_restore_gpr,
10198 cfun_frame_layout.last_restore_gpr);
10199 new_insn = emit_insn_before (new_insn, insn);
10200 INSN_ADDRESSES_NEW (new_insn, -1);
10201 }
10202
10203 remove_insn (insn);
10204 continue;
10205 }
10206
10207 if (cfun_frame_layout.first_restore_gpr == -1
10208 && GET_CODE (PATTERN (insn)) == SET
10209 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10210 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10211 || (!TARGET_CPU_ZARCH
10212 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10213 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10214 {
10215 set = PATTERN (insn);
10216 first = REGNO (SET_DEST (set));
10217 offset = const0_rtx;
10218 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10219 off = INTVAL (offset);
10220
10221 if (GET_CODE (base) != REG || off < 0)
10222 continue;
10223 if (REGNO (base) != STACK_POINTER_REGNUM
10224 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10225 continue;
10226
10227 remove_insn (insn);
10228 continue;
10229 }
10230 }
10231 }
10232
10233 /* On z10 and later the dynamic branch prediction must see the
10234 backward jump within a certain windows. If not it falls back to
10235 the static prediction. This function rearranges the loop backward
10236 branch in a way which makes the static prediction always correct.
10237 The function returns true if it added an instruction. */
10238 static bool
10239 s390_fix_long_loop_prediction (rtx insn)
10240 {
10241 rtx set = single_set (insn);
10242 rtx code_label, label_ref, new_label;
10243 rtx uncond_jump;
10244 rtx cur_insn;
10245 rtx tmp;
10246 int distance;
10247
10248 /* This will exclude branch on count and branch on index patterns
10249 since these are correctly statically predicted. */
10250 if (!set
10251 || SET_DEST (set) != pc_rtx
10252 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10253 return false;
10254
10255 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10256 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10257
10258 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10259
10260 code_label = XEXP (label_ref, 0);
10261
10262 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10263 || INSN_ADDRESSES (INSN_UID (insn)) == -1
10264 || (INSN_ADDRESSES (INSN_UID (insn))
10265 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10266 return false;
10267
10268 for (distance = 0, cur_insn = PREV_INSN (insn);
10269 distance < PREDICT_DISTANCE - 6;
10270 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10271 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10272 return false;
10273
10274 new_label = gen_label_rtx ();
10275 uncond_jump = emit_jump_insn_after (
10276 gen_rtx_SET (VOIDmode, pc_rtx,
10277 gen_rtx_LABEL_REF (VOIDmode, code_label)),
10278 insn);
10279 emit_label_after (new_label, uncond_jump);
10280
10281 tmp = XEXP (SET_SRC (set), 1);
10282 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10283 XEXP (SET_SRC (set), 2) = tmp;
10284 INSN_CODE (insn) = -1;
10285
10286 XEXP (label_ref, 0) = new_label;
10287 JUMP_LABEL (insn) = new_label;
10288 JUMP_LABEL (uncond_jump) = code_label;
10289
10290 return true;
10291 }
10292
10293 /* Returns 1 if INSN reads the value of REG for purposes not related
10294 to addressing of memory, and 0 otherwise. */
10295 static int
10296 s390_non_addr_reg_read_p (rtx reg, rtx insn)
10297 {
10298 return reg_referenced_p (reg, PATTERN (insn))
10299 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10300 }
10301
10302 /* Starting from INSN find_cond_jump looks downwards in the insn
10303 stream for a single jump insn which is the last user of the
10304 condition code set in INSN. */
10305 static rtx
10306 find_cond_jump (rtx insn)
10307 {
10308 for (; insn; insn = NEXT_INSN (insn))
10309 {
10310 rtx ite, cc;
10311
10312 if (LABEL_P (insn))
10313 break;
10314
10315 if (!JUMP_P (insn))
10316 {
10317 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10318 break;
10319 continue;
10320 }
10321
10322 /* This will be triggered by a return. */
10323 if (GET_CODE (PATTERN (insn)) != SET)
10324 break;
10325
10326 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10327 ite = SET_SRC (PATTERN (insn));
10328
10329 if (GET_CODE (ite) != IF_THEN_ELSE)
10330 break;
10331
10332 cc = XEXP (XEXP (ite, 0), 0);
10333 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10334 break;
10335
10336 if (find_reg_note (insn, REG_DEAD, cc))
10337 return insn;
10338 break;
10339 }
10340
10341 return NULL_RTX;
10342 }
10343
10344 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10345 the semantics does not change. If NULL_RTX is passed as COND the
10346 function tries to find the conditional jump starting with INSN. */
10347 static void
10348 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10349 {
10350 rtx tmp = *op0;
10351
10352 if (cond == NULL_RTX)
10353 {
10354 rtx jump = find_cond_jump (NEXT_INSN (insn));
10355 jump = jump ? single_set (jump) : NULL_RTX;
10356
10357 if (jump == NULL_RTX)
10358 return;
10359
10360 cond = XEXP (XEXP (jump, 1), 0);
10361 }
10362
10363 *op0 = *op1;
10364 *op1 = tmp;
10365 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10366 }
10367
10368 /* On z10, instructions of the compare-and-branch family have the
10369 property to access the register occurring as second operand with
10370 its bits complemented. If such a compare is grouped with a second
10371 instruction that accesses the same register non-complemented, and
10372 if that register's value is delivered via a bypass, then the
10373 pipeline recycles, thereby causing significant performance decline.
10374 This function locates such situations and exchanges the two
10375 operands of the compare. The function return true whenever it
10376 added an insn. */
10377 static bool
10378 s390_z10_optimize_cmp (rtx insn)
10379 {
10380 rtx prev_insn, next_insn;
10381 bool insn_added_p = false;
10382 rtx cond, *op0, *op1;
10383
10384 if (GET_CODE (PATTERN (insn)) == PARALLEL)
10385 {
10386 /* Handle compare and branch and branch on count
10387 instructions. */
10388 rtx pattern = single_set (insn);
10389
10390 if (!pattern
10391 || SET_DEST (pattern) != pc_rtx
10392 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10393 return false;
10394
10395 cond = XEXP (SET_SRC (pattern), 0);
10396 op0 = &XEXP (cond, 0);
10397 op1 = &XEXP (cond, 1);
10398 }
10399 else if (GET_CODE (PATTERN (insn)) == SET)
10400 {
10401 rtx src, dest;
10402
10403 /* Handle normal compare instructions. */
10404 src = SET_SRC (PATTERN (insn));
10405 dest = SET_DEST (PATTERN (insn));
10406
10407 if (!REG_P (dest)
10408 || !CC_REGNO_P (REGNO (dest))
10409 || GET_CODE (src) != COMPARE)
10410 return false;
10411
10412 /* s390_swap_cmp will try to find the conditional
10413 jump when passing NULL_RTX as condition. */
10414 cond = NULL_RTX;
10415 op0 = &XEXP (src, 0);
10416 op1 = &XEXP (src, 1);
10417 }
10418 else
10419 return false;
10420
10421 if (!REG_P (*op0) || !REG_P (*op1))
10422 return false;
10423
10424 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10425 return false;
10426
10427 /* Swap the COMPARE arguments and its mask if there is a
10428 conflicting access in the previous insn. */
10429 prev_insn = prev_active_insn (insn);
10430 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10431 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10432 s390_swap_cmp (cond, op0, op1, insn);
10433
10434 /* Check if there is a conflict with the next insn. If there
10435 was no conflict with the previous insn, then swap the
10436 COMPARE arguments and its mask. If we already swapped
10437 the operands, or if swapping them would cause a conflict
10438 with the previous insn, issue a NOP after the COMPARE in
10439 order to separate the two instuctions. */
10440 next_insn = next_active_insn (insn);
10441 if (next_insn != NULL_RTX && INSN_P (next_insn)
10442 && s390_non_addr_reg_read_p (*op1, next_insn))
10443 {
10444 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10445 && s390_non_addr_reg_read_p (*op0, prev_insn))
10446 {
10447 if (REGNO (*op1) == 0)
10448 emit_insn_after (gen_nop1 (), insn);
10449 else
10450 emit_insn_after (gen_nop (), insn);
10451 insn_added_p = true;
10452 }
10453 else
10454 s390_swap_cmp (cond, op0, op1, insn);
10455 }
10456 return insn_added_p;
10457 }
10458
10459 /* Perform machine-dependent processing. */
10460
10461 static void
10462 s390_reorg (void)
10463 {
10464 bool pool_overflow = false;
10465
10466 /* Make sure all splits have been performed; splits after
10467 machine_dependent_reorg might confuse insn length counts. */
10468 split_all_insns_noflow ();
10469
10470 /* Install the main literal pool and the associated base
10471 register load insns.
10472
10473 In addition, there are two problematic situations we need
10474 to correct:
10475
10476 - the literal pool might be > 4096 bytes in size, so that
10477 some of its elements cannot be directly accessed
10478
10479 - a branch target might be > 64K away from the branch, so that
10480 it is not possible to use a PC-relative instruction.
10481
10482 To fix those, we split the single literal pool into multiple
10483 pool chunks, reloading the pool base register at various
10484 points throughout the function to ensure it always points to
10485 the pool chunk the following code expects, and / or replace
10486 PC-relative branches by absolute branches.
10487
10488 However, the two problems are interdependent: splitting the
10489 literal pool can move a branch further away from its target,
10490 causing the 64K limit to overflow, and on the other hand,
10491 replacing a PC-relative branch by an absolute branch means
10492 we need to put the branch target address into the literal
10493 pool, possibly causing it to overflow.
10494
10495 So, we loop trying to fix up both problems until we manage
10496 to satisfy both conditions at the same time. Note that the
10497 loop is guaranteed to terminate as every pass of the loop
10498 strictly decreases the total number of PC-relative branches
10499 in the function. (This is not completely true as there
10500 might be branch-over-pool insns introduced by chunkify_start.
10501 Those never need to be split however.) */
10502
10503 for (;;)
10504 {
10505 struct constant_pool *pool = NULL;
10506
10507 /* Collect the literal pool. */
10508 if (!pool_overflow)
10509 {
10510 pool = s390_mainpool_start ();
10511 if (!pool)
10512 pool_overflow = true;
10513 }
10514
10515 /* If literal pool overflowed, start to chunkify it. */
10516 if (pool_overflow)
10517 pool = s390_chunkify_start ();
10518
10519 /* Split out-of-range branches. If this has created new
10520 literal pool entries, cancel current chunk list and
10521 recompute it. zSeries machines have large branch
10522 instructions, so we never need to split a branch. */
10523 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10524 {
10525 if (pool_overflow)
10526 s390_chunkify_cancel (pool);
10527 else
10528 s390_mainpool_cancel (pool);
10529
10530 continue;
10531 }
10532
10533 /* If we made it up to here, both conditions are satisfied.
10534 Finish up literal pool related changes. */
10535 if (pool_overflow)
10536 s390_chunkify_finish (pool);
10537 else
10538 s390_mainpool_finish (pool);
10539
10540 /* We're done splitting branches. */
10541 cfun->machine->split_branches_pending_p = false;
10542 break;
10543 }
10544
10545 /* Generate out-of-pool execute target insns. */
10546 if (TARGET_CPU_ZARCH)
10547 {
10548 rtx insn, label, target;
10549
10550 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10551 {
10552 label = s390_execute_label (insn);
10553 if (!label)
10554 continue;
10555
10556 gcc_assert (label != const0_rtx);
10557
10558 target = emit_label (XEXP (label, 0));
10559 INSN_ADDRESSES_NEW (target, -1);
10560
10561 target = emit_insn (s390_execute_target (insn));
10562 INSN_ADDRESSES_NEW (target, -1);
10563 }
10564 }
10565
10566 /* Try to optimize prologue and epilogue further. */
10567 s390_optimize_prologue ();
10568
10569 /* Walk over the insns and do some >=z10 specific changes. */
10570 if (s390_tune == PROCESSOR_2097_Z10
10571 || s390_tune == PROCESSOR_2817_Z196)
10572 {
10573 rtx insn;
10574 bool insn_added_p = false;
10575
10576 /* The insn lengths and addresses have to be up to date for the
10577 following manipulations. */
10578 shorten_branches (get_insns ());
10579
10580 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10581 {
10582 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10583 continue;
10584
10585 if (JUMP_P (insn))
10586 insn_added_p |= s390_fix_long_loop_prediction (insn);
10587
10588 if ((GET_CODE (PATTERN (insn)) == PARALLEL
10589 || GET_CODE (PATTERN (insn)) == SET)
10590 && s390_tune == PROCESSOR_2097_Z10)
10591 insn_added_p |= s390_z10_optimize_cmp (insn);
10592 }
10593
10594 /* Adjust branches if we added new instructions. */
10595 if (insn_added_p)
10596 shorten_branches (get_insns ());
10597 }
10598 }
10599
10600 /* Return true if INSN is a fp load insn writing register REGNO. */
10601 static inline bool
10602 s390_fpload_toreg (rtx insn, unsigned int regno)
10603 {
10604 rtx set;
10605 enum attr_type flag = s390_safe_attr_type (insn);
10606
10607 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10608 return false;
10609
10610 set = single_set (insn);
10611
10612 if (set == NULL_RTX)
10613 return false;
10614
10615 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10616 return false;
10617
10618 if (REGNO (SET_DEST (set)) != regno)
10619 return false;
10620
10621 return true;
10622 }
10623
10624 /* This value describes the distance to be avoided between an
10625 aritmetic fp instruction and an fp load writing the same register.
10626 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10627 fine but the exact value has to be avoided. Otherwise the FP
10628 pipeline will throw an exception causing a major penalty. */
10629 #define Z10_EARLYLOAD_DISTANCE 7
10630
10631 /* Rearrange the ready list in order to avoid the situation described
10632 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10633 moved to the very end of the ready list. */
10634 static void
10635 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10636 {
10637 unsigned int regno;
10638 int nready = *nready_p;
10639 rtx tmp;
10640 int i;
10641 rtx insn;
10642 rtx set;
10643 enum attr_type flag;
10644 int distance;
10645
10646 /* Skip DISTANCE - 1 active insns. */
10647 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10648 distance > 0 && insn != NULL_RTX;
10649 distance--, insn = prev_active_insn (insn))
10650 if (CALL_P (insn) || JUMP_P (insn))
10651 return;
10652
10653 if (insn == NULL_RTX)
10654 return;
10655
10656 set = single_set (insn);
10657
10658 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10659 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10660 return;
10661
10662 flag = s390_safe_attr_type (insn);
10663
10664 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10665 return;
10666
10667 regno = REGNO (SET_DEST (set));
10668 i = nready - 1;
10669
10670 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10671 i--;
10672
10673 if (!i)
10674 return;
10675
10676 tmp = ready[i];
10677 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10678 ready[0] = tmp;
10679 }
10680
10681 /* This function is called via hook TARGET_SCHED_REORDER before
10682 issuing one insn from list READY which contains *NREADYP entries.
10683 For target z10 it reorders load instructions to avoid early load
10684 conflicts in the floating point pipeline */
10685 static int
10686 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10687 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10688 {
10689 if (s390_tune == PROCESSOR_2097_Z10)
10690 if (reload_completed && *nreadyp > 1)
10691 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10692
10693 return s390_issue_rate ();
10694 }
10695
10696 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10697 the scheduler has issued INSN. It stores the last issued insn into
10698 last_scheduled_insn in order to make it available for
10699 s390_sched_reorder. */
10700 static int
10701 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10702 int verbose ATTRIBUTE_UNUSED,
10703 rtx insn, int more)
10704 {
10705 last_scheduled_insn = insn;
10706
10707 if (GET_CODE (PATTERN (insn)) != USE
10708 && GET_CODE (PATTERN (insn)) != CLOBBER)
10709 return more - 1;
10710 else
10711 return more;
10712 }
10713
10714 static void
10715 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10716 int verbose ATTRIBUTE_UNUSED,
10717 int max_ready ATTRIBUTE_UNUSED)
10718 {
10719 last_scheduled_insn = NULL_RTX;
10720 }
10721
10722 /* This function checks the whole of insn X for memory references. The
10723 function always returns zero because the framework it is called
10724 from would stop recursively analyzing the insn upon a return value
10725 other than zero. The real result of this function is updating
10726 counter variable MEM_COUNT. */
10727 static int
10728 check_dpu (rtx *x, unsigned *mem_count)
10729 {
10730 if (*x != NULL_RTX && MEM_P (*x))
10731 (*mem_count)++;
10732 return 0;
10733 }
10734
10735 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10736 a new number struct loop *loop should be unrolled if tuned for cpus with
10737 a built-in stride prefetcher.
10738 The loop is analyzed for memory accesses by calling check_dpu for
10739 each rtx of the loop. Depending on the loop_depth and the amount of
10740 memory accesses a new number <=nunroll is returned to improve the
10741 behaviour of the hardware prefetch unit. */
10742 static unsigned
10743 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10744 {
10745 basic_block *bbs;
10746 rtx insn;
10747 unsigned i;
10748 unsigned mem_count = 0;
10749
10750 if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10751 return nunroll;
10752
10753 /* Count the number of memory references within the loop body. */
10754 bbs = get_loop_body (loop);
10755 for (i = 0; i < loop->num_nodes; i++)
10756 {
10757 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10758 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10759 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10760 }
10761 free (bbs);
10762
10763 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10764 if (mem_count == 0)
10765 return nunroll;
10766
10767 switch (loop_depth(loop))
10768 {
10769 case 1:
10770 return MIN (nunroll, 28 / mem_count);
10771 case 2:
10772 return MIN (nunroll, 22 / mem_count);
10773 default:
10774 return MIN (nunroll, 16 / mem_count);
10775 }
10776 }
10777
10778 /* Initialize GCC target structure. */
10779
10780 #undef TARGET_ASM_ALIGNED_HI_OP
10781 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10782 #undef TARGET_ASM_ALIGNED_DI_OP
10783 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10784 #undef TARGET_ASM_INTEGER
10785 #define TARGET_ASM_INTEGER s390_assemble_integer
10786
10787 #undef TARGET_ASM_OPEN_PAREN
10788 #define TARGET_ASM_OPEN_PAREN ""
10789
10790 #undef TARGET_ASM_CLOSE_PAREN
10791 #define TARGET_ASM_CLOSE_PAREN ""
10792
10793 #undef TARGET_OPTION_OVERRIDE
10794 #define TARGET_OPTION_OVERRIDE s390_option_override
10795
10796 #undef TARGET_ENCODE_SECTION_INFO
10797 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10798
10799 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10800 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10801
10802 #ifdef HAVE_AS_TLS
10803 #undef TARGET_HAVE_TLS
10804 #define TARGET_HAVE_TLS true
10805 #endif
10806 #undef TARGET_CANNOT_FORCE_CONST_MEM
10807 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10808
10809 #undef TARGET_DELEGITIMIZE_ADDRESS
10810 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10811
10812 #undef TARGET_LEGITIMIZE_ADDRESS
10813 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10814
10815 #undef TARGET_RETURN_IN_MEMORY
10816 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10817
10818 #undef TARGET_INIT_BUILTINS
10819 #define TARGET_INIT_BUILTINS s390_init_builtins
10820 #undef TARGET_EXPAND_BUILTIN
10821 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10822
10823 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10824 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10825
10826 #undef TARGET_ASM_OUTPUT_MI_THUNK
10827 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10828 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10829 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10830
10831 #undef TARGET_SCHED_ADJUST_PRIORITY
10832 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10833 #undef TARGET_SCHED_ISSUE_RATE
10834 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10835 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10836 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10837
10838 #undef TARGET_SCHED_VARIABLE_ISSUE
10839 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10840 #undef TARGET_SCHED_REORDER
10841 #define TARGET_SCHED_REORDER s390_sched_reorder
10842 #undef TARGET_SCHED_INIT
10843 #define TARGET_SCHED_INIT s390_sched_init
10844
10845 #undef TARGET_CANNOT_COPY_INSN_P
10846 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10847 #undef TARGET_RTX_COSTS
10848 #define TARGET_RTX_COSTS s390_rtx_costs
10849 #undef TARGET_ADDRESS_COST
10850 #define TARGET_ADDRESS_COST s390_address_cost
10851 #undef TARGET_REGISTER_MOVE_COST
10852 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10853 #undef TARGET_MEMORY_MOVE_COST
10854 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10855
10856 #undef TARGET_MACHINE_DEPENDENT_REORG
10857 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10858
10859 #undef TARGET_VALID_POINTER_MODE
10860 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10861
10862 #undef TARGET_BUILD_BUILTIN_VA_LIST
10863 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10864 #undef TARGET_EXPAND_BUILTIN_VA_START
10865 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10866 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10867 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10868
10869 #undef TARGET_PROMOTE_FUNCTION_MODE
10870 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10871 #undef TARGET_PASS_BY_REFERENCE
10872 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10873
10874 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10875 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10876 #undef TARGET_FUNCTION_ARG
10877 #define TARGET_FUNCTION_ARG s390_function_arg
10878 #undef TARGET_FUNCTION_ARG_ADVANCE
10879 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10880 #undef TARGET_FUNCTION_VALUE
10881 #define TARGET_FUNCTION_VALUE s390_function_value
10882 #undef TARGET_LIBCALL_VALUE
10883 #define TARGET_LIBCALL_VALUE s390_libcall_value
10884
10885 #undef TARGET_FIXED_CONDITION_CODE_REGS
10886 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10887
10888 #undef TARGET_CC_MODES_COMPATIBLE
10889 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10890
10891 #undef TARGET_INVALID_WITHIN_DOLOOP
10892 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10893
10894 #ifdef HAVE_AS_TLS
10895 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10896 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10897 #endif
10898
10899 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10900 #undef TARGET_MANGLE_TYPE
10901 #define TARGET_MANGLE_TYPE s390_mangle_type
10902 #endif
10903
10904 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10905 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10906
10907 #undef TARGET_PREFERRED_RELOAD_CLASS
10908 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10909
10910 #undef TARGET_SECONDARY_RELOAD
10911 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10912
10913 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10914 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10915
10916 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10917 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10918
10919 #undef TARGET_LEGITIMATE_ADDRESS_P
10920 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10921
10922 #undef TARGET_LEGITIMATE_CONSTANT_P
10923 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10924
10925 #undef TARGET_CAN_ELIMINATE
10926 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10927
10928 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10929 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10930
10931 #undef TARGET_LOOP_UNROLL_ADJUST
10932 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10933
10934 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10935 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10936 #undef TARGET_TRAMPOLINE_INIT
10937 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10938
10939 #undef TARGET_UNWIND_WORD_MODE
10940 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10941
10942 struct gcc_target targetm = TARGET_INITIALIZER;
10943
10944 #include "gt-s390.h"