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[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "except.h"
39 #include "function.h"
40 #include "recog.h"
41 #include "expr.h"
42 #include "reload.h"
43 #include "toplev.h"
44 #include "basic-block.h"
45 #include "integrate.h"
46 #include "ggc.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "debug.h"
50 #include "langhooks.h"
51 #include "optabs.h"
52 #include "gimple.h"
53 #include "df.h"
54 #include "params.h"
55 #include "cfgloop.h"
56
57
58 /* Define the specific costs for a given cpu. */
59
60 struct processor_costs
61 {
62 /* multiplication */
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
76 const int mxbr;
77 /* square root */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
84 /* division */
85 const int dxbr;
86 const int ddbr;
87 const int debr;
88 const int dlgr;
89 const int dlr;
90 const int dr;
91 const int dsgfr;
92 const int dsgr;
93 };
94
95 const struct processor_costs *s390_cost;
96
97 static const
98 struct processor_costs z900_cost =
99 {
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
127 };
128
129 static const
130 struct processor_costs z990_cost =
131 {
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
159 };
160
161 static const
162 struct processor_costs z9_109_cost =
163 {
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
191 };
192
193 static const
194 struct processor_costs z10_cost =
195 {
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
223 };
224
225 extern int reload_completed;
226
227 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
228 static rtx last_scheduled_insn;
229
230 /* Structure used to hold the components of a S/390 memory
231 address. A legitimate address on S/390 is of the general
232 form
233 base + index + displacement
234 where any of the components is optional.
235
236 base and index are registers of the class ADDR_REGS,
237 displacement is an unsigned 12-bit immediate constant. */
238
239 struct s390_address
240 {
241 rtx base;
242 rtx indx;
243 rtx disp;
244 bool pointer;
245 bool literal_pool;
246 };
247
248 /* Which cpu are we tuning for. */
249 enum processor_type s390_tune = PROCESSOR_max;
250 int s390_tune_flags;
251 /* Which instruction set architecture to use. */
252 enum processor_type s390_arch;
253 int s390_arch_flags;
254
255 HOST_WIDE_INT s390_warn_framesize = 0;
256 HOST_WIDE_INT s390_stack_size = 0;
257 HOST_WIDE_INT s390_stack_guard = 0;
258
259 /* The following structure is embedded in the machine
260 specific part of struct function. */
261
262 struct GTY (()) s390_frame_layout
263 {
264 /* Offset within stack frame. */
265 HOST_WIDE_INT gprs_offset;
266 HOST_WIDE_INT f0_offset;
267 HOST_WIDE_INT f4_offset;
268 HOST_WIDE_INT f8_offset;
269 HOST_WIDE_INT backchain_offset;
270
271 /* Number of first and last gpr where slots in the register
272 save area are reserved for. */
273 int first_save_gpr_slot;
274 int last_save_gpr_slot;
275
276 /* Number of first and last gpr to be saved, restored. */
277 int first_save_gpr;
278 int first_restore_gpr;
279 int last_save_gpr;
280 int last_restore_gpr;
281
282 /* Bits standing for floating point registers. Set, if the
283 respective register has to be saved. Starting with reg 16 (f0)
284 at the rightmost bit.
285 Bit 15 - 8 7 6 5 4 3 2 1 0
286 fpr 15 - 8 7 5 3 1 6 4 2 0
287 reg 31 - 24 23 22 21 20 19 18 17 16 */
288 unsigned int fpr_bitmap;
289
290 /* Number of floating point registers f8-f15 which must be saved. */
291 int high_fprs;
292
293 /* Set if return address needs to be saved.
294 This flag is set by s390_return_addr_rtx if it could not use
295 the initial value of r14 and therefore depends on r14 saved
296 to the stack. */
297 bool save_return_addr_p;
298
299 /* Size of stack frame. */
300 HOST_WIDE_INT frame_size;
301 };
302
303 /* Define the structure for the machine field in struct function. */
304
305 struct GTY(()) machine_function
306 {
307 struct s390_frame_layout frame_layout;
308
309 /* Literal pool base register. */
310 rtx base_reg;
311
312 /* True if we may need to perform branch splitting. */
313 bool split_branches_pending_p;
314
315 /* Some local-dynamic TLS symbol name. */
316 const char *some_ld_name;
317
318 bool has_landing_pad_p;
319 };
320
321 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
322
323 #define cfun_frame_layout (cfun->machine->frame_layout)
324 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
325 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
326 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
327 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
328 (1 << (BITNUM)))
329 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
330 (1 << (BITNUM))))
331
332 /* Number of GPRs and FPRs used for argument passing. */
333 #define GP_ARG_NUM_REG 5
334 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
335
336 /* A couple of shortcuts. */
337 #define CONST_OK_FOR_J(x) \
338 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
339 #define CONST_OK_FOR_K(x) \
340 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
341 #define CONST_OK_FOR_Os(x) \
342 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
343 #define CONST_OK_FOR_Op(x) \
344 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
345 #define CONST_OK_FOR_On(x) \
346 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
347
348 #define REGNO_PAIR_OK(REGNO, MODE) \
349 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
350
351 /* That's the read ahead of the dynamic branch prediction unit in
352 bytes on a z10 CPU. */
353 #define Z10_PREDICT_DISTANCE 384
354
355 static enum machine_mode
356 s390_libgcc_cmp_return_mode (void)
357 {
358 return TARGET_64BIT ? DImode : SImode;
359 }
360
361 static enum machine_mode
362 s390_libgcc_shift_count_mode (void)
363 {
364 return TARGET_64BIT ? DImode : SImode;
365 }
366
367 static enum machine_mode
368 s390_unwind_word_mode (void)
369 {
370 return TARGET_64BIT ? DImode : SImode;
371 }
372
373 /* Return true if the back end supports mode MODE. */
374 static bool
375 s390_scalar_mode_supported_p (enum machine_mode mode)
376 {
377 /* In contrast to the default implementation reject TImode constants on 31bit
378 TARGET_ZARCH for ABI compliance. */
379 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
380 return false;
381
382 if (DECIMAL_FLOAT_MODE_P (mode))
383 return default_decimal_float_supported_p ();
384
385 return default_scalar_mode_supported_p (mode);
386 }
387
388 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
389
390 void
391 s390_set_has_landing_pad_p (bool value)
392 {
393 cfun->machine->has_landing_pad_p = value;
394 }
395
396 /* If two condition code modes are compatible, return a condition code
397 mode which is compatible with both. Otherwise, return
398 VOIDmode. */
399
400 static enum machine_mode
401 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
402 {
403 if (m1 == m2)
404 return m1;
405
406 switch (m1)
407 {
408 case CCZmode:
409 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
410 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
411 return m2;
412 return VOIDmode;
413
414 case CCSmode:
415 case CCUmode:
416 case CCTmode:
417 case CCSRmode:
418 case CCURmode:
419 case CCZ1mode:
420 if (m2 == CCZmode)
421 return m1;
422
423 return VOIDmode;
424
425 default:
426 return VOIDmode;
427 }
428 return VOIDmode;
429 }
430
431 /* Return true if SET either doesn't set the CC register, or else
432 the source and destination have matching CC modes and that
433 CC mode is at least as constrained as REQ_MODE. */
434
435 static bool
436 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
437 {
438 enum machine_mode set_mode;
439
440 gcc_assert (GET_CODE (set) == SET);
441
442 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
443 return 1;
444
445 set_mode = GET_MODE (SET_DEST (set));
446 switch (set_mode)
447 {
448 case CCSmode:
449 case CCSRmode:
450 case CCUmode:
451 case CCURmode:
452 case CCLmode:
453 case CCL1mode:
454 case CCL2mode:
455 case CCL3mode:
456 case CCT1mode:
457 case CCT2mode:
458 case CCT3mode:
459 if (req_mode != set_mode)
460 return 0;
461 break;
462
463 case CCZmode:
464 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
465 && req_mode != CCSRmode && req_mode != CCURmode)
466 return 0;
467 break;
468
469 case CCAPmode:
470 case CCANmode:
471 if (req_mode != CCAmode)
472 return 0;
473 break;
474
475 default:
476 gcc_unreachable ();
477 }
478
479 return (GET_MODE (SET_SRC (set)) == set_mode);
480 }
481
482 /* Return true if every SET in INSN that sets the CC register
483 has source and destination with matching CC modes and that
484 CC mode is at least as constrained as REQ_MODE.
485 If REQ_MODE is VOIDmode, always return false. */
486
487 bool
488 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
489 {
490 int i;
491
492 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
493 if (req_mode == VOIDmode)
494 return false;
495
496 if (GET_CODE (PATTERN (insn)) == SET)
497 return s390_match_ccmode_set (PATTERN (insn), req_mode);
498
499 if (GET_CODE (PATTERN (insn)) == PARALLEL)
500 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
501 {
502 rtx set = XVECEXP (PATTERN (insn), 0, i);
503 if (GET_CODE (set) == SET)
504 if (!s390_match_ccmode_set (set, req_mode))
505 return false;
506 }
507
508 return true;
509 }
510
511 /* If a test-under-mask instruction can be used to implement
512 (compare (and ... OP1) OP2), return the CC mode required
513 to do that. Otherwise, return VOIDmode.
514 MIXED is true if the instruction can distinguish between
515 CC1 and CC2 for mixed selected bits (TMxx), it is false
516 if the instruction cannot (TM). */
517
518 enum machine_mode
519 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
520 {
521 int bit0, bit1;
522
523 /* ??? Fixme: should work on CONST_DOUBLE as well. */
524 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
525 return VOIDmode;
526
527 /* Selected bits all zero: CC0.
528 e.g.: int a; if ((a & (16 + 128)) == 0) */
529 if (INTVAL (op2) == 0)
530 return CCTmode;
531
532 /* Selected bits all one: CC3.
533 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
534 if (INTVAL (op2) == INTVAL (op1))
535 return CCT3mode;
536
537 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
538 int a;
539 if ((a & (16 + 128)) == 16) -> CCT1
540 if ((a & (16 + 128)) == 128) -> CCT2 */
541 if (mixed)
542 {
543 bit1 = exact_log2 (INTVAL (op2));
544 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
545 if (bit0 != -1 && bit1 != -1)
546 return bit0 > bit1 ? CCT1mode : CCT2mode;
547 }
548
549 return VOIDmode;
550 }
551
552 /* Given a comparison code OP (EQ, NE, etc.) and the operands
553 OP0 and OP1 of a COMPARE, return the mode to be used for the
554 comparison. */
555
556 enum machine_mode
557 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
558 {
559 switch (code)
560 {
561 case EQ:
562 case NE:
563 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
564 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
565 return CCAPmode;
566 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
567 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
568 return CCAPmode;
569 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
570 || GET_CODE (op1) == NEG)
571 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
572 return CCLmode;
573
574 if (GET_CODE (op0) == AND)
575 {
576 /* Check whether we can potentially do it via TM. */
577 enum machine_mode ccmode;
578 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
579 if (ccmode != VOIDmode)
580 {
581 /* Relax CCTmode to CCZmode to allow fall-back to AND
582 if that turns out to be beneficial. */
583 return ccmode == CCTmode ? CCZmode : ccmode;
584 }
585 }
586
587 if (register_operand (op0, HImode)
588 && GET_CODE (op1) == CONST_INT
589 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
590 return CCT3mode;
591 if (register_operand (op0, QImode)
592 && GET_CODE (op1) == CONST_INT
593 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
594 return CCT3mode;
595
596 return CCZmode;
597
598 case LE:
599 case LT:
600 case GE:
601 case GT:
602 /* The only overflow condition of NEG and ABS happens when
603 -INT_MAX is used as parameter, which stays negative. So
604 we have an overflow from a positive value to a negative.
605 Using CCAP mode the resulting cc can be used for comparisons. */
606 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
607 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
608 return CCAPmode;
609
610 /* If constants are involved in an add instruction it is possible to use
611 the resulting cc for comparisons with zero. Knowing the sign of the
612 constant the overflow behavior gets predictable. e.g.:
613 int a, b; if ((b = a + c) > 0)
614 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
615 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
616 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
617 {
618 if (INTVAL (XEXP((op0), 1)) < 0)
619 return CCANmode;
620 else
621 return CCAPmode;
622 }
623 /* Fall through. */
624 case UNORDERED:
625 case ORDERED:
626 case UNEQ:
627 case UNLE:
628 case UNLT:
629 case UNGE:
630 case UNGT:
631 case LTGT:
632 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
633 && GET_CODE (op1) != CONST_INT)
634 return CCSRmode;
635 return CCSmode;
636
637 case LTU:
638 case GEU:
639 if (GET_CODE (op0) == PLUS
640 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
641 return CCL1mode;
642
643 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
644 && GET_CODE (op1) != CONST_INT)
645 return CCURmode;
646 return CCUmode;
647
648 case LEU:
649 case GTU:
650 if (GET_CODE (op0) == MINUS
651 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
652 return CCL2mode;
653
654 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
655 && GET_CODE (op1) != CONST_INT)
656 return CCURmode;
657 return CCUmode;
658
659 default:
660 gcc_unreachable ();
661 }
662 }
663
664 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
665 that we can implement more efficiently. */
666
667 void
668 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
669 {
670 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
671 if ((*code == EQ || *code == NE)
672 && *op1 == const0_rtx
673 && GET_CODE (*op0) == ZERO_EXTRACT
674 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
675 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
676 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
677 {
678 rtx inner = XEXP (*op0, 0);
679 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
680 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
681 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
682
683 if (len > 0 && len < modesize
684 && pos >= 0 && pos + len <= modesize
685 && modesize <= HOST_BITS_PER_WIDE_INT)
686 {
687 unsigned HOST_WIDE_INT block;
688 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
689 block <<= modesize - pos - len;
690
691 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
692 gen_int_mode (block, GET_MODE (inner)));
693 }
694 }
695
696 /* Narrow AND of memory against immediate to enable TM. */
697 if ((*code == EQ || *code == NE)
698 && *op1 == const0_rtx
699 && GET_CODE (*op0) == AND
700 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
701 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
702 {
703 rtx inner = XEXP (*op0, 0);
704 rtx mask = XEXP (*op0, 1);
705
706 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
707 if (GET_CODE (inner) == SUBREG
708 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
709 && (GET_MODE_SIZE (GET_MODE (inner))
710 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
711 && ((INTVAL (mask)
712 & GET_MODE_MASK (GET_MODE (inner))
713 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
714 == 0))
715 inner = SUBREG_REG (inner);
716
717 /* Do not change volatile MEMs. */
718 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
719 {
720 int part = s390_single_part (XEXP (*op0, 1),
721 GET_MODE (inner), QImode, 0);
722 if (part >= 0)
723 {
724 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
725 inner = adjust_address_nv (inner, QImode, part);
726 *op0 = gen_rtx_AND (QImode, inner, mask);
727 }
728 }
729 }
730
731 /* Narrow comparisons against 0xffff to HImode if possible. */
732 if ((*code == EQ || *code == NE)
733 && GET_CODE (*op1) == CONST_INT
734 && INTVAL (*op1) == 0xffff
735 && SCALAR_INT_MODE_P (GET_MODE (*op0))
736 && (nonzero_bits (*op0, GET_MODE (*op0))
737 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
738 {
739 *op0 = gen_lowpart (HImode, *op0);
740 *op1 = constm1_rtx;
741 }
742
743 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
744 if (GET_CODE (*op0) == UNSPEC
745 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
746 && XVECLEN (*op0, 0) == 1
747 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
748 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
749 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
750 && *op1 == const0_rtx)
751 {
752 enum rtx_code new_code = UNKNOWN;
753 switch (*code)
754 {
755 case EQ: new_code = EQ; break;
756 case NE: new_code = NE; break;
757 case LT: new_code = GTU; break;
758 case GT: new_code = LTU; break;
759 case LE: new_code = GEU; break;
760 case GE: new_code = LEU; break;
761 default: break;
762 }
763
764 if (new_code != UNKNOWN)
765 {
766 *op0 = XVECEXP (*op0, 0, 0);
767 *code = new_code;
768 }
769 }
770
771 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
772 if (GET_CODE (*op0) == UNSPEC
773 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
774 && XVECLEN (*op0, 0) == 1
775 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
776 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
777 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
778 && *op1 == const0_rtx)
779 {
780 enum rtx_code new_code = UNKNOWN;
781 switch (*code)
782 {
783 case EQ: new_code = EQ; break;
784 case NE: new_code = NE; break;
785 default: break;
786 }
787
788 if (new_code != UNKNOWN)
789 {
790 *op0 = XVECEXP (*op0, 0, 0);
791 *code = new_code;
792 }
793 }
794
795 /* Simplify cascaded EQ, NE with const0_rtx. */
796 if ((*code == NE || *code == EQ)
797 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
798 && GET_MODE (*op0) == SImode
799 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
800 && REG_P (XEXP (*op0, 0))
801 && XEXP (*op0, 1) == const0_rtx
802 && *op1 == const0_rtx)
803 {
804 if ((*code == EQ && GET_CODE (*op0) == NE)
805 || (*code == NE && GET_CODE (*op0) == EQ))
806 *code = EQ;
807 else
808 *code = NE;
809 *op0 = XEXP (*op0, 0);
810 }
811
812 /* Prefer register over memory as first operand. */
813 if (MEM_P (*op0) && REG_P (*op1))
814 {
815 rtx tem = *op0; *op0 = *op1; *op1 = tem;
816 *code = swap_condition (*code);
817 }
818 }
819
820 /* Emit a compare instruction suitable to implement the comparison
821 OP0 CODE OP1. Return the correct condition RTL to be placed in
822 the IF_THEN_ELSE of the conditional branch testing the result. */
823
824 rtx
825 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
826 {
827 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
828 rtx cc;
829
830 /* Do not output a redundant compare instruction if a compare_and_swap
831 pattern already computed the result and the machine modes are compatible. */
832 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
833 {
834 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
835 == GET_MODE (op0));
836 cc = op0;
837 }
838 else
839 {
840 cc = gen_rtx_REG (mode, CC_REGNUM);
841 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
842 }
843
844 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
845 }
846
847 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
848 matches CMP.
849 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
850 conditional branch testing the result. */
851
852 static rtx
853 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
854 {
855 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
856 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
857 }
858
859 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
860 unconditional jump, else a conditional jump under condition COND. */
861
862 void
863 s390_emit_jump (rtx target, rtx cond)
864 {
865 rtx insn;
866
867 target = gen_rtx_LABEL_REF (VOIDmode, target);
868 if (cond)
869 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
870
871 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
872 emit_jump_insn (insn);
873 }
874
875 /* Return branch condition mask to implement a branch
876 specified by CODE. Return -1 for invalid comparisons. */
877
878 int
879 s390_branch_condition_mask (rtx code)
880 {
881 const int CC0 = 1 << 3;
882 const int CC1 = 1 << 2;
883 const int CC2 = 1 << 1;
884 const int CC3 = 1 << 0;
885
886 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
887 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
888 gcc_assert (XEXP (code, 1) == const0_rtx);
889
890 switch (GET_MODE (XEXP (code, 0)))
891 {
892 case CCZmode:
893 case CCZ1mode:
894 switch (GET_CODE (code))
895 {
896 case EQ: return CC0;
897 case NE: return CC1 | CC2 | CC3;
898 default: return -1;
899 }
900 break;
901
902 case CCT1mode:
903 switch (GET_CODE (code))
904 {
905 case EQ: return CC1;
906 case NE: return CC0 | CC2 | CC3;
907 default: return -1;
908 }
909 break;
910
911 case CCT2mode:
912 switch (GET_CODE (code))
913 {
914 case EQ: return CC2;
915 case NE: return CC0 | CC1 | CC3;
916 default: return -1;
917 }
918 break;
919
920 case CCT3mode:
921 switch (GET_CODE (code))
922 {
923 case EQ: return CC3;
924 case NE: return CC0 | CC1 | CC2;
925 default: return -1;
926 }
927 break;
928
929 case CCLmode:
930 switch (GET_CODE (code))
931 {
932 case EQ: return CC0 | CC2;
933 case NE: return CC1 | CC3;
934 default: return -1;
935 }
936 break;
937
938 case CCL1mode:
939 switch (GET_CODE (code))
940 {
941 case LTU: return CC2 | CC3; /* carry */
942 case GEU: return CC0 | CC1; /* no carry */
943 default: return -1;
944 }
945 break;
946
947 case CCL2mode:
948 switch (GET_CODE (code))
949 {
950 case GTU: return CC0 | CC1; /* borrow */
951 case LEU: return CC2 | CC3; /* no borrow */
952 default: return -1;
953 }
954 break;
955
956 case CCL3mode:
957 switch (GET_CODE (code))
958 {
959 case EQ: return CC0 | CC2;
960 case NE: return CC1 | CC3;
961 case LTU: return CC1;
962 case GTU: return CC3;
963 case LEU: return CC1 | CC2;
964 case GEU: return CC2 | CC3;
965 default: return -1;
966 }
967
968 case CCUmode:
969 switch (GET_CODE (code))
970 {
971 case EQ: return CC0;
972 case NE: return CC1 | CC2 | CC3;
973 case LTU: return CC1;
974 case GTU: return CC2;
975 case LEU: return CC0 | CC1;
976 case GEU: return CC0 | CC2;
977 default: return -1;
978 }
979 break;
980
981 case CCURmode:
982 switch (GET_CODE (code))
983 {
984 case EQ: return CC0;
985 case NE: return CC2 | CC1 | CC3;
986 case LTU: return CC2;
987 case GTU: return CC1;
988 case LEU: return CC0 | CC2;
989 case GEU: return CC0 | CC1;
990 default: return -1;
991 }
992 break;
993
994 case CCAPmode:
995 switch (GET_CODE (code))
996 {
997 case EQ: return CC0;
998 case NE: return CC1 | CC2 | CC3;
999 case LT: return CC1 | CC3;
1000 case GT: return CC2;
1001 case LE: return CC0 | CC1 | CC3;
1002 case GE: return CC0 | CC2;
1003 default: return -1;
1004 }
1005 break;
1006
1007 case CCANmode:
1008 switch (GET_CODE (code))
1009 {
1010 case EQ: return CC0;
1011 case NE: return CC1 | CC2 | CC3;
1012 case LT: return CC1;
1013 case GT: return CC2 | CC3;
1014 case LE: return CC0 | CC1;
1015 case GE: return CC0 | CC2 | CC3;
1016 default: return -1;
1017 }
1018 break;
1019
1020 case CCSmode:
1021 switch (GET_CODE (code))
1022 {
1023 case EQ: return CC0;
1024 case NE: return CC1 | CC2 | CC3;
1025 case LT: return CC1;
1026 case GT: return CC2;
1027 case LE: return CC0 | CC1;
1028 case GE: return CC0 | CC2;
1029 case UNORDERED: return CC3;
1030 case ORDERED: return CC0 | CC1 | CC2;
1031 case UNEQ: return CC0 | CC3;
1032 case UNLT: return CC1 | CC3;
1033 case UNGT: return CC2 | CC3;
1034 case UNLE: return CC0 | CC1 | CC3;
1035 case UNGE: return CC0 | CC2 | CC3;
1036 case LTGT: return CC1 | CC2;
1037 default: return -1;
1038 }
1039 break;
1040
1041 case CCSRmode:
1042 switch (GET_CODE (code))
1043 {
1044 case EQ: return CC0;
1045 case NE: return CC2 | CC1 | CC3;
1046 case LT: return CC2;
1047 case GT: return CC1;
1048 case LE: return CC0 | CC2;
1049 case GE: return CC0 | CC1;
1050 case UNORDERED: return CC3;
1051 case ORDERED: return CC0 | CC2 | CC1;
1052 case UNEQ: return CC0 | CC3;
1053 case UNLT: return CC2 | CC3;
1054 case UNGT: return CC1 | CC3;
1055 case UNLE: return CC0 | CC2 | CC3;
1056 case UNGE: return CC0 | CC1 | CC3;
1057 case LTGT: return CC2 | CC1;
1058 default: return -1;
1059 }
1060 break;
1061
1062 default:
1063 return -1;
1064 }
1065 }
1066
1067
1068 /* Return branch condition mask to implement a compare and branch
1069 specified by CODE. Return -1 for invalid comparisons. */
1070
1071 int
1072 s390_compare_and_branch_condition_mask (rtx code)
1073 {
1074 const int CC0 = 1 << 3;
1075 const int CC1 = 1 << 2;
1076 const int CC2 = 1 << 1;
1077
1078 switch (GET_CODE (code))
1079 {
1080 case EQ:
1081 return CC0;
1082 case NE:
1083 return CC1 | CC2;
1084 case LT:
1085 case LTU:
1086 return CC1;
1087 case GT:
1088 case GTU:
1089 return CC2;
1090 case LE:
1091 case LEU:
1092 return CC0 | CC1;
1093 case GE:
1094 case GEU:
1095 return CC0 | CC2;
1096 default:
1097 gcc_unreachable ();
1098 }
1099 return -1;
1100 }
1101
1102 /* If INV is false, return assembler mnemonic string to implement
1103 a branch specified by CODE. If INV is true, return mnemonic
1104 for the corresponding inverted branch. */
1105
1106 static const char *
1107 s390_branch_condition_mnemonic (rtx code, int inv)
1108 {
1109 int mask;
1110
1111 static const char *const mnemonic[16] =
1112 {
1113 NULL, "o", "h", "nle",
1114 "l", "nhe", "lh", "ne",
1115 "e", "nlh", "he", "nl",
1116 "le", "nh", "no", NULL
1117 };
1118
1119 if (GET_CODE (XEXP (code, 0)) == REG
1120 && REGNO (XEXP (code, 0)) == CC_REGNUM
1121 && XEXP (code, 1) == const0_rtx)
1122 mask = s390_branch_condition_mask (code);
1123 else
1124 mask = s390_compare_and_branch_condition_mask (code);
1125
1126 gcc_assert (mask >= 0);
1127
1128 if (inv)
1129 mask ^= 15;
1130
1131 gcc_assert (mask >= 1 && mask <= 14);
1132
1133 return mnemonic[mask];
1134 }
1135
1136 /* Return the part of op which has a value different from def.
1137 The size of the part is determined by mode.
1138 Use this function only if you already know that op really
1139 contains such a part. */
1140
1141 unsigned HOST_WIDE_INT
1142 s390_extract_part (rtx op, enum machine_mode mode, int def)
1143 {
1144 unsigned HOST_WIDE_INT value = 0;
1145 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1146 int part_bits = GET_MODE_BITSIZE (mode);
1147 unsigned HOST_WIDE_INT part_mask
1148 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1149 int i;
1150
1151 for (i = 0; i < max_parts; i++)
1152 {
1153 if (i == 0)
1154 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1155 else
1156 value >>= part_bits;
1157
1158 if ((value & part_mask) != (def & part_mask))
1159 return value & part_mask;
1160 }
1161
1162 gcc_unreachable ();
1163 }
1164
1165 /* If OP is an integer constant of mode MODE with exactly one
1166 part of mode PART_MODE unequal to DEF, return the number of that
1167 part. Otherwise, return -1. */
1168
1169 int
1170 s390_single_part (rtx op,
1171 enum machine_mode mode,
1172 enum machine_mode part_mode,
1173 int def)
1174 {
1175 unsigned HOST_WIDE_INT value = 0;
1176 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1177 unsigned HOST_WIDE_INT part_mask
1178 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1179 int i, part = -1;
1180
1181 if (GET_CODE (op) != CONST_INT)
1182 return -1;
1183
1184 for (i = 0; i < n_parts; i++)
1185 {
1186 if (i == 0)
1187 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1188 else
1189 value >>= GET_MODE_BITSIZE (part_mode);
1190
1191 if ((value & part_mask) != (def & part_mask))
1192 {
1193 if (part != -1)
1194 return -1;
1195 else
1196 part = i;
1197 }
1198 }
1199 return part == -1 ? -1 : n_parts - 1 - part;
1200 }
1201
1202 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1203 bits and no other bits are set in IN. POS and LENGTH can be used
1204 to obtain the start position and the length of the bitfield.
1205
1206 POS gives the position of the first bit of the bitfield counting
1207 from the lowest order bit starting with zero. In order to use this
1208 value for S/390 instructions this has to be converted to "bits big
1209 endian" style. */
1210
1211 bool
1212 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1213 int *pos, int *length)
1214 {
1215 int tmp_pos = 0;
1216 int tmp_length = 0;
1217 int i;
1218 unsigned HOST_WIDE_INT mask = 1ULL;
1219 bool contiguous = false;
1220
1221 for (i = 0; i < size; mask <<= 1, i++)
1222 {
1223 if (contiguous)
1224 {
1225 if (mask & in)
1226 tmp_length++;
1227 else
1228 break;
1229 }
1230 else
1231 {
1232 if (mask & in)
1233 {
1234 contiguous = true;
1235 tmp_length++;
1236 }
1237 else
1238 tmp_pos++;
1239 }
1240 }
1241
1242 if (!tmp_length)
1243 return false;
1244
1245 /* Calculate a mask for all bits beyond the contiguous bits. */
1246 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1247
1248 if (mask & in)
1249 return false;
1250
1251 if (tmp_length + tmp_pos - 1 > size)
1252 return false;
1253
1254 if (length)
1255 *length = tmp_length;
1256
1257 if (pos)
1258 *pos = tmp_pos;
1259
1260 return true;
1261 }
1262
1263 /* Check whether we can (and want to) split a double-word
1264 move in mode MODE from SRC to DST into two single-word
1265 moves, moving the subword FIRST_SUBWORD first. */
1266
1267 bool
1268 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1269 {
1270 /* Floating point registers cannot be split. */
1271 if (FP_REG_P (src) || FP_REG_P (dst))
1272 return false;
1273
1274 /* We don't need to split if operands are directly accessible. */
1275 if (s_operand (src, mode) || s_operand (dst, mode))
1276 return false;
1277
1278 /* Non-offsettable memory references cannot be split. */
1279 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1280 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1281 return false;
1282
1283 /* Moving the first subword must not clobber a register
1284 needed to move the second subword. */
1285 if (register_operand (dst, mode))
1286 {
1287 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1288 if (reg_overlap_mentioned_p (subreg, src))
1289 return false;
1290 }
1291
1292 return true;
1293 }
1294
1295 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1296 and [MEM2, MEM2 + SIZE] do overlap and false
1297 otherwise. */
1298
1299 bool
1300 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1301 {
1302 rtx addr1, addr2, addr_delta;
1303 HOST_WIDE_INT delta;
1304
1305 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1306 return true;
1307
1308 if (size == 0)
1309 return false;
1310
1311 addr1 = XEXP (mem1, 0);
1312 addr2 = XEXP (mem2, 0);
1313
1314 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1315
1316 /* This overlapping check is used by peepholes merging memory block operations.
1317 Overlapping operations would otherwise be recognized by the S/390 hardware
1318 and would fall back to a slower implementation. Allowing overlapping
1319 operations would lead to slow code but not to wrong code. Therefore we are
1320 somewhat optimistic if we cannot prove that the memory blocks are
1321 overlapping.
1322 That's why we return false here although this may accept operations on
1323 overlapping memory areas. */
1324 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1325 return false;
1326
1327 delta = INTVAL (addr_delta);
1328
1329 if (delta == 0
1330 || (delta > 0 && delta < size)
1331 || (delta < 0 && -delta < size))
1332 return true;
1333
1334 return false;
1335 }
1336
1337 /* Check whether the address of memory reference MEM2 equals exactly
1338 the address of memory reference MEM1 plus DELTA. Return true if
1339 we can prove this to be the case, false otherwise. */
1340
1341 bool
1342 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1343 {
1344 rtx addr1, addr2, addr_delta;
1345
1346 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1347 return false;
1348
1349 addr1 = XEXP (mem1, 0);
1350 addr2 = XEXP (mem2, 0);
1351
1352 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1353 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1354 return false;
1355
1356 return true;
1357 }
1358
1359 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1360
1361 void
1362 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1363 rtx *operands)
1364 {
1365 enum machine_mode wmode = mode;
1366 rtx dst = operands[0];
1367 rtx src1 = operands[1];
1368 rtx src2 = operands[2];
1369 rtx op, clob, tem;
1370
1371 /* If we cannot handle the operation directly, use a temp register. */
1372 if (!s390_logical_operator_ok_p (operands))
1373 dst = gen_reg_rtx (mode);
1374
1375 /* QImode and HImode patterns make sense only if we have a destination
1376 in memory. Otherwise perform the operation in SImode. */
1377 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1378 wmode = SImode;
1379
1380 /* Widen operands if required. */
1381 if (mode != wmode)
1382 {
1383 if (GET_CODE (dst) == SUBREG
1384 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1385 dst = tem;
1386 else if (REG_P (dst))
1387 dst = gen_rtx_SUBREG (wmode, dst, 0);
1388 else
1389 dst = gen_reg_rtx (wmode);
1390
1391 if (GET_CODE (src1) == SUBREG
1392 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1393 src1 = tem;
1394 else if (GET_MODE (src1) != VOIDmode)
1395 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1396
1397 if (GET_CODE (src2) == SUBREG
1398 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1399 src2 = tem;
1400 else if (GET_MODE (src2) != VOIDmode)
1401 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1402 }
1403
1404 /* Emit the instruction. */
1405 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1406 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1407 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1408
1409 /* Fix up the destination if needed. */
1410 if (dst != operands[0])
1411 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1412 }
1413
1414 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1415
1416 bool
1417 s390_logical_operator_ok_p (rtx *operands)
1418 {
1419 /* If the destination operand is in memory, it needs to coincide
1420 with one of the source operands. After reload, it has to be
1421 the first source operand. */
1422 if (GET_CODE (operands[0]) == MEM)
1423 return rtx_equal_p (operands[0], operands[1])
1424 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1425
1426 return true;
1427 }
1428
1429 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1430 operand IMMOP to switch from SS to SI type instructions. */
1431
1432 void
1433 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1434 {
1435 int def = code == AND ? -1 : 0;
1436 HOST_WIDE_INT mask;
1437 int part;
1438
1439 gcc_assert (GET_CODE (*memop) == MEM);
1440 gcc_assert (!MEM_VOLATILE_P (*memop));
1441
1442 mask = s390_extract_part (*immop, QImode, def);
1443 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1444 gcc_assert (part >= 0);
1445
1446 *memop = adjust_address (*memop, QImode, part);
1447 *immop = gen_int_mode (mask, QImode);
1448 }
1449
1450
1451 /* How to allocate a 'struct machine_function'. */
1452
1453 static struct machine_function *
1454 s390_init_machine_status (void)
1455 {
1456 return ggc_alloc_cleared_machine_function ();
1457 }
1458
1459 /* Change optimizations to be performed, depending on the
1460 optimization level.
1461
1462 LEVEL is the optimization level specified; 2 if `-O2' is
1463 specified, 1 if `-O' is specified, and 0 if neither is specified.
1464
1465 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1466
1467 void
1468 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1469 {
1470 /* ??? There are apparently still problems with -fcaller-saves. */
1471 flag_caller_saves = 0;
1472
1473 /* By default, always emit DWARF-2 unwind info. This allows debugging
1474 without maintaining a stack frame back-chain. */
1475 flag_asynchronous_unwind_tables = 1;
1476
1477 /* Use MVCLE instructions to decrease code size if requested. */
1478 if (size != 0)
1479 target_flags |= MASK_MVCLE;
1480 }
1481
1482 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1483 to the associated processor_type and processor_flags if so. */
1484
1485 static bool
1486 s390_handle_arch_option (const char *arg,
1487 enum processor_type *type,
1488 int *flags)
1489 {
1490 static struct pta
1491 {
1492 const char *const name; /* processor name or nickname. */
1493 const enum processor_type processor;
1494 const int flags; /* From enum processor_flags. */
1495 }
1496 const processor_alias_table[] =
1497 {
1498 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1499 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1500 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1501 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1502 | PF_LONG_DISPLACEMENT},
1503 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1504 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1505 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1506 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1507 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1508 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1509 };
1510 size_t i;
1511
1512 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1513 if (strcmp (arg, processor_alias_table[i].name) == 0)
1514 {
1515 *type = processor_alias_table[i].processor;
1516 *flags = processor_alias_table[i].flags;
1517 return true;
1518 }
1519 return false;
1520 }
1521
1522 /* Implement TARGET_HANDLE_OPTION. */
1523
1524 static bool
1525 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1526 {
1527 switch (code)
1528 {
1529 case OPT_march_:
1530 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1531
1532 case OPT_mstack_guard_:
1533 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1534 return false;
1535 if (exact_log2 (s390_stack_guard) == -1)
1536 error ("stack guard value must be an exact power of 2");
1537 return true;
1538
1539 case OPT_mstack_size_:
1540 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1541 return false;
1542 if (exact_log2 (s390_stack_size) == -1)
1543 error ("stack size must be an exact power of 2");
1544 return true;
1545
1546 case OPT_mtune_:
1547 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1548
1549 case OPT_mwarn_framesize_:
1550 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1551
1552 default:
1553 return true;
1554 }
1555 }
1556
1557 void
1558 override_options (void)
1559 {
1560 /* Set up function hooks. */
1561 init_machine_status = s390_init_machine_status;
1562
1563 /* Architecture mode defaults according to ABI. */
1564 if (!(target_flags_explicit & MASK_ZARCH))
1565 {
1566 if (TARGET_64BIT)
1567 target_flags |= MASK_ZARCH;
1568 else
1569 target_flags &= ~MASK_ZARCH;
1570 }
1571
1572 /* Determine processor architectural level. */
1573 if (!s390_arch_string)
1574 {
1575 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1576 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1577 }
1578
1579 /* Determine processor to tune for. */
1580 if (s390_tune == PROCESSOR_max)
1581 {
1582 s390_tune = s390_arch;
1583 s390_tune_flags = s390_arch_flags;
1584 }
1585
1586 /* Sanity checks. */
1587 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1588 error ("z/Architecture mode not supported on %s", s390_arch_string);
1589 if (TARGET_64BIT && !TARGET_ZARCH)
1590 error ("64-bit ABI not supported in ESA/390 mode");
1591
1592 if (TARGET_HARD_DFP && !TARGET_DFP)
1593 {
1594 if (target_flags_explicit & MASK_HARD_DFP)
1595 {
1596 if (!TARGET_CPU_DFP)
1597 error ("Hardware decimal floating point instructions"
1598 " not available on %s", s390_arch_string);
1599 if (!TARGET_ZARCH)
1600 error ("Hardware decimal floating point instructions"
1601 " not available in ESA/390 mode");
1602 }
1603 else
1604 target_flags &= ~MASK_HARD_DFP;
1605 }
1606
1607 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1608 {
1609 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1610 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1611
1612 target_flags &= ~MASK_HARD_DFP;
1613 }
1614
1615 /* Set processor cost function. */
1616 switch (s390_tune)
1617 {
1618 case PROCESSOR_2084_Z990:
1619 s390_cost = &z990_cost;
1620 break;
1621 case PROCESSOR_2094_Z9_109:
1622 s390_cost = &z9_109_cost;
1623 break;
1624 case PROCESSOR_2097_Z10:
1625 s390_cost = &z10_cost;
1626 break;
1627 default:
1628 s390_cost = &z900_cost;
1629 }
1630
1631 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1632 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1633 "in combination");
1634
1635 if (s390_stack_size)
1636 {
1637 if (s390_stack_guard >= s390_stack_size)
1638 error ("stack size must be greater than the stack guard value");
1639 else if (s390_stack_size > 1 << 16)
1640 error ("stack size must not be greater than 64k");
1641 }
1642 else if (s390_stack_guard)
1643 error ("-mstack-guard implies use of -mstack-size");
1644
1645 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1646 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1647 target_flags |= MASK_LONG_DOUBLE_128;
1648 #endif
1649
1650 if (s390_tune == PROCESSOR_2097_Z10)
1651 {
1652 if (!PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1653 set_param_value ("max-unrolled-insns", 100);
1654 if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES))
1655 set_param_value ("max-unroll-times", 32);
1656 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEELED_INSNS))
1657 set_param_value ("max-completely-peeled-insns", 2000);
1658 if (!PARAM_SET_P (PARAM_MAX_COMPLETELY_PEEL_TIMES))
1659 set_param_value ("max-completely-peel-times", 64);
1660 }
1661
1662 set_param_value ("max-pending-list-length", 256);
1663 /* values for loop prefetching */
1664 set_param_value ("l1-cache-line-size", 256);
1665 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1666 set_param_value ("l1-cache-size", 128);
1667 /* s390 has more than 2 levels and the size is much larger. Since
1668 we are always running virtualized assume that we only get a small
1669 part of the caches above l1. */
1670 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1671 set_param_value ("l2-cache-size", 1500);
1672 if (!PARAM_SET_P (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO))
1673 set_param_value ("prefetch-min-insn-to-mem-ratio", 2);
1674 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1675 set_param_value ("simultaneous-prefetches", 6);
1676
1677 /* This cannot reside in optimization_options since HAVE_prefetch
1678 requires the arch flags to be evaluated already. */
1679 if (HAVE_prefetch && optimize >= 3)
1680 flag_prefetch_loop_arrays = 1;
1681 }
1682
1683 /* Map for smallest class containing reg regno. */
1684
1685 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1686 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1687 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1688 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1689 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1690 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1691 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1692 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1693 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1694 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1695 ACCESS_REGS, ACCESS_REGS
1696 };
1697
1698 /* Return attribute type of insn. */
1699
1700 static enum attr_type
1701 s390_safe_attr_type (rtx insn)
1702 {
1703 if (recog_memoized (insn) >= 0)
1704 return get_attr_type (insn);
1705 else
1706 return TYPE_NONE;
1707 }
1708
1709 /* Return true if DISP is a valid short displacement. */
1710
1711 static bool
1712 s390_short_displacement (rtx disp)
1713 {
1714 /* No displacement is OK. */
1715 if (!disp)
1716 return true;
1717
1718 /* Without the long displacement facility we don't need to
1719 distingiush between long and short displacement. */
1720 if (!TARGET_LONG_DISPLACEMENT)
1721 return true;
1722
1723 /* Integer displacement in range. */
1724 if (GET_CODE (disp) == CONST_INT)
1725 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1726
1727 /* GOT offset is not OK, the GOT can be large. */
1728 if (GET_CODE (disp) == CONST
1729 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1730 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1731 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1732 return false;
1733
1734 /* All other symbolic constants are literal pool references,
1735 which are OK as the literal pool must be small. */
1736 if (GET_CODE (disp) == CONST)
1737 return true;
1738
1739 return false;
1740 }
1741
1742 /* Decompose a RTL expression ADDR for a memory address into
1743 its components, returned in OUT.
1744
1745 Returns false if ADDR is not a valid memory address, true
1746 otherwise. If OUT is NULL, don't return the components,
1747 but check for validity only.
1748
1749 Note: Only addresses in canonical form are recognized.
1750 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1751 canonical form so that they will be recognized. */
1752
1753 static int
1754 s390_decompose_address (rtx addr, struct s390_address *out)
1755 {
1756 HOST_WIDE_INT offset = 0;
1757 rtx base = NULL_RTX;
1758 rtx indx = NULL_RTX;
1759 rtx disp = NULL_RTX;
1760 rtx orig_disp;
1761 bool pointer = false;
1762 bool base_ptr = false;
1763 bool indx_ptr = false;
1764 bool literal_pool = false;
1765
1766 /* We may need to substitute the literal pool base register into the address
1767 below. However, at this point we do not know which register is going to
1768 be used as base, so we substitute the arg pointer register. This is going
1769 to be treated as holding a pointer below -- it shouldn't be used for any
1770 other purpose. */
1771 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1772
1773 /* Decompose address into base + index + displacement. */
1774
1775 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1776 base = addr;
1777
1778 else if (GET_CODE (addr) == PLUS)
1779 {
1780 rtx op0 = XEXP (addr, 0);
1781 rtx op1 = XEXP (addr, 1);
1782 enum rtx_code code0 = GET_CODE (op0);
1783 enum rtx_code code1 = GET_CODE (op1);
1784
1785 if (code0 == REG || code0 == UNSPEC)
1786 {
1787 if (code1 == REG || code1 == UNSPEC)
1788 {
1789 indx = op0; /* index + base */
1790 base = op1;
1791 }
1792
1793 else
1794 {
1795 base = op0; /* base + displacement */
1796 disp = op1;
1797 }
1798 }
1799
1800 else if (code0 == PLUS)
1801 {
1802 indx = XEXP (op0, 0); /* index + base + disp */
1803 base = XEXP (op0, 1);
1804 disp = op1;
1805 }
1806
1807 else
1808 {
1809 return false;
1810 }
1811 }
1812
1813 else
1814 disp = addr; /* displacement */
1815
1816 /* Extract integer part of displacement. */
1817 orig_disp = disp;
1818 if (disp)
1819 {
1820 if (GET_CODE (disp) == CONST_INT)
1821 {
1822 offset = INTVAL (disp);
1823 disp = NULL_RTX;
1824 }
1825 else if (GET_CODE (disp) == CONST
1826 && GET_CODE (XEXP (disp, 0)) == PLUS
1827 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1828 {
1829 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1830 disp = XEXP (XEXP (disp, 0), 0);
1831 }
1832 }
1833
1834 /* Strip off CONST here to avoid special case tests later. */
1835 if (disp && GET_CODE (disp) == CONST)
1836 disp = XEXP (disp, 0);
1837
1838 /* We can convert literal pool addresses to
1839 displacements by basing them off the base register. */
1840 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1841 {
1842 /* Either base or index must be free to hold the base register. */
1843 if (!base)
1844 base = fake_pool_base, literal_pool = true;
1845 else if (!indx)
1846 indx = fake_pool_base, literal_pool = true;
1847 else
1848 return false;
1849
1850 /* Mark up the displacement. */
1851 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1852 UNSPEC_LTREL_OFFSET);
1853 }
1854
1855 /* Validate base register. */
1856 if (base)
1857 {
1858 if (GET_CODE (base) == UNSPEC)
1859 switch (XINT (base, 1))
1860 {
1861 case UNSPEC_LTREF:
1862 if (!disp)
1863 disp = gen_rtx_UNSPEC (Pmode,
1864 gen_rtvec (1, XVECEXP (base, 0, 0)),
1865 UNSPEC_LTREL_OFFSET);
1866 else
1867 return false;
1868
1869 base = XVECEXP (base, 0, 1);
1870 break;
1871
1872 case UNSPEC_LTREL_BASE:
1873 if (XVECLEN (base, 0) == 1)
1874 base = fake_pool_base, literal_pool = true;
1875 else
1876 base = XVECEXP (base, 0, 1);
1877 break;
1878
1879 default:
1880 return false;
1881 }
1882
1883 if (!REG_P (base)
1884 || (GET_MODE (base) != SImode
1885 && GET_MODE (base) != Pmode))
1886 return false;
1887
1888 if (REGNO (base) == STACK_POINTER_REGNUM
1889 || REGNO (base) == FRAME_POINTER_REGNUM
1890 || ((reload_completed || reload_in_progress)
1891 && frame_pointer_needed
1892 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1893 || REGNO (base) == ARG_POINTER_REGNUM
1894 || (flag_pic
1895 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1896 pointer = base_ptr = true;
1897
1898 if ((reload_completed || reload_in_progress)
1899 && base == cfun->machine->base_reg)
1900 pointer = base_ptr = literal_pool = true;
1901 }
1902
1903 /* Validate index register. */
1904 if (indx)
1905 {
1906 if (GET_CODE (indx) == UNSPEC)
1907 switch (XINT (indx, 1))
1908 {
1909 case UNSPEC_LTREF:
1910 if (!disp)
1911 disp = gen_rtx_UNSPEC (Pmode,
1912 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1913 UNSPEC_LTREL_OFFSET);
1914 else
1915 return false;
1916
1917 indx = XVECEXP (indx, 0, 1);
1918 break;
1919
1920 case UNSPEC_LTREL_BASE:
1921 if (XVECLEN (indx, 0) == 1)
1922 indx = fake_pool_base, literal_pool = true;
1923 else
1924 indx = XVECEXP (indx, 0, 1);
1925 break;
1926
1927 default:
1928 return false;
1929 }
1930
1931 if (!REG_P (indx)
1932 || (GET_MODE (indx) != SImode
1933 && GET_MODE (indx) != Pmode))
1934 return false;
1935
1936 if (REGNO (indx) == STACK_POINTER_REGNUM
1937 || REGNO (indx) == FRAME_POINTER_REGNUM
1938 || ((reload_completed || reload_in_progress)
1939 && frame_pointer_needed
1940 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1941 || REGNO (indx) == ARG_POINTER_REGNUM
1942 || (flag_pic
1943 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1944 pointer = indx_ptr = true;
1945
1946 if ((reload_completed || reload_in_progress)
1947 && indx == cfun->machine->base_reg)
1948 pointer = indx_ptr = literal_pool = true;
1949 }
1950
1951 /* Prefer to use pointer as base, not index. */
1952 if (base && indx && !base_ptr
1953 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1954 {
1955 rtx tmp = base;
1956 base = indx;
1957 indx = tmp;
1958 }
1959
1960 /* Validate displacement. */
1961 if (!disp)
1962 {
1963 /* If virtual registers are involved, the displacement will change later
1964 anyway as the virtual registers get eliminated. This could make a
1965 valid displacement invalid, but it is more likely to make an invalid
1966 displacement valid, because we sometimes access the register save area
1967 via negative offsets to one of those registers.
1968 Thus we don't check the displacement for validity here. If after
1969 elimination the displacement turns out to be invalid after all,
1970 this is fixed up by reload in any case. */
1971 if (base != arg_pointer_rtx
1972 && indx != arg_pointer_rtx
1973 && base != return_address_pointer_rtx
1974 && indx != return_address_pointer_rtx
1975 && base != frame_pointer_rtx
1976 && indx != frame_pointer_rtx
1977 && base != virtual_stack_vars_rtx
1978 && indx != virtual_stack_vars_rtx)
1979 if (!DISP_IN_RANGE (offset))
1980 return false;
1981 }
1982 else
1983 {
1984 /* All the special cases are pointers. */
1985 pointer = true;
1986
1987 /* In the small-PIC case, the linker converts @GOT
1988 and @GOTNTPOFF offsets to possible displacements. */
1989 if (GET_CODE (disp) == UNSPEC
1990 && (XINT (disp, 1) == UNSPEC_GOT
1991 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1992 && flag_pic == 1)
1993 {
1994 ;
1995 }
1996
1997 /* Accept pool label offsets. */
1998 else if (GET_CODE (disp) == UNSPEC
1999 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2000 ;
2001
2002 /* Accept literal pool references. */
2003 else if (GET_CODE (disp) == UNSPEC
2004 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2005 {
2006 orig_disp = gen_rtx_CONST (Pmode, disp);
2007 if (offset)
2008 {
2009 /* If we have an offset, make sure it does not
2010 exceed the size of the constant pool entry. */
2011 rtx sym = XVECEXP (disp, 0, 0);
2012 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2013 return false;
2014
2015 orig_disp = plus_constant (orig_disp, offset);
2016 }
2017 }
2018
2019 else
2020 return false;
2021 }
2022
2023 if (!base && !indx)
2024 pointer = true;
2025
2026 if (out)
2027 {
2028 out->base = base;
2029 out->indx = indx;
2030 out->disp = orig_disp;
2031 out->pointer = pointer;
2032 out->literal_pool = literal_pool;
2033 }
2034
2035 return true;
2036 }
2037
2038 /* Decompose a RTL expression OP for a shift count into its components,
2039 and return the base register in BASE and the offset in OFFSET.
2040
2041 Return true if OP is a valid shift count, false if not. */
2042
2043 bool
2044 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2045 {
2046 HOST_WIDE_INT off = 0;
2047
2048 /* We can have an integer constant, an address register,
2049 or a sum of the two. */
2050 if (GET_CODE (op) == CONST_INT)
2051 {
2052 off = INTVAL (op);
2053 op = NULL_RTX;
2054 }
2055 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2056 {
2057 off = INTVAL (XEXP (op, 1));
2058 op = XEXP (op, 0);
2059 }
2060 while (op && GET_CODE (op) == SUBREG)
2061 op = SUBREG_REG (op);
2062
2063 if (op && GET_CODE (op) != REG)
2064 return false;
2065
2066 if (offset)
2067 *offset = off;
2068 if (base)
2069 *base = op;
2070
2071 return true;
2072 }
2073
2074
2075 /* Return true if CODE is a valid address without index. */
2076
2077 bool
2078 s390_legitimate_address_without_index_p (rtx op)
2079 {
2080 struct s390_address addr;
2081
2082 if (!s390_decompose_address (XEXP (op, 0), &addr))
2083 return false;
2084 if (addr.indx)
2085 return false;
2086
2087 return true;
2088 }
2089
2090
2091 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2092 and return these parts in SYMREF and ADDEND. You can pass NULL in
2093 SYMREF and/or ADDEND if you are not interested in these values. */
2094
2095 static bool
2096 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2097 {
2098 HOST_WIDE_INT tmpaddend = 0;
2099
2100 if (GET_CODE (addr) == CONST)
2101 addr = XEXP (addr, 0);
2102
2103 if (GET_CODE (addr) == PLUS)
2104 {
2105 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2106 && CONST_INT_P (XEXP (addr, 1)))
2107 {
2108 tmpaddend = INTVAL (XEXP (addr, 1));
2109 addr = XEXP (addr, 0);
2110 }
2111 else
2112 return false;
2113 }
2114 else
2115 if (GET_CODE (addr) != SYMBOL_REF)
2116 return false;
2117
2118 if (symref)
2119 *symref = addr;
2120 if (addend)
2121 *addend = tmpaddend;
2122
2123 return true;
2124 }
2125
2126
2127 /* Return true if the address in OP is valid for constraint letter C
2128 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2129 pool MEMs should be accepted. Only the Q, R, S, T constraint
2130 letters are allowed for C. */
2131
2132 static int
2133 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2134 {
2135 struct s390_address addr;
2136 bool decomposed = false;
2137
2138 /* This check makes sure that no symbolic address (except literal
2139 pool references) are accepted by the R or T constraints. */
2140 if (s390_symref_operand_p (op, NULL, NULL))
2141 {
2142 if (!lit_pool_ok)
2143 return 0;
2144 if (!s390_decompose_address (op, &addr))
2145 return 0;
2146 if (!addr.literal_pool)
2147 return 0;
2148 decomposed = true;
2149 }
2150
2151 switch (c)
2152 {
2153 case 'Q': /* no index short displacement */
2154 if (!decomposed && !s390_decompose_address (op, &addr))
2155 return 0;
2156 if (addr.indx)
2157 return 0;
2158 if (!s390_short_displacement (addr.disp))
2159 return 0;
2160 break;
2161
2162 case 'R': /* with index short displacement */
2163 if (TARGET_LONG_DISPLACEMENT)
2164 {
2165 if (!decomposed && !s390_decompose_address (op, &addr))
2166 return 0;
2167 if (!s390_short_displacement (addr.disp))
2168 return 0;
2169 }
2170 /* Any invalid address here will be fixed up by reload,
2171 so accept it for the most generic constraint. */
2172 break;
2173
2174 case 'S': /* no index long displacement */
2175 if (!TARGET_LONG_DISPLACEMENT)
2176 return 0;
2177 if (!decomposed && !s390_decompose_address (op, &addr))
2178 return 0;
2179 if (addr.indx)
2180 return 0;
2181 if (s390_short_displacement (addr.disp))
2182 return 0;
2183 break;
2184
2185 case 'T': /* with index long displacement */
2186 if (!TARGET_LONG_DISPLACEMENT)
2187 return 0;
2188 /* Any invalid address here will be fixed up by reload,
2189 so accept it for the most generic constraint. */
2190 if ((decomposed || s390_decompose_address (op, &addr))
2191 && s390_short_displacement (addr.disp))
2192 return 0;
2193 break;
2194 default:
2195 return 0;
2196 }
2197 return 1;
2198 }
2199
2200
2201 /* Evaluates constraint strings described by the regular expression
2202 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2203 the constraint given in STR, or 0 else. */
2204
2205 int
2206 s390_mem_constraint (const char *str, rtx op)
2207 {
2208 char c = str[0];
2209
2210 switch (c)
2211 {
2212 case 'A':
2213 /* Check for offsettable variants of memory constraints. */
2214 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2215 return 0;
2216 if ((reload_completed || reload_in_progress)
2217 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2218 return 0;
2219 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2220 case 'B':
2221 /* Check for non-literal-pool variants of memory constraints. */
2222 if (!MEM_P (op))
2223 return 0;
2224 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2225 case 'Q':
2226 case 'R':
2227 case 'S':
2228 case 'T':
2229 if (GET_CODE (op) != MEM)
2230 return 0;
2231 return s390_check_qrst_address (c, XEXP (op, 0), true);
2232 case 'U':
2233 return (s390_check_qrst_address ('Q', op, true)
2234 || s390_check_qrst_address ('R', op, true));
2235 case 'W':
2236 return (s390_check_qrst_address ('S', op, true)
2237 || s390_check_qrst_address ('T', op, true));
2238 case 'Y':
2239 /* Simply check for the basic form of a shift count. Reload will
2240 take care of making sure we have a proper base register. */
2241 if (!s390_decompose_shift_count (op, NULL, NULL))
2242 return 0;
2243 break;
2244 case 'Z':
2245 return s390_check_qrst_address (str[1], op, true);
2246 default:
2247 return 0;
2248 }
2249 return 1;
2250 }
2251
2252
2253 /* Evaluates constraint strings starting with letter O. Input
2254 parameter C is the second letter following the "O" in the constraint
2255 string. Returns 1 if VALUE meets the respective constraint and 0
2256 otherwise. */
2257
2258 int
2259 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2260 {
2261 if (!TARGET_EXTIMM)
2262 return 0;
2263
2264 switch (c)
2265 {
2266 case 's':
2267 return trunc_int_for_mode (value, SImode) == value;
2268
2269 case 'p':
2270 return value == 0
2271 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2272
2273 case 'n':
2274 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2275
2276 default:
2277 gcc_unreachable ();
2278 }
2279 }
2280
2281
2282 /* Evaluates constraint strings starting with letter N. Parameter STR
2283 contains the letters following letter "N" in the constraint string.
2284 Returns true if VALUE matches the constraint. */
2285
2286 int
2287 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2288 {
2289 enum machine_mode mode, part_mode;
2290 int def;
2291 int part, part_goal;
2292
2293
2294 if (str[0] == 'x')
2295 part_goal = -1;
2296 else
2297 part_goal = str[0] - '0';
2298
2299 switch (str[1])
2300 {
2301 case 'Q':
2302 part_mode = QImode;
2303 break;
2304 case 'H':
2305 part_mode = HImode;
2306 break;
2307 case 'S':
2308 part_mode = SImode;
2309 break;
2310 default:
2311 return 0;
2312 }
2313
2314 switch (str[2])
2315 {
2316 case 'H':
2317 mode = HImode;
2318 break;
2319 case 'S':
2320 mode = SImode;
2321 break;
2322 case 'D':
2323 mode = DImode;
2324 break;
2325 default:
2326 return 0;
2327 }
2328
2329 switch (str[3])
2330 {
2331 case '0':
2332 def = 0;
2333 break;
2334 case 'F':
2335 def = -1;
2336 break;
2337 default:
2338 return 0;
2339 }
2340
2341 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2342 return 0;
2343
2344 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2345 if (part < 0)
2346 return 0;
2347 if (part_goal != -1 && part_goal != part)
2348 return 0;
2349
2350 return 1;
2351 }
2352
2353
2354 /* Returns true if the input parameter VALUE is a float zero. */
2355
2356 int
2357 s390_float_const_zero_p (rtx value)
2358 {
2359 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2360 && value == CONST0_RTX (GET_MODE (value)));
2361 }
2362
2363
2364 /* Compute a (partial) cost for rtx X. Return true if the complete
2365 cost has been computed, and false if subexpressions should be
2366 scanned. In either case, *TOTAL contains the cost result.
2367 CODE contains GET_CODE (x), OUTER_CODE contains the code
2368 of the superexpression of x. */
2369
2370 static bool
2371 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2372 bool speed ATTRIBUTE_UNUSED)
2373 {
2374 switch (code)
2375 {
2376 case CONST:
2377 case CONST_INT:
2378 case LABEL_REF:
2379 case SYMBOL_REF:
2380 case CONST_DOUBLE:
2381 case MEM:
2382 *total = 0;
2383 return true;
2384
2385 case ASHIFT:
2386 case ASHIFTRT:
2387 case LSHIFTRT:
2388 case ROTATE:
2389 case ROTATERT:
2390 case AND:
2391 case IOR:
2392 case XOR:
2393 case NEG:
2394 case NOT:
2395 *total = COSTS_N_INSNS (1);
2396 return false;
2397
2398 case PLUS:
2399 case MINUS:
2400 /* Check for multiply and add. */
2401 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2402 && GET_CODE (XEXP (x, 0)) == MULT
2403 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2404 {
2405 /* This is the multiply and add case. */
2406 if (GET_MODE (x) == DFmode)
2407 *total = s390_cost->madbr;
2408 else
2409 *total = s390_cost->maebr;
2410 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2411 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2412 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2413 return true; /* Do not do an additional recursive descent. */
2414 }
2415 *total = COSTS_N_INSNS (1);
2416 return false;
2417
2418 case MULT:
2419 switch (GET_MODE (x))
2420 {
2421 case SImode:
2422 {
2423 rtx left = XEXP (x, 0);
2424 rtx right = XEXP (x, 1);
2425 if (GET_CODE (right) == CONST_INT
2426 && CONST_OK_FOR_K (INTVAL (right)))
2427 *total = s390_cost->mhi;
2428 else if (GET_CODE (left) == SIGN_EXTEND)
2429 *total = s390_cost->mh;
2430 else
2431 *total = s390_cost->ms; /* msr, ms, msy */
2432 break;
2433 }
2434 case DImode:
2435 {
2436 rtx left = XEXP (x, 0);
2437 rtx right = XEXP (x, 1);
2438 if (TARGET_ZARCH)
2439 {
2440 if (GET_CODE (right) == CONST_INT
2441 && CONST_OK_FOR_K (INTVAL (right)))
2442 *total = s390_cost->mghi;
2443 else if (GET_CODE (left) == SIGN_EXTEND)
2444 *total = s390_cost->msgf;
2445 else
2446 *total = s390_cost->msg; /* msgr, msg */
2447 }
2448 else /* TARGET_31BIT */
2449 {
2450 if (GET_CODE (left) == SIGN_EXTEND
2451 && GET_CODE (right) == SIGN_EXTEND)
2452 /* mulsidi case: mr, m */
2453 *total = s390_cost->m;
2454 else if (GET_CODE (left) == ZERO_EXTEND
2455 && GET_CODE (right) == ZERO_EXTEND
2456 && TARGET_CPU_ZARCH)
2457 /* umulsidi case: ml, mlr */
2458 *total = s390_cost->ml;
2459 else
2460 /* Complex calculation is required. */
2461 *total = COSTS_N_INSNS (40);
2462 }
2463 break;
2464 }
2465 case SFmode:
2466 case DFmode:
2467 *total = s390_cost->mult_df;
2468 break;
2469 case TFmode:
2470 *total = s390_cost->mxbr;
2471 break;
2472 default:
2473 return false;
2474 }
2475 return false;
2476
2477 case UDIV:
2478 case UMOD:
2479 if (GET_MODE (x) == TImode) /* 128 bit division */
2480 *total = s390_cost->dlgr;
2481 else if (GET_MODE (x) == DImode)
2482 {
2483 rtx right = XEXP (x, 1);
2484 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2485 *total = s390_cost->dlr;
2486 else /* 64 by 64 bit division */
2487 *total = s390_cost->dlgr;
2488 }
2489 else if (GET_MODE (x) == SImode) /* 32 bit division */
2490 *total = s390_cost->dlr;
2491 return false;
2492
2493 case DIV:
2494 case MOD:
2495 if (GET_MODE (x) == DImode)
2496 {
2497 rtx right = XEXP (x, 1);
2498 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2499 if (TARGET_ZARCH)
2500 *total = s390_cost->dsgfr;
2501 else
2502 *total = s390_cost->dr;
2503 else /* 64 by 64 bit division */
2504 *total = s390_cost->dsgr;
2505 }
2506 else if (GET_MODE (x) == SImode) /* 32 bit division */
2507 *total = s390_cost->dlr;
2508 else if (GET_MODE (x) == SFmode)
2509 {
2510 *total = s390_cost->debr;
2511 }
2512 else if (GET_MODE (x) == DFmode)
2513 {
2514 *total = s390_cost->ddbr;
2515 }
2516 else if (GET_MODE (x) == TFmode)
2517 {
2518 *total = s390_cost->dxbr;
2519 }
2520 return false;
2521
2522 case SQRT:
2523 if (GET_MODE (x) == SFmode)
2524 *total = s390_cost->sqebr;
2525 else if (GET_MODE (x) == DFmode)
2526 *total = s390_cost->sqdbr;
2527 else /* TFmode */
2528 *total = s390_cost->sqxbr;
2529 return false;
2530
2531 case SIGN_EXTEND:
2532 case ZERO_EXTEND:
2533 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2534 || outer_code == PLUS || outer_code == MINUS
2535 || outer_code == COMPARE)
2536 *total = 0;
2537 return false;
2538
2539 case COMPARE:
2540 *total = COSTS_N_INSNS (1);
2541 if (GET_CODE (XEXP (x, 0)) == AND
2542 && GET_CODE (XEXP (x, 1)) == CONST_INT
2543 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2544 {
2545 rtx op0 = XEXP (XEXP (x, 0), 0);
2546 rtx op1 = XEXP (XEXP (x, 0), 1);
2547 rtx op2 = XEXP (x, 1);
2548
2549 if (memory_operand (op0, GET_MODE (op0))
2550 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2551 return true;
2552 if (register_operand (op0, GET_MODE (op0))
2553 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2554 return true;
2555 }
2556 return false;
2557
2558 default:
2559 return false;
2560 }
2561 }
2562
2563 /* Return the cost of an address rtx ADDR. */
2564
2565 static int
2566 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2567 {
2568 struct s390_address ad;
2569 if (!s390_decompose_address (addr, &ad))
2570 return 1000;
2571
2572 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2573 }
2574
2575 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2576 otherwise return 0. */
2577
2578 int
2579 tls_symbolic_operand (rtx op)
2580 {
2581 if (GET_CODE (op) != SYMBOL_REF)
2582 return 0;
2583 return SYMBOL_REF_TLS_MODEL (op);
2584 }
2585 \f
2586 /* Split DImode access register reference REG (on 64-bit) into its constituent
2587 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2588 gen_highpart cannot be used as they assume all registers are word-sized,
2589 while our access registers have only half that size. */
2590
2591 void
2592 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2593 {
2594 gcc_assert (TARGET_64BIT);
2595 gcc_assert (ACCESS_REG_P (reg));
2596 gcc_assert (GET_MODE (reg) == DImode);
2597 gcc_assert (!(REGNO (reg) & 1));
2598
2599 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2600 *hi = gen_rtx_REG (SImode, REGNO (reg));
2601 }
2602
2603 /* Return true if OP contains a symbol reference */
2604
2605 bool
2606 symbolic_reference_mentioned_p (rtx op)
2607 {
2608 const char *fmt;
2609 int i;
2610
2611 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2612 return 1;
2613
2614 fmt = GET_RTX_FORMAT (GET_CODE (op));
2615 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2616 {
2617 if (fmt[i] == 'E')
2618 {
2619 int j;
2620
2621 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2622 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2623 return 1;
2624 }
2625
2626 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2627 return 1;
2628 }
2629
2630 return 0;
2631 }
2632
2633 /* Return true if OP contains a reference to a thread-local symbol. */
2634
2635 bool
2636 tls_symbolic_reference_mentioned_p (rtx op)
2637 {
2638 const char *fmt;
2639 int i;
2640
2641 if (GET_CODE (op) == SYMBOL_REF)
2642 return tls_symbolic_operand (op);
2643
2644 fmt = GET_RTX_FORMAT (GET_CODE (op));
2645 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2646 {
2647 if (fmt[i] == 'E')
2648 {
2649 int j;
2650
2651 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2652 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2653 return true;
2654 }
2655
2656 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2657 return true;
2658 }
2659
2660 return false;
2661 }
2662
2663
2664 /* Return true if OP is a legitimate general operand when
2665 generating PIC code. It is given that flag_pic is on
2666 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2667
2668 int
2669 legitimate_pic_operand_p (rtx op)
2670 {
2671 /* Accept all non-symbolic constants. */
2672 if (!SYMBOLIC_CONST (op))
2673 return 1;
2674
2675 /* Reject everything else; must be handled
2676 via emit_symbolic_move. */
2677 return 0;
2678 }
2679
2680 /* Returns true if the constant value OP is a legitimate general operand.
2681 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2682
2683 int
2684 legitimate_constant_p (rtx op)
2685 {
2686 /* Accept all non-symbolic constants. */
2687 if (!SYMBOLIC_CONST (op))
2688 return 1;
2689
2690 /* Accept immediate LARL operands. */
2691 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2692 return 1;
2693
2694 /* Thread-local symbols are never legal constants. This is
2695 so that emit_call knows that computing such addresses
2696 might require a function call. */
2697 if (TLS_SYMBOLIC_CONST (op))
2698 return 0;
2699
2700 /* In the PIC case, symbolic constants must *not* be
2701 forced into the literal pool. We accept them here,
2702 so that they will be handled by emit_symbolic_move. */
2703 if (flag_pic)
2704 return 1;
2705
2706 /* All remaining non-PIC symbolic constants are
2707 forced into the literal pool. */
2708 return 0;
2709 }
2710
2711 /* Determine if it's legal to put X into the constant pool. This
2712 is not possible if X contains the address of a symbol that is
2713 not constant (TLS) or not known at final link time (PIC). */
2714
2715 static bool
2716 s390_cannot_force_const_mem (rtx x)
2717 {
2718 switch (GET_CODE (x))
2719 {
2720 case CONST_INT:
2721 case CONST_DOUBLE:
2722 /* Accept all non-symbolic constants. */
2723 return false;
2724
2725 case LABEL_REF:
2726 /* Labels are OK iff we are non-PIC. */
2727 return flag_pic != 0;
2728
2729 case SYMBOL_REF:
2730 /* 'Naked' TLS symbol references are never OK,
2731 non-TLS symbols are OK iff we are non-PIC. */
2732 if (tls_symbolic_operand (x))
2733 return true;
2734 else
2735 return flag_pic != 0;
2736
2737 case CONST:
2738 return s390_cannot_force_const_mem (XEXP (x, 0));
2739 case PLUS:
2740 case MINUS:
2741 return s390_cannot_force_const_mem (XEXP (x, 0))
2742 || s390_cannot_force_const_mem (XEXP (x, 1));
2743
2744 case UNSPEC:
2745 switch (XINT (x, 1))
2746 {
2747 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2748 case UNSPEC_LTREL_OFFSET:
2749 case UNSPEC_GOT:
2750 case UNSPEC_GOTOFF:
2751 case UNSPEC_PLTOFF:
2752 case UNSPEC_TLSGD:
2753 case UNSPEC_TLSLDM:
2754 case UNSPEC_NTPOFF:
2755 case UNSPEC_DTPOFF:
2756 case UNSPEC_GOTNTPOFF:
2757 case UNSPEC_INDNTPOFF:
2758 return false;
2759
2760 /* If the literal pool shares the code section, be put
2761 execute template placeholders into the pool as well. */
2762 case UNSPEC_INSN:
2763 return TARGET_CPU_ZARCH;
2764
2765 default:
2766 return true;
2767 }
2768 break;
2769
2770 default:
2771 gcc_unreachable ();
2772 }
2773 }
2774
2775 /* Returns true if the constant value OP is a legitimate general
2776 operand during and after reload. The difference to
2777 legitimate_constant_p is that this function will not accept
2778 a constant that would need to be forced to the literal pool
2779 before it can be used as operand. */
2780
2781 bool
2782 legitimate_reload_constant_p (rtx op)
2783 {
2784 /* Accept la(y) operands. */
2785 if (GET_CODE (op) == CONST_INT
2786 && DISP_IN_RANGE (INTVAL (op)))
2787 return true;
2788
2789 /* Accept l(g)hi/l(g)fi operands. */
2790 if (GET_CODE (op) == CONST_INT
2791 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2792 return true;
2793
2794 /* Accept lliXX operands. */
2795 if (TARGET_ZARCH
2796 && GET_CODE (op) == CONST_INT
2797 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2798 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2799 return true;
2800
2801 if (TARGET_EXTIMM
2802 && GET_CODE (op) == CONST_INT
2803 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2804 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2805 return true;
2806
2807 /* Accept larl operands. */
2808 if (TARGET_CPU_ZARCH
2809 && larl_operand (op, VOIDmode))
2810 return true;
2811
2812 /* Accept double-word operands that can be split. */
2813 if (GET_CODE (op) == CONST_INT
2814 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2815 {
2816 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2817 rtx hi = operand_subword (op, 0, 0, dword_mode);
2818 rtx lo = operand_subword (op, 1, 0, dword_mode);
2819 return legitimate_reload_constant_p (hi)
2820 && legitimate_reload_constant_p (lo);
2821 }
2822
2823 /* Everything else cannot be handled without reload. */
2824 return false;
2825 }
2826
2827 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2828 return the class of reg to actually use. */
2829
2830 enum reg_class
2831 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2832 {
2833 switch (GET_CODE (op))
2834 {
2835 /* Constants we cannot reload must be forced into the
2836 literal pool. */
2837
2838 case CONST_DOUBLE:
2839 case CONST_INT:
2840 if (legitimate_reload_constant_p (op))
2841 return rclass;
2842 else
2843 return NO_REGS;
2844
2845 /* If a symbolic constant or a PLUS is reloaded,
2846 it is most likely being used as an address, so
2847 prefer ADDR_REGS. If 'class' is not a superset
2848 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2849 case PLUS:
2850 case LABEL_REF:
2851 case SYMBOL_REF:
2852 case CONST:
2853 if (reg_class_subset_p (ADDR_REGS, rclass))
2854 return ADDR_REGS;
2855 else
2856 return NO_REGS;
2857
2858 default:
2859 break;
2860 }
2861
2862 return rclass;
2863 }
2864
2865 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2866 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2867 aligned. */
2868
2869 bool
2870 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2871 {
2872 HOST_WIDE_INT addend;
2873 rtx symref;
2874
2875 if (!s390_symref_operand_p (addr, &symref, &addend))
2876 return false;
2877
2878 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2879 && !(addend & (alignment - 1)));
2880 }
2881
2882 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2883 operand SCRATCH is used to reload the even part of the address and
2884 adding one. */
2885
2886 void
2887 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2888 {
2889 HOST_WIDE_INT addend;
2890 rtx symref;
2891
2892 if (!s390_symref_operand_p (addr, &symref, &addend))
2893 gcc_unreachable ();
2894
2895 if (!(addend & 1))
2896 /* Easy case. The addend is even so larl will do fine. */
2897 emit_move_insn (reg, addr);
2898 else
2899 {
2900 /* We can leave the scratch register untouched if the target
2901 register is a valid base register. */
2902 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2903 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2904 scratch = reg;
2905
2906 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2907 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2908
2909 if (addend != 1)
2910 emit_move_insn (scratch,
2911 gen_rtx_CONST (Pmode,
2912 gen_rtx_PLUS (Pmode, symref,
2913 GEN_INT (addend - 1))));
2914 else
2915 emit_move_insn (scratch, symref);
2916
2917 /* Increment the address using la in order to avoid clobbering cc. */
2918 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2919 }
2920 }
2921
2922 /* Generate what is necessary to move between REG and MEM using
2923 SCRATCH. The direction is given by TOMEM. */
2924
2925 void
2926 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2927 {
2928 /* Reload might have pulled a constant out of the literal pool.
2929 Force it back in. */
2930 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2931 || GET_CODE (mem) == CONST)
2932 mem = force_const_mem (GET_MODE (reg), mem);
2933
2934 gcc_assert (MEM_P (mem));
2935
2936 /* For a load from memory we can leave the scratch register
2937 untouched if the target register is a valid base register. */
2938 if (!tomem
2939 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2940 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2941 && GET_MODE (reg) == GET_MODE (scratch))
2942 scratch = reg;
2943
2944 /* Load address into scratch register. Since we can't have a
2945 secondary reload for a secondary reload we have to cover the case
2946 where larl would need a secondary reload here as well. */
2947 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2948
2949 /* Now we can use a standard load/store to do the move. */
2950 if (tomem)
2951 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2952 else
2953 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2954 }
2955
2956 /* Inform reload about cases where moving X with a mode MODE to a register in
2957 RCLASS requires an extra scratch or immediate register. Return the class
2958 needed for the immediate register. */
2959
2960 static reg_class_t
2961 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
2962 enum machine_mode mode, secondary_reload_info *sri)
2963 {
2964 enum reg_class rclass = (enum reg_class) rclass_i;
2965
2966 /* Intermediate register needed. */
2967 if (reg_classes_intersect_p (CC_REGS, rclass))
2968 return GENERAL_REGS;
2969
2970 if (TARGET_Z10)
2971 {
2972 /* On z10 several optimizer steps may generate larl operands with
2973 an odd addend. */
2974 if (in_p
2975 && s390_symref_operand_p (x, NULL, NULL)
2976 && mode == Pmode
2977 && !s390_check_symref_alignment (x, 2))
2978 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2979 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2980
2981 /* On z10 we need a scratch register when moving QI, TI or floating
2982 point mode values from or to a memory location with a SYMBOL_REF
2983 or if the symref addend of a SI or DI move is not aligned to the
2984 width of the access. */
2985 if (MEM_P (x)
2986 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2987 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2988 || (!TARGET_ZARCH && mode == DImode)
2989 || ((mode == HImode || mode == SImode || mode == DImode)
2990 && (!s390_check_symref_alignment (XEXP (x, 0),
2991 GET_MODE_SIZE (mode))))))
2992 {
2993 #define __SECONDARY_RELOAD_CASE(M,m) \
2994 case M##mode: \
2995 if (TARGET_64BIT) \
2996 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2997 CODE_FOR_reload##m##di_tomem_z10; \
2998 else \
2999 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3000 CODE_FOR_reload##m##si_tomem_z10; \
3001 break;
3002
3003 switch (GET_MODE (x))
3004 {
3005 __SECONDARY_RELOAD_CASE (QI, qi);
3006 __SECONDARY_RELOAD_CASE (HI, hi);
3007 __SECONDARY_RELOAD_CASE (SI, si);
3008 __SECONDARY_RELOAD_CASE (DI, di);
3009 __SECONDARY_RELOAD_CASE (TI, ti);
3010 __SECONDARY_RELOAD_CASE (SF, sf);
3011 __SECONDARY_RELOAD_CASE (DF, df);
3012 __SECONDARY_RELOAD_CASE (TF, tf);
3013 __SECONDARY_RELOAD_CASE (SD, sd);
3014 __SECONDARY_RELOAD_CASE (DD, dd);
3015 __SECONDARY_RELOAD_CASE (TD, td);
3016
3017 default:
3018 gcc_unreachable ();
3019 }
3020 #undef __SECONDARY_RELOAD_CASE
3021 }
3022 }
3023
3024 /* We need a scratch register when loading a PLUS expression which
3025 is not a legitimate operand of the LOAD ADDRESS instruction. */
3026 if (in_p && s390_plus_operand (x, mode))
3027 sri->icode = (TARGET_64BIT ?
3028 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3029
3030 /* Performing a multiword move from or to memory we have to make sure the
3031 second chunk in memory is addressable without causing a displacement
3032 overflow. If that would be the case we calculate the address in
3033 a scratch register. */
3034 if (MEM_P (x)
3035 && GET_CODE (XEXP (x, 0)) == PLUS
3036 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3037 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3038 + GET_MODE_SIZE (mode) - 1))
3039 {
3040 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3041 in a s_operand address since we may fallback to lm/stm. So we only
3042 have to care about overflows in the b+i+d case. */
3043 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3044 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3045 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3046 /* For FP_REGS no lm/stm is available so this check is triggered
3047 for displacement overflows in b+i+d and b+d like addresses. */
3048 || (reg_classes_intersect_p (FP_REGS, rclass)
3049 && s390_class_max_nregs (FP_REGS, mode) > 1))
3050 {
3051 if (in_p)
3052 sri->icode = (TARGET_64BIT ?
3053 CODE_FOR_reloaddi_nonoffmem_in :
3054 CODE_FOR_reloadsi_nonoffmem_in);
3055 else
3056 sri->icode = (TARGET_64BIT ?
3057 CODE_FOR_reloaddi_nonoffmem_out :
3058 CODE_FOR_reloadsi_nonoffmem_out);
3059 }
3060 }
3061
3062 /* A scratch address register is needed when a symbolic constant is
3063 copied to r0 compiling with -fPIC. In other cases the target
3064 register might be used as temporary (see legitimize_pic_address). */
3065 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3066 sri->icode = (TARGET_64BIT ?
3067 CODE_FOR_reloaddi_PIC_addr :
3068 CODE_FOR_reloadsi_PIC_addr);
3069
3070 /* Either scratch or no register needed. */
3071 return NO_REGS;
3072 }
3073
3074 /* Generate code to load SRC, which is PLUS that is not a
3075 legitimate operand for the LA instruction, into TARGET.
3076 SCRATCH may be used as scratch register. */
3077
3078 void
3079 s390_expand_plus_operand (rtx target, rtx src,
3080 rtx scratch)
3081 {
3082 rtx sum1, sum2;
3083 struct s390_address ad;
3084
3085 /* src must be a PLUS; get its two operands. */
3086 gcc_assert (GET_CODE (src) == PLUS);
3087 gcc_assert (GET_MODE (src) == Pmode);
3088
3089 /* Check if any of the two operands is already scheduled
3090 for replacement by reload. This can happen e.g. when
3091 float registers occur in an address. */
3092 sum1 = find_replacement (&XEXP (src, 0));
3093 sum2 = find_replacement (&XEXP (src, 1));
3094 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3095
3096 /* If the address is already strictly valid, there's nothing to do. */
3097 if (!s390_decompose_address (src, &ad)
3098 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3099 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3100 {
3101 /* Otherwise, one of the operands cannot be an address register;
3102 we reload its value into the scratch register. */
3103 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3104 {
3105 emit_move_insn (scratch, sum1);
3106 sum1 = scratch;
3107 }
3108 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3109 {
3110 emit_move_insn (scratch, sum2);
3111 sum2 = scratch;
3112 }
3113
3114 /* According to the way these invalid addresses are generated
3115 in reload.c, it should never happen (at least on s390) that
3116 *neither* of the PLUS components, after find_replacements
3117 was applied, is an address register. */
3118 if (sum1 == scratch && sum2 == scratch)
3119 {
3120 debug_rtx (src);
3121 gcc_unreachable ();
3122 }
3123
3124 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3125 }
3126
3127 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3128 is only ever performed on addresses, so we can mark the
3129 sum as legitimate for LA in any case. */
3130 s390_load_address (target, src);
3131 }
3132
3133
3134 /* Return true if ADDR is a valid memory address.
3135 STRICT specifies whether strict register checking applies. */
3136
3137 static bool
3138 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3139 {
3140 struct s390_address ad;
3141
3142 if (TARGET_Z10
3143 && larl_operand (addr, VOIDmode)
3144 && (mode == VOIDmode
3145 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3146 return true;
3147
3148 if (!s390_decompose_address (addr, &ad))
3149 return false;
3150
3151 if (strict)
3152 {
3153 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3154 return false;
3155
3156 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3157 return false;
3158 }
3159 else
3160 {
3161 if (ad.base
3162 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3163 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3164 return false;
3165
3166 if (ad.indx
3167 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3168 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3169 return false;
3170 }
3171 return true;
3172 }
3173
3174 /* Return true if OP is a valid operand for the LA instruction.
3175 In 31-bit, we need to prove that the result is used as an
3176 address, as LA performs only a 31-bit addition. */
3177
3178 bool
3179 legitimate_la_operand_p (rtx op)
3180 {
3181 struct s390_address addr;
3182 if (!s390_decompose_address (op, &addr))
3183 return false;
3184
3185 return (TARGET_64BIT || addr.pointer);
3186 }
3187
3188 /* Return true if it is valid *and* preferable to use LA to
3189 compute the sum of OP1 and OP2. */
3190
3191 bool
3192 preferred_la_operand_p (rtx op1, rtx op2)
3193 {
3194 struct s390_address addr;
3195
3196 if (op2 != const0_rtx)
3197 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3198
3199 if (!s390_decompose_address (op1, &addr))
3200 return false;
3201 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3202 return false;
3203 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3204 return false;
3205
3206 if (!TARGET_64BIT && !addr.pointer)
3207 return false;
3208
3209 if (addr.pointer)
3210 return true;
3211
3212 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3213 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3214 return true;
3215
3216 return false;
3217 }
3218
3219 /* Emit a forced load-address operation to load SRC into DST.
3220 This will use the LOAD ADDRESS instruction even in situations
3221 where legitimate_la_operand_p (SRC) returns false. */
3222
3223 void
3224 s390_load_address (rtx dst, rtx src)
3225 {
3226 if (TARGET_64BIT)
3227 emit_move_insn (dst, src);
3228 else
3229 emit_insn (gen_force_la_31 (dst, src));
3230 }
3231
3232 /* Return a legitimate reference for ORIG (an address) using the
3233 register REG. If REG is 0, a new pseudo is generated.
3234
3235 There are two types of references that must be handled:
3236
3237 1. Global data references must load the address from the GOT, via
3238 the PIC reg. An insn is emitted to do this load, and the reg is
3239 returned.
3240
3241 2. Static data references, constant pool addresses, and code labels
3242 compute the address as an offset from the GOT, whose base is in
3243 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3244 differentiate them from global data objects. The returned
3245 address is the PIC reg + an unspec constant.
3246
3247 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3248 reg also appears in the address. */
3249
3250 rtx
3251 legitimize_pic_address (rtx orig, rtx reg)
3252 {
3253 rtx addr = orig;
3254 rtx new_rtx = orig;
3255 rtx base;
3256
3257 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3258
3259 if (GET_CODE (addr) == LABEL_REF
3260 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3261 {
3262 /* This is a local symbol. */
3263 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3264 {
3265 /* Access local symbols PC-relative via LARL.
3266 This is the same as in the non-PIC case, so it is
3267 handled automatically ... */
3268 }
3269 else
3270 {
3271 /* Access local symbols relative to the GOT. */
3272
3273 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3274
3275 if (reload_in_progress || reload_completed)
3276 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3277
3278 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3279 addr = gen_rtx_CONST (Pmode, addr);
3280 addr = force_const_mem (Pmode, addr);
3281 emit_move_insn (temp, addr);
3282
3283 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3284 if (reg != 0)
3285 {
3286 s390_load_address (reg, new_rtx);
3287 new_rtx = reg;
3288 }
3289 }
3290 }
3291 else if (GET_CODE (addr) == SYMBOL_REF)
3292 {
3293 if (reg == 0)
3294 reg = gen_reg_rtx (Pmode);
3295
3296 if (flag_pic == 1)
3297 {
3298 /* Assume GOT offset < 4k. This is handled the same way
3299 in both 31- and 64-bit code (@GOT). */
3300
3301 if (reload_in_progress || reload_completed)
3302 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3303
3304 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3305 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3306 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3307 new_rtx = gen_const_mem (Pmode, new_rtx);
3308 emit_move_insn (reg, new_rtx);
3309 new_rtx = reg;
3310 }
3311 else if (TARGET_CPU_ZARCH)
3312 {
3313 /* If the GOT offset might be >= 4k, we determine the position
3314 of the GOT entry via a PC-relative LARL (@GOTENT). */
3315
3316 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3317
3318 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3319 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3320
3321 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3322 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3323 emit_move_insn (temp, new_rtx);
3324
3325 new_rtx = gen_const_mem (Pmode, temp);
3326 emit_move_insn (reg, new_rtx);
3327 new_rtx = reg;
3328 }
3329 else
3330 {
3331 /* If the GOT offset might be >= 4k, we have to load it
3332 from the literal pool (@GOT). */
3333
3334 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3335
3336 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3337 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3338
3339 if (reload_in_progress || reload_completed)
3340 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3341
3342 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3343 addr = gen_rtx_CONST (Pmode, addr);
3344 addr = force_const_mem (Pmode, addr);
3345 emit_move_insn (temp, addr);
3346
3347 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3348 new_rtx = gen_const_mem (Pmode, new_rtx);
3349 emit_move_insn (reg, new_rtx);
3350 new_rtx = reg;
3351 }
3352 }
3353 else
3354 {
3355 if (GET_CODE (addr) == CONST)
3356 {
3357 addr = XEXP (addr, 0);
3358 if (GET_CODE (addr) == UNSPEC)
3359 {
3360 gcc_assert (XVECLEN (addr, 0) == 1);
3361 switch (XINT (addr, 1))
3362 {
3363 /* If someone moved a GOT-relative UNSPEC
3364 out of the literal pool, force them back in. */
3365 case UNSPEC_GOTOFF:
3366 case UNSPEC_PLTOFF:
3367 new_rtx = force_const_mem (Pmode, orig);
3368 break;
3369
3370 /* @GOT is OK as is if small. */
3371 case UNSPEC_GOT:
3372 if (flag_pic == 2)
3373 new_rtx = force_const_mem (Pmode, orig);
3374 break;
3375
3376 /* @GOTENT is OK as is. */
3377 case UNSPEC_GOTENT:
3378 break;
3379
3380 /* @PLT is OK as is on 64-bit, must be converted to
3381 GOT-relative @PLTOFF on 31-bit. */
3382 case UNSPEC_PLT:
3383 if (!TARGET_CPU_ZARCH)
3384 {
3385 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3386
3387 if (reload_in_progress || reload_completed)
3388 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3389
3390 addr = XVECEXP (addr, 0, 0);
3391 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3392 UNSPEC_PLTOFF);
3393 addr = gen_rtx_CONST (Pmode, addr);
3394 addr = force_const_mem (Pmode, addr);
3395 emit_move_insn (temp, addr);
3396
3397 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3398 if (reg != 0)
3399 {
3400 s390_load_address (reg, new_rtx);
3401 new_rtx = reg;
3402 }
3403 }
3404 break;
3405
3406 /* Everything else cannot happen. */
3407 default:
3408 gcc_unreachable ();
3409 }
3410 }
3411 else
3412 gcc_assert (GET_CODE (addr) == PLUS);
3413 }
3414 if (GET_CODE (addr) == PLUS)
3415 {
3416 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3417
3418 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3419 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3420
3421 /* Check first to see if this is a constant offset
3422 from a local symbol reference. */
3423 if ((GET_CODE (op0) == LABEL_REF
3424 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3425 && GET_CODE (op1) == CONST_INT)
3426 {
3427 if (TARGET_CPU_ZARCH
3428 && larl_operand (op0, VOIDmode)
3429 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3430 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3431 {
3432 if (INTVAL (op1) & 1)
3433 {
3434 /* LARL can't handle odd offsets, so emit a
3435 pair of LARL and LA. */
3436 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3437
3438 if (!DISP_IN_RANGE (INTVAL (op1)))
3439 {
3440 HOST_WIDE_INT even = INTVAL (op1) - 1;
3441 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3442 op0 = gen_rtx_CONST (Pmode, op0);
3443 op1 = const1_rtx;
3444 }
3445
3446 emit_move_insn (temp, op0);
3447 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3448
3449 if (reg != 0)
3450 {
3451 s390_load_address (reg, new_rtx);
3452 new_rtx = reg;
3453 }
3454 }
3455 else
3456 {
3457 /* If the offset is even, we can just use LARL.
3458 This will happen automatically. */
3459 }
3460 }
3461 else
3462 {
3463 /* Access local symbols relative to the GOT. */
3464
3465 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3466
3467 if (reload_in_progress || reload_completed)
3468 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3469
3470 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3471 UNSPEC_GOTOFF);
3472 addr = gen_rtx_PLUS (Pmode, addr, op1);
3473 addr = gen_rtx_CONST (Pmode, addr);
3474 addr = force_const_mem (Pmode, addr);
3475 emit_move_insn (temp, addr);
3476
3477 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3478 if (reg != 0)
3479 {
3480 s390_load_address (reg, new_rtx);
3481 new_rtx = reg;
3482 }
3483 }
3484 }
3485
3486 /* Now, check whether it is a GOT relative symbol plus offset
3487 that was pulled out of the literal pool. Force it back in. */
3488
3489 else if (GET_CODE (op0) == UNSPEC
3490 && GET_CODE (op1) == CONST_INT
3491 && XINT (op0, 1) == UNSPEC_GOTOFF)
3492 {
3493 gcc_assert (XVECLEN (op0, 0) == 1);
3494
3495 new_rtx = force_const_mem (Pmode, orig);
3496 }
3497
3498 /* Otherwise, compute the sum. */
3499 else
3500 {
3501 base = legitimize_pic_address (XEXP (addr, 0), reg);
3502 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3503 base == reg ? NULL_RTX : reg);
3504 if (GET_CODE (new_rtx) == CONST_INT)
3505 new_rtx = plus_constant (base, INTVAL (new_rtx));
3506 else
3507 {
3508 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3509 {
3510 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3511 new_rtx = XEXP (new_rtx, 1);
3512 }
3513 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3514 }
3515
3516 if (GET_CODE (new_rtx) == CONST)
3517 new_rtx = XEXP (new_rtx, 0);
3518 new_rtx = force_operand (new_rtx, 0);
3519 }
3520 }
3521 }
3522 return new_rtx;
3523 }
3524
3525 /* Load the thread pointer into a register. */
3526
3527 rtx
3528 s390_get_thread_pointer (void)
3529 {
3530 rtx tp = gen_reg_rtx (Pmode);
3531
3532 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3533 mark_reg_pointer (tp, BITS_PER_WORD);
3534
3535 return tp;
3536 }
3537
3538 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3539 in s390_tls_symbol which always refers to __tls_get_offset.
3540 The returned offset is written to RESULT_REG and an USE rtx is
3541 generated for TLS_CALL. */
3542
3543 static GTY(()) rtx s390_tls_symbol;
3544
3545 static void
3546 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3547 {
3548 rtx insn;
3549
3550 gcc_assert (flag_pic);
3551
3552 if (!s390_tls_symbol)
3553 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3554
3555 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3556 gen_rtx_REG (Pmode, RETURN_REGNUM));
3557
3558 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3559 RTL_CONST_CALL_P (insn) = 1;
3560 }
3561
3562 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3563 this (thread-local) address. REG may be used as temporary. */
3564
3565 static rtx
3566 legitimize_tls_address (rtx addr, rtx reg)
3567 {
3568 rtx new_rtx, tls_call, temp, base, r2, insn;
3569
3570 if (GET_CODE (addr) == SYMBOL_REF)
3571 switch (tls_symbolic_operand (addr))
3572 {
3573 case TLS_MODEL_GLOBAL_DYNAMIC:
3574 start_sequence ();
3575 r2 = gen_rtx_REG (Pmode, 2);
3576 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3577 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3578 new_rtx = force_const_mem (Pmode, new_rtx);
3579 emit_move_insn (r2, new_rtx);
3580 s390_emit_tls_call_insn (r2, tls_call);
3581 insn = get_insns ();
3582 end_sequence ();
3583
3584 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3585 temp = gen_reg_rtx (Pmode);
3586 emit_libcall_block (insn, temp, r2, new_rtx);
3587
3588 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3589 if (reg != 0)
3590 {
3591 s390_load_address (reg, new_rtx);
3592 new_rtx = reg;
3593 }
3594 break;
3595
3596 case TLS_MODEL_LOCAL_DYNAMIC:
3597 start_sequence ();
3598 r2 = gen_rtx_REG (Pmode, 2);
3599 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3600 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3601 new_rtx = force_const_mem (Pmode, new_rtx);
3602 emit_move_insn (r2, new_rtx);
3603 s390_emit_tls_call_insn (r2, tls_call);
3604 insn = get_insns ();
3605 end_sequence ();
3606
3607 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3608 temp = gen_reg_rtx (Pmode);
3609 emit_libcall_block (insn, temp, r2, new_rtx);
3610
3611 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3612 base = gen_reg_rtx (Pmode);
3613 s390_load_address (base, new_rtx);
3614
3615 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3616 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3617 new_rtx = force_const_mem (Pmode, new_rtx);
3618 temp = gen_reg_rtx (Pmode);
3619 emit_move_insn (temp, new_rtx);
3620
3621 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3622 if (reg != 0)
3623 {
3624 s390_load_address (reg, new_rtx);
3625 new_rtx = reg;
3626 }
3627 break;
3628
3629 case TLS_MODEL_INITIAL_EXEC:
3630 if (flag_pic == 1)
3631 {
3632 /* Assume GOT offset < 4k. This is handled the same way
3633 in both 31- and 64-bit code. */
3634
3635 if (reload_in_progress || reload_completed)
3636 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3637
3638 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3639 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3640 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3641 new_rtx = gen_const_mem (Pmode, new_rtx);
3642 temp = gen_reg_rtx (Pmode);
3643 emit_move_insn (temp, new_rtx);
3644 }
3645 else if (TARGET_CPU_ZARCH)
3646 {
3647 /* If the GOT offset might be >= 4k, we determine the position
3648 of the GOT entry via a PC-relative LARL. */
3649
3650 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3651 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3652 temp = gen_reg_rtx (Pmode);
3653 emit_move_insn (temp, new_rtx);
3654
3655 new_rtx = gen_const_mem (Pmode, temp);
3656 temp = gen_reg_rtx (Pmode);
3657 emit_move_insn (temp, new_rtx);
3658 }
3659 else if (flag_pic)
3660 {
3661 /* If the GOT offset might be >= 4k, we have to load it
3662 from the literal pool. */
3663
3664 if (reload_in_progress || reload_completed)
3665 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3666
3667 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3668 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3669 new_rtx = force_const_mem (Pmode, new_rtx);
3670 temp = gen_reg_rtx (Pmode);
3671 emit_move_insn (temp, new_rtx);
3672
3673 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3674 new_rtx = gen_const_mem (Pmode, new_rtx);
3675
3676 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3677 temp = gen_reg_rtx (Pmode);
3678 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3679 }
3680 else
3681 {
3682 /* In position-dependent code, load the absolute address of
3683 the GOT entry from the literal pool. */
3684
3685 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3686 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3687 new_rtx = force_const_mem (Pmode, new_rtx);
3688 temp = gen_reg_rtx (Pmode);
3689 emit_move_insn (temp, new_rtx);
3690
3691 new_rtx = temp;
3692 new_rtx = gen_const_mem (Pmode, new_rtx);
3693 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3694 temp = gen_reg_rtx (Pmode);
3695 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3696 }
3697
3698 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3699 if (reg != 0)
3700 {
3701 s390_load_address (reg, new_rtx);
3702 new_rtx = reg;
3703 }
3704 break;
3705
3706 case TLS_MODEL_LOCAL_EXEC:
3707 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3708 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3709 new_rtx = force_const_mem (Pmode, new_rtx);
3710 temp = gen_reg_rtx (Pmode);
3711 emit_move_insn (temp, new_rtx);
3712
3713 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3714 if (reg != 0)
3715 {
3716 s390_load_address (reg, new_rtx);
3717 new_rtx = reg;
3718 }
3719 break;
3720
3721 default:
3722 gcc_unreachable ();
3723 }
3724
3725 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3726 {
3727 switch (XINT (XEXP (addr, 0), 1))
3728 {
3729 case UNSPEC_INDNTPOFF:
3730 gcc_assert (TARGET_CPU_ZARCH);
3731 new_rtx = addr;
3732 break;
3733
3734 default:
3735 gcc_unreachable ();
3736 }
3737 }
3738
3739 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3740 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3741 {
3742 new_rtx = XEXP (XEXP (addr, 0), 0);
3743 if (GET_CODE (new_rtx) != SYMBOL_REF)
3744 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3745
3746 new_rtx = legitimize_tls_address (new_rtx, reg);
3747 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3748 new_rtx = force_operand (new_rtx, 0);
3749 }
3750
3751 else
3752 gcc_unreachable (); /* for now ... */
3753
3754 return new_rtx;
3755 }
3756
3757 /* Emit insns making the address in operands[1] valid for a standard
3758 move to operands[0]. operands[1] is replaced by an address which
3759 should be used instead of the former RTX to emit the move
3760 pattern. */
3761
3762 void
3763 emit_symbolic_move (rtx *operands)
3764 {
3765 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3766
3767 if (GET_CODE (operands[0]) == MEM)
3768 operands[1] = force_reg (Pmode, operands[1]);
3769 else if (TLS_SYMBOLIC_CONST (operands[1]))
3770 operands[1] = legitimize_tls_address (operands[1], temp);
3771 else if (flag_pic)
3772 operands[1] = legitimize_pic_address (operands[1], temp);
3773 }
3774
3775 /* Try machine-dependent ways of modifying an illegitimate address X
3776 to be legitimate. If we find one, return the new, valid address.
3777
3778 OLDX is the address as it was before break_out_memory_refs was called.
3779 In some cases it is useful to look at this to decide what needs to be done.
3780
3781 MODE is the mode of the operand pointed to by X.
3782
3783 When -fpic is used, special handling is needed for symbolic references.
3784 See comments by legitimize_pic_address for details. */
3785
3786 static rtx
3787 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3788 enum machine_mode mode ATTRIBUTE_UNUSED)
3789 {
3790 rtx constant_term = const0_rtx;
3791
3792 if (TLS_SYMBOLIC_CONST (x))
3793 {
3794 x = legitimize_tls_address (x, 0);
3795
3796 if (s390_legitimate_address_p (mode, x, FALSE))
3797 return x;
3798 }
3799 else if (GET_CODE (x) == PLUS
3800 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3801 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3802 {
3803 return x;
3804 }
3805 else if (flag_pic)
3806 {
3807 if (SYMBOLIC_CONST (x)
3808 || (GET_CODE (x) == PLUS
3809 && (SYMBOLIC_CONST (XEXP (x, 0))
3810 || SYMBOLIC_CONST (XEXP (x, 1)))))
3811 x = legitimize_pic_address (x, 0);
3812
3813 if (s390_legitimate_address_p (mode, x, FALSE))
3814 return x;
3815 }
3816
3817 x = eliminate_constant_term (x, &constant_term);
3818
3819 /* Optimize loading of large displacements by splitting them
3820 into the multiple of 4K and the rest; this allows the
3821 former to be CSE'd if possible.
3822
3823 Don't do this if the displacement is added to a register
3824 pointing into the stack frame, as the offsets will
3825 change later anyway. */
3826
3827 if (GET_CODE (constant_term) == CONST_INT
3828 && !TARGET_LONG_DISPLACEMENT
3829 && !DISP_IN_RANGE (INTVAL (constant_term))
3830 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3831 {
3832 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3833 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3834
3835 rtx temp = gen_reg_rtx (Pmode);
3836 rtx val = force_operand (GEN_INT (upper), temp);
3837 if (val != temp)
3838 emit_move_insn (temp, val);
3839
3840 x = gen_rtx_PLUS (Pmode, x, temp);
3841 constant_term = GEN_INT (lower);
3842 }
3843
3844 if (GET_CODE (x) == PLUS)
3845 {
3846 if (GET_CODE (XEXP (x, 0)) == REG)
3847 {
3848 rtx temp = gen_reg_rtx (Pmode);
3849 rtx val = force_operand (XEXP (x, 1), temp);
3850 if (val != temp)
3851 emit_move_insn (temp, val);
3852
3853 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3854 }
3855
3856 else if (GET_CODE (XEXP (x, 1)) == REG)
3857 {
3858 rtx temp = gen_reg_rtx (Pmode);
3859 rtx val = force_operand (XEXP (x, 0), temp);
3860 if (val != temp)
3861 emit_move_insn (temp, val);
3862
3863 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3864 }
3865 }
3866
3867 if (constant_term != const0_rtx)
3868 x = gen_rtx_PLUS (Pmode, x, constant_term);
3869
3870 return x;
3871 }
3872
3873 /* Try a machine-dependent way of reloading an illegitimate address AD
3874 operand. If we find one, push the reload and and return the new address.
3875
3876 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3877 and TYPE is the reload type of the current reload. */
3878
3879 rtx
3880 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3881 int opnum, int type)
3882 {
3883 if (!optimize || TARGET_LONG_DISPLACEMENT)
3884 return NULL_RTX;
3885
3886 if (GET_CODE (ad) == PLUS)
3887 {
3888 rtx tem = simplify_binary_operation (PLUS, Pmode,
3889 XEXP (ad, 0), XEXP (ad, 1));
3890 if (tem)
3891 ad = tem;
3892 }
3893
3894 if (GET_CODE (ad) == PLUS
3895 && GET_CODE (XEXP (ad, 0)) == REG
3896 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3897 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3898 {
3899 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3900 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3901 rtx cst, tem, new_rtx;
3902
3903 cst = GEN_INT (upper);
3904 if (!legitimate_reload_constant_p (cst))
3905 cst = force_const_mem (Pmode, cst);
3906
3907 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3908 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3909
3910 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3911 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3912 opnum, (enum reload_type) type);
3913 return new_rtx;
3914 }
3915
3916 return NULL_RTX;
3917 }
3918
3919 /* Emit code to move LEN bytes from DST to SRC. */
3920
3921 void
3922 s390_expand_movmem (rtx dst, rtx src, rtx len)
3923 {
3924 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3925 {
3926 if (INTVAL (len) > 0)
3927 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3928 }
3929
3930 else if (TARGET_MVCLE)
3931 {
3932 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3933 }
3934
3935 else
3936 {
3937 rtx dst_addr, src_addr, count, blocks, temp;
3938 rtx loop_start_label = gen_label_rtx ();
3939 rtx loop_end_label = gen_label_rtx ();
3940 rtx end_label = gen_label_rtx ();
3941 enum machine_mode mode;
3942
3943 mode = GET_MODE (len);
3944 if (mode == VOIDmode)
3945 mode = Pmode;
3946
3947 dst_addr = gen_reg_rtx (Pmode);
3948 src_addr = gen_reg_rtx (Pmode);
3949 count = gen_reg_rtx (mode);
3950 blocks = gen_reg_rtx (mode);
3951
3952 convert_move (count, len, 1);
3953 emit_cmp_and_jump_insns (count, const0_rtx,
3954 EQ, NULL_RTX, mode, 1, end_label);
3955
3956 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3957 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3958 dst = change_address (dst, VOIDmode, dst_addr);
3959 src = change_address (src, VOIDmode, src_addr);
3960
3961 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3962 OPTAB_DIRECT);
3963 if (temp != count)
3964 emit_move_insn (count, temp);
3965
3966 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3967 OPTAB_DIRECT);
3968 if (temp != blocks)
3969 emit_move_insn (blocks, temp);
3970
3971 emit_cmp_and_jump_insns (blocks, const0_rtx,
3972 EQ, NULL_RTX, mode, 1, loop_end_label);
3973
3974 emit_label (loop_start_label);
3975
3976 if (TARGET_Z10
3977 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
3978 {
3979 rtx prefetch;
3980
3981 /* Issue a read prefetch for the +3 cache line. */
3982 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
3983 const0_rtx, const0_rtx);
3984 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3985 emit_insn (prefetch);
3986
3987 /* Issue a write prefetch for the +3 cache line. */
3988 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
3989 const1_rtx, const0_rtx);
3990 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
3991 emit_insn (prefetch);
3992 }
3993
3994 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3995 s390_load_address (dst_addr,
3996 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3997 s390_load_address (src_addr,
3998 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3999
4000 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4001 OPTAB_DIRECT);
4002 if (temp != blocks)
4003 emit_move_insn (blocks, temp);
4004
4005 emit_cmp_and_jump_insns (blocks, const0_rtx,
4006 EQ, NULL_RTX, mode, 1, loop_end_label);
4007
4008 emit_jump (loop_start_label);
4009 emit_label (loop_end_label);
4010
4011 emit_insn (gen_movmem_short (dst, src,
4012 convert_to_mode (Pmode, count, 1)));
4013 emit_label (end_label);
4014 }
4015 }
4016
4017 /* Emit code to set LEN bytes at DST to VAL.
4018 Make use of clrmem if VAL is zero. */
4019
4020 void
4021 s390_expand_setmem (rtx dst, rtx len, rtx val)
4022 {
4023 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4024 return;
4025
4026 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4027
4028 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4029 {
4030 if (val == const0_rtx && INTVAL (len) <= 256)
4031 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4032 else
4033 {
4034 /* Initialize memory by storing the first byte. */
4035 emit_move_insn (adjust_address (dst, QImode, 0), val);
4036
4037 if (INTVAL (len) > 1)
4038 {
4039 /* Initiate 1 byte overlap move.
4040 The first byte of DST is propagated through DSTP1.
4041 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4042 DST is set to size 1 so the rest of the memory location
4043 does not count as source operand. */
4044 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4045 set_mem_size (dst, const1_rtx);
4046
4047 emit_insn (gen_movmem_short (dstp1, dst,
4048 GEN_INT (INTVAL (len) - 2)));
4049 }
4050 }
4051 }
4052
4053 else if (TARGET_MVCLE)
4054 {
4055 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4056 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4057 }
4058
4059 else
4060 {
4061 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4062 rtx loop_start_label = gen_label_rtx ();
4063 rtx loop_end_label = gen_label_rtx ();
4064 rtx end_label = gen_label_rtx ();
4065 enum machine_mode mode;
4066
4067 mode = GET_MODE (len);
4068 if (mode == VOIDmode)
4069 mode = Pmode;
4070
4071 dst_addr = gen_reg_rtx (Pmode);
4072 count = gen_reg_rtx (mode);
4073 blocks = gen_reg_rtx (mode);
4074
4075 convert_move (count, len, 1);
4076 emit_cmp_and_jump_insns (count, const0_rtx,
4077 EQ, NULL_RTX, mode, 1, end_label);
4078
4079 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4080 dst = change_address (dst, VOIDmode, dst_addr);
4081
4082 if (val == const0_rtx)
4083 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4084 OPTAB_DIRECT);
4085 else
4086 {
4087 dstp1 = adjust_address (dst, VOIDmode, 1);
4088 set_mem_size (dst, const1_rtx);
4089
4090 /* Initialize memory by storing the first byte. */
4091 emit_move_insn (adjust_address (dst, QImode, 0), val);
4092
4093 /* If count is 1 we are done. */
4094 emit_cmp_and_jump_insns (count, const1_rtx,
4095 EQ, NULL_RTX, mode, 1, end_label);
4096
4097 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4098 OPTAB_DIRECT);
4099 }
4100 if (temp != count)
4101 emit_move_insn (count, temp);
4102
4103 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4104 OPTAB_DIRECT);
4105 if (temp != blocks)
4106 emit_move_insn (blocks, temp);
4107
4108 emit_cmp_and_jump_insns (blocks, const0_rtx,
4109 EQ, NULL_RTX, mode, 1, loop_end_label);
4110
4111 emit_label (loop_start_label);
4112
4113 if (TARGET_Z10
4114 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4115 {
4116 /* Issue a write prefetch for the +4 cache line. */
4117 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4118 GEN_INT (1024)),
4119 const1_rtx, const0_rtx);
4120 emit_insn (prefetch);
4121 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4122 }
4123
4124 if (val == const0_rtx)
4125 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4126 else
4127 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4128 s390_load_address (dst_addr,
4129 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4130
4131 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4132 OPTAB_DIRECT);
4133 if (temp != blocks)
4134 emit_move_insn (blocks, temp);
4135
4136 emit_cmp_and_jump_insns (blocks, const0_rtx,
4137 EQ, NULL_RTX, mode, 1, loop_end_label);
4138
4139 emit_jump (loop_start_label);
4140 emit_label (loop_end_label);
4141
4142 if (val == const0_rtx)
4143 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4144 else
4145 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4146 emit_label (end_label);
4147 }
4148 }
4149
4150 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4151 and return the result in TARGET. */
4152
4153 void
4154 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4155 {
4156 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4157 rtx tmp;
4158
4159 /* As the result of CMPINT is inverted compared to what we need,
4160 we have to swap the operands. */
4161 tmp = op0; op0 = op1; op1 = tmp;
4162
4163 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4164 {
4165 if (INTVAL (len) > 0)
4166 {
4167 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4168 emit_insn (gen_cmpint (target, ccreg));
4169 }
4170 else
4171 emit_move_insn (target, const0_rtx);
4172 }
4173 else if (TARGET_MVCLE)
4174 {
4175 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4176 emit_insn (gen_cmpint (target, ccreg));
4177 }
4178 else
4179 {
4180 rtx addr0, addr1, count, blocks, temp;
4181 rtx loop_start_label = gen_label_rtx ();
4182 rtx loop_end_label = gen_label_rtx ();
4183 rtx end_label = gen_label_rtx ();
4184 enum machine_mode mode;
4185
4186 mode = GET_MODE (len);
4187 if (mode == VOIDmode)
4188 mode = Pmode;
4189
4190 addr0 = gen_reg_rtx (Pmode);
4191 addr1 = gen_reg_rtx (Pmode);
4192 count = gen_reg_rtx (mode);
4193 blocks = gen_reg_rtx (mode);
4194
4195 convert_move (count, len, 1);
4196 emit_cmp_and_jump_insns (count, const0_rtx,
4197 EQ, NULL_RTX, mode, 1, end_label);
4198
4199 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4200 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4201 op0 = change_address (op0, VOIDmode, addr0);
4202 op1 = change_address (op1, VOIDmode, addr1);
4203
4204 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4205 OPTAB_DIRECT);
4206 if (temp != count)
4207 emit_move_insn (count, temp);
4208
4209 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4210 OPTAB_DIRECT);
4211 if (temp != blocks)
4212 emit_move_insn (blocks, temp);
4213
4214 emit_cmp_and_jump_insns (blocks, const0_rtx,
4215 EQ, NULL_RTX, mode, 1, loop_end_label);
4216
4217 emit_label (loop_start_label);
4218
4219 if (TARGET_Z10
4220 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4221 {
4222 rtx prefetch;
4223
4224 /* Issue a read prefetch for the +2 cache line of operand 1. */
4225 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4226 const0_rtx, const0_rtx);
4227 emit_insn (prefetch);
4228 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4229
4230 /* Issue a read prefetch for the +2 cache line of operand 2. */
4231 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4232 const0_rtx, const0_rtx);
4233 emit_insn (prefetch);
4234 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4235 }
4236
4237 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4238 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4239 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4240 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4241 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4242 emit_jump_insn (temp);
4243
4244 s390_load_address (addr0,
4245 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4246 s390_load_address (addr1,
4247 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4248
4249 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4250 OPTAB_DIRECT);
4251 if (temp != blocks)
4252 emit_move_insn (blocks, temp);
4253
4254 emit_cmp_and_jump_insns (blocks, const0_rtx,
4255 EQ, NULL_RTX, mode, 1, loop_end_label);
4256
4257 emit_jump (loop_start_label);
4258 emit_label (loop_end_label);
4259
4260 emit_insn (gen_cmpmem_short (op0, op1,
4261 convert_to_mode (Pmode, count, 1)));
4262 emit_label (end_label);
4263
4264 emit_insn (gen_cmpint (target, ccreg));
4265 }
4266 }
4267
4268
4269 /* Expand conditional increment or decrement using alc/slb instructions.
4270 Should generate code setting DST to either SRC or SRC + INCREMENT,
4271 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4272 Returns true if successful, false otherwise.
4273
4274 That makes it possible to implement some if-constructs without jumps e.g.:
4275 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4276 unsigned int a, b, c;
4277 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4278 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4279 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4280 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4281
4282 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4283 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4284 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4285 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4286 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4287
4288 bool
4289 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4290 rtx dst, rtx src, rtx increment)
4291 {
4292 enum machine_mode cmp_mode;
4293 enum machine_mode cc_mode;
4294 rtx op_res;
4295 rtx insn;
4296 rtvec p;
4297 int ret;
4298
4299 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4300 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4301 cmp_mode = SImode;
4302 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4303 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4304 cmp_mode = DImode;
4305 else
4306 return false;
4307
4308 /* Try ADD LOGICAL WITH CARRY. */
4309 if (increment == const1_rtx)
4310 {
4311 /* Determine CC mode to use. */
4312 if (cmp_code == EQ || cmp_code == NE)
4313 {
4314 if (cmp_op1 != const0_rtx)
4315 {
4316 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4317 NULL_RTX, 0, OPTAB_WIDEN);
4318 cmp_op1 = const0_rtx;
4319 }
4320
4321 cmp_code = cmp_code == EQ ? LEU : GTU;
4322 }
4323
4324 if (cmp_code == LTU || cmp_code == LEU)
4325 {
4326 rtx tem = cmp_op0;
4327 cmp_op0 = cmp_op1;
4328 cmp_op1 = tem;
4329 cmp_code = swap_condition (cmp_code);
4330 }
4331
4332 switch (cmp_code)
4333 {
4334 case GTU:
4335 cc_mode = CCUmode;
4336 break;
4337
4338 case GEU:
4339 cc_mode = CCL3mode;
4340 break;
4341
4342 default:
4343 return false;
4344 }
4345
4346 /* Emit comparison instruction pattern. */
4347 if (!register_operand (cmp_op0, cmp_mode))
4348 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4349
4350 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4351 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4352 /* We use insn_invalid_p here to add clobbers if required. */
4353 ret = insn_invalid_p (emit_insn (insn));
4354 gcc_assert (!ret);
4355
4356 /* Emit ALC instruction pattern. */
4357 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4358 gen_rtx_REG (cc_mode, CC_REGNUM),
4359 const0_rtx);
4360
4361 if (src != const0_rtx)
4362 {
4363 if (!register_operand (src, GET_MODE (dst)))
4364 src = force_reg (GET_MODE (dst), src);
4365
4366 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4367 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4368 }
4369
4370 p = rtvec_alloc (2);
4371 RTVEC_ELT (p, 0) =
4372 gen_rtx_SET (VOIDmode, dst, op_res);
4373 RTVEC_ELT (p, 1) =
4374 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4375 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4376
4377 return true;
4378 }
4379
4380 /* Try SUBTRACT LOGICAL WITH BORROW. */
4381 if (increment == constm1_rtx)
4382 {
4383 /* Determine CC mode to use. */
4384 if (cmp_code == EQ || cmp_code == NE)
4385 {
4386 if (cmp_op1 != const0_rtx)
4387 {
4388 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4389 NULL_RTX, 0, OPTAB_WIDEN);
4390 cmp_op1 = const0_rtx;
4391 }
4392
4393 cmp_code = cmp_code == EQ ? LEU : GTU;
4394 }
4395
4396 if (cmp_code == GTU || cmp_code == GEU)
4397 {
4398 rtx tem = cmp_op0;
4399 cmp_op0 = cmp_op1;
4400 cmp_op1 = tem;
4401 cmp_code = swap_condition (cmp_code);
4402 }
4403
4404 switch (cmp_code)
4405 {
4406 case LEU:
4407 cc_mode = CCUmode;
4408 break;
4409
4410 case LTU:
4411 cc_mode = CCL3mode;
4412 break;
4413
4414 default:
4415 return false;
4416 }
4417
4418 /* Emit comparison instruction pattern. */
4419 if (!register_operand (cmp_op0, cmp_mode))
4420 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4421
4422 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4423 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4424 /* We use insn_invalid_p here to add clobbers if required. */
4425 ret = insn_invalid_p (emit_insn (insn));
4426 gcc_assert (!ret);
4427
4428 /* Emit SLB instruction pattern. */
4429 if (!register_operand (src, GET_MODE (dst)))
4430 src = force_reg (GET_MODE (dst), src);
4431
4432 op_res = gen_rtx_MINUS (GET_MODE (dst),
4433 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4434 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4435 gen_rtx_REG (cc_mode, CC_REGNUM),
4436 const0_rtx));
4437 p = rtvec_alloc (2);
4438 RTVEC_ELT (p, 0) =
4439 gen_rtx_SET (VOIDmode, dst, op_res);
4440 RTVEC_ELT (p, 1) =
4441 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4442 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4443
4444 return true;
4445 }
4446
4447 return false;
4448 }
4449
4450 /* Expand code for the insv template. Return true if successful. */
4451
4452 bool
4453 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4454 {
4455 int bitsize = INTVAL (op1);
4456 int bitpos = INTVAL (op2);
4457
4458 /* On z10 we can use the risbg instruction to implement insv. */
4459 if (TARGET_Z10
4460 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4461 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4462 {
4463 rtx op;
4464 rtx clobber;
4465
4466 op = gen_rtx_SET (GET_MODE(src),
4467 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4468 src);
4469 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4470 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4471
4472 return true;
4473 }
4474
4475 /* We need byte alignment. */
4476 if (bitsize % BITS_PER_UNIT)
4477 return false;
4478
4479 if (bitpos == 0
4480 && memory_operand (dest, VOIDmode)
4481 && (register_operand (src, word_mode)
4482 || const_int_operand (src, VOIDmode)))
4483 {
4484 /* Emit standard pattern if possible. */
4485 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4486 if (GET_MODE_BITSIZE (mode) == bitsize)
4487 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4488
4489 /* (set (ze (mem)) (const_int)). */
4490 else if (const_int_operand (src, VOIDmode))
4491 {
4492 int size = bitsize / BITS_PER_UNIT;
4493 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4494 GET_MODE_SIZE (word_mode) - size);
4495
4496 dest = adjust_address (dest, BLKmode, 0);
4497 set_mem_size (dest, GEN_INT (size));
4498 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4499 }
4500
4501 /* (set (ze (mem)) (reg)). */
4502 else if (register_operand (src, word_mode))
4503 {
4504 if (bitsize <= GET_MODE_BITSIZE (SImode))
4505 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4506 const0_rtx), src);
4507 else
4508 {
4509 /* Emit st,stcmh sequence. */
4510 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4511 int size = stcmh_width / BITS_PER_UNIT;
4512
4513 emit_move_insn (adjust_address (dest, SImode, size),
4514 gen_lowpart (SImode, src));
4515 set_mem_size (dest, GEN_INT (size));
4516 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4517 (stcmh_width), const0_rtx),
4518 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4519 (GET_MODE_BITSIZE (SImode))));
4520 }
4521 }
4522 else
4523 return false;
4524
4525 return true;
4526 }
4527
4528 /* (set (ze (reg)) (const_int)). */
4529 if (TARGET_ZARCH
4530 && register_operand (dest, word_mode)
4531 && (bitpos % 16) == 0
4532 && (bitsize % 16) == 0
4533 && const_int_operand (src, VOIDmode))
4534 {
4535 HOST_WIDE_INT val = INTVAL (src);
4536 int regpos = bitpos + bitsize;
4537
4538 while (regpos > bitpos)
4539 {
4540 enum machine_mode putmode;
4541 int putsize;
4542
4543 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4544 putmode = SImode;
4545 else
4546 putmode = HImode;
4547
4548 putsize = GET_MODE_BITSIZE (putmode);
4549 regpos -= putsize;
4550 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4551 GEN_INT (putsize),
4552 GEN_INT (regpos)),
4553 gen_int_mode (val, putmode));
4554 val >>= putsize;
4555 }
4556 gcc_assert (regpos == bitpos);
4557 return true;
4558 }
4559
4560 return false;
4561 }
4562
4563 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4564 register that holds VAL of mode MODE shifted by COUNT bits. */
4565
4566 static inline rtx
4567 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4568 {
4569 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4570 NULL_RTX, 1, OPTAB_DIRECT);
4571 return expand_simple_binop (SImode, ASHIFT, val, count,
4572 NULL_RTX, 1, OPTAB_DIRECT);
4573 }
4574
4575 /* Structure to hold the initial parameters for a compare_and_swap operation
4576 in HImode and QImode. */
4577
4578 struct alignment_context
4579 {
4580 rtx memsi; /* SI aligned memory location. */
4581 rtx shift; /* Bit offset with regard to lsb. */
4582 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4583 rtx modemaski; /* ~modemask */
4584 bool aligned; /* True if memory is aligned, false else. */
4585 };
4586
4587 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4588 structure AC for transparent simplifying, if the memory alignment is known
4589 to be at least 32bit. MEM is the memory location for the actual operation
4590 and MODE its mode. */
4591
4592 static void
4593 init_alignment_context (struct alignment_context *ac, rtx mem,
4594 enum machine_mode mode)
4595 {
4596 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4597 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4598
4599 if (ac->aligned)
4600 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4601 else
4602 {
4603 /* Alignment is unknown. */
4604 rtx byteoffset, addr, align;
4605
4606 /* Force the address into a register. */
4607 addr = force_reg (Pmode, XEXP (mem, 0));
4608
4609 /* Align it to SImode. */
4610 align = expand_simple_binop (Pmode, AND, addr,
4611 GEN_INT (-GET_MODE_SIZE (SImode)),
4612 NULL_RTX, 1, OPTAB_DIRECT);
4613 /* Generate MEM. */
4614 ac->memsi = gen_rtx_MEM (SImode, align);
4615 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4616 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4617 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4618
4619 /* Calculate shiftcount. */
4620 byteoffset = expand_simple_binop (Pmode, AND, addr,
4621 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4622 NULL_RTX, 1, OPTAB_DIRECT);
4623 /* As we already have some offset, evaluate the remaining distance. */
4624 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4625 NULL_RTX, 1, OPTAB_DIRECT);
4626
4627 }
4628 /* Shift is the byte count, but we need the bitcount. */
4629 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4630 NULL_RTX, 1, OPTAB_DIRECT);
4631 /* Calculate masks. */
4632 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4633 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4634 NULL_RTX, 1, OPTAB_DIRECT);
4635 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4636 }
4637
4638 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4639 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4640 to set if CMP == MEM.
4641 CMP is never in memory for compare_and_swap_cc because
4642 expand_bool_compare_and_swap puts it into a register for later compare. */
4643
4644 void
4645 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4646 {
4647 struct alignment_context ac;
4648 rtx cmpv, newv, val, resv, cc;
4649 rtx res = gen_reg_rtx (SImode);
4650 rtx csloop = gen_label_rtx ();
4651 rtx csend = gen_label_rtx ();
4652
4653 gcc_assert (register_operand (target, VOIDmode));
4654 gcc_assert (MEM_P (mem));
4655
4656 init_alignment_context (&ac, mem, mode);
4657
4658 /* Shift the values to the correct bit positions. */
4659 if (!(ac.aligned && MEM_P (cmp)))
4660 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4661 if (!(ac.aligned && MEM_P (new_rtx)))
4662 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4663
4664 /* Load full word. Subsequent loads are performed by CS. */
4665 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4666 NULL_RTX, 1, OPTAB_DIRECT);
4667
4668 /* Start CS loop. */
4669 emit_label (csloop);
4670 /* val = "<mem>00..0<mem>"
4671 * cmp = "00..0<cmp>00..0"
4672 * new = "00..0<new>00..0"
4673 */
4674
4675 /* Patch cmp and new with val at correct position. */
4676 if (ac.aligned && MEM_P (cmp))
4677 {
4678 cmpv = force_reg (SImode, val);
4679 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4680 }
4681 else
4682 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4683 NULL_RTX, 1, OPTAB_DIRECT));
4684 if (ac.aligned && MEM_P (new_rtx))
4685 {
4686 newv = force_reg (SImode, val);
4687 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4688 }
4689 else
4690 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4691 NULL_RTX, 1, OPTAB_DIRECT));
4692
4693 /* Jump to end if we're done (likely?). */
4694 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4695 cmpv, newv));
4696
4697 /* Check for changes outside mode. */
4698 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4699 NULL_RTX, 1, OPTAB_DIRECT);
4700 cc = s390_emit_compare (NE, resv, val);
4701 emit_move_insn (val, resv);
4702 /* Loop internal if so. */
4703 s390_emit_jump (csloop, cc);
4704
4705 emit_label (csend);
4706
4707 /* Return the correct part of the bitfield. */
4708 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4709 NULL_RTX, 1, OPTAB_DIRECT), 1);
4710 }
4711
4712 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4713 and VAL the value to play with. If AFTER is true then store the value
4714 MEM holds after the operation, if AFTER is false then store the value MEM
4715 holds before the operation. If TARGET is zero then discard that value, else
4716 store it to TARGET. */
4717
4718 void
4719 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4720 rtx target, rtx mem, rtx val, bool after)
4721 {
4722 struct alignment_context ac;
4723 rtx cmp;
4724 rtx new_rtx = gen_reg_rtx (SImode);
4725 rtx orig = gen_reg_rtx (SImode);
4726 rtx csloop = gen_label_rtx ();
4727
4728 gcc_assert (!target || register_operand (target, VOIDmode));
4729 gcc_assert (MEM_P (mem));
4730
4731 init_alignment_context (&ac, mem, mode);
4732
4733 /* Shift val to the correct bit positions.
4734 Preserve "icm", but prevent "ex icm". */
4735 if (!(ac.aligned && code == SET && MEM_P (val)))
4736 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4737
4738 /* Further preparation insns. */
4739 if (code == PLUS || code == MINUS)
4740 emit_move_insn (orig, val);
4741 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4742 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4743 NULL_RTX, 1, OPTAB_DIRECT);
4744
4745 /* Load full word. Subsequent loads are performed by CS. */
4746 cmp = force_reg (SImode, ac.memsi);
4747
4748 /* Start CS loop. */
4749 emit_label (csloop);
4750 emit_move_insn (new_rtx, cmp);
4751
4752 /* Patch new with val at correct position. */
4753 switch (code)
4754 {
4755 case PLUS:
4756 case MINUS:
4757 val = expand_simple_binop (SImode, code, new_rtx, orig,
4758 NULL_RTX, 1, OPTAB_DIRECT);
4759 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4760 NULL_RTX, 1, OPTAB_DIRECT);
4761 /* FALLTHRU */
4762 case SET:
4763 if (ac.aligned && MEM_P (val))
4764 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4765 else
4766 {
4767 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4768 NULL_RTX, 1, OPTAB_DIRECT);
4769 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4770 NULL_RTX, 1, OPTAB_DIRECT);
4771 }
4772 break;
4773 case AND:
4774 case IOR:
4775 case XOR:
4776 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4777 NULL_RTX, 1, OPTAB_DIRECT);
4778 break;
4779 case MULT: /* NAND */
4780 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4781 NULL_RTX, 1, OPTAB_DIRECT);
4782 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4783 NULL_RTX, 1, OPTAB_DIRECT);
4784 break;
4785 default:
4786 gcc_unreachable ();
4787 }
4788
4789 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4790 ac.memsi, cmp, new_rtx));
4791
4792 /* Return the correct part of the bitfield. */
4793 if (target)
4794 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4795 after ? new_rtx : cmp, ac.shift,
4796 NULL_RTX, 1, OPTAB_DIRECT), 1);
4797 }
4798
4799 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4800 We need to emit DTP-relative relocations. */
4801
4802 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4803
4804 static void
4805 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4806 {
4807 switch (size)
4808 {
4809 case 4:
4810 fputs ("\t.long\t", file);
4811 break;
4812 case 8:
4813 fputs ("\t.quad\t", file);
4814 break;
4815 default:
4816 gcc_unreachable ();
4817 }
4818 output_addr_const (file, x);
4819 fputs ("@DTPOFF", file);
4820 }
4821
4822 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4823 /* Implement TARGET_MANGLE_TYPE. */
4824
4825 static const char *
4826 s390_mangle_type (const_tree type)
4827 {
4828 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4829 && TARGET_LONG_DOUBLE_128)
4830 return "g";
4831
4832 /* For all other types, use normal C++ mangling. */
4833 return NULL;
4834 }
4835 #endif
4836
4837 /* In the name of slightly smaller debug output, and to cater to
4838 general assembler lossage, recognize various UNSPEC sequences
4839 and turn them back into a direct symbol reference. */
4840
4841 static rtx
4842 s390_delegitimize_address (rtx orig_x)
4843 {
4844 rtx x, y;
4845
4846 orig_x = delegitimize_mem_from_attrs (orig_x);
4847 x = orig_x;
4848 if (GET_CODE (x) != MEM)
4849 return orig_x;
4850
4851 x = XEXP (x, 0);
4852 if (GET_CODE (x) == PLUS
4853 && GET_CODE (XEXP (x, 1)) == CONST
4854 && GET_CODE (XEXP (x, 0)) == REG
4855 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4856 {
4857 y = XEXP (XEXP (x, 1), 0);
4858 if (GET_CODE (y) == UNSPEC
4859 && XINT (y, 1) == UNSPEC_GOT)
4860 return XVECEXP (y, 0, 0);
4861 return orig_x;
4862 }
4863
4864 if (GET_CODE (x) == CONST)
4865 {
4866 y = XEXP (x, 0);
4867 if (GET_CODE (y) == UNSPEC
4868 && XINT (y, 1) == UNSPEC_GOTENT)
4869 return XVECEXP (y, 0, 0);
4870 return orig_x;
4871 }
4872
4873 return orig_x;
4874 }
4875
4876 /* Output operand OP to stdio stream FILE.
4877 OP is an address (register + offset) which is not used to address data;
4878 instead the rightmost bits are interpreted as the value. */
4879
4880 static void
4881 print_shift_count_operand (FILE *file, rtx op)
4882 {
4883 HOST_WIDE_INT offset;
4884 rtx base;
4885
4886 /* Extract base register and offset. */
4887 if (!s390_decompose_shift_count (op, &base, &offset))
4888 gcc_unreachable ();
4889
4890 /* Sanity check. */
4891 if (base)
4892 {
4893 gcc_assert (GET_CODE (base) == REG);
4894 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4895 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4896 }
4897
4898 /* Offsets are constricted to twelve bits. */
4899 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4900 if (base)
4901 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4902 }
4903
4904 /* See 'get_some_local_dynamic_name'. */
4905
4906 static int
4907 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4908 {
4909 rtx x = *px;
4910
4911 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4912 {
4913 x = get_pool_constant (x);
4914 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4915 }
4916
4917 if (GET_CODE (x) == SYMBOL_REF
4918 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4919 {
4920 cfun->machine->some_ld_name = XSTR (x, 0);
4921 return 1;
4922 }
4923
4924 return 0;
4925 }
4926
4927 /* Locate some local-dynamic symbol still in use by this function
4928 so that we can print its name in local-dynamic base patterns. */
4929
4930 static const char *
4931 get_some_local_dynamic_name (void)
4932 {
4933 rtx insn;
4934
4935 if (cfun->machine->some_ld_name)
4936 return cfun->machine->some_ld_name;
4937
4938 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4939 if (INSN_P (insn)
4940 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4941 return cfun->machine->some_ld_name;
4942
4943 gcc_unreachable ();
4944 }
4945
4946 /* Output machine-dependent UNSPECs occurring in address constant X
4947 in assembler syntax to stdio stream FILE. Returns true if the
4948 constant X could be recognized, false otherwise. */
4949
4950 bool
4951 s390_output_addr_const_extra (FILE *file, rtx x)
4952 {
4953 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4954 switch (XINT (x, 1))
4955 {
4956 case UNSPEC_GOTENT:
4957 output_addr_const (file, XVECEXP (x, 0, 0));
4958 fprintf (file, "@GOTENT");
4959 return true;
4960 case UNSPEC_GOT:
4961 output_addr_const (file, XVECEXP (x, 0, 0));
4962 fprintf (file, "@GOT");
4963 return true;
4964 case UNSPEC_GOTOFF:
4965 output_addr_const (file, XVECEXP (x, 0, 0));
4966 fprintf (file, "@GOTOFF");
4967 return true;
4968 case UNSPEC_PLT:
4969 output_addr_const (file, XVECEXP (x, 0, 0));
4970 fprintf (file, "@PLT");
4971 return true;
4972 case UNSPEC_PLTOFF:
4973 output_addr_const (file, XVECEXP (x, 0, 0));
4974 fprintf (file, "@PLTOFF");
4975 return true;
4976 case UNSPEC_TLSGD:
4977 output_addr_const (file, XVECEXP (x, 0, 0));
4978 fprintf (file, "@TLSGD");
4979 return true;
4980 case UNSPEC_TLSLDM:
4981 assemble_name (file, get_some_local_dynamic_name ());
4982 fprintf (file, "@TLSLDM");
4983 return true;
4984 case UNSPEC_DTPOFF:
4985 output_addr_const (file, XVECEXP (x, 0, 0));
4986 fprintf (file, "@DTPOFF");
4987 return true;
4988 case UNSPEC_NTPOFF:
4989 output_addr_const (file, XVECEXP (x, 0, 0));
4990 fprintf (file, "@NTPOFF");
4991 return true;
4992 case UNSPEC_GOTNTPOFF:
4993 output_addr_const (file, XVECEXP (x, 0, 0));
4994 fprintf (file, "@GOTNTPOFF");
4995 return true;
4996 case UNSPEC_INDNTPOFF:
4997 output_addr_const (file, XVECEXP (x, 0, 0));
4998 fprintf (file, "@INDNTPOFF");
4999 return true;
5000 }
5001
5002 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5003 switch (XINT (x, 1))
5004 {
5005 case UNSPEC_POOL_OFFSET:
5006 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5007 output_addr_const (file, x);
5008 return true;
5009 }
5010 return false;
5011 }
5012
5013 /* Output address operand ADDR in assembler syntax to
5014 stdio stream FILE. */
5015
5016 void
5017 print_operand_address (FILE *file, rtx addr)
5018 {
5019 struct s390_address ad;
5020
5021 if (s390_symref_operand_p (addr, NULL, NULL))
5022 {
5023 gcc_assert (TARGET_Z10);
5024 output_addr_const (file, addr);
5025 return;
5026 }
5027
5028 if (!s390_decompose_address (addr, &ad)
5029 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5030 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5031 output_operand_lossage ("cannot decompose address");
5032
5033 if (ad.disp)
5034 output_addr_const (file, ad.disp);
5035 else
5036 fprintf (file, "0");
5037
5038 if (ad.base && ad.indx)
5039 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5040 reg_names[REGNO (ad.base)]);
5041 else if (ad.base)
5042 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5043 }
5044
5045 /* Output operand X in assembler syntax to stdio stream FILE.
5046 CODE specified the format flag. The following format flags
5047 are recognized:
5048
5049 'C': print opcode suffix for branch condition.
5050 'D': print opcode suffix for inverse branch condition.
5051 'E': print opcode suffix for branch on index instruction.
5052 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5053 'G': print the size of the operand in bytes.
5054 'O': print only the displacement of a memory reference.
5055 'R': print only the base register of a memory reference.
5056 'S': print S-type memory reference (base+displacement).
5057 'N': print the second word of a DImode operand.
5058 'M': print the second word of a TImode operand.
5059 'Y': print shift count operand.
5060
5061 'b': print integer X as if it's an unsigned byte.
5062 'c': print integer X as if it's an signed byte.
5063 'x': print integer X as if it's an unsigned halfword.
5064 'h': print integer X as if it's a signed halfword.
5065 'i': print the first nonzero HImode part of X.
5066 'j': print the first HImode part unequal to -1 of X.
5067 'k': print the first nonzero SImode part of X.
5068 'm': print the first SImode part unequal to -1 of X.
5069 'o': print integer X as if it's an unsigned 32bit word. */
5070
5071 void
5072 print_operand (FILE *file, rtx x, int code)
5073 {
5074 switch (code)
5075 {
5076 case 'C':
5077 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5078 return;
5079
5080 case 'D':
5081 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5082 return;
5083
5084 case 'E':
5085 if (GET_CODE (x) == LE)
5086 fprintf (file, "l");
5087 else if (GET_CODE (x) == GT)
5088 fprintf (file, "h");
5089 else
5090 gcc_unreachable ();
5091 return;
5092
5093 case 'J':
5094 if (GET_CODE (x) == SYMBOL_REF)
5095 {
5096 fprintf (file, "%s", ":tls_load:");
5097 output_addr_const (file, x);
5098 }
5099 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5100 {
5101 fprintf (file, "%s", ":tls_gdcall:");
5102 output_addr_const (file, XVECEXP (x, 0, 0));
5103 }
5104 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5105 {
5106 fprintf (file, "%s", ":tls_ldcall:");
5107 assemble_name (file, get_some_local_dynamic_name ());
5108 }
5109 else
5110 gcc_unreachable ();
5111 return;
5112
5113 case 'G':
5114 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5115 return;
5116
5117 case 'O':
5118 {
5119 struct s390_address ad;
5120 int ret;
5121
5122 gcc_assert (GET_CODE (x) == MEM);
5123 ret = s390_decompose_address (XEXP (x, 0), &ad);
5124 gcc_assert (ret);
5125 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5126 gcc_assert (!ad.indx);
5127
5128 if (ad.disp)
5129 output_addr_const (file, ad.disp);
5130 else
5131 fprintf (file, "0");
5132 }
5133 return;
5134
5135 case 'R':
5136 {
5137 struct s390_address ad;
5138 int ret;
5139
5140 gcc_assert (GET_CODE (x) == MEM);
5141 ret = s390_decompose_address (XEXP (x, 0), &ad);
5142 gcc_assert (ret);
5143 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5144 gcc_assert (!ad.indx);
5145
5146 if (ad.base)
5147 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5148 else
5149 fprintf (file, "0");
5150 }
5151 return;
5152
5153 case 'S':
5154 {
5155 struct s390_address ad;
5156 int ret;
5157
5158 gcc_assert (GET_CODE (x) == MEM);
5159 ret = s390_decompose_address (XEXP (x, 0), &ad);
5160 gcc_assert (ret);
5161 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5162 gcc_assert (!ad.indx);
5163
5164 if (ad.disp)
5165 output_addr_const (file, ad.disp);
5166 else
5167 fprintf (file, "0");
5168
5169 if (ad.base)
5170 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5171 }
5172 return;
5173
5174 case 'N':
5175 if (GET_CODE (x) == REG)
5176 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5177 else if (GET_CODE (x) == MEM)
5178 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5179 else
5180 gcc_unreachable ();
5181 break;
5182
5183 case 'M':
5184 if (GET_CODE (x) == REG)
5185 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5186 else if (GET_CODE (x) == MEM)
5187 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5188 else
5189 gcc_unreachable ();
5190 break;
5191
5192 case 'Y':
5193 print_shift_count_operand (file, x);
5194 return;
5195 }
5196
5197 switch (GET_CODE (x))
5198 {
5199 case REG:
5200 fprintf (file, "%s", reg_names[REGNO (x)]);
5201 break;
5202
5203 case MEM:
5204 output_address (XEXP (x, 0));
5205 break;
5206
5207 case CONST:
5208 case CODE_LABEL:
5209 case LABEL_REF:
5210 case SYMBOL_REF:
5211 output_addr_const (file, x);
5212 break;
5213
5214 case CONST_INT:
5215 if (code == 'b')
5216 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5217 else if (code == 'c')
5218 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5219 else if (code == 'x')
5220 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5221 else if (code == 'h')
5222 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5223 else if (code == 'i')
5224 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5225 s390_extract_part (x, HImode, 0));
5226 else if (code == 'j')
5227 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5228 s390_extract_part (x, HImode, -1));
5229 else if (code == 'k')
5230 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5231 s390_extract_part (x, SImode, 0));
5232 else if (code == 'm')
5233 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5234 s390_extract_part (x, SImode, -1));
5235 else if (code == 'o')
5236 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5237 else
5238 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5239 break;
5240
5241 case CONST_DOUBLE:
5242 gcc_assert (GET_MODE (x) == VOIDmode);
5243 if (code == 'b')
5244 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5245 else if (code == 'x')
5246 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5247 else if (code == 'h')
5248 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5249 else
5250 gcc_unreachable ();
5251 break;
5252
5253 default:
5254 fatal_insn ("UNKNOWN in print_operand !?", x);
5255 break;
5256 }
5257 }
5258
5259 /* Target hook for assembling integer objects. We need to define it
5260 here to work a round a bug in some versions of GAS, which couldn't
5261 handle values smaller than INT_MIN when printed in decimal. */
5262
5263 static bool
5264 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5265 {
5266 if (size == 8 && aligned_p
5267 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5268 {
5269 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5270 INTVAL (x));
5271 return true;
5272 }
5273 return default_assemble_integer (x, size, aligned_p);
5274 }
5275
5276 /* Returns true if register REGNO is used for forming
5277 a memory address in expression X. */
5278
5279 static bool
5280 reg_used_in_mem_p (int regno, rtx x)
5281 {
5282 enum rtx_code code = GET_CODE (x);
5283 int i, j;
5284 const char *fmt;
5285
5286 if (code == MEM)
5287 {
5288 if (refers_to_regno_p (regno, regno+1,
5289 XEXP (x, 0), 0))
5290 return true;
5291 }
5292 else if (code == SET
5293 && GET_CODE (SET_DEST (x)) == PC)
5294 {
5295 if (refers_to_regno_p (regno, regno+1,
5296 SET_SRC (x), 0))
5297 return true;
5298 }
5299
5300 fmt = GET_RTX_FORMAT (code);
5301 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5302 {
5303 if (fmt[i] == 'e'
5304 && reg_used_in_mem_p (regno, XEXP (x, i)))
5305 return true;
5306
5307 else if (fmt[i] == 'E')
5308 for (j = 0; j < XVECLEN (x, i); j++)
5309 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5310 return true;
5311 }
5312 return false;
5313 }
5314
5315 /* Returns true if expression DEP_RTX sets an address register
5316 used by instruction INSN to address memory. */
5317
5318 static bool
5319 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5320 {
5321 rtx target, pat;
5322
5323 if (GET_CODE (dep_rtx) == INSN)
5324 dep_rtx = PATTERN (dep_rtx);
5325
5326 if (GET_CODE (dep_rtx) == SET)
5327 {
5328 target = SET_DEST (dep_rtx);
5329 if (GET_CODE (target) == STRICT_LOW_PART)
5330 target = XEXP (target, 0);
5331 while (GET_CODE (target) == SUBREG)
5332 target = SUBREG_REG (target);
5333
5334 if (GET_CODE (target) == REG)
5335 {
5336 int regno = REGNO (target);
5337
5338 if (s390_safe_attr_type (insn) == TYPE_LA)
5339 {
5340 pat = PATTERN (insn);
5341 if (GET_CODE (pat) == PARALLEL)
5342 {
5343 gcc_assert (XVECLEN (pat, 0) == 2);
5344 pat = XVECEXP (pat, 0, 0);
5345 }
5346 gcc_assert (GET_CODE (pat) == SET);
5347 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5348 }
5349 else if (get_attr_atype (insn) == ATYPE_AGEN)
5350 return reg_used_in_mem_p (regno, PATTERN (insn));
5351 }
5352 }
5353 return false;
5354 }
5355
5356 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5357
5358 int
5359 s390_agen_dep_p (rtx dep_insn, rtx insn)
5360 {
5361 rtx dep_rtx = PATTERN (dep_insn);
5362 int i;
5363
5364 if (GET_CODE (dep_rtx) == SET
5365 && addr_generation_dependency_p (dep_rtx, insn))
5366 return 1;
5367 else if (GET_CODE (dep_rtx) == PARALLEL)
5368 {
5369 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5370 {
5371 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5372 return 1;
5373 }
5374 }
5375 return 0;
5376 }
5377
5378
5379 /* A C statement (sans semicolon) to update the integer scheduling priority
5380 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5381 reduce the priority to execute INSN later. Do not define this macro if
5382 you do not need to adjust the scheduling priorities of insns.
5383
5384 A STD instruction should be scheduled earlier,
5385 in order to use the bypass. */
5386
5387
5388 static int
5389 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5390 {
5391 if (! INSN_P (insn))
5392 return priority;
5393
5394 if (s390_tune != PROCESSOR_2084_Z990
5395 && s390_tune != PROCESSOR_2094_Z9_109
5396 && s390_tune != PROCESSOR_2097_Z10)
5397 return priority;
5398
5399 switch (s390_safe_attr_type (insn))
5400 {
5401 case TYPE_FSTOREDF:
5402 case TYPE_FSTORESF:
5403 priority = priority << 3;
5404 break;
5405 case TYPE_STORE:
5406 case TYPE_STM:
5407 priority = priority << 1;
5408 break;
5409 default:
5410 break;
5411 }
5412 return priority;
5413 }
5414
5415
5416 /* The number of instructions that can be issued per cycle. */
5417
5418 static int
5419 s390_issue_rate (void)
5420 {
5421 switch (s390_tune)
5422 {
5423 case PROCESSOR_2084_Z990:
5424 case PROCESSOR_2094_Z9_109:
5425 return 3;
5426 case PROCESSOR_2097_Z10:
5427 return 2;
5428 default:
5429 return 1;
5430 }
5431 }
5432
5433 static int
5434 s390_first_cycle_multipass_dfa_lookahead (void)
5435 {
5436 return 4;
5437 }
5438
5439 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5440 Fix up MEMs as required. */
5441
5442 static void
5443 annotate_constant_pool_refs (rtx *x)
5444 {
5445 int i, j;
5446 const char *fmt;
5447
5448 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5449 || !CONSTANT_POOL_ADDRESS_P (*x));
5450
5451 /* Literal pool references can only occur inside a MEM ... */
5452 if (GET_CODE (*x) == MEM)
5453 {
5454 rtx memref = XEXP (*x, 0);
5455
5456 if (GET_CODE (memref) == SYMBOL_REF
5457 && CONSTANT_POOL_ADDRESS_P (memref))
5458 {
5459 rtx base = cfun->machine->base_reg;
5460 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5461 UNSPEC_LTREF);
5462
5463 *x = replace_equiv_address (*x, addr);
5464 return;
5465 }
5466
5467 if (GET_CODE (memref) == CONST
5468 && GET_CODE (XEXP (memref, 0)) == PLUS
5469 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5470 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5471 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5472 {
5473 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5474 rtx sym = XEXP (XEXP (memref, 0), 0);
5475 rtx base = cfun->machine->base_reg;
5476 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5477 UNSPEC_LTREF);
5478
5479 *x = replace_equiv_address (*x, plus_constant (addr, off));
5480 return;
5481 }
5482 }
5483
5484 /* ... or a load-address type pattern. */
5485 if (GET_CODE (*x) == SET)
5486 {
5487 rtx addrref = SET_SRC (*x);
5488
5489 if (GET_CODE (addrref) == SYMBOL_REF
5490 && CONSTANT_POOL_ADDRESS_P (addrref))
5491 {
5492 rtx base = cfun->machine->base_reg;
5493 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5494 UNSPEC_LTREF);
5495
5496 SET_SRC (*x) = addr;
5497 return;
5498 }
5499
5500 if (GET_CODE (addrref) == CONST
5501 && GET_CODE (XEXP (addrref, 0)) == PLUS
5502 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5503 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5504 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5505 {
5506 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5507 rtx sym = XEXP (XEXP (addrref, 0), 0);
5508 rtx base = cfun->machine->base_reg;
5509 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5510 UNSPEC_LTREF);
5511
5512 SET_SRC (*x) = plus_constant (addr, off);
5513 return;
5514 }
5515 }
5516
5517 /* Annotate LTREL_BASE as well. */
5518 if (GET_CODE (*x) == UNSPEC
5519 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5520 {
5521 rtx base = cfun->machine->base_reg;
5522 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5523 UNSPEC_LTREL_BASE);
5524 return;
5525 }
5526
5527 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5528 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5529 {
5530 if (fmt[i] == 'e')
5531 {
5532 annotate_constant_pool_refs (&XEXP (*x, i));
5533 }
5534 else if (fmt[i] == 'E')
5535 {
5536 for (j = 0; j < XVECLEN (*x, i); j++)
5537 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5538 }
5539 }
5540 }
5541
5542 /* Split all branches that exceed the maximum distance.
5543 Returns true if this created a new literal pool entry. */
5544
5545 static int
5546 s390_split_branches (void)
5547 {
5548 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5549 int new_literal = 0, ret;
5550 rtx insn, pat, tmp, target;
5551 rtx *label;
5552
5553 /* We need correct insn addresses. */
5554
5555 shorten_branches (get_insns ());
5556
5557 /* Find all branches that exceed 64KB, and split them. */
5558
5559 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5560 {
5561 if (GET_CODE (insn) != JUMP_INSN)
5562 continue;
5563
5564 pat = PATTERN (insn);
5565 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5566 pat = XVECEXP (pat, 0, 0);
5567 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5568 continue;
5569
5570 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5571 {
5572 label = &SET_SRC (pat);
5573 }
5574 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5575 {
5576 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5577 label = &XEXP (SET_SRC (pat), 1);
5578 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5579 label = &XEXP (SET_SRC (pat), 2);
5580 else
5581 continue;
5582 }
5583 else
5584 continue;
5585
5586 if (get_attr_length (insn) <= 4)
5587 continue;
5588
5589 /* We are going to use the return register as scratch register,
5590 make sure it will be saved/restored by the prologue/epilogue. */
5591 cfun_frame_layout.save_return_addr_p = 1;
5592
5593 if (!flag_pic)
5594 {
5595 new_literal = 1;
5596 tmp = force_const_mem (Pmode, *label);
5597 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5598 INSN_ADDRESSES_NEW (tmp, -1);
5599 annotate_constant_pool_refs (&PATTERN (tmp));
5600
5601 target = temp_reg;
5602 }
5603 else
5604 {
5605 new_literal = 1;
5606 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5607 UNSPEC_LTREL_OFFSET);
5608 target = gen_rtx_CONST (Pmode, target);
5609 target = force_const_mem (Pmode, target);
5610 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5611 INSN_ADDRESSES_NEW (tmp, -1);
5612 annotate_constant_pool_refs (&PATTERN (tmp));
5613
5614 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5615 cfun->machine->base_reg),
5616 UNSPEC_LTREL_BASE);
5617 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5618 }
5619
5620 ret = validate_change (insn, label, target, 0);
5621 gcc_assert (ret);
5622 }
5623
5624 return new_literal;
5625 }
5626
5627
5628 /* Find an annotated literal pool symbol referenced in RTX X,
5629 and store it at REF. Will abort if X contains references to
5630 more than one such pool symbol; multiple references to the same
5631 symbol are allowed, however.
5632
5633 The rtx pointed to by REF must be initialized to NULL_RTX
5634 by the caller before calling this routine. */
5635
5636 static void
5637 find_constant_pool_ref (rtx x, rtx *ref)
5638 {
5639 int i, j;
5640 const char *fmt;
5641
5642 /* Ignore LTREL_BASE references. */
5643 if (GET_CODE (x) == UNSPEC
5644 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5645 return;
5646 /* Likewise POOL_ENTRY insns. */
5647 if (GET_CODE (x) == UNSPEC_VOLATILE
5648 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5649 return;
5650
5651 gcc_assert (GET_CODE (x) != SYMBOL_REF
5652 || !CONSTANT_POOL_ADDRESS_P (x));
5653
5654 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5655 {
5656 rtx sym = XVECEXP (x, 0, 0);
5657 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5658 && CONSTANT_POOL_ADDRESS_P (sym));
5659
5660 if (*ref == NULL_RTX)
5661 *ref = sym;
5662 else
5663 gcc_assert (*ref == sym);
5664
5665 return;
5666 }
5667
5668 fmt = GET_RTX_FORMAT (GET_CODE (x));
5669 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5670 {
5671 if (fmt[i] == 'e')
5672 {
5673 find_constant_pool_ref (XEXP (x, i), ref);
5674 }
5675 else if (fmt[i] == 'E')
5676 {
5677 for (j = 0; j < XVECLEN (x, i); j++)
5678 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5679 }
5680 }
5681 }
5682
5683 /* Replace every reference to the annotated literal pool
5684 symbol REF in X by its base plus OFFSET. */
5685
5686 static void
5687 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5688 {
5689 int i, j;
5690 const char *fmt;
5691
5692 gcc_assert (*x != ref);
5693
5694 if (GET_CODE (*x) == UNSPEC
5695 && XINT (*x, 1) == UNSPEC_LTREF
5696 && XVECEXP (*x, 0, 0) == ref)
5697 {
5698 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5699 return;
5700 }
5701
5702 if (GET_CODE (*x) == PLUS
5703 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5704 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5705 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5706 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5707 {
5708 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5709 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5710 return;
5711 }
5712
5713 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5714 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5715 {
5716 if (fmt[i] == 'e')
5717 {
5718 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5719 }
5720 else if (fmt[i] == 'E')
5721 {
5722 for (j = 0; j < XVECLEN (*x, i); j++)
5723 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5724 }
5725 }
5726 }
5727
5728 /* Check whether X contains an UNSPEC_LTREL_BASE.
5729 Return its constant pool symbol if found, NULL_RTX otherwise. */
5730
5731 static rtx
5732 find_ltrel_base (rtx x)
5733 {
5734 int i, j;
5735 const char *fmt;
5736
5737 if (GET_CODE (x) == UNSPEC
5738 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5739 return XVECEXP (x, 0, 0);
5740
5741 fmt = GET_RTX_FORMAT (GET_CODE (x));
5742 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5743 {
5744 if (fmt[i] == 'e')
5745 {
5746 rtx fnd = find_ltrel_base (XEXP (x, i));
5747 if (fnd)
5748 return fnd;
5749 }
5750 else if (fmt[i] == 'E')
5751 {
5752 for (j = 0; j < XVECLEN (x, i); j++)
5753 {
5754 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5755 if (fnd)
5756 return fnd;
5757 }
5758 }
5759 }
5760
5761 return NULL_RTX;
5762 }
5763
5764 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5765
5766 static void
5767 replace_ltrel_base (rtx *x)
5768 {
5769 int i, j;
5770 const char *fmt;
5771
5772 if (GET_CODE (*x) == UNSPEC
5773 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5774 {
5775 *x = XVECEXP (*x, 0, 1);
5776 return;
5777 }
5778
5779 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5780 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5781 {
5782 if (fmt[i] == 'e')
5783 {
5784 replace_ltrel_base (&XEXP (*x, i));
5785 }
5786 else if (fmt[i] == 'E')
5787 {
5788 for (j = 0; j < XVECLEN (*x, i); j++)
5789 replace_ltrel_base (&XVECEXP (*x, i, j));
5790 }
5791 }
5792 }
5793
5794
5795 /* We keep a list of constants which we have to add to internal
5796 constant tables in the middle of large functions. */
5797
5798 #define NR_C_MODES 11
5799 enum machine_mode constant_modes[NR_C_MODES] =
5800 {
5801 TFmode, TImode, TDmode,
5802 DFmode, DImode, DDmode,
5803 SFmode, SImode, SDmode,
5804 HImode,
5805 QImode
5806 };
5807
5808 struct constant
5809 {
5810 struct constant *next;
5811 rtx value;
5812 rtx label;
5813 };
5814
5815 struct constant_pool
5816 {
5817 struct constant_pool *next;
5818 rtx first_insn;
5819 rtx pool_insn;
5820 bitmap insns;
5821 rtx emit_pool_after;
5822
5823 struct constant *constants[NR_C_MODES];
5824 struct constant *execute;
5825 rtx label;
5826 int size;
5827 };
5828
5829 /* Allocate new constant_pool structure. */
5830
5831 static struct constant_pool *
5832 s390_alloc_pool (void)
5833 {
5834 struct constant_pool *pool;
5835 int i;
5836
5837 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5838 pool->next = NULL;
5839 for (i = 0; i < NR_C_MODES; i++)
5840 pool->constants[i] = NULL;
5841
5842 pool->execute = NULL;
5843 pool->label = gen_label_rtx ();
5844 pool->first_insn = NULL_RTX;
5845 pool->pool_insn = NULL_RTX;
5846 pool->insns = BITMAP_ALLOC (NULL);
5847 pool->size = 0;
5848 pool->emit_pool_after = NULL_RTX;
5849
5850 return pool;
5851 }
5852
5853 /* Create new constant pool covering instructions starting at INSN
5854 and chain it to the end of POOL_LIST. */
5855
5856 static struct constant_pool *
5857 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5858 {
5859 struct constant_pool *pool, **prev;
5860
5861 pool = s390_alloc_pool ();
5862 pool->first_insn = insn;
5863
5864 for (prev = pool_list; *prev; prev = &(*prev)->next)
5865 ;
5866 *prev = pool;
5867
5868 return pool;
5869 }
5870
5871 /* End range of instructions covered by POOL at INSN and emit
5872 placeholder insn representing the pool. */
5873
5874 static void
5875 s390_end_pool (struct constant_pool *pool, rtx insn)
5876 {
5877 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5878
5879 if (!insn)
5880 insn = get_last_insn ();
5881
5882 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5883 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5884 }
5885
5886 /* Add INSN to the list of insns covered by POOL. */
5887
5888 static void
5889 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5890 {
5891 bitmap_set_bit (pool->insns, INSN_UID (insn));
5892 }
5893
5894 /* Return pool out of POOL_LIST that covers INSN. */
5895
5896 static struct constant_pool *
5897 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5898 {
5899 struct constant_pool *pool;
5900
5901 for (pool = pool_list; pool; pool = pool->next)
5902 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5903 break;
5904
5905 return pool;
5906 }
5907
5908 /* Add constant VAL of mode MODE to the constant pool POOL. */
5909
5910 static void
5911 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5912 {
5913 struct constant *c;
5914 int i;
5915
5916 for (i = 0; i < NR_C_MODES; i++)
5917 if (constant_modes[i] == mode)
5918 break;
5919 gcc_assert (i != NR_C_MODES);
5920
5921 for (c = pool->constants[i]; c != NULL; c = c->next)
5922 if (rtx_equal_p (val, c->value))
5923 break;
5924
5925 if (c == NULL)
5926 {
5927 c = (struct constant *) xmalloc (sizeof *c);
5928 c->value = val;
5929 c->label = gen_label_rtx ();
5930 c->next = pool->constants[i];
5931 pool->constants[i] = c;
5932 pool->size += GET_MODE_SIZE (mode);
5933 }
5934 }
5935
5936 /* Return an rtx that represents the offset of X from the start of
5937 pool POOL. */
5938
5939 static rtx
5940 s390_pool_offset (struct constant_pool *pool, rtx x)
5941 {
5942 rtx label;
5943
5944 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5945 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5946 UNSPEC_POOL_OFFSET);
5947 return gen_rtx_CONST (GET_MODE (x), x);
5948 }
5949
5950 /* Find constant VAL of mode MODE in the constant pool POOL.
5951 Return an RTX describing the distance from the start of
5952 the pool to the location of the new constant. */
5953
5954 static rtx
5955 s390_find_constant (struct constant_pool *pool, rtx val,
5956 enum machine_mode mode)
5957 {
5958 struct constant *c;
5959 int i;
5960
5961 for (i = 0; i < NR_C_MODES; i++)
5962 if (constant_modes[i] == mode)
5963 break;
5964 gcc_assert (i != NR_C_MODES);
5965
5966 for (c = pool->constants[i]; c != NULL; c = c->next)
5967 if (rtx_equal_p (val, c->value))
5968 break;
5969
5970 gcc_assert (c);
5971
5972 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5973 }
5974
5975 /* Check whether INSN is an execute. Return the label_ref to its
5976 execute target template if so, NULL_RTX otherwise. */
5977
5978 static rtx
5979 s390_execute_label (rtx insn)
5980 {
5981 if (GET_CODE (insn) == INSN
5982 && GET_CODE (PATTERN (insn)) == PARALLEL
5983 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5984 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5985 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5986
5987 return NULL_RTX;
5988 }
5989
5990 /* Add execute target for INSN to the constant pool POOL. */
5991
5992 static void
5993 s390_add_execute (struct constant_pool *pool, rtx insn)
5994 {
5995 struct constant *c;
5996
5997 for (c = pool->execute; c != NULL; c = c->next)
5998 if (INSN_UID (insn) == INSN_UID (c->value))
5999 break;
6000
6001 if (c == NULL)
6002 {
6003 c = (struct constant *) xmalloc (sizeof *c);
6004 c->value = insn;
6005 c->label = gen_label_rtx ();
6006 c->next = pool->execute;
6007 pool->execute = c;
6008 pool->size += 6;
6009 }
6010 }
6011
6012 /* Find execute target for INSN in the constant pool POOL.
6013 Return an RTX describing the distance from the start of
6014 the pool to the location of the execute target. */
6015
6016 static rtx
6017 s390_find_execute (struct constant_pool *pool, rtx insn)
6018 {
6019 struct constant *c;
6020
6021 for (c = pool->execute; c != NULL; c = c->next)
6022 if (INSN_UID (insn) == INSN_UID (c->value))
6023 break;
6024
6025 gcc_assert (c);
6026
6027 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6028 }
6029
6030 /* For an execute INSN, extract the execute target template. */
6031
6032 static rtx
6033 s390_execute_target (rtx insn)
6034 {
6035 rtx pattern = PATTERN (insn);
6036 gcc_assert (s390_execute_label (insn));
6037
6038 if (XVECLEN (pattern, 0) == 2)
6039 {
6040 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6041 }
6042 else
6043 {
6044 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6045 int i;
6046
6047 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6048 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6049
6050 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6051 }
6052
6053 return pattern;
6054 }
6055
6056 /* Indicate that INSN cannot be duplicated. This is the case for
6057 execute insns that carry a unique label. */
6058
6059 static bool
6060 s390_cannot_copy_insn_p (rtx insn)
6061 {
6062 rtx label = s390_execute_label (insn);
6063 return label && label != const0_rtx;
6064 }
6065
6066 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6067 do not emit the pool base label. */
6068
6069 static void
6070 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6071 {
6072 struct constant *c;
6073 rtx insn = pool->pool_insn;
6074 int i;
6075
6076 /* Switch to rodata section. */
6077 if (TARGET_CPU_ZARCH)
6078 {
6079 insn = emit_insn_after (gen_pool_section_start (), insn);
6080 INSN_ADDRESSES_NEW (insn, -1);
6081 }
6082
6083 /* Ensure minimum pool alignment. */
6084 if (TARGET_CPU_ZARCH)
6085 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6086 else
6087 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6088 INSN_ADDRESSES_NEW (insn, -1);
6089
6090 /* Emit pool base label. */
6091 if (!remote_label)
6092 {
6093 insn = emit_label_after (pool->label, insn);
6094 INSN_ADDRESSES_NEW (insn, -1);
6095 }
6096
6097 /* Dump constants in descending alignment requirement order,
6098 ensuring proper alignment for every constant. */
6099 for (i = 0; i < NR_C_MODES; i++)
6100 for (c = pool->constants[i]; c; c = c->next)
6101 {
6102 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6103 rtx value = copy_rtx (c->value);
6104 if (GET_CODE (value) == CONST
6105 && GET_CODE (XEXP (value, 0)) == UNSPEC
6106 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6107 && XVECLEN (XEXP (value, 0), 0) == 1)
6108 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6109
6110 insn = emit_label_after (c->label, insn);
6111 INSN_ADDRESSES_NEW (insn, -1);
6112
6113 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6114 gen_rtvec (1, value),
6115 UNSPECV_POOL_ENTRY);
6116 insn = emit_insn_after (value, insn);
6117 INSN_ADDRESSES_NEW (insn, -1);
6118 }
6119
6120 /* Ensure minimum alignment for instructions. */
6121 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6122 INSN_ADDRESSES_NEW (insn, -1);
6123
6124 /* Output in-pool execute template insns. */
6125 for (c = pool->execute; c; c = c->next)
6126 {
6127 insn = emit_label_after (c->label, insn);
6128 INSN_ADDRESSES_NEW (insn, -1);
6129
6130 insn = emit_insn_after (s390_execute_target (c->value), insn);
6131 INSN_ADDRESSES_NEW (insn, -1);
6132 }
6133
6134 /* Switch back to previous section. */
6135 if (TARGET_CPU_ZARCH)
6136 {
6137 insn = emit_insn_after (gen_pool_section_end (), insn);
6138 INSN_ADDRESSES_NEW (insn, -1);
6139 }
6140
6141 insn = emit_barrier_after (insn);
6142 INSN_ADDRESSES_NEW (insn, -1);
6143
6144 /* Remove placeholder insn. */
6145 remove_insn (pool->pool_insn);
6146 }
6147
6148 /* Free all memory used by POOL. */
6149
6150 static void
6151 s390_free_pool (struct constant_pool *pool)
6152 {
6153 struct constant *c, *next;
6154 int i;
6155
6156 for (i = 0; i < NR_C_MODES; i++)
6157 for (c = pool->constants[i]; c; c = next)
6158 {
6159 next = c->next;
6160 free (c);
6161 }
6162
6163 for (c = pool->execute; c; c = next)
6164 {
6165 next = c->next;
6166 free (c);
6167 }
6168
6169 BITMAP_FREE (pool->insns);
6170 free (pool);
6171 }
6172
6173
6174 /* Collect main literal pool. Return NULL on overflow. */
6175
6176 static struct constant_pool *
6177 s390_mainpool_start (void)
6178 {
6179 struct constant_pool *pool;
6180 rtx insn;
6181
6182 pool = s390_alloc_pool ();
6183
6184 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6185 {
6186 if (GET_CODE (insn) == INSN
6187 && GET_CODE (PATTERN (insn)) == SET
6188 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6189 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6190 {
6191 gcc_assert (!pool->pool_insn);
6192 pool->pool_insn = insn;
6193 }
6194
6195 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6196 {
6197 s390_add_execute (pool, insn);
6198 }
6199 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6200 {
6201 rtx pool_ref = NULL_RTX;
6202 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6203 if (pool_ref)
6204 {
6205 rtx constant = get_pool_constant (pool_ref);
6206 enum machine_mode mode = get_pool_mode (pool_ref);
6207 s390_add_constant (pool, constant, mode);
6208 }
6209 }
6210
6211 /* If hot/cold partitioning is enabled we have to make sure that
6212 the literal pool is emitted in the same section where the
6213 initialization of the literal pool base pointer takes place.
6214 emit_pool_after is only used in the non-overflow case on non
6215 Z cpus where we can emit the literal pool at the end of the
6216 function body within the text section. */
6217 if (NOTE_P (insn)
6218 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6219 && !pool->emit_pool_after)
6220 pool->emit_pool_after = PREV_INSN (insn);
6221 }
6222
6223 gcc_assert (pool->pool_insn || pool->size == 0);
6224
6225 if (pool->size >= 4096)
6226 {
6227 /* We're going to chunkify the pool, so remove the main
6228 pool placeholder insn. */
6229 remove_insn (pool->pool_insn);
6230
6231 s390_free_pool (pool);
6232 pool = NULL;
6233 }
6234
6235 /* If the functions ends with the section where the literal pool
6236 should be emitted set the marker to its end. */
6237 if (pool && !pool->emit_pool_after)
6238 pool->emit_pool_after = get_last_insn ();
6239
6240 return pool;
6241 }
6242
6243 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6244 Modify the current function to output the pool constants as well as
6245 the pool register setup instruction. */
6246
6247 static void
6248 s390_mainpool_finish (struct constant_pool *pool)
6249 {
6250 rtx base_reg = cfun->machine->base_reg;
6251 rtx insn;
6252
6253 /* If the pool is empty, we're done. */
6254 if (pool->size == 0)
6255 {
6256 /* We don't actually need a base register after all. */
6257 cfun->machine->base_reg = NULL_RTX;
6258
6259 if (pool->pool_insn)
6260 remove_insn (pool->pool_insn);
6261 s390_free_pool (pool);
6262 return;
6263 }
6264
6265 /* We need correct insn addresses. */
6266 shorten_branches (get_insns ());
6267
6268 /* On zSeries, we use a LARL to load the pool register. The pool is
6269 located in the .rodata section, so we emit it after the function. */
6270 if (TARGET_CPU_ZARCH)
6271 {
6272 insn = gen_main_base_64 (base_reg, pool->label);
6273 insn = emit_insn_after (insn, pool->pool_insn);
6274 INSN_ADDRESSES_NEW (insn, -1);
6275 remove_insn (pool->pool_insn);
6276
6277 insn = get_last_insn ();
6278 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6279 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6280
6281 s390_dump_pool (pool, 0);
6282 }
6283
6284 /* On S/390, if the total size of the function's code plus literal pool
6285 does not exceed 4096 bytes, we use BASR to set up a function base
6286 pointer, and emit the literal pool at the end of the function. */
6287 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6288 + pool->size + 8 /* alignment slop */ < 4096)
6289 {
6290 insn = gen_main_base_31_small (base_reg, pool->label);
6291 insn = emit_insn_after (insn, pool->pool_insn);
6292 INSN_ADDRESSES_NEW (insn, -1);
6293 remove_insn (pool->pool_insn);
6294
6295 insn = emit_label_after (pool->label, insn);
6296 INSN_ADDRESSES_NEW (insn, -1);
6297
6298 /* emit_pool_after will be set by s390_mainpool_start to the
6299 last insn of the section where the literal pool should be
6300 emitted. */
6301 insn = pool->emit_pool_after;
6302
6303 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6304 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6305
6306 s390_dump_pool (pool, 1);
6307 }
6308
6309 /* Otherwise, we emit an inline literal pool and use BASR to branch
6310 over it, setting up the pool register at the same time. */
6311 else
6312 {
6313 rtx pool_end = gen_label_rtx ();
6314
6315 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6316 insn = emit_insn_after (insn, pool->pool_insn);
6317 INSN_ADDRESSES_NEW (insn, -1);
6318 remove_insn (pool->pool_insn);
6319
6320 insn = emit_label_after (pool->label, insn);
6321 INSN_ADDRESSES_NEW (insn, -1);
6322
6323 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6324 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6325
6326 insn = emit_label_after (pool_end, pool->pool_insn);
6327 INSN_ADDRESSES_NEW (insn, -1);
6328
6329 s390_dump_pool (pool, 1);
6330 }
6331
6332
6333 /* Replace all literal pool references. */
6334
6335 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6336 {
6337 if (INSN_P (insn))
6338 replace_ltrel_base (&PATTERN (insn));
6339
6340 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6341 {
6342 rtx addr, pool_ref = NULL_RTX;
6343 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6344 if (pool_ref)
6345 {
6346 if (s390_execute_label (insn))
6347 addr = s390_find_execute (pool, insn);
6348 else
6349 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6350 get_pool_mode (pool_ref));
6351
6352 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6353 INSN_CODE (insn) = -1;
6354 }
6355 }
6356 }
6357
6358
6359 /* Free the pool. */
6360 s390_free_pool (pool);
6361 }
6362
6363 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6364 We have decided we cannot use this pool, so revert all changes
6365 to the current function that were done by s390_mainpool_start. */
6366 static void
6367 s390_mainpool_cancel (struct constant_pool *pool)
6368 {
6369 /* We didn't actually change the instruction stream, so simply
6370 free the pool memory. */
6371 s390_free_pool (pool);
6372 }
6373
6374
6375 /* Chunkify the literal pool. */
6376
6377 #define S390_POOL_CHUNK_MIN 0xc00
6378 #define S390_POOL_CHUNK_MAX 0xe00
6379
6380 static struct constant_pool *
6381 s390_chunkify_start (void)
6382 {
6383 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6384 int extra_size = 0;
6385 bitmap far_labels;
6386 rtx pending_ltrel = NULL_RTX;
6387 rtx insn;
6388
6389 rtx (*gen_reload_base) (rtx, rtx) =
6390 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6391
6392
6393 /* We need correct insn addresses. */
6394
6395 shorten_branches (get_insns ());
6396
6397 /* Scan all insns and move literals to pool chunks. */
6398
6399 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6400 {
6401 bool section_switch_p = false;
6402
6403 /* Check for pending LTREL_BASE. */
6404 if (INSN_P (insn))
6405 {
6406 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6407 if (ltrel_base)
6408 {
6409 gcc_assert (ltrel_base == pending_ltrel);
6410 pending_ltrel = NULL_RTX;
6411 }
6412 }
6413
6414 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6415 {
6416 if (!curr_pool)
6417 curr_pool = s390_start_pool (&pool_list, insn);
6418
6419 s390_add_execute (curr_pool, insn);
6420 s390_add_pool_insn (curr_pool, insn);
6421 }
6422 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6423 {
6424 rtx pool_ref = NULL_RTX;
6425 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6426 if (pool_ref)
6427 {
6428 rtx constant = get_pool_constant (pool_ref);
6429 enum machine_mode mode = get_pool_mode (pool_ref);
6430
6431 if (!curr_pool)
6432 curr_pool = s390_start_pool (&pool_list, insn);
6433
6434 s390_add_constant (curr_pool, constant, mode);
6435 s390_add_pool_insn (curr_pool, insn);
6436
6437 /* Don't split the pool chunk between a LTREL_OFFSET load
6438 and the corresponding LTREL_BASE. */
6439 if (GET_CODE (constant) == CONST
6440 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6441 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6442 {
6443 gcc_assert (!pending_ltrel);
6444 pending_ltrel = pool_ref;
6445 }
6446 }
6447 }
6448
6449 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6450 {
6451 if (curr_pool)
6452 s390_add_pool_insn (curr_pool, insn);
6453 /* An LTREL_BASE must follow within the same basic block. */
6454 gcc_assert (!pending_ltrel);
6455 }
6456
6457 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6458 section_switch_p = true;
6459
6460 if (!curr_pool
6461 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6462 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6463 continue;
6464
6465 if (TARGET_CPU_ZARCH)
6466 {
6467 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6468 continue;
6469
6470 s390_end_pool (curr_pool, NULL_RTX);
6471 curr_pool = NULL;
6472 }
6473 else
6474 {
6475 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6476 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6477 + extra_size;
6478
6479 /* We will later have to insert base register reload insns.
6480 Those will have an effect on code size, which we need to
6481 consider here. This calculation makes rather pessimistic
6482 worst-case assumptions. */
6483 if (GET_CODE (insn) == CODE_LABEL)
6484 extra_size += 6;
6485
6486 if (chunk_size < S390_POOL_CHUNK_MIN
6487 && curr_pool->size < S390_POOL_CHUNK_MIN
6488 && !section_switch_p)
6489 continue;
6490
6491 /* Pool chunks can only be inserted after BARRIERs ... */
6492 if (GET_CODE (insn) == BARRIER)
6493 {
6494 s390_end_pool (curr_pool, insn);
6495 curr_pool = NULL;
6496 extra_size = 0;
6497 }
6498
6499 /* ... so if we don't find one in time, create one. */
6500 else if (chunk_size > S390_POOL_CHUNK_MAX
6501 || curr_pool->size > S390_POOL_CHUNK_MAX
6502 || section_switch_p)
6503 {
6504 rtx label, jump, barrier;
6505
6506 if (!section_switch_p)
6507 {
6508 /* We can insert the barrier only after a 'real' insn. */
6509 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6510 continue;
6511 if (get_attr_length (insn) == 0)
6512 continue;
6513 /* Don't separate LTREL_BASE from the corresponding
6514 LTREL_OFFSET load. */
6515 if (pending_ltrel)
6516 continue;
6517 }
6518 else
6519 {
6520 gcc_assert (!pending_ltrel);
6521
6522 /* The old pool has to end before the section switch
6523 note in order to make it part of the current
6524 section. */
6525 insn = PREV_INSN (insn);
6526 }
6527
6528 label = gen_label_rtx ();
6529 jump = emit_jump_insn_after (gen_jump (label), insn);
6530 barrier = emit_barrier_after (jump);
6531 insn = emit_label_after (label, barrier);
6532 JUMP_LABEL (jump) = label;
6533 LABEL_NUSES (label) = 1;
6534
6535 INSN_ADDRESSES_NEW (jump, -1);
6536 INSN_ADDRESSES_NEW (barrier, -1);
6537 INSN_ADDRESSES_NEW (insn, -1);
6538
6539 s390_end_pool (curr_pool, barrier);
6540 curr_pool = NULL;
6541 extra_size = 0;
6542 }
6543 }
6544 }
6545
6546 if (curr_pool)
6547 s390_end_pool (curr_pool, NULL_RTX);
6548 gcc_assert (!pending_ltrel);
6549
6550 /* Find all labels that are branched into
6551 from an insn belonging to a different chunk. */
6552
6553 far_labels = BITMAP_ALLOC (NULL);
6554
6555 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6556 {
6557 /* Labels marked with LABEL_PRESERVE_P can be target
6558 of non-local jumps, so we have to mark them.
6559 The same holds for named labels.
6560
6561 Don't do that, however, if it is the label before
6562 a jump table. */
6563
6564 if (GET_CODE (insn) == CODE_LABEL
6565 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6566 {
6567 rtx vec_insn = next_real_insn (insn);
6568 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6569 PATTERN (vec_insn) : NULL_RTX;
6570 if (!vec_pat
6571 || !(GET_CODE (vec_pat) == ADDR_VEC
6572 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6573 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6574 }
6575
6576 /* If we have a direct jump (conditional or unconditional)
6577 or a casesi jump, check all potential targets. */
6578 else if (GET_CODE (insn) == JUMP_INSN)
6579 {
6580 rtx pat = PATTERN (insn);
6581 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6582 pat = XVECEXP (pat, 0, 0);
6583
6584 if (GET_CODE (pat) == SET)
6585 {
6586 rtx label = JUMP_LABEL (insn);
6587 if (label)
6588 {
6589 if (s390_find_pool (pool_list, label)
6590 != s390_find_pool (pool_list, insn))
6591 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6592 }
6593 }
6594 else if (GET_CODE (pat) == PARALLEL
6595 && XVECLEN (pat, 0) == 2
6596 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6597 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6598 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6599 {
6600 /* Find the jump table used by this casesi jump. */
6601 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6602 rtx vec_insn = next_real_insn (vec_label);
6603 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6604 PATTERN (vec_insn) : NULL_RTX;
6605 if (vec_pat
6606 && (GET_CODE (vec_pat) == ADDR_VEC
6607 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6608 {
6609 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6610
6611 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6612 {
6613 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6614
6615 if (s390_find_pool (pool_list, label)
6616 != s390_find_pool (pool_list, insn))
6617 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6618 }
6619 }
6620 }
6621 }
6622 }
6623
6624 /* Insert base register reload insns before every pool. */
6625
6626 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6627 {
6628 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6629 curr_pool->label);
6630 rtx insn = curr_pool->first_insn;
6631 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6632 }
6633
6634 /* Insert base register reload insns at every far label. */
6635
6636 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6637 if (GET_CODE (insn) == CODE_LABEL
6638 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6639 {
6640 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6641 if (pool)
6642 {
6643 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6644 pool->label);
6645 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6646 }
6647 }
6648
6649
6650 BITMAP_FREE (far_labels);
6651
6652
6653 /* Recompute insn addresses. */
6654
6655 init_insn_lengths ();
6656 shorten_branches (get_insns ());
6657
6658 return pool_list;
6659 }
6660
6661 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6662 After we have decided to use this list, finish implementing
6663 all changes to the current function as required. */
6664
6665 static void
6666 s390_chunkify_finish (struct constant_pool *pool_list)
6667 {
6668 struct constant_pool *curr_pool = NULL;
6669 rtx insn;
6670
6671
6672 /* Replace all literal pool references. */
6673
6674 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6675 {
6676 if (INSN_P (insn))
6677 replace_ltrel_base (&PATTERN (insn));
6678
6679 curr_pool = s390_find_pool (pool_list, insn);
6680 if (!curr_pool)
6681 continue;
6682
6683 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6684 {
6685 rtx addr, pool_ref = NULL_RTX;
6686 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6687 if (pool_ref)
6688 {
6689 if (s390_execute_label (insn))
6690 addr = s390_find_execute (curr_pool, insn);
6691 else
6692 addr = s390_find_constant (curr_pool,
6693 get_pool_constant (pool_ref),
6694 get_pool_mode (pool_ref));
6695
6696 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6697 INSN_CODE (insn) = -1;
6698 }
6699 }
6700 }
6701
6702 /* Dump out all literal pools. */
6703
6704 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6705 s390_dump_pool (curr_pool, 0);
6706
6707 /* Free pool list. */
6708
6709 while (pool_list)
6710 {
6711 struct constant_pool *next = pool_list->next;
6712 s390_free_pool (pool_list);
6713 pool_list = next;
6714 }
6715 }
6716
6717 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6718 We have decided we cannot use this list, so revert all changes
6719 to the current function that were done by s390_chunkify_start. */
6720
6721 static void
6722 s390_chunkify_cancel (struct constant_pool *pool_list)
6723 {
6724 struct constant_pool *curr_pool = NULL;
6725 rtx insn;
6726
6727 /* Remove all pool placeholder insns. */
6728
6729 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6730 {
6731 /* Did we insert an extra barrier? Remove it. */
6732 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6733 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6734 rtx label = NEXT_INSN (curr_pool->pool_insn);
6735
6736 if (jump && GET_CODE (jump) == JUMP_INSN
6737 && barrier && GET_CODE (barrier) == BARRIER
6738 && label && GET_CODE (label) == CODE_LABEL
6739 && GET_CODE (PATTERN (jump)) == SET
6740 && SET_DEST (PATTERN (jump)) == pc_rtx
6741 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6742 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6743 {
6744 remove_insn (jump);
6745 remove_insn (barrier);
6746 remove_insn (label);
6747 }
6748
6749 remove_insn (curr_pool->pool_insn);
6750 }
6751
6752 /* Remove all base register reload insns. */
6753
6754 for (insn = get_insns (); insn; )
6755 {
6756 rtx next_insn = NEXT_INSN (insn);
6757
6758 if (GET_CODE (insn) == INSN
6759 && GET_CODE (PATTERN (insn)) == SET
6760 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6761 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6762 remove_insn (insn);
6763
6764 insn = next_insn;
6765 }
6766
6767 /* Free pool list. */
6768
6769 while (pool_list)
6770 {
6771 struct constant_pool *next = pool_list->next;
6772 s390_free_pool (pool_list);
6773 pool_list = next;
6774 }
6775 }
6776
6777 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6778
6779 void
6780 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6781 {
6782 REAL_VALUE_TYPE r;
6783
6784 switch (GET_MODE_CLASS (mode))
6785 {
6786 case MODE_FLOAT:
6787 case MODE_DECIMAL_FLOAT:
6788 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6789
6790 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6791 assemble_real (r, mode, align);
6792 break;
6793
6794 case MODE_INT:
6795 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6796 mark_symbol_refs_as_used (exp);
6797 break;
6798
6799 default:
6800 gcc_unreachable ();
6801 }
6802 }
6803
6804
6805 /* Return an RTL expression representing the value of the return address
6806 for the frame COUNT steps up from the current frame. FRAME is the
6807 frame pointer of that frame. */
6808
6809 rtx
6810 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6811 {
6812 int offset;
6813 rtx addr;
6814
6815 /* Without backchain, we fail for all but the current frame. */
6816
6817 if (!TARGET_BACKCHAIN && count > 0)
6818 return NULL_RTX;
6819
6820 /* For the current frame, we need to make sure the initial
6821 value of RETURN_REGNUM is actually saved. */
6822
6823 if (count == 0)
6824 {
6825 /* On non-z architectures branch splitting could overwrite r14. */
6826 if (TARGET_CPU_ZARCH)
6827 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6828 else
6829 {
6830 cfun_frame_layout.save_return_addr_p = true;
6831 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6832 }
6833 }
6834
6835 if (TARGET_PACKED_STACK)
6836 offset = -2 * UNITS_PER_LONG;
6837 else
6838 offset = RETURN_REGNUM * UNITS_PER_LONG;
6839
6840 addr = plus_constant (frame, offset);
6841 addr = memory_address (Pmode, addr);
6842 return gen_rtx_MEM (Pmode, addr);
6843 }
6844
6845 /* Return an RTL expression representing the back chain stored in
6846 the current stack frame. */
6847
6848 rtx
6849 s390_back_chain_rtx (void)
6850 {
6851 rtx chain;
6852
6853 gcc_assert (TARGET_BACKCHAIN);
6854
6855 if (TARGET_PACKED_STACK)
6856 chain = plus_constant (stack_pointer_rtx,
6857 STACK_POINTER_OFFSET - UNITS_PER_LONG);
6858 else
6859 chain = stack_pointer_rtx;
6860
6861 chain = gen_rtx_MEM (Pmode, chain);
6862 return chain;
6863 }
6864
6865 /* Find first call clobbered register unused in a function.
6866 This could be used as base register in a leaf function
6867 or for holding the return address before epilogue. */
6868
6869 static int
6870 find_unused_clobbered_reg (void)
6871 {
6872 int i;
6873 for (i = 0; i < 6; i++)
6874 if (!df_regs_ever_live_p (i))
6875 return i;
6876 return 0;
6877 }
6878
6879
6880 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6881 clobbered hard regs in SETREG. */
6882
6883 static void
6884 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6885 {
6886 int *regs_ever_clobbered = (int *)data;
6887 unsigned int i, regno;
6888 enum machine_mode mode = GET_MODE (setreg);
6889
6890 if (GET_CODE (setreg) == SUBREG)
6891 {
6892 rtx inner = SUBREG_REG (setreg);
6893 if (!GENERAL_REG_P (inner))
6894 return;
6895 regno = subreg_regno (setreg);
6896 }
6897 else if (GENERAL_REG_P (setreg))
6898 regno = REGNO (setreg);
6899 else
6900 return;
6901
6902 for (i = regno;
6903 i < regno + HARD_REGNO_NREGS (regno, mode);
6904 i++)
6905 regs_ever_clobbered[i] = 1;
6906 }
6907
6908 /* Walks through all basic blocks of the current function looking
6909 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6910 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6911 each of those regs. */
6912
6913 static void
6914 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6915 {
6916 basic_block cur_bb;
6917 rtx cur_insn;
6918 unsigned int i;
6919
6920 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6921
6922 /* For non-leaf functions we have to consider all call clobbered regs to be
6923 clobbered. */
6924 if (!current_function_is_leaf)
6925 {
6926 for (i = 0; i < 16; i++)
6927 regs_ever_clobbered[i] = call_really_used_regs[i];
6928 }
6929
6930 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6931 this work is done by liveness analysis (mark_regs_live_at_end).
6932 Special care is needed for functions containing landing pads. Landing pads
6933 may use the eh registers, but the code which sets these registers is not
6934 contained in that function. Hence s390_regs_ever_clobbered is not able to
6935 deal with this automatically. */
6936 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6937 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6938 if (crtl->calls_eh_return
6939 || (cfun->machine->has_landing_pad_p
6940 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6941 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6942
6943 /* For nonlocal gotos all call-saved registers have to be saved.
6944 This flag is also set for the unwinding code in libgcc.
6945 See expand_builtin_unwind_init. For regs_ever_live this is done by
6946 reload. */
6947 if (cfun->has_nonlocal_label)
6948 for (i = 0; i < 16; i++)
6949 if (!call_really_used_regs[i])
6950 regs_ever_clobbered[i] = 1;
6951
6952 FOR_EACH_BB (cur_bb)
6953 {
6954 FOR_BB_INSNS (cur_bb, cur_insn)
6955 {
6956 if (INSN_P (cur_insn))
6957 note_stores (PATTERN (cur_insn),
6958 s390_reg_clobbered_rtx,
6959 regs_ever_clobbered);
6960 }
6961 }
6962 }
6963
6964 /* Determine the frame area which actually has to be accessed
6965 in the function epilogue. The values are stored at the
6966 given pointers AREA_BOTTOM (address of the lowest used stack
6967 address) and AREA_TOP (address of the first item which does
6968 not belong to the stack frame). */
6969
6970 static void
6971 s390_frame_area (int *area_bottom, int *area_top)
6972 {
6973 int b, t;
6974 int i;
6975
6976 b = INT_MAX;
6977 t = INT_MIN;
6978
6979 if (cfun_frame_layout.first_restore_gpr != -1)
6980 {
6981 b = (cfun_frame_layout.gprs_offset
6982 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
6983 t = b + (cfun_frame_layout.last_restore_gpr
6984 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
6985 }
6986
6987 if (TARGET_64BIT && cfun_save_high_fprs_p)
6988 {
6989 b = MIN (b, cfun_frame_layout.f8_offset);
6990 t = MAX (t, (cfun_frame_layout.f8_offset
6991 + cfun_frame_layout.high_fprs * 8));
6992 }
6993
6994 if (!TARGET_64BIT)
6995 for (i = 2; i < 4; i++)
6996 if (cfun_fpr_bit_p (i))
6997 {
6998 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6999 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7000 }
7001
7002 *area_bottom = b;
7003 *area_top = t;
7004 }
7005
7006 /* Fill cfun->machine with info about register usage of current function.
7007 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7008
7009 static void
7010 s390_register_info (int clobbered_regs[])
7011 {
7012 int i, j;
7013
7014 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7015 cfun_frame_layout.fpr_bitmap = 0;
7016 cfun_frame_layout.high_fprs = 0;
7017 if (TARGET_64BIT)
7018 for (i = 24; i < 32; i++)
7019 if (df_regs_ever_live_p (i) && !global_regs[i])
7020 {
7021 cfun_set_fpr_bit (i - 16);
7022 cfun_frame_layout.high_fprs++;
7023 }
7024
7025 /* Find first and last gpr to be saved. We trust regs_ever_live
7026 data, except that we don't save and restore global registers.
7027
7028 Also, all registers with special meaning to the compiler need
7029 to be handled extra. */
7030
7031 s390_regs_ever_clobbered (clobbered_regs);
7032
7033 for (i = 0; i < 16; i++)
7034 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7035
7036 if (frame_pointer_needed)
7037 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7038
7039 if (flag_pic)
7040 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7041 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7042
7043 clobbered_regs[BASE_REGNUM]
7044 |= (cfun->machine->base_reg
7045 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7046
7047 clobbered_regs[RETURN_REGNUM]
7048 |= (!current_function_is_leaf
7049 || TARGET_TPF_PROFILING
7050 || cfun->machine->split_branches_pending_p
7051 || cfun_frame_layout.save_return_addr_p
7052 || crtl->calls_eh_return
7053 || cfun->stdarg);
7054
7055 clobbered_regs[STACK_POINTER_REGNUM]
7056 |= (!current_function_is_leaf
7057 || TARGET_TPF_PROFILING
7058 || cfun_save_high_fprs_p
7059 || get_frame_size () > 0
7060 || cfun->calls_alloca
7061 || cfun->stdarg);
7062
7063 for (i = 6; i < 16; i++)
7064 if (df_regs_ever_live_p (i) || clobbered_regs[i])
7065 break;
7066 for (j = 15; j > i; j--)
7067 if (df_regs_ever_live_p (j) || clobbered_regs[j])
7068 break;
7069
7070 if (i == 16)
7071 {
7072 /* Nothing to save/restore. */
7073 cfun_frame_layout.first_save_gpr_slot = -1;
7074 cfun_frame_layout.last_save_gpr_slot = -1;
7075 cfun_frame_layout.first_save_gpr = -1;
7076 cfun_frame_layout.first_restore_gpr = -1;
7077 cfun_frame_layout.last_save_gpr = -1;
7078 cfun_frame_layout.last_restore_gpr = -1;
7079 }
7080 else
7081 {
7082 /* Save slots for gprs from i to j. */
7083 cfun_frame_layout.first_save_gpr_slot = i;
7084 cfun_frame_layout.last_save_gpr_slot = j;
7085
7086 for (i = cfun_frame_layout.first_save_gpr_slot;
7087 i < cfun_frame_layout.last_save_gpr_slot + 1;
7088 i++)
7089 if (clobbered_regs[i])
7090 break;
7091
7092 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7093 if (clobbered_regs[j])
7094 break;
7095
7096 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7097 {
7098 /* Nothing to save/restore. */
7099 cfun_frame_layout.first_save_gpr = -1;
7100 cfun_frame_layout.first_restore_gpr = -1;
7101 cfun_frame_layout.last_save_gpr = -1;
7102 cfun_frame_layout.last_restore_gpr = -1;
7103 }
7104 else
7105 {
7106 /* Save / Restore from gpr i to j. */
7107 cfun_frame_layout.first_save_gpr = i;
7108 cfun_frame_layout.first_restore_gpr = i;
7109 cfun_frame_layout.last_save_gpr = j;
7110 cfun_frame_layout.last_restore_gpr = j;
7111 }
7112 }
7113
7114 if (cfun->stdarg)
7115 {
7116 /* Varargs functions need to save gprs 2 to 6. */
7117 if (cfun->va_list_gpr_size
7118 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7119 {
7120 int min_gpr = crtl->args.info.gprs;
7121 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7122 if (max_gpr > GP_ARG_NUM_REG)
7123 max_gpr = GP_ARG_NUM_REG;
7124
7125 if (cfun_frame_layout.first_save_gpr == -1
7126 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7127 {
7128 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7129 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7130 }
7131
7132 if (cfun_frame_layout.last_save_gpr == -1
7133 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7134 {
7135 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7136 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7137 }
7138 }
7139
7140 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7141 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7142 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7143 {
7144 int min_fpr = crtl->args.info.fprs;
7145 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7146 if (max_fpr > FP_ARG_NUM_REG)
7147 max_fpr = FP_ARG_NUM_REG;
7148
7149 /* ??? This is currently required to ensure proper location
7150 of the fpr save slots within the va_list save area. */
7151 if (TARGET_PACKED_STACK)
7152 min_fpr = 0;
7153
7154 for (i = min_fpr; i < max_fpr; i++)
7155 cfun_set_fpr_bit (i);
7156 }
7157 }
7158
7159 if (!TARGET_64BIT)
7160 for (i = 2; i < 4; i++)
7161 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7162 cfun_set_fpr_bit (i);
7163 }
7164
7165 /* Fill cfun->machine with info about frame of current function. */
7166
7167 static void
7168 s390_frame_info (void)
7169 {
7170 int i;
7171
7172 cfun_frame_layout.frame_size = get_frame_size ();
7173 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7174 fatal_error ("total size of local variables exceeds architecture limit");
7175
7176 if (!TARGET_PACKED_STACK)
7177 {
7178 cfun_frame_layout.backchain_offset = 0;
7179 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7180 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7181 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7182 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7183 * UNITS_PER_LONG);
7184 }
7185 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7186 {
7187 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7188 - UNITS_PER_LONG);
7189 cfun_frame_layout.gprs_offset
7190 = (cfun_frame_layout.backchain_offset
7191 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7192 * UNITS_PER_LONG);
7193
7194 if (TARGET_64BIT)
7195 {
7196 cfun_frame_layout.f4_offset
7197 = (cfun_frame_layout.gprs_offset
7198 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7199
7200 cfun_frame_layout.f0_offset
7201 = (cfun_frame_layout.f4_offset
7202 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7203 }
7204 else
7205 {
7206 /* On 31 bit we have to care about alignment of the
7207 floating point regs to provide fastest access. */
7208 cfun_frame_layout.f0_offset
7209 = ((cfun_frame_layout.gprs_offset
7210 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7211 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7212
7213 cfun_frame_layout.f4_offset
7214 = (cfun_frame_layout.f0_offset
7215 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7216 }
7217 }
7218 else /* no backchain */
7219 {
7220 cfun_frame_layout.f4_offset
7221 = (STACK_POINTER_OFFSET
7222 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7223
7224 cfun_frame_layout.f0_offset
7225 = (cfun_frame_layout.f4_offset
7226 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7227
7228 cfun_frame_layout.gprs_offset
7229 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7230 }
7231
7232 if (current_function_is_leaf
7233 && !TARGET_TPF_PROFILING
7234 && cfun_frame_layout.frame_size == 0
7235 && !cfun_save_high_fprs_p
7236 && !cfun->calls_alloca
7237 && !cfun->stdarg)
7238 return;
7239
7240 if (!TARGET_PACKED_STACK)
7241 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7242 + crtl->outgoing_args_size
7243 + cfun_frame_layout.high_fprs * 8);
7244 else
7245 {
7246 if (TARGET_BACKCHAIN)
7247 cfun_frame_layout.frame_size += UNITS_PER_LONG;
7248
7249 /* No alignment trouble here because f8-f15 are only saved under
7250 64 bit. */
7251 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7252 cfun_frame_layout.f4_offset),
7253 cfun_frame_layout.gprs_offset)
7254 - cfun_frame_layout.high_fprs * 8);
7255
7256 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7257
7258 for (i = 0; i < 8; i++)
7259 if (cfun_fpr_bit_p (i))
7260 cfun_frame_layout.frame_size += 8;
7261
7262 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7263
7264 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7265 the frame size to sustain 8 byte alignment of stack frames. */
7266 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7267 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7268 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7269
7270 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7271 }
7272 }
7273
7274 /* Generate frame layout. Fills in register and frame data for the current
7275 function in cfun->machine. This routine can be called multiple times;
7276 it will re-do the complete frame layout every time. */
7277
7278 static void
7279 s390_init_frame_layout (void)
7280 {
7281 HOST_WIDE_INT frame_size;
7282 int base_used;
7283 int clobbered_regs[16];
7284
7285 /* On S/390 machines, we may need to perform branch splitting, which
7286 will require both base and return address register. We have no
7287 choice but to assume we're going to need them until right at the
7288 end of the machine dependent reorg phase. */
7289 if (!TARGET_CPU_ZARCH)
7290 cfun->machine->split_branches_pending_p = true;
7291
7292 do
7293 {
7294 frame_size = cfun_frame_layout.frame_size;
7295
7296 /* Try to predict whether we'll need the base register. */
7297 base_used = cfun->machine->split_branches_pending_p
7298 || crtl->uses_const_pool
7299 || (!DISP_IN_RANGE (frame_size)
7300 && !CONST_OK_FOR_K (frame_size));
7301
7302 /* Decide which register to use as literal pool base. In small
7303 leaf functions, try to use an unused call-clobbered register
7304 as base register to avoid save/restore overhead. */
7305 if (!base_used)
7306 cfun->machine->base_reg = NULL_RTX;
7307 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7308 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7309 else
7310 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7311
7312 s390_register_info (clobbered_regs);
7313 s390_frame_info ();
7314 }
7315 while (frame_size != cfun_frame_layout.frame_size);
7316 }
7317
7318 /* Update frame layout. Recompute actual register save data based on
7319 current info and update regs_ever_live for the special registers.
7320 May be called multiple times, but may never cause *more* registers
7321 to be saved than s390_init_frame_layout allocated room for. */
7322
7323 static void
7324 s390_update_frame_layout (void)
7325 {
7326 int clobbered_regs[16];
7327
7328 s390_register_info (clobbered_regs);
7329
7330 df_set_regs_ever_live (BASE_REGNUM,
7331 clobbered_regs[BASE_REGNUM] ? true : false);
7332 df_set_regs_ever_live (RETURN_REGNUM,
7333 clobbered_regs[RETURN_REGNUM] ? true : false);
7334 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7335 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7336
7337 if (cfun->machine->base_reg)
7338 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7339 }
7340
7341 /* Return true if it is legal to put a value with MODE into REGNO. */
7342
7343 bool
7344 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7345 {
7346 switch (REGNO_REG_CLASS (regno))
7347 {
7348 case FP_REGS:
7349 if (REGNO_PAIR_OK (regno, mode))
7350 {
7351 if (mode == SImode || mode == DImode)
7352 return true;
7353
7354 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7355 return true;
7356 }
7357 break;
7358 case ADDR_REGS:
7359 if (FRAME_REGNO_P (regno) && mode == Pmode)
7360 return true;
7361
7362 /* fallthrough */
7363 case GENERAL_REGS:
7364 if (REGNO_PAIR_OK (regno, mode))
7365 {
7366 if (TARGET_ZARCH
7367 || (mode != TFmode && mode != TCmode && mode != TDmode))
7368 return true;
7369 }
7370 break;
7371 case CC_REGS:
7372 if (GET_MODE_CLASS (mode) == MODE_CC)
7373 return true;
7374 break;
7375 case ACCESS_REGS:
7376 if (REGNO_PAIR_OK (regno, mode))
7377 {
7378 if (mode == SImode || mode == Pmode)
7379 return true;
7380 }
7381 break;
7382 default:
7383 return false;
7384 }
7385
7386 return false;
7387 }
7388
7389 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7390
7391 bool
7392 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7393 {
7394 /* Once we've decided upon a register to use as base register, it must
7395 no longer be used for any other purpose. */
7396 if (cfun->machine->base_reg)
7397 if (REGNO (cfun->machine->base_reg) == old_reg
7398 || REGNO (cfun->machine->base_reg) == new_reg)
7399 return false;
7400
7401 return true;
7402 }
7403
7404 /* Maximum number of registers to represent a value of mode MODE
7405 in a register of class RCLASS. */
7406
7407 bool
7408 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7409 {
7410 switch (rclass)
7411 {
7412 case FP_REGS:
7413 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7414 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7415 else
7416 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7417 case ACCESS_REGS:
7418 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7419 default:
7420 break;
7421 }
7422 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7423 }
7424
7425 /* Return true if register FROM can be eliminated via register TO. */
7426
7427 static bool
7428 s390_can_eliminate (const int from, const int to)
7429 {
7430 /* On zSeries machines, we have not marked the base register as fixed.
7431 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7432 If a function requires the base register, we say here that this
7433 elimination cannot be performed. This will cause reload to free
7434 up the base register (as if it were fixed). On the other hand,
7435 if the current function does *not* require the base register, we
7436 say here the elimination succeeds, which in turn allows reload
7437 to allocate the base register for any other purpose. */
7438 if (from == BASE_REGNUM && to == BASE_REGNUM)
7439 {
7440 if (TARGET_CPU_ZARCH)
7441 {
7442 s390_init_frame_layout ();
7443 return cfun->machine->base_reg == NULL_RTX;
7444 }
7445
7446 return false;
7447 }
7448
7449 /* Everything else must point into the stack frame. */
7450 gcc_assert (to == STACK_POINTER_REGNUM
7451 || to == HARD_FRAME_POINTER_REGNUM);
7452
7453 gcc_assert (from == FRAME_POINTER_REGNUM
7454 || from == ARG_POINTER_REGNUM
7455 || from == RETURN_ADDRESS_POINTER_REGNUM);
7456
7457 /* Make sure we actually saved the return address. */
7458 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7459 if (!crtl->calls_eh_return
7460 && !cfun->stdarg
7461 && !cfun_frame_layout.save_return_addr_p)
7462 return false;
7463
7464 return true;
7465 }
7466
7467 /* Return offset between register FROM and TO initially after prolog. */
7468
7469 HOST_WIDE_INT
7470 s390_initial_elimination_offset (int from, int to)
7471 {
7472 HOST_WIDE_INT offset;
7473 int index;
7474
7475 /* ??? Why are we called for non-eliminable pairs? */
7476 if (!s390_can_eliminate (from, to))
7477 return 0;
7478
7479 switch (from)
7480 {
7481 case FRAME_POINTER_REGNUM:
7482 offset = (get_frame_size()
7483 + STACK_POINTER_OFFSET
7484 + crtl->outgoing_args_size);
7485 break;
7486
7487 case ARG_POINTER_REGNUM:
7488 s390_init_frame_layout ();
7489 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7490 break;
7491
7492 case RETURN_ADDRESS_POINTER_REGNUM:
7493 s390_init_frame_layout ();
7494 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7495 gcc_assert (index >= 0);
7496 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7497 offset += index * UNITS_PER_LONG;
7498 break;
7499
7500 case BASE_REGNUM:
7501 offset = 0;
7502 break;
7503
7504 default:
7505 gcc_unreachable ();
7506 }
7507
7508 return offset;
7509 }
7510
7511 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7512 to register BASE. Return generated insn. */
7513
7514 static rtx
7515 save_fpr (rtx base, int offset, int regnum)
7516 {
7517 rtx addr;
7518 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7519
7520 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7521 set_mem_alias_set (addr, get_varargs_alias_set ());
7522 else
7523 set_mem_alias_set (addr, get_frame_alias_set ());
7524
7525 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7526 }
7527
7528 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7529 to register BASE. Return generated insn. */
7530
7531 static rtx
7532 restore_fpr (rtx base, int offset, int regnum)
7533 {
7534 rtx addr;
7535 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7536 set_mem_alias_set (addr, get_frame_alias_set ());
7537
7538 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7539 }
7540
7541 /* Return true if REGNO is a global register, but not one
7542 of the special ones that need to be saved/restored in anyway. */
7543
7544 static inline bool
7545 global_not_special_regno_p (int regno)
7546 {
7547 return (global_regs[regno]
7548 /* These registers are special and need to be
7549 restored in any case. */
7550 && !(regno == STACK_POINTER_REGNUM
7551 || regno == RETURN_REGNUM
7552 || regno == BASE_REGNUM
7553 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7554 }
7555
7556 /* Generate insn to save registers FIRST to LAST into
7557 the register save area located at offset OFFSET
7558 relative to register BASE. */
7559
7560 static rtx
7561 save_gprs (rtx base, int offset, int first, int last)
7562 {
7563 rtx addr, insn, note;
7564 int i;
7565
7566 addr = plus_constant (base, offset);
7567 addr = gen_rtx_MEM (Pmode, addr);
7568
7569 set_mem_alias_set (addr, get_frame_alias_set ());
7570
7571 /* Special-case single register. */
7572 if (first == last)
7573 {
7574 if (TARGET_64BIT)
7575 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7576 else
7577 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7578
7579 if (!global_not_special_regno_p (first))
7580 RTX_FRAME_RELATED_P (insn) = 1;
7581 return insn;
7582 }
7583
7584
7585 insn = gen_store_multiple (addr,
7586 gen_rtx_REG (Pmode, first),
7587 GEN_INT (last - first + 1));
7588
7589 if (first <= 6 && cfun->stdarg)
7590 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7591 {
7592 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7593
7594 if (first + i <= 6)
7595 set_mem_alias_set (mem, get_varargs_alias_set ());
7596 }
7597
7598 /* We need to set the FRAME_RELATED flag on all SETs
7599 inside the store-multiple pattern.
7600
7601 However, we must not emit DWARF records for registers 2..5
7602 if they are stored for use by variable arguments ...
7603
7604 ??? Unfortunately, it is not enough to simply not the
7605 FRAME_RELATED flags for those SETs, because the first SET
7606 of the PARALLEL is always treated as if it had the flag
7607 set, even if it does not. Therefore we emit a new pattern
7608 without those registers as REG_FRAME_RELATED_EXPR note. */
7609
7610 if (first >= 6 && !global_not_special_regno_p (first))
7611 {
7612 rtx pat = PATTERN (insn);
7613
7614 for (i = 0; i < XVECLEN (pat, 0); i++)
7615 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7616 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7617 0, i)))))
7618 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7619
7620 RTX_FRAME_RELATED_P (insn) = 1;
7621 }
7622 else if (last >= 6)
7623 {
7624 int start;
7625
7626 for (start = first >= 6 ? first : 6; start <= last; start++)
7627 if (!global_not_special_regno_p (start))
7628 break;
7629
7630 if (start > last)
7631 return insn;
7632
7633 addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7634 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7635 gen_rtx_REG (Pmode, start),
7636 GEN_INT (last - start + 1));
7637 note = PATTERN (note);
7638
7639 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7640
7641 for (i = 0; i < XVECLEN (note, 0); i++)
7642 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7643 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7644 0, i)))))
7645 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7646
7647 RTX_FRAME_RELATED_P (insn) = 1;
7648 }
7649
7650 return insn;
7651 }
7652
7653 /* Generate insn to restore registers FIRST to LAST from
7654 the register save area located at offset OFFSET
7655 relative to register BASE. */
7656
7657 static rtx
7658 restore_gprs (rtx base, int offset, int first, int last)
7659 {
7660 rtx addr, insn;
7661
7662 addr = plus_constant (base, offset);
7663 addr = gen_rtx_MEM (Pmode, addr);
7664 set_mem_alias_set (addr, get_frame_alias_set ());
7665
7666 /* Special-case single register. */
7667 if (first == last)
7668 {
7669 if (TARGET_64BIT)
7670 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7671 else
7672 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7673
7674 return insn;
7675 }
7676
7677 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7678 addr,
7679 GEN_INT (last - first + 1));
7680 return insn;
7681 }
7682
7683 /* Return insn sequence to load the GOT register. */
7684
7685 static GTY(()) rtx got_symbol;
7686 rtx
7687 s390_load_got (void)
7688 {
7689 rtx insns;
7690
7691 if (!got_symbol)
7692 {
7693 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7694 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7695 }
7696
7697 start_sequence ();
7698
7699 if (TARGET_CPU_ZARCH)
7700 {
7701 emit_move_insn (pic_offset_table_rtx, got_symbol);
7702 }
7703 else
7704 {
7705 rtx offset;
7706
7707 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7708 UNSPEC_LTREL_OFFSET);
7709 offset = gen_rtx_CONST (Pmode, offset);
7710 offset = force_const_mem (Pmode, offset);
7711
7712 emit_move_insn (pic_offset_table_rtx, offset);
7713
7714 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7715 UNSPEC_LTREL_BASE);
7716 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7717
7718 emit_move_insn (pic_offset_table_rtx, offset);
7719 }
7720
7721 insns = get_insns ();
7722 end_sequence ();
7723 return insns;
7724 }
7725
7726 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7727 and the change to the stack pointer. */
7728
7729 static void
7730 s390_emit_stack_tie (void)
7731 {
7732 rtx mem = gen_frame_mem (BLKmode,
7733 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7734
7735 emit_insn (gen_stack_tie (mem));
7736 }
7737
7738 /* Expand the prologue into a bunch of separate insns. */
7739
7740 void
7741 s390_emit_prologue (void)
7742 {
7743 rtx insn, addr;
7744 rtx temp_reg;
7745 int i;
7746 int offset;
7747 int next_fpr = 0;
7748
7749 /* Complete frame layout. */
7750
7751 s390_update_frame_layout ();
7752
7753 /* Annotate all constant pool references to let the scheduler know
7754 they implicitly use the base register. */
7755
7756 push_topmost_sequence ();
7757
7758 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7759 if (INSN_P (insn))
7760 {
7761 annotate_constant_pool_refs (&PATTERN (insn));
7762 df_insn_rescan (insn);
7763 }
7764
7765 pop_topmost_sequence ();
7766
7767 /* Choose best register to use for temp use within prologue.
7768 See below for why TPF must use the register 1. */
7769
7770 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7771 && !current_function_is_leaf
7772 && !TARGET_TPF_PROFILING)
7773 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7774 else
7775 temp_reg = gen_rtx_REG (Pmode, 1);
7776
7777 /* Save call saved gprs. */
7778 if (cfun_frame_layout.first_save_gpr != -1)
7779 {
7780 insn = save_gprs (stack_pointer_rtx,
7781 cfun_frame_layout.gprs_offset +
7782 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7783 - cfun_frame_layout.first_save_gpr_slot),
7784 cfun_frame_layout.first_save_gpr,
7785 cfun_frame_layout.last_save_gpr);
7786 emit_insn (insn);
7787 }
7788
7789 /* Dummy insn to mark literal pool slot. */
7790
7791 if (cfun->machine->base_reg)
7792 emit_insn (gen_main_pool (cfun->machine->base_reg));
7793
7794 offset = cfun_frame_layout.f0_offset;
7795
7796 /* Save f0 and f2. */
7797 for (i = 0; i < 2; i++)
7798 {
7799 if (cfun_fpr_bit_p (i))
7800 {
7801 save_fpr (stack_pointer_rtx, offset, i + 16);
7802 offset += 8;
7803 }
7804 else if (!TARGET_PACKED_STACK)
7805 offset += 8;
7806 }
7807
7808 /* Save f4 and f6. */
7809 offset = cfun_frame_layout.f4_offset;
7810 for (i = 2; i < 4; i++)
7811 {
7812 if (cfun_fpr_bit_p (i))
7813 {
7814 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7815 offset += 8;
7816
7817 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7818 therefore are not frame related. */
7819 if (!call_really_used_regs[i + 16])
7820 RTX_FRAME_RELATED_P (insn) = 1;
7821 }
7822 else if (!TARGET_PACKED_STACK)
7823 offset += 8;
7824 }
7825
7826 if (TARGET_PACKED_STACK
7827 && cfun_save_high_fprs_p
7828 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7829 {
7830 offset = (cfun_frame_layout.f8_offset
7831 + (cfun_frame_layout.high_fprs - 1) * 8);
7832
7833 for (i = 15; i > 7 && offset >= 0; i--)
7834 if (cfun_fpr_bit_p (i))
7835 {
7836 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7837
7838 RTX_FRAME_RELATED_P (insn) = 1;
7839 offset -= 8;
7840 }
7841 if (offset >= cfun_frame_layout.f8_offset)
7842 next_fpr = i + 16;
7843 }
7844
7845 if (!TARGET_PACKED_STACK)
7846 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7847
7848 /* Decrement stack pointer. */
7849
7850 if (cfun_frame_layout.frame_size > 0)
7851 {
7852 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7853 rtx real_frame_off;
7854
7855 if (s390_stack_size)
7856 {
7857 HOST_WIDE_INT stack_guard;
7858
7859 if (s390_stack_guard)
7860 stack_guard = s390_stack_guard;
7861 else
7862 {
7863 /* If no value for stack guard is provided the smallest power of 2
7864 larger than the current frame size is chosen. */
7865 stack_guard = 1;
7866 while (stack_guard < cfun_frame_layout.frame_size)
7867 stack_guard <<= 1;
7868 }
7869
7870 if (cfun_frame_layout.frame_size >= s390_stack_size)
7871 {
7872 warning (0, "frame size of function %qs is "
7873 HOST_WIDE_INT_PRINT_DEC
7874 " bytes exceeding user provided stack limit of "
7875 HOST_WIDE_INT_PRINT_DEC " bytes. "
7876 "An unconditional trap is added.",
7877 current_function_name(), cfun_frame_layout.frame_size,
7878 s390_stack_size);
7879 emit_insn (gen_trap ());
7880 }
7881 else
7882 {
7883 /* stack_guard has to be smaller than s390_stack_size.
7884 Otherwise we would emit an AND with zero which would
7885 not match the test under mask pattern. */
7886 if (stack_guard >= s390_stack_size)
7887 {
7888 warning (0, "frame size of function %qs is "
7889 HOST_WIDE_INT_PRINT_DEC
7890 " bytes which is more than half the stack size. "
7891 "The dynamic check would not be reliable. "
7892 "No check emitted for this function.",
7893 current_function_name(),
7894 cfun_frame_layout.frame_size);
7895 }
7896 else
7897 {
7898 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7899 & ~(stack_guard - 1));
7900
7901 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7902 GEN_INT (stack_check_mask));
7903 if (TARGET_64BIT)
7904 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
7905 t, const0_rtx),
7906 t, const0_rtx, const0_rtx));
7907 else
7908 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
7909 t, const0_rtx),
7910 t, const0_rtx, const0_rtx));
7911 }
7912 }
7913 }
7914
7915 if (s390_warn_framesize > 0
7916 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7917 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7918 current_function_name (), cfun_frame_layout.frame_size);
7919
7920 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7921 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7922
7923 /* Save incoming stack pointer into temp reg. */
7924 if (TARGET_BACKCHAIN || next_fpr)
7925 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7926
7927 /* Subtract frame size from stack pointer. */
7928
7929 if (DISP_IN_RANGE (INTVAL (frame_off)))
7930 {
7931 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7932 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7933 frame_off));
7934 insn = emit_insn (insn);
7935 }
7936 else
7937 {
7938 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7939 frame_off = force_const_mem (Pmode, frame_off);
7940
7941 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7942 annotate_constant_pool_refs (&PATTERN (insn));
7943 }
7944
7945 RTX_FRAME_RELATED_P (insn) = 1;
7946 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7947 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7948 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7949 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7950 real_frame_off)));
7951
7952 /* Set backchain. */
7953
7954 if (TARGET_BACKCHAIN)
7955 {
7956 if (cfun_frame_layout.backchain_offset)
7957 addr = gen_rtx_MEM (Pmode,
7958 plus_constant (stack_pointer_rtx,
7959 cfun_frame_layout.backchain_offset));
7960 else
7961 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7962 set_mem_alias_set (addr, get_frame_alias_set ());
7963 insn = emit_insn (gen_move_insn (addr, temp_reg));
7964 }
7965
7966 /* If we support non-call exceptions (e.g. for Java),
7967 we need to make sure the backchain pointer is set up
7968 before any possibly trapping memory access. */
7969 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
7970 {
7971 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7972 emit_clobber (addr);
7973 }
7974 }
7975
7976 /* Save fprs 8 - 15 (64 bit ABI). */
7977
7978 if (cfun_save_high_fprs_p && next_fpr)
7979 {
7980 /* If the stack might be accessed through a different register
7981 we have to make sure that the stack pointer decrement is not
7982 moved below the use of the stack slots. */
7983 s390_emit_stack_tie ();
7984
7985 insn = emit_insn (gen_add2_insn (temp_reg,
7986 GEN_INT (cfun_frame_layout.f8_offset)));
7987
7988 offset = 0;
7989
7990 for (i = 24; i <= next_fpr; i++)
7991 if (cfun_fpr_bit_p (i - 16))
7992 {
7993 rtx addr = plus_constant (stack_pointer_rtx,
7994 cfun_frame_layout.frame_size
7995 + cfun_frame_layout.f8_offset
7996 + offset);
7997
7998 insn = save_fpr (temp_reg, offset, i);
7999 offset += 8;
8000 RTX_FRAME_RELATED_P (insn) = 1;
8001 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8002 gen_rtx_SET (VOIDmode,
8003 gen_rtx_MEM (DFmode, addr),
8004 gen_rtx_REG (DFmode, i)));
8005 }
8006 }
8007
8008 /* Set frame pointer, if needed. */
8009
8010 if (frame_pointer_needed)
8011 {
8012 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8013 RTX_FRAME_RELATED_P (insn) = 1;
8014 }
8015
8016 /* Set up got pointer, if needed. */
8017
8018 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8019 {
8020 rtx insns = s390_load_got ();
8021
8022 for (insn = insns; insn; insn = NEXT_INSN (insn))
8023 annotate_constant_pool_refs (&PATTERN (insn));
8024
8025 emit_insn (insns);
8026 }
8027
8028 if (TARGET_TPF_PROFILING)
8029 {
8030 /* Generate a BAS instruction to serve as a function
8031 entry intercept to facilitate the use of tracing
8032 algorithms located at the branch target. */
8033 emit_insn (gen_prologue_tpf ());
8034
8035 /* Emit a blockage here so that all code
8036 lies between the profiling mechanisms. */
8037 emit_insn (gen_blockage ());
8038 }
8039 }
8040
8041 /* Expand the epilogue into a bunch of separate insns. */
8042
8043 void
8044 s390_emit_epilogue (bool sibcall)
8045 {
8046 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8047 int area_bottom, area_top, offset = 0;
8048 int next_offset;
8049 rtvec p;
8050 int i;
8051
8052 if (TARGET_TPF_PROFILING)
8053 {
8054
8055 /* Generate a BAS instruction to serve as a function
8056 entry intercept to facilitate the use of tracing
8057 algorithms located at the branch target. */
8058
8059 /* Emit a blockage here so that all code
8060 lies between the profiling mechanisms. */
8061 emit_insn (gen_blockage ());
8062
8063 emit_insn (gen_epilogue_tpf ());
8064 }
8065
8066 /* Check whether to use frame or stack pointer for restore. */
8067
8068 frame_pointer = (frame_pointer_needed
8069 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8070
8071 s390_frame_area (&area_bottom, &area_top);
8072
8073 /* Check whether we can access the register save area.
8074 If not, increment the frame pointer as required. */
8075
8076 if (area_top <= area_bottom)
8077 {
8078 /* Nothing to restore. */
8079 }
8080 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8081 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8082 {
8083 /* Area is in range. */
8084 offset = cfun_frame_layout.frame_size;
8085 }
8086 else
8087 {
8088 rtx insn, frame_off, cfa;
8089
8090 offset = area_bottom < 0 ? -area_bottom : 0;
8091 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8092
8093 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8094 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8095 if (DISP_IN_RANGE (INTVAL (frame_off)))
8096 {
8097 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8098 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8099 insn = emit_insn (insn);
8100 }
8101 else
8102 {
8103 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8104 frame_off = force_const_mem (Pmode, frame_off);
8105
8106 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8107 annotate_constant_pool_refs (&PATTERN (insn));
8108 }
8109 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8110 RTX_FRAME_RELATED_P (insn) = 1;
8111 }
8112
8113 /* Restore call saved fprs. */
8114
8115 if (TARGET_64BIT)
8116 {
8117 if (cfun_save_high_fprs_p)
8118 {
8119 next_offset = cfun_frame_layout.f8_offset;
8120 for (i = 24; i < 32; i++)
8121 {
8122 if (cfun_fpr_bit_p (i - 16))
8123 {
8124 restore_fpr (frame_pointer,
8125 offset + next_offset, i);
8126 cfa_restores
8127 = alloc_reg_note (REG_CFA_RESTORE,
8128 gen_rtx_REG (DFmode, i), cfa_restores);
8129 next_offset += 8;
8130 }
8131 }
8132 }
8133
8134 }
8135 else
8136 {
8137 next_offset = cfun_frame_layout.f4_offset;
8138 for (i = 18; i < 20; i++)
8139 {
8140 if (cfun_fpr_bit_p (i - 16))
8141 {
8142 restore_fpr (frame_pointer,
8143 offset + next_offset, i);
8144 cfa_restores
8145 = alloc_reg_note (REG_CFA_RESTORE,
8146 gen_rtx_REG (DFmode, i), cfa_restores);
8147 next_offset += 8;
8148 }
8149 else if (!TARGET_PACKED_STACK)
8150 next_offset += 8;
8151 }
8152
8153 }
8154
8155 /* Return register. */
8156
8157 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8158
8159 /* Restore call saved gprs. */
8160
8161 if (cfun_frame_layout.first_restore_gpr != -1)
8162 {
8163 rtx insn, addr;
8164 int i;
8165
8166 /* Check for global register and save them
8167 to stack location from where they get restored. */
8168
8169 for (i = cfun_frame_layout.first_restore_gpr;
8170 i <= cfun_frame_layout.last_restore_gpr;
8171 i++)
8172 {
8173 if (global_not_special_regno_p (i))
8174 {
8175 addr = plus_constant (frame_pointer,
8176 offset + cfun_frame_layout.gprs_offset
8177 + (i - cfun_frame_layout.first_save_gpr_slot)
8178 * UNITS_PER_LONG);
8179 addr = gen_rtx_MEM (Pmode, addr);
8180 set_mem_alias_set (addr, get_frame_alias_set ());
8181 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8182 }
8183 else
8184 cfa_restores
8185 = alloc_reg_note (REG_CFA_RESTORE,
8186 gen_rtx_REG (Pmode, i), cfa_restores);
8187 }
8188
8189 if (! sibcall)
8190 {
8191 /* Fetch return address from stack before load multiple,
8192 this will do good for scheduling. */
8193
8194 if (cfun_frame_layout.save_return_addr_p
8195 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8196 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8197 {
8198 int return_regnum = find_unused_clobbered_reg();
8199 if (!return_regnum)
8200 return_regnum = 4;
8201 return_reg = gen_rtx_REG (Pmode, return_regnum);
8202
8203 addr = plus_constant (frame_pointer,
8204 offset + cfun_frame_layout.gprs_offset
8205 + (RETURN_REGNUM
8206 - cfun_frame_layout.first_save_gpr_slot)
8207 * UNITS_PER_LONG);
8208 addr = gen_rtx_MEM (Pmode, addr);
8209 set_mem_alias_set (addr, get_frame_alias_set ());
8210 emit_move_insn (return_reg, addr);
8211 }
8212 }
8213
8214 insn = restore_gprs (frame_pointer,
8215 offset + cfun_frame_layout.gprs_offset
8216 + (cfun_frame_layout.first_restore_gpr
8217 - cfun_frame_layout.first_save_gpr_slot)
8218 * UNITS_PER_LONG,
8219 cfun_frame_layout.first_restore_gpr,
8220 cfun_frame_layout.last_restore_gpr);
8221 insn = emit_insn (insn);
8222 REG_NOTES (insn) = cfa_restores;
8223 add_reg_note (insn, REG_CFA_DEF_CFA,
8224 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8225 RTX_FRAME_RELATED_P (insn) = 1;
8226 }
8227
8228 if (! sibcall)
8229 {
8230
8231 /* Return to caller. */
8232
8233 p = rtvec_alloc (2);
8234
8235 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8236 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8237 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8238 }
8239 }
8240
8241
8242 /* Return the size in bytes of a function argument of
8243 type TYPE and/or mode MODE. At least one of TYPE or
8244 MODE must be specified. */
8245
8246 static int
8247 s390_function_arg_size (enum machine_mode mode, const_tree type)
8248 {
8249 if (type)
8250 return int_size_in_bytes (type);
8251
8252 /* No type info available for some library calls ... */
8253 if (mode != BLKmode)
8254 return GET_MODE_SIZE (mode);
8255
8256 /* If we have neither type nor mode, abort */
8257 gcc_unreachable ();
8258 }
8259
8260 /* Return true if a function argument of type TYPE and mode MODE
8261 is to be passed in a floating-point register, if available. */
8262
8263 static bool
8264 s390_function_arg_float (enum machine_mode mode, tree type)
8265 {
8266 int size = s390_function_arg_size (mode, type);
8267 if (size > 8)
8268 return false;
8269
8270 /* Soft-float changes the ABI: no floating-point registers are used. */
8271 if (TARGET_SOFT_FLOAT)
8272 return false;
8273
8274 /* No type info available for some library calls ... */
8275 if (!type)
8276 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8277
8278 /* The ABI says that record types with a single member are treated
8279 just like that member would be. */
8280 while (TREE_CODE (type) == RECORD_TYPE)
8281 {
8282 tree field, single = NULL_TREE;
8283
8284 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8285 {
8286 if (TREE_CODE (field) != FIELD_DECL)
8287 continue;
8288
8289 if (single == NULL_TREE)
8290 single = TREE_TYPE (field);
8291 else
8292 return false;
8293 }
8294
8295 if (single == NULL_TREE)
8296 return false;
8297 else
8298 type = single;
8299 }
8300
8301 return TREE_CODE (type) == REAL_TYPE;
8302 }
8303
8304 /* Return true if a function argument of type TYPE and mode MODE
8305 is to be passed in an integer register, or a pair of integer
8306 registers, if available. */
8307
8308 static bool
8309 s390_function_arg_integer (enum machine_mode mode, tree type)
8310 {
8311 int size = s390_function_arg_size (mode, type);
8312 if (size > 8)
8313 return false;
8314
8315 /* No type info available for some library calls ... */
8316 if (!type)
8317 return GET_MODE_CLASS (mode) == MODE_INT
8318 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8319
8320 /* We accept small integral (and similar) types. */
8321 if (INTEGRAL_TYPE_P (type)
8322 || POINTER_TYPE_P (type)
8323 || TREE_CODE (type) == OFFSET_TYPE
8324 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8325 return true;
8326
8327 /* We also accept structs of size 1, 2, 4, 8 that are not
8328 passed in floating-point registers. */
8329 if (AGGREGATE_TYPE_P (type)
8330 && exact_log2 (size) >= 0
8331 && !s390_function_arg_float (mode, type))
8332 return true;
8333
8334 return false;
8335 }
8336
8337 /* Return 1 if a function argument of type TYPE and mode MODE
8338 is to be passed by reference. The ABI specifies that only
8339 structures of size 1, 2, 4, or 8 bytes are passed by value,
8340 all other structures (and complex numbers) are passed by
8341 reference. */
8342
8343 static bool
8344 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8345 enum machine_mode mode, const_tree type,
8346 bool named ATTRIBUTE_UNUSED)
8347 {
8348 int size = s390_function_arg_size (mode, type);
8349 if (size > 8)
8350 return true;
8351
8352 if (type)
8353 {
8354 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8355 return 1;
8356
8357 if (TREE_CODE (type) == COMPLEX_TYPE
8358 || TREE_CODE (type) == VECTOR_TYPE)
8359 return 1;
8360 }
8361
8362 return 0;
8363 }
8364
8365 /* Update the data in CUM to advance over an argument of mode MODE and
8366 data type TYPE. (TYPE is null for libcalls where that information
8367 may not be available.). The boolean NAMED specifies whether the
8368 argument is a named argument (as opposed to an unnamed argument
8369 matching an ellipsis). */
8370
8371 void
8372 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8373 tree type, int named ATTRIBUTE_UNUSED)
8374 {
8375 if (s390_function_arg_float (mode, type))
8376 {
8377 cum->fprs += 1;
8378 }
8379 else if (s390_function_arg_integer (mode, type))
8380 {
8381 int size = s390_function_arg_size (mode, type);
8382 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8383 }
8384 else
8385 gcc_unreachable ();
8386 }
8387
8388 /* Define where to put the arguments to a function.
8389 Value is zero to push the argument on the stack,
8390 or a hard register in which to store the argument.
8391
8392 MODE is the argument's machine mode.
8393 TYPE is the data type of the argument (as a tree).
8394 This is null for libcalls where that information may
8395 not be available.
8396 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8397 the preceding args and about the function being called.
8398 NAMED is nonzero if this argument is a named parameter
8399 (otherwise it is an extra parameter matching an ellipsis).
8400
8401 On S/390, we use general purpose registers 2 through 6 to
8402 pass integer, pointer, and certain structure arguments, and
8403 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8404 to pass floating point arguments. All remaining arguments
8405 are pushed to the stack. */
8406
8407 rtx
8408 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8409 int named ATTRIBUTE_UNUSED)
8410 {
8411 if (s390_function_arg_float (mode, type))
8412 {
8413 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8414 return 0;
8415 else
8416 return gen_rtx_REG (mode, cum->fprs + 16);
8417 }
8418 else if (s390_function_arg_integer (mode, type))
8419 {
8420 int size = s390_function_arg_size (mode, type);
8421 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8422
8423 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8424 return 0;
8425 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8426 return gen_rtx_REG (mode, cum->gprs + 2);
8427 else if (n_gprs == 2)
8428 {
8429 rtvec p = rtvec_alloc (2);
8430
8431 RTVEC_ELT (p, 0)
8432 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8433 const0_rtx);
8434 RTVEC_ELT (p, 1)
8435 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8436 GEN_INT (4));
8437
8438 return gen_rtx_PARALLEL (mode, p);
8439 }
8440 }
8441
8442 /* After the real arguments, expand_call calls us once again
8443 with a void_type_node type. Whatever we return here is
8444 passed as operand 2 to the call expanders.
8445
8446 We don't need this feature ... */
8447 else if (type == void_type_node)
8448 return const0_rtx;
8449
8450 gcc_unreachable ();
8451 }
8452
8453 /* Return true if return values of type TYPE should be returned
8454 in a memory buffer whose address is passed by the caller as
8455 hidden first argument. */
8456
8457 static bool
8458 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8459 {
8460 /* We accept small integral (and similar) types. */
8461 if (INTEGRAL_TYPE_P (type)
8462 || POINTER_TYPE_P (type)
8463 || TREE_CODE (type) == OFFSET_TYPE
8464 || TREE_CODE (type) == REAL_TYPE)
8465 return int_size_in_bytes (type) > 8;
8466
8467 /* Aggregates and similar constructs are always returned
8468 in memory. */
8469 if (AGGREGATE_TYPE_P (type)
8470 || TREE_CODE (type) == COMPLEX_TYPE
8471 || TREE_CODE (type) == VECTOR_TYPE)
8472 return true;
8473
8474 /* ??? We get called on all sorts of random stuff from
8475 aggregate_value_p. We can't abort, but it's not clear
8476 what's safe to return. Pretend it's a struct I guess. */
8477 return true;
8478 }
8479
8480 /* Function arguments and return values are promoted to word size. */
8481
8482 static enum machine_mode
8483 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8484 int *punsignedp,
8485 const_tree fntype ATTRIBUTE_UNUSED,
8486 int for_return ATTRIBUTE_UNUSED)
8487 {
8488 if (INTEGRAL_MODE_P (mode)
8489 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8490 {
8491 if (POINTER_TYPE_P (type))
8492 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8493 return Pmode;
8494 }
8495
8496 return mode;
8497 }
8498
8499 /* Define where to return a (scalar) value of type TYPE.
8500 If TYPE is null, define where to return a (scalar)
8501 value of mode MODE from a libcall. */
8502
8503 rtx
8504 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8505 {
8506 if (type)
8507 {
8508 int unsignedp = TYPE_UNSIGNED (type);
8509 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8510 }
8511
8512 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8513 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8514
8515 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8516 return gen_rtx_REG (mode, 16);
8517 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8518 || UNITS_PER_LONG == UNITS_PER_WORD)
8519 return gen_rtx_REG (mode, 2);
8520 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8521 {
8522 rtvec p = rtvec_alloc (2);
8523
8524 RTVEC_ELT (p, 0)
8525 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8526 RTVEC_ELT (p, 1)
8527 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8528
8529 return gen_rtx_PARALLEL (mode, p);
8530 }
8531
8532 gcc_unreachable ();
8533 }
8534
8535
8536 /* Create and return the va_list datatype.
8537
8538 On S/390, va_list is an array type equivalent to
8539
8540 typedef struct __va_list_tag
8541 {
8542 long __gpr;
8543 long __fpr;
8544 void *__overflow_arg_area;
8545 void *__reg_save_area;
8546 } va_list[1];
8547
8548 where __gpr and __fpr hold the number of general purpose
8549 or floating point arguments used up to now, respectively,
8550 __overflow_arg_area points to the stack location of the
8551 next argument passed on the stack, and __reg_save_area
8552 always points to the start of the register area in the
8553 call frame of the current function. The function prologue
8554 saves all registers used for argument passing into this
8555 area if the function uses variable arguments. */
8556
8557 static tree
8558 s390_build_builtin_va_list (void)
8559 {
8560 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8561
8562 record = lang_hooks.types.make_type (RECORD_TYPE);
8563
8564 type_decl =
8565 build_decl (BUILTINS_LOCATION,
8566 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8567
8568 f_gpr = build_decl (BUILTINS_LOCATION,
8569 FIELD_DECL, get_identifier ("__gpr"),
8570 long_integer_type_node);
8571 f_fpr = build_decl (BUILTINS_LOCATION,
8572 FIELD_DECL, get_identifier ("__fpr"),
8573 long_integer_type_node);
8574 f_ovf = build_decl (BUILTINS_LOCATION,
8575 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8576 ptr_type_node);
8577 f_sav = build_decl (BUILTINS_LOCATION,
8578 FIELD_DECL, get_identifier ("__reg_save_area"),
8579 ptr_type_node);
8580
8581 va_list_gpr_counter_field = f_gpr;
8582 va_list_fpr_counter_field = f_fpr;
8583
8584 DECL_FIELD_CONTEXT (f_gpr) = record;
8585 DECL_FIELD_CONTEXT (f_fpr) = record;
8586 DECL_FIELD_CONTEXT (f_ovf) = record;
8587 DECL_FIELD_CONTEXT (f_sav) = record;
8588
8589 TREE_CHAIN (record) = type_decl;
8590 TYPE_NAME (record) = type_decl;
8591 TYPE_FIELDS (record) = f_gpr;
8592 TREE_CHAIN (f_gpr) = f_fpr;
8593 TREE_CHAIN (f_fpr) = f_ovf;
8594 TREE_CHAIN (f_ovf) = f_sav;
8595
8596 layout_type (record);
8597
8598 /* The correct type is an array type of one element. */
8599 return build_array_type (record, build_index_type (size_zero_node));
8600 }
8601
8602 /* Implement va_start by filling the va_list structure VALIST.
8603 STDARG_P is always true, and ignored.
8604 NEXTARG points to the first anonymous stack argument.
8605
8606 The following global variables are used to initialize
8607 the va_list structure:
8608
8609 crtl->args.info:
8610 holds number of gprs and fprs used for named arguments.
8611 crtl->args.arg_offset_rtx:
8612 holds the offset of the first anonymous stack argument
8613 (relative to the virtual arg pointer). */
8614
8615 static void
8616 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8617 {
8618 HOST_WIDE_INT n_gpr, n_fpr;
8619 int off;
8620 tree f_gpr, f_fpr, f_ovf, f_sav;
8621 tree gpr, fpr, ovf, sav, t;
8622
8623 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8624 f_fpr = TREE_CHAIN (f_gpr);
8625 f_ovf = TREE_CHAIN (f_fpr);
8626 f_sav = TREE_CHAIN (f_ovf);
8627
8628 valist = build_va_arg_indirect_ref (valist);
8629 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8630 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8631 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8632 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8633
8634 /* Count number of gp and fp argument registers used. */
8635
8636 n_gpr = crtl->args.info.gprs;
8637 n_fpr = crtl->args.info.fprs;
8638
8639 if (cfun->va_list_gpr_size)
8640 {
8641 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8642 build_int_cst (NULL_TREE, n_gpr));
8643 TREE_SIDE_EFFECTS (t) = 1;
8644 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8645 }
8646
8647 if (cfun->va_list_fpr_size)
8648 {
8649 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8650 build_int_cst (NULL_TREE, n_fpr));
8651 TREE_SIDE_EFFECTS (t) = 1;
8652 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8653 }
8654
8655 /* Find the overflow area. */
8656 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8657 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8658 {
8659 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8660
8661 off = INTVAL (crtl->args.arg_offset_rtx);
8662 off = off < 0 ? 0 : off;
8663 if (TARGET_DEBUG_ARG)
8664 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8665 (int)n_gpr, (int)n_fpr, off);
8666
8667 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8668
8669 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8670 TREE_SIDE_EFFECTS (t) = 1;
8671 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8672 }
8673
8674 /* Find the register save area. */
8675 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8676 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8677 {
8678 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8679 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8680 size_int (-RETURN_REGNUM * UNITS_PER_LONG));
8681
8682 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8683 TREE_SIDE_EFFECTS (t) = 1;
8684 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8685 }
8686 }
8687
8688 /* Implement va_arg by updating the va_list structure
8689 VALIST as required to retrieve an argument of type
8690 TYPE, and returning that argument.
8691
8692 Generates code equivalent to:
8693
8694 if (integral value) {
8695 if (size <= 4 && args.gpr < 5 ||
8696 size > 4 && args.gpr < 4 )
8697 ret = args.reg_save_area[args.gpr+8]
8698 else
8699 ret = *args.overflow_arg_area++;
8700 } else if (float value) {
8701 if (args.fgpr < 2)
8702 ret = args.reg_save_area[args.fpr+64]
8703 else
8704 ret = *args.overflow_arg_area++;
8705 } else if (aggregate value) {
8706 if (args.gpr < 5)
8707 ret = *args.reg_save_area[args.gpr]
8708 else
8709 ret = **args.overflow_arg_area++;
8710 } */
8711
8712 static tree
8713 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8714 gimple_seq *post_p ATTRIBUTE_UNUSED)
8715 {
8716 tree f_gpr, f_fpr, f_ovf, f_sav;
8717 tree gpr, fpr, ovf, sav, reg, t, u;
8718 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8719 tree lab_false, lab_over, addr;
8720
8721 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8722 f_fpr = TREE_CHAIN (f_gpr);
8723 f_ovf = TREE_CHAIN (f_fpr);
8724 f_sav = TREE_CHAIN (f_ovf);
8725
8726 valist = build_va_arg_indirect_ref (valist);
8727 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8728 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8729 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8730
8731 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8732 both appear on a lhs. */
8733 valist = unshare_expr (valist);
8734 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8735
8736 size = int_size_in_bytes (type);
8737
8738 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8739 {
8740 if (TARGET_DEBUG_ARG)
8741 {
8742 fprintf (stderr, "va_arg: aggregate type");
8743 debug_tree (type);
8744 }
8745
8746 /* Aggregates are passed by reference. */
8747 indirect_p = 1;
8748 reg = gpr;
8749 n_reg = 1;
8750
8751 /* kernel stack layout on 31 bit: It is assumed here that no padding
8752 will be added by s390_frame_info because for va_args always an even
8753 number of gprs has to be saved r15-r2 = 14 regs. */
8754 sav_ofs = 2 * UNITS_PER_LONG;
8755 sav_scale = UNITS_PER_LONG;
8756 size = UNITS_PER_LONG;
8757 max_reg = GP_ARG_NUM_REG - n_reg;
8758 }
8759 else if (s390_function_arg_float (TYPE_MODE (type), type))
8760 {
8761 if (TARGET_DEBUG_ARG)
8762 {
8763 fprintf (stderr, "va_arg: float type");
8764 debug_tree (type);
8765 }
8766
8767 /* FP args go in FP registers, if present. */
8768 indirect_p = 0;
8769 reg = fpr;
8770 n_reg = 1;
8771 sav_ofs = 16 * UNITS_PER_LONG;
8772 sav_scale = 8;
8773 max_reg = FP_ARG_NUM_REG - n_reg;
8774 }
8775 else
8776 {
8777 if (TARGET_DEBUG_ARG)
8778 {
8779 fprintf (stderr, "va_arg: other type");
8780 debug_tree (type);
8781 }
8782
8783 /* Otherwise into GP registers. */
8784 indirect_p = 0;
8785 reg = gpr;
8786 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8787
8788 /* kernel stack layout on 31 bit: It is assumed here that no padding
8789 will be added by s390_frame_info because for va_args always an even
8790 number of gprs has to be saved r15-r2 = 14 regs. */
8791 sav_ofs = 2 * UNITS_PER_LONG;
8792
8793 if (size < UNITS_PER_LONG)
8794 sav_ofs += UNITS_PER_LONG - size;
8795
8796 sav_scale = UNITS_PER_LONG;
8797 max_reg = GP_ARG_NUM_REG - n_reg;
8798 }
8799
8800 /* Pull the value out of the saved registers ... */
8801
8802 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8803 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8804 addr = create_tmp_var (ptr_type_node, "addr");
8805
8806 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8807 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8808 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8809 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8810 gimplify_and_add (t, pre_p);
8811
8812 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8813 size_int (sav_ofs));
8814 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8815 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8816 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8817
8818 gimplify_assign (addr, t, pre_p);
8819
8820 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8821
8822 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8823
8824
8825 /* ... Otherwise out of the overflow area. */
8826
8827 t = ovf;
8828 if (size < UNITS_PER_LONG)
8829 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8830 size_int (UNITS_PER_LONG - size));
8831
8832 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8833
8834 gimplify_assign (addr, t, pre_p);
8835
8836 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8837 size_int (size));
8838 gimplify_assign (ovf, t, pre_p);
8839
8840 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8841
8842
8843 /* Increment register save count. */
8844
8845 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8846 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8847 gimplify_and_add (u, pre_p);
8848
8849 if (indirect_p)
8850 {
8851 t = build_pointer_type_for_mode (build_pointer_type (type),
8852 ptr_mode, true);
8853 addr = fold_convert (t, addr);
8854 addr = build_va_arg_indirect_ref (addr);
8855 }
8856 else
8857 {
8858 t = build_pointer_type_for_mode (type, ptr_mode, true);
8859 addr = fold_convert (t, addr);
8860 }
8861
8862 return build_va_arg_indirect_ref (addr);
8863 }
8864
8865
8866 /* Builtins. */
8867
8868 enum s390_builtin
8869 {
8870 S390_BUILTIN_THREAD_POINTER,
8871 S390_BUILTIN_SET_THREAD_POINTER,
8872
8873 S390_BUILTIN_max
8874 };
8875
8876 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8877 CODE_FOR_get_tp_64,
8878 CODE_FOR_set_tp_64
8879 };
8880
8881 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8882 CODE_FOR_get_tp_31,
8883 CODE_FOR_set_tp_31
8884 };
8885
8886 static void
8887 s390_init_builtins (void)
8888 {
8889 tree ftype;
8890
8891 ftype = build_function_type (ptr_type_node, void_list_node);
8892 add_builtin_function ("__builtin_thread_pointer", ftype,
8893 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8894 NULL, NULL_TREE);
8895
8896 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8897 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8898 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8899 NULL, NULL_TREE);
8900 }
8901
8902 /* Expand an expression EXP that calls a built-in function,
8903 with result going to TARGET if that's convenient
8904 (and in mode MODE if that's convenient).
8905 SUBTARGET may be used as the target for computing one of EXP's operands.
8906 IGNORE is nonzero if the value is to be ignored. */
8907
8908 static rtx
8909 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8910 enum machine_mode mode ATTRIBUTE_UNUSED,
8911 int ignore ATTRIBUTE_UNUSED)
8912 {
8913 #define MAX_ARGS 2
8914
8915 enum insn_code const *code_for_builtin =
8916 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8917
8918 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8919 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8920 enum insn_code icode;
8921 rtx op[MAX_ARGS], pat;
8922 int arity;
8923 bool nonvoid;
8924 tree arg;
8925 call_expr_arg_iterator iter;
8926
8927 if (fcode >= S390_BUILTIN_max)
8928 internal_error ("bad builtin fcode");
8929 icode = code_for_builtin[fcode];
8930 if (icode == 0)
8931 internal_error ("bad builtin fcode");
8932
8933 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8934
8935 arity = 0;
8936 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8937 {
8938 const struct insn_operand_data *insn_op;
8939
8940 if (arg == error_mark_node)
8941 return NULL_RTX;
8942 if (arity > MAX_ARGS)
8943 return NULL_RTX;
8944
8945 insn_op = &insn_data[icode].operand[arity + nonvoid];
8946
8947 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8948
8949 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8950 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8951 arity++;
8952 }
8953
8954 if (nonvoid)
8955 {
8956 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8957 if (!target
8958 || GET_MODE (target) != tmode
8959 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8960 target = gen_reg_rtx (tmode);
8961 }
8962
8963 switch (arity)
8964 {
8965 case 0:
8966 pat = GEN_FCN (icode) (target);
8967 break;
8968 case 1:
8969 if (nonvoid)
8970 pat = GEN_FCN (icode) (target, op[0]);
8971 else
8972 pat = GEN_FCN (icode) (op[0]);
8973 break;
8974 case 2:
8975 pat = GEN_FCN (icode) (target, op[0], op[1]);
8976 break;
8977 default:
8978 gcc_unreachable ();
8979 }
8980 if (!pat)
8981 return NULL_RTX;
8982 emit_insn (pat);
8983
8984 if (nonvoid)
8985 return target;
8986 else
8987 return const0_rtx;
8988 }
8989
8990
8991 /* Output assembly code for the trampoline template to
8992 stdio stream FILE.
8993
8994 On S/390, we use gpr 1 internally in the trampoline code;
8995 gpr 0 is used to hold the static chain. */
8996
8997 static void
8998 s390_asm_trampoline_template (FILE *file)
8999 {
9000 rtx op[2];
9001 op[0] = gen_rtx_REG (Pmode, 0);
9002 op[1] = gen_rtx_REG (Pmode, 1);
9003
9004 if (TARGET_64BIT)
9005 {
9006 output_asm_insn ("basr\t%1,0", op);
9007 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
9008 output_asm_insn ("br\t%1", op);
9009 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9010 }
9011 else
9012 {
9013 output_asm_insn ("basr\t%1,0", op);
9014 output_asm_insn ("lm\t%0,%1,6(%1)", op);
9015 output_asm_insn ("br\t%1", op);
9016 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9017 }
9018 }
9019
9020 /* Emit RTL insns to initialize the variable parts of a trampoline.
9021 FNADDR is an RTX for the address of the function's pure code.
9022 CXT is an RTX for the static chain value for the function. */
9023
9024 static void
9025 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9026 {
9027 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9028 rtx mem;
9029
9030 emit_block_move (m_tramp, assemble_trampoline_template (),
9031 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
9032
9033 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
9034 emit_move_insn (mem, cxt);
9035 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
9036 emit_move_insn (mem, fnaddr);
9037 }
9038
9039 /* Output assembler code to FILE to increment profiler label # LABELNO
9040 for profiling a function entry. */
9041
9042 void
9043 s390_function_profiler (FILE *file, int labelno)
9044 {
9045 rtx op[7];
9046
9047 char label[128];
9048 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9049
9050 fprintf (file, "# function profiler \n");
9051
9052 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9053 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9054 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9055
9056 op[2] = gen_rtx_REG (Pmode, 1);
9057 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9058 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9059
9060 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9061 if (flag_pic)
9062 {
9063 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9064 op[4] = gen_rtx_CONST (Pmode, op[4]);
9065 }
9066
9067 if (TARGET_64BIT)
9068 {
9069 output_asm_insn ("stg\t%0,%1", op);
9070 output_asm_insn ("larl\t%2,%3", op);
9071 output_asm_insn ("brasl\t%0,%4", op);
9072 output_asm_insn ("lg\t%0,%1", op);
9073 }
9074 else if (!flag_pic)
9075 {
9076 op[6] = gen_label_rtx ();
9077
9078 output_asm_insn ("st\t%0,%1", op);
9079 output_asm_insn ("bras\t%2,%l6", op);
9080 output_asm_insn (".long\t%4", op);
9081 output_asm_insn (".long\t%3", op);
9082 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9083 output_asm_insn ("l\t%0,0(%2)", op);
9084 output_asm_insn ("l\t%2,4(%2)", op);
9085 output_asm_insn ("basr\t%0,%0", op);
9086 output_asm_insn ("l\t%0,%1", op);
9087 }
9088 else
9089 {
9090 op[5] = gen_label_rtx ();
9091 op[6] = gen_label_rtx ();
9092
9093 output_asm_insn ("st\t%0,%1", op);
9094 output_asm_insn ("bras\t%2,%l6", op);
9095 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9096 output_asm_insn (".long\t%4-%l5", op);
9097 output_asm_insn (".long\t%3-%l5", op);
9098 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9099 output_asm_insn ("lr\t%0,%2", op);
9100 output_asm_insn ("a\t%0,0(%2)", op);
9101 output_asm_insn ("a\t%2,4(%2)", op);
9102 output_asm_insn ("basr\t%0,%0", op);
9103 output_asm_insn ("l\t%0,%1", op);
9104 }
9105 }
9106
9107 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9108 into its SYMBOL_REF_FLAGS. */
9109
9110 static void
9111 s390_encode_section_info (tree decl, rtx rtl, int first)
9112 {
9113 default_encode_section_info (decl, rtl, first);
9114
9115 if (TREE_CODE (decl) == VAR_DECL)
9116 {
9117 /* If a variable has a forced alignment to < 2 bytes, mark it
9118 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9119 operand. */
9120 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9121 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9122 if (!DECL_SIZE (decl)
9123 || !DECL_ALIGN (decl)
9124 || !host_integerp (DECL_SIZE (decl), 0)
9125 || (DECL_ALIGN (decl) <= 64
9126 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9127 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9128 }
9129
9130 /* Literal pool references don't have a decl so they are handled
9131 differently here. We rely on the information in the MEM_ALIGN
9132 entry to decide upon natural alignment. */
9133 if (MEM_P (rtl)
9134 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9135 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9136 && (MEM_ALIGN (rtl) == 0
9137 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9138 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9139 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9140 }
9141
9142 /* Output thunk to FILE that implements a C++ virtual function call (with
9143 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9144 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9145 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9146 relative to the resulting this pointer. */
9147
9148 static void
9149 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9150 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9151 tree function)
9152 {
9153 rtx op[10];
9154 int nonlocal = 0;
9155
9156 /* Make sure unwind info is emitted for the thunk if needed. */
9157 final_start_function (emit_barrier (), file, 1);
9158
9159 /* Operand 0 is the target function. */
9160 op[0] = XEXP (DECL_RTL (function), 0);
9161 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9162 {
9163 nonlocal = 1;
9164 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9165 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9166 op[0] = gen_rtx_CONST (Pmode, op[0]);
9167 }
9168
9169 /* Operand 1 is the 'this' pointer. */
9170 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9171 op[1] = gen_rtx_REG (Pmode, 3);
9172 else
9173 op[1] = gen_rtx_REG (Pmode, 2);
9174
9175 /* Operand 2 is the delta. */
9176 op[2] = GEN_INT (delta);
9177
9178 /* Operand 3 is the vcall_offset. */
9179 op[3] = GEN_INT (vcall_offset);
9180
9181 /* Operand 4 is the temporary register. */
9182 op[4] = gen_rtx_REG (Pmode, 1);
9183
9184 /* Operands 5 to 8 can be used as labels. */
9185 op[5] = NULL_RTX;
9186 op[6] = NULL_RTX;
9187 op[7] = NULL_RTX;
9188 op[8] = NULL_RTX;
9189
9190 /* Operand 9 can be used for temporary register. */
9191 op[9] = NULL_RTX;
9192
9193 /* Generate code. */
9194 if (TARGET_64BIT)
9195 {
9196 /* Setup literal pool pointer if required. */
9197 if ((!DISP_IN_RANGE (delta)
9198 && !CONST_OK_FOR_K (delta)
9199 && !CONST_OK_FOR_Os (delta))
9200 || (!DISP_IN_RANGE (vcall_offset)
9201 && !CONST_OK_FOR_K (vcall_offset)
9202 && !CONST_OK_FOR_Os (vcall_offset)))
9203 {
9204 op[5] = gen_label_rtx ();
9205 output_asm_insn ("larl\t%4,%5", op);
9206 }
9207
9208 /* Add DELTA to this pointer. */
9209 if (delta)
9210 {
9211 if (CONST_OK_FOR_J (delta))
9212 output_asm_insn ("la\t%1,%2(%1)", op);
9213 else if (DISP_IN_RANGE (delta))
9214 output_asm_insn ("lay\t%1,%2(%1)", op);
9215 else if (CONST_OK_FOR_K (delta))
9216 output_asm_insn ("aghi\t%1,%2", op);
9217 else if (CONST_OK_FOR_Os (delta))
9218 output_asm_insn ("agfi\t%1,%2", op);
9219 else
9220 {
9221 op[6] = gen_label_rtx ();
9222 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9223 }
9224 }
9225
9226 /* Perform vcall adjustment. */
9227 if (vcall_offset)
9228 {
9229 if (DISP_IN_RANGE (vcall_offset))
9230 {
9231 output_asm_insn ("lg\t%4,0(%1)", op);
9232 output_asm_insn ("ag\t%1,%3(%4)", op);
9233 }
9234 else if (CONST_OK_FOR_K (vcall_offset))
9235 {
9236 output_asm_insn ("lghi\t%4,%3", op);
9237 output_asm_insn ("ag\t%4,0(%1)", op);
9238 output_asm_insn ("ag\t%1,0(%4)", op);
9239 }
9240 else if (CONST_OK_FOR_Os (vcall_offset))
9241 {
9242 output_asm_insn ("lgfi\t%4,%3", op);
9243 output_asm_insn ("ag\t%4,0(%1)", op);
9244 output_asm_insn ("ag\t%1,0(%4)", op);
9245 }
9246 else
9247 {
9248 op[7] = gen_label_rtx ();
9249 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9250 output_asm_insn ("ag\t%4,0(%1)", op);
9251 output_asm_insn ("ag\t%1,0(%4)", op);
9252 }
9253 }
9254
9255 /* Jump to target. */
9256 output_asm_insn ("jg\t%0", op);
9257
9258 /* Output literal pool if required. */
9259 if (op[5])
9260 {
9261 output_asm_insn (".align\t4", op);
9262 targetm.asm_out.internal_label (file, "L",
9263 CODE_LABEL_NUMBER (op[5]));
9264 }
9265 if (op[6])
9266 {
9267 targetm.asm_out.internal_label (file, "L",
9268 CODE_LABEL_NUMBER (op[6]));
9269 output_asm_insn (".long\t%2", op);
9270 }
9271 if (op[7])
9272 {
9273 targetm.asm_out.internal_label (file, "L",
9274 CODE_LABEL_NUMBER (op[7]));
9275 output_asm_insn (".long\t%3", op);
9276 }
9277 }
9278 else
9279 {
9280 /* Setup base pointer if required. */
9281 if (!vcall_offset
9282 || (!DISP_IN_RANGE (delta)
9283 && !CONST_OK_FOR_K (delta)
9284 && !CONST_OK_FOR_Os (delta))
9285 || (!DISP_IN_RANGE (delta)
9286 && !CONST_OK_FOR_K (vcall_offset)
9287 && !CONST_OK_FOR_Os (vcall_offset)))
9288 {
9289 op[5] = gen_label_rtx ();
9290 output_asm_insn ("basr\t%4,0", op);
9291 targetm.asm_out.internal_label (file, "L",
9292 CODE_LABEL_NUMBER (op[5]));
9293 }
9294
9295 /* Add DELTA to this pointer. */
9296 if (delta)
9297 {
9298 if (CONST_OK_FOR_J (delta))
9299 output_asm_insn ("la\t%1,%2(%1)", op);
9300 else if (DISP_IN_RANGE (delta))
9301 output_asm_insn ("lay\t%1,%2(%1)", op);
9302 else if (CONST_OK_FOR_K (delta))
9303 output_asm_insn ("ahi\t%1,%2", op);
9304 else if (CONST_OK_FOR_Os (delta))
9305 output_asm_insn ("afi\t%1,%2", op);
9306 else
9307 {
9308 op[6] = gen_label_rtx ();
9309 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9310 }
9311 }
9312
9313 /* Perform vcall adjustment. */
9314 if (vcall_offset)
9315 {
9316 if (CONST_OK_FOR_J (vcall_offset))
9317 {
9318 output_asm_insn ("l\t%4,0(%1)", op);
9319 output_asm_insn ("a\t%1,%3(%4)", op);
9320 }
9321 else if (DISP_IN_RANGE (vcall_offset))
9322 {
9323 output_asm_insn ("l\t%4,0(%1)", op);
9324 output_asm_insn ("ay\t%1,%3(%4)", op);
9325 }
9326 else if (CONST_OK_FOR_K (vcall_offset))
9327 {
9328 output_asm_insn ("lhi\t%4,%3", op);
9329 output_asm_insn ("a\t%4,0(%1)", op);
9330 output_asm_insn ("a\t%1,0(%4)", op);
9331 }
9332 else if (CONST_OK_FOR_Os (vcall_offset))
9333 {
9334 output_asm_insn ("iilf\t%4,%3", op);
9335 output_asm_insn ("a\t%4,0(%1)", op);
9336 output_asm_insn ("a\t%1,0(%4)", op);
9337 }
9338 else
9339 {
9340 op[7] = gen_label_rtx ();
9341 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9342 output_asm_insn ("a\t%4,0(%1)", op);
9343 output_asm_insn ("a\t%1,0(%4)", op);
9344 }
9345
9346 /* We had to clobber the base pointer register.
9347 Re-setup the base pointer (with a different base). */
9348 op[5] = gen_label_rtx ();
9349 output_asm_insn ("basr\t%4,0", op);
9350 targetm.asm_out.internal_label (file, "L",
9351 CODE_LABEL_NUMBER (op[5]));
9352 }
9353
9354 /* Jump to target. */
9355 op[8] = gen_label_rtx ();
9356
9357 if (!flag_pic)
9358 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9359 else if (!nonlocal)
9360 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9361 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9362 else if (flag_pic == 1)
9363 {
9364 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9365 output_asm_insn ("l\t%4,%0(%4)", op);
9366 }
9367 else if (flag_pic == 2)
9368 {
9369 op[9] = gen_rtx_REG (Pmode, 0);
9370 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9371 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9372 output_asm_insn ("ar\t%4,%9", op);
9373 output_asm_insn ("l\t%4,0(%4)", op);
9374 }
9375
9376 output_asm_insn ("br\t%4", op);
9377
9378 /* Output literal pool. */
9379 output_asm_insn (".align\t4", op);
9380
9381 if (nonlocal && flag_pic == 2)
9382 output_asm_insn (".long\t%0", op);
9383 if (nonlocal)
9384 {
9385 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9386 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9387 }
9388
9389 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9390 if (!flag_pic)
9391 output_asm_insn (".long\t%0", op);
9392 else
9393 output_asm_insn (".long\t%0-%5", op);
9394
9395 if (op[6])
9396 {
9397 targetm.asm_out.internal_label (file, "L",
9398 CODE_LABEL_NUMBER (op[6]));
9399 output_asm_insn (".long\t%2", op);
9400 }
9401 if (op[7])
9402 {
9403 targetm.asm_out.internal_label (file, "L",
9404 CODE_LABEL_NUMBER (op[7]));
9405 output_asm_insn (".long\t%3", op);
9406 }
9407 }
9408 final_end_function ();
9409 }
9410
9411 static bool
9412 s390_valid_pointer_mode (enum machine_mode mode)
9413 {
9414 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9415 }
9416
9417 /* Checks whether the given CALL_EXPR would use a caller
9418 saved register. This is used to decide whether sibling call
9419 optimization could be performed on the respective function
9420 call. */
9421
9422 static bool
9423 s390_call_saved_register_used (tree call_expr)
9424 {
9425 CUMULATIVE_ARGS cum;
9426 tree parameter;
9427 enum machine_mode mode;
9428 tree type;
9429 rtx parm_rtx;
9430 int reg, i;
9431
9432 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9433
9434 for (i = 0; i < call_expr_nargs (call_expr); i++)
9435 {
9436 parameter = CALL_EXPR_ARG (call_expr, i);
9437 gcc_assert (parameter);
9438
9439 /* For an undeclared variable passed as parameter we will get
9440 an ERROR_MARK node here. */
9441 if (TREE_CODE (parameter) == ERROR_MARK)
9442 return true;
9443
9444 type = TREE_TYPE (parameter);
9445 gcc_assert (type);
9446
9447 mode = TYPE_MODE (type);
9448 gcc_assert (mode);
9449
9450 if (pass_by_reference (&cum, mode, type, true))
9451 {
9452 mode = Pmode;
9453 type = build_pointer_type (type);
9454 }
9455
9456 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9457
9458 s390_function_arg_advance (&cum, mode, type, 0);
9459
9460 if (!parm_rtx)
9461 continue;
9462
9463 if (REG_P (parm_rtx))
9464 {
9465 for (reg = 0;
9466 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9467 reg++)
9468 if (!call_used_regs[reg + REGNO (parm_rtx)])
9469 return true;
9470 }
9471
9472 if (GET_CODE (parm_rtx) == PARALLEL)
9473 {
9474 int i;
9475
9476 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9477 {
9478 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9479
9480 gcc_assert (REG_P (r));
9481
9482 for (reg = 0;
9483 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9484 reg++)
9485 if (!call_used_regs[reg + REGNO (r)])
9486 return true;
9487 }
9488 }
9489
9490 }
9491 return false;
9492 }
9493
9494 /* Return true if the given call expression can be
9495 turned into a sibling call.
9496 DECL holds the declaration of the function to be called whereas
9497 EXP is the call expression itself. */
9498
9499 static bool
9500 s390_function_ok_for_sibcall (tree decl, tree exp)
9501 {
9502 /* The TPF epilogue uses register 1. */
9503 if (TARGET_TPF_PROFILING)
9504 return false;
9505
9506 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9507 which would have to be restored before the sibcall. */
9508 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9509 return false;
9510
9511 /* Register 6 on s390 is available as an argument register but unfortunately
9512 "caller saved". This makes functions needing this register for arguments
9513 not suitable for sibcalls. */
9514 return !s390_call_saved_register_used (exp);
9515 }
9516
9517 /* Return the fixed registers used for condition codes. */
9518
9519 static bool
9520 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9521 {
9522 *p1 = CC_REGNUM;
9523 *p2 = INVALID_REGNUM;
9524
9525 return true;
9526 }
9527
9528 /* This function is used by the call expanders of the machine description.
9529 It emits the call insn itself together with the necessary operations
9530 to adjust the target address and returns the emitted insn.
9531 ADDR_LOCATION is the target address rtx
9532 TLS_CALL the location of the thread-local symbol
9533 RESULT_REG the register where the result of the call should be stored
9534 RETADDR_REG the register where the return address should be stored
9535 If this parameter is NULL_RTX the call is considered
9536 to be a sibling call. */
9537
9538 rtx
9539 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9540 rtx retaddr_reg)
9541 {
9542 bool plt_call = false;
9543 rtx insn;
9544 rtx call;
9545 rtx clobber;
9546 rtvec vec;
9547
9548 /* Direct function calls need special treatment. */
9549 if (GET_CODE (addr_location) == SYMBOL_REF)
9550 {
9551 /* When calling a global routine in PIC mode, we must
9552 replace the symbol itself with the PLT stub. */
9553 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9554 {
9555 if (retaddr_reg != NULL_RTX)
9556 {
9557 addr_location = gen_rtx_UNSPEC (Pmode,
9558 gen_rtvec (1, addr_location),
9559 UNSPEC_PLT);
9560 addr_location = gen_rtx_CONST (Pmode, addr_location);
9561 plt_call = true;
9562 }
9563 else
9564 /* For -fpic code the PLT entries might use r12 which is
9565 call-saved. Therefore we cannot do a sibcall when
9566 calling directly using a symbol ref. When reaching
9567 this point we decided (in s390_function_ok_for_sibcall)
9568 to do a sibcall for a function pointer but one of the
9569 optimizers was able to get rid of the function pointer
9570 by propagating the symbol ref into the call. This
9571 optimization is illegal for S/390 so we turn the direct
9572 call into a indirect call again. */
9573 addr_location = force_reg (Pmode, addr_location);
9574 }
9575
9576 /* Unless we can use the bras(l) insn, force the
9577 routine address into a register. */
9578 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9579 {
9580 if (flag_pic)
9581 addr_location = legitimize_pic_address (addr_location, 0);
9582 else
9583 addr_location = force_reg (Pmode, addr_location);
9584 }
9585 }
9586
9587 /* If it is already an indirect call or the code above moved the
9588 SYMBOL_REF to somewhere else make sure the address can be found in
9589 register 1. */
9590 if (retaddr_reg == NULL_RTX
9591 && GET_CODE (addr_location) != SYMBOL_REF
9592 && !plt_call)
9593 {
9594 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9595 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9596 }
9597
9598 addr_location = gen_rtx_MEM (QImode, addr_location);
9599 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9600
9601 if (result_reg != NULL_RTX)
9602 call = gen_rtx_SET (VOIDmode, result_reg, call);
9603
9604 if (retaddr_reg != NULL_RTX)
9605 {
9606 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9607
9608 if (tls_call != NULL_RTX)
9609 vec = gen_rtvec (3, call, clobber,
9610 gen_rtx_USE (VOIDmode, tls_call));
9611 else
9612 vec = gen_rtvec (2, call, clobber);
9613
9614 call = gen_rtx_PARALLEL (VOIDmode, vec);
9615 }
9616
9617 insn = emit_call_insn (call);
9618
9619 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9620 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9621 {
9622 /* s390_function_ok_for_sibcall should
9623 have denied sibcalls in this case. */
9624 gcc_assert (retaddr_reg != NULL_RTX);
9625
9626 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9627 }
9628 return insn;
9629 }
9630
9631 /* Implement CONDITIONAL_REGISTER_USAGE. */
9632
9633 void
9634 s390_conditional_register_usage (void)
9635 {
9636 int i;
9637
9638 if (flag_pic)
9639 {
9640 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9641 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9642 }
9643 if (TARGET_CPU_ZARCH)
9644 {
9645 fixed_regs[BASE_REGNUM] = 0;
9646 call_used_regs[BASE_REGNUM] = 0;
9647 fixed_regs[RETURN_REGNUM] = 0;
9648 call_used_regs[RETURN_REGNUM] = 0;
9649 }
9650 if (TARGET_64BIT)
9651 {
9652 for (i = 24; i < 32; i++)
9653 call_used_regs[i] = call_really_used_regs[i] = 0;
9654 }
9655 else
9656 {
9657 for (i = 18; i < 20; i++)
9658 call_used_regs[i] = call_really_used_regs[i] = 0;
9659 }
9660
9661 if (TARGET_SOFT_FLOAT)
9662 {
9663 for (i = 16; i < 32; i++)
9664 call_used_regs[i] = fixed_regs[i] = 1;
9665 }
9666 }
9667
9668 /* Corresponding function to eh_return expander. */
9669
9670 static GTY(()) rtx s390_tpf_eh_return_symbol;
9671 void
9672 s390_emit_tpf_eh_return (rtx target)
9673 {
9674 rtx insn, reg;
9675
9676 if (!s390_tpf_eh_return_symbol)
9677 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9678
9679 reg = gen_rtx_REG (Pmode, 2);
9680
9681 emit_move_insn (reg, target);
9682 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9683 gen_rtx_REG (Pmode, RETURN_REGNUM));
9684 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9685
9686 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9687 }
9688
9689 /* Rework the prologue/epilogue to avoid saving/restoring
9690 registers unnecessarily. */
9691
9692 static void
9693 s390_optimize_prologue (void)
9694 {
9695 rtx insn, new_insn, next_insn;
9696
9697 /* Do a final recompute of the frame-related data. */
9698
9699 s390_update_frame_layout ();
9700
9701 /* If all special registers are in fact used, there's nothing we
9702 can do, so no point in walking the insn list. */
9703
9704 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9705 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9706 && (TARGET_CPU_ZARCH
9707 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9708 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9709 return;
9710
9711 /* Search for prologue/epilogue insns and replace them. */
9712
9713 for (insn = get_insns (); insn; insn = next_insn)
9714 {
9715 int first, last, off;
9716 rtx set, base, offset;
9717
9718 next_insn = NEXT_INSN (insn);
9719
9720 if (GET_CODE (insn) != INSN)
9721 continue;
9722
9723 if (GET_CODE (PATTERN (insn)) == PARALLEL
9724 && store_multiple_operation (PATTERN (insn), VOIDmode))
9725 {
9726 set = XVECEXP (PATTERN (insn), 0, 0);
9727 first = REGNO (SET_SRC (set));
9728 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9729 offset = const0_rtx;
9730 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9731 off = INTVAL (offset);
9732
9733 if (GET_CODE (base) != REG || off < 0)
9734 continue;
9735 if (cfun_frame_layout.first_save_gpr != -1
9736 && (cfun_frame_layout.first_save_gpr < first
9737 || cfun_frame_layout.last_save_gpr > last))
9738 continue;
9739 if (REGNO (base) != STACK_POINTER_REGNUM
9740 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9741 continue;
9742 if (first > BASE_REGNUM || last < BASE_REGNUM)
9743 continue;
9744
9745 if (cfun_frame_layout.first_save_gpr != -1)
9746 {
9747 new_insn = save_gprs (base,
9748 off + (cfun_frame_layout.first_save_gpr
9749 - first) * UNITS_PER_LONG,
9750 cfun_frame_layout.first_save_gpr,
9751 cfun_frame_layout.last_save_gpr);
9752 new_insn = emit_insn_before (new_insn, insn);
9753 INSN_ADDRESSES_NEW (new_insn, -1);
9754 }
9755
9756 remove_insn (insn);
9757 continue;
9758 }
9759
9760 if (cfun_frame_layout.first_save_gpr == -1
9761 && GET_CODE (PATTERN (insn)) == SET
9762 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9763 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9764 || (!TARGET_CPU_ZARCH
9765 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9766 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9767 {
9768 set = PATTERN (insn);
9769 first = REGNO (SET_SRC (set));
9770 offset = const0_rtx;
9771 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9772 off = INTVAL (offset);
9773
9774 if (GET_CODE (base) != REG || off < 0)
9775 continue;
9776 if (REGNO (base) != STACK_POINTER_REGNUM
9777 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9778 continue;
9779
9780 remove_insn (insn);
9781 continue;
9782 }
9783
9784 if (GET_CODE (PATTERN (insn)) == PARALLEL
9785 && load_multiple_operation (PATTERN (insn), VOIDmode))
9786 {
9787 set = XVECEXP (PATTERN (insn), 0, 0);
9788 first = REGNO (SET_DEST (set));
9789 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9790 offset = const0_rtx;
9791 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9792 off = INTVAL (offset);
9793
9794 if (GET_CODE (base) != REG || off < 0)
9795 continue;
9796 if (cfun_frame_layout.first_restore_gpr != -1
9797 && (cfun_frame_layout.first_restore_gpr < first
9798 || cfun_frame_layout.last_restore_gpr > last))
9799 continue;
9800 if (REGNO (base) != STACK_POINTER_REGNUM
9801 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9802 continue;
9803 if (first > BASE_REGNUM || last < BASE_REGNUM)
9804 continue;
9805
9806 if (cfun_frame_layout.first_restore_gpr != -1)
9807 {
9808 new_insn = restore_gprs (base,
9809 off + (cfun_frame_layout.first_restore_gpr
9810 - first) * UNITS_PER_LONG,
9811 cfun_frame_layout.first_restore_gpr,
9812 cfun_frame_layout.last_restore_gpr);
9813 new_insn = emit_insn_before (new_insn, insn);
9814 INSN_ADDRESSES_NEW (new_insn, -1);
9815 }
9816
9817 remove_insn (insn);
9818 continue;
9819 }
9820
9821 if (cfun_frame_layout.first_restore_gpr == -1
9822 && GET_CODE (PATTERN (insn)) == SET
9823 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9824 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9825 || (!TARGET_CPU_ZARCH
9826 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9827 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9828 {
9829 set = PATTERN (insn);
9830 first = REGNO (SET_DEST (set));
9831 offset = const0_rtx;
9832 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9833 off = INTVAL (offset);
9834
9835 if (GET_CODE (base) != REG || off < 0)
9836 continue;
9837 if (REGNO (base) != STACK_POINTER_REGNUM
9838 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9839 continue;
9840
9841 remove_insn (insn);
9842 continue;
9843 }
9844 }
9845 }
9846
9847 /* On z10 the dynamic branch prediction must see the backward jump in
9848 a window of 384 bytes. If not it falls back to the static
9849 prediction. This function rearranges the loop backward branch in a
9850 way which makes the static prediction always correct. The function
9851 returns true if it added an instruction. */
9852 static bool
9853 s390_z10_fix_long_loop_prediction (rtx insn)
9854 {
9855 rtx set = single_set (insn);
9856 rtx code_label, label_ref, new_label;
9857 rtx uncond_jump;
9858 rtx cur_insn;
9859 rtx tmp;
9860 int distance;
9861
9862 /* This will exclude branch on count and branch on index patterns
9863 since these are correctly statically predicted. */
9864 if (!set
9865 || SET_DEST (set) != pc_rtx
9866 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9867 return false;
9868
9869 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9870 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9871
9872 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9873
9874 code_label = XEXP (label_ref, 0);
9875
9876 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9877 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9878 || (INSN_ADDRESSES (INSN_UID (insn))
9879 - INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE))
9880 return false;
9881
9882 for (distance = 0, cur_insn = PREV_INSN (insn);
9883 distance < Z10_PREDICT_DISTANCE - 6;
9884 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9885 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
9886 return false;
9887
9888 new_label = gen_label_rtx ();
9889 uncond_jump = emit_jump_insn_after (
9890 gen_rtx_SET (VOIDmode, pc_rtx,
9891 gen_rtx_LABEL_REF (VOIDmode, code_label)),
9892 insn);
9893 emit_label_after (new_label, uncond_jump);
9894
9895 tmp = XEXP (SET_SRC (set), 1);
9896 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
9897 XEXP (SET_SRC (set), 2) = tmp;
9898 INSN_CODE (insn) = -1;
9899
9900 XEXP (label_ref, 0) = new_label;
9901 JUMP_LABEL (insn) = new_label;
9902 JUMP_LABEL (uncond_jump) = code_label;
9903
9904 return true;
9905 }
9906
9907 /* Returns 1 if INSN reads the value of REG for purposes not related
9908 to addressing of memory, and 0 otherwise. */
9909 static int
9910 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9911 {
9912 return reg_referenced_p (reg, PATTERN (insn))
9913 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9914 }
9915
9916 /* Starting from INSN find_cond_jump looks downwards in the insn
9917 stream for a single jump insn which is the last user of the
9918 condition code set in INSN. */
9919 static rtx
9920 find_cond_jump (rtx insn)
9921 {
9922 for (; insn; insn = NEXT_INSN (insn))
9923 {
9924 rtx ite, cc;
9925
9926 if (LABEL_P (insn))
9927 break;
9928
9929 if (!JUMP_P (insn))
9930 {
9931 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9932 break;
9933 continue;
9934 }
9935
9936 /* This will be triggered by a return. */
9937 if (GET_CODE (PATTERN (insn)) != SET)
9938 break;
9939
9940 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9941 ite = SET_SRC (PATTERN (insn));
9942
9943 if (GET_CODE (ite) != IF_THEN_ELSE)
9944 break;
9945
9946 cc = XEXP (XEXP (ite, 0), 0);
9947 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9948 break;
9949
9950 if (find_reg_note (insn, REG_DEAD, cc))
9951 return insn;
9952 break;
9953 }
9954
9955 return NULL_RTX;
9956 }
9957
9958 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9959 the semantics does not change. If NULL_RTX is passed as COND the
9960 function tries to find the conditional jump starting with INSN. */
9961 static void
9962 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9963 {
9964 rtx tmp = *op0;
9965
9966 if (cond == NULL_RTX)
9967 {
9968 rtx jump = find_cond_jump (NEXT_INSN (insn));
9969 jump = jump ? single_set (jump) : NULL_RTX;
9970
9971 if (jump == NULL_RTX)
9972 return;
9973
9974 cond = XEXP (XEXP (jump, 1), 0);
9975 }
9976
9977 *op0 = *op1;
9978 *op1 = tmp;
9979 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9980 }
9981
9982 /* On z10, instructions of the compare-and-branch family have the
9983 property to access the register occurring as second operand with
9984 its bits complemented. If such a compare is grouped with a second
9985 instruction that accesses the same register non-complemented, and
9986 if that register's value is delivered via a bypass, then the
9987 pipeline recycles, thereby causing significant performance decline.
9988 This function locates such situations and exchanges the two
9989 operands of the compare. The function return true whenever it
9990 added an insn. */
9991 static bool
9992 s390_z10_optimize_cmp (rtx insn)
9993 {
9994 rtx prev_insn, next_insn;
9995 bool insn_added_p = false;
9996 rtx cond, *op0, *op1;
9997
9998 if (GET_CODE (PATTERN (insn)) == PARALLEL)
9999 {
10000 /* Handle compare and branch and branch on count
10001 instructions. */
10002 rtx pattern = single_set (insn);
10003
10004 if (!pattern
10005 || SET_DEST (pattern) != pc_rtx
10006 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10007 return false;
10008
10009 cond = XEXP (SET_SRC (pattern), 0);
10010 op0 = &XEXP (cond, 0);
10011 op1 = &XEXP (cond, 1);
10012 }
10013 else if (GET_CODE (PATTERN (insn)) == SET)
10014 {
10015 rtx src, dest;
10016
10017 /* Handle normal compare instructions. */
10018 src = SET_SRC (PATTERN (insn));
10019 dest = SET_DEST (PATTERN (insn));
10020
10021 if (!REG_P (dest)
10022 || !CC_REGNO_P (REGNO (dest))
10023 || GET_CODE (src) != COMPARE)
10024 return false;
10025
10026 /* s390_swap_cmp will try to find the conditional
10027 jump when passing NULL_RTX as condition. */
10028 cond = NULL_RTX;
10029 op0 = &XEXP (src, 0);
10030 op1 = &XEXP (src, 1);
10031 }
10032 else
10033 return false;
10034
10035 if (!REG_P (*op0) || !REG_P (*op1))
10036 return false;
10037
10038 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10039 return false;
10040
10041 /* Swap the COMPARE arguments and its mask if there is a
10042 conflicting access in the previous insn. */
10043 prev_insn = prev_active_insn (insn);
10044 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10045 && reg_referenced_p (*op1, PATTERN (prev_insn)))
10046 s390_swap_cmp (cond, op0, op1, insn);
10047
10048 /* Check if there is a conflict with the next insn. If there
10049 was no conflict with the previous insn, then swap the
10050 COMPARE arguments and its mask. If we already swapped
10051 the operands, or if swapping them would cause a conflict
10052 with the previous insn, issue a NOP after the COMPARE in
10053 order to separate the two instuctions. */
10054 next_insn = next_active_insn (insn);
10055 if (next_insn != NULL_RTX && INSN_P (next_insn)
10056 && s390_non_addr_reg_read_p (*op1, next_insn))
10057 {
10058 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10059 && s390_non_addr_reg_read_p (*op0, prev_insn))
10060 {
10061 if (REGNO (*op1) == 0)
10062 emit_insn_after (gen_nop1 (), insn);
10063 else
10064 emit_insn_after (gen_nop (), insn);
10065 insn_added_p = true;
10066 }
10067 else
10068 s390_swap_cmp (cond, op0, op1, insn);
10069 }
10070 return insn_added_p;
10071 }
10072
10073 /* Perform machine-dependent processing. */
10074
10075 static void
10076 s390_reorg (void)
10077 {
10078 bool pool_overflow = false;
10079
10080 /* Make sure all splits have been performed; splits after
10081 machine_dependent_reorg might confuse insn length counts. */
10082 split_all_insns_noflow ();
10083
10084 /* Install the main literal pool and the associated base
10085 register load insns.
10086
10087 In addition, there are two problematic situations we need
10088 to correct:
10089
10090 - the literal pool might be > 4096 bytes in size, so that
10091 some of its elements cannot be directly accessed
10092
10093 - a branch target might be > 64K away from the branch, so that
10094 it is not possible to use a PC-relative instruction.
10095
10096 To fix those, we split the single literal pool into multiple
10097 pool chunks, reloading the pool base register at various
10098 points throughout the function to ensure it always points to
10099 the pool chunk the following code expects, and / or replace
10100 PC-relative branches by absolute branches.
10101
10102 However, the two problems are interdependent: splitting the
10103 literal pool can move a branch further away from its target,
10104 causing the 64K limit to overflow, and on the other hand,
10105 replacing a PC-relative branch by an absolute branch means
10106 we need to put the branch target address into the literal
10107 pool, possibly causing it to overflow.
10108
10109 So, we loop trying to fix up both problems until we manage
10110 to satisfy both conditions at the same time. Note that the
10111 loop is guaranteed to terminate as every pass of the loop
10112 strictly decreases the total number of PC-relative branches
10113 in the function. (This is not completely true as there
10114 might be branch-over-pool insns introduced by chunkify_start.
10115 Those never need to be split however.) */
10116
10117 for (;;)
10118 {
10119 struct constant_pool *pool = NULL;
10120
10121 /* Collect the literal pool. */
10122 if (!pool_overflow)
10123 {
10124 pool = s390_mainpool_start ();
10125 if (!pool)
10126 pool_overflow = true;
10127 }
10128
10129 /* If literal pool overflowed, start to chunkify it. */
10130 if (pool_overflow)
10131 pool = s390_chunkify_start ();
10132
10133 /* Split out-of-range branches. If this has created new
10134 literal pool entries, cancel current chunk list and
10135 recompute it. zSeries machines have large branch
10136 instructions, so we never need to split a branch. */
10137 if (!TARGET_CPU_ZARCH && s390_split_branches ())
10138 {
10139 if (pool_overflow)
10140 s390_chunkify_cancel (pool);
10141 else
10142 s390_mainpool_cancel (pool);
10143
10144 continue;
10145 }
10146
10147 /* If we made it up to here, both conditions are satisfied.
10148 Finish up literal pool related changes. */
10149 if (pool_overflow)
10150 s390_chunkify_finish (pool);
10151 else
10152 s390_mainpool_finish (pool);
10153
10154 /* We're done splitting branches. */
10155 cfun->machine->split_branches_pending_p = false;
10156 break;
10157 }
10158
10159 /* Generate out-of-pool execute target insns. */
10160 if (TARGET_CPU_ZARCH)
10161 {
10162 rtx insn, label, target;
10163
10164 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10165 {
10166 label = s390_execute_label (insn);
10167 if (!label)
10168 continue;
10169
10170 gcc_assert (label != const0_rtx);
10171
10172 target = emit_label (XEXP (label, 0));
10173 INSN_ADDRESSES_NEW (target, -1);
10174
10175 target = emit_insn (s390_execute_target (insn));
10176 INSN_ADDRESSES_NEW (target, -1);
10177 }
10178 }
10179
10180 /* Try to optimize prologue and epilogue further. */
10181 s390_optimize_prologue ();
10182
10183 /* Walk over the insns and do some z10 specific changes. */
10184 if (s390_tune == PROCESSOR_2097_Z10)
10185 {
10186 rtx insn;
10187 bool insn_added_p = false;
10188
10189 /* The insn lengths and addresses have to be up to date for the
10190 following manipulations. */
10191 shorten_branches (get_insns ());
10192
10193 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10194 {
10195 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10196 continue;
10197
10198 if (JUMP_P (insn))
10199 insn_added_p |= s390_z10_fix_long_loop_prediction (insn);
10200
10201 if (GET_CODE (PATTERN (insn)) == PARALLEL
10202 || GET_CODE (PATTERN (insn)) == SET)
10203 insn_added_p |= s390_z10_optimize_cmp (insn);
10204 }
10205
10206 /* Adjust branches if we added new instructions. */
10207 if (insn_added_p)
10208 shorten_branches (get_insns ());
10209 }
10210 }
10211
10212 /* Return true if INSN is a fp load insn writing register REGNO. */
10213 static inline bool
10214 s390_fpload_toreg (rtx insn, unsigned int regno)
10215 {
10216 rtx set;
10217 enum attr_type flag = s390_safe_attr_type (insn);
10218
10219 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10220 return false;
10221
10222 set = single_set (insn);
10223
10224 if (set == NULL_RTX)
10225 return false;
10226
10227 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10228 return false;
10229
10230 if (REGNO (SET_DEST (set)) != regno)
10231 return false;
10232
10233 return true;
10234 }
10235
10236 /* This value describes the distance to be avoided between an
10237 aritmetic fp instruction and an fp load writing the same register.
10238 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10239 fine but the exact value has to be avoided. Otherwise the FP
10240 pipeline will throw an exception causing a major penalty. */
10241 #define Z10_EARLYLOAD_DISTANCE 7
10242
10243 /* Rearrange the ready list in order to avoid the situation described
10244 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10245 moved to the very end of the ready list. */
10246 static void
10247 s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10248 {
10249 unsigned int regno;
10250 int nready = *nready_p;
10251 rtx tmp;
10252 int i;
10253 rtx insn;
10254 rtx set;
10255 enum attr_type flag;
10256 int distance;
10257
10258 /* Skip DISTANCE - 1 active insns. */
10259 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10260 distance > 0 && insn != NULL_RTX;
10261 distance--, insn = prev_active_insn (insn))
10262 if (CALL_P (insn) || JUMP_P (insn))
10263 return;
10264
10265 if (insn == NULL_RTX)
10266 return;
10267
10268 set = single_set (insn);
10269
10270 if (set == NULL_RTX || !REG_P (SET_DEST (set))
10271 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10272 return;
10273
10274 flag = s390_safe_attr_type (insn);
10275
10276 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10277 return;
10278
10279 regno = REGNO (SET_DEST (set));
10280 i = nready - 1;
10281
10282 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10283 i--;
10284
10285 if (!i)
10286 return;
10287
10288 tmp = ready[i];
10289 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10290 ready[0] = tmp;
10291 }
10292
10293 /* This function is called via hook TARGET_SCHED_REORDER before
10294 issueing one insn from list READY which contains *NREADYP entries.
10295 For target z10 it reorders load instructions to avoid early load
10296 conflicts in the floating point pipeline */
10297 static int
10298 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10299 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10300 {
10301 if (s390_tune == PROCESSOR_2097_Z10)
10302 if (reload_completed && *nreadyp > 1)
10303 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10304
10305 return s390_issue_rate ();
10306 }
10307
10308 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10309 the scheduler has issued INSN. It stores the last issued insn into
10310 last_scheduled_insn in order to make it available for
10311 s390_sched_reorder. */
10312 static int
10313 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10314 int verbose ATTRIBUTE_UNUSED,
10315 rtx insn, int more)
10316 {
10317 last_scheduled_insn = insn;
10318
10319 if (GET_CODE (PATTERN (insn)) != USE
10320 && GET_CODE (PATTERN (insn)) != CLOBBER)
10321 return more - 1;
10322 else
10323 return more;
10324 }
10325
10326 static void
10327 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10328 int verbose ATTRIBUTE_UNUSED,
10329 int max_ready ATTRIBUTE_UNUSED)
10330 {
10331 last_scheduled_insn = NULL_RTX;
10332 }
10333
10334 /* This function checks the whole of insn X for memory references. The
10335 function always returns zero because the framework it is called
10336 from would stop recursively analyzing the insn upon a return value
10337 other than zero. The real result of this function is updating
10338 counter variable MEM_COUNT. */
10339 static int
10340 check_dpu (rtx *x, unsigned *mem_count)
10341 {
10342 if (*x != NULL_RTX && MEM_P (*x))
10343 (*mem_count)++;
10344 return 0;
10345 }
10346
10347 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10348 a new number struct loop *loop should be unrolled if tuned for the z10
10349 cpu. The loop is analyzed for memory accesses by calling check_dpu for
10350 each rtx of the loop. Depending on the loop_depth and the amount of
10351 memory accesses a new number <=nunroll is returned to improve the
10352 behaviour of the hardware prefetch unit. */
10353 static unsigned
10354 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10355 {
10356 basic_block *bbs;
10357 rtx insn;
10358 unsigned i;
10359 unsigned mem_count = 0;
10360
10361 /* Only z10 needs special handling. */
10362 if (s390_tune != PROCESSOR_2097_Z10)
10363 return nunroll;
10364
10365 /* Count the number of memory references within the loop body. */
10366 bbs = get_loop_body (loop);
10367 for (i = 0; i < loop->num_nodes; i++)
10368 {
10369 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10370 if (INSN_P (insn) && INSN_CODE (insn) != -1)
10371 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10372 }
10373 free (bbs);
10374
10375 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10376 if (mem_count == 0)
10377 return nunroll;
10378
10379 switch (loop_depth(loop))
10380 {
10381 case 1:
10382 return MIN (nunroll, 28 / mem_count);
10383 case 2:
10384 return MIN (nunroll, 22 / mem_count);
10385 default:
10386 return MIN (nunroll, 16 / mem_count);
10387 }
10388 }
10389
10390 /* Initialize GCC target structure. */
10391
10392 #undef TARGET_ASM_ALIGNED_HI_OP
10393 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10394 #undef TARGET_ASM_ALIGNED_DI_OP
10395 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10396 #undef TARGET_ASM_INTEGER
10397 #define TARGET_ASM_INTEGER s390_assemble_integer
10398
10399 #undef TARGET_ASM_OPEN_PAREN
10400 #define TARGET_ASM_OPEN_PAREN ""
10401
10402 #undef TARGET_ASM_CLOSE_PAREN
10403 #define TARGET_ASM_CLOSE_PAREN ""
10404
10405 #undef TARGET_DEFAULT_TARGET_FLAGS
10406 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10407
10408 #undef TARGET_HANDLE_OPTION
10409 #define TARGET_HANDLE_OPTION s390_handle_option
10410
10411 #undef TARGET_ENCODE_SECTION_INFO
10412 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10413
10414 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10415 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10416
10417 #ifdef HAVE_AS_TLS
10418 #undef TARGET_HAVE_TLS
10419 #define TARGET_HAVE_TLS true
10420 #endif
10421 #undef TARGET_CANNOT_FORCE_CONST_MEM
10422 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10423
10424 #undef TARGET_DELEGITIMIZE_ADDRESS
10425 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10426
10427 #undef TARGET_LEGITIMIZE_ADDRESS
10428 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10429
10430 #undef TARGET_RETURN_IN_MEMORY
10431 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10432
10433 #undef TARGET_INIT_BUILTINS
10434 #define TARGET_INIT_BUILTINS s390_init_builtins
10435 #undef TARGET_EXPAND_BUILTIN
10436 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10437
10438 #undef TARGET_ASM_OUTPUT_MI_THUNK
10439 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10440 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10441 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10442
10443 #undef TARGET_SCHED_ADJUST_PRIORITY
10444 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10445 #undef TARGET_SCHED_ISSUE_RATE
10446 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10447 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10448 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10449
10450 #undef TARGET_SCHED_VARIABLE_ISSUE
10451 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10452 #undef TARGET_SCHED_REORDER
10453 #define TARGET_SCHED_REORDER s390_sched_reorder
10454 #undef TARGET_SCHED_INIT
10455 #define TARGET_SCHED_INIT s390_sched_init
10456
10457 #undef TARGET_CANNOT_COPY_INSN_P
10458 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10459 #undef TARGET_RTX_COSTS
10460 #define TARGET_RTX_COSTS s390_rtx_costs
10461 #undef TARGET_ADDRESS_COST
10462 #define TARGET_ADDRESS_COST s390_address_cost
10463
10464 #undef TARGET_MACHINE_DEPENDENT_REORG
10465 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10466
10467 #undef TARGET_VALID_POINTER_MODE
10468 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10469
10470 #undef TARGET_BUILD_BUILTIN_VA_LIST
10471 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10472 #undef TARGET_EXPAND_BUILTIN_VA_START
10473 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10474 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10475 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10476
10477 #undef TARGET_PROMOTE_FUNCTION_MODE
10478 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10479 #undef TARGET_PASS_BY_REFERENCE
10480 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10481
10482 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10483 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10484
10485 #undef TARGET_FIXED_CONDITION_CODE_REGS
10486 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10487
10488 #undef TARGET_CC_MODES_COMPATIBLE
10489 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10490
10491 #undef TARGET_INVALID_WITHIN_DOLOOP
10492 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10493
10494 #ifdef HAVE_AS_TLS
10495 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10496 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10497 #endif
10498
10499 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10500 #undef TARGET_MANGLE_TYPE
10501 #define TARGET_MANGLE_TYPE s390_mangle_type
10502 #endif
10503
10504 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10505 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10506
10507 #undef TARGET_SECONDARY_RELOAD
10508 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10509
10510 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10511 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10512
10513 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10514 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10515
10516 #undef TARGET_LEGITIMATE_ADDRESS_P
10517 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10518
10519 #undef TARGET_CAN_ELIMINATE
10520 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10521
10522 #undef TARGET_LOOP_UNROLL_ADJUST
10523 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10524
10525 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10526 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10527 #undef TARGET_TRAMPOLINE_INIT
10528 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10529
10530 #undef TARGET_UNWIND_WORD_MODE
10531 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10532
10533 struct gcc_target targetm = TARGET_INITIALIZER;
10534
10535 #include "gt-s390.h"